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// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ac_ROM_reg(
rdaddress,
clock,
wraddress,
data,
wren,
q);
parameter AC_ROM_DATA_WIDTH = "";
parameter AC_ROM_ADDRESS_WIDTH = "";
input [(AC_ROM_ADDRESS_WIDTH-1):0] rdaddress;
input clock;
input [(AC_ROM_ADDRESS_WIDTH-1):0] wraddress;
input [(AC_ROM_DATA_WIDTH-1):0] data;
input wren;
output reg [(AC_ROM_DATA_WIDTH-1):0] q;
reg [(AC_ROM_DATA_WIDTH-1):0] ac_mem[(2**AC_ROM_ADDRESS_WIDTH-1):0];
always @(posedge clock)
begin
if(wren)
ac_mem[wraddress] <= data;
q <= ac_mem[rdaddress];
end
endmodule
|
//======================================================================
//
// blake2_core.v
// --------------
// Verilog 2001 implementation of the hash function Blake2.
// This is the internal core with wide interfaces.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`include "blake2_G.v"
`include "blake2_m_select.v"
module blake2_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire final_block,
input wire [1023 : 0] block,
input wire [127 : 0] data_length,
output wire ready,
output wire [511 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Configuration parameters.
//----------------------------------------------------------------
// Default number of rounds
parameter NUM_ROUNDS = 4'hc;
//----------------------------------------------------------------
// Parameter block.
//----------------------------------------------------------------
// The digest length in bytes. Minimum: 1, Maximum: 64
parameter [7:0] DIGEST_LENGTH = 8'd64;
// The key length in bytes. Minimum: 0 (for no key used), Maximum: 64
parameter [7:0] KEY_LENGTH = 8'd0;
// Fanout
parameter [7:0] FANOUT = 8'h01;
// Depth (maximal)
parameter [7:0] DEPTH = 8'h01;
// 4-byte leaf length
parameter [31:0] LEAF_LENGTH = 32'h00000000;
// 8-byte node offset
parameter [64:0] NODE_OFFSET = 64'h0000000000000000;
// Node Depth
parameter [7:0] NODE_DEPTH = 8'h00;
// Inner hash length
parameter [7:0] INNER_LENGTH = 8'h00;
// Reserved for future use (14 bytes)
parameter [111:0] RESERVED = 112'h0000000000000000000000000000;
// 16-byte salt, little-endian byte order
parameter [127:0] SALT = 128'h00000000000000000000000000000000;
// 16-byte personalization, little-endian byte order
parameter [127:0] PERSONALIZATION = 128'h00000000000000000000000000000000;
wire [511:0] parameter_block = {PERSONALIZATION, SALT, RESERVED, INNER_LENGTH,
NODE_DEPTH, NODE_OFFSET, LEAF_LENGTH, DEPTH,
FANOUT, KEY_LENGTH, DIGEST_LENGTH};
//----------------------------------------------------------------
// Internal constant definitions.
//----------------------------------------------------------------
// Datapath quartterround states names.
localparam STATE_G0 = 1'b0;
localparam STATE_G1 = 1'b1;
localparam IV0 = 64'h6a09e667f3bcc908;
localparam IV1 = 64'hbb67ae8584caa73b;
localparam IV2 = 64'h3c6ef372fe94f82b;
localparam IV3 = 64'ha54ff53a5f1d36f1;
localparam IV4 = 64'h510e527fade682d1;
localparam IV5 = 64'h9b05688c2b3e6c1f;
localparam IV6 = 64'h1f83d9abfb41bd6b;
localparam IV7 = 64'h5be0cd19137e2179;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
localparam CTRL_ROUNDS = 3'h2;
localparam CTRL_FINALIZE = 3'h3;
localparam CTRL_DONE = 3'h4;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [63 : 0] h0_reg;
reg [63 : 0] h0_new;
reg [63 : 0] h1_reg;
reg [63 : 0] h1_new;
reg [63 : 0] h2_reg;
reg [63 : 0] h2_new;
reg [63 : 0] h3_reg;
reg [63 : 0] h3_new;
reg [63 : 0] h4_reg;
reg [63 : 0] h4_new;
reg [63 : 0] h5_reg;
reg [63 : 0] h5_new;
reg [63 : 0] h6_reg;
reg [63 : 0] h6_new;
reg [63 : 0] h7_reg;
reg [63 : 0] h7_new;
reg update_chain_value;
reg h_we;
reg [63 : 0] v0_reg;
reg [63 : 0] v0_new;
reg [63 : 0] v1_reg;
reg [63 : 0] v1_new;
reg [63 : 0] v2_reg;
reg [63 : 0] v2_new;
reg [63 : 0] v3_reg;
reg [63 : 0] v3_new;
reg [63 : 0] v4_reg;
reg [63 : 0] v4_new;
reg [63 : 0] v5_reg;
reg [63 : 0] v5_new;
reg [63 : 0] v6_reg;
reg [63 : 0] v6_new;
reg [63 : 0] v7_reg;
reg [63 : 0] v7_new;
reg [63 : 0] v8_reg;
reg [63 : 0] v8_new;
reg [63 : 0] v9_reg;
reg [63 : 0] v9_new;
reg [63 : 0] v10_reg;
reg [63 : 0] v10_new;
reg [63 : 0] v11_reg;
reg [63 : 0] v11_new;
reg [63 : 0] v12_reg;
reg [63 : 0] v12_new;
reg [63 : 0] v13_reg;
reg [63 : 0] v13_new;
reg [63 : 0] v14_reg;
reg [63 : 0] v14_new;
reg [63 : 0] v15_reg;
reg [63 : 0] v15_new;
reg v_we;
reg [63 : 0] t0_reg;
reg [63 : 0] t0_new;
reg t0_we;
reg [63 : 0] t1_reg;
reg [63 : 0] t1_new;
reg t1_we;
reg [63 : 0] f0_reg;
reg [63 : 0] f0_new;
reg f0_we;
reg [63 : 0] f1_reg;
reg [63 : 0] f1_new;
reg f1_we;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg G_ctr_reg;
reg G_ctr_new;
reg G_ctr_we;
reg G_ctr_inc;
reg G_ctr_rst;
reg [3 : 0] dr_ctr_reg;
reg [3 : 0] dr_ctr_new;
reg dr_ctr_we;
reg dr_ctr_inc;
reg dr_ctr_rst;
reg [2 : 0] blake2_ctrl_reg;
reg [2 : 0] blake2_ctrl_new;
reg blake2_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg sample_params;
reg init_state;
reg update_state;
reg update_output;
reg load_m;
reg [63 : 0] G0_a;
reg [63 : 0] G0_b;
reg [63 : 0] G0_c;
reg [63 : 0] G0_d;
wire [63 : 0] G0_m0;
wire [63 : 0] G0_m1;
wire [63 : 0] G0_a_prim;
wire [63 : 0] G0_b_prim;
wire [63 : 0] G0_c_prim;
wire [63 : 0] G0_d_prim;
reg [63 : 0] G1_a;
reg [63 : 0] G1_b;
reg [63 : 0] G1_c;
reg [63 : 0] G1_d;
wire [63 : 0] G1_m0;
wire [63 : 0] G1_m1;
wire [63 : 0] G1_a_prim;
wire [63 : 0] G1_b_prim;
wire [63 : 0] G1_c_prim;
wire [63 : 0] G1_d_prim;
reg [63 : 0] G2_a;
reg [63 : 0] G2_b;
reg [63 : 0] G2_c;
reg [63 : 0] G2_d;
wire [63 : 0] G2_m0;
wire [63 : 0] G2_m1;
wire [63 : 0] G2_a_prim;
wire [63 : 0] G2_b_prim;
wire [63 : 0] G2_c_prim;
wire [63 : 0] G2_d_prim;
reg [63 : 0] G3_a;
reg [63 : 0] G3_b;
reg [63 : 0] G3_c;
reg [63 : 0] G3_d;
wire [63 : 0] G3_m0;
wire [63 : 0] G3_m1;
wire [63 : 0] G3_a_prim;
wire [63 : 0] G3_b_prim;
wire [63 : 0] G3_c_prim;
wire [63 : 0] G3_d_prim;
//----------------------------------------------------------------
// Instantiation of the compression modules.
//----------------------------------------------------------------
blake2_m_select mselect(
.clk(clk),
.reset_n(reset_n),
.load(load_m),
.m(block),
.r(dr_ctr_reg),
.state(G_ctr_reg),
.G0_m0(G0_m0),
.G0_m1(G0_m1),
.G1_m0(G1_m0),
.G1_m1(G1_m1),
.G2_m0(G2_m0),
.G2_m1(G2_m1),
.G3_m0(G3_m0),
.G3_m1(G3_m1)
);
blake2_G G0(
.a(G0_a),
.b(G0_b),
.c(G0_c),
.d(G0_d),
.m0(G0_m0),
.m1(G0_m1),
.a_prim(G0_a_prim),
.b_prim(G0_b_prim),
.c_prim(G0_c_prim),
.d_prim(G0_d_prim)
);
blake2_G G1(
.a(G1_a),
.b(G1_b),
.c(G1_c),
.d(G1_d),
.m0(G1_m0),
.m1(G1_m1),
.a_prim(G1_a_prim),
.b_prim(G1_b_prim),
.c_prim(G1_c_prim),
.d_prim(G1_d_prim)
);
blake2_G G2(
.a(G2_a),
.b(G2_b),
.c(G2_c),
.d(G2_d),
.m0(G2_m0),
.m1(G2_m1),
.a_prim(G2_a_prim),
.b_prim(G2_b_prim),
.c_prim(G2_c_prim),
.d_prim(G2_d_prim)
);
blake2_G G3(
.a(G3_a),
.b(G3_b),
.c(G3_c),
.d(G3_d),
.m0(G3_m0),
.m1(G3_m1),
.a_prim(G3_a_prim),
.b_prim(G3_b_prim),
.c_prim(G3_c_prim),
.d_prim(G3_d_prim)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign digest = {h0_reg[7:0], h0_reg[15:8], h0_reg[23:16], h0_reg[31:24], h0_reg[39:32], h0_reg[47:40], h0_reg[55:48], h0_reg[63:56],
h1_reg[7:0], h1_reg[15:8], h1_reg[23:16], h1_reg[31:24], h1_reg[39:32], h1_reg[47:40], h1_reg[55:48], h1_reg[63:56],
h2_reg[7:0], h2_reg[15:8], h2_reg[23:16], h2_reg[31:24], h2_reg[39:32], h2_reg[47:40], h2_reg[55:48], h2_reg[63:56],
h3_reg[7:0], h3_reg[15:8], h3_reg[23:16], h3_reg[31:24], h3_reg[39:32], h3_reg[47:40], h3_reg[55:48], h3_reg[63:56],
h4_reg[7:0], h4_reg[15:8], h4_reg[23:16], h4_reg[31:24], h4_reg[39:32], h4_reg[47:40], h4_reg[55:48], h4_reg[63:56],
h5_reg[7:0], h5_reg[15:8], h5_reg[23:16], h5_reg[31:24], h5_reg[39:32], h5_reg[47:40], h5_reg[55:48], h5_reg[63:56],
h6_reg[7:0], h6_reg[15:8], h6_reg[23:16], h6_reg[31:24], h6_reg[39:32], h6_reg[47:40], h6_reg[55:48], h6_reg[63:56],
h7_reg[7:0], h7_reg[15:8], h7_reg[23:16], h7_reg[31:24], h7_reg[39:32], h7_reg[47:40], h7_reg[55:48], h7_reg[63:56]};
assign digest_valid = digest_valid_reg;
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
t0_reg <= 64'h0000000000000000;
t1_reg <= 64'h0000000000000000;
f0_reg <= 64'h0000000000000000;
f1_reg <= 64'h0000000000000000;
h0_reg <= 64'h0000000000000000;
h1_reg <= 64'h0000000000000000;
h2_reg <= 64'h0000000000000000;
h3_reg <= 64'h0000000000000000;
h4_reg <= 64'h0000000000000000;
h5_reg <= 64'h0000000000000000;
h6_reg <= 64'h0000000000000000;
h7_reg <= 64'h0000000000000000;
v0_reg <= 64'h0000000000000000;
v1_reg <= 64'h0000000000000000;
v2_reg <= 64'h0000000000000000;
v3_reg <= 64'h0000000000000000;
v4_reg <= 64'h0000000000000000;
v5_reg <= 64'h0000000000000000;
v6_reg <= 64'h0000000000000000;
v7_reg <= 64'h0000000000000000;
v8_reg <= 64'h0000000000000000;
v9_reg <= 64'h0000000000000000;
v10_reg <= 64'h0000000000000000;
v11_reg <= 64'h0000000000000000;
v12_reg <= 64'h0000000000000000;
v13_reg <= 64'h0000000000000000;
v14_reg <= 64'h0000000000000000;
v15_reg <= 64'h0000000000000000;
ready_reg <= 1;
digest_valid_reg <= 0;
G_ctr_reg <= STATE_G0;
dr_ctr_reg <= 0;
blake2_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (h_we)
begin
h0_reg <= h0_new;
h1_reg <= h1_new;
h2_reg <= h2_new;
h3_reg <= h3_new;
h4_reg <= h4_new;
h5_reg <= h5_new;
h6_reg <= h6_new;
h7_reg <= h7_new;
end
if (v_we)
begin
v0_reg <= v0_new;
v1_reg <= v1_new;
v2_reg <= v2_new;
v3_reg <= v3_new;
v4_reg <= v4_new;
v5_reg <= v5_new;
v6_reg <= v6_new;
v7_reg <= v7_new;
v8_reg <= v8_new;
v9_reg <= v9_new;
v10_reg <= v10_new;
v11_reg <= v11_new;
v12_reg <= v12_new;
v13_reg <= v13_new;
v14_reg <= v14_new;
v15_reg <= v15_new;
end
if (ready_we)
begin
ready_reg <= ready_new;
end
if (digest_valid_we)
begin
digest_valid_reg <= digest_valid_new;
end
if (G_ctr_we)
begin
G_ctr_reg <= G_ctr_new;
end
if (dr_ctr_we)
begin
dr_ctr_reg <= dr_ctr_new;
end
if (blake2_ctrl_we)
begin
blake2_ctrl_reg <= blake2_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// chain_logic
//
// Logic for updating the chain registers.
//----------------------------------------------------------------
always @*
begin : chain_logic
if (init_state)
begin
h0_new = IV0 ^ parameter_block[63:0];
h1_new = IV1 ^ parameter_block[127:64];
h2_new = IV2 ^ parameter_block[191:128];
h3_new = IV3 ^ parameter_block[255:192];
h4_new = IV4 ^ parameter_block[319:256];
h5_new = IV5 ^ parameter_block[383:320];
h6_new = IV6 ^ parameter_block[447:384];
h7_new = IV7 ^ parameter_block[511:448];
h_we = 1;
end
else if (update_chain_value)
begin
h0_new = h0_reg ^ v0_reg ^ v8_reg;
h1_new = h1_reg ^ v1_reg ^ v9_reg;
h2_new = h2_reg ^ v2_reg ^ v10_reg;
h3_new = h3_reg ^ v3_reg ^ v11_reg;
h4_new = h4_reg ^ v4_reg ^ v12_reg;
h5_new = h5_reg ^ v5_reg ^ v13_reg;
h6_new = h6_reg ^ v6_reg ^ v14_reg;
h7_new = h7_reg ^ v7_reg ^ v15_reg;
h_we = 1;
end
else
begin
h0_new = 64'h0000000000000000;
h1_new = 64'h0000000000000000;
h2_new = 64'h0000000000000000;
h3_new = 64'h0000000000000000;
h4_new = 64'h0000000000000000;
h5_new = 64'h0000000000000000;
h6_new = 64'h0000000000000000;
h7_new = 64'h0000000000000000;
h_we = 0;
end
end // chain_logic
//----------------------------------------------------------------
// state_logic
//
// Logic to init and update the internal state.
//----------------------------------------------------------------
always @*
begin : state_logic
if (init_state)
begin
v0_new = IV0 ^ parameter_block[63:0];
v1_new = IV1 ^ parameter_block[127:64];
v2_new = IV2 ^ parameter_block[191:128];
v3_new = IV3 ^ parameter_block[255:192];
v4_new = IV4 ^ parameter_block[319:256];
v5_new = IV5 ^ parameter_block[383:320];
v6_new = IV6 ^ parameter_block[447:384];
v7_new = IV7 ^ parameter_block[511:448];
v8_new = IV0;
v9_new = IV1;
v10_new = IV2;
v11_new = IV3;
v12_new = data_length[63:0] ^ IV4;
v13_new = t1_reg ^ IV5;
if (final_block)
v14_new = 64'hffffffffffffffff ^ IV6;
else
v14_new = IV6;
v15_new = f1_reg ^ IV7;
v_we = 1;
end
else if (update_state)
begin
case (G_ctr_reg)
// Column updates.
STATE_G0:
begin
G0_a = v0_reg;
G0_b = v4_reg;
G0_c = v8_reg;
G0_d = v12_reg;
v0_new = G0_a_prim;
v4_new = G0_b_prim;
v8_new = G0_c_prim;
v12_new = G0_d_prim;
G1_a = v1_reg;
G1_b = v5_reg;
G1_c = v9_reg;
G1_d = v13_reg;
v1_new = G1_a_prim;
v5_new = G1_b_prim;
v9_new = G1_c_prim;
v13_new = G1_d_prim;
G2_a = v2_reg;
G2_b = v6_reg;
G2_c = v10_reg;
G2_d = v14_reg;
v2_new = G2_a_prim;
v6_new = G2_b_prim;
v10_new = G2_c_prim;
v14_new = G2_d_prim;
G3_a = v3_reg;
G3_b = v7_reg;
G3_c = v11_reg;
G3_d = v15_reg;
v3_new = G3_a_prim;
v7_new = G3_b_prim;
v11_new = G3_c_prim;
v15_new = G3_d_prim;
v_we = 1;
end
// Diagonal updates.
STATE_G1:
begin
G0_a = v0_reg;
G0_b = v5_reg;
G0_c = v10_reg;
G0_d = v15_reg;
v0_new = G0_a_prim;
v5_new = G0_b_prim;
v10_new = G0_c_prim;
v15_new = G0_d_prim;
G1_a = v1_reg;
G1_b = v6_reg;
G1_c = v11_reg;
G1_d = v12_reg;
v1_new = G1_a_prim;
v6_new = G1_b_prim;
v11_new = G1_c_prim;
v12_new = G1_d_prim;
G2_a = v2_reg;
G2_b = v7_reg;
G2_c = v8_reg;
G2_d = v13_reg;
v2_new = G2_a_prim;
v7_new = G2_b_prim;
v8_new = G2_c_prim;
v13_new = G2_d_prim;
G3_a = v3_reg;
G3_b = v4_reg;
G3_c = v9_reg;
G3_d = v14_reg;
v3_new = G3_a_prim;
v4_new = G3_b_prim;
v9_new = G3_c_prim;
v14_new = G3_d_prim;
v_we = 1;
end
default:
begin
G0_a = 0;
G0_b = 0;
G0_c = 0;
G0_d = 0;
G1_a = 0;
G1_b = 0;
G1_c = 0;
G1_d = 0;
G2_a = 0;
G2_b = 0;
G2_c = 0;
G2_d = 0;
G3_a = 0;
G3_b = 0;
G3_c = 0;
G3_d = 0;
end
endcase // case (G_ctr_reg)
end // if (update_state)
else
begin
v0_new = 64'h0000000000000000;
v1_new = 64'h0000000000000000;
v2_new = 64'h0000000000000000;
v3_new = 64'h0000000000000000;
v4_new = 64'h0000000000000000;
v5_new = 64'h0000000000000000;
v6_new = 64'h0000000000000000;
v7_new = 64'h0000000000000000;
v8_new = 64'h0000000000000000;
v9_new = 64'h0000000000000000;
v10_new = 64'h0000000000000000;
v11_new = 64'h0000000000000000;
v12_new = 64'h0000000000000000;
v13_new = 64'h0000000000000000;
v14_new = 64'h0000000000000000;
v15_new = 64'h0000000000000000;
v_we = 0;
end
end // state_logic
//----------------------------------------------------------------
// G_ctr
// Update logic for the G function counter. Basically a one bit
// counter that selects if we column of diaginal updates.
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : G_ctr
if (G_ctr_rst)
begin
G_ctr_new = 0;
G_ctr_we = 1;
end
else if (G_ctr_inc)
begin
G_ctr_new = G_ctr_reg + 1'b1;
G_ctr_we = 1;
end
else
begin
G_ctr_new = 0;
G_ctr_we = 0;
end
end // G_ctr
//----------------------------------------------------------------
// dr_ctr
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : dr_ctr
if (dr_ctr_rst)
begin
dr_ctr_new = 0;
dr_ctr_we = 1;
end
else if (dr_ctr_inc)
begin
dr_ctr_new = dr_ctr_reg + 1'b1;
dr_ctr_we = 1;
end
else
begin
dr_ctr_new = 0;
dr_ctr_we = 0;
end
end // dr_ctr
//----------------------------------------------------------------
// blake2_ctrl_fsm
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : blake2_ctrl_fsm
init_state = 0;
update_state = 0;
load_m = 0;
G_ctr_inc = 0;
G_ctr_rst = 0;
dr_ctr_inc = 0;
dr_ctr_rst = 0;
update_chain_value = 0;
ready_new = 0;
ready_we = 0;
digest_valid_new = 0;
digest_valid_we = 0;
blake2_ctrl_new = CTRL_IDLE;
blake2_ctrl_we = 0;
case (blake2_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
ready_new = 0;
ready_we = 1;
load_m = 1;
blake2_ctrl_new = CTRL_INIT;
blake2_ctrl_we = 1;
end
end
CTRL_INIT:
begin
init_state = 1;
G_ctr_rst = 1;
dr_ctr_rst = 1;
blake2_ctrl_new = CTRL_ROUNDS;
blake2_ctrl_we = 1;
end
CTRL_ROUNDS:
begin
update_state = 1;
G_ctr_inc = 1;
if (G_ctr_reg == STATE_G1)
begin
dr_ctr_inc = 1;
if (dr_ctr_reg == (NUM_ROUNDS - 1))
begin
blake2_ctrl_new = CTRL_FINALIZE;
blake2_ctrl_we = 1;
end
end
end
CTRL_FINALIZE:
begin
update_chain_value = 1;
ready_new = 1;
ready_we = 1;
digest_valid_new = 1;
digest_valid_we = 1;
blake2_ctrl_new = CTRL_DONE;
blake2_ctrl_we = 1;
end
CTRL_DONE:
begin
if (init)
begin
ready_new = 0;
ready_we = 1;
digest_valid_new = 0;
digest_valid_we = 1;
load_m = 1;
blake2_ctrl_new = CTRL_INIT;
blake2_ctrl_we = 1;
end
else if (next)
begin
ready_new = 0;
ready_we = 1;
digest_valid_new = 0;
digest_valid_we = 1;
load_m = 1;
blake2_ctrl_new = CTRL_INIT;
blake2_ctrl_we = 1;
end
end
default:
begin
blake2_ctrl_new = CTRL_IDLE;
blake2_ctrl_we = 1;
end
endcase // case (blake2_ctrl_reg)
end // blake2_ctrl_fsm
endmodule // blake2_core
//======================================================================
// EOF blake2_core.v
//======================================================================
|
/*******************************************************************************
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* devices or technologies is expressly prohibited and immediately *
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* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
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* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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*******************************************************************************/
// You must compile the wrapper file gsu_cache.v when simulating
// the core, gsu_cache. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module gsu_cache(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//
// Conformal-LEC Version 15.20-d227 ( 10-Mar-2016) ( 64 bit executable)
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , PI_DFF_B_reg_Q , n9 , PI_DFF_rd_reg_Q , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , PI_DFF_wr_reg_Q , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , PI_PI_reset , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , PI_DFF_state_reg_Q , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , PI_PI_clock , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , PI_DFF_B_reg_Q , n9 , PI_DFF_rd_reg_Q , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , PI_DFF_wr_reg_Q , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , PI_PI_reset , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , PI_DFF_state_reg_Q , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , PI_PI_clock , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 ;
output n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 ;
wire n516 , n517 , n518 , n519 , n520 , n521 , n522 , n523 , n524 ,
n525 , n526 , n527 , n528 , n529 , n530 , n531 , n532 , n533 , n534 ,
n535 , n536 , n537 , n538 , n539 , n540 , n541 , n542 , n543 , n544 ,
n545 , n546 , n547 , n548 , n549 , n550 , n551 , n552 , n553 , n554 ,
n555 , n556 , n557 , n558 , n559 , n560 , n561 , n562 , n563 , n564 ,
n565 , n566 , n567 , n568 , n569 , n570 , n571 , n572 , n573 , n574 ,
n575 , n576 , n577 , n578 , n579 , n580 , n581 , n582 , n583 , n584 ,
n585 , n586 , n587 , n588 , n589 , n590 , n591 , n592 , n593 , n594 ,
n595 , n596 , n597 , n598 , n599 , n600 , n601 , n602 , n603 , n604 ,
n605 , n606 , n607 , n608 , n609 , n610 , n611 , n612 , n613 , n614 ,
n615 , n616 , n617 , n618 , n619 , n620 , n621 , n622 , n623 , n624 ,
n625 , n626 , n627 , n628 , n629 , n630 , n631 , n632 , n633 , n634 ,
n635 , n636 , n637 , n638 , n639 , n640 , n641 , n642 , n643 , n644 ,
n645 , n646 , n647 , n648 , n649 , n650 , n651 , n652 , n653 , n654 ,
n655 , n656 , n657 , n658 , n659 , n660 , n661 , n662 , n663 , n664 ,
n665 , n666 , n667 , n668 , n669 , n670 , n671 , n672 , n673 , n674 ,
n675 , n676 , n677 , n678 , n679 , n680 , n681 , n682 , n683 , n684 ,
n685 , n686 , n687 , n688 , n689 , n690 , n691 , n692 , n693 , n694 ,
n695 , n696 , n697 , n698 , n699 , n700 , n701 , n702 , n703 , n704 ,
n705 , n706 , n707 , n708 , n709 , n710 , n711 , n712 , n713 , n714 ,
n715 , n716 , n717 , n718 , n719 , n720 , n721 , n722 , n723 , n724 ,
n725 , n726 , n727 , n728 , n729 , n730 , n731 , n732 , n733 , n734 ,
n735 , n736 , n737 , n738 , n739 , n740 , n741 , n742 , n743 , n744 ,
n745 , n746 , n747 , n748 , n749 , n750 , n751 , n752 , n753 , n754 ,
n755 , n756 , n757 , n758 , n759 , n760 , n761 , n762 , n763 , n764 ,
n765 , n766 , n767 , n768 , n769 , n770 , n771 , n772 , n773 , n774 ,
n775 , n776 , n777 , n778 , n779 , n780 , n781 , n782 , n783 , n784 ,
n785 , n786 , n787 , n788 , n789 , n790 , n791 , n792 , n793 , n794 ,
n795 , n796 , n797 , n798 , n799 , n800 , n801 , n802 , n803 , n804 ,
n805 , n806 , n807 , n808 , n809 , n810 , n811 , n812 , n813 , n814 ,
n815 , n816 , n817 , n818 , n819 , n820 , n821 , n822 , n823 , n824 ,
n825 , n826 , n827 , n828 , n829 , n830 , n831 , n832 , n833 , n834 ,
n835 , n836 , n837 , n838 , n839 , n840 , n841 , n842 , n843 , n844 ,
n845 , n846 , n847 , n848 , n849 , n850 , n851 , n852 , n853 , n854 ,
n855 , n856 , n857 , n858 , n859 , n860 , n861 , n862 , n863 , n864 ,
n865 , n866 , n867 , n868 , n869 , n870 , n871 , n872 , n873 , n874 ,
n875 , n876 , n877 , n878 , n879 , n880 , n881 , n882 , n883 , n884 ,
n885 , n886 , n887 , n888 , n889 , n890 , n891 , n892 , n893 , n894 ,
n895 , n896 , n897 , n898 , n899 , n900 , n901 , n902 , n903 , n904 ,
n905 , n906 , n907 , n908 , n909 , n910 , n911 , n912 , n913 , n914 ,
n915 , n916 , n917 , n918 , n919 , n920 , n921 , n922 , n923 , n924 ,
n925 , n926 , n927 , n928 , n929 , n930 , n931 , n932 , n933 , n934 ,
n935 , n936 , n937 , n938 , n939 , n940 , n941 , n942 , n943 , n944 ,
n945 , n946 , n947 , n948 , n949 , n950 , n951 , n952 , n953 , n954 ,
n955 , n956 , n957 , n958 , n959 , n960 , n961 , n962 , n963 , n964 ,
n965 , n966 , n967 , n968 , n969 , n970 , n971 , n972 , n973 , n974 ,
n975 , n976 , n977 , n978 , n979 , n980 , n981 , n982 , n983 , n984 ,
n985 , n986 , n987 , n988 , n989 , n990 , n991 , n992 , n993 , n994 ,
n995 , n996 , n997 , n998 , n999 , n1000 , n1001 , n1002 , n1003 , n1004 ,
n1005 , n1006 , n1007 , n1008 , n1009 , n1010 , n1011 , n1012 , n1013 , n1014 ,
n1015 , n1016 , n1017 , n1018 , n1019 , n1020 , n1021 , n1022 , n1023 , n1024 ,
n1025 , n1026 , n1027 , n1028 , n1029 , n1030 , n1031 , n1032 , n1033 , n1034 ,
n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 , n1043 , n1044 ,
n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 , n1053 , n1054 ,
n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 , n1063 , n1064 ,
n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 , n1073 , n1074 ,
n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 , n1083 , n1084 ,
n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 , n1093 , n1094 ,
n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 , n1103 , n1104 ,
n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 , n1113 , n1114 ,
n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 , n1123 , n1124 ,
n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 , n1133 , n1134 ,
n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 , n1143 , n1144 ,
n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 , n1153 , n1154 ,
n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 , n1163 , n1164 ,
n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 , n1173 , n1174 ,
n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 , n1183 , n1184 ,
n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 , n1193 , n1194 ,
n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 , n1203 , n1204 ,
n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 , n1213 , n1214 ,
n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 , n1223 , n1224 ,
n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 , n1233 , n1234 ,
n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 , n1243 , n1244 ,
n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 , n1253 , n1254 ,
n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 , n1263 , n1264 ,
n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 , n1273 , n1274 ,
n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 , n1283 , n1284 ,
n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 , n1293 , n1294 ,
n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 , n1303 , n1304 ,
n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 , n1313 , n1314 ,
n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 , n1323 , n1324 ,
n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 , n1333 , n1334 ,
n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 , n1343 , n1344 ,
n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 , n1353 , n1354 ,
n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 , n1363 , n1364 ,
n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 , n1373 , n1374 ,
n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 , n1383 , n1384 ,
n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 , n1393 , n1394 ,
n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 , n1403 , n1404 ,
n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 , n1413 , n1414 ,
n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 , n1423 , n1424 ,
n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 , n1433 , n1434 ,
n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 , n1443 , n1444 ,
n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 , n1453 , n1454 ,
n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 , n1463 , n1464 ,
n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 , n1473 , n1474 ,
n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 , n1483 , n1484 ,
n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 , n1493 , n1494 ,
n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 , n1503 , n1504 ,
n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 , n1513 , n1514 ,
n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 , n1523 , n1524 ,
n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 , n1533 , n1534 ,
n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 , n1543 , n1544 ,
n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 , n1553 , n1554 ,
n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 , n1563 , n1564 ,
n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 , n1573 , n1574 ,
n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 , n1583 , n1584 ,
n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 , n1593 , n1594 ,
n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 , n1603 , n1604 ,
n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 , n1613 , n1614 ,
n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 , n1623 , n1624 ,
n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 , n1633 , n1634 ,
n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 , n1643 , n1644 ,
n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 , n1653 , n1654 ,
n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 , n1663 , n1664 ,
n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 , n1673 , n1674 ,
n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 , n1683 , n1684 ,
n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 , n1693 , n1694 ,
n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 , n1703 , n1704 ,
n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 , n1713 , n1714 ,
n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 , n1723 , n1724 ,
n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 , n1733 , n1734 ,
n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 , n1743 , n1744 ,
n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 , n1753 , n1754 ,
n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 , n1763 , n1764 ,
n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 , n1773 , n1774 ,
n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 , n1783 , n1784 ,
n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 , n1793 , n1794 ,
n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 , n1803 , n1804 ,
n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 , n1813 , n1814 ,
n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 , n1823 , n1824 ,
n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 , n1833 , n1834 ,
n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 , n1843 , n1844 ,
n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 , n1853 , n1854 ,
n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 , n1863 , n1864 ,
n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 , n1873 , n1874 ,
n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 , n1883 , n1884 ,
n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 , n1893 , n1894 ,
n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 , n1903 , n1904 ,
n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 , n1913 , n1914 ,
n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 , n1923 , n1924 ,
n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 , n1933 , n1934 ,
n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 , n1943 , n1944 ,
n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 , n1953 , n1954 ,
n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 , n1963 , n1964 ,
n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 , n1973 , n1974 ,
n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 , n1983 , n1984 ,
n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 , n1993 , n1994 ,
n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 , n2003 , n2004 ,
n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 , n2013 , n2014 ,
n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 , n2023 , n2024 ,
n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 , n2033 , n2034 ,
n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 , n2043 , n2044 ,
n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 , n2053 , n2054 ,
n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 , n2063 , n2064 ,
n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 , n2073 , n2074 ,
n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 , n2083 , n2084 ,
n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 , n2093 , n2094 ,
n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 , n2103 , n2104 ,
n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 , n2113 , n2114 ,
n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 , n2123 , n2124 ,
n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 , n2133 , n2134 ,
n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 , n2143 , n2144 ,
n2145 , n2146 , n2147 , n2148 , n2149 , n2150 , n2151 , n2152 , n2153 , n2154 ,
n2155 , n2156 , n2157 , n2158 , n2159 , n2160 , n2161 , n2162 , n2163 , n2164 ,
n2165 , n2166 , n2167 , n2168 , n2169 , n2170 , n2171 , n2172 , n2173 , n2174 ,
n2175 , n2176 , n2177 , n2178 , n2179 , n2180 , n2181 , n2182 , n2183 , n2184 ,
n2185 , n2186 , n2187 , n2188 , n2189 , n2190 , n2191 , n2192 , n2193 , n2194 ,
n2195 , n2196 , n2197 , n2198 , n2199 , n2200 , n2201 , n2202 , n2203 , n2204 ,
n2205 , n2206 , n2207 , n2208 , n2209 , n2210 , n2211 , n2212 , n2213 , n2214 ,
n2215 , n2216 , n2217 , n2218 , n2219 , n2220 , n2221 , n2222 , n2223 , n2224 ,
n2225 , n2226 , n2227 , n2228 , n2229 , n2230 , n2231 , n2232 , n2233 , n2234 ,
n2235 , n2236 , n2237 , n2238 , n2239 , n2240 , n2241 , n2242 , n2243 , n2244 ,
n2245 , n2246 , n2247 , n2248 , n2249 , n2250 , n2251 , n2252 , n2253 , n2254 ,
n2255 , n2256 , n2257 , n2258 , n2259 , n2260 , n2261 , n2262 , n2263 , n2264 ,
n2265 , n2266 , n2267 , n2268 , n2269 , n2270 , n2271 , n2272 , n2273 , n2274 ,
n2275 , n2276 , n2277 , n2278 , n2279 , n2280 , n2281 , n2282 , n2283 , n2284 ,
n2285 , n2286 , n2287 , n2288 , n2289 , n2290 , n2291 , n2292 , n2293 , n2294 ,
n2295 , n2296 , n2297 , n2298 , n2299 , n2300 , n2301 , n2302 , n2303 , n2304 ,
n2305 , n2306 , n2307 , n2308 , n2309 , n2310 , n2311 , n2312 , n2313 , n2314 ,
n2315 , n2316 , n2317 , n2318 , n2319 , n2320 , n2321 , n2322 , n2323 , n2324 ,
n2325 , n2326 , n2327 , n2328 , n2329 , n2330 , n2331 , n2332 , n2333 , n2334 ,
n2335 , n2336 , n2337 , n2338 , n2339 , n2340 , n2341 , n2342 , n2343 , n2344 ,
n2345 , n2346 , n2347 , n2348 , n2349 , n2350 , n2351 , n2352 , n2353 , n2354 ,
n2355 , n2356 , n2357 , n2358 , n2359 , n2360 , n2361 , n2362 , n2363 , n2364 ,
n2365 , n2366 , n2367 , n2368 , n2369 , n2370 , n2371 , n2372 , n2373 , n2374 ,
n2375 , n2376 , n2377 , n2378 , n2379 , n2380 , n2381 , n2382 , n2383 , n2384 ,
n2385 , n2386 , n2387 , n2388 , n2389 , n2390 , n2391 , n2392 , n2393 , n2394 ,
n2395 , n2396 , n2397 , n2398 , n2399 , n2400 , n2401 , n2402 , n2403 , n2404 ,
n2405 , n2406 , n2407 , n2408 , n2409 , n2410 , n2411 , n2412 , n2413 , n2414 ,
n2415 , n2416 , n2417 , n2418 , n2419 , n2420 , n2421 , n2422 , n2423 , n2424 ,
n2425 , n2426 , n2427 , n2428 , n2429 , n2430 , n2431 , n2432 , n2433 , n2434 ,
n2435 , n2436 , n2437 , n2438 , n2439 , n2440 , n2441 , n2442 , n2443 , n2444 ,
n2445 , n2446 , n2447 , n2448 , n2449 , n2450 , n2451 , n2452 , n2453 , n2454 ,
n2455 , n2456 , n2457 , n2458 , n2459 , n2460 , n2461 , n2462 , n2463 , n2464 ,
n2465 , n2466 , n2467 , n2468 , n2469 , n2470 , n2471 , n2472 , n2473 , n2474 ,
n2475 , n2476 , n2477 , n2478 , n2479 , n2480 , n2481 , n2482 , n2483 , n2484 ,
n2485 , n2486 , n2487 , n2488 , n2489 , n2490 , n2491 , n2492 , n2493 , n2494 ,
n2495 , n2496 , n2497 , n2498 , n2499 , n2500 , n2501 , n2502 , n2503 , n2504 ,
n2505 , n2506 , n2507 , n2508 , n2509 , n2510 , n2511 , n2512 , n2513 , n2514 ,
n2515 , n2516 , n2517 , n2518 , n2519 , n2520 , n2521 , n2522 , n2523 , n2524 ,
n2525 , n2526 , n2527 , n2528 , n2529 , n2530 , n2531 , n2532 , n2533 , n2534 ,
n2535 , n2536 , n2537 , n2538 , n2539 , n2540 , n2541 , n2542 , n2543 , n2544 ,
n2545 , n2546 , n2547 , n2548 , n2549 , n2550 , n2551 , n2552 , n2553 , n2554 ,
n2555 , n2556 , n2557 , n2558 , n2559 , n2560 , n2561 , n2562 , n2563 , n2564 ,
n2565 , n2566 , n2567 , n2568 , n2569 , n2570 , n2571 , n2572 , n2573 , n2574 ,
n2575 , n2576 , n2577 , n2578 , n2579 , n2580 , n2581 , n2582 , n2583 , n2584 ,
n2585 , n2586 , n2587 , n2588 , n2589 , n2590 , n2591 , n2592 , n2593 , n2594 ,
n2595 , n2596 , n2597 , n2598 , n2599 , n2600 , n2601 , n2602 , n2603 , n2604 ,
n2605 , n2606 , n2607 , n2608 , n2609 , n2610 , n2611 , n2612 , n2613 , n2614 ,
n2615 , n2616 , n2617 , n2618 , n2619 , n2620 , n2621 , n2622 , n2623 , n2624 ,
n2625 , n2626 , n2627 , n2628 , n2629 , n2630 , n2631 , n2632 , n2633 , n2634 ,
n2635 , n2636 , n2637 , n2638 , n2639 , n2640 , n2641 , n2642 , n2643 , n2644 ,
n2645 , n2646 , n2647 , n2648 , n2649 , n2650 , n2651 , n2652 , n2653 , n2654 ,
n2655 , n2656 , n2657 , n2658 , n2659 , n2660 , n2661 , n2662 , n2663 , n2664 ,
n2665 , n2666 , n2667 , n2668 , n2669 , n2670 , n2671 , n2672 , n2673 , n2674 ,
n2675 , n2676 , n2677 , n2678 , n2679 , n2680 , n2681 , n2682 , n2683 , n2684 ,
n2685 , n2686 , n2687 , n2688 , n2689 , n2690 , n2691 , n2692 , n2693 , n2694 ,
n2695 , n2696 , n2697 , n2698 , n2699 , n2700 , n2701 , n2702 , n2703 , n2704 ,
n2705 , n2706 , n2707 , n2708 , n2709 , n2710 , n2711 , n2712 , n2713 , n2714 ,
n2715 , n2716 , n2717 , n2718 , n2719 , n2720 , n2721 , n2722 , n2723 , n2724 ,
n2725 , n2726 , n2727 , n2728 , n2729 , n2730 , n2731 , n2732 , n2733 , n2734 ,
n2735 , n2736 , n2737 , n2738 , n2739 , n2740 , n2741 , n2742 , n2743 , n2744 ,
n2745 , n2746 , n2747 , n2748 , n2749 , n2750 , n2751 , n2752 , n2753 , n2754 ,
n2755 , n2756 , n2757 , n2758 , n2759 , n2760 , n2761 , n2762 , n2763 , n2764 ,
n2765 , n2766 , n2767 , n2768 , n2769 , n2770 , n2771 , n2772 , n2773 , n2774 ,
n2775 , n2776 , n2777 , n2778 , n2779 , n2780 , n2781 , n2782 , n2783 , n2784 ,
n2785 , n2786 , n2787 , n2788 , n2789 , n2790 , n2791 , n2792 , n2793 , n2794 ,
n2795 , n2796 , n2797 , n2798 , n2799 , n2800 , n2801 , n2802 , n2803 , n2804 ,
n2805 , n2806 , n2807 , n2808 , n2809 , n2810 , n2811 , n2812 , n2813 , n2814 ,
n2815 , n2816 , n2817 , n2818 , n2819 , n2820 , n2821 , n2822 , n2823 , n2824 ,
n2825 , n2826 , n2827 , n2828 , n2829 , n2830 , n2831 , n2832 , n2833 , n2834 ,
n2835 , n2836 , n2837 , n2838 , n2839 , n2840 , n2841 , n2842 , n2843 , n2844 ,
n2845 , n2846 , n2847 , n2848 , n2849 , n2850 , n2851 , n2852 , n2853 , n2854 ,
n2855 , n2856 , n2857 , n2858 , n2859 , n2860 , n2861 , n2862 , n2863 , n2864 ,
n2865 , n2866 , n2867 , n2868 , n2869 , n2870 , n2871 , n2872 , n2873 , n2874 ,
n2875 , n2876 , n2877 , n2878 , n2879 , n2880 , n2881 , n2882 , n2883 , n2884 ,
n2885 , n2886 , n2887 , n2888 , n2889 , n2890 , n2891 , n2892 , n2893 , n2894 ,
n2895 , n2896 , n2897 , n2898 , n2899 , n2900 , n2901 , n2902 , n2903 , n2904 ,
n2905 , n2906 , n2907 , n2908 , n2909 , n2910 , n2911 , n2912 , n2913 , n2914 ,
n2915 , n2916 , n2917 , n2918 , n2919 , n2920 , n2921 , n2922 , n2923 , n2924 ,
n2925 , n2926 , n2927 , n2928 , n2929 , n2930 , n2931 , n2932 , n2933 , n2934 ,
n2935 , n2936 , n2937 , n2938 , n2939 , n2940 , n2941 , n2942 , n2943 , n2944 ,
n2945 , n2946 , n2947 , n2948 , n2949 , n2950 , n2951 , n2952 , n2953 , n2954 ,
n2955 , n2956 , n2957 , n2958 , n2959 , n2960 , n2961 , n2962 , n2963 , n2964 ,
n2965 , n2966 , n2967 , n2968 , n2969 , n2970 , n2971 , n2972 , n2973 , n2974 ,
n2975 , n2976 , n2977 , n2978 , n2979 , n2980 , n2981 , n2982 , n2983 , n2984 ,
n2985 , n2986 , n2987 , n2988 , n2989 , n2990 , n2991 , n2992 , n2993 , n2994 ,
n2995 , n2996 , n2997 , n2998 , n2999 , n3000 , n3001 , n3002 , n3003 , n3004 ,
n3005 , n3006 , n3007 , n3008 , n3009 , n3010 , n3011 , n3012 , n3013 , n3014 ,
n3015 , n3016 , n3017 , n3018 , n3019 , n3020 , n3021 , n3022 , n3023 , n3024 ,
n3025 , n3026 , n3027 , n3028 , n3029 , n3030 , n3031 , n3032 , n3033 , n3034 ,
n3035 , n3036 , n3037 , n3038 , n3039 , n3040 , n3041 , n3042 , n3043 , n3044 ,
n3045 , n3046 , n3047 , n3048 , n3049 , n3050 , n3051 , n3052 , n3053 , n3054 ,
n3055 , n3056 , n3057 , n3058 , n3059 , n3060 , n3061 , n3062 , n3063 , n3064 ,
n3065 , n3066 , n3067 , n3068 , n3069 , n3070 , n3071 , n3072 , n3073 , n3074 ,
n3075 , n3076 , n3077 , n3078 , n3079 , n3080 , n3081 , n3082 , n3083 , n3084 ,
n3085 , n3086 , n3087 , n3088 , n3089 , n3090 , n3091 , n3092 , n3093 , n3094 ,
n3095 , n3096 , n3097 , n3098 , n3099 , n3100 , n3101 , n3102 , n3103 , n3104 ,
n3105 , n3106 , n3107 , n3108 , n3109 , n3110 , n3111 , n3112 , n3113 , n3114 ,
n3115 , n3116 , n3117 , n3118 , n3119 , n3120 , n3121 , n3122 , n3123 , n3124 ,
n3125 , n3126 , n3127 , n3128 , n3129 , n3130 , n3131 , n3132 , n3133 , n3134 ,
n3135 , n3136 , n3137 , n3138 , n3139 , n3140 , n3141 , n3142 , n3143 , n3144 ,
n3145 , n3146 , n3147 , n3148 , n3149 , n3150 , n3151 , n3152 , n3153 , n3154 ,
n3155 , n3156 , n3157 , n3158 , n3159 , n3160 , n3161 , n3162 , n3163 , n3164 ,
n3165 , n3166 , n3167 , n3168 , n3169 , n3170 , n3171 , n3172 , n3173 , n3174 ,
n3175 , n3176 , n3177 , n3178 , n3179 , n3180 , n3181 , n3182 , n3183 , n3184 ,
n3185 , n3186 , n3187 , n3188 , n3189 , n3190 , n3191 , n3192 , n3193 , n3194 ,
n3195 , n3196 , n3197 , n3198 , n3199 , n3200 , n3201 , n3202 , n3203 , n3204 ,
n3205 , n3206 , n3207 , n3208 , n3209 , n3210 , n3211 , n3212 , n3213 , n3214 ,
n3215 , n3216 , n3217 , n3218 , n3219 , n3220 , n3221 , n3222 , n3223 , n3224 ,
n3225 , n3226 , n3227 , n3228 , n3229 , n3230 , n3231 , n3232 , n3233 , n3234 ,
n3235 , n3236 , n3237 , n3238 , n3239 , n3240 , n3241 , n3242 , n3243 , n3244 ,
n3245 , n3246 , n3247 , n3248 , n3249 , n3250 , n3251 , n3252 , n3253 , n3254 ,
n3255 , n3256 , n3257 , n3258 , n3259 , n3260 , n3261 , n3262 , n3263 , n3264 ,
n3265 , n3266 , n3267 , n3268 , n3269 , n3270 , n3271 , n3272 , n3273 , n3274 ,
n3275 , n3276 , n3277 , n3278 , n3279 , n3280 , n3281 , n3282 , n3283 , n3284 ,
n3285 , n3286 , n3287 , n3288 , n3289 , n3290 , n3291 , n3292 , n3293 , n3294 ,
n3295 , n3296 , n3297 , n3298 , n3299 , n3300 , n3301 , n3302 , n3303 , n3304 ,
n3305 , n3306 , n3307 , n3308 , n3309 , n3310 , n3311 , n3312 , n3313 , n3314 ,
n3315 , n3316 , n3317 , n3318 , n3319 , n3320 , n3321 , n3322 , n3323 , n3324 ,
n3325 , n3326 , n3327 , n3328 , n3329 , n3330 , n3331 , n3332 , n3333 , n3334 ,
n3335 , n3336 , n3337 , n3338 , n3339 , n3340 , n3341 , n3342 , n3343 , n3344 ,
n3345 , n3346 , n3347 , n3348 , n3349 , n3350 , n3351 , n3352 , n3353 , n3354 ,
n3355 , n3356 , n3357 , n3358 , n3359 , n3360 , n3361 , n3362 , n3363 , n3364 ,
n3365 , n3366 , n3367 , n3368 , n3369 , n3370 , n3371 , n3372 , n3373 , n3374 ,
n3375 , n3376 , n3377 , n3378 , n3379 , n3380 , n3381 , n3382 , n3383 , n3384 ,
n3385 , n3386 , n3387 , n3388 , n3389 , n3390 , n3391 , n3392 , n3393 , n3394 ,
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buf ( n247 , 1'b0 );
buf ( n249 , n5217 );
buf ( n250 , n5218 );
buf ( n253 , n5290 );
buf ( n245 , 1'b0 );
buf ( n652 , PI_PI_clock);
buf ( n653 , PI_PI_reset);
buf ( n654 , n6 );
buf ( n655 , n50 );
buf ( n656 , n58 );
buf ( n657 , n76 );
buf ( n658 , n71 );
buf ( n659 , n163 );
buf ( n660 , n234 );
buf ( n661 , n39 );
buf ( n662 , n225 );
buf ( n663 , n144 );
buf ( n664 , n156 );
buf ( n665 , n217 );
buf ( n666 , n194 );
buf ( n667 , n114 );
buf ( n668 , n17 );
buf ( n669 , n160 );
buf ( n670 , n209 );
buf ( n671 , n137 );
buf ( n672 , n167 );
buf ( n673 , n140 );
buf ( n674 , n147 );
buf ( n675 , n195 );
buf ( n676 , n60 );
buf ( n677 , n73 );
buf ( n678 , n242 );
buf ( n679 , n25 );
buf ( n680 , n223 );
buf ( n681 , n150 );
buf ( n682 , n227 );
buf ( n683 , n92 );
buf ( n684 , n54 );
buf ( n685 , n123 );
buf ( n686 , PI_DFF_state_reg_Q);
buf ( n687 , n190 );
buf ( n688 , n237 );
buf ( n689 , n183 );
buf ( n690 , n161 );
buf ( n691 , n86 );
buf ( n692 , n91 );
buf ( n693 , n178 );
buf ( n694 , n119 );
buf ( n695 , n11 );
buf ( n696 , n218 );
buf ( n697 , n192 );
buf ( n698 , n166 );
buf ( n699 , n63 );
buf ( n700 , n145 );
buf ( n701 , n38 );
buf ( n702 , n1 );
buf ( n703 , n3 );
buf ( n704 , n122 );
buf ( n705 , n40 );
buf ( n706 , n230 );
buf ( n707 , n228 );
buf ( n708 , n138 );
buf ( n709 , n32 );
buf ( n710 , n168 );
buf ( n711 , n0 );
buf ( n712 , n61 );
buf ( n713 , n26 );
buf ( n714 , n191 );
buf ( n715 , n68 );
buf ( n716 , n204 );
buf ( n717 , n197 );
buf ( n718 , n128 );
buf ( n719 , n34 );
buf ( n720 , n141 );
buf ( n721 , n108 );
buf ( n722 , n42 );
buf ( n723 , n117 );
buf ( n724 , n151 );
buf ( n725 , n198 );
buf ( n726 , n74 );
buf ( n727 , n111 );
buf ( n728 , n16 );
buf ( n729 , n79 );
buf ( n730 , n15 );
buf ( n731 , n52 );
buf ( n732 , n72 );
buf ( n733 , n124 );
buf ( n734 , n19 );
buf ( n735 , n98 );
buf ( n736 , n31 );
buf ( n737 , n81 );
buf ( n738 , n14 );
buf ( n739 , n200 );
buf ( n740 , n220 );
buf ( n741 , n43 );
buf ( n742 , n224 );
buf ( n743 , n233 );
buf ( n744 , n196 );
buf ( n745 , n132 );
buf ( n746 , n184 );
buf ( n747 , n94 );
buf ( n748 , n109 );
buf ( n749 , n21 );
buf ( n750 , n10 );
buf ( n751 , n95 );
buf ( n752 , n110 );
buf ( n753 , n78 );
buf ( n754 , n29 );
buf ( n755 , n189 );
buf ( n756 , n212 );
buf ( n757 , n51 );
buf ( n758 , n49 );
buf ( n759 , n77 );
buf ( n760 , n90 );
buf ( n761 , n4 );
buf ( n762 , n148 );
buf ( n763 , n7 );
buf ( n764 , n181 );
buf ( n765 , n9 );
buf ( n766 , n87 );
buf ( n767 , n232 );
buf ( n768 , n177 );
buf ( n769 , n240 );
buf ( n770 , n105 );
buf ( n771 , n236 );
buf ( n772 , n45 );
buf ( n773 , n30 );
buf ( n774 , n57 );
buf ( n775 , n65 );
buf ( n776 , n241 );
buf ( n777 , n202 );
buf ( n778 , n18 );
buf ( n779 , n106 );
buf ( n780 , n149 );
buf ( n781 , n113 );
buf ( n782 , n23 );
buf ( n783 , n101 );
buf ( n784 , n206 );
buf ( n785 , n2 );
buf ( n786 , n231 );
buf ( n787 , n70 );
buf ( n788 , n59 );
buf ( n789 , n180 );
buf ( n790 , n12 );
buf ( n791 , n172 );
buf ( n792 , n219 );
buf ( n793 , n80 );
buf ( n794 , n121 );
buf ( n795 , n8 );
buf ( n796 , n36 );
buf ( n797 , n207 );
buf ( n798 , n53 );
buf ( n799 , n69 );
buf ( n800 , n107 );
buf ( n801 , n176 );
buf ( n802 , n64 );
buf ( n803 , n136 );
buf ( n804 , n55 );
buf ( n805 , n130 );
buf ( n806 , n125 );
buf ( n807 , n157 );
buf ( n808 , n100 );
buf ( n809 , n99 );
buf ( n810 , n187 );
buf ( n811 , n96 );
buf ( n812 , n154 );
buf ( n813 , n164 );
buf ( n814 , PI_DFF_B_reg_Q);
buf ( n815 , n214 );
buf ( n816 , n135 );
buf ( n817 , n46 );
buf ( n818 , n5 );
buf ( n819 , n24 );
buf ( n820 , n13 );
buf ( n821 , n222 );
buf ( n822 , n118 );
buf ( n823 , n97 );
buf ( n824 , n238 );
buf ( n825 , n169 );
buf ( n826 , n133 );
buf ( n827 , n89 );
buf ( n828 , n142 );
buf ( n829 , n146 );
buf ( n830 , n213 );
buf ( n831 , n188 );
buf ( n832 , n44 );
buf ( n833 , n28 );
buf ( n834 , n112 );
buf ( n835 , n22 );
buf ( n836 , n171 );
buf ( n837 , n179 );
buf ( n838 , n162 );
buf ( n839 , n102 );
buf ( n840 , n186 );
buf ( n841 , n175 );
buf ( n842 , n203 );
buf ( n843 , n83 );
buf ( n844 , n153 );
buf ( n845 , n67 );
buf ( n846 , n210 );
buf ( n847 , n652 );
buf ( n848 , n847 );
buf ( n849 , n718 );
not ( n850 , n849 );
buf ( n851 , n717 );
not ( n852 , n851 );
buf ( n853 , n716 );
not ( n854 , n853 );
buf ( n855 , n715 );
not ( n856 , n855 );
buf ( n857 , n714 );
not ( n858 , n857 );
buf ( n859 , n713 );
not ( n860 , n859 );
buf ( n861 , n712 );
not ( n862 , n861 );
buf ( n863 , n711 );
not ( n864 , n863 );
buf ( n865 , n710 );
not ( n866 , n865 );
buf ( n867 , n709 );
not ( n868 , n867 );
buf ( n869 , n708 );
not ( n870 , n869 );
buf ( n871 , n707 );
not ( n872 , n871 );
buf ( n873 , n706 );
not ( n874 , n873 );
buf ( n875 , n705 );
not ( n876 , n875 );
buf ( n877 , n704 );
not ( n878 , n877 );
buf ( n879 , n703 );
not ( n880 , n879 );
buf ( n881 , n702 );
not ( n882 , n881 );
buf ( n883 , n701 );
not ( n884 , n883 );
buf ( n885 , n700 );
not ( n886 , n885 );
buf ( n887 , n699 );
not ( n888 , n887 );
buf ( n889 , n698 );
not ( n890 , n889 );
buf ( n891 , n697 );
not ( n892 , n891 );
buf ( n893 , n696 );
not ( n894 , n893 );
buf ( n895 , n695 );
not ( n896 , n895 );
buf ( n897 , n694 );
not ( n898 , n897 );
buf ( n899 , n693 );
not ( n900 , n899 );
buf ( n901 , n692 );
not ( n902 , n901 );
buf ( n903 , n691 );
not ( n904 , n903 );
buf ( n905 , n690 );
not ( n906 , n905 );
buf ( n907 , n689 );
not ( n908 , n907 );
buf ( n909 , n688 );
not ( n910 , n909 );
buf ( n911 , n687 );
not ( n912 , n911 );
and ( n913 , n910 , n912 );
and ( n914 , n908 , n913 );
and ( n915 , n906 , n914 );
and ( n916 , n904 , n915 );
and ( n917 , n902 , n916 );
and ( n918 , n900 , n917 );
and ( n919 , n898 , n918 );
and ( n920 , n896 , n919 );
and ( n921 , n894 , n920 );
and ( n922 , n892 , n921 );
and ( n923 , n890 , n922 );
and ( n924 , n888 , n923 );
and ( n925 , n886 , n924 );
and ( n926 , n884 , n925 );
and ( n927 , n882 , n926 );
and ( n928 , n880 , n927 );
and ( n929 , n878 , n928 );
and ( n930 , n876 , n929 );
and ( n931 , n874 , n930 );
and ( n932 , n872 , n931 );
and ( n933 , n870 , n932 );
and ( n934 , n868 , n933 );
and ( n935 , n866 , n934 );
and ( n936 , n864 , n935 );
and ( n937 , n862 , n936 );
and ( n938 , n860 , n937 );
and ( n939 , n858 , n938 );
and ( n940 , n856 , n939 );
and ( n941 , n854 , n940 );
and ( n942 , n852 , n941 );
xor ( n943 , n850 , n942 );
buf ( n944 , n849 );
and ( n945 , n943 , n944 );
buf ( n946 , n945 );
not ( n947 , n946 );
not ( n948 , n849 );
and ( n949 , n948 , n865 );
xor ( n950 , n866 , n934 );
and ( n951 , n950 , n849 );
or ( n952 , n949 , n951 );
and ( n953 , n947 , n952 );
not ( n954 , n952 );
not ( n955 , n849 );
and ( n956 , n955 , n867 );
xor ( n957 , n868 , n933 );
and ( n958 , n957 , n849 );
or ( n959 , n956 , n958 );
not ( n960 , n959 );
not ( n961 , n849 );
and ( n962 , n961 , n869 );
xor ( n963 , n870 , n932 );
and ( n964 , n963 , n849 );
or ( n965 , n962 , n964 );
not ( n966 , n965 );
not ( n967 , n849 );
and ( n968 , n967 , n871 );
xor ( n969 , n872 , n931 );
and ( n970 , n969 , n849 );
or ( n971 , n968 , n970 );
not ( n972 , n971 );
not ( n973 , n849 );
and ( n974 , n973 , n873 );
xor ( n975 , n874 , n930 );
and ( n976 , n975 , n849 );
or ( n977 , n974 , n976 );
not ( n978 , n977 );
not ( n979 , n849 );
and ( n980 , n979 , n875 );
xor ( n981 , n876 , n929 );
and ( n982 , n981 , n849 );
or ( n983 , n980 , n982 );
not ( n984 , n983 );
not ( n985 , n849 );
and ( n986 , n985 , n877 );
xor ( n987 , n878 , n928 );
and ( n988 , n987 , n849 );
or ( n989 , n986 , n988 );
not ( n990 , n989 );
not ( n991 , n849 );
and ( n992 , n991 , n879 );
xor ( n993 , n880 , n927 );
and ( n994 , n993 , n849 );
or ( n995 , n992 , n994 );
not ( n996 , n995 );
not ( n997 , n849 );
and ( n998 , n997 , n881 );
xor ( n999 , n882 , n926 );
and ( n1000 , n999 , n849 );
or ( n1001 , n998 , n1000 );
not ( n1002 , n1001 );
not ( n1003 , n849 );
and ( n1004 , n1003 , n883 );
xor ( n1005 , n884 , n925 );
and ( n1006 , n1005 , n849 );
or ( n1007 , n1004 , n1006 );
not ( n1008 , n1007 );
not ( n1009 , n849 );
and ( n1010 , n1009 , n885 );
xor ( n1011 , n886 , n924 );
and ( n1012 , n1011 , n849 );
or ( n1013 , n1010 , n1012 );
not ( n1014 , n1013 );
not ( n1015 , n849 );
and ( n1016 , n1015 , n887 );
xor ( n1017 , n888 , n923 );
and ( n1018 , n1017 , n849 );
or ( n1019 , n1016 , n1018 );
not ( n1020 , n1019 );
not ( n1021 , n849 );
and ( n1022 , n1021 , n889 );
xor ( n1023 , n890 , n922 );
and ( n1024 , n1023 , n849 );
or ( n1025 , n1022 , n1024 );
not ( n1026 , n1025 );
not ( n1027 , n849 );
and ( n1028 , n1027 , n891 );
xor ( n1029 , n892 , n921 );
and ( n1030 , n1029 , n849 );
or ( n1031 , n1028 , n1030 );
not ( n1032 , n1031 );
not ( n1033 , n849 );
and ( n1034 , n1033 , n893 );
xor ( n1035 , n894 , n920 );
and ( n1036 , n1035 , n849 );
or ( n1037 , n1034 , n1036 );
not ( n1038 , n1037 );
not ( n1039 , n849 );
and ( n1040 , n1039 , n895 );
xor ( n1041 , n896 , n919 );
and ( n1042 , n1041 , n849 );
or ( n1043 , n1040 , n1042 );
not ( n1044 , n1043 );
not ( n1045 , n849 );
and ( n1046 , n1045 , n897 );
xor ( n1047 , n898 , n918 );
and ( n1048 , n1047 , n849 );
or ( n1049 , n1046 , n1048 );
not ( n1050 , n1049 );
not ( n1051 , n849 );
and ( n1052 , n1051 , n899 );
xor ( n1053 , n900 , n917 );
and ( n1054 , n1053 , n849 );
or ( n1055 , n1052 , n1054 );
not ( n1056 , n1055 );
not ( n1057 , n849 );
and ( n1058 , n1057 , n901 );
xor ( n1059 , n902 , n916 );
and ( n1060 , n1059 , n849 );
or ( n1061 , n1058 , n1060 );
not ( n1062 , n1061 );
not ( n1063 , n849 );
and ( n1064 , n1063 , n903 );
xor ( n1065 , n904 , n915 );
and ( n1066 , n1065 , n849 );
or ( n1067 , n1064 , n1066 );
not ( n1068 , n1067 );
not ( n1069 , n849 );
and ( n1070 , n1069 , n905 );
xor ( n1071 , n906 , n914 );
and ( n1072 , n1071 , n849 );
or ( n1073 , n1070 , n1072 );
not ( n1074 , n1073 );
not ( n1075 , n849 );
and ( n1076 , n1075 , n907 );
xor ( n1077 , n908 , n913 );
and ( n1078 , n1077 , n849 );
or ( n1079 , n1076 , n1078 );
not ( n1080 , n1079 );
not ( n1081 , n849 );
and ( n1082 , n1081 , n909 );
xor ( n1083 , n910 , n912 );
and ( n1084 , n1083 , n849 );
or ( n1085 , n1082 , n1084 );
not ( n1086 , n1085 );
not ( n1087 , n911 );
and ( n1088 , n1086 , n1087 );
and ( n1089 , n1080 , n1088 );
and ( n1090 , n1074 , n1089 );
and ( n1091 , n1068 , n1090 );
and ( n1092 , n1062 , n1091 );
and ( n1093 , n1056 , n1092 );
and ( n1094 , n1050 , n1093 );
and ( n1095 , n1044 , n1094 );
and ( n1096 , n1038 , n1095 );
and ( n1097 , n1032 , n1096 );
and ( n1098 , n1026 , n1097 );
and ( n1099 , n1020 , n1098 );
and ( n1100 , n1014 , n1099 );
and ( n1101 , n1008 , n1100 );
and ( n1102 , n1002 , n1101 );
and ( n1103 , n996 , n1102 );
and ( n1104 , n990 , n1103 );
and ( n1105 , n984 , n1104 );
and ( n1106 , n978 , n1105 );
and ( n1107 , n972 , n1106 );
and ( n1108 , n966 , n1107 );
and ( n1109 , n960 , n1108 );
xor ( n1110 , n954 , n1109 );
and ( n1111 , n1110 , n946 );
or ( n1112 , n953 , n1111 );
not ( n1113 , n1112 );
not ( n1114 , n1113 );
not ( n1115 , n1114 );
not ( n1116 , n1115 );
buf ( n1117 , n1116 );
buf ( n1118 , n1117 );
not ( n1119 , n946 );
not ( n1120 , n849 );
and ( n1121 , n1120 , n851 );
xor ( n1122 , n852 , n941 );
and ( n1123 , n1122 , n849 );
or ( n1124 , n1121 , n1123 );
not ( n1125 , n1124 );
not ( n1126 , n849 );
and ( n1127 , n1126 , n853 );
xor ( n1128 , n854 , n940 );
and ( n1129 , n1128 , n849 );
or ( n1130 , n1127 , n1129 );
not ( n1131 , n1130 );
not ( n1132 , n849 );
and ( n1133 , n1132 , n855 );
xor ( n1134 , n856 , n939 );
and ( n1135 , n1134 , n849 );
or ( n1136 , n1133 , n1135 );
not ( n1137 , n1136 );
not ( n1138 , n849 );
and ( n1139 , n1138 , n857 );
xor ( n1140 , n858 , n938 );
and ( n1141 , n1140 , n849 );
or ( n1142 , n1139 , n1141 );
not ( n1143 , n1142 );
not ( n1144 , n849 );
and ( n1145 , n1144 , n859 );
xor ( n1146 , n860 , n937 );
and ( n1147 , n1146 , n849 );
or ( n1148 , n1145 , n1147 );
not ( n1149 , n1148 );
not ( n1150 , n849 );
and ( n1151 , n1150 , n861 );
xor ( n1152 , n862 , n936 );
and ( n1153 , n1152 , n849 );
or ( n1154 , n1151 , n1153 );
not ( n1155 , n1154 );
not ( n1156 , n849 );
and ( n1157 , n1156 , n863 );
xor ( n1158 , n864 , n935 );
and ( n1159 , n1158 , n849 );
or ( n1160 , n1157 , n1159 );
not ( n1161 , n1160 );
and ( n1162 , n954 , n1109 );
and ( n1163 , n1161 , n1162 );
and ( n1164 , n1155 , n1163 );
and ( n1165 , n1149 , n1164 );
and ( n1166 , n1143 , n1165 );
and ( n1167 , n1137 , n1166 );
and ( n1168 , n1131 , n1167 );
and ( n1169 , n1125 , n1168 );
xor ( n1170 , n1119 , n1169 );
buf ( n1171 , n946 );
and ( n1172 , n1170 , n1171 );
buf ( n1173 , n1172 );
not ( n1174 , n1173 );
not ( n1175 , n1174 );
not ( n1176 , n1175 );
not ( n1177 , n946 );
and ( n1178 , n1177 , n1124 );
xor ( n1179 , n1125 , n1168 );
and ( n1180 , n1179 , n946 );
or ( n1181 , n1178 , n1180 );
not ( n1182 , n1181 );
not ( n1183 , n1182 );
not ( n1184 , n1183 );
not ( n1185 , n946 );
and ( n1186 , n1185 , n1130 );
xor ( n1187 , n1131 , n1167 );
and ( n1188 , n1187 , n946 );
or ( n1189 , n1186 , n1188 );
not ( n1190 , n1189 );
not ( n1191 , n1190 );
not ( n1192 , n1191 );
not ( n1193 , n946 );
and ( n1194 , n1193 , n1136 );
xor ( n1195 , n1137 , n1166 );
and ( n1196 , n1195 , n946 );
or ( n1197 , n1194 , n1196 );
not ( n1198 , n1197 );
not ( n1199 , n1198 );
not ( n1200 , n1199 );
not ( n1201 , n946 );
and ( n1202 , n1201 , n1142 );
xor ( n1203 , n1143 , n1165 );
and ( n1204 , n1203 , n946 );
or ( n1205 , n1202 , n1204 );
not ( n1206 , n1205 );
not ( n1207 , n1206 );
not ( n1208 , n1207 );
not ( n1209 , n946 );
and ( n1210 , n1209 , n1148 );
xor ( n1211 , n1149 , n1164 );
and ( n1212 , n1211 , n946 );
or ( n1213 , n1210 , n1212 );
not ( n1214 , n1213 );
not ( n1215 , n1214 );
not ( n1216 , n1215 );
not ( n1217 , n946 );
and ( n1218 , n1217 , n1154 );
xor ( n1219 , n1155 , n1163 );
and ( n1220 , n1219 , n946 );
or ( n1221 , n1218 , n1220 );
not ( n1222 , n1221 );
not ( n1223 , n1222 );
not ( n1224 , n1223 );
not ( n1225 , n946 );
and ( n1226 , n1225 , n1160 );
xor ( n1227 , n1161 , n1162 );
and ( n1228 , n1227 , n946 );
or ( n1229 , n1226 , n1228 );
not ( n1230 , n1229 );
not ( n1231 , n1230 );
not ( n1232 , n1231 );
not ( n1233 , n1114 );
and ( n1234 , n1232 , n1233 );
and ( n1235 , n1224 , n1234 );
and ( n1236 , n1216 , n1235 );
and ( n1237 , n1208 , n1236 );
and ( n1238 , n1200 , n1237 );
and ( n1239 , n1192 , n1238 );
and ( n1240 , n1184 , n1239 );
and ( n1241 , n1176 , n1240 );
not ( n1242 , n1241 );
and ( n1243 , n1242 , n946 );
buf ( n1244 , n1243 );
and ( n1245 , n1118 , n1244 );
not ( n1246 , n1245 );
and ( n1247 , n1246 , n1116 );
xor ( n1248 , n1116 , n1244 );
xor ( n1249 , n1248 , n1244 );
and ( n1250 , n1249 , n1245 );
or ( n1251 , n1247 , n1250 );
not ( n1252 , n946 );
and ( n1253 , n1252 , n1160 );
not ( n1254 , n1160 );
not ( n1255 , n952 );
not ( n1256 , n959 );
not ( n1257 , n965 );
not ( n1258 , n971 );
not ( n1259 , n977 );
not ( n1260 , n983 );
not ( n1261 , n989 );
not ( n1262 , n995 );
not ( n1263 , n1001 );
not ( n1264 , n1007 );
not ( n1265 , n1013 );
not ( n1266 , n1019 );
not ( n1267 , n1025 );
not ( n1268 , n1031 );
not ( n1269 , n1037 );
not ( n1270 , n1043 );
not ( n1271 , n1049 );
not ( n1272 , n1055 );
not ( n1273 , n1061 );
not ( n1274 , n1067 );
not ( n1275 , n1073 );
not ( n1276 , n1079 );
not ( n1277 , n1085 );
not ( n1278 , n911 );
and ( n1279 , n1277 , n1278 );
and ( n1280 , n1276 , n1279 );
and ( n1281 , n1275 , n1280 );
and ( n1282 , n1274 , n1281 );
and ( n1283 , n1273 , n1282 );
and ( n1284 , n1272 , n1283 );
and ( n1285 , n1271 , n1284 );
and ( n1286 , n1270 , n1285 );
and ( n1287 , n1269 , n1286 );
and ( n1288 , n1268 , n1287 );
and ( n1289 , n1267 , n1288 );
and ( n1290 , n1266 , n1289 );
and ( n1291 , n1265 , n1290 );
and ( n1292 , n1264 , n1291 );
and ( n1293 , n1263 , n1292 );
and ( n1294 , n1262 , n1293 );
and ( n1295 , n1261 , n1294 );
and ( n1296 , n1260 , n1295 );
and ( n1297 , n1259 , n1296 );
and ( n1298 , n1258 , n1297 );
and ( n1299 , n1257 , n1298 );
and ( n1300 , n1256 , n1299 );
and ( n1301 , n1255 , n1300 );
xor ( n1302 , n1254 , n1301 );
and ( n1303 , n1302 , n946 );
or ( n1304 , n1253 , n1303 );
not ( n1305 , n1304 );
not ( n1306 , n1305 );
not ( n1307 , n1306 );
not ( n1308 , n1307 );
not ( n1309 , n946 );
not ( n1310 , n1124 );
not ( n1311 , n1130 );
not ( n1312 , n1136 );
not ( n1313 , n1142 );
not ( n1314 , n1148 );
not ( n1315 , n1154 );
and ( n1316 , n1254 , n1301 );
and ( n1317 , n1315 , n1316 );
and ( n1318 , n1314 , n1317 );
and ( n1319 , n1313 , n1318 );
and ( n1320 , n1312 , n1319 );
and ( n1321 , n1311 , n1320 );
and ( n1322 , n1310 , n1321 );
xor ( n1323 , n1309 , n1322 );
buf ( n1324 , n946 );
and ( n1325 , n1323 , n1324 );
buf ( n1326 , n1325 );
not ( n1327 , n1326 );
not ( n1328 , n1327 );
not ( n1329 , n1328 );
not ( n1330 , n946 );
and ( n1331 , n1330 , n1124 );
xor ( n1332 , n1310 , n1321 );
and ( n1333 , n1332 , n946 );
or ( n1334 , n1331 , n1333 );
not ( n1335 , n1334 );
not ( n1336 , n1335 );
not ( n1337 , n1336 );
not ( n1338 , n946 );
and ( n1339 , n1338 , n1130 );
xor ( n1340 , n1311 , n1320 );
and ( n1341 , n1340 , n946 );
or ( n1342 , n1339 , n1341 );
not ( n1343 , n1342 );
not ( n1344 , n1343 );
not ( n1345 , n1344 );
not ( n1346 , n946 );
and ( n1347 , n1346 , n1136 );
xor ( n1348 , n1312 , n1319 );
and ( n1349 , n1348 , n946 );
or ( n1350 , n1347 , n1349 );
not ( n1351 , n1350 );
not ( n1352 , n1351 );
not ( n1353 , n1352 );
not ( n1354 , n946 );
and ( n1355 , n1354 , n1142 );
xor ( n1356 , n1313 , n1318 );
and ( n1357 , n1356 , n946 );
or ( n1358 , n1355 , n1357 );
not ( n1359 , n1358 );
not ( n1360 , n1359 );
not ( n1361 , n1360 );
not ( n1362 , n946 );
and ( n1363 , n1362 , n1148 );
xor ( n1364 , n1314 , n1317 );
and ( n1365 , n1364 , n946 );
or ( n1366 , n1363 , n1365 );
not ( n1367 , n1366 );
not ( n1368 , n1367 );
not ( n1369 , n1368 );
not ( n1370 , n946 );
and ( n1371 , n1370 , n1154 );
xor ( n1372 , n1315 , n1316 );
and ( n1373 , n1372 , n946 );
or ( n1374 , n1371 , n1373 );
not ( n1375 , n1374 );
not ( n1376 , n1375 );
not ( n1377 , n1376 );
not ( n1378 , n1306 );
and ( n1379 , n1377 , n1378 );
and ( n1380 , n1369 , n1379 );
and ( n1381 , n1361 , n1380 );
and ( n1382 , n1353 , n1381 );
and ( n1383 , n1345 , n1382 );
and ( n1384 , n1337 , n1383 );
and ( n1385 , n1329 , n1384 );
not ( n1386 , n1385 );
and ( n1387 , n1386 , n946 );
buf ( n1388 , n1387 );
not ( n1389 , n1388 );
not ( n1390 , n946 );
and ( n1391 , n1390 , n1376 );
xor ( n1392 , n1377 , n1378 );
and ( n1393 , n1392 , n946 );
or ( n1394 , n1391 , n1393 );
and ( n1395 , n1389 , n1394 );
not ( n1396 , n1394 );
not ( n1397 , n1306 );
xor ( n1398 , n1396 , n1397 );
and ( n1399 , n1398 , n1388 );
or ( n1400 , n1395 , n1399 );
not ( n1401 , n1400 );
not ( n1402 , n1401 );
or ( n1403 , n1308 , n1402 );
not ( n1404 , n1388 );
not ( n1405 , n946 );
and ( n1406 , n1405 , n1368 );
xor ( n1407 , n1369 , n1379 );
and ( n1408 , n1407 , n946 );
or ( n1409 , n1406 , n1408 );
and ( n1410 , n1404 , n1409 );
not ( n1411 , n1409 );
and ( n1412 , n1396 , n1397 );
xor ( n1413 , n1411 , n1412 );
and ( n1414 , n1413 , n1388 );
or ( n1415 , n1410 , n1414 );
not ( n1416 , n1415 );
not ( n1417 , n1416 );
or ( n1418 , n1403 , n1417 );
and ( n1419 , n1418 , n1388 );
not ( n1420 , n1419 );
and ( n1421 , n1420 , n1308 );
xor ( n1422 , n1308 , n1388 );
xor ( n1423 , n1422 , n1388 );
and ( n1424 , n1423 , n1419 );
or ( n1425 , n1421 , n1424 );
not ( n1426 , n1419 );
and ( n1427 , n1426 , n1402 );
xor ( n1428 , n1402 , n1388 );
and ( n1429 , n1422 , n1388 );
xor ( n1430 , n1428 , n1429 );
and ( n1431 , n1430 , n1419 );
or ( n1432 , n1427 , n1431 );
not ( n1433 , n1419 );
and ( n1434 , n1433 , n1417 );
xor ( n1435 , n1417 , n1388 );
and ( n1436 , n1428 , n1429 );
xor ( n1437 , n1435 , n1436 );
and ( n1438 , n1437 , n1419 );
or ( n1439 , n1434 , n1438 );
and ( n1440 , n1425 , n1432 , n1439 );
or ( n1441 , n1251 , n1440 );
not ( n1442 , n1441 );
buf ( n1443 , n722 );
buf ( n1444 , n1443 );
not ( n1445 , n1444 );
not ( n1446 , n1445 );
buf ( n1447 , n1446 );
not ( n1448 , n946 );
and ( n1449 , n1448 , n977 );
not ( n1450 , n977 );
not ( n1451 , n983 );
not ( n1452 , n989 );
not ( n1453 , n995 );
not ( n1454 , n1001 );
not ( n1455 , n1007 );
not ( n1456 , n1013 );
not ( n1457 , n1019 );
not ( n1458 , n1025 );
not ( n1459 , n1031 );
not ( n1460 , n1037 );
not ( n1461 , n1043 );
not ( n1462 , n1049 );
not ( n1463 , n1055 );
not ( n1464 , n1061 );
not ( n1465 , n1067 );
not ( n1466 , n1073 );
not ( n1467 , n1079 );
not ( n1468 , n1085 );
not ( n1469 , n911 );
and ( n1470 , n1468 , n1469 );
and ( n1471 , n1467 , n1470 );
and ( n1472 , n1466 , n1471 );
and ( n1473 , n1465 , n1472 );
and ( n1474 , n1464 , n1473 );
and ( n1475 , n1463 , n1474 );
and ( n1476 , n1462 , n1475 );
and ( n1477 , n1461 , n1476 );
and ( n1478 , n1460 , n1477 );
and ( n1479 , n1459 , n1478 );
and ( n1480 , n1458 , n1479 );
and ( n1481 , n1457 , n1480 );
and ( n1482 , n1456 , n1481 );
and ( n1483 , n1455 , n1482 );
and ( n1484 , n1454 , n1483 );
and ( n1485 , n1453 , n1484 );
and ( n1486 , n1452 , n1485 );
and ( n1487 , n1451 , n1486 );
xor ( n1488 , n1450 , n1487 );
and ( n1489 , n1488 , n946 );
or ( n1490 , n1449 , n1489 );
not ( n1491 , n1490 );
not ( n1492 , n1491 );
not ( n1493 , n1492 );
not ( n1494 , n1493 );
not ( n1495 , n946 );
not ( n1496 , n1124 );
not ( n1497 , n1130 );
not ( n1498 , n1136 );
not ( n1499 , n1142 );
not ( n1500 , n1148 );
not ( n1501 , n1154 );
not ( n1502 , n1160 );
not ( n1503 , n952 );
not ( n1504 , n959 );
not ( n1505 , n965 );
not ( n1506 , n971 );
and ( n1507 , n1450 , n1487 );
and ( n1508 , n1506 , n1507 );
and ( n1509 , n1505 , n1508 );
and ( n1510 , n1504 , n1509 );
and ( n1511 , n1503 , n1510 );
and ( n1512 , n1502 , n1511 );
and ( n1513 , n1501 , n1512 );
and ( n1514 , n1500 , n1513 );
and ( n1515 , n1499 , n1514 );
and ( n1516 , n1498 , n1515 );
and ( n1517 , n1497 , n1516 );
and ( n1518 , n1496 , n1517 );
xor ( n1519 , n1495 , n1518 );
buf ( n1520 , n946 );
and ( n1521 , n1519 , n1520 );
buf ( n1522 , n1521 );
not ( n1523 , n1522 );
not ( n1524 , n1523 );
not ( n1525 , n1524 );
not ( n1526 , n946 );
and ( n1527 , n1526 , n1124 );
xor ( n1528 , n1496 , n1517 );
and ( n1529 , n1528 , n946 );
or ( n1530 , n1527 , n1529 );
not ( n1531 , n1530 );
not ( n1532 , n1531 );
not ( n1533 , n1532 );
not ( n1534 , n946 );
and ( n1535 , n1534 , n1130 );
xor ( n1536 , n1497 , n1516 );
and ( n1537 , n1536 , n946 );
or ( n1538 , n1535 , n1537 );
not ( n1539 , n1538 );
not ( n1540 , n1539 );
not ( n1541 , n1540 );
not ( n1542 , n946 );
and ( n1543 , n1542 , n1136 );
xor ( n1544 , n1498 , n1515 );
and ( n1545 , n1544 , n946 );
or ( n1546 , n1543 , n1545 );
not ( n1547 , n1546 );
not ( n1548 , n1547 );
not ( n1549 , n1548 );
not ( n1550 , n946 );
and ( n1551 , n1550 , n1142 );
xor ( n1552 , n1499 , n1514 );
and ( n1553 , n1552 , n946 );
or ( n1554 , n1551 , n1553 );
not ( n1555 , n1554 );
not ( n1556 , n1555 );
not ( n1557 , n1556 );
not ( n1558 , n946 );
and ( n1559 , n1558 , n1148 );
xor ( n1560 , n1500 , n1513 );
and ( n1561 , n1560 , n946 );
or ( n1562 , n1559 , n1561 );
not ( n1563 , n1562 );
not ( n1564 , n1563 );
not ( n1565 , n1564 );
not ( n1566 , n946 );
and ( n1567 , n1566 , n1154 );
xor ( n1568 , n1501 , n1512 );
and ( n1569 , n1568 , n946 );
or ( n1570 , n1567 , n1569 );
not ( n1571 , n1570 );
not ( n1572 , n1571 );
not ( n1573 , n1572 );
not ( n1574 , n946 );
and ( n1575 , n1574 , n1160 );
xor ( n1576 , n1502 , n1511 );
and ( n1577 , n1576 , n946 );
or ( n1578 , n1575 , n1577 );
not ( n1579 , n1578 );
not ( n1580 , n1579 );
not ( n1581 , n1580 );
not ( n1582 , n946 );
and ( n1583 , n1582 , n952 );
xor ( n1584 , n1503 , n1510 );
and ( n1585 , n1584 , n946 );
or ( n1586 , n1583 , n1585 );
not ( n1587 , n1586 );
not ( n1588 , n1587 );
not ( n1589 , n1588 );
not ( n1590 , n946 );
and ( n1591 , n1590 , n959 );
xor ( n1592 , n1504 , n1509 );
and ( n1593 , n1592 , n946 );
or ( n1594 , n1591 , n1593 );
not ( n1595 , n1594 );
not ( n1596 , n1595 );
not ( n1597 , n1596 );
not ( n1598 , n946 );
and ( n1599 , n1598 , n965 );
xor ( n1600 , n1505 , n1508 );
and ( n1601 , n1600 , n946 );
or ( n1602 , n1599 , n1601 );
not ( n1603 , n1602 );
not ( n1604 , n1603 );
not ( n1605 , n1604 );
not ( n1606 , n946 );
and ( n1607 , n1606 , n971 );
xor ( n1608 , n1506 , n1507 );
and ( n1609 , n1608 , n946 );
or ( n1610 , n1607 , n1609 );
not ( n1611 , n1610 );
not ( n1612 , n1611 );
not ( n1613 , n1612 );
not ( n1614 , n1492 );
and ( n1615 , n1613 , n1614 );
and ( n1616 , n1605 , n1615 );
and ( n1617 , n1597 , n1616 );
and ( n1618 , n1589 , n1617 );
and ( n1619 , n1581 , n1618 );
and ( n1620 , n1573 , n1619 );
and ( n1621 , n1565 , n1620 );
and ( n1622 , n1557 , n1621 );
and ( n1623 , n1549 , n1622 );
and ( n1624 , n1541 , n1623 );
and ( n1625 , n1533 , n1624 );
and ( n1626 , n1525 , n1625 );
not ( n1627 , n1626 );
and ( n1628 , n1627 , n946 );
buf ( n1629 , n1628 );
not ( n1630 , n1629 );
not ( n1631 , n946 );
and ( n1632 , n1631 , n1612 );
xor ( n1633 , n1613 , n1614 );
and ( n1634 , n1633 , n946 );
or ( n1635 , n1632 , n1634 );
and ( n1636 , n1630 , n1635 );
not ( n1637 , n1635 );
not ( n1638 , n1492 );
xor ( n1639 , n1637 , n1638 );
and ( n1640 , n1639 , n1629 );
or ( n1641 , n1636 , n1640 );
not ( n1642 , n1641 );
not ( n1643 , n1642 );
or ( n1644 , n1494 , n1643 );
not ( n1645 , n1629 );
not ( n1646 , n946 );
and ( n1647 , n1646 , n1604 );
xor ( n1648 , n1605 , n1615 );
and ( n1649 , n1648 , n946 );
or ( n1650 , n1647 , n1649 );
and ( n1651 , n1645 , n1650 );
not ( n1652 , n1650 );
and ( n1653 , n1637 , n1638 );
xor ( n1654 , n1652 , n1653 );
and ( n1655 , n1654 , n1629 );
or ( n1656 , n1651 , n1655 );
not ( n1657 , n1656 );
not ( n1658 , n1657 );
or ( n1659 , n1644 , n1658 );
not ( n1660 , n1629 );
not ( n1661 , n946 );
and ( n1662 , n1661 , n1596 );
xor ( n1663 , n1597 , n1616 );
and ( n1664 , n1663 , n946 );
or ( n1665 , n1662 , n1664 );
and ( n1666 , n1660 , n1665 );
not ( n1667 , n1665 );
and ( n1668 , n1652 , n1653 );
xor ( n1669 , n1667 , n1668 );
and ( n1670 , n1669 , n1629 );
or ( n1671 , n1666 , n1670 );
not ( n1672 , n1671 );
not ( n1673 , n1672 );
or ( n1674 , n1659 , n1673 );
buf ( n1675 , n1674 );
buf ( n1676 , n1675 );
and ( n1677 , n1676 , n1629 );
not ( n1678 , n1677 );
and ( n1679 , n1678 , n1494 );
xor ( n1680 , n1494 , n1629 );
xor ( n1681 , n1680 , n1629 );
and ( n1682 , n1681 , n1677 );
or ( n1683 , n1679 , n1682 );
not ( n1684 , n1677 );
and ( n1685 , n1684 , n1643 );
xor ( n1686 , n1643 , n1629 );
and ( n1687 , n1680 , n1629 );
xor ( n1688 , n1686 , n1687 );
and ( n1689 , n1688 , n1677 );
or ( n1690 , n1685 , n1689 );
not ( n1691 , n1690 );
not ( n1692 , n1677 );
and ( n1693 , n1692 , n1658 );
xor ( n1694 , n1658 , n1629 );
and ( n1695 , n1686 , n1687 );
xor ( n1696 , n1694 , n1695 );
and ( n1697 , n1696 , n1677 );
or ( n1698 , n1693 , n1697 );
not ( n1699 , n1677 );
and ( n1700 , n1699 , n1673 );
xor ( n1701 , n1673 , n1629 );
and ( n1702 , n1694 , n1695 );
xor ( n1703 , n1701 , n1702 );
and ( n1704 , n1703 , n1677 );
or ( n1705 , n1700 , n1704 );
and ( n1706 , n1683 , n1691 , n1698 , n1705 );
not ( n1707 , n1683 );
and ( n1708 , n1707 , n1690 , n1698 , n1705 );
or ( n1709 , n1706 , n1708 );
and ( n1710 , n1683 , n1690 , n1698 , n1705 );
or ( n1711 , n1709 , n1710 );
and ( n1712 , n1447 , n1711 );
buf ( n1713 , n721 );
not ( n1714 , n1713 );
not ( n1715 , n1714 );
buf ( n1716 , n1715 );
not ( n1717 , n946 );
and ( n1718 , n1717 , n1130 );
not ( n1719 , n1130 );
not ( n1720 , n1136 );
not ( n1721 , n1142 );
not ( n1722 , n1148 );
not ( n1723 , n1154 );
not ( n1724 , n1160 );
not ( n1725 , n952 );
not ( n1726 , n959 );
not ( n1727 , n965 );
not ( n1728 , n971 );
not ( n1729 , n977 );
not ( n1730 , n983 );
not ( n1731 , n989 );
not ( n1732 , n995 );
not ( n1733 , n1001 );
not ( n1734 , n1007 );
not ( n1735 , n1013 );
not ( n1736 , n1019 );
not ( n1737 , n1025 );
not ( n1738 , n1031 );
not ( n1739 , n1037 );
not ( n1740 , n1043 );
not ( n1741 , n1049 );
not ( n1742 , n1055 );
not ( n1743 , n1061 );
not ( n1744 , n1067 );
not ( n1745 , n1073 );
not ( n1746 , n1079 );
not ( n1747 , n1085 );
not ( n1748 , n911 );
and ( n1749 , n1747 , n1748 );
and ( n1750 , n1746 , n1749 );
and ( n1751 , n1745 , n1750 );
and ( n1752 , n1744 , n1751 );
and ( n1753 , n1743 , n1752 );
and ( n1754 , n1742 , n1753 );
and ( n1755 , n1741 , n1754 );
and ( n1756 , n1740 , n1755 );
and ( n1757 , n1739 , n1756 );
and ( n1758 , n1738 , n1757 );
and ( n1759 , n1737 , n1758 );
and ( n1760 , n1736 , n1759 );
and ( n1761 , n1735 , n1760 );
and ( n1762 , n1734 , n1761 );
and ( n1763 , n1733 , n1762 );
and ( n1764 , n1732 , n1763 );
and ( n1765 , n1731 , n1764 );
and ( n1766 , n1730 , n1765 );
and ( n1767 , n1729 , n1766 );
and ( n1768 , n1728 , n1767 );
and ( n1769 , n1727 , n1768 );
and ( n1770 , n1726 , n1769 );
and ( n1771 , n1725 , n1770 );
and ( n1772 , n1724 , n1771 );
and ( n1773 , n1723 , n1772 );
and ( n1774 , n1722 , n1773 );
and ( n1775 , n1721 , n1774 );
and ( n1776 , n1720 , n1775 );
xor ( n1777 , n1719 , n1776 );
and ( n1778 , n1777 , n946 );
or ( n1779 , n1718 , n1778 );
not ( n1780 , n1779 );
not ( n1781 , n1780 );
not ( n1782 , n1781 );
not ( n1783 , n1782 );
not ( n1784 , n946 );
not ( n1785 , n1124 );
and ( n1786 , n1719 , n1776 );
and ( n1787 , n1785 , n1786 );
xor ( n1788 , n1784 , n1787 );
buf ( n1789 , n946 );
and ( n1790 , n1788 , n1789 );
buf ( n1791 , n1790 );
not ( n1792 , n1791 );
not ( n1793 , n1792 );
not ( n1794 , n1793 );
not ( n1795 , n946 );
and ( n1796 , n1795 , n1124 );
xor ( n1797 , n1785 , n1786 );
and ( n1798 , n1797 , n946 );
or ( n1799 , n1796 , n1798 );
not ( n1800 , n1799 );
not ( n1801 , n1800 );
not ( n1802 , n1801 );
not ( n1803 , n1781 );
and ( n1804 , n1802 , n1803 );
and ( n1805 , n1794 , n1804 );
not ( n1806 , n1805 );
and ( n1807 , n1806 , n946 );
buf ( n1808 , n1807 );
not ( n1809 , n1808 );
not ( n1810 , n946 );
and ( n1811 , n1810 , n1801 );
xor ( n1812 , n1802 , n1803 );
and ( n1813 , n1812 , n946 );
or ( n1814 , n1811 , n1813 );
and ( n1815 , n1809 , n1814 );
not ( n1816 , n1814 );
not ( n1817 , n1781 );
xor ( n1818 , n1816 , n1817 );
and ( n1819 , n1818 , n1808 );
or ( n1820 , n1815 , n1819 );
not ( n1821 , n1820 );
not ( n1822 , n1821 );
or ( n1823 , n1783 , n1822 );
and ( n1824 , n1823 , n1808 );
not ( n1825 , n1824 );
and ( n1826 , n1825 , n1783 );
xor ( n1827 , n1783 , n1808 );
xor ( n1828 , n1827 , n1808 );
and ( n1829 , n1828 , n1824 );
or ( n1830 , n1826 , n1829 );
not ( n1831 , n1824 );
and ( n1832 , n1831 , n1822 );
xor ( n1833 , n1822 , n1808 );
and ( n1834 , n1827 , n1808 );
xor ( n1835 , n1833 , n1834 );
and ( n1836 , n1835 , n1824 );
or ( n1837 , n1832 , n1836 );
and ( n1838 , n1830 , n1837 );
and ( n1839 , n1716 , n1838 );
buf ( n1840 , n815 );
not ( n1841 , n1830 );
and ( n1842 , n1841 , n1837 );
and ( n1843 , n1840 , n1842 );
buf ( n1844 , n750 );
nor ( n1845 , n1841 , n1837 );
and ( n1846 , n1844 , n1845 );
buf ( n1847 , n782 );
nor ( n1848 , n1830 , n1837 );
and ( n1849 , n1847 , n1848 );
or ( n1850 , n1839 , n1843 , n1846 , n1849 );
not ( n1851 , n1850 );
not ( n1852 , n1851 );
buf ( n1853 , n846 );
and ( n1854 , n1853 , n1842 );
buf ( n1855 , n781 );
and ( n1856 , n1855 , n1845 );
buf ( n1857 , n813 );
and ( n1858 , n1857 , n1848 );
or ( n1859 , 1'b0 , n1854 , n1856 , n1858 );
not ( n1860 , n1859 );
and ( n1861 , n1447 , n1838 );
buf ( n1862 , n816 );
and ( n1863 , n1862 , n1842 );
buf ( n1864 , n751 );
and ( n1865 , n1864 , n1845 );
buf ( n1866 , n783 );
and ( n1867 , n1866 , n1848 );
or ( n1868 , n1861 , n1863 , n1865 , n1867 );
and ( n1869 , n1860 , n1868 );
not ( n1870 , n1868 );
not ( n1871 , n1850 );
xor ( n1872 , n1870 , n1871 );
and ( n1873 , n1872 , n1859 );
or ( n1874 , n1869 , n1873 );
not ( n1875 , n1874 );
not ( n1876 , n1875 );
or ( n1877 , n1852 , n1876 );
not ( n1878 , n1859 );
buf ( n1879 , n723 );
buf ( n1880 , n1879 );
not ( n1881 , n1880 );
not ( n1882 , n1881 );
buf ( n1883 , n1882 );
and ( n1884 , n1883 , n1838 );
buf ( n1885 , n817 );
and ( n1886 , n1885 , n1842 );
buf ( n1887 , n752 );
and ( n1888 , n1887 , n1845 );
buf ( n1889 , n784 );
and ( n1890 , n1889 , n1848 );
or ( n1891 , n1884 , n1886 , n1888 , n1890 );
and ( n1892 , n1878 , n1891 );
not ( n1893 , n1891 );
and ( n1894 , n1870 , n1871 );
xor ( n1895 , n1893 , n1894 );
and ( n1896 , n1895 , n1859 );
or ( n1897 , n1892 , n1896 );
not ( n1898 , n1897 );
not ( n1899 , n1898 );
or ( n1900 , n1877 , n1899 );
not ( n1901 , n1859 );
buf ( n1902 , n724 );
buf ( n1903 , n1902 );
not ( n1904 , n1903 );
not ( n1905 , n1904 );
buf ( n1906 , n1905 );
not ( n1907 , n1906 );
and ( n1908 , n1907 , n1838 );
buf ( n1909 , n818 );
and ( n1910 , n1909 , n1842 );
buf ( n1911 , n753 );
and ( n1912 , n1911 , n1845 );
buf ( n1913 , n785 );
and ( n1914 , n1913 , n1848 );
or ( n1915 , n1908 , n1910 , n1912 , n1914 );
and ( n1916 , n1901 , n1915 );
not ( n1917 , n1915 );
and ( n1918 , n1893 , n1894 );
xor ( n1919 , n1917 , n1918 );
and ( n1920 , n1919 , n1859 );
or ( n1921 , n1916 , n1920 );
not ( n1922 , n1921 );
not ( n1923 , n1922 );
or ( n1924 , n1900 , n1923 );
not ( n1925 , n1859 );
buf ( n1926 , n725 );
buf ( n1927 , n1926 );
not ( n1928 , n1927 );
not ( n1929 , n1928 );
buf ( n1930 , n1929 );
xor ( n1931 , n1930 , n1906 );
and ( n1932 , n1931 , n1838 );
buf ( n1933 , n819 );
and ( n1934 , n1933 , n1842 );
buf ( n1935 , n754 );
and ( n1936 , n1935 , n1845 );
buf ( n1937 , n786 );
and ( n1938 , n1937 , n1848 );
or ( n1939 , n1932 , n1934 , n1936 , n1938 );
and ( n1940 , n1925 , n1939 );
not ( n1941 , n1939 );
and ( n1942 , n1917 , n1918 );
xor ( n1943 , n1941 , n1942 );
and ( n1944 , n1943 , n1859 );
or ( n1945 , n1940 , n1944 );
not ( n1946 , n1945 );
not ( n1947 , n1946 );
or ( n1948 , n1924 , n1947 );
not ( n1949 , n1859 );
buf ( n1950 , n726 );
not ( n1951 , n1950 );
not ( n1952 , n1951 );
buf ( n1953 , n1952 );
and ( n1954 , n1930 , n1906 );
xor ( n1955 , n1953 , n1954 );
and ( n1956 , n1955 , n1838 );
buf ( n1957 , n820 );
and ( n1958 , n1957 , n1842 );
buf ( n1959 , n755 );
and ( n1960 , n1959 , n1845 );
buf ( n1961 , n787 );
and ( n1962 , n1961 , n1848 );
or ( n1963 , n1956 , n1958 , n1960 , n1962 );
and ( n1964 , n1949 , n1963 );
not ( n1965 , n1963 );
and ( n1966 , n1941 , n1942 );
xor ( n1967 , n1965 , n1966 );
and ( n1968 , n1967 , n1859 );
or ( n1969 , n1964 , n1968 );
not ( n1970 , n1969 );
not ( n1971 , n1970 );
or ( n1972 , n1948 , n1971 );
not ( n1973 , n1859 );
buf ( n1974 , n727 );
not ( n1975 , n1974 );
not ( n1976 , n1975 );
buf ( n1977 , n1976 );
and ( n1978 , n1953 , n1954 );
xor ( n1979 , n1977 , n1978 );
and ( n1980 , n1979 , n1838 );
buf ( n1981 , n821 );
and ( n1982 , n1981 , n1842 );
buf ( n1983 , n756 );
and ( n1984 , n1983 , n1845 );
buf ( n1985 , n788 );
and ( n1986 , n1985 , n1848 );
or ( n1987 , n1980 , n1982 , n1984 , n1986 );
and ( n1988 , n1973 , n1987 );
not ( n1989 , n1987 );
and ( n1990 , n1965 , n1966 );
xor ( n1991 , n1989 , n1990 );
and ( n1992 , n1991 , n1859 );
or ( n1993 , n1988 , n1992 );
not ( n1994 , n1993 );
not ( n1995 , n1994 );
or ( n1996 , n1972 , n1995 );
not ( n1997 , n1859 );
buf ( n1998 , n728 );
not ( n1999 , n1998 );
not ( n2000 , n1999 );
buf ( n2001 , n2000 );
and ( n2002 , n1977 , n1978 );
xor ( n2003 , n2001 , n2002 );
and ( n2004 , n2003 , n1838 );
buf ( n2005 , n822 );
and ( n2006 , n2005 , n1842 );
buf ( n2007 , n757 );
and ( n2008 , n2007 , n1845 );
buf ( n2009 , n789 );
and ( n2010 , n2009 , n1848 );
or ( n2011 , n2004 , n2006 , n2008 , n2010 );
and ( n2012 , n1997 , n2011 );
not ( n2013 , n2011 );
and ( n2014 , n1989 , n1990 );
xor ( n2015 , n2013 , n2014 );
and ( n2016 , n2015 , n1859 );
or ( n2017 , n2012 , n2016 );
not ( n2018 , n2017 );
not ( n2019 , n2018 );
or ( n2020 , n1996 , n2019 );
not ( n2021 , n1859 );
buf ( n2022 , n729 );
not ( n2023 , n2022 );
not ( n2024 , n2023 );
buf ( n2025 , n2024 );
and ( n2026 , n2001 , n2002 );
xor ( n2027 , n2025 , n2026 );
and ( n2028 , n2027 , n1838 );
buf ( n2029 , n823 );
and ( n2030 , n2029 , n1842 );
buf ( n2031 , n758 );
and ( n2032 , n2031 , n1845 );
buf ( n2033 , n790 );
and ( n2034 , n2033 , n1848 );
or ( n2035 , n2028 , n2030 , n2032 , n2034 );
and ( n2036 , n2021 , n2035 );
not ( n2037 , n2035 );
and ( n2038 , n2013 , n2014 );
xor ( n2039 , n2037 , n2038 );
and ( n2040 , n2039 , n1859 );
or ( n2041 , n2036 , n2040 );
not ( n2042 , n2041 );
not ( n2043 , n2042 );
or ( n2044 , n2020 , n2043 );
not ( n2045 , n1859 );
buf ( n2046 , n730 );
not ( n2047 , n2046 );
not ( n2048 , n2047 );
buf ( n2049 , n2048 );
and ( n2050 , n2025 , n2026 );
xor ( n2051 , n2049 , n2050 );
and ( n2052 , n2051 , n1838 );
buf ( n2053 , n824 );
and ( n2054 , n2053 , n1842 );
buf ( n2055 , n759 );
and ( n2056 , n2055 , n1845 );
buf ( n2057 , n791 );
and ( n2058 , n2057 , n1848 );
or ( n2059 , n2052 , n2054 , n2056 , n2058 );
and ( n2060 , n2045 , n2059 );
not ( n2061 , n2059 );
and ( n2062 , n2037 , n2038 );
xor ( n2063 , n2061 , n2062 );
and ( n2064 , n2063 , n1859 );
or ( n2065 , n2060 , n2064 );
not ( n2066 , n2065 );
not ( n2067 , n2066 );
or ( n2068 , n2044 , n2067 );
not ( n2069 , n1859 );
buf ( n2070 , n731 );
not ( n2071 , n2070 );
not ( n2072 , n2071 );
buf ( n2073 , n2072 );
and ( n2074 , n2049 , n2050 );
xor ( n2075 , n2073 , n2074 );
and ( n2076 , n2075 , n1838 );
buf ( n2077 , n825 );
and ( n2078 , n2077 , n1842 );
buf ( n2079 , n760 );
and ( n2080 , n2079 , n1845 );
buf ( n2081 , n792 );
and ( n2082 , n2081 , n1848 );
or ( n2083 , n2076 , n2078 , n2080 , n2082 );
and ( n2084 , n2069 , n2083 );
not ( n2085 , n2083 );
and ( n2086 , n2061 , n2062 );
xor ( n2087 , n2085 , n2086 );
and ( n2088 , n2087 , n1859 );
or ( n2089 , n2084 , n2088 );
not ( n2090 , n2089 );
not ( n2091 , n2090 );
or ( n2092 , n2068 , n2091 );
not ( n2093 , n1859 );
buf ( n2094 , n732 );
not ( n2095 , n2094 );
not ( n2096 , n2095 );
buf ( n2097 , n2096 );
and ( n2098 , n2073 , n2074 );
xor ( n2099 , n2097 , n2098 );
and ( n2100 , n2099 , n1838 );
buf ( n2101 , n826 );
and ( n2102 , n2101 , n1842 );
buf ( n2103 , n761 );
and ( n2104 , n2103 , n1845 );
buf ( n2105 , n793 );
and ( n2106 , n2105 , n1848 );
or ( n2107 , n2100 , n2102 , n2104 , n2106 );
and ( n2108 , n2093 , n2107 );
not ( n2109 , n2107 );
and ( n2110 , n2085 , n2086 );
xor ( n2111 , n2109 , n2110 );
and ( n2112 , n2111 , n1859 );
or ( n2113 , n2108 , n2112 );
not ( n2114 , n2113 );
not ( n2115 , n2114 );
or ( n2116 , n2092 , n2115 );
not ( n2117 , n1859 );
buf ( n2118 , n733 );
not ( n2119 , n2118 );
not ( n2120 , n2119 );
buf ( n2121 , n2120 );
and ( n2122 , n2097 , n2098 );
xor ( n2123 , n2121 , n2122 );
and ( n2124 , n2123 , n1838 );
buf ( n2125 , n827 );
and ( n2126 , n2125 , n1842 );
buf ( n2127 , n762 );
and ( n2128 , n2127 , n1845 );
buf ( n2129 , n794 );
and ( n2130 , n2129 , n1848 );
or ( n2131 , n2124 , n2126 , n2128 , n2130 );
and ( n2132 , n2117 , n2131 );
not ( n2133 , n2131 );
and ( n2134 , n2109 , n2110 );
xor ( n2135 , n2133 , n2134 );
and ( n2136 , n2135 , n1859 );
or ( n2137 , n2132 , n2136 );
not ( n2138 , n2137 );
not ( n2139 , n2138 );
or ( n2140 , n2116 , n2139 );
not ( n2141 , n1859 );
buf ( n2142 , n734 );
not ( n2143 , n2142 );
not ( n2144 , n2143 );
buf ( n2145 , n2144 );
and ( n2146 , n2121 , n2122 );
xor ( n2147 , n2145 , n2146 );
and ( n2148 , n2147 , n1838 );
buf ( n2149 , n828 );
and ( n2150 , n2149 , n1842 );
buf ( n2151 , n763 );
and ( n2152 , n2151 , n1845 );
buf ( n2153 , n795 );
and ( n2154 , n2153 , n1848 );
or ( n2155 , n2148 , n2150 , n2152 , n2154 );
and ( n2156 , n2141 , n2155 );
not ( n2157 , n2155 );
and ( n2158 , n2133 , n2134 );
xor ( n2159 , n2157 , n2158 );
and ( n2160 , n2159 , n1859 );
or ( n2161 , n2156 , n2160 );
not ( n2162 , n2161 );
not ( n2163 , n2162 );
or ( n2164 , n2140 , n2163 );
not ( n2165 , n1859 );
buf ( n2166 , n735 );
not ( n2167 , n2166 );
not ( n2168 , n2167 );
buf ( n2169 , n2168 );
and ( n2170 , n2145 , n2146 );
xor ( n2171 , n2169 , n2170 );
and ( n2172 , n2171 , n1838 );
buf ( n2173 , n829 );
and ( n2174 , n2173 , n1842 );
buf ( n2175 , n764 );
and ( n2176 , n2175 , n1845 );
buf ( n2177 , n796 );
and ( n2178 , n2177 , n1848 );
or ( n2179 , n2172 , n2174 , n2176 , n2178 );
and ( n2180 , n2165 , n2179 );
not ( n2181 , n2179 );
and ( n2182 , n2157 , n2158 );
xor ( n2183 , n2181 , n2182 );
and ( n2184 , n2183 , n1859 );
or ( n2185 , n2180 , n2184 );
not ( n2186 , n2185 );
not ( n2187 , n2186 );
or ( n2188 , n2164 , n2187 );
not ( n2189 , n1859 );
buf ( n2190 , n736 );
not ( n2191 , n2190 );
not ( n2192 , n2191 );
buf ( n2193 , n2192 );
and ( n2194 , n2169 , n2170 );
xor ( n2195 , n2193 , n2194 );
and ( n2196 , n2195 , n1838 );
buf ( n2197 , n830 );
and ( n2198 , n2197 , n1842 );
buf ( n2199 , n765 );
and ( n2200 , n2199 , n1845 );
buf ( n2201 , n797 );
and ( n2202 , n2201 , n1848 );
or ( n2203 , n2196 , n2198 , n2200 , n2202 );
and ( n2204 , n2189 , n2203 );
not ( n2205 , n2203 );
and ( n2206 , n2181 , n2182 );
xor ( n2207 , n2205 , n2206 );
and ( n2208 , n2207 , n1859 );
or ( n2209 , n2204 , n2208 );
not ( n2210 , n2209 );
not ( n2211 , n2210 );
or ( n2212 , n2188 , n2211 );
not ( n2213 , n1859 );
buf ( n2214 , n737 );
not ( n2215 , n2214 );
not ( n2216 , n2215 );
buf ( n2217 , n2216 );
and ( n2218 , n2193 , n2194 );
xor ( n2219 , n2217 , n2218 );
and ( n2220 , n2219 , n1838 );
buf ( n2221 , n831 );
and ( n2222 , n2221 , n1842 );
buf ( n2223 , n766 );
and ( n2224 , n2223 , n1845 );
buf ( n2225 , n798 );
and ( n2226 , n2225 , n1848 );
or ( n2227 , n2220 , n2222 , n2224 , n2226 );
and ( n2228 , n2213 , n2227 );
not ( n2229 , n2227 );
and ( n2230 , n2205 , n2206 );
xor ( n2231 , n2229 , n2230 );
and ( n2232 , n2231 , n1859 );
or ( n2233 , n2228 , n2232 );
not ( n2234 , n2233 );
not ( n2235 , n2234 );
or ( n2236 , n2212 , n2235 );
not ( n2237 , n1859 );
buf ( n2238 , n738 );
not ( n2239 , n2238 );
not ( n2240 , n2239 );
buf ( n2241 , n2240 );
and ( n2242 , n2217 , n2218 );
xor ( n2243 , n2241 , n2242 );
and ( n2244 , n2243 , n1838 );
buf ( n2245 , n832 );
and ( n2246 , n2245 , n1842 );
buf ( n2247 , n767 );
and ( n2248 , n2247 , n1845 );
buf ( n2249 , n799 );
and ( n2250 , n2249 , n1848 );
or ( n2251 , n2244 , n2246 , n2248 , n2250 );
and ( n2252 , n2237 , n2251 );
not ( n2253 , n2251 );
and ( n2254 , n2229 , n2230 );
xor ( n2255 , n2253 , n2254 );
and ( n2256 , n2255 , n1859 );
or ( n2257 , n2252 , n2256 );
not ( n2258 , n2257 );
not ( n2259 , n2258 );
or ( n2260 , n2236 , n2259 );
not ( n2261 , n1859 );
buf ( n2262 , n739 );
not ( n2263 , n2262 );
not ( n2264 , n2263 );
buf ( n2265 , n2264 );
and ( n2266 , n2241 , n2242 );
xor ( n2267 , n2265 , n2266 );
and ( n2268 , n2267 , n1838 );
buf ( n2269 , n833 );
and ( n2270 , n2269 , n1842 );
buf ( n2271 , n768 );
and ( n2272 , n2271 , n1845 );
buf ( n2273 , n800 );
and ( n2274 , n2273 , n1848 );
or ( n2275 , n2268 , n2270 , n2272 , n2274 );
and ( n2276 , n2261 , n2275 );
not ( n2277 , n2275 );
and ( n2278 , n2253 , n2254 );
xor ( n2279 , n2277 , n2278 );
and ( n2280 , n2279 , n1859 );
or ( n2281 , n2276 , n2280 );
not ( n2282 , n2281 );
not ( n2283 , n2282 );
or ( n2284 , n2260 , n2283 );
not ( n2285 , n1859 );
buf ( n2286 , n740 );
not ( n2287 , n2286 );
not ( n2288 , n2287 );
buf ( n2289 , n2288 );
and ( n2290 , n2265 , n2266 );
xor ( n2291 , n2289 , n2290 );
and ( n2292 , n2291 , n1838 );
buf ( n2293 , n834 );
and ( n2294 , n2293 , n1842 );
buf ( n2295 , n769 );
and ( n2296 , n2295 , n1845 );
buf ( n2297 , n801 );
and ( n2298 , n2297 , n1848 );
or ( n2299 , n2292 , n2294 , n2296 , n2298 );
and ( n2300 , n2285 , n2299 );
not ( n2301 , n2299 );
and ( n2302 , n2277 , n2278 );
xor ( n2303 , n2301 , n2302 );
and ( n2304 , n2303 , n1859 );
or ( n2305 , n2300 , n2304 );
not ( n2306 , n2305 );
not ( n2307 , n2306 );
or ( n2308 , n2284 , n2307 );
not ( n2309 , n1859 );
buf ( n2310 , n741 );
not ( n2311 , n2310 );
not ( n2312 , n2311 );
buf ( n2313 , n2312 );
and ( n2314 , n2289 , n2290 );
xor ( n2315 , n2313 , n2314 );
and ( n2316 , n2315 , n1838 );
buf ( n2317 , n835 );
and ( n2318 , n2317 , n1842 );
buf ( n2319 , n770 );
and ( n2320 , n2319 , n1845 );
buf ( n2321 , n802 );
and ( n2322 , n2321 , n1848 );
or ( n2323 , n2316 , n2318 , n2320 , n2322 );
and ( n2324 , n2309 , n2323 );
not ( n2325 , n2323 );
and ( n2326 , n2301 , n2302 );
xor ( n2327 , n2325 , n2326 );
and ( n2328 , n2327 , n1859 );
or ( n2329 , n2324 , n2328 );
not ( n2330 , n2329 );
not ( n2331 , n2330 );
or ( n2332 , n2308 , n2331 );
not ( n2333 , n1859 );
buf ( n2334 , n742 );
not ( n2335 , n2334 );
not ( n2336 , n2335 );
buf ( n2337 , n2336 );
and ( n2338 , n2313 , n2314 );
xor ( n2339 , n2337 , n2338 );
and ( n2340 , n2339 , n1838 );
buf ( n2341 , n836 );
and ( n2342 , n2341 , n1842 );
buf ( n2343 , n771 );
and ( n2344 , n2343 , n1845 );
buf ( n2345 , n803 );
and ( n2346 , n2345 , n1848 );
or ( n2347 , n2340 , n2342 , n2344 , n2346 );
and ( n2348 , n2333 , n2347 );
not ( n2349 , n2347 );
and ( n2350 , n2325 , n2326 );
xor ( n2351 , n2349 , n2350 );
and ( n2352 , n2351 , n1859 );
or ( n2353 , n2348 , n2352 );
not ( n2354 , n2353 );
not ( n2355 , n2354 );
or ( n2356 , n2332 , n2355 );
not ( n2357 , n1859 );
buf ( n2358 , n743 );
not ( n2359 , n2358 );
not ( n2360 , n2359 );
buf ( n2361 , n2360 );
and ( n2362 , n2337 , n2338 );
xor ( n2363 , n2361 , n2362 );
and ( n2364 , n2363 , n1838 );
buf ( n2365 , n837 );
and ( n2366 , n2365 , n1842 );
buf ( n2367 , n772 );
and ( n2368 , n2367 , n1845 );
buf ( n2369 , n804 );
and ( n2370 , n2369 , n1848 );
or ( n2371 , n2364 , n2366 , n2368 , n2370 );
and ( n2372 , n2357 , n2371 );
not ( n2373 , n2371 );
and ( n2374 , n2349 , n2350 );
xor ( n2375 , n2373 , n2374 );
and ( n2376 , n2375 , n1859 );
or ( n2377 , n2372 , n2376 );
not ( n2378 , n2377 );
not ( n2379 , n2378 );
or ( n2380 , n2356 , n2379 );
not ( n2381 , n1859 );
buf ( n2382 , n744 );
not ( n2383 , n2382 );
not ( n2384 , n2383 );
buf ( n2385 , n2384 );
and ( n2386 , n2361 , n2362 );
xor ( n2387 , n2385 , n2386 );
and ( n2388 , n2387 , n1838 );
buf ( n2389 , n838 );
and ( n2390 , n2389 , n1842 );
buf ( n2391 , n773 );
and ( n2392 , n2391 , n1845 );
buf ( n2393 , n805 );
and ( n2394 , n2393 , n1848 );
or ( n2395 , n2388 , n2390 , n2392 , n2394 );
and ( n2396 , n2381 , n2395 );
not ( n2397 , n2395 );
and ( n2398 , n2373 , n2374 );
xor ( n2399 , n2397 , n2398 );
and ( n2400 , n2399 , n1859 );
or ( n2401 , n2396 , n2400 );
not ( n2402 , n2401 );
not ( n2403 , n2402 );
or ( n2404 , n2380 , n2403 );
not ( n2405 , n1859 );
buf ( n2406 , n745 );
not ( n2407 , n2406 );
not ( n2408 , n2407 );
buf ( n2409 , n2408 );
and ( n2410 , n2385 , n2386 );
xor ( n2411 , n2409 , n2410 );
and ( n2412 , n2411 , n1838 );
buf ( n2413 , n839 );
and ( n2414 , n2413 , n1842 );
buf ( n2415 , n774 );
and ( n2416 , n2415 , n1845 );
buf ( n2417 , n806 );
and ( n2418 , n2417 , n1848 );
or ( n2419 , n2412 , n2414 , n2416 , n2418 );
and ( n2420 , n2405 , n2419 );
not ( n2421 , n2419 );
and ( n2422 , n2397 , n2398 );
xor ( n2423 , n2421 , n2422 );
and ( n2424 , n2423 , n1859 );
or ( n2425 , n2420 , n2424 );
not ( n2426 , n2425 );
not ( n2427 , n2426 );
or ( n2428 , n2404 , n2427 );
not ( n2429 , n1859 );
buf ( n2430 , n746 );
not ( n2431 , n2430 );
not ( n2432 , n2431 );
buf ( n2433 , n2432 );
and ( n2434 , n2409 , n2410 );
xor ( n2435 , n2433 , n2434 );
and ( n2436 , n2435 , n1838 );
buf ( n2437 , n840 );
and ( n2438 , n2437 , n1842 );
buf ( n2439 , n775 );
and ( n2440 , n2439 , n1845 );
buf ( n2441 , n807 );
and ( n2442 , n2441 , n1848 );
or ( n2443 , n2436 , n2438 , n2440 , n2442 );
and ( n2444 , n2429 , n2443 );
not ( n2445 , n2443 );
and ( n2446 , n2421 , n2422 );
xor ( n2447 , n2445 , n2446 );
and ( n2448 , n2447 , n1859 );
or ( n2449 , n2444 , n2448 );
not ( n2450 , n2449 );
not ( n2451 , n2450 );
or ( n2452 , n2428 , n2451 );
not ( n2453 , n1859 );
buf ( n2454 , n747 );
not ( n2455 , n2454 );
not ( n2456 , n2455 );
buf ( n2457 , n2456 );
and ( n2458 , n2433 , n2434 );
xor ( n2459 , n2457 , n2458 );
and ( n2460 , n2459 , n1838 );
buf ( n2461 , n841 );
and ( n2462 , n2461 , n1842 );
buf ( n2463 , n776 );
and ( n2464 , n2463 , n1845 );
buf ( n2465 , n808 );
and ( n2466 , n2465 , n1848 );
or ( n2467 , n2460 , n2462 , n2464 , n2466 );
and ( n2468 , n2453 , n2467 );
not ( n2469 , n2467 );
and ( n2470 , n2445 , n2446 );
xor ( n2471 , n2469 , n2470 );
and ( n2472 , n2471 , n1859 );
or ( n2473 , n2468 , n2472 );
not ( n2474 , n2473 );
not ( n2475 , n2474 );
or ( n2476 , n2452 , n2475 );
not ( n2477 , n1859 );
buf ( n2478 , n748 );
not ( n2479 , n2478 );
not ( n2480 , n2479 );
buf ( n2481 , n2480 );
and ( n2482 , n2457 , n2458 );
xor ( n2483 , n2481 , n2482 );
and ( n2484 , n2483 , n1838 );
buf ( n2485 , n842 );
and ( n2486 , n2485 , n1842 );
buf ( n2487 , n777 );
and ( n2488 , n2487 , n1845 );
buf ( n2489 , n809 );
and ( n2490 , n2489 , n1848 );
or ( n2491 , n2484 , n2486 , n2488 , n2490 );
and ( n2492 , n2477 , n2491 );
not ( n2493 , n2491 );
and ( n2494 , n2469 , n2470 );
xor ( n2495 , n2493 , n2494 );
and ( n2496 , n2495 , n1859 );
or ( n2497 , n2492 , n2496 );
not ( n2498 , n2497 );
not ( n2499 , n2498 );
or ( n2500 , n2476 , n2499 );
not ( n2501 , n1859 );
buf ( n2502 , n749 );
not ( n2503 , n2502 );
not ( n2504 , n2503 );
buf ( n2505 , n2504 );
and ( n2506 , n2481 , n2482 );
xor ( n2507 , n2505 , n2506 );
and ( n2508 , n2507 , n1838 );
buf ( n2509 , n843 );
and ( n2510 , n2509 , n1842 );
buf ( n2511 , n778 );
and ( n2512 , n2511 , n1845 );
buf ( n2513 , n810 );
and ( n2514 , n2513 , n1848 );
or ( n2515 , n2508 , n2510 , n2512 , n2514 );
and ( n2516 , n2501 , n2515 );
not ( n2517 , n2515 );
and ( n2518 , n2493 , n2494 );
xor ( n2519 , n2517 , n2518 );
and ( n2520 , n2519 , n1859 );
or ( n2521 , n2516 , n2520 );
not ( n2522 , n2521 );
not ( n2523 , n2522 );
or ( n2524 , n2500 , n2523 );
and ( n2525 , n2524 , n1859 );
not ( n2526 , n2525 );
and ( n2527 , n2526 , n1852 );
xor ( n2528 , n1852 , n1859 );
xor ( n2529 , n2528 , n1859 );
and ( n2530 , n2529 , n2525 );
or ( n2531 , n2527 , n2530 );
not ( n2532 , n946 );
and ( n2533 , n2532 , n1142 );
not ( n2534 , n1142 );
not ( n2535 , n1148 );
not ( n2536 , n1154 );
not ( n2537 , n1160 );
not ( n2538 , n952 );
not ( n2539 , n959 );
not ( n2540 , n965 );
not ( n2541 , n971 );
not ( n2542 , n977 );
not ( n2543 , n983 );
not ( n2544 , n989 );
not ( n2545 , n995 );
not ( n2546 , n1001 );
not ( n2547 , n1007 );
not ( n2548 , n1013 );
not ( n2549 , n1019 );
not ( n2550 , n1025 );
not ( n2551 , n1031 );
not ( n2552 , n1037 );
not ( n2553 , n1043 );
not ( n2554 , n1049 );
not ( n2555 , n1055 );
not ( n2556 , n1061 );
not ( n2557 , n1067 );
not ( n2558 , n1073 );
not ( n2559 , n1079 );
not ( n2560 , n1085 );
not ( n2561 , n911 );
and ( n2562 , n2560 , n2561 );
and ( n2563 , n2559 , n2562 );
and ( n2564 , n2558 , n2563 );
and ( n2565 , n2557 , n2564 );
and ( n2566 , n2556 , n2565 );
and ( n2567 , n2555 , n2566 );
and ( n2568 , n2554 , n2567 );
and ( n2569 , n2553 , n2568 );
and ( n2570 , n2552 , n2569 );
and ( n2571 , n2551 , n2570 );
and ( n2572 , n2550 , n2571 );
and ( n2573 , n2549 , n2572 );
and ( n2574 , n2548 , n2573 );
and ( n2575 , n2547 , n2574 );
and ( n2576 , n2546 , n2575 );
and ( n2577 , n2545 , n2576 );
and ( n2578 , n2544 , n2577 );
and ( n2579 , n2543 , n2578 );
and ( n2580 , n2542 , n2579 );
and ( n2581 , n2541 , n2580 );
and ( n2582 , n2540 , n2581 );
and ( n2583 , n2539 , n2582 );
and ( n2584 , n2538 , n2583 );
and ( n2585 , n2537 , n2584 );
and ( n2586 , n2536 , n2585 );
and ( n2587 , n2535 , n2586 );
xor ( n2588 , n2534 , n2587 );
and ( n2589 , n2588 , n946 );
or ( n2590 , n2533 , n2589 );
not ( n2591 , n2590 );
not ( n2592 , n2591 );
not ( n2593 , n2592 );
not ( n2594 , n2593 );
not ( n2595 , n946 );
not ( n2596 , n1124 );
not ( n2597 , n1130 );
not ( n2598 , n1136 );
and ( n2599 , n2534 , n2587 );
and ( n2600 , n2598 , n2599 );
and ( n2601 , n2597 , n2600 );
and ( n2602 , n2596 , n2601 );
xor ( n2603 , n2595 , n2602 );
buf ( n2604 , n946 );
and ( n2605 , n2603 , n2604 );
buf ( n2606 , n2605 );
not ( n2607 , n2606 );
not ( n2608 , n2607 );
not ( n2609 , n2608 );
not ( n2610 , n946 );
and ( n2611 , n2610 , n1124 );
xor ( n2612 , n2596 , n2601 );
and ( n2613 , n2612 , n946 );
or ( n2614 , n2611 , n2613 );
not ( n2615 , n2614 );
not ( n2616 , n2615 );
not ( n2617 , n2616 );
not ( n2618 , n946 );
and ( n2619 , n2618 , n1130 );
xor ( n2620 , n2597 , n2600 );
and ( n2621 , n2620 , n946 );
or ( n2622 , n2619 , n2621 );
not ( n2623 , n2622 );
not ( n2624 , n2623 );
not ( n2625 , n2624 );
not ( n2626 , n946 );
and ( n2627 , n2626 , n1136 );
xor ( n2628 , n2598 , n2599 );
and ( n2629 , n2628 , n946 );
or ( n2630 , n2627 , n2629 );
not ( n2631 , n2630 );
not ( n2632 , n2631 );
not ( n2633 , n2632 );
not ( n2634 , n2592 );
and ( n2635 , n2633 , n2634 );
and ( n2636 , n2625 , n2635 );
and ( n2637 , n2617 , n2636 );
and ( n2638 , n2609 , n2637 );
not ( n2639 , n2638 );
and ( n2640 , n2639 , n946 );
buf ( n2641 , n2640 );
not ( n2642 , n2641 );
not ( n2643 , n946 );
and ( n2644 , n2643 , n2632 );
xor ( n2645 , n2633 , n2634 );
and ( n2646 , n2645 , n946 );
or ( n2647 , n2644 , n2646 );
and ( n2648 , n2642 , n2647 );
not ( n2649 , n2647 );
not ( n2650 , n2592 );
xor ( n2651 , n2649 , n2650 );
and ( n2652 , n2651 , n2641 );
or ( n2653 , n2648 , n2652 );
not ( n2654 , n2653 );
not ( n2655 , n2654 );
or ( n2656 , n2594 , n2655 );
and ( n2657 , n2656 , n2641 );
not ( n2658 , n2657 );
and ( n2659 , n2658 , n2594 );
xor ( n2660 , n2594 , n2641 );
xor ( n2661 , n2660 , n2641 );
and ( n2662 , n2661 , n2657 );
or ( n2663 , n2659 , n2662 );
not ( n2664 , n2657 );
and ( n2665 , n2664 , n2655 );
xor ( n2666 , n2655 , n2641 );
and ( n2667 , n2660 , n2641 );
xor ( n2668 , n2666 , n2667 );
and ( n2669 , n2668 , n2657 );
or ( n2670 , n2665 , n2669 );
and ( n2671 , n2663 , n2670 );
and ( n2672 , n2531 , n2671 );
not ( n2673 , n2663 );
and ( n2674 , n2673 , n2670 );
and ( n2675 , n2531 , n2674 );
buf ( n2676 , n814 );
not ( n2677 , n2676 );
not ( n2678 , n1859 );
not ( n2679 , n1859 );
and ( n2680 , n2679 , n1891 );
not ( n2681 , n1891 );
not ( n2682 , n1868 );
not ( n2683 , n1850 );
and ( n2684 , n2682 , n2683 );
xor ( n2685 , n2681 , n2684 );
and ( n2686 , n2685 , n1859 );
or ( n2687 , n2680 , n2686 );
not ( n2688 , n2687 );
buf ( n2689 , n2688 );
buf ( n2690 , n2689 );
not ( n2691 , n2690 );
and ( n2692 , n2678 , n2691 );
not ( n2693 , n2691 );
not ( n2694 , n1859 );
and ( n2695 , n2694 , n1868 );
xor ( n2696 , n2682 , n2683 );
and ( n2697 , n2696 , n1859 );
or ( n2698 , n2695 , n2697 );
not ( n2699 , n2698 );
buf ( n2700 , n2699 );
buf ( n2701 , n2700 );
not ( n2702 , n2701 );
not ( n2703 , n2702 );
xor ( n2704 , n2693 , n2703 );
and ( n2705 , n2704 , n1859 );
or ( n2706 , n2692 , n2705 );
and ( n2707 , n2677 , n2706 );
not ( n2708 , n2702 );
not ( n2709 , n2708 );
not ( n2710 , n1859 );
buf ( n2711 , n845 );
and ( n2712 , n2711 , n1842 );
buf ( n2713 , n780 );
and ( n2714 , n2713 , n1845 );
buf ( n2715 , n812 );
and ( n2716 , n2715 , n1848 );
or ( n2717 , 1'b0 , n2712 , n2714 , n2716 );
not ( n2718 , n2717 );
and ( n2719 , n2505 , n2506 );
buf ( n2720 , n2719 );
and ( n2721 , n2720 , n1838 );
buf ( n2722 , n844 );
and ( n2723 , n2722 , n1842 );
buf ( n2724 , n779 );
and ( n2725 , n2724 , n1845 );
buf ( n2726 , n811 );
and ( n2727 , n2726 , n1848 );
or ( n2728 , n2721 , n2723 , n2725 , n2727 );
not ( n2729 , n2728 );
not ( n2730 , n2515 );
not ( n2731 , n2491 );
not ( n2732 , n2467 );
not ( n2733 , n2443 );
not ( n2734 , n2419 );
not ( n2735 , n2395 );
not ( n2736 , n2371 );
not ( n2737 , n2347 );
not ( n2738 , n2323 );
not ( n2739 , n2299 );
not ( n2740 , n2275 );
not ( n2741 , n2251 );
not ( n2742 , n2227 );
not ( n2743 , n2203 );
not ( n2744 , n2179 );
not ( n2745 , n2155 );
not ( n2746 , n2131 );
not ( n2747 , n2107 );
not ( n2748 , n2083 );
not ( n2749 , n2059 );
not ( n2750 , n2035 );
not ( n2751 , n2011 );
not ( n2752 , n1987 );
not ( n2753 , n1963 );
not ( n2754 , n1939 );
not ( n2755 , n1915 );
and ( n2756 , n2681 , n2684 );
and ( n2757 , n2755 , n2756 );
and ( n2758 , n2754 , n2757 );
and ( n2759 , n2753 , n2758 );
and ( n2760 , n2752 , n2759 );
and ( n2761 , n2751 , n2760 );
and ( n2762 , n2750 , n2761 );
and ( n2763 , n2749 , n2762 );
and ( n2764 , n2748 , n2763 );
and ( n2765 , n2747 , n2764 );
and ( n2766 , n2746 , n2765 );
and ( n2767 , n2745 , n2766 );
and ( n2768 , n2744 , n2767 );
and ( n2769 , n2743 , n2768 );
and ( n2770 , n2742 , n2769 );
and ( n2771 , n2741 , n2770 );
and ( n2772 , n2740 , n2771 );
and ( n2773 , n2739 , n2772 );
and ( n2774 , n2738 , n2773 );
and ( n2775 , n2737 , n2774 );
and ( n2776 , n2736 , n2775 );
and ( n2777 , n2735 , n2776 );
and ( n2778 , n2734 , n2777 );
and ( n2779 , n2733 , n2778 );
and ( n2780 , n2732 , n2779 );
and ( n2781 , n2731 , n2780 );
and ( n2782 , n2730 , n2781 );
and ( n2783 , n2729 , n2782 );
and ( n2784 , n2718 , n2783 );
xor ( n2785 , n2710 , n2784 );
buf ( n2786 , n1859 );
and ( n2787 , n2785 , n2786 );
buf ( n2788 , n2787 );
not ( n2789 , n2788 );
not ( n2790 , n2789 );
not ( n2791 , n2790 );
not ( n2792 , n1859 );
and ( n2793 , n2792 , n2717 );
xor ( n2794 , n2718 , n2783 );
and ( n2795 , n2794 , n1859 );
or ( n2796 , n2793 , n2795 );
not ( n2797 , n2796 );
not ( n2798 , n2797 );
not ( n2799 , n2798 );
not ( n2800 , n1859 );
and ( n2801 , n2800 , n2728 );
xor ( n2802 , n2729 , n2782 );
and ( n2803 , n2802 , n1859 );
or ( n2804 , n2801 , n2803 );
not ( n2805 , n2804 );
not ( n2806 , n2805 );
not ( n2807 , n2806 );
not ( n2808 , n1859 );
and ( n2809 , n2808 , n2515 );
xor ( n2810 , n2730 , n2781 );
and ( n2811 , n2810 , n1859 );
or ( n2812 , n2809 , n2811 );
not ( n2813 , n2812 );
not ( n2814 , n2813 );
not ( n2815 , n2814 );
not ( n2816 , n1859 );
and ( n2817 , n2816 , n2491 );
xor ( n2818 , n2731 , n2780 );
and ( n2819 , n2818 , n1859 );
or ( n2820 , n2817 , n2819 );
not ( n2821 , n2820 );
not ( n2822 , n2821 );
not ( n2823 , n2822 );
not ( n2824 , n1859 );
and ( n2825 , n2824 , n2467 );
xor ( n2826 , n2732 , n2779 );
and ( n2827 , n2826 , n1859 );
or ( n2828 , n2825 , n2827 );
not ( n2829 , n2828 );
not ( n2830 , n2829 );
not ( n2831 , n2830 );
not ( n2832 , n1859 );
and ( n2833 , n2832 , n2443 );
xor ( n2834 , n2733 , n2778 );
and ( n2835 , n2834 , n1859 );
or ( n2836 , n2833 , n2835 );
not ( n2837 , n2836 );
not ( n2838 , n2837 );
not ( n2839 , n2838 );
not ( n2840 , n1859 );
and ( n2841 , n2840 , n2419 );
xor ( n2842 , n2734 , n2777 );
and ( n2843 , n2842 , n1859 );
or ( n2844 , n2841 , n2843 );
not ( n2845 , n2844 );
not ( n2846 , n2845 );
not ( n2847 , n2846 );
not ( n2848 , n1859 );
and ( n2849 , n2848 , n2395 );
xor ( n2850 , n2735 , n2776 );
and ( n2851 , n2850 , n1859 );
or ( n2852 , n2849 , n2851 );
not ( n2853 , n2852 );
not ( n2854 , n2853 );
not ( n2855 , n2854 );
not ( n2856 , n1859 );
and ( n2857 , n2856 , n2371 );
xor ( n2858 , n2736 , n2775 );
and ( n2859 , n2858 , n1859 );
or ( n2860 , n2857 , n2859 );
not ( n2861 , n2860 );
not ( n2862 , n2861 );
not ( n2863 , n2862 );
not ( n2864 , n1859 );
and ( n2865 , n2864 , n2347 );
xor ( n2866 , n2737 , n2774 );
and ( n2867 , n2866 , n1859 );
or ( n2868 , n2865 , n2867 );
not ( n2869 , n2868 );
not ( n2870 , n2869 );
not ( n2871 , n2870 );
not ( n2872 , n1859 );
and ( n2873 , n2872 , n2323 );
xor ( n2874 , n2738 , n2773 );
and ( n2875 , n2874 , n1859 );
or ( n2876 , n2873 , n2875 );
not ( n2877 , n2876 );
not ( n2878 , n2877 );
not ( n2879 , n2878 );
not ( n2880 , n1859 );
and ( n2881 , n2880 , n2299 );
xor ( n2882 , n2739 , n2772 );
and ( n2883 , n2882 , n1859 );
or ( n2884 , n2881 , n2883 );
not ( n2885 , n2884 );
not ( n2886 , n2885 );
not ( n2887 , n2886 );
not ( n2888 , n1859 );
and ( n2889 , n2888 , n2275 );
xor ( n2890 , n2740 , n2771 );
and ( n2891 , n2890 , n1859 );
or ( n2892 , n2889 , n2891 );
not ( n2893 , n2892 );
not ( n2894 , n2893 );
not ( n2895 , n2894 );
not ( n2896 , n1859 );
and ( n2897 , n2896 , n2251 );
xor ( n2898 , n2741 , n2770 );
and ( n2899 , n2898 , n1859 );
or ( n2900 , n2897 , n2899 );
not ( n2901 , n2900 );
not ( n2902 , n2901 );
not ( n2903 , n2902 );
not ( n2904 , n1859 );
and ( n2905 , n2904 , n2227 );
xor ( n2906 , n2742 , n2769 );
and ( n2907 , n2906 , n1859 );
or ( n2908 , n2905 , n2907 );
not ( n2909 , n2908 );
not ( n2910 , n2909 );
not ( n2911 , n2910 );
not ( n2912 , n1859 );
and ( n2913 , n2912 , n2203 );
xor ( n2914 , n2743 , n2768 );
and ( n2915 , n2914 , n1859 );
or ( n2916 , n2913 , n2915 );
not ( n2917 , n2916 );
not ( n2918 , n2917 );
not ( n2919 , n2918 );
not ( n2920 , n1859 );
and ( n2921 , n2920 , n2179 );
xor ( n2922 , n2744 , n2767 );
and ( n2923 , n2922 , n1859 );
or ( n2924 , n2921 , n2923 );
not ( n2925 , n2924 );
not ( n2926 , n2925 );
not ( n2927 , n2926 );
not ( n2928 , n1859 );
and ( n2929 , n2928 , n2155 );
xor ( n2930 , n2745 , n2766 );
and ( n2931 , n2930 , n1859 );
or ( n2932 , n2929 , n2931 );
not ( n2933 , n2932 );
not ( n2934 , n2933 );
not ( n2935 , n2934 );
not ( n2936 , n1859 );
and ( n2937 , n2936 , n2131 );
xor ( n2938 , n2746 , n2765 );
and ( n2939 , n2938 , n1859 );
or ( n2940 , n2937 , n2939 );
not ( n2941 , n2940 );
not ( n2942 , n2941 );
not ( n2943 , n2942 );
not ( n2944 , n1859 );
and ( n2945 , n2944 , n2107 );
xor ( n2946 , n2747 , n2764 );
and ( n2947 , n2946 , n1859 );
or ( n2948 , n2945 , n2947 );
not ( n2949 , n2948 );
not ( n2950 , n2949 );
not ( n2951 , n2950 );
not ( n2952 , n1859 );
and ( n2953 , n2952 , n2083 );
xor ( n2954 , n2748 , n2763 );
and ( n2955 , n2954 , n1859 );
or ( n2956 , n2953 , n2955 );
not ( n2957 , n2956 );
buf ( n2958 , n2957 );
buf ( n2959 , n2958 );
not ( n2960 , n2959 );
not ( n2961 , n2960 );
not ( n2962 , n1859 );
and ( n2963 , n2962 , n2059 );
xor ( n2964 , n2749 , n2762 );
and ( n2965 , n2964 , n1859 );
or ( n2966 , n2963 , n2965 );
not ( n2967 , n2966 );
buf ( n2968 , n2967 );
buf ( n2969 , n2968 );
not ( n2970 , n2969 );
not ( n2971 , n2970 );
not ( n2972 , n1859 );
and ( n2973 , n2972 , n2035 );
xor ( n2974 , n2750 , n2761 );
and ( n2975 , n2974 , n1859 );
or ( n2976 , n2973 , n2975 );
not ( n2977 , n2976 );
buf ( n2978 , n2977 );
buf ( n2979 , n2978 );
not ( n2980 , n2979 );
not ( n2981 , n2980 );
not ( n2982 , n1859 );
and ( n2983 , n2982 , n2011 );
xor ( n2984 , n2751 , n2760 );
and ( n2985 , n2984 , n1859 );
or ( n2986 , n2983 , n2985 );
not ( n2987 , n2986 );
buf ( n2988 , n2987 );
buf ( n2989 , n2988 );
not ( n2990 , n2989 );
not ( n2991 , n2990 );
not ( n2992 , n1859 );
and ( n2993 , n2992 , n1987 );
xor ( n2994 , n2752 , n2759 );
and ( n2995 , n2994 , n1859 );
or ( n2996 , n2993 , n2995 );
not ( n2997 , n2996 );
buf ( n2998 , n2997 );
buf ( n2999 , n2998 );
not ( n3000 , n2999 );
not ( n3001 , n3000 );
not ( n3002 , n1859 );
and ( n3003 , n3002 , n1963 );
xor ( n3004 , n2753 , n2758 );
and ( n3005 , n3004 , n1859 );
or ( n3006 , n3003 , n3005 );
not ( n3007 , n3006 );
buf ( n3008 , n3007 );
buf ( n3009 , n3008 );
not ( n3010 , n3009 );
not ( n3011 , n3010 );
not ( n3012 , n1859 );
and ( n3013 , n3012 , n1939 );
xor ( n3014 , n2754 , n2757 );
and ( n3015 , n3014 , n1859 );
or ( n3016 , n3013 , n3015 );
not ( n3017 , n3016 );
buf ( n3018 , n3017 );
buf ( n3019 , n3018 );
not ( n3020 , n3019 );
not ( n3021 , n3020 );
not ( n3022 , n1859 );
and ( n3023 , n3022 , n1915 );
xor ( n3024 , n2755 , n2756 );
and ( n3025 , n3024 , n1859 );
or ( n3026 , n3023 , n3025 );
not ( n3027 , n3026 );
buf ( n3028 , n3027 );
buf ( n3029 , n3028 );
not ( n3030 , n3029 );
not ( n3031 , n3030 );
and ( n3032 , n2693 , n2703 );
and ( n3033 , n3031 , n3032 );
and ( n3034 , n3021 , n3033 );
and ( n3035 , n3011 , n3034 );
and ( n3036 , n3001 , n3035 );
and ( n3037 , n2991 , n3036 );
and ( n3038 , n2981 , n3037 );
and ( n3039 , n2971 , n3038 );
and ( n3040 , n2961 , n3039 );
and ( n3041 , n2951 , n3040 );
and ( n3042 , n2943 , n3041 );
and ( n3043 , n2935 , n3042 );
and ( n3044 , n2927 , n3043 );
and ( n3045 , n2919 , n3044 );
and ( n3046 , n2911 , n3045 );
and ( n3047 , n2903 , n3046 );
and ( n3048 , n2895 , n3047 );
and ( n3049 , n2887 , n3048 );
and ( n3050 , n2879 , n3049 );
and ( n3051 , n2871 , n3050 );
and ( n3052 , n2863 , n3051 );
and ( n3053 , n2855 , n3052 );
and ( n3054 , n2847 , n3053 );
and ( n3055 , n2839 , n3054 );
and ( n3056 , n2831 , n3055 );
and ( n3057 , n2823 , n3056 );
and ( n3058 , n2815 , n3057 );
and ( n3059 , n2807 , n3058 );
and ( n3060 , n2799 , n3059 );
and ( n3061 , n2791 , n3060 );
not ( n3062 , n3061 );
and ( n3063 , n3062 , n1859 );
buf ( n3064 , n3063 );
not ( n3065 , n3064 );
and ( n3066 , n3065 , n2706 );
not ( n3067 , n2706 );
not ( n3068 , n2702 );
xor ( n3069 , n3067 , n3068 );
and ( n3070 , n3069 , n3064 );
or ( n3071 , n3066 , n3070 );
not ( n3072 , n3071 );
not ( n3073 , n3072 );
or ( n3074 , n2709 , n3073 );
not ( n3075 , n3064 );
not ( n3076 , n1859 );
and ( n3077 , n3076 , n3030 );
xor ( n3078 , n3031 , n3032 );
and ( n3079 , n3078 , n1859 );
or ( n3080 , n3077 , n3079 );
and ( n3081 , n3075 , n3080 );
not ( n3082 , n3080 );
and ( n3083 , n3067 , n3068 );
xor ( n3084 , n3082 , n3083 );
and ( n3085 , n3084 , n3064 );
or ( n3086 , n3081 , n3085 );
not ( n3087 , n3086 );
not ( n3088 , n3087 );
or ( n3089 , n3074 , n3088 );
not ( n3090 , n3064 );
not ( n3091 , n1859 );
and ( n3092 , n3091 , n3020 );
xor ( n3093 , n3021 , n3033 );
and ( n3094 , n3093 , n1859 );
or ( n3095 , n3092 , n3094 );
and ( n3096 , n3090 , n3095 );
not ( n3097 , n3095 );
and ( n3098 , n3082 , n3083 );
xor ( n3099 , n3097 , n3098 );
and ( n3100 , n3099 , n3064 );
or ( n3101 , n3096 , n3100 );
not ( n3102 , n3101 );
not ( n3103 , n3102 );
or ( n3104 , n3089 , n3103 );
not ( n3105 , n3064 );
not ( n3106 , n1859 );
and ( n3107 , n3106 , n3010 );
xor ( n3108 , n3011 , n3034 );
and ( n3109 , n3108 , n1859 );
or ( n3110 , n3107 , n3109 );
and ( n3111 , n3105 , n3110 );
not ( n3112 , n3110 );
and ( n3113 , n3097 , n3098 );
xor ( n3114 , n3112 , n3113 );
and ( n3115 , n3114 , n3064 );
or ( n3116 , n3111 , n3115 );
not ( n3117 , n3116 );
not ( n3118 , n3117 );
or ( n3119 , n3104 , n3118 );
not ( n3120 , n3064 );
not ( n3121 , n1859 );
and ( n3122 , n3121 , n3000 );
xor ( n3123 , n3001 , n3035 );
and ( n3124 , n3123 , n1859 );
or ( n3125 , n3122 , n3124 );
and ( n3126 , n3120 , n3125 );
not ( n3127 , n3125 );
and ( n3128 , n3112 , n3113 );
xor ( n3129 , n3127 , n3128 );
and ( n3130 , n3129 , n3064 );
or ( n3131 , n3126 , n3130 );
not ( n3132 , n3131 );
not ( n3133 , n3132 );
or ( n3134 , n3119 , n3133 );
not ( n3135 , n3064 );
not ( n3136 , n1859 );
and ( n3137 , n3136 , n2990 );
xor ( n3138 , n2991 , n3036 );
and ( n3139 , n3138 , n1859 );
or ( n3140 , n3137 , n3139 );
and ( n3141 , n3135 , n3140 );
not ( n3142 , n3140 );
and ( n3143 , n3127 , n3128 );
xor ( n3144 , n3142 , n3143 );
and ( n3145 , n3144 , n3064 );
or ( n3146 , n3141 , n3145 );
not ( n3147 , n3146 );
not ( n3148 , n3147 );
or ( n3149 , n3134 , n3148 );
not ( n3150 , n3064 );
not ( n3151 , n1859 );
and ( n3152 , n3151 , n2980 );
xor ( n3153 , n2981 , n3037 );
and ( n3154 , n3153 , n1859 );
or ( n3155 , n3152 , n3154 );
and ( n3156 , n3150 , n3155 );
not ( n3157 , n3155 );
and ( n3158 , n3142 , n3143 );
xor ( n3159 , n3157 , n3158 );
and ( n3160 , n3159 , n3064 );
or ( n3161 , n3156 , n3160 );
not ( n3162 , n3161 );
not ( n3163 , n3162 );
or ( n3164 , n3149 , n3163 );
not ( n3165 , n3064 );
not ( n3166 , n1859 );
and ( n3167 , n3166 , n2970 );
xor ( n3168 , n2971 , n3038 );
and ( n3169 , n3168 , n1859 );
or ( n3170 , n3167 , n3169 );
and ( n3171 , n3165 , n3170 );
not ( n3172 , n3170 );
and ( n3173 , n3157 , n3158 );
xor ( n3174 , n3172 , n3173 );
and ( n3175 , n3174 , n3064 );
or ( n3176 , n3171 , n3175 );
not ( n3177 , n3176 );
not ( n3178 , n3177 );
or ( n3179 , n3164 , n3178 );
not ( n3180 , n3064 );
not ( n3181 , n1859 );
and ( n3182 , n3181 , n2960 );
xor ( n3183 , n2961 , n3039 );
and ( n3184 , n3183 , n1859 );
or ( n3185 , n3182 , n3184 );
and ( n3186 , n3180 , n3185 );
not ( n3187 , n3185 );
and ( n3188 , n3172 , n3173 );
xor ( n3189 , n3187 , n3188 );
and ( n3190 , n3189 , n3064 );
or ( n3191 , n3186 , n3190 );
not ( n3192 , n3191 );
not ( n3193 , n3192 );
or ( n3194 , n3179 , n3193 );
not ( n3195 , n3064 );
not ( n3196 , n1859 );
and ( n3197 , n3196 , n2950 );
xor ( n3198 , n2951 , n3040 );
and ( n3199 , n3198 , n1859 );
or ( n3200 , n3197 , n3199 );
and ( n3201 , n3195 , n3200 );
not ( n3202 , n3200 );
and ( n3203 , n3187 , n3188 );
xor ( n3204 , n3202 , n3203 );
and ( n3205 , n3204 , n3064 );
or ( n3206 , n3201 , n3205 );
not ( n3207 , n3206 );
not ( n3208 , n3207 );
or ( n3209 , n3194 , n3208 );
not ( n3210 , n3064 );
not ( n3211 , n1859 );
and ( n3212 , n3211 , n2942 );
xor ( n3213 , n2943 , n3041 );
and ( n3214 , n3213 , n1859 );
or ( n3215 , n3212 , n3214 );
and ( n3216 , n3210 , n3215 );
not ( n3217 , n3215 );
and ( n3218 , n3202 , n3203 );
xor ( n3219 , n3217 , n3218 );
and ( n3220 , n3219 , n3064 );
or ( n3221 , n3216 , n3220 );
not ( n3222 , n3221 );
not ( n3223 , n3222 );
or ( n3224 , n3209 , n3223 );
not ( n3225 , n3064 );
not ( n3226 , n1859 );
and ( n3227 , n3226 , n2934 );
xor ( n3228 , n2935 , n3042 );
and ( n3229 , n3228 , n1859 );
or ( n3230 , n3227 , n3229 );
and ( n3231 , n3225 , n3230 );
not ( n3232 , n3230 );
and ( n3233 , n3217 , n3218 );
xor ( n3234 , n3232 , n3233 );
and ( n3235 , n3234 , n3064 );
or ( n3236 , n3231 , n3235 );
not ( n3237 , n3236 );
not ( n3238 , n3237 );
or ( n3239 , n3224 , n3238 );
not ( n3240 , n3064 );
not ( n3241 , n1859 );
and ( n3242 , n3241 , n2926 );
xor ( n3243 , n2927 , n3043 );
and ( n3244 , n3243 , n1859 );
or ( n3245 , n3242 , n3244 );
and ( n3246 , n3240 , n3245 );
not ( n3247 , n3245 );
and ( n3248 , n3232 , n3233 );
xor ( n3249 , n3247 , n3248 );
and ( n3250 , n3249 , n3064 );
or ( n3251 , n3246 , n3250 );
not ( n3252 , n3251 );
not ( n3253 , n3252 );
or ( n3254 , n3239 , n3253 );
not ( n3255 , n3064 );
not ( n3256 , n1859 );
and ( n3257 , n3256 , n2918 );
xor ( n3258 , n2919 , n3044 );
and ( n3259 , n3258 , n1859 );
or ( n3260 , n3257 , n3259 );
and ( n3261 , n3255 , n3260 );
not ( n3262 , n3260 );
and ( n3263 , n3247 , n3248 );
xor ( n3264 , n3262 , n3263 );
and ( n3265 , n3264 , n3064 );
or ( n3266 , n3261 , n3265 );
not ( n3267 , n3266 );
not ( n3268 , n3267 );
or ( n3269 , n3254 , n3268 );
not ( n3270 , n3064 );
not ( n3271 , n1859 );
and ( n3272 , n3271 , n2910 );
xor ( n3273 , n2911 , n3045 );
and ( n3274 , n3273 , n1859 );
or ( n3275 , n3272 , n3274 );
and ( n3276 , n3270 , n3275 );
not ( n3277 , n3275 );
and ( n3278 , n3262 , n3263 );
xor ( n3279 , n3277 , n3278 );
and ( n3280 , n3279 , n3064 );
or ( n3281 , n3276 , n3280 );
not ( n3282 , n3281 );
not ( n3283 , n3282 );
or ( n3284 , n3269 , n3283 );
not ( n3285 , n3064 );
not ( n3286 , n1859 );
and ( n3287 , n3286 , n2902 );
xor ( n3288 , n2903 , n3046 );
and ( n3289 , n3288 , n1859 );
or ( n3290 , n3287 , n3289 );
and ( n3291 , n3285 , n3290 );
not ( n3292 , n3290 );
and ( n3293 , n3277 , n3278 );
xor ( n3294 , n3292 , n3293 );
and ( n3295 , n3294 , n3064 );
or ( n3296 , n3291 , n3295 );
not ( n3297 , n3296 );
not ( n3298 , n3297 );
or ( n3299 , n3284 , n3298 );
not ( n3300 , n3064 );
not ( n3301 , n1859 );
and ( n3302 , n3301 , n2894 );
xor ( n3303 , n2895 , n3047 );
and ( n3304 , n3303 , n1859 );
or ( n3305 , n3302 , n3304 );
and ( n3306 , n3300 , n3305 );
not ( n3307 , n3305 );
and ( n3308 , n3292 , n3293 );
xor ( n3309 , n3307 , n3308 );
and ( n3310 , n3309 , n3064 );
or ( n3311 , n3306 , n3310 );
not ( n3312 , n3311 );
not ( n3313 , n3312 );
or ( n3314 , n3299 , n3313 );
not ( n3315 , n3064 );
not ( n3316 , n1859 );
and ( n3317 , n3316 , n2886 );
xor ( n3318 , n2887 , n3048 );
and ( n3319 , n3318 , n1859 );
or ( n3320 , n3317 , n3319 );
and ( n3321 , n3315 , n3320 );
not ( n3322 , n3320 );
and ( n3323 , n3307 , n3308 );
xor ( n3324 , n3322 , n3323 );
and ( n3325 , n3324 , n3064 );
or ( n3326 , n3321 , n3325 );
not ( n3327 , n3326 );
not ( n3328 , n3327 );
or ( n3329 , n3314 , n3328 );
not ( n3330 , n3064 );
not ( n3331 , n1859 );
and ( n3332 , n3331 , n2878 );
xor ( n3333 , n2879 , n3049 );
and ( n3334 , n3333 , n1859 );
or ( n3335 , n3332 , n3334 );
and ( n3336 , n3330 , n3335 );
not ( n3337 , n3335 );
and ( n3338 , n3322 , n3323 );
xor ( n3339 , n3337 , n3338 );
and ( n3340 , n3339 , n3064 );
or ( n3341 , n3336 , n3340 );
not ( n3342 , n3341 );
not ( n3343 , n3342 );
or ( n3344 , n3329 , n3343 );
not ( n3345 , n3064 );
not ( n3346 , n1859 );
and ( n3347 , n3346 , n2870 );
xor ( n3348 , n2871 , n3050 );
and ( n3349 , n3348 , n1859 );
or ( n3350 , n3347 , n3349 );
and ( n3351 , n3345 , n3350 );
not ( n3352 , n3350 );
and ( n3353 , n3337 , n3338 );
xor ( n3354 , n3352 , n3353 );
and ( n3355 , n3354 , n3064 );
or ( n3356 , n3351 , n3355 );
not ( n3357 , n3356 );
not ( n3358 , n3357 );
or ( n3359 , n3344 , n3358 );
not ( n3360 , n3064 );
not ( n3361 , n1859 );
and ( n3362 , n3361 , n2862 );
xor ( n3363 , n2863 , n3051 );
and ( n3364 , n3363 , n1859 );
or ( n3365 , n3362 , n3364 );
and ( n3366 , n3360 , n3365 );
not ( n3367 , n3365 );
and ( n3368 , n3352 , n3353 );
xor ( n3369 , n3367 , n3368 );
and ( n3370 , n3369 , n3064 );
or ( n3371 , n3366 , n3370 );
not ( n3372 , n3371 );
not ( n3373 , n3372 );
or ( n3374 , n3359 , n3373 );
not ( n3375 , n3064 );
not ( n3376 , n1859 );
and ( n3377 , n3376 , n2854 );
xor ( n3378 , n2855 , n3052 );
and ( n3379 , n3378 , n1859 );
or ( n3380 , n3377 , n3379 );
and ( n3381 , n3375 , n3380 );
not ( n3382 , n3380 );
and ( n3383 , n3367 , n3368 );
xor ( n3384 , n3382 , n3383 );
and ( n3385 , n3384 , n3064 );
or ( n3386 , n3381 , n3385 );
not ( n3387 , n3386 );
not ( n3388 , n3387 );
or ( n3389 , n3374 , n3388 );
not ( n3390 , n3064 );
not ( n3391 , n1859 );
and ( n3392 , n3391 , n2846 );
xor ( n3393 , n2847 , n3053 );
and ( n3394 , n3393 , n1859 );
or ( n3395 , n3392 , n3394 );
and ( n3396 , n3390 , n3395 );
not ( n3397 , n3395 );
and ( n3398 , n3382 , n3383 );
xor ( n3399 , n3397 , n3398 );
and ( n3400 , n3399 , n3064 );
or ( n3401 , n3396 , n3400 );
not ( n3402 , n3401 );
not ( n3403 , n3402 );
or ( n3404 , n3389 , n3403 );
not ( n3405 , n3064 );
not ( n3406 , n1859 );
and ( n3407 , n3406 , n2838 );
xor ( n3408 , n2839 , n3054 );
and ( n3409 , n3408 , n1859 );
or ( n3410 , n3407 , n3409 );
and ( n3411 , n3405 , n3410 );
not ( n3412 , n3410 );
and ( n3413 , n3397 , n3398 );
xor ( n3414 , n3412 , n3413 );
and ( n3415 , n3414 , n3064 );
or ( n3416 , n3411 , n3415 );
not ( n3417 , n3416 );
not ( n3418 , n3417 );
or ( n3419 , n3404 , n3418 );
not ( n3420 , n3064 );
not ( n3421 , n1859 );
and ( n3422 , n3421 , n2830 );
xor ( n3423 , n2831 , n3055 );
and ( n3424 , n3423 , n1859 );
or ( n3425 , n3422 , n3424 );
and ( n3426 , n3420 , n3425 );
not ( n3427 , n3425 );
and ( n3428 , n3412 , n3413 );
xor ( n3429 , n3427 , n3428 );
and ( n3430 , n3429 , n3064 );
or ( n3431 , n3426 , n3430 );
not ( n3432 , n3431 );
not ( n3433 , n3432 );
or ( n3434 , n3419 , n3433 );
not ( n3435 , n3064 );
not ( n3436 , n1859 );
and ( n3437 , n3436 , n2822 );
xor ( n3438 , n2823 , n3056 );
and ( n3439 , n3438 , n1859 );
or ( n3440 , n3437 , n3439 );
and ( n3441 , n3435 , n3440 );
not ( n3442 , n3440 );
and ( n3443 , n3427 , n3428 );
xor ( n3444 , n3442 , n3443 );
and ( n3445 , n3444 , n3064 );
or ( n3446 , n3441 , n3445 );
not ( n3447 , n3446 );
not ( n3448 , n3447 );
or ( n3449 , n3434 , n3448 );
not ( n3450 , n3064 );
not ( n3451 , n1859 );
and ( n3452 , n3451 , n2814 );
xor ( n3453 , n2815 , n3057 );
and ( n3454 , n3453 , n1859 );
or ( n3455 , n3452 , n3454 );
and ( n3456 , n3450 , n3455 );
not ( n3457 , n3455 );
and ( n3458 , n3442 , n3443 );
xor ( n3459 , n3457 , n3458 );
and ( n3460 , n3459 , n3064 );
or ( n3461 , n3456 , n3460 );
not ( n3462 , n3461 );
not ( n3463 , n3462 );
or ( n3464 , n3449 , n3463 );
not ( n3465 , n3064 );
not ( n3466 , n1859 );
and ( n3467 , n3466 , n2806 );
xor ( n3468 , n2807 , n3058 );
and ( n3469 , n3468 , n1859 );
or ( n3470 , n3467 , n3469 );
and ( n3471 , n3465 , n3470 );
not ( n3472 , n3470 );
and ( n3473 , n3457 , n3458 );
xor ( n3474 , n3472 , n3473 );
and ( n3475 , n3474 , n3064 );
or ( n3476 , n3471 , n3475 );
not ( n3477 , n3476 );
not ( n3478 , n3477 );
or ( n3479 , n3464 , n3478 );
and ( n3480 , n3479 , n3064 );
not ( n3481 , n3480 );
and ( n3482 , n3481 , n3073 );
xor ( n3483 , n3073 , n3064 );
xor ( n3484 , n2709 , n3064 );
and ( n3485 , n3484 , n3064 );
xor ( n3486 , n3483 , n3485 );
and ( n3487 , n3486 , n3480 );
or ( n3488 , n3482 , n3487 );
and ( n3489 , n3488 , n2676 );
or ( n3490 , n2707 , n3489 );
nor ( n3491 , n2673 , n2670 );
and ( n3492 , n3490 , n3491 );
nor ( n3493 , n2663 , n2670 );
and ( n3494 , n2706 , n3493 );
or ( n3495 , n2672 , n2675 , n3492 , n3494 );
not ( n3496 , n1425 );
not ( n3497 , n1439 );
nor ( n3498 , n3496 , n1432 , n3497 );
not ( n3499 , n3498 );
nor ( n3500 , n1425 , n1432 , n3497 );
not ( n3501 , n3500 );
and ( n3502 , n1425 , n1432 , n3497 );
not ( n3503 , n3502 );
and ( n3504 , n3496 , n1432 , n3497 );
not ( n3505 , n3504 );
nor ( n3506 , n3496 , n1432 , n1439 );
not ( n3507 , n3506 );
nor ( n3508 , n1425 , n1432 , n1439 );
not ( n3509 , n3508 );
buf ( n3510 , n719 );
and ( n3511 , n3509 , n3510 );
buf ( n3512 , n3511 );
and ( n3513 , n3507 , n3512 );
buf ( n3514 , n3506 );
or ( n3515 , n3513 , n3514 );
and ( n3516 , n3505 , n3515 );
buf ( n3517 , n3516 );
and ( n3518 , n3503 , n3517 );
buf ( n3519 , n3502 );
or ( n3520 , n3518 , n3519 );
and ( n3521 , n3501 , n3520 );
not ( n3522 , n2676 );
and ( n3523 , n3522 , n3510 );
buf ( n3524 , n2676 );
or ( n3525 , n3523 , n3524 );
and ( n3526 , n3525 , n3500 );
or ( n3527 , n3521 , n3526 );
and ( n3528 , n3499 , n3527 );
not ( n3529 , n2676 );
not ( n3530 , n3529 );
and ( n3531 , n3530 , n3510 );
buf ( n3532 , n3529 );
or ( n3533 , n3531 , n3532 );
and ( n3534 , n3533 , n3498 );
or ( n3535 , n3528 , n3534 );
not ( n3536 , n3535 );
not ( n3537 , n3498 );
not ( n3538 , n3500 );
not ( n3539 , n3502 );
not ( n3540 , n3504 );
not ( n3541 , n3506 );
not ( n3542 , n3508 );
buf ( n3543 , n720 );
and ( n3544 , n3542 , n3543 );
buf ( n3545 , n3544 );
and ( n3546 , n3541 , n3545 );
buf ( n3547 , n3546 );
and ( n3548 , n3540 , n3547 );
buf ( n3549 , n3504 );
or ( n3550 , n3548 , n3549 );
and ( n3551 , n3539 , n3550 );
buf ( n3552 , n3502 );
or ( n3553 , n3551 , n3552 );
and ( n3554 , n3538 , n3553 );
not ( n3555 , n2676 );
and ( n3556 , n3555 , n3543 );
buf ( n3557 , n2676 );
or ( n3558 , n3556 , n3557 );
and ( n3559 , n3558 , n3500 );
or ( n3560 , n3554 , n3559 );
and ( n3561 , n3537 , n3560 );
not ( n3562 , n3529 );
and ( n3563 , n3562 , n3543 );
buf ( n3564 , n3529 );
or ( n3565 , n3563 , n3564 );
and ( n3566 , n3565 , n3498 );
or ( n3567 , n3561 , n3566 );
not ( n3568 , n3567 );
nor ( n3569 , n3536 , n3568 );
and ( n3570 , n3495 , n3569 );
nor ( n3571 , n3536 , n3567 );
nor ( n3572 , n3535 , n3567 );
or ( n3573 , n3571 , n3572 );
nor ( n3574 , n3535 , n3568 );
or ( n3575 , n3573 , n3574 );
buf ( n3576 , n3575 );
and ( n3577 , n1447 , n3576 );
or ( n3578 , n3570 , n3577 );
and ( n3579 , n1707 , n1691 , n1698 , n1705 );
and ( n3580 , n3578 , n3579 );
buf ( n3581 , n685 );
or ( n3582 , n3491 , n2674 );
or ( n3583 , n3582 , n2671 );
and ( n3584 , n3581 , n3583 );
not ( n3585 , n911 );
not ( n3586 , n3585 );
not ( n3587 , n946 );
and ( n3588 , n3587 , n1085 );
not ( n3589 , n1085 );
not ( n3590 , n911 );
xor ( n3591 , n3589 , n3590 );
and ( n3592 , n3591 , n946 );
or ( n3593 , n3588 , n3592 );
not ( n3594 , n3593 );
not ( n3595 , n3594 );
or ( n3596 , n3586 , n3595 );
not ( n3597 , n946 );
and ( n3598 , n3597 , n1079 );
not ( n3599 , n1079 );
and ( n3600 , n3589 , n3590 );
xor ( n3601 , n3599 , n3600 );
and ( n3602 , n3601 , n946 );
or ( n3603 , n3598 , n3602 );
not ( n3604 , n3603 );
not ( n3605 , n3604 );
or ( n3606 , n3596 , n3605 );
not ( n3607 , n946 );
and ( n3608 , n3607 , n1073 );
not ( n3609 , n1073 );
and ( n3610 , n3599 , n3600 );
xor ( n3611 , n3609 , n3610 );
and ( n3612 , n3611 , n946 );
or ( n3613 , n3608 , n3612 );
not ( n3614 , n3613 );
not ( n3615 , n3614 );
or ( n3616 , n3606 , n3615 );
not ( n3617 , n946 );
and ( n3618 , n3617 , n1067 );
not ( n3619 , n1067 );
and ( n3620 , n3609 , n3610 );
xor ( n3621 , n3619 , n3620 );
and ( n3622 , n3621 , n946 );
or ( n3623 , n3618 , n3622 );
not ( n3624 , n3623 );
not ( n3625 , n3624 );
or ( n3626 , n3616 , n3625 );
not ( n3627 , n946 );
and ( n3628 , n3627 , n1061 );
not ( n3629 , n1061 );
and ( n3630 , n3619 , n3620 );
xor ( n3631 , n3629 , n3630 );
and ( n3632 , n3631 , n946 );
or ( n3633 , n3628 , n3632 );
not ( n3634 , n3633 );
not ( n3635 , n3634 );
or ( n3636 , n3626 , n3635 );
not ( n3637 , n946 );
and ( n3638 , n3637 , n1055 );
not ( n3639 , n1055 );
and ( n3640 , n3629 , n3630 );
xor ( n3641 , n3639 , n3640 );
and ( n3642 , n3641 , n946 );
or ( n3643 , n3638 , n3642 );
not ( n3644 , n3643 );
not ( n3645 , n3644 );
or ( n3646 , n3636 , n3645 );
not ( n3647 , n946 );
and ( n3648 , n3647 , n1049 );
not ( n3649 , n1049 );
and ( n3650 , n3639 , n3640 );
xor ( n3651 , n3649 , n3650 );
and ( n3652 , n3651 , n946 );
or ( n3653 , n3648 , n3652 );
not ( n3654 , n3653 );
not ( n3655 , n3654 );
or ( n3656 , n3646 , n3655 );
not ( n3657 , n946 );
and ( n3658 , n3657 , n1043 );
not ( n3659 , n1043 );
and ( n3660 , n3649 , n3650 );
xor ( n3661 , n3659 , n3660 );
and ( n3662 , n3661 , n946 );
or ( n3663 , n3658 , n3662 );
not ( n3664 , n3663 );
not ( n3665 , n3664 );
or ( n3666 , n3656 , n3665 );
not ( n3667 , n946 );
and ( n3668 , n3667 , n1037 );
not ( n3669 , n1037 );
and ( n3670 , n3659 , n3660 );
xor ( n3671 , n3669 , n3670 );
and ( n3672 , n3671 , n946 );
or ( n3673 , n3668 , n3672 );
not ( n3674 , n3673 );
not ( n3675 , n3674 );
or ( n3676 , n3666 , n3675 );
not ( n3677 , n946 );
and ( n3678 , n3677 , n1031 );
not ( n3679 , n1031 );
and ( n3680 , n3669 , n3670 );
xor ( n3681 , n3679 , n3680 );
and ( n3682 , n3681 , n946 );
or ( n3683 , n3678 , n3682 );
not ( n3684 , n3683 );
not ( n3685 , n3684 );
or ( n3686 , n3676 , n3685 );
not ( n3687 , n946 );
and ( n3688 , n3687 , n1025 );
not ( n3689 , n1025 );
and ( n3690 , n3679 , n3680 );
xor ( n3691 , n3689 , n3690 );
and ( n3692 , n3691 , n946 );
or ( n3693 , n3688 , n3692 );
not ( n3694 , n3693 );
not ( n3695 , n3694 );
or ( n3696 , n3686 , n3695 );
not ( n3697 , n946 );
and ( n3698 , n3697 , n1019 );
not ( n3699 , n1019 );
and ( n3700 , n3689 , n3690 );
xor ( n3701 , n3699 , n3700 );
and ( n3702 , n3701 , n946 );
or ( n3703 , n3698 , n3702 );
not ( n3704 , n3703 );
not ( n3705 , n3704 );
or ( n3706 , n3696 , n3705 );
not ( n3707 , n946 );
and ( n3708 , n3707 , n1013 );
not ( n3709 , n1013 );
and ( n3710 , n3699 , n3700 );
xor ( n3711 , n3709 , n3710 );
and ( n3712 , n3711 , n946 );
or ( n3713 , n3708 , n3712 );
not ( n3714 , n3713 );
not ( n3715 , n3714 );
or ( n3716 , n3706 , n3715 );
not ( n3717 , n946 );
and ( n3718 , n3717 , n1007 );
not ( n3719 , n1007 );
and ( n3720 , n3709 , n3710 );
xor ( n3721 , n3719 , n3720 );
and ( n3722 , n3721 , n946 );
or ( n3723 , n3718 , n3722 );
not ( n3724 , n3723 );
not ( n3725 , n3724 );
or ( n3726 , n3716 , n3725 );
not ( n3727 , n946 );
and ( n3728 , n3727 , n1001 );
not ( n3729 , n1001 );
and ( n3730 , n3719 , n3720 );
xor ( n3731 , n3729 , n3730 );
and ( n3732 , n3731 , n946 );
or ( n3733 , n3728 , n3732 );
not ( n3734 , n3733 );
not ( n3735 , n3734 );
or ( n3736 , n3726 , n3735 );
not ( n3737 , n946 );
and ( n3738 , n3737 , n995 );
not ( n3739 , n995 );
and ( n3740 , n3729 , n3730 );
xor ( n3741 , n3739 , n3740 );
and ( n3742 , n3741 , n946 );
or ( n3743 , n3738 , n3742 );
not ( n3744 , n3743 );
not ( n3745 , n3744 );
or ( n3746 , n3736 , n3745 );
not ( n3747 , n946 );
and ( n3748 , n3747 , n989 );
not ( n3749 , n989 );
and ( n3750 , n3739 , n3740 );
xor ( n3751 , n3749 , n3750 );
and ( n3752 , n3751 , n946 );
or ( n3753 , n3748 , n3752 );
not ( n3754 , n3753 );
not ( n3755 , n3754 );
or ( n3756 , n3746 , n3755 );
not ( n3757 , n946 );
and ( n3758 , n3757 , n983 );
not ( n3759 , n983 );
and ( n3760 , n3749 , n3750 );
xor ( n3761 , n3759 , n3760 );
and ( n3762 , n3761 , n946 );
or ( n3763 , n3758 , n3762 );
not ( n3764 , n3763 );
not ( n3765 , n3764 );
or ( n3766 , n3756 , n3765 );
not ( n3767 , n946 );
and ( n3768 , n3767 , n977 );
not ( n3769 , n977 );
and ( n3770 , n3759 , n3760 );
xor ( n3771 , n3769 , n3770 );
and ( n3772 , n3771 , n946 );
or ( n3773 , n3768 , n3772 );
not ( n3774 , n3773 );
not ( n3775 , n3774 );
or ( n3776 , n3766 , n3775 );
and ( n3777 , n3776 , n946 );
not ( n3778 , n3777 );
and ( n3779 , n3778 , n3586 );
xor ( n3780 , n3586 , n946 );
xor ( n3781 , n3780 , n946 );
and ( n3782 , n3781 , n3777 );
or ( n3783 , n3779 , n3782 );
and ( n3784 , n3783 , n3493 );
or ( n3785 , n3584 , n3784 );
xor ( n3786 , n1850 , n3785 );
not ( n3787 , n3786 );
not ( n3788 , n3787 );
buf ( n3789 , n654 );
and ( n3790 , n3789 , n3583 );
not ( n3791 , n3790 );
xor ( n3792 , n1859 , n3791 );
buf ( n3793 , n655 );
and ( n3794 , n3793 , n3583 );
not ( n3795 , n3794 );
and ( n3796 , n2717 , n3795 );
buf ( n3797 , n656 );
and ( n3798 , n3797 , n3583 );
not ( n3799 , n3798 );
and ( n3800 , n2728 , n3799 );
buf ( n3801 , n657 );
and ( n3802 , n3801 , n3583 );
not ( n3803 , n3802 );
and ( n3804 , n2515 , n3803 );
buf ( n3805 , n658 );
and ( n3806 , n3805 , n3583 );
not ( n3807 , n3806 );
and ( n3808 , n2491 , n3807 );
buf ( n3809 , n659 );
and ( n3810 , n3809 , n3583 );
not ( n3811 , n3810 );
and ( n3812 , n2467 , n3811 );
buf ( n3813 , n660 );
and ( n3814 , n3813 , n3583 );
not ( n3815 , n3814 );
and ( n3816 , n2443 , n3815 );
buf ( n3817 , n661 );
and ( n3818 , n3817 , n3583 );
not ( n3819 , n3818 );
and ( n3820 , n2419 , n3819 );
buf ( n3821 , n662 );
and ( n3822 , n3821 , n3583 );
not ( n3823 , n3822 );
and ( n3824 , n2395 , n3823 );
buf ( n3825 , n663 );
and ( n3826 , n3825 , n3583 );
not ( n3827 , n3826 );
and ( n3828 , n2371 , n3827 );
buf ( n3829 , n664 );
and ( n3830 , n3829 , n3583 );
not ( n3831 , n3830 );
and ( n3832 , n2347 , n3831 );
buf ( n3833 , n665 );
and ( n3834 , n3833 , n3583 );
not ( n3835 , n3834 );
and ( n3836 , n2323 , n3835 );
buf ( n3837 , n666 );
and ( n3838 , n3837 , n3583 );
not ( n3839 , n3777 );
and ( n3840 , n3839 , n3775 );
xor ( n3841 , n3775 , n946 );
xor ( n3842 , n3765 , n946 );
xor ( n3843 , n3755 , n946 );
xor ( n3844 , n3745 , n946 );
xor ( n3845 , n3735 , n946 );
xor ( n3846 , n3725 , n946 );
xor ( n3847 , n3715 , n946 );
xor ( n3848 , n3705 , n946 );
xor ( n3849 , n3695 , n946 );
xor ( n3850 , n3685 , n946 );
xor ( n3851 , n3675 , n946 );
xor ( n3852 , n3665 , n946 );
xor ( n3853 , n3655 , n946 );
xor ( n3854 , n3645 , n946 );
xor ( n3855 , n3635 , n946 );
xor ( n3856 , n3625 , n946 );
xor ( n3857 , n3615 , n946 );
xor ( n3858 , n3605 , n946 );
xor ( n3859 , n3595 , n946 );
and ( n3860 , n3780 , n946 );
and ( n3861 , n3859 , n3860 );
and ( n3862 , n3858 , n3861 );
and ( n3863 , n3857 , n3862 );
and ( n3864 , n3856 , n3863 );
and ( n3865 , n3855 , n3864 );
and ( n3866 , n3854 , n3865 );
and ( n3867 , n3853 , n3866 );
and ( n3868 , n3852 , n3867 );
and ( n3869 , n3851 , n3868 );
and ( n3870 , n3850 , n3869 );
and ( n3871 , n3849 , n3870 );
and ( n3872 , n3848 , n3871 );
and ( n3873 , n3847 , n3872 );
and ( n3874 , n3846 , n3873 );
and ( n3875 , n3845 , n3874 );
and ( n3876 , n3844 , n3875 );
and ( n3877 , n3843 , n3876 );
and ( n3878 , n3842 , n3877 );
xor ( n3879 , n3841 , n3878 );
and ( n3880 , n3879 , n3777 );
or ( n3881 , n3840 , n3880 );
and ( n3882 , n3881 , n3493 );
or ( n3883 , n3838 , n3882 );
not ( n3884 , n3883 );
and ( n3885 , n2299 , n3884 );
buf ( n3886 , n667 );
and ( n3887 , n3886 , n3583 );
not ( n3888 , n3777 );
and ( n3889 , n3888 , n3765 );
xor ( n3890 , n3842 , n3877 );
and ( n3891 , n3890 , n3777 );
or ( n3892 , n3889 , n3891 );
and ( n3893 , n3892 , n3493 );
or ( n3894 , n3887 , n3893 );
not ( n3895 , n3894 );
and ( n3896 , n2275 , n3895 );
buf ( n3897 , n668 );
and ( n3898 , n3897 , n3583 );
not ( n3899 , n3777 );
and ( n3900 , n3899 , n3755 );
xor ( n3901 , n3843 , n3876 );
and ( n3902 , n3901 , n3777 );
or ( n3903 , n3900 , n3902 );
and ( n3904 , n3903 , n3493 );
or ( n3905 , n3898 , n3904 );
not ( n3906 , n3905 );
and ( n3907 , n2251 , n3906 );
buf ( n3908 , n669 );
and ( n3909 , n3908 , n3583 );
not ( n3910 , n3777 );
and ( n3911 , n3910 , n3745 );
xor ( n3912 , n3844 , n3875 );
and ( n3913 , n3912 , n3777 );
or ( n3914 , n3911 , n3913 );
and ( n3915 , n3914 , n3493 );
or ( n3916 , n3909 , n3915 );
not ( n3917 , n3916 );
and ( n3918 , n2227 , n3917 );
buf ( n3919 , n670 );
and ( n3920 , n3919 , n3583 );
not ( n3921 , n3777 );
and ( n3922 , n3921 , n3735 );
xor ( n3923 , n3845 , n3874 );
and ( n3924 , n3923 , n3777 );
or ( n3925 , n3922 , n3924 );
and ( n3926 , n3925 , n3493 );
or ( n3927 , n3920 , n3926 );
not ( n3928 , n3927 );
and ( n3929 , n2203 , n3928 );
buf ( n3930 , n671 );
and ( n3931 , n3930 , n3583 );
not ( n3932 , n3777 );
and ( n3933 , n3932 , n3725 );
xor ( n3934 , n3846 , n3873 );
and ( n3935 , n3934 , n3777 );
or ( n3936 , n3933 , n3935 );
and ( n3937 , n3936 , n3493 );
or ( n3938 , n3931 , n3937 );
not ( n3939 , n3938 );
and ( n3940 , n2179 , n3939 );
buf ( n3941 , n672 );
and ( n3942 , n3941 , n3583 );
not ( n3943 , n3777 );
and ( n3944 , n3943 , n3715 );
xor ( n3945 , n3847 , n3872 );
and ( n3946 , n3945 , n3777 );
or ( n3947 , n3944 , n3946 );
and ( n3948 , n3947 , n3493 );
or ( n3949 , n3942 , n3948 );
not ( n3950 , n3949 );
and ( n3951 , n2155 , n3950 );
buf ( n3952 , n673 );
and ( n3953 , n3952 , n3583 );
not ( n3954 , n3777 );
and ( n3955 , n3954 , n3705 );
xor ( n3956 , n3848 , n3871 );
and ( n3957 , n3956 , n3777 );
or ( n3958 , n3955 , n3957 );
and ( n3959 , n3958 , n3493 );
or ( n3960 , n3953 , n3959 );
not ( n3961 , n3960 );
and ( n3962 , n2131 , n3961 );
buf ( n3963 , n674 );
and ( n3964 , n3963 , n3583 );
not ( n3965 , n3777 );
and ( n3966 , n3965 , n3695 );
xor ( n3967 , n3849 , n3870 );
and ( n3968 , n3967 , n3777 );
or ( n3969 , n3966 , n3968 );
and ( n3970 , n3969 , n3493 );
or ( n3971 , n3964 , n3970 );
not ( n3972 , n3971 );
and ( n3973 , n2107 , n3972 );
buf ( n3974 , n675 );
and ( n3975 , n3974 , n3583 );
not ( n3976 , n3777 );
and ( n3977 , n3976 , n3685 );
xor ( n3978 , n3850 , n3869 );
and ( n3979 , n3978 , n3777 );
or ( n3980 , n3977 , n3979 );
and ( n3981 , n3980 , n3493 );
or ( n3982 , n3975 , n3981 );
not ( n3983 , n3982 );
and ( n3984 , n2083 , n3983 );
buf ( n3985 , n676 );
and ( n3986 , n3985 , n3583 );
not ( n3987 , n3777 );
and ( n3988 , n3987 , n3675 );
xor ( n3989 , n3851 , n3868 );
and ( n3990 , n3989 , n3777 );
or ( n3991 , n3988 , n3990 );
and ( n3992 , n3991 , n3493 );
or ( n3993 , n3986 , n3992 );
not ( n3994 , n3993 );
and ( n3995 , n2059 , n3994 );
buf ( n3996 , n677 );
and ( n3997 , n3996 , n3583 );
not ( n3998 , n3777 );
and ( n3999 , n3998 , n3665 );
xor ( n4000 , n3852 , n3867 );
and ( n4001 , n4000 , n3777 );
or ( n4002 , n3999 , n4001 );
and ( n4003 , n4002 , n3493 );
or ( n4004 , n3997 , n4003 );
not ( n4005 , n4004 );
and ( n4006 , n2035 , n4005 );
buf ( n4007 , n678 );
and ( n4008 , n4007 , n3583 );
not ( n4009 , n3777 );
and ( n4010 , n4009 , n3655 );
xor ( n4011 , n3853 , n3866 );
and ( n4012 , n4011 , n3777 );
or ( n4013 , n4010 , n4012 );
and ( n4014 , n4013 , n3493 );
or ( n4015 , n4008 , n4014 );
not ( n4016 , n4015 );
and ( n4017 , n2011 , n4016 );
buf ( n4018 , n679 );
and ( n4019 , n4018 , n3583 );
not ( n4020 , n3777 );
and ( n4021 , n4020 , n3645 );
xor ( n4022 , n3854 , n3865 );
and ( n4023 , n4022 , n3777 );
or ( n4024 , n4021 , n4023 );
and ( n4025 , n4024 , n3493 );
or ( n4026 , n4019 , n4025 );
not ( n4027 , n4026 );
and ( n4028 , n1987 , n4027 );
buf ( n4029 , n680 );
and ( n4030 , n4029 , n3583 );
not ( n4031 , n3777 );
and ( n4032 , n4031 , n3635 );
xor ( n4033 , n3855 , n3864 );
and ( n4034 , n4033 , n3777 );
or ( n4035 , n4032 , n4034 );
and ( n4036 , n4035 , n3493 );
or ( n4037 , n4030 , n4036 );
not ( n4038 , n4037 );
and ( n4039 , n1963 , n4038 );
buf ( n4040 , n681 );
and ( n4041 , n4040 , n3583 );
not ( n4042 , n3777 );
and ( n4043 , n4042 , n3625 );
xor ( n4044 , n3856 , n3863 );
and ( n4045 , n4044 , n3777 );
or ( n4046 , n4043 , n4045 );
and ( n4047 , n4046 , n3493 );
or ( n4048 , n4041 , n4047 );
not ( n4049 , n4048 );
and ( n4050 , n1939 , n4049 );
buf ( n4051 , n682 );
and ( n4052 , n4051 , n3583 );
not ( n4053 , n3777 );
and ( n4054 , n4053 , n3615 );
xor ( n4055 , n3857 , n3862 );
and ( n4056 , n4055 , n3777 );
or ( n4057 , n4054 , n4056 );
and ( n4058 , n4057 , n3493 );
or ( n4059 , n4052 , n4058 );
not ( n4060 , n4059 );
and ( n4061 , n1915 , n4060 );
buf ( n4062 , n683 );
and ( n4063 , n4062 , n3583 );
not ( n4064 , n3777 );
and ( n4065 , n4064 , n3605 );
xor ( n4066 , n3858 , n3861 );
and ( n4067 , n4066 , n3777 );
or ( n4068 , n4065 , n4067 );
and ( n4069 , n4068 , n3493 );
or ( n4070 , n4063 , n4069 );
not ( n4071 , n4070 );
and ( n4072 , n1891 , n4071 );
buf ( n4073 , n684 );
and ( n4074 , n4073 , n3583 );
not ( n4075 , n3777 );
and ( n4076 , n4075 , n3595 );
xor ( n4077 , n3859 , n3860 );
and ( n4078 , n4077 , n3777 );
or ( n4079 , n4076 , n4078 );
and ( n4080 , n4079 , n3493 );
or ( n4081 , n4074 , n4080 );
not ( n4082 , n4081 );
and ( n4083 , n1868 , n4082 );
not ( n4084 , n3785 );
or ( n4085 , n1850 , n4084 );
and ( n4086 , n4082 , n4085 );
and ( n4087 , n1868 , n4085 );
or ( n4088 , n4083 , n4086 , n4087 );
and ( n4089 , n4071 , n4088 );
and ( n4090 , n1891 , n4088 );
or ( n4091 , n4072 , n4089 , n4090 );
and ( n4092 , n4060 , n4091 );
and ( n4093 , n1915 , n4091 );
or ( n4094 , n4061 , n4092 , n4093 );
and ( n4095 , n4049 , n4094 );
and ( n4096 , n1939 , n4094 );
or ( n4097 , n4050 , n4095 , n4096 );
and ( n4098 , n4038 , n4097 );
and ( n4099 , n1963 , n4097 );
or ( n4100 , n4039 , n4098 , n4099 );
and ( n4101 , n4027 , n4100 );
and ( n4102 , n1987 , n4100 );
or ( n4103 , n4028 , n4101 , n4102 );
and ( n4104 , n4016 , n4103 );
and ( n4105 , n2011 , n4103 );
or ( n4106 , n4017 , n4104 , n4105 );
and ( n4107 , n4005 , n4106 );
and ( n4108 , n2035 , n4106 );
or ( n4109 , n4006 , n4107 , n4108 );
and ( n4110 , n3994 , n4109 );
and ( n4111 , n2059 , n4109 );
or ( n4112 , n3995 , n4110 , n4111 );
and ( n4113 , n3983 , n4112 );
and ( n4114 , n2083 , n4112 );
or ( n4115 , n3984 , n4113 , n4114 );
and ( n4116 , n3972 , n4115 );
and ( n4117 , n2107 , n4115 );
or ( n4118 , n3973 , n4116 , n4117 );
and ( n4119 , n3961 , n4118 );
and ( n4120 , n2131 , n4118 );
or ( n4121 , n3962 , n4119 , n4120 );
and ( n4122 , n3950 , n4121 );
and ( n4123 , n2155 , n4121 );
or ( n4124 , n3951 , n4122 , n4123 );
and ( n4125 , n3939 , n4124 );
and ( n4126 , n2179 , n4124 );
or ( n4127 , n3940 , n4125 , n4126 );
and ( n4128 , n3928 , n4127 );
and ( n4129 , n2203 , n4127 );
or ( n4130 , n3929 , n4128 , n4129 );
and ( n4131 , n3917 , n4130 );
and ( n4132 , n2227 , n4130 );
or ( n4133 , n3918 , n4131 , n4132 );
and ( n4134 , n3906 , n4133 );
and ( n4135 , n2251 , n4133 );
or ( n4136 , n3907 , n4134 , n4135 );
and ( n4137 , n3895 , n4136 );
and ( n4138 , n2275 , n4136 );
or ( n4139 , n3896 , n4137 , n4138 );
and ( n4140 , n3884 , n4139 );
and ( n4141 , n2299 , n4139 );
or ( n4142 , n3885 , n4140 , n4141 );
and ( n4143 , n3835 , n4142 );
and ( n4144 , n2323 , n4142 );
or ( n4145 , n3836 , n4143 , n4144 );
and ( n4146 , n3831 , n4145 );
and ( n4147 , n2347 , n4145 );
or ( n4148 , n3832 , n4146 , n4147 );
and ( n4149 , n3827 , n4148 );
and ( n4150 , n2371 , n4148 );
or ( n4151 , n3828 , n4149 , n4150 );
and ( n4152 , n3823 , n4151 );
and ( n4153 , n2395 , n4151 );
or ( n4154 , n3824 , n4152 , n4153 );
and ( n4155 , n3819 , n4154 );
and ( n4156 , n2419 , n4154 );
or ( n4157 , n3820 , n4155 , n4156 );
and ( n4158 , n3815 , n4157 );
and ( n4159 , n2443 , n4157 );
or ( n4160 , n3816 , n4158 , n4159 );
and ( n4161 , n3811 , n4160 );
and ( n4162 , n2467 , n4160 );
or ( n4163 , n3812 , n4161 , n4162 );
and ( n4164 , n3807 , n4163 );
and ( n4165 , n2491 , n4163 );
or ( n4166 , n3808 , n4164 , n4165 );
and ( n4167 , n3803 , n4166 );
and ( n4168 , n2515 , n4166 );
or ( n4169 , n3804 , n4167 , n4168 );
and ( n4170 , n3799 , n4169 );
and ( n4171 , n2728 , n4169 );
or ( n4172 , n3800 , n4170 , n4171 );
and ( n4173 , n3795 , n4172 );
and ( n4174 , n2717 , n4172 );
or ( n4175 , n3796 , n4173 , n4174 );
xor ( n4176 , n3792 , n4175 );
not ( n4177 , n4176 );
xor ( n4178 , n1868 , n4082 );
xor ( n4179 , n4178 , n4085 );
and ( n4180 , n4177 , n4179 );
not ( n4181 , n4179 );
not ( n4182 , n3786 );
xor ( n4183 , n4181 , n4182 );
and ( n4184 , n4183 , n4176 );
or ( n4185 , n4180 , n4184 );
not ( n4186 , n4185 );
not ( n4187 , n4186 );
or ( n4188 , n3788 , n4187 );
not ( n4189 , n4176 );
xor ( n4190 , n1891 , n4071 );
xor ( n4191 , n4190 , n4088 );
and ( n4192 , n4189 , n4191 );
not ( n4193 , n4191 );
and ( n4194 , n4181 , n4182 );
xor ( n4195 , n4193 , n4194 );
and ( n4196 , n4195 , n4176 );
or ( n4197 , n4192 , n4196 );
not ( n4198 , n4197 );
not ( n4199 , n4198 );
or ( n4200 , n4188 , n4199 );
not ( n4201 , n4176 );
xor ( n4202 , n1915 , n4060 );
xor ( n4203 , n4202 , n4091 );
and ( n4204 , n4201 , n4203 );
not ( n4205 , n4203 );
and ( n4206 , n4193 , n4194 );
xor ( n4207 , n4205 , n4206 );
and ( n4208 , n4207 , n4176 );
or ( n4209 , n4204 , n4208 );
not ( n4210 , n4209 );
not ( n4211 , n4210 );
or ( n4212 , n4200 , n4211 );
not ( n4213 , n4176 );
xor ( n4214 , n1939 , n4049 );
xor ( n4215 , n4214 , n4094 );
and ( n4216 , n4213 , n4215 );
not ( n4217 , n4215 );
and ( n4218 , n4205 , n4206 );
xor ( n4219 , n4217 , n4218 );
and ( n4220 , n4219 , n4176 );
or ( n4221 , n4216 , n4220 );
not ( n4222 , n4221 );
not ( n4223 , n4222 );
or ( n4224 , n4212 , n4223 );
not ( n4225 , n4176 );
xor ( n4226 , n1963 , n4038 );
xor ( n4227 , n4226 , n4097 );
and ( n4228 , n4225 , n4227 );
not ( n4229 , n4227 );
and ( n4230 , n4217 , n4218 );
xor ( n4231 , n4229 , n4230 );
and ( n4232 , n4231 , n4176 );
or ( n4233 , n4228 , n4232 );
not ( n4234 , n4233 );
not ( n4235 , n4234 );
or ( n4236 , n4224 , n4235 );
not ( n4237 , n4176 );
xor ( n4238 , n1987 , n4027 );
xor ( n4239 , n4238 , n4100 );
and ( n4240 , n4237 , n4239 );
not ( n4241 , n4239 );
and ( n4242 , n4229 , n4230 );
xor ( n4243 , n4241 , n4242 );
and ( n4244 , n4243 , n4176 );
or ( n4245 , n4240 , n4244 );
not ( n4246 , n4245 );
not ( n4247 , n4246 );
or ( n4248 , n4236 , n4247 );
not ( n4249 , n4176 );
xor ( n4250 , n2011 , n4016 );
xor ( n4251 , n4250 , n4103 );
and ( n4252 , n4249 , n4251 );
not ( n4253 , n4251 );
and ( n4254 , n4241 , n4242 );
xor ( n4255 , n4253 , n4254 );
and ( n4256 , n4255 , n4176 );
or ( n4257 , n4252 , n4256 );
not ( n4258 , n4257 );
not ( n4259 , n4258 );
or ( n4260 , n4248 , n4259 );
not ( n4261 , n4176 );
xor ( n4262 , n2035 , n4005 );
xor ( n4263 , n4262 , n4106 );
and ( n4264 , n4261 , n4263 );
not ( n4265 , n4263 );
and ( n4266 , n4253 , n4254 );
xor ( n4267 , n4265 , n4266 );
and ( n4268 , n4267 , n4176 );
or ( n4269 , n4264 , n4268 );
not ( n4270 , n4269 );
not ( n4271 , n4270 );
or ( n4272 , n4260 , n4271 );
not ( n4273 , n4176 );
xor ( n4274 , n2059 , n3994 );
xor ( n4275 , n4274 , n4109 );
and ( n4276 , n4273 , n4275 );
not ( n4277 , n4275 );
and ( n4278 , n4265 , n4266 );
xor ( n4279 , n4277 , n4278 );
and ( n4280 , n4279 , n4176 );
or ( n4281 , n4276 , n4280 );
not ( n4282 , n4281 );
not ( n4283 , n4282 );
or ( n4284 , n4272 , n4283 );
not ( n4285 , n4176 );
xor ( n4286 , n2083 , n3983 );
xor ( n4287 , n4286 , n4112 );
and ( n4288 , n4285 , n4287 );
not ( n4289 , n4287 );
and ( n4290 , n4277 , n4278 );
xor ( n4291 , n4289 , n4290 );
and ( n4292 , n4291 , n4176 );
or ( n4293 , n4288 , n4292 );
not ( n4294 , n4293 );
not ( n4295 , n4294 );
or ( n4296 , n4284 , n4295 );
not ( n4297 , n4176 );
xor ( n4298 , n2107 , n3972 );
xor ( n4299 , n4298 , n4115 );
and ( n4300 , n4297 , n4299 );
not ( n4301 , n4299 );
and ( n4302 , n4289 , n4290 );
xor ( n4303 , n4301 , n4302 );
and ( n4304 , n4303 , n4176 );
or ( n4305 , n4300 , n4304 );
not ( n4306 , n4305 );
not ( n4307 , n4306 );
or ( n4308 , n4296 , n4307 );
not ( n4309 , n4176 );
xor ( n4310 , n2131 , n3961 );
xor ( n4311 , n4310 , n4118 );
and ( n4312 , n4309 , n4311 );
not ( n4313 , n4311 );
and ( n4314 , n4301 , n4302 );
xor ( n4315 , n4313 , n4314 );
and ( n4316 , n4315 , n4176 );
or ( n4317 , n4312 , n4316 );
not ( n4318 , n4317 );
not ( n4319 , n4318 );
or ( n4320 , n4308 , n4319 );
not ( n4321 , n4176 );
xor ( n4322 , n2155 , n3950 );
xor ( n4323 , n4322 , n4121 );
and ( n4324 , n4321 , n4323 );
not ( n4325 , n4323 );
and ( n4326 , n4313 , n4314 );
xor ( n4327 , n4325 , n4326 );
and ( n4328 , n4327 , n4176 );
or ( n4329 , n4324 , n4328 );
not ( n4330 , n4329 );
not ( n4331 , n4330 );
or ( n4332 , n4320 , n4331 );
not ( n4333 , n4176 );
xor ( n4334 , n2179 , n3939 );
xor ( n4335 , n4334 , n4124 );
and ( n4336 , n4333 , n4335 );
not ( n4337 , n4335 );
and ( n4338 , n4325 , n4326 );
xor ( n4339 , n4337 , n4338 );
and ( n4340 , n4339 , n4176 );
or ( n4341 , n4336 , n4340 );
not ( n4342 , n4341 );
not ( n4343 , n4342 );
or ( n4344 , n4332 , n4343 );
not ( n4345 , n4176 );
xor ( n4346 , n2203 , n3928 );
xor ( n4347 , n4346 , n4127 );
and ( n4348 , n4345 , n4347 );
not ( n4349 , n4347 );
and ( n4350 , n4337 , n4338 );
xor ( n4351 , n4349 , n4350 );
and ( n4352 , n4351 , n4176 );
or ( n4353 , n4348 , n4352 );
not ( n4354 , n4353 );
not ( n4355 , n4354 );
or ( n4356 , n4344 , n4355 );
not ( n4357 , n4176 );
xor ( n4358 , n2227 , n3917 );
xor ( n4359 , n4358 , n4130 );
and ( n4360 , n4357 , n4359 );
not ( n4361 , n4359 );
and ( n4362 , n4349 , n4350 );
xor ( n4363 , n4361 , n4362 );
and ( n4364 , n4363 , n4176 );
or ( n4365 , n4360 , n4364 );
not ( n4366 , n4365 );
not ( n4367 , n4366 );
or ( n4368 , n4356 , n4367 );
not ( n4369 , n4176 );
xor ( n4370 , n2251 , n3906 );
xor ( n4371 , n4370 , n4133 );
and ( n4372 , n4369 , n4371 );
not ( n4373 , n4371 );
and ( n4374 , n4361 , n4362 );
xor ( n4375 , n4373 , n4374 );
and ( n4376 , n4375 , n4176 );
or ( n4377 , n4372 , n4376 );
not ( n4378 , n4377 );
not ( n4379 , n4378 );
or ( n4380 , n4368 , n4379 );
not ( n4381 , n4176 );
xor ( n4382 , n2275 , n3895 );
xor ( n4383 , n4382 , n4136 );
and ( n4384 , n4381 , n4383 );
not ( n4385 , n4383 );
and ( n4386 , n4373 , n4374 );
xor ( n4387 , n4385 , n4386 );
and ( n4388 , n4387 , n4176 );
or ( n4389 , n4384 , n4388 );
not ( n4390 , n4389 );
not ( n4391 , n4390 );
or ( n4392 , n4380 , n4391 );
not ( n4393 , n4176 );
xor ( n4394 , n2299 , n3884 );
xor ( n4395 , n4394 , n4139 );
and ( n4396 , n4393 , n4395 );
not ( n4397 , n4395 );
and ( n4398 , n4385 , n4386 );
xor ( n4399 , n4397 , n4398 );
and ( n4400 , n4399 , n4176 );
or ( n4401 , n4396 , n4400 );
not ( n4402 , n4401 );
not ( n4403 , n4402 );
or ( n4404 , n4392 , n4403 );
not ( n4405 , n4176 );
xor ( n4406 , n2323 , n3835 );
xor ( n4407 , n4406 , n4142 );
and ( n4408 , n4405 , n4407 );
not ( n4409 , n4407 );
and ( n4410 , n4397 , n4398 );
xor ( n4411 , n4409 , n4410 );
and ( n4412 , n4411 , n4176 );
or ( n4413 , n4408 , n4412 );
not ( n4414 , n4413 );
not ( n4415 , n4414 );
or ( n4416 , n4404 , n4415 );
not ( n4417 , n4176 );
xor ( n4418 , n2347 , n3831 );
xor ( n4419 , n4418 , n4145 );
and ( n4420 , n4417 , n4419 );
not ( n4421 , n4419 );
and ( n4422 , n4409 , n4410 );
xor ( n4423 , n4421 , n4422 );
and ( n4424 , n4423 , n4176 );
or ( n4425 , n4420 , n4424 );
not ( n4426 , n4425 );
not ( n4427 , n4426 );
or ( n4428 , n4416 , n4427 );
not ( n4429 , n4176 );
xor ( n4430 , n2371 , n3827 );
xor ( n4431 , n4430 , n4148 );
and ( n4432 , n4429 , n4431 );
not ( n4433 , n4431 );
and ( n4434 , n4421 , n4422 );
xor ( n4435 , n4433 , n4434 );
and ( n4436 , n4435 , n4176 );
or ( n4437 , n4432 , n4436 );
not ( n4438 , n4437 );
not ( n4439 , n4438 );
or ( n4440 , n4428 , n4439 );
not ( n4441 , n4176 );
xor ( n4442 , n2395 , n3823 );
xor ( n4443 , n4442 , n4151 );
and ( n4444 , n4441 , n4443 );
not ( n4445 , n4443 );
and ( n4446 , n4433 , n4434 );
xor ( n4447 , n4445 , n4446 );
and ( n4448 , n4447 , n4176 );
or ( n4449 , n4444 , n4448 );
not ( n4450 , n4449 );
not ( n4451 , n4450 );
or ( n4452 , n4440 , n4451 );
not ( n4453 , n4176 );
xor ( n4454 , n2419 , n3819 );
xor ( n4455 , n4454 , n4154 );
and ( n4456 , n4453 , n4455 );
not ( n4457 , n4455 );
and ( n4458 , n4445 , n4446 );
xor ( n4459 , n4457 , n4458 );
and ( n4460 , n4459 , n4176 );
or ( n4461 , n4456 , n4460 );
not ( n4462 , n4461 );
not ( n4463 , n4462 );
or ( n4464 , n4452 , n4463 );
not ( n4465 , n4176 );
xor ( n4466 , n2443 , n3815 );
xor ( n4467 , n4466 , n4157 );
and ( n4468 , n4465 , n4467 );
not ( n4469 , n4467 );
and ( n4470 , n4457 , n4458 );
xor ( n4471 , n4469 , n4470 );
and ( n4472 , n4471 , n4176 );
or ( n4473 , n4468 , n4472 );
not ( n4474 , n4473 );
not ( n4475 , n4474 );
or ( n4476 , n4464 , n4475 );
not ( n4477 , n4176 );
xor ( n4478 , n2467 , n3811 );
xor ( n4479 , n4478 , n4160 );
and ( n4480 , n4477 , n4479 );
not ( n4481 , n4479 );
and ( n4482 , n4469 , n4470 );
xor ( n4483 , n4481 , n4482 );
and ( n4484 , n4483 , n4176 );
or ( n4485 , n4480 , n4484 );
not ( n4486 , n4485 );
not ( n4487 , n4486 );
or ( n4488 , n4476 , n4487 );
not ( n4489 , n4176 );
xor ( n4490 , n2491 , n3807 );
xor ( n4491 , n4490 , n4163 );
and ( n4492 , n4489 , n4491 );
not ( n4493 , n4491 );
and ( n4494 , n4481 , n4482 );
xor ( n4495 , n4493 , n4494 );
and ( n4496 , n4495 , n4176 );
or ( n4497 , n4492 , n4496 );
not ( n4498 , n4497 );
not ( n4499 , n4498 );
or ( n4500 , n4488 , n4499 );
not ( n4501 , n4176 );
xor ( n4502 , n2515 , n3803 );
xor ( n4503 , n4502 , n4166 );
and ( n4504 , n4501 , n4503 );
not ( n4505 , n4503 );
and ( n4506 , n4493 , n4494 );
xor ( n4507 , n4505 , n4506 );
and ( n4508 , n4507 , n4176 );
or ( n4509 , n4504 , n4508 );
not ( n4510 , n4509 );
not ( n4511 , n4510 );
or ( n4512 , n4500 , n4511 );
not ( n4513 , n4176 );
xor ( n4514 , n2728 , n3799 );
xor ( n4515 , n4514 , n4169 );
and ( n4516 , n4513 , n4515 );
not ( n4517 , n4515 );
and ( n4518 , n4505 , n4506 );
xor ( n4519 , n4517 , n4518 );
and ( n4520 , n4519 , n4176 );
or ( n4521 , n4516 , n4520 );
not ( n4522 , n4521 );
not ( n4523 , n4522 );
or ( n4524 , n4512 , n4523 );
and ( n4525 , n4524 , n4176 );
not ( n4526 , n4525 );
and ( n4527 , n4526 , n4187 );
xor ( n4528 , n4187 , n4176 );
xor ( n4529 , n3788 , n4176 );
and ( n4530 , n4529 , n4176 );
xor ( n4531 , n4528 , n4530 );
and ( n4532 , n4531 , n4525 );
or ( n4533 , n4527 , n4532 );
and ( n4534 , n4533 , n3569 );
and ( n4535 , n1447 , n3576 );
or ( n4536 , n4534 , n4535 );
not ( n4537 , n1705 );
and ( n4538 , n1707 , n1690 , n1698 , n4537 );
and ( n4539 , n1683 , n1690 , n1698 , n4537 );
or ( n4540 , n4538 , n4539 );
nor ( n4541 , n1707 , n1690 , n1698 , n4537 );
or ( n4542 , n4540 , n4541 );
nor ( n4543 , n1707 , n1691 , n1698 , n4537 );
or ( n4544 , n4542 , n4543 );
and ( n4545 , n4536 , n4544 );
xor ( n4546 , n1850 , n3785 );
not ( n4547 , n4546 );
not ( n4548 , n4547 );
xor ( n4549 , n1859 , n3790 );
and ( n4550 , n2717 , n3794 );
and ( n4551 , n2728 , n3798 );
and ( n4552 , n2515 , n3802 );
and ( n4553 , n2491 , n3806 );
and ( n4554 , n2467 , n3810 );
and ( n4555 , n2443 , n3814 );
and ( n4556 , n2419 , n3818 );
and ( n4557 , n2395 , n3822 );
and ( n4558 , n2371 , n3826 );
and ( n4559 , n2347 , n3830 );
and ( n4560 , n2323 , n3834 );
and ( n4561 , n2299 , n3883 );
and ( n4562 , n2275 , n3894 );
and ( n4563 , n2251 , n3905 );
and ( n4564 , n2227 , n3916 );
and ( n4565 , n2203 , n3927 );
and ( n4566 , n2179 , n3938 );
and ( n4567 , n2155 , n3949 );
and ( n4568 , n2131 , n3960 );
and ( n4569 , n2107 , n3971 );
and ( n4570 , n2083 , n3982 );
and ( n4571 , n2059 , n3993 );
and ( n4572 , n2035 , n4004 );
and ( n4573 , n2011 , n4015 );
and ( n4574 , n1987 , n4026 );
and ( n4575 , n1963 , n4037 );
and ( n4576 , n1939 , n4048 );
and ( n4577 , n1915 , n4059 );
and ( n4578 , n1891 , n4070 );
and ( n4579 , n1868 , n4081 );
and ( n4580 , n1850 , n3785 );
and ( n4581 , n4081 , n4580 );
and ( n4582 , n1868 , n4580 );
or ( n4583 , n4579 , n4581 , n4582 );
and ( n4584 , n4070 , n4583 );
and ( n4585 , n1891 , n4583 );
or ( n4586 , n4578 , n4584 , n4585 );
and ( n4587 , n4059 , n4586 );
and ( n4588 , n1915 , n4586 );
or ( n4589 , n4577 , n4587 , n4588 );
and ( n4590 , n4048 , n4589 );
and ( n4591 , n1939 , n4589 );
or ( n4592 , n4576 , n4590 , n4591 );
and ( n4593 , n4037 , n4592 );
and ( n4594 , n1963 , n4592 );
or ( n4595 , n4575 , n4593 , n4594 );
and ( n4596 , n4026 , n4595 );
and ( n4597 , n1987 , n4595 );
or ( n4598 , n4574 , n4596 , n4597 );
and ( n4599 , n4015 , n4598 );
and ( n4600 , n2011 , n4598 );
or ( n4601 , n4573 , n4599 , n4600 );
and ( n4602 , n4004 , n4601 );
and ( n4603 , n2035 , n4601 );
or ( n4604 , n4572 , n4602 , n4603 );
and ( n4605 , n3993 , n4604 );
and ( n4606 , n2059 , n4604 );
or ( n4607 , n4571 , n4605 , n4606 );
and ( n4608 , n3982 , n4607 );
and ( n4609 , n2083 , n4607 );
or ( n4610 , n4570 , n4608 , n4609 );
and ( n4611 , n3971 , n4610 );
and ( n4612 , n2107 , n4610 );
or ( n4613 , n4569 , n4611 , n4612 );
and ( n4614 , n3960 , n4613 );
and ( n4615 , n2131 , n4613 );
or ( n4616 , n4568 , n4614 , n4615 );
and ( n4617 , n3949 , n4616 );
and ( n4618 , n2155 , n4616 );
or ( n4619 , n4567 , n4617 , n4618 );
and ( n4620 , n3938 , n4619 );
and ( n4621 , n2179 , n4619 );
or ( n4622 , n4566 , n4620 , n4621 );
and ( n4623 , n3927 , n4622 );
and ( n4624 , n2203 , n4622 );
or ( n4625 , n4565 , n4623 , n4624 );
and ( n4626 , n3916 , n4625 );
and ( n4627 , n2227 , n4625 );
or ( n4628 , n4564 , n4626 , n4627 );
and ( n4629 , n3905 , n4628 );
and ( n4630 , n2251 , n4628 );
or ( n4631 , n4563 , n4629 , n4630 );
and ( n4632 , n3894 , n4631 );
and ( n4633 , n2275 , n4631 );
or ( n4634 , n4562 , n4632 , n4633 );
and ( n4635 , n3883 , n4634 );
and ( n4636 , n2299 , n4634 );
or ( n4637 , n4561 , n4635 , n4636 );
and ( n4638 , n3834 , n4637 );
and ( n4639 , n2323 , n4637 );
or ( n4640 , n4560 , n4638 , n4639 );
and ( n4641 , n3830 , n4640 );
and ( n4642 , n2347 , n4640 );
or ( n4643 , n4559 , n4641 , n4642 );
and ( n4644 , n3826 , n4643 );
and ( n4645 , n2371 , n4643 );
or ( n4646 , n4558 , n4644 , n4645 );
and ( n4647 , n3822 , n4646 );
and ( n4648 , n2395 , n4646 );
or ( n4649 , n4557 , n4647 , n4648 );
and ( n4650 , n3818 , n4649 );
and ( n4651 , n2419 , n4649 );
or ( n4652 , n4556 , n4650 , n4651 );
and ( n4653 , n3814 , n4652 );
and ( n4654 , n2443 , n4652 );
or ( n4655 , n4555 , n4653 , n4654 );
and ( n4656 , n3810 , n4655 );
and ( n4657 , n2467 , n4655 );
or ( n4658 , n4554 , n4656 , n4657 );
and ( n4659 , n3806 , n4658 );
and ( n4660 , n2491 , n4658 );
or ( n4661 , n4553 , n4659 , n4660 );
and ( n4662 , n3802 , n4661 );
and ( n4663 , n2515 , n4661 );
or ( n4664 , n4552 , n4662 , n4663 );
and ( n4665 , n3798 , n4664 );
and ( n4666 , n2728 , n4664 );
or ( n4667 , n4551 , n4665 , n4666 );
and ( n4668 , n3794 , n4667 );
and ( n4669 , n2717 , n4667 );
or ( n4670 , n4550 , n4668 , n4669 );
xor ( n4671 , n4549 , n4670 );
not ( n4672 , n4671 );
xor ( n4673 , n1868 , n4081 );
xor ( n4674 , n4673 , n4580 );
and ( n4675 , n4672 , n4674 );
not ( n4676 , n4674 );
not ( n4677 , n4546 );
xor ( n4678 , n4676 , n4677 );
and ( n4679 , n4678 , n4671 );
or ( n4680 , n4675 , n4679 );
not ( n4681 , n4680 );
not ( n4682 , n4681 );
or ( n4683 , n4548 , n4682 );
not ( n4684 , n4671 );
xor ( n4685 , n1891 , n4070 );
xor ( n4686 , n4685 , n4583 );
and ( n4687 , n4684 , n4686 );
not ( n4688 , n4686 );
and ( n4689 , n4676 , n4677 );
xor ( n4690 , n4688 , n4689 );
and ( n4691 , n4690 , n4671 );
or ( n4692 , n4687 , n4691 );
not ( n4693 , n4692 );
not ( n4694 , n4693 );
or ( n4695 , n4683 , n4694 );
not ( n4696 , n4671 );
xor ( n4697 , n1915 , n4059 );
xor ( n4698 , n4697 , n4586 );
and ( n4699 , n4696 , n4698 );
not ( n4700 , n4698 );
and ( n4701 , n4688 , n4689 );
xor ( n4702 , n4700 , n4701 );
and ( n4703 , n4702 , n4671 );
or ( n4704 , n4699 , n4703 );
not ( n4705 , n4704 );
not ( n4706 , n4705 );
or ( n4707 , n4695 , n4706 );
not ( n4708 , n4671 );
xor ( n4709 , n1939 , n4048 );
xor ( n4710 , n4709 , n4589 );
and ( n4711 , n4708 , n4710 );
not ( n4712 , n4710 );
and ( n4713 , n4700 , n4701 );
xor ( n4714 , n4712 , n4713 );
and ( n4715 , n4714 , n4671 );
or ( n4716 , n4711 , n4715 );
not ( n4717 , n4716 );
not ( n4718 , n4717 );
or ( n4719 , n4707 , n4718 );
not ( n4720 , n4671 );
xor ( n4721 , n1963 , n4037 );
xor ( n4722 , n4721 , n4592 );
and ( n4723 , n4720 , n4722 );
not ( n4724 , n4722 );
and ( n4725 , n4712 , n4713 );
xor ( n4726 , n4724 , n4725 );
and ( n4727 , n4726 , n4671 );
or ( n4728 , n4723 , n4727 );
not ( n4729 , n4728 );
not ( n4730 , n4729 );
or ( n4731 , n4719 , n4730 );
not ( n4732 , n4671 );
xor ( n4733 , n1987 , n4026 );
xor ( n4734 , n4733 , n4595 );
and ( n4735 , n4732 , n4734 );
not ( n4736 , n4734 );
and ( n4737 , n4724 , n4725 );
xor ( n4738 , n4736 , n4737 );
and ( n4739 , n4738 , n4671 );
or ( n4740 , n4735 , n4739 );
not ( n4741 , n4740 );
not ( n4742 , n4741 );
or ( n4743 , n4731 , n4742 );
not ( n4744 , n4671 );
xor ( n4745 , n2011 , n4015 );
xor ( n4746 , n4745 , n4598 );
and ( n4747 , n4744 , n4746 );
not ( n4748 , n4746 );
and ( n4749 , n4736 , n4737 );
xor ( n4750 , n4748 , n4749 );
and ( n4751 , n4750 , n4671 );
or ( n4752 , n4747 , n4751 );
not ( n4753 , n4752 );
not ( n4754 , n4753 );
or ( n4755 , n4743 , n4754 );
not ( n4756 , n4671 );
xor ( n4757 , n2035 , n4004 );
xor ( n4758 , n4757 , n4601 );
and ( n4759 , n4756 , n4758 );
not ( n4760 , n4758 );
and ( n4761 , n4748 , n4749 );
xor ( n4762 , n4760 , n4761 );
and ( n4763 , n4762 , n4671 );
or ( n4764 , n4759 , n4763 );
not ( n4765 , n4764 );
not ( n4766 , n4765 );
or ( n4767 , n4755 , n4766 );
not ( n4768 , n4671 );
xor ( n4769 , n2059 , n3993 );
xor ( n4770 , n4769 , n4604 );
and ( n4771 , n4768 , n4770 );
not ( n4772 , n4770 );
and ( n4773 , n4760 , n4761 );
xor ( n4774 , n4772 , n4773 );
and ( n4775 , n4774 , n4671 );
or ( n4776 , n4771 , n4775 );
not ( n4777 , n4776 );
not ( n4778 , n4777 );
or ( n4779 , n4767 , n4778 );
not ( n4780 , n4671 );
xor ( n4781 , n2083 , n3982 );
xor ( n4782 , n4781 , n4607 );
and ( n4783 , n4780 , n4782 );
not ( n4784 , n4782 );
and ( n4785 , n4772 , n4773 );
xor ( n4786 , n4784 , n4785 );
and ( n4787 , n4786 , n4671 );
or ( n4788 , n4783 , n4787 );
not ( n4789 , n4788 );
not ( n4790 , n4789 );
or ( n4791 , n4779 , n4790 );
not ( n4792 , n4671 );
xor ( n4793 , n2107 , n3971 );
xor ( n4794 , n4793 , n4610 );
and ( n4795 , n4792 , n4794 );
not ( n4796 , n4794 );
and ( n4797 , n4784 , n4785 );
xor ( n4798 , n4796 , n4797 );
and ( n4799 , n4798 , n4671 );
or ( n4800 , n4795 , n4799 );
not ( n4801 , n4800 );
not ( n4802 , n4801 );
or ( n4803 , n4791 , n4802 );
not ( n4804 , n4671 );
xor ( n4805 , n2131 , n3960 );
xor ( n4806 , n4805 , n4613 );
and ( n4807 , n4804 , n4806 );
not ( n4808 , n4806 );
and ( n4809 , n4796 , n4797 );
xor ( n4810 , n4808 , n4809 );
and ( n4811 , n4810 , n4671 );
or ( n4812 , n4807 , n4811 );
not ( n4813 , n4812 );
not ( n4814 , n4813 );
or ( n4815 , n4803 , n4814 );
not ( n4816 , n4671 );
xor ( n4817 , n2155 , n3949 );
xor ( n4818 , n4817 , n4616 );
and ( n4819 , n4816 , n4818 );
not ( n4820 , n4818 );
and ( n4821 , n4808 , n4809 );
xor ( n4822 , n4820 , n4821 );
and ( n4823 , n4822 , n4671 );
or ( n4824 , n4819 , n4823 );
not ( n4825 , n4824 );
not ( n4826 , n4825 );
or ( n4827 , n4815 , n4826 );
not ( n4828 , n4671 );
xor ( n4829 , n2179 , n3938 );
xor ( n4830 , n4829 , n4619 );
and ( n4831 , n4828 , n4830 );
not ( n4832 , n4830 );
and ( n4833 , n4820 , n4821 );
xor ( n4834 , n4832 , n4833 );
and ( n4835 , n4834 , n4671 );
or ( n4836 , n4831 , n4835 );
not ( n4837 , n4836 );
not ( n4838 , n4837 );
or ( n4839 , n4827 , n4838 );
not ( n4840 , n4671 );
xor ( n4841 , n2203 , n3927 );
xor ( n4842 , n4841 , n4622 );
and ( n4843 , n4840 , n4842 );
not ( n4844 , n4842 );
and ( n4845 , n4832 , n4833 );
xor ( n4846 , n4844 , n4845 );
and ( n4847 , n4846 , n4671 );
or ( n4848 , n4843 , n4847 );
not ( n4849 , n4848 );
not ( n4850 , n4849 );
or ( n4851 , n4839 , n4850 );
not ( n4852 , n4671 );
xor ( n4853 , n2227 , n3916 );
xor ( n4854 , n4853 , n4625 );
and ( n4855 , n4852 , n4854 );
not ( n4856 , n4854 );
and ( n4857 , n4844 , n4845 );
xor ( n4858 , n4856 , n4857 );
and ( n4859 , n4858 , n4671 );
or ( n4860 , n4855 , n4859 );
not ( n4861 , n4860 );
not ( n4862 , n4861 );
or ( n4863 , n4851 , n4862 );
not ( n4864 , n4671 );
xor ( n4865 , n2251 , n3905 );
xor ( n4866 , n4865 , n4628 );
and ( n4867 , n4864 , n4866 );
not ( n4868 , n4866 );
and ( n4869 , n4856 , n4857 );
xor ( n4870 , n4868 , n4869 );
and ( n4871 , n4870 , n4671 );
or ( n4872 , n4867 , n4871 );
not ( n4873 , n4872 );
not ( n4874 , n4873 );
or ( n4875 , n4863 , n4874 );
not ( n4876 , n4671 );
xor ( n4877 , n2275 , n3894 );
xor ( n4878 , n4877 , n4631 );
and ( n4879 , n4876 , n4878 );
not ( n4880 , n4878 );
and ( n4881 , n4868 , n4869 );
xor ( n4882 , n4880 , n4881 );
and ( n4883 , n4882 , n4671 );
or ( n4884 , n4879 , n4883 );
not ( n4885 , n4884 );
not ( n4886 , n4885 );
or ( n4887 , n4875 , n4886 );
not ( n4888 , n4671 );
xor ( n4889 , n2299 , n3883 );
xor ( n4890 , n4889 , n4634 );
and ( n4891 , n4888 , n4890 );
not ( n4892 , n4890 );
and ( n4893 , n4880 , n4881 );
xor ( n4894 , n4892 , n4893 );
and ( n4895 , n4894 , n4671 );
or ( n4896 , n4891 , n4895 );
not ( n4897 , n4896 );
not ( n4898 , n4897 );
or ( n4899 , n4887 , n4898 );
not ( n4900 , n4671 );
xor ( n4901 , n2323 , n3834 );
xor ( n4902 , n4901 , n4637 );
and ( n4903 , n4900 , n4902 );
not ( n4904 , n4902 );
and ( n4905 , n4892 , n4893 );
xor ( n4906 , n4904 , n4905 );
and ( n4907 , n4906 , n4671 );
or ( n4908 , n4903 , n4907 );
not ( n4909 , n4908 );
not ( n4910 , n4909 );
or ( n4911 , n4899 , n4910 );
not ( n4912 , n4671 );
xor ( n4913 , n2347 , n3830 );
xor ( n4914 , n4913 , n4640 );
and ( n4915 , n4912 , n4914 );
not ( n4916 , n4914 );
and ( n4917 , n4904 , n4905 );
xor ( n4918 , n4916 , n4917 );
and ( n4919 , n4918 , n4671 );
or ( n4920 , n4915 , n4919 );
not ( n4921 , n4920 );
not ( n4922 , n4921 );
or ( n4923 , n4911 , n4922 );
not ( n4924 , n4671 );
xor ( n4925 , n2371 , n3826 );
xor ( n4926 , n4925 , n4643 );
and ( n4927 , n4924 , n4926 );
not ( n4928 , n4926 );
and ( n4929 , n4916 , n4917 );
xor ( n4930 , n4928 , n4929 );
and ( n4931 , n4930 , n4671 );
or ( n4932 , n4927 , n4931 );
not ( n4933 , n4932 );
not ( n4934 , n4933 );
or ( n4935 , n4923 , n4934 );
not ( n4936 , n4671 );
xor ( n4937 , n2395 , n3822 );
xor ( n4938 , n4937 , n4646 );
and ( n4939 , n4936 , n4938 );
not ( n4940 , n4938 );
and ( n4941 , n4928 , n4929 );
xor ( n4942 , n4940 , n4941 );
and ( n4943 , n4942 , n4671 );
or ( n4944 , n4939 , n4943 );
not ( n4945 , n4944 );
not ( n4946 , n4945 );
or ( n4947 , n4935 , n4946 );
not ( n4948 , n4671 );
xor ( n4949 , n2419 , n3818 );
xor ( n4950 , n4949 , n4649 );
and ( n4951 , n4948 , n4950 );
not ( n4952 , n4950 );
and ( n4953 , n4940 , n4941 );
xor ( n4954 , n4952 , n4953 );
and ( n4955 , n4954 , n4671 );
or ( n4956 , n4951 , n4955 );
not ( n4957 , n4956 );
not ( n4958 , n4957 );
or ( n4959 , n4947 , n4958 );
not ( n4960 , n4671 );
xor ( n4961 , n2443 , n3814 );
xor ( n4962 , n4961 , n4652 );
and ( n4963 , n4960 , n4962 );
not ( n4964 , n4962 );
and ( n4965 , n4952 , n4953 );
xor ( n4966 , n4964 , n4965 );
and ( n4967 , n4966 , n4671 );
or ( n4968 , n4963 , n4967 );
not ( n4969 , n4968 );
not ( n4970 , n4969 );
or ( n4971 , n4959 , n4970 );
not ( n4972 , n4671 );
xor ( n4973 , n2467 , n3810 );
xor ( n4974 , n4973 , n4655 );
and ( n4975 , n4972 , n4974 );
not ( n4976 , n4974 );
and ( n4977 , n4964 , n4965 );
xor ( n4978 , n4976 , n4977 );
and ( n4979 , n4978 , n4671 );
or ( n4980 , n4975 , n4979 );
not ( n4981 , n4980 );
not ( n4982 , n4981 );
or ( n4983 , n4971 , n4982 );
not ( n4984 , n4671 );
xor ( n4985 , n2491 , n3806 );
xor ( n4986 , n4985 , n4658 );
and ( n4987 , n4984 , n4986 );
not ( n4988 , n4986 );
and ( n4989 , n4976 , n4977 );
xor ( n4990 , n4988 , n4989 );
and ( n4991 , n4990 , n4671 );
or ( n4992 , n4987 , n4991 );
not ( n4993 , n4992 );
not ( n4994 , n4993 );
or ( n4995 , n4983 , n4994 );
not ( n4996 , n4671 );
xor ( n4997 , n2515 , n3802 );
xor ( n4998 , n4997 , n4661 );
and ( n4999 , n4996 , n4998 );
not ( n5000 , n4998 );
and ( n5001 , n4988 , n4989 );
xor ( n5002 , n5000 , n5001 );
and ( n5003 , n5002 , n4671 );
or ( n5004 , n4999 , n5003 );
not ( n5005 , n5004 );
not ( n5006 , n5005 );
or ( n5007 , n4995 , n5006 );
not ( n5008 , n4671 );
xor ( n5009 , n2728 , n3798 );
xor ( n5010 , n5009 , n4664 );
and ( n5011 , n5008 , n5010 );
not ( n5012 , n5010 );
and ( n5013 , n5000 , n5001 );
xor ( n5014 , n5012 , n5013 );
and ( n5015 , n5014 , n4671 );
or ( n5016 , n5011 , n5015 );
not ( n5017 , n5016 );
not ( n5018 , n5017 );
or ( n5019 , n5007 , n5018 );
and ( n5020 , n5019 , n4671 );
not ( n5021 , n5020 );
and ( n5022 , n5021 , n4682 );
xor ( n5023 , n4682 , n4671 );
xor ( n5024 , n4548 , n4671 );
and ( n5025 , n5024 , n4671 );
xor ( n5026 , n5023 , n5025 );
and ( n5027 , n5026 , n5020 );
or ( n5028 , n5022 , n5027 );
and ( n5029 , n5028 , n3569 );
and ( n5030 , n1447 , n3576 );
or ( n5031 , n5029 , n5030 );
and ( n5032 , n1707 , n1691 , n1698 , n4537 );
and ( n5033 , n1683 , n1691 , n1698 , n4537 );
or ( n5034 , n5032 , n5033 );
nor ( n5035 , n1683 , n1690 , n1698 , n4537 );
or ( n5036 , n5034 , n5035 );
nor ( n5037 , n1683 , n1691 , n1698 , n4537 );
or ( n5038 , n5036 , n5037 );
and ( n5039 , n5031 , n5038 );
and ( n5040 , n4081 , n3569 );
and ( n5041 , n1447 , n3576 );
or ( n5042 , n5040 , n5041 );
nor ( n5043 , n1683 , n1691 , n1698 , n1705 );
nor ( n5044 , n1707 , n1691 , n1698 , n1705 );
or ( n5045 , n5043 , n5044 );
and ( n5046 , n5042 , n5045 );
nor ( n5047 , n1707 , n1690 , n1698 , n1705 );
and ( n5048 , n4081 , n5047 );
not ( n5049 , n4081 );
not ( n5050 , n3785 );
xor ( n5051 , n5049 , n5050 );
and ( n5052 , n5051 , n3569 );
and ( n5053 , n1447 , n3576 );
or ( n5054 , n5052 , n5053 );
nor ( n5055 , n1683 , n1690 , n1698 , n1705 );
and ( n5056 , n5054 , n5055 );
or ( n5057 , n1712 , n3580 , n4545 , n5039 , n5046 , n5048 , n5056 );
and ( n5058 , n1442 , n5057 );
and ( n5059 , n1447 , n1441 );
or ( n5060 , n5058 , n5059 );
buf ( n5061 , n686 );
and ( n5062 , n5060 , n5061 );
not ( n5063 , n5061 );
and ( n5064 , n1443 , n5063 );
or ( n5065 , n5062 , n5064 );
buf ( n5066 , n5065 );
buf ( n5067 , n5066 );
buf ( n5068 , n653 );
buf ( n5069 , n5068 );
buf ( n5070 , n847 );
not ( n5071 , n1441 );
and ( n5072 , n1883 , n1711 );
not ( n5073 , n2525 );
and ( n5074 , n5073 , n1876 );
xor ( n5075 , n1876 , n1859 );
and ( n5076 , n2528 , n1859 );
xor ( n5077 , n5075 , n5076 );
and ( n5078 , n5077 , n2525 );
or ( n5079 , n5074 , n5078 );
and ( n5080 , n5079 , n2671 );
and ( n5081 , n5079 , n2674 );
not ( n5082 , n2676 );
and ( n5083 , n5082 , n3080 );
not ( n5084 , n3480 );
and ( n5085 , n5084 , n3088 );
xor ( n5086 , n3088 , n3064 );
and ( n5087 , n3483 , n3485 );
xor ( n5088 , n5086 , n5087 );
and ( n5089 , n5088 , n3480 );
or ( n5090 , n5085 , n5089 );
and ( n5091 , n5090 , n2676 );
or ( n5092 , n5083 , n5091 );
and ( n5093 , n5092 , n3491 );
and ( n5094 , n3080 , n3493 );
or ( n5095 , n5080 , n5081 , n5093 , n5094 );
and ( n5096 , n5095 , n3569 );
and ( n5097 , n1883 , n3576 );
or ( n5098 , n5096 , n5097 );
and ( n5099 , n5098 , n3579 );
not ( n5100 , n4525 );
and ( n5101 , n5100 , n4199 );
xor ( n5102 , n4199 , n4176 );
and ( n5103 , n4528 , n4530 );
xor ( n5104 , n5102 , n5103 );
and ( n5105 , n5104 , n4525 );
or ( n5106 , n5101 , n5105 );
and ( n5107 , n5106 , n3569 );
and ( n5108 , n1883 , n3576 );
or ( n5109 , n5107 , n5108 );
and ( n5110 , n5109 , n4544 );
not ( n5111 , n5020 );
and ( n5112 , n5111 , n4694 );
xor ( n5113 , n4694 , n4671 );
and ( n5114 , n5023 , n5025 );
xor ( n5115 , n5113 , n5114 );
and ( n5116 , n5115 , n5020 );
or ( n5117 , n5112 , n5116 );
and ( n5118 , n5117 , n3569 );
and ( n5119 , n1883 , n3576 );
or ( n5120 , n5118 , n5119 );
and ( n5121 , n5120 , n5038 );
and ( n5122 , n4070 , n3569 );
and ( n5123 , n1883 , n3576 );
or ( n5124 , n5122 , n5123 );
and ( n5125 , n5124 , n5045 );
and ( n5126 , n4070 , n5047 );
not ( n5127 , n4070 );
and ( n5128 , n5049 , n5050 );
xor ( n5129 , n5127 , n5128 );
and ( n5130 , n5129 , n3569 );
and ( n5131 , n1883 , n3576 );
or ( n5132 , n5130 , n5131 );
and ( n5133 , n5132 , n5055 );
or ( n5134 , n5072 , n5099 , n5110 , n5121 , n5125 , n5126 , n5133 );
and ( n5135 , n5071 , n5134 );
and ( n5136 , n1883 , n1441 );
or ( n5137 , n5135 , n5136 );
and ( n5138 , n5137 , n5061 );
and ( n5139 , n1879 , n5063 );
or ( n5140 , n5138 , n5139 );
buf ( n5141 , n5140 );
buf ( n5142 , n5141 );
buf ( n5143 , n5068 );
buf ( n5144 , n847 );
not ( n5145 , n1441 );
and ( n5146 , n1907 , n1711 );
not ( n5147 , n2525 );
and ( n5148 , n5147 , n1899 );
xor ( n5149 , n1899 , n1859 );
and ( n5150 , n5075 , n5076 );
xor ( n5151 , n5149 , n5150 );
and ( n5152 , n5151 , n2525 );
or ( n5153 , n5148 , n5152 );
and ( n5154 , n5153 , n2671 );
and ( n5155 , n5153 , n2674 );
not ( n5156 , n2676 );
and ( n5157 , n5156 , n3095 );
not ( n5158 , n3480 );
and ( n5159 , n5158 , n3103 );
xor ( n5160 , n3103 , n3064 );
and ( n5161 , n5086 , n5087 );
xor ( n5162 , n5160 , n5161 );
and ( n5163 , n5162 , n3480 );
or ( n5164 , n5159 , n5163 );
and ( n5165 , n5164 , n2676 );
or ( n5166 , n5157 , n5165 );
and ( n5167 , n5166 , n3491 );
and ( n5168 , n3095 , n3493 );
or ( n5169 , n5154 , n5155 , n5167 , n5168 );
and ( n5170 , n5169 , n3569 );
and ( n5171 , n1907 , n3576 );
or ( n5172 , n5170 , n5171 );
and ( n5173 , n5172 , n3579 );
not ( n5174 , n4525 );
and ( n5175 , n5174 , n4211 );
xor ( n5176 , n4211 , n4176 );
and ( n5177 , n5102 , n5103 );
xor ( n5178 , n5176 , n5177 );
and ( n5179 , n5178 , n4525 );
or ( n5180 , n5175 , n5179 );
and ( n5181 , n5180 , n3569 );
and ( n5182 , n1907 , n3576 );
or ( n5183 , n5181 , n5182 );
and ( n5184 , n5183 , n4544 );
not ( n5185 , n5020 );
and ( n5186 , n5185 , n4706 );
xor ( n5187 , n4706 , n4671 );
and ( n5188 , n5113 , n5114 );
xor ( n5189 , n5187 , n5188 );
and ( n5190 , n5189 , n5020 );
or ( n5191 , n5186 , n5190 );
and ( n5192 , n5191 , n3569 );
and ( n5193 , n1907 , n3576 );
or ( n5194 , n5192 , n5193 );
and ( n5195 , n5194 , n5038 );
and ( n5196 , n4059 , n3569 );
and ( n5197 , n1907 , n3576 );
or ( n5198 , n5196 , n5197 );
and ( n5199 , n5198 , n5045 );
and ( n5200 , n4059 , n5047 );
not ( n5201 , n4059 );
and ( n5202 , n5127 , n5128 );
xor ( n5203 , n5201 , n5202 );
and ( n5204 , n5203 , n3569 );
and ( n5205 , n1907 , n3576 );
or ( n5206 , n5204 , n5205 );
and ( n5207 , n5206 , n5055 );
or ( n5208 , n5146 , n5173 , n5184 , n5195 , n5199 , n5200 , n5207 );
and ( n5209 , n5145 , n5208 );
and ( n5210 , n1907 , n1441 );
or ( n5211 , n5209 , n5210 );
and ( n5212 , n5211 , n5061 );
and ( n5213 , n1902 , n5063 );
or ( n5214 , n5212 , n5213 );
buf ( n5215 , n5214 );
buf ( n5216 , n5215 );
buf ( n5217 , n5068 );
buf ( n5218 , n847 );
not ( n5219 , n1441 );
and ( n5220 , n1931 , n1711 );
not ( n5221 , n2525 );
and ( n5222 , n5221 , n1923 );
xor ( n5223 , n1923 , n1859 );
and ( n5224 , n5149 , n5150 );
xor ( n5225 , n5223 , n5224 );
and ( n5226 , n5225 , n2525 );
or ( n5227 , n5222 , n5226 );
and ( n5228 , n5227 , n2671 );
and ( n5229 , n5227 , n2674 );
not ( n5230 , n2676 );
and ( n5231 , n5230 , n3110 );
not ( n5232 , n3480 );
and ( n5233 , n5232 , n3118 );
xor ( n5234 , n3118 , n3064 );
and ( n5235 , n5160 , n5161 );
xor ( n5236 , n5234 , n5235 );
and ( n5237 , n5236 , n3480 );
or ( n5238 , n5233 , n5237 );
and ( n5239 , n5238 , n2676 );
or ( n5240 , n5231 , n5239 );
and ( n5241 , n5240 , n3491 );
and ( n5242 , n3110 , n3493 );
or ( n5243 , n5228 , n5229 , n5241 , n5242 );
and ( n5244 , n5243 , n3569 );
and ( n5245 , n1931 , n3576 );
or ( n5246 , n5244 , n5245 );
and ( n5247 , n5246 , n3579 );
not ( n5248 , n4525 );
and ( n5249 , n5248 , n4223 );
xor ( n5250 , n4223 , n4176 );
and ( n5251 , n5176 , n5177 );
xor ( n5252 , n5250 , n5251 );
and ( n5253 , n5252 , n4525 );
or ( n5254 , n5249 , n5253 );
and ( n5255 , n5254 , n3569 );
and ( n5256 , n1931 , n3576 );
or ( n5257 , n5255 , n5256 );
and ( n5258 , n5257 , n4544 );
not ( n5259 , n5020 );
and ( n5260 , n5259 , n4718 );
xor ( n5261 , n4718 , n4671 );
and ( n5262 , n5187 , n5188 );
xor ( n5263 , n5261 , n5262 );
and ( n5264 , n5263 , n5020 );
or ( n5265 , n5260 , n5264 );
and ( n5266 , n5265 , n3569 );
and ( n5267 , n1931 , n3576 );
or ( n5268 , n5266 , n5267 );
and ( n5269 , n5268 , n5038 );
and ( n5270 , n4048 , n3569 );
and ( n5271 , n1931 , n3576 );
or ( n5272 , n5270 , n5271 );
and ( n5273 , n5272 , n5045 );
and ( n5274 , n4048 , n5047 );
not ( n5275 , n4048 );
and ( n5276 , n5201 , n5202 );
xor ( n5277 , n5275 , n5276 );
and ( n5278 , n5277 , n3569 );
and ( n5279 , n1931 , n3576 );
or ( n5280 , n5278 , n5279 );
and ( n5281 , n5280 , n5055 );
or ( n5282 , n5220 , n5247 , n5258 , n5269 , n5273 , n5274 , n5281 );
and ( n5283 , n5219 , n5282 );
and ( n5284 , n1931 , n1441 );
or ( n5285 , n5283 , n5284 );
and ( n5286 , n5285 , n5061 );
and ( n5287 , n1926 , n5063 );
or ( n5288 , n5286 , n5287 );
buf ( n5289 , n5288 );
buf ( n5290 , n5289 );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_2_V
`define SKY130_FD_SC_LP__OR2B_2_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2b_2 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2b_2 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_2_V
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2012/08/12 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input clk,
output reset_out
);
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
wire merged_reset;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin
assign reset_out = merged_reset;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out)
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
`define SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFXBP_PP_BLACKBOX_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_PP_BLACKBOX_V
|
module ControlUnit (output reg IR_CU, RFLOAD, PCLOAD, SRLOAD, SRENABLED, ALUSTORE, MFA, WORD_BYTE,READ_WRITE,IRLOAD,MBRLOAD,MBRSTORE,MARLOAD,output reg[4:0] opcode, output reg[3:0] CU, input MFC, Reset,Clk, input [31:0] IR,input [3:0] SR);
reg [4:0] State, NextState;
task registerTask;
input [17:0] signals;
//6 7 8 12 14 16
fork
//#2 set the alu signals
#2 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = {signals[17],1'b0,signals[15],1'b0,signals[13],1'b0,signals[11:9],1'b0,1'b0,1'b0,signals[5:0]};
//#4 set the register signals
#4 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
//#6 let data be saved
#6 {CU,IR_CU, RFLOAD, PCLOAD, SRLOAD,opcode, SRENABLED, ALUSTORE, MARLOAD,MBRSTORE,MBRLOAD,IRLOAD,MFA,READ_WRITE, WORD_BYTE} = signals;
join
endtask
always @ (negedge Clk, posedge Reset)
if (Reset) begin
State <= 5'b00000; end
else
State <= NextState;
always @ (State, MFC)
case (State)
5'b00000 : if(Reset) NextState = 5'b00000; else NextState = 5'b00001;
5'b00001 : NextState = 5'b00010;
5'b00010 : NextState = 5'b00011;
5'b00011 : NextState = 5'b00100;
5'b00100 : NextState = 5'b00101;
5'b00101 : NextState = 5'b00110;
5'b00110 : NextState = 5'b00111;
5'b00111 : NextState = 5'b01000;
5'b01000 : NextState = 5'b01001;
5'b01001 : NextState = 5'b01010;
5'b01010 : NextState = 5'b01011;
5'b01011 : NextState = 5'b01100;
5'b01100 : NextState = 5'b01101;
5'b01101 : NextState = 5'b01110;
5'b01110 : NextState = 5'b01111;
5'b01111 : NextState = 5'b10000;
5'b10000 : NextState = 5'b10001;
5'b10001 : NextState = 5'b00000;
endcase
always @ (State, MFC)
case (State)
5'b00000 : begin opcode = 0; ALUSTORE = 1 ; IR_CU= 0 ; RFLOAD= 0 ; PCLOAD= 0 ; SRLOAD= 0 ; SRENABLED= 0 ; MFA= 0 ; WORD_BYTE= 0 ;READ_WRITE= 0 ;IRLOAD= 0 ;MBRLOAD= 0 ;MBRSTORE= 0 ;MARLOAD = 0 ;end
5'b00001 : begin opcode = 1; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end // send pc to mar: ircu = 1 cu = 1111,MARLOAD = 1
5'b00010 : begin opcode = 2; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end // increment pc : loadpc = 1 ircu = 1 cu = 1111 op = 17
5'b00011 : begin opcode = 3; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end // wait for MFC: MFA = 1 LOADIR = 1 read_write = 1 word_byte = 1
5'b00100 : begin opcode = 4; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end // transfer data to IR
5'b00101 : begin opcode = 5; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end // Check status codes
5'b00110 : begin opcode = 6; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end // Decode instruction type and set out signals
5'b00111 : begin opcode = 7; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b01000 : begin opcode = 8; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b01001 : begin opcode = 9; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b01010 : begin opcode = 10; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b01011 : begin opcode = 11; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b01100 : begin opcode = 12; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b01101 : begin opcode = 13; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b01110 : begin opcode = 14; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b01111 : begin opcode = 15; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b10000 : begin opcode = 16; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
5'b10001 : begin opcode = 17; ALUSTORE = 1 ; IR_CU= 0; CU = 0 ; RFLOAD = 1 ;end
/*branch and load_store instruction*/
default : begin end
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_M_V
`define SKY130_FD_SC_LP__FA_M_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fa_m (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fa_m (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_M_V
|
//--------------------------------------------------------------------------------
// meta.v
//
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// Inserts META data into spi_transmitter datapath upon command...
//
`timescale 1ns/100ps
module meta_handler (
// system signals
input wire clock,
input wire extReset,
//
input wire query_metadata,
input wire xmit_idle,
// outputs...
output reg writeMeta,
output wire [7:0] meta_data
);
reg [5:0] metasel, next_metasel;
`define ADDBYTE(cmd) meta_rom[i]=cmd; i=i+1
`define ADDSHORT(cmd,b0) meta_rom[i]=cmd; meta_rom[i+1]=b0; i=i+2
`define ADDLONG(cmd,b0,b1,b2,b3) meta_rom[i]=cmd; meta_rom[i+1]=b0; meta_rom[i+2]=b1; meta_rom[i+3]=b2; meta_rom[i+4]=b3; i=i+5
// Create meta data ROM...
reg [5:0] METADATA_LEN;
reg [7:0] meta_rom[63:0];
assign meta_data = meta_rom[metasel];
initial
begin : meta
integer i;
i=0;
`ADDLONG(8'h01, "O", "p", "e", "n"); // Device name string...
`ADDLONG(" ", "L", "o", "g", "i");
`ADDLONG("c", " ", "S", "n", "i");
`ADDLONG("f", "f", "e", "r", " ");
`ADDLONG("v", "1", ".", "0", "1");
`ADDBYTE(0);
`ADDLONG(8'h02, "3", ".", "0", "7"); // FPGA firmware version string
`ADDBYTE(0);
//`ADDLONG(8'h21,8'h00,8'h60,8'h00,8'h00); // Amount of sample memory (24K)
//`ADDLONG(8'h23,8'h00,8'hC2,8'hEB,8'h0B); // Max sample rate (200Mhz)
`ADDLONG(8'h21,8'h00,8'h00,8'h60,8'h00); // Amount of sample memory (24K)
`ADDLONG(8'h23,8'h0B,8'hEB,8'hC2,8'h00); // Max sample rate (200Mhz)
`ADDSHORT(8'h40,8'h20); // Max # of probes
`ADDSHORT(8'h41,8'h02); // Protocol version
`ADDBYTE(0); // End of data flag
METADATA_LEN = i;
for (i=i; i<64; i=i+1) meta_rom[i]=0; // Padding
end
//
// Control FSM for sending meta data...
//
parameter [1:0] IDLE = 0, METASEND = 1, METAPOLL = 2;
reg [1:0] state, next_state;
initial state = IDLE;
always @(posedge clock, posedge extReset)
if (extReset) begin
state <= IDLE;
metasel <= 3'h0;
end else begin
state <= next_state;
metasel <= next_metasel;
end
always @*
begin
next_state = state;
next_metasel = metasel;
writeMeta = 1'b0;
case (state)
IDLE :
begin
next_metasel = 0;
next_state = (query_metadata && xmit_idle) ? METASEND : IDLE;
end
METASEND : // output contents of META data rom - IED
begin
writeMeta = 1'b1;
next_metasel = metasel+1'b1;
next_state = METAPOLL;
end
METAPOLL :
begin
if (xmit_idle)
next_state = (metasel==METADATA_LEN) ? IDLE : METASEND;
end
default : next_state = IDLE;
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:25:17 06/03/2014
// Design Name:
// Module Name: packet_gen
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//(* tristate2logic = "no" *)
`include "commands.vh"
module packet_gen#(
parameter DATAP = 8,
parameter ADDRP = 16,
parameter EXPIRE_AFTER = 31'h6000
)
(
input Clk,
input Rst,
input [DATAP-1:0] RX_byte,
input REceived,
input IS_receiving,
input IS_transmitting,
input REcv_error,
input [DATAP-1:0] Ram_dout,
input [7:0] Status,
output reg [DATAP-1:0] TX_byte,
output wire Transmit,
output wire [ADDRP-1:0] Ram_addr,
output reg Ram_we,
output reg [DATAP-1:0] Ram_din,
output reg [DATAP-1:0] Command,
output [31:0] Module_status
);
/*********************************************************************************
packet generator(pg) States
*********************************************************************************/
parameter [7:0]
IDLE = 8'h01,
CHK_HEAD = 8'h02,
WR_COMMAND = 8'h03,
SND_PKT = 8'h04,
SND_HEAD = 8'h05,
TRANS = 8'h06,
CALC_LnA = 8'h07,
WR_MEMORY = 8'h08,
RD_MEMORY = 8'h09,
SNT_LnA = 8'h0a,
DEFAULT = 8'hf0;
//********************************************************************************
reg [7:0] module_status1;
reg [7:0] pg_state;
reg [7:0] head;
reg [15:0] pkt_len;
reg [15:0] pkt_addr;
reg [7:0] len1;
reg [7:0] addr1;
reg [ADDRP-1:0] addr2;
reg [1:0] lna_count;
reg [ADDRP-1:0] data_count;
reg [31:0] waTCHDOG;
reg [ADDRP-1:0] Ram_addr_i;
reg Transmit1;
//********************************************************************************
initial begin
Ram_we <= 1'b0;
Ram_addr_i <= 15'h0000;
Transmit1 <= 1'b0;
TX_byte <= 8'h00;
head <= 8'h00;
lna_count <= 2'b00;
pg_state <= IDLE;
waTCHDOG <= 0;
module_status1 <= 0;
end
assign Transmit = Transmit1 & !IS_transmitting;
assign Module_status = {pkt_len,head,module_status1};
assign Ram_addr = Ram_we ? (Ram_addr_i - 1) : Ram_addr_i;
//*******************************--FSM--******************************************
always@(posedge Clk or posedge Rst)
begin : PKT_FSM
if(Rst) begin
pg_state <= IDLE;
end
else begin
/* waTCHDOG <= waTCHDOG - 1;
if (waTCHDOG == 0) begin
pg_state <= IDLE;
end
*/
case (pg_state)
IDLE: begin
module_status1 <= IDLE;
Ram_we <= 1'b0;
Ram_addr_i <= 16'h0000;
if (!IS_transmitting) begin
if (!Transmit1)
TX_byte <= 8'h00;
end
else begin
Transmit1 <= 1'b0;
end
head <= 8'h00;
if(REceived && (RX_byte == `PKT_START)) begin
waTCHDOG <= EXPIRE_AFTER;
pg_state <= CHK_HEAD;
end
end
CHK_HEAD: begin
module_status1 <= CHK_HEAD;
if(REceived) begin
head <= RX_byte;
case (RX_byte)
`WR_CMND: begin
pg_state <= WR_COMMAND;
waTCHDOG <= EXPIRE_AFTER;
end
`RD_STAT: begin
pg_state <= SND_PKT;
waTCHDOG <= EXPIRE_AFTER;
end
`WR_MEM: begin
lna_count <= 2'b00;
waTCHDOG <= EXPIRE_AFTER;
pg_state <= CALC_LnA;
end
`RD_MEM: begin
lna_count <= 2'b00;
waTCHDOG <= EXPIRE_AFTER;
pg_state <= CALC_LnA;
end
default: pg_state <= IDLE;
endcase
end
end
WR_COMMAND: begin
module_status1 <= WR_COMMAND;
if(REceived) begin
Command <= RX_byte;
waTCHDOG <= EXPIRE_AFTER;
pg_state <= SND_PKT;
end
end
SND_PKT: begin
module_status1 <= SND_PKT;
if (!IS_transmitting)
begin
if (Transmit1 == 1'b0) begin
Transmit1 <= 1'b1;
TX_byte <= `PKT_START;
waTCHDOG <= EXPIRE_AFTER;
pg_state <= SND_HEAD;
end
end
else begin
Transmit1 <= 1'b0;
end
end
SND_HEAD: begin
module_status1 <= SND_HEAD;
if (!IS_transmitting)
begin
if (Transmit1 == 1'b0 ) begin
Transmit1 <= 1'b1;
TX_byte <= head;
waTCHDOG <= EXPIRE_AFTER;
pg_state <= TRANS;
end
end
else begin
Transmit1 <= 1'b0;
end
end
TRANS: begin
module_status1 <= TRANS;
if (!IS_transmitting)
begin
case (head)
`RD_STAT: begin
if (Transmit1 == 1'b0) begin
TX_byte <= Status;
Transmit1 <= 1'b1;
waTCHDOG <= EXPIRE_AFTER;
pg_state <= IDLE;
end
end
`WR_CMND: begin
if (Transmit1 == 1'b0) begin
TX_byte <= Command;
Transmit1 <= 1'b1;
waTCHDOG <= EXPIRE_AFTER;
pg_state <= IDLE;
end
end
`RD_MEM: begin
pg_state <= SNT_LnA;
lna_count <= 2'b00;
waTCHDOG <= EXPIRE_AFTER;
Transmit1 <= 1'b0;
end
`WR_MEM: begin
pg_state <= SNT_LnA;
lna_count <= 2'b00;
waTCHDOG <= EXPIRE_AFTER;
Transmit1 <= 1'b0;
end
default: pg_state <= IDLE;
endcase
end
else begin
Transmit1 <= 1'b0;
end
end
CALC_LnA: begin
module_status1 <= CALC_LnA;
if(REceived) begin
waTCHDOG <= EXPIRE_AFTER;
case (lna_count)
2'b00: begin
len1 <= RX_byte;
lna_count <= 2'b01;
end
2'b01: begin
pkt_len <= {len1,RX_byte};
lna_count <= 2'b10;
end
2'b10: begin
addr1 <= RX_byte;
data_count <= pkt_len + 1;
lna_count <= 2'b11;
end
2'b11: begin
Ram_addr_i <= {addr1,RX_byte};
addr2 <= {addr1,RX_byte};
case (head)
`RD_MEM: pg_state <= SND_PKT;
`WR_MEM: pg_state <= WR_MEMORY;
default: pg_state <= IDLE;
endcase
end
endcase
end
end
SNT_LnA: begin
module_status1 <= SNT_LnA;
if (!IS_transmitting)
begin
if (!Transmit1) begin
waTCHDOG <= EXPIRE_AFTER;
Transmit1 <= 1'b1;
case (lna_count)
2'b00: begin
TX_byte <= pkt_len[15:8];
lna_count <= 2'b01;
end
2'b01: begin
TX_byte <= pkt_len[7:0];
lna_count <= 2'b10;
end
2'b10: begin
TX_byte <= addr2[15:8];
lna_count <= 2'b11;
end
2'b11: begin
TX_byte <= addr2[7:0];
if(head == `RD_MEM) begin
data_count <= pkt_len + 1;
pg_state <= RD_MEMORY; end
else
pg_state <= IDLE;
end
endcase
end
end
else begin
Transmit1 <= 1'b0;
end
end
RD_MEMORY: begin
module_status1 <= RD_MEMORY;
if (!IS_transmitting)
begin
if (!Transmit1) begin
waTCHDOG <= EXPIRE_AFTER;
if(data_count != 0) begin
Transmit1 <= 1'b1;
Ram_we <= 1'b0;
TX_byte <= Ram_dout;
Ram_addr_i <= Ram_addr_i + 1'b1;
data_count <= data_count - 1'b1;
end
else if(data_count == 0) begin
Ram_we <= 1'b0;
Ram_addr_i <= 16'h0000;
TX_byte <= 8'h00;
Transmit1 <= 1'b0;
pg_state <= IDLE;
end
end
end
else begin
Transmit1 <= 1'b0;
end
end
WR_MEMORY: begin
module_status1 <= WR_MEMORY;
if(data_count != 0) begin
if(REceived) begin
waTCHDOG <= EXPIRE_AFTER;
Ram_din <= RX_byte;
Ram_we <= 1'b1;
Ram_addr_i <= Ram_addr_i + 1'b1;
data_count <= data_count - 1'b1;
end
else begin
Ram_we <= 1'b0;
end
end
else if(data_count == 0) begin
Ram_we <= 1'b0;
Ram_din <= 8'h00;
pg_state <= SND_PKT;
end
end
default: begin
pg_state <= IDLE;
module_status1 <= DEFAULT;
end
endcase
end
end
//********************************************************************************
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:18:15 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemScore/MemScore_stub.v
// Design : MemScore
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dist_mem_gen_v8_0,Vivado 2014.4" *)
module MemScore(a, clk, spo)
/* synthesis syn_black_box black_box_pad_pin="a[7:0],clk,spo[11:0]" */;
input [7:0]a;
input clk;
output [11:0]spo;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_SYMBOL_V
`define SKY130_FD_SC_LP__XNOR2_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:35:15 11/08/2013
// Design Name: nco
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/tec-drums/nco_test.v
// Project Name: tec-drums
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: nco
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module nco_test;
// Inputs
reg aclk;
// Outputs
wire m_axis_data_tvalid;
wire [31:0] m_axis_data_tdata;
// Instantiate the Unit Under Test (UUT)
nco uut (
.aclk(aclk),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tdata(m_axis_data_tdata)
);
initial begin
// Initialize Inputs
aclk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2_BEHAVIORAL_V
|
//==================================================================================================
// Filename : antares_shifter.v
// Created On : Wed Sep 2 09:04:04 2015
// Last Modified : Sat Nov 07 12:16:18 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Arithmetic/Loogic shifter.
// WARNING: shift_shamnt range is 0 -> 31
//==================================================================================================
module antares_shifter (
input [31:0] shift_input_data, // Input data
input [4:0] shift_shamnt, // Shift amount
input shift_direction, // 0: right, 1: left
input shift_sign_extend, // 1: Signed operation
output [31:0] shift_result // Result
);
//-------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [31:0] input_inv; // invert input for shift left
reg [31:0] result_shift_temp; // shift result
reg [31:0] result_inv; // invert output for shift left
//-------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire sign;
wire [31:0] operand;
//-------------------------------------------------------------------------
// assignments
//-------------------------------------------------------------------------
assign sign = (shift_sign_extend) ? shift_input_data[31] : 1'b0;
assign operand = (shift_direction) ? input_inv : shift_input_data;
assign shift_result = (shift_direction) ? result_inv : result_shift_temp;
//-------------------------------------------------------------------------
// invert data if the operation is SLL
//-------------------------------------------------------------------------
integer index0;
integer index1;
// first inversion: input data
always @ (*) begin
for (index0 = 0; index0 < 32; index0 = index0 + 1) begin
input_inv[31 - index0] = shift_input_data[index0];
end
end
// second inversion : output
always @(*) begin
for (index1 = 0; index1 < 32; index1 = index1 + 1)
result_inv[31 - index1] = result_shift_temp[index1];
end
//--------------------------------------------------------------------------
// the BIG multiplexer
// Perform SRA. Sign depends if operation is SRA or SRL (shift_sign_extend)
//--------------------------------------------------------------------------
always @(*) begin
case(shift_shamnt)
5'd0 : result_shift_temp = operand[31:0];
5'd1 : result_shift_temp = { {1 {sign}}, operand[31:1] };
5'd2 : result_shift_temp = { {2 {sign}}, operand[31:2] };
5'd3 : result_shift_temp = { {3 {sign}}, operand[31:3] };
5'd4 : result_shift_temp = { {4 {sign}}, operand[31:4] };
5'd5 : result_shift_temp = { {5 {sign}}, operand[31:5] };
5'd6 : result_shift_temp = { {6 {sign}}, operand[31:6] };
5'd7 : result_shift_temp = { {7 {sign}}, operand[31:7] };
5'd8 : result_shift_temp = { {8 {sign}}, operand[31:8] };
5'd9 : result_shift_temp = { {9 {sign}}, operand[31:9] };
5'd10 : result_shift_temp = { {10{sign}}, operand[31:10] };
5'd11 : result_shift_temp = { {11{sign}}, operand[31:11] };
5'd12 : result_shift_temp = { {12{sign}}, operand[31:12] };
5'd13 : result_shift_temp = { {13{sign}}, operand[31:13] };
5'd14 : result_shift_temp = { {14{sign}}, operand[31:14] };
5'd15 : result_shift_temp = { {15{sign}}, operand[31:15] };
5'd16 : result_shift_temp = { {16{sign}}, operand[31:16] };
5'd17 : result_shift_temp = { {17{sign}}, operand[31:17] };
5'd18 : result_shift_temp = { {18{sign}}, operand[31:18] };
5'd19 : result_shift_temp = { {19{sign}}, operand[31:19] };
5'd20 : result_shift_temp = { {20{sign}}, operand[31:20] };
5'd21 : result_shift_temp = { {21{sign}}, operand[31:21] };
5'd22 : result_shift_temp = { {22{sign}}, operand[31:22] };
5'd23 : result_shift_temp = { {23{sign}}, operand[31:23] };
5'd24 : result_shift_temp = { {24{sign}}, operand[31:24] };
5'd25 : result_shift_temp = { {25{sign}}, operand[31:25] };
5'd26 : result_shift_temp = { {26{sign}}, operand[31:26] };
5'd27 : result_shift_temp = { {27{sign}}, operand[31:27] };
5'd28 : result_shift_temp = { {28{sign}}, operand[31:28] };
5'd29 : result_shift_temp = { {29{sign}}, operand[31:29] };
5'd30 : result_shift_temp = { {30{sign}}, operand[31:30] };
5'd31 : result_shift_temp = { {31{sign}}, operand[31:31] };
default : result_shift_temp = 32'bx;
endcase
end
endmodule // antares_shifter
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Attribute Reg Dec
// File : attr_reg_dec.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module attr_reg_dec
(
input h_reset_n,
input h_iord,
input h_iowr,
input h_dec_3cx,
input [15:0] h_io_addr,
input c_cr24_rd,
input c_cr26_rd,
input c_dec_3ba_or_3da, // decode of address 3ba or 3da
input h_io_16,
input h_hclk, // host clock
input [15:0] h_io_dbus,
output attr_data_wr, // Need to enable the attribute writing
output dport_we, // Write enable for the dual ports
output [7:0] attr_index,
output [7:0] int_io_dbus,
output a_ready_n,
output attr_mod_rd_en_hb,
output attr_mod_rd_en_lb,
output a_arx_b5, // Video display enable control bit
output pal_reg_bank_b7_b6_rd
);
reg final_toggle_ff;
reg final_toggle_ff_d; // final_toggle_ff delayed by one h_hclk
reg toggle_ff;
reg [5:0] store_index;
reg h_iowr_trim_d;
reg h_iowr_d; // Host io write delayed by one h_hclk
reg rd_or_wr_d;
wire wr_to_3c0;
wire rd_to_3ba_or_3da;
wire attr_index_rd; // Attribute index read
wire attr_data_rd;
wire dec_3c0;
wire dec_3c1;
wire attr_io_hit;
wire rd_or_wr;
wire h_iowr_trim;
integer i;
// Infering Attribute index register.
// dout is connected to h_io_dbus[15:8]
// because reading of this register happens at odd address ("03C1")
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n)
store_index <= 6'b0;
else if (~final_toggle_ff_d & h_iowr & h_io_addr == 16'h03c0)
store_index <= h_io_dbus[5:0];
assign attr_index = {2'b0, store_index};
assign a_arx_b5 = attr_index[5]; // Video display enable control bit
// Realizing index toggle register
assign dec_3c0 = h_io_addr == 16'h03c0;
assign dec_3c1 = h_io_addr == 16'h03c1;
assign rd_to_3ba_or_3da = c_dec_3ba_or_3da & h_iord;
assign h_iowr_trim = (h_iowr & (~h_iowr_d));
assign wr_to_3c0 = h_iowr_trim_d & dec_3c0;
always @(posedge h_hclk or negedge h_reset_n)
if(~h_reset_n) toggle_ff <= 1'b0;
else toggle_ff <= ((wr_to_3c0 ^ toggle_ff) &
(~rd_to_3ba_or_3da));
always @(posedge h_hclk or negedge h_reset_n)
if(~h_reset_n) final_toggle_ff <= 1'b0;
else final_toggle_ff <= (toggle_ff & (~rd_to_3ba_or_3da));
always @(posedge h_hclk or negedge h_reset_n)
if(~h_reset_n) final_toggle_ff_d <= 1'b0;
else final_toggle_ff_d <= final_toggle_ff;
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) begin
h_iowr_trim_d <= 1'b0;
h_iowr_d <= 1'b0;
end else begin
h_iowr_trim_d <= h_iowr_trim;
h_iowr_d <= h_iowr;
end
assign dport_we = final_toggle_ff_d & ~attr_index[4] & h_iowr & dec_3c0;
assign attr_index_rd = h_iord & (h_io_addr == 16'h03c0);
assign attr_data_wr = final_toggle_ff_d & h_iowr & dec_3c0;
assign attr_data_rd = ( (dec_3c0 & h_io_16) | dec_3c1 ) & h_iord;
assign int_io_dbus = { final_toggle_ff, attr_index[6:0] };
// detecting index 0 through f. pal_reg_bank_b7_b6_rd will be set whenever
// there is a read to any of registers in the palette register bank.
assign pal_reg_bank_b7_b6_rd = (~attr_index[4]) & attr_data_rd;
assign attr_mod_rd_en_hb = attr_data_rd | c_cr24_rd | c_cr26_rd;
assign attr_mod_rd_en_lb = attr_index_rd;
// Generating attr_io_hit by checking that the address range falls into one
// of the IO register of attr module
assign attr_io_hit = dec_3c0 | dec_3c1 | c_cr24_rd | c_cr26_rd;
assign rd_or_wr = h_iowr | h_iord;
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) rd_or_wr_d <= 1'b0;
else rd_or_wr_d <= rd_or_wr;
// delay (h_iowr | h_iord) by one h_hclk and then give it out as a_ready_n
assign a_ready_n = (~(rd_or_wr_d & attr_io_hit) ) ;
endmodule
|
// Driver for an LCD TFT display. Specifically, this was written to drive
// the AdaFruit YX700WV03, which is an 800x480 7" display. It's driven
// like a VGA monitor, but with digital color values, separate horizontal and
// vertical sync signals, a data enable signal, a clock, and with different
// timings.
module LCD_control(
// Host Side
input [7:0] iRed,
input [7:0] iGreen,
input [7:0] iBlue,
output [9:0] oCurrent_X, // Max horizontal pixels: 1023.
output [9:0] oCurrent_Y, // Max vertical pixels: 1023.
output [21:0] oAddress, // [0..(w*h))
output oRequest, // Whether we need a pixel right now.
output reg oTopOfScreen, // 1 when at the very top of screen.
// LCD Side
output [7:0] oLCD_R,
output [7:0] oLCD_G,
output [7:0] oLCD_B,
output reg oLCD_HS, // Active low.
output reg oLCD_VS, // Active low.
output oLCD_DE, // Active high.
// Control Signal
input iCLK,
input iRST_N
);
// LK: There are two internal registers, H_Cont and V_Cont. They are 0-based. The
// H_Cont value has these ranges:
//
// H_Cont oLCD_HS
// [0, H_FRONT) 1 (front porch)
// [H_FRONT, H_FRONT + H_SYNC) 0 (sync pulse)
// [H_FRONT + H_SYNC, H_BLANK) 1 (back porch, V_Cont is incremented)
// [H_BLANK, H_TOTAL) 1 (pixels are visible)
//
// V_Cont value has these ranges:
//
// V_Cont oLCD_VS
// [0, V_FRONT) 1 (front porch)
// [V_FRONT, V_FRONT + V_SYNC) 0 (sync pulse)
// [V_FRONT + V_SYNC, V_BLANK) 1 (back porch)
// [V_BLANK, V_TOTAL) 1 (pixels are visible)
//
// Note that V_Cont is incremented on the positive edge of oLCD_HS, which means
// that its values are offset from the normal 0-799 range of H_Cont.
//
// oTopOfScreen is the first pixel of the second row, since that's where
// both are zero.
//
// The LCD clock is 25.175 MHz. With 992x500 pixels (800x480 visible),
// that's about 50 FPS.
// Internal Registers
reg [10:0] H_Cont;
reg [10:0] V_Cont;
////////////////////////////////////////////////////////////
// Horizontal Parameter
parameter H_FRONT = 24;
parameter H_SYNC = 72;
parameter H_BACK = 96;
parameter H_ACT = 800;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 3;
parameter V_SYNC = 10;
parameter V_BACK = 7;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
////////////////////////////////////////////////////////////
assign oLCD_R = oRequest ? iRed : 8'b0 ;
assign oLCD_G = oRequest ? iGreen : 8'b0 ;
assign oLCD_B = oRequest ? iBlue : 8'b0 ;
assign oAddress = oCurrent_Y*H_ACT + oCurrent_X;
assign oRequest = H_Cont >= H_BLANK && V_Cont >= V_BLANK;
assign oCurrent_X = (H_Cont>=H_BLANK) ? H_Cont-H_BLANK : 11'h0;
assign oCurrent_Y = (V_Cont>=V_BLANK) ? V_Cont-V_BLANK : 11'h0;
assign oLCD_DE = oRequest;
// Latch the top-of-screen register. That means that it's one clock late,
// but that's okay since it's nowhere near the visible portion of the screen.
wire oTopOfScreenNext = H_Cont == 0 && V_Cont == 0;
always @(posedge iCLK)
begin
oTopOfScreen <= oTopOfScreenNext;
end
// Horizontal Generator: Refers to the pixel clock.
always @(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N) begin
H_Cont <= 0;
oLCD_HS <= 1;
end else begin
// Advance pixel.
if (H_Cont < H_TOTAL - 1) begin
H_Cont <= H_Cont + 1'b1;
end else begin
H_Cont <= 0;
end
// Horizontal Sync
if (H_Cont == H_FRONT - 1) begin
// Front porch end
oLCD_HS <= 1'b0;
end
if (H_Cont == H_FRONT + H_SYNC - 1) begin
// Sync pulse end
oLCD_HS <= 1'b1;
end
end
end
// Vertical Generator: Refers to the horizontal sync.
always @(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N) begin
V_Cont <= 0;
oLCD_VS <= 1;
end else if (H_Cont == 0) begin
// Advance line.
if (V_Cont < V_TOTAL-1) begin
V_Cont <= V_Cont+1'b1;
end else begin
V_Cont <= 0;
end
// Vertical Sync
if (V_Cont == V_FRONT - 1) begin
// Front porch end
oLCD_VS <= 1'b0;
end
if (V_Cont == V_FRONT + V_SYNC - 1) begin
// Sync pulse end
oLCD_VS <= 1'b1;
end
end
end
endmodule
|
/*
* Author : Tom Stanway-Mayers
* Description : FIFO
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
`include "riscv_defs.v"
module merlin_fifo
#(
parameter C_FIFO_PASSTHROUGH = 0,
parameter C_FIFO_WIDTH = 1,
parameter C_FIFO_DEPTH_X = 1,
//
parameter C_FIFO_DEPTH = 2**C_FIFO_DEPTH_X
)
(
// global
input wire clk_i,
input wire reset_i,
// control and status
input wire flush_i,
output wire empty_o,
output reg full_o,
// write port
input wire wr_i,
input wire [C_FIFO_WIDTH-1:0] din_i,
// read port
input wire rd_i,
output wire [C_FIFO_WIDTH-1:0] dout_o
);
//--------------------------------------------------------------
// interface assignments
// status signals
reg empty_int;
// pointers
reg [C_FIFO_DEPTH_X:0] rd_ptr_q;
reg [C_FIFO_DEPTH_X:0] wr_ptr_q;
// memory
reg [C_FIFO_WIDTH-1:0] mem[C_FIFO_DEPTH-1:0];
//--------------------------------------------------------------
//--------------------------------------------------------------
// interface assignments
//--------------------------------------------------------------
generate if (C_FIFO_PASSTHROUGH) begin
assign empty_o = (empty_int == 1'b1 ? ~wr_i : empty_int);
assign dout_o = (empty_int == 1'b1 ? din_i : mem[rd_ptr_q[C_FIFO_DEPTH_X-1:0]]);
end else begin
assign empty_o = empty_int;
assign dout_o = mem[rd_ptr_q[C_FIFO_DEPTH_X-1:0]];
end endgenerate
//--------------------------------------------------------------
// status signals
//--------------------------------------------------------------
always @ (*) begin
empty_int = 1'b0;
full_o = 1'b0;
if (rd_ptr_q[C_FIFO_DEPTH_X-1:0] == wr_ptr_q[C_FIFO_DEPTH_X-1:0]) begin
if (rd_ptr_q[C_FIFO_DEPTH_X] == wr_ptr_q[C_FIFO_DEPTH_X]) begin
empty_int = 1'b1;
end else begin
full_o = 1'b1;
end
end
end
//--------------------------------------------------------------
// pointers
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK_RESET(clk_i, reset_i) begin
if (reset_i) begin
rd_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
wr_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
end else begin
if (flush_i) begin
rd_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
wr_ptr_q <= { C_FIFO_DEPTH_X+1 {1'b0} };
end else begin
if (rd_i) begin
rd_ptr_q <= rd_ptr_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end
if (wr_i) begin
wr_ptr_q <= wr_ptr_q + { { C_FIFO_DEPTH_X {1'b0} }, 1'b1 };
end
end
end
end
//--------------------------------------------------------------
// memory
//--------------------------------------------------------------
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
if (wr_i) begin
mem[wr_ptr_q[C_FIFO_DEPTH_X-1:0]] <= din_i;
end
end
//--------------------------------------------------------------
// asserts
//--------------------------------------------------------------
`ifdef RV_ASSERTS_ON
always @ `RV_SYNC_LOGIC_CLOCK(clk_i) begin
`RV_ASSERT(((full_o & wr_i) == 1'b0), "FIFO written when full!")
`RV_ASSERT(((empty_o & rd_i) == 1'b0), "FIFO read when empty!")
end
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O31AI_FUNCTIONAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o31ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
// Local signals
wire B1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_FUNCTIONAL_V
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Int63 FloatClass.
(** * Definition of the interface for primitive floating-point arithmetic
This interface provides processor operators for the Binary64 format of the
IEEE 754-2008 standard. *)
(** ** Type definition for the co-domain of [compare] *)
Variant float_comparison : Set := FEq | FLt | FGt | FNotComparable.
Register float_comparison as kernel.ind_f_cmp.
Register float_class as kernel.ind_f_class.
(** ** The main type *)
(** [float]: primitive type for Binary64 floating-point numbers. *)
Primitive float := #float64_type.
(** ** Syntax support *)
Module Import PrimFloatNotationsInternalA.
Declare Scope float_scope.
Delimit Scope float_scope with float.
Bind Scope float_scope with float.
End PrimFloatNotationsInternalA.
Declare ML Module "float_syntax_plugin".
(** ** Floating-point operators *)
Primitive classify := #float64_classify.
Primitive abs := #float64_abs.
Primitive sqrt := #float64_sqrt.
Primitive opp := #float64_opp.
Primitive eqb := #float64_eq.
Primitive ltb := #float64_lt.
Primitive leb := #float64_le.
Primitive compare := #float64_compare.
Primitive mul := #float64_mul.
Primitive add := #float64_add.
Primitive sub := #float64_sub.
Primitive div := #float64_div.
Module Import PrimFloatNotationsInternalB.
Notation "- x" := (opp x) : float_scope.
Notation "x =? y" := (eqb x y) (at level 70, no associativity) : float_scope.
Notation "x <? y" := (ltb x y) (at level 70, no associativity) : float_scope.
Notation "x <=? y" := (leb x y) (at level 70, no associativity) : float_scope.
Notation "x ?= y" := (compare x y) (at level 70, no associativity) : float_scope.
Notation "x * y" := (mul x y) : float_scope.
Notation "x + y" := (add x y) : float_scope.
Notation "x - y" := (sub x y) : float_scope.
Notation "x / y" := (div x y) : float_scope.
End PrimFloatNotationsInternalB.
(** ** Conversions *)
(** [of_int63]: convert a primitive integer into a float value.
The value is rounded if need be. *)
Primitive of_int63 := #float64_of_int63.
(** Specification of [normfr_mantissa]:
- If the input is a float value with an absolute value inside $[0.5, 1.)$#[0.5, 1.)#;
- Then return its mantissa as a primitive integer.
The mantissa will be a 53-bit integer with its most significant bit set to 1;
- Else return zero.
The sign bit is always ignored. *)
Primitive normfr_mantissa := #float64_normfr_mantissa.
(** ** Exponent manipulation functions *)
(** [frshiftexp]: convert a float to fractional part in $[0.5, 1.)$#[0.5, 1.)#
and integer part. *)
Primitive frshiftexp := #float64_frshiftexp.
(** [ldshiftexp]: multiply a float by an integral power of 2. *)
Primitive ldshiftexp := #float64_ldshiftexp.
(** ** Predecesor/Successor functions *)
(** [next_up]: return the next float towards positive infinity. *)
Primitive next_up := #float64_next_up.
(** [next_down]: return the next float towards negative infinity. *)
Primitive next_down := #float64_next_down.
(** ** Special values (needed for pretty-printing) *)
Definition infinity := Eval compute in div (of_int63 1) (of_int63 0).
Definition neg_infinity := Eval compute in opp infinity.
Definition nan := Eval compute in div (of_int63 0) (of_int63 0).
Register infinity as num.float.infinity.
Register neg_infinity as num.float.neg_infinity.
Register nan as num.float.nan.
(** ** Other special values *)
Definition one := Eval compute in (of_int63 1).
Definition zero := Eval compute in (of_int63 0).
Definition neg_zero := Eval compute in (-zero)%float.
Definition two := Eval compute in (of_int63 2).
(** ** Predicates and helper functions *)
Definition is_nan f := negb (f =? f)%float.
Definition is_zero f := (f =? zero)%float. (* note: 0 =? -0 with floats *)
Definition is_infinity f := (abs f =? infinity)%float.
Definition is_finite (x : float) := negb (is_nan x || is_infinity x).
(** [get_sign]: return [true] for [-] sign, [false] for [+] sign. *)
Definition get_sign f :=
let f := if is_zero f then (one / f)%float else f in
(f <? zero)%float.
Module Export PrimFloatNotations.
Local Open Scope float_scope.
#[deprecated(since="8.13",note="use infix <? instead")]
Notation "x < y" := (x <? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix <=? instead")]
Notation "x <= y" := (x <=? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix =? instead")]
Notation "x == y" := (x =? y) (at level 70, no associativity) : float_scope.
Export PrimFloatNotationsInternalA.
Export PrimFloatNotationsInternalB.
End PrimFloatNotations.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSBP_TB_V
`define SKY130_FD_SC_HVL__DFSBP_TB_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfsbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__dfsbp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSBP_TB_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
// Date : Tue Mar 22 03:45:28 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_decoder_prj/project_1.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_funcsim.v
// Design : dcfifo_32in_32out_16kb
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "dcfifo_32in_32out_16kb,fifo_generator_v12_0,{}" *) (* core_generation_info = "dcfifo_32in_32out_16kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=9,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=1,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=509,C_PROG_FULL_THRESH_NEGATE_VAL=508,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=9,C_RD_DEPTH=512,C_RD_FREQ=1,C_RD_PNTR_WIDTH=9,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=2,C_WR_DEPTH=512,C_WR_FREQ=1,C_WR_PNTR_WIDTH=9,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
(* NotValidForBitStream *)
module dcfifo_32in_32out_16kb
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
wr_data_count);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [31:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [31:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output [1:0]wr_data_count;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [8:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [8:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "9" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "32" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "512x36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "509" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "508" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "9" *)
(* C_RD_DEPTH = "512" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "9" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "2" *)
(* C_WR_DEPTH = "512" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "9" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
dcfifo_32in_32out_16kb_fifo_generator_v12_0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[8:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[8:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module dcfifo_32in_32out_16kb_blk_mem_gen_generic_cstr
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_16kb_blk_mem_gen_prim_width \ramloop[0].ram.r
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module dcfifo_32in_32out_16kb_blk_mem_gen_prim_width
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_16kb_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module dcfifo_32in_32out_16kb_blk_mem_gen_prim_wrapper
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [31:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 ;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram
(.ADDRARDADDR({\gc0.count_d1_reg[8] ,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({\gic0.gc0.count_d2_reg[8] ,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(rd_clk),
.CLKBWRCLK(wr_clk),
.DIADI(din[15:0]),
.DIBDI(din[31:16]),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO(dout[15:0]),
.DOBDO(dout[31:16]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(tmp_ram_rd_en),
.ENBWREN(WEBWE),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(Q),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({WEBWE,WEBWE,WEBWE,WEBWE}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module dcfifo_32in_32out_16kb_blk_mem_gen_top
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_16kb_blk_mem_gen_generic_cstr \valid.cstr
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *)
module dcfifo_32in_32out_16kb_blk_mem_gen_v8_2
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_16kb_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module dcfifo_32in_32out_16kb_blk_mem_gen_v8_2_synth
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_16kb_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module dcfifo_32in_32out_16kb_clk_x_pntrs
(ram_empty_fb_i_reg,
WR_PNTR_RD,
v1_reg,
v1_reg_0,
RD_PNTR_WR,
Q,
\gc0.count_reg[7] ,
\gic0.gc0.count_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output ram_empty_fb_i_reg;
output [8:0]WR_PNTR_RD;
output [3:0]v1_reg;
output [0:0]v1_reg_0;
output [8:0]RD_PNTR_WR;
input [8:0]Q;
input [7:0]\gc0.count_reg[7] ;
input [0:0]\gic0.gc0.count_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [8:0]Q;
wire [8:0]RD_PNTR_WR;
wire [8:0]WR_PNTR_RD;
wire [7:0]\gc0.count_reg[7] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire [0:0]\gic0.gc0.count_reg[8] ;
wire \gsync_stage[2].wr_stg_inst_n_1 ;
wire \gsync_stage[2].wr_stg_inst_n_2 ;
wire \gsync_stage[2].wr_stg_inst_n_3 ;
wire \gsync_stage[2].wr_stg_inst_n_4 ;
wire \gsync_stage[2].wr_stg_inst_n_5 ;
wire \gsync_stage[2].wr_stg_inst_n_6 ;
wire \gsync_stage[2].wr_stg_inst_n_7 ;
wire \gsync_stage[2].wr_stg_inst_n_8 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]p_0_in;
wire [7:0]p_0_in7_out;
wire [8:8]p_0_out;
wire [8:8]p_1_out;
wire [8:0]p_2_out;
wire [8:0]p_3_out;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire [8:0]rd_pntr_gc;
wire \rd_pntr_gc[0]_i_1_n_0 ;
wire \rd_pntr_gc[1]_i_1_n_0 ;
wire \rd_pntr_gc[2]_i_1_n_0 ;
wire \rd_pntr_gc[3]_i_1_n_0 ;
wire \rd_pntr_gc[4]_i_1_n_0 ;
wire \rd_pntr_gc[5]_i_1_n_0 ;
wire \rd_pntr_gc[6]_i_1_n_0 ;
wire \rd_pntr_gc[7]_i_1_n_0 ;
wire [3:0]v1_reg;
wire [0:0]v1_reg_0;
wire wr_clk;
wire [8:0]wr_pntr_gc;
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(WR_PNTR_RD[1]),
.I1(\gc0.count_reg[7] [1]),
.I2(WR_PNTR_RD[0]),
.I3(\gc0.count_reg[7] [0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(WR_PNTR_RD[3]),
.I1(\gc0.count_reg[7] [3]),
.I2(WR_PNTR_RD[2]),
.I3(\gc0.count_reg[7] [2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(WR_PNTR_RD[5]),
.I1(\gc0.count_reg[7] [5]),
.I2(WR_PNTR_RD[4]),
.I3(\gc0.count_reg[7] [4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(WR_PNTR_RD[7]),
.I1(\gc0.count_reg[7] [7]),
.I2(WR_PNTR_RD[6]),
.I3(\gc0.count_reg[7] [6]),
.O(v1_reg[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__0
(.I0(RD_PNTR_WR[8]),
.I1(\gic0.gc0.count_reg[8] ),
.O(v1_reg_0));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__2
(.I0(WR_PNTR_RD[8]),
.I1(Q[8]),
.O(ram_empty_fb_i_reg));
dcfifo_32in_32out_16kb_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
dcfifo_32in_32out_16kb_synchronizer_ff_3 \gsync_stage[1].wr_stg_inst
(.D(p_2_out),
.Q(rd_pntr_gc),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.wr_clk(wr_clk));
dcfifo_32in_32out_16kb_synchronizer_ff_4 \gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_1_out),
.rd_clk(rd_clk),
.\wr_pntr_bin_reg[7] (p_0_in));
dcfifo_32in_32out_16kb_synchronizer_ff_5 \gsync_stage[2].wr_stg_inst
(.D(p_2_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.out(p_0_out),
.\rd_pntr_bin_reg[7] ({\gsync_stage[2].wr_stg_inst_n_1 ,\gsync_stage[2].wr_stg_inst_n_2 ,\gsync_stage[2].wr_stg_inst_n_3 ,\gsync_stage[2].wr_stg_inst_n_4 ,\gsync_stage[2].wr_stg_inst_n_5 ,\gsync_stage[2].wr_stg_inst_n_6 ,\gsync_stage[2].wr_stg_inst_n_7 ,\gsync_stage[2].wr_stg_inst_n_8 }),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_8 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_out),
.Q(RD_PNTR_WR[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\rd_pntr_gc[7]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[7]),
.Q(WR_PNTR_RD[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_1_out),
.Q(WR_PNTR_RD[8]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [0]),
.I1(\gic0.gc0.count_d2_reg[8] [1]),
.O(p_0_in7_out[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [1]),
.I1(\gic0.gc0.count_d2_reg[8] [2]),
.O(p_0_in7_out[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [2]),
.I1(\gic0.gc0.count_d2_reg[8] [3]),
.O(p_0_in7_out[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [3]),
.I1(\gic0.gc0.count_d2_reg[8] [4]),
.O(p_0_in7_out[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [4]),
.I1(\gic0.gc0.count_d2_reg[8] [5]),
.O(p_0_in7_out[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [5]),
.I1(\gic0.gc0.count_d2_reg[8] [6]),
.O(p_0_in7_out[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [6]),
.I1(\gic0.gc0.count_d2_reg[8] [7]),
.O(p_0_in7_out[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[8] [7]),
.I1(\gic0.gc0.count_d2_reg[8] [8]),
.O(p_0_in7_out[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in7_out[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gic0.gc0.count_d2_reg[8] [8]),
.Q(wr_pntr_gc[8]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module dcfifo_32in_32out_16kb_compare
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module dcfifo_32in_32out_16kb_compare_0
(comp2,
v1_reg_0,
\rd_pntr_bin_reg[8] );
output comp2;
input [3:0]v1_reg_0;
input [0:0]\rd_pntr_bin_reg[8] ;
wire comp2;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [0:0]\rd_pntr_bin_reg[8] ;
wire [3:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\rd_pntr_bin_reg[8] }));
endmodule
(* ORIG_REF_NAME = "compare" *)
module dcfifo_32in_32out_16kb_compare_1
(comp0,
v1_reg_0,
\wr_pntr_bin_reg[8] );
output comp0;
input [3:0]v1_reg_0;
input \wr_pntr_bin_reg[8] ;
wire comp0;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [3:0]v1_reg_0;
wire \wr_pntr_bin_reg[8] ;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\wr_pntr_bin_reg[8] }));
endmodule
(* ORIG_REF_NAME = "compare" *)
module dcfifo_32in_32out_16kb_compare_2
(comp1,
v1_reg,
\gc0.count_reg[8] );
output comp1;
input [3:0]v1_reg;
input \gc0.count_reg[8] ;
wire comp1;
wire \gc0.count_reg[8] ;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [3:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],\gc0.count_reg[8] }));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module dcfifo_32in_32out_16kb_fifo_generator_ramfifo
(dout,
empty,
full,
wr_data_count,
wr_en,
rd_clk,
wr_clk,
din,
rst,
rd_en);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
input rd_en;
wire RD_RST;
wire WR_RST;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gcx.clkx_n_0 ;
wire \gntv_or_sync_fifo.gl0.wr_n_1 ;
wire [3:0]\gras.rsts/c1/v1_reg ;
wire [4:4]\gwas.wsts/c2/v1_reg ;
wire [8:0]p_0_out;
wire p_18_out;
wire [8:0]p_1_out;
wire [8:0]p_20_out;
wire [8:0]p_9_out;
wire rd_clk;
wire rd_en;
wire [7:0]rd_pntr_plus1;
wire [1:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire [8:8]wr_pntr_plus2;
wire [0:0]wr_rst_i;
dcfifo_32in_32out_16kb_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.Q(p_20_out),
.RD_PNTR_WR(p_0_out),
.WR_PNTR_RD(p_1_out),
.\gc0.count_reg[7] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[8] (p_9_out),
.\gic0.gc0.count_reg[8] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (wr_rst_i),
.ram_empty_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_0 ),
.rd_clk(rd_clk),
.v1_reg(\gras.rsts/c1/v1_reg ),
.v1_reg_0(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk));
dcfifo_32in_32out_16kb_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (p_20_out),
.Q(RD_RST),
.WR_PNTR_RD(p_1_out),
.empty(empty),
.\gc0.count_d1_reg[7] (rd_pntr_plus1),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(\gras.rsts/c1/v1_reg ),
.\wr_pntr_bin_reg[8] (\gntv_or_sync_fifo.gcx.clkx_n_0 ));
dcfifo_32in_32out_16kb_wr_logic \gntv_or_sync_fifo.gl0.wr
(.Q(p_9_out),
.RD_PNTR_WR(p_0_out),
.WEBWE(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.full(full),
.\gic0.gc0.count_d1_reg[8] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (WR_RST),
.\rd_pntr_bin_reg[8] (\gwas.wsts/c2/v1_reg ),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
dcfifo_32in_32out_16kb_memory \gntv_or_sync_fifo.mem
(.Q(rd_rst_i[0]),
.WEBWE(\gntv_or_sync_fifo.gl0.wr_n_1 ),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (p_20_out),
.\gic0.gc0.count_d2_reg[8] (p_9_out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
dcfifo_32in_32out_16kb_reset_blk_ramfifo rstblk
(.Q({RD_RST,rd_rst_i}),
.\gic0.gc0.count_reg[0] ({WR_RST,wr_rst_i}),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module dcfifo_32in_32out_16kb_fifo_generator_top
(dout,
empty,
full,
wr_data_count,
wr_en,
rd_clk,
wr_clk,
din,
rst,
rd_en);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
input rd_en;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_16kb_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "9" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "32" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "512x36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "509" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "508" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "9" *) (* C_RD_DEPTH = "512" *)
(* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "9" *) (* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "2" *) (* C_WR_DEPTH = "512" *) (* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "9" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v12_0" *)
module dcfifo_32in_32out_16kb_fifo_generator_v12_0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [31:0]din;
input wr_en;
input rd_en;
input [8:0]prog_empty_thresh;
input [8:0]prog_empty_thresh_assert;
input [8:0]prog_empty_thresh_negate;
input [8:0]prog_full_thresh;
input [8:0]prog_full_thresh_assert;
input [8:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [31:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [8:0]data_count;
output [8:0]rd_data_count;
output [1:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [8:0]prog_empty_thresh;
wire [8:0]prog_empty_thresh_assert;
wire [8:0]prog_empty_thresh_negate;
wire [8:0]prog_full_thresh;
wire [8:0]prog_full_thresh_assert;
wire [8:0]prog_full_thresh_negate;
wire rd_clk;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
dcfifo_32in_32out_16kb_fifo_generator_v12_0_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *)
module dcfifo_32in_32out_16kb_fifo_generator_v12_0_synth
(dout,
empty,
full,
wr_data_count,
wr_en,
rd_clk,
wr_clk,
din,
rst,
rd_en);
output [31:0]dout;
output empty;
output full;
output [1:0]wr_data_count;
input wr_en;
input rd_clk;
input wr_clk;
input [31:0]din;
input rst;
input rd_en;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_16kb_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "memory" *)
module dcfifo_32in_32out_16kb_memory
(dout,
rd_clk,
wr_clk,
tmp_ram_rd_en,
WEBWE,
Q,
\gc0.count_d1_reg[8] ,
\gic0.gc0.count_d2_reg[8] ,
din);
output [31:0]dout;
input rd_clk;
input wr_clk;
input tmp_ram_rd_en;
input [0:0]WEBWE;
input [0:0]Q;
input [8:0]\gc0.count_d1_reg[8] ;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [31:0]din;
wire [0:0]Q;
wire [0:0]WEBWE;
wire [31:0]din;
wire [31:0]dout;
wire [8:0]\gc0.count_d1_reg[8] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_16kb_blk_mem_gen_v8_2 \gbm.gbmg.gbmga.ngecc.bmg
(.Q(Q),
.WEBWE(WEBWE),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[8] (\gc0.count_d1_reg[8] ),
.\gic0.gc0.count_d2_reg[8] (\gic0.gc0.count_d2_reg[8] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module dcfifo_32in_32out_16kb_rd_bin_cntr
(ram_empty_fb_i_reg,
Q,
v1_reg,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
WR_PNTR_RD,
E,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output ram_empty_fb_i_reg;
output [7:0]Q;
output [3:0]v1_reg;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
input [8:0]WR_PNTR_RD;
input [0:0]E;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [8:0]WR_PNTR_RD;
wire \gc0.count[8]_i_2_n_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [8:0]plusOp;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire [8:8]rd_pntr_plus1;
wire [3:0]v1_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h6A))
\gc0.count[2]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[4]_i_1
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[5]_i_1
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[2]),
.I3(Q[0]),
.I4(Q[1]),
.I5(Q[4]),
.O(plusOp[5]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[6]_i_1
(.I0(Q[6]),
.I1(Q[4]),
.I2(\gc0.count[8]_i_2_n_0 ),
.I3(Q[5]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[7]_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\gc0.count[8]_i_2_n_0 ),
.I3(Q[4]),
.I4(Q[6]),
.O(plusOp[7]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[8]_i_1
(.I0(rd_pntr_plus1),
.I1(Q[6]),
.I2(Q[4]),
.I3(\gc0.count[8]_i_2_n_0 ),
.I4(Q[5]),
.I5(Q[7]),
.O(plusOp[8]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h8000))
\gc0.count[8]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.O(\gc0.count[8]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(rd_pntr_plus1),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [8]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[8]),
.Q(rd_pntr_plus1));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [1]),
.I1(WR_PNTR_RD[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [0]),
.I3(WR_PNTR_RD[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [3]),
.I1(WR_PNTR_RD[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [2]),
.I3(WR_PNTR_RD[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [5]),
.I1(WR_PNTR_RD[5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [4]),
.I3(WR_PNTR_RD[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [7]),
.I1(WR_PNTR_RD[7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram [6]),
.I3(WR_PNTR_RD[6]),
.O(v1_reg[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1__1
(.I0(rd_pntr_plus1),
.I1(WR_PNTR_RD[8]),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module dcfifo_32in_32out_16kb_rd_logic
(empty,
p_18_out,
\gc0.count_d1_reg[7] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,
\wr_pntr_bin_reg[8] ,
v1_reg,
rd_clk,
Q,
WR_PNTR_RD,
rd_en);
output empty;
output p_18_out;
output [7:0]\gc0.count_d1_reg[7] ;
output [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
input \wr_pntr_bin_reg[8] ;
input [3:0]v1_reg;
input rd_clk;
input [0:0]Q;
input [8:0]WR_PNTR_RD;
input rd_en;
wire [8:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]Q;
wire [8:0]WR_PNTR_RD;
wire [3:0]\c0/v1_reg ;
wire empty;
wire [7:0]\gc0.count_d1_reg[7] ;
wire p_14_out;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rpntr_n_0;
wire [3:0]v1_reg;
wire \wr_pntr_bin_reg[8] ;
dcfifo_32in_32out_16kb_rd_status_flags_as \gras.rsts
(.E(p_14_out),
.Q(Q),
.empty(empty),
.\gc0.count_reg[8] (rpntr_n_0),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ),
.\wr_pntr_bin_reg[8] (\wr_pntr_bin_reg[8] ));
dcfifo_32in_32out_16kb_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ),
.E(p_14_out),
.Q(\gc0.count_d1_reg[7] ),
.WR_PNTR_RD(WR_PNTR_RD),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (Q),
.ram_empty_fb_i_reg(rpntr_n_0),
.rd_clk(rd_clk),
.v1_reg(\c0/v1_reg ));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module dcfifo_32in_32out_16kb_rd_status_flags_as
(empty,
p_18_out,
E,
v1_reg_0,
\wr_pntr_bin_reg[8] ,
v1_reg,
\gc0.count_reg[8] ,
rd_clk,
Q,
rd_en);
output empty;
output p_18_out;
output [0:0]E;
input [3:0]v1_reg_0;
input \wr_pntr_bin_reg[8] ;
input [3:0]v1_reg;
input \gc0.count_reg[8] ;
input rd_clk;
input [0:0]Q;
input rd_en;
wire [0:0]E;
wire [0:0]Q;
wire comp0;
wire comp1;
wire empty;
wire \gc0.count_reg[8] ;
wire p_18_out;
wire ram_empty_i_i_1_n_0;
wire rd_clk;
wire rd_en;
wire [3:0]v1_reg;
wire [3:0]v1_reg_0;
wire \wr_pntr_bin_reg[8] ;
dcfifo_32in_32out_16kb_compare_1 c0
(.comp0(comp0),
.v1_reg_0(v1_reg_0),
.\wr_pntr_bin_reg[8] (\wr_pntr_bin_reg[8] ));
dcfifo_32in_32out_16kb_compare_2 c1
(.comp1(comp1),
.\gc0.count_reg[8] (\gc0.count_reg[8] ),
.v1_reg(v1_reg));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[8]_i_1
(.I0(rd_en),
.I1(p_18_out),
.O(E));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(ram_empty_i_i_1_n_0),
.PRE(Q),
.Q(p_18_out));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hAEAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(p_18_out),
.I3(comp1),
.O(ram_empty_i_i_1_n_0));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(ram_empty_i_i_1_n_0),
.PRE(Q),
.Q(empty));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module dcfifo_32in_32out_16kb_reset_blk_ramfifo
(rst_full_ff_i,
rst_full_gen_i,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_reg[0] ,
wr_clk,
rst,
rd_clk,
p_18_out,
rd_en);
output rst_full_ff_i;
output rst_full_gen_i;
output tmp_ram_rd_en;
output [2:0]Q;
output [1:0]\gic0.gc0.count_reg[0] ;
input wr_clk;
input rst;
input rd_clk;
input p_18_out;
input rd_en;
wire [2:0]Q;
wire [1:0]\gic0.gc0.count_reg[0] ;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire rst_rd_reg1;
wire rst_rd_reg2;
wire rst_wr_reg1;
wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
assign rst_full_ff_i = rst_d2;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1
(.I0(Q[0]),
.I1(p_18_out),
.I2(rd_en),
.O(tmp_ram_rd_en));
FDCE #(
.INIT(1'b0))
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d1),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d1),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(\gic0.gc0.count_reg[0] [0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(\gic0.gc0.count_reg[0] [1]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_16kb_synchronizer_ff
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [8:0]D;
input [8:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [8:0]Q;
wire [8:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[8:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_16kb_synchronizer_ff_3
(D,
Q,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [8:0]D;
input [8:0]Q;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [8:0]Q;
wire [8:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire wr_clk;
assign D[8:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[8]),
.Q(Q_reg[8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_16kb_synchronizer_ff_4
(out,
\wr_pntr_bin_reg[7] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [7:0]\wr_pntr_bin_reg[7] ;
input [8:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [8:0]D;
wire [8:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
wire [7:0]\wr_pntr_bin_reg[7] ;
assign out[0] = Q_reg[8];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[8]),
.Q(Q_reg[8]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[0]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[0]),
.I3(\wr_pntr_bin_reg[7] [3]),
.O(\wr_pntr_bin_reg[7] [0]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(\wr_pntr_bin_reg[7] [3]),
.O(\wr_pntr_bin_reg[7] [1]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[2]_i_1
(.I0(\wr_pntr_bin_reg[7] [3]),
.I1(Q_reg[2]),
.O(\wr_pntr_bin_reg[7] [2]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[3]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[8]),
.I2(Q_reg[6]),
.I3(Q_reg[7]),
.I4(Q_reg[5]),
.I5(Q_reg[3]),
.O(\wr_pntr_bin_reg[7] [3]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[4]_i_1
(.I0(Q_reg[5]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[8]),
.I4(Q_reg[4]),
.O(\wr_pntr_bin_reg[7] [4]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[5]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[6]),
.I2(Q_reg[7]),
.I3(Q_reg[5]),
.O(\wr_pntr_bin_reg[7] [5]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[8]),
.O(\wr_pntr_bin_reg[7] [6]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[7]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[8]),
.O(\wr_pntr_bin_reg[7] [7]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_16kb_synchronizer_ff_5
(out,
\rd_pntr_bin_reg[7] ,
D,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [0:0]out;
output [7:0]\rd_pntr_bin_reg[7] ;
input [8:0]D;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [8:0]D;
wire [8:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [7:0]\rd_pntr_bin_reg[7] ;
wire wr_clk;
assign out[0] = Q_reg[8];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(D[8]),
.Q(Q_reg[8]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[0]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[0]),
.I3(\rd_pntr_bin_reg[7] [3]),
.O(\rd_pntr_bin_reg[7] [0]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(\rd_pntr_bin_reg[7] [3]),
.O(\rd_pntr_bin_reg[7] [1]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[2]_i_1
(.I0(\rd_pntr_bin_reg[7] [3]),
.I1(Q_reg[2]),
.O(\rd_pntr_bin_reg[7] [2]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[3]_i_1
(.I0(Q_reg[4]),
.I1(Q_reg[8]),
.I2(Q_reg[6]),
.I3(Q_reg[7]),
.I4(Q_reg[5]),
.I5(Q_reg[3]),
.O(\rd_pntr_bin_reg[7] [3]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[4]_i_1
(.I0(Q_reg[5]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[8]),
.I4(Q_reg[4]),
.O(\rd_pntr_bin_reg[7] [4]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[5]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[6]),
.I2(Q_reg[7]),
.I3(Q_reg[5]),
.O(\rd_pntr_bin_reg[7] [5]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[8]),
.O(\rd_pntr_bin_reg[7] [6]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[7]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[8]),
.O(\rd_pntr_bin_reg[7] [7]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module dcfifo_32in_32out_16kb_wr_bin_cntr
(\wr_data_count_i_reg[8] ,
Q,
\wr_data_count_i_reg[7] ,
S,
\gic0.gc0.count_d1_reg[8]_0 ,
v1_reg,
v1_reg_0,
RD_PNTR_WR,
E,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output [0:0]\wr_data_count_i_reg[8] ;
output [8:0]Q;
output [3:0]\wr_data_count_i_reg[7] ;
output [3:0]S;
output [0:0]\gic0.gc0.count_d1_reg[8]_0 ;
output [4:0]v1_reg;
output [3:0]v1_reg_0;
input [8:0]RD_PNTR_WR;
input [0:0]E;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [0:0]E;
wire [8:0]Q;
wire [8:0]RD_PNTR_WR;
wire [3:0]S;
wire \gic0.gc0.count[8]_i_2_n_0 ;
wire [0:0]\gic0.gc0.count_d1_reg[8]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [8:0]p_8_out;
wire [8:0]plusOp__0;
wire [4:0]v1_reg;
wire [3:0]v1_reg_0;
wire wr_clk;
wire [3:0]\wr_data_count_i_reg[7] ;
wire [0:0]\wr_data_count_i_reg[8] ;
wire [7:0]wr_pntr_plus2;
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(wr_pntr_plus2[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(wr_pntr_plus2[1]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[2]),
.I3(wr_pntr_plus2[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(wr_pntr_plus2[2]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[3]),
.I4(wr_pntr_plus2[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(wr_pntr_plus2[3]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[0]),
.I3(wr_pntr_plus2[2]),
.I4(wr_pntr_plus2[4]),
.I5(wr_pntr_plus2[5]),
.O(plusOp__0[5]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count[8]_i_2_n_0 ),
.I1(wr_pntr_plus2[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count[8]_i_2_n_0 ),
.I1(wr_pntr_plus2[6]),
.I2(wr_pntr_plus2[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[8]_i_1
(.I0(wr_pntr_plus2[6]),
.I1(\gic0.gc0.count[8]_i_2_n_0 ),
.I2(wr_pntr_plus2[7]),
.I3(\gic0.gc0.count_d1_reg[8]_0 ),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h8000000000000000))
\gic0.gc0.count[8]_i_2
(.I0(wr_pntr_plus2[5]),
.I1(wr_pntr_plus2[3]),
.I2(wr_pntr_plus2[1]),
.I3(wr_pntr_plus2[0]),
.I4(wr_pntr_plus2[2]),
.I5(wr_pntr_plus2[4]),
.O(\gic0.gc0.count[8]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(wr_pntr_plus2[0]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(p_8_out[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[1]),
.Q(p_8_out[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[2]),
.Q(p_8_out[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[3]),
.Q(p_8_out[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[4]),
.Q(p_8_out[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[5]),
.Q(p_8_out[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[6]),
.Q(p_8_out[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(wr_pntr_plus2[7]),
.Q(p_8_out[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[8]_0 ),
.Q(p_8_out[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(p_8_out[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[0]),
.Q(wr_pntr_plus2[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(wr_pntr_plus2[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[2]),
.Q(wr_pntr_plus2[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[3]),
.Q(wr_pntr_plus2[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[4]),
.Q(wr_pntr_plus2[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[5]),
.Q(wr_pntr_plus2[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[6]),
.Q(wr_pntr_plus2[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[7]),
.Q(wr_pntr_plus2[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[8]),
.Q(\gic0.gc0.count_d1_reg[8]_0 ));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(p_8_out[0]),
.I1(RD_PNTR_WR[0]),
.I2(p_8_out[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(wr_pntr_plus2[0]),
.I1(RD_PNTR_WR[0]),
.I2(wr_pntr_plus2[1]),
.I3(RD_PNTR_WR[1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(p_8_out[2]),
.I1(RD_PNTR_WR[2]),
.I2(p_8_out[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(wr_pntr_plus2[2]),
.I1(RD_PNTR_WR[2]),
.I2(wr_pntr_plus2[3]),
.I3(RD_PNTR_WR[3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(p_8_out[4]),
.I1(RD_PNTR_WR[4]),
.I2(p_8_out[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(wr_pntr_plus2[4]),
.I1(RD_PNTR_WR[4]),
.I2(wr_pntr_plus2[5]),
.I3(RD_PNTR_WR[5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(p_8_out[6]),
.I1(RD_PNTR_WR[6]),
.I2(p_8_out[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(wr_pntr_plus2[6]),
.I1(RD_PNTR_WR[6]),
.I2(wr_pntr_plus2[7]),
.I3(RD_PNTR_WR[7]),
.O(v1_reg_0[3]));
LUT2 #(
.INIT(4'h9))
\gmux.gm[4].gms.ms_i_1
(.I0(p_8_out[8]),
.I1(RD_PNTR_WR[8]),
.O(v1_reg[4]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_10
(.I0(Q[0]),
.I1(RD_PNTR_WR[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_3
(.I0(Q[7]),
.I1(RD_PNTR_WR[7]),
.O(\wr_data_count_i_reg[7] [3]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_4
(.I0(Q[6]),
.I1(RD_PNTR_WR[6]),
.O(\wr_data_count_i_reg[7] [2]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_5
(.I0(Q[5]),
.I1(RD_PNTR_WR[5]),
.O(\wr_data_count_i_reg[7] [1]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_6
(.I0(Q[4]),
.I1(RD_PNTR_WR[4]),
.O(\wr_data_count_i_reg[7] [0]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_7
(.I0(Q[3]),
.I1(RD_PNTR_WR[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_8
(.I0(Q[2]),
.I1(RD_PNTR_WR[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[7]_i_9
(.I0(Q[1]),
.I1(RD_PNTR_WR[1]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[8]_i_2
(.I0(Q[8]),
.I1(RD_PNTR_WR[8]),
.O(\wr_data_count_i_reg[8] ));
endmodule
(* ORIG_REF_NAME = "wr_dc_as" *)
module dcfifo_32in_32out_16kb_wr_dc_as
(wr_data_count,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
Q,
S,
\gic0.gc0.count_d2_reg[7] ,
\gic0.gc0.count_d2_reg[8] );
output [1:0]wr_data_count;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input [7:0]Q;
input [3:0]S;
input [3:0]\gic0.gc0.count_d2_reg[7] ;
input [0:0]\gic0.gc0.count_d2_reg[8] ;
wire [7:0]Q;
wire [3:0]S;
wire [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [0:0]\gic0.gc0.count_d2_reg[8] ;
wire [8:0]minusOp;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire wr_clk;
wire [1:0]wr_data_count;
wire \wr_data_count_i_reg[7]_i_1_n_0 ;
wire \wr_data_count_i_reg[7]_i_1_n_1 ;
wire \wr_data_count_i_reg[7]_i_1_n_2 ;
wire \wr_data_count_i_reg[7]_i_1_n_3 ;
wire \wr_data_count_i_reg[7]_i_2_n_0 ;
wire \wr_data_count_i_reg[7]_i_2_n_1 ;
wire \wr_data_count_i_reg[7]_i_2_n_2 ;
wire \wr_data_count_i_reg[7]_i_2_n_3 ;
wire [3:0]\NLW_wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ;
wire [3:1]\NLW_wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ;
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(minusOp[7]),
.Q(wr_data_count[0]));
CARRY4 \wr_data_count_i_reg[7]_i_1
(.CI(\wr_data_count_i_reg[7]_i_2_n_0 ),
.CO({\wr_data_count_i_reg[7]_i_1_n_0 ,\wr_data_count_i_reg[7]_i_1_n_1 ,\wr_data_count_i_reg[7]_i_1_n_2 ,\wr_data_count_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O(minusOp[7:4]),
.S(\gic0.gc0.count_d2_reg[7] ));
CARRY4 \wr_data_count_i_reg[7]_i_2
(.CI(1'b0),
.CO({\wr_data_count_i_reg[7]_i_2_n_0 ,\wr_data_count_i_reg[7]_i_2_n_1 ,\wr_data_count_i_reg[7]_i_2_n_2 ,\wr_data_count_i_reg[7]_i_2_n_3 }),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O(minusOp[3:0]),
.S(S));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(minusOp[8]),
.Q(wr_data_count[1]));
CARRY4 \wr_data_count_i_reg[8]_i_1
(.CI(\wr_data_count_i_reg[7]_i_1_n_0 ),
.CO(\NLW_wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [3:1],minusOp[8]}),
.S({1'b0,1'b0,1'b0,\gic0.gc0.count_d2_reg[8] }));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module dcfifo_32in_32out_16kb_wr_logic
(full,
WEBWE,
Q,
\gic0.gc0.count_d1_reg[8] ,
wr_data_count,
\rd_pntr_bin_reg[8] ,
wr_clk,
rst_full_ff_i,
wr_en,
RD_PNTR_WR,
rst_full_gen_i,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output full;
output [0:0]WEBWE;
output [8:0]Q;
output [0:0]\gic0.gc0.count_d1_reg[8] ;
output [1:0]wr_data_count;
input [0:0]\rd_pntr_bin_reg[8] ;
input wr_clk;
input rst_full_ff_i;
input wr_en;
input [8:0]RD_PNTR_WR;
input rst_full_gen_i;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [8:0]Q;
wire [8:0]RD_PNTR_WR;
wire [0:0]WEBWE;
wire [4:0]\c1/v1_reg ;
wire [3:0]\c2/v1_reg ;
wire full;
wire [0:0]\gic0.gc0.count_d1_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [0:0]\rd_pntr_bin_reg[8] ;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire wpntr_n_0;
wire wpntr_n_10;
wire wpntr_n_11;
wire wpntr_n_12;
wire wpntr_n_13;
wire wpntr_n_14;
wire wpntr_n_15;
wire wpntr_n_16;
wire wpntr_n_17;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_16kb_wr_dc_as \gwas.gwdc0.wdc
(.Q(Q[7:0]),
.S({wpntr_n_14,wpntr_n_15,wpntr_n_16,wpntr_n_17}),
.\gic0.gc0.count_d2_reg[7] ({wpntr_n_10,wpntr_n_11,wpntr_n_12,wpntr_n_13}),
.\gic0.gc0.count_d2_reg[8] (wpntr_n_0),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count));
dcfifo_32in_32out_16kb_wr_status_flags_as \gwas.wsts
(.E(WEBWE),
.full(full),
.\rd_pntr_bin_reg[8] (\rd_pntr_bin_reg[8] ),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(\c1/v1_reg ),
.v1_reg_0(\c2/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en));
dcfifo_32in_32out_16kb_wr_bin_cntr wpntr
(.E(WEBWE),
.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.S({wpntr_n_14,wpntr_n_15,wpntr_n_16,wpntr_n_17}),
.\gic0.gc0.count_d1_reg[8]_0 (\gic0.gc0.count_d1_reg[8] ),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.v1_reg(\c1/v1_reg ),
.v1_reg_0(\c2/v1_reg ),
.wr_clk(wr_clk),
.\wr_data_count_i_reg[7] ({wpntr_n_10,wpntr_n_11,wpntr_n_12,wpntr_n_13}),
.\wr_data_count_i_reg[8] (wpntr_n_0));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module dcfifo_32in_32out_16kb_wr_status_flags_as
(full,
E,
v1_reg,
v1_reg_0,
\rd_pntr_bin_reg[8] ,
wr_clk,
rst_full_ff_i,
wr_en,
rst_full_gen_i);
output full;
output [0:0]E;
input [4:0]v1_reg;
input [3:0]v1_reg_0;
input [0:0]\rd_pntr_bin_reg[8] ;
input wr_clk;
input rst_full_ff_i;
input wr_en;
input rst_full_gen_i;
wire [0:0]E;
wire comp1;
wire comp2;
wire full;
wire p_1_out;
wire ram_full_i;
wire [0:0]\rd_pntr_bin_reg[8] ;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire [4:0]v1_reg;
wire [3:0]v1_reg_0;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2
(.I0(wr_en),
.I1(p_1_out),
.O(E));
dcfifo_32in_32out_16kb_compare c1
(.comp1(comp1),
.v1_reg(v1_reg));
dcfifo_32in_32out_16kb_compare_0 c2
(.comp2(comp2),
.\rd_pntr_bin_reg[8] (\rd_pntr_bin_reg[8] ),
.v1_reg_0(v1_reg_0));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(p_1_out));
LUT5 #(
.INIT(32'h55550400))
ram_full_i_i_1
(.I0(rst_full_gen_i),
.I1(comp2),
.I2(p_1_out),
.I3(wr_en),
.I4(comp1),
.O(ram_full_i));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
module dut_qa_contents;
reg clk;
reg rst_n;
reg [`WIDTH-1:0] in_data;
reg in_nd;
reg [`MWIDTH-1:0] in_m;
reg [`MSG_WIDTH-1:0] in_msg;
reg in_msg_nd;
wire [`WIDTH-1:0] out_data;
wire out_nd;
wire [`MWIDTH-1:0] out_m;
wire [`MSG_WIDTH-1:0] out_msg;
wire out_msg_nd;
wire error;
initial begin
$from_myhdl(clk, rst_n, in_data, in_nd, in_m, in_msg, in_msg_nd);
$to_myhdl(out_data, out_nd, out_m, out_msg, out_msg_nd, error);
end
qa_contents #(`WIDTH, `MWIDTH) qa_contents_0
(.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nd),
.in_m(in_m),
.in_msg(in_msg),
.in_msg_nd(in_msg_nd),
.out_data(out_data),
.out_nd(out_nd),
.out_m(out_m),
.out_msg(out_msg),
.out_msg_nd(out_msg_nd),
.error(error)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// camctl.v: BCAM Controller //
// //
// Author: Ameer M. S. Abdelhadi ( [email protected] ; [email protected] ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
// Controller / Mealy FSM
module camctl
( input clk , // clock / input
input rst , // global registers reset / input
input wEnb , // CAM write enable / input
input oldPattV , // is old (rewritten) pattern valid? / input from setram
input oldPattMultiOcc, // does old pattern has multi(other)-occurrences? / input from setram
input newPattMultiOcc, // does new pattern has multi(other)-occurrences? / input from setram
input oldEqNewPatt,
output reg wEnb_setram , // write enable to sets RAM / output to setram
output reg wEnb_idxram , // write enable to indices RAM / output to idxram
output reg wEnb_vacram , // write enable to vacancy RAM / output to vacram
output reg wEnb_indc , // write enable / full indicators MLABs / output to iitram9b
output reg wEnb_indx , // write enable / indicator index RAM / output to iitram9b
output reg wEnb_iVld , // write enable / indicator valid RAM / output to iitram9b
output reg wIVld , // write indicator validity / output to iitram9b
output reg oldNewbPattWr ); // old pattern / new pattern (inverted) write / output
// state declaration
reg [1:0] curStt, nxtStt ;
localparam S0 = 2'b00;
localparam S1 = 2'b01;
localparam S2 = 2'b10;
// synchronous process
always @(posedge clk, posedge rst)
if (rst) curStt <= S0 ;
else curStt <= nxtStt;
// combinatorial process
always @(*) begin
{wEnb_setram,wEnb_idxram,wEnb_vacram,wEnb_indc,wEnb_indx,wEnb_iVld,wIVld,oldNewbPattWr} = 8'h00;
case (curStt)
S0: nxtStt = wEnb?S1:S0; // idle; read RAM and generate status
S1: begin // delete old pattern
nxtStt = S2 ;
wEnb_indc = !(oldEqNewPatt && oldPattV) && oldPattV && oldPattMultiOcc;
wEnb_iVld = !(oldEqNewPatt && oldPattV) && oldPattV && !oldPattMultiOcc;
oldNewbPattWr = oldPattV ;
end
S2: begin // write new pattarn
nxtStt = S0 ;
wEnb_setram = !(oldEqNewPatt && oldPattV) && 1'b1 ;
// wEnb_idxram = !newPattMultiOcc ;
wEnb_idxram = !(oldEqNewPatt && oldPattV) && 1'b1 ;
wEnb_vacram = !(oldEqNewPatt && oldPattV) && (oldPattV && !oldPattMultiOcc) || !newPattMultiOcc;
wEnb_indc = !(oldEqNewPatt && oldPattV) && 1'b1 ;
wEnb_indx = !(oldEqNewPatt && oldPattV) && !newPattMultiOcc ;
wEnb_iVld = !(oldEqNewPatt && oldPattV) && !newPattMultiOcc ;
wIVld = 1'b1 ;
oldNewbPattWr = 1'b0 ;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__FAH_BEHAVIORAL_PP_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__fah (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
// Local signals
wire xor0_out_SUM ;
wire u_vpwr_vgnd0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT ;
wire u_vpwr_vgnd1_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_SUM , xor0_out_SUM, VPWR, VGND);
buf buf0 (SUM , u_vpwr_vgnd0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT , a_b, a_ci, b_ci );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_COUT, or0_out_COUT, VPWR, VGND);
buf buf1 (COUT , u_vpwr_vgnd1_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_BEHAVIORAL_PP_V
|
// soc_system_mm_interconnect_1.v
// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.06.17.12:43:17
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_1 (
output wire [7:0] hps_0_f2h_axi_slave_awid, // hps_0_f2h_axi_slave.awid
output wire [31:0] hps_0_f2h_axi_slave_awaddr, // .awaddr
output wire [3:0] hps_0_f2h_axi_slave_awlen, // .awlen
output wire [2:0] hps_0_f2h_axi_slave_awsize, // .awsize
output wire [1:0] hps_0_f2h_axi_slave_awburst, // .awburst
output wire [1:0] hps_0_f2h_axi_slave_awlock, // .awlock
output wire [3:0] hps_0_f2h_axi_slave_awcache, // .awcache
output wire [2:0] hps_0_f2h_axi_slave_awprot, // .awprot
output wire [4:0] hps_0_f2h_axi_slave_awuser, // .awuser
output wire hps_0_f2h_axi_slave_awvalid, // .awvalid
input wire hps_0_f2h_axi_slave_awready, // .awready
output wire [7:0] hps_0_f2h_axi_slave_wid, // .wid
output wire [63:0] hps_0_f2h_axi_slave_wdata, // .wdata
output wire [7:0] hps_0_f2h_axi_slave_wstrb, // .wstrb
output wire hps_0_f2h_axi_slave_wlast, // .wlast
output wire hps_0_f2h_axi_slave_wvalid, // .wvalid
input wire hps_0_f2h_axi_slave_wready, // .wready
input wire [7:0] hps_0_f2h_axi_slave_bid, // .bid
input wire [1:0] hps_0_f2h_axi_slave_bresp, // .bresp
input wire hps_0_f2h_axi_slave_bvalid, // .bvalid
output wire hps_0_f2h_axi_slave_bready, // .bready
output wire [7:0] hps_0_f2h_axi_slave_arid, // .arid
output wire [31:0] hps_0_f2h_axi_slave_araddr, // .araddr
output wire [3:0] hps_0_f2h_axi_slave_arlen, // .arlen
output wire [2:0] hps_0_f2h_axi_slave_arsize, // .arsize
output wire [1:0] hps_0_f2h_axi_slave_arburst, // .arburst
output wire [1:0] hps_0_f2h_axi_slave_arlock, // .arlock
output wire [3:0] hps_0_f2h_axi_slave_arcache, // .arcache
output wire [2:0] hps_0_f2h_axi_slave_arprot, // .arprot
output wire [4:0] hps_0_f2h_axi_slave_aruser, // .aruser
output wire hps_0_f2h_axi_slave_arvalid, // .arvalid
input wire hps_0_f2h_axi_slave_arready, // .arready
input wire [7:0] hps_0_f2h_axi_slave_rid, // .rid
input wire [63:0] hps_0_f2h_axi_slave_rdata, // .rdata
input wire [1:0] hps_0_f2h_axi_slave_rresp, // .rresp
input wire hps_0_f2h_axi_slave_rlast, // .rlast
input wire hps_0_f2h_axi_slave_rvalid, // .rvalid
output wire hps_0_f2h_axi_slave_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
input wire master_secure_clk_reset_reset_bridge_in_reset_reset, // master_secure_clk_reset_reset_bridge_in_reset.reset
input wire master_secure_master_translator_reset_reset_bridge_in_reset_reset, // master_secure_master_translator_reset_reset_bridge_in_reset.reset
input wire [31:0] master_secure_master_address, // master_secure_master.address
output wire master_secure_master_waitrequest, // .waitrequest
input wire [3:0] master_secure_master_byteenable, // .byteenable
input wire master_secure_master_read, // .read
output wire [31:0] master_secure_master_readdata, // .readdata
output wire master_secure_master_readdatavalid, // .readdatavalid
input wire master_secure_master_write, // .write
input wire [31:0] master_secure_master_writedata // .writedata
);
wire master_secure_master_translator_avalon_universal_master_0_waitrequest; // master_secure_master_translator_avalon_universal_master_0_agent:av_waitrequest -> master_secure_master_translator:uav_waitrequest
wire [2:0] master_secure_master_translator_avalon_universal_master_0_burstcount; // master_secure_master_translator:uav_burstcount -> master_secure_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] master_secure_master_translator_avalon_universal_master_0_writedata; // master_secure_master_translator:uav_writedata -> master_secure_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] master_secure_master_translator_avalon_universal_master_0_address; // master_secure_master_translator:uav_address -> master_secure_master_translator_avalon_universal_master_0_agent:av_address
wire master_secure_master_translator_avalon_universal_master_0_lock; // master_secure_master_translator:uav_lock -> master_secure_master_translator_avalon_universal_master_0_agent:av_lock
wire master_secure_master_translator_avalon_universal_master_0_write; // master_secure_master_translator:uav_write -> master_secure_master_translator_avalon_universal_master_0_agent:av_write
wire master_secure_master_translator_avalon_universal_master_0_read; // master_secure_master_translator:uav_read -> master_secure_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] master_secure_master_translator_avalon_universal_master_0_readdata; // master_secure_master_translator_avalon_universal_master_0_agent:av_readdata -> master_secure_master_translator:uav_readdata
wire master_secure_master_translator_avalon_universal_master_0_debugaccess; // master_secure_master_translator:uav_debugaccess -> master_secure_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] master_secure_master_translator_avalon_universal_master_0_byteenable; // master_secure_master_translator:uav_byteenable -> master_secure_master_translator_avalon_universal_master_0_agent:av_byteenable
wire master_secure_master_translator_avalon_universal_master_0_readdatavalid; // master_secure_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> master_secure_master_translator:uav_readdatavalid
wire master_secure_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // master_secure_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire master_secure_master_translator_avalon_universal_master_0_agent_cp_valid; // master_secure_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire master_secure_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // master_secure_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [117:0] master_secure_master_translator_avalon_universal_master_0_agent_cp_data; // master_secure_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire master_secure_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> master_secure_master_translator_avalon_universal_master_0_agent:cp_ready
wire hps_0_f2h_axi_slave_agent_write_rp_endofpacket; // hps_0_f2h_axi_slave_agent:write_rp_endofpacket -> id_router:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_write_rp_valid; // hps_0_f2h_axi_slave_agent:write_rp_valid -> id_router:sink_valid
wire hps_0_f2h_axi_slave_agent_write_rp_startofpacket; // hps_0_f2h_axi_slave_agent:write_rp_startofpacket -> id_router:sink_startofpacket
wire [153:0] hps_0_f2h_axi_slave_agent_write_rp_data; // hps_0_f2h_axi_slave_agent:write_rp_data -> id_router:sink_data
wire hps_0_f2h_axi_slave_agent_write_rp_ready; // id_router:sink_ready -> hps_0_f2h_axi_slave_agent:write_rp_ready
wire hps_0_f2h_axi_slave_agent_read_rp_endofpacket; // hps_0_f2h_axi_slave_agent:read_rp_endofpacket -> id_router_001:sink_endofpacket
wire hps_0_f2h_axi_slave_agent_read_rp_valid; // hps_0_f2h_axi_slave_agent:read_rp_valid -> id_router_001:sink_valid
wire hps_0_f2h_axi_slave_agent_read_rp_startofpacket; // hps_0_f2h_axi_slave_agent:read_rp_startofpacket -> id_router_001:sink_startofpacket
wire [153:0] hps_0_f2h_axi_slave_agent_read_rp_data; // hps_0_f2h_axi_slave_agent:read_rp_data -> id_router_001:sink_data
wire hps_0_f2h_axi_slave_agent_read_rp_ready; // id_router_001:sink_ready -> hps_0_f2h_axi_slave_agent:read_rp_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [117:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [1:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [117:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [1:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [117:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [1:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> master_secure_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> master_secure_master_translator_avalon_universal_master_0_agent:rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> master_secure_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [117:0] limiter_rsp_src_data; // limiter:rsp_src_data -> master_secure_master_translator_avalon_universal_master_0_agent:rp_data
wire [1:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> master_secure_master_translator_avalon_universal_master_0_agent:rp_channel
wire limiter_rsp_src_ready; // master_secure_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [117:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [1:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [117:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [1:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [117:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [1:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [117:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [1:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> width_adapter:in_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> width_adapter:in_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> width_adapter:in_startofpacket
wire [117:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> width_adapter:in_data
wire [1:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> width_adapter:in_channel
wire cmd_xbar_mux_src_ready; // width_adapter:in_ready -> cmd_xbar_mux:src_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> hps_0_f2h_axi_slave_agent:write_cp_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> hps_0_f2h_axi_slave_agent:write_cp_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> hps_0_f2h_axi_slave_agent:write_cp_startofpacket
wire [153:0] width_adapter_src_data; // width_adapter:out_data -> hps_0_f2h_axi_slave_agent:write_cp_data
wire width_adapter_src_ready; // hps_0_f2h_axi_slave_agent:write_cp_ready -> width_adapter:out_ready
wire [1:0] width_adapter_src_channel; // width_adapter:out_channel -> hps_0_f2h_axi_slave_agent:write_cp_channel
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> width_adapter_001:in_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> width_adapter_001:in_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> width_adapter_001:in_startofpacket
wire [117:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> width_adapter_001:in_data
wire [1:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> width_adapter_001:in_channel
wire cmd_xbar_mux_001_src_ready; // width_adapter_001:in_ready -> cmd_xbar_mux_001:src_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> hps_0_f2h_axi_slave_agent:read_cp_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> hps_0_f2h_axi_slave_agent:read_cp_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> hps_0_f2h_axi_slave_agent:read_cp_startofpacket
wire [153:0] width_adapter_001_src_data; // width_adapter_001:out_data -> hps_0_f2h_axi_slave_agent:read_cp_data
wire width_adapter_001_src_ready; // hps_0_f2h_axi_slave_agent:read_cp_ready -> width_adapter_001:out_ready
wire [1:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> hps_0_f2h_axi_slave_agent:read_cp_channel
wire id_router_src_endofpacket; // id_router:src_endofpacket -> width_adapter_002:in_endofpacket
wire id_router_src_valid; // id_router:src_valid -> width_adapter_002:in_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> width_adapter_002:in_startofpacket
wire [153:0] id_router_src_data; // id_router:src_data -> width_adapter_002:in_data
wire [1:0] id_router_src_channel; // id_router:src_channel -> width_adapter_002:in_channel
wire id_router_src_ready; // width_adapter_002:in_ready -> id_router:src_ready
wire width_adapter_002_src_endofpacket; // width_adapter_002:out_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire width_adapter_002_src_valid; // width_adapter_002:out_valid -> rsp_xbar_demux:sink_valid
wire width_adapter_002_src_startofpacket; // width_adapter_002:out_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [117:0] width_adapter_002_src_data; // width_adapter_002:out_data -> rsp_xbar_demux:sink_data
wire width_adapter_002_src_ready; // rsp_xbar_demux:sink_ready -> width_adapter_002:out_ready
wire [1:0] width_adapter_002_src_channel; // width_adapter_002:out_channel -> rsp_xbar_demux:sink_channel
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> width_adapter_003:in_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> width_adapter_003:in_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> width_adapter_003:in_startofpacket
wire [153:0] id_router_001_src_data; // id_router_001:src_data -> width_adapter_003:in_data
wire [1:0] id_router_001_src_channel; // id_router_001:src_channel -> width_adapter_003:in_channel
wire id_router_001_src_ready; // width_adapter_003:in_ready -> id_router_001:src_ready
wire width_adapter_003_src_endofpacket; // width_adapter_003:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire width_adapter_003_src_valid; // width_adapter_003:out_valid -> rsp_xbar_demux_001:sink_valid
wire width_adapter_003_src_startofpacket; // width_adapter_003:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [117:0] width_adapter_003_src_data; // width_adapter_003:out_data -> rsp_xbar_demux_001:sink_data
wire width_adapter_003_src_ready; // rsp_xbar_demux_001:sink_ready -> width_adapter_003:out_ready
wire [1:0] width_adapter_003_src_channel; // width_adapter_003:out_channel -> rsp_xbar_demux_001:sink_channel
wire [1:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) master_secure_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (master_secure_master_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (master_secure_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (master_secure_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (master_secure_master_translator_avalon_universal_master_0_read), // .read
.uav_write (master_secure_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (master_secure_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (master_secure_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (master_secure_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (master_secure_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (master_secure_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (master_secure_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (master_secure_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (master_secure_master_address), // avalon_anti_master_0.address
.av_waitrequest (master_secure_master_waitrequest), // .waitrequest
.av_byteenable (master_secure_master_byteenable), // .byteenable
.av_read (master_secure_master_read), // .read
.av_readdata (master_secure_master_readdata), // .readdata
.av_readdatavalid (master_secure_master_readdatavalid), // .readdatavalid
.av_write (master_secure_master_write), // .write
.av_writedata (master_secure_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (108),
.PKT_PROTECTION_L (106),
.PKT_BEGIN_BURST (101),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (82),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (103),
.PKT_SRC_ID_L (103),
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (104),
.PKT_THREAD_ID_H (105),
.PKT_THREAD_ID_L (105),
.PKT_CACHE_H (112),
.PKT_CACHE_L (109),
.PKT_DATA_SIDEBAND_H (100),
.PKT_DATA_SIDEBAND_L (100),
.PKT_QOS_H (102),
.PKT_QOS_L (102),
.PKT_ADDR_SIDEBAND_H (99),
.PKT_ADDR_SIDEBAND_L (95),
.PKT_RESPONSE_STATUS_H (114),
.PKT_RESPONSE_STATUS_L (113),
.PKT_ORI_BURST_SIZE_L (115),
.PKT_ORI_BURST_SIZE_H (117),
.ST_DATA_W (118),
.ST_CHANNEL_W (2),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (255),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) master_secure_master_translator_avalon_universal_master_0_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (master_secure_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (master_secure_master_translator_avalon_universal_master_0_address), // av.address
.av_write (master_secure_master_translator_avalon_universal_master_0_write), // .write
.av_read (master_secure_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (master_secure_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (master_secure_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (master_secure_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (master_secure_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (master_secure_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (master_secure_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (master_secure_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (master_secure_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (master_secure_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (master_secure_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (master_secure_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (master_secure_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (master_secure_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (limiter_rsp_src_valid), // rp.valid
.rp_data (limiter_rsp_src_data), // .data
.rp_channel (limiter_rsp_src_channel), // .channel
.rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_axi_slave_ni #(
.PKT_QOS_H (138),
.PKT_QOS_L (138),
.PKT_THREAD_ID_H (141),
.PKT_THREAD_ID_L (141),
.PKT_RESPONSE_STATUS_H (150),
.PKT_RESPONSE_STATUS_L (149),
.PKT_BEGIN_BURST (137),
.PKT_CACHE_H (148),
.PKT_CACHE_L (145),
.PKT_DATA_SIDEBAND_H (136),
.PKT_DATA_SIDEBAND_L (136),
.PKT_ADDR_SIDEBAND_H (135),
.PKT_ADDR_SIDEBAND_L (131),
.PKT_BURST_TYPE_H (130),
.PKT_BURST_TYPE_L (129),
.PKT_PROTECTION_H (144),
.PKT_PROTECTION_L (142),
.PKT_BURST_SIZE_H (128),
.PKT_BURST_SIZE_L (126),
.PKT_BURSTWRAP_H (125),
.PKT_BURSTWRAP_L (118),
.PKT_BYTE_CNT_H (117),
.PKT_BYTE_CNT_L (110),
.PKT_ADDR_H (103),
.PKT_ADDR_L (72),
.PKT_TRANS_EXCLUSIVE (109),
.PKT_TRANS_LOCK (108),
.PKT_TRANS_COMPRESSED_READ (104),
.PKT_TRANS_POSTED (105),
.PKT_TRANS_WRITE (106),
.PKT_TRANS_READ (107),
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_SRC_ID_H (139),
.PKT_SRC_ID_L (139),
.PKT_DEST_ID_H (140),
.PKT_DEST_ID_L (140),
.PKT_ORI_BURST_SIZE_L (151),
.PKT_ORI_BURST_SIZE_H (153),
.ADDR_USER_WIDTH (5),
.DATA_USER_WIDTH (1),
.ST_DATA_W (154),
.ADDR_WIDTH (32),
.RDATA_WIDTH (64),
.WDATA_WIDTH (64),
.ST_CHANNEL_W (2),
.AXI_SLAVE_ID_W (8),
.PASS_ID_TO_SLAVE (1),
.AXI_VERSION ("AXI3"),
.WRITE_ACCEPTANCE_CAPABILITY (8),
.READ_ACCEPTANCE_CAPABILITY (8)
) hps_0_f2h_axi_slave_agent (
.aclk (clk_0_clk_clk), // clock_sink.clk
.aresetn (~hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // reset_sink.reset_n
.read_cp_valid (width_adapter_001_src_valid), // read_cp.valid
.read_cp_ready (width_adapter_001_src_ready), // .ready
.read_cp_data (width_adapter_001_src_data), // .data
.read_cp_channel (width_adapter_001_src_channel), // .channel
.read_cp_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.read_cp_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.write_cp_ready (width_adapter_src_ready), // write_cp.ready
.write_cp_valid (width_adapter_src_valid), // .valid
.write_cp_data (width_adapter_src_data), // .data
.write_cp_channel (width_adapter_src_channel), // .channel
.write_cp_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.write_cp_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.read_rp_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // read_rp.ready
.read_rp_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.read_rp_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.read_rp_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.write_rp_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // write_rp.ready
.write_rp_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.write_rp_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.write_rp_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.awid (hps_0_f2h_axi_slave_awid), // altera_axi_master.awid
.awaddr (hps_0_f2h_axi_slave_awaddr), // .awaddr
.awlen (hps_0_f2h_axi_slave_awlen), // .awlen
.awsize (hps_0_f2h_axi_slave_awsize), // .awsize
.awburst (hps_0_f2h_axi_slave_awburst), // .awburst
.awlock (hps_0_f2h_axi_slave_awlock), // .awlock
.awcache (hps_0_f2h_axi_slave_awcache), // .awcache
.awprot (hps_0_f2h_axi_slave_awprot), // .awprot
.awuser (hps_0_f2h_axi_slave_awuser), // .awuser
.awvalid (hps_0_f2h_axi_slave_awvalid), // .awvalid
.awready (hps_0_f2h_axi_slave_awready), // .awready
.wid (hps_0_f2h_axi_slave_wid), // .wid
.wdata (hps_0_f2h_axi_slave_wdata), // .wdata
.wstrb (hps_0_f2h_axi_slave_wstrb), // .wstrb
.wlast (hps_0_f2h_axi_slave_wlast), // .wlast
.wvalid (hps_0_f2h_axi_slave_wvalid), // .wvalid
.wready (hps_0_f2h_axi_slave_wready), // .wready
.bid (hps_0_f2h_axi_slave_bid), // .bid
.bresp (hps_0_f2h_axi_slave_bresp), // .bresp
.bvalid (hps_0_f2h_axi_slave_bvalid), // .bvalid
.bready (hps_0_f2h_axi_slave_bready), // .bready
.arid (hps_0_f2h_axi_slave_arid), // .arid
.araddr (hps_0_f2h_axi_slave_araddr), // .araddr
.arlen (hps_0_f2h_axi_slave_arlen), // .arlen
.arsize (hps_0_f2h_axi_slave_arsize), // .arsize
.arburst (hps_0_f2h_axi_slave_arburst), // .arburst
.arlock (hps_0_f2h_axi_slave_arlock), // .arlock
.arcache (hps_0_f2h_axi_slave_arcache), // .arcache
.arprot (hps_0_f2h_axi_slave_arprot), // .arprot
.aruser (hps_0_f2h_axi_slave_aruser), // .aruser
.arvalid (hps_0_f2h_axi_slave_arvalid), // .arvalid
.arready (hps_0_f2h_axi_slave_arready), // .arready
.rid (hps_0_f2h_axi_slave_rid), // .rid
.rdata (hps_0_f2h_axi_slave_rdata), // .rdata
.rresp (hps_0_f2h_axi_slave_rresp), // .rresp
.rlast (hps_0_f2h_axi_slave_rlast), // .rlast
.rvalid (hps_0_f2h_axi_slave_rvalid), // .rvalid
.rready (hps_0_f2h_axi_slave_rready) // .rready
);
soc_system_mm_interconnect_1_addr_router addr_router (
.sink_ready (master_secure_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (master_secure_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (master_secure_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (master_secure_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (master_secure_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (master_secure_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_id_router id_router (
.sink_ready (hps_0_f2h_axi_slave_agent_write_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_write_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_write_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_write_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_write_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_id_router id_router_001 (
.sink_ready (hps_0_f2h_axi_slave_agent_read_rp_ready), // sink.ready
.sink_valid (hps_0_f2h_axi_slave_agent_read_rp_valid), // .valid
.sink_data (hps_0_f2h_axi_slave_agent_read_rp_data), // .data
.sink_startofpacket (hps_0_f2h_axi_slave_agent_read_rp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_f2h_axi_slave_agent_read_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (104),
.PKT_DEST_ID_L (104),
.PKT_SRC_ID_H (103),
.PKT_SRC_ID_L (103),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (16),
.PIPELINED (0),
.ST_DATA_W (118),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (1),
.PKT_BYTE_CNT_H (81),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (master_secure_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
soc_system_mm_interconnect_1_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (master_secure_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (width_adapter_002_src_ready), // sink.ready
.sink_channel (width_adapter_002_src_channel), // .channel
.sink_data (width_adapter_002_src_data), // .data
.sink_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_002_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (width_adapter_003_src_ready), // sink.ready
.sink_channel (width_adapter_003_src_channel), // .channel
.sink_data (width_adapter_003_src_data), // .data
.sink_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_003_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_1_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (master_secure_master_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (81),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (89),
.IN_PKT_BURSTWRAP_L (82),
.IN_PKT_BURST_SIZE_H (92),
.IN_PKT_BURST_SIZE_L (90),
.IN_PKT_RESPONSE_STATUS_H (114),
.IN_PKT_RESPONSE_STATUS_L (113),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (94),
.IN_PKT_BURST_TYPE_L (93),
.IN_PKT_ORI_BURST_SIZE_L (115),
.IN_PKT_ORI_BURST_SIZE_H (117),
.IN_ST_DATA_W (118),
.OUT_PKT_ADDR_H (103),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (117),
.OUT_PKT_BYTE_CNT_L (110),
.OUT_PKT_TRANS_COMPRESSED_READ (104),
.OUT_PKT_BURST_SIZE_H (128),
.OUT_PKT_BURST_SIZE_L (126),
.OUT_PKT_RESPONSE_STATUS_H (150),
.OUT_PKT_RESPONSE_STATUS_L (149),
.OUT_PKT_TRANS_EXCLUSIVE (109),
.OUT_PKT_BURST_TYPE_H (130),
.OUT_PKT_BURST_TYPE_L (129),
.OUT_PKT_ORI_BURST_SIZE_L (151),
.OUT_PKT_ORI_BURST_SIZE_H (153),
.OUT_ST_DATA_W (154),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0)
) width_adapter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_src_ready), // .ready
.in_data (cmd_xbar_mux_src_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (81),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (89),
.IN_PKT_BURSTWRAP_L (82),
.IN_PKT_BURST_SIZE_H (92),
.IN_PKT_BURST_SIZE_L (90),
.IN_PKT_RESPONSE_STATUS_H (114),
.IN_PKT_RESPONSE_STATUS_L (113),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (94),
.IN_PKT_BURST_TYPE_L (93),
.IN_PKT_ORI_BURST_SIZE_L (115),
.IN_PKT_ORI_BURST_SIZE_H (117),
.IN_ST_DATA_W (118),
.OUT_PKT_ADDR_H (103),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (117),
.OUT_PKT_BYTE_CNT_L (110),
.OUT_PKT_TRANS_COMPRESSED_READ (104),
.OUT_PKT_BURST_SIZE_H (128),
.OUT_PKT_BURST_SIZE_L (126),
.OUT_PKT_RESPONSE_STATUS_H (150),
.OUT_PKT_RESPONSE_STATUS_L (149),
.OUT_PKT_TRANS_EXCLUSIVE (109),
.OUT_PKT_BURST_TYPE_H (130),
.OUT_PKT_BURST_TYPE_L (129),
.OUT_PKT_ORI_BURST_SIZE_L (151),
.OUT_PKT_ORI_BURST_SIZE_H (153),
.OUT_ST_DATA_W (154),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (0),
.PACKING (0)
) width_adapter_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_001_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_001_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_001_src_ready), // .ready
.in_data (cmd_xbar_mux_001_src_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (103),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (117),
.IN_PKT_BYTE_CNT_L (110),
.IN_PKT_TRANS_COMPRESSED_READ (104),
.IN_PKT_BURSTWRAP_H (125),
.IN_PKT_BURSTWRAP_L (118),
.IN_PKT_BURST_SIZE_H (128),
.IN_PKT_BURST_SIZE_L (126),
.IN_PKT_RESPONSE_STATUS_H (150),
.IN_PKT_RESPONSE_STATUS_L (149),
.IN_PKT_TRANS_EXCLUSIVE (109),
.IN_PKT_BURST_TYPE_H (130),
.IN_PKT_BURST_TYPE_L (129),
.IN_PKT_ORI_BURST_SIZE_L (151),
.IN_PKT_ORI_BURST_SIZE_H (153),
.IN_ST_DATA_W (154),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (81),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (92),
.OUT_PKT_BURST_SIZE_L (90),
.OUT_PKT_RESPONSE_STATUS_H (114),
.OUT_PKT_RESPONSE_STATUS_L (113),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (94),
.OUT_PKT_BURST_TYPE_L (93),
.OUT_PKT_ORI_BURST_SIZE_L (115),
.OUT_PKT_ORI_BURST_SIZE_H (117),
.OUT_ST_DATA_W (118),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1)
) width_adapter_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (id_router_src_valid), // sink.valid
.in_channel (id_router_src_channel), // .channel
.in_startofpacket (id_router_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_src_endofpacket), // .endofpacket
.in_ready (id_router_src_ready), // .ready
.in_data (id_router_src_data), // .data
.out_endofpacket (width_adapter_002_src_endofpacket), // src.endofpacket
.out_data (width_adapter_002_src_data), // .data
.out_channel (width_adapter_002_src_channel), // .channel
.out_valid (width_adapter_002_src_valid), // .valid
.out_ready (width_adapter_002_src_ready), // .ready
.out_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (103),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (117),
.IN_PKT_BYTE_CNT_L (110),
.IN_PKT_TRANS_COMPRESSED_READ (104),
.IN_PKT_BURSTWRAP_H (125),
.IN_PKT_BURSTWRAP_L (118),
.IN_PKT_BURST_SIZE_H (128),
.IN_PKT_BURST_SIZE_L (126),
.IN_PKT_RESPONSE_STATUS_H (150),
.IN_PKT_RESPONSE_STATUS_L (149),
.IN_PKT_TRANS_EXCLUSIVE (109),
.IN_PKT_BURST_TYPE_H (130),
.IN_PKT_BURST_TYPE_L (129),
.IN_PKT_ORI_BURST_SIZE_L (151),
.IN_PKT_ORI_BURST_SIZE_H (153),
.IN_ST_DATA_W (154),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (81),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (92),
.OUT_PKT_BURST_SIZE_L (90),
.OUT_PKT_RESPONSE_STATUS_H (114),
.OUT_PKT_RESPONSE_STATUS_L (113),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (94),
.OUT_PKT_BURST_TYPE_L (93),
.OUT_PKT_ORI_BURST_SIZE_L (115),
.OUT_PKT_ORI_BURST_SIZE_H (117),
.OUT_ST_DATA_W (118),
.ST_CHANNEL_W (2),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (0),
.PACKING (1)
) width_adapter_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (id_router_001_src_valid), // sink.valid
.in_channel (id_router_001_src_channel), // .channel
.in_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.in_ready (id_router_001_src_ready), // .ready
.in_data (id_router_001_src_data), // .data
.out_endofpacket (width_adapter_003_src_endofpacket), // src.endofpacket
.out_data (width_adapter_003_src_data), // .data
.out_channel (width_adapter_003_src_channel), // .channel
.out_valid (width_adapter_003_src_valid), // .valid
.out_ready (width_adapter_003_src_ready), // .ready
.out_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_oqctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`define ACK_IDLE 0
`define ACK_WAIT 1
`define ACK_CCX_REQ 2
`include "iop.h"
`include "sctag.h"
module sctag_oqctl(/*AUTOARG*/
// Outputs
so, sctag_cpx_req_cq, sctag_cpx_atom_cq, oqctl_diag_acc_c8,
oqctl_rqtyp_rtn_c7, oqctl_cerr_ack_c7, oqctl_uerr_ack_c7,
str_ld_hit_c7, fwd_req_ret_c7, atm_inst_ack_c7, strst_ack_c7,
oqctl_int_ack_c7, oqctl_imiss_hit_c8, oqctl_pf_ack_c7,
oqctl_rmo_st_c7, oqctl_l2_miss_c7, mux1_sel_data_c7,
mux_csr_sel_c7, sel_inval_c7, out_mux1_sel_c7, out_mux2_sel_c7,
sel_array_out_l, sel_mux1_c6, sel_mux2_c6, sel_mux3_c6,
mux_vec_sel_c6, oqarray_wr_en, oqarray_rd_en, oqarray_wr_ptr,
oqarray_rd_ptr, oqctl_arbctl_full_px2, oqctl_st_complete_c7,
// Inputs
arbdp_cpuid_c5, arbdp_int_bcast_c5, decdp_strld_inst_c6,
decdp_atm_inst_c6, decdp_pf_inst_c5, arbctl_evict_c5,
dirdp_req_vec_c6, tagctl_imiss_hit_c5, tagctl_ld_hit_c5,
tagctl_nonmem_comp_c6, tagctl_st_ack_c5, tagctl_strst_ack_c5,
tagctl_uerr_ack_c5, tagctl_cerr_ack_c5, tagctl_int_ack_c5,
tagctl_st_req_c5, tagctl_fwd_req_ret_c5, sel_rdma_inval_vec_c5,
tagctl_rdma_wr_comp_c4, tagctl_store_inst_c5,
tagctl_fwd_req_ld_c6, tagctl_rmo_st_ack_c5, tagctl_inst_mb_c5,
tagctl_hit_c5, arbctl_inst_l2data_vld_c6,
arbctl_inst_l2tag_vld_c6, arbctl_inst_l2vuad_vld_c6,
arbctl_csr_rd_en_c7, lkup_bank_ena_dcd_c4, lkup_bank_ena_icd_c4,
rst_tri_en, sehold, cpx_sctag_grant_cx, arst_l, grst_l, si, se,
rclk
);
// from arbdecdp
input [2:0] arbdp_cpuid_c5; // account for fwd_req cpuid
input arbdp_int_bcast_c5;
input decdp_strld_inst_c6;
input decdp_atm_inst_c6;
input decdp_pf_inst_c5; // NEW_PIN from arbdec
// from arbctl.
input arbctl_evict_c5;
input [7:0] dirdp_req_vec_c6;
// from tagctl.
input tagctl_imiss_hit_c5;
input tagctl_ld_hit_c5;
input tagctl_nonmem_comp_c6;
input tagctl_st_ack_c5;
input tagctl_strst_ack_c5;
input tagctl_uerr_ack_c5;
input tagctl_cerr_ack_c5;
input tagctl_int_ack_c5;
input tagctl_st_req_c5;
input tagctl_fwd_req_ret_c5; // tells oqctl to send a req 2 cycles later.
//input tagctl_fwd_req_in_c5;
input sel_rdma_inval_vec_c5;
input tagctl_rdma_wr_comp_c4;
input tagctl_store_inst_c5;
input tagctl_fwd_req_ld_c6;
input tagctl_rmo_st_ack_c5; // NEW_PIN from tagctl
input tagctl_inst_mb_c5; // NEW_PIN from tagctl.
input tagctl_hit_c5; // NEW_PIN from tagctl.
// from arbctl.
input arbctl_inst_l2data_vld_c6;
input arbctl_inst_l2tag_vld_c6;
input arbctl_inst_l2vuad_vld_c6;
input arbctl_csr_rd_en_c7;
input [3:0] lkup_bank_ena_dcd_c4;
input [3:0] lkup_bank_ena_icd_c4;
input rst_tri_en;
input sehold ; // NEW PIN POST_4.2
// from cpx
input [7:0] cpx_sctag_grant_cx;
input arst_l, grst_l;
input si, se;
input rclk;
output so;
// cpx
output [7:0] sctag_cpx_req_cq ;
output sctag_cpx_atom_cq;
// to oqdp.
output oqctl_diag_acc_c8;
output [3:0] oqctl_rqtyp_rtn_c7;
output oqctl_cerr_ack_c7 ;
output oqctl_uerr_ack_c7 ;
output str_ld_hit_c7;
output fwd_req_ret_c7;
output atm_inst_ack_c7;
output strst_ack_c7;
output oqctl_int_ack_c7;
output oqctl_imiss_hit_c8;
output oqctl_pf_ack_c7; // NEW_PIN to oqdp.
output oqctl_rmo_st_c7; // NEW_PIN to oqdp
output oqctl_l2_miss_c7; // NEW_PIN to oqdp
// mux selects to oqdp
output [3:0] mux1_sel_data_c7;
output mux_csr_sel_c7;
output sel_inval_c7;
output [2:0] out_mux1_sel_c7; // sel for mux1 // new_pin POST_3.3 advanced to C7
output [2:0] out_mux2_sel_c7; // sel for mux2 // new_pin POST_3.3 advanced to C7
output sel_array_out_l; // NEW_PIN
// outputs going to dirvec_dp
output [3:0] sel_mux1_c6;
output [3:0] sel_mux2_c6;
output sel_mux3_c6;
output [3:0] mux_vec_sel_c6;
// to oq array.
output oqarray_wr_en;
output oqarray_rd_en;
output [3:0] oqarray_wr_ptr;
output [3:0] oqarray_rd_ptr;
// to arbctl
output oqctl_arbctl_full_px2;
// to tagctl
output oqctl_st_complete_c7;
wire int_bcast_c5, int_bcast_c6;
wire [7:0] dec_cpu_c5, dec_cpu_c6, dec_cpu_c7;
wire sel_stinv_req_c5, sel_stinv_req_c6;
wire sel_inv_vec_c5, sel_inv_vec_c6 ;
wire sel_dec_vec_c5, sel_dec_vec_c5_d1;
wire sel_dec_vec_c6, sel_dec_vec_c6_d1;
wire [7:0] inval_vec_c6;
wire [3:0] sel_req_out_c6;
wire [7:0] req_out_c6, req_out_c7;
wire imiss1_out_c6, imiss1_out_c7, imiss1_out_c8;
wire imiss2_out_c6, imiss2_out_c7;
wire [7:0] imiss2_req_vec_c6, imiss2_req_vec_c7;
wire c6_req_vld, c7_req_vld;
wire sel_c7_req, sel_c7_req_d1 ;
wire old_req_vld_d1, oq_count_nonzero_d1;
wire mux1_sel_c7_req, mux1_sel_dec_vec_c6;
wire mux1_sel_def_c6, mux1_sel_dec_vec_c7;
wire imiss1_to_xbar_tmp_c6;
wire [7:0] imiss2_to_xbar_tmp_c6;
wire mux2_sel_inv_vec_c6;
wire oq_count_nonzero;
wire mux3_sel_oq_req;
wire imiss1_oq_or_pipe;
wire sel_old_req;
wire imiss1_to_xbarq_c6, imiss1_to_xbarq_c7;
wire [7:0] imiss2_from_oq, imiss2_oq_or_pipe;
wire [7:0] req_to_xbarq_c6, req_to_xbarq_c7;
wire [7:0] imiss2_to_xbarq_c6, imiss2_to_xbarq_c7;
wire [7:0] mux2_req_vec_c6, mux3_req_vec_c6;
wire [7:0] mux1_req_vec_c6;
wire [4:0] oq_count_p;
wire [7:0] bcast_st_req_c6, bcast_inval_req_c6;
wire bcast_req_c6,bcast_req_c7 ;
wire bcast_req_pipe;
wire bcast_req_oq_or_pipe, bcast_to_xbar_c6, bcast_to_xbar_c7;
wire [7:0] bcast_req_xbarqfull_c6, req_to_que_in_xbarq_c7;
wire allow_new_req_bcast, allow_old_req_bcast ;
wire allow_req_c6, allow_req_c7 ;
wire [7:0] que_in_xbarq_c7;
wire old_req_vld ;
wire [3:0] load_ret, stack_ret, imiss_err_or_int_rqtyp_c7 ;
wire st_req_c6, st_req_c7, int_req_sel_c7 ;
wire fwd_req_ret_c6 ;
wire int_ack_c6, int_ack_c7 ;
wire ld_hit_c6, ld_hit_c7 ;
wire strld_inst_c7;
wire atm_inst_c7;
wire strst_ack_c6 ;
wire uerr_ack_c6, uerr_ack_c7 ;
wire cerr_ack_c6, cerr_ack_c7 ;
wire imiss_req_sel_c7, err_req_sel_c7 ;
wire sel_evict_vec_c7;
wire imiss_err_or_int_sel_c7, sel_st_ack_c7, sel_ld_ret_c7;
wire [3:0] rqtyp_rtn_c7;
wire inc_wr_ptr, inc_wr_ptr_d1, inc_rd_ptr, inc_rd_ptr_d1;
wire [15:0] wr_word_line, rd_word_line;
wire [3:0] enc_wr_ptr, enc_rd_ptr;
wire [3:0] enc_wr_ptr_d1, enc_rd_ptr_d1;
wire [15:0] wr_ptr, wr_ptr_d1, wr_ptr_lsby1;
wire wr_ptr0_n, wr_ptr0_n_d1 ;
wire [15:0] rd_ptr, rd_ptr_d1, rd_ptr_lsby1;
wire rd_ptr0_n, rd_ptr0_n_d1 ;
wire sel_count_inc, sel_count_dec, sel_count_def;
wire [4:0] oq_count_plus_1,oq_count_minus_1, oq_count_reset_p ;
wire [4:0] oq_count_d1, oq_count_plus_1_d1, oq_count_minus_1_d1;
wire oqctl_full_px1;
wire [11:0] oq0_out;
wire [11:0] oq1_out;
wire [11:0] oq2_out;
wire [11:0] oq3_out;
wire [11:0] oq4_out;
wire [11:0] oq5_out;
wire [11:0] oq6_out;
wire [11:0] oq7_out;
wire [11:0] oq8_out;
wire [11:0] oq9_out;
wire [11:0] oq10_out;
wire [11:0] oq11_out;
wire [11:0] oq12_out;
wire [11:0] oq13_out;
wire [11:0] oq14_out;
wire [11:0] oq15_out;
wire [7:0] oq_rd_out;
wire imiss1_rd_out, imiss2_rd_out;
wire oq_bcast_out;
wire [1:0] xbar0_cnt, xbar0_cnt_p, xbar0_cnt_plus1, xbar0_cnt_minus1;
wire [1:0] xbar1_cnt, xbar1_cnt_p, xbar1_cnt_plus1, xbar1_cnt_minus1;
wire [1:0] xbar2_cnt, xbar2_cnt_p, xbar2_cnt_plus1, xbar2_cnt_minus1;
wire [1:0] xbar3_cnt, xbar3_cnt_p, xbar3_cnt_plus1, xbar3_cnt_minus1;
wire [1:0] xbar4_cnt, xbar4_cnt_p, xbar4_cnt_plus1, xbar4_cnt_minus1;
wire [1:0] xbar5_cnt, xbar5_cnt_p, xbar5_cnt_plus1, xbar5_cnt_minus1;
wire [1:0] xbar6_cnt, xbar6_cnt_p, xbar6_cnt_plus1, xbar6_cnt_minus1;
wire [1:0] xbar7_cnt, xbar7_cnt_p, xbar7_cnt_plus1, xbar7_cnt_minus1;
wire [7:0] xbarq_full, xbarq_cnt1;
wire [7:0] inc_xbar_cnt;
wire [7:0] dec_xbar_cnt;
wire [7:0] nochange_xbar_cnt;
wire [7:0] change_xbar_cnt;
wire [15:0] oq_out_bit7,oq_out_bit6,oq_out_bit5,oq_out_bit4;
wire [15:0] oq_out_bit3,oq_out_bit2,oq_out_bit1,oq_out_bit0;
wire [15:0] imiss1_oq_out;
wire [15:0] imiss2_oq_out;
wire [15:0] bcast_oq_out ;
wire [7:0] evict_inv_vec;
wire [15:0] rdma_oq_out;
wire oq_rdma_out;
wire rdma_inv_c6, rdma_inv_c7;
wire rdma_to_xbar_tmp_c6, rdma_oq_or_pipe;
wire rdma_to_xbarq_c6, rdma_to_xbarq_c7 ;
wire rdma_wr_comp_c5;
wire dir_hit_c6 ;
wire ack_idle_state_in_l, ack_idle_state_l ;
wire oqctl_st_complete_c6 ;
wire [2:0] rdma_state_in, rdma_state;
wire rdma_req_sent_c7;
wire oqctl_prev_data_c7;
wire oqctl_sel_oq_c7;
wire oqctl_sel_old_req_c7;
wire oqctl_sel_inval_c6;
wire store_inst_c6;
wire store_inst_c7;
wire diag_data_sel_c7;
wire diag_tag_sel_c7;
wire diag_vuad_sel_c7;
wire diag_lddata_sel_c7;
wire diag_ldtag_sel_c7;
wire diag_ldvuad_sel_c7;
wire diag_lddata_sel_c8;
wire diag_ldtag_sel_c8;
wire diag_ldvuad_sel_c8;
wire diag_def_sel_c7;
wire diag_def_sel_c8;
wire fwd_req_vld_ld_c7;
wire oqctl_sel_inval_c7;
wire csr_reg_rd_en_c8;
wire sel_old_data_c7;
wire [2:0] cpuid_c5;
wire [2:0] inst_cpuid_c6;
wire [6:0] dec_cpuid_c6 ;
wire [6:0] dec_cpuid_c5;
wire [3:0] lkup_bank_ena_dcd_c5;
wire [3:0] lkup_bank_ena_icd_c5;
wire [3:0] mux_vec_sel_c5;
wire [3:0] mux_vec_sel_c6_unqual ;
wire pf_inst_c6, pf_inst_c7 ;
wire rmo_st_c6, rmo_st_c7 ;
wire l2_miss_c5, l2_miss_c6, l2_miss_c7 ;
wire [3:0] enc_wr_ptr_d2 ;
wire inc_wr_ptr_d2;
wire dbb_rst_l;
wire inc_rd_ptr_d1_1, inc_rd_ptr_d1_2;
wire inc_wr_ptr_d1_1, inc_wr_ptr_d1_2;
wire st_ack_c6, st_ack_c7;
wire oq_count_15_p, oq_count_15_d1;
wire oq_count_16_p, oq_count_16_d1;
wire wr_wl_disable;
///////////////////////////////////////////////////////////////////
// Reset flop
///////////////////////////////////////////////////////////////////
dffrl_async #(1) reset_flop (.q(dbb_rst_l),
.clk(rclk),
.rst_l(arst_l),
.din(grst_l),
.se(se), .si(), .so());
///////////////////////////////////////////////////////////////////////////
// Request vector generation.
// The CPUs need to be either invalidated or acknowledged for actions that
// happen in the L2 $. Most of these actions are caused by cpu requests to
// the L2. However, evictions and disrupting errors are independent of
// requests coming from the CPU and form a portion of the requests going
// to the CPUs
//
// All requests are sent to the CPUs in C7 except requests in response
// to diagnostic accesses which are sent a cycle later.
//
// Request can be generated from an instruction in the pipe or an older
// request. The request vector is generated in C6 The request vector is generated in C6.
// The 4 sources of requests in the following logic are as follows:
// * Request in pipe
// * delayed ( 1cycle ) Request in pipe
// * Request from the OQ.
// * Request that was selected from the above 3 sources but
// was not able to send to the xbar because of a xbar fulll condition
//
///////////////////////////////////////////////////////////////////////////
assign int_bcast_c5 = tagctl_int_ack_c5 & arbdp_int_bcast_c5 ;
dff_s #(1) ff_int_bcast_c6 ( .din(int_bcast_c5), .clk(rclk),
.q(int_bcast_c6), .se(se), .si(), .so());
///////////////
// FWD req responses are now forwarded to the
// cpu that made the request.
//////////
//
//mux2ds #(3) mux_cpuid_c5 (.dout(cpu_c5[2:0]),
// .in0(arbdp_cpuid_c5[2:0]), // instr cpu id
// .in1(3'b0), // fwd req response alwaya to cpu0
// .sel0(~tagctl_fwd_req_in_c5), // no fwd req
// .sel1(tagctl_fwd_req_in_c5)); // fwd req
//////////////
assign dec_cpu_c5[0] = ( arbdp_cpuid_c5[2:0] == 3'd0 ) | int_bcast_c5 ;
assign dec_cpu_c5[1] = ( arbdp_cpuid_c5[2:0] == 3'd1 ) | int_bcast_c5 ;
assign dec_cpu_c5[2] = ( arbdp_cpuid_c5[2:0] == 3'd2 ) | int_bcast_c5 ;
assign dec_cpu_c5[3] = ( arbdp_cpuid_c5[2:0] == 3'd3 ) | int_bcast_c5 ;
assign dec_cpu_c5[4] = ( arbdp_cpuid_c5[2:0] == 3'd4 ) | int_bcast_c5 ;
assign dec_cpu_c5[5] = ( arbdp_cpuid_c5[2:0] == 3'd5 ) | int_bcast_c5 ;
assign dec_cpu_c5[6] = ( arbdp_cpuid_c5[2:0] == 3'd6 ) | int_bcast_c5 ;
assign dec_cpu_c5[7] = ( arbdp_cpuid_c5[2:0] == 3'd7 ) | int_bcast_c5 ;
dff_s #(8) ff_dec_cpu_c6 ( .din(dec_cpu_c5[7:0]), .clk(rclk),
.q(dec_cpu_c6[7:0]), .se(se), .si(), .so());
dff_s #(8) ff_dec_cpu_c7 ( .din(dec_cpu_c6[7:0]), .clk(rclk),
.q(dec_cpu_c7[7:0]), .se(se), .si(), .so());
// select the req vec for the instruction in C6 for a diagnostic
// access or a CSR instruction store completion.
assign sel_dec_vec_c6 = tagctl_nonmem_comp_c6;
dff_s #(1) ff_sel_dec_vec_c7 ( .din(sel_dec_vec_c6), .clk(rclk),
.q(sel_dec_vec_c6_d1), .se(se), .si(), .so());
dff_s #(1) ff_diag_acc_c8 ( .din(sel_dec_vec_c6_d1), .clk(rclk),
.q(oqctl_diag_acc_c8), .se(se), .si(), .so());
assign sel_stinv_req_c5 = ( tagctl_st_ack_c5
| tagctl_strst_ack_c5 ) ;
dff_s #(1) ff_sel_stinv_req_c6 ( .din(sel_stinv_req_c5), .clk(rclk),
.q(sel_stinv_req_c6), .se(se), .si(), .so());
assign sel_inv_vec_c5 = ( arbctl_evict_c5 | sel_rdma_inval_vec_c5 ) ;
dff_s #(1) ff_sel_inv_vec_c6 ( .din(sel_inv_vec_c5), .clk(rclk),
.q(sel_inv_vec_c6), .se(se), .si(), .so());
assign sel_dec_vec_c5 = ( tagctl_imiss_hit_c5 |
tagctl_ld_hit_c5 |
tagctl_uerr_ack_c5 |
tagctl_cerr_ack_c5 |
tagctl_int_ack_c5 ) ;
dff_s #(1) ff_sel_dec_vec_c5_d1 ( .din(sel_dec_vec_c5), .clk(rclk),
.q(sel_dec_vec_c5_d1), .se(se), .si(), .so());
// invalidate/stack vector
assign inval_vec_c6 = ( dirdp_req_vec_c6 |
( dec_cpu_c6 &
{8{sel_stinv_req_c6}} ) ) ;
assign sel_req_out_c6[0] = sel_dec_vec_c5_d1 ;
assign sel_req_out_c6[1] = sel_dec_vec_c6_d1 & ~sel_dec_vec_c5_d1 ;
assign sel_req_out_c6[2] = ( sel_stinv_req_c6 | sel_inv_vec_c6 ) & ~sel_dec_vec_c5_d1 &
~sel_dec_vec_c6_d1 ;
assign sel_req_out_c6[3] = ~( sel_stinv_req_c6 |
sel_inv_vec_c6 |
sel_dec_vec_c5_d1 |
sel_dec_vec_c6_d1 ) ;
// pipeline request C6
mux4ds #(8) mux_req_out_c6 ( .dout (req_out_c6[7:0]),
.in0(dec_cpu_c6[7:0]),
.in1(dec_cpu_c7[7:0]),
.in2(inval_vec_c6[7:0]),
.in3(8'b0),
.sel0(sel_req_out_c6[0]),
.sel1(sel_req_out_c6[1]),
.sel2(sel_req_out_c6[2]),
.sel3(sel_req_out_c6[3]));
dff_s #(8) ff_req_out_c7 ( .din(req_out_c6[7:0]), .clk(rclk),
.q(req_out_c7[7:0]), .se(se), .si(), .so());
// imiss 1 request C6.
dff_s #(1) ff_imiss1_out_c6 ( .din(tagctl_imiss_hit_c5), .clk(rclk),
.q(imiss1_out_c6), .se(se), .si(), .so());
dff_s #(1) ff_imiss1_out_c7 ( .din(imiss1_out_c6), .clk(rclk),
.q(imiss1_out_c7), .se(se), .si(), .so());
dff_s #(1) ff_imiss1_out_c8 ( .din(imiss1_out_c7), .clk(rclk),
.q(imiss1_out_c8), .se(se), .si(), .so());
assign oqctl_imiss_hit_c8 = imiss1_out_c8 ;
assign imiss2_out_c6 = imiss1_out_c7;
assign imiss2_out_c7 = imiss1_out_c8;
assign imiss2_req_vec_c6 = {8{imiss2_out_c6}} & req_out_c7 ;
dff_s #(8) ff_imiss2_req_vec_c7( .din(imiss2_req_vec_c6[7:0]), .clk(rclk),
.q(imiss2_req_vec_c7[7:0]), .se(se), .si(), .so());
//////////////////////
// A request in the pipe is valid under the following conditions.
// -dir inval vec is non-zero for an eviction
// -an imiss 2nd packet is in C7
// -all conditions that cause assertion of sel_dec_vec_c5_d1
// -all conditions that cause the assertion of sel_dec_vec_c6_d1
//
// A delayed pipe( by 1 cycle ) request is selected
// over an incomping pipe request in Cycle T
// if the pipe request is cycle T-1 was overruled due
// to higher priority requests.
//////////////////////
assign evict_inv_vec = {8{sel_inv_vec_c6}} & dirdp_req_vec_c6 ;
assign c6_req_vld = |( evict_inv_vec | imiss2_req_vec_c6 ) |
sel_dec_vec_c5_d1 |
sel_stinv_req_c6 |
sel_dec_vec_c6_d1 ;
dff_s #(1) ff_c6_req_vld ( .din(c6_req_vld), .clk(rclk),
.q(c7_req_vld), .se(se), .si(), .so());
assign sel_c7_req = c7_req_vld & ( sel_c7_req_d1 |// selected delayed pipe req
old_req_vld_d1 | // selected existing req to xbar
oq_count_nonzero_d1) ; // selected from OQ.
dff_s #(1) ff_sel_c7_req_d1 (.din(sel_c7_req), .clk(rclk),
.q(sel_c7_req_d1), .se(se), .si(), .so());
//////////////////////////
// request Mux1.
// Select between the following
// request sources -
// - delayed pipe req
// - c6 pipe req
// - c7 pipe req
// - default.
//
// A delayed pipe request has the
// highest priority.
//////////////////////////
assign mux1_sel_c7_req = sel_c7_req ;
assign mux1_sel_dec_vec_c6 = sel_dec_vec_c5_d1 & ~sel_c7_req;
assign mux1_sel_dec_vec_c7 = sel_dec_vec_c6_d1 &
~sel_dec_vec_c5_d1 &
~sel_c7_req ;
assign mux1_sel_def_c6 = ~( sel_dec_vec_c5_d1 |
sel_dec_vec_c6_d1 ) &
~sel_c7_req ;
mux4ds #(8) mux_mux1_req_vec_c6 ( .dout (mux1_req_vec_c6[7:0]),
.in0(req_out_c7[7:0]),
.in1(dec_cpu_c6[7:0]),
.in2(dec_cpu_c7[7:0]),
.in3(8'b0),
.sel0(mux1_sel_c7_req),
.sel1(mux1_sel_dec_vec_c6),
.sel2(mux1_sel_dec_vec_c7),
.sel3(mux1_sel_def_c6));
mux2ds #(1) mux_mux1_imiss1_c6 (.dout(imiss1_to_xbar_tmp_c6),
.in0(imiss1_out_c6),
.in1(imiss1_out_c7),
.sel0(~sel_c7_req),
.sel1(sel_c7_req));
mux2ds #(8) mux_mux1_imiss2_c6 (.dout(imiss2_to_xbar_tmp_c6[7:0]),
.in0(imiss2_req_vec_c6[7:0]),
.in1(imiss2_req_vec_c7[7:0]),
.sel0(~sel_c7_req),
.sel1(sel_c7_req));
assign rdma_inv_c6 = rdma_state[`ACK_WAIT] & |( dirdp_req_vec_c6 );
dff_s #(1) ff_rdma_inv_c7 ( .din(rdma_inv_c6), .clk(rclk),
.q(rdma_inv_c7), .se(se), .si(),.so());
mux2ds #(1) mux_mux1_rdma_c6 (.dout(rdma_to_xbar_tmp_c6),
.in0(rdma_inv_c6),
.in1(rdma_inv_c7),
.sel0(~sel_c7_req),
.sel1(sel_c7_req));
//////////////////////////
// request Mux2.
// Select between the following
// - Mux1 request
// - invalidation/ack vector.
//////////////////////////
assign mux2_sel_inv_vec_c6 = mux1_sel_def_c6 &
( sel_stinv_req_c6 | sel_inv_vec_c6 );
mux2ds #(8) mux_mux2_req_c6 ( .dout (mux2_req_vec_c6[7:0]),
.in0(mux1_req_vec_c6[7:0]),
.in1(inval_vec_c6[7:0]),
.sel0(~mux2_sel_inv_vec_c6),
.sel1(mux2_sel_inv_vec_c6)) ;
//////////////////////////
// request Mux3.
// Select between the following
// - Mux2 request
// - Oq request.
// OQ request has priority
//////////////////////////
assign mux3_sel_oq_req = dbb_rst_l & oq_count_nonzero;
mux2ds #(8) mux_mux3_req_vec_c6 ( .dout (mux3_req_vec_c6[7:0]),
.in0(mux2_req_vec_c6[7:0]),
.in1(oq_rd_out[7:0]),
.sel0(~mux3_sel_oq_req),
.sel1(mux3_sel_oq_req));
mux2ds #(1) mux_imiss1_oq_or_pipe ( .dout (imiss1_oq_or_pipe),
.in0(imiss1_to_xbar_tmp_c6),
.in1(imiss1_rd_out),
.sel0(~mux3_sel_oq_req),
.sel1(mux3_sel_oq_req));
mux2ds #(1) mux_rdma_oq_or_pipe ( .dout (rdma_oq_or_pipe),
.in0(rdma_to_xbar_tmp_c6),
.in1(oq_rdma_out),
.sel0(~mux3_sel_oq_req),
.sel1(mux3_sel_oq_req));
assign imiss2_from_oq = {8{imiss2_rd_out}} & req_to_xbarq_c7 ;
mux2ds #(8) mux_imiss2_oq_or_pipe ( .dout (imiss2_oq_or_pipe[7:0]),
.in0(imiss2_to_xbar_tmp_c6[7:0]),
.in1(imiss2_from_oq[7:0]),
.sel0(~mux3_sel_oq_req),
.sel1(mux3_sel_oq_req));
//////////////////////////
// A 2 to 1 mux flop to select
// either the old request
// or a new one.
//////////////////////////
mux2ds #(8) mux_req_to_xbar_c6 ( .dout (req_to_xbarq_c6[7:0]),
.in0(req_to_xbarq_c7[7:0]),
.in1(mux3_req_vec_c6[7:0]),
.sel0(sel_old_req),
.sel1(~sel_old_req));
dff_s #(8) ff_xbar_req_c7 (.din(req_to_xbarq_c6[7:0]), .clk(rclk),
.q(req_to_xbarq_c7[7:0]), .se(se), .si(), .so());
// use a mux flop here
mux2ds #(1) mux_imiss1_to_xbar_c6 ( .dout (imiss1_to_xbarq_c6),
.in0(imiss1_to_xbarq_c7),
.in1(imiss1_oq_or_pipe),
.sel0(sel_old_req),
.sel1(~sel_old_req));
dff_s #(1) ff_imiss1_to_xbarq_c7 ( .din(imiss1_to_xbarq_c6), .clk(rclk),
.q(imiss1_to_xbarq_c7), .se(se), .si(),.so());
// use a mux flop here
mux2ds #(1) mux_rdma_to_xbar_c6 ( .dout (rdma_to_xbarq_c6),
.in0(rdma_to_xbarq_c7),
.in1(rdma_oq_or_pipe),
.sel0(sel_old_req),
.sel1(~sel_old_req));
dff_s #(1) ff_rdma_to_xbarq_c7 ( .din(rdma_to_xbarq_c6), .clk(rclk),
.q(rdma_to_xbarq_c7), .se(se), .si(),.so());
// use a mux flop here
mux2ds #(8) mux_imiss2_to_xbar_c6 ( .dout (imiss2_to_xbarq_c6[7:0]),
.in0(imiss2_to_xbarq_c7[7:0]),
.in1(imiss2_oq_or_pipe[7:0]),
.sel0(sel_old_req),
.sel1(~sel_old_req));
dff_s #(8) ff_imiss2_to_xbarq_c7 ( .din(imiss2_to_xbarq_c6[7:0]), .clk(rclk),
.q(imiss2_to_xbarq_c7[7:0]), .se(se), .si(), .so());
///////////////////////////////////////////////////////////////////////////
// For TSO it is essential that a multicast request be queued up in all
// Xbar Qs at the same time. In order for this to happen, a request that
// is multicast will have to wait for all destination Xbar Qs to be
// available.
//
// The following requests are multicast requests.
// - eviction requests ( that go to atleast one cpu ).
// - interrupt broadcasts
// - store invalidates ( that go to more than one cpu ).
///////////////////////////////////////////////////////////////////////////
assign bcast_st_req_c6 = {8{sel_stinv_req_c6}} & ~dec_cpu_c6 ;
assign bcast_inval_req_c6 = {8{sel_inv_vec_c6}} ;
assign bcast_req_c6 = int_bcast_c6 |
(|( ( bcast_st_req_c6 | bcast_inval_req_c6)
& dirdp_req_vec_c6 ) ) ;
dff_s #(1) ff_bcast_req_c6 ( .din(bcast_req_c6), .clk(rclk),
.q(bcast_req_c7), .se(se), .si(), .so());
mux2ds #(1) mux_bcast_req_pipe (.dout(bcast_req_pipe),
.in0(bcast_req_c7),.in1(bcast_req_c6),
.sel0(sel_c7_req),.sel1(~sel_c7_req));
mux2ds #(1) mux_bcast_req_oq_or_pipe ( .dout( bcast_req_oq_or_pipe),
.in0(bcast_req_pipe),.in1(oq_bcast_out),
.sel0(~oq_count_nonzero),.sel1(oq_count_nonzero));
// use a mux flop here
mux2ds #(1) mux_bcast_to_xbar_c6 ( .dout (bcast_to_xbar_c6),
.in0(bcast_to_xbar_c7), .in1(bcast_req_oq_or_pipe),
.sel0(sel_old_req), .sel1(~sel_old_req));
dff_s #(1) ff_bcast_to_xbar_c7 ( .din(bcast_to_xbar_c6), .clk(rclk),
.q(bcast_to_xbar_c7), .se(se), .si(),.so());
////////////////////////
// logic for disallowing a request from transmitting.
//
// A request that is in the pipe will be gated off
// if:
// - xbar is full or
// - xbar=1 and incrementing in that cycle.
//
// Request that has already made it to the output
// of the request muxes will be gate off if
// - xbar is full.
////////////////////////
assign bcast_req_xbarqfull_c6 = ( xbarq_full
| ( xbarq_cnt1 & que_in_xbarq_c7 ) );
assign allow_new_req_bcast = (&( ~mux3_req_vec_c6 |
~bcast_req_xbarqfull_c6 )) |
~bcast_req_oq_or_pipe ;
assign allow_old_req_bcast = (&( ~req_to_que_in_xbarq_c7 |
~xbarq_full )) |
~bcast_to_xbar_c7 ;
// use a mux flop here
mux2ds #(1) mux_allow_req_c6 ( .dout (allow_req_c6),
.in0(allow_old_req_bcast), .in1(allow_new_req_bcast),
.sel0(sel_old_req), .sel1(~sel_old_req));
dff_s #(1) ff_allow_req_c7 ( .din(allow_req_c6), .clk(rclk),
.q(allow_req_c7), .se(se), .si(),.so());
assign req_to_que_in_xbarq_c7 = ( req_to_xbarq_c7 | imiss2_to_xbarq_c7) ;
assign que_in_xbarq_c7 = req_to_que_in_xbarq_c7 & {8{allow_req_c7}};
assign old_req_vld = |( req_to_que_in_xbarq_c7 & xbarq_full &
~cpx_sctag_grant_cx ) |
~allow_req_c7 ;
assign sel_old_req = dbb_rst_l & old_req_vld ;
assign sctag_cpx_req_cq = req_to_xbarq_c7 & {8{allow_req_c7}};
assign sctag_cpx_atom_cq = imiss1_to_xbarq_c7 ;
///////////////////////////////////////////////////////////
// RQTYP and other signals sent to oqdp
// RQTYP is generated using several stages of muxing as follows:
// 1. mux between st ack and fwd reply
// 2. mux between ld ret and fwd reply
// 3. mux between int_ack, imiss_ret and err_ack
// 4. mux between mux1, mux2 and mux3 outputs and eviction_ret.
// 5. If an ack is a strm load or strm store ret, then the streaming
// bit of the request type is set.
//
// The request type logic is performed in C7.
///////////////////////////////////////////////////////////
dff_s #(1) ff_fwd_req_ret_c6 ( .din(tagctl_fwd_req_ret_c5), .clk(rclk),
.q(fwd_req_ret_c6), .se(se), .si(), .so());
dff_s #(1) ff_fwd_req_ret_c7 ( .din(fwd_req_ret_c6), .clk(rclk),
.q(fwd_req_ret_c7), .se(se), .si(), .so());
dff_s #(1) ff_int_ack_c6 ( .din(tagctl_int_ack_c5), .clk(rclk),
.q(int_ack_c6), .se(se), .si(), .so());
dff_s #(1) ff_int_ack_c7 ( .din(int_ack_c6), .clk(rclk),
.q(int_ack_c7), .se(se), .si(), .so());
assign oqctl_int_ack_c7 = int_ack_c7;
dff_s #(1) ff_ld_hit_c6 ( .din(tagctl_ld_hit_c5), .clk(rclk),
.q(ld_hit_c6), .se(se), .si(), .so());
dff_s #(1) ff_ld_hit_c7 ( .din(ld_hit_c6), .clk(rclk),
.q(ld_hit_c7), .se(se), .si(), .so());
dff_s #(1) ff_st_req_c6 ( .din(tagctl_st_req_c5), .clk(rclk),
.q(st_req_c6), .se(se), .si(), .so());
dff_s #(1) ff_st_req_c7 ( .din(st_req_c6), .clk(rclk),
.q(st_req_c7), .se(se), .si(), .so());
dff_s #(1) ff_strst_ack_c6 ( .din(tagctl_strst_ack_c5), .clk(rclk),
.q(strst_ack_c6), .se(se), .si(), .so());
dff_s #(1) ff_strst_ack_c7 ( .din(strst_ack_c6), .clk(rclk),
.q(strst_ack_c7), .se(se), .si(), .so());
// RMO store ACK.
dff_s #(1) ff_rmo_st_c6 ( .din(tagctl_rmo_st_ack_c5), .clk(rclk),
.q(rmo_st_c6), .se(se), .si(), .so());
dff_s #(1) ff_rmo_st_c7 ( .din(rmo_st_c6), .clk(rclk),
.q(rmo_st_c7), .se(se), .si(), .so());
assign oqctl_rmo_st_c7 = rmo_st_c7 ;
dff_s #(1) ff_sel_inv_vec_c7 ( .din(sel_inv_vec_c6), .clk(rclk),
.q(sel_evict_vec_c7), .se(se), .si(), .so());
dff_s #(1) ff_uerr_ack_c6 ( .din(tagctl_uerr_ack_c5), .clk(rclk),
.q(uerr_ack_c6), .se(se), .si(), .so());
dff_s #(1) ff_uerr_ack_c7 ( .din(uerr_ack_c6), .clk(rclk),
.q(uerr_ack_c7), .se(se), .si(), .so());
assign oqctl_uerr_ack_c7 = uerr_ack_c7 ;
dff_s #(1) ff_st_ack_c6 ( .din(tagctl_st_ack_c5), .clk(rclk),
.q(st_ack_c6), .se(se), .si(), .so());
dff_s #(1) ff_st_ack_c7 ( .din(st_ack_c6), .clk(rclk),
.q(st_ack_c7), .se(se), .si(), .so());
dff_s #(1) ff_cerr_ack_c6 ( .din(tagctl_cerr_ack_c5), .clk(rclk),
.q(cerr_ack_c6), .se(se), .si(), .so());
dff_s #(1) ff_cerr_ack_c7 ( .din(cerr_ack_c6), .clk(rclk),
.q(cerr_ack_c7), .se(se), .si(), .so());
assign oqctl_cerr_ack_c7 = cerr_ack_c7 ;
dff_s #(1) ff_strld_inst_c7 ( .din(decdp_strld_inst_c6), .clk(rclk),
.q(strld_inst_c7), .se(se), .si(), .so());
dff_s #(1) ff_atm_inst_c7 ( .din(decdp_atm_inst_c6), .clk(rclk),
.q(atm_inst_c7), .se(se), .si(), .so());
////////////////////////////////////////////////////////
// L2 miss is reported for LDs, IMIsses(1st pckt only )
// and stores. In all these cases, a miss is reported
// - if the instruction is issued from the miss Buffer
// - or if a st ack is sent for an instruction missing the
// L2.
////////////////////////////////////////////////////////
assign l2_miss_c5 = (tagctl_inst_mb_c5 &
( tagctl_st_ack_c5 |
tagctl_ld_hit_c5 |
tagctl_imiss_hit_c5 )) |
( ~tagctl_hit_c5 &
tagctl_st_ack_c5 );
dff_s #(1) ff_l2_miss_c6 ( .din(l2_miss_c5), .clk(rclk),
.q(l2_miss_c6), .se(se), .si(), .so());
dff_s #(1) ff_l2_miss_c7 ( .din(l2_miss_c6), .clk(rclk),
.q(l2_miss_c7), .se(se), .si(), .so());
assign oqctl_l2_miss_c7 = l2_miss_c7 ;
/////////////////////////////////////////
// A prefetch instruction has a "LOAD"
// opcode . Used to set bit 128 of the CPX
// packet
/////////////////////////////////////////
dff_s #(1) ff_pf_inst_c6 ( .din(decdp_pf_inst_c5), .clk(rclk),
.q(pf_inst_c6), .se(se), .si(), .so());
dff_s #(1) ff_pf_inst_c7 ( .din(pf_inst_c6), .clk(rclk),
.q(pf_inst_c7), .se(se), .si(), .so());
assign oqctl_pf_ack_c7 = pf_inst_c7 & ld_hit_c7 ;
mux2ds #(4) mux_load_ret ( .dout (load_ret[3:0]),
.in0(`LOAD_RET),
.in1(`FWD_RPY_RET),
.sel0(~fwd_req_ret_c7),
.sel1(fwd_req_ret_c7));
mux2ds #(4) mux_stack_ret ( .dout (stack_ret[3:0]),
.in0(`ST_ACK),
.in1(`FWD_RPY_RET),
.sel0(~fwd_req_ret_c7),
.sel1(fwd_req_ret_c7));
assign imiss_req_sel_c7 = imiss1_out_c7 | imiss1_out_c8 ;
assign err_req_sel_c7 = ( ~imiss_req_sel_c7 & ~int_ack_c7 );
assign int_req_sel_c7 = int_ack_c7 & ~imiss_req_sel_c7 ;
mux3ds #(4) mux_imiss_err_or_intreq_c5 ( .dout (imiss_err_or_int_rqtyp_c7[3:0]),
.in0(`IFILL_RET),
.in1(`INT_RET),
.in2(`ERR_RET),
.sel0(imiss_req_sel_c7),
.sel1(int_req_sel_c7),
.sel2(err_req_sel_c7));
assign imiss_err_or_int_sel_c7 = ( imiss_req_sel_c7 | int_ack_c7 |
uerr_ack_c7 | cerr_ack_c7) &
~sel_evict_vec_c7 ; // no eviction
assign sel_st_ack_c7 = ( st_req_c7 | strst_ack_c7 ) &
~imiss_err_or_int_sel_c7
& ~sel_evict_vec_c7 ;
assign sel_ld_ret_c7 = ~imiss_err_or_int_sel_c7 & ~sel_st_ack_c7 &
~sel_evict_vec_c7 ;
mux4ds #(4) mux_req_type_c7 ( .dout (rqtyp_rtn_c7[3:0]),
.in0(load_ret[3:0]), // load return
.in1(stack_ret[3:0]), // store ack return
.in2(`EVICT_REQ), // evict req
.in3(imiss_err_or_int_rqtyp_c7[3:0]), //imiss err or int
.sel0(sel_ld_ret_c7),
.sel1(sel_st_ack_c7),
.sel2(sel_evict_vec_c7),
.sel3(imiss_err_or_int_sel_c7));
assign str_ld_hit_c7 = strld_inst_c7 & ld_hit_c7 ;
assign oqctl_rqtyp_rtn_c7[3] = rqtyp_rtn_c7[3] ;
assign oqctl_rqtyp_rtn_c7[2] = rqtyp_rtn_c7[2] ;
assign oqctl_rqtyp_rtn_c7[1] = rqtyp_rtn_c7[1] | str_ld_hit_c7 | strst_ack_c7 ;
assign oqctl_rqtyp_rtn_c7[0] = rqtyp_rtn_c7[0] ;
assign atm_inst_ack_c7 = ( atm_inst_c7 & ( ld_hit_c7 | st_ack_c7 ) ) |
imiss1_out_c8 ;
////////////////////////////////////////////////////////////////////
// Oq counter: The Oq counter is a C9 flop. However, the
// full signal is generated in C8 using the previous value
// of the counter. The full signal is asserted when the
// counter is 7 or higher. THis means that instructions
// PX2-C8 can be accomodated in the OQ. Here re the pipelines
// for incrementing and decrementing OQ count.
//-----------------------------------------------------------------
// #1(C7) #2(C8) #3 #4
//-----------------------------------------------------------------
//
// if the C7 req
// is still vld
// AND ((oq_count!=0 ) inc counter.
// OR old_req_vld ).
//
// setup wline for wr_Data into
// oqarray write. oqarray
//
// setup wline for
// req Q write.
//
// req Q write.
//-----------------------------------------------------------------
// #1 #2 #3
//-----------------------------------------------------------------
// inc rd pointer
// if ~oldreq dec counter send to CPX
// and if oq_count
// non_zero rd data
// from array
// setup wline
// for reading next
// entry.(earliest
// issue out of
// OQ is in C10)
//
////////////////////////////////////////////////////////////////////
////////////////////
// Wr Pointer
////////////////////
assign inc_wr_ptr = sel_c7_req
& (oq_count_nonzero | old_req_vld) ;
// use a big flop that has a fanout of 16 so that the
// output of the flop can be used directly to mux out
// the wr ptr
dffrl_s #(1) ff_inc_wr_ptr_d1 ( .din(inc_wr_ptr), .clk(rclk),
.rst_l(dbb_rst_l),
.q(inc_wr_ptr_d1), .se(se), .si(), .so());
dffrl_s #(1) ff_inc_wr_ptr_d1_1 ( .din(inc_wr_ptr), .clk(rclk),
.rst_l(dbb_rst_l),
.q(inc_wr_ptr_d1_1), .se(se), .si(), .so());
dffrl_s #(1) ff_inc_wr_ptr_d1_2 ( .din(inc_wr_ptr), .clk(rclk),
.rst_l(dbb_rst_l),
.q(inc_wr_ptr_d1_2), .se(se), .si(), .so());
assign oqarray_wr_en = inc_wr_ptr_d1 ; // wen for array write
assign wr_word_line = wr_ptr & {16{~wr_wl_disable}} ; // wline for req Q write.
assign enc_wr_ptr[0] = ( wr_ptr[1] | wr_ptr[3] | wr_ptr[5] |
wr_ptr[7] | wr_ptr[9] | wr_ptr[11] |
wr_ptr[13] | wr_ptr[15] ) ;
assign enc_wr_ptr[1] = ( wr_ptr[2] | wr_ptr[3] | wr_ptr[6] |
wr_ptr[7] | wr_ptr[10] | wr_ptr[11] |
wr_ptr[14] | wr_ptr[15] ) ;
assign enc_wr_ptr[2] = ( wr_ptr[4] | wr_ptr[5] | wr_ptr[6] |
wr_ptr[7] | wr_ptr[12] | wr_ptr[13] |
wr_ptr[14] | wr_ptr[15] ) ;
assign enc_wr_ptr[3] = ( wr_ptr[8] | wr_ptr[9] | wr_ptr[10] |
wr_ptr[11] | wr_ptr[12] | wr_ptr[13] |
wr_ptr[14] | wr_ptr[15] ) ;
dff_s #(4) ff_enc_wr_ptr_d1 ( .din(enc_wr_ptr[3:0]), .clk(rclk),
.q(enc_wr_ptr_d1[3:0]), .se(se), .si(), .so());
assign oqarray_wr_ptr = enc_wr_ptr_d1 ; // write wline for array
assign wr_ptr_lsby1 = { wr_ptr_d1[14:0], wr_ptr_d1[15] } ;
mux2ds #(16) mux_wr_ptr ( .dout (wr_ptr[15:0]), // used for FIFO write
.in0(wr_ptr_lsby1[15:0]), // advanced
.in1(wr_ptr_d1[15:0]), // same
.sel0(inc_wr_ptr_d1_1), // sel advance
.sel1(~inc_wr_ptr_d1_1));
dffrl_s #(15) ff_wr_ptr15to1_d1 ( .din(wr_ptr[15:1]), .clk(rclk),
.rst_l(dbb_rst_l), .q(wr_ptr_d1[15:1]), .se(se), .si(), .so());
assign wr_ptr0_n = ~wr_ptr[0];
dffrl_s #(1) ff_wr_ptr0_d1 ( .din(wr_ptr0_n), .clk(rclk),
.rst_l(dbb_rst_l), .q(wr_ptr0_n_d1), .se(se), .si(), .so());
assign wr_ptr_d1[0] = ~wr_ptr0_n_d1;
////////////////////
// Rd Pointer
////////////////////
assign inc_rd_ptr = oq_count_nonzero & ~old_req_vld ;
dffrl_s #(1) ff_inc_rd_ptr_d1 ( .din(inc_rd_ptr), .clk(rclk),
.rst_l(dbb_rst_l),
.q(inc_rd_ptr_d1), .se(se), .si(), .so());
dffrl_s #(1) ff_inc_rd_ptr_d1_1 ( .din(inc_rd_ptr), .clk(rclk),
.rst_l(dbb_rst_l),
.q(inc_rd_ptr_d1_1), .se(se), .si(), .so());
dffrl_s #(1) ff_inc_rd_ptr_d1_2 ( .din(inc_rd_ptr), .clk(rclk),
.rst_l(dbb_rst_l),
.q(inc_rd_ptr_d1_2), .se(se), .si(), .so());
assign oqarray_rd_en = oq_count_nonzero; // array rd enable
assign rd_word_line = rd_ptr ; // wline for req Q read
assign enc_rd_ptr[0] = ( rd_ptr[1] | rd_ptr[3] | rd_ptr[5] |
rd_ptr[7] | rd_ptr[9] | rd_ptr[11] |
rd_ptr[13] | rd_ptr[15] ) ;
assign enc_rd_ptr[1] = ( rd_ptr[2] | rd_ptr[3] | rd_ptr[6] |
rd_ptr[7] | rd_ptr[10] | rd_ptr[11] |
rd_ptr[14] | rd_ptr[15] ) ;
assign enc_rd_ptr[2] = ( rd_ptr[4] | rd_ptr[5] | rd_ptr[6] |
rd_ptr[7] | rd_ptr[12] | rd_ptr[13] |
rd_ptr[14] | rd_ptr[15] ) ;
assign enc_rd_ptr[3] = ( rd_ptr[8] | rd_ptr[9] | rd_ptr[10] |
rd_ptr[11] | rd_ptr[12] | rd_ptr[13] |
rd_ptr[14] | rd_ptr[15] ) ;
assign oqarray_rd_ptr = enc_rd_ptr; // ph1 read
assign rd_ptr_lsby1 = { rd_ptr_d1[14:0], rd_ptr_d1[15] } ;
mux2ds #(16) mux_rd_ptr ( .dout (rd_ptr[15:0]),
.in0(rd_ptr_lsby1[15:0]),
.in1(rd_ptr_d1[15:0]),
.sel0(inc_rd_ptr_d1_1),
.sel1(~inc_rd_ptr_d1_1));
dffrl_s #(15) ff_rd_ptr15to1_d1 ( .din(rd_ptr[15:1]), .clk(rclk),
.rst_l(dbb_rst_l), .q(rd_ptr_d1[15:1]), .se(se), .si(), .so());
assign rd_ptr0_n = ~rd_ptr[0] ;
dffrl_s #(1) ff_rd_ptr0_d1 ( .din(rd_ptr0_n), .clk(rclk),
.rst_l(dbb_rst_l), .q(rd_ptr0_n_d1), .se(se), .si(), .so());
assign rd_ptr_d1[0] = ~rd_ptr0_n_d1;
//////////////////
// What If????
// Wrptr == Rdptr.
// If the Wr ptr is equal t th eread ptr.
// the array read data is not going to
// be correct. In this case, the
// write data needs to be forwarded to
// the rd data.
//////////////////
dff_s #(4) ff_enc_wr_ptr_d2 ( .din(enc_wr_ptr_d1[3:0]), .clk(rclk),
.q(enc_wr_ptr_d2[3:0]), .se(se), .si(), .so());
dff_s #(4) ff_enc_rd_ptr_d1 ( .din(enc_rd_ptr[3:0]), .clk(rclk),
.q(enc_rd_ptr_d1[3:0]), .se(se), .si(), .so());
dff_s #(1) ff_inc_wr_ptr_d2 ( .din(inc_wr_ptr_d1), .clk(rclk),
.q(inc_wr_ptr_d2), .se(se), .si(), .so());
//////---\/ FIx for macrotest \/---------
// sehold assertion during macrotest will guarantee that
// the array output is always picked.
// /////////////////////////////////////////////////////
assign sel_array_out_l = (( enc_wr_ptr_d2 == enc_rd_ptr_d1 ) &
inc_wr_ptr_d2 & // WR
oq_count_nonzero_d1) & // RD
~sehold ;
//////////////////
// OQ counter.
// assert full when 6 or greater.
//
// Bug#4503. The oqcount full assumption is
// wrong. Here is why
// Currently we assert oq_count_full when the
// counter is 7.
// The case that will cause the worst case skid
// and break the above assumption is as follows.
//-------------------------------------
// cycle #X cycle #X+1
//-------------------------------------
//
// C8 (~stall if C9(cnt=6)
// cnt <= 6)
// C7 C8(7)
// C6 C7(8)
// C5 C6(9)
// C4 C5(10)
// C3 C4(11)
// C2 C3(12)
// C1 C2(13)
// PX2 C1(14 and 15)
// PX1 PX2(16 and 17)
//
//-------------------------------------
// The C1 instruction could be an imiss. that requires 2 slots in the IQ.
// Similarly, the PX2 instruction could be an IMISS/CAS that requires 2 slots.
// This would put the counter at 17. Hence the oq counter full needs to be asserted
// at 6 or more
//////////////////
assign sel_count_inc = inc_wr_ptr_d1_2 & ~inc_rd_ptr_d1_2;
assign sel_count_dec = ~inc_wr_ptr_d1 & inc_rd_ptr_d1 ;
assign sel_count_def = ~( sel_count_inc | sel_count_dec ) ;
assign oq_count_plus_1 = (oq_count_p + 5'b1 ) ;
assign oq_count_minus_1 = ( oq_count_p - 5'b1 ) ;
assign oq_count_reset_p = ( oq_count_p );
dffrl_s #(5) ff_oq_cnt_d1 ( .din(oq_count_reset_p[4:0]), .clk(rclk),
.rst_l(dbb_rst_l),.q(oq_count_d1[4:0]), .se(se), .si(), .so());
dff_s #(5) ff_oq_cnt_plus1_d1 ( .din(oq_count_plus_1[4:0]), .clk(rclk),
.q(oq_count_plus_1_d1[4:0]), .se(se), .si(), .so());
dff_s #(5) ff_oq_cnt_minus1_d1 ( .din(oq_count_minus_1[4:0]), .clk(rclk),
.q(oq_count_minus_1_d1[4:0]), .se(se), .si(), .so());
mux3ds #(5) mux_oq_count ( .dout (oq_count_p[4:0]),
.in0(oq_count_d1[4:0]),
.in1(oq_count_minus_1_d1[4:0]),
.in2(oq_count_plus_1_d1[4:0]),
.sel0(sel_count_def),
.sel1(sel_count_dec),
.sel2(sel_count_inc));
assign oq_count_nonzero = |( oq_count_p) ;
// Read bug report for Bug # 3352.
// Funtionality to turn OFF the wr_wordline when the
// counter is at 16 or is going to reach 16 . Since the
// wr pointer advances with every write, we need to prevent
// a write when the counter is 16 and the pointer has wrapped
// around.
// Here is pipeline.
//--------------------------------------------------------
// X X+1 X+2
//--------------------------------------------------------
// 1) cnt_p==15 insert=1
// delete=0
// cnt_p=16
// wr_wline!=0 wr_wline=0;
//
// 2) cnt_p==16 if delete=0
// wr_wline==0 wr_wline=0;
//
// if delete=1
// wr_wline!=0;
//--------------------------------------------------------
assign oq_count_15_p = ( oq_count_p == 5'hf ) ;
dff_s #(1) ff_oq_count_15_d1 ( .din(oq_count_15_p), .clk(rclk),
.q(oq_count_15_d1), .se(se), .si(), .so());
assign oq_count_16_p = ( oq_count_p == 5'h10 ) ;
dff_s #(1) ff_oq_count_16_d1 ( .din(oq_count_16_p), .clk(rclk),
.q(oq_count_16_d1), .se(se), .si(), .so());
assign wr_wl_disable = ( ( oq_count_15_d1 & sel_count_inc ) |
( oq_count_16_d1 & ~sel_count_dec ) ) ;
assign oqctl_full_px1 = ( oq_count_p[2] & oq_count_p[1]) |
( oq_count_p[3] ) |
( oq_count_p[4] ) ;
dff_s #(1) ff_oqctl_arbctl_full_px2 ( .din(oqctl_full_px1), .clk(rclk),
.q(oqctl_arbctl_full_px2), .se(se), .si(), .so());
////////////////////////////////////////////////////////////////////
// Oqdp mux select generation:
////////////////////////////////////////////////////////////////////
dff_s #(1) ff_oq_count_nonzero_d1 (.din(oq_count_nonzero), .clk(rclk),
.q(oq_count_nonzero_d1), .se(se), .si(), .so());
dff_s #(1) ff_old_req_vld_d1 (.din(old_req_vld), .clk(rclk),
.q(old_req_vld_d1), .se(se), .si(), .so());
assign oqctl_sel_inval_c6 = ( sel_inv_vec_c6 | sel_stinv_req_c6 | int_ack_c6 |
mux1_sel_dec_vec_c7 ) ;
assign oqctl_sel_old_req_c7 = old_req_vld_d1 ;
assign oqctl_sel_oq_c7 = inc_rd_ptr_d1 ;
assign oqctl_prev_data_c7 = sel_c7_req_d1 & ~old_req_vld_d1 &
~oq_count_nonzero_d1 ;
///////////////////////////////////////////////////////////////////////////////////
// OQ request Q
///////////////////////////////////////////////////////////////////////////////////
dffe_s #(12) ff_oq0_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[0]),
.clk(rclk), .q(oq0_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq1_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[1]),
.clk(rclk), .q(oq1_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq2_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[2]),
.clk(rclk), .q(oq2_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq3_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[3]),
.clk(rclk), .q(oq3_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq4_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[4]),
.clk(rclk), .q(oq4_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq5_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[5]),
.clk(rclk), .q(oq5_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq6_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[6]),
.clk(rclk), .q(oq6_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq7_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[7]),
.clk(rclk), .q(oq7_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq8_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[8]),
.clk(rclk), .q(oq8_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq9_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[9]),
.clk(rclk), .q(oq9_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq10_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[10]),
.clk(rclk), .q(oq10_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq11_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[11]),
.clk(rclk), .q(oq11_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq12_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[12]),
.clk(rclk), .q(oq12_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq13_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[13]),
.clk(rclk), .q(oq13_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq14_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[14]),
.clk(rclk), .q(oq14_out[11:0]), .se(se), .si(), .so());
dffe_s #(12) ff_oq15_out ( .din({rdma_inv_c7,bcast_req_c7,req_out_c7[7:0],imiss1_out_c7,imiss2_out_c7}),
.en(wr_word_line[15]),
.clk(rclk), .q(oq15_out[11:0]), .se(se), .si(), .so());
assign oq_out_bit7 = { oq15_out[9],oq14_out[9],oq13_out[9],oq12_out[9],
oq11_out[9],oq10_out[9],oq9_out[9],oq8_out[9],
oq7_out[9],oq6_out[9],oq5_out[9],oq4_out[9],
oq3_out[9],oq2_out[9],oq1_out[9],oq0_out[9] } ;
assign oq_out_bit6 = { oq15_out[8],oq14_out[8],oq13_out[8],oq12_out[8],
oq11_out[8],oq10_out[8],oq9_out[8],oq8_out[8],
oq7_out[8],oq6_out[8],oq5_out[8],oq4_out[8],
oq3_out[8],oq2_out[8],oq1_out[8],oq0_out[8] } ;
assign oq_out_bit5 = { oq15_out[7],oq14_out[7],oq13_out[7],oq12_out[7],
oq11_out[7],oq10_out[7],oq9_out[7],oq8_out[7],
oq7_out[7],oq6_out[7],oq5_out[7],oq4_out[7],
oq3_out[7],oq2_out[7],oq1_out[7],oq0_out[7] } ;
assign oq_out_bit4 = { oq15_out[6],oq14_out[6],oq13_out[6],oq12_out[6],
oq11_out[6],oq10_out[6],oq9_out[6],oq8_out[6],
oq7_out[6],oq6_out[6],oq5_out[6],oq4_out[6],
oq3_out[6],oq2_out[6],oq1_out[6],oq0_out[6] } ;
assign oq_out_bit3 = { oq15_out[5],oq14_out[5],oq13_out[5],oq12_out[5],
oq11_out[5],oq10_out[5],oq9_out[5],oq8_out[5],
oq7_out[5],oq6_out[5],oq5_out[5],oq4_out[5],
oq3_out[5],oq2_out[5],oq1_out[5],oq0_out[5] } ;
assign oq_out_bit2 = { oq15_out[4],oq14_out[4],oq13_out[4],oq12_out[4],
oq11_out[4],oq10_out[4],oq9_out[4],oq8_out[4],
oq7_out[4],oq6_out[4],oq5_out[4],oq4_out[4],
oq3_out[4],oq2_out[4],oq1_out[4],oq0_out[4] } ;
assign oq_out_bit1 = { oq15_out[3],oq14_out[3],oq13_out[3],oq12_out[3],
oq11_out[3],oq10_out[3],oq9_out[3],oq8_out[3],
oq7_out[3],oq6_out[3],oq5_out[3],oq4_out[3],
oq3_out[3],oq2_out[3],oq1_out[3],oq0_out[3] } ;
assign oq_out_bit0 = { oq15_out[2],oq14_out[2],oq13_out[2],oq12_out[2],
oq11_out[2],oq10_out[2],oq9_out[2],oq8_out[2],
oq7_out[2],oq6_out[2],oq5_out[2],oq4_out[2],
oq3_out[2],oq2_out[2],oq1_out[2],oq0_out[2] } ;
assign imiss2_oq_out = { oq15_out[0],oq14_out[0],oq13_out[0],oq12_out[0],
oq11_out[0],oq10_out[0],oq9_out[0],oq8_out[0],
oq7_out[0],oq6_out[0],oq5_out[0],oq4_out[0],
oq3_out[0],oq2_out[0],oq1_out[0],oq0_out[0] };
assign imiss1_oq_out = { oq15_out[1],oq14_out[1],oq13_out[1],oq12_out[1],
oq11_out[1],oq10_out[1],oq9_out[1],oq8_out[1],
oq7_out[1],oq6_out[1],oq5_out[1],oq4_out[1],
oq3_out[1],oq2_out[1],oq1_out[1],oq0_out[1] };
assign bcast_oq_out = { oq15_out[10],oq14_out[10],oq13_out[10],oq12_out[10],
oq11_out[10],oq10_out[10],oq9_out[10],oq8_out[10],
oq7_out[10],oq6_out[10],oq5_out[10],oq4_out[10],
oq3_out[10],oq2_out[10],oq1_out[10],oq0_out[10] };
assign rdma_oq_out = { oq15_out[11],oq14_out[11],oq13_out[11],oq12_out[11],
oq11_out[11],oq10_out[11],oq9_out[11],oq8_out[11],
oq7_out[11],oq6_out[11],oq5_out[11],oq4_out[11],
oq3_out[11],oq2_out[11],oq1_out[11],oq0_out[11] };
assign oq_rd_out[7] = |( oq_out_bit7 & rd_word_line ) ;
assign oq_rd_out[6] = |( oq_out_bit6 & rd_word_line ) ;
assign oq_rd_out[5] = |( oq_out_bit5 & rd_word_line ) ;
assign oq_rd_out[4] = |( oq_out_bit4 & rd_word_line ) ;
assign oq_rd_out[3] = |( oq_out_bit3 & rd_word_line ) ;
assign oq_rd_out[2] = |( oq_out_bit2 & rd_word_line ) ;
assign oq_rd_out[1] = |( oq_out_bit1 & rd_word_line ) ;
assign oq_rd_out[0] = |( oq_out_bit0 & rd_word_line ) ;
assign imiss1_rd_out = |( imiss1_oq_out & rd_word_line ) ;
assign imiss2_rd_out = |( imiss2_oq_out & rd_word_line ) ;
assign oq_bcast_out = |( bcast_oq_out & rd_word_line ) ;
assign oq_rdma_out = |( rdma_oq_out & rd_word_line ) ;
///////////////////////////////////////////////////////////////////////////////////
// CROSSBAR Q COUNT
/** The crossbar q count is maintained here */
// Each crossbar queue is incremented if
// * A request is issued to that destination
// OR if "atomic" is high and a request was issued to that
// destination
// Each crossbar queue is decremented if
// * A grant is received from the crossbar for a request
// * crossbar queue counters are initialized to 0 on reset
// The crossbar Q full signal is high if
// * the crossbar count is 2
// * the crossbar count is non-zero and the request is an imiss return.
///////////////////////////////////////////////////////////////////////////////////
assign xbarq_full[0] = ( xbar0_cnt[1]) ;
assign xbarq_full[1] = ( xbar1_cnt[1]) ;
assign xbarq_full[2] = ( xbar2_cnt[1]) ;
assign xbarq_full[3] = ( xbar3_cnt[1]) ;
assign xbarq_full[4] = ( xbar4_cnt[1]) ;
assign xbarq_full[5] = ( xbar5_cnt[1]) ;
assign xbarq_full[6] = ( xbar6_cnt[1]) ;
assign xbarq_full[7] = ( xbar7_cnt[1]) ;
assign xbarq_cnt1[0] = ( xbar0_cnt[0]) ;
assign xbarq_cnt1[1] = ( xbar1_cnt[0]) ;
assign xbarq_cnt1[2] = ( xbar2_cnt[0]) ;
assign xbarq_cnt1[3] = ( xbar3_cnt[0]) ;
assign xbarq_cnt1[4] = ( xbar4_cnt[0]) ;
assign xbarq_cnt1[5] = ( xbar5_cnt[0]) ;
assign xbarq_cnt1[6] = ( xbar6_cnt[0]) ;
assign xbarq_cnt1[7] = ( xbar7_cnt[0]) ;
assign inc_xbar_cnt[0] = ( que_in_xbarq_c7[0] & ~xbarq_full[0] & ~cpx_sctag_grant_cx[0] ) ;
assign dec_xbar_cnt[0] = ( ~que_in_xbarq_c7[0] & cpx_sctag_grant_cx[0] ) ;
assign nochange_xbar_cnt[0] = ~dec_xbar_cnt[0] & ~inc_xbar_cnt[0] ;
assign change_xbar_cnt[0] = ~nochange_xbar_cnt[0] ;
assign xbar0_cnt_plus1[1:0] = xbar0_cnt[1:0] + 2'b1 ;
assign xbar0_cnt_minus1[1:0] = xbar0_cnt[1:0] - 2'b1 ;
mux2ds #(2) mux_xbar0_cnt ( .dout (xbar0_cnt_p[1:0]),
.in0(xbar0_cnt_plus1[1:0]), .in1(xbar0_cnt_minus1[1:0]),
.sel0(inc_xbar_cnt[0]), .sel1(~inc_xbar_cnt[0])) ;
dffrle_s #(2) ff_xbar0 ( .din(xbar0_cnt_p[1:0]), .clk(rclk),
.rst_l(dbb_rst_l), .en(change_xbar_cnt[0]),
.q(xbar0_cnt[1:0]), .se(se), .si(), .so());
assign inc_xbar_cnt[1] = ( que_in_xbarq_c7[1] & ~xbarq_full[1] & ~cpx_sctag_grant_cx[1] ) ;
assign dec_xbar_cnt[1] = ( ~que_in_xbarq_c7[1] & cpx_sctag_grant_cx[1] ) ;
assign nochange_xbar_cnt[1] = ~dec_xbar_cnt[1] & ~inc_xbar_cnt[1] ;
assign change_xbar_cnt[1] = ~nochange_xbar_cnt[1] ;
assign xbar1_cnt_plus1[1:0] = xbar1_cnt[1:0] + 2'b1 ;
assign xbar1_cnt_minus1[1:0] = xbar1_cnt[1:0] - 2'b1 ;
mux2ds #(2) mux_xbar1_cnt ( .dout (xbar1_cnt_p[1:0]),
.in0(xbar1_cnt_plus1[1:0]), .in1(xbar1_cnt_minus1[1:0]),
.sel0(inc_xbar_cnt[1]), .sel1(~inc_xbar_cnt[1])) ;
dffrle_s #(2) ff_xbar1 ( .din(xbar1_cnt_p[1:0]), .clk(rclk),
.rst_l(dbb_rst_l), .en(change_xbar_cnt[1]),
.q(xbar1_cnt[1:0]), .se(se), .si(), .so());
assign inc_xbar_cnt[2] = ( que_in_xbarq_c7[2] & ~xbarq_full[2] & ~cpx_sctag_grant_cx[2] ) ;
assign dec_xbar_cnt[2] = ( ~que_in_xbarq_c7[2] & cpx_sctag_grant_cx[2] ) ;
assign nochange_xbar_cnt[2] = ~dec_xbar_cnt[2] & ~inc_xbar_cnt[2] ;
assign change_xbar_cnt[2] = ~nochange_xbar_cnt[2] ;
assign xbar2_cnt_plus1[1:0] = xbar2_cnt[1:0] + 2'b1 ;
assign xbar2_cnt_minus1[1:0] = xbar2_cnt[1:0] - 2'b1 ;
mux2ds #(2) mux_xbar2_cnt ( .dout (xbar2_cnt_p[1:0]),
.in0(xbar2_cnt_plus1[1:0]), .in1(xbar2_cnt_minus1[1:0]),
.sel0(inc_xbar_cnt[2]), .sel1(~inc_xbar_cnt[2])) ;
dffrle_s #(2) ff_xbar2 ( .din(xbar2_cnt_p[1:0]), .clk(rclk),
.rst_l(dbb_rst_l), .en(change_xbar_cnt[2]),
.q(xbar2_cnt[1:0]), .se(se), .si(), .so());
assign inc_xbar_cnt[3] = ( que_in_xbarq_c7[3] & ~xbarq_full[3] & ~cpx_sctag_grant_cx[3] ) ;
assign dec_xbar_cnt[3] = ( ~que_in_xbarq_c7[3] & cpx_sctag_grant_cx[3] ) ;
assign nochange_xbar_cnt[3] = ~dec_xbar_cnt[3] & ~inc_xbar_cnt[3] ;
assign change_xbar_cnt[3] = ~nochange_xbar_cnt[3] ;
assign xbar3_cnt_plus1[1:0] = xbar3_cnt[1:0] + 2'b1 ;
assign xbar3_cnt_minus1[1:0] = xbar3_cnt[1:0] - 2'b1 ;
mux2ds #(2) mux_xbar3_cnt ( .dout (xbar3_cnt_p[1:0]),
.in0(xbar3_cnt_plus1[1:0]), .in1(xbar3_cnt_minus1[1:0]),
.sel0(inc_xbar_cnt[3]), .sel1(~inc_xbar_cnt[3])) ;
dffrle_s #(2) ff_xbar3 ( .din(xbar3_cnt_p[1:0]), .clk(rclk),
.rst_l(dbb_rst_l), .en(change_xbar_cnt[3]),
.q(xbar3_cnt[1:0]), .se(se), .si(), .so());
assign inc_xbar_cnt[4] = ( que_in_xbarq_c7[4] & ~xbarq_full[4] & ~cpx_sctag_grant_cx[4] ) ;
assign dec_xbar_cnt[4] = ( ~que_in_xbarq_c7[4] & cpx_sctag_grant_cx[4] ) ;
assign nochange_xbar_cnt[4] = ~dec_xbar_cnt[4] & ~inc_xbar_cnt[4] ;
assign change_xbar_cnt[4] = ~nochange_xbar_cnt[4] ;
assign xbar4_cnt_plus1[1:0] = xbar4_cnt[1:0] + 2'b1 ;
assign xbar4_cnt_minus1[1:0] = xbar4_cnt[1:0] - 2'b1 ;
mux2ds #(2) mux_xbar4_cnt ( .dout (xbar4_cnt_p[1:0]),
.in0(xbar4_cnt_plus1[1:0]), .in1(xbar4_cnt_minus1[1:0]),
.sel0(inc_xbar_cnt[4]), .sel1(~inc_xbar_cnt[4])) ;
dffrle_s #(2) ff_xbar4 ( .din(xbar4_cnt_p[1:0]), .clk(rclk),
.rst_l(dbb_rst_l), .en(change_xbar_cnt[4]),
.q(xbar4_cnt[1:0]), .se(se), .si(), .so());
assign inc_xbar_cnt[5] = ( que_in_xbarq_c7[5] & ~xbarq_full[5] & ~cpx_sctag_grant_cx[5] ) ;
assign dec_xbar_cnt[5] = ( ~que_in_xbarq_c7[5] & cpx_sctag_grant_cx[5] ) ;
assign nochange_xbar_cnt[5] = ~dec_xbar_cnt[5] & ~inc_xbar_cnt[5] ;
assign change_xbar_cnt[5] = ~nochange_xbar_cnt[5] ;
assign xbar5_cnt_plus1[1:0] = xbar5_cnt[1:0] + 2'b1 ;
assign xbar5_cnt_minus1[1:0] = xbar5_cnt[1:0] - 2'b1 ;
mux2ds #(2) mux_xbar5_cnt ( .dout (xbar5_cnt_p[1:0]),
.in0(xbar5_cnt_plus1[1:0]), .in1(xbar5_cnt_minus1[1:0]),
.sel0(inc_xbar_cnt[5]), .sel1(~inc_xbar_cnt[5])) ;
dffrle_s #(2) ff_xbar5 ( .din(xbar5_cnt_p[1:0]), .clk(rclk),
.rst_l(dbb_rst_l), .en(change_xbar_cnt[5]),
.q(xbar5_cnt[1:0]), .se(se), .si(), .so());
assign inc_xbar_cnt[6] = ( que_in_xbarq_c7[6] & ~xbarq_full[6] & ~cpx_sctag_grant_cx[6] ) ;
assign dec_xbar_cnt[6] = ( ~que_in_xbarq_c7[6] & cpx_sctag_grant_cx[6] ) ;
assign nochange_xbar_cnt[6] = ~dec_xbar_cnt[6] & ~inc_xbar_cnt[6] ;
assign change_xbar_cnt[6] = ~nochange_xbar_cnt[6] ;
assign xbar6_cnt_plus1[1:0] = xbar6_cnt[1:0] + 2'b1 ;
assign xbar6_cnt_minus1[1:0] = xbar6_cnt[1:0] - 2'b1 ;
mux2ds #(2) mux_xbar6_cnt ( .dout (xbar6_cnt_p[1:0]),
.in0(xbar6_cnt_plus1[1:0]), .in1(xbar6_cnt_minus1[1:0]),
.sel0(inc_xbar_cnt[6]), .sel1(~inc_xbar_cnt[6])) ;
dffrle_s #(2) ff_xbar6 ( .din(xbar6_cnt_p[1:0]), .clk(rclk),
.rst_l(dbb_rst_l), .en(change_xbar_cnt[6]),
.q(xbar6_cnt[1:0]), .se(se), .si(), .so());
assign inc_xbar_cnt[7] = ( que_in_xbarq_c7[7] & ~xbarq_full[7] & ~cpx_sctag_grant_cx[7] ) ;
assign dec_xbar_cnt[7] = ( ~que_in_xbarq_c7[7] & cpx_sctag_grant_cx[7] ) ;
assign nochange_xbar_cnt[7] = ~dec_xbar_cnt[7] & ~inc_xbar_cnt[7] ;
assign change_xbar_cnt[7] = ~nochange_xbar_cnt[7] ;
assign xbar7_cnt_plus1[1:0] = xbar7_cnt[1:0] + 2'b1 ;
assign xbar7_cnt_minus1[1:0] = xbar7_cnt[1:0] - 2'b1 ;
mux2ds #(2) mux_xbar7_cnt ( .dout (xbar7_cnt_p[1:0]),
.in0(xbar7_cnt_plus1[1:0]), .in1(xbar7_cnt_minus1[1:0]),
.sel0(inc_xbar_cnt[7]), .sel1(~inc_xbar_cnt[7])) ;
dffrle_s #(2) ff_xbar7 ( .din(xbar7_cnt_p[1:0]), .clk(rclk),
.rst_l(dbb_rst_l), .en(change_xbar_cnt[7]),
.q(xbar7_cnt[1:0]), .se(se), .si(), .so());
///////////////////////////////////////////////////////////////
//
// RDMA store completion state machine.
//
// An RDMA store WR8 or WR64 acks the src only after
// all the L1$ invalidates have queued up at the crossbar.
// There are 3 possible cases with stores.
//
// - Stores missing the L2 send a completion signal in C7
// - Store missing the L1 ( i.e. directory ) will send a
// completion signal in C7.
// - Stores hitting the L1 will send a completion signal
// after making a request to the crossbar.
// ACK_WAIT state is hit on completion.
// ACK_CCX_REQ_ST is hit on a completion followed by a directory hit.
// The following table represents all state transitions in this
// FSM.
//
//---------------------------------------------------------------------------
// STATES ACK_IDLE ACK_WAIT ACK_CCX_REQ
//---------------------------------------------------------------------------
// ACK_IDLE ~comp_c5 comp_c5 never
//
//---------------------------------------------------------------------------
// ACK_WAIT ~hit_c6 directory
// or no never hit_c6
// directory
// hit
//---------------------------------------------------------------------------
// ACK_CCX_REQ req_cq & never ~(rdma_inv
// rdma_invtoxbar to xbar & req)
//---------------------------------------------------------------------------
//
// oqctl_st_complete_c7 if there is a transition
// to the ACK_IDLE state from
// ACK_WAIT or ACK_CCX_REQ
//
///////////////////////////////////////////////////////////////
dff_s #(1) ff_rdma_wr_comp_c5 (.din(tagctl_rdma_wr_comp_c4), .clk(rclk),
.q(rdma_wr_comp_c5), .se(se), .si(), .so());
assign dir_hit_c6 = |(dirdp_req_vec_c6);
assign rdma_req_sent_c7 = |(sctag_cpx_req_cq) &
rdma_to_xbarq_c7 ;
assign rdma_state_in[`ACK_IDLE] = (
(rdma_state[`ACK_WAIT] & ~dir_hit_c6) | // NO L1 INVAL
(rdma_state[`ACK_CCX_REQ] &
rdma_req_sent_c7 )| // L1 INVAL SENT
rdma_state[`ACK_IDLE]
) & ~rdma_wr_comp_c5 ; // completion of a write
assign ack_idle_state_in_l = ~rdma_state_in[`ACK_IDLE] ;
dffrl_s #(1) ff_rdma_req_state_0 (.din(ack_idle_state_in_l), .clk(rclk),
.rst_l(dbb_rst_l),
.q(ack_idle_state_l), .se(se), .si(), .so());
assign rdma_state[`ACK_IDLE] = ~ack_idle_state_l ;
assign rdma_state_in[`ACK_WAIT] =
(rdma_state[`ACK_IDLE] & rdma_wr_comp_c5 ) ;
assign rdma_state_in[`ACK_CCX_REQ] = (
(rdma_state[`ACK_WAIT] & dir_hit_c6 ) |
// l1 INVAL to BE SENT
rdma_state[`ACK_CCX_REQ]) &
~rdma_req_sent_c7 ;
dffrl_s #(2) ff_rdma_state
(.din(rdma_state_in[`ACK_CCX_REQ:`ACK_WAIT]),
.clk(rclk), .rst_l(dbb_rst_l),
.q(rdma_state[`ACK_CCX_REQ:`ACK_WAIT]),
.se(se), .si(), .so());
assign oqctl_st_complete_c6 = rdma_state_in[`ACK_IDLE] &
~rdma_state[`ACK_IDLE] ;
dff_s #(1) ff_oqctl_st_complete_c6 (.din(oqctl_st_complete_c6), .clk(rclk),
.q(oqctl_st_complete_c7), .se(se), .si(), .so());
////////////////////////////////////////
// Generation of mux selects for
// oqdp. This was previously done in
// oq_dctl. Now that logic has been
// merged into oqctl. (11/05/2002).
////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// staging flops.
dff_s #(1) ff_store_inst_c6
(.q (store_inst_c6),
.din (tagctl_store_inst_c5),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_store_inst_c7
(.q (store_inst_c7),
.din (store_inst_c6),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_csr_reg_rd_en_c8
(.q (csr_reg_rd_en_c8),
.din (arbctl_csr_rd_en_c7),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_sel_inval_c7
(.q (oqctl_sel_inval_c7),
.din (oqctl_sel_inval_c6),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(1) ff_fwd_req_vld_ld_c7
(.q (fwd_req_vld_ld_c7),
.din (tagctl_fwd_req_ld_c6),
.clk (rclk),
.se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// DATA Diagnostic access.
// remember tagctl_fwd_req_ld_c6 is only asserted for non-diag accesses.
// "mux1_sel_data_c7[3:0]" is used for select signal for a 39 bit 4to1 MUX in
// OQDP that selects among Diag data, Tag Diag data, VUAD Diag data & Interrupt
// return data.
////////////////////////////////////////////////////////////////////////////////
dff_s #(1) ff_diag_data_sel_c7
(.q (diag_data_sel_c7),
.din (arbctl_inst_l2data_vld_c6),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign diag_lddata_sel_c7 = (diag_data_sel_c7 & ~store_inst_c7) |
tagctl_fwd_req_ld_c6 ;
dff_s #(1) ff_diag_lddata_sel_c8
(.q (diag_lddata_sel_c8),
.din (diag_lddata_sel_c7),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign mux1_sel_data_c7[0] = diag_lddata_sel_c8 & ~rst_tri_en ;
// rst_tri_en is used to insure mux exclusivity during the scan testing
////////////////////////////////////////
// Tag Diagnostic access.
////////////////////////////////////////
dff_s #(1) ff_diag_tag_sel_c7
(.q (diag_tag_sel_c7),
.din (arbctl_inst_l2tag_vld_c6),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign diag_ldtag_sel_c7 = diag_tag_sel_c7 & ~store_inst_c7 ;
dff_s #(1) ff_diag_ldtag_sel_c8
(.q (diag_ldtag_sel_c8),
.din (diag_ldtag_sel_c7),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign mux1_sel_data_c7[1] = diag_ldtag_sel_c8 & ~rst_tri_en ;
////////////////////////////////////////
// VUAD Diagnostic access.
////////////////////////////////////////
dff_s #(1) ff_diag_vuad_sel_c7
(.q (diag_vuad_sel_c7),
.din (arbctl_inst_l2vuad_vld_c6),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign diag_ldvuad_sel_c7 = diag_vuad_sel_c7 & ~store_inst_c7 ;
dff_s #(1) ff_diag_ldvuad_sel_c8
(.q (diag_ldvuad_sel_c8),
.din (diag_ldvuad_sel_c7),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign mux1_sel_data_c7[2] = diag_ldvuad_sel_c8 & ~rst_tri_en ;
////////////////////////////////////////
// default mux sel
////////////////////////////////////////
assign diag_def_sel_c7 = ~(diag_lddata_sel_c7 | diag_ldtag_sel_c7 |
diag_ldvuad_sel_c7) ;
dff_s #(1) ff_diag_def_sel_c8
(.q (diag_def_sel_c8),
.din (diag_def_sel_c7),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign mux1_sel_data_c7[3] = diag_def_sel_c8 | rst_tri_en ;
////////////////////////////////////////////////////////////////////////////////
assign mux_csr_sel_c7 = csr_reg_rd_en_c8 ; // buferred here.
////////////////////////////////////////////////////////////////////////////////
// mux select to choose between
// inval and retdp data for oqarray_datain
////////////////////////////////////////////////////////////////////////////////
assign sel_inval_c7 = oqctl_sel_inval_c7 | diag_lddata_sel_c8 |
diag_ldtag_sel_c8 | diag_ldvuad_sel_c8 |
fwd_req_vld_ld_c7 ;
////////////////////////////////////////////////////////////////////////////////
// mux select for 3-1 mux in oqdp.
// sel0 .... old packet
// sel1 .... oq data
// sel2 .... def.
////////////////////////////////////////////////////////////////////////////////
assign out_mux1_sel_c7[0] = oqctl_sel_old_req_c7 ;
assign out_mux1_sel_c7[1] = oqctl_sel_oq_c7 ;
assign out_mux1_sel_c7[2] = ~(oqctl_sel_old_req_c7 | oqctl_sel_oq_c7 ) ;
////////////////////////////////////////////////////////////////////////////////
// mux2 select for 3-1 mux in oqdp.
// sel0.....oq,old or prev data
// sel1.....inval data
// sel2.....def
////////////////////////////////////////////////////////////////////////////////
assign sel_old_data_c7 = (oqctl_sel_old_req_c7 | oqctl_sel_oq_c7 |
oqctl_prev_data_c7);
assign out_mux2_sel_c7[0] = sel_old_data_c7 ;
assign out_mux2_sel_c7[1] = sel_inval_c7 & ~sel_old_data_c7 ;
assign out_mux2_sel_c7[2] = ~(sel_old_data_c7 | sel_inval_c7) ;
////////////////////////////////////////////////////////////////////////////////
// Directory in L2 is arranged in the form of 32 Panels (8 Rows x 4 Columns).
// Each panel contains 1 Set (4 Ways) for each of the 8 CPU. A Panel is selected
// for Camming based on address bit <4,5,8,9,10> for the D$ Cam and address bit
// <5,8,9,10,11> for the I$ Cam. In D$ bit <10,9,8> is used for selecting a Row
// and bit <5,4> is used for selecting the a Column. In I$ bit <10,9,8> is used
// for selecting a Row and bit <5,11> is used for selecting a Column.
//
// I$ and D$ Cam produce a 128 bit output which corresponds to the CAM hit or
// miss output bit for a Row of 4 Panels (each panel have 32 entry, 4 way of a
// set for each of the 8 cpu). In case of an eviction all the 128 bit of the
// D$ Cam and only 64 bits of the I$ Cam will be valid. In case of Load only
// 4 bit of the I$ cam output will be valid (For Load, if the data requested by
// a particular cpu is also present in the I$ of the same processor then that
// data in L1's I$ must be invalidated. So for a load only one panel in
// I$ Cam will be Cammed and only bits corresponding to that particular cpu will
// be relevant). In case of Imiss, in first cycle one set of the 4 bit of the
// D$ Cam output will be valid and in the second cycle another set of the 4 bit
// of the D$ Cam output will be valid.
// To mux out relevant 4 bits out of the 128 bit output from the I$ and D$ Cam
// Three stage muxing is done. First 8to1 muxing is done in 2 stages (first
// 4to1 and then 2to1) to mux out all the 16 bits corresponding a particular cpu.
// This muxing is done based on the cpu id. Then 4:1 muxing is done to select a
// particular column out of the four column, this is done based on the address
// bit <5,4> for the D$ and address bit <5,11> for the I$.
//
// sel_mux1_c6[3:0], sel_mux2_c6[3:0] and sel_mux3_c6 is used for the 8to1
// Muxing. sel_mux1_c6[3:0] & sel_mux2_c6[3:0] is used for the 4to1 muxing in
// the first stage and sel_mux3_c6 is used to do 2to1 muxing in the second
// stage.
// mux_vec_sel_c6[3:0] is used to do final 4to1 Muxing.
//
////////////////////////////////////////////////////////////////////////////////
// the arbdp_cpuid_c5 requires ~10 gates of setup.
dff_s #(3) ff_dirvec_cpuid_c6
(.q (inst_cpuid_c6[2:0]),
.din (arbdp_cpuid_c5[2:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
mux2ds #(3) mux_dirvec_cpuid_c5
(.dout (cpuid_c5[2:0]),
.in0 (arbdp_cpuid_c5[2:0]), .sel0 (~imiss1_out_c6),
.in1 (inst_cpuid_c6[2:0]), .sel1 (imiss1_out_c6)
) ;
assign dec_cpuid_c5[0] = (cpuid_c5 == 3'd0) ;
assign dec_cpuid_c5[1] = (cpuid_c5 == 3'd1) ;
assign dec_cpuid_c5[2] = (cpuid_c5 == 3'd2) ;
assign dec_cpuid_c5[3] = (cpuid_c5 == 3'd3) ;
assign dec_cpuid_c5[4] = (cpuid_c5 == 3'd4) ;
assign dec_cpuid_c5[5] = (cpuid_c5 == 3'd5) ;
assign dec_cpuid_c5[6] = (cpuid_c5 == 3'd6) ;
dff_s #(7) ff_dec_cpuid_c6
(.q (dec_cpuid_c6[6:0]),
.din (dec_cpuid_c5[6:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign sel_mux1_c6[0] = dec_cpuid_c6[0] & ~rst_tri_en ;
assign sel_mux1_c6[1] = dec_cpuid_c6[1] & ~rst_tri_en ;
assign sel_mux1_c6[2] = dec_cpuid_c6[2] & ~rst_tri_en ;
assign sel_mux1_c6[3] = ~(dec_cpuid_c6[0] | dec_cpuid_c6[1] |
dec_cpuid_c6[2]) | rst_tri_en ;
assign sel_mux2_c6[0] = dec_cpuid_c6[4] & ~rst_tri_en ;
assign sel_mux2_c6[1] = dec_cpuid_c6[5] & ~rst_tri_en ;
assign sel_mux2_c6[2] = dec_cpuid_c6[6] & ~rst_tri_en ;
assign sel_mux2_c6[3] = ~(dec_cpuid_c6[4] | dec_cpuid_c6[5] |
dec_cpuid_c6[6]) | rst_tri_en ;
assign sel_mux3_c6 = |(dec_cpuid_c6[3:0]) ;
////////////////////////////////////////////////////////////////////////////////
// mux selects for the mux that selects the data
// for way-wayvld bits of the cpx packet.
dff_s #(4) ff_lkup_bank_ena_icd_c5
(.q (lkup_bank_ena_icd_c5[3:0]),
.din (lkup_bank_ena_icd_c4[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_lkup_bank_ena_dcd_c5
(.q (lkup_bank_ena_dcd_c5[3:0]),
.din (lkup_bank_ena_dcd_c4[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign mux_vec_sel_c5[0] = (lkup_bank_ena_icd_c5[0] | lkup_bank_ena_dcd_c5[0] |
lkup_bank_ena_icd_c5[1]) ;
assign mux_vec_sel_c5[1] = lkup_bank_ena_dcd_c5[1] & ~mux_vec_sel_c5[0] ;
assign mux_vec_sel_c5[2] = (lkup_bank_ena_icd_c5[2] | lkup_bank_ena_dcd_c5[2] |
lkup_bank_ena_icd_c5[3]) &
~(mux_vec_sel_c5[0] | mux_vec_sel_c5[1]) ;
assign mux_vec_sel_c5[3] = ~(mux_vec_sel_c5[0] | mux_vec_sel_c5[1] |
mux_vec_sel_c5[2]) ;
dff_s #(4) ff_mux_vec_sel_c6
(.q (mux_vec_sel_c6_unqual[3:0]),
.din (mux_vec_sel_c5[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
assign mux_vec_sel_c6[0] = mux_vec_sel_c6_unqual[0] & ~rst_tri_en ;
assign mux_vec_sel_c6[1] = mux_vec_sel_c6_unqual[1] & ~rst_tri_en ;
assign mux_vec_sel_c6[2] = mux_vec_sel_c6_unqual[2] & ~rst_tri_en ;
assign mux_vec_sel_c6[3] = mux_vec_sel_c6_unqual[3] | rst_tri_en ;
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// TODO: Check if all pins are listed OK
module aes_cart(
// PROG top
input nPORTADRS,
input nSDPOE, SDPMPX,
input [11:8] SDPA,
inout [7:0] SDPAD,
input nRESET,
input CLK_68KCLKB,
input nPORTWEL, nPORTWEU, nPORTOEL, nPORTOEU,
input nROMOEL, nROMOEU,
input nAS, M68K_RW,
inout [15:0] M68K_DATA,
// PROG bottom
input [19:1] M68K_ADDR,
input nROMOE,
output nROMWAIT, nPWAIT1, nPWAIT0, PDTACK,
inout [7:0] SDRAD,
input [9:8] SDRA_L,
input [23:20] SDRA_U,
input SDRMPX, nSDROE,
input CLK_4MB,
// CHA top
input CLK_24M,
input nSDROM, nSDMRD,
input [15:0] SDA,
input SDRD1, SDRD0,
input [23:0] PBUS,
input CA4, LOAD, H, EVEN, S2H1,
input CLK_12M,
input PCK2B, PCK1B,
// CHA bottom
output [7:0] FIXD,
output DOTA, DOTB,
output [3:0] GAD,
output [3:0] GBD,
inout [7:0] SDD,
input CLK_8M
);
aes_prog PROG(nPORTADRS, nSDPOE, SDPMPX, SDPA, SDPAD, nRESET, CLK_68KCLKB, nPORTWEL, nPORTWEU,
nPORTOEL, nPORTOEU, nROMOEL, nROMOEU, nAS, M68K_RW, M68K_DATA, M68K_ADDR, nROMOE,
nROMWAIT, nPWAIT1, nPWAIT0, PDTACK, SDRAD, SDRA_L, SDRA_U, SDRMPX, nSDROE, CLK_4MB);
aes_cha CHA(CLK_24M, nSDROM, nSDMRD, SDA, SDRD1, SDRD0, PBUS, CA4, LOAD, H, EVEN, S2H1, CLK_12M,
PCK2B, PCK1B, FIXD, DOTA, DOTB, GAD, GBD, SDD, CLK_8M);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O31AI_2_V
`define SKY130_FD_SC_HDLL__O31AI_2_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o31ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o31ai_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O31AI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_1_V
`define SKY130_FD_SC_MS__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_1_V
|
module exercise_8_10 (output reg [1:0] state, input x, y, Clk);
initial state = 2'b00;
always @ (posedge Clk) begin
case ({x,y})
2'b00: begin if (state == 2'b00) state <= state;
else if (state == 2'b01) state <= 2'b10;
else if (state == 2'b10) state <= 2'b00;
else state <= 2'b10;
end
2'b01: begin if (state == 2'b00) state <= state;
else if (state == 2'b01) state <= 2'b11;
else if (state == 2'b10) state <= 2'b00;
else state <= state;
end
2'b10: begin if (state == 2'b00) state <= 2'b01;
else if (state == 2'b01) state <= 2'b10;
else if (state == 2'b10) state <= state;
else state <= 2'b00;
end
2'b11: begin if (state == 2'b00) state <= 2'b01;
else if (state == 2'b01) state <= 2'b11;
else if (state == 2'b10) state <= 2'b11;
else state <= 2'b00;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:55:21 05/03/2016
// Design Name:
// Module Name: data_deal
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module data_deal(
clk,
rst_n,
data_in,
data_in_sign,
data_out,
data_out_sign,
data_valid,
data_ok
);
input clk;
input rst_n;
input [7:0] data_in;
input data_in_sign;
output [7:0] data_out;
output data_out_sign;
input data_valid;
output data_ok;
reg [7:0] data_reg;
reg [3:0] data_regnum;
reg data_ok;
reg [7:0] data_out;
reg data_out_sign;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_reg <= 8'h0;
data_regnum <= 4'h0;
data_ok <= 1'h0;
end
else if(data_regnum == 4'h8) begin
data_ok <= ((data_reg == 8'd28)||(data_reg == 8'd36)) ? 1'b1 : 1'b0;
end
else if(data_regnum < 4'h8)begin
data_regnum <= data_in_sign ? data_regnum + 1'b1 : data_regnum;
data_reg <= data_in_sign ? (data_in + data_reg) : data_reg;
end
else
data_regnum <= data_regnum ;
end
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
data_out_sign <= 1'b0;
data_out <= 'h0;
end
else begin
if(~data_out_sign & data_valid) data_out_sign <= 1'b1;
else data_out_sign <= 1'b0;
data_out <= ~data_out_sign & data_valid ? data_out + 1'b1 : data_out;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2O_BLACKBOX_V
`define SKY130_FD_SC_LS__A2BB2O_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2O_BLACKBOX_V
|
/*!
* <b>Module:</b>ahci_dma_rd_stuff
* @file ahci_dma_rd_stuff.v
* @date 2016-01-01
* @author Andrey Filippov
*
* @brief Stuff DWORD data with missing words into continuous 32-bit data
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* ahci_dma_rd_stuff.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ahci_dma_rd_stuff.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module ahci_dma_rd_stuff(
input rst, // sync reset
input clk, // single clock
input din_av, // input data available
input din_avm_w,// >1 word of data available (early)
input din_avm, // >1 word of data available (registered din_avm_w)
input flushing, // output partial dword if available (should be ? cycles after last _re/ with data?)
input [31:0] din, // 32-bit input dfata
input [1:0] dm, // data mask showing which (if any) words in input dword are valid
output din_re, // read input data
output flushed, // flush (end of last PRD is finished - data left module)
output reg [31:0] dout, // output 32-bit data
output dout_vld, // output data valid
input dout_re, // consumer reads output data (should be AND-ed with dout_vld)
output last_DW
);
reg [15:0] hr; // holds 16-bit data from previous din_re if not consumed
reg hr_full;
reg [1:0] dout_vld_r;
reg din_av_safe_r;
reg din_re_r;
wire [1:0] dav_in = {2{din_av_safe_r}} & dm;
wire [1:0] drd_in = {2{din_re}} & dm;
wire [15:0] debug_din_low = din[15: 0];
wire [15:0] debug_din_high = din[31:16];
wire [15:0] debug_dout_low = dout[15: 0];
wire [15:0] debug_dout_high = dout[31:16];
// wire empty_in = din_av_safe_r && !(|dm);
// wire two_words_avail = &dav_in || (|dav_in && hr_full);
wire more_words_avail = |dav_in || hr_full;
wire [1:0] next_or_empty = {2{dout_re}} | ~dout_vld_r;
/// assign din_re = (din_av_safe_r && !(|dm)) || ((!dout_vld_r || dout_re) && (two_words_avail)) ; // flush
// ---------------
wire room_for2 = dout_re || (!(&dout_vld_r) && !hr_full) || !(|dout_vld_r);
wire room_for1 = dout_re || !hr_full || !(&dout_vld_r);
reg slow_down; // first time fifo almost empty
reg slow_dav; // enable dout_vld waiting after each read out not to miss last DWORD
reg last_DW_r;
reg last_dw_sent;
wire no_new_data_w;
reg [1:0] no_new_data_r;
assign din_re = din_av_safe_r && (!(|dm) || room_for2 || (room_for1 && !(&dm)));
/// assign dout_vld = (&dout_vld_r) || ((|dout_vld_r) && flushing);
assign dout_vld = (!slow_down && (&dout_vld_r)) || slow_dav;
assign last_DW = last_DW_r;
assign flushed = last_DW_r && dout_re;
assign no_new_data_w = !din_av && !hr_full;
// assign flushed =
always @ (posedge clk) begin
din_re_r <= din_re;
if (rst) din_av_safe_r <= 0;
else din_av_safe_r <= din_av && (din_avm || (!din_re && !din_re_r));
// set low word of the OR
if (rst) dout_vld_r[0] <= 0;
else if (next_or_empty[0]) dout_vld_r[0] <= hr_full || (din_re && (|dm));
if (next_or_empty[0]) begin
if (hr_full) dout[15: 0] <= hr;
else if (din_re) begin
if (dm[0]) dout[15: 0] <= din[15: 0];
else if (dm[1]) dout[15: 0] <= din[31:16];
end
end
// set high word of the OR
if (rst) dout_vld_r[1] <= 0;
else if (next_or_empty[1]) dout_vld_r[1] <= next_or_empty[0]?
(din_re && ((hr_full &&(|dm)) || (&dm))) :
(hr_full || (din_re && (|dm)));
if (next_or_empty[1]) begin
if (next_or_empty[0]) begin
if (din_re) begin
if (hr_full && dm[0]) dout[31:16] <= din[15: 0];
else if (dm[1] && (!hr_full || dm[0])) dout[31:16] <= din[31:16];
end
end else begin
if (hr_full) dout[31:16] <= hr;
else if (din_re) begin
if (dm[0]) dout[31:16] <= din[15: 0];
else if (dm[1]) dout[31:16] <= din[31:16];
end
end
end
// set holding register
if (rst) hr_full <= 0;
else if (((&next_or_empty) && !(&drd_in)) ||
((|next_or_empty) && !(|drd_in))) hr_full <= 0;
else if (((&drd_in) && !(&next_or_empty)) ||
((|drd_in) && !(|next_or_empty))) hr_full <= 1;
if (drd_in[1]) hr <= din[31:16];
else if (drd_in[0]) hr <= din[15: 0];
if (rst || !flushing) slow_down <= 0;
else if (!din_avm_w) slow_down <= 1;
if (rst || !flushing || last_dw_sent) slow_dav <= 0;
else slow_dav <= !dout_re && !last_dw_sent && ((!next_or_empty[1] && more_words_avail) || last_DW_r);
if (rst || !flushing) last_dw_sent <= 0;
else if (last_DW_r && dout_re) last_dw_sent <= 1;
no_new_data_r <= {no_new_data_r[0], no_new_data_w};
if (rst || !flushing) last_DW_r <= 0;
else if (slow_down && no_new_data_w && (&no_new_data_r)) last_DW_r <= 1;
else if (dout_re) last_DW_r <= 0;
end
endmodule
|
module mand_core (input clk,
input reset,
input [31:0] cx0,
input [31:0] cxstep, // will execute 11 threads
input [31:0] cy,
input rq,
output ack,
output [(7*11)-1:0] counters);
reg ack;
reg [(7*11)-1:0] counters;
/*
Since pipeline is 11-stage deep, we can issue 11 threads
one thread per cycle.
Once thread is retired, we check the output r, if it's > 16384,
thread is finalised, otherwise it is reschedulled back into
pipeline, increasing the counter.
When there are no active threads left, raise ACK and pass all the counters
as a 7*11-bit register.
*/
// control fsm
parameter S_IDLE = 0;
parameter S_ISSUE = 1;
parameter S_REISSUE = 2;
reg [2:0] state;
// pipeline input registers
reg [31:0] cx;
reg [31:0] i_vx;
reg [31:0] i_vy;
reg [31:0] i_dvx;
reg [31:0] i_dvy;
reg [6:0] i_counter;
reg [3:0] i_thrid;
wire [31:0] vx;
wire [31:0] vy;
wire [31:0] dvx;
wire [31:0] dvy;
wire [31:0] counter;
wire [31:0] thrid;
// pipeline stages registers:
reg [31:0] s00vx1;
reg [31:0] s00tmp1;
reg [31:0] s01tmp1A;
reg [31:0] s01tmp2;
reg [31:0] s01vx;
reg [31:0] s02vx;
reg [31:0] s02tmp1B;
reg [31:0] s02tmp2A;
reg [31:0] s03tmp1C;
reg [31:0] s03tmp2B;
reg [31:0] s03vx;
reg [31:0] s04tmp1D;
reg [31:0] s04tmp2C;
reg [31:0] s04vx;
reg [31:0] s05tmp2D;
reg [31:0] s05vy1;
reg [31:0] s05tmp3;
reg [31:0] s05vx;
reg [31:0] s06tmp3A;
reg [31:0] s06vx;
reg [31:0] s06vy;
reg [31:0] s06tmp2;
reg [31:0] s07tmp3B;
reg [31:0] s07vx;
reg [31:0] s07vy;
reg [31:0] s07tmp2;
reg [31:0] s08tmp3C;
reg [31:0] s08vx;
reg [31:0] s08vy;
reg [31:0] s08tmp2;
reg [31:0] s09tmp3D;
reg [31:0] s09vx;
reg [31:0] s09vy;
reg [31:0] s09tmp2;
reg [31:0] s10dvx;
reg [31:0] s10dvy;
reg [31:0] s10r;
reg [31:0] s10vx;
reg [31:0] s10vy;
// thrid and counter pipeline registers - just passing through
reg [3:0] s00thrid;
reg [3:0] s01thrid;
reg [3:0] s02thrid;
reg [3:0] s03thrid;
reg [3:0] s04thrid;
reg [3:0] s05thrid;
reg [3:0] s06thrid;
reg [3:0] s07thrid;
reg [3:0] s08thrid;
reg [3:0] s09thrid;
reg [3:0] s10thrid;
reg [6:0] s00counter;
reg [6:0] s01counter;
reg [6:0] s02counter;
reg [6:0] s03counter;
reg [6:0] s04counter;
reg [6:0] s05counter;
reg [6:0] s06counter;
reg [6:0] s07counter;
reg [6:0] s08counter;
reg [6:0] s09counter;
reg [6:0] s10counter;
// hoisted logic
wire [31:0] s05vy1_comb;
// xilinx ise does not infer a proper arithmetic shift for >>>
wire s1;
assign s1 = s04tmp1D[31];
assign s05vy1_comb = {s1,s1,s1,s1,s1,s1,s1,s1,s1,s1,s1,s04tmp1D[31:11]} + cy;
wire [31:0] s10dvx_comb;
wire [31:0] s10dvy_comb;
wire [31:0] s10r_comb;
wire s2;
assign s2 = s09tmp2[31];
assign s10dvx_comb = {s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s2,s09tmp2[31:12]};
wire s3;
assign s3 = s09tmp3D[31];
assign s10dvy_comb = {s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s3,s09tmp3D[31:12]};
assign s10r_comb = s10dvx_comb + s10dvy_comb;
/* reissue logic */
wire reissue;
assign reissue = (state == S_REISSUE) && (s10r < 16384) && (s10thrid !=0);
assign vx = reissue?s10vx:i_vx;
assign vy = reissue?s10vy:i_vy;
assign dvx = reissue?s10dvx:i_dvx;
assign dvy = reissue?s10dvy:i_dvy;
assign counter = reissue?s10counter+1:i_counter;
assign thrid = reissue?s10thrid:i_thrid;
always @(posedge clk)
if (!reset) begin
s00vx1 <= 0;
s00tmp1 <= 0;
s01tmp1A <= 0;
s01tmp2 <= 0;
s01vx <= 0;
s02vx <= 0;
s02tmp1B <= 0;
s02tmp2A <= 0;
s03tmp1C <= 0;
s03tmp2B <= 0;
s03vx <= 0;
s04tmp1D <= 0;
s04tmp2C <= 0;
s04vx <= 0;
s05tmp2D <= 0;
s05vy1 <= 0;
s05tmp3 <= 0;
s05vx <= 0;
s06tmp3A <= 0;
s06vx <= 0;
s06vy <= 0;
s06tmp2 <= 0;
s07tmp3B <= 0;
s07vx <= 0;
s07vy <= 0;
s07tmp2 <= 0;
s08tmp3C <= 0;
s08vx <= 0;
s08vy <= 0;
s08tmp2 <= 0;
s09tmp3D <= 0;
s09vx <= 0;
s09vy <= 0;
s09tmp2 <= 0;
s10dvx <= 0;
s10dvy <= 0;
s10r <= 0;
s10vx <= 0;
s10vy <= 0;
s00thrid <= 0;
s01thrid <= 0;
s02thrid <= 0;
s03thrid <= 0;
s04thrid <= 0;
s05thrid <= 0;
s06thrid <= 0;
s07thrid <= 0;
s08thrid <= 0;
s09thrid <= 0;
s10thrid <= 0;
s00counter <= 0;
s01counter <= 0;
s02counter <= 0;
s03counter <= 0;
s04counter <= 0;
s05counter <= 0;
s06counter <= 0;
s07counter <= 0;
s08counter <= 0;
s09counter <= 0;
s10counter <= 0;
end else begin // if (!reset)
// Flush thrid through the pipeline
s00thrid <= thrid;
s01thrid <= s00thrid;
s02thrid <= s01thrid;
s03thrid <= s02thrid;
s04thrid <= s03thrid;
s05thrid <= s04thrid;
s06thrid <= s05thrid;
s07thrid <= s06thrid;
s08thrid <= s07thrid;
s09thrid <= s08thrid;
s10thrid <= s09thrid;
s00counter <= counter;
s01counter <= s00counter;
s02counter <= s01counter;
s03counter <= s02counter;
s04counter <= s03counter;
s05counter <= s04counter;
s06counter <= s05counter;
s07counter <= s06counter;
s08counter <= s07counter;
s09counter <= s08counter;
s10counter <= s09counter;
// Stage0
// Inputs: dvx, dvy, cx, dy, vx, vy
s00vx1 <= dvx - dvy + cx;
s00tmp1 <= vx * vy;
// Stage1
s01tmp1A <= s00tmp1;
s01tmp2 <= s00vx1 * s00vx1;
s01vx <= s00vx1;
// Stage2
s02tmp1B <= s01tmp1A;
s02tmp2A <= s01tmp2;
s02vx <= s01vx;
// Stage3
s03tmp1C <= s02tmp1B;
s03tmp2B <= s02tmp2A;
s03vx <= s02vx;
// Stage4
s04tmp1D <= s03tmp1C;
s04tmp2C <= s03tmp2B;
s04vx <= s03vx;
// Stage5
s05tmp2D <= s04tmp2C;
s05vy1 <= s05vy1_comb; // (signed s04tmp1D >>> 11) + cy
s05tmp3 <= s05vy1_comb * s05vy1_comb;
s05vx <= s04vx;
// Stage6
s06tmp3A <= s05tmp3;
s06vx <= s05vx;
s06vy <= s05vy1;
s06tmp2 <= s05tmp2D;
// Stage7
s07tmp3B <= s06tmp3A;
s07vx <= s06vx;
s07vy <= s06vy;
s07tmp2 <= s06tmp2;
// Stage8
s08tmp3C <= s07tmp3B;
s08vx <= s07vx;
s08vy <= s07vy;
s08tmp2 <= s07tmp2;
// Stage9
s09tmp3D <= s08tmp3C;
s09vx <= s08vx;
s09vy <= s08vy;
s09tmp2 <= s08tmp2;
// Stage10
s10dvx <= s10dvx_comb;
s10dvy <= s10dvy_comb;
s10r <= s10r_comb;
s10vx <= s09vx;
s10vy <= s09vy;
end
// Main loop, thread management
reg [3:0] thrid1;
reg [6:0] iterations;
wire [(11*7)-1:0] counters_comb;
assign counters_comb =
{
(s10thrid==11)?s10counter:counters[(11*7)-1:10*7],
(s10thrid==10)?s10counter:counters[(10*7)-1:9*7],
(s10thrid==9)?s10counter:counters[( 9*7)-1:8*7],
(s10thrid==8)?s10counter:counters[( 8*7)-1:7*7],
(s10thrid==7)?s10counter:counters[( 7*7)-1:6*7],
(s10thrid==6)?s10counter:counters[( 6*7)-1:5*7],
(s10thrid==5)?s10counter:counters[( 5*7)-1:4*7],
(s10thrid==4)?s10counter:counters[( 4*7)-1:3*7],
(s10thrid==3)?s10counter:counters[( 3*7)-1:2*7],
(s10thrid==2)?s10counter:counters[(2*7)-1:1*7],
(s10thrid==1)?s10counter:counters[(1*7)-1:0]};
reg [4:0] reissues;
always @(posedge clk)
if (!reset) begin
state <= S_IDLE;
i_thrid <= 0;
i_dvx <= 0;
i_dvy <= 0;
i_vx <= 0;
i_vy <= 0;
counters <= 0;
iterations <= 0;
thrid1 <= 0;
ack <= 0;
cx <= 0;
reissues <= 0;
end else begin
counters <= counters_comb;
case(state)
S_IDLE: if (rq) begin
state <= S_ISSUE;
i_thrid <= 1;
cx <= cx0;
i_dvx <= 0;
i_dvy <= 0;
i_vx <= 0;
i_vy <= 0;
counters <= 0;
iterations <= 0;
ack <= 0;
reissues <= 0;
end
S_ISSUE: begin
i_thrid <= i_thrid + 1;
cx <= cx + cxstep;
if (i_thrid == 11) begin
cx <= cx0;
state <= S_REISSUE;
i_thrid <= 0;
i_counter <= 0;
thrid1 <= 1;
end
end
S_REISSUE: begin
if (thrid1 == 11) begin
cx <= cx0;
thrid1 <= 1;
reissues <= 0;
if (iterations == 100 || reissues == 0) begin
state <= S_IDLE;
ack <= 1;
end else begin
iterations <= iterations + 1;
end
end else begin
cx <= cx + cxstep;
thrid1 <= thrid1 + 1;
reissues <= reissues + reissue?1:0;
end
end
endcase
end
endmodule
|
/* verilator lint_off STMTDLY */
module dv_ctrl(/*AUTOARG*/
// Outputs
nreset, clk1, clk2, start, vdd, vss,
// Inputs
dut_active, stim_done, test_done
);
parameter CFG_CLK1_PERIOD = 10;
parameter CFG_CLK1_PHASE = CFG_CLK1_PERIOD/2;
parameter CFG_CLK2_PERIOD = 100;
parameter CFG_CLK2_PHASE = CFG_CLK2_PERIOD/2;
parameter CFG_TIMEOUT = 50000;
output nreset; // async active low reset
output clk1; // main clock
output clk2; // secondary clock
output start; // start test (level)
output vdd; // driving vdd
output vss; // driving vss
input dut_active; // reset sequence is done
input stim_done; //stimulus is done
input test_done; //test is done
//signal declarations
reg vdd;
reg vss;
reg nreset;
reg start;
reg clk1=0;
reg clk2=0;
reg [6:0] clk1_phase;
reg [6:0] clk2_phase;
integer seed,r;
//#################################
// RANDOM NUMBER GENERATOR
// (SEED SUPPLIED EXERNALLY)
//#################################
initial
begin
r=$value$plusargs("SEED=%s", seed);
$display("SEED=%d", seed);
`ifdef CFG_RANDOM
clk1_phase = 1 + {$random(seed)}; //generate random values
clk2_phase = 1 + {$random(seed)}; //generate random values
`else
clk1_phase = CFG_CLK1_PHASE;
clk2_phase = CFG_CLK2_PHASE;
`endif
$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);
end
//#################################
//CLK1 GENERATOR
//#################################
always
#(clk1_phase) clk1 = ~clk1; //add one to avoid "DC" state
//#################################
//CLK2 GENERATOR
//#################################
always
#(clk2_phase) clk2 = ~clk2;
//#################################
//ASYNC
//#################################
initial
begin
#(1)
nreset = 'b0;
vdd = 'b0;
vss = 'b0;
#(clk1_phase * 10 + 100) //ramping voltage
vdd = 'bx;
#(clk1_phase * 10 + 100) //voltage is safe
vdd = 'b1;
#(clk1_phase * 40 + 100) //hold reset for 20 clk cycles
nreset = 'b1;
end
//#################################
//SYNCHRONOUS STIMULUS
//#################################
//START TEST
always @ (posedge clk1 or negedge nreset)
if(!nreset)
start = 1'b0;
else if(dut_active)
start = 1'b1;
//STOP SIMULATION
always @ (posedge clk1)
if(stim_done & test_done)
#(CFG_TIMEOUT) $finish;
//WAVEFORM DUMP
//Better solution?
`ifndef VERILATOR
initial
begin
$dumpfile("waveform.vcd");
$dumpvars(0, dv_top);
end
`endif
endmodule // dv_ctrl
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Stefan Wendler
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/**
* Simple Clock Devider
*
* Devides a given input clock.
*
* parameters:
* div count which is used to devide the input clock
* inputs:
* clk_i input clock
* outputs:
* clk_o output clock
*/
module clkdiv(
input rst,
input clk_i,
input [15:0] div,
output clk_o
);
reg r_clk_o = 1'b0;
reg [15:0] count = 16'h0;
always @(posedge clk_i) begin
if(rst) begin
r_clk_o = 1'b0;
count = 16'h0;
end
else begin
count = count + 1;
if(count == div) begin
count = 16'h0;
r_clk_o = ~r_clk_o;
end
end
end
assign clk_o = r_clk_o;
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
/*
tab size 4
*/
module jt51_pg(
input clk,
input zero,
// Channel frequency
input [6:0] kc_I,
input [5:0] kf_I,
// Operator multiplying
input [3:0] mul_VI,
// Operator detuning
input [2:0] dt1_II,
input [1:0] dt2_I,
// phase modulation from LFO
input [7:0] pm,
input [2:0] pms_I,
// phase operation
input pg_rst_III,
output reg [ 4:0] keycode_III,
output [ 9:0] pg_phase_X
);
wire [19:0] ph_VII;
reg [19:0] phase_base_VI, phase_step_VII, ph_VIII;
reg [17:0] phase_base_IV, phase_base_V;
wire pg_rst_VII;
wire [11:0] phinc_III;
reg [ 9:0] phinc_addr_III;
reg [13:0] keycode_II;
reg [5:0] dt1_kf_III;
reg [ 2:0] dt1_kf_IV;
reg [4:0] pow2;
reg [4:0] dt1_offset_V;
reg [2:0] pow2ind_IV;
reg [2:0] dt1_III, dt1_IV, dt1_V;
jt51_phinc_rom u_phinctable(
// .clk ( clk ),
.keycode( phinc_addr_III[9:0] ),
.phinc ( phinc_III )
);
always @(*) begin : calcpow2
case( pow2ind_IV )
3'd0: pow2 = 5'd16;
3'd1: pow2 = 5'd17;
3'd2: pow2 = 5'd19;
3'd3: pow2 = 5'd20;
3'd4: pow2 = 5'd22;
3'd5: pow2 = 5'd24;
3'd6: pow2 = 5'd26;
3'd7: pow2 = 5'd29;
endcase
end
reg [5:0] dt1_limit, dt1_unlimited;
reg [4:0] dt1_limited_IV;
always @(*) begin : dt1_limit_mux
case( dt1_IV[1:0] )
default: dt1_limit = 5'd8;
2'd1: dt1_limit = 5'd8;
2'd2: dt1_limit = 5'd16;
2'd3: dt1_limit = 5'd22;
endcase
case( dt1_kf_IV )
3'd0: dt1_unlimited = { 5'd0, pow2[4] }; // <2
3'd1: dt1_unlimited = { 4'd0, pow2[4:3] }; // <4
3'd2: dt1_unlimited = { 3'd0, pow2[4:2] }; // <8
3'd3: dt1_unlimited = { 2'd0, pow2[4:1] };
3'd4: dt1_unlimited = { 1'd0, pow2[4:0] };
3'd5: dt1_unlimited = { pow2[4:0], 1'd0 };
default:dt1_unlimited = 6'd0;
endcase
dt1_limited_IV = dt1_unlimited > dt1_limit ?
dt1_limit : dt1_unlimited[4:0];
end
reg signed [8:0] mod_I;
always @(*) begin
case( pms_I ) // comprobar en silicio
3'd0: mod_I = 9'd0;
3'd1: mod_I = { 7'd0, pm[6:5] };
3'd2: mod_I = { 6'd0, pm[6:4] };
3'd3: mod_I = { 5'd0, pm[6:3] };
3'd4: mod_I = { 4'd0, pm[6:2] };
3'd5: mod_I = { 3'd0, pm[6:1] };
3'd6: mod_I = { 1'd0, pm[6:0], 1'b0 };
3'd7: mod_I = { pm[6:0], 2'b0 };
endcase
end
reg [3:0] octave_III;
wire [12:0] keycode_I;
jt51_pm u_pm(
// Channel frequency
.kc_I ( kc_I ),
.kf_I ( kf_I ),
.add ( ~pm[7] ),
.mod_I ( mod_I ),
.kcex ( keycode_I )
);
// limit value at which we add +64 to the keycode
// I assume this is to avoid the note==3 violation somehow
parameter dt2_lim2 = 8'd11 + 8'd64;
parameter dt2_lim3 = 8'd31 + 8'd64;
// I
always @(posedge clk) begin : phase_calculation
case ( dt2_I )
2'd0: keycode_II <= { 1'b0, keycode_I } +
(keycode_I[7:6]==2'd3 ? 14'd64:14'd0);
2'd1: keycode_II <= { 1'b0, keycode_I } + 14'd512 +
(keycode_I[7:6]==2'd3 ? 14'd64:14'd0);
2'd2: keycode_II <= { 1'b0, keycode_I } + 14'd628 +
(keycode_I[7:0]>dt2_lim2 ? 14'd64:14'd0);
2'd3: keycode_II <= { 1'b0, keycode_I } + 14'd800 +
(keycode_I[7:0]>dt2_lim3 ? 14'd64:14'd0);
endcase
end
// II
always @(posedge clk) begin
phinc_addr_III <= keycode_II[9:0];
octave_III <= keycode_II[13:10];
keycode_III <= keycode_II[12:8];
case( dt1_II[1:0] )
2'd1: dt1_kf_III <= keycode_II[13:8] - (6'b1<<2);
2'd2: dt1_kf_III <= keycode_II[13:8] + (6'b1<<2);
2'd3: dt1_kf_III <= keycode_II[13:8] + (6'b1<<3);
default:dt1_kf_III <= keycode_II[13:8];
endcase
dt1_III <= dt1_II;
end
// III
always @(posedge clk) begin
case( octave_III )
4'd0: phase_base_IV <= { 8'd0, phinc_III[11:2] };
4'd1: phase_base_IV <= { 7'd0, phinc_III[11:1] };
4'd2: phase_base_IV <= { 6'd0, phinc_III[11:0] };
4'd3: phase_base_IV <= { 5'd0, phinc_III[11:0], 1'b0 };
4'd4: phase_base_IV <= { 4'd0, phinc_III[11:0], 2'b0 };
4'd5: phase_base_IV <= { 3'd0, phinc_III[11:0], 3'b0 };
4'd6: phase_base_IV <= { 2'd0, phinc_III[11:0], 4'b0 };
4'd7: phase_base_IV <= { 1'd0, phinc_III[11:0], 5'b0 };
4'd8: phase_base_IV <= { phinc_III[11:0], 6'b0 };
default:phase_base_IV <= 18'd0;
endcase
pow2ind_IV <= dt1_kf_III[2:0];
dt1_IV <= dt1_III;
dt1_kf_IV <= dt1_kf_III[5:3];
end
// IV LIMIT_BASE
always @(posedge clk) begin
if( phase_base_IV > 18'd82976 )
phase_base_V <= 18'd82976;
else
phase_base_V <= phase_base_IV;
dt1_offset_V <= dt1_limited_IV;
dt1_V <= dt1_IV;
end
// V APPLY_DT1
always @(posedge clk) begin
if( dt1_V[1:0]==2'd0 )
phase_base_VI <= phase_base_V;
else begin
if( !dt1_V[2] )
phase_base_VI <= phase_base_V + dt1_offset_V;
else
phase_base_VI <= phase_base_V - dt1_offset_V;
end
end
// VI APPLY_MUL
always @(posedge clk) begin
if( mul_VI==4'd0 )
phase_step_VII <= { 1'b0, phase_base_VI[19:1] };
else
phase_step_VII <= phase_base_VI * mul_VI;
end
// VII have same number of stages as jt51_envelope
always @(posedge clk) begin
ph_VIII <= pg_rst_VII ? 20'd0 : ph_VII + phase_step_VII;
`ifdef DISPLAY_STEP
$display( "%d", phase_step_VII );
`endif
end
// VIII
reg [19:0] ph_IX;
always @(posedge clk)
ph_IX <= ph_VIII[19:0];
// IX
reg [19:0] ph_X;
assign pg_phase_X = ph_X[19:10];
always @(posedge clk)
ph_X <= ph_IX;
jt51_sh #( .width(20), .stages(32-3) ) u_phsh(
.clk ( clk ),
.din ( ph_X ),
.drop ( ph_VII )
);
jt51_sh #( .width(1), .stages(4) ) u_pgrstsh(
.clk ( clk ),
.din ( pg_rst_III),
.drop ( pg_rst_VII)
);
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt;
sep32_cnt u_sep32_cnt (.clk(clk), .zero(zero), .cnt(cnt));
/*
wire zero_VIII;
jt51_sh #(.width(1),.stages(7)) u_sep_aux(
.clk ( clk ),
.din ( zero ),
.drop ( zero_VIII )
);
sep32 #(.width(1),.stg(8)) sep_ref(
.clk ( clk ),
.mixed ( zero_VIII ),
.cnt ( cnt )
);
*/
sep32 #(.width(10),.stg(10)) sep_ph(
.clk ( clk ),
.mixed ( pg_phase_X ),
.cnt ( cnt )
);
/* verilator lint_on PINMISSING */
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND3_PP_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_PP_BLACKBOX_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 11
(* X_CORE_INFO = "axi_protocol_converter_v2_1_11_axi_protocol_converter,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_pc_0,axi_protocol_converter_v2_1_11_axi_protocol_converter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=11,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WI\
DTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_11_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_4_V
`define SKY130_FD_SC_MS__A32OI_4_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__XOR2_BEHAVIORAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XOR2_BEHAVIORAL_V
|
//====================================================================
// bsg_fsb_node_async_buffer.v
// 19/05/2018, [email protected]
//====================================================================
//
//This module converts the bsg_fsb node signals between different
//clock domains.
//
//default: FSB on Right,
// NODE on Left
`include "bsg_defines.v"
`ifndef FSB_LEGACY
module bsg_fsb_node_async_buffer
#( parameter `BSG_INV_PARAM(ring_width_p)
,parameter fifo_els_p = 2
)
(
/////////////////////////////////////////////
// signals on the node side
input L_clk_i
, input L_reset_i
// control
, output L_en_o // FIXME unused
// input channel
, output L_v_o
, output [ring_width_p-1:0] L_data_o
, input L_ready_i
// output channel
, input L_v_i
, input [ring_width_p-1:0] L_data_i
, output L_yumi_o // late
/////////////////////////////////////////////
// signals on the FSB side
, input R_clk_i
, input R_reset_i
// control
, input R_en_i // FIXME unused
// input channel
, input R_v_i
, input [ring_width_p-1:0] R_data_i
, output R_ready_o
// output channel
, output R_v_o
, output [ring_width_p-1:0] R_data_o
, input R_yumi_i // late
);
localparam fifo_lg_size_lp = `BSG_SAFE_CLOG2( fifo_els_p );
////////////////////////////////////////////////////////////////////////////////////////
// Covert FSB to NODE packet signals
// FSB == w
// NODE == r
wire R_w_full_lo ;
assign R_ready_o = ~R_w_full_lo ;
bsg_async_fifo #(.lg_size_p ( fifo_lg_size_lp )
,.width_p ( ring_width_p )
)r2l_fifo
(
.w_clk_i ( R_clk_i )
,.w_reset_i ( R_reset_i )
// not legal to w_enq_i if w_full_o is not low.
,.w_enq_i ( (~R_w_full_lo) & R_v_i )
,.w_data_i ( R_data_i )
,.w_full_o ( R_w_full_lo )
// not legal to r_deq_i if r_valid_o is not high.
,.r_clk_i ( L_clk_i )
,.r_reset_i ( L_reset_i )
,.r_deq_i ( L_v_o & L_ready_i )
,.r_data_o ( L_data_o )
,.r_valid_o ( L_v_o )
);
////////////////////////////////////////////////////////////////////////////////////////
// Covert NODE to FSB packet signals
// FSB == r
// NODE == w
wire L_w_full_lo ;
assign L_yumi_o = (~L_w_full_lo) & L_v_i ;
bsg_async_fifo #(.lg_size_p ( fifo_lg_size_lp )
,.width_p ( ring_width_p )
)l2r_fifo
(
.w_clk_i ( L_clk_i )
,.w_reset_i ( L_reset_i )
// not legal to w_enq_i if w_full_o is not low.
,.w_enq_i ( L_yumi_o )
,.w_data_i ( L_data_i )
,.w_full_o ( L_w_full_lo)
// not legal to r_deq_i if r_valid_o is not high.
,.r_clk_i ( R_clk_i )
,.r_reset_i ( R_reset_i )
,.r_deq_i ( R_yumi_i )
,.r_data_o ( R_data_o )
,.r_valid_o ( R_v_o )
);
bsg_sync_sync #(.width_p(1)) fsb_en_sync
(
.oclk_i ( L_clk_i ) //TODO
, .iclk_data_i ( R_en_i )
, .oclk_data_o ( L_en_o )
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fsb_node_async_buffer)
`else
// | ____/ ____| _ \ | | | ____/ ____| /\ / ____\ \ / /
// | |__ | (___ | |_) || | | |__ | | __ / \ | | \ \_/ /
// | __| \___ \| _ < | | | __|| | |_ | / /\ \| | \ /
// | | ____) | |_) || |____| |___| |__| |/ ____ \ |____ | |
// |_| |_____/|____/ |______|______\_____/_/ \_\_____| |_|
// ______
// |______|
module bsg_fsb_node_async_buffer
import bsg_fsb_pkg::*;
#( parameter `BSG_INV_PARAM(ring_width_p)
,parameter fifo_els_p = 2
)
(
/////////////////////////////////////////////
// signals on the node side
input L_clk_i
, input L_reset_i
// control
, output L_en_o // FIXME unused
// input channel
, output L_v_o
, output [ring_width_p-1:0] L_data_o
, input L_ready_i
// output channel
, input L_v_i
, input [ring_width_p-1:0] L_data_i
, output L_yumi_o // late
/////////////////////////////////////////////
// signals on the FSB side
, input R_clk_i
, input R_reset_i
// control
, input R_en_i // FIXME unused
// input channel
, input R_v_i
, input [ring_width_p-1:0] R_data_i
, output R_ready_o
// output channel
, output R_v_o
, output [ring_width_p-1:0] R_data_o
, input R_yumi_i // late
);
localparam fifo_lg_size_lp = `BSG_SAFE_CLOG2( fifo_els_p );
////////////////////////////////////////////////////////////////////////////////////////
// Covert FSB to NODE packet signals
// FSB == w
// NODE == r
wire R_w_full_lo ;
assign R_ready_o = ~R_w_full_lo ;
bsg_async_fifo #(.lg_size_p ( fifo_lg_size_lp )
,.width_p ( ring_width_p )
)r2l_fifo
(
.w_clk_i ( R_clk_i )
,.w_reset_i ( R_reset_i )
// not legal to w_enq_i if w_full_o is not low.
,.w_enq_i ( (~R_w_full_lo) & R_v_i )
,.w_data_i ( R_data_i )
,.w_full_o ( R_w_full_lo )
// not legal to r_deq_i if r_valid_o is not high.
,.r_clk_i ( L_clk_i )
,.r_reset_i ( L_reset_i )
,.r_deq_i ( L_v_o & L_ready_i )
,.r_data_o ( L_data_o )
,.r_valid_o ( L_v_o )
);
////////////////////////////////////////////////////////////////////////////////////////
// Covert NODE to FSB packet signals
// FSB == r
// NODE == w
wire L_w_full_lo ;
assign L_yumi_o = (~L_w_full_lo) & L_v_i ;
bsg_async_fifo #(.lg_size_p ( fifo_lg_size_lp )
,.width_p ( ring_width_p )
)l2r_fifo
(
.w_clk_i ( L_clk_i )
,.w_reset_i ( L_reset_i )
// not legal to w_enq_i if w_full_o is not low.
,.w_enq_i ( L_yumi_o )
,.w_data_i ( L_data_i )
,.w_full_o ( L_w_full_lo)
// not legal to r_deq_i if r_valid_o is not high.
,.r_clk_i ( R_clk_i )
,.r_reset_i ( R_reset_i )
,.r_deq_i ( R_yumi_i )
,.r_data_o ( R_data_o )
,.r_valid_o ( R_v_o )
);
bsg_sync_sync #(.width_p(1)) fsb_en_sync
(
.oclk_i ( L_clk_i ) //TODO
, .iclk_data_i ( R_en_i )
, .oclk_data_o ( L_en_o )
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fsb_node_async_buffer)
`endif
|
`timescale 1ns / 1ps
/*
-- Module Name: Selector
-- Description: Seleccion de peticion activa para este ciclo de reloj.
El uso de algoritmos adaptativos o semi adaptativos
produce una o mas salidas validas para un paquete. Sin
embargo la solicitud de dos o mas puertos de salida a la
vez puede ocacionar dupliacion o liberacion de paquetes
corruptos a la red.
Este modulo recibe una o mas solicitudes para los
"planificadores de salida", pero solo permite la salida
de una peticion a la vez.
La seleccion de peticion activa depende de un esquema de
prioridad y de la disponibilidad de puertos.
-- Dependencies: -- system.vh
-- Parameters: -- PORT_DIR: Direccion del puerto de entrada
conectado a este modulo {x+, y+
x-, y-}.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
(05/06/2015) El esquema de prioridad utilizado es fijo, y otorga
preferencia de salida en el siguiente orden {pe, x+, y+, x-, y-}
-- History:
-- Creacion 05 de Junio 2015
*/
`include "system.vh"
module selector #(
parameter PORT_DIR = `X_POS
)
(
// -- inputs ------------------------------------------------- >>>>>
input wire [3:0] request_vector_din,
input wire transfer_strobe_din,
input wire [3:0] status_register_din,
// -- outputs ------------------------------------------------ >>>>>
output reg [3:0] masked_request_vector_dout
);
/*
-- Si se a aceptado una transferencia (transfer_strobe_din) se anula
toda peticion saliendo del selector.
En caso contrario se aplica una primera etapa de enmascarado, donde
solo se permite pasar las peticiones de puertos que se encuentran
disponibles actualmente.
*/
wire [3:0] masked_request;
assign masked_request = (transfer_strobe_din) ? {4{1'b0}} :
request_vector_din & status_register_din;
/*
-- Segunda etapa de filtrado. En esta etapa se aplica un esquema de
prioridad de peticion. El esquema es fijo y da prioridad en el
siguiente orden: {pe, x+, y+, x-, y-}
El puerto de entrada ligado al "selector" determina que direcciones
pueden recibir una peticion. Ej. El selector ligado al puerto x+ no
puede emitir una solicitud a su misma direccion (x+). Solo uno de
los casos de abajo es sintetizado a la vez y es seleccionado por el
parametro: PORT_DIR.
*/
always @(*)
begin
masked_request_vector_dout = 4'b0000;
// -- Selector de Peticion puerto de entrada PE ------ >>>>>
if (PORT_DIR == `PE)
begin
if (masked_request[`PE_XPOS])
masked_request_vector_dout = 4'b0001;
else if (masked_request[`PE_YPOS])
masked_request_vector_dout = 4'b0010;
else if (masked_request[`PE_XNEG])
masked_request_vector_dout = 4'b0100;
else if (masked_request[`PE_YNEG])
masked_request_vector_dout = 4'b1000;
else
masked_request_vector_dout = 4'b0000;
end //PORT_DIR == PE
// -- Selector de Peticion puerto de entrada X+ ------ >>>>>
else if (PORT_DIR == `X_POS)
begin
if (masked_request[`XPOS_PE])
masked_request_vector_dout = 4'b0001;
else if (masked_request[`XPOS_YPOS])
masked_request_vector_dout = 4'b0010;
else if (masked_request[`XPOS_XNEG])
masked_request_vector_dout = 4'b0100;
else if (masked_request[`XPOS_YNEG])
masked_request_vector_dout = 4'b1000;
else
masked_request_vector_dout = 4'b0000;
end //PORT_DIR == X+
// -- Selector de Peticion puerto de entrada Y+ ------ >>>>>
else if (PORT_DIR == `Y_POS)
begin
if (masked_request[`YPOS_PE])
masked_request_vector_dout = 4'b0001;
else if (masked_request[`YPOS_XPOS])
masked_request_vector_dout = 4'b0010;
else if (masked_request[`YPOS_XNEG])
masked_request_vector_dout = 4'b0100;
else if (masked_request[`YPOS_YNEG])
masked_request_vector_dout = 4'b1000;
else
masked_request_vector_dout = 4'b0000;
end //PORT_DIR == Y+
// -- Selector de Peticion puerto de entrada X- ------ >>>>>
else if (PORT_DIR == `X_NEG)
begin
if (masked_request[`XNEG_PE])
masked_request_vector_dout = 4'b0001;
else if (masked_request[`XNEG_XPOS])
masked_request_vector_dout = 4'b0010;
else if (masked_request[`XNEG_YPOS])
masked_request_vector_dout = 4'b0100;
else if (masked_request[`XNEG_YNEG])
masked_request_vector_dout = 4'b1000;
else
masked_request_vector_dout = 4'b0000;
end //PORT_DIR == X-
// -- Selector de Peticion puerto de entrada Y- ------ >>>>>
else if (PORT_DIR == `Y_NEG)
begin
if (masked_request[`YNEG_PE])
masked_request_vector_dout = 4'b0001;
else if (masked_request[`YNEG_XPOS])
masked_request_vector_dout = 4'b0010;
else if (masked_request[`YNEG_YPOS])
masked_request_vector_dout = 4'b0100;
else if (masked_request[`YNEG_XNEG])
masked_request_vector_dout = 4'b1000;
else
masked_request_vector_dout = 4'b0000;
end //PORT_DIR == Y-
end //*
// -- Codigo no sintetizable ------------------------------------- >>>>>
// -- Simbolos de Depuracion ------------------------------------- >>>>>
reg [(16*8)-1:0] masked_request_dbg;
always @(*)
// -- Route Planner :: LC | PE ------------------------------- >>>>>
if (PORT_DIR == `PE)
begin
masked_request_dbg[127-:32] = (masked_request_vector_dout[`PE_XPOS]) ?
"X+, " : " ";
masked_request_dbg[95-:32] = (masked_request_vector_dout[`PE_YPOS]) ?
"Y+, " : " ";
masked_request_dbg[63-:32] = (masked_request_vector_dout[`PE_XNEG]) ?
"X-, " : " ";
masked_request_dbg[31 :0] = (masked_request_vector_dout[`PE_YNEG]) ?
"Y-, " : " ";
end
// -- Route Planner :: LC | X+ ------------------------------- >>>>>
else if(PORT_DIR == `X_POS)
begin
masked_request_dbg[127-:32] = (masked_request_vector_dout[`XPOS_PE]) ?
"PE, " : " ";
masked_request_dbg[95-:32] = (masked_request_vector_dout[`XPOS_YPOS]) ?
"Y+, " : " ";
masked_request_dbg[63-:32] = (masked_request_vector_dout[`XPOS_XNEG]) ?
"X-, " : " ";
masked_request_dbg[31 :0] = (masked_request_vector_dout[`XPOS_YNEG]) ?
"Y-, " : " ";
end
// -- Route Planner :: LC | Y+ ------------------------------- >>>>>
else if(PORT_DIR == `Y_POS)
begin
masked_request_dbg[127-:32] = (masked_request_vector_dout[`YPOS_PE]) ?
"PE, " : " ";
masked_request_dbg[95-:32] = (masked_request_vector_dout[`YPOS_XPOS]) ?
"X+, " : " ";
masked_request_dbg[63-:32] = (masked_request_vector_dout[`YPOS_XNEG]) ?
"X-, " : " ";
masked_request_dbg[31 :0] = (masked_request_vector_dout[`YPOS_YNEG]) ?
"Y-, " : " ";
end
// -- Route Planner :: LC | X- ------------------------------- >>>>>
else if(PORT_DIR == `X_NEG)
begin
masked_request_dbg[127-:32] = (masked_request_vector_dout[`XNEG_PE]) ?
"PE, " : " ";
masked_request_dbg[95-:32] = (masked_request_vector_dout[`XNEG_XPOS]) ?
"X+, " : " ";
masked_request_dbg[63-:32] = (masked_request_vector_dout[`XNEG_YPOS]) ?
"Y+, " : " ";
masked_request_dbg[31 :0] = (masked_request_vector_dout[`XNEG_YNEG]) ?
"Y-, " : " ";
end
// -- Route Planner :: LC | Y- ------------------------------- >>>>>
else if(PORT_DIR == `Y_NEG)
begin
masked_request_dbg[127-:32] = (masked_request_vector_dout[`YNEG_PE]) ?
"PE, " : " ";
masked_request_dbg[95-:32] = (masked_request_vector_dout[`YNEG_XPOS]) ?
"X+, " : " ";
masked_request_dbg[63-:32] = (masked_request_vector_dout[`YNEG_YPOS]) ?
"Y+, " : " ";
masked_request_dbg[31 :0] = (masked_request_vector_dout[`YNEG_XNEG]) ?
"X-, " : " ";
end
endmodule
/* -- Plantilla de Instancia ------------------------------------ >>>>>>
wire [3:0] masked_request_vector;
selector selector #(
.PORT_DIR (PORT_DIR)
)
(
// -- inputs --------------------------------------------- >>>>>
.request_vector_din (request_vector_din),
.transfer_strobe_din (transfer_strobe_din),
.status_register_din (status_register_din),
// -- outputs -------------------------------------------- >>>>>
.masked_request_vector_dout (masked_request_vector)
);
*/
|
/*
* uart_tx.v
*
* Created on: 17.04.2016
* Author: Alexander Antonov <[email protected]>
* License: See LICENSE file for details
*/
module uart_tx
#(
parameter RTX_EXTERNAL_OVERRIDE = "NO"
)
(
input clk_i, rst_i,
input tx_start_i,
input [7:0] din_bi,
input locked_i,
input [28:0] bitperiod_i,
output reg tx_done_tick_o,
output reg tx_o
);
reg [7:0] databuf;
reg [3:0] state;
reg [31:0] clk_counter;
reg [2:0] bit_counter;
localparam ST_IDLE = 8'h0;
localparam ST_START = 8'h1;
localparam ST_TX_DATA = 8'h2;
localparam ST_STOP = 8'h3;
always @(posedge clk_i)
begin
if (rst_i)
begin
state <= ST_IDLE;
databuf <= 8'h0;
clk_counter <= 32'h0;
tx_o <= 1'b1;
tx_done_tick_o <= 1'b0;
end
else
begin
if (RTX_EXTERNAL_OVERRIDE == "NO") tx_done_tick_o <= 1'b0;
else tx_done_tick_o <= 1'b1;
case (state)
ST_IDLE:
begin
tx_o <= 1'b1;
if ((tx_start_i == 1'b1) && (locked_i == 1'b1))
begin
tx_o <= 1'b0;
state <= ST_START;
databuf <= din_bi;
clk_counter <= 32'h0;
end
end
ST_START:
begin
clk_counter <= clk_counter + 32'h1;
if (clk_counter == {3'h0, bitperiod_i})
begin
state <= ST_TX_DATA;
clk_counter <= 32'h0;
bit_counter <= 3'h0;
tx_o <= databuf[0];
databuf <= {1'b0, databuf[7:1]};
end
end
ST_TX_DATA:
begin
clk_counter <= clk_counter + 32'h1;
if (clk_counter == {3'h0, bitperiod_i})
begin
clk_counter <= 32'h0;
bit_counter <= bit_counter + 3'h1;
if (bit_counter == 3'h7)
begin
tx_o <= 1'b1;
state <= ST_STOP;
end
else
begin
tx_o <= databuf[0];
databuf <= {1'b0, databuf[7:1]};
end
end
end
ST_STOP:
begin
clk_counter <= clk_counter + 32'h1;
if (clk_counter == {2'h0, bitperiod_i, 1'b0}) // 2 * bit
begin
tx_o <= 1'b1;
tx_done_tick_o <= 1'b1;
state <= ST_IDLE;
end
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:06:53 11/19/2013
// Design Name:
// Module Name: top_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_module(
input clock,
input reset,
input c_pad,
input d_pad,
input e_pad,
input f_pad,
input g_pad,
output lrck,
output mclk,
output sdin,
output[15:0] left_data_o,
output [15:0] right_data_o
);
/** Para generar el clock a 50MHz */
wire clock_50Mhz;
/** Entradas sincronizados */
wire reset_sync, c_pad_sync, d_pad_sync, e_pad_sync, f_pad_sync, g_pad_sync, pad_touched;
/** Variables que contienen los datos de los nco */
wire[15:0] c_data, d_data, e_data, f_data, g_data;
/** Variables que contienen los datos que se mandan al i2s */
wire[15:0] left_data, right_data;
/** Variables para la maquina de estados */
wire play;
/** Genera un clock a 50MHz a partir del de 100MHz del de la spartan */
half_clock_divider half_divider(
.clock(clock),
.reset(reset_sync),
.clock_out(clock_50Mhz)
);
/** Debounce que sincroniza las senales */
debounce debounce_m(
.clock(clock),
.reset(reset),
.c_pad(c_pad),
.d_pad(d_pad),
.e_pad(e_pad),
.f_pad(f_pad),
.g_pad(g_pad),
.reset_sync(reset_sync),
.c_pad_sync(c_pad_sync),
.d_pad_sync(d_pad_sync),
.e_pad_sync(e_pad_sync),
.f_pad_sync(f_pad_sync),
.g_pad_sync(g_pad_sync),
.pad_touched(pad_touched)
);
/** Maquina de estados que le indica al banco de sonidos que puede reproducir */
fsm maquina(
.clock(clock),
.reset(reset_sync),
.play(play),
.pad_touched(pad_touched)
);
/** Modulo que produce la salida para el pmodi2s
Siempre va a estar generando la salida, solo que
si no hay boton presionado va a tirar cero */
i2s_out i2s_generator (
.clock(clock_50Mhz),
.reset(reset_sync),
.right_data(right_data),
.left_data(left_data),
.mclk(mclk),
.lrck(lrck),
.sdin(sdin)
);
/** Banco de sonidos, lo que suena se produce a partir de los botones
presionados */
sounds_bank sonidos(
.lrck(lrck),
.c_pad_sync(c_pad_sync),
.d_pad_sync(d_pad_sync),
.e_pad_sync(e_pad_sync),
.f_pad_sync(f_pad_sync),
.g_pad_sync(g_pad_sync),
.play(play),
.c_data_out(c_data),
.d_data_out(d_data),
.e_data_out(e_data),
.f_data_out(f_data),
.g_data_out(g_data)
);
/** Adder que suma la salida de cada sonido(tono) */
adder sumador(
.c_data(c_data),
.d_data(d_data),
.e_data(e_data),
.f_data(f_data),
.g_data(g_data),
.left_data(left_data),
.right_data(right_data)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// too bad- we have to do this!
`timescale 1ns/100ps
module util_ccat (
data_0,
data_1,
data_2,
data_3,
data_4,
data_5,
data_6,
data_7,
ccat_data);
// parameters
parameter CH_DW = 1;
parameter CH_CNT = 8;
localparam CH_MCNT = 8;
// interface
input [(CH_DW-1):0] data_0;
input [(CH_DW-1):0] data_1;
input [(CH_DW-1):0] data_2;
input [(CH_DW-1):0] data_3;
input [(CH_DW-1):0] data_4;
input [(CH_DW-1):0] data_5;
input [(CH_DW-1):0] data_6;
input [(CH_DW-1):0] data_7;
output [((CH_CNT*CH_DW)-1):0] ccat_data;
// internal signals
wire [((CH_MCNT*CH_DW)-1):0] data_s;
// concatenate
assign data_s[((CH_DW*1)-1):(CH_DW*0)] = data_0;
assign data_s[((CH_DW*2)-1):(CH_DW*1)] = data_1;
assign data_s[((CH_DW*3)-1):(CH_DW*2)] = data_2;
assign data_s[((CH_DW*4)-1):(CH_DW*3)] = data_3;
assign data_s[((CH_DW*5)-1):(CH_DW*4)] = data_4;
assign data_s[((CH_DW*6)-1):(CH_DW*5)] = data_5;
assign data_s[((CH_DW*7)-1):(CH_DW*6)] = data_6;
assign data_s[((CH_DW*8)-1):(CH_DW*7)] = data_7;
assign ccat_data = data_s[((CH_CNT*CH_DW)-1):0];
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_4_V
`define SKY130_FD_SC_MS__NAND4BB_4_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4bb_4 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4bb_4 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_4_V
|
// Generated by DDR3 High Performance Controller 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2012 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_int (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_n,
dll_reference_clk,
dqs_delay_ctrl_export,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
mem_reset_n,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
reset_request_n,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqsn);
input [23:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [255:0] local_wdata;
input [31:0] local_be;
input [4:0] local_size;
input global_reset_n;
input pll_ref_clk;
input soft_reset_n;
output local_ready;
output [255:0] local_rdata;
output local_rdata_valid;
output local_refresh_ack;
output local_init_done;
output reset_phy_clk_n;
output dll_reference_clk;
output [5:0] dqs_delay_ctrl_export;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [7:0] mem_dm;
output mem_reset_n;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
output reset_request_n;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [63:0] mem_dq;
inout [7:0] mem_dqs;
inout [7:0] mem_dqsn;
endmodule
|
Set Automatic Coercions Import.
From mathcomp.ssreflect
Require Import ssreflect ssrbool ssrnat eqtype seq ssrfun.
Require Import pred prelude pcm unionmap heap heaptac stmod stsep stlog.
Set Implicit Arguments.
Unset Strict Implicit.
Import Prenex Implicits.
(**************************************************************************)
(* This file implements two different automations related to Hoare logic. *)
(* *)
(* First automation concerns selection of Hoare-style rule for symbolic *)
(* evaluation. The first command of the program determines the applicable *)
(* rule uniquely. The implemented automation picks out this rule, and *)
(* applies it, while using AC-theory of heaps to rearrange the goal, if *)
(* necessary for the rule to apply. *)
(* *)
(* Second automation concerns pulling ghost variables out of a Hoare *)
(* type. The non-automated lemmas do this pulling one variable at a *)
(* time. The automation pulls all the variable at once. *)
(**************************************************************************)
(****************************************************************)
(* First, the reflection mechanism for search-and-replace *)
(* pattern-matching on heap expressions; the AC theory of heaps *)
(****************************************************************)
Structure tagged_heap := Tag {untag :> heap}.
Definition right_tag := Tag.
Definition left_tag := right_tag.
Canonical Structure found_tag i := left_tag i.
Definition form_axiom k r (h : tagged_heap) := untag h = k \+ r.
Structure form (k r : heap) :=
Form {heap_of :> tagged_heap;
_ : form_axiom k r heap_of}.
Implicit Arguments Form [].
Lemma formE r k (f : form k r) : untag f = k \+ r.
Proof. by case: f=>[[j]] /=; rewrite /form_axiom /= => ->. Qed.
Lemma found_pf k : form_axiom k Unit (found_tag k).
Proof. by rewrite /form_axiom unitR. Qed.
Canonical Structure heap_found k := Form k Unit (found_tag k) (found_pf k).
Lemma left_pf h r (f : forall k, form k r) k :
form_axiom k (r \+ h) (left_tag (untag (f k) \+ h)).
Proof. by rewrite formE /form_axiom /= joinA. Qed.
Canonical Structure search_left h r (f : forall k, form k r) k :=
Form k (r \+ h) (left_tag (untag (f k) \+ h)) (left_pf h f k).
Lemma right_pf h r (f : forall k, form k r) k :
form_axiom k (h \+ r) (right_tag (h \+ f k)).
Proof. by rewrite formE /form_axiom /= joinCA. Qed.
Canonical Structure search_right h r (f : forall k, form k r) k :=
Form k (h \+ r) (right_tag (h \+ f k)) (right_pf h f k).
(**********************************************************)
(* Reflective lemmas that apply module AC-theory of heaps *)
(**********************************************************)
Notation cont A := (ans A -> heap -> Prop).
Section EvalDoR.
Variables (A B : Type) (p : heap -> Prop) (q : ans A -> heap -> Prop).
Lemma val_doR e i j (f : forall k, form k j) (r : cont A) :
(valid i -> p i) ->
(forall x m, q (Val x) m ->
valid (untag (f m)) -> r (Val x) (f m)) ->
(forall x m, q (Exn x) m ->
valid (untag (f m)) -> r (Exn x) (f m)) ->
verify (f i) (with_spec (binarify p q) e) r.
Proof.
move=>H1 H2 H3; rewrite formE; apply: (val_do H1).
- by move=>x m; move: (H2 x m); rewrite formE.
by move=>x m; move: (H3 x m); rewrite formE.
Qed.
End EvalDoR.
(* We maintain three different kinds of lemmas *)
(* in order to streamline the stepping *)
(* The only important ones are the val lemmas, the bnd and try *)
(* are there just to remove some spurious hypotheses about validity, and make the *)
(* verification flow easier *)
(* Each call to some bnd_* or try_* lemma is really a call to bnd_seq or try_seq *)
(* followed by a val_* lemma. Except that doing things in such a sequence *)
(* actually gives us some additional, spurious, valididity hypotheses, which we *)
(* always discard anyway. However the discarding interrupts automation, so we want to avoid it *)
(* However, we only need only val_doR lemma *)
(* This one is always applied by hand, not automatically, so *)
(* if we need to prefix it with a call to bnd_seq or try_seq, we can *)
(* do that by hand *)
(* If we were to do this by hand, whenever *)
(* there should be a nicer way to do this *)
(* e.g., suppress all the spruious validity as a default *)
(* and let the user generate them by hand at the leaves, when necessary *)
Section EvalRetR.
Variables (A B : Type).
Definition val_retR := val_ret.
Lemma try_retR e1 e2 (v : A) i (r : cont B) :
verify i (e1 v) r -> verify i (ttry (ret v) e1 e2) r.
Proof. by move=>H; apply: try_seq; apply: val_ret. Qed.
Lemma bnd_retR e (v : A) i (r : cont B) :
verify i (e v) r -> verify i (bind (ret v) e) r.
Proof. by move=>H; apply: bnd_seq; apply: val_ret. Qed.
End EvalRetR.
Section EvalReadR.
Variables (A B : Type).
Lemma val_readR v x i (f : form (x :-> v) i) (r : cont A) :
(valid (untag f) -> r (Val v) f) ->
verify f (read A x) r.
Proof. by rewrite formE; apply: val_read. Qed.
Lemma try_readR e1 e2 v x i (f : form (x :-> v) i) (r : cont B) :
verify f (e1 v) r ->
verify f (ttry (read A x) e1 e2) r.
Proof. by move=>H; apply: try_seq; apply: val_readR. Qed.
Lemma bnd_readR e v x i (f : form (x :-> v) i) (r : cont B) :
verify f (e v) r ->
verify f (bind (read A x) e) r.
Proof. by move=>H; apply: bnd_seq; apply: val_readR. Qed.
End EvalReadR.
Section EvalWriteR.
Variables (A B C : Type).
Lemma val_writeR (v : A) (w : B) x i (f : forall k, form k i) (r : cont unit) :
(valid (untag (f (x :-> v))) -> r (Val tt) (f (x :-> v))) ->
verify (f (x :-> w)) (write x v) r.
Proof. by rewrite !formE; apply: val_write. Qed.
Lemma try_writeR e1 e2 (v : A) (w : B) x i
(f : forall k, form k i) (r : cont C) :
verify (f (x :-> v)) (e1 tt) r ->
verify (f (x :-> w)) (ttry (write x v) e1 e2) r.
Proof. by move=>H; apply: try_seq; apply: val_writeR. Qed.
Lemma bnd_writeR e (v : A) (w : B) x i (f : forall k, form k i) (r : cont C) :
verify (f (x :-> v)) (e tt) r ->
verify (f (x :-> w)) (bind (write x v) e) r.
Proof. by move=>H; apply: bnd_seq; apply: val_writeR. Qed.
End EvalWriteR.
Section EvalAllocR.
Variables (A B : Type).
Definition val_allocR := val_alloc.
Lemma try_allocR e1 e2 (v : A) i (r : cont B) :
(forall x, verify (x :-> v \+ i) (e1 x) r) ->
verify i (ttry (alloc v) e1 e2) r.
Proof. by move=>H; apply: try_seq; apply: val_alloc. Qed.
Lemma bnd_allocR e (v : A) i (r : cont B) :
(forall x, verify (x :-> v \+ i) (e x) r) ->
verify i (bind (alloc v) e) r.
Proof. by move=>H; apply: bnd_seq; apply: val_alloc. Qed.
End EvalAllocR.
Section EvalAllocbR.
Variables (A B : Type).
Definition val_allocbR := val_allocb.
Lemma try_allocbR e1 e2 (v : A) n i (r : cont B) :
(forall x, verify (updi x (nseq n v) \+ i) (e1 x) r) ->
verify i (ttry (allocb v n) e1 e2) r.
Proof. by move=>H; apply: try_seq; apply: val_allocb. Qed.
Lemma bnd_allocbR e (v : A) n i (r : cont B) :
(forall x, verify (updi x (nseq n v) \+ i) (e x) r) ->
verify i (bind (allocb v n) e) r.
Proof. by move=>H; apply: bnd_seq; apply: val_allocb. Qed.
End EvalAllocbR.
Section EvalDeallocR.
Variables (A B : Type).
Lemma val_deallocR (v : A) x i (f : forall k, form k i) (r : cont unit) :
(valid (untag (f Unit)) -> r (Val tt) (f Unit)) ->
verify (f (x :-> v)) (dealloc x) r.
Proof. by rewrite !formE unitL; apply: val_dealloc. Qed.
Lemma try_deallocR e1 e2 (v : A) x i (f : forall k, form k i) (r : cont B) :
verify (f Unit) (e1 tt) r ->
verify (f (x :-> v)) (ttry (dealloc x) e1 e2) r.
Proof. by move=>H; apply: try_seq; apply: val_deallocR. Qed.
Lemma bnd_deallocR e (v : A) x i (f : forall k, form k i) (r : cont B) :
verify (f Unit) (e tt) r ->
verify (f (x :-> v)) (bind (dealloc x) e) r.
Proof. by move=>H; apply: bnd_seq; apply: val_deallocR. Qed.
End EvalDeallocR.
Section EvalThrowR.
Variables (A B : Type).
Definition val_throwR := val_throw.
Lemma try_throwR e e1 e2 i (r : cont B) :
verify i (e2 e) r ->
verify i (ttry (throw A e) e1 e2) r.
Proof. by move=>H; apply: try_seq; apply: val_throw. Qed.
Lemma bnd_throwR e e1 i (r : cont B) :
(valid i -> r (Exn e) i) ->
verify i (bind (throw A e) e1) r.
Proof. by move=>H; apply: bnd_seq; apply: val_throw. Qed.
End EvalThrowR.
(****************************************************)
(* Automating the selection of which lemma to apply *)
(* (reflective implementation of the hstep tactic) *)
(****************************************************)
(* Need to case-split on bnd_, try_, or a val_ lemma. *)
(* Hence, three classes of canonical structures. *)
Structure val_form A i r (p : Prop):=
ValForm {val_pivot :> ST A;
_ : p -> verify i val_pivot r}.
Structure bnd_form A B i (e : A -> ST B) r (p : Prop) :=
BndForm {bnd_pivot :> ST A;
_ : p -> verify i (bind bnd_pivot e) r}.
Structure try_form A B i (e1 : A -> ST B)
(e2 : exn -> ST B) r (p : Prop) :=
TryForm {try_pivot :> ST A;
_ : p -> verify i (ttry try_pivot e1 e2) r}.
(* The main lemma which triggers the selection. *)
Lemma hstep A i (r : cont A) p (e : val_form i r p) :
p -> verify i e r.
Proof. by case:e=>[?]; apply. Qed.
(* First check if matching on bnd_ or try_. If so, switch to searching *)
(* for bnd_ or try_form, respectively. Otherwise, fall through, and *)
(* continue searching for a val_form. *)
Lemma bnd_case_pf A B i (s : A -> ST B) r p (e : bnd_form i s r p) :
p -> verify i (bind e s) r.
Proof. by case:e=>[?]; apply. Qed.
Canonical Structure
bnd_case_form A B i (s : A -> ST B) r p (e : bnd_form i s r p) :=
ValForm (bnd_case_pf e).
Lemma try_case_pf A B i (s1 : A -> ST B) (s2 : exn -> ST B) r p
(e : try_form i s1 s2 r p) :
p -> verify i (ttry e s1 s2) r.
Proof. by case:e=>[?]; apply. Qed.
(* After that, find the form in the following list. Notice that the list *)
(* can be extended arbitrarily in the future. There is no centralized *)
(* tactic to maintain. *)
Canonical Structure val_ret_form A v i r :=
ValForm (@val_retR A v i r).
Canonical Structure bnd_ret_form A B s v i r :=
BndForm (@bnd_retR A B s v i r).
Canonical Structure try_ret_form A B s1 s2 v i r :=
TryForm (@try_retR A B s1 s2 v i r).
Canonical Structure val_read_form A v x r j f :=
ValForm (@val_readR A v x j f r).
Canonical Structure bnd_read_form A B s v x r j f :=
BndForm (@bnd_readR A B s v x j f r).
Canonical Structure try_read_form A B s1 s2 v x r j f :=
TryForm (@try_readR A B s1 s2 v x j f r).
Canonical Structure val_write_form A B v w x r j f :=
ValForm (@val_writeR A B v w x j f r).
Canonical Structure bnd_write_form A B C s v w x r j f :=
BndForm (@bnd_writeR A B C s v w x j f r).
Canonical Structure try_write_form A B C s1 s2 v w x r j f :=
TryForm (@try_writeR A B C s1 s2 v w x j f r).
Canonical Structure val_alloc_form A v i r :=
ValForm (@val_allocR A v i r).
Canonical Structure bnd_alloc_form A B s v i r :=
BndForm (@bnd_allocR A B s v i r).
Canonical Structure try_alloc_form A B s1 s2 v i r :=
TryForm (@try_allocR A B s1 s2 v i r).
Canonical Structure val_allocb_form A v n i r :=
ValForm (@val_allocbR A v n i r).
Canonical Structure bnd_allocb_form A B s v n i r :=
BndForm (@bnd_allocbR A B s v n i r).
Canonical Structure try_allocb_form A B s1 s2 v n i r :=
TryForm (@try_allocbR A B s1 s2 v n i r).
Canonical Structure val_dealloc_form A v x r j f :=
ValForm (@val_deallocR A v x j f r).
Canonical Structure bnd_dealloc_form A B s v x r j f :=
BndForm (@bnd_deallocR A B s v x j f r).
Canonical Structure try_dealloc_form A B s1 s2 v x r j f :=
TryForm (@try_deallocR A B s1 s2 v x j f r).
(* Second automation *)
(**************************************************************************)
(* A simple canonical structure program to automate applying ghE and gh. *)
(* *)
(* The gh_form pivots on a spec, and computes as output the following. *)
(* - rT is a product of types of all encounted ghost vars. *)
(* - p and q are pre and post parametrized by rT that should be output by *)
(* the main lemma. *)
(* *)
(* In the future, rT should be a list of types, rather than a product, *)
(* but that leads to arity polimorphism, and dependent programming, which *)
(* I want to avoid for now. *)
(**************************************************************************)
Section Automation.
Structure tagged_spec A := gh_step {gh_untag :> spec A}.
Canonical Structure gh_base A (s : spec A) := gh_step s.
Definition gh_axiom A rT p q (pivot : tagged_spec A) :=
gh_untag pivot = logvar (fun x : rT => binarify (p x) (q x)).
Structure gh_form A rT (p : rT -> pre) (q : rT -> cont A) := GhForm {
gh_pivot :> tagged_spec A;
_ : gh_axiom p q gh_pivot}.
(* the main lemma that automates the applications of ghE and gh *)
Lemma ghR A e rT p q (f : @gh_form A rT p q) :
(forall i x, p x i -> valid i -> verify i e (q x)) ->
conseq e f.
Proof. by case: f=>p' ->; apply: gh. Qed.
(* base case; check if we reached binarify *)
Lemma gh_base_pf A rT (p : rT -> pre) (q : rT -> cont A) :
gh_axiom p q (gh_base (logvar (fun x => binarify (p x) (q x)))).
Proof. by []. Qed.
Canonical gh_base_struct A rT p q := GhForm (@gh_base_pf A rT p q).
(* inductive case; merge adjacent logvars and continue *)
Lemma gh_step_pf A B rT p q (f : forall x : A, @gh_form B rT (p x) (q x)) :
gh_axiom (fun xy => p xy.1 xy.2) (fun xy => q xy.1 xy.2)
(gh_step (logvar (fun x => f x))).
Proof.
congr (_, _).
- apply: fext=>i; apply: pext; split.
- by case=>x; case: (f x)=>[_ ->] /= [y H]; exists (x, y).
by case; case=>x y; exists x; case: (f x)=>[_ ->]; exists y.
apply: fext=>y; apply: fext=>i; apply: fext=>m; apply: pext; split.
- by move=>H [x z] /= H1; case: (f x) (H x)=>[_ ->]; apply.
by move=>H x; case: (f x)=>[_ ->] z; apply: (H (x, z)).
Qed.
Canonical gh_step_struct A B rT p q f := GhForm (@gh_step_pf A B rT p q f).
End Automation.
(* we keep some tactics to kill final goals, which *)
(* are usually full of existentials *)
Ltac vauto := (do ?econstructor=>//).
Ltac step := (apply: hstep=>/=).
Ltac hhauto := (vauto; try by [heap_congr])=>//.
Ltac heval := do ![step | by hhauto].
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Tue Mar 21 08:35:02 2017
//Host : WK115 running 64-bit major release (build 9200)
//Command : generate_target PmodNAV.bd
//Design : PmodNAV
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "PmodNAV,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=PmodNAV,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=18,numReposBlks=18,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,synth_mode=Global}" *) (* HW_HANDOFF = "PmodNAV.hwdef" *)
module PmodNAV
(AXI_LITE_GPIO_araddr,
AXI_LITE_GPIO_arready,
AXI_LITE_GPIO_arvalid,
AXI_LITE_GPIO_awaddr,
AXI_LITE_GPIO_awready,
AXI_LITE_GPIO_awvalid,
AXI_LITE_GPIO_bready,
AXI_LITE_GPIO_bresp,
AXI_LITE_GPIO_bvalid,
AXI_LITE_GPIO_rdata,
AXI_LITE_GPIO_rready,
AXI_LITE_GPIO_rresp,
AXI_LITE_GPIO_rvalid,
AXI_LITE_GPIO_wdata,
AXI_LITE_GPIO_wready,
AXI_LITE_GPIO_wstrb,
AXI_LITE_GPIO_wvalid,
AXI_LITE_SPI_araddr,
AXI_LITE_SPI_arready,
AXI_LITE_SPI_arvalid,
AXI_LITE_SPI_awaddr,
AXI_LITE_SPI_awready,
AXI_LITE_SPI_awvalid,
AXI_LITE_SPI_bready,
AXI_LITE_SPI_bresp,
AXI_LITE_SPI_bvalid,
AXI_LITE_SPI_rdata,
AXI_LITE_SPI_rready,
AXI_LITE_SPI_rresp,
AXI_LITE_SPI_rvalid,
AXI_LITE_SPI_wdata,
AXI_LITE_SPI_wready,
AXI_LITE_SPI_wstrb,
AXI_LITE_SPI_wvalid,
GPIO_Interrupt,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
SPI_Interrupt,
ext_spi_clk,
s_axi_aclk,
s_axi_aresetn);
input [8:0]AXI_LITE_GPIO_araddr;
output AXI_LITE_GPIO_arready;
input AXI_LITE_GPIO_arvalid;
input [8:0]AXI_LITE_GPIO_awaddr;
output AXI_LITE_GPIO_awready;
input AXI_LITE_GPIO_awvalid;
input AXI_LITE_GPIO_bready;
output [1:0]AXI_LITE_GPIO_bresp;
output AXI_LITE_GPIO_bvalid;
output [31:0]AXI_LITE_GPIO_rdata;
input AXI_LITE_GPIO_rready;
output [1:0]AXI_LITE_GPIO_rresp;
output AXI_LITE_GPIO_rvalid;
input [31:0]AXI_LITE_GPIO_wdata;
output AXI_LITE_GPIO_wready;
input [3:0]AXI_LITE_GPIO_wstrb;
input AXI_LITE_GPIO_wvalid;
input [6:0]AXI_LITE_SPI_araddr;
output AXI_LITE_SPI_arready;
input AXI_LITE_SPI_arvalid;
input [6:0]AXI_LITE_SPI_awaddr;
output AXI_LITE_SPI_awready;
input AXI_LITE_SPI_awvalid;
input AXI_LITE_SPI_bready;
output [1:0]AXI_LITE_SPI_bresp;
output AXI_LITE_SPI_bvalid;
output [31:0]AXI_LITE_SPI_rdata;
input AXI_LITE_SPI_rready;
output [1:0]AXI_LITE_SPI_rresp;
output AXI_LITE_SPI_rvalid;
input [31:0]AXI_LITE_SPI_wdata;
output AXI_LITE_SPI_wready;
input [3:0]AXI_LITE_SPI_wstrb;
input AXI_LITE_SPI_wvalid;
output GPIO_Interrupt;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
output SPI_Interrupt;
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
wire [6:0]AXI_LITE_1_ARADDR;
wire AXI_LITE_1_ARREADY;
wire AXI_LITE_1_ARVALID;
wire [6:0]AXI_LITE_1_AWADDR;
wire AXI_LITE_1_AWREADY;
wire AXI_LITE_1_AWVALID;
wire AXI_LITE_1_BREADY;
wire [1:0]AXI_LITE_1_BRESP;
wire AXI_LITE_1_BVALID;
wire [31:0]AXI_LITE_1_RDATA;
wire AXI_LITE_1_RREADY;
wire [1:0]AXI_LITE_1_RRESP;
wire AXI_LITE_1_RVALID;
wire [31:0]AXI_LITE_1_WDATA;
wire AXI_LITE_1_WREADY;
wire [3:0]AXI_LITE_1_WSTRB;
wire AXI_LITE_1_WVALID;
wire [8:0]AXI_LITE_GPIO_1_ARADDR;
wire AXI_LITE_GPIO_1_ARREADY;
wire AXI_LITE_GPIO_1_ARVALID;
wire [8:0]AXI_LITE_GPIO_1_AWADDR;
wire AXI_LITE_GPIO_1_AWREADY;
wire AXI_LITE_GPIO_1_AWVALID;
wire AXI_LITE_GPIO_1_BREADY;
wire [1:0]AXI_LITE_GPIO_1_BRESP;
wire AXI_LITE_GPIO_1_BVALID;
wire [31:0]AXI_LITE_GPIO_1_RDATA;
wire AXI_LITE_GPIO_1_RREADY;
wire [1:0]AXI_LITE_GPIO_1_RRESP;
wire AXI_LITE_GPIO_1_RVALID;
wire [31:0]AXI_LITE_GPIO_1_WDATA;
wire AXI_LITE_GPIO_1_WREADY;
wire [3:0]AXI_LITE_GPIO_1_WSTRB;
wire AXI_LITE_GPIO_1_WVALID;
wire [1:0]axi_gpio_0_gpio_io_o;
wire [1:0]axi_gpio_0_gpio_io_t;
wire axi_gpio_0_ip2intc_irpt;
wire axi_quad_spi_0_io0_o;
wire axi_quad_spi_0_io0_t;
wire axi_quad_spi_0_io1_o;
wire axi_quad_spi_0_io1_t;
wire axi_quad_spi_0_ip2intc_irpt;
wire axi_quad_spi_0_sck_o;
wire axi_quad_spi_0_sck_t;
wire [2:0]axi_quad_spi_0_ss_o;
wire axi_quad_spi_0_ss_t;
wire ext_spi_clk_1;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire [3:0]pmod_bridge_0_in_bottom_bus_I;
wire [3:0]pmod_bridge_0_in_top_bus_I;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
wire [3:0]xlconcat_bottom_o_dout;
wire [3:0]xlconcat_bottom_t_dout;
wire [2:0]xlconcat_ss_i_dout;
wire [3:0]xlconcat_top_o_dout;
wire [3:0]xlconcat_top_t_dout;
wire [0:0]xlslice_ag_ss_i_Dout;
wire [0:0]xlslice_ag_ss_o_Dout;
wire [0:0]xlslice_alt_ss_i_Dout;
wire [0:0]xlslice_alt_ss_o_Dout;
wire [1:0]xlslice_gpio_i_Dout;
wire [0:0]xlslice_mag_ss_i_Dout;
wire [0:0]xlslice_mag_ss_o_Dout;
wire [0:0]xlslice_sck_i_Dout;
wire [0:0]xlslice_sdo_i_Dout;
wire [0:0]xlslice_ss_sdi_i_Dout;
assign AXI_LITE_1_ARADDR = AXI_LITE_SPI_araddr[6:0];
assign AXI_LITE_1_ARVALID = AXI_LITE_SPI_arvalid;
assign AXI_LITE_1_AWADDR = AXI_LITE_SPI_awaddr[6:0];
assign AXI_LITE_1_AWVALID = AXI_LITE_SPI_awvalid;
assign AXI_LITE_1_BREADY = AXI_LITE_SPI_bready;
assign AXI_LITE_1_RREADY = AXI_LITE_SPI_rready;
assign AXI_LITE_1_WDATA = AXI_LITE_SPI_wdata[31:0];
assign AXI_LITE_1_WSTRB = AXI_LITE_SPI_wstrb[3:0];
assign AXI_LITE_1_WVALID = AXI_LITE_SPI_wvalid;
assign AXI_LITE_GPIO_1_ARADDR = AXI_LITE_GPIO_araddr[8:0];
assign AXI_LITE_GPIO_1_ARVALID = AXI_LITE_GPIO_arvalid;
assign AXI_LITE_GPIO_1_AWADDR = AXI_LITE_GPIO_awaddr[8:0];
assign AXI_LITE_GPIO_1_AWVALID = AXI_LITE_GPIO_awvalid;
assign AXI_LITE_GPIO_1_BREADY = AXI_LITE_GPIO_bready;
assign AXI_LITE_GPIO_1_RREADY = AXI_LITE_GPIO_rready;
assign AXI_LITE_GPIO_1_WDATA = AXI_LITE_GPIO_wdata[31:0];
assign AXI_LITE_GPIO_1_WSTRB = AXI_LITE_GPIO_wstrb[3:0];
assign AXI_LITE_GPIO_1_WVALID = AXI_LITE_GPIO_wvalid;
assign AXI_LITE_GPIO_arready = AXI_LITE_GPIO_1_ARREADY;
assign AXI_LITE_GPIO_awready = AXI_LITE_GPIO_1_AWREADY;
assign AXI_LITE_GPIO_bresp[1:0] = AXI_LITE_GPIO_1_BRESP;
assign AXI_LITE_GPIO_bvalid = AXI_LITE_GPIO_1_BVALID;
assign AXI_LITE_GPIO_rdata[31:0] = AXI_LITE_GPIO_1_RDATA;
assign AXI_LITE_GPIO_rresp[1:0] = AXI_LITE_GPIO_1_RRESP;
assign AXI_LITE_GPIO_rvalid = AXI_LITE_GPIO_1_RVALID;
assign AXI_LITE_GPIO_wready = AXI_LITE_GPIO_1_WREADY;
assign AXI_LITE_SPI_arready = AXI_LITE_1_ARREADY;
assign AXI_LITE_SPI_awready = AXI_LITE_1_AWREADY;
assign AXI_LITE_SPI_bresp[1:0] = AXI_LITE_1_BRESP;
assign AXI_LITE_SPI_bvalid = AXI_LITE_1_BVALID;
assign AXI_LITE_SPI_rdata[31:0] = AXI_LITE_1_RDATA;
assign AXI_LITE_SPI_rresp[1:0] = AXI_LITE_1_RRESP;
assign AXI_LITE_SPI_rvalid = AXI_LITE_1_RVALID;
assign AXI_LITE_SPI_wready = AXI_LITE_1_WREADY;
assign GPIO_Interrupt = axi_gpio_0_ip2intc_irpt;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign SPI_Interrupt = axi_quad_spi_0_ip2intc_irpt;
assign ext_spi_clk_1 = ext_spi_clk;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodNAV_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i(xlslice_gpio_i_Dout),
.gpio_io_o(axi_gpio_0_gpio_io_o),
.gpio_io_t(axi_gpio_0_gpio_io_t),
.ip2intc_irpt(axi_gpio_0_ip2intc_irpt),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(AXI_LITE_GPIO_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(AXI_LITE_GPIO_1_ARREADY),
.s_axi_arvalid(AXI_LITE_GPIO_1_ARVALID),
.s_axi_awaddr(AXI_LITE_GPIO_1_AWADDR),
.s_axi_awready(AXI_LITE_GPIO_1_AWREADY),
.s_axi_awvalid(AXI_LITE_GPIO_1_AWVALID),
.s_axi_bready(AXI_LITE_GPIO_1_BREADY),
.s_axi_bresp(AXI_LITE_GPIO_1_BRESP),
.s_axi_bvalid(AXI_LITE_GPIO_1_BVALID),
.s_axi_rdata(AXI_LITE_GPIO_1_RDATA),
.s_axi_rready(AXI_LITE_GPIO_1_RREADY),
.s_axi_rresp(AXI_LITE_GPIO_1_RRESP),
.s_axi_rvalid(AXI_LITE_GPIO_1_RVALID),
.s_axi_wdata(AXI_LITE_GPIO_1_WDATA),
.s_axi_wready(AXI_LITE_GPIO_1_WREADY),
.s_axi_wstrb(AXI_LITE_GPIO_1_WSTRB),
.s_axi_wvalid(AXI_LITE_GPIO_1_WVALID));
PmodNAV_axi_quad_spi_0_0 axi_quad_spi_0
(.ext_spi_clk(ext_spi_clk_1),
.io0_i(xlslice_ss_sdi_i_Dout),
.io0_o(axi_quad_spi_0_io0_o),
.io0_t(axi_quad_spi_0_io0_t),
.io1_i(xlslice_sdo_i_Dout),
.io1_o(axi_quad_spi_0_io1_o),
.io1_t(axi_quad_spi_0_io1_t),
.ip2intc_irpt(axi_quad_spi_0_ip2intc_irpt),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(AXI_LITE_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(AXI_LITE_1_ARREADY),
.s_axi_arvalid(AXI_LITE_1_ARVALID),
.s_axi_awaddr(AXI_LITE_1_AWADDR),
.s_axi_awready(AXI_LITE_1_AWREADY),
.s_axi_awvalid(AXI_LITE_1_AWVALID),
.s_axi_bready(AXI_LITE_1_BREADY),
.s_axi_bresp(AXI_LITE_1_BRESP),
.s_axi_bvalid(AXI_LITE_1_BVALID),
.s_axi_rdata(AXI_LITE_1_RDATA),
.s_axi_rready(AXI_LITE_1_RREADY),
.s_axi_rresp(AXI_LITE_1_RRESP),
.s_axi_rvalid(AXI_LITE_1_RVALID),
.s_axi_wdata(AXI_LITE_1_WDATA),
.s_axi_wready(AXI_LITE_1_WREADY),
.s_axi_wstrb(AXI_LITE_1_WSTRB),
.s_axi_wvalid(AXI_LITE_1_WVALID),
.sck_i(xlslice_sck_i_Dout),
.sck_o(axi_quad_spi_0_sck_o),
.sck_t(axi_quad_spi_0_sck_t),
.ss_i(xlconcat_ss_i_dout),
.ss_o(axi_quad_spi_0_ss_o),
.ss_t(axi_quad_spi_0_ss_t));
PmodNAV_pmod_bridge_0_0 pmod_bridge_0
(.in_bottom_bus_I(pmod_bridge_0_in_bottom_bus_I),
.in_bottom_bus_O(xlconcat_bottom_o_dout),
.in_bottom_bus_T(xlconcat_bottom_t_dout),
.in_top_bus_I(pmod_bridge_0_in_top_bus_I),
.in_top_bus_O(xlconcat_top_o_dout),
.in_top_bus_T(xlconcat_top_t_dout),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
PmodNAV_xlconcat_0_3 xlconcat_bottom_o
(.In0(axi_gpio_0_gpio_io_o),
.In1(xlslice_mag_ss_o_Dout),
.In2(xlslice_alt_ss_o_Dout),
.dout(xlconcat_bottom_o_dout));
PmodNAV_xlconcat_0_2 xlconcat_bottom_t
(.In0(axi_gpio_0_gpio_io_t),
.In1(axi_quad_spi_0_ss_t),
.In2(axi_quad_spi_0_ss_t),
.dout(xlconcat_bottom_t_dout));
PmodNAV_xlconcat_0_4 xlconcat_ss_i
(.In0(xlslice_ag_ss_i_Dout),
.In1(xlslice_mag_ss_i_Dout),
.In2(xlslice_alt_ss_i_Dout),
.dout(xlconcat_ss_i_dout));
PmodNAV_xlconcat_0_1 xlconcat_top_o
(.In0(xlslice_ag_ss_o_Dout),
.In1(axi_quad_spi_0_io0_o),
.In2(axi_quad_spi_0_io1_o),
.In3(axi_quad_spi_0_sck_o),
.dout(xlconcat_top_o_dout));
PmodNAV_xlconcat_0_0 xlconcat_top_t
(.In0(axi_quad_spi_0_ss_t),
.In1(axi_quad_spi_0_io0_t),
.In2(axi_quad_spi_0_io1_t),
.In3(axi_quad_spi_0_sck_t),
.dout(xlconcat_top_t_dout));
PmodNAV_xlslice_0_0 xlslice_ag_ss_i
(.Din(pmod_bridge_0_in_top_bus_I),
.Dout(xlslice_ag_ss_i_Dout));
PmodNAV_xlslice_8_0 xlslice_ag_ss_o
(.Din(axi_quad_spi_0_ss_o),
.Dout(xlslice_ag_ss_o_Dout));
PmodNAV_xlslice_0_9 xlslice_alt_ss_i
(.Din(pmod_bridge_0_in_bottom_bus_I),
.Dout(xlslice_alt_ss_i_Dout));
PmodNAV_xlslice_8_2 xlslice_alt_ss_o
(.Din(axi_quad_spi_0_ss_o),
.Dout(xlslice_alt_ss_o_Dout));
PmodNAV_xlslice_0_6 xlslice_gpio_i
(.Din(pmod_bridge_0_in_bottom_bus_I),
.Dout(xlslice_gpio_i_Dout));
PmodNAV_xlslice_0_8 xlslice_mag_ss_i
(.Din(pmod_bridge_0_in_bottom_bus_I),
.Dout(xlslice_mag_ss_i_Dout));
PmodNAV_xlslice_8_1 xlslice_mag_ss_o
(.Din(axi_quad_spi_0_ss_o),
.Dout(xlslice_mag_ss_o_Dout));
PmodNAV_xlslice_0_5 xlslice_sck_i
(.Din(pmod_bridge_0_in_top_bus_I),
.Dout(xlslice_sck_i_Dout));
PmodNAV_xlslice_0_4 xlslice_sdo_i
(.Din(pmod_bridge_0_in_top_bus_I),
.Dout(xlslice_sdo_i_Dout));
PmodNAV_xlslice_0_3 xlslice_ss_sdi_i
(.Din(pmod_bridge_0_in_top_bus_I),
.Dout(xlslice_ss_sdi_i_Dout));
endmodule
|
`timescale 1 ps / 1 ps
module myproj_top(
inout [14:0]DDR_addr,
inout [2:0]DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0]DDR_dm,
inout [31:0]DDR_dq,
inout [3:0]DDR_dqs_n,
inout [3:0]DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0]FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
output testled
);
myproj_bd_wrapper i_myproj_bd_wrapper(
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.clk_alive (testled)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog wrapper for lsbuflv2hv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbuflv2hv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbuflv2hv base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbuflv2hv base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_TB_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_TB_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dlatch_pr_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 RESET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 RESET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 RESET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 RESET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_TB_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_84x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_84x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [83:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [83:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [83:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [83:0] q = sub_wire2[83:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 84,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "84"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "84"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "84"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 84 0 INPUT NODEFVAL data[83..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 84 0 OUTPUT NODEFVAL q[83..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 84 0 data 0 0 84 0
// Retrieval info: CONNECT: q 0 0 84 0 @q 0 0 84 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_84x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_84x256.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_84x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_84x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_84x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_84x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_84x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_84x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1 ns / 1 ps
module axi_axis_reader #
(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// Slave side
output wire s_axis_tready,
input wire [AXI_DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg int_rvalid_reg, int_rvalid_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_rvalid_reg <= 1'b0;
int_rdata_reg <= {(AXI_DATA_WIDTH){1'b0}};
end
else
begin
int_rvalid_reg <= int_rvalid_next;
int_rdata_reg <= int_rdata_next;
end
end
always @*
begin
int_rvalid_next = int_rvalid_reg;
int_rdata_next = int_rdata_reg;
if(s_axi_arvalid)
begin
int_rvalid_next = 1'b1;
int_rdata_next = s_axis_tvalid ? s_axis_tdata : {(AXI_DATA_WIDTH){1'b0}};
end
if(s_axi_rready & int_rvalid_reg)
begin
int_rvalid_next = 1'b0;
end
end
assign s_axi_rresp = 2'd0;
assign s_axi_arready = 1'b1;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rvalid = int_rvalid_reg;
assign s_axis_tready = s_axi_rready & int_rvalid_reg;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: dma_engine_ctrl.v
// Project: CPCI (PCI Control FPGA)
// Description: Main state machine for the DMA engine
//
// Note: read and write are from the perspective of the driver.
// Read means retrieve a packet from the CNET and place in memory.
// Write means send a packet from memory to CNET.
//
// Change history: 12/9/07 - Split from DMA engine
//
// Issues to address:
//
///////////////////////////////////////////////////////////////////////////////
module dma_engine_ctrl (
// PCI Signals
output reg dma_rd_intr, // Request an interrupt to indicate read done
output reg dma_wr_intr, // Request an interrupt to indicate write done
// CPCI register interface signals
output reg [3:0] dma_rd_mac, // Which MAC was read data from
input [31:0] dma_wr_size, // Packet size when performing writes
input dma_rd_owner, // Who owns read buffer (1 = CPCI)
input dma_wr_owner, // Who owns write buffer (1 = CPCI)
output reg dma_rd_done, // The current read is done
output reg dma_wr_done, // The current write is done
output reg dma_rd_size_err, // Read size is invalid
output reg dma_wr_size_err, // Write size is invalid
output reg dma_rd_addr_err, // Read address is invalid
output reg dma_wr_addr_err, // Write address is invalid
output reg dma_rd_mac_err, // No data is available to read from the requested MAC (not used)
output reg dma_wr_mac_err, // No space is available to write to the requested MAC
output dma_fatal_err, // Non-recoverable error
output dma_in_progress, // Is a DMA transfer currently taking place?
// CNET DMA interface signals
output reg dma_rd_request, // Request packet from buffer
input [15:0] dma_xfer_size, // Transfer size of DMA read
input dma_rd_en, // Read a word from the buffer
input [15:0] dma_tx_full, // Buffer full in the CNET
input dma_nearly_empty, // Three words or less left in the buffer
input dma_all_in_buf, // All data for the packet is in the buffer
input dma_wr_rdy, // There's space in the buffer
input tx_wait_done,
input to_cnet_done,
input wr_empty,
input fatal, // Fatal error
output reg start, // Start (or continue) transferring
input done, // Is the transfer done?
output reg ld_xfer_cnt, // Load the xfer counter
output reg ld_dma_addr, // Load the DMA address
output reg read_get_len, // Record the length of the packet during a write
output reg write_start, // In the write start state
output ctrl_done, // In the done state
input dma_rd_request_q_vld,
input [3:0] dma_rd_request_q,
input [15:0] dma_wr_mac_one_hot,
output reg xfer_is_rd, // Xfer is a read
output reg discard, // Discard the current word
output reg reset_xfer_timer, // Reset the xfer timer
output enable_xfer_timer, // Enable the xfer timer
input abort_xfer, // Abort the transfer
output reg tx_wait_cnt_ld,// Tx Wait counter
// Miscelaneous signals
input cnet_reprog, // Indicates that the CNET is
// currently being reprogrammed
input reset,
input clk
);
// ==================================================================
// Local
// ==================================================================
// Try to start a PCI transaction
reg start_nxt;
reg ld_xfer_cnt_nxt;
// Address pointer
reg ld_dma_addr_nxt;
// DMA request signals
reg dma_rd_request_nxt;
// Delayed version of dma_rd_en
reg dma_rd_en_d1;
// Read and write done
reg dma_rd_done_nxt,dma_wr_done_nxt;
// Transfer direction
reg xfer_is_rd_nxt;
// Discard a word from the read fifo
reg discard_nxt;
// Error signals
reg dma_rd_size_err_nxt;
reg dma_wr_size_err_nxt;
reg dma_rd_addr_err_nxt;
reg dma_wr_addr_err_nxt;
reg dma_rd_mac_err_nxt;
reg dma_wr_mac_err_nxt;
// Transfer timer
reg reset_xfer_timer_nxt;
// DMA interrupt signal
reg dma_rd_intr_nxt, dma_wr_intr_nxt;
// State variables
reg read_start_nxt;
reg read_get_len_nxt;
reg write_start_nxt;
// Which MAC did we read?
reg [3:0] dma_rd_mac_nxt;
// ==================================================================
// Control state machine
// ==================================================================
/* The state machine has the following states:
* DMAC_Idle - Waiting for a transaction
* DMAC_Read - Read transaction
* DMAC_Write - Write transaction
*/
reg [3:0] curr_state, curr_state_nxt;
`define DMAC_Idle 4'h0
`define DMAC_Read_Start 4'h1
`define DMAC_Read_Get_Len 4'h2
`define DMAC_Read 4'h3
`define DMAC_Write_Start 4'h4
`define DMAC_Write 4'h5
`define DMAC_Wait 4'h8
`define DMAC_Done 4'h9
`define DMAC_Wait_Tx 4'ha
`define DMAC_Error 4'hf
always @(posedge clk)
begin
curr_state <= curr_state_nxt;
start <= start_nxt;
ld_xfer_cnt <= ld_xfer_cnt_nxt;
ld_dma_addr <= ld_dma_addr_nxt;
discard <= discard_nxt;
reset_xfer_timer <= reset_xfer_timer_nxt;
// External signals
xfer_is_rd <= xfer_is_rd_nxt;
dma_rd_request <= dma_rd_request_nxt;
dma_rd_mac <= dma_rd_mac_nxt;
dma_rd_done <= dma_rd_done_nxt;
dma_wr_done <=dma_wr_done_nxt;
dma_rd_size_err <= dma_rd_size_err_nxt;
dma_wr_size_err <= dma_wr_size_err_nxt;
dma_rd_addr_err <= dma_rd_addr_err_nxt;
dma_wr_addr_err <= dma_wr_addr_err_nxt;
dma_rd_mac_err <= dma_rd_mac_err_nxt;
dma_wr_mac_err <= dma_wr_mac_err_nxt;
dma_rd_intr <= dma_rd_intr_nxt;
dma_wr_intr <= dma_wr_intr_nxt;
read_get_len <= read_get_len_nxt;
write_start <= write_start_nxt;
end
always @*
begin
// Set defaults
curr_state_nxt = curr_state;
start_nxt = start;
ld_xfer_cnt_nxt = 1'b0;
ld_dma_addr_nxt = 1'b0;
discard_nxt = 1'b0;
reset_xfer_timer_nxt = 1'b0;
xfer_is_rd_nxt = xfer_is_rd;
dma_rd_request_nxt = 1'b0;
dma_rd_mac_nxt = dma_rd_mac;
dma_rd_done_nxt = 1'b0;
dma_wr_done_nxt = 1'b0;
dma_rd_size_err_nxt = 1'b0;
dma_wr_size_err_nxt = 1'b0;
dma_rd_addr_err_nxt = 1'b0;
dma_wr_addr_err_nxt = 1'b0;
dma_rd_mac_err_nxt = 1'b0;
dma_wr_mac_err_nxt = 1'b0;
dma_rd_intr_nxt = 1'b0;
dma_wr_intr_nxt = 1'b0;
read_get_len_nxt = read_get_len;
write_start_nxt = write_start;
tx_wait_cnt_ld = 0;
// On either reset or the CNET being reprogrammed, go to the idle state
if (reset || cnet_reprog) begin
curr_state_nxt = `DMAC_Idle;
start_nxt = 1'b0;
xfer_is_rd_nxt = 1'b0;
dma_rd_mac_nxt = 4'h0;
end
else
case (curr_state)
`DMAC_Idle : begin
// Check if there is a read request and there is data available
if (dma_rd_owner && dma_rd_request_q_vld) begin
curr_state_nxt = `DMAC_Read_Start;
reset_xfer_timer_nxt = 1'b1;
xfer_is_rd_nxt = 1'b1;
read_start_nxt = 1'b1;
end
// Check if there is a write request
else if (dma_wr_owner) begin
curr_state_nxt = `DMAC_Write_Start;
reset_xfer_timer_nxt = 1'b1;
xfer_is_rd_nxt = 1'b0;
write_start_nxt = 1'b1;
end
end
`DMAC_Read_Start : begin
curr_state_nxt = `DMAC_Read_Get_Len;
// Sample the target address
ld_dma_addr_nxt = 1'b1;
// Instruct the CNET to start transferring a packet
dma_rd_request_nxt = 1'b1;
dma_rd_mac_nxt = dma_rd_request_q;
read_start_nxt = 1'b0;
read_get_len_nxt = 1'b1;
end
`DMAC_Read_Get_Len : begin
if (dma_rd_en && !dma_rd_en_d1) begin
// Discard the word from the FIFO
discard_nxt = 1'b1;
end
if (abort_xfer) begin
curr_state_nxt = fatal ? `DMAC_Error : `DMAC_Done;
dma_rd_done_nxt = !fatal;
end
// Capture the first word that is transferred as the length
else if (dma_rd_en_d1) begin
// Make sure the size is < 2048
if (dma_xfer_size[15:11] != 'h0) begin
curr_state_nxt = `DMAC_Done;
dma_rd_done_nxt = 1'b1;
dma_rd_size_err_nxt = 1'b1;
end
else begin
curr_state_nxt = `DMAC_Wait;
// Capture the length of the transfer
ld_xfer_cnt_nxt = 1'b1;
end
// Record that we're no longer in the get len state
read_get_len_nxt = 1'b0;
end
end
`DMAC_Read : begin
// Generate a start signal if the buffer is not empty or if all
// of the data has been transferred
if (!dma_nearly_empty || (dma_all_in_buf && !done))
start_nxt = 1'b1;
else if (dma_nearly_empty || done || abort_xfer)
start_nxt = 1'b0;
// Return to the idle state when done
if (done || abort_xfer) begin
curr_state_nxt = fatal ? `DMAC_Error : `DMAC_Done;
dma_rd_done_nxt = !fatal;
dma_rd_intr_nxt = !abort_xfer;
end
end
`DMAC_Write_Start : begin
if (|(dma_wr_mac_one_hot & dma_tx_full)) begin
// wait a while to see if current pkt gets transmitted
// before we indicate an error.
curr_state_nxt = `DMAC_Wait_Tx;
tx_wait_cnt_ld = 1;
end
// Make sure the size is < 2048
else if (dma_wr_size[31:11] != 'h0) begin
curr_state_nxt = `DMAC_Done;
dma_wr_done_nxt = 1'b1;
dma_wr_size_err_nxt = 1'b1;
end
else begin
curr_state_nxt = `DMAC_Wait;
// Sample the target address
ld_dma_addr_nxt = 1'b1;
ld_xfer_cnt_nxt = 1'b1;
// Start the transfer
start_nxt = 1'b1;
end
// Record that we're leaving the write start state
write_start_nxt = 1'b0;
end
`DMAC_Write : begin
// Halt the transfer if the register buffer to the CNET becomes full
// or we've transferred everything or a timeout occurs
if (done || !dma_wr_rdy || abort_xfer)
start_nxt = 1'b0;
else if (wr_empty)
start_nxt = 1'b1;
// Return to the idle state when we're done sending all data to
// the CNET
if (to_cnet_done || abort_xfer) begin
curr_state_nxt = fatal ? `DMAC_Error : `DMAC_Done;
dma_wr_done_nxt = !fatal;
dma_wr_intr_nxt = !abort_xfer;
end
end
`DMAC_Wait : begin
// Wait a clock cycle for counts to settle
curr_state_nxt = xfer_is_rd ? `DMAC_Read : `DMAC_Write ;
end
`DMAC_Done : begin
// Wait here for one cycle for the read/write flags to be reset
curr_state_nxt = `DMAC_Idle;
end
`DMAC_Error : begin
// Stay here until reset
end
`DMAC_Wait_Tx : begin
if (tx_wait_done) begin
if (|(dma_wr_mac_one_hot & dma_tx_full)) begin
curr_state_nxt = `DMAC_Done;
dma_wr_done_nxt = 1'b1;
dma_wr_mac_err_nxt = 1'b1;
end
else // go back and try again
curr_state_nxt = `DMAC_Write_Start;
end
end
default : begin
curr_state_nxt = `DMAC_Idle;
end
endcase
end
always @(posedge clk)
begin
if (reset || cnet_reprog)
dma_rd_en_d1 <= 1'b0;
else
dma_rd_en_d1 <= dma_rd_en;
end
// ==================================================================
// Miscelaneous signal generation
// ==================================================================
assign dma_fatal_err = curr_state == `DMAC_Error;
assign dma_in_progress = curr_state != `DMAC_Idle;
assign enable_xfer_timer = curr_state != `DMAC_Idle;
assign ctrl_done = curr_state == `DMAC_Done;
endmodule // dma_engine_ctrl
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_SYMBOL_V
`define SKY130_FD_SC_HS__O2111AI_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2111ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_SYMBOL_V
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- This is a simple synchronous FIFO. --
// -----------------------------------------------------------------------------
`default_nettype none
// FWFT means "First Word Fall Through".
module zap_sync_fifo #(
parameter WIDTH = 32,
parameter DEPTH = 32,
parameter FWFT = 1,
parameter PROVIDE_NXT_DATA = 0
)
(
// Clock and reset
input wire i_clk,
input wire i_reset,
// Flow control
input wire i_ack,
input wire i_wr_en,
// Data busses
input wire [WIDTH-1:0] i_data,
output reg [WIDTH-1:0] o_data,
output reg [WIDTH-1:0] o_data_nxt,
// Flags
output wire o_empty,
output wire o_full,
output wire o_empty_n,
output wire o_full_n,
output wire o_full_n_nxt
);
// Xilinx ISE does not allow $CLOG2 in localparams.
parameter PTR_WDT = $clog2(DEPTH) + 32'd1;
parameter [PTR_WDT-1:0] DEFAULT = {PTR_WDT{1'd0}};
// Variables
reg [PTR_WDT-1:0] rptr_ff;
reg [PTR_WDT-1:0] rptr_nxt;
reg [PTR_WDT-1:0] wptr_ff;
reg empty, nempty;
reg full, nfull;
reg [PTR_WDT-1:0] wptr_nxt;
reg [WIDTH-1:0] mem [DEPTH-1:0];
wire [WIDTH-1:0] dt;
reg [WIDTH-1:0] dt1;
reg sel_ff;
reg [WIDTH-1:0] bram_ff;
reg [WIDTH-1:0] dt_ff;
// Assigns
assign o_empty = empty;
assign o_full = full;
assign o_empty_n = nempty;
assign o_full_n = nfull;
assign o_full_n_nxt = i_reset ? 1 :
!( ( wptr_nxt[PTR_WDT-2:0] == rptr_nxt[PTR_WDT-2:0] ) &&
( wptr_nxt != rptr_nxt ) );
// FIFO write logic.
always @ (posedge i_clk)
if ( i_wr_en && !o_full )
mem[wptr_ff[PTR_WDT-2:0]] <= i_data;
// FIFO read logic
generate
begin:gb1
if ( FWFT == 1 )
begin:f1
// Retimed output data compared to normal FIFO.
always @ (posedge i_clk)
begin
dt_ff <= i_data;
sel_ff <= ( i_wr_en && (wptr_ff == rptr_nxt) );
bram_ff <= mem[rptr_nxt[PTR_WDT-2:0]];
end
// Output signal steering MUX.
always @*
begin
o_data = sel_ff ? dt_ff : bram_ff;
o_data_nxt = 0; // Tied off.
end
end
else
begin:f0
always @ (posedge i_clk)
begin
if ( i_ack && nempty ) // Read request and not empty.
begin
o_data <= mem [ rptr_ff[PTR_WDT-2:0] ];
end
end
if ( PROVIDE_NXT_DATA )
begin: f11
always @ (*)
begin
if ( i_ack && nempty )
o_data_nxt = mem [ rptr_ff[PTR_WDT-2:0] ];
else
o_data_nxt = o_data;
end
end
else
begin: f22
always @* o_data_nxt = 0;
end
end
end
endgenerate
// Flip-flop update.
always @ (posedge i_clk)
begin
dt1 <= i_reset ? 0 : i_data;
rptr_ff <= i_reset ? 0 : rptr_nxt;
wptr_ff <= i_reset ? 0 : wptr_nxt;
empty <= i_reset ? 1 : ( wptr_nxt == rptr_nxt );
nempty <= i_reset ? 0 : ( wptr_nxt != rptr_nxt );
nfull <= o_full_n_nxt;
full <= !o_full_n_nxt;
end
// Pointer updates.
always @*
begin
wptr_nxt = wptr_ff + (i_wr_en && !o_full);
rptr_nxt = rptr_ff + (i_ack && !o_empty);
end
endmodule // zap_sync_fifo
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_1r1w_16x10.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
//Verilog code automatically generated by genregfile
module jbi_1r1w_16x10(
do,
rd_a,
wr_a,
di,
rd_clk,
wr_clk,
csn_wr
);
output [9:0] do;
input [3:0] rd_a;
input [3:0] wr_a;
input [9:0] di;
input rd_clk;
input wr_clk;
input csn_wr;
wire cs_wr;
reg [9:0] dout;
wire wrstrb_0000;
wire wrstrb_0001;
wire wrstrb_0010;
wire wrstrb_0011;
wire wrstrb_0100;
wire wrstrb_0101;
wire wrstrb_0110;
wire wrstrb_0111;
wire wrstrb_1000;
wire wrstrb_1001;
wire wrstrb_1010;
wire wrstrb_1011;
wire wrstrb_1100;
wire wrstrb_1101;
wire wrstrb_1110;
wire wrstrb_1111;
wire [9:0] mem_0000;
wire [9:0] mem_0001;
wire [9:0] mem_0010;
wire [9:0] mem_0011;
wire [9:0] mem_0100;
wire [9:0] mem_0101;
wire [9:0] mem_0110;
wire [9:0] mem_0111;
wire [9:0] mem_1000;
wire [9:0] mem_1001;
wire [9:0] mem_1010;
wire [9:0] mem_1011;
wire [9:0] mem_1100;
wire [9:0] mem_1101;
wire [9:0] mem_1110;
wire [9:0] mem_1111;
assign cs_wr = ~csn_wr;
assign do = dout;
assign wrstrb_0000 = ~wr_a[3] & ~wr_a[2] & ~wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_0001 = ~wr_a[3] & ~wr_a[2] & ~wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_0010 = ~wr_a[3] & ~wr_a[2] & wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_0011 = ~wr_a[3] & ~wr_a[2] & wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_0100 = ~wr_a[3] & wr_a[2] & ~wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_0101 = ~wr_a[3] & wr_a[2] & ~wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_0110 = ~wr_a[3] & wr_a[2] & wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_0111 = ~wr_a[3] & wr_a[2] & wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_1000 = wr_a[3] & ~wr_a[2] & ~wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_1001 = wr_a[3] & ~wr_a[2] & ~wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_1010 = wr_a[3] & ~wr_a[2] & wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_1011 = wr_a[3] & ~wr_a[2] & wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_1100 = wr_a[3] & wr_a[2] & ~wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_1101 = wr_a[3] & wr_a[2] & ~wr_a[1] & wr_a[0] & cs_wr;
assign wrstrb_1110 = wr_a[3] & wr_a[2] & wr_a[1] & ~wr_a[0] & cs_wr;
assign wrstrb_1111 = wr_a[3] & wr_a[2] & wr_a[1] & wr_a[0] & cs_wr;
dffe_ns #(10) U_dff_mem0000( .en(wrstrb_0000),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0000[9:0]));
dffe_ns #(10) U_dff_mem0001( .en(wrstrb_0001),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0001[9:0]));
dffe_ns #(10) U_dff_mem0010( .en(wrstrb_0010),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0010[9:0]));
dffe_ns #(10) U_dff_mem0011( .en(wrstrb_0011),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0011[9:0]));
dffe_ns #(10) U_dff_mem0100( .en(wrstrb_0100),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0100[9:0]));
dffe_ns #(10) U_dff_mem0101( .en(wrstrb_0101),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0101[9:0]));
dffe_ns #(10) U_dff_mem0110( .en(wrstrb_0110),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0110[9:0]));
dffe_ns #(10) U_dff_mem0111( .en(wrstrb_0111),
.din(di[9:0]), .clk(wr_clk),
.q(mem_0111[9:0]));
dffe_ns #(10) U_dff_mem1000( .en(wrstrb_1000),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1000[9:0]));
dffe_ns #(10) U_dff_mem1001( .en(wrstrb_1001),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1001[9:0]));
dffe_ns #(10) U_dff_mem1010( .en(wrstrb_1010),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1010[9:0]));
dffe_ns #(10) U_dff_mem1011( .en(wrstrb_1011),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1011[9:0]));
dffe_ns #(10) U_dff_mem1100( .en(wrstrb_1100),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1100[9:0]));
dffe_ns #(10) U_dff_mem1101( .en(wrstrb_1101),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1101[9:0]));
dffe_ns #(10) U_dff_mem1110( .en(wrstrb_1110),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1110[9:0]));
dffe_ns #(10) U_dff_mem1111( .en(wrstrb_1111),
.din(di[9:0]), .clk(wr_clk),
.q(mem_1111[9:0]));
always@(rd_a
or mem_0000
or mem_0001
or mem_0010
or mem_0011
or mem_0100
or mem_0101
or mem_0110
or mem_0111
or mem_1000
or mem_1001
or mem_1010
or mem_1011
or mem_1100
or mem_1101
or mem_1110
or mem_1111
)
begin
case(rd_a)
4'b0000 : dout= mem_0000;
4'b0001 : dout= mem_0001;
4'b0010 : dout= mem_0010;
4'b0011 : dout= mem_0011;
4'b0100 : dout= mem_0100;
4'b0101 : dout= mem_0101;
4'b0110 : dout= mem_0110;
4'b0111 : dout= mem_0111;
4'b1000 : dout= mem_1000;
4'b1001 : dout= mem_1001;
4'b1010 : dout= mem_1010;
4'b1011 : dout= mem_1011;
4'b1100 : dout= mem_1100;
4'b1101 : dout= mem_1101;
4'b1110 : dout= mem_1110;
4'b1111 : dout= mem_1111;
// CoverMeter line_off
default: dout= mem_0000;
// CoverMeter line_on
endcase
end
endmodule
|
/*
* lzw - Simple, Logarithmic Right Shift Unit Test
* Copyright (C) 2015 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_TEST_RIGHT_SHIFT
`else
`define INC_TEST_RIGHT_SHIFT
`timescale 1 ns / 100 ps
module sub_test_RightShift();
localparam LOGWORD = 7;
localparam WORD = (1<<LOGWORD);
localparam TEST_MIN_SHIFT = 0;
localparam TEST_MAX_SHIFT = WORD;
localparam TEST_MIN_IVALUE = 0;
localparam TEST_MAX_IVALUE = 32; // this range will be shifted down to -16 to 15
wire [WORD-1:0] test_ovalue;
reg [WORD+1-1:0] test_ivalue; // +1 just for good measure
reg [LOGWORD+1-1:0] test_shift; // +1 just for good measure
reg [LOGWORD+1-1:0] test_step; // +1 just for good measure
reg [WORD-1:0] test_validate;
reg test_error;
initial begin
test_error = 0;
for(test_shift=TEST_MIN_SHIFT; test_shift<TEST_MAX_SHIFT; test_shift=test_shift+1) begin
for(test_step=0; test_step<TEST_MAX_IVALUE; test_step=test_step+1) begin
test_ivalue <= (test_step - (TEST_MAX_IVALUE/2));
#5;
test_validate = test_ivalue;
test_validate = test_validate>>test_shift;
if(test_ovalue !== test_validate) begin
$display(
"ERROR: Input:(shift:%d ivalue:%x) => Actual:(ovalue:%x) Expected(ovalue:%x)",
test_shift[LOGWORD-1:0],
test_ivalue[WORD-1:0],
test_ovalue[WORD-1:0],
test_validate[WORD-1:0]
);
test_error = 1;
end
#5;
end
end
if(test_error) begin
$display("TEST FAILED");
$exit(-1);
end
else begin
$display("TEST PASSED");
$finish();
end
end
RightShift #(
.LOGWORD(LOGWORD)
)
i_rightshift (
.ovalue (test_ovalue[WORD-1:0] ),
.ivalue (test_ivalue[WORD-1:0] ),
.amount (test_shift[LOGWORD-1:0] )
);
endmodule
module test_RightShift();
sub_test_RightShift i_test();
initial begin
$dumpfile("test_RightShift.vcd");
$dumpvars(0, i_test);
end
endmodule
`endif
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is FALSE");
end
end
end
assign fire_2state_1 = (test_expr == 1'b0);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
// No coverage for this OVL
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_BLACKBOX_V
`define SKY130_FD_SC_LP__A22O_BLACKBOX_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22o (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_BLACKBOX_V
|
// ======================================================================
// CBC-DES encryption/decryption
// algorithm according to FIPS 46-3 specification
// Copyright (C) 2013 Torsten Meissner
//-----------------------------------------------------------------------
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write:the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
// ======================================================================
`timescale 1ns/1ps
module cbcdes
(
input reset_i, // async reset
input clk_i, // clock
input start_i, // start cbc
input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
input [0:63] key_i, // key input
input [0:63] iv_i, // iv input
input [0:63] data_i, // data input
input valid_i, // input key/data valid flag
output reg ready_o, // ready to encrypt/decrypt
output reg [0:63] data_o, // data output
output valid_o // output data valid flag
);
reg mode;
wire des_mode;
reg start;
reg [0:63] key;
wire [0:63] des_key;
reg [0:63] iv;
reg [0:63] datain;
reg [0:63] datain_d;
reg [0:63] des_datain;
wire validin;
wire [0:63] des_dataout;
reg reset;
reg [0:63] dataout;
assign des_key = (start_i) ? key_i : key;
assign des_mode = (start_i) ? mode_i : mode;
assign validin = valid_i & ready_o;
always @(*) begin
if (~mode_i && start_i) begin
des_datain = iv_i ^ data_i;
end
else if (~mode && ~start_i) begin
des_datain = dataout ^ data_i;
end
else begin
des_datain = data_i;
end
end
always @(*) begin
if (mode && start) begin
data_o = iv ^ des_dataout;
end
else if (mode && ~start) begin
data_o = datain_d ^ des_dataout;
end
else begin
data_o = des_dataout;
end
end
// input register
always @(posedge clk_i, negedge reset_i) begin
if (~reset_i) begin
reset <= 0;
mode <= 0;
start <= 0;
key <= 0;
iv <= 0;
datain <= 0;
datain_d <= 0;
end
else begin
reset <= reset_i;
if (valid_i && ready_o) begin
start <= start_i;
datain <= data_i;
datain_d <= datain;
end
else if (valid_i && ready_o && start_i) begin
mode <= mode_i;
key <= key_i;
iv <= iv_i;
end
end
end
// output register
always @(posedge clk_i, negedge reset_i) begin
if (~reset_i) begin
ready_o <= 0;
dataout <= 0;
end
else begin
if (valid_i && ready_o) begin
ready_o <= 0;
end
else if (valid_o || (reset_i && ~reset)) begin
ready_o <= 1;
dataout <= des_dataout;
end
end
end
// des instance
des i_des (
.reset_i(reset),
.clk_i(clk_i),
.mode_i(des_mode),
.key_i(des_key),
.data_i(des_datain),
.valid_i(validin),
.data_o(des_dataout),
.valid_o(valid_o)
);
endmodule
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0] FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
inout [15:0] DDR3_addr,
inout [2:0] DDR3_ba,
inout DDR3_cas_n,
inout DDR3_ck_n,
inout DDR3_ck_p,
inout DDR3_cke,
inout DDR3_cs_n,
inout [3:0] DDR3_dm,
inout [31:0] DDR3_dq,
inout [3:0] DDR3_dqs_n,
inout [3:0] DDR3_dqs_p,
inout DDR3_odt,
inout DDR3_ras_n,
inout DDR3_reset_n,
inout DDR3_we_n,
input sgmii_refclk_p,
input sgmii_refclk_n,
output [1:0] pl_led,
output [1:0] pl_pmod,
input pl_btn
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
wire bd_aresetn ;
wire init_calib_complete;
wire mmcm_locked;
wire sgmii_refclk_se;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge sgmii_refclk_se) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = mmcm_locked;
assign pl_pmod[0] = init_calib_complete;
assign pl_pmod[1] = bd_aresetn;
// sgmii ref clk
IBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFDS_i_sgmii_refclk (
.O (sgmii_refclk_se), // Buffer output
.I (sgmii_refclk_p), // Diff_p buffer input (connect directly to top-level port)
.IB (sgmii_refclk_n) // Diff_n buffer input (connect directly to top-level port)
);
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.DDR3_addr (DDR3_addr),
.DDR3_ba (DDR3_ba),
.DDR3_cas_n (DDR3_cas_n),
.DDR3_ck_n (DDR3_ck_n),
.DDR3_ck_p (DDR3_ck_p),
.DDR3_cke (DDR3_cke),
.DDR3_cs_n (DDR3_cs_n),
.DDR3_dm (DDR3_dm),
.DDR3_dq (DDR3_dq),
.DDR3_dqs_n (DDR3_dqs_n),
.DDR3_dqs_p (DDR3_dqs_p),
.DDR3_odt (DDR3_odt),
.DDR3_ras_n (DDR3_ras_n),
.DDR3_reset_n (DDR3_reset_n),
.DDR3_we_n (DDR3_we_n),
.mmcm_locked (mmcm_locked),
.init_calib_complete (init_calib_complete),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m ),
.bd_aresetn ( bd_aresetn ),
.ext_rst ( pl_btn )
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Graphics module top level
// File : graph_top.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the integration of all the graphic
// interface modules described below.
//
// The signal which have the suffic as c_ indicates that
// this are generated from crt module, if g_ indicate
// that this are generated from graph module, if h_ indicates
// its generated from host module, if a_ indicates that
// this are generated from attribute module and if m_ then
// signals are generated from memory module.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
// sm_cpu_cy124.v
// htaddmap.v
// grap_reg_dec.v
// grap_data_wr.v
// grap_data_rd.v
// read_data.v
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module graph_top
(
input t_mem_io_n,
input t_svga_sel,
input cpu_rd_gnt,
input m_cpurd_s0,
input t_data_ready_n,
input svga_ack,
input h_reset_n, // Power on reset
input t_mem_clk, // Memory reference clock input.
input h_svga_sel, /* This pin is driven by the host I/F block
* indicating that a valid address has been
* decoded in a SVGA memory space or a svga
* IO space. These signals are buffered
* from the top level. */
input h_hrd_hwr_n, // indicates whether a read or a write.
input h_mem_io_n, // indicates whether a memory or a IO acc.
input [3:0] h_byte_en_n, // specify the width of the data.
input [31:0] h_mem_dbus_out, /* Data bus for Memory read/write operation
* from/to Host module. */
input m_cpu_ff_full, // Indicates the cpu fifo is full.
input [22:0] h_mem_addr, // Lower 23 bits for memory operation.
input c_mis_3c2_b5, // Odd/Even page select.
input h_iord, // Indicates curr IO cycle is a read cycle.
input h_iowr, // Indicates curr IO cycle is a write cycle
input h_io_16, // Indicates the current IO cycle is 16 bit.
input h_dec_3cx, // IO group decode of address range 03CX.
input [15:0] h_io_addr, // Used for IO decodes.
input c_misc_b0, //
input c_misc_b1,
input c_gr_ext_en, //
input [7:0] c_ext_index,
input m_sr04_b3, // Double odd/even (chain4) addressing mode.
input m_ready_n,
input m_chain4, // Double odd/even (chain4) addressing mode.
input m_odd_even, // Odd/Even addressing mode.
input m_planar, // Plannar addressing mode.
input m_memrd_ready_n,
input [3:0] m_sr02_b, // Plane enable register bits.
input [15:8] h_io_dbus, // Data bus for I/O read/write operation
input [31:0] g_graph_data_in,// Data bus to/from memory module.
output [7:0] g_reg_gr0,
output [7:0] g_reg_gr1,
output [7:0] g_reg_gr2,
output [7:0] g_reg_gr3,
output [7:0] g_reg_gr4,
output [7:0] g_reg_gr5,
output [7:0] g_reg_gr6,
output [7:0] g_reg_gr7,
output [7:0] g_reg_gr8,
output [31:0] h_mem_dbus_in,
output g_ready_n, // Indicates the current IO cycle is done.
output g_mem_ready_n, // Indicates the current memory cycle is done.
output g_memwr, // Indicates memory write cycle in progress.
output g_gr05_b5,
output g_gr05_b6,
output g_gr05_b4,
output g_gr06_b0,
output g_gr06_b1,
output [31:0] g_graph_data_out, // Data bus to/from memory module.
output [5:0] g_t_ctl_bit, /* Indicates the appropriate address range
* required to be decoded in order to
* generate SVGA_SEL. */
output [7:0] g_int_crt22_data,
output g_memrd,
output [19:0] val_mrdwr_addr,
output [7:0] fin_plane_sel,
output g_lt_hwr_cmd,
output g_cpult_state1,
output g_cpu_data_done,
output g_cpu_cycle_done,
output gra_mod_rd_en
);
//
// Define Variables
//
wire en_cy1;
wire en_cy2;
wire en_cy3;
wire en_cy4;
wire en_cy1_ff;
wire en_cy2_ff;
wire en_cy3_ff;
wire en_cy4_ff;
wire odd_8bit;
wire rd_en_0, rd_en_1;
wire memwr_inpr;
wire [31:0] sftw_h_mem_dbus;
wire [1:0] g_graph_addr;
wire gr4_b0;
wire gr4_b1;
wire gr6_b2;
wire gr6_b3;
wire [3:0] reg_gr0_qout;
wire [3:0] reg_gr1_qout;
wire [3:0] reg_gr2_qout;
wire [4:0] reg_gr3_qout;
wire [3:0] reg_gr7_qout;
wire [7:0] reg_gr8_qout;
wire gr5_b0; // write mode[0]
wire gr5_b1; // write mode[1]
wire mem_clk;
wire read_mode_1;
wire read_mode_0;
wire [31:0] cpu_lat_data;
wire cpucy_1_2;
wire cpucy_2_2;
wire cpucy_1_3;
wire cpucy_2_3;
wire cpucy_3_3;
wire cpucy_1_4;
wire cpucy_2_4;
wire cpucy_3_4;
wire cpucy_4_4;
wire cy2_gnt;
wire cy3_gnt;
wire cy4_gnt;
wire mem_write;
wire [31:0] h2mem_bout;
wire mem_read;
wire svga_sel_hit;
wire svmem_sel_hit;
wire svmem_hit_we;
wire cur_cpurd_done;
wire cycle2;
wire m2s1_q;
wire m2s2_q;
sm_cpu_cy124 CY124
(
.t_mem_io_n (t_mem_io_n),
.t_svga_sel (t_svga_sel),
.m_cpurd_s0 (m_cpurd_s0),
.t_data_ready_n (t_data_ready_n),
.cpu_rd_gnt (cpu_rd_gnt),
.svga_ack (svga_ack),
.en_cy1 (en_cy1),
.en_cy2 (en_cy2),
.en_cy3 (en_cy3),
.en_cy4 (en_cy4),
.c_misc_b1 (c_misc_b1),
.h_reset_n (h_reset_n),
.t_mem_clk (t_mem_clk),
.h_svga_sel (h_svga_sel),
.h_hrd_hwr_n (h_hrd_hwr_n),
.h_mem_io_n (h_mem_io_n),
.m_cpu_ff_full (m_cpu_ff_full),
.m_chain4 (m_chain4),
.m_odd_even (m_odd_even),
.m_planar (m_planar),
.m_memrd_ready_n (m_memrd_ready_n),
.cpucy_1_2 (cpucy_1_2),
.cpucy_2_2 (cpucy_2_2),
.cpucy_1_3 (cpucy_1_3),
.cpucy_2_3 (cpucy_2_3),
.cpucy_3_3 (cpucy_3_3),
.cpucy_1_4 (cpucy_1_4),
.cpucy_2_4 (cpucy_2_4),
.cpucy_3_4 (cpucy_3_4),
.cpucy_4_4 (cpucy_4_4),
.g_mem_ready_n (g_mem_ready_n),
.g_memwr (g_memwr),
.mem_clk (mem_clk),
.g_memrd (g_memrd),
.g_lt_hwr_cmd (g_lt_hwr_cmd),
.g_cpult_state1 (g_cpult_state1),
.cy2_gnt (cy2_gnt),
.cy3_gnt (cy3_gnt),
.cy4_gnt (cy4_gnt),
.mem_write (mem_write),
.memwr_inpr (memwr_inpr),
.g_cpu_data_done (g_cpu_data_done),
.g_cpu_cycle_done (g_cpu_cycle_done),
.mem_read (mem_read),
.svga_sel_hit (svga_sel_hit),
.svmem_sel_hit (svmem_sel_hit),
.svmem_hit_we (svmem_hit_we),
.en_cy1_ff (en_cy1_ff),
.en_cy2_ff (en_cy2_ff),
.en_cy3_ff (en_cy3_ff),
.en_cy4_ff (en_cy4_ff),
.cur_cpurd_done (cur_cpurd_done)
);
htaddmap HADMAP
(
.mem_read (mem_read),
.cpu_rd_gnt (cpu_rd_gnt),
.svmem_hit_we (svmem_hit_we),
.svmem_sel_hit (svmem_sel_hit),
.svga_sel_hit (svga_sel_hit),
.t_mem_io_n (t_mem_io_n),
.h_mem_dbus_out (h_mem_dbus_out),
.memwr_inpr (memwr_inpr),
.mem_write (mem_write),
.cy2_gnt (cy2_gnt),
.cy3_gnt (cy3_gnt),
.cy4_gnt (cy4_gnt),
.h_byte_en_n (h_byte_en_n),
.m_planar (m_planar),
.cpucy_1_2 (cpucy_1_2),
.cpucy_2_2 (cpucy_2_2),
.cpucy_1_3 (cpucy_1_3),
.cpucy_2_3 (cpucy_2_3),
.cpucy_3_3 (cpucy_3_3),
.cpucy_1_4 (cpucy_1_4),
.cpucy_2_4 (cpucy_2_4),
.cpucy_3_4 (cpucy_3_4),
.cpucy_4_4 (cpucy_4_4),
.h_mem_addr (h_mem_addr),
.c_mis_3c2_b5 (c_mis_3c2_b5),
.gr6_b2 (gr6_b2),
.gr6_b3 (gr6_b3),
.g_gr06_b1 (g_gr06_b1),
.m_odd_even (m_odd_even),
.m_chain4 (m_chain4),
.m_sr02_b (m_sr02_b),
.val_mrdwr_addr (val_mrdwr_addr),
.fin_plane_sel (fin_plane_sel),
.en_cy1 (en_cy1),
.en_cy2 (en_cy2),
.en_cy3 (en_cy3),
.en_cy4 (en_cy4),
.sftw_h_mem_dbus (sftw_h_mem_dbus),
.odd_8bit (odd_8bit)
);
grap_reg_dec GREGD
(
.h_reset_n (h_reset_n),
.h_iord (h_iord),
.h_iowr (h_iowr),
.h_io_16 (h_io_16),
.h_dec_3cx (h_dec_3cx),
.h_io_addr (h_io_addr),
.h_io_dbus (h_io_dbus[15:8]),
.h_hclk (t_mem_clk),
.c_misc_b0 (c_misc_b0),
.c_gr_ext_en (c_gr_ext_en),
.c_ext_index (c_ext_index),
.g_t_ctl_bit (g_t_ctl_bit),
.gr5_b0 (gr5_b0),
.gr5_b1 (gr5_b1),
.read_mode_0 (read_mode_0),
.read_mode_1 (read_mode_1),
.g_gr05_b4 (g_gr05_b4),
.g_gr05_b5 (g_gr05_b5),
.g_gr05_b6 (g_gr05_b6),
.gr4_b0 (gr4_b0),
.gr4_b1 (gr4_b1),
.g_gr06_b0 (g_gr06_b0),
.g_gr06_b1 (g_gr06_b1),
.gr6_b2 (gr6_b2),
.gr6_b3 (gr6_b3),
.reg_gr0_qout (reg_gr0_qout),
.reg_gr1_qout (reg_gr1_qout),
.reg_gr2_qout (reg_gr2_qout),
.reg_gr3_qout (reg_gr3_qout),
.reg_gr7_qout (reg_gr7_qout),
.reg_gr8_qout (reg_gr8_qout),
.g_ready_n (g_ready_n),
.gra_mod_rd_en (gra_mod_rd_en),
.g_reg_gr0 (g_reg_gr0),
.g_reg_gr1 (g_reg_gr1),
.g_reg_gr2 (g_reg_gr2),
.g_reg_gr3 (g_reg_gr3),
.g_reg_gr4 (g_reg_gr4),
.g_reg_gr5 (g_reg_gr5),
.g_reg_gr6 (g_reg_gr6),
.g_reg_gr7 (g_reg_gr7),
.g_reg_gr8 (g_reg_gr8)
);
grap_data_wr GDWR
(
.sftw_h_mem_dbus (sftw_h_mem_dbus),
.g_memrd (g_memrd),
.m_sr04_b3 (m_sr04_b3),
.reg_gr0_qout (reg_gr0_qout),
.reg_gr1_qout (reg_gr1_qout),
.gr5_b0 (gr5_b0),
.gr5_b1 (gr5_b1),
.m_odd_even (m_odd_even),
.reg_gr3_qout (reg_gr3_qout),
.reg_gr8_qout (reg_gr8_qout),
.cpu_lat_data (cpu_lat_data),
.g_graph_data_out (g_graph_data_out)
);
grap_data_rd GDRD
(
.m2s1_q (m2s1_q),
.m2s2_q (m2s2_q),
.cycle2 (cycle2),
.h_byte_en_n (h_byte_en_n[3:0]),
.cur_cpurd_done (cur_cpurd_done),
.m_memrd_ready_n (m_memrd_ready_n),
.odd_8bit (odd_8bit),
.h_hrd_hwr_n (h_hrd_hwr_n),
.h_mem_io_n (h_mem_io_n),
.g_mem_ready_n (g_mem_ready_n),
.hreset_n (h_reset_n),
.mem_clk (mem_clk),
.m_sr04_b3 (m_sr04_b3),
.m_odd_even (m_odd_even),
.val_mrdwr_addr (val_mrdwr_addr[1:0]),
.gr4_b1 (gr4_b1),
.gr4_b0 (gr4_b0),
.reg_gr2_qout (reg_gr2_qout),
.reg_gr7_qout (reg_gr7_qout),
.read_mode_1 (read_mode_1),
.read_mode_0 (read_mode_0),
.m_ready_n (m_ready_n),
.g_graph_data_in (g_graph_data_in),
.cpu_lat_data (cpu_lat_data),
.h2mem_bout (h2mem_bout),
.g_int_crt22_data (g_int_crt22_data),
.rd_en_0 (rd_en_0),
.rd_en_1 (rd_en_1)
);
read_data RDD
(
.h_byte_en_n (h_byte_en_n),
.rd_en_0 (rd_en_0),
.rd_en_1 (rd_en_1),
.en_cy1_ff (en_cy1_ff),
.en_cy2_ff (en_cy2_ff),
.en_cy3_ff (en_cy3_ff),
.en_cy4_ff (en_cy4_ff),
.mem_read (mem_read),
.mem_clk (mem_clk),
.hreset_n (h_reset_n),
.m_odd_even (m_odd_even),
.h2mem_bout (h2mem_bout),
.h_mem_dbus_in (h_mem_dbus_in),
.cycle2 (cycle2),
.m2s1_q (m2s1_q),
.m2s2_q (m2s2_q)
);
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_mutex (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 2;
parameter invert_mode = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1 : 0] test_expr;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_MUTEX";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_mutex_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_mutex
|
// qsys.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module qsys (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
input wire sdram_clock_areset_conduit_export, // sdram_clock_areset_conduit.export
output wire sdram_clock_c0_clk, // sdram_clock_c0.clk
input wire sdram_read_control_fixed_location, // sdram_read_control.fixed_location
input wire [31:0] sdram_read_control_read_base, // .read_base
input wire [31:0] sdram_read_control_read_length, // .read_length
input wire sdram_read_control_go, // .go
output wire sdram_read_control_done, // .done
output wire sdram_read_control_early_done, // .early_done
input wire sdram_read_user_read_buffer, // sdram_read_user.read_buffer
output wire [63:0] sdram_read_user_buffer_output_data, // .buffer_output_data
output wire sdram_read_user_data_available, // .data_available
output wire [12:0] sdram_wire_addr, // sdram_wire.addr
output wire [1:0] sdram_wire_ba, // .ba
output wire sdram_wire_cas_n, // .cas_n
output wire sdram_wire_cke, // .cke
output wire sdram_wire_cs_n, // .cs_n
inout wire [15:0] sdram_wire_dq, // .dq
output wire [1:0] sdram_wire_dqm, // .dqm
output wire sdram_wire_ras_n, // .ras_n
output wire sdram_wire_we_n, // .we_n
input wire sdram_write_control_fixed_location, // sdram_write_control.fixed_location
input wire [31:0] sdram_write_control_write_base, // .write_base
input wire [31:0] sdram_write_control_write_length, // .write_length
input wire sdram_write_control_go, // .go
output wire sdram_write_control_done, // .done
input wire sdram_write_user_write_buffer, // sdram_write_user.write_buffer
input wire [15:0] sdram_write_user_buffer_input_data, // .buffer_input_data
output wire sdram_write_user_buffer_full // .buffer_full
);
wire [63:0] sdram_read_avalon_master_readdata; // mm_interconnect_0:sdram_read_avalon_master_readdata -> sdram_read:master_readdata
wire sdram_read_avalon_master_waitrequest; // mm_interconnect_0:sdram_read_avalon_master_waitrequest -> sdram_read:master_waitrequest
wire [31:0] sdram_read_avalon_master_address; // sdram_read:master_address -> mm_interconnect_0:sdram_read_avalon_master_address
wire sdram_read_avalon_master_read; // sdram_read:master_read -> mm_interconnect_0:sdram_read_avalon_master_read
wire [7:0] sdram_read_avalon_master_byteenable; // sdram_read:master_byteenable -> mm_interconnect_0:sdram_read_avalon_master_byteenable
wire sdram_read_avalon_master_readdatavalid; // mm_interconnect_0:sdram_read_avalon_master_readdatavalid -> sdram_read:master_readdatavalid
wire sdram_write_avalon_master_waitrequest; // mm_interconnect_0:sdram_write_avalon_master_waitrequest -> sdram_write:master_waitrequest
wire [31:0] sdram_write_avalon_master_address; // sdram_write:master_address -> mm_interconnect_0:sdram_write_avalon_master_address
wire [1:0] sdram_write_avalon_master_byteenable; // sdram_write:master_byteenable -> mm_interconnect_0:sdram_write_avalon_master_byteenable
wire sdram_write_avalon_master_write; // sdram_write:master_write -> mm_interconnect_0:sdram_write_avalon_master_write
wire [15:0] sdram_write_avalon_master_writedata; // sdram_write:master_writedata -> mm_interconnect_0:sdram_write_avalon_master_writedata
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire [15:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [23:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [1:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire [15:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:sdram_read_clock_reset_reset_reset_bridge_in_reset_reset, sdram:reset_n, sdram_clock:reset, sdram_read:reset, sdram_write:reset]
qsys_sdram sdram (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_wire_addr), // wire.export
.zs_ba (sdram_wire_ba), // .export
.zs_cas_n (sdram_wire_cas_n), // .export
.zs_cke (sdram_wire_cke), // .export
.zs_cs_n (sdram_wire_cs_n), // .export
.zs_dq (sdram_wire_dq), // .export
.zs_dqm (sdram_wire_dqm), // .export
.zs_ras_n (sdram_wire_ras_n), // .export
.zs_we_n (sdram_wire_we_n) // .export
);
qsys_sdram_clock sdram_clock (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_reset_out_reset), // inclk_interface_reset.reset
.read (), // pll_slave.read
.write (), // .write
.address (), // .address
.readdata (), // .readdata
.writedata (), // .writedata
.c0 (sdram_clock_c0_clk), // c0.clk
.areset (sdram_clock_areset_conduit_export), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
custom_master #(
.MASTER_DIRECTION (0),
.DATA_WIDTH (64),
.ADDRESS_WIDTH (32),
.BURST_CAPABLE (0),
.MAXIMUM_BURST_COUNT (2),
.BURST_COUNT_WIDTH (2),
.FIFO_DEPTH (32),
.FIFO_DEPTH_LOG2 (5),
.MEMORY_BASED_FIFO (1)
) sdram_read (
.clk (clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_address (sdram_read_avalon_master_address), // avalon_master.address
.master_read (sdram_read_avalon_master_read), // .read
.master_byteenable (sdram_read_avalon_master_byteenable), // .byteenable
.master_readdata (sdram_read_avalon_master_readdata), // .readdata
.master_readdatavalid (sdram_read_avalon_master_readdatavalid), // .readdatavalid
.master_waitrequest (sdram_read_avalon_master_waitrequest), // .waitrequest
.control_fixed_location (sdram_read_control_fixed_location), // control.export
.control_read_base (sdram_read_control_read_base), // .export
.control_read_length (sdram_read_control_read_length), // .export
.control_go (sdram_read_control_go), // .export
.control_done (sdram_read_control_done), // .export
.control_early_done (sdram_read_control_early_done), // .export
.user_read_buffer (sdram_read_user_read_buffer), // user.export
.user_buffer_output_data (sdram_read_user_buffer_output_data), // .export
.user_data_available (sdram_read_user_data_available), // .export
.master_write (), // (terminated)
.master_writedata (), // (terminated)
.master_burstcount (), // (terminated)
.control_write_base (32'b00000000000000000000000000000000), // (terminated)
.control_write_length (32'b00000000000000000000000000000000), // (terminated)
.user_write_buffer (1'b0), // (terminated)
.user_buffer_input_data (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.user_buffer_full () // (terminated)
);
custom_master #(
.MASTER_DIRECTION (1),
.DATA_WIDTH (16),
.ADDRESS_WIDTH (32),
.BURST_CAPABLE (0),
.MAXIMUM_BURST_COUNT (2),
.BURST_COUNT_WIDTH (2),
.FIFO_DEPTH (32),
.FIFO_DEPTH_LOG2 (5),
.MEMORY_BASED_FIFO (1)
) sdram_write (
.clk (clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_address (sdram_write_avalon_master_address), // avalon_master.address
.master_write (sdram_write_avalon_master_write), // .write
.master_byteenable (sdram_write_avalon_master_byteenable), // .byteenable
.master_writedata (sdram_write_avalon_master_writedata), // .writedata
.master_waitrequest (sdram_write_avalon_master_waitrequest), // .waitrequest
.control_fixed_location (sdram_write_control_fixed_location), // control.export
.control_write_base (sdram_write_control_write_base), // .export
.control_write_length (sdram_write_control_write_length), // .export
.control_go (sdram_write_control_go), // .export
.control_done (sdram_write_control_done), // .export
.user_write_buffer (sdram_write_user_write_buffer), // user.export
.user_buffer_input_data (sdram_write_user_buffer_input_data), // .export
.user_buffer_full (sdram_write_user_buffer_full), // .export
.master_read (), // (terminated)
.master_readdata (16'b0000000000000000), // (terminated)
.master_readdatavalid (1'b0), // (terminated)
.master_burstcount (), // (terminated)
.control_read_base (32'b00000000000000000000000000000000), // (terminated)
.control_read_length (32'b00000000000000000000000000000000), // (terminated)
.control_early_done (), // (terminated)
.user_read_buffer (1'b0), // (terminated)
.user_buffer_output_data (), // (terminated)
.user_data_available () // (terminated)
);
qsys_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.sdram_read_clock_reset_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // sdram_read_clock_reset_reset_reset_bridge_in_reset.reset
.sdram_read_avalon_master_address (sdram_read_avalon_master_address), // sdram_read_avalon_master.address
.sdram_read_avalon_master_waitrequest (sdram_read_avalon_master_waitrequest), // .waitrequest
.sdram_read_avalon_master_byteenable (sdram_read_avalon_master_byteenable), // .byteenable
.sdram_read_avalon_master_read (sdram_read_avalon_master_read), // .read
.sdram_read_avalon_master_readdata (sdram_read_avalon_master_readdata), // .readdata
.sdram_read_avalon_master_readdatavalid (sdram_read_avalon_master_readdatavalid), // .readdatavalid
.sdram_write_avalon_master_address (sdram_write_avalon_master_address), // sdram_write_avalon_master.address
.sdram_write_avalon_master_waitrequest (sdram_write_avalon_master_waitrequest), // .waitrequest
.sdram_write_avalon_master_byteenable (sdram_write_avalon_master_byteenable), // .byteenable
.sdram_write_avalon_master_write (sdram_write_avalon_master_write), // .write
.sdram_write_avalon_master_writedata (sdram_write_avalon_master_writedata), // .writedata
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_axi_basic_tx_thrtl_ctl.v
// Version : 1.11
// //
// Description: //
// TX throttle controller. Anticipates back-pressure from PCIe block and //
// preemptively back-pressures user design (packet boundary throttling). //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// axi_basic_tx_thrtl_ctl //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_axi_basic_tx_thrtl_ctl #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter TCQ = 1 // Clock to Q time
) (
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
input [3:0] s_axis_tx_tuser, // TX user signals
input s_axis_tx_tlast, // TX data is last
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
// TRN TX
//-----------
input [5:0] trn_tbuf_av, // TX buffers available
input trn_tdst_rdy, // TX destination ready
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // TX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output reg cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output reg tready_thrtl, // TREADY to pipeline
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Thrtl user when TBUF hits this val
localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :
(C_DATA_WIDTH == 64) ? 1 : 0;
// Pause user when TBUF hits this val
localparam TBUF_AV_GAP = TBUF_AV_MIN + 1;
// GAP pause time - the latency from the time a packet is accepted on the TRN
// interface to the time trn_tbuf_av from the Block will decrement.
localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;
// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle
localparam TCFG_LATENCY_TIME = 2'd2;
// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only
localparam TCFG_GNT_PIPE_STAGES = 3;
// Throttle condition registers and constants
reg lnk_up_thrtl;
wire lnk_up_trig;
wire lnk_up_exit;
reg tbuf_av_min_thrtl;
wire tbuf_av_min_trig;
reg tbuf_av_gap_thrtl;
reg [2:0] tbuf_gap_cnt;
wire tbuf_av_gap_trig;
wire tbuf_av_gap_exit;
wire gap_trig_tlast;
wire gap_trig_decr;
reg [5:0] tbuf_av_d;
reg tcfg_req_thrtl;
reg [1:0] tcfg_req_cnt;
reg trn_tdst_rdy_d;
wire tcfg_req_trig;
wire tcfg_req_exit;
reg tcfg_gnt_log;
wire pre_throttle;
wire reg_throttle;
wire exit_crit;
reg reg_tcfg_gnt;
reg trn_tcfg_req_d;
reg tcfg_gnt_pending;
wire wire_to_turnoff;
reg reg_turnoff_ok;
reg tready_thrtl_mux;
localparam LINKSTATE_L0 = 3'b000;
localparam LINKSTATE_PPM_L1 = 3'b001;
localparam LINKSTATE_PPM_L1_TRANS = 3'b101;
localparam LINKSTATE_PPM_L23R_TRANS = 3'b110;
localparam PM_ENTER_L1 = 8'h20;
localparam POWERSTATE_D0 = 2'b00;
reg ppm_L1_thrtl;
wire ppm_L1_trig;
wire ppm_L1_exit;
reg [2:0] cfg_pcie_link_state_d;
reg trn_rdllp_src_rdy_d;
reg ppm_L23_thrtl;
wire ppm_L23_trig;
reg cfg_turnoff_ok_pending;
reg reg_tlast;
// Throttle control state machine states and registers
localparam IDLE = 0;
localparam THROTTLE = 1;
reg cur_state;
reg next_state;
reg reg_axi_in_pkt;
wire axi_in_pkt;
wire axi_pkt_ending;
wire axi_throttled;
wire axi_thrtl_ok;
wire tx_ecrc_pause;
//----------------------------------------------------------------------------//
// THROTTLE REASON: PCIe link is down //
// - When to throttle: trn_lnk_up deasserted //
// - When to stop: trn_tdst_rdy assesrted //
//----------------------------------------------------------------------------//
assign lnk_up_trig = !trn_lnk_up;
assign lnk_up_exit = trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else begin
if(lnk_up_trig) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else if(lnk_up_exit) begin
lnk_up_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers depleted //
// - When to throttle: trn_tbuf_av falls to 0 //
// - When to stop: trn_tbuf_av rises above 0 again //
//----------------------------------------------------------------------------//
assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
else begin
if(tbuf_av_min_trig) begin
tbuf_av_min_thrtl <= #TCQ 1'b1;
end
// The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig
else begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers getting low //
// - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP //
// - When to stop: after TBUF_GAP_TIME cycles elapse //
// //
// If we're about to run out of transmit buffers, throttle the user for a //
// few clock cycles to give the PCIe block time to catch up. This is //
// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe //
// Block transmit path. //
//----------------------------------------------------------------------------//
// Detect two different scenarios for buffers getting low:
// 1) If we see a TLAST. a new packet has been inserted into the buffer, and
// we need to pause and let that packet "soak in"
assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&
s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;
// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to
// pause and make sure no other packets are about to soak in and cause the
// buffer availability to drop further.
assign gap_trig_decr = (trn_tbuf_av == (TBUF_AV_GAP)) &&
(tbuf_av_d == (TBUF_AV_GAP+1));
assign gap_trig_tcfg = (tcfg_req_thrtl && tcfg_req_exit);
assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;
assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
tbuf_gap_cnt <= #TCQ 3'h0;
tbuf_av_d <= #TCQ 6'h00;
end
else begin
if(tbuf_av_gap_trig) begin
tbuf_av_gap_thrtl <= #TCQ 1'b1;
end
else if(tbuf_av_gap_exit) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
end
// tbuf gap counter:
// This logic controls the length of the throttle condition when tbufs are
// getting low.
if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin
if(tbuf_gap_cnt > 0) begin
tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;
end
end
else begin
tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;
end
tbuf_av_d <= #TCQ trn_tbuf_av;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to send a CFG response //
// - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted //
// - When to stop: after trn_tdst_rdy transitions to unasserted //
// //
// If the block needs to send a response to a CFG packet, this will cause //
// the subsequent deassertion of trn_tdst_rdy. When the user design permits, //
// grant permission to the block to service request and throttle the user. //
//----------------------------------------------------------------------------//
assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;
assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&
trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_req_thrtl <= #TCQ 1'b0;
trn_tcfg_req_d <= #TCQ 1'b0;
trn_tdst_rdy_d <= #TCQ 1'b1;
reg_tcfg_gnt <= #TCQ 1'b0;
tcfg_req_cnt <= #TCQ 2'd0;
tcfg_gnt_pending <= #TCQ 1'b0;
end
else begin
if(tcfg_req_trig) begin
tcfg_req_thrtl <= #TCQ 1'b1;
end
else if(tcfg_req_exit) begin
tcfg_req_thrtl <= #TCQ 1'b0;
end
// We need to wait the appropriate amount of time for the tcfg_gnt to
// "sink in" to the PCIe block. After that, we know that the PCIe block will
// not reassert trn_tdst_rdy until the CFG request has been serviced. If a
// new request is being service (tcfg_gnt_log == 1), then reset the timer.
if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin
tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;
end
else begin
if(tcfg_req_cnt > 0) begin
tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;
end
end
// Make sure tcfg_gnt_log pulses once for one clock cycle for every
// cfg packet request.
if(trn_tcfg_req && !trn_tcfg_req_d) begin
tcfg_gnt_pending <= #TCQ 1'b1;
end
else if(tcfg_gnt_log) begin
tcfg_gnt_pending <= #TCQ 1'b0;
end
trn_tcfg_req_d <= #TCQ trn_tcfg_req;
trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;
reg_tcfg_gnt <= #TCQ user_tcfg_gnt;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L1 //
// - When to throttle: appropriate low power state signal asserted //
// (architecture dependent) //
// - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT //
// dependent) //
// //
// If the block needs to transition to PM state PPM L1, we need to finish //
// up what we're doing and throttle immediately. //
//----------------------------------------------------------------------------//
generate
// PPM L1 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for 7 Series in EP mode
else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp
assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&
trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for V6 in EP mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 detection not supported for S6
else begin : s6_L1_thrtl
assign ppm_L1_trig = 1'b0;
assign ppm_L1_exit = 1'b1;
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L1_thrtl <= #TCQ 1'b0;
cfg_pcie_link_state_d <= #TCQ 3'b0;
trn_rdllp_src_rdy_d <= #TCQ 1'b0;
end
else begin
if(ppm_L1_trig) begin
ppm_L1_thrtl <= #TCQ 1'b1;
end
else if(ppm_L1_exit) begin
ppm_L1_thrtl <= #TCQ 1'b0;
end
cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;
trn_rdllp_src_rdy_d <= #TCQ trn_rdllp_src_rdy;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L2/3 //
// - When to throttle: appropriate PM signal indicates a transition to //
// L2/3 is pending or in progress (family and role dependent) //
// - When to stop: never (the only path out of L2/3 is a full reset) //
// //
// If the block needs to transition to PM state PPM L2/3, we need to finish //
// up what we're doing and throttle when the user gives permission. //
//----------------------------------------------------------------------------//
generate
// PPM L2/3 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp
assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp
assign ppm_L23_trig = cfg_pm_send_pme_to;
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals in EP mode
else begin : L23_thrtl_ep
assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;
// PPM L2/3 signals for 7 Series in EP mode
// For 7 Series, cfg_to_turnoff pulses once when a turnoff request is
// outstanding, so we need a "sticky" register that grabs the request.
if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep
reg reg_to_turnoff;
always @(posedge user_clk) begin
if(user_rst) begin
reg_to_turnoff <= #TCQ 1'b0;
end
else begin
if(cfg_to_turnoff) begin
reg_to_turnoff <= #TCQ 1'b1;
end
end
end
assign wire_to_turnoff = reg_to_turnoff;
end
// PPM L2/3 signals for V6/S6 in EP mode
// In V6 and S6, the to_turnoff signal asserts and remains asserted until
// turnoff_ok is asserted, so a sticky reg is not necessary.
else begin : v6_s6_L23_thrtl_ep
assign wire_to_turnoff = cfg_to_turnoff;
end
always @(posedge user_clk) begin
if(user_rst) begin
reg_turnoff_ok <= #TCQ 1'b0;
end
else begin
reg_turnoff_ok <= #TCQ user_turnoff_ok;
end
end
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L23_thrtl <= #TCQ 1'b0;
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
else begin
if(ppm_L23_trig) begin
ppm_L23_thrtl <= #TCQ 1'b1;
end
// Make sure cfg_turnoff_ok pulses once for one clock cycle for every
// turnoff request.
if(ppm_L23_trig && !ppm_L23_thrtl) begin
cfg_turnoff_ok_pending <= #TCQ 1'b1;
end
else if(cfg_turnoff_ok) begin
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_thrtl_ok. This signal determines if it's OK to throttle the //
// user design on the AXI interface. Since TREADY is registered, this signal //
// needs to assert on the cycle ~before~ we actually intend to throttle. //
// The only time it's OK to throttle when TVALID is asserted is on the first //
// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the //
// is true: //
// 1) The user is not in a packet and is not starting one //
// 2) The user is just finishing a packet //
// 3) We're already throttled, so it's OK to continue throttling //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else begin
if(s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else if(tready_thrtl && s_axis_tx_tvalid) begin
reg_axi_in_pkt <= #TCQ 1'b1;
end
end
end
assign axi_in_pkt = s_axis_tx_tvalid || reg_axi_in_pkt;
assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;
assign axi_throttled = !tready_thrtl;
assign axi_thrtl_ok = !axi_in_pkt || axi_pkt_ending || axi_throttled;
//----------------------------------------------------------------------------//
// Throttle CTL State Machine: //
// Throttle user design when a throttle trigger (or triggers) occur. //
// Keep user throttled until all exit criteria have been met. //
//----------------------------------------------------------------------------//
// Immediate throttle signal. Used to "pounce" on a throttle opportunity when
// we're seeking one
assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig
|| tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;
// Registered throttle signals. Used to control throttle state machine
assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl
|| tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;
assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl
&& !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;
always @(*) begin
case(cur_state)
// IDLE: in this state we're waiting for a trigger event to occur. As
// soon as an event occurs and the user isn't transmitting a packet, we
// throttle the PCIe block and the user and next state is THROTTLE.
IDLE: begin
if(reg_throttle && axi_thrtl_ok) begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(ppm_L23_thrtl) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
// If there's not throttle event, do nothing
else begin
// Throttle user as soon as possible
tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
end
// THROTTLE: in this state the user is throttle and we're waiting for
// exit criteria, which tells us that the throttle event is over. When
// the exit criteria is satisfied, de-throttle the user and next state
// is IDLE.
THROTTLE: begin
if(exit_crit) begin
// Dethrottle user
tready_thrtl_mux = !pre_throttle;
next_state = IDLE;
end
else begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
end
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl && tcfg_gnt_pending) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(cfg_turnoff_ok_pending) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
default: begin
tready_thrtl_mux = 1'b0;
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
endcase
end
// Synchronous logic
always @(posedge user_clk) begin
if(user_rst) begin
// Throttle user by default until link comes up
cur_state <= #TCQ THROTTLE;
reg_tlast <= #TCQ 1'b0;
tready_thrtl <= #TCQ 1'b0;
end
else begin
cur_state <= #TCQ next_state;
tready_thrtl <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;
reg_tlast <= #TCQ s_axis_tx_tlast;
end
end
// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen
// is asserted at SOF. In this case, the Block needs an extra data beat to
// calculate the ECRC, but only if the following conditions are met:
// 1) there is no empty DWORDS at the end of the packet
// (i.e. packet length % C_DATA_WIDTH == 0)
//
// 2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the
// TLP header
//
// If both conditions are met, the Block will stall the TRN interface for one
// data beat after EOF. We need to predict this stall and preemptively stall the
// User for one beat.
generate
if(C_FAMILY == "X7") begin : ecrc_pause_enabled
wire tx_ecrc_pkt;
reg reg_tx_ecrc_pkt;
wire [1:0] packet_fmt;
wire packet_td;
wire [2:0] header_len;
wire [9:0] payload_len;
wire [13:0] packet_len;
wire pause_needed;
// Grab necessary packet fields
assign packet_fmt = s_axis_tx_tdata[30:29];
assign packet_td = s_axis_tx_tdata[15];
// Calculate total packet length
assign header_len = packet_fmt[0] ? 3'd4 : 3'd3;
assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;
assign packet_len = {10'h000, header_len} + {4'h0, payload_len};
// Determine if packet a ECRC pause is needed
if(C_DATA_WIDTH == 128) begin : packet_len_check_128
assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;
end
else begin : packet_len_check_64
assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;
end
// Create flag to alert TX pipeline to insert a stall
assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&
tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;
always @(posedge user_clk) begin
if(user_rst) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
else begin
if(tx_ecrc_pkt && !s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b1;
end
else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
end
end
// Insert the stall now
assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&
s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);
end
else begin : ecrc_pause_disabled
assign tx_ecrc_pause = 1'b0;
end
endgenerate
// Logic for 128-bit single cycle bug fix.
// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a
// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt
// from AXI Basic causes the packet to be dropped. The packet drop occurs
// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor
// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle
// prediction just as we do, it ignores the value of trn_tdst_rdy, and
// ultimately drops the packet when transmitting the packet to the block.
generate
if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline
genvar stage;
reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];
// Create a configurable depth FF delay pipeline
for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)
begin : tcfg_gnt_pipeline_stage
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_gnt_pipe[stage] <= #TCQ 1'b0;
end
else begin
// For stage 0, insert the actual tcfg_gnt signal from logic
if(stage == 0) begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;
end
// For stages 1+, chain together
else begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];
end
end
end
// tcfg_gnt output to block assigned the last pipeline stage
assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];
end
end
else begin : tcfg_gnt_no_pipeline
// For all other architectures, no pipeline delay needed for tcfg_gnt
assign trn_tcfg_gnt = tcfg_gnt_log;
end
endgenerate
endmodule
|
/*
zybo_top.v -- Top level entity for ION demo on Zybo board.
As of right now this does not actually work. All I want for the time being
is to make sure I can synthesize the demo entity without the whole thing
being optimized away.
So all I do here is connect the MCU module to the very few I/O available on
the board.
In other wordS: SYNTHESIS DUMMY -- DOES NOT WORK!
*/
module zybo_top
(
// Main clock. See @note1.
input CLK_125MHZ_I,
// Various I/O ports connected to board devices.
input [3:0] BUTTONS_I,
input [3:0] SWITCHES_I,
output reg [3:0] LEDS_O,
// PMOD E (Std) connector -- PMOD UART (Digilent).
output reg PMOD_E_2_TXD_O,
input PMOD_E_3_RXD_I
);
//==== MCU instantiation ===================================================
reg [31:0] bogoinput;
wire [31:0] dbg_out;
reg [31:0] dbg_in;
reg reset;
mcu # (
// Size of Code TCM in 32-bit words.
.OPTION_CTCM_NUM_WORDS(1024)
)
mcu (
.CLK (CLK_125MHZ_I),
.RESET_I (reset),
.DEBUG_I (dbg_in),
.DEBUG_O (dbg_out)
);
// Bogus logic to keep all MCU outputs relevant.
always @(*) begin
LEDS_O =
dbg_out[31:28] ^ dbg_out[27:24] ^ dbg_out[23:20] ^ dbg_out[19:16] ^
dbg_out[15:12] ^ dbg_out[11: 8] ^ dbg_out[ 7: 4] ^ dbg_out[ 3: 0];
reset = |BUTTONS_I;
PMOD_E_2_TXD_O = PMOD_E_3_RXD_I;
end
// Bogus logic to keep all MCU inputs relevant.
always @(posedge CLK_125MHZ_I) begin
if (reset) begin // TODO Async input used as sync reset...
bogoinput <= 32'h0;
dbg_in <= 32'h0;
end
else begin
bogoinput <= {8{SWITCHES_I}};
dbg_in <= dbg_out + bogoinput;
end
end
endmodule
// @note1: Clock active if PHYRSTB is high. PHYRSTB pin unused, pulled high.
|
module microfono_TB;
reg reset, clk;
reg micData, enable;
microfono uut(.reset(reset),.micData(micData),.clk(clk),.enable(enable));
always
begin
clk =1'b1;
#2;
clk=1'b0;
#2;
end
initial
begin
enable=1'b0;
#10000;
enable =1'b1;
end
initial
begin
reset =1'b1;
#10000;
reset =1'b0;
end
/*initial
begin
rd = 1'b0;
wr = 1'b0;
#10000 wr = 1'b1;
#150000 wr = 1'b0;
#15010 rd = 1'b1;
end
*/
initial begin
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
end
initial begin: TEST_CASE
$dumpfile("microfono_TB.vcd");
$dumpvars(-1, uut);
#(1000000) $finish;
end
endmodule //
|
// nios_system_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 189
`timescale 1 ps / 1 ps
module nios_system_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_system_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR2B_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2b (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NAND4_FUNCTIONAL_PP_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4_FUNCTIONAL_PP_V
|
/*
* verilog model of 6502 CPU.
*
* (C) Arlet Ottens, <[email protected]>
*
* Feel free to use this code in any project (commercial or not), as long as you
* keep this message, and the copyright notice. This code is provided "as is",
* without any warranties of any kind.
*
*/
/*
* Note that not all 6502 interface signals are supported (yet). The goal
* is to create an Acorn Atom model, and the Atom didn't use all signals on
* the main board.
*
* The data bus is implemented as separate read/write buses. Combine them
* on the output pads if external memory is required.
*/
`timescale 1ns / 1ps
`include "atari7800.vh"
module cpu( clk, reset, AB, DI, DO, WE, IRQ, NMI, RDY );
input clk; // CPU clock
input reset; // reset signal
output reg [15:0] AB; // address bus
input [7:0] DI; // data in, read bus
output [7:0] DO; // data out, write bus
output WE; // write enable
input IRQ; // interrupt request
input NMI; // non-maskable interrupt request
input RDY; // Ready signal. Pauses CPU when RDY=0
/*
* internal signals
*/
reg [15:0] PC; // Program Counter
reg [7:0] ABL; // Address Bus Register LSB
reg [7:0] ABH; // Address Bus Register MSB
wire [7:0] ADD; // Adder Hold Register (registered in ALU)
reg [7:0] DIHOLD; // Hold for Data In
reg DIHOLD_valid; //
wire [7:0] DIMUX; //
reg [7:0] IRHOLD; // Hold for Instruction register
reg IRHOLD_valid; // Valid instruction in IRHOLD
reg [7:0] AXYS[3:0]; // A, X, Y and S register file
reg C = 0; // carry flag (init at zero to avoid X's in ALU sim)
reg Z = 0; // zero flag
reg I = 0; // interrupt flag
reg D = 0; // decimal flag
reg V = 0; // overflow flag
reg N = 0; // negative flag
wire AZ; // ALU Zero flag
wire AV; // ALU overflow flag
wire AN; // ALU negative flag
wire HC; // ALU half carry
reg [7:0] AI; // ALU Input A
reg [7:0] BI; // ALU Input B
wire [7:0] DI; // Data In
wire [7:0] IR; // Instruction register
reg [7:0] DO; // Data Out
reg WE; // Write Enable
reg CI; // Carry In
wire CO; // Carry Out
wire [7:0] PCH = PC[15:8];
wire [7:0] PCL = PC[7:0];
reg NMI_edge = 0; // captured NMI edge
reg [1:0] regsel; // Select A, X, Y or S register
wire [7:0] regfile = AXYS[regsel]; // Selected register output
parameter
SEL_A = 2'd0,
SEL_S = 2'd1,
SEL_X = 2'd2,
SEL_Y = 2'd3;
/*
* define some signals for watching in simulator output
*/
`ifdef SIM
wire [7:0] A = AXYS[SEL_A]; // Accumulator
wire [7:0] X = AXYS[SEL_X]; // X register
wire [7:0] Y = AXYS[SEL_Y]; // Y register
wire [7:0] S = AXYS[SEL_S]; // Stack pointer
`endif
wire [7:0] P = { N, V, 2'b11, D, I, Z, C };
/*
* instruction decoder/sequencer
*/
reg [5:0] state;
/*
* control signals
*/
reg PC_inc; // Increment PC
reg [15:0] PC_temp; // intermediate value of PC
reg [1:0] src_reg; // source register index
reg [1:0] dst_reg; // destination register index
reg index_y; // if set, then Y is index reg rather than X
reg load_reg; // loading a register (A, X, Y, S) in this instruction
reg inc; // increment
reg write_back; // set if memory is read/modified/written
reg load_only; // LDA/LDX/LDY instruction
reg store; // doing store (STA/STX/STY)
reg adc_sbc; // doing ADC/SBC
reg compare; // doing CMP/CPY/CPX
reg shift; // doing shift/rotate instruction
reg rotate; // doing rotate (no shift)
reg backwards; // backwards branch
reg cond_true; // branch condition is true
reg [2:0] cond_code; // condition code bits from instruction
reg shift_right; // Instruction ALU shift/rotate right
reg alu_shift_right; // Current cycle shift right enable
reg [3:0] op; // Main ALU operation for instruction
reg [3:0] alu_op; // Current cycle ALU operation
reg adc_bcd; // ALU should do BCD style carry
reg adj_bcd; // results should be BCD adjusted
/*
* some flip flops to remember we're doing special instructions. These
* get loaded at the DECODE state, and used later
*/
reg bit_ins; // doing BIT instruction
reg plp; // doing PLP instruction
reg php; // doing PHP instruction
reg clc; // clear carry
reg sec; // set carry
reg cld; // clear decimal
reg sed; // set decimal
reg cli; // clear interrupt
reg sei; // set interrupt
reg clv; // clear overflow
reg brk; // doing BRK
reg res; // in reset
/*
* ALU operations
*/
parameter
OP_OR = 4'b1100,
OP_AND = 4'b1101,
OP_EOR = 4'b1110,
OP_ADD = 4'b0011,
OP_SUB = 4'b0111,
OP_ROL = 4'b1011,
OP_A = 4'b1111;
/*
* Microcode state machine. Basically, every addressing mode has its own
* path through the state machine. Additional information, such as the
* operation, source and destination registers are decoded in parallel, and
* kept in separate flops.
*/
parameter
ABS0 = 6'd0, // ABS - fetch LSB
ABS1 = 6'd1, // ABS - fetch MSB
ABSX0 = 6'd2, // ABS, X - fetch LSB and send to ALU (+X)
ABSX1 = 6'd3, // ABS, X - fetch MSB and send to ALU (+Carry)
ABSX2 = 6'd4, // ABS, X - Wait for ALU (only if needed)
BRA0 = 6'd5, // Branch - fetch offset and send to ALU (+PC[7:0])
BRA1 = 6'd6, // Branch - fetch opcode, and send PC[15:8] to ALU
BRA2 = 6'd7, // Branch - fetch opcode (if page boundary crossed)
BRK0 = 6'd8, // BRK/IRQ - push PCH, send S to ALU (-1)
BRK1 = 6'd9, // BRK/IRQ - push PCL, send S to ALU (-1)
BRK2 = 6'd10, // BRK/IRQ - push P, send S to ALU (-1)
BRK3 = 6'd11, // BRK/IRQ - write S, and fetch @ fffe
DECODE = 6'd12, // IR is valid, decode instruction, and write prev reg
FETCH = 6'd13, // fetch next opcode, and perform prev ALU op
INDX0 = 6'd14, // (ZP,X) - fetch ZP address, and send to ALU (+X)
INDX1 = 6'd15, // (ZP,X) - fetch LSB at ZP+X, calculate ZP+X+1
INDX2 = 6'd16, // (ZP,X) - fetch MSB at ZP+X+1
INDX3 = 6'd17, // (ZP,X) - fetch data
INDY0 = 6'd18, // (ZP),Y - fetch ZP address, and send ZP to ALU (+1)
INDY1 = 6'd19, // (ZP),Y - fetch at ZP+1, and send LSB to ALU (+Y)
INDY2 = 6'd20, // (ZP),Y - fetch data, and send MSB to ALU (+Carry)
INDY3 = 6'd21, // (ZP),Y) - fetch data (if page boundary crossed)
JMP0 = 6'd22, // JMP - fetch PCL and hold
JMP1 = 6'd23, // JMP - fetch PCH
JMPI0 = 6'd24, // JMP IND - fetch LSB and send to ALU for delay (+0)
JMPI1 = 6'd25, // JMP IND - fetch MSB, proceed with JMP0 state
JSR0 = 6'd26, // JSR - push PCH, save LSB, send S to ALU (-1)
JSR1 = 6'd27, // JSR - push PCL, send S to ALU (-1)
JSR2 = 6'd28, // JSR - write S
JSR3 = 6'd29, // JSR - fetch MSB
PULL0 = 6'd30, // PLP/PLA - save next op in IRHOLD, send S to ALU (+1)
PULL1 = 6'd31, // PLP/PLA - fetch data from stack, write S
PULL2 = 6'd32, // PLP/PLA - prefetch op, but don't increment PC
PUSH0 = 6'd33, // PHP/PHA - send A to ALU (+0)
PUSH1 = 6'd34, // PHP/PHA - write A/P, send S to ALU (-1)
READ = 6'd35, // Read memory for read/modify/write (INC, DEC, shift)
REG = 6'd36, // Read register for reg-reg transfers
RTI0 = 6'd37, // RTI - send S to ALU (+1)
RTI1 = 6'd38, // RTI - read P from stack
RTI2 = 6'd39, // RTI - read PCL from stack
RTI3 = 6'd40, // RTI - read PCH from stack
RTI4 = 6'd41, // RTI - read PCH from stack
RTS0 = 6'd42, // RTS - send S to ALU (+1)
RTS1 = 6'd43, // RTS - read PCL from stack
RTS2 = 6'd44, // RTS - write PCL to ALU, read PCH
RTS3 = 6'd45, // RTS - load PC and increment
WRITE = 6'd46, // Write memory for read/modify/write
ZP0 = 6'd47, // Z-page - fetch ZP address
ZPX0 = 6'd48, // ZP, X - fetch ZP, and send to ALU (+X)
ZPX1 = 6'd49; // ZP, X - load from memory
`ifdef SIM
/*
* easy to read names in simulator output
*/
reg [8*6-1:0] statename;
always @*
case( state )
DECODE: statename = "DECODE";
REG: statename = "REG";
ZP0: statename = "ZP0";
ZPX0: statename = "ZPX0";
ZPX1: statename = "ZPX1";
ABS0: statename = "ABS0";
ABS1: statename = "ABS1";
ABSX0: statename = "ABSX0";
ABSX1: statename = "ABSX1";
ABSX2: statename = "ABSX2";
INDX0: statename = "INDX0";
INDX1: statename = "INDX1";
INDX2: statename = "INDX2";
INDX3: statename = "INDX3";
INDY0: statename = "INDY0";
INDY1: statename = "INDY1";
INDY2: statename = "INDY2";
INDY3: statename = "INDY3";
READ: statename = "READ";
WRITE: statename = "WRITE";
FETCH: statename = "FETCH";
PUSH0: statename = "PUSH0";
PUSH1: statename = "PUSH1";
PULL0: statename = "PULL0";
PULL1: statename = "PULL1";
PULL2: statename = "PULL2";
JSR0: statename = "JSR0";
JSR1: statename = "JSR1";
JSR2: statename = "JSR2";
JSR3: statename = "JSR3";
RTI0: statename = "RTI0";
RTI1: statename = "RTI1";
RTI2: statename = "RTI2";
RTI3: statename = "RTI3";
RTI4: statename = "RTI4";
RTS0: statename = "RTS0";
RTS1: statename = "RTS1";
RTS2: statename = "RTS2";
RTS3: statename = "RTS3";
BRK0: statename = "BRK0";
BRK1: statename = "BRK1";
BRK2: statename = "BRK2";
BRK3: statename = "BRK3";
BRA0: statename = "BRA0";
BRA1: statename = "BRA1";
BRA2: statename = "BRA2";
JMP0: statename = "JMP0";
JMP1: statename = "JMP1";
JMPI0: statename = "JMPI0";
JMPI1: statename = "JMPI1";
endcase
//always @( PC )
// $display( "%t, PC:%04x IR:%02x A:%02x X:%02x Y:%02x S:%02x C:%d Z:%d V:%d N:%d P:%02x", $time, PC, IR, A, X, Y, S, C, Z, V, N, P );
`endif
/*
* Program Counter Increment/Load. First calculate the base value in
* PC_temp.
*/
always @*
case( state )
DECODE: if( (~I & IRQ) | NMI_edge )
PC_temp = { ABH, ABL };
else
PC_temp = PC;
JMP1,
JMPI1,
JSR3,
RTS3,
RTI4: PC_temp = { DIMUX, ADD };
BRA1: PC_temp = { ABH, ADD };
BRA2: PC_temp = { ADD, PCL };
BRK2: PC_temp = res ? 16'hfffc :
NMI_edge ? 16'hfffa : 16'hfffe;
default: PC_temp = PC;
endcase
/*
* Determine wether we need PC_temp, or PC_temp + 1
*/
always @*
case( state )
DECODE: if( (~I & IRQ) | NMI_edge )
PC_inc = 0;
else
PC_inc = 1;
ABS0,
ABSX0,
FETCH,
BRA0,
BRA2,
BRK3,
JMPI1,
JMP1,
RTI4,
RTS3: PC_inc = 1;
BRA1: PC_inc = CO ^~ backwards;
default: PC_inc = 0;
endcase
/*
* Set new PC
*/
always @(posedge clk)
if( RDY )
PC <= PC_temp + PC_inc;
/*
* Address Generator
*/
parameter
ZEROPAGE = 8'h00,
STACKPAGE = 8'h01;
always @*
case( state )
ABSX1,
INDX3,
INDY2,
JMP1,
JMPI1,
RTI4,
ABS1: AB = { DIMUX, ADD };
BRA2,
INDY3,
ABSX2: AB = { ADD, ABL };
BRA1: AB = { ABH, ADD };
JSR0,
PUSH1,
RTS0,
RTI0,
BRK0: AB = { STACKPAGE, regfile };
BRK1,
JSR1,
PULL1,
RTS1,
RTS2,
RTI1,
RTI2,
RTI3,
BRK2: AB = { STACKPAGE, ADD };
INDY1,
INDX1,
ZPX1,
INDX2: AB = { ZEROPAGE, ADD };
ZP0,
INDY0: AB = { ZEROPAGE, DIMUX };
REG,
READ,
WRITE: AB = { ABH, ABL };
default: AB = PC;
endcase
/*
* ABH/ABL pair is used for registering previous address bus state.
* This can be used to keep the current address, freeing up the original
* source of the address, such as the ALU or DI.
*/
always @(posedge clk)
if( state != PUSH0 && state != PUSH1 && RDY &&
state != PULL0 && state != PULL1 && state != PULL2 )
begin
ABL <= AB[7:0];
ABH <= AB[15:8];
end
/*
* Data Out MUX
*/
always @*
case( state )
WRITE: DO = ADD;
JSR0,
BRK0: DO = PCH;
JSR1,
BRK1: DO = PCL;
PUSH1: DO = php ? P : ADD;
BRK2: DO = (IRQ | NMI_edge) ? (P & 8'b1110_1111) : P;
default: DO = regfile;
endcase
/*
* Write Enable Generator
*/
always @*
case( state )
BRK0, // writing to stack or memory
BRK1,
BRK2,
JSR0,
JSR1,
PUSH1,
WRITE: WE = 1;
INDX3, // only if doing a STA, STX or STY
INDY3,
ABSX2,
ABS1,
ZPX1,
ZP0: WE = store;
default: WE = 0;
endcase
/*
* register file, contains A, X, Y and S (stack pointer) registers. At each
* cycle only 1 of those registers needs to be accessed, so they combined
* in a small memory, saving resources.
*/
reg write_register; // set when register file is written
always @*
case( state )
DECODE: write_register = load_reg & ~plp;
PULL1,
RTS2,
RTI3,
BRK3,
JSR0,
JSR2 : write_register = 1;
default: write_register = 0;
endcase
/*
* BCD adjust logic
*/
always @(posedge clk)
adj_bcd <= adc_sbc & D; // '1' when doing a BCD instruction
reg [3:0] ADJL;
reg [3:0] ADJH;
// adjustment term to be added to ADD[3:0] based on the following
// adj_bcd: '1' if doing ADC/SBC with D=1
// adc_bcd: '1' if doing ADC with D=1
// HC : half carry bit from ALU
always @* begin
casex( {adj_bcd, adc_bcd, HC} )
3'b0xx: ADJL = 4'd0; // no BCD instruction
3'b100: ADJL = 4'd10; // SBC, and digital borrow
3'b101: ADJL = 4'd0; // SBC, but no borrow
3'b110: ADJL = 4'd0; // ADC, but no carry
3'b111: ADJL = 4'd6; // ADC, and decimal/digital carry
endcase
end
// adjustment term to be added to ADD[7:4] based on the following
// adj_bcd: '1' if doing ADC/SBC with D=1
// adc_bcd: '1' if doing ADC with D=1
// CO : carry out bit from ALU
always @* begin
casex( {adj_bcd, adc_bcd, CO} )
3'b0xx: ADJH = 4'd0; // no BCD instruction
3'b100: ADJH = 4'd10; // SBC, and digital borrow
3'b101: ADJH = 4'd0; // SBC, but no borrow
3'b110: ADJH = 4'd0; // ADC, but no carry
3'b111: ADJH = 4'd6; // ADC, and decimal/digital carry
endcase
end
/*
* write to a register. Usually this is the (BCD corrected) output of the
* ALU, but in case of the JSR0 we use the S register to temporarily store
* the PCL. This is possible, because the S register itself is stored in
* the ALU during those cycles.
*/
always @(posedge clk)
if( write_register & RDY )
AXYS[regsel] <= (state == JSR0) ? DIMUX : { ADD[7:4] + ADJH, ADD[3:0] + ADJL };
/*
* register select logic. This determines which of the A, X, Y or
* S registers will be accessed.
*/
always @*
case( state )
INDY1,
INDX0,
ZPX0,
ABSX0 : regsel = index_y ? SEL_Y : SEL_X;
DECODE : regsel = dst_reg;
BRK0,
BRK3,
JSR0,
JSR2,
PULL0,
PULL1,
PUSH1,
RTI0,
RTI3,
RTS0,
RTS2 : regsel = SEL_S;
default: regsel = src_reg;
endcase
/*
* ALU
*/
ALU ALU( .clk(clk),
.op(alu_op),
.right(alu_shift_right),
.AI(AI),
.BI(BI),
.CI(CI),
.BCD(adc_bcd & (state == FETCH)),
.CO(CO),
.OUT(ADD),
.V(AV),
.Z(AZ),
.N(AN),
.HC(HC),
.RDY(RDY) );
/*
* Select current ALU operation
*/
always @*
case( state )
READ: alu_op = op;
BRA1: alu_op = backwards ? OP_SUB : OP_ADD;
FETCH,
REG : alu_op = op;
DECODE,
ABS1: alu_op = 1'bx;
PUSH1,
BRK0,
BRK1,
BRK2,
JSR0,
JSR1: alu_op = OP_SUB;
default: alu_op = OP_ADD;
endcase
/*
* Determine shift right signal to ALU
*/
always @*
if( state == FETCH || state == REG || state == READ )
alu_shift_right = shift_right;
else
alu_shift_right = 0;
/*
* Sign extend branch offset.
*/
always @(posedge clk)
if( RDY )
backwards <= DIMUX[7];
/*
* ALU A Input MUX
*/
always @*
case( state )
JSR1,
RTS1,
RTI1,
RTI2,
BRK1,
BRK2,
INDX1: AI = ADD;
REG,
ZPX0,
INDX0,
ABSX0,
RTI0,
RTS0,
JSR0,
JSR2,
BRK0,
PULL0,
INDY1,
PUSH0,
PUSH1: AI = regfile;
BRA0,
READ: AI = DIMUX;
BRA1: AI = ABH; // don't use PCH in case we're
FETCH: AI = load_only ? 0 : regfile;
DECODE,
ABS1: AI = 8'hxx; // don't care
default: AI = 0;
endcase
/*
* ALU B Input mux
*/
always @*
case( state )
BRA1,
RTS1,
RTI0,
RTI1,
RTI2,
INDX1,
READ,
REG,
JSR0,
JSR1,
JSR2,
BRK0,
BRK1,
BRK2,
PUSH0,
PUSH1,
PULL0,
RTS0: BI = 8'h00;
BRA0: BI = PCL;
DECODE,
ABS1: BI = 8'hxx;
default: BI = DIMUX;
endcase
/*
* ALU CI (carry in) mux
*/
always @*
case( state )
INDY2,
BRA1,
ABSX1: CI = CO;
DECODE,
ABS1: CI = 1'bx;
READ,
REG: CI = rotate ? C :
shift ? 0 : inc;
FETCH: CI = rotate ? C :
compare ? 1 :
(shift | load_only) ? 0 : C;
PULL0,
RTI0,
RTI1,
RTI2,
RTS0,
RTS1,
INDY0,
INDX1: CI = 1;
default: CI = 0;
endcase
/*
* Processor Status Register update
*
*/
/*
* Update C flag when doing ADC/SBC, shift/rotate, compare
*/
always @(posedge clk )
if( shift && state == WRITE )
C <= CO;
else if( state == RTI2 )
C <= DIMUX[0];
else if( ~write_back && state == DECODE ) begin
if( adc_sbc | shift | compare )
C <= CO;
else if( plp )
C <= ADD[0];
else begin
if( sec ) C <= 1;
if( clc ) C <= 0;
end
end
/*
* Update Z, N flags when writing A, X, Y, Memory, or when doing compare
*/
always @(posedge clk)
if( state == WRITE )
Z <= AZ;
else if( state == RTI2 )
Z <= DIMUX[1];
else if( state == DECODE ) begin
if( plp )
Z <= ADD[1];
else if( (load_reg & (regsel != SEL_S)) | compare | bit_ins )
Z <= AZ;
end
always @(posedge clk)
if( state == WRITE )
N <= AN;
else if( state == RTI2 )
N <= DIMUX[7];
else if( state == DECODE ) begin
if( plp )
N <= ADD[7];
else if( (load_reg & (regsel != SEL_S)) | compare )
N <= AN;
end else if( state == FETCH && bit_ins )
N <= DIMUX[7];
/*
* Update I flag
*/
always @(posedge clk)
if( state == BRK3 )
I <= 1;
else if( state == RTI2 )
I <= DIMUX[2];
else if( state == REG ) begin
if( sei ) I <= 1;
if( cli ) I <= 0;
end else if( state == DECODE )
if( plp ) I <= ADD[2];
/*
* Update D flag
*/
always @(posedge clk )
if( state == RTI2 )
D <= DIMUX[3];
else if( state == DECODE ) begin
if( sed ) D <= 1;
if( cld ) D <= 0;
if( plp ) D <= ADD[3];
end
/*
* Update V flag
*/
always @(posedge clk )
if( state == RTI2 )
V <= DIMUX[6];
else if( state == DECODE ) begin
if( adc_sbc ) V <= AV;
if( clv ) V <= 0;
if( plp ) V <= ADD[6];
end else if( state == FETCH && bit_ins )
V <= DIMUX[6];
/*
* Instruction decoder
*/
/*
* IR register/mux. Hold previous DI value in IRHOLD in PULL0 and PUSH0
* states. In these states, the IR has been prefetched, and there is no
* time to read the IR again before the next decode.
*/
reg RDY1 = 1;
always @(posedge clk )
RDY1 <= RDY;
always @(posedge clk )
if( ~RDY && RDY1 )
DIHOLD <= DI;
always @(posedge clk )
if( reset )
IRHOLD_valid <= 0;
else if( RDY ) begin
if( state == PULL0 || state == PUSH0 ) begin
IRHOLD <= DIMUX;
IRHOLD_valid <= 1;
end else if( state == DECODE )
IRHOLD_valid <= 0;
end
assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 :
IRHOLD_valid ? IRHOLD : DIMUX;
assign DIMUX = ~RDY1 ? DIHOLD : DI;
/*
* Microcode state machine
*/
always @(posedge clk or posedge reset)
if( reset )
state <= BRK0;
else if( RDY ) case( state )
DECODE :
casex ( IR )
8'b0000_0000: state <= BRK0;
8'b0010_0000: state <= JSR0;
8'b0010_1100: state <= ABS0; // BIT abs
8'b0100_0000: state <= RTI0; //
8'b0100_1100: state <= JMP0;
8'b0110_0000: state <= RTS0;
8'b0110_1100: state <= JMPI0;
8'b0x00_1000: state <= PUSH0;
8'b0x10_1000: state <= PULL0;
8'b0xx1_1000: state <= REG; // CLC, SEC, CLI, SEI
8'b1xx0_00x0: state <= FETCH; // IMM
8'b1xx0_1100: state <= ABS0; // X/Y abs
8'b1xxx_1000: state <= REG; // DEY, TYA, ...
8'bxxx0_0001: state <= INDX0;
8'bxxx0_01xx: state <= ZP0;
8'bxxx0_1001: state <= FETCH; // IMM
8'bxxx0_1101: state <= ABS0; // even E column
8'bxxx0_1110: state <= ABS0; // even E column
8'bxxx1_0000: state <= BRA0; // odd 0 column
8'bxxx1_0001: state <= INDY0; // odd 1 column
8'bxxx1_01xx: state <= ZPX0; // odd 4,5,6,7 columns
8'bxxx1_1001: state <= ABSX0; // odd 9 column
8'bxxx1_11xx: state <= ABSX0; // odd C, D, E, F columns
8'bxxxx_1010: state <= REG; // <shift> A, TXA, ... NOP
endcase
ZP0 : state <= write_back ? READ : FETCH;
ZPX0 : state <= ZPX1;
ZPX1 : state <= write_back ? READ : FETCH;
ABS0 : state <= ABS1;
ABS1 : state <= write_back ? READ : FETCH;
ABSX0 : state <= ABSX1;
ABSX1 : state <= (CO | store | write_back) ? ABSX2 : FETCH;
ABSX2 : state <= write_back ? READ : FETCH;
INDX0 : state <= INDX1;
INDX1 : state <= INDX2;
INDX2 : state <= INDX3;
INDX3 : state <= FETCH;
INDY0 : state <= INDY1;
INDY1 : state <= INDY2;
INDY2 : state <= (CO | store) ? INDY3 : FETCH;
INDY3 : state <= FETCH;
READ : state <= WRITE;
WRITE : state <= FETCH;
FETCH : state <= DECODE;
REG : state <= DECODE;
PUSH0 : state <= PUSH1;
PUSH1 : state <= DECODE;
PULL0 : state <= PULL1;
PULL1 : state <= PULL2;
PULL2 : state <= DECODE;
JSR0 : state <= JSR1;
JSR1 : state <= JSR2;
JSR2 : state <= JSR3;
JSR3 : state <= FETCH;
RTI0 : state <= RTI1;
RTI1 : state <= RTI2;
RTI2 : state <= RTI3;
RTI3 : state <= RTI4;
RTI4 : state <= DECODE;
RTS0 : state <= RTS1;
RTS1 : state <= RTS2;
RTS2 : state <= RTS3;
RTS3 : state <= FETCH;
BRA0 : state <= cond_true ? BRA1 : DECODE;
BRA1 : state <= (CO ^ backwards) ? BRA2 : DECODE;
BRA2 : state <= DECODE;
JMP0 : state <= JMP1;
JMP1 : state <= DECODE;
JMPI0 : state <= JMPI1;
JMPI1 : state <= JMP0;
BRK0 : state <= BRK1;
BRK1 : state <= BRK2;
BRK2 : state <= BRK3;
BRK3 : state <= JMP0;
endcase
/*
* Additional control signals
*/
always @(posedge clk)
if( reset )
res <= 1;
else if( state == DECODE )
res <= 0;
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b0xx01010, // ASLA, ROLA, LSRA, RORA
8'b0xxxxx01, // ORA, AND, EOR, ADC
8'b100x10x0, // DEY, TYA, TXA, TXS
8'b1010xxx0, // LDA/LDX/LDY
8'b10111010, // TSX
8'b1011x1x0, // LDX/LDY
8'b11001010, // DEX
8'b1x1xxx01, // LDA, SBC
8'bxxx01000: // DEY, TAY, INY, INX
load_reg <= 1;
default: load_reg <= 0;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b1110_1000, // INX
8'b1100_1010, // DEX
8'b101x_xx10: // LDX, TAX, TSX
dst_reg <= SEL_X;
8'b0x00_1000, // PHP, PHA
8'b1001_1010: // TXS
dst_reg <= SEL_S;
8'b1x00_1000, // DEY, DEX
8'b101x_x100, // LDY
8'b1010_x000: // LDY #imm, TAY
dst_reg <= SEL_Y;
default: dst_reg <= SEL_A;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b1011_1010: // TSX
src_reg <= SEL_S;
8'b100x_x110, // STX
8'b100x_1x10, // TXA, TXS
8'b1110_xx00, // INX, CPX
8'b1100_1010: // DEX
src_reg <= SEL_X;
8'b100x_x100, // STY
8'b1001_1000, // TYA
8'b1100_xx00, // CPY
8'b1x00_1000: // DEY, INY
src_reg <= SEL_Y;
default: src_reg <= SEL_A;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'bxxx1_0001, // INDY
8'b10x1_x110, // LDX/STX zpg/abs, Y
8'bxxxx_1001: // abs, Y
index_y <= 1;
default: index_y <= 0;
endcase
always @(posedge clk)
if( state == DECODE && RDY )
casex( IR )
8'b100x_x1x0, // STX, STY
8'b100x_xx01: // STA
store <= 1;
default: store <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0xxx_x110, // ASL, ROL, LSR, ROR
8'b11xx_x110: // DEC/INC
write_back <= 1;
default: write_back <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b101x_xxxx: // LDA, LDX, LDY
load_only <= 1;
default: load_only <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b111x_x110, // INC
8'b11x0_1000: // INX, INY
inc <= 1;
default: inc <= 0;
endcase
always @(posedge clk )
if( (state == DECODE || state == BRK0) && RDY )
casex( IR )
8'bx11x_xx01: // SBC, ADC
adc_sbc <= 1;
default: adc_sbc <= 0;
endcase
always @(posedge clk )
if( (state == DECODE || state == BRK0) && RDY )
casex( IR )
8'b011x_xx01: // ADC
adc_bcd <= D;
default: adc_bcd <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0xxx_x110, // ASL, ROL, LSR, ROR (abs, absx, zpg, zpgx)
8'b0xxx_1010: // ASL, ROL, LSR, ROR (acc)
shift <= 1;
default: shift <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b11x0_0x00, // CPX, CPY (imm/zp)
8'b11x0_1100, // CPX, CPY (abs)
8'b110x_xx01: // CMP
compare <= 1;
default: compare <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b01xx_xx10: // ROR, LSR
shift_right <= 1;
default: shift_right <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0x1x_1010, // ROL A, ROR A
8'b0x1x_x110: // ROR, ROL
rotate <= 1;
default: rotate <= 0;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b00xx_xx10: // ROL, ASL
op <= OP_ROL;
8'b0010_x100: // BIT zp/abs
op <= OP_AND;
8'b01xx_xx10: // ROR, LSR
op <= OP_A;
8'b1000_1000, // DEY
8'b1100_1010, // DEX
8'b110x_x110, // DEC
8'b11xx_xx01, // CMP, SBC
8'b11x0_0x00, // CPX, CPY (imm, zpg)
8'b11x0_1100: op <= OP_SUB;
8'b010x_xx01, // EOR
8'b00xx_xx01: // ORA, AND
op <= { 2'b11, IR[6:5] };
default: op <= OP_ADD;
endcase
always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0010_x100: // BIT zp/abs
bit_ins <= 1;
default: bit_ins <= 0;
endcase
/*
* special instructions
*/
always @(posedge clk )
if( state == DECODE && RDY ) begin
php <= (IR == 8'h08);
clc <= (IR == 8'h18);
plp <= (IR == 8'h28);
sec <= (IR == 8'h38);
cli <= (IR == 8'h58);
sei <= (IR == 8'h78);
clv <= (IR == 8'hb8);
cld <= (IR == 8'hd8);
sed <= (IR == 8'hf8);
brk <= (IR == 8'h00);
end
always @(posedge clk)
if( RDY )
cond_code <= IR[7:5];
always @*
case( cond_code )
3'b000: cond_true = ~N;
3'b001: cond_true = N;
3'b010: cond_true = ~V;
3'b011: cond_true = V;
3'b100: cond_true = ~C;
3'b101: cond_true = C;
3'b110: cond_true = ~Z;
3'b111: cond_true = Z;
endcase
reg NMI_1 = 0; // delayed NMI signal
always @(posedge clk)
NMI_1 <= NMI;
always @(posedge clk )
if( NMI_edge && state == BRK3 )
NMI_edge <= 0;
else if( NMI & ~NMI_1 )
NMI_edge <= 1;
endmodule
|
(** * PE: Partial Evaluation *)
(* Chapter written and maintained by Chung-chieh Shan *)
(** The [Equiv] chapter introduced constant folding as an example of a
program transformation and proved that it preserves the meaning of
programs. Constant folding operates on manifest constants such as
[ANum] expressions. For example, it simplifies the command [Y ::=
APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4]. However,
it does not propagate known constants along data flow. For
example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We might naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is like
running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Logic.FunctionalExtensionality.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import SfLib.
Require Import Maps.
Require Import Imp.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if beq_id V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V'
means to reason by cases over [beq_id V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) :=
let H := fresh "Heq" i j in
destruct (beq_idP i j);
[ subst j | ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
- (* [] *) inversion H.
- (* :: *) simpl in H. simpl. compare V V'; auto. Qed.
(** In what follows, we will make heavy use of the [In] property from
the standard library, also defined in [Logic.v]: *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** Besides the various lemmas about [In] that we've already come
across, the following one (taken from the standard library) will
also be useful: *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
(** If a type [A] has an operator [beq] for testing equality of its
elements, we can compute a boolean [inb beq a l] for testing
whether [In a l] holds or not. *)
Fixpoint inb {A : Type} (beq : A -> A -> bool) (a : A) (l : list A) :=
match l with
| [] => false
| a'::l' => beq a a' || inb beq a l'
end.
(** It is easy to relate [inb] to [In] with the [reflect] property: *)
Lemma inbP : forall A : Type, forall beq : A->A->bool,
(forall a1 a2, reflect (a1 = a2) (beq a1 a2)) ->
forall a l, reflect (In a l) (inb beq a l).
Proof.
intros A beq beqP a l.
induction l as [|a' l' IH].
- constructor. intros [].
- simpl. destruct (beqP a a').
+ subst. constructor. left. reflexivity.
+ simpl. destruct IH; constructor.
* right. trivial.
* intros [H1 | H2]; congruence.
Qed.
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
- (* AId *)
remember (pe_lookup pe_st i) as l. destruct l.
+ (* Some *) rewrite H with (n:=n) by apply Heql. reflexivity.
+ (* None *) reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_update (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => t_update (pe_update st pe_st) V n
end.
Example test_pe_update:
pe_update (t_update empty_state Y 1) [(X,3);(Z,2)]
= t_update (t_update (t_update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_update] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_update_correct: forall st pe_st V0,
pe_update st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold t_update.
compare V0 V; auto. rewrite <- beq_id_refl; auto. rewrite false_beq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_update] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_update_consistent: forall st pe_st,
pe_consistent (pe_update st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_update_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_update: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_update st pe_st V.
Proof. intros st pe_st H V. rewrite pe_update_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_update st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_update_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if leb n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_update st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
induction b; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_update st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_update st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0);
try destruct (leb n n0); reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st \\ c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_update] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if beq_id V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if beq_id V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
- (* [] *) destruct (beq_id V V0); reflexivity.
- (* :: *) simpl. compare V V'.
+ (* equal *) rewrite IHpe_st.
destruct (beq_idP V V0). reflexivity.
rewrite false_beq_id; auto.
+ (* not equal *) simpl. compare V0 V'.
* (* equal *) rewrite false_beq_id; auto.
* (* not equal *) rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if beq_id V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0.
- (* equal *) rewrite <- beq_id_refl; auto.
- (* not equal *) rewrite pe_remove_correct.
repeat rewrite false_beq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_update_update_remove: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update (t_update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality.
intros V0. unfold t_update. rewrite !pe_update_correct.
rewrite pe_remove_correct. destruct (beq_id V V0); reflexivity.
Qed.
Theorem pe_update_update_add: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold t_update. rewrite !pe_update_correct. rewrite pe_add_correct.
destruct (beq_id V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_app_iff.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l =>
x :: filter (fun y => if beq_id x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
- (* -> *)
intros. inversion H; clear H.
left. assumption.
destruct (beq_idP h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite false_beq_id; auto.
- (* <- *)
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
- (* -> *)
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
- (* <- *)
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
{ (* Proof of assertion *)
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
exfalso. apply Heq. split. assumption. reflexivity. }
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_update] only depends on the
[pe_lookup] interpretation of partial states, [pe_update] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_update] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if inb beq_id V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V.
- rewrite <- beq_id_refl. reflexivity.
- rewrite false_beq_id; try congruence. reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof.
intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (inbP _ _ beq_idP V (pe_compare pe_st1 pe_st2)).
- reflexivity.
- apply pe_compare_correct. auto. Qed.
Theorem pe_compare_update: forall pe_st1 pe_st2 st,
pe_update st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_update st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if inb beq_id V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_update st pe_st =
pe_update (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_removes_correct. unfold assigned.
destruct (inbP _ _ beq_idP V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st \\ st1 -> (forall V, st1 V = st2 V) -> c / st \\ st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st \\ assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
- (* [] *) eapply ceval_extensionality. apply E_Skip. reflexivity.
- (* V::ids *)
remember (pe_lookup pe_st V) as lookup. destruct lookup.
+ (* Some *) eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold t_update. compare V V0.
* (* equal *) rewrite <- Heqlookup. rewrite <- beq_id_refl. reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
+ (* None *) eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0.
* (* equal *) rewrite <- Heqlookup.
rewrite <- beq_id_refl.
destruct (inbP _ _ beq_idP V ids); reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '\\' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st \\ c1' / pe_st' ->
c2 / pe_st' \\ c2' / pe_st'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 ->
c2 / pe_st \\ c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '\\' c1' '/' st'" := (pe_com c1 st c1' st').
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] \\ (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
\\ (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '\\' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st \\ st' ->
pe_update st' pe_st' = st'' ->
c' / pe_st' / st \\ st''
where "c' '/' pe_st' '/' st '\\' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') ->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. reflexivity.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
reflexivity.
- (* PE_Seq *)
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c' / pe_st' / st \\ st'') ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_If *)
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
+ (* E_IfTrue *)
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
+ (* E_IfFalse *)
rewrite -> pe_compare_update.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) apply pe_com_complete. apply H.
- (* <- *) apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be, for example,
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking whether [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '\\' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st \\ c1' / pe_st' / SKIP ->
c2 / pe_st' \\ c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 / c'' ->
c2 / pe_st \\ c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st \\ (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
\\ SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '\\' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
\\ (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
\\ (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
\\ (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] \\ (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '\\' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st \\ st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st \\ (t_update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st \\ st' # n1 ->
c2 / st' \\ st'' # n2 ->
(c1 ;; c2) / st \\ st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st \\ st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st \\ st' # n1 ->
(WHILE b1 DO c1 END) / st' \\ st'' # n2 ->
(WHILE b1 DO c1 END) / st \\ st'' # S (n1 + n2)
where "c1 '/' st '\\' st' # n" := (ceval_count c1 st st' n).
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st \\ st' -> exists n, c / st \\ st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st \\ st' # n -> c / st \\ st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_update: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_update st pe_st1 = pe_update st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_update_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st \\ st' ->
c'' / pe_update st' pe_st' \\ st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n
where "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n' ->
c' / pe_st' / c'' / st \\ st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_update st pe_st \\ st'' # n) ->
(c' / pe_st' / c'' / st \\ st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. apply E'Skip. auto.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
apply E'Skip. auto.
- (* PE_Seq *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption. eassumption.
- (* PE_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_While *) inversion Heval; subst.
+ (* E_WhileEnd *) econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
+ (* E_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_update, <- assign_removes. eassumption.
omega.
- (* PE_WhileFixedLoop *) exfalso.
generalize dependent (S (n1 + n2)). intros n.
clear - H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct, H in H7. inversion H7.
+ (* E'WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
- (* PE_WhileFixed *) generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct in H8. eauto.
+ (* E'WhileLoop *) rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st \\ st'' # n) ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_If *) inversion Heval; subst; inversion H7; subst; clear H7.
+ (* E_IfTrue *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
+ (* E_IfFalse *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
- (* PE_WhileEnd *) apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
- (* PE_WhileLoop *) eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
- (* PE_While *) inversion Heval; subst.
+ (* E_IfTrue *)
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
+ (* E_IfFalse *) apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
* (* c2'' = SKIP *) inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
* (* c2'' = WHILE b1 DO c1 END *) assumption.
- (* PE_WhileFixedEnd *) eapply ceval_count_sound. apply Heval'.
- (* PE_WhileFixedLoop *)
apply loop_never_stops in Heval. inversion Heval.
- (* PE_WhileFixed *)
clear - H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
induction Heval;
inversion Heqc'; subst; clear Heqc'.
+ (* E_WhileEnd *) apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
+ (* E_WhileLoop *)
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' / SKIP ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(exists st', c' / st \\ st' /\ pe_update st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
- (* <- *) intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (t_update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (t_update (t_update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite t_update_same; auto.
Qed.
(** ** Partial Evaluation of Basic Blocks and Flowchart Programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_update st pe_st) k = (pe_update st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
induction k as [l | b l1 l2 | i a k];
intros st pe_st H.
- (* Goto *) inversion H; reflexivity.
- (* If *)
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
- (* Assign *)
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_update_update_add; apply IHk; apply H];
solve [rewrite pe_update_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_update st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_update st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split.
- (* -> *) intros Heval.
remember (pe_update st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ];
intros st pe_st Heqsto; subst sto.
+ (* E_None *) eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
+ (* E_Some *)
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
- (* <- *) intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ];
intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
+ (* E_None *) apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
+ (* E_Some *)
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: cpu_dma_queue_regs.v
// Project: NF2.1
// Description: Register module for the CPU DMA queue
//
///////////////////////////////////////////////////////////////////////////////
module cpu_dma_queue_regs
#(
parameter TX_WATCHDOG_TIMEOUT = 125000
)
(
// Interface to "main" module
input tx_timeout,
// Register interface
input reg_req,
input reg_rd_wr_L,
input [`MAC_GRP_REG_ADDR_WIDTH-1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_wr_data,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_rd_data,
output reg reg_ack,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// -------- Internal parameters --------------
localparam NUM_REGS_USED = 'h2; /* don't forget to update this when adding regs */
localparam REG_FILE_ADDR_WIDTH = log2(NUM_REGS_USED);
// ------------- Wires/reg ------------------
wire [REG_FILE_ADDR_WIDTH-1:0] addr;
wire addr_good;
wire new_reg_req;
reg reg_req_d1;
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_rd_data_nxt;
reg [31:0] tx_timeout_cnt;
// ---------- Logic ----------
assign addr = reg_addr[REG_FILE_ADDR_WIDTH-1:0];
assign addr_good = (reg_addr[`CPU_QUEUE_REG_ADDR_WIDTH-1:REG_FILE_ADDR_WIDTH] == 'h0 && addr < NUM_REGS_USED);
assign new_reg_req = reg_req && !reg_req_d1;
// Update the tx timeout counter
always @(posedge clk) begin
if (reset) begin
tx_timeout_cnt <= 'h0;
end
else begin
if (tx_timeout)
tx_timeout_cnt <= tx_timeout_cnt + 'h1;
end
end
// Work out the data to return from a register request
always @*
begin
case (addr)
'h0: reg_rd_data_nxt = tx_timeout_cnt;
default: reg_rd_data_nxt = 'h dead_beef;
endcase
end
// Handle register requests
always @(posedge clk) begin
reg_req_d1 <= reg_req;
if( reset ) begin
reg_rd_data <= 0;
reg_ack <= 0;
end
else begin
// Register access logic
if(new_reg_req) begin // read request
if(addr_good) begin
reg_rd_data <= reg_rd_data_nxt;
end
else begin
reg_rd_data <= 32'hdead_beef;
end
end
// requests complete after one cycle
reg_ack <= new_reg_req;
end // else: !if( reset )
end // always @ (posedge clk)
endmodule // cpu_dma_queue_regs
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 18:55:12 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_1_0_sim_netlist.v
// Design : ip_design_axi_gpio_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
(reg3,
reg1,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg,
gpio_io_o,
gpio_io_t,
gpio2_io_o,
gpio2_io_t,
Q,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ,
bus2ip_rnw_i_reg,
\Dual.gpio2_Data_In_reg[7]_0 ,
s_axi_aclk,
\Dual.gpio2_Data_In_reg[6]_0 ,
\Dual.gpio2_Data_In_reg[5]_0 ,
\Dual.gpio2_Data_In_reg[4]_0 ,
\Dual.gpio2_Data_In_reg[3]_0 ,
\Dual.gpio2_Data_In_reg[2]_0 ,
\Dual.gpio2_Data_In_reg[1]_0 ,
\Dual.gpio2_Data_In_reg[0]_0 ,
Read_Reg_In,
SS,
bus2ip_rnw,
bus2ip_cs,
gpio_io_i,
gpio2_io_i,
E,
D,
bus2ip_rnw_i_reg_0,
bus2ip_rnw_i_reg_1,
bus2ip_rnw_i_reg_2);
output [7:0]reg3;
output [4:0]reg1;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output ip2bus_rdack_i;
output ip2bus_wrack_i_D1_reg;
output [4:0]gpio_io_o;
output [4:0]gpio_io_t;
output [7:0]gpio2_io_o;
output [7:0]gpio2_io_t;
output [7:0]Q;
output [4:0]\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ;
input bus2ip_rnw_i_reg;
input \Dual.gpio2_Data_In_reg[7]_0 ;
input s_axi_aclk;
input \Dual.gpio2_Data_In_reg[6]_0 ;
input \Dual.gpio2_Data_In_reg[5]_0 ;
input \Dual.gpio2_Data_In_reg[4]_0 ;
input \Dual.gpio2_Data_In_reg[3]_0 ;
input \Dual.gpio2_Data_In_reg[2]_0 ;
input \Dual.gpio2_Data_In_reg[1]_0 ;
input \Dual.gpio2_Data_In_reg[0]_0 ;
input [0:4]Read_Reg_In;
input [0:0]SS;
input bus2ip_rnw;
input bus2ip_cs;
input [4:0]gpio_io_i;
input [7:0]gpio2_io_i;
input [0:0]E;
input [7:0]D;
input [0:0]bus2ip_rnw_i_reg_0;
input [0:0]bus2ip_rnw_i_reg_1;
input [0:0]bus2ip_rnw_i_reg_2;
wire [7:0]D;
wire [4:0]\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ;
wire \Dual.gpio2_Data_In_reg[0]_0 ;
wire \Dual.gpio2_Data_In_reg[1]_0 ;
wire \Dual.gpio2_Data_In_reg[2]_0 ;
wire \Dual.gpio2_Data_In_reg[3]_0 ;
wire \Dual.gpio2_Data_In_reg[4]_0 ;
wire \Dual.gpio2_Data_In_reg[5]_0 ;
wire \Dual.gpio2_Data_In_reg[6]_0 ;
wire \Dual.gpio2_Data_In_reg[7]_0 ;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [7:0]Q;
wire [0:4]Read_Reg_In;
wire [0:0]SS;
wire bus2ip_cs;
wire bus2ip_rnw;
wire bus2ip_rnw_i_reg;
wire [0:0]bus2ip_rnw_i_reg_0;
wire [0:0]bus2ip_rnw_i_reg_1;
wire [0:0]bus2ip_rnw_i_reg_2;
wire [7:0]gpio2_io_i;
wire [0:7]gpio2_io_i_d2;
wire [7:0]gpio2_io_o;
wire [7:0]gpio2_io_t;
wire [4:0]gpio_io_i;
wire [0:4]gpio_io_i_d2;
wire [4:0]gpio_io_o;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i_D1_reg;
wire [4:0]reg1;
wire [7:0]reg3;
wire s_axi_aclk;
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[0]),
.Q(reg1[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[1].reg1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[1]),
.Q(reg1[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[2].reg1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[2]),
.Q(reg1[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[3].reg1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[3]),
.Q(reg1[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G0.READ_REG_GEN[4].reg1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(Read_Reg_In[4]),
.Q(reg1[0]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[0]_0 ),
.Q(reg3[7]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[1]_0 ),
.Q(reg3[6]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[2]_0 ),
.Q(reg3[5]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[3]_0 ),
.Q(reg3[4]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[4]_0 ),
.Q(reg3[3]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[5]_0 ),
.Q(reg3[2]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[6]_0 ),
.Q(reg3[1]),
.R(bus2ip_rnw_i_reg));
FDRE \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Dual.gpio2_Data_In_reg[7]_0 ),
.Q(reg3[0]),
.R(bus2ip_rnw_i_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \Dual.INPUT_DOUBLE_REGS4
(.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0 \Dual.INPUT_DOUBLE_REGS5
(.gpio2_io_i(gpio2_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio2_io_i_d2[0],gpio2_io_i_d2[1],gpio2_io_i_d2[2],gpio2_io_i_d2[3],gpio2_io_i_d2[4],gpio2_io_i_d2[5],gpio2_io_i_d2[6],gpio2_io_i_d2[7]}));
FDRE \Dual.gpio2_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[0]),
.Q(Q[7]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[1]),
.Q(Q[6]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[2]),
.Q(Q[5]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[3]),
.Q(Q[4]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[4]),
.Q(Q[3]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[5]),
.Q(Q[2]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[6]),
.Q(Q[1]),
.R(1'b0));
FDRE \Dual.gpio2_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i_d2[7]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[7]),
.Q(gpio2_io_o[7]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[6]),
.Q(gpio2_io_o[6]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[5]),
.Q(gpio2_io_o[5]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[4]),
.Q(gpio2_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[3]),
.Q(gpio2_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[2]),
.Q(gpio2_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[1]),
.Q(gpio2_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio2_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_1),
.D(D[0]),
.Q(gpio2_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[7]),
.Q(gpio2_io_t[7]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[6]),
.Q(gpio2_io_t[6]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[5]),
.Q(gpio2_io_t[5]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[4]),
.Q(gpio2_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[3]),
.Q(gpio2_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[2]),
.Q(gpio2_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[1]),
.Q(gpio2_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio2_OE_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_2),
.D(D[0]),
.Q(gpio2_io_t[0]),
.S(SS));
FDRE \Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [4]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [3]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [2]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [1]),
.R(1'b0));
FDRE \Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[7]),
.Q(gpio_io_o[4]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[6]),
.Q(gpio_io_o[3]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[5]),
.Q(gpio_io_o[2]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(D[4]),
.Q(gpio_io_o[1]),
.R(SS));
FDRE #(
.INIT(1'b0))
\Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(D[3]),
.Q(gpio_io_o[0]),
.R(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[7]),
.Q(gpio_io_t[4]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[6]),
.Q(gpio_io_t[3]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[5]),
.Q(gpio_io_t[2]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[4]),
.Q(gpio_io_t[1]),
.S(SS));
FDSE #(
.INIT(1'b1))
\Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg_0),
.D(D[3]),
.Q(gpio_io_t[0]),
.S(SS));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h02))
iGPIO_xferAck_i_1
(.I0(bus2ip_cs),
.I1(gpio_xferAck_Reg),
.I2(GPIO_xferAck_i),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(SS));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h8))
ip2bus_rdack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_rdack_i));
LUT2 #(
.INIT(4'h2))
ip2bus_wrack_i_D1_i_1
(.I0(GPIO_xferAck_i),
.I1(bus2ip_rnw),
.O(ip2bus_wrack_i_D1_reg));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ,
s_axi_wready,
s_axi_arready,
D,
E,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
\Dual.gpio2_OE_reg[0] ,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ,
\ip2bus_data_i_D1_reg[0] ,
Q,
s_axi_aclk,
s_axi_aresetn,
ip2bus_rdack_i_D1,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
ip2bus_wrack_i_D1,
is_write_reg,
s_axi_wdata,
\bus2ip_addr_i_reg[8] ,
bus2ip_rnw_i_reg,
gpio_xferAck_Reg,
GPIO_xferAck_i,
reg3,
reg1);
output \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
output s_axi_wready;
output s_axi_arready;
output [7:0]D;
output [0:0]E;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
output [8:0]\ip2bus_data_i_D1_reg[0] ;
input Q;
input s_axi_aclk;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input is_read;
input [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input ip2bus_wrack_i_D1;
input is_write_reg;
input [7:0]s_axi_wdata;
input [2:0]\bus2ip_addr_i_reg[8] ;
input bus2ip_rnw_i_reg;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]reg3;
input [4:0]reg1;
wire Bus_RNW_reg;
wire Bus_RNW_reg_i_1_n_0;
wire [7:0]D;
wire \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_rnw_i_reg;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire cs_ce_clr;
wire gpio_xferAck_Reg;
wire \ip2bus_data_i_D1[27]_i_2_n_0 ;
wire \ip2bus_data_i_D1[27]_i_3_n_0 ;
wire [8:0]\ip2bus_data_i_D1_reg[0] ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_write_reg;
wire [4:0]reg1;
wire [7:0]reg3;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [7:0]s_axi_wdata;
wire s_axi_wready;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(Q),
.I2(Bus_RNW_reg),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(Bus_RNW_reg),
.R(1'b0));
LUT4 #(
.INIT(16'hFFF7))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(gpio_xferAck_Reg),
.I3(GPIO_xferAck_i),
.O(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00100000))
\Dual.gpio2_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [1]),
.O(\Dual.gpio2_Data_Out_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h8A))
\Dual.gpio2_Data_Out[5]_i_1
(.I0(s_axi_wdata[2]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h8A))
\Dual.gpio2_Data_Out[6]_i_1
(.I0(s_axi_wdata[1]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h8A))
\Dual.gpio2_Data_Out[7]_i_1
(.I0(s_axi_wdata[0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h10000000))
\Dual.gpio2_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.O(\Dual.gpio2_OE_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00000010))
\Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[4]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[3]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[2]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[1]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFB08))
\Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[0]),
.I1(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(s_axi_wdata[3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00100000))
\Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\bus2ip_addr_i_reg[8] [0]),
.O(\Dual.gpio_OE_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h1))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_3),
.Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\bus2ip_addr_i_reg[8] [0]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_2),
.Q(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.O(ce_expnd_i_1));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_1),
.Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hEF))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arready),
.I2(s_axi_aresetn),
.O(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h8))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [0]),
.O(ce_expnd_i_0));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.R(cs_ce_clr));
LUT5 #(
.INIT(32'h000000E0))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.I1(Q),
.I2(s_axi_aresetn),
.I3(s_axi_arready),
.I4(s_axi_wready),
.O(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0 ),
.Q(\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00040400))
\ip2bus_data_i_D1[0]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.O(\ip2bus_data_i_D1_reg[0] [8]));
LUT6 #(
.INIT(64'h00020000003C0000))
\ip2bus_data_i_D1[24]_i_1
(.I0(reg3[7]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(Bus_RNW_reg),
.I5(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1_reg[0] [7]));
LUT6 #(
.INIT(64'h00020000003C0000))
\ip2bus_data_i_D1[25]_i_1
(.I0(reg3[6]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(Bus_RNW_reg),
.I5(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1_reg[0] [6]));
LUT6 #(
.INIT(64'h00020000003C0000))
\ip2bus_data_i_D1[26]_i_1
(.I0(reg3[5]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(Bus_RNW_reg),
.I5(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1_reg[0] [5]));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[27]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[4]),
.I3(reg3[4]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [4]));
LUT5 #(
.INIT(32'h00020000))
\ip2bus_data_i_D1[27]_i_2
(.I0(Bus_RNW_reg),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(\ip2bus_data_i_D1[27]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00020000))
\ip2bus_data_i_D1[27]_i_3
(.I0(Bus_RNW_reg),
.I1(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(\ip2bus_data_i_D1[27]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[28]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[3]),
.I3(reg3[3]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [3]));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[29]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[2]),
.I3(reg3[2]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [2]));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[30]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[1]),
.I3(reg3[1]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [1]));
LUT5 #(
.INIT(32'hFFEAEAEA))
\ip2bus_data_i_D1[31]_i_1
(.I0(\ip2bus_data_i_D1_reg[0] [8]),
.I1(\ip2bus_data_i_D1[27]_i_2_n_0 ),
.I2(reg1[0]),
.I3(reg3[0]),
.I4(\ip2bus_data_i_D1[27]_i_3_n_0 ),
.O(\ip2bus_data_i_D1_reg[0] [0]));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_arready_INST_0
(.I0(ip2bus_rdack_i_D1),
.I1(is_read),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hAAAAAAAAAAAEAAAA))
s_axi_wready_INST_0
(.I0(ip2bus_wrack_i_D1),
.I1(is_write_reg),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [1]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [3]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] [0]),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "1" *) (* C_ALL_INPUTS_2 = "1" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "8" *) (* C_GPIO_WIDTH = "5" *)
(* C_INTERRUPT_PRESENT = "0" *) (* C_IS_DUAL = "1" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [4:0]gpio_io_i;
output [4:0]gpio_io_o;
output [4:0]gpio_io_t;
input [7:0]gpio2_io_i;
output [7:0]gpio2_io_o;
output [7:0]gpio2_io_t;
wire \<const0> ;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire AXI_LITE_IPIF_I_n_15;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_17;
wire AXI_LITE_IPIF_I_n_18;
wire AXI_LITE_IPIF_I_n_24;
wire AXI_LITE_IPIF_I_n_25;
wire AXI_LITE_IPIF_I_n_26;
wire AXI_LITE_IPIF_I_n_27;
wire AXI_LITE_IPIF_I_n_28;
wire AXI_LITE_IPIF_I_n_29;
wire AXI_LITE_IPIF_I_n_30;
wire AXI_LITE_IPIF_I_n_31;
wire AXI_LITE_IPIF_I_n_32;
wire GPIO_xferAck_i;
wire [0:4]Read_Reg_In;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [0:7]gpio2_Data_In;
wire [7:0]gpio2_io_i;
wire [7:0]gpio2_io_o;
wire [7:0]gpio2_io_t;
wire [0:4]gpio_Data_In;
wire gpio_core_1_n_16;
wire [4:0]gpio_io_i;
wire [4:0]gpio_io_o;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [0:31]ip2bus_data;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire [4:0]p_0_out;
wire [27:31]reg1;
wire [24:31]reg3;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [30:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign ip2intc_irpt = \<const0> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [30];
assign s_axi_rdata[30] = \^s_axi_rdata [30];
assign s_axi_rdata[29] = \^s_axi_rdata [30];
assign s_axi_rdata[28] = \^s_axi_rdata [30];
assign s_axi_rdata[27] = \^s_axi_rdata [30];
assign s_axi_rdata[26] = \^s_axi_rdata [30];
assign s_axi_rdata[25] = \^s_axi_rdata [30];
assign s_axi_rdata[24] = \^s_axi_rdata [30];
assign s_axi_rdata[23] = \^s_axi_rdata [30];
assign s_axi_rdata[22] = \^s_axi_rdata [30];
assign s_axi_rdata[21] = \^s_axi_rdata [30];
assign s_axi_rdata[20] = \^s_axi_rdata [30];
assign s_axi_rdata[19] = \^s_axi_rdata [30];
assign s_axi_rdata[18] = \^s_axi_rdata [30];
assign s_axi_rdata[17] = \^s_axi_rdata [30];
assign s_axi_rdata[16] = \^s_axi_rdata [30];
assign s_axi_rdata[15] = \^s_axi_rdata [30];
assign s_axi_rdata[14] = \^s_axi_rdata [30];
assign s_axi_rdata[13] = \^s_axi_rdata [30];
assign s_axi_rdata[12] = \^s_axi_rdata [30];
assign s_axi_rdata[11] = \^s_axi_rdata [30];
assign s_axi_rdata[10] = \^s_axi_rdata [30];
assign s_axi_rdata[9] = \^s_axi_rdata [30];
assign s_axi_rdata[8] = \^s_axi_rdata [30];
assign s_axi_rdata[7:0] = \^s_axi_rdata [7:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.D({p_0_out,AXI_LITE_IPIF_I_n_12,AXI_LITE_IPIF_I_n_13,AXI_LITE_IPIF_I_n_14}),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] (AXI_LITE_IPIF_I_n_24),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] (AXI_LITE_IPIF_I_n_32),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] (AXI_LITE_IPIF_I_n_31),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] (AXI_LITE_IPIF_I_n_30),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] (AXI_LITE_IPIF_I_n_29),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] (AXI_LITE_IPIF_I_n_28),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] (AXI_LITE_IPIF_I_n_27),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] (AXI_LITE_IPIF_I_n_26),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] (AXI_LITE_IPIF_I_n_25),
.\Dual.gpio2_Data_In_reg[0] ({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7]}),
.\Dual.gpio2_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_17),
.\Dual.gpio2_OE_reg[0] (AXI_LITE_IPIF_I_n_18),
.\Dual.gpio_OE_reg[0] (AXI_LITE_IPIF_I_n_16),
.E(AXI_LITE_IPIF_I_n_15),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4]}),
.Read_Reg_In(Read_Reg_In),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[0] ({ip2bus_data[0],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.reg1({reg1[27],reg1[28],reg1[29],reg1[30],reg1[31]}),
.reg3({reg3[24],reg3[25],reg3[26],reg3[27],reg3[28],reg3[29],reg3[30],reg3[31]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr({s_axi_araddr[8],s_axi_araddr[3:2]}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr({s_axi_awaddr[8],s_axi_awaddr[3:2]}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [30],\^s_axi_rdata [7:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata[7:0]),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core gpio_core_1
(.D({p_0_out,AXI_LITE_IPIF_I_n_12,AXI_LITE_IPIF_I_n_13,AXI_LITE_IPIF_I_n_14}),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4]}),
.\Dual.gpio2_Data_In_reg[0]_0 (AXI_LITE_IPIF_I_n_32),
.\Dual.gpio2_Data_In_reg[1]_0 (AXI_LITE_IPIF_I_n_31),
.\Dual.gpio2_Data_In_reg[2]_0 (AXI_LITE_IPIF_I_n_30),
.\Dual.gpio2_Data_In_reg[3]_0 (AXI_LITE_IPIF_I_n_29),
.\Dual.gpio2_Data_In_reg[4]_0 (AXI_LITE_IPIF_I_n_28),
.\Dual.gpio2_Data_In_reg[5]_0 (AXI_LITE_IPIF_I_n_27),
.\Dual.gpio2_Data_In_reg[6]_0 (AXI_LITE_IPIF_I_n_26),
.\Dual.gpio2_Data_In_reg[7]_0 (AXI_LITE_IPIF_I_n_25),
.E(AXI_LITE_IPIF_I_n_15),
.GPIO_xferAck_i(GPIO_xferAck_i),
.Q({gpio2_Data_In[0],gpio2_Data_In[1],gpio2_Data_In[2],gpio2_Data_In[3],gpio2_Data_In[4],gpio2_Data_In[5],gpio2_Data_In[6],gpio2_Data_In[7]}),
.Read_Reg_In(Read_Reg_In),
.SS(bus2ip_reset),
.bus2ip_cs(bus2ip_cs),
.bus2ip_rnw(bus2ip_rnw),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_24),
.bus2ip_rnw_i_reg_0(AXI_LITE_IPIF_I_n_16),
.bus2ip_rnw_i_reg_1(AXI_LITE_IPIF_I_n_17),
.bus2ip_rnw_i_reg_2(AXI_LITE_IPIF_I_n_18),
.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(gpio2_io_o),
.gpio2_io_t(gpio2_io_t),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i_D1_reg(gpio_core_1_n_16),
.reg1({reg1[27],reg1[28],reg1[29],reg1[30],reg1[31]}),
.reg3({reg3[24],reg3[25],reg3[26],reg3[27],reg3[28],reg3[29],reg3[30],reg3[31]}),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[0]),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[31]),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_core_1_n_16),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(bus2ip_reset,
bus2ip_rnw,
s_axi_rvalid,
s_axi_bvalid,
bus2ip_cs,
s_axi_wready,
s_axi_arready,
D,
E,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
\Dual.gpio2_OE_reg[0] ,
Read_Reg_In,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ,
s_axi_rdata,
\ip2bus_data_i_D1_reg[0] ,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
s_axi_araddr,
s_axi_awaddr,
Q,
gpio_io_t,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\Dual.gpio2_Data_In_reg[0] ,
gpio2_io_t,
\ip2bus_data_i_D1_reg[0]_0 ,
reg3,
reg1);
output bus2ip_reset;
output bus2ip_rnw;
output s_axi_rvalid;
output s_axi_bvalid;
output bus2ip_cs;
output s_axi_wready;
output s_axi_arready;
output [7:0]D;
output [0:0]E;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output [0:4]Read_Reg_In;
output \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
output [8:0]s_axi_rdata;
output [8:0]\ip2bus_data_i_D1_reg[0] ;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [7:0]s_axi_wdata;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input [4:0]Q;
input [4:0]gpio_io_t;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]\Dual.gpio2_Data_In_reg[0] ;
input [7:0]gpio2_io_t;
input [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
input [7:0]reg3;
input [4:0]reg1;
wire [7:0]D;
wire \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ;
wire [7:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [4:0]Q;
wire [0:4]Read_Reg_In;
wire bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [7:0]gpio2_io_t;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [8:0]\ip2bus_data_i_D1_reg[0] ;
wire [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire [4:0]reg1;
wire [7:0]reg3;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [8:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [7:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] (bus2ip_rnw),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 (\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ),
.\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] (\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ),
.\Dual.gpio2_Data_In_reg[0] (\Dual.gpio2_Data_In_reg[0] ),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (\Dual.gpio2_OE_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0] (bus2ip_cs),
.Q(Q),
.Read_Reg_In(Read_Reg_In),
.SR(bus2ip_reset),
.gpio2_io_t(gpio2_io_t),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.reg1(reg1),
.reg3(reg3),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(scndry_vect_out,
gpio_io_i,
s_axi_aclk);
output [4:0]scndry_vect_out;
input [4:0]gpio_io_i;
input s_axi_aclk;
wire [4:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire [4:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync__parameterized0
(scndry_vect_out,
gpio2_io_i,
s_axi_aclk);
output [7:0]scndry_vect_out;
input [7:0]gpio2_io_i;
input s_axi_aclk;
wire [7:0]gpio2_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire [7:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio2_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "ip_design_axi_gpio_1_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
gpio_io_i,
gpio2_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE" *) input [4:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I" *) (* x_interface_parameter = "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE" *) input [7:0]gpio2_io_i;
wire [7:0]gpio2_io_i;
wire [4:0]gpio_io_i;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ip2intc_irpt_UNCONNECTED;
wire [7:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [7:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [4:0]NLW_U0_gpio_io_o_UNCONNECTED;
wire [4:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "1" *)
(* C_ALL_INPUTS_2 = "1" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "8" *)
(* C_GPIO_WIDTH = "5" *)
(* C_INTERRUPT_PRESENT = "0" *)
(* C_IS_DUAL = "1" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio U0
(.gpio2_io_i(gpio2_io_i),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[7:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[7:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[4:0]),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[4:0]),
.ip2intc_irpt(NLW_U0_ip2intc_irpt_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(SR,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ,
s_axi_rvalid,
s_axi_bvalid,
\MEM_DECODE_GEN[0].cs_out_i_reg[0] ,
s_axi_wready,
s_axi_arready,
D,
E,
\Dual.gpio_OE_reg[0] ,
\Dual.gpio2_Data_Out_reg[0] ,
\Dual.gpio2_OE_reg[0] ,
Read_Reg_In,
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ,
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ,
s_axi_rdata,
\ip2bus_data_i_D1_reg[0] ,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
s_axi_awvalid,
s_axi_wvalid,
s_axi_rready,
s_axi_bready,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_wdata,
s_axi_araddr,
s_axi_awaddr,
Q,
gpio_io_t,
gpio_xferAck_Reg,
GPIO_xferAck_i,
\Dual.gpio2_Data_In_reg[0] ,
gpio2_io_t,
\ip2bus_data_i_D1_reg[0]_0 ,
reg3,
reg1);
output SR;
output \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
output s_axi_rvalid;
output s_axi_bvalid;
output \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
output s_axi_wready;
output s_axi_arready;
output [7:0]D;
output [0:0]E;
output [0:0]\Dual.gpio_OE_reg[0] ;
output [0:0]\Dual.gpio2_Data_Out_reg[0] ;
output [0:0]\Dual.gpio2_OE_reg[0] ;
output [0:4]Read_Reg_In;
output \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ;
output \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
output [8:0]s_axi_rdata;
output [8:0]\ip2bus_data_i_D1_reg[0] ;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_rready;
input s_axi_bready;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input [7:0]s_axi_wdata;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input [4:0]Q;
input [4:0]gpio_io_t;
input gpio_xferAck_Reg;
input GPIO_xferAck_i;
input [7:0]\Dual.gpio2_Data_In_reg[0] ;
input [7:0]gpio2_io_t;
input [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
input [7:0]reg3;
input [4:0]reg1;
wire [7:0]D;
wire \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ;
wire \Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ;
wire \Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ;
wire [7:0]\Dual.gpio2_Data_In_reg[0] ;
wire [0:0]\Dual.gpio2_Data_Out_reg[0] ;
wire [0:0]\Dual.gpio2_OE_reg[0] ;
wire [0:0]\Dual.gpio_OE_reg[0] ;
wire [0:0]E;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \MEM_DECODE_GEN[0].cs_out_i_reg[0] ;
wire [4:0]Q;
wire [0:4]Read_Reg_In;
wire SR;
wire [0:6]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_1_n_0 ;
wire \bus2ip_addr_i[8]_i_2_n_0 ;
wire clear;
wire [7:0]gpio2_io_t;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire [8:0]\ip2bus_data_i_D1_reg[0] ;
wire [8:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [3:0]plusOp;
wire [4:0]reg1;
wire [7:0]reg3;
wire rst_i_1_n_0;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [8:0]s_axi_rdata;
wire \s_axi_rdata_i[31]_i_1_n_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [7:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[0]_i_1_n_0 ;
wire \state[1]_i_1_n_0 ;
wire \state[1]_i_3_n_0 ;
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1[27]_i_1
(.I0(Q[4]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[4]),
.O(Read_Reg_In[0]));
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[1].reg1[28]_i_1
(.I0(Q[3]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[3]),
.O(Read_Reg_In[1]));
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[2].reg1[29]_i_1
(.I0(Q[2]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[2]),
.O(Read_Reg_In[2]));
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[3].reg1[30]_i_1
(.I0(Q[1]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[1]),
.O(Read_Reg_In[3]));
LUT5 #(
.INIT(32'h03020002))
\Dual.ALLIN0_ND_G0.READ_REG_GEN[4].reg1[31]_i_1
(.I0(Q[0]),
.I1(bus2ip_addr[0]),
.I2(bus2ip_addr[5]),
.I3(bus2ip_addr[6]),
.I4(gpio_io_t[0]),
.O(Read_Reg_In[4]));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3[24]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [7]),
.I1(gpio2_io_t[7]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[0].reg3_reg[24] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3[25]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [6]),
.I1(gpio2_io_t[6]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[1].reg3_reg[25] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3[26]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [5]),
.I1(gpio2_io_t[5]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[2].reg3_reg[26] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3[27]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [4]),
.I1(gpio2_io_t[4]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[3].reg3_reg[27] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3[28]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [3]),
.I1(gpio2_io_t[3]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[4].reg3_reg[28] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3[29]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [2]),
.I1(gpio2_io_t[2]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[5].reg3_reg[29] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3[30]_i_1
(.I0(\Dual.gpio2_Data_In_reg[0] [1]),
.I1(gpio2_io_t[1]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[6].reg3_reg[30] ));
LUT5 #(
.INIT(32'h0000CA00))
\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3[31]_i_2
(.I0(\Dual.gpio2_Data_In_reg[0] [0]),
.I1(gpio2_io_t[0]),
.I2(bus2ip_addr[6]),
.I3(bus2ip_addr[5]),
.I4(bus2ip_addr[0]),
.O(\Dual.ALLIN0_ND_G2.READ_REG2_GEN[7].reg3_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D(D),
.\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] (\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27]_0 ),
.\Dual.gpio2_Data_Out_reg[0] (\Dual.gpio2_Data_Out_reg[0] ),
.\Dual.gpio2_OE_reg[0] (\Dual.gpio2_OE_reg[0] ),
.\Dual.gpio_OE_reg[0] (\Dual.gpio_OE_reg[0] ),
.E(E),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0 (\MEM_DECODE_GEN[0].cs_out_i_reg[0] ),
.Q(start2),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_rnw_i_reg(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.reg1(reg1),
.reg3(reg3),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready));
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_awaddr[0]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_awaddr[1]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\bus2ip_addr_i[8]_i_2
(.I0(s_axi_araddr[2]),
.I1(s_axi_awaddr[2]),
.I2(s_axi_arvalid),
.O(\bus2ip_addr_i[8]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[6]),
.R(SR));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[5]),
.R(SR));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(\bus2ip_addr_i[8]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(SR));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[8]_i_1_n_0 ),
.D(s_axi_arvalid),
.Q(\Dual.ALLIN0_ND_G0.READ_REG_GEN[0].reg1_reg[27] ),
.R(SR));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(SR));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(SR));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(s_axi_aresetn),
.O(rst_i_1_n_0));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rst_i_1_n_0),
.Q(SR),
.R(1'b0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(SR));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[31]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [0]),
.Q(s_axi_rdata[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [1]),
.Q(s_axi_rdata[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [2]),
.Q(s_axi_rdata[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [8]),
.Q(s_axi_rdata[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [3]),
.Q(s_axi_rdata[3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [4]),
.Q(s_axi_rdata[4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [5]),
.Q(s_axi_rdata[5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [6]),
.Q(s_axi_rdata[6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(\ip2bus_data_i_D1_reg[0]_0 [7]),
.Q(s_axi_rdata[7]),
.R(SR));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(SR));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(state[0]),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(s_axi_wready),
.O(\state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(\state[1]_i_3_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(s_axi_arready),
.O(\state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(state[0]),
.R(SR));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\state[1]_i_1_n_0 ),
.Q(state[1]),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_static_mrdwr.v
// Version : v1.0
// Description: master write channel: Issue write commands based on the
// cmdgen block output
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_static_mrdwr #
(
parameter C_M_AXI_THREAD_ID_WIDTH = 1 ,
parameter C_M_AXI_AWUSER_WIDTH = 8 ,
parameter C_M_AXI_ARUSER_WIDTH = 8 ,
parameter C_ATG_STATIC_RD_ADDRESS = 32'h12A0_0000 ,
parameter C_ATG_STATIC_WR_ADDRESS = 32'h13A0_0000 ,
parameter C_ATG_STATIC_WR_HIGH_ADDRESS = 32'h12A0_0FFF ,
parameter C_ATG_STATIC_RD_HIGH_ADDRESS = 32'h13A0_0FFF ,
parameter C_ATG_STATIC_INCR = 0 ,
parameter C_ATG_STATIC_EN_READ = 1 ,
parameter C_ATG_STATIC_EN_WRITE = 1 ,
parameter C_ATG_STATIC_LENGTH = 5 ,
parameter C_ATG_STATIC_RD_SELFTEST = 0 ,
parameter C_ATG_STATIC_RD_PIPELINE = 1 ,
parameter C_ATG_STATIC_WR_PIPELINE = 1 ,
parameter C_ATG_STATIC_FREE_RUN = 1 ,
parameter C_ATG_STATIC_TRANGAP = 32'd255,
parameter C_ATG_HLTP_MODE = 0 , //0-Custom,1-High Level Traffic.
parameter C_M_AXI_DATA_WIDTH = 32
) (
// system
input Clk ,
input rst_l ,
//aw
output [C_M_AXI_THREAD_ID_WIDTH-1:0] awid_m ,
output [31:0] awaddr_m ,
output [7:0] awlen_m ,
output [2:0] awsize_m ,
output [1:0] awburst_m ,
output [0:0] awlock_m ,
output [3:0] awcache_m ,
output [2:0] awprot_m ,
output [3:0] awqos_m ,
output [C_M_AXI_AWUSER_WIDTH-1:0] awuser_m ,
output awvalid_m ,
input awready_m ,
//w
output wlast_m ,
output [C_M_AXI_DATA_WIDTH-1:0] wdata_m ,
output [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_m ,
output wvalid_m ,
input wready_m ,
//b
input [C_M_AXI_THREAD_ID_WIDTH-1:0] bid_m ,
input [1:0] bresp_m ,
input bvalid_m ,
output bready_m ,
//ar
output [C_M_AXI_THREAD_ID_WIDTH-1:0] arid_m ,
output [31:0] araddr_m ,
output [7:0] arlen_m ,
output [2:0] arsize_m ,
output [1:0] arburst_m ,
output [0:0] arlock_m ,
output [3:0] arcache_m ,
output [2:0] arprot_m ,
output [3:0] arqos_m ,
output [C_M_AXI_ARUSER_WIDTH-1:0] aruser_m ,
output arvalid_m ,
input arready_m ,
//r
input [C_M_AXI_THREAD_ID_WIDTH-1:0] rid_m ,
input rlast_m ,
input [C_M_AXI_DATA_WIDTH-1:0] rdata_m ,
input [1:0] rresp_m ,
input rvalid_m ,
output rready_m ,
//register module
input reg1_st_enable ,
output reg1_done ,
input reset_reg1_done ,
input reset_reg1_en ,
input [7:0] reg2_length ,
input reg2_length_req ,
output [31:0] reg3_rdcnt ,
output [31:0] reg4_wrcnt ,
output [31:0] reg5_glcnt
);
//**********************Enabling ATG*************************
localparam C_ATG_STATIC_WR_HIGH_ADDRESS_C = C_ATG_STATIC_WR_HIGH_ADDRESS + 1'h1;
localparam C_ATG_STATIC_RD_HIGH_ADDRESS_C = C_ATG_STATIC_RD_HIGH_ADDRESS + 1'h1;
reg st_en_reg1, st_en_reg2 ;
wire st_en_reg_edge ;
wire st_dis_reg_edge ;
reg [7:0] burst_len ;
reg st_mode_active ;
reg done ;
assign reg1_done = done;
reg [31:0] glcnt_reg;
wire glcnt_done ;
generate if(C_ATG_STATIC_FREE_RUN == 0) begin : ATG_MODE_STATIC_DEBUG_ON_CNT_DONE
assign glcnt_done = &glcnt_reg;
end
endgenerate
generate if(C_ATG_STATIC_FREE_RUN == 1) begin : ATG_MODE_STATIC_DEBUG_OFF_CNT_DONE
assign glcnt_done = 1'b0;
end
endgenerate
// Increment addres based on the burst length
wire [8:0] bl_addr_incr = (C_M_AXI_DATA_WIDTH==32) ? 9'h4 :
(C_M_AXI_DATA_WIDTH==64) ? 9'h8 :
(C_M_AXI_DATA_WIDTH==128) ? 9'h10 :
(C_M_AXI_DATA_WIDTH==256) ? 9'h20 :9'h40;
always @(posedge Clk) begin
if (~rst_l) begin
st_en_reg1 <= 1'b0;
st_en_reg2 <= 1'b0;
end
else begin
st_en_reg1 <= reg1_st_enable;
st_en_reg2 <= st_en_reg1;
end
end
assign st_en_reg_edge = st_en_reg1 & ~st_en_reg2;
assign st_dis_reg_edge = ~st_en_reg1 & st_en_reg2;
reg stop_generation;
always @(posedge Clk) begin
if (~rst_l) begin
stop_generation <= 1'b0;
end else if (st_en_reg_edge | reset_reg1_done) begin
stop_generation <= 1'b0;
end else if (st_dis_reg_edge) begin
stop_generation <= 1'b1;
end
end
always @(posedge Clk) begin
if (~rst_l) begin
burst_len <= C_ATG_STATIC_LENGTH-1;
end
else if (reg2_length_req) begin
burst_len <= reg2_length;
end
end
//*************************** Write Master standard signal assignement*******************************
reg awvalid_m_reg ;
reg [31:0] awaddr_m_reg ;
reg [31:0] awaddr_m_reg_incr;
reg [12:0] cmdw_addrincr_ff;
reg [31:0] awaddr_nxt_chk;
reg [7:0] awlen_m_reg ;
reg wlast_reg ;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_m_reg ;
reg wvalid_m_reg ;
reg [7:0] wlast_cnt_reg ;
reg bready_m_reg ;
reg [2:0] wr_addr_pipe ;
reg wr_addr_pend ;
reg [2:0] wr_data_queue ;
reg [31:0] write_four_k ;
/*
output [C_M_AXI_THREAD_ID_WIDTH-1:0] awid_m ,
output [31:0] awaddr_m ,
output [7:0] awlen_m ,
output [2:0] awsize_m ,
output [1:0] awburst_m ,
output [0:0] awlock_m ,
output [3:0] awcache_m ,
output [2:0] awprot_m ,
output [3:0] awqos_m ,
output [C_M_AXI_AWUSER_WIDTH-1:0] awuser_m ,
output awvalid_m ,
*/
wire [3:0] param_incr_shift = (C_M_AXI_DATA_WIDTH == 32) ? 4'h2 : (C_M_AXI_DATA_WIDTH == 64) ? 4'h3 : (C_M_AXI_DATA_WIDTH == 128) ? 4'h4 : (C_M_AXI_DATA_WIDTH == 256) ? 4'h5: 4'h6;
generate if(C_ATG_STATIC_EN_WRITE == 1) begin : ATG_MODE_STATIC_WR_ON
assign awid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] = {C_M_AXI_THREAD_ID_WIDTH {1'b0}};
assign awaddr_m = (C_ATG_STATIC_INCR == 0) ? awaddr_m_reg : awaddr_m_reg_incr;
assign awlen_m = awlen_m_reg;
assign awprot_m = 3'b000;
assign awlock_m[0:0] = 1'b0;
assign awcache_m = 4'b0011;
assign awuser_m[C_M_AXI_AWUSER_WIDTH-1:0] = {C_M_AXI_AWUSER_WIDTH{1'b0}};
assign awqos_m[3:0] = 4'h0;
assign awburst_m = 2'b01;
assign awsize_m = (C_M_AXI_DATA_WIDTH==32) ? 3'b010 :
(C_M_AXI_DATA_WIDTH==64) ? 3'b011 :
(C_M_AXI_DATA_WIDTH==128) ? 3'b100 :
(C_M_AXI_DATA_WIDTH==256) ? 3'b101 :3'b110;
assign awvalid_m = awvalid_m_reg;
assign wlast_m = wlast_reg;
assign wdata_m = wdata_m_reg;
assign wstrb_m = {(C_M_AXI_DATA_WIDTH/8){1'b1}};
assign wvalid_m = wvalid_m_reg;
assign bready_m = bready_m_reg;
/////////////Auto INCR PR
wire [12:0] cmdw_addrincr = (burst_len+1) << param_incr_shift;
always @(posedge Clk) begin
if (~rst_l) begin
awaddr_nxt_chk <= C_ATG_STATIC_WR_ADDRESS;
cmdw_addrincr_ff <= cmdw_addrincr;
end
else begin
cmdw_addrincr_ff <= cmdw_addrincr;
awaddr_nxt_chk <= cmdw_addrincr_ff + cmdw_addrincr_ff;
end
end
//****************************Write Master Interface******************************
// Enable this based on generic C_ATG_STATIC_EN_WRITE
wire launch_nxt_wtrn;
// Write Master Logic
always @(posedge Clk) begin
if (~rst_l) begin
awvalid_m_reg <= 1'b0;
awaddr_m_reg <= 32'b0;
awaddr_m_reg_incr <= 32'b0;
awlen_m_reg <= 8'b0;
write_four_k <= 32'b0;
end else if (st_en_reg_edge) begin
awvalid_m_reg <= 1'b1;
awaddr_m_reg <= C_ATG_STATIC_WR_ADDRESS;
awaddr_m_reg_incr <= C_ATG_STATIC_WR_ADDRESS;
awlen_m_reg <= burst_len;
write_four_k <= C_ATG_STATIC_WR_ADDRESS + 32'd4096;
end else if (awvalid_m_reg & ~awready_m) begin
awvalid_m_reg <= awvalid_m_reg;
awaddr_m_reg <= C_ATG_STATIC_WR_ADDRESS;
awaddr_m_reg_incr <= awaddr_m_reg_incr;
awlen_m_reg <= burst_len;
write_four_k <= write_four_k;
end else if ((wr_addr_pipe == C_ATG_STATIC_WR_PIPELINE-1) && awvalid_m && awready_m ) begin
awvalid_m_reg <= 1'b0;
awaddr_m_reg <= 32'b0;
awaddr_m_reg_incr <= awaddr_m_reg_incr;
awlen_m_reg <= 8'b0;
write_four_k <= write_four_k;
end else if ((wr_addr_pipe < C_ATG_STATIC_WR_PIPELINE) ) begin
awvalid_m_reg <= st_en_reg1 & ~glcnt_done & launch_nxt_wtrn;
awaddr_m_reg <= C_ATG_STATIC_WR_ADDRESS;
awlen_m_reg <= burst_len;
if (~(st_en_reg1 & ~glcnt_done & launch_nxt_wtrn)) begin
awaddr_m_reg_incr <= awaddr_m_reg_incr;
write_four_k <= write_four_k;
end else if (awaddr_nxt_chk + awaddr_m_reg_incr > C_ATG_STATIC_WR_HIGH_ADDRESS_C) begin
awaddr_m_reg_incr <= C_ATG_STATIC_WR_ADDRESS;
write_four_k <= C_ATG_STATIC_WR_ADDRESS + 32'd4096;
end else if (awaddr_nxt_chk + awaddr_m_reg_incr > write_four_k) begin
awaddr_m_reg_incr <= write_four_k;
write_four_k <= write_four_k + 32'd4096;
end else begin
awaddr_m_reg_incr <= awaddr_m_reg_incr + cmdw_addrincr;
write_four_k <= write_four_k;
end
end
end
// Write Address Pipeline
wire btrns_complete;
wire wtrns_complete;
wire bwtrns_complete;
assign btrns_complete = bvalid_m & bready_m;
assign bwtrns_complete = (C_ATG_HLTP_MODE == 0) ? btrns_complete : wtrns_complete;
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge) begin
wr_addr_pipe <=3'b0;
end
else if (awvalid_m_reg && awready_m && bwtrns_complete) begin
wr_addr_pipe <= wr_addr_pipe;
end
else if (awvalid_m_reg && awready_m) begin
wr_addr_pipe <= wr_addr_pipe + 1;
end
else if (bwtrns_complete) begin
wr_addr_pipe <= wr_addr_pipe - 1;
end
end
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge) begin
wr_addr_pend <=1'b0;
end
else if (awvalid_m_reg && ~awready_m) begin
wr_addr_pend <=1'b1;
end
else if (awvalid_m_reg && awready_m) begin
wr_addr_pend <= 1'b0;
end
end
wire launch_awaddr;
assign wtrns_complete = wlast_reg & wvalid_m & wready_m;
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge) begin
wr_data_queue <=3'b0;
end
else if (launch_awaddr & wtrns_complete) begin
wr_data_queue <= wr_data_queue;
end
else if (launch_awaddr ) begin
wr_data_queue <= wr_data_queue + 1;
end
else if (wtrns_complete) begin
wr_data_queue <= wr_data_queue - 1;
end
end
wire [C_M_AXI_DATA_WIDTH-1:0] test_data ;
assign test_data= {
32'h12A0_A51F, 32'hCAFE_5AFE,
32'hC001_A51F, 32'hC001_CA5E,
32'hC001_12AF, 32'h5AFE_5AFE,
32'hA51F_A51F, 32'h5AFE_CAFE,
32'h12A0_12A0, 32'hCAFE_C001,
32'hA51F_12A0, 32'hC001_CAFE,
32'hCAA1_A51F, 32'hCAFE_A51F,
32'hCAA1_12a0, 32'hC001_5AFE
};
// WData logic
always @(posedge Clk) begin
if (~rst_l ) begin
wvalid_m_reg <= 1'b0;
wdata_m_reg <= {C_M_AXI_DATA_WIDTH{1'b0}};
end else if (wvalid_m_reg && wready_m && wlast_reg) begin
wvalid_m_reg <= 1'b0;
//end else if (((awvalid_m_reg && awready_m)|| (wr_addr_pipe > 0)) && ~wlast_reg) begin
//end else if (((st_en_reg_edge)|
// ((wr_addr_pipe == 3'h0 )&(launch_awaddr))|
// ((wr_addr_pipe > 0) &(wr_addr_pipe <C_ATG_STATIC_WR_PIPELINE))) && ~wlast_reg) begin
end else if ( wr_data_queue >0 ) begin
wvalid_m_reg <= 1'b1;
wdata_m_reg <= test_data[C_M_AXI_DATA_WIDTH-1:0];
//end else if ( wr_addr_pipe == 1 && wlast_reg && wready_m) begin
// wvalid_m_reg <= 1'b0;
// wdata_m_reg <= {C_M_AXI_DATA_WIDTH{1'b0}};
end else begin
wdata_m_reg <= wdata_m_reg;
wvalid_m_reg <= wvalid_m_reg;
end
end
always @(posedge Clk) begin
if (~rst_l) begin
wlast_cnt_reg <= 8'b0;
wlast_reg <= 1'b0;
end
else if (wlast_reg & wready_m & wvalid_m) begin
wlast_cnt_reg <= 8'b0;
wlast_reg <= 1'b0;
end
// len=0 case, generate wlast along with wvalid
//else if (((awvalid_m_reg && awready_m)|| wr_addr_pipe > 0) && ~wlast_reg && (burst_len == 0)) begin
//else if (((st_en_reg_edge)|| wr_addr_pipe > 0) && ~wlast_reg && (burst_len == 0)) begin
else if ( (wr_data_queue >0 )& (burst_len == 0) ) begin
wlast_cnt_reg <= 8'b0;
wlast_reg <= 1'b1;
end
else if (wvalid_m_reg && wready_m) begin
wlast_cnt_reg <= wlast_cnt_reg + 1;
wlast_reg <= (wlast_cnt_reg + 1 == burst_len);
end
end
// Write Response Logic
always @(posedge Clk) begin
if (~rst_l) begin
bready_m_reg <=1'b0;
end
else if (awvalid_m_reg) begin
bready_m_reg <=1'b1;
end
else if (bvalid_m) begin
bready_m_reg <=1'b1;
end
end
//
//2013.3: Traffic Profiles.
//Counter to count required no.of Clocks
//
reg [31:0] tran_gap_wcntr;
reg awvalid_m_reg_ff;
wire awaddr_sampled;
reg awaddr_sampled_reg;
assign awaddr_sampled = awvalid_m & awready_m;
always @(posedge Clk) begin
if (~rst_l ) begin
awvalid_m_reg_ff <= 1'b0;
awaddr_sampled_reg <= 1'b0;
end else begin
awvalid_m_reg_ff <= awvalid_m_reg;
awaddr_sampled_reg <= awaddr_sampled;
end
end
assign launch_awaddr = (awvalid_m_reg & ~awvalid_m_reg_ff) |(awaddr_sampled_reg & awvalid_m_reg);
always @(posedge Clk) begin
if (~rst_l ) begin
tran_gap_wcntr <= 32'h0;
end else if (launch_awaddr) begin
tran_gap_wcntr <= 32'h0;
end else if (tran_gap_wcntr == C_ATG_STATIC_TRANGAP ) begin
tran_gap_wcntr <= tran_gap_wcntr;
end else begin
tran_gap_wcntr <= tran_gap_wcntr + 1;
end
end
assign launch_nxt_wtrn = (tran_gap_wcntr == C_ATG_STATIC_TRANGAP) ? 1'b1: 1'b0;
end
endgenerate // ATG_MODE_STATIC_WR_ON
generate if(C_ATG_STATIC_EN_WRITE == 0) begin : ATG_MODE_STATIC_WR_OFF
assign awid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] = 'h0;
assign awaddr_m = 'h0;
assign awlen_m = 'h0;
assign awprot_m = 'h0;
assign awlock_m[0:0] = 'h0;
assign awcache_m = 'h0;
assign awuser_m[C_M_AXI_AWUSER_WIDTH-1:0] = 'h0;
assign awqos_m[3:0] = 'h0;
assign awburst_m = 'h0;
assign awsize_m = 'h0;
assign awvalid_m = 'h0;
assign wlast_m = 'h0;
assign wdata_m = 'h0;
assign wstrb_m = 'h0;
assign wvalid_m = 'h0;
assign bready_m = 'h0;
always @(posedge Clk) begin
wr_addr_pipe <=3'b0;
wr_addr_pend <=1'b0;
end
end
endgenerate // ATG_MODE_STATIC_WR_OFF
//*************************** READ Master Interface*******************************
// Enable this based on generic C_ATG_STATIC_EN_READ
reg arvalid_m_reg;
reg [31:0] araddr_m_reg;
reg [31:0] araddr_m_reg_incr;
reg [31:0] araddr_nxt_chk;
reg [12:0] cmdr_addrincr_ff;
reg [31:0] araddr_inc_reg;
reg [7:0] arlen_m_reg;
reg rlast_reg;
reg [31:0] read_four_k;
reg [7:0] rlast_cnt_reg;
reg rready_m_reg;
reg [2:0] rd_addr_pipe;
reg rd_addr_pend;
wire [12:0] cmdr_addrincr = (burst_len+1) << param_incr_shift;
generate if(C_ATG_STATIC_EN_READ == 1) begin : ATG_MODE_STATIC_RD_ON
assign arid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] = {C_M_AXI_THREAD_ID_WIDTH{1'b0}};
assign arlen_m[7:0] = arlen_m_reg;
assign araddr_m[31:0] = (C_ATG_STATIC_INCR == 0) ? araddr_m_reg : araddr_m_reg_incr;
assign arvalid_m = arvalid_m_reg;
assign arlock_m[0:0] = 1'b0;
assign arburst_m[1:0] = 2'b01;
assign arprot_m[2:0] = 3'b000;
assign arcache_m[3:0] = 4'b0011;
assign aruser_m[C_M_AXI_ARUSER_WIDTH-1:0] = {C_M_AXI_ARUSER_WIDTH{1'b0}};
assign arqos_m[3:0] = 4'h0;
assign arsize_m = (C_M_AXI_DATA_WIDTH==32) ? 3'b010 :
(C_M_AXI_DATA_WIDTH==64) ? 3'b011 :
(C_M_AXI_DATA_WIDTH==128) ? 3'b100 :
(C_M_AXI_DATA_WIDTH==256) ? 3'b101 :3'b110;
assign rready_m = rready_m_reg;
always @(posedge Clk) begin
if (~rst_l) begin
araddr_nxt_chk <= C_ATG_STATIC_RD_ADDRESS;
cmdr_addrincr_ff <= cmdr_addrincr;
end
else begin
cmdr_addrincr_ff <= cmdr_addrincr;
araddr_nxt_chk <= cmdr_addrincr_ff + cmdr_addrincr_ff;
end
end
// Read Master Logic
wire launch_nxt_rtrn;
always @(posedge Clk) begin
if (~rst_l) begin
arvalid_m_reg <= 1'b0;
araddr_m_reg <= 32'b0;
araddr_m_reg_incr <= 32'b0;
arlen_m_reg <= 8'b0;
read_four_k <= 32'b0;
end else if (st_en_reg_edge) begin
arvalid_m_reg <= 1'b1;
araddr_m_reg <= C_ATG_STATIC_RD_ADDRESS;
araddr_m_reg_incr <= C_ATG_STATIC_RD_ADDRESS;
arlen_m_reg <= burst_len;
read_four_k <= C_ATG_STATIC_RD_ADDRESS + 32'd4096;
end else if (arvalid_m_reg & ~arready_m) begin
arvalid_m_reg <= arvalid_m_reg;
araddr_m_reg <= C_ATG_STATIC_RD_ADDRESS;
araddr_m_reg_incr <= araddr_m_reg_incr;
arlen_m_reg <= burst_len;
read_four_k <= read_four_k;
end else if (( rd_addr_pipe == C_ATG_STATIC_RD_PIPELINE-1) && arvalid_m && arready_m ) begin
arvalid_m_reg <= 1'b0;
araddr_m_reg <= 32'b0;
araddr_m_reg_incr <= araddr_m_reg_incr;
arlen_m_reg <= 8'b0;
read_four_k <= read_four_k;
end else if ((rd_addr_pipe < C_ATG_STATIC_RD_PIPELINE) ) begin
arvalid_m_reg <= st_en_reg1 & ~glcnt_done & launch_nxt_rtrn;
araddr_m_reg <= C_ATG_STATIC_RD_ADDRESS;
arlen_m_reg <= burst_len;
if (~(st_en_reg1 & ~glcnt_done & launch_nxt_rtrn)) begin
araddr_m_reg_incr <= araddr_m_reg_incr;
read_four_k <= read_four_k;
end else if (araddr_nxt_chk + araddr_m_reg_incr > C_ATG_STATIC_RD_HIGH_ADDRESS_C) begin
araddr_m_reg_incr <= C_ATG_STATIC_RD_ADDRESS;
read_four_k <= C_ATG_STATIC_RD_ADDRESS + 32'd4096;
end else if (araddr_nxt_chk + araddr_m_reg_incr > read_four_k) begin
araddr_m_reg_incr <= read_four_k;
read_four_k <= read_four_k + 32'd4096;
end else begin
araddr_m_reg_incr <= araddr_m_reg_incr + cmdr_addrincr;
read_four_k <= read_four_k;
end
end
end
// Read Address Pipeline
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge) begin
rd_addr_pipe <=3'b0;
end
else if (arvalid_m_reg && arready_m && rlast_reg && rvalid_m && rready_m) begin
rd_addr_pipe <= rd_addr_pipe;
end
else if (arvalid_m_reg && arready_m) begin
rd_addr_pipe <= rd_addr_pipe + 1;
end
else if (rlast_reg && rvalid_m && rready_m) begin
rd_addr_pipe <= rd_addr_pipe - 1;
end
end
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge) begin
rd_addr_pend <=1'b0;
end
else if (arvalid_m_reg && ~arready_m) begin
rd_addr_pend <=1'b1;
end
else if (arvalid_m_reg && arready_m) begin
rd_addr_pend <= 1'b0;
end
end
// Pend Read Logic
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge) begin
rready_m_reg <=1'b1;
end else if (rlast_m && rvalid_m && rready_m && ~arvalid_m && (stop_generation || glcnt_done) && (rd_addr_pipe == 1)) begin
rready_m_reg <= 1'b0;
end else if (~arvalid_m && (stop_generation || glcnt_done) && (rd_addr_pipe == 0)) begin
rready_m_reg <= 1'b0;
end
end
always @(rlast_m) begin
rlast_reg = rlast_m;
end
//
//2013.3: Traffic Profiles.
//Counter to count required no.of Clocks
//
reg [31:0] tran_gap_rcntr;
reg arvalid_m_reg_ff;
wire araddr_sampled;
reg araddr_sampled_reg;
wire launch_araddr;
assign araddr_sampled = arvalid_m & arready_m;
always @(posedge Clk) begin
if (~rst_l ) begin
arvalid_m_reg_ff <= 1'b0;
araddr_sampled_reg <= 1'b0;
end else begin
arvalid_m_reg_ff <= arvalid_m_reg;
araddr_sampled_reg <= araddr_sampled;
end
end
assign launch_araddr = (arvalid_m_reg & ~arvalid_m_reg_ff) |(araddr_sampled_reg & arvalid_m_reg);
always @(posedge Clk) begin
if (~rst_l ) begin
tran_gap_rcntr <= 32'h0;
end else if (launch_araddr) begin
tran_gap_rcntr <= 32'h0;
end else if (tran_gap_rcntr == C_ATG_STATIC_TRANGAP ) begin
tran_gap_rcntr <= tran_gap_rcntr;
end else begin
tran_gap_rcntr <= tran_gap_rcntr + 1;
end
end
assign launch_nxt_rtrn = (tran_gap_rcntr == C_ATG_STATIC_TRANGAP) ? 1'b1: 1'b0;
end
endgenerate // ATG_MODE_STATIC_RD_ON
generate if(C_ATG_STATIC_EN_READ == 0) begin : ATG_MODE_STATIC_RD_OFF
assign arid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] = 'h0 ;
assign arlen_m[7:0] = 'h0 ;
assign araddr_m[31:0] = 'h0 ;
assign arvalid_m = 'h0 ;
assign arlock_m[0:0] = 'h0 ;
assign arburst_m[1:0] = 'h0 ;
assign arprot_m[2:0] = 'h0 ;
assign arcache_m[3:0] = 'h0 ;
assign aruser_m[C_M_AXI_ARUSER_WIDTH-1:0] = 'h0 ;
assign arqos_m[3:0] = 'h0 ;
assign arsize_m = 'h0 ;
assign rready_m = 'h0 ;
always @(posedge Clk) begin
rd_addr_pipe <=3'b0;
rd_addr_pend <=1'b0;
end
end
endgenerate // ATG_MODE_STATIC_RD_OFF
//**********************Counter Logic*************************
//
reg [31:0] rdcnt_reg;
reg [31:0] wrcnt_reg;
generate if(C_ATG_STATIC_FREE_RUN == 0) begin : ATG_MODE_STATIC_DEBUG_ON
assign reg3_rdcnt = rdcnt_reg;
assign reg4_wrcnt = wrcnt_reg;
assign reg5_glcnt = glcnt_reg;
end
endgenerate // ATG_MODE_STATIC_DEBUG_ON
generate if(C_ATG_STATIC_FREE_RUN == 1) begin : ATG_MODE_STATIC_DEBUG_OFF
assign reg3_rdcnt = 32'h0;
assign reg4_wrcnt = 32'h0;
assign reg5_glcnt = 32'h0;
end
endgenerate // ATG_MODE_STATIC_DEBUG_ON
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge) begin
rdcnt_reg <= 32'b0;
end else if (glcnt_done) begin
rdcnt_reg <= rdcnt_reg ;
end else if (rlast_reg && rvalid_m) begin
rdcnt_reg <= rdcnt_reg + 1;
end
end
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge) begin
wrcnt_reg <= 32'b0;
end else if (glcnt_done) begin
wrcnt_reg <= wrcnt_reg;
end else if (wlast_reg && wready_m) begin
wrcnt_reg <= wrcnt_reg + 1;
end
end
always @(posedge Clk) begin
if (~rst_l || st_en_reg_edge || reset_reg1_done) begin
glcnt_reg <= 32'h0;
end else if (glcnt_done) begin
glcnt_reg <= 32'hFFFFFFFF;
end else if (~done && st_en_reg1 ) begin
glcnt_reg <= glcnt_reg + 1;
end
end
//done- generation
generate if(C_ATG_STATIC_FREE_RUN == 1) begin : ATG_MODE_STATIC_DEBUG_OFF_DONE
always @(posedge Clk) begin
if (~rst_l ) begin
done <= 1'b0;
end else if ((st_en_reg_edge == 1'b1) || (reset_reg1_done == 1'b1)) begin
done <= 1'b0;
//set done bit when a. Core disabled
// provided the last read/write transaction got completed.
end else if ((stop_generation) &&
(~wvalid_m && ~wr_addr_pend && (wr_addr_pipe == 0)) &&
(~rready_m && ~rd_addr_pend && (rd_addr_pipe == 0))
) begin
done <= 1'b1;
end
end
end
endgenerate // ATG_MODE_STATIC_DEBUG_ON_DONE
generate if(C_ATG_STATIC_FREE_RUN == 0) begin : ATG_MODE_STATIC_DEBUG_ON_DONE
always @(posedge Clk) begin
if (~rst_l ) begin
done <= 1'b0;
end else if ((st_en_reg_edge == 1'b1) || (reset_reg1_done == 1'b1)) begin
done <= 1'b0;
//set done bit when a.Global counter reached max limit or b. Core disabled
// provided the last read/write transaction got completed.
end else if (((glcnt_done)||(stop_generation)) &&
(~wvalid_m && ~wr_addr_pend && (wr_addr_pipe == 0)) &&
(~rready_m && ~rd_addr_pend && (rd_addr_pipe == 0))
) begin
done <= 1'b1;
end
end
end
endgenerate // ATG_MODE_STATIC_DEBUG_OFF_DONE
endmodule
|
// file: ibert_7series_gtx_0.v
//////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 2012.3
// \ \ Application : IBERT 7Series
// / / Filename : example_ibert_7series_gtx_0
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module example_ibert_7series_gtx_0
// Generated by Xilinx IBERT_7S
//////////////////////////////////////////////////////////////////////////////
`define C_NUM_QUADS 1
`define C_REFCLKS_USED 0
module onetswitch_top
(
// GT top level ports
output [(4*`C_NUM_QUADS)-1:0] TXN_O,
output [(4*`C_NUM_QUADS)-1:0] TXP_O,
input [(4*`C_NUM_QUADS)-1:0] RXN_I,
input [(4*`C_NUM_QUADS)-1:0] RXP_I,
input [`C_REFCLKS_USED-1:0] GTREFCLK0P_I,
input [`C_REFCLKS_USED-1:0] GTREFCLK0N_I,
input [`C_REFCLKS_USED-1:0] GTREFCLK1P_I,
input [`C_REFCLKS_USED-1:0] GTREFCLK1N_I
);
//
// Ibert refclk internal signals
//
wire [`C_NUM_QUADS-1:0] gtrefclk0_i;
wire [`C_NUM_QUADS-1:0] gtrefclk1_i;
wire [`C_REFCLKS_USED-1:0] refclk0_i;
wire [`C_REFCLKS_USED-1:0] refclk1_i;
//
// Refclk IBUFDS instantiations
//
IBUFDS_GTE2 #(
.CLKCM_CFG("TRUE"), // Refer to Transceiver User Guide
.CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
.CLKSWING_CFG(2'b11) // Refer to Transceiver User Guide
)
IBUFDS_GTE2_inst0 (
.O(gtrefclk0_i), // 1-bit output: Refer to Transceiver User Guide
.ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide
.CEB(1'b0), // 1-bit input: Refer to Transceiver User Guide
.I(GTREFCLK0P_I[0]), // 1-bit input: Refer to Transceiver User Guide
.IB(GTREFCLK0N_I[0]) // 1-bit input: Refer to Transceiver User Guide
);
IBUFDS_GTE2 #(
.CLKCM_CFG("TRUE"), // Refer to Transceiver User Guide
.CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
.CLKSWING_CFG(2'b11) // Refer to Transceiver User Guide
)
IBUFDS_GTE2_inst1 (
.O(gtrefclk1_i), // 1-bit output: Refer to Transceiver User Guide
.ODIV2(ODIV2), // 1-bit output: Refer to Transceiver User Guide
.CEB(1'b0), // 1-bit input: Refer to Transceiver User Guide
.I(GTREFCLK1P_I[0]), // 1-bit input: Refer to Transceiver User Guide
.IB(GTREFCLK1N_I[0]) // 1-bit input: Refer to Transceiver User Guide
);
//
//
// Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
//
//
// IBERT core instantiation
//
ibert_7series_gtx_0 u_ibert_core
(
.TXN_O(TXN_O),
.TXP_O(TXP_O),
.RXN_I(RXN_I),
.RXP_I(RXP_I),
.GTREFCLK0_I(gtrefclk0_i),
.GTREFCLK1_I(gtrefclk1_i)
);
endmodule
|
//
// Paul Gao 02/2021
//
// This is the receiver part of bsg_link_sdr, an SDR communication endpoint
// over single source-synchronous channel.
//
// Typical usage: Communication between different hierarchical blocks in
// different clock domains on ASIC. In this way the clock trees can be
// fully independent in different hierarchical blocks.
//
//
// General reset procedures:
//
// Step 1: Assert io_link_reset and core_link_reset.
// Step 2: async_token_reset must be posedge/negedge toggled (0->1->0)
// at least once. token_clk_i cannot toggle during this step.
// Step 3: io_clk_i posedge toggled at least four times after that.
// Step 4: De-assert upstream_io_link_reset to generate io_clk_o.
// Step 5: De-assert downstream_io_link_reset.
// Step 6: De-assert downstream_core_link_reset.
//
// *************************************************************************
// async upstream downstream downstream
// token_reset io_link_reset io_link_reset core_link_reset
// Step 1 0 1 1 1
// Step 2 1 1 1 1
// Step 3 0 1 1 1
// Step 4 0 0 1 1
// Step 5 0 0 0 1
// Step 6 0 0 0 0
// *************************************************************************
//
module bsg_link_sdr_downstream
#(parameter `BSG_INV_PARAM(width_p )
// Receive fifo depth
// MUST MATCH paired bsg_link_ddr_upstream setting
,parameter lg_fifo_depth_p = 3
// Token credit decimation
// MUST MATCH paired bsg_link_ddr_upstream setting
,parameter lg_credit_to_token_decimation_p = 0
,parameter bypass_twofer_fifo_p = 0
)
(// Core side
input core_clk_i
,input core_link_reset_i
,output core_v_o
,output [width_p-1:0] core_data_o
,input core_yumi_i
// IO side
,input async_io_link_reset_i
,input io_clk_i
,input io_v_i
,input [width_p-1:0] io_data_i
,output core_token_r_o
);
logic isdr_clk_lo, isdr_v_lo;
logic [width_p-1:0] isdr_data_lo;
// valid and data signals are received together
bsg_link_isdr_phy
#(.width_p(width_p+1)
) isdr_phy
(.clk_i (io_clk_i)
,.clk_o (isdr_clk_lo)
,.data_i ({io_v_i, io_data_i})
,.data_o ({isdr_v_lo, isdr_data_lo})
);
logic io_link_reset_sync;
bsg_sync_sync #(.width_p(1)) bss
(.oclk_i (isdr_clk_lo )
,.iclk_data_i(async_io_link_reset_i)
,.oclk_data_o(io_link_reset_sync )
);
bsg_link_source_sync_downstream
#(.channel_width_p(width_p)
,.lg_fifo_depth_p(lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p(bypass_twofer_fifo_p)
) downstream
(.core_clk_i (core_clk_i)
,.core_link_reset_i(core_link_reset_i)
,.io_link_reset_i (io_link_reset_sync)
// source synchronous input channel
,.io_clk_i (isdr_clk_lo)
,.io_data_i (isdr_data_lo)
,.io_valid_i (isdr_v_lo)
,.core_token_r_o (core_token_r_o)
// going into core
,.core_data_o (core_data_o)
,.core_valid_o (core_v_o)
,.core_yumi_i (core_yumi_i)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_link_sdr_downstream)
|
//*******************************************************************************************
//Author: Yejoong Kim
//Last Modified: Jul 26 2017
//Description: MBus Member Controller
// Structural verilog netlist using sc_x_hvt_tsmc90
//Update History: Jul 26 2017 - First added in MBus r04p2
//*******************************************************************************************
module lname_mbus_member_ctrl (
input RESETn,
// MBus Clock & Data
input CIN,
input DIN,
input COUT_FROM_BUS,
input DOUT_FROM_BUS,
output COUT,
output DOUT,
// Sleep & Wakeup Requests
input SLEEP_REQ,
input WAKEUP_REQ,
// Power-Gating Signals
output MBC_ISOLATE,
output MBC_ISOLATE_B,
output MBC_RESET,
output MBC_RESET_B,
output MBC_SLEEP,
output MBC_SLEEP_B,
// Handshaking with MBus Ctrl
input CLR_EXT_INT,
output EXTERNAL_INT,
// Short-Prefix
input ADDR_WR_EN,
input ADDR_CLR_B,
input [3:0] ADDR_IN,
output [3:0] ADDR_OUT,
output ADDR_VALID,
// Misc
input LRC_SLEEP,
input MBUS_BUSY
);
//****************************************************************************
// Internal Wire Declaration
//****************************************************************************
wire cin_b;
wire cin_buf;
wire mbc_sleep_b_int;
wire mbc_isolate_b_int;
wire mbc_reset_b_int;
wire next_mbc_isolate;
wire next_mbc_isolate_b;
wire sleep_req_isol;
wire sleep_req_b_isol;
wire mbc_isolate_int;
wire mbc_sleep_int;
wire goingsleep;
wire mbc_reset_int;
wire clr_ext_int_iso;
wire clr_ext_int_b;
wire RESETn_local;
wire RESETn_local2;
wire mbus_busy_b_isol;
wire int_busy;
wire int_busy_b;
wire ext_int_dout;
wire cout_from_bus_iso;
wire cout_int;
wire cout_unbuf;
wire dout_from_bus_iso;
wire dout_int_1;
wire dout_int_0;
wire dout_unbuf;
wire addr_clr_b_iso;
wire [3:0] addr_in_iso;
wire RESETn_local3;
wire addr_update;
// ---------------------------------------------
// NOTE: Functional Relationship:
// ---------------------------------------------
// MBC_ISOLATE = mbc_isolate_int
// MBC_ISOLATE_B = mbc_isolate_b_int
// MBC_RESET = mbc_reset_int
// MBC_RESET_B = mbc_reset_b_int
// MBC_SLEEP = mbc_sleep_int
// MBC_SLEEP_B = mbc_sleep_b_int
// ---------------------------------------------
// clr_ext_int_b = ~clr_ext_int_iso
// ---------------------------------------------
//****************************************************************************
// GLOBAL
//****************************************************************************
// CIN Buffer
INVX1HVT_TSMC90 INV_cin_b (.Y(cin_b), .A(CIN));
INVX2HVT_TSMC90 INV_cin_buf (.Y(cin_buf), .A(cin_b));
//****************************************************************************
// SLEEP CONTROLLER
//****************************************************************************
//assign MBC_SLEEP_B = ~MBC_SLEEP;
INVX1HVT_TSMC90 INV_mbc_sleep_b_int (.Y(mbc_sleep_b_int), .A(mbc_sleep_int));
INVX8HVT_TSMC90 INV_MBC_SLEEP (.Y(MBC_SLEEP), .A(mbc_sleep_b_int));
INVX8HVT_TSMC90 INV_MBC_SLEEP_B (.Y(MBC_SLEEP_B), .A(mbc_sleep_int));
//assign MBC_ISOLATE_B = ~MBC_ISOLATE;
INVX1HVT_TSMC90 INV_mbc_isolate_b_int (.Y(mbc_isolate_b_int), .A(mbc_isolate_int));
INVX8HVT_TSMC90 INV_MBC_ISOLATE (.Y(MBC_ISOLATE), .A(mbc_isolate_b_int));
INVX8HVT_TSMC90 INV_MBC_ISOLATE_B (.Y(MBC_ISOLATE_B), .A(mbc_isolate_int));
//assign MBC_RESET_B = ~MBC_RESET;
INVX1HVT_TSMC90 INV_mbc_reset_b_int (.Y(mbc_reset_b_int), .A(mbc_reset_int));
INVX8HVT_TSMC90 INV_MBC_RESET (.Y(MBC_RESET), .A(mbc_reset_b_int));
INVX8HVT_TSMC90 INV_MBC_RESET_B (.Y(MBC_RESET_B), .A(mbc_reset_int));
//assign next_mbc_isolate = goingsleep | sleep_req_isol | MBC_SLEEP;
INVX1HVT_TSMC90 INV_next_mbc_isolate (.Y(next_mbc_isolate), .A(next_mbc_isolate_b));
NOR3X1HVT_TSMC90 NOR3_next_mbc_isolate_b (.C(goingsleep), .B(sleep_req_isol), .A(mbc_sleep_int), .Y(next_mbc_isolate_b));
//assign sleep_req_isol = SLEEP_REQ & MBC_ISOLATE_B;
INVX1HVT_TSMC90 INV_next_goingsleep (.Y(sleep_req_isol), .A(sleep_req_b_isol));
NAND2X1HVT_TSMC90 NAND2_next_goingsleep_b (.Y(sleep_req_b_isol), .A(SLEEP_REQ), .B(mbc_isolate_b_int));
// goingsleep, mbc_sleep_int, mbc_isolate_int, mbc_reset_int
DFFRNSNX1HVT_TSMC90 DFFSR_mbc_isolate_int (.SN(RESETn), .RN(1'b1), .CLK(cin_buf), .Q(mbc_isolate_int), .QN(), .D(next_mbc_isolate));
DFFRNSNX1HVT_TSMC90 DFFSR_mbc_sleep_int (.SN(RESETn), .RN(1'b1), .CLK(cin_buf), .Q(mbc_sleep_int), .QN(), .D(goingsleep));
DFFRNSNX1HVT_TSMC90 DFFSR_goingsleep (.SN(1'b1), .RN(RESETn), .CLK(cin_buf), .Q(goingsleep), .QN(), .D(sleep_req_isol));
DFFRNSNX1HVT_TSMC90 DFFSR_mbc_reset_int (.SN(RESETn), .RN(1'b1), .CLK(cin_b), .Q(mbc_reset_int), .QN(), .D(mbc_isolate_int));
//****************************************************************************
// INTERRUPT CONTROLLER
//****************************************************************************
//wire clr_ext_int_b = ~(MBC_ISOLATE_B & CLR_EXT_INT);
AND2X1HVT_TSMC90 AND2_clr_ext_int_iso (.Y(clr_ext_int_iso), .A(MBC_ISOLATE_B), .B(CLR_EXT_INT));
INVX1HVT_TSMC90 INV_clr_ext_int_b (.Y(clr_ext_int_b), .A(clr_ext_int_iso));
//wire RESETn_local = RESETn & CIN;
AND2X1HVT_TSMC90 AND2_RESETn_local (.Y(RESETn_local), .A(CIN), .B(RESETn));
//wire RESETn_local2 = RESETn & clr_ext_int_b;
AND2X1HVT_TSMC90 AND2_RESETn_local2 (.Y(RESETn_local2), .A(clr_ext_int_b), .B(RESETn));
//wire mbus_busy_b_isol = ~(MBUS_BUSY & MBC_RESET_B);
NAND2X1HVT_TSMC90 NAND2_mbus_busy_b_isol (.A(MBUS_BUSY), .B(mbc_reset_b_int), .Y(mbus_busy_b_isol));
//wire int_busy = (WAKEUP_REQ & mbus_busy_b_isol & LRC_SLEEP)
NAND3X1HVT_TSMC90 NAND3_int_busy_b (.A(WAKEUP_REQ), .B(mbus_busy_b_isol), .C(LRC_SLEEP), .Y(int_busy_b));
INVX2HVT_TSMC90 INV_int_busy (.Y(int_busy), .A(int_busy_b));
// ext_int_dout
DFFRNX1HVT_TSMC90 DFFR_ext_int_dout (.RN(RESETn_local), .CLK(int_busy), .Q(ext_int_dout), .QN(), .D(1'b1));
// EXTERNAL_INT
DFFRNX1HVT_TSMC90 DFFR_EXTERNAL_INT (.RN(RESETn_local2), .CLK(int_busy), .Q(EXTERNAL_INT), .QN(), .D(1'b1));
//****************************************************************************
// WIRE CONTROLLER
//****************************************************************************
// COUT
OR2X1HVT_TSMC90 OR2_cout_from_bus_iso (.Y(cout_from_bus_iso), .A(COUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2X1HVT_TSMC90 MUX2_cout_int (.S0(MBC_ISOLATE), .A(cout_from_bus_iso), .Y(cout_int), .B(CIN));
MUX2X1HVT_TSMC90 MUX2_cout_unbuf (.S0(RESETn), .A(1'b1), .Y(cout_unbuf), .B(cout_int));
BUFX4HVT_TSMC90 BUF_COUT (.A(cout_unbuf), .Y(COUT));
// DOUT
OR2X1HVT_TSMC90 OR2_dout_from_bus_iso (.Y(dout_from_bus_iso), .A(DOUT_FROM_BUS), .B(MBC_ISOLATE));
MUX2X1HVT_TSMC90 MUX2_dout_int_1 (.S0(MBC_ISOLATE), .A(dout_from_bus_iso), .Y(dout_int_1), .B(DIN));
MUX2X1HVT_TSMC90 MUX2_dout_int_0 (.S0(ext_int_dout), .A(dout_int_1), .Y(dout_int_0), .B(1'b0));
MUX2X1HVT_TSMC90 MUX2_dout_unbuf (.S0(RESETn), .A(1'b1), .Y(dout_unbuf), .B(dout_int_0));
BUFX4HVT_TSMC90 BUF_DOUT (.A(dout_unbuf), .Y(DOUT));
//****************************************************************************
// SHORT-PREFIX ADDRESS REGISTER
//****************************************************************************
// Isolation
OR2X1HVT_TSMC90 AND2_addr_clr_b_iso (.A(MBC_ISOLATE), .B(ADDR_CLR_B), .Y(addr_clr_b_iso));
AND2X1HVT_TSMC90 AND2_addr_in_iso_0 (.A(MBC_ISOLATE_B), .B(ADDR_IN[0]), .Y(addr_in_iso[0]));
AND2X1HVT_TSMC90 AND2_addr_in_iso_1 (.A(MBC_ISOLATE_B), .B(ADDR_IN[1]), .Y(addr_in_iso[1]));
AND2X1HVT_TSMC90 AND2_addr_in_iso_2 (.A(MBC_ISOLATE_B), .B(ADDR_IN[2]), .Y(addr_in_iso[2]));
AND2X1HVT_TSMC90 AND2_addr_in_iso_3 (.A(MBC_ISOLATE_B), .B(ADDR_IN[3]), .Y(addr_in_iso[3]));
//wire RESETn_local3 = (RESETn & ADDR_CLR_B);
AND2X1HVT_TSMC90 AND2_RESETn_local3 (.A(RESETn), .B(addr_clr_b_iso), .Y(RESETn_local3));
//wire addr_update = (ADDR_WR_EN & (~MBC_ISOLATE));
AND2X1HVT_TSMC90 AND2_addr_update (.A(MBC_ISOLATE_B), .B(ADDR_WR_EN), .Y(addr_update));
// ADDR_OUT, ADDR_VALID
DFFSNX1HVT_TSMC90 DFFS_ADDR_OUT_0 (.CLK(addr_update), .D(addr_in_iso[0]), .SN(RESETn_local3), .Q(ADDR_OUT[0]), .QN());
DFFSNX1HVT_TSMC90 DFFS_ADDR_OUT_1 (.CLK(addr_update), .D(addr_in_iso[1]), .SN(RESETn_local3), .Q(ADDR_OUT[1]), .QN());
DFFSNX1HVT_TSMC90 DFFS_ADDR_OUT_2 (.CLK(addr_update), .D(addr_in_iso[2]), .SN(RESETn_local3), .Q(ADDR_OUT[2]), .QN());
DFFSNX1HVT_TSMC90 DFFS_ADDR_OUT_3 (.CLK(addr_update), .D(addr_in_iso[3]), .SN(RESETn_local3), .Q(ADDR_OUT[3]), .QN());
DFFRNX1HVT_TSMC90 DFFR_ADDR_VALID (.CLK(addr_update), .D(1'b1), .RN(RESETn_local3), .Q(ADDR_VALID), .QN());
endmodule // lname_mbus_member_ctrl
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_clamp(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [10:0] tex_hres,
input [10:0] tex_vres,
input [10:0] dst_hres,
input [10:0] dst_vres,
output reg pipe_stb_o,
input pipe_ack_i,
output reg [10:0] dx_c,
output reg [10:0] dy_c,
output reg [16:0] tx_c,
output reg [16:0] ty_c
);
always @(posedge sys_clk) begin
if(sys_rst)
pipe_stb_o <= 1'b0;
else begin
if(pipe_ack_i)
pipe_stb_o <= 1'b0;
if(pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= (~dx[11]) && (dx[10:0] < dst_hres)
&& (~dy[11]) && (dy[10:0] < dst_vres);
dx_c <= dx[10:0];
dy_c <= dy[10:0];
if(tx[17])
tx_c <= 17'd0;
else if(tx[16:0] > {tex_hres - 11'd1, 6'd0})
tx_c <= {tex_hres - 11'd1, 6'd0};
else
tx_c <= tx[16:0];
if(ty[17])
ty_c <= 17'd0;
else if(ty[16:0] > {tex_vres - 11'd1, 6'd0})
ty_c <= {tex_vres - 11'd1, 6'd0};
else
ty_c <= ty[16:0];
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
|
module cn0363_phase_data_sync (
input clk,
input resetn,
input processing_resetn,
output s_axis_sample_ready,
input s_axis_sample_valid,
input [7:0] s_axis_sample_data,
input sample_has_stat,
input conv_done,
input [31:0] phase,
output reg m_axis_sample_valid,
input m_axis_sample_ready,
output [23:0] m_axis_sample_data,
output reg m_axis_phase_valid,
input m_axis_phase_ready,
output [31:0] m_axis_phase_data,
output reg overflow
);
reg [1:0] data_counter = 'h00;
reg [31:0] phase_hold = 'h00;
reg [23:0] sample_hold = 'h00;
reg sample_hold_valid = 1'b0;
reg conv_done_d1 = 1'b0;
reg synced = 1'b0;
wire sync;
/* The ADC will do conversions regardless of whether the pipeline is ready or
not. So we'll always accept new samples and assert overflow if necessary if
the pipeline is not ready. */
assign s_axis_sample_ready = 1'b1;
// Conversion from offset binary to signed on data
assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]};
assign m_axis_phase_data = phase_hold;
always @(posedge clk) begin
if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin
// Is the processing pipeline ready to accept data?
if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin
overflow <= 1'b1;
end else begin
phase_hold <= phase;
overflow <= 1'b0;
end
end else begin
overflow <= 1'b0;
end
conv_done_d1 <= conv_done;
end
always @(posedge clk) begin
if (processing_resetn == 1'b0) begin
m_axis_phase_valid <= 1'b0;
m_axis_sample_valid <= 1'b0;
end else begin
/* Data and phase become valid once we have both */
if (sample_hold_valid == 1'b1) begin
m_axis_phase_valid <= 1'b1;
m_axis_sample_valid <= 1'b1;
end else begin
if (m_axis_phase_ready == 1'b1) begin
m_axis_phase_valid <= 1'b0;
end
if (m_axis_sample_ready == 1'b1) begin
m_axis_sample_valid <= 1'b0;
end
end
end
end
/* If the STAT register is included in the sample we get 4 bytes per sample and
* are able to detect channel swaps and synchronize the first output sample to
* the first channel. If the STAT register is not included we only get 3 bytes
* per sample and rely on that the first sample will always be from the first
* channel */
always @(posedge clk) begin
sample_hold_valid <= 1'b0;
if (sample_has_stat == 1'b0) begin
if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin
sample_hold_valid <= 1'b1;
end
end else begin
if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 &&
(sync == 1'b1 || synced == 1'b1)) begin
sample_hold_valid <= 1'b1;
end
end
end
always @(posedge clk) begin
if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin
sample_hold <= {sample_hold[15:0],s_axis_sample_data};
end
end
always @(posedge clk) begin
if (s_axis_sample_valid == 1'b1) begin
if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin
data_counter <= 2'h0;
end else begin
data_counter <= data_counter + 1'b1;
end
end
end
assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3;
always @(posedge clk) begin
if (processing_resetn == 1'b0) begin
synced <= ~sample_has_stat;
end else begin
if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin
synced <= 1'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKINV_16_V
`define SKY130_FD_SC_LS__CLKINV_16_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKINV_16_V
|
/*
*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2004 by Babak Falsafi and James Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),
* Carnegie Mellon University.
*
* This source file was written and maintained by Jared Smolens
* as part of the Two-Way In-Order Superscalar project for Carnegie Mellon's
* Introduction to Computer Architecture course, 18-447. The source file
* is in part derived from code originally written by Herman Schmit and
* Diana Marculescu.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* If you modify the software you must place a notice on or within any
* modified version provided or made available to any third party stating
* that you have modified the software. The notice shall include at least
* your name, address, phone number, email address and the date and purpose
* of the modification.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANYWARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Include the MIPS constants
`include "mips_defines.vh"
`include "mips_internalDefines.vh"
// include MIPS modules
`include "mips_mux2to1.v"
`include "mips_mux4to1.v"
`include "mips_reg.v"
`include "mips_regFile.v"
`include "mips_alu.v"
`include "mips_addConst.v"
`include "mips_decode.v"
`include "mips_exceptionUnit.v"
`include "mips_syscallUnit.v"
////
//// The MIPS standalone processor module
////
//// clk (input) - The clock
//// inst_addr (output) - Address of instruction to load
//// inst (input) - Instruction from memory
//// inst_excpt (input) - inst_addr not valid
//// mem_addr (output) - Address of data to load
//// mem_data_in (output) - Data for memory store
//// mem_data_out (input) - Data from memory load
//// mem_write_en (output) - Memory write mask
//// mem_excpt (input) - mem_addr not valid
//// halted (output) - Processor halted
//// reset (input) - Reset the processor
////
module mips_core(/*AUTOARG*/
// Outputs
inst_addr, mem_addr, mem_data_in, mem_write_en, halted,
// Inputs
clk, inst_excpt, mem_excpt, inst, mem_data_out, rst_b
);
parameter text_start = 32'h00400000; /* Initial value of $pc */
// Core Interface
input clk, inst_excpt, mem_excpt;
output [29:0] inst_addr;
output [29:0] mem_addr;
input [31:0] inst, mem_data_out;
output [31:0] mem_data_in;
output [3:0] mem_write_en;
output halted;
input rst_b;
// Forced interface signals -- required for synthesis to work OK.
// This is probably not what you want!
assign mem_addr = 0;
assign mem_data_in = mem_data_out;
assign mem_write_en = 4'b0;
// Internal signals
wire [31:0] pc, nextpc, nextnextpc;
wire exception_halt, syscall_halt, internal_halt;
wire load_epc, load_bva, load_bva_sel;
wire [31:0] rt_data, rs_data, rd_data, alu__out, r_v0;
wire [31:0] epc, cause, bad_v_addr;
wire [4:0] cause_code;
// Decode signals
wire [31:0] dcd_se_imm, dcd_se_offset, dcd_e_imm, dcd_se_mem_offset;
wire [5:0] dcd_op, dcd_funct2;
wire [4:0] dcd_rs, dcd_funct1, dcd_rt, dcd_rd, dcd_shamt;
wire [15:0] dcd_offset, dcd_imm;
wire [25:0] dcd_target;
wire [19:0] dcd_code;
wire dcd_bczft;
// alu signals
wire [31:0] imm_value;
wire [31:0] alu_op2;
// PC Management
mips_reg #(32, text_start) PCReg(pc, nextpc, clk, ~internal_halt, rst_b);
mips_reg #(32, text_start+4) PCReg2(nextpc, nextnextpc, clk,
~internal_halt, rst_b);
mips_addConst #(4) NextPCAdder(nextnextpc, nextpc);
assign inst_addr = pc[31:2];
// Instruction decoding
assign dcd_op = inst[31:26]; // Opcode
assign dcd_rs = inst[25:21]; // rs field
assign dcd_rt = inst[20:16]; // rt field
assign dcd_rd = inst[15:11]; // rd field
assign dcd_shamt = inst[10:6]; // Shift amount
assign dcd_bczft = inst[16]; // bczt or bczf?
assign dcd_funct1 = inst[4:0]; // Coprocessor 0 function field
assign dcd_funct2 = inst[5:0]; // funct field; secondary opcode
assign dcd_offset = inst[15:0]; // offset field
// Sign-extended offset for branches
assign dcd_se_offset = { {14{dcd_offset[15]}}, dcd_offset, 2'b00 };
// Sign-extended offset for load/store
assign dcd_se_mem_offset = { {16{dcd_offset[15]}}, dcd_offset };
assign dcd_imm = inst[15:0]; // immediate field
assign dcd_e_imm = { 16'h0, dcd_imm }; // zero-extended immediate
// Sign-extended immediate
assign dcd_se_imm = { {16{dcd_imm[15]}}, dcd_imm };
assign dcd_target = inst[25:0]; // target field
assign dcd_code = inst[25:6]; // Breakpoint code
// synthesis translate_off
always @(posedge clk) begin
// useful for debugging, you will want to comment this out for long programs
if (rst_b) begin
$display ( "=== Simulation Cycle %d ===", $time );
$display ( "[pc=%x, inst=%x] [op=%x, rs=%d, rt=%d, rd=%d, imm=%x, f2=%x] [reset=%d, halted=%d]",
pc, inst, dcd_op, dcd_rs, dcd_rt, dcd_rd, dcd_imm, dcd_funct2, ~rst_b, halted);
end
end
// synthesis translate_on
// Let Verilog-Mode pipe wires through for us. This is another example
// of Verilog-Mode's power -- undeclared nets get AUTOWIREd up when we
// run 'make auto'.
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] alu__sel; // From Decoder of mips_decode.v
wire ctrl_RI; // From Decoder of mips_decode.v
wire ctrl_Sys; // From Decoder of mips_decode.v
wire ctrl_we; // From Decoder of mips_decode.v
// End of automatics
// Generate control signals
mips_decode Decoder(/*AUTOINST*/
// Outputs
.ctrl_we (ctrl_we),
.ctrl_Sys (ctrl_Sys),
.ctrl_RI (ctrl_RI),
.alu__sel (alu__sel[3:0]),
// Inputs
.dcd_op (dcd_op[5:0]),
.dcd_funct2 (dcd_funct2[5:0]));
// Register File
// Instantiate the register file from reg_file.v here.
// Don't forget to hookup the "halted" signal to trigger the register dump
mips_regFile RegFile(
.clk (clk),
.rst_n (rst_b),
.rdAddr0 (dcd_rs),
.rdAddr1 (dcd_rt),
.we (ctrl_we),
.wrAddr (dcd_rd),
.wrData (alu__out),
.halted (internal_halt),
.rdData0 (rs_data),
.rdData1 (rt_data));
// synthesis translate_off
initial begin
// Delete this block when you are ready to try for real
$display("");
$display("");
$display("");
$display("");
$display(">>>>> This works much better after you have hooked up the reg file. <<<<<");
$display("");
$display("");
$display("");
$display("");
$finish;
end
// synthesis translate_on
mux2_1 #(32) se_e_MUX(dcd_se_imm, dcd_e_imm, isSe, imm_value);
mux2_1 #(32) aluOP2(imm_value, rt_data, isImm, alu_op2);
// Execute
mips_alu ALU(.alu__out(alu__out),
.alu__op1(rs_data),
.alu__op2(alu_op2),
.alu__sel(alu__sel));
// Miscellaneous stuff (Exceptions, syscalls, and halt)
mips_exceptionUnit EU(.exception_halt(exception_halt), .pc(pc), .rst_b(rst_b),
.clk(clk), .load_ex_regs(load_ex_regs),
.load_bva(load_bva), .load_bva_sel(load_bva_sel),
.cause(cause_code),
.IBE(inst_excpt),
.DBE(1'b0),
.RI(ctrl_RI),
.Ov(1'b0),
.BP(1'b0),
.AdEL_inst(pc[1:0]?1'b1:1'b0),
.AdEL_data(1'b0),
.AdES(1'b0),
.CpU(1'b0));
assign r_v0 = 32'h0a; // Good enough for now. To support syscall for real,
// you should read the syscall
// argument from $v0 of the register file
mips_syscallUnit SU(.syscall_halt(syscall_halt), .pc(pc), .clk(clk), .Sys(ctrl_Sys),
.r_v0(r_v0), .rst_b(rst_b));
assign internal_halt = exception_halt | syscall_halt;
mips_reg #(1, 0) Halt(halted, internal_halt, clk, 1'b1, rst_b);
mips_reg #(32, 0) EPCReg(epc, pc, clk, load_ex_regs, rst_b);
mips_reg #(32, 0) CauseReg(cause,
{25'b0, cause_code, 2'b0},
clk, load_ex_regs, rst_b);
mips_reg #(32, 0) BadVAddrReg(bad_v_addr, pc, clk, load_bva, rst_b);
endmodule // mips_core
// Local Variables:
// verilog-library-directories:("." "../447rtl")
// End:
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:25:27 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
module zqynq_lab_1_design_axi_bram_ctrl_0_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arlen,
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, bram_rst_a,
bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a, bram_rst_b,
bram_clk_b, bram_en_b, bram_we_b, bram_addr_b, bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
|
// --------------------------------------------------------------------
// ng_CRG Central register Module
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_CRG(
input CLK2, // Clock Pulse 2
input [100:0] CP, // Control Pulse
input [ 15:0] WRITE_BUS, // Control Pulse
output [ 15:0] A_REG_BUS, // A Register output
output [ 15:0] LP_REG_BUS, // LP Register output
output [ 15:0] Q_REG_BUS, // Q Register output
output [ 15:0] Z_REG_BUS // Z Register output
);
// --------------------------------------------------------------------
// Register Storage
// --------------------------------------------------------------------
reg [ 15:0] A; // A Register
reg [ 15:0] Q; // Q Register
reg [ 15:0] Z; // Z Register
reg [ 15:0] LP; // LP Register
// --------------------------------------------------------------------
// Register output assignments
// --------------------------------------------------------------------
assign A_REG_BUS = A;
assign LP_REG_BUS = LP;
assign Q_REG_BUS = Q;
assign Z_REG_BUS = Z;
// --------------------------------------------------------------------
// Control Signals
// --------------------------------------------------------------------
wire GENRST = CP[`CPX(`GENRST)]; // General reset signal
wire WA = CP[`CPX(`WA)]; // Write A
wire WA0 = CP[`CPX(`WA0)]; // Write register at address 0 (A)
wire WALP = CP[`CPX(`WALP)]; // Write A and LP
wire WQ = CP[`CPX(`WQ)]; // Write Q
wire WA1 = CP[`CPX(`WA1)]; // Write register at address 1 (Q)
wire WLP = CP[`CPX(`WLP)]; // Write LP
wire WA3 = CP[`CPX(`WA3)]; // Write register at address 3 (LP)
wire WZ = CP[`CPX(`WZ)]; // Write Z
wire WA2 = CP[`CPX(`WA2)]; // Write register at address 2 (Z)
// --------------------------------------------------------------------
// Instantiate Register A Latch
// --------------------------------------------------------------------
always @(posedge CLK2) begin // Instantiate the A latch
if(!GENRST) A <= 16'h0000;
else if(!WA | !WA0) A <= WRITE_BUS; // Write to A, No Shift
else if(!WALP) begin // If a shift is requested
A[15] <= WRITE_BUS[15]; // MSBit
A[14] <= WRITE_BUS[15]; // Duplicate it
A[13:0] <= WRITE_BUS[14:1]; // Shifted
end
end
// --------------------------------------------------------------------
// Instantiate Register LP Latch
// --------------------------------------------------------------------
always @(posedge CLK2) begin // Instantiate the LP latch
if(!GENRST) LP <= 16'h0000;
else if(!WLP | !WA3) begin
LP[15 ] <= WRITE_BUS[0]; // LSB to MSBit
LP[14 ] <= WRITE_BUS[0]; // Duplicate it
LP[12:0] <= WRITE_BUS[13:1]; // Shifted
end
if(!WALP | !WLP | !WA3) LP[13] <= !(WALP | !WRITE_BUS[0]); // Handle Bit 14
end
// --------------------------------------------------------------------
// Instantiate Register Q Latch
// --------------------------------------------------------------------
always @(posedge CLK2) begin // Instantiate the Q latch
if(!GENRST) Q <= 16'h0000;
else if(!WQ | !WA1) Q <= WRITE_BUS;
end
// --------------------------------------------------------------------
// Instantiate Register Z Latch
// --------------------------------------------------------------------
always @(posedge CLK2) begin // Instantiate the Z latch
if(!GENRST) Z <= 16'h0000;
else if(!WZ | !WA2) Z <= WRITE_BUS;
end
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580wm80a.v
//
// Processor k580wm80a core design file of Bashkiria-2M replica.
module k580wm80a(
input clk,
input ce,
input reset,
input intr,
input [7:0] idata,
output reg [15:0] addr,
output reg sync,
output rd,
output reg wr,
output inta,
output reg [7:0] odata);
reg M1,M2,M3,M4,M5,M6,M7,M8,M9,M10,M11,M12,M13,M14,M15,M16,M17,T5;
reg[2:0] state;
wire M1n = M2|M3|M4|M5|M6|M7|M8|M9|M10|M11|M12|M13|M14|M15|M16|M17;
reg[15:0] PC;
reg[15:0] SP;
reg[7:0] B,C,D,E,H,L,A;
reg[7:0] W,Z,IR;
reg[9:0] ALU;
reg FS,FZ,FA,FP,FC;
reg rd_,intproc;
assign rd = rd_&~intproc;
assign inta = (rd_&intproc);
reg[1:0] inte;
reg jmp,call,halt;
reg save_alu,save_a,save_r,save_rp,read_r,read_rp;
reg incdec,xthl,xchg,sphl,daa,ALUb4;
reg ccc;
always @(*) begin
casex (IR[5:3])
3'b00x: ALU = {1'b0,A,1'b1}+{1'b0,Z,FC&IR[3]};
3'b01x: ALU = {1'b0,A,1'b0}-{1'b0,Z,FC&IR[3]};
3'b100: ALU = {1'b0,A & Z,1'b0};
3'b101: ALU = {1'b0,A ^ Z,1'b0};
3'b110: ALU = {1'b0,A | Z,1'b0};
3'b111: ALU = {1'b0,A,1'b0}-{1'b0,Z,1'b0};
endcase
end
always @(*) begin
casex (IR[5:3])
3'b00x: ALUb4 = A[4]+Z[4];
3'b01x: ALUb4 = A[4]-Z[4];
3'b10x: ALUb4 = A[4]^Z[4];
3'b110: ALUb4 = A[4]|Z[4];
3'b111: ALUb4 = A[4]-Z[4];
endcase
end
always @(*) begin
// SZ.A.P.C
case(idata[5:3])
3'h0: ccc = ~FZ;
3'h1: ccc = FZ;
3'h2: ccc = ~FC;
3'h3: ccc = FC;
3'h4: ccc = ~FP;
3'h5: ccc = FP;
3'h6: ccc = ~FS;
3'h7: ccc = FS;
endcase
end
wire[7:0] F = {FS,FZ,1'b0,FA,1'b0,FP,1'b1,FC};
wire[7:0] Z1 = incdec ? Z+{{7{IR[0]}},1'b1} : Z;
wire[15:0] WZ1 = incdec ? {W,Z}+{{15{IR[3]}},1'b1} : {W,Z};
wire[3:0] daaZL = FA!=0 || A[3:0] > 4'h9 ? 4'h6 : 4'h0;
wire[3:0] daaZH = FC!=0 || A[7:4] > {3'b100, A[3:0]>4'h9 ? 1'b0 : 1'b1} ? 4'h6 : 4'h0;
always @(posedge clk or posedge reset)
begin
if (reset) begin
{M1,M2,M3,M4,M5,M6,M7,M8,M9,M10,M11,M12,M13,M14,M15,M16,M17} <= 0;
state <= 0; PC <= 0; {FS,FZ,FA,FP,FC} <= 0; {addr,odata} <= 0;
{sync,rd_,jmp,halt,inte,save_alu,save_a,save_r,save_rp,incdec,intproc} <= 0;
wr <= 1'b0;
end else if (ce) begin
sync <= 0; rd_ <= 0; wr <= 1'b0;
if (halt&~(M1|(intr&inte[1]))) begin
sync <= 1'b1; // state: rd in m1 out hlt stk ~wr int
odata <= 8'b10001010; // rd? hlt ~wr
end else
if (M1|~M1n) begin
case (state)
3'b000: begin
halt <= 0; intproc <= intr&inte[1]; inte[1] <= inte[0];
M1 <= 1'b1;
sync <= 1'b1;
odata <= {7'b1010001,intr&inte[1]}; // rd m1 ~wr
addr <= jmp ? {W,Z} : PC;
state <= 3'b001;
if (intr&inte[1]) inte <= 2'b0;
if (save_alu) begin
FS <= ALU[8];
FZ <= ~|ALU[8:1];
FA <= ALU[5]^ALUb4;
FP <= ~^ALU[8:1];
FC <= ALU[9]|(FC&daa);
if (IR[5:3]!=3'b111) A <= ALU[8:1];
end else
if (save_a) begin
A <= Z1;
end else
if (save_r) begin
case (IR[5:3])
3'b000: B <= Z1;
3'b001: C <= Z1;
3'b010: D <= Z1;
3'b011: E <= Z1;
3'b100: H <= Z1;
3'b101: L <= Z1;
3'b111: A <= Z1;
endcase
if (incdec) begin
FS <= Z1[7];
FZ <= ~|Z1;
FA <= IR[0] ? Z1[3:0]!=4'b1111 : Z1[3:0]==0;
FP <= ~^Z1;
end
end else
if (save_rp) begin
case (IR[5:4])
2'b00: {B,C} <= WZ1;
2'b01: {D,E} <= WZ1;
2'b10: {H,L} <= WZ1;
2'b11:
if (sphl || !IR[7]) begin
SP <= WZ1;
end else begin
{A,FS,FZ,FA,FP,FC} <= {WZ1[15:8],WZ1[7],WZ1[6],WZ1[4],WZ1[2],WZ1[0]};
end
endcase
end
end
3'b001: begin
rd_ <= 1'b1;
PC <= addr+{15'b0,~intproc};
state <= 3'b010;
end
3'b010: begin
IR <= idata;
{jmp,call,save_alu,save_a,save_r,save_rp,read_r,read_rp,incdec,xthl,xchg,sphl,T5,daa} <= 0;
casex (idata)
8'b00xx0001: {save_rp,M2,M3} <= 3'b111;
8'b00xx1001: {read_rp,M16,M17} <= 3'b111;
8'b000x0010: {read_rp,M14} <= 2'b11;
8'b00100010: {M2,M3,M14,M15} <= 4'b1111;
8'b00110010: {M2,M3,M14} <= 3'b111;
8'b000x1010: {read_rp,save_a,M12} <= 3'b111;
8'b00101010: {save_rp,M2,M3,M12,M13} <= 5'b11111;
8'b00111010: {save_a,M2,M3,M12} <= 4'b1111;
8'b00xxx011: {read_rp,save_rp,incdec,T5} <= 4'b1111;
8'b00xxx10x: {read_r,save_r,incdec,T5} <= {3'b111,idata[5:3]!=3'b110};
8'b00xxx110: {save_r,M2} <= 2'b11;
8'b00000111: {FC,A} <= {A,A[7]};
8'b00001111: {A,FC} <= {A[0],A};
8'b00010111: {FC,A} <= {A,FC};
8'b00011111: {A,FC} <= {FC,A};
8'b00100111: {daa,save_alu,IR[5:3],Z} <= {5'b11000,daaZH,daaZL};
8'b00101111: A <= ~A;
8'b00110111: FC <= 1'b1;
8'b00111111: FC <= ~FC;
8'b01xxxxxx: if (idata[5:0]==6'b110110) halt <= 1'b1; else {read_r,save_r,T5} <= {2'b11,~(idata[5:3]==3'b110||idata[2:0]==3'b110)};
8'b10xxxxxx: {read_r,save_alu} <= 2'b11;
8'b11xxx000: {jmp,M8,M9} <= {3{ccc}};
8'b11xx0001: {save_rp,M8,M9} <= 3'b111;
8'b110x1001: {jmp,M8,M9} <= 3'b111;
8'b11101001: {read_rp,jmp,T5} <= 3'b111;
8'b11111001: {read_rp,save_rp,T5,sphl} <= 4'b1111;
8'b11xxx010: {jmp,M2,M3} <= {ccc,2'b11};
8'b1100x011: {jmp,M2,M3} <= 3'b111;
8'b11010011: {M2,M7} <= 2'b11;
8'b11011011: {M2,M6} <= 2'b11;
8'b11100011: {save_rp,M8,M9,M10,M11,xthl} <= 6'b111111;
8'b11101011: {read_rp,save_rp,xchg} <= 3'b111;
8'b1111x011: inte <= idata[3] ? 2'b1 : 2'b0;
8'b11xxx100: {jmp,M2,M3,T5,M10,M11,call} <= {ccc,3'b111,{3{ccc}}};
8'b11xx0101: {read_rp,T5,M10,M11} <= 4'b1111;
8'b11xx1101: {jmp,M2,M3,T5,M10,M11,call} <= 7'b1111111;
8'b11xxx110: {save_alu,M2} <= 2'b11;
8'b11xxx111: {jmp,T5,M10,M11,call,W,Z} <= {5'b11111,10'b0,idata[5:3],3'b0};
endcase
state <= 3'b011;
end
3'b011: begin
if (read_rp) begin
case (IR[5:4])
2'b00: {W,Z} <= {B,C};
2'b01: {W,Z} <= {D,E};
2'b10: {W,Z} <= xchg ? {D,E} : {H,L};
2'b11: {W,Z} <= sphl ? {H,L} : IR[7] ? {A,F} : SP;
endcase
if (xchg) {D,E} <= {H,L};
end else
if (~(jmp|daa)) begin
case (incdec?IR[5:3]:IR[2:0])
3'b000: Z <= B;
3'b001: Z <= C;
3'b010: Z <= D;
3'b011: Z <= E;
3'b100: Z <= H;
3'b101: Z <= L;
3'b110: M4 <= read_r;
3'b111: Z <= A;
endcase
M5 <= save_r && IR[5:3]==3'b110;
end
state <= T5 ? 3'b100 : 0;
M1 <= T5;
end
3'b100: begin
if (M10) SP <= SP-16'b1;
state <= 0;
M1 <= 0;
end
endcase
end else
if (M2 || M3) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b1000001,intproc}; // rd ~wr
addr <= PC;
state <= 3'b001;
end
3'b001: begin
rd_ <= 1'b1;
PC <= addr+{15'b0,~intproc};
state <= 3'b010;
end
3'b010: begin
if (M2) begin
Z <= idata;
M2 <= 0;
end else begin
W <= idata;
M3 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (M4) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b1000001,intproc}; // rd ~wr
addr <= {H,L};
state <= 3'b001;
end
3'b001: begin
rd_ <= 1'b1;
state <= 3'b010;
end
3'b010: begin
Z <= idata;
M4 <= 0;
state <= 3'b000;
end
endcase
end else
if (M5) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b0000000,intproc}; // ~wr=0
addr <= {H,L};
state <= 3'b001;
end
3'b001: begin
odata <= Z1;
wr <= 1'b1;
state <= 3'b010;
end
3'b010: begin
M5 <= 0;
state <= 3'b000;
end
endcase
end else
if (M6) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b0100001,intproc}; // in ~wr
addr <= {Z,Z};
state <= 3'b001;
end
3'b001: begin
rd_ <= 1'b1;
state <= 3'b010;
end
3'b010: begin
A <= idata;
M6 <= 0;
state <= 3'b000;
end
endcase
end else
if (M7) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b0001000,intproc}; // out
addr <= {Z,Z};
state <= 3'b001;
end
3'b001: begin
odata <= A;
wr <= 1'b1;
state <= 3'b010;
end
3'b010: begin
M7 <= 0;
state <= 3'b000;
end
endcase
end else
if (M8 || M9) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b1000011,intproc}; // rd stk ~wr
addr <= SP;
state <= 3'b001;
end
3'b001: begin
rd_ <= 1'b1;
if (M8 || !xthl) SP <= SP+16'b1;
state <= 3'b010;
end
3'b010: begin
if (M8) begin
Z <= idata;
M8 <= 0;
end else begin
W <= idata;
M9 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (M10 || M11) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b0000010,intproc}; // stk
addr <= SP;
state <= 3'b001;
end
3'b001: begin
if (M10) begin
SP <= SP-16'b1;
odata <= xthl ? H : call ? PC[15:8] : W;
end else begin
odata <= xthl ? L : call ? PC[7:0] : Z;
end
wr <= 1'b1;
state <= 3'b010;
end
3'b010: begin
if (M10) begin
M10 <= 0;
end else begin
M11 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (M12 || M13) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b1000001,intproc}; // rd ~wr
addr <= M12 ? {W,Z} : addr+16'b1;
state <= 3'b001;
end
3'b001: begin
rd_ <= 1'b1;
state <= 3'b010;
end
3'b010: begin
if (M12) begin
Z <= idata;
M12 <= 0;
end else begin
W <= idata;
M13 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (M14 || M15) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b0000000,intproc}; // ~wr=0
addr <= M14 ? {W,Z} : addr+16'b1;
state <= 3'b001;
end
3'b001: begin
if (M14) begin
odata <= M15 ? L : A;
end else begin
odata <= H;
end
wr <= 1'b1;
state <= 3'b010;
end
3'b010: begin
if (M14) begin
M14 <= 0;
end else begin
M15 <= 0;
end
state <= 3'b000;
end
endcase
end else
if (M16 || M17) begin
case (state)
3'b000: begin
sync <= 1'b1;
odata <= {7'b0000001,intproc}; // ~wr
state <= 3'b001;
end
3'b001: begin
state <= 3'b010;
end
3'b010: begin
if (M16) begin
M16 <= 0;
end else begin
{FC,H,L} <= {1'b0,H,L}+{1'b0,W,Z};
M17 <= 0;
end
state <= 3'b000;
end
endcase
end
end
end
endmodule
|
/*
* File: pippo_if.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
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* Task.I:
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[TBV] imx, pipelining and PC bahavior
1. npc_branch, npc_except can't assert simultaneously
2. after recover from freezing, first fetch request from previous pc/npc?
3. the case of canceling fetch request(cache miss, and inst transfer event happened)
processing by imx protocol: diassert rqt, then diassert ack.
4. check id_snia timing
5. coding style of pipelining register
[TBD]make "itlb, immu" logic conditional
* Task.II:
* full synthesis & verification
* rtl performance refactor-improve speed, reduce power and area.
* to improve fetch performance, add buffer to register fetched instruction and address at some case
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module pippo_if(
clk, rst,
iimx_adr_o, iimx_rqt_o, iimx_rty_i,
iimx_ack_i, iimx_err_i, iimx_dat_i, iimx_adr_i,
npc_branch, npc_except, npc_branch_valid, npc_except_valid,
pc_freeze, if_stall, if_freeze, id_freeze, flushpipe,
id_inst, id_cia, id_valid, id_snia,
id_sig_ibuserr
);
input clk;
input rst;
// IMX I/F to fetch instructions (from cache/ocm/memory controller)
input [31:0] iimx_dat_i;
input iimx_ack_i;
input iimx_err_i;
input [31:0] iimx_adr_i;
input iimx_rty_i;
output [31:0] iimx_adr_o;
output iimx_rqt_o;
// inst. flow transfer
input [29:0] npc_branch;
input npc_branch_valid;
input [31:0] npc_except; // keep least two address bits to code ISR entrance easily.
input npc_except_valid;
// pipeline control
input pc_freeze;
input if_freeze;
input id_freeze;
input flushpipe;
output if_stall;
// pipeling register
output id_valid;
output [31:0] id_inst;
output [29:0] id_cia;
output [29:0] id_snia;
// exception request
output id_sig_ibuserr;
//
//
//
reg id_valid;
reg [31:0] id_inst;
reg [29:0] id_cia;
reg [29:0] id_snia;
reg id_sig_ibuserr;
reg [31:0] npc_value;
reg if_valid;
reg [31:0] if_inst;
reg [29:0] if_cia;
reg if_sig_ibuserr;
reg [31:0] pc;
wire if_rqt_valid;
wire [32:0] pcadd4;
wire except_ibuserr;
//
// send fetch rqt to I-IMX
//
assign iimx_adr_o = pc;
assign iimx_rqt_o = if_rqt_valid;
// stall request, waiting for I-IMX response
assign if_stall = ~iimx_ack_i;
//
// PC Register logic
//
// NPC source
assign pcadd4={(pc[31:2]+31'd1), 2'b00};
//
assign fetch_lost = id_freeze & iimx_ack_i;
always @(npc_branch_valid or npc_except_valid or id_freeze or iimx_adr_i or
fetch_lost or npc_branch or npc_except or pc or pcadd4) begin
casex ({npc_branch_valid, npc_except_valid, id_freeze, fetch_lost}) // synopsys parallel_case
4'b0000: begin
npc_value = pcadd4[31:0];
end
4'b0100: begin
npc_value = npc_except;
end
4'b1000: begin
npc_value = {npc_branch, 2'b00};
end
4'b0010: begin // if pipeline(if_freeze & id_freeze) is freezon, keep current pc
npc_value = pc;
end
4'b0011: begin
npc_value = iimx_adr_i; // fetch current fetched instruction again
end
default: begin
npc_value = pc;
end
endcase
end
//
// PC update policy
//
// 1. after hard reset, keep RESET_VECTOR (pcadd4[32]) to avoid overflow
// 2. update pc when
// a) flushpipe: flush pipeline, fetch with npc
// b) !iimx_rty_i: current transaction is complete
// c) fetch lost
always @(posedge clk or posedge rst) begin
if (rst)
pc <= #1 `pippo_RESET_VECTOR;
else if (pcadd4[32] & !flushpipe) // !flushpipe: keep normal when fetched first branch inst
pc <= #1 `pippo_RESET_VECTOR;
else if (flushpipe | (!iimx_rty_i) | fetch_lost)
pc <= #1 npc_value;
end
//
// inst. fetch request logic: if_rqt_valid signal
// 1. when flushpipe assert(pc_freeze asserts), if_rqt_valid disassert
// 2. when pipeline freeze(id_freeze freeze), if_rqt_valid disassert to reduce memory access
// NOT use if_freeze signal to exclude if_stall deadlock, or additional logic is needed for biu
// deadloack: if_freeze assert at wait state, if you diassert this request, system stop forever.
// 3. hard-reset case: if_rqt_valid assert until RESET_VECTOR's ack(!iimx_rty_i) come, then keep disassertion.
// At normal state, always send fetch request - if_rqt_valid keep assert, when address ack(!iimx_rty_i) assert
// or disassert. including case that if_stall asserts, to avoid deadlock: no new fetch send out
// deadlock: (if_stall raised -> if_freeze assert -> rqt_valid disassert forever)
// after hard reset, to avoid fetch reset vector many times,
// "!flushpipe" logic is to reduce one cycle delay after reset vector's branch
reg rst_rqt_done;
always @(posedge clk or posedge rst) begin
if (rst)
rst_rqt_done <= #1 1'b0;
else if (flushpipe)
rst_rqt_done <= #1 1'b0;
else if (pcadd4[32] & !iimx_rty_i)
rst_rqt_done <= #1 1'b1;
end
// to check the timing of rqt_valid signal - rqt_valid must have budget for addr_ack logic, i.e.:
// at IMX address phase(cycle 1):
// Master send out if_rqt_valid, slave check address and give back addr_ack;
// Addr_ack(!iimx_rty_i) signal must satisfy the setup time, when inputting to master;
// [TBD] register out if_rqt_valid signal to improve timing, add a pipeline bubble under some case
// note: keep pace with pc update
assign if_rqt_valid = !(pc_freeze | id_freeze | (pcadd4[32] & rst_rqt_done));
//
// IF/ID pipelining logic
//
always @(iimx_ack_i or if_freeze or id_freeze or flushpipe or
if_valid or if_inst or if_cia or
id_valid or id_inst or id_cia or
iimx_dat_i or iimx_adr_i or
except_ibuserr or id_sig_ibuserr) begin
casex ({iimx_ack_i, if_freeze, id_freeze, flushpipe}) // synopsys parallel_case
4'b1000: begin // Normal pipelining. I-IMX returns valid value
if_valid = 1'b1;
if_inst = iimx_dat_i;
if_cia = iimx_adr_i[31:2];
if_sig_ibuserr = except_ibuserr;
end
4'bxxx1: begin // flushpipe is asserted, insert NOP bubble
if_valid = 1'b0;
if_inst = `pippo_PWR_NOP;
if_cia = id_cia;
if_sig_ibuserr = 1'b0;
end
4'bx100: begin // if_freeze is asserted, id_freeze is disasserted, insert NOP bubble
if_valid = 1'b0;
if_inst = `pippo_PWR_NOP;
if_cia = id_cia;
if_sig_ibuserr = 1'b0;
end
4'bx110: begin // if_freeze/id_freeze is asserted, insert KCS bubble
if_valid = id_valid;
if_inst = id_inst;
if_cia = id_cia;
if_sig_ibuserr = id_sig_ibuserr;
end
default: begin // [TBV]iimx_err_i is asserted
if_valid = 1'b0;
if_inst = `pippo_PWR_NOP;
if_cia = id_cia;
if_sig_ibuserr = except_ibuserr;
end
endcase
end
always @(posedge clk or posedge rst) begin
if(rst) begin
id_valid <= #1 1'b0;
id_inst <= #1 `pippo_PWR_NOP;
id_cia <= #1 30'd0;
id_snia <= #1 30'd0;
id_sig_ibuserr = 1'b0;
end
else begin
id_valid <= #1 if_valid;
id_inst <= #1 if_inst;
id_cia <= #1 if_cia;
id_snia <= #1 pcadd4[31:2];
id_sig_ibuserr = if_sig_ibuserr;
`ifdef pippo_VERBOSE
// synopsys translate_off
$display("%t: id_valid <= %h", $time, id_valid);
$display("%t: id_inst <= %h", $time, id_inst);
$display("%t: id_cia <= %h", $time, id_cia);
$display("%t: id_snia <= %h", $time, id_snia);
// synopsys translate_on
`endif
end
end
//
// except request from IF stage
//
assign except_ibuserr = iimx_err_i & iimx_ack_i; // err valid only when ack assert
endmodule
|
/*
This block receives the IO transaction and converts to a 104 bit packet.
*/
`include "elink_constants.v"
module erx_io (/*AUTOARG*/
// Outputs
rx_clkin, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
// Inputs
erx_io_reset, rx_lclk, rx_lclk_div4, idelay_value, load_taps,
rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
rxi_data_n, rx_wr_wait, rx_rd_wait
);
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 1;//0=parallella
//1=ephycard
//#########################
//# reset, clocks
//#########################
input erx_io_reset; // high sped reset
input rx_lclk; // fast I/O clock
input rx_lclk_div4; // slow clock
output rx_clkin; // clock output for pll
//#########################
//# idelays
//#########################
input [44:0] idelay_value;
input load_taps;
//##########################
//# elink pins
//##########################
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
//##########################
//# erx logic interface
//##########################
output rx_access;
output rx_burst;
output [PW-1:0] rx_packet;
input rx_wr_wait;
input rx_rd_wait;
//############
//# WIRES
//############
wire [7:0] rxi_data;
wire rxi_frame;
wire rxi_lclk;
wire access_wide;
reg valid_packet;
wire [15:0] rx_word;
reg [15:0] rx_word_sync;
//############
//# REGS
//############
reg [7:0] data_even_reg;
reg [7:0] data_odd_reg;
wire rx_frame;
reg [111:0] rx_sample;
reg [6:0] rx_pointer;
reg access;
reg burst;
reg [PW-1:0] rx_packet_lclk;
reg rx_access;
reg [PW-1:0] rx_packet;
reg rx_burst;
wire rx_lclk_iddr;
wire [8:0] rxi_delay_in;
wire [8:0] rxi_delay_out;
reg reset_sync;
reg burst_detect;
//#####################
//#CREATE 112 BIT PACKET
//#####################
//write Pointer
always @ (posedge rx_lclk or posedge erx_io_reset)
if(erx_io_reset)
rx_pointer[6:0] <= 7'b0;
else if (~rx_frame)
rx_pointer[6:0] <= 7'b0000001; //new frame
else if (rx_pointer[6])
rx_pointer[6:0] <= 7'b0001000; //anticipate burst
else if(rx_frame)
rx_pointer[6:0] <= {rx_pointer[5:0],1'b0};//middle of frame
//convert to 112 bit packet
always @ (posedge rx_lclk)
if(rx_frame)
begin
if(rx_pointer[0])
rx_sample[15:0] <= rx_word[15:0];
if(rx_pointer[1])
rx_sample[31:16] <= rx_word[15:0];
if(rx_pointer[2])
rx_sample[47:32] <= rx_word[15:0];
if(rx_pointer[3])
rx_sample[63:48] <= rx_word[15:0];
if(rx_pointer[4])
rx_sample[79:64] <= rx_word[15:0];
if(rx_pointer[5])
rx_sample[95:80] <= rx_word[15:0];
if(rx_pointer[6])
rx_sample[111:96] <= rx_word[15:0];
end // if (rx_frame)
//#####################
//#DATA VALID SIGNAL
//####################
always @ (posedge rx_lclk)
begin
access <= rx_pointer[6];
valid_packet <= access;//data pipeline
end
always @ (posedge rx_lclk or posedge erx_io_reset)
if(erx_io_reset)
burst_detect <= 1'b0;
else if(access & rx_frame)
burst_detect <= 1'b1;
else if(~rx_frame)
burst_detect <= 1'b0;
//###################################
//#SAMPLE AND HOLD DATA
//###################################
//(..and shuffle data for 104 bit packet)
always @ (posedge rx_lclk)
if(access)
begin
//pipelin burst (delay by one frame)
burst <= burst_detect;
//access
rx_packet_lclk[0] <= rx_sample[40];
//write
rx_packet_lclk[1] <= rx_sample[41];
//datamode
rx_packet_lclk[3:2] <= rx_sample[43:42];
//ctrlmode
rx_packet_lclk[7:4] <= rx_sample[15:12];
//dstaddr
rx_packet_lclk[39:8] <= {rx_sample[11:8],
rx_sample[23:16],
rx_sample[31:24],
rx_sample[39:32],
rx_sample[47:44]};
//data
rx_packet_lclk[71:40] <= {rx_sample[55:48],
rx_sample[63:56],
rx_sample[71:64],
rx_sample[79:72]};
//srcaddr
rx_packet_lclk[103:72]<= {rx_sample[87:80],
rx_sample[95:88],
rx_sample[103:96],
rx_sample[111:104]
};
end
//###################################
//#SYNCHRONIZE TO SLOW CLK
//###################################
//stretch access pulse to 4 cycles
pulse_stretcher #(.DW(3))
ps0 (
.out(access_wide),
.in(valid_packet),
.clk(rx_lclk));
always @ (posedge rx_lclk_div4)
rx_access <= access_wide;
always @ (posedge rx_lclk_div4)
if(access_wide)
begin
rx_packet[PW-1:0] <= rx_packet_lclk[PW-1:0];
rx_burst <= burst;
end
//################################
//# I/O Buffers Instantiation
//################################
IBUFDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_data[7:0]
(.I (rxi_data_p[7:0]),
.IB (rxi_data_n[7:0]),
.O (rxi_data[7:0]));
IBUFDS #(.DIFF_TERM ("TRUE"), .IOSTANDARD (IOSTD_ELINK))
ibuf_frame
(.I (rxi_frame_p),
.IB (rxi_frame_n),
.O (rxi_frame));
IBUFGDS #(.DIFF_TERM ("TRUE"),.IOSTANDARD (IOSTD_ELINK))
ibuf_lclk (.I (rxi_lclk_p),
.IB (rxi_lclk_n),
.O (rxi_lclk)
);
generate
if(ETYPE==1)
begin
OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
obuft_wrwait (
.O(rxo_wr_wait_p),
.T(rx_wr_wait),
.I(1'b0)
);
OBUFT #(.IOSTANDARD("LVCMOS18"), .SLEW("SLOW"))
obuft_rdwait (
.O(rxo_rd_wait_p),
.T(rx_rd_wait),
.I(1'b0)
);
assign rxo_wr_wait_n = 1'b0;
assign rxo_rd_wait_n = 1'b0;
end
else if(ETYPE==0)
begin
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_wrwait (
.O(rxo_wr_wait_p),
.OB(rxo_wr_wait_n),
.I(rx_wr_wait)
);
OBUFDS #(.IOSTANDARD(IOSTD_ELINK),.SLEW("SLOW"))
obufds_rdwait (.O(rxo_rd_wait_p),
.OB(rxo_rd_wait_n),
.I(rx_rd_wait)
);
end
endgenerate
//###################################
//#RX CLOCK
//###################################
BUFG rxi_lclk_bufg_i(.I(rxi_lclk), .O(rx_clkin)); //for mmcm
BUFIO rx_lclk_bufio_i(.I(rxi_delay_out[9]), .O(rx_lclk_iddr));//for iddr (NOT USED!)
//###################################
//#IDELAY CIRCUIT
//###################################
assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
genvar j;
generate for(j=0; j<9; j=j+1)
begin : gen_idelay
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("IDATAIN"),
.HIGH_PERFORMANCE_MODE("FALSE"),
.IDELAY_TYPE("VAR_LOAD"),
.IDELAY_VALUE(5'b0),
.PIPE_SEL("FALSE"),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA"))
idelay_inst (.CNTVALUEOUT(), // monitoring value
.DATAOUT(rxi_delay_out[j]), // delayed data
.C(rx_lclk_div4), // variable tap delay clock
.CE(1'b0), // inc/dec tap value
.CINVCTRL(1'b0), // inverts clock polarity
.CNTVALUEIN(idelay_value[(j+1)*5-1:j*5]), //variable tap
.DATAIN(1'b0), // data from FPGA
.IDATAIN(rxi_delay_in[j]), // data from ibuf
.INC(1'b0), // increment tap
.LD(load_taps), // load new
.LDPIPEEN(1'b0), // only for pipeline mode
.REGRST(1'b0) // only for pipeline mode
);
end // block: gen_idelay
endgenerate
//#############################
//# IDDR SAMPLERS
//#############################
//DATA
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_iddr
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_data (
.Q1 (rx_word[i]),
.Q2 (rx_word[i+8]),
.C (rx_lclk),//rx_lclk_iddr
.CE (1'b1),
.D (rxi_delay_out[i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
//FRAME
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .SRTYPE("SYNC"))
iddr_frame (
.Q1 (rx_frame),
.Q2 (),
.C (rx_lclk),//rx_lclk_iddr
.CE (1'b1),
.D (rxi_delay_out[8]),
.R (1'b0),
.S (1'b0)
);
endmodule // erx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
Contributed by Gunnar Hillerstrom
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/* Verilog netlist generated by SCUBA Diamond_2.2_Production (99) */
/* Module Version: 5.1 */
/* C:\lscc\diamond\2.2_x64\ispfpga\bin\nt64\scuba.exe -w -n biosrom -lang verilog -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 16 -num_rows 1024 -memfile c:/users/tmatsuya/dropbox/fpga/magukara/software/biosrom/biosrom.d16 -memformat hex -cascade -1 -e */
/* Tue Aug 05 00:00:20 2014 */
`timescale 1 ns / 1 ps
module biosrom (Address, OutClock, OutClockEn, Reset, Q)/* synthesis NGD_DRC_MASK=1 */;
input wire [9:0] Address;
input wire OutClock;
input wire OutClockEn;
input wire Reset;
output wire [15:0] Q;
wire scuba_vhi;
wire scuba_vlo;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam biosrom_0_0_0.INITVAL_3F = "0x0E500000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biosrom_0_0_0.INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biosrom_0_0_0.INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biosrom_0_0_0.INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biosrom_0_0_0.INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biosrom_0_0_0.INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biosrom_0_0_0.INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000" ;
defparam biosrom_0_0_0.INITVAL_38 = "0x00000000000000000000000000000000000000000007406978045000202002020020200202002020" ;
defparam biosrom_0_0_0.INITVAL_37 = "0x02020020200202002020020200202002020020200202002020020200202002020020200202002020" ;
defparam biosrom_0_0_0.INITVAL_36 = "0x020200006C06F6306F7406F720500005D32031300303A0746C07561066650442002039039390392E" ;
defparam biosrom_0_0_0.INITVAL_35 = "0x02E31030300305B02020020200202002020020200202002020020200202000070061470206506D61" ;
defparam biosrom_0_0_0.INITVAL_34 = "0x07246020720657406E490005D038310353103A3702030038320313A03620034320303103A3502032" ;
defparam biosrom_0_0_0.INITVAL_33 = "0x0313503A34020360353203A33020380323103A32020340363A0315B0202002020020200202002020" ;
defparam biosrom_0_0_0.INITVAL_32 = "0x0202002020020200202002020020200006507A69053200746506B6306150000000047B0047800473" ;
defparam biosrom_0_0_0.INITVAL_31 = "0x0070B004620045200441006D50041100401003D500698003C7003B7003AD006480006C0656306E61" ;
defparam biosrom_0_0_0.INITVAL_30 = "0x0433A0637304520020730656706E6106863020640726106373069640206406E6102074069780453A" ;
defparam biosrom_0_0_0.INITVAL_2F = "0x04E20073650676E061680632006576061730206406E6102074069780453A059000294E02F590283F" ;
defparam biosrom_0_0_0.INITVAL_2E = "0x02073072650746506D61072610502006576061530006D06574049200656706E610684303A7206574" ;
defparam biosrom_0_0_0.INITVAL_2D = "0x06E45020200736D0657404920074630656C0655303A1901800079740696C0697405520061720616B" ;
defparam biosrom_0_0_0.INITVAL_2C = "0x075670614D0000A00D290756E0656D02065068740207007520074720617407320073690205A02D54" ;
defparam biosrom_0_0_0.INITVAL_2B = "0x04C410280A00D0A00D2E0657506E690746E06F630206F074200796506B200796E061200737306572" ;
defparam biosrom_0_0_0.INITVAL_2A = "0x0500A00D0A00D7006A2E0646102E65064690772E063660734007D6E06168063630616D02C610726F" ;
defparam biosrom_0_0_0.INITVAL_29 = "0x0737B0202C034310303202D3203130032200746806769072790706F0430A00D300302E0302006E6F" ;
defparam biosrom_0_0_0.INITVAL_28 = "0x069730726505620079740696C0697405520061720616B075670614D0C358059100CD20000B9001B4" ;
defparam biosrom_0_0_0.INITVAL_27 = "0x051500C35805B59010CD0071100E8B001B4010CD002B40FF3205153050C30EAEB0465805B100CDFF" ;
defparam biosrom_0_0_0.INITVAL_26 = "0x0320E0B453050900900F074C00840408A2E0C35A0585B059100CD090B4FF03251053500581F00450" ;
defparam biosrom_0_0_0.INITVAL_25 = "0x016890D88E0C03301E50052C3058590EFEB0C2FE04600008E80909000A740C0840048A02E00001B9" ;
defparam biosrom_0_0_0.INITVAL_24 = "0x051500C35805B5905A1F010CD000000B9070B706000B804A040843608A0404A1608AD808EC00331E" ;
defparam biosrom_0_0_0.INITVAL_23 = "0x05251053500C3C30FFB40C346000040C6C305FF80E246047050880408A00010B90071A0BF570C3FD" ;
defparam biosrom_0_0_0.INITVAL_22 = "0x0E6E80001000714006C70900000713006C60C35F0F8E204647004880058A000100B90701ABF057C3" ;
defparam biosrom_0_0_0.INITVAL_21 = "0x00718016890DEEB0D00A004E20C12002C90090040721003C0702C900900C0720A03C3002C900901B" ;
defparam biosrom_0_0_0.INITVAL_20 = "0x074C0084460048A0D2330909002A740003C080C30FE370E80000407014060C79000107013060C6C3" ;
defparam biosrom_0_0_0.INITVAL_1F = "0x046040880700490090040723A03C30004040E2C1004E80C0C608AC305A00004C6000050E800008E8" ;
defparam biosrom_0_0_0.INITVAL_1E = "0x0000B0E80000EE8007180168B052C3007170A23002C9009007074C00840408AC30FE810E80000107" ;
defparam biosrom_0_0_0.INITVAL_1D = "0x014060C79000207013060C6C3004890E43203004007170A0C30CF030071400E8B0F4EB046C20FEFE" ;
defparam biosrom_0_0_0.INITVAL_1C = "0x0B28400F0003C800FEB90E9F708BD002AC702BC608BFE0C4E905E5A0012D0E800001B9020B00011C" ;
defparam biosrom_0_0_0.INITVAL_1B = "0x0E852056CA0FE4E05EF6075C0084460FF440880408A560FEE50840F0F73B090160EB5E0F6750C084" ;
defparam biosrom_0_0_0.INITVAL_1A = "0x04604088010448A056FE0FA8400F0003C800FF010E94E0CAFE0FF070840F0F73B0FF0D0E9460C2FE" ;
defparam biosrom_0_0_0.INITVAL_19 = "0x0FF130840F0003C080C30FF1B0E9C20FE01084E8000010B9240889009004075E408446004880248A" ;
defparam biosrom_0_0_0.INITVAL_18 = "0x0FF330830F0F13B0008C0E8FF03CE905EFF040E90C2FE0465A05E01093E805652004880F6770F13B" ;
defparam biosrom_0_0_0.INITVAL_17 = "0x04E24088FF0648A059900901C073F103BF3075E4084460248A09090029730F13B056000C1E809090" ;
defparam biosrom_0_0_0.INITVAL_16 = "0x0377401F5808004017060F6D808EC00335001E820774603C860724103CDF0248C07490002070133E" ;
defparam biosrom_0_0_0.INITVAL_15 = "0x08090090140763903C9A0723003C900901E07490000070133E080A80722003C000AB8400F530003D" ;
defparam biosrom_0_0_0.INITVAL_14 = "0x0B3740520003D000FF8400F4F0003D000A50840F04D0003D000B98400F4B0003D000B20840F04800" ;
defparam biosrom_0_0_0.INITVAL_13 = "0x03D010108400F470003D000C00840F0500003D000C78400F1C0FC80000CE0840F001FC0800100584" ;
defparam biosrom_0_0_0.INITVAL_12 = "0x00F0803C160CD000B4100CD020B4FF0325E05A0204DE8052560FE8B0029F0E8F0000FF0F0EA0D7EB" ;
defparam biosrom_0_0_0.INITVAL_11 = "0x0F8E204746005880048A000670BF0701ABE000100B900065A3007180A100064A2007170A0C3010CD" ;
defparam biosrom_0_0_0.INITVAL_10 = "0x0007F025100CD0F0B4E90754E03C90090100745903CDF024FE0ED8400F010FC80016CD000B40029C" ;
defparam biosrom_0_0_0.INITVAL_0F = "0x0E8050E7BE018000BA070B3020A7E8005D00BE14005BA070B30FF270E990006550FF2E0072A0BEFF" ;
defparam biosrom_0_0_0.INITVAL_0E = "0x0328500F1C0FC8009090014740FFFC0805F0032C0E890004550FF2E057150B20702ABE09002055FF" ;
defparam biosrom_0_0_0.INITVAL_0D = "0x02E0702ABE002E20E8070B3070163600202001BA090900358B02EF800306026BF0E4F6008B400716" ;
defparam biosrom_0_0_0.INITVAL_0C = "0x0A0FF074E90900000716006C60FF7D0820F090040071603E8000716006FE08BEB0900300716006C6" ;
defparam biosrom_0_0_0.INITVAL_0B = "0x093790071600EFE0E5EB090900297401CFC0809009019074500FC800909001274048FC080160CD00" ;
defparam biosrom_0_0_0.INITVAL_0A = "0x0B4B90EBC60FE90008C708303047E80072A0BE150B290002550FF2E0072A0BE03070E80CA2A00015" ;
defparam biosrom_0_0_0.INITVAL_09 = "0x0B9200B003061E8007B304603067E8070B3090900047500716006380022C0C68A007B30909003D74" ;
defparam biosrom_0_0_0.INITVAL_08 = "0x0F685090900358B001B2006260BF020B60308BE8005AD0BE18000BA003940E80509CBE0D233007B3" ;
defparam biosrom_0_0_0.INITVAL_07 = "0x0037C0E804001E80F8E204746005880048A0071A0BF00067BE000100B907018A3000650A107017A2" ;
defparam biosrom_0_0_0.INITVAL_06 = "0x000640A0070110E089100CDFF032030B4CB004880FBE20460402AF6033C003249009E10C1CB00077" ;
defparam biosrom_0_0_0.INITVAL_05 = "0x006C60000200E88009E90C1010FFC108100078B90CB00024E8090900057502C0003D160CD000B490" ;
defparam biosrom_0_0_0.INITVAL_04 = "0x00FEB0E47504AEA0E2900900A075160CD010B4FA075100A8610E4FA074100A8610E482035B900008" ;
defparam biosrom_0_0_0.INITVAL_03 = "0x0BA04053E80050A0BE1F00E20020200202002020020500445502F340565004900012010000000000" ;
defparam biosrom_0_0_0.INITVAL_02 = "0x00000000040000000000000000000008000037760524904350000290204D04F52020540412F04350" ;
defparam biosrom_0_0_0.INITVAL_01 = "0x0207206F6602028020650676106D490206D061720676F072500206506C7006D610532004D4F05220" ;
defparam biosrom_0_0_0.INITVAL_00 = "0x06E6F069740704F0004C04D4F0526E06F690747004F20064720616F0424904350090720EB040AA55" ;
defparam biosrom_0_0_0.CSDECODE_B = "0b111" ;
defparam biosrom_0_0_0.CSDECODE_A = "0b000" ;
defparam biosrom_0_0_0.WRITEMODE_B = "NORMAL" ;
defparam biosrom_0_0_0.WRITEMODE_A = "NORMAL" ;
defparam biosrom_0_0_0.GSR = "DISABLED" ;
defparam biosrom_0_0_0.REGMODE_B = "NOREG" ;
defparam biosrom_0_0_0.REGMODE_A = "NOREG" ;
defparam biosrom_0_0_0.DATA_WIDTH_B = 18 ;
defparam biosrom_0_0_0.DATA_WIDTH_A = 18 ;
DP16KC biosrom_0_0_0 (.DIA0(scuba_vlo), .DIA1(scuba_vlo), .DIA2(scuba_vlo),
.DIA3(scuba_vlo), .DIA4(scuba_vlo), .DIA5(scuba_vlo), .DIA6(scuba_vlo),
.DIA7(scuba_vlo), .DIA8(scuba_vlo), .DIA9(scuba_vlo), .DIA10(scuba_vlo),
.DIA11(scuba_vlo), .DIA12(scuba_vlo), .DIA13(scuba_vlo), .DIA14(scuba_vlo),
.DIA15(scuba_vlo), .DIA16(scuba_vlo), .DIA17(scuba_vlo), .ADA0(scuba_vlo),
.ADA1(scuba_vlo), .ADA2(scuba_vlo), .ADA3(scuba_vlo), .ADA4(Address[0]),
.ADA5(Address[1]), .ADA6(Address[2]), .ADA7(Address[3]), .ADA8(Address[4]),
.ADA9(Address[5]), .ADA10(Address[6]), .ADA11(Address[7]), .ADA12(Address[8]),
.ADA13(Address[9]), .CEA(OutClockEn), .CLKA(OutClock), .OCEA(OutClockEn),
.WEA(scuba_vlo), .CSA0(scuba_vlo), .CSA1(scuba_vlo), .CSA2(scuba_vlo),
.RSTA(Reset), .DIB0(scuba_vlo), .DIB1(scuba_vlo), .DIB2(scuba_vlo),
.DIB3(scuba_vlo), .DIB4(scuba_vlo), .DIB5(scuba_vlo), .DIB6(scuba_vlo),
.DIB7(scuba_vlo), .DIB8(scuba_vlo), .DIB9(scuba_vlo), .DIB10(scuba_vlo),
.DIB11(scuba_vlo), .DIB12(scuba_vlo), .DIB13(scuba_vlo), .DIB14(scuba_vlo),
.DIB15(scuba_vlo), .DIB16(scuba_vlo), .DIB17(scuba_vlo), .ADB0(scuba_vlo),
.ADB1(scuba_vlo), .ADB2(scuba_vlo), .ADB3(scuba_vlo), .ADB4(scuba_vlo),
.ADB5(scuba_vlo), .ADB6(scuba_vlo), .ADB7(scuba_vlo), .ADB8(scuba_vlo),
.ADB9(scuba_vlo), .ADB10(scuba_vlo), .ADB11(scuba_vlo), .ADB12(scuba_vlo),
.ADB13(scuba_vlo), .CEB(scuba_vhi), .CLKB(scuba_vlo), .OCEB(scuba_vhi),
.WEB(scuba_vlo), .CSB0(scuba_vlo), .CSB1(scuba_vlo), .CSB2(scuba_vlo),
.RSTB(scuba_vlo), .DOA0(Q[0]), .DOA1(Q[1]), .DOA2(Q[2]), .DOA3(Q[3]),
.DOA4(Q[4]), .DOA5(Q[5]), .DOA6(Q[6]), .DOA7(Q[7]), .DOA8(Q[8]),
.DOA9(Q[9]), .DOA10(Q[10]), .DOA11(Q[11]), .DOA12(Q[12]), .DOA13(Q[13]),
.DOA14(Q[14]), .DOA15(Q[15]), .DOA16(), .DOA17(), .DOB0(), .DOB1(),
.DOB2(), .DOB3(), .DOB4(), .DOB5(), .DOB6(), .DOB7(), .DOB8(), .DOB9(),
.DOB10(), .DOB11(), .DOB12(), .DOB13(), .DOB14(), .DOB15(), .DOB16(),
.DOB17())
/* synthesis MEM_LPC_FILE="biosrom.lpc" */
/* synthesis MEM_INIT_FILE="biosrom.d16" */
/* synthesis RESETMODE="SYNC" */;
// exemplar begin
// exemplar attribute biosrom_0_0_0 MEM_LPC_FILE biosrom.lpc
// exemplar attribute biosrom_0_0_0 MEM_INIT_FILE biosrom.d16
// exemplar attribute biosrom_0_0_0 RESETMODE SYNC
// exemplar end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_BEHAVIORAL_PP_V
|
module Datapath(
output [3:0] FLAG_out, // Flag Bus
output [WORD_WIDTH-1:0] A_bus, // Address out Bus
output [WORD_WIDTH-1:0] D_bus, // Data out Bus
input [WORD_WIDTH-1:0] D_in, // Data in bus
input [15:0] CNTRL_in, // Instruction Bus
input [WORD_WIDTH-1:0] CONST_in, // Constant In Bus
input CLK
);
parameter WORD_WIDTH = 16;
Datapath_RegisterFile RF0 (
.A_data(A_bus),
.B_data(RF0_out_B),
.D_data(BMD_out),
.AA(CNTRL_in[9:7]),
.BA(CNTRL_in[12:10]),
.DA(CNTRL_in[15:13]),
.RW(CNTRL_in[0]),
.CLK(CLK)
);
Datapath_BusMuxer BMB(
.out(D_bus),
.A_in(RF0_out_B),
.B_in(CONST_in),
.S(CNTRL_in[6])
);
Datapath_BusMuxer BMD(
.out(BMD_out),
.A_in(FU0_out),
.B_in(D_in),
.S(CNTRL_in[1])
);
Datapath_FunctionUnit FU0(
.F(FU0_out),
.V(FLAG_out[3]),
.C(FLAG_out[2]),
.N(FLAG_out[1]),
.Z(FLAG_out[0]),
.A(A_bus),
.B(D_bus),
.FS(FS)
);
defparam FU0.WORD_WIDTH = WORD_WIDTH;
defparam BMD.WORD_WIDTH = WORD_WIDTH;
defparam BMB.WORD_WIDTH = WORD_WIDTH;
defparam RF0.WORD_WIDTH = WORD_WIDTH;
endmodule
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export CoRN.reals.IVT.
Import CRing_Homomorphisms.coercions.
(**
* Roots of polynomials of odd degree *)
Section CPoly_Big.
(**
** Monic polynomials are positive near infinity
%\begin{convention}% Let [R] be an ordered field.
%\end{convention}%
*)
Variable R : COrdField.
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Lemma Cbigger : forall x y : R, {z : R | x [<=] z | y [<=] z}.
Proof.
intros.
elim (less_cotransitive_unfolded _ x (x[+][1]) (less_plusOne _ _) y); intro.
exists (y[+][1]); apply less_leEq.
apply less_leEq_trans with y. auto. apply less_leEq; apply less_plusOne.
apply less_plusOne.
exists (x[+][1]); apply less_leEq.
apply less_plusOne.
auto.
Qed.
Lemma Ccpoly_big : forall (p : RX) n, 0 < n ->
monic n p -> forall Y, {X : R | forall x, X [<=] x -> Y [<=] p ! x}.
Proof.
intro. elim p.
unfold monic in |- *. simpl in |- *. intros. elim H0. intros H1 H2.
cut ([0][~=] ([1]:R)). intro. elim (H3 H1).
apply ap_imp_neq. apply ap_symmetric_unfolded. apply ring_non_triv.
intros c q. intros H n H0 H1 Y.
elim (O_or_S n); intro y. elim y. intro m. intro y0.
rewrite <- y0 in H1.
elim (zerop m); intro y1. simpl in |- *.
exists (Y[-]c). intros.
rewrite y1 in H1.
apply shift_leEq_plus'.
cut (q ! x [=] [1]). intro.
astepr (x[*][1]). astepr x. auto.
apply monic_one with c. auto.
cut (monic m q). intro H2.
elim (Cbigger [0] (Y[-]c)). intro Y'. intros H3 H4.
elim (H m y1 H2 Y'). intro X'. intro H5.
simpl in |- *.
elim (Cbigger [1] X'). intro X. intros H6 H7.
exists X. intros.
apply shift_leEq_plus'.
apply leEq_transitive with ([1][*]Y').
astepr Y'. auto.
apply mult_resp_leEq_both; auto.
apply less_leEq. apply pos_one.
apply leEq_transitive with X; auto.
change (Y' [<=] q ! x) in |- *.
apply H5.
apply leEq_transitive with X; auto.
apply monic_cpoly_linear with c; auto.
rewrite <- y in H0.
elim (lt_irrefl _ H0).
Qed.
Lemma cpoly_pos : forall (p : RX) n, 0 < n -> monic n p -> {x : R | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_big _ _ H H0 [0]). intros x H1.
exists (x[+][1]).
apply H1. apply less_leEq. apply less_plusOne.
Qed.
Lemma Ccpoly_pos' : forall (p : RX) a n, 0 < n -> monic n p -> {x : R | a [<] x | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_big _ _ H H0 [0]). intro x'. intro H1.
elim (Cbigger (a[+][1]) x'). intro x. intros.
exists x; auto.
apply less_leEq_trans with (a[+][1]).
apply less_plusOne. auto.
Qed.
End CPoly_Big.
Section Flip_Poly.
(**
** Flipping a polynomial
%\begin{convention}% Let [R] be a ring.
%\end{convention}%
*)
Variable R : CRing.
Add Ring R: (CRing_Ring R).
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Fixpoint flip (p : RX) : RX :=
match p with
| cpoly_zero _ => cpoly_zero _
| cpoly_linear _ c q => cpoly_inv _ (cpoly_linear _ c (flip q))
end.
Lemma flip_poly : forall (p : RX) x, (flip p) ! x [=] [--]p ! ( [--]x).
Proof.
intro p. elim p.
intros. simpl in |- *. algebra.
intros c q. intros.
change ( [--]c[+]x[*] (cpoly_inv _ (flip q)) ! x [=] [--] (c[+][--]x[*]q ! ( [--]x))) in |- *.
astepl ( [--]c[+]x[*][--] (flip q) ! x).
astepl ( [--]c[+]x[*][--][--]q ! ( [--]x)).
ring.
Qed.
Lemma flip_coefficient : forall (p : RX) i,
nth_coeff i (flip p) [=] [--] ( [--][1][^]i) [*]nth_coeff i p.
Proof.
intro p. elim p.
simpl in |- *. algebra.
intros c q. intros.
elim i. simpl in |- *. ring.
intros. simpl in |- *.
astepl ( [--] (nth_coeff n (flip q))).
astepl ( [--] ( [--] ( [--][1][^]n) [*]nth_coeff n q)).
simpl in |- *. ring.
Qed.
Hint Resolve flip_coefficient: algebra.
Lemma flip_odd : forall (p : RX) n, odd n -> monic n p -> monic n (flip p).
Proof.
unfold monic in |- *. unfold degree_le in |- *.
intros.
elim H0. clear H0. intros.
split.
astepl ( [--] ( [--][1][^]n) [*]nth_coeff n p).
astepl ( [--][--] ([1][^]n) [*]nth_coeff n p).
astepl ([1][^]n[*]nth_coeff n p).
astepl ([1][*]nth_coeff n p).
Step_final ([1][*] ([1]:R)).
intros.
astepl ( [--] ( [--][1][^]m) [*]nth_coeff m p).
Step_final ( [--] ( [--][1][^]m) [*] ([0]:R)).
Qed.
End Flip_Poly.
Hint Resolve flip_poly: algebra.
Section OddPoly_Signs.
(**
** Sign of a polynomial of odd degree
%\begin{convention}% Let [R] be an ordered field.
%\end{convention}%
*)
Variable R : COrdField.
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Lemma oddpoly_pos : forall (p : RX) n, odd n -> monic n p -> {x : R | [0] [<=] p ! x}.
Proof.
intros.
apply cpoly_pos with n; auto.
elim H. intros. auto with arith.
Qed.
Lemma oddpoly_pos' : forall (p : RX) a n,
odd n -> monic n p -> {x : R | a [<] x | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_pos' _ p a n). intros x H1 H2.
exists x; assumption.
elim H; auto with arith.
assumption.
Qed.
Lemma oddpoly_neg : forall (p : RX) n, odd n -> monic n p -> {x : R | p ! x [<=] [0]}.
Proof.
intros.
elim (oddpoly_pos _ _ H (flip_odd _ _ _ H H0)). intro x. intros.
exists ( [--]x).
astepl ( [--][--]p ! ( [--]x)). astepr ( [--] ([0]:R)).
apply inv_resp_leEq.
astepr (flip _ p) ! x. auto.
Qed.
End OddPoly_Signs.
Section Poly_Norm.
(**
** The norm of a polynomial
%\begin{convention}% Let [R] be a field, and [RX] the polynomials over
this field.
%\end{convention}%
*)
Variable R : CField.
(* begin hide *)
Let RX := cpoly_cring R.
(* end hide *)
Lemma poly_norm_aux : forall (p : RX) n, degree n p -> nth_coeff n p [#] [0].
Proof.
unfold degree in |- *. intros p n H.
elim H. auto.
Qed.
Definition poly_norm p n H := _C_ ([1][/] _[//]poly_norm_aux p n H) [*]p.
Lemma poly_norm_monic : forall p n H, monic n (poly_norm p n H).
Proof.
unfold poly_norm in |- *. unfold monic in |- *. unfold degree in |- *. unfold degree_le in |- *. intros.
elim H. intros H0 H1.
split.
Step_final (([1][/] nth_coeff n p[//]poly_norm_aux p n (pair H0 H1)) [*] nth_coeff n p).
intros.
astepl (([1][/] nth_coeff n p[//]poly_norm_aux p n (pair H0 H1)) [*] nth_coeff m p).
Step_final (([1][/] nth_coeff n p[//]poly_norm_aux p n H) [*][0]).
Qed.
Lemma poly_norm_apply : forall p n H x, (poly_norm p n H) ! x [=] [0] -> p ! x [=] [0].
Proof.
unfold poly_norm in |- *. intros.
apply mult_cancel_lft with ([1][/] nth_coeff n p[//]poly_norm_aux p n H).
apply div_resp_ap_zero_rev. apply ring_non_triv.
astepl ((_C_ ([1][/] nth_coeff n p[//]poly_norm_aux p n H)) ! x[*]p ! x).
astepl (_C_ ([1][/] nth_coeff n p[//]poly_norm_aux p n H) [*]p) ! x.
Step_final ([0]:R).
Qed.
End Poly_Norm.
Section OddPoly_Root.
(**
** Roots of polynomials of odd degree
Polynomials of odd degree over the reals always have a root. *)
Lemma oddpoly_root' : forall f n, odd n -> monic n f -> {x : IR | f ! x [=] [0]}.
Proof.
intros.
elim (oddpoly_neg _ f n); auto. intro a. intro H1.
elim (oddpoly_pos' _ f a n); auto. intro b. intros H2 H3.
cut {x : IR | a [<=] x /\ x [<=] b /\ f ! x [=] [0]}.
intro H4.
elim H4. clear H4. intros x H4.
elim H4. clear H4. intros H4 H5.
elim H5. clear H5. intros.
exists x. auto.
apply Civt_poly; auto.
apply monic_apzero with n; auto.
Qed.
Lemma oddpoly_root : forall f n, odd n -> degree n f -> {x : IR | f ! x [=] [0]}.
Proof.
intros f n H H0.
elim (oddpoly_root' (poly_norm _ f n H0) n); auto.
intros. exists x.
apply poly_norm_apply with n H0; auto.
apply poly_norm_monic; auto.
Qed.
Lemma realpolyn_oddhaszero : forall f, odd_cpoly _ f -> {x : IR | f ! x [=] [0]}.
Proof.
unfold odd_cpoly in |- *.
intros f H.
elim H. clear H. intro n. intros H H0.
cut (odd n).
intro.
elim (oddpoly_root f n H1 H0). intros. exists x. auto.
apply Codd_to.
assumption.
Qed.
End OddPoly_Root.
|
// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
logic_four <= 4'h0;
m_def2_r <= {(1+(`M)-(`L)){1'b0}};
m_param_r <= {(1+(MS)-(LS)){1'b0}};
m_wid1_r <= 1'h0;
m_wid3_r <= 3'h0;
m_wid4_r_l <= ~4'h0;
paramed <= {PARAM{1'b0}};
// End of automatics
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: t
// verilog-active-low-regexp: "_l$"
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/08 20:53:23
// Design Name:
// Module Name: timing_signal
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module timing_signal
#(parameter LEN = 4)
(
input clk,
input clr_n,
output [(LEN-1):0] Tp
);
// D_ff
wire D_Q, D_Qbar;
// rotate register
wire [(LEN-1):0] Q, Qbar;
// output timing signal
assign Tp = {Qbar[3], Q[1], Q[2]&Qbar[1], Q[3]&Qbar[2]};
D_ff #(.LEN(1)) D (
.clk(~clk),
.clr_n(clr_n),
.D(Q[1]),
.Q(D_Q),
.Qbar(D_Qbar));
rotate_shift_register #(LEN) ROTATE (
.clk(~(~clk&D_Qbar)),
.clr(clk&D_Q),
.D({1'b1, Q[3], Q[2],1'b0}),
.Q(Q),
.Qbar(Qbar));
endmodule
|
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