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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_TB_V
`define SKY130_FD_SC_LP__O2111A_TB_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o2111a dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: franp.com
// Engineer: Fran Pregernik <[email protected]>
//
// Create Date: 01/06/2017 05:35:32 AM
// Design Name:
// Module Name: clk_divider_15_1_mhz
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module acp_generator(
// Declare the attributes above the port declaration
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 IN_CLK CLK" *)
// Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET, ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
// Output clocks will require FREQ_HZ to be set (note the value is in HZ and an integer is expected).
(* X_INTERFACE_PARAMETER = "FREQ_HZ 100000000" *)
input IN_CLK, // (required)
output RADAR_ACP // (required)
);
// 100_000_000 MHz / 146484 = 682 Hz
clk_divider #(146484) cd(
.IN_SIG(IN_CLK),
.OUT_SIG(RADAR_ACP)
);
endmodule
|
/*
* Copyright (c) Mercury Federal Systems, Inc., Arlington VA., 2009-2010
*
* Mercury Federal Systems, Incorporated
* 1901 South Bell Street
* Suite 402
* Arlington, Virginia 22202
* United States of America
* Telephone 703-413-0781
* FAX 703-413-0784
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
//
// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24)
//
// On Thu Aug 19 14:12:06 EDT 2010
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 32 reg
// wsiM0_MByteEn O 4 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 20
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef ORIGINAL
module mkDDCWorker(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
parameter [31 : 0] ddcCtrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [19 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [31 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [3 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [31 : 0] wciS0_SData, wsiM0_MData;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [3 : 0] wsiM0_MByteEn;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
`else
`define NOT_EMPTY_ddc.v
`include "ddc_defs.v"
`endif
// inlined wires
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [60 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [59 : 0] wci_wciReq$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] ddc_sRegPwdata_w$wget,
wci_Es_mData_w$wget,
wsi_Es_mData_w$wget;
wire [19 : 0] wci_Es_mAddr_w$wget;
wire [15 : 0] ddc_sDataR_w$wget;
wire [11 : 0] ddc_sRegPaddr_w$wget, wsi_Es_mBurstLength_w$wget;
wire [7 : 0] wsi_Es_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget, wsi_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget;
wire ddc_dataResetn_w$wget,
ddc_dataResetn_w$whas,
ddc_mDataReady_w$wget,
ddc_mDataReady_w$whas,
ddc_sDataR_w$whas,
ddc_sDataValid_w$wget,
ddc_sDataValid_w$whas,
ddc_sRegPaddr_w$whas,
ddc_sRegPenable_w$wget,
ddc_sRegPenable_w$whas,
ddc_sRegPsel_w$wget,
ddc_sRegPsel_w$whas,
ddc_sRegPwdata_w$whas,
ddc_sRegPwrite_w$wget,
ddc_sRegPwrite_w$whas,
wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_doResetClr$whas,
wsiS_reqFifo_doResetDeq$whas,
wsiS_reqFifo_doResetEnq$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_sThreadBusy_dw$wget,
wsiS_sThreadBusy_dw$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register ambaErrCnt
reg [31 : 0] ambaErrCnt;
wire [31 : 0] ambaErrCnt$D_IN;
wire ambaErrCnt$EN;
// register ambaRdReqCnt
reg [31 : 0] ambaRdReqCnt;
wire [31 : 0] ambaRdReqCnt$D_IN;
wire ambaRdReqCnt$EN;
// register ambaRespCnt
reg [31 : 0] ambaRespCnt;
wire [31 : 0] ambaRespCnt$D_IN;
wire ambaRespCnt$EN;
// register ambaWrReqCnt
reg [31 : 0] ambaWrReqCnt;
wire [31 : 0] ambaWrReqCnt$D_IN;
wire ambaWrReqCnt$EN;
// register ddcCtrl
reg [31 : 0] ddcCtrl;
wire [31 : 0] ddcCtrl$D_IN;
wire ddcCtrl$EN;
// register ddc_reqSetup
reg ddc_reqSetup;
wire ddc_reqSetup$D_IN, ddc_reqSetup$EN;
// register ddc_started
reg ddc_started;
wire ddc_started$D_IN, ddc_started$EN;
// register outMesgCnt
reg [31 : 0] outMesgCnt;
wire [31 : 0] outMesgCnt$D_IN;
wire outMesgCnt$EN;
// register splitReadInFlight
reg splitReadInFlight;
wire splitReadInFlight$D_IN, splitReadInFlight$EN;
// register splitWriteInFlight
reg splitWriteInFlight;
wire splitWriteInFlight$D_IN, splitWriteInFlight$EN;
// register takeEven
reg takeEven;
wire takeEven$D_IN, takeEven$EN;
// register unloadCnt
reg [15 : 0] unloadCnt;
wire [15 : 0] unloadCnt$D_IN;
wire unloadCnt$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [60 : 0] wsiM_reqFifo_q_0;
reg [60 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [60 : 0] wsiM_reqFifo_q_1;
reg [60 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength$D_IN;
wire wsiS_mesgWordLength$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount$D_IN;
wire wsiS_wordCount$EN;
// ports of submodule ddc_apbReqF
wire [45 : 0] ddc_apbReqF$D_IN, ddc_apbReqF$D_OUT;
wire ddc_apbReqF$CLR,
ddc_apbReqF$DEQ,
ddc_apbReqF$EMPTY_N,
ddc_apbReqF$ENQ,
ddc_apbReqF$FULL_N;
// ports of submodule ddc_apbRespF
wire [32 : 0] ddc_apbRespF$D_IN, ddc_apbRespF$D_OUT;
wire ddc_apbRespF$CLR,
ddc_apbRespF$DEQ,
ddc_apbRespF$EMPTY_N,
ddc_apbRespF$ENQ,
ddc_apbRespF$FULL_N;
// ports of submodule ddc_ddc
wire [31 : 0] ddc_ddc$sreg_prdata, ddc_ddc$sreg_pwdata;
wire [15 : 0] ddc_ddc$mdata_i, ddc_ddc$mdata_q, ddc_ddc$sdata_r;
wire [11 : 0] ddc_ddc$sreg_paddr;
wire ddc_ddc$data_resetn,
ddc_ddc$int_ducddc,
ddc_ddc$int_errpacket,
ddc_ddc$int_lostoutput,
ddc_ddc$int_missinput,
ddc_ddc$mdata_ready,
ddc_ddc$mdata_valid,
ddc_ddc$sdata_ready,
ddc_ddc$sdata_valid,
ddc_ddc$sreg_penable,
ddc_ddc$sreg_pready,
ddc_ddc$sreg_psel,
ddc_ddc$sreg_pslverr,
ddc_ddc$sreg_pwrite;
// ports of submodule ddc_xkF
wire [31 : 0] ddc_xkF$D_IN, ddc_xkF$D_OUT;
wire ddc_xkF$CLR, ddc_xkF$DEQ, ddc_xkF$EMPTY_N, ddc_xkF$ENQ, ddc_xkF$FULL_N;
// ports of submodule ddc_xnF
wire [15 : 0] ddc_xnF$D_IN, ddc_xnF$D_OUT;
wire ddc_xnF$CLR, ddc_xnF$DEQ, ddc_xnF$EMPTY_N, ddc_xnF$ENQ, ddc_xnF$FULL_N;
// ports of submodule wci_isReset
wire wci_isReset$VAL;
// ports of submodule wci_reqF
wire [59 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wsiM_isReset
wire wsiM_isReset$VAL;
// ports of submodule wsiS_isReset
wire wsiS_isReset$VAL;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// ports of submodule xnF
wire [31 : 0] xnF$D_IN, xnF$D_OUT;
wire xnF$CLR, xnF$DEQ, xnF$EMPTY_N, xnF$ENQ, xnF$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_advance_wci_response,
CAN_FIRE_RL_ddcEnable_doEgress,
CAN_FIRE_RL_ddcEnable_doIngress,
CAN_FIRE_RL_ddcEnable_output_feedDDC,
CAN_FIRE_RL_ddcPass_bypass,
CAN_FIRE_RL_ddc_ddc_stream_egress,
CAN_FIRE_RL_ddc_ddc_stream_ingress,
CAN_FIRE_RL_ddc_drive_ddc_always_enabled,
CAN_FIRE_RL_ddc_run,
CAN_FIRE_RL_ddc_sreg_request,
CAN_FIRE_RL_ddc_start,
CAN_FIRE_RL_operating_actions,
CAN_FIRE_RL_wci_Es_doAlways_Req,
CAN_FIRE_RL_wci_cfrd,
CAN_FIRE_RL_wci_cfwr,
CAN_FIRE_RL_wci_ctlAckReg__dreg_update,
CAN_FIRE_RL_wci_ctl_op_complete,
CAN_FIRE_RL_wci_ctl_op_start,
CAN_FIRE_RL_wci_ctrl_EiI,
CAN_FIRE_RL_wci_ctrl_IsO,
CAN_FIRE_RL_wci_ctrl_OrE,
CAN_FIRE_RL_wci_reqF__updateLevelCounter,
CAN_FIRE_RL_wci_reqF_enq,
CAN_FIRE_RL_wci_request_decode,
CAN_FIRE_RL_wci_respF_both,
CAN_FIRE_RL_wci_respF_decCtr,
CAN_FIRE_RL_wci_respF_deq,
CAN_FIRE_RL_wci_respF_incCtr,
CAN_FIRE_RL_wci_sFlagReg__dreg_update,
CAN_FIRE_RL_wci_sThreadBusy_reg,
CAN_FIRE_RL_wsiM_ext_status_assign,
CAN_FIRE_RL_wsiM_inc_tBusyCount,
CAN_FIRE_RL_wsiM_operateD__dreg_update,
CAN_FIRE_RL_wsiM_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiM_reqFifo_both,
CAN_FIRE_RL_wsiM_reqFifo_decCtr,
CAN_FIRE_RL_wsiM_reqFifo_deq,
CAN_FIRE_RL_wsiM_reqFifo_incCtr,
CAN_FIRE_RL_wsiM_sThreadBusy_reg,
CAN_FIRE_RL_wsiM_update_statusR,
CAN_FIRE_RL_wsiS_backpressure,
CAN_FIRE_RL_wsiS_ext_status_assign,
CAN_FIRE_RL_wsiS_inc_tBusyCount,
CAN_FIRE_RL_wsiS_operateD__dreg_update,
CAN_FIRE_RL_wsiS_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
CAN_FIRE_RL_wsiS_reqFifo_enq,
CAN_FIRE_RL_wsiS_reqFifo_reset,
CAN_FIRE_RL_wsiS_update_statusR,
CAN_FIRE_RL_wsi_Es_doAlways,
CAN_FIRE_wciS0_mAddr,
CAN_FIRE_wciS0_mAddrSpace,
CAN_FIRE_wciS0_mByteEn,
CAN_FIRE_wciS0_mCmd,
CAN_FIRE_wciS0_mData,
CAN_FIRE_wciS0_mFlag,
CAN_FIRE_wsiM0_sReset_n,
CAN_FIRE_wsiM0_sThreadBusy,
CAN_FIRE_wsiS0_mBurstLength,
CAN_FIRE_wsiS0_mBurstPrecise,
CAN_FIRE_wsiS0_mByteEn,
CAN_FIRE_wsiS0_mCmd,
CAN_FIRE_wsiS0_mData,
CAN_FIRE_wsiS0_mDataInfo,
CAN_FIRE_wsiS0_mReqInfo,
CAN_FIRE_wsiS0_mReqLast,
CAN_FIRE_wsiS0_mReset_n,
WILL_FIRE_RL_advance_wci_response,
WILL_FIRE_RL_ddcEnable_doEgress,
WILL_FIRE_RL_ddcEnable_doIngress,
WILL_FIRE_RL_ddcEnable_output_feedDDC,
WILL_FIRE_RL_ddcPass_bypass,
WILL_FIRE_RL_ddc_ddc_stream_egress,
WILL_FIRE_RL_ddc_ddc_stream_ingress,
WILL_FIRE_RL_ddc_drive_ddc_always_enabled,
WILL_FIRE_RL_ddc_run,
WILL_FIRE_RL_ddc_sreg_request,
WILL_FIRE_RL_ddc_start,
WILL_FIRE_RL_operating_actions,
WILL_FIRE_RL_wci_Es_doAlways_Req,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctlAckReg__dreg_update,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_reqF__updateLevelCounter,
WILL_FIRE_RL_wci_reqF_enq,
WILL_FIRE_RL_wci_request_decode,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_deq,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wci_sFlagReg__dreg_update,
WILL_FIRE_RL_wci_sThreadBusy_reg,
WILL_FIRE_RL_wsiM_ext_status_assign,
WILL_FIRE_RL_wsiM_inc_tBusyCount,
WILL_FIRE_RL_wsiM_operateD__dreg_update,
WILL_FIRE_RL_wsiM_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiM_sThreadBusy_reg,
WILL_FIRE_RL_wsiM_update_statusR,
WILL_FIRE_RL_wsiS_backpressure,
WILL_FIRE_RL_wsiS_ext_status_assign,
WILL_FIRE_RL_wsiS_inc_tBusyCount,
WILL_FIRE_RL_wsiS_operateD__dreg_update,
WILL_FIRE_RL_wsiS_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset,
WILL_FIRE_RL_wsiS_update_statusR,
WILL_FIRE_RL_wsi_Es_doAlways,
WILL_FIRE_wciS0_mAddr,
WILL_FIRE_wciS0_mAddrSpace,
WILL_FIRE_wciS0_mByteEn,
WILL_FIRE_wciS0_mCmd,
WILL_FIRE_wciS0_mData,
WILL_FIRE_wciS0_mFlag,
WILL_FIRE_wsiM0_sReset_n,
WILL_FIRE_wsiM0_sThreadBusy,
WILL_FIRE_wsiS0_mBurstLength,
WILL_FIRE_wsiS0_mBurstPrecise,
WILL_FIRE_wsiS0_mByteEn,
WILL_FIRE_wsiS0_mCmd,
WILL_FIRE_wsiS0_mData,
WILL_FIRE_wsiS0_mDataInfo,
WILL_FIRE_wsiS0_mReqInfo,
WILL_FIRE_wsiS0_mReqLast,
WILL_FIRE_wsiS0_mReset_n;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1;
wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
MUX_wsiM_reqFifo_q_1$write_1__VAL_2,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1;
wire [45 : 0] MUX_ddc_apbReqF$enq_1__VAL_1, MUX_ddc_apbReqF$enq_1__VAL_2;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2,
MUX_wci_respF_q_1$write_1__VAL_2,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2,
MUX_wci_respF_x_wire$wset_1__VAL_3;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_ddc_apbReqF$enq_1__SEL_1,
MUX_ddc_apbReqF$enq_1__SEL_2,
MUX_splitReadInFlight$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_2,
MUX_wci_illegalEdge$write_1__VAL_2,
MUX_wci_respF_q_0$write_1__SEL_1,
MUX_wci_respF_q_1$write_1__SEL_1,
MUX_wci_respF_x_wire$wset_1__SEL_1,
MUX_wsiM_reqFifo_q_0$write_1__SEL_1,
MUX_wsiM_reqFifo_q_1$write_1__SEL_1,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4;
// remaining internal signals
reg [63 : 0] v__h12747, v__h2629, v__h2776, v__h3675;
reg [31 : 0] IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136;
wire [31 : 0] ddcStatus__h12624,
rdat___1__h13067,
rdat___1__h13146,
rdat___1__h13160,
rdat___1__h13168,
rdat___1__h13174,
rdat___1__h13188,
rdat___1__h13196,
rdat___1__h13202,
rdat___1__h13209,
rdat___1__h13215,
rdat___1__h13222,
rdat___1__h13229,
x_data__h11943,
x_data__h13030;
wire [15 : 0] x__h13071;
wire [7 : 0] x__h13044;
wire wci_reqF_i_notEmpty__7_AND_IF_wci_reqF_first___ETC___d65,
wsiS_reqFifo_notFull__67_AND_wsiS_burstKind_47_ETC___d387;
// action method wciS0_mCmd
assign CAN_FIRE_wciS0_mCmd = 1'd1 ;
assign WILL_FIRE_wciS0_mCmd = 1'd1 ;
// action method wciS0_mAddrSpace
assign CAN_FIRE_wciS0_mAddrSpace = 1'd1 ;
assign WILL_FIRE_wciS0_mAddrSpace = 1'd1 ;
// action method wciS0_mByteEn
assign CAN_FIRE_wciS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wciS0_mByteEn = 1'd1 ;
// action method wciS0_mAddr
assign CAN_FIRE_wciS0_mAddr = 1'd1 ;
assign WILL_FIRE_wciS0_mAddr = 1'd1 ;
// action method wciS0_mData
assign CAN_FIRE_wciS0_mData = 1'd1 ;
assign WILL_FIRE_wciS0_mData = 1'd1 ;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy = wci_reqF_countReg > 2'd1 || wci_isReset$VAL ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// action method wciS0_mFlag
assign CAN_FIRE_wciS0_mFlag = 1'd1 ;
assign WILL_FIRE_wciS0_mFlag = 1'd1 ;
// action method wsiS0_mCmd
assign CAN_FIRE_wsiS0_mCmd = 1'd1 ;
assign WILL_FIRE_wsiS0_mCmd = 1'd1 ;
// action method wsiS0_mReqLast
assign CAN_FIRE_wsiS0_mReqLast = 1'd1 ;
assign WILL_FIRE_wsiS0_mReqLast = wsiS0_MReqLast ;
// action method wsiS0_mBurstPrecise
assign CAN_FIRE_wsiS0_mBurstPrecise = 1'd1 ;
assign WILL_FIRE_wsiS0_mBurstPrecise = wsiS0_MBurstPrecise ;
// action method wsiS0_mBurstLength
assign CAN_FIRE_wsiS0_mBurstLength = 1'd1 ;
assign WILL_FIRE_wsiS0_mBurstLength = 1'd1 ;
// action method wsiS0_mData
assign CAN_FIRE_wsiS0_mData = 1'd1 ;
assign WILL_FIRE_wsiS0_mData = 1'd1 ;
// action method wsiS0_mByteEn
assign CAN_FIRE_wsiS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wsiS0_mByteEn = 1'd1 ;
// action method wsiS0_mReqInfo
assign CAN_FIRE_wsiS0_mReqInfo = 1'd1 ;
assign WILL_FIRE_wsiS0_mReqInfo = 1'd1 ;
// action method wsiS0_mDataInfo
assign CAN_FIRE_wsiS0_mDataInfo = 1'd1 ;
assign WILL_FIRE_wsiS0_mDataInfo = 1'd1 ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset$VAL && wsiS_operateD ;
// action method wsiS0_mReset_n
assign CAN_FIRE_wsiS0_mReset_n = 1'd1 ;
assign WILL_FIRE_wsiS0_mReset_n = wsiS0_MReset_n ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// action method wsiM0_sThreadBusy
assign CAN_FIRE_wsiM0_sThreadBusy = 1'd1 ;
assign WILL_FIRE_wsiM0_sThreadBusy = wsiM0_SThreadBusy ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset$VAL && wsiM_operateD ;
// action method wsiM0_sReset_n
assign CAN_FIRE_wsiM0_sReset_n = 1'd1 ;
assign WILL_FIRE_wsiM0_sReset_n = wsiM0_SReset_n ;
// submodule ddc_apbReqF
FIFO2 #(.width(32'd46), .guarded(32'd1)) ddc_apbReqF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(ddc_apbReqF$D_IN),
.ENQ(ddc_apbReqF$ENQ),
.DEQ(ddc_apbReqF$DEQ),
.CLR(ddc_apbReqF$CLR),
.D_OUT(ddc_apbReqF$D_OUT),
.FULL_N(ddc_apbReqF$FULL_N),
.EMPTY_N(ddc_apbReqF$EMPTY_N));
// submodule ddc_apbRespF
FIFO2 #(.width(32'd33),
.guarded(32'd1)) ddc_apbRespF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(ddc_apbRespF$D_IN),
.ENQ(ddc_apbRespF$ENQ),
.DEQ(ddc_apbRespF$DEQ),
.CLR(ddc_apbRespF$CLR),
.D_OUT(ddc_apbRespF$D_OUT),
.FULL_N(ddc_apbRespF$FULL_N),
.EMPTY_N(ddc_apbRespF$EMPTY_N));
// submodule ddc_ddc
duc_ddc_compiler_v1_0 ddc_ddc(.clk(wciS0_Clk),
.sreg_presetn(wciS0_MReset_n),
.data_resetn(ddc_ddc$data_resetn),
.mdata_ready(ddc_ddc$mdata_ready),
.sdata_r(ddc_ddc$sdata_r),
.sdata_valid(ddc_ddc$sdata_valid),
.sreg_paddr(ddc_ddc$sreg_paddr),
.sreg_penable(ddc_ddc$sreg_penable),
.sreg_psel(ddc_ddc$sreg_psel),
.sreg_pwdata(ddc_ddc$sreg_pwdata),
.sreg_pwrite(ddc_ddc$sreg_pwrite),
.mdata_valid(ddc_ddc$mdata_valid),
.mdata_last(),
.sdata_ready(ddc_ddc$sdata_ready),
.mdata_clean(),
.mdata_i(ddc_ddc$mdata_i),
.mdata_q(ddc_ddc$mdata_q),
.sreg_pready(ddc_ddc$sreg_pready),
.sreg_prdata(ddc_ddc$sreg_prdata),
.sreg_pslverr(ddc_ddc$sreg_pslverr),
.int_missinput(ddc_ddc$int_missinput),
.int_errpacket(ddc_ddc$int_errpacket),
.int_lostoutput(ddc_ddc$int_lostoutput),
.int_ducddc(ddc_ddc$int_ducddc));
// submodule ddc_xkF
FIFO2 #(.width(32'd32), .guarded(32'd1)) ddc_xkF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(ddc_xkF$D_IN),
.ENQ(ddc_xkF$ENQ),
.DEQ(ddc_xkF$DEQ),
.CLR(ddc_xkF$CLR),
.D_OUT(ddc_xkF$D_OUT),
.FULL_N(ddc_xkF$FULL_N),
.EMPTY_N(ddc_xkF$EMPTY_N));
// submodule ddc_xnF
FIFO2 #(.width(32'd16), .guarded(32'd1)) ddc_xnF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(ddc_xnF$D_IN),
.ENQ(ddc_xnF$ENQ),
.DEQ(ddc_xnF$DEQ),
.CLR(ddc_xnF$CLR),
.D_OUT(ddc_xnF$D_OUT),
.FULL_N(ddc_xnF$FULL_N),
.EMPTY_N(ddc_xnF$EMPTY_N));
// submodule wci_isReset
ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset$VAL));
// submodule wci_reqF
SizedFIFO #(.p1width(32'd60),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wsiM_isReset
ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset$VAL));
// submodule wsiS_isReset
ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset$VAL));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// submodule xnF
FIFO2 #(.width(32'd32), .guarded(32'd1)) xnF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(xnF$D_IN),
.ENQ(xnF$ENQ),
.DEQ(xnF$DEQ),
.CLR(xnF$CLR),
.D_OUT(xnF$D_OUT),
.FULL_N(xnF$FULL_N),
.EMPTY_N(xnF$EMPTY_N));
// rule RL_wsiS_backpressure
assign CAN_FIRE_RL_wsiS_backpressure =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign WILL_FIRE_RL_wsiS_backpressure = CAN_FIRE_RL_wsiS_backpressure ;
// rule RL_wci_request_decode
assign CAN_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
assign WILL_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
// rule RL_wci_ctl_op_start
assign CAN_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas ;
assign WILL_FIRE_RL_wci_ctl_op_start =
CAN_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_advance_wci_response
assign CAN_FIRE_RL_advance_wci_response =
wci_respF_c_r != 2'd2 && ddc_apbRespF$EMPTY_N &&
!wci_wci_cfwr_pw$whas ;
assign WILL_FIRE_RL_advance_wci_response =
CAN_FIRE_RL_advance_wci_response && !WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign CAN_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ;
// rule RL_wci_ctrl_IsO
assign CAN_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ;
// rule RL_wci_ctrl_OrE
assign CAN_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ;
// rule RL_wsi_Es_doAlways
assign CAN_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
// rule RL_wci_Es_doAlways_Req
assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
// rule RL_ddcEnable_doIngress
assign CAN_FIRE_RL_ddcEnable_doIngress =
ddc_xnF$FULL_N && xnF$EMPTY_N && wci_cState == 3'd2 &&
ddcCtrl[1:0] == 2'd1 &&
!wsiM_statusR[6] ;
assign WILL_FIRE_RL_ddcEnable_doIngress = CAN_FIRE_RL_ddcEnable_doIngress ;
// rule RL_operating_actions
assign CAN_FIRE_RL_operating_actions = wci_cState == 3'd2 ;
assign WILL_FIRE_RL_operating_actions = CAN_FIRE_RL_operating_actions ;
// rule RL_ddc_sreg_request
assign CAN_FIRE_RL_ddc_sreg_request =
ddc_apbReqF$EMPTY_N &&
(!ddc_reqSetup || !ddc_ddc$sreg_pready ||
ddc_apbReqF$D_OUT[45] ||
ddc_apbRespF$FULL_N) ;
assign WILL_FIRE_RL_ddc_sreg_request = CAN_FIRE_RL_ddc_sreg_request ;
// rule RL_ddc_run
assign CAN_FIRE_RL_ddc_run = ddc_started ;
assign WILL_FIRE_RL_ddc_run = ddc_started ;
// rule RL_ddc_start
assign CAN_FIRE_RL_ddc_start = !ddc_started ;
assign WILL_FIRE_RL_ddc_start = CAN_FIRE_RL_ddc_start ;
// rule RL_ddc_ddc_stream_egress
assign CAN_FIRE_RL_ddc_ddc_stream_egress =
ddc_xkF$FULL_N && ddc_ddc$mdata_valid ;
assign WILL_FIRE_RL_ddc_ddc_stream_egress =
CAN_FIRE_RL_ddc_ddc_stream_egress ;
// rule RL_ddc_ddc_stream_ingress
assign CAN_FIRE_RL_ddc_ddc_stream_ingress =
ddc_xnF$EMPTY_N && ddc_ddc$sdata_ready ;
assign WILL_FIRE_RL_ddc_ddc_stream_ingress =
CAN_FIRE_RL_ddc_ddc_stream_ingress ;
// rule RL_ddc_drive_ddc_always_enabled
assign CAN_FIRE_RL_ddc_drive_ddc_always_enabled = 1'd1 ;
assign WILL_FIRE_RL_ddc_drive_ddc_always_enabled = 1'd1 ;
// rule RL_wsiM_update_statusR
assign CAN_FIRE_RL_wsiM_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiM_update_statusR = 1'd1 ;
// rule RL_wsiM_ext_status_assign
assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
// rule RL_wsiM_inc_tBusyCount
assign CAN_FIRE_RL_wsiM_inc_tBusyCount =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// rule RL_wsiM_reqFifo_deq
assign CAN_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_sThreadBusy_reg
assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
// rule RL_wsiM_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiM_operateD__dreg_update
assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
// rule RL_wsiS_update_statusR
assign CAN_FIRE_RL_wsiS_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiS_update_statusR = 1'd1 ;
// rule RL_wsiS_ext_status_assign
assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_reqF_i_notEmpty__7_AND_IF_wci_reqF_first___ETC___d65 &&
wci_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_ddcEnable_doEgress
assign CAN_FIRE_RL_ddcEnable_doEgress =
wsiM_reqFifo_c_r != 2'd2 && ddc_xkF$EMPTY_N &&
wci_cState == 3'd2 &&
ddcCtrl[1:0] == 2'd1 ;
assign WILL_FIRE_RL_ddcEnable_doEgress = CAN_FIRE_RL_ddcEnable_doEgress ;
// rule RL_wsiS_inc_tBusyCount
assign CAN_FIRE_RL_wsiS_inc_tBusyCount =
wsiS_operateD && wsiS_peerIsReady &&
(!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget) ;
assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// rule RL_wsiS_reqFifo_enq
assign CAN_FIRE_RL_wsiS_reqFifo_enq =
wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[60:58] == 3'd1 ;
assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ;
// rule RL_ddcEnable_output_feedDDC
assign CAN_FIRE_RL_ddcEnable_output_feedDDC =
wsiS_reqFifo$EMPTY_N && xnF$FULL_N && wci_cState == 3'd2 &&
ddcCtrl[1:0] == 2'd1 ;
assign WILL_FIRE_RL_ddcEnable_output_feedDDC =
CAN_FIRE_RL_ddcEnable_output_feedDDC ;
// rule RL_ddcPass_bypass
assign CAN_FIRE_RL_ddcPass_bypass =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_cState == 3'd2 &&
ddcCtrl[1:0] == 2'd0 ;
assign WILL_FIRE_RL_ddcPass_bypass = CAN_FIRE_RL_ddcPass_bypass ;
// rule RL_wci_ctl_op_complete
assign CAN_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_cfwr
assign CAN_FIRE_RL_wci_cfwr =
wci_reqF$EMPTY_N && wci_respF_c_r != 2'd2 &&
(!wci_reqF$D_OUT[44] || ddc_apbReqF$FULL_N) &&
wci_wci_cfwr_pw$whas ;
assign WILL_FIRE_RL_wci_cfwr =
CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wsiM_reqFifo_both
assign CAN_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_x_wire$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_x_wire$whas) &&
CAN_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ;
// rule RL_wsiM_reqFifo_decCtr
assign CAN_FIRE_RL_wsiM_reqFifo_decCtr =
CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ;
// rule RL_wsiM_reqFifo_incCtr
assign CAN_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_x_wire$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_x_wire$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ;
// rule RL_wsiS_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiS_operateD__dreg_update
assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
// rule RL_wsiS_reqFifo_reset
assign CAN_FIRE_RL_wsiS_reqFifo_reset =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ||
wsiS_reqFifo_r_deq$whas ;
assign WILL_FIRE_RL_wsiS_reqFifo_reset = CAN_FIRE_RL_wsiS_reqFifo_reset ;
// rule RL_wsiS_reqFifo__updateLevelCounter
assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 !=
wsiS_reqFifo_r_deq$whas ;
assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// rule RL_wci_respF_deq
assign CAN_FIRE_RL_wci_respF_deq = 1'd1 ;
assign WILL_FIRE_RL_wci_respF_deq = 1'd1 ;
// rule RL_wci_reqF_enq
assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq$wget[59:57] != 3'd0 ;
assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ;
// rule RL_wci_sThreadBusy_reg
assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
// rule RL_wci_ctlAckReg__dreg_update
assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
// rule RL_wci_sFlagReg__dreg_update
assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
// rule RL_wci_respF_both
assign CAN_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd2 || wci_respF_x_wire$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ;
// rule RL_wci_respF_decCtr
assign CAN_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ;
// rule RL_wci_respF_incCtr
assign CAN_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd1 || wci_respF_x_wire$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ;
// rule RL_wci_reqF__updateLevelCounter
assign CAN_FIRE_RL_wci_reqF__updateLevelCounter =
(wci_wciReq$wget[59:57] != 3'd0) != wci_reqF_r_deq$whas ;
assign WILL_FIRE_RL_wci_reqF__updateLevelCounter =
CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_ddc_apbReqF$enq_1__VAL_1 = { 2'd2, wci_reqF$D_OUT[43:0] } ;
assign MUX_ddc_apbReqF$enq_1__VAL_2 = { 2'd0, wci_reqF$D_OUT[43:0] } ;
assign MUX_wci_illegalEdge$write_1__VAL_2 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_3 =
ddc_apbRespF$D_OUT[32] ?
34'h3C0DE4202 :
{ 2'd1,
splitWriteInFlight ?
32'hC0DE4201 :
ddc_apbRespF$D_OUT[31:0] } ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 =
{ 3'd1,
unloadCnt == 16'd2047,
13'd6144,
x_data__h11943,
12'd3840 } ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
WILL_FIRE_RL_ddcEnable_doEgress ?
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 :
wsiS_reqFifo$D_OUT ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
61'h00000AAAAAAAAA00 ;
assign MUX_ddc_apbReqF$enq_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[44] ;
assign MUX_ddc_apbReqF$enq_1__SEL_2 =
WILL_FIRE_RL_wci_cfrd && wci_reqF$D_OUT[44] ;
assign MUX_splitReadInFlight$write_1__SEL_1 =
WILL_FIRE_RL_advance_wci_response && splitReadInFlight ;
assign MUX_wci_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_wci_cfrd && !wci_reqF$D_OUT[44] ;
assign MUX_wci_respF_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 = { 2'd1, x_data__h13030 } ;
always@(MUX_wci_respF_x_wire$wset_1__SEL_1 or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_2 or
WILL_FIRE_RL_advance_wci_response or
MUX_wci_respF_x_wire$wset_1__VAL_3 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_x_wire$wset_1__SEL_1:
MUX_wci_respF_q_0$write_1__VAL_1 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_1 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_advance_wci_response:
MUX_wci_respF_q_0$write_1__VAL_1 =
MUX_wci_respF_x_wire$wset_1__VAL_3;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_1 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_1 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_0$write_1__VAL_2 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_1 :
wci_respF_q_1 ;
assign MUX_wci_respF_q_1$write_1__VAL_2 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_1 :
34'h0AAAAAAAA ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd1 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd && !wci_reqF$D_OUT[44] ||
WILL_FIRE_RL_advance_wci_response ||
WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_respF_x_wire$whas =
WILL_FIRE_RL_wci_cfrd && !wci_reqF$D_OUT[44] ||
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_advance_wci_response ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wsiS_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_reqFifo_r_enq$whas =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
assign wsiS_reqFifo_r_deq$whas =
WILL_FIRE_RL_ddcPass_bypass ||
WILL_FIRE_RL_ddcEnable_output_feedDDC ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq$whas =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw$whas = CAN_FIRE_RL_wsiS_backpressure ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_reqFifo_enqueueing$whas =
WILL_FIRE_RL_ddcPass_bypass || WILL_FIRE_RL_ddcEnable_doEgress ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ;
assign wsiM_reqFifo_x_wire$whas =
WILL_FIRE_RL_ddcEnable_doEgress || WILL_FIRE_RL_ddcPass_bypass ;
assign wsiM_reqFifo_dequeueing$whas = CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsiM_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_1 ;
assign ddc_sDataValid_w$wget = 1'd1 ;
assign ddc_sDataValid_w$whas = CAN_FIRE_RL_ddc_ddc_stream_ingress ;
assign ddc_sDataR_w$wget = ddc_xnF$D_OUT ;
assign ddc_sDataR_w$whas = CAN_FIRE_RL_ddc_ddc_stream_ingress ;
assign ddc_mDataReady_w$wget = 1'd1 ;
assign ddc_mDataReady_w$whas = CAN_FIRE_RL_ddc_ddc_stream_egress ;
assign ddc_dataResetn_w$wget = 1'd1 ;
assign ddc_dataResetn_w$whas = ddc_started ;
assign ddc_sRegPaddr_w$wget = ddc_apbReqF$D_OUT[43:32] ;
assign ddc_sRegPaddr_w$whas = CAN_FIRE_RL_ddc_sreg_request ;
assign ddc_sRegPsel_w$wget = 1'd1 ;
assign ddc_sRegPsel_w$whas = CAN_FIRE_RL_ddc_sreg_request ;
assign ddc_sRegPenable_w$wget = ddc_reqSetup ;
assign ddc_sRegPenable_w$whas = CAN_FIRE_RL_ddc_sreg_request ;
assign ddc_sRegPwrite_w$wget = ddc_apbReqF$D_OUT[45] ;
assign ddc_sRegPwrite_w$whas = CAN_FIRE_RL_ddc_sreg_request ;
assign ddc_sRegPwdata_w$wget = ddc_apbReqF$D_OUT[31:0] ;
assign ddc_sRegPwdata_w$whas = CAN_FIRE_RL_ddc_sreg_request ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS0_MData ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
// register ambaErrCnt
assign ambaErrCnt$D_IN = ambaErrCnt + 32'd1 ;
assign ambaErrCnt$EN =
WILL_FIRE_RL_advance_wci_response && ddc_apbRespF$D_OUT[32] ;
// register ambaRdReqCnt
assign ambaRdReqCnt$D_IN = ambaRdReqCnt + 32'd1 ;
assign ambaRdReqCnt$EN = MUX_ddc_apbReqF$enq_1__SEL_2 ;
// register ambaRespCnt
assign ambaRespCnt$D_IN = ambaRespCnt + 32'd1 ;
assign ambaRespCnt$EN =
WILL_FIRE_RL_advance_wci_response && !ddc_apbRespF$D_OUT[32] ;
// register ambaWrReqCnt
assign ambaWrReqCnt$D_IN = ambaWrReqCnt + 32'd1 ;
assign ambaWrReqCnt$EN = MUX_ddc_apbReqF$enq_1__SEL_1 ;
// register ddcCtrl
assign ddcCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign ddcCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[51:32] == 20'h00004 ;
// register ddc_reqSetup
assign ddc_reqSetup$D_IN = !ddc_reqSetup ;
assign ddc_reqSetup$EN =
WILL_FIRE_RL_ddc_sreg_request &&
(ddc_ddc$sreg_pready || !ddc_reqSetup) ;
// register ddc_started
assign ddc_started$D_IN = 1'd1 ;
assign ddc_started$EN = CAN_FIRE_RL_ddc_start ;
// register outMesgCnt
assign outMesgCnt$D_IN = outMesgCnt + 32'd1 ;
assign outMesgCnt$EN =
WILL_FIRE_RL_ddcEnable_doEgress && unloadCnt == 16'd2047 ;
// register splitReadInFlight
assign splitReadInFlight$D_IN = !MUX_splitReadInFlight$write_1__SEL_1 ;
assign splitReadInFlight$EN =
WILL_FIRE_RL_advance_wci_response && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && wci_reqF$D_OUT[44] ;
// register splitWriteInFlight
assign splitWriteInFlight$D_IN = 1'd0 ;
assign splitWriteInFlight$EN =
WILL_FIRE_RL_advance_wci_response && splitWriteInFlight ;
// register takeEven
assign takeEven$D_IN = !takeEven ;
assign takeEven$EN = CAN_FIRE_RL_ddcEnable_doIngress ;
// register unloadCnt
assign unloadCnt$D_IN =
(unloadCnt == 16'd2047) ? 16'd0 : unloadCnt + 16'd1 ;
assign unloadCnt$EN = CAN_FIRE_RL_ddcEnable_doEgress ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
!MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_2 ;
assign wci_illegalEdge$EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge$write_1__SEL_2 ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[59:57] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_decCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ;
// register wci_respF_q_0
always@(MUX_wci_respF_q_0$write_1__SEL_1 or
MUX_wci_respF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_q_0$write_1__SEL_1:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_1
always@(MUX_wci_respF_q_1$write_1__SEL_1 or
MUX_wci_respF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_q_1$write_1__SEL_1:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[57]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0$write_1__SEL_1:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1$write_1__SEL_1:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset$VAL,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
wsiS_reqFifo_notFull__67_AND_wsiS_burstKind_47_ETC___d387 ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'd1 ;
assign wsiS_errorSticky$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo$FULL_N ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_wsiReq$wget[57] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N ||
WILL_FIRE_RL_ddcPass_bypass ||
WILL_FIRE_RL_ddcEnable_output_feedDDC ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR$D_IN =
{ wsiS_isReset$VAL,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR$EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
// register wsiS_wordCount
assign wsiS_wordCount$D_IN =
wsiS_wsiReq$wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
// submodule ddc_apbReqF
assign ddc_apbReqF$D_IN =
MUX_ddc_apbReqF$enq_1__SEL_1 ?
MUX_ddc_apbReqF$enq_1__VAL_1 :
MUX_ddc_apbReqF$enq_1__VAL_2 ;
assign ddc_apbReqF$DEQ =
WILL_FIRE_RL_ddc_sreg_request && ddc_reqSetup &&
ddc_ddc$sreg_pready ;
assign ddc_apbReqF$ENQ =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[44] ||
WILL_FIRE_RL_wci_cfrd && wci_reqF$D_OUT[44] ;
assign ddc_apbReqF$CLR = 1'b0 ;
// submodule ddc_apbRespF
assign ddc_apbRespF$D_IN = { ddc_ddc$sreg_pslverr, ddc_ddc$sreg_prdata } ;
assign ddc_apbRespF$DEQ = WILL_FIRE_RL_advance_wci_response ;
assign ddc_apbRespF$ENQ =
WILL_FIRE_RL_ddc_sreg_request && ddc_reqSetup &&
ddc_ddc$sreg_pready &&
!ddc_apbReqF$D_OUT[45] ;
assign ddc_apbRespF$CLR = 1'b0 ;
// submodule ddc_ddc
assign ddc_ddc$data_resetn = ddc_started ;
assign ddc_ddc$mdata_ready = CAN_FIRE_RL_ddc_ddc_stream_egress ;
assign ddc_ddc$sdata_r =
CAN_FIRE_RL_ddc_ddc_stream_ingress ? ddc_xnF$D_OUT : 16'd0 ;
assign ddc_ddc$sdata_valid = CAN_FIRE_RL_ddc_ddc_stream_ingress ;
assign ddc_ddc$sreg_paddr =
CAN_FIRE_RL_ddc_sreg_request ? ddc_apbReqF$D_OUT[43:32] : 12'd0 ;
assign ddc_ddc$sreg_penable = CAN_FIRE_RL_ddc_sreg_request && ddc_reqSetup ;
assign ddc_ddc$sreg_psel = CAN_FIRE_RL_ddc_sreg_request ;
assign ddc_ddc$sreg_pwdata =
CAN_FIRE_RL_ddc_sreg_request ? ddc_apbReqF$D_OUT[31:0] : 32'd0 ;
assign ddc_ddc$sreg_pwrite =
CAN_FIRE_RL_ddc_sreg_request && ddc_apbReqF$D_OUT[45] ;
// submodule ddc_xkF
assign ddc_xkF$D_IN = { ddc_ddc$mdata_i, ddc_ddc$mdata_q } ;
assign ddc_xkF$DEQ = CAN_FIRE_RL_ddcEnable_doEgress ;
assign ddc_xkF$ENQ = CAN_FIRE_RL_ddc_ddc_stream_egress ;
assign ddc_xkF$CLR = 1'b0 ;
// submodule ddc_xnF
assign ddc_xnF$D_IN = takeEven ? xnF$D_OUT[15:0] : xnF$D_OUT[31:16] ;
assign ddc_xnF$DEQ = CAN_FIRE_RL_ddc_ddc_stream_ingress ;
assign ddc_xnF$ENQ = CAN_FIRE_RL_ddcEnable_doIngress ;
assign ddc_xnF$CLR = 1'b0 ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$ENQ = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$DEQ = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo$ENQ = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
assign wsiS_reqFifo$CLR = 1'b0 ;
// submodule xnF
assign xnF$D_IN = wsiS_reqFifo$D_OUT[43:12] ;
assign xnF$DEQ = WILL_FIRE_RL_ddcEnable_doIngress && !takeEven ;
assign xnF$ENQ = CAN_FIRE_RL_ddcEnable_output_feedDDC ;
assign xnF$CLR = 1'b0 ;
// remaining internal signals
assign ddcStatus__h12624 = { 24'd0, x__h13044 } ;
assign rdat___1__h13067 = hasDebugLogic ? { 16'd0, x__h13071 } : 32'd0 ;
assign rdat___1__h13146 =
hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ;
assign rdat___1__h13160 =
hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ;
assign rdat___1__h13168 =
hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ;
assign rdat___1__h13174 =
hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
assign rdat___1__h13188 =
hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
assign rdat___1__h13196 =
hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
assign rdat___1__h13202 = hasDebugLogic ? ambaWrReqCnt : 32'd0 ;
assign rdat___1__h13209 = hasDebugLogic ? ambaRdReqCnt : 32'd0 ;
assign rdat___1__h13215 = hasDebugLogic ? ambaRespCnt : 32'd0 ;
assign rdat___1__h13222 = hasDebugLogic ? ambaErrCnt : 32'd0 ;
assign rdat___1__h13229 = hasDebugLogic ? outMesgCnt : 32'd0 ;
assign wci_reqF_i_notEmpty__7_AND_IF_wci_reqF_first___ETC___d65 =
wci_reqF$EMPTY_N &&
(wci_reqF$D_OUT[44] ?
ddc_apbReqF$FULL_N :
wci_respF_c_r != 2'd2) ;
assign wsiS_reqFifo_notFull__67_AND_wsiS_burstKind_47_ETC___d387 =
wsiS_reqFifo$FULL_N &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[57]) ;
assign x__h13044 =
{ ddc_ddc$int_missinput,
ddc_ddc$int_errpacket,
ddc_ddc$int_lostoutput,
ddc_ddc$int_ducddc,
3'b0,
hasDebugLogic } ;
assign x__h13071 = { wsiS_statusR, wsiM_statusR } ;
assign x_data__h11943 = { ddc_xkF$D_OUT[15:0], ddc_xkF$D_OUT[31:16] } ;
assign x_data__h13030 =
wci_reqF$D_OUT[44] ?
32'd0 :
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 ;
always@(wci_reqF$D_OUT or
ddcStatus__h12624 or
ddcCtrl or
rdat___1__h13067 or
rdat___1__h13146 or
rdat___1__h13160 or
rdat___1__h13168 or
rdat___1__h13174 or
rdat___1__h13188 or
rdat___1__h13196 or
rdat___1__h13202 or
rdat___1__h13209 or
rdat___1__h13215 or rdat___1__h13222 or rdat___1__h13229)
begin
case (wci_reqF$D_OUT[51:32])
20'h0:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
ddcStatus__h12624;
20'h00004:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 = ddcCtrl;
20'h00010:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13067;
20'h00014:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13146;
20'h00018:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13160;
20'h0001C:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13168;
20'h00020:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13174;
20'h00024:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13188;
20'h00028:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13196;
20'h0002C:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13202;
20'h00030:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13209;
20'h00034:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13215;
20'h00038:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13222;
20'h0003C:
IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
rdat___1__h13229;
default: IF_wci_reqF_first__8_BITS_51_TO_32_3_EQ_0x0_4__ETC___d136 =
32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (!wciS0_MReset_n)
begin
ambaErrCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ambaRdReqCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ambaRespCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ambaWrReqCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
ddcCtrl <= `BSV_ASSIGNMENT_DELAY ddcCtrlInit;
ddc_reqSetup <= `BSV_ASSIGNMENT_DELAY 1'd0;
ddc_started <= `BSV_ASSIGNMENT_DELAY 1'd0;
outMesgCnt <= `BSV_ASSIGNMENT_DELAY 32'd0;
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
splitWriteInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
takeEven <= `BSV_ASSIGNMENT_DELAY 1'd1;
unloadCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'd7;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (ambaErrCnt$EN)
ambaErrCnt <= `BSV_ASSIGNMENT_DELAY ambaErrCnt$D_IN;
if (ambaRdReqCnt$EN)
ambaRdReqCnt <= `BSV_ASSIGNMENT_DELAY ambaRdReqCnt$D_IN;
if (ambaRespCnt$EN)
ambaRespCnt <= `BSV_ASSIGNMENT_DELAY ambaRespCnt$D_IN;
if (ambaWrReqCnt$EN)
ambaWrReqCnt <= `BSV_ASSIGNMENT_DELAY ambaWrReqCnt$D_IN;
if (ddcCtrl$EN) ddcCtrl <= `BSV_ASSIGNMENT_DELAY ddcCtrl$D_IN;
if (ddc_reqSetup$EN)
ddc_reqSetup <= `BSV_ASSIGNMENT_DELAY ddc_reqSetup$D_IN;
if (ddc_started$EN)
ddc_started <= `BSV_ASSIGNMENT_DELAY ddc_started$D_IN;
if (outMesgCnt$EN)
outMesgCnt <= `BSV_ASSIGNMENT_DELAY outMesgCnt$D_IN;
if (splitReadInFlight$EN)
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight$D_IN;
if (splitWriteInFlight$EN)
splitWriteInFlight <= `BSV_ASSIGNMENT_DELAY splitWriteInFlight$D_IN;
if (takeEven$EN) takeEven <= `BSV_ASSIGNMENT_DELAY takeEven$D_IN;
if (unloadCnt$EN) unloadCnt <= `BSV_ASSIGNMENT_DELAY unloadCnt$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_reqFifo_levelsValid$EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiS_wordCount$EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN;
end
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_mesgWordLength$EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
ambaErrCnt = 32'hAAAAAAAA;
ambaRdReqCnt = 32'hAAAAAAAA;
ambaRespCnt = 32'hAAAAAAAA;
ambaWrReqCnt = 32'hAAAAAAAA;
ddcCtrl = 32'hAAAAAAAA;
ddc_reqSetup = 1'h0;
ddc_started = 1'h0;
outMesgCnt = 32'hAAAAAAAA;
splitReadInFlight = 1'h0;
splitWriteInFlight = 1'h0;
takeEven = 1'h0;
unloadCnt = 16'hAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3675 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3675,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h12747 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting DDC ddcCtrl:%0x", v__h12747, ddcCtrl);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/DDCWorker.bsv\", line 156, column 8: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/DDCWorker.bsv\", line 162, column 8: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_IsO fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/DDCWorker.bsv\", line 162, column 8: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/DDCWorker.bsv\", line 126, column 8: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/DDCWorker.bsv\", line 126, column 8: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/DDCWorker.bsv\", line 126, column 8: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h2776 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h2776,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h2629 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h2629,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/DDCWorker.bsv\", line 108, column 8: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/DDCWorker.bsv\", line 108, column 8: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/DDCWorker.bsv\", line 108, column 8: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/DDCWorker.bsv\", line 108, column 8: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_cfrd fired in the same clock\n cycle.\n");
end
// synopsys translate_on
endmodule // mkDDCWorker
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_4_V
`define SKY130_FD_SC_LS__FILL_4_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_4 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_4 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_4_V
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Generate ack signal from early ack signal and mask strobe.
* After an early acked write, it should pulse after 2 cycles.
* After an early acked read, it should pulse after CL+3 cycles, that is
* 5 cycles when tim_cas = 0 (assumed here)
* 6 cycles when tim_cas = 1
*/
module fmlarb_dack(
input sys_clk,
input sys_rst,
input stb,
input eack,
input we,
output stbm,
output reg ack
);
wire read = eack & ~we;
wire write = eack & we;
reg ack_read2;
reg ack_read1;
reg ack_read0;
always @(posedge sys_clk) begin
if(sys_rst) begin
ack_read2 <= 1'b0;
ack_read1 <= 1'b0;
ack_read0 <= 1'b0;
end else begin
ack_read2 <= read;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end
end
reg ack0;
always @(posedge sys_clk) begin
if(sys_rst) begin
ack0 <= 1'b0;
ack <= 1'b0;
end else begin
// ack0 <= ack_read0;
ack <= ack_read0|write;
end
end
reg mask;
assign stbm = stb & ~mask;
always @(posedge sys_clk) begin
if(sys_rst)
mask <= 1'b0;
else begin
if(eack)
mask <= 1'b1;
if(ack)
mask <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A211O_PP_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_TB_V
`define SKY130_FD_SC_HS__AND2_TB_V
/**
* and2: 2-input AND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__and2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_dmac_resize_dest #(
parameter DATA_WIDTH_DEST = 64,
parameter DATA_WIDTH_MEM = 64
) (
input clk,
input reset,
input mem_data_valid,
output mem_data_ready,
input [DATA_WIDTH_MEM-1:0] mem_data,
input mem_data_last,
output dest_data_valid,
input dest_data_ready,
output [DATA_WIDTH_DEST-1:0] dest_data,
output dest_data_last
);
/*
* Resize the data width between the burst memory and the destination interface
* if necessary.
*/
generate if (DATA_WIDTH_DEST == DATA_WIDTH_MEM) begin
assign dest_data_valid = mem_data_valid;
assign dest_data = mem_data;
assign dest_data_last = mem_data_last;
assign mem_data_ready = dest_data_ready;
end else begin
localparam RATIO = DATA_WIDTH_MEM / DATA_WIDTH_DEST;
reg [$clog2(RATIO)-1:0] count = 'h0;
reg valid = 1'b0;
reg [RATIO-1:0] last = 'h0;
reg [DATA_WIDTH_MEM-1:0] data = 'h0;
wire last_beat;
assign last_beat = count == RATIO - 1;
always @(posedge clk) begin
if (reset == 1'b1) begin
valid <= 1'b0;
end else if (mem_data_valid == 1'b1) begin
valid <= 1'b1;
end else if (last_beat == 1'b1 && dest_data_ready == 1'b1) begin
valid <= 1'b0;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
count <= 'h0;
end else if (dest_data_ready == 1'b1 && dest_data_valid == 1'b1) begin
count <= count + 1;
end
end
assign mem_data_ready = ~valid | (dest_data_ready & last_beat);
always @(posedge clk) begin
if (mem_data_ready == 1'b1) begin
data <= mem_data;
last <= {mem_data_last,{RATIO-1{1'b0}}};
end else if (dest_data_ready == 1'b1) begin
data[DATA_WIDTH_MEM-DATA_WIDTH_DEST-1:0] <= data[DATA_WIDTH_MEM-1:DATA_WIDTH_DEST];
last[RATIO-2:0] <= last[RATIO-1:1];
end
end
assign dest_data_valid = valid;
assign dest_data = data[DATA_WIDTH_DEST-1:0];
assign dest_data_last = last[0];
end endgenerate
endmodule
|
module register_file_testbench;
reg[1:0] read_register_port_0;
reg[1:0] read_register_port_1;
reg[1:0] write_register;
reg[31:0] write_data;
reg write_enable;
wire[31:0] read_data_port_0;
wire[31:0] read_data_port_1;
register_file rf(read_register_port_0, read_register_port_1,
write_register, write_data, write_enable,
read_data_port_0, read_data_port_1);
initial
begin
$dumpfile("register-file-test.vcd");
$dumpvars(0, register_file_testbench);
$monitor("read_register_port_0=%d write_register=%d write_data=%d write_enable=%d read_data_port_0=%d",
read_register_port_0, write_register, write_data,
write_enable, read_data_port_0);
#0 write_enable = 'b0;
#0 write_data = 'd21;
#0 write_register = 'b00;
#1 write_enable = 'b1;
#1 write_enable = 'b0;
#0 write_register = 'b01;
#0 write_data = 'd42;
#1 write_enable = 'b1;
#1 write_enable = 'b0;
#0 write_register = 'b10;
#0 write_data = 'd84;
#1 write_enable = 'b1;
#1 write_enable = 'b0;
#0 write_register = 'b11;
#0 write_data = 'd168;
#1 write_enable = 'b1;
#1 write_enable = 'b0;
#1 read_register_port_0 = 'b00;
#1 read_register_port_0 = 'b01;
#1 read_register_port_0 = 'b10;
#1 read_register_port_0 = 'b11;
end
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_load_store_unit.v
// Title : Load and store unit
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Instead of disallowing an instruction cache miss on a data cache
// : miss, both can now occur at the same time. If both occur at same
// : time, then restart address is the address of instruction that
// : caused data cache miss.
// Version : 3.2
// : EBRs use SYNC resets instead of ASYNC resets.
// Version : 3.3
// : Support for new non-cacheable Data Memory that is accessible by
// : the data port and has a one cycle access latency.
// Version : 3.4
// : No change
// Version : 3.5
// : Bug fix: Inline memory is correctly generated if it is not a
// : power-of-two
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_load_store_unit (
// ----- Inputs -------
clk_i,
rst_i,
// From pipeline
stall_a,
stall_x,
stall_m,
kill_m,
exception_m,
store_operand_x,
load_store_address_x,
load_store_address_m,
load_store_address_w,
`ifdef CFG_MMU_ENABLED
load_d,
store_d,
`endif
load_x,
store_x,
load_q_x,
store_q_x,
load_q_m,
store_q_m,
sign_extend_x,
size_x,
`ifdef CFG_DCACHE_ENABLED
dflush,
`endif
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
`ifdef CFG_MMU_ENABLED
dtlb_enable,
tlbpaddr,
tlbvaddr,
dtlb_update,
dtlb_flush,
dtlb_invalidate,
`endif
// From Wishbone
d_dat_i,
d_ack_i,
d_err_i,
d_rty_i,
// ----- Outputs -------
// To pipeline
`ifdef CFG_DCACHE_ENABLED
dcache_refill_request,
dcache_restart_request,
dcache_stall_request,
dcache_refilling,
`endif
`ifdef CFG_IROM_ENABLED
irom_store_data_m,
irom_address_xm,
irom_we_xm,
irom_stall_request_x,
`endif
load_data_w,
stall_wb_load,
`ifdef CFG_MMU_ENABLED
dtlb_stall_request,
dtlb_miss_vfn,
dtlb_miss_x,
dtlb_fault_x,
`endif
// To Wishbone
d_dat_o,
d_adr_o,
d_cyc_o,
d_sel_o,
d_stb_o,
d_we_o,
d_cti_o,
d_lock_o,
d_bte_o
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_a; // A stage stall
input stall_x; // X stage stall
input stall_m; // M stage stall
input kill_m; // Kill instruction in M stage
input exception_m; // An exception occured in the M stage
input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
`ifdef CFG_MMU_ENABLED
input load_d; // Load instruction in D stage
input store_d; // Store instruction in D stage
`endif
input load_x; // Load instruction in X stage
input store_x; // Store instruction in X stage
input load_q_x; // Load instruction in X stage
input store_q_x; // Store instruction in X stage
input load_q_m; // Load instruction in M stage
input store_q_m; // Store instruction in M stage
input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
`ifdef CFG_DCACHE_ENABLED
input dflush; // Flush the data cache
`endif
`ifdef CFG_IROM_ENABLED
input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
`endif
`ifdef CFG_MMU_ENABLED
input dtlb_enable; // Data TLB enable
input [`LM32_WORD_RNG] tlbpaddr; // TLBPADDR CSR
input [`LM32_WORD_RNG] tlbvaddr; // TLBVADDR CSR
input dtlb_update; // Data TLB update
input dtlb_flush; // Data TLB flush
input dtlb_invalidate; // Data TLB invalidate
`endif
input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
input d_ack_i; // Data Wishbone interface acknowledgement
input d_err_i; // Data Wishbone interface error
input d_rty_i; // Data Wishbone interface retry
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_DCACHE_ENABLED
output dcache_refill_request; // Request to refill data cache
wire dcache_refill_request;
output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
wire dcache_restart_request;
output dcache_stall_request; // Data cache stall request
wire dcache_stall_request;
output dcache_refilling;
wire dcache_refilling;
`endif
`ifdef CFG_IROM_ENABLED
output [`LM32_WORD_RNG] irom_store_data_m; // Store data to Instruction ROM
wire [`LM32_WORD_RNG] irom_store_data_m;
output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM
wire [`LM32_WORD_RNG] irom_address_xm;
output irom_we_xm; // Write-enable of 2nd port of Instruction ROM
wire irom_we_xm;
output irom_stall_request_x; // Stall instruction in D stage
wire irom_stall_request_x;
`endif
output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
reg [`LM32_WORD_RNG] load_data_w;
output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
reg stall_wb_load;
`ifdef CFG_MMU_ENABLED
output dtlb_stall_request; // Data TLB stall request
wire dtlb_stall_request;
output [`LM32_WORD_RNG] dtlb_miss_vfn; // Virtual frame number of missed load or store address
wire [`LM32_WORD_RNG] dtlb_miss_vfn;
output dtlb_miss_x; // Indicates if a data TLB miss has occured
wire dtlb_miss_x;
output dtlb_fault_x; // Indicates if a data TLB fault has occured in X stage
wire dtlb_fault_x;
`endif
output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
reg [`LM32_WORD_RNG] d_dat_o;
output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
reg [`LM32_WORD_RNG] d_adr_o;
output d_cyc_o; // Data Wishbone interface cycle
reg d_cyc_o;
output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
output d_stb_o; // Data Wishbone interface strobe
reg d_stb_o;
output d_we_o; // Data Wishbone interface write enable
reg d_we_o;
output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
reg [`LM32_CTYPE_RNG] d_cti_o;
output d_lock_o; // Date Wishbone interface lock bus
reg d_lock_o;
output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] d_bte_o;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
// Microcode pipeline registers - See inputs for description
reg [`LM32_SIZE_RNG] size_m;
reg [`LM32_SIZE_RNG] size_w;
reg sign_extend_m;
reg sign_extend_w;
reg [`LM32_WORD_RNG] store_data_x;
reg [`LM32_WORD_RNG] store_data_m;
reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
wire [`LM32_WORD_RNG] data_m;
reg [`LM32_WORD_RNG] data_w;
`ifdef CFG_DCACHE_ENABLED
wire dcache_select_x; // Select data cache to load from / store to
reg dcache_select_m;
wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
reg dcache_refill_ready; // Indicates the next word of refill data is ready
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
wire last_word; // Indicates if this is the last word in the cache line
wire [`LM32_WORD_RNG] first_address; // First cache refill address
`endif
`ifdef CFG_DRAM_ENABLED
wire dram_select_x; // Select data RAM to load from / store to
reg dram_select_m;
reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory
reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM
wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM
wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory
wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
`endif
wire wb_select_x; // Select Wishbone to load from / store to
`ifdef CFG_IROM_ENABLED
wire irom_select_x; // Select instruction ROM to load from / store to
reg irom_select_m;
`endif
reg wb_select_m;
reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
reg wb_load_complete; // Indicates when a Wishbone load is complete
`ifdef CFG_MMU_ENABLED
wire [`LM32_WORD_RNG] physical_load_store_address_m; // X stage physical load/store address
wire cache_inhibit_x; // Indicates if data cache should be bypassed
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
`ifdef CFG_DRAM_ENABLED
`define LM32_DRAM_WIDTH `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)
`define LM32_DRAM_RNG (`LM32_DRAM_WIDTH-1+2):2
// Data RAM
lm32_ram #(
.data_width (`LM32_WORD_WIDTH),
.address_width (`LM32_DRAM_WIDTH),
.init_file (`CFG_DRAM_INIT_FILE)
) ram (
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.enable_read (!stall_x),
.read_address (load_store_address_x[`LM32_DRAM_RNG]),
.enable_write (!stall_m),
.write_address (load_store_address_m[`LM32_DRAM_RNG]),
.write_data (dram_store_data_m),
.write_enable (store_q_m & dram_select_m),
// ----- Outputs -------
.read_data (dram_data_out)
);
/*----------------------------------------------------------------------
EBRs cannot perform reads from location 'written to' on the same clock
edge. Therefore bypass logic is required to latch the store'd value
and use it for the load (instead of value from memory).
----------------------------------------------------------------------*/
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
if (rst_i == `TRUE)
begin
dram_bypass_en <= `FALSE;
dram_bypass_data <= 0;
end
else
begin
if (stall_x == `FALSE)
dram_bypass_data <= dram_store_data_m;
if ( (stall_m == `FALSE)
&& (stall_x == `FALSE)
&& (store_q_m == `TRUE)
&& ( (load_x == `TRUE)
|| (store_x == `TRUE)
)
&& (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
)
dram_bypass_en <= `TRUE;
else
if ( (dram_bypass_en == `TRUE)
&& (stall_x == `FALSE)
)
dram_bypass_en <= `FALSE;
end
assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
`endif
`ifdef CFG_DCACHE_ENABLED
// Data cache
lm32_dcache #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
.base_address (base_address),
.limit (limit)
) dcache (
// ----- Inputs -----
.clk_i (clk_i),
.rst_i (rst_i),
.stall_a (stall_a),
.stall_x (stall_x),
.stall_m (stall_m),
.address_x (load_store_address_x),
`ifdef CFG_MMU_ENABLED
/* VIPT cache, address_m is (only) used for tag */
.address_m (physical_load_store_address_m),
`else
.address_m (load_store_address_m),
`endif
.load_q_m (load_q_m & dcache_select_m),
.store_q_m (store_q_m & dcache_select_m),
.store_data (store_data_m),
.store_byte_select (byte_enable_m & {4{dcache_select_m}}),
.refill_ready (dcache_refill_ready),
.refill_data (wb_data_m),
.dflush (dflush),
`ifdef CFG_MMU_ENABLED
.dtlb_miss_x (dtlb_miss_x),
`endif
// ----- Outputs -----
.stall_request (dcache_stall_request),
.restart_request (dcache_restart_request),
.refill_request (dcache_refill_request),
.refill_address (dcache_refill_address),
.refilling (dcache_refilling),
.load_data (dcache_data_m)
);
`endif
`ifdef CFG_MMU_ENABLED
// Data TLB
lm32_dtlb dtlb (
// ----- Inputs -----
.clk_i (clk_i),
.rst_i (rst_i),
.enable (dtlb_enable),
.stall_x (stall_x),
.stall_m (stall_m),
.address_x (load_store_address_x),
.address_m (load_store_address_m),
.load_d (load_d),
.store_d (store_d),
.load_q_x (load_q_x),
.store_q_x (store_q_x),
.tlbpaddr (tlbpaddr),
.tlbvaddr (tlbvaddr),
.update (dtlb_update),
.flush (dtlb_flush),
.invalidate (dtlb_invalidate),
// ----- Outputs -----
.physical_load_store_address_m (physical_load_store_address_m),
.stall_request (dtlb_stall_request),
.miss_vfn (dtlb_miss_vfn),
.miss_x (dtlb_miss_x),
.fault_x (dtlb_fault_x),
.cache_inhibit_x (cache_inhibit_x)
);
`endif
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Select where data should be loaded from / stored to
`ifdef CFG_DRAM_ENABLED
assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_DRAM_LIMIT);
`endif
`ifdef CFG_IROM_ENABLED
assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_IROM_LIMIT);
`endif
`ifdef CFG_DCACHE_ENABLED
assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_DCACHE_LIMIT)
`ifdef CFG_DRAM_ENABLED
&& (dram_select_x == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_x == `FALSE)
`endif
`ifdef CFG_MMU_ENABLED
&& (cache_inhibit_x == `FALSE)
`endif
;
`endif
assign wb_select_x = `TRUE
`ifdef CFG_DCACHE_ENABLED
&& !dcache_select_x
`endif
`ifdef CFG_DRAM_ENABLED
&& !dram_select_x
`endif
`ifdef CFG_IROM_ENABLED
&& !irom_select_x
`endif
;
// Make sure data to store is in correct byte lane
always @(*)
begin
case (size_x)
`LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
`LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
`LM32_SIZE_WORD: store_data_x = store_operand_x;
default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
// Generate byte enable accoring to size of load or store and address being accessed
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
{`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
{`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
{`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
{`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
{`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
{`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
{`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
`ifdef CFG_DRAM_ENABLED
// Only replace selected bytes
assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
`endif
`ifdef CFG_IROM_ENABLED
// Only replace selected bytes
assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
`endif
`ifdef CFG_IROM_ENABLED
// Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
// a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
// byte is replaced, and the whole 32-bit value is written back
assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
? load_store_address_m
: load_store_address_x;
// All store instructions perform a write operation in the M stage
assign irom_we_xm = (irom_select_m == `TRUE)
&& (store_q_m == `TRUE);
// A single port in instruction ROM is available to load-store unit for doing loads/stores.
// Since every store requires a load (in X stage) and then a store (in M stage), we cannot
// allow load (or store) instructions sequentially after the store instructions to proceed
// until the store instruction has vacated M stage (i.e., completed the store operation)
assign irom_stall_request_x = (irom_select_x == `TRUE)
&& (store_q_x == `TRUE);
`endif
`ifdef CFG_DCACHE_ENABLED
`ifdef CFG_DRAM_ENABLED
`ifdef CFG_IROM_ENABLED
// WB + DC + DRAM + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: irom_select_m == `TRUE
? irom_data_m
: dcache_data_m;
`else
// WB + DC + DRAM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: dcache_data_m;
`endif
`else
`ifdef CFG_IROM_ENABLED
// WB + DC + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: irom_select_m == `TRUE
? irom_data_m
: dcache_data_m;
`else
// WB + DC
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dcache_data_m;
`endif
`endif
`else
`ifdef CFG_DRAM_ENABLED
`ifdef CFG_IROM_ENABLED
// WB + DRAM + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: irom_data_m;
`else
// WB + DRAM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_data_m;
`endif
`else
`ifdef CFG_IROM_ENABLED
// WB + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: irom_data_m;
`else
// WB
assign data_m = wb_data_m;
`endif
`endif
`endif
// Sub-word selection and sign/zero-extension for loads
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
{`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
{`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
{`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
{`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
{`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
{`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
{`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
// Unused/constant Wishbone signals
assign d_bte_o = `LM32_BTYPE_LINEAR;
`ifdef CFG_DCACHE_ENABLED
// Generate signal to indicate last word in cache line
generate
case (bytes_per_line)
4:
begin
assign first_cycle_type = `LM32_CTYPE_END;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = `TRUE;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
end
8:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
default:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = d_adr_o[addr_offset_msb:addr_offset_lsb+1] == {addr_offset_width-1{1'b1}} ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
endcase
endgenerate
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Data Wishbone interface
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
d_we_o <= `FALSE;
d_cti_o <= `LM32_CTYPE_END;
d_lock_o <= `FALSE;
wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
wb_load_complete <= `FALSE;
stall_wb_load <= `FALSE;
`ifdef CFG_DCACHE_ENABLED
dcache_refill_ready <= `FALSE;
`endif
end
else
begin
`ifdef CFG_DCACHE_ENABLED
// Refill ready should only be asserted for a single cycle
dcache_refill_ready <= `FALSE;
`endif
// Is a Wishbone cycle already in progress?
if (d_cyc_o == `TRUE)
begin
// Is the cycle complete?
if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
begin
`ifdef CFG_DCACHE_ENABLED
if ((dcache_refilling == `TRUE) && (!last_word))
begin
// Fetch next word of cache line
d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
end
else
`endif
begin
// Refill/access complete
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
d_lock_o <= `FALSE;
end
`ifdef CFG_DCACHE_ENABLED
d_cti_o <= next_cycle_type;
// If we are performing a refill, indicate to cache next word of data is ready
dcache_refill_ready <= dcache_refilling;
`endif
// Register data read from Wishbone interface
wb_data_m <= d_dat_i;
// Don't set when stores complete - otherwise we'll deadlock if load in m stage
wb_load_complete <= !d_we_o;
end
// synthesis translate_off
if (d_err_i == `TRUE)
$display ("Data bus error. Address: %x @ %d", d_adr_o, $time);
// synthesis translate_on
end
else
begin
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
begin
// Start cache refill
d_adr_o <= first_address;
d_cyc_o <= `TRUE;
d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
d_stb_o <= `TRUE;
d_we_o <= `FALSE;
d_cti_o <= first_cycle_type;
//d_lock_o <= `TRUE;
end
else
`endif
if ( (store_q_m == `TRUE)
&& (stall_m == `FALSE)
`ifdef CFG_DRAM_ENABLED
&& (dram_select_m == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_m == `FALSE)
`endif
)
begin
// Data cache is write through, so all stores go to memory
d_dat_o <= store_data_m;
d_adr_o <=
`ifdef CFG_MMU_ENABLED
(dtlb_enable) ? physical_load_store_address_m :
`endif
load_store_address_m;
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
d_we_o <= `TRUE;
d_cti_o <= `LM32_CTYPE_END;
end
else if ( (load_q_m == `TRUE)
&& (wb_select_m == `TRUE)
&& (wb_load_complete == `FALSE)
// stall_m will be TRUE, because stall_wb_load will be TRUE
)
begin
// Read requested address
stall_wb_load <= `FALSE;
d_adr_o <=
`ifdef CFG_MMU_ENABLED
(dtlb_enable) ? physical_load_store_address_m :
`endif
load_store_address_m;
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
d_we_o <= `FALSE;
d_cti_o <= `LM32_CTYPE_END;
end
end
// Clear load/store complete flag when instruction leaves M stage
if (stall_m == `FALSE)
wb_load_complete <= `FALSE;
// When a Wishbone load first enters the M stage, we need to stall it
if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
stall_wb_load <= `TRUE;
// Clear stall request if load instruction is killed
if ((kill_m == `TRUE) || (exception_m == `TRUE))
stall_wb_load <= `FALSE;
end
end
// Pipeline registers
// X/M stage pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
sign_extend_m <= `FALSE;
size_m <= 2'b00;
byte_enable_m <= `FALSE;
store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
`ifdef CFG_DCACHE_ENABLED
dcache_select_m <= `FALSE;
`endif
`ifdef CFG_DRAM_ENABLED
dram_select_m <= `FALSE;
`endif
`ifdef CFG_IROM_ENABLED
irom_select_m <= `FALSE;
`endif
wb_select_m <= `FALSE;
end
else
begin
if (stall_m == `FALSE)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
`ifdef CFG_DCACHE_ENABLED
dcache_select_m <= dcache_select_x;
`endif
`ifdef CFG_DRAM_ENABLED
dram_select_m <= dram_select_x;
`endif
`ifdef CFG_IROM_ENABLED
irom_select_m <= irom_select_x;
`endif
wb_select_m <= wb_select_x;
end
end
end
// M/W stage pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
size_w <= 2'b00;
data_w <= {`LM32_WORD_WIDTH{1'b0}};
sign_extend_w <= `FALSE;
end
else
begin
size_w <= size_m;
data_w <= data_m;
sign_extend_w <= sign_extend_m;
end
end
/////////////////////////////////////////////////////
// Behavioural Logic
/////////////////////////////////////////////////////
// synthesis translate_off
// Check for non-aligned loads or stores
always @(posedge clk_i)
begin
if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
begin
if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
// synthesis translate_on
endmodule
|
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
/*
Implements a butterfly module for a FFT.
Takes complex numbers W, XA, XB and returns
YA = XA + W*XB
YB = XA - W*XB
It can take input no more frequently than once every
two steps. This is so, hopefully, less multiply
blocks can be used.
*/
module butterfly
#(
// The width of m_in.
parameter M_WDTH = 0,
// The width of the input, output and twiddle factors.
parameter X_WDTH = 0
)
(
input wire clk,
input wire rst_n,
// m_in contains data that passes through this block with no change.
// It is delayed for 3 counts like x_nd->y_nd.
input wire [M_WDTH-1:0] m_in,
// The twiddle factor.
input wire signed [2*X_WDTH-1:0] w,
// XA
input wire signed [2*X_WDTH-1:0] xa,
// XB
input wire signed [2*X_WDTH-1:0] xb,
// Set to 1 when new data is present on inputs.
// Cannot be set to 1 for two consecutive steps.
input wire x_nd,
// delayed version of m_in.
output reg [M_WDTH-1:0] m_out,
// YA = XA + W*XB
// YB = XA - W*XB
// When y_nd=1 y_re and y_im are outputing YA.
// The step after they are outputting YB.
output wire signed [2*X_WDTH-1:0] y,
output reg y_nd
);
// Set wire to the real and imag parts for convenience.
wire signed [X_WDTH-1:0] w_re;
wire signed [X_WDTH-1:0] w_im;
assign w_re = w[2*X_WDTH-1:X_WDTH];
assign w_im = w[X_WDTH-1:0];
wire signed [X_WDTH-1:0] xa_re;
wire signed [X_WDTH-1:0] xa_im;
assign xa_re = xa[2*X_WDTH-1:X_WDTH];
assign xa_im = xa[X_WDTH-1:0];
wire signed [X_WDTH-1:0] xb_re;
wire signed [X_WDTH-1:0] xb_im;
assign xb_re = xb[2*X_WDTH-1:X_WDTH];
assign xb_im = xb[X_WDTH-1:0];
reg signed [X_WDTH-1: 0] y_re;
reg signed [X_WDTH-1: 0] y_im;
assign y = {y_re, y_im};
// Delayed m_in.
reg signed [M_WDTH-1:0] m[1:0];
// Delayed XA
reg signed [X_WDTH-1:0] za_re[1:0];
reg signed [X_WDTH-1:0] za_im[1:0];
// Delayed XB
reg signed [X_WDTH-1:0] zb_re;
reg signed [X_WDTH-1:0] zb_im;
// Delayed W
reg signed [X_WDTH-1:0] ww_re;
reg signed [X_WDTH-1:0] ww_im;
// Delayed x_nd
reg signed x_nd_old[2:0];
// Storage for output of multipliers
reg signed [2*X_WDTH-1:0] zbw_m1;
reg signed [2*X_WDTH-1:0] zbw_m2;
// W * XB
reg signed [X_WDTH-1:0] zbw_re;
wire signed [X_WDTH-1:0] zbw_im;
assign zbw_im = (zbw_m1 >>> (X_WDTH-2)) + (zbw_m2 >>> (X_WDTH-2));
reg signed [X_WDTH-1:0] zbw_im_old;
// Wire of longer length for adding or substracting W*XB to XA.
// If we don't create longer wires for them then we can lose the
// high bit. The contents of these wires are downshifted into a
// normal size for use.
wire signed [X_WDTH:0] z1_re_big;
wire signed [X_WDTH:0] z1_im_big;
assign z1_re_big = za_re[0] + zbw_re;
assign z1_im_big = za_im[0] + zbw_im;
wire signed [X_WDTH:0] z2_re_big;
wire signed [X_WDTH:0] z2_im_big;
assign z2_re_big = za_re[1] - zbw_re;
assign z2_im_big = za_im[1] - zbw_im_old;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
y_nd <= 1'b0;
end
else
begin
// Set delay for x_nd_old and m.
x_nd_old[0] <= x_nd;
x_nd_old[1] <= x_nd_old[0];
x_nd_old[2] <= x_nd_old[1];
m[0] <= m_in;
m[1] <= m[0];
m_out <= m[1];
// STAGE 1
if (x_nd)
begin
za_re[0] <= xa_re;
za_im[0] <= xa_im;
ww_re <= w_re;
ww_im <= w_im;
zb_re <= xb_re;
zb_im <= xb_im;
// We perform two multiplications for calculate the real part
// of W*XB.
zbw_m1 <= xb_re*w_re;
zbw_m2 <= xb_im*w_im;
if (x_nd_old[0])
$display("ERROR: BF got new data two steps in a row.");
end
if (x_nd_old[0])
// STAGE 2
begin
// Now start the multiplications for the imag part of W*WB.
zbw_m1 <= zb_re*ww_im;
zbw_m2 <= zb_im*ww_re;
// Downshift the multiplied results into normal width and
// substract them.
// Overflow is not possible upon substraction since we
// know that W and XB both have magnitude less than 1
// so their multiple must also.
zbw_re <= (zbw_m1 >>> (X_WDTH-2)) - (zbw_m2 >>> (X_WDTH-2));
end
// STAGE 3
if (x_nd_old[1])
begin
// We only need to shift the required delayed data
// with XA every two steps since new input cannot
// arrive more frequently than that.
// XA is needed by a wire calculating z2_re_big and ze_im_big
// next step.
za_re[1] <= za_re[0];
za_im[1] <= za_im[0];
// Output YA.
y_nd <= 1'b1;
y_re <= z1_re_big >>> 1;
y_im <= z1_im_big >>> 1;
zbw_im_old <= zbw_im;
end
// STAGE 4
if (x_nd_old[2])
begin
// Output YB.
y_nd <= 1'b0;
y_re <= z2_re_big >>> 1;
y_im <= z2_im_big >>> 1;
end
end
end
endmodule
|
/*!
* <b>Module:</b>gtxe2_channel_wrapper
* @file gtxe2_channel_wrapper.v
* @date 2015-09-07
* @author Alexey
*
* @brief wrapper to switch between closed unisims primitive and open-source one
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* GTXE2_GPL.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* GTXE2_GPL.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`include "system_defines.vh"
module gtxe2_channel_wrapper(
// clocking ports, UG476 p.37
input [2:0] CPLLREFCLKSEL,
input GTGREFCLK,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input [1:0] RXSYSCLKSEL,
input [1:0] TXSYSCLKSEL,
output GTREFCLKMONITOR,
// CPLL Ports, UG476 p.48
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input CPLLRESET,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [9:0] TSTOUT,
input [15:0] GTRSVD,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input [4:0] PMARSVDIN2,
input [19:0] TSTIN,
// Reset Mode ports, ug476 p.62
input GTRESETSEL,
input RESETOVRD,
// TX Reset ports, ug476 p.65
input CFGRESET,
input GTTXRESET,
input TXPCSRESET,
input TXPMARESET,
output TXRESETDONE,
input TXUSERRDY,
output [15:0] PCSRSVDOUT,
// RX Reset ports, UG476 p.73
input GTRXRESET,
input RXPMARESET,
input RXCDRRESET,
input RXCDRFREQRESET,
input RXDFELPMRESET,
input EYESCANRESET,
input RXPCSRESET,
input RXBUFRESET,
input RXUSERRDY,
output RXRESETDONE,
input RXOOBRESET,
// Power Down ports, ug476 p.88
input [1:0] RXPD,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHDLYPD,
input RXPHDLYPD,
// Loopback ports, ug476 p.91
input [2:0] LOOPBACK,
// Dynamic Reconfiguration Port, ug476 p.92
input [8:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
output [15:0] DRPDO,
input DRPEN,
output DRPRDY,
input DRPWE,
// Digital Monitor Ports, ug476 p.95
input [3:0] CLKRSVD,
output [7:0] DMONITOROUT,
// TX Interface Ports, ug476 p.110
input [7:0] TXCHARDISPMODE,
input [7:0] TXCHARDISPVAL,
input [63:0] TXDATA,
input TXUSRCLK,
input TXUSRCLK2,
// TX 8B/10B encoder ports, ug476 p.118
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [7:0] TXCHARISK,
// TX Gearbox ports, ug476 p.122
output TXGEARBOXREADY,
input [2:0] TXHEADER,
input [6:0] TXSEQUENCE,
input TXSTARTSEQ,
// TX BUffer Ports, ug476 p.134
output [1:0] TXBUFSTATUS,
// TX Buffer Bypass Ports, ug476 p.136
input TXDLYSRESET,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHINIT,
input TXPHOVRDEN,
input TXPHDLYRESET,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYOVRDEN,
input TXPHDLYTSTCLK,
input TXDLYHOLD,
input TXDLYUPDOWN,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXDLYSRESETDONE,
/* input TXSYNCMODE,
input TXSYNCALLIN,
input TXSYNCIN,
output TXSYNCOUT,
output TXSYNCDONE,*/
// TX Pattern Generator, ug476 p.147
input [2:0] TXPRBSSEL,
input TXPRBSFORCEERR,
// TX Polarity Control Ports, ug476 p.149
input TXPOLARITY,
// TX Fabric Clock Output Control Ports, ug476 p.152
input [2:0] TXOUTCLKSEL,
input [2:0] TXRATE,
output TXOUTCLKFABRIC,
output TXOUTCLK,
output TXOUTCLKPCS,
output TXRATEDONE,
// TX Phase Interpolator PPM Controller Ports, ug476 p.154
// GTH only
/* input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMSEL,
input TXPIPPMPD,
input [4:0] TXPIPPMSTEPSIZE,*/
// TX Configurable Driver Ports, ug476 p.156
input [2:0] TXBUFDIFFCTRL,
input TXDEEMPH,
input [3:0] TXDIFFCTRL,
input TXELECIDLE,
input TXINHIBIT,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input TXQPIBIASEN,
output TXQPISENN,
output TXQPISENP,
input TXQPISTRONGPDOWN,
input TXQPIWEAKPUP,
input [4:0] TXPOSTCURSOR,
input TXPOSTCURSORINV,
input [4:0] TXPRECURSOR,
input TXPRECURSORINV,
input TXSWING,
input TXDIFFPD,
input TXPISOPD,
// TX Receiver Detection Ports, ug476 p.165
input TXDETECTRX,
output PHYSTATUS,
output [2:0] RXSTATUS,
// TX OOB Signaling Ports, ug476 p.166
output TXCOMFINISH,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
// RX AFE Ports, ug476 p.171
output RXQPISENN,
output RXQPISENP,
input RXQPIEN,
// RX OOB Signaling Ports, ug476 p.178
input [1:0] RXELECIDLEMODE,
output RXELECIDLE,
output RXCOMINITDET,
output RXCOMSASDET,
output RXCOMWAKEDET,
// RX Equalizer Ports, ug476 p.189
input RXLPMEN,
input RXOSHOLD,
input RXOSOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFECM1EN,
input RXDFEXYDHOLD,
input RXDFEXYDOVRDEN,
input RXDFEXYDEN,
input [1:0] RXMONITORSEL,
output [6:0] RXMONITOROUT,
// CDR Ports, ug476 p.202
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESETRSV,
input [2:0] RXRATE,
output RXCDRLOCK,
// RX Fabric Clock Output Control Ports, ug476 p.213
input [2:0] RXOUTCLKSEL,
output RXOUTCLKFABRIC,
output RXOUTCLK,
output RXOUTCLKPCS,
output RXRATEDONE,
input RXDLYBYPASS,
// RX Margin Analysis Ports, ug476 p.220
output EYESCANDATAERROR,
input EYESCANTRIGGER,
input EYESCANMODE,
// RX Polarity Control Ports, ug476 p.224
input RXPOLARITY,
// Pattern Checker Ports, ug476 p.225
input RXPRBSCNTRESET,
input [2:0] RXPRBSSEL,
output RXPRBSERR,
// RX Byte and Word Alignment Ports, ug476 p.233
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCOMMADET,
input RXCOMMADETEN,
input RXPCOMMAALIGNEN,
input RXMCOMMAALIGNEN,
input RXSLIDE,
// RX 8B/10B Decoder Ports, ug476 p.241
input RX8B10BEN,
output [7:0] RXCHARISCOMMA,
output [7:0] RXCHARISK,
output [7:0] RXDISPERR,
output [7:0] RXNOTINTABLE,
input SETERRSTATUS,
// RX Buffer Bypass Ports, ug476 p.244
input RXPHDLYRESET,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHOVRDEN,
input RXDLYSRESET,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDDIEN,
output RXPHALIGNDONE,
output [4:0] RXPHMONITOR,
output [4:0] RXPHSLIPMONITOR,
output RXDLYSRESETDONE,
// RX Buffer Ports, ug476 p.259
output [2:0] RXBUFSTATUS,
// RX Clock Correction Ports, ug476 p.263
output [1:0] RXCLKCORCNT,
// RX Channel Bonding Ports, ug476 p.274
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
input [4:0] RXCHBONDI,
output [4:0] RXCHBONDO,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCHBONDEN,
// RX Gearbox Ports, ug476 p.285
output RXDATAVALID,
input RXGEARBOXSLIP,
output [2:0] RXHEADER,
output RXHEADERVALID,
output RXSTARTOFSEQ,
// FPGA RX Interface Ports, ug476 p.299
output [63:0] RXDATA,
input RXUSRCLK,
input RXUSRCLK2,
// ug476, p.323
output RXVALID,
// for correct clocking scheme in case of multilane structure
input QPLLCLK,
input QPLLREFCLK,
// Diffpairs
input GTXRXP,
input GTXRXN,
output GTXTXN,
output GTXTXP
);
// simulation common attributes, UG476 p.28
parameter SIM_RESET_SPEEDUP = "TRUE";
parameter SIM_CPLLREFCLK_SEL = 3'b001;
parameter SIM_RECEIVER_DETECT_PASS = "TRUE";
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X";
parameter SIM_VERSION = "1.0";
// Clocking Atributes, UG476 p.38
parameter OUTREFCLK_SEL_INV = 1'b0;
// CPLL Attributes, UG476 p.49
parameter CPLL_CFG = 24'h0;
parameter CPLL_FBDIV = 4;
parameter CPLL_FBDIV_45 = 5;
parameter CPLL_INIT_CFG = 24'h0;
parameter CPLL_LOCK_CFG = 16'h0;
parameter CPLL_REFCLK_DIV = 1;
parameter RXOUT_DIV = 2;
parameter TXOUT_DIV = 2;
parameter SATA_CPLL_CFG = "VCO_3000MHZ";
parameter PMA_RSV3 = 2'b00;
// TX Initialization and Reset Attributes, ug476 p.66
parameter TXPCSRESET_TIME = 5'b00001;
parameter TXPMARESET_TIME = 5'b00001;
// RX Initialization and Reset Attributes, UG476 p.75
parameter RXPMARESET_TIME = 5'h0;
parameter RXCDRPHRESET_TIME = 5'h0;
parameter RXCDRFREQRESET_TIME = 5'h0;
parameter RXDFELPMRESET_TIME = 7'h0;
parameter RXISCANRESET_TIME = 7'h0;
parameter RXPCSRESET_TIME = 5'h0;
parameter RXBUFRESET_TIME = 5'h0;
// Power Down attributes, ug476 p.88
parameter PD_TRANS_TIME_FROM_P2 = 12'h0;
parameter PD_TRANS_TIME_NONE_P2 = 8'h0;
parameter PD_TRANS_TIME_TO_P2 = 8'h0;
parameter TRANS_TIME_RATE = 8'h0;
parameter RX_CLKMUX_PD = 1'b0;
parameter TX_CLKMUX_PD = 1'b0;
// GTX Digital Monitor Attributes, ug476 p.96
parameter DMONITOR_CFG = 24'h008101;
// TX Interface attributes, ug476 p.111
parameter TX_DATA_WIDTH = 20;
parameter TX_INT_DATAWIDTH = 0;
// TX Gearbox Attributes, ug476 p.121
parameter GEARBOX_MODE = 3'h0;
parameter TXGEARBOX_EN = "FALSE";
// TX BUffer Attributes, ug476 p.134
parameter TXBUF_EN = "TRUE";
// TX Bypass buffer, ug476 p.138
parameter TX_XCLK_SEL = "TXOUT";
parameter TXPH_CFG = 16'h0;
parameter TXPH_MONITOR_SEL = 5'h0;
parameter TXPHDLY_CFG = 24'h0;
parameter TXDLY_CFG = 16'h0;
parameter TXDLY_LCFG = 9'h0;
parameter TXDLY_TAP_CFG = 16'h0;
//parameter TXSYNC_MULTILANE = 1'b0;
//parameter TXSYNC_SKIP_DA = 1'b0;
//parameter TXSYNC_OVRD = 1'b1;
//parameter LOOPBACK_CFG = 1'b0;
// TX Pattern Generator, ug476 p.147
parameter RXPRBS_ERR_LOOPBACK = 1'b0;
// TX Fabric Clock Output Control Attributes, ug476 p. 153
parameter TXBUF_RESET_ON_RATE_CHANGE = "TRUE";
// TX Phase Interpolator PPM Controller Attributes, ug476 p.155
// GTH only
/*parameter TXPI_SYNCFREQ_PPM = 3'b001;
parameter TXPI_PPM_CFG = 8'd0;
parameter TXPI_INVSTROBE_SEL = 1'b0;
parameter TXPI_GREY_SEL = 1'b0;
parameter TXPI_PPMCLK_SEL = "12345";*/
// TX Configurable Driver Attributes, ug476 p.162
parameter TX_DEEMPH0 = 5'b10100;
parameter TX_DEEMPH1 = 5'b01101;
parameter TX_DRIVE_MODE = "DIRECT";
parameter TX_MAINCURSOR_SEL = 1'b0;
parameter TX_MARGIN_FULL_0 = 7'b0;
parameter TX_MARGIN_FULL_1 = 7'b0;
parameter TX_MARGIN_FULL_2 = 7'b0;
parameter TX_MARGIN_FULL_3 = 7'b0;
parameter TX_MARGIN_FULL_4 = 7'b0;
parameter TX_MARGIN_LOW_0 = 7'b0;
parameter TX_MARGIN_LOW_1 = 7'b0;
parameter TX_MARGIN_LOW_2 = 7'b0;
parameter TX_MARGIN_LOW_3 = 7'b0;
parameter TX_MARGIN_LOW_4 = 7'b0;
parameter TX_PREDRIVER_MODE = 1'b0;
parameter TX_QPI_STATUS_EN = 1'b0;
parameter TX_EIDLE_ASSERT_DELAY = 3'b110;
parameter TX_EIDLE_DEASSERT_DELAY = 3'b100;
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE";
// TX Receiver Detection Attributes, ug476 p.165
parameter TX_RXDETECT_CFG = 14'h0;
parameter TX_RXDETECT_REF = 3'h0;
// TX OOB Signaling Attributes
parameter SATA_BURST_SEQ_LEN = 4'b0101;
// RX AFE Attributes, ug476 p.171
parameter RX_CM_SEL = 2'b11;
parameter TERM_RCAL_CFG = 5'b0;
parameter TERM_RCAL_OVRD = 1'b0;
parameter RX_CM_TRIM = 3'b010;
// RX OOB Signaling Attributes, ug476 p.179
parameter PCS_RSVD_ATTR = 48'h0100; // oob is up
parameter RXOOB_CFG = 7'b0000110;
parameter SATA_BURST_VAL = 3'b110;
parameter SATA_EIDLE_VAL = 3'b110;
parameter SAS_MIN_COM = 36;
parameter SATA_MIN_INIT = 12;
parameter SATA_MIN_WAKE = 4;
parameter SATA_MAX_BURST = 8;
parameter SATA_MIN_BURST = 4;
parameter SAS_MAX_COM = 64;
parameter SATA_MAX_INIT = 21;
parameter SATA_MAX_WAKE = 7;
// RX Equalizer Attributes, ug476 p.193
parameter RX_OS_CFG = 13'h0080;
parameter RXLPM_LF_CFG = 14'h00f0;
parameter RXLPM_HF_CFG = 14'h00f0;
parameter RX_DFE_LPM_CFG = 16'h0;
parameter RX_DFE_GAIN_CFG = 23'h020FEA;
parameter RX_DFE_H2_CFG = 12'h0;
parameter RX_DFE_H3_CFG = 12'h040;
parameter RX_DFE_H4_CFG = 11'h0e0;
parameter RX_DFE_H5_CFG = 11'h0e0;
parameter PMA_RSV = 32'h00018480;
parameter RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0;
parameter RX_DFE_XYD_CFG = 13'h0;
parameter PMA_RSV4 = 32'h0;
parameter PMA_RSV2 = 16'h0;
parameter RX_BIAS_CFG = 12'h040;
parameter RX_DEBUG_CFG = 12'h0;
parameter RX_DFE_KL_CFG = 13'h0;
parameter RX_DFE_KL_CFG2 = 32'h0;
parameter RX_DFE_UT_CFG = 17'h11e00;
parameter RX_DFE_VP_CFG = 17'h03f03;
// CDR Attributes, ug476 p.203
parameter RXCDR_CFG = 72'h0;
parameter RXCDR_LOCK_CFG = 6'h0;
parameter RXCDR_HOLD_DURING_EIDLE = 1'b0;
parameter RXCDR_FR_RESET_ON_EIDLE = 1'b0;
parameter RXCDR_PH_RESET_ON_EIDLE = 1'b0;
// RX Fabric Clock Output Control Attributes
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE";
// RX Margin Analysis Attributes
parameter ES_VERT_OFFSET = 9'h0;
parameter ES_HORZ_OFFSET = 12'h0;
parameter ES_PRESCALE = 5'h0;
parameter ES_SDATA_MASK = 80'h0;
parameter ES_QUALIFIER = 80'h0;
parameter ES_QUAL_MASK = 80'h0;
parameter ES_EYE_SCAN_EN = 1'b1;
parameter ES_ERRDET_EN = 1'b0;
parameter ES_CONTROL = 6'h0;
parameter RX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0;
parameter ES_PMA_CFG = 10'h0;
// Pattern Checker Attributes, ug476 p.226
//parameter RX_PRBS_ERR_CNT = 16'h15c;
// RX Byte and Word Alignment Attributes, ug476 p.235
parameter ALIGN_COMMA_WORD = 1;
parameter ALIGN_COMMA_ENABLE = 10'b1111111111;
parameter ALIGN_COMMA_DOUBLE = "FALSE";
parameter ALIGN_MCOMMA_DET = "TRUE";
parameter ALIGN_MCOMMA_VALUE = 10'b1010000011;
parameter ALIGN_PCOMMA_DET = "TRUE";
parameter ALIGN_PCOMMA_VALUE = 10'b0101111100;
parameter SHOW_REALIGN_COMMA = "TRUE";
parameter RXSLIDE_MODE = "OFF";
parameter RXSLIDE_AUTO_WAIT = 7;
parameter RX_SIG_VALID_DLY = 10;
//parameter COMMA_ALIGN_LATENCY = 9'h14e;
// RX 8B/10B Decoder Attributes, ug476 p.242
parameter RX_DISPERR_SEQ_MATCH = "TRUE";
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "FALSE";
parameter UCODEER_CLR = 1'b0;
// RX Buffer Bypass Attributes, ug476 p.247
parameter RXBUF_EN = "TRUE";
parameter RX_XCLK_SEL = "RXREC";
parameter RXPH_CFG = 24'h0;
parameter RXPH_MONITOR_SEL = 5'h0;
parameter RXPHDLY_CFG = 24'h0;
parameter RXDLY_CFG = 16'h0;
parameter RXDLY_LCFG = 9'h0;
parameter RXDLY_TAP_CFG = 16'h0;
parameter RX_DDI_SEL = 6'h0;
parameter TST_RSV = 32'h0;
// RX Buffer Attributes, ug476 p.259
parameter RX_BUFFER_CFG = 6'b0;
parameter RX_DEFER_RESET_BUF_EN = "TRUE";
parameter RXBUF_ADDR_MODE = "FAST";
parameter RXBUF_EIDLE_HI_CNT = 4'b0;
parameter RXBUF_EIDLE_LO_CNT = 4'b0;
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE";
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE";
parameter RXBUF_RESET_ON_EIDLE = "FALSE";
parameter RXBUF_THRESH_OVFLW = 0;
parameter RXBUF_THRESH_OVRD = "FALSE";
parameter RXBUF_THRESH_UNDFLW = 0;
// RX Clock Correction Attributes, ug476 p.265
parameter CBCC_DATA_SOURCE_SEL = "DECODED";
parameter CLK_CORRECT_USE = "FALSE";
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_KEEP_IDLE = "FALSE";
parameter CLK_COR_MAX_LAT = 9;
parameter CLK_COR_MIN_LAT = 7;
parameter CLK_COR_PRECEDENCE = "TRUE";
parameter CLK_COR_REPEAT_WAIT = 0;
parameter CLK_COR_SEQ_LEN = 1;
parameter CLK_COR_SEQ_1_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_1_1 = 10'b0;
parameter CLK_COR_SEQ_1_2 = 10'b0;
parameter CLK_COR_SEQ_1_3 = 10'b0;
parameter CLK_COR_SEQ_1_4 = 10'b0;
parameter CLK_COR_SEQ_2_ENABLE = 4'b1111;
parameter CLK_COR_SEQ_2_1 = 10'b0;
parameter CLK_COR_SEQ_2_2 = 10'b0;
parameter CLK_COR_SEQ_2_3 = 10'b0;
parameter CLK_COR_SEQ_2_4 = 10'b0;
// RX Channel Bonding Attributes, ug476 p.276
parameter CHAN_BOND_MAX_SKEW = 1;
parameter CHAN_BOND_KEEP_ALIGN = "FALSE";
parameter CHAN_BOND_SEQ_LEN = 1;
parameter CHAN_BOND_SEQ_1_1 = 10'b0;
parameter CHAN_BOND_SEQ_1_2 = 10'b0;
parameter CHAN_BOND_SEQ_1_3 = 10'b0;
parameter CHAN_BOND_SEQ_1_4 = 10'b0;
parameter CHAN_BOND_SEQ_1_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_1 = 10'b0;
parameter CHAN_BOND_SEQ_2_2 = 10'b0;
parameter CHAN_BOND_SEQ_2_3 = 10'b0;
parameter CHAN_BOND_SEQ_2_4 = 10'b0;
parameter CHAN_BOND_SEQ_2_ENABLE = 4'b1111;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter FTS_DESKEW_SEQ_ENABLE = 4'b1111;
parameter FTS_LANE_DESKEW_CFG = 4'b1111;
parameter FTS_LANE_DESKEW_EN = "FALSE";
parameter PCS_PCIE_EN = "FALSE";
// RX Gearbox Attributes, ug476 p.287
parameter RXGEARBOX_EN = "FALSE";
// ug476 table p.326 - undocumented parameters
parameter RX_CLK25_DIV = 6;
parameter TX_CLK25_DIV = 6;
`ifdef OPEN_SOURCE_ONLY
GTXE2_GPL #(
`else // OPEN_SOURCE_ONLY
GTXE2_CHANNEL #(
`endif // OPEN_SOURCE_ONLY
// simulation common attributes, UG476 p.28
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_CPLLREFCLK_SEL (SIM_CPLLREFCLK_SEL),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION),
// Clocking Atributes, UG476 p.38
.OUTREFCLK_SEL_INV (OUTREFCLK_SEL_INV),
// CPLL Attributes, UG476 p.49
.CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV),
.CPLL_FBDIV_45 (CPLL_FBDIV_45),
.CPLL_INIT_CFG (CPLL_INIT_CFG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV),
.RXOUT_DIV (RXOUT_DIV),
.TXOUT_DIV (TXOUT_DIV),
.SATA_CPLL_CFG (SATA_CPLL_CFG),
.PMA_RSV3 (PMA_RSV3),
// TX Initialization and Reset Attributes, ug476 p.66
.TXPCSRESET_TIME (TXPCSRESET_TIME),
.TXPMARESET_TIME (TXPMARESET_TIME),
// RX Initialization and Reset Attributes, UG476 p.75
.RXPMARESET_TIME (RXPMARESET_TIME),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME),
.RXISCANRESET_TIME (RXISCANRESET_TIME),
.RXPCSRESET_TIME (RXPCSRESET_TIME),
.RXBUFRESET_TIME (RXBUFRESET_TIME),
// Power Down attributes, ug476 p.88
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2),
.TRANS_TIME_RATE (TRANS_TIME_RATE),
.RX_CLKMUX_PD (RX_CLKMUX_PD),
.TX_CLKMUX_PD (TX_CLKMUX_PD),
// GTX Digital Monitor Attributes, ug476 p.96
.DMONITOR_CFG (DMONITOR_CFG),
// TX Interface attributes, ug476 p.111
.TX_DATA_WIDTH (TX_DATA_WIDTH),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH),
// TX Gearbox Attributes, ug476 p.121
.GEARBOX_MODE (GEARBOX_MODE),
.TXGEARBOX_EN (TXGEARBOX_EN),
// TX BUffer Attributes, ug476 p.134
.TXBUF_EN (TXBUF_EN),
// TX Bypass buffer, ug476 p.138
.TX_XCLK_SEL (TX_XCLK_SEL),
.TXPH_CFG (TXPH_CFG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL),
.TXPHDLY_CFG (TXPHDLY_CFG),
.TXDLY_CFG (TXDLY_CFG),
.TXDLY_LCFG (TXDLY_LCFG),
.TXDLY_TAP_CFG (TXDLY_TAP_CFG),
/* .TXSYNC_MULTILANE (TXSYNC_MULTILANE),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA),
.TXSYNC_OVRD (TXSYNC_OVRD),
.LOOPBACK_CFG (LOOPBACK_CFG),*/
// TX Pattern Generator, ug476 p.147
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK),
// TX Fabric Clock Output Control Attributes, ug476 p. 153
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE),
// TX Phase Interpolator PPM Controller Attributes, ug476 p.155
// GTH only
/* .TXPI_SYNCFREQ_PPM (TXPI_SYNCFREQ_PPM),
.TXPI_PPM_CFG (TXPI_PPM_CFG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL),
.TXPI_GREY_SEL (TXPI_GREY_SEL),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL),*/
// TX Configurable Driver Attributes, ug476 p.162
.TX_DEEMPH0 (TX_DEEMPH0),
.TX_DEEMPH1 (TX_DEEMPH1),
.TX_DRIVE_MODE (TX_DRIVE_MODE),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.TX_PREDRIVER_MODE (TX_PREDRIVER_MODE),
.TX_QPI_STATUS_EN (TX_QPI_STATUS_EN),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ),
// TX Receiver Detection Attributes, ug476 p.165
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
.TX_RXDETECT_REF (TX_RXDETECT_REF),
// TX OOB Signaling Attributes
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN),
// RX AFE Attributes, ug476 p.171
.RX_CM_SEL (RX_CM_SEL),
.TERM_RCAL_CFG (TERM_RCAL_CFG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD),
.RX_CM_TRIM (RX_CM_TRIM),
// RX OOB Signaling Attributes, ug476 p.179
.PCS_RSVD_ATTR (PCS_RSVD_ATTR),
.RXOOB_CFG (RXOOB_CFG),
.SATA_BURST_VAL (SATA_BURST_VAL),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL),
.SAS_MIN_COM (SAS_MIN_COM),
.SATA_MIN_INIT (SATA_MIN_INIT),
.SATA_MIN_WAKE (SATA_MIN_WAKE),
.SATA_MAX_BURST (SATA_MAX_BURST),
.SATA_MIN_BURST (SATA_MIN_BURST),
.SAS_MAX_COM (SAS_MAX_COM),
.SATA_MAX_INIT (SATA_MAX_INIT),
.SATA_MAX_WAKE (SATA_MAX_WAKE),
// RX Equalizer Attributes, ug476 p.193
.RX_OS_CFG (RX_OS_CFG),
.RXLPM_LF_CFG (RXLPM_LF_CFG),
.RXLPM_HF_CFG (RXLPM_HF_CFG),
.RX_DFE_LPM_CFG (RX_DFE_LPM_CFG),
.RX_DFE_GAIN_CFG (RX_DFE_GAIN_CFG),
.RX_DFE_H2_CFG (RX_DFE_H2_CFG),
.RX_DFE_H3_CFG (RX_DFE_H3_CFG),
.RX_DFE_H4_CFG (RX_DFE_H4_CFG),
.RX_DFE_H5_CFG (RX_DFE_H5_CFG),
.PMA_RSV (PMA_RSV),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE),
.RX_DFE_XYD_CFG (RX_DFE_XYD_CFG),
.PMA_RSV4 (PMA_RSV4),
.PMA_RSV2 (PMA_RSV2),
.RX_BIAS_CFG (RX_BIAS_CFG),
.RX_DEBUG_CFG (RX_DEBUG_CFG),
.RX_DFE_KL_CFG (RX_DFE_KL_CFG),
.RX_DFE_KL_CFG2 (RX_DFE_KL_CFG2),
.RX_DFE_UT_CFG (RX_DFE_UT_CFG),
.RX_DFE_VP_CFG (RX_DFE_VP_CFG),
// CDR Attributes, ug476 p.203
.RXCDR_CFG (RXCDR_CFG),
.RXCDR_LOCK_CFG (RXCDR_LOCK_CFG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE),
// RX Fabric Clock Output Control Attributes
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE),
// RX Margin Analysis Attributes
.ES_VERT_OFFSET (ES_VERT_OFFSET),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET),
.ES_PRESCALE (ES_PRESCALE),
.ES_SDATA_MASK (ES_SDATA_MASK),
.ES_QUALIFIER (ES_QUALIFIER),
.ES_QUAL_MASK (ES_QUAL_MASK),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN),
.ES_ERRDET_EN (ES_ERRDET_EN),
.ES_CONTROL (ES_CONTROL),
/* .es_control_status (es_control_status),
.es_rdata (es_rdata),
.es_sdata (es_sdata),
.es_error_count (es_error_count),
.es_sample_count (es_sample_count),*/
.RX_DATA_WIDTH (RX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.ES_PMA_CFG (ES_PMA_CFG),
// Pattern Checker Attributes, ug476 p.226
//.RX_PRBS_ERR_CNT (RX_PRBS_ERR_CNT),
// RX Byte and Word Alignment Attributes, ug476 p.235
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA),
.RXSLIDE_MODE (RXSLIDE_MODE),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY),
//.COMMA_ALIGN_LATENCY (COMMA_ALIGN_LATENCY),
// RX 8B/10B Decoder Attributes, ug476 p.242
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY),
.UCODEER_CLR (UCODEER_CLR),
// RX Buffer Bypass Attributes, ug476 p.247
.RXBUF_EN (RXBUF_EN),
.RX_XCLK_SEL (RX_XCLK_SEL),
.RXPH_CFG (RXPH_CFG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL),
.RXPHDLY_CFG (RXPHDLY_CFG),
.RXDLY_CFG (RXDLY_CFG),
.RXDLY_LCFG (RXDLY_LCFG),
.RXDLY_TAP_CFG (RXDLY_TAP_CFG),
.RX_DDI_SEL (RX_DDI_SEL),
.TST_RSV (TST_RSV),
// RX Buffer Attributes, ug476 p.259
.RX_BUFFER_CFG (RX_BUFFER_CFG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
// RX Clock Correction Attributes, ug476 p.265
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
.CLK_CORRECT_USE (CLK_CORRECT_USE),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4),
// RX Channel Bonding Attributes, ug476 p.276
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN),
.PCS_PCIE_EN (PCS_PCIE_EN),
// RX Gearbox Attributes, ug476 p.287
.RXGEARBOX_EN (RXGEARBOX_EN),
// ug476 table p.326 - undocumented parameters
.RX_CLK25_DIV (RX_CLK25_DIV),
.TX_CLK25_DIV (TX_CLK25_DIV)
)
`ifdef OPEN_SOURCE_ONLY
gtx_gpl(
`else // OPEN_SOURCE_ONLY
gtx_unisims(
`endif // OPEN_SOURCE_ONLY
// clocking ports, UG476 p.37
.CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTGREFCLK (GTGREFCLK),
.GTNORTHREFCLK0 (GTNORTHREFCLK0),
.GTNORTHREFCLK1 (GTNORTHREFCLK1),
.GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1),
.RXSYSCLKSEL (RXSYSCLKSEL),
.TXSYSCLKSEL (TXSYSCLKSEL),
.GTREFCLKMONITOR (GTREFCLKMONITOR),
// CPLL Ports, UG476 p.48
.CPLLLOCKDETCLK (CPLLLOCKDETCLK),
.CPLLLOCKEN (CPLLLOCKEN),
.CPLLPD (CPLLPD),
.CPLLRESET (CPLLRESET),
.CPLLFBCLKLOST (CPLLFBCLKLOST),
.CPLLLOCK (CPLLLOCK),
.CPLLREFCLKLOST (CPLLREFCLKLOST),
.TSTOUT (TSTOUT),
.GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN),
.PCSRSVDIN2 (PCSRSVDIN2),
.PMARSVDIN (PMARSVDIN),
.PMARSVDIN2 (PMARSVDIN2),
.TSTIN (TSTIN),
// Reset Mode ports, ug476 p.62
.GTRESETSEL (GTRESETSEL),
.RESETOVRD (RESETOVRD),
// TX Reset ports, ug476 p.65
.CFGRESET (CFGRESET),
.GTTXRESET (GTTXRESET),
.TXPCSRESET (TXPCSRESET),
.TXPMARESET (TXPMARESET),
.TXRESETDONE (TXRESETDONE),
.TXUSERRDY (TXUSERRDY),
.PCSRSVDOUT (PCSRSVDOUT),
// RX Reset ports, UG476 p.73
.GTRXRESET (GTRXRESET),
.RXPMARESET (RXPMARESET),
.RXCDRRESET (RXCDRRESET),
.RXCDRFREQRESET (RXCDRFREQRESET),
.RXDFELPMRESET (RXDFELPMRESET),
.EYESCANRESET (EYESCANRESET),
.RXPCSRESET (RXPCSRESET),
.RXBUFRESET (RXBUFRESET),
.RXUSERRDY (RXUSERRDY),
.RXRESETDONE (RXRESETDONE),
.RXOOBRESET (RXOOBRESET),
// Power Down ports, ug476 p.88
.RXPD (RXPD),
.TXPD (TXPD),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE),
.TXPHDLYPD (TXPHDLYPD),
.RXPHDLYPD (RXPHDLYPD),
// Loopback ports, ug476 p.91
.LOOPBACK (LOOPBACK),
// Dynamic Reconfiguration Port, ug476 p.92
.DRPADDR (DRPADDR),
.DRPCLK (DRPCLK),
.DRPDI (DRPDI),
.DRPDO (DRPDO),
.DRPEN (DRPEN),
.DRPRDY (DRPRDY),
.DRPWE (DRPWE),
// Digital Monitor Ports, ug476 p.95
.CLKRSVD (CLKRSVD),
.DMONITOROUT (DMONITOROUT),
// TX Interface Ports, ug476 p.110
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXDATA (TXDATA),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
// TX 8B/10B encoder ports, ug476 p.118
.TX8B10BBYPASS (TX8B10BBYPASS),
.TX8B10BEN (TX8B10BEN),
.TXCHARISK (TXCHARISK),
// TX Gearbox ports, ug476 p.122
.TXGEARBOXREADY (TXGEARBOXREADY),
.TXHEADER (TXHEADER),
.TXSEQUENCE (TXSEQUENCE),
.TXSTARTSEQ (TXSTARTSEQ),
// TX BUffer Ports, ug476 p.134
.TXBUFSTATUS (TXBUFSTATUS),
// TX Buffer Bypass Ports, ug476 p.136
.TXDLYSRESET (TXDLYSRESET),
.TXPHALIGN (TXPHALIGN),
.TXPHALIGNEN (TXPHALIGNEN),
.TXPHINIT (TXPHINIT),
.TXPHOVRDEN (TXPHOVRDEN),
.TXPHDLYRESET (TXPHDLYRESET),
.TXDLYBYPASS (TXDLYBYPASS),
.TXDLYEN (TXDLYEN),
.TXDLYOVRDEN (TXDLYOVRDEN),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK),
.TXDLYHOLD (TXDLYHOLD),
.TXDLYUPDOWN (TXDLYUPDOWN),
.TXPHALIGNDONE (TXPHALIGNDONE),
.TXPHINITDONE (TXPHINITDONE),
.TXDLYSRESETDONE (TXDLYSRESETDONE),
/* .TXSYNCMODE (TXSYNCMODE),
.TXSYNCALLIN (TXSYNCALLIN),
.TXSYNCIN (TXSYNCIN),
.TXSYNCOUT (TXSYNCOUT),
.TXSYNCDONE (TXSYNCDONE),*/
// TX Pattern Generator, ug476 p.147
.TXPRBSSEL (TXPRBSSEL),
.TXPRBSFORCEERR (TXPRBSFORCEERR),
// TX Polarity Control Ports, ug476 p.149
.TXPOLARITY (TXPOLARITY),
// TX Fabric Clock Output Control Ports, ug476 p.152
.TXOUTCLKSEL (TXOUTCLKSEL),
.TXRATE (TXRATE),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.TXOUTCLK (TXOUTCLK),
.TXOUTCLKPCS (TXOUTCLKPCS),
.TXRATEDONE (TXRATEDONE),
// TX Phase Interpolator PPM Controller Ports, ug476 p.154
// GTH only
/* input TXPIPPMEN,
.TXPIPPMOVRDEN (TXPIPPMOVRDEN),
.TXPIPPMSEL (TXPIPPMSEL),
.TXPIPPMPD (TXPIPPMPD),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE),*/
// TX Configurable Driver Ports, ug476 p.156
.TXBUFDIFFCTRL (TXBUFDIFFCTRL),
.TXDEEMPH (TXDEEMPH),
.TXDIFFCTRL (TXDIFFCTRL),
.TXELECIDLE (TXELECIDLE),
.TXINHIBIT (TXINHIBIT),
.TXMAINCURSOR (TXMAINCURSOR),
.TXMARGIN (TXMARGIN),
.TXQPIBIASEN (TXQPIBIASEN),
.TXQPISENN (TXQPISENN),
.TXQPISENP (TXQPISENP),
.TXQPISTRONGPDOWN (TXQPISTRONGPDOWN),
.TXQPIWEAKPUP (TXQPIWEAKPUP),
.TXPOSTCURSOR (TXPOSTCURSOR),
.TXPOSTCURSORINV (TXPOSTCURSORINV),
.TXPRECURSOR (TXPRECURSOR),
.TXPRECURSORINV (TXPRECURSORINV),
.TXSWING (TXSWING),
.TXDIFFPD (TXDIFFPD),
.TXPISOPD (TXPISOPD),
// TX Receiver Detection Ports, ug476 p.165
.TXDETECTRX (TXDETECTRX),
.PHYSTATUS (PHYSTATUS),
.RXSTATUS (RXSTATUS),
// TX OOB Signaling Ports, ug476 p.166
.TXCOMFINISH (TXCOMFINISH),
.TXCOMINIT (TXCOMINIT),
.TXCOMSAS (TXCOMSAS),
.TXCOMWAKE (TXCOMWAKE),
// RX AFE Ports, ug476 p.171
.RXQPISENN (RXQPISENN),
.RXQPISENP (RXQPISENP),
.RXQPIEN (RXQPIEN),
// RX OOB Signaling Ports, ug476 p.178
.RXELECIDLEMODE (RXELECIDLEMODE),
.RXELECIDLE (RXELECIDLE),
.RXCOMINITDET (RXCOMINITDET),
.RXCOMSASDET (RXCOMSASDET),
.RXCOMWAKEDET (RXCOMWAKEDET),
// RX Equalizer Ports, ug476 p.189
.RXLPMEN (RXLPMEN),
.RXOSHOLD (RXOSHOLD),
.RXOSOVRDEN (RXOSOVRDEN),
.RXLPMLFHOLD (RXLPMLFHOLD),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN),
.RXLPMHFHOLD (RXLPMHFHOLD),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN),
.RXDFEAGCHOLD (RXDFEAGCHOLD),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN),
.RXDFELFHOLD (RXDFELFHOLD),
.RXDFELFOVRDEN (RXDFELFOVRDEN),
.RXDFEUTHOLD (RXDFEUTHOLD),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN),
// this signal shall be present only in GTH, but for some reason it's included in unisims gtxe2
.RXDFEVSEN (1'b0),
.RXDFEVPHOLD (RXDFEVPHOLD),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN),
.RXDFETAP2HOLD (RXDFETAP2HOLD),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN),
.RXDFETAP3HOLD (RXDFETAP3HOLD),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN),
.RXDFETAP4HOLD (RXDFETAP4HOLD),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN),
.RXDFETAP5HOLD (RXDFETAP5HOLD),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN),
.RXDFECM1EN (RXDFECM1EN),
.RXDFEXYDHOLD (RXDFEXYDHOLD),
.RXDFEXYDOVRDEN (RXDFEXYDOVRDEN),
.RXDFEXYDEN (RXDFEXYDEN),
.RXMONITORSEL (RXMONITORSEL),
.RXMONITOROUT (RXMONITOROUT),
// CDR Ports, ug476 p.202
.RXCDRHOLD (RXCDRHOLD),
.RXCDROVRDEN (RXCDROVRDEN),
.RXCDRRESETRSV (RXCDRRESETRSV),
.RXRATE (RXRATE),
.RXCDRLOCK (RXCDRLOCK),
// RX Fabric Clock Output Control Ports, ug476 p.213
.RXOUTCLKSEL (RXOUTCLKSEL),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.RXOUTCLK (RXOUTCLK),
.RXOUTCLKPCS (RXOUTCLKPCS),
.RXRATEDONE (RXRATEDONE),
.RXDLYBYPASS (RXDLYBYPASS),
// RX Margin Analysis Ports, ug476 p.220
.EYESCANDATAERROR (EYESCANDATAERROR),
.EYESCANTRIGGER (EYESCANTRIGGER),
.EYESCANMODE (EYESCANMODE),
// RX Polarity Control Ports, ug476 p.224
.RXPOLARITY (RXPOLARITY),
// Pattern Checker Ports, ug476 p.225
.RXPRBSCNTRESET (RXPRBSCNTRESET),
.RXPRBSSEL (RXPRBSSEL),
.RXPRBSERR (RXPRBSERR),
// RX Byte and Word Alignment Ports, ug476 p.233
.RXBYTEISALIGNED (RXBYTEISALIGNED),
.RXBYTEREALIGN (RXBYTEREALIGN),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETEN (RXCOMMADETEN),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN),
.RXSLIDE (RXSLIDE),
// RX 8B/10B Decoder Ports, ug476 p.24
.RX8B10BEN (RX8B10BEN),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXDISPERR (RXDISPERR),
.RXNOTINTABLE (RXNOTINTABLE),
.SETERRSTATUS (SETERRSTATUS),
// RX Buffer Bypass Ports, ug476 p.244
.RXPHDLYRESET (RXPHDLYRESET),
.RXPHALIGN (RXPHALIGN),
.RXPHALIGNEN (RXPHALIGNEN),
.RXPHOVRDEN (RXPHOVRDEN),
.RXDLYSRESET (RXDLYSRESET),
.RXDLYEN (RXDLYEN),
.RXDLYOVRDEN (RXDLYOVRDEN),
.RXDDIEN (RXDDIEN),
.RXPHALIGNDONE (RXPHALIGNDONE),
.RXPHMONITOR (RXPHMONITOR),
.RXPHSLIPMONITOR (RXPHSLIPMONITOR),
.RXDLYSRESETDONE (RXDLYSRESETDONE),
// RX Buffer Ports, ug476 p.259
.RXBUFSTATUS (RXBUFSTATUS),
// RX Clock Correction Ports, ug476 p.263
.RXCLKCORCNT (RXCLKCORCNT),
// RX Channel Bonding Ports, ug476 p.274
.RXCHANBONDSEQ (RXCHANBONDSEQ),
.RXCHANISALIGNED (RXCHANISALIGNED),
.RXCHANREALIGN (RXCHANREALIGN),
.RXCHBONDI (RXCHBONDI),
.RXCHBONDO (RXCHBONDO),
.RXCHBONDLEVEL (RXCHBONDLEVEL),
.RXCHBONDMASTER (RXCHBONDMASTER),
.RXCHBONDSLAVE (RXCHBONDSLAVE),
.RXCHBONDEN (RXCHBONDEN),
// RX Gearbox Ports, ug476 p.285
.RXDATAVALID (RXDATAVALID),
.RXGEARBOXSLIP (RXGEARBOXSLIP),
.RXHEADER (RXHEADER),
.RXHEADERVALID (RXHEADERVALID),
.RXSTARTOFSEQ (RXSTARTOFSEQ),
// FPGA RX Interface Ports, ug476 p.299
.RXDATA (RXDATA),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
// ug476, p.323
.RXVALID (RXVALID),
// for correct clocking scheme in case of multilane structure
.QPLLCLK (QPLLCLK),
.QPLLREFCLK (QPLLREFCLK),
// Diffpairs
.GTXRXP (GTXRXP),
.GTXRXN (GTXRXN),
.GTXTXN (GTXTXN),
.GTXTXP (GTXTXP)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_dp(/*AUTOARG*/
// Outputs
dp_data_mecc0, dp_data_mecc1, dp_data_mecc2, dp_data_mecc3,
dp_data_mecc4, dp_data_mecc5, dp_data_mecc6, dp_data_mecc7,
dram_io_data_out, dp_data_in, dp_ecc_in, dp_data_valid,
// Inputs
clk, rst_l, l2if_data_mecc0, l2if_data_mecc1, l2if_data_mecc2,
l2if_data_mecc3, l2if_data_mecc4, l2if_data_mecc5,
l2if_data_mecc6, l2if_data_mecc7, io_dram_data_in, io_dram_ecc_in,
io_dram_data_valid, que_bypass_scrb_data, que_mem_addr, que_mem_data,
dram_fail_over_mask, l2if_scrb_data_en, l2if_scrb_data,
l2if_scrb_ecc, err_inj_reg, err_mask_reg, que_wr_channel_mux,
ch1_que_mem_data, ch1_dp_data_mecc0, ch1_dp_data_mecc1,
ch1_dp_data_mecc2, ch1_dp_data_mecc3, ch1_dp_data_mecc4,
ch1_dp_data_mecc5, ch1_dp_data_mecc6, ch1_dp_data_mecc7,
que_st_cmd_addr_parity, que_channel_disabled, sshot_err_reg
);
//////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////
input clk;
input rst_l;
input [3:0] l2if_data_mecc0;
input [3:0] l2if_data_mecc1;
input [3:0] l2if_data_mecc2;
input [3:0] l2if_data_mecc3;
input [3:0] l2if_data_mecc4;
input [3:0] l2if_data_mecc5;
input [3:0] l2if_data_mecc6;
input [3:0] l2if_data_mecc7;
input [255:0] io_dram_data_in; // from pad
input [31:0] io_dram_ecc_in; // from pad
input io_dram_data_valid; // from pad
input que_bypass_scrb_data;
input [4:0] que_mem_addr;
input [255:0] que_mem_data;
input que_st_cmd_addr_parity;
input que_channel_disabled;
input [34:0] dram_fail_over_mask;
input l2if_scrb_data_en;
input [255:0] l2if_scrb_data;
input [33:0] l2if_scrb_ecc;
input err_inj_reg;
input [15:0] err_mask_reg;
// DUE TO 2 CHANNEL MODE
input que_wr_channel_mux;
input [255:0] ch1_que_mem_data;
input [3:0] ch1_dp_data_mecc0;
input [3:0] ch1_dp_data_mecc1;
input [3:0] ch1_dp_data_mecc2;
input [3:0] ch1_dp_data_mecc3;
input [3:0] ch1_dp_data_mecc4;
input [3:0] ch1_dp_data_mecc5;
input [3:0] ch1_dp_data_mecc6;
input [3:0] ch1_dp_data_mecc7;
output [3:0] dp_data_mecc0;
output [3:0] dp_data_mecc1;
output [3:0] dp_data_mecc2;
output [3:0] dp_data_mecc3;
output [3:0] dp_data_mecc4;
output [3:0] dp_data_mecc5;
output [3:0] dp_data_mecc6;
output [3:0] dp_data_mecc7;
//////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////
output [287:0] dram_io_data_out;
output [255:0] dp_data_in;
output [31:0] dp_ecc_in;
output dp_data_valid;
input sshot_err_reg;
//////////////////////////////////////////////////////////////////
// WIRES
//////////////////////////////////////////////////////////////////
wire [15:0] ecch;
wire [15:0] eccl;
wire [15:0] dp_mux_ecc_hi;
wire [15:0] dp_mux_ecc_pre_xor_hi;
wire [15:0] dp_mux_ecc_lo;
wire [15:0] dp_mux_ecc_pre_xor_lo;
wire [287:0] dp_pad_data;
wire [287:0] dp_wr_data_muxed_nibbles;
wire [255:0] dp_mux_data;
wire [33:0] dp_scrb_ecc0;
wire [33:0] dp_scrb_ecc1;
wire dp_scrb_data_en_cnt_in;
wire dp_scrb_data_en_cnt;
wire dp_scrb_wr_en;
wire dp_scrb_data0_en;
wire dp_scrb_data1_en;
wire dp_scrb_data_en;
wire [255:0] dp_scrb_cor_data;
wire [255:0] dp_scrb_data0;
wire [255:0] dp_scrb_data1;
wire [33:0] dp_scrb_cor_ecc;
wire [3:0] dp_data_mecc0_int;
wire [3:0] dp_data_mecc1_int;
wire [3:0] dp_data_mecc2_int;
wire [3:0] dp_data_mecc3_int;
wire [3:0] dp_data_mecc4_int;
wire [3:0] dp_data_mecc5_int;
wire [3:0] dp_data_mecc6_int;
wire [3:0] dp_data_mecc7_int;
wire dp_scrb_wr_data_en_cnt_in;
wire dp_scrb_wr_data_en_cnt;
//////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////
////////////////////////////////////////////////
// Scrub and Initial data
////////////////////////////////////////////////
// Flop the scrb enable and data from cpu clk to dramclk
dffrl_ns #(1) ff_data_en(
.din(l2if_scrb_data_en),
.q(dp_scrb_data_en),
.rst_l(rst_l),
.clk(clk));
dff_ns #(256) ff_l2_scrb_data(
.din(l2if_scrb_data[255:0]),
.q(dp_scrb_cor_data[255:0]),
.clk(clk));
dff_ns #(34) ff_l2_scrb_ecc(
.din(l2if_scrb_ecc[33:0]),
.q(dp_scrb_cor_ecc[33:0]),
.clk(clk));
// counter to keep track of data enable for capturing scrb data
assign dp_scrb_wr_en = dp_scrb_data_en | (|(dp_scrb_data_en_cnt));
assign dp_scrb_data_en_cnt_in = dp_scrb_data_en_cnt + 1'b1;
dffrle_ns #(1) ff_wr_en(
.din(dp_scrb_data_en_cnt_in),
.q(dp_scrb_data_en_cnt),
.rst_l(rst_l),
.en(dp_scrb_wr_en),
.clk(clk));
assign dp_scrb_data0_en = dp_scrb_data_en & (dp_scrb_data_en_cnt == 1'h0);
assign dp_scrb_data1_en = dp_scrb_data_en & (dp_scrb_data_en_cnt == 1'h1);
// scrub and initial data holders waiting to be written to dram
dffrle_ns #(256) ff_scrb_wr_data0(
.din({dp_scrb_cor_data[63:0],dp_scrb_cor_data[127:64], dp_scrb_cor_data[191:128],
dp_scrb_cor_data[255:192]}),
.q(dp_scrb_data0[255:0]),
.rst_l(rst_l),
.en(dp_scrb_data0_en),
.clk(clk));
dffrle_ns #(34) ff_scrb_wr_ecc0(
.din(dp_scrb_cor_ecc[33:0]),
.q(dp_scrb_ecc0[33:0]),
.rst_l(rst_l),
.en(dp_scrb_data0_en),
.clk(clk));
dffrle_ns #(256) ff_scrb_wr_data1(
.din({dp_scrb_cor_data[63:0],dp_scrb_cor_data[127:64], dp_scrb_cor_data[191:128],
dp_scrb_cor_data[255:192]}),
.q(dp_scrb_data1[255:0]),
.rst_l(rst_l),
.en(dp_scrb_data1_en),
.clk(clk));
dffrle_ns #(34) ff_scrb_wr_ecc1(
.din(dp_scrb_cor_ecc[33:0]),
.q(dp_scrb_ecc1[33:0]),
.rst_l(rst_l),
.en(dp_scrb_data1_en),
.clk(clk));
/////////////////////////////////////////
// Check if l2 data needs to be piosoned
/////////////////////////////////////////
wire [3:0] dp_pioson_l2_data;
wire [1:0] dp_pioson_l2_chunk;
wire [3:0] que_mem_addr_d1;
wire que_dp_wr_data_vld;
dffrl_ns #(32) ff_data_mecc(
.din({l2if_data_mecc0[3:0],l2if_data_mecc1[3:0],l2if_data_mecc2[3:0],l2if_data_mecc3[3:0],
l2if_data_mecc4[3:0],l2if_data_mecc5[3:0],l2if_data_mecc6[3:0],l2if_data_mecc7[3:0]}),
.q({dp_data_mecc0[3:0],dp_data_mecc1[3:0],dp_data_mecc2[3:0],dp_data_mecc3[3:0],
dp_data_mecc4[3:0],dp_data_mecc5[3:0],dp_data_mecc6[3:0],dp_data_mecc7[3:0]}),
.rst_l(rst_l),
.clk(clk));
assign dp_data_mecc0_int = que_wr_channel_mux ? ch1_dp_data_mecc0 : dp_data_mecc0;
assign dp_data_mecc1_int = que_wr_channel_mux ? ch1_dp_data_mecc1 : dp_data_mecc1;
assign dp_data_mecc2_int = que_wr_channel_mux ? ch1_dp_data_mecc2 : dp_data_mecc2;
assign dp_data_mecc3_int = que_wr_channel_mux ? ch1_dp_data_mecc3 : dp_data_mecc3;
assign dp_data_mecc4_int = que_wr_channel_mux ? ch1_dp_data_mecc4 : dp_data_mecc4;
assign dp_data_mecc5_int = que_wr_channel_mux ? ch1_dp_data_mecc5 : dp_data_mecc5;
assign dp_data_mecc6_int = que_wr_channel_mux ? ch1_dp_data_mecc6 : dp_data_mecc6;
assign dp_data_mecc7_int = que_wr_channel_mux ? ch1_dp_data_mecc7 : dp_data_mecc7;
assign dp_pioson_l2_data[3:0] = (que_mem_addr_d1[3:1] == 3'h0) ? dp_data_mecc0_int[3:0] :
(que_mem_addr_d1[3:1] == 3'h1) ? dp_data_mecc1_int[3:0] :
(que_mem_addr_d1[3:1] == 3'h2) ? dp_data_mecc2_int[3:0] :
(que_mem_addr_d1[3:1] == 3'h3) ? dp_data_mecc3_int[3:0] :
(que_mem_addr_d1[3:1] == 3'h4) ? dp_data_mecc4_int[3:0] :
(que_mem_addr_d1[3:1] == 3'h5) ? dp_data_mecc5_int[3:0] :
(que_mem_addr_d1[3:1] == 3'h6) ? dp_data_mecc6_int[3:0] :
(que_mem_addr_d1[3:1] == 3'h7) ? dp_data_mecc7_int[3:0] : 4'h0;
dff_ns #(5) ff_mem_addr(
.din(que_mem_addr[4:0]),
.q({que_dp_wr_data_vld, que_mem_addr_d1[3:0]}),
.clk(clk));
assign dp_pioson_l2_chunk = ( (que_bypass_scrb_data & dp_scrb_wr_data_en_cnt == 1'b0) |
(~dp_scrb_data1_en & dp_scrb_wr_data_en_cnt == 1'b1) ) ? 2'h0 :
(que_mem_addr_d1[0] == 1'b0) ? dp_pioson_l2_data[1:0] :
dp_pioson_l2_data[3:2];
// counter to keep track of scrb write back data bypass enable
wire dp_scrb_wr_data_en = que_bypass_scrb_data | dp_scrb_wr_data_en_cnt;
assign dp_scrb_wr_data_en_cnt_in = dp_scrb_wr_data_en_cnt + 1'b1;
dffrle_ns #(1) ff_wr_data_en(
.din(dp_scrb_wr_data_en_cnt_in),
.q(dp_scrb_wr_data_en_cnt),
.rst_l(rst_l),
.en(dp_scrb_wr_data_en),
.clk(clk));
assign dp_mux_data[255:0] =
~que_channel_disabled & (que_bypass_scrb_data & dp_scrb_wr_data_en_cnt == 1'b0) ?
dp_scrb_data0[255:0] :
~que_channel_disabled & (~dp_scrb_data1_en & dp_scrb_wr_data_en_cnt == 1'b1) ?
dp_scrb_data1[255:0] :
~que_channel_disabled & ~que_dp_wr_data_vld ? que_mem_data[255:0] :
que_wr_channel_mux ? ch1_que_mem_data : 256'h0;
dram_ecc_gen ecc_gen_h(
// Outputs
.ecc(dp_mux_ecc_pre_xor_hi),
// Intputs
.data({dp_mux_data[191:128], dp_mux_data[255:192]}));
dram_ecc_gen ecc_gen_l(
// Outputs
.ecc(dp_mux_ecc_pre_xor_lo),
// Intputs
.data({dp_mux_data[63:0], dp_mux_data[127:64]}));
// Need to XOR ecc generated with address parity
// Save the parity till the memory addr is not changed or a new store happens
// que_st_cmd_addr_parity is one cycle ahead of data for stores
dffe_ns #(1) ff_st_addr_parity(
.din(que_st_cmd_addr_parity),
.q(dp_mem_st_cmd_addr_parity),
.en(~que_mem_addr[0]),
.clk(clk));
// Save the parity till two cycles for scrub as the data is written back to back to memory
dff_ns #(1) ff_st_addr_parity_d1(
.din(que_st_cmd_addr_parity),
.q(que_scrb_cmd_addr_parity_d1),
.clk(clk));
dff_ns #(1) ff_st_addr_parity_d2(
.din(que_scrb_cmd_addr_parity_d1),
.q(que_scrb_cmd_addr_parity_d2),
.clk(clk));
wire dp_st_cmd_addr_parity = que_bypass_scrb_data ? que_scrb_cmd_addr_parity_d1 :
(~dp_scrb_data1_en & dp_scrb_wr_data_en_cnt == 1'b1) ? que_scrb_cmd_addr_parity_d2 :
dp_mem_st_cmd_addr_parity;
assign dp_mux_ecc_hi = dp_mux_ecc_pre_xor_hi ^ {16{dp_st_cmd_addr_parity}};
assign dp_mux_ecc_lo = dp_mux_ecc_pre_xor_lo ^ {16{dp_st_cmd_addr_parity}};
assign ecch[15:0] = (que_bypass_scrb_data & dp_scrb_wr_data_en_cnt == 1'b0 & dp_scrb_ecc0[32]) ?
dp_scrb_ecc0[15:0] :
(~dp_scrb_data1_en & dp_scrb_wr_data_en_cnt == 1'b1 & dp_scrb_ecc1[32]) ?
dp_scrb_ecc1[15:0] : dp_mux_ecc_hi[15:0];
assign eccl[15:0] = (que_bypass_scrb_data & dp_scrb_wr_data_en_cnt == 1'b0 & dp_scrb_ecc0[33]) ?
dp_scrb_ecc0[31:16] :
(~dp_scrb_data1_en & dp_scrb_wr_data_en_cnt == 1'b1 & dp_scrb_ecc1[33]) ?
dp_scrb_ecc1[31:16] : dp_mux_ecc_lo[15:0];
// Generate 16 bit vector that injects error
wire [15:0] dp_err_inj_vec;
assign dp_err_inj_vec = {16{err_inj_reg}} & err_mask_reg[15:0];
assign dp_pad_data[287:0] = {dp_pioson_l2_chunk[1] ^ ecch[15] ^ (dp_err_inj_vec[15] & ~sshot_err_reg),
ecch[14:9] ^ (dp_err_inj_vec[14:9] & {6{~sshot_err_reg}}),
dp_pioson_l2_chunk[1] ^ ecch[8] ^ (dp_err_inj_vec[8] & ~sshot_err_reg),
ecch[7:5] ^ (dp_err_inj_vec[7:5] & {3{~sshot_err_reg}}),
dp_pioson_l2_chunk[1] ^ ecch[4] ^ (dp_err_inj_vec[4] & ~sshot_err_reg),
ecch[3:1] ^ (dp_err_inj_vec[3:1] & {3{~sshot_err_reg}}),
dp_pioson_l2_chunk[1] ^ ecch[0] ^ (dp_err_inj_vec[0] & ~sshot_err_reg),
dp_mux_data[191:128], dp_mux_data[255:192],
dp_pioson_l2_chunk[0] ^ eccl[15] ^ dp_err_inj_vec[15],
eccl[14:9] ^ dp_err_inj_vec[14:9],
dp_pioson_l2_chunk[0] ^ eccl[8] ^ dp_err_inj_vec[8],
eccl[7:5] ^ dp_err_inj_vec[7:5],
dp_pioson_l2_chunk[0] ^ eccl[4] ^ dp_err_inj_vec[4],
eccl[3:1] ^ dp_err_inj_vec[3:1],
dp_pioson_l2_chunk[0] ^ eccl[0] ^ dp_err_inj_vec[0],
dp_mux_data[63:0], dp_mux_data[127:64]};
dff_ns #(288) ff_wr_pad_data(
.din(dp_pad_data[287:0]),
.q(dp_wr_data_muxed_nibbles[287:0]),
.clk(clk));
// ecc[287:272]
assign dram_io_data_out[287:284] = dram_fail_over_mask[31] ? dp_wr_data_muxed_nibbles[271:268] : dp_wr_data_muxed_nibbles[287:284];
assign dram_io_data_out[283:280] = dram_fail_over_mask[32] ? dp_wr_data_muxed_nibbles[287:284] : dp_wr_data_muxed_nibbles[283:280];
assign dram_io_data_out[279:276] = dram_fail_over_mask[33] ? dp_wr_data_muxed_nibbles[283:280] : dp_wr_data_muxed_nibbles[279:276];
assign dram_io_data_out[275:272] = dram_fail_over_mask[34] ? dp_wr_data_muxed_nibbles[279:276] : dp_wr_data_muxed_nibbles[275:272];
// data[271:144]
assign dram_io_data_out[271:268] = dram_fail_over_mask[30] ? dp_wr_data_muxed_nibbles[267:264] : dp_wr_data_muxed_nibbles[271:268];
assign dram_io_data_out[267:264] = dram_fail_over_mask[29] ? dp_wr_data_muxed_nibbles[263:260] : dp_wr_data_muxed_nibbles[267:264];
assign dram_io_data_out[263:260] = dram_fail_over_mask[28] ? dp_wr_data_muxed_nibbles[259:256] : dp_wr_data_muxed_nibbles[263:260];
assign dram_io_data_out[259:256] = dram_fail_over_mask[27] ? dp_wr_data_muxed_nibbles[255:252] : dp_wr_data_muxed_nibbles[259:256];
assign dram_io_data_out[255:252] = dram_fail_over_mask[26] ? dp_wr_data_muxed_nibbles[251:248] : dp_wr_data_muxed_nibbles[255:252];
assign dram_io_data_out[251:248] = dram_fail_over_mask[25] ? dp_wr_data_muxed_nibbles[247:244] : dp_wr_data_muxed_nibbles[251:248];
assign dram_io_data_out[247:244] = dram_fail_over_mask[24] ? dp_wr_data_muxed_nibbles[243:240] : dp_wr_data_muxed_nibbles[247:244];
assign dram_io_data_out[243:240] = dram_fail_over_mask[23] ? dp_wr_data_muxed_nibbles[239:236] : dp_wr_data_muxed_nibbles[243:240];
assign dram_io_data_out[239:236] = dram_fail_over_mask[22] ? dp_wr_data_muxed_nibbles[235:232] : dp_wr_data_muxed_nibbles[239:236];
assign dram_io_data_out[235:232] = dram_fail_over_mask[21] ? dp_wr_data_muxed_nibbles[231:228] : dp_wr_data_muxed_nibbles[235:232];
assign dram_io_data_out[231:228] = dram_fail_over_mask[20] ? dp_wr_data_muxed_nibbles[227:224] : dp_wr_data_muxed_nibbles[231:228];
assign dram_io_data_out[227:224] = dram_fail_over_mask[19] ? dp_wr_data_muxed_nibbles[223:220] : dp_wr_data_muxed_nibbles[227:224];
assign dram_io_data_out[223:220] = dram_fail_over_mask[18] ? dp_wr_data_muxed_nibbles[219:216] : dp_wr_data_muxed_nibbles[223:220];
assign dram_io_data_out[219:216] = dram_fail_over_mask[17] ? dp_wr_data_muxed_nibbles[215:212] : dp_wr_data_muxed_nibbles[219:216];
assign dram_io_data_out[215:212] = dram_fail_over_mask[16] ? dp_wr_data_muxed_nibbles[211:208] : dp_wr_data_muxed_nibbles[215:212];
assign dram_io_data_out[211:208] = dram_fail_over_mask[15] ? dp_wr_data_muxed_nibbles[207:204] : dp_wr_data_muxed_nibbles[211:208];
assign dram_io_data_out[207:204] = dram_fail_over_mask[14] ? dp_wr_data_muxed_nibbles[203:200] : dp_wr_data_muxed_nibbles[207:204];
assign dram_io_data_out[203:200] = dram_fail_over_mask[13] ? dp_wr_data_muxed_nibbles[199:196] : dp_wr_data_muxed_nibbles[203:200];
assign dram_io_data_out[199:196] = dram_fail_over_mask[12] ? dp_wr_data_muxed_nibbles[195:192] : dp_wr_data_muxed_nibbles[199:196];
assign dram_io_data_out[195:192] = dram_fail_over_mask[11] ? dp_wr_data_muxed_nibbles[191:188] : dp_wr_data_muxed_nibbles[195:192];
assign dram_io_data_out[191:188] = dram_fail_over_mask[10] ? dp_wr_data_muxed_nibbles[187:184] : dp_wr_data_muxed_nibbles[191:188];
assign dram_io_data_out[187:184] = dram_fail_over_mask[9] ? dp_wr_data_muxed_nibbles[183:180] : dp_wr_data_muxed_nibbles[187:184];
assign dram_io_data_out[183:180] = dram_fail_over_mask[8] ? dp_wr_data_muxed_nibbles[179:176] : dp_wr_data_muxed_nibbles[183:180];
assign dram_io_data_out[179:176] = dram_fail_over_mask[7] ? dp_wr_data_muxed_nibbles[175:172] : dp_wr_data_muxed_nibbles[179:176];
assign dram_io_data_out[175:172] = dram_fail_over_mask[6] ? dp_wr_data_muxed_nibbles[171:168] : dp_wr_data_muxed_nibbles[175:172];
assign dram_io_data_out[171:168] = dram_fail_over_mask[5] ? dp_wr_data_muxed_nibbles[167:164] : dp_wr_data_muxed_nibbles[171:168];
assign dram_io_data_out[167:164] = dram_fail_over_mask[4] ? dp_wr_data_muxed_nibbles[163:160] : dp_wr_data_muxed_nibbles[167:164];
assign dram_io_data_out[163:160] = dram_fail_over_mask[3] ? dp_wr_data_muxed_nibbles[159:156] : dp_wr_data_muxed_nibbles[163:160];
assign dram_io_data_out[159:156] = dram_fail_over_mask[2] ? dp_wr_data_muxed_nibbles[155:152] : dp_wr_data_muxed_nibbles[159:156];
assign dram_io_data_out[155:152] = dram_fail_over_mask[1] ? dp_wr_data_muxed_nibbles[151:148] : dp_wr_data_muxed_nibbles[155:152];
assign dram_io_data_out[151:148] = dram_fail_over_mask[0] ? dp_wr_data_muxed_nibbles[147:144] : dp_wr_data_muxed_nibbles[151:148];
assign dram_io_data_out[147:144] = dp_wr_data_muxed_nibbles[147:144];
// ecc[143:128]
assign dram_io_data_out[143:140] = dram_fail_over_mask[31] ? dp_wr_data_muxed_nibbles[127:124] : dp_wr_data_muxed_nibbles[143:140];
assign dram_io_data_out[139:136] = dram_fail_over_mask[32] ? dp_wr_data_muxed_nibbles[143:140] : dp_wr_data_muxed_nibbles[139:136];
assign dram_io_data_out[135:132] = dram_fail_over_mask[33] ? dp_wr_data_muxed_nibbles[139:136] : dp_wr_data_muxed_nibbles[135:132];
assign dram_io_data_out[131:128] = dram_fail_over_mask[34] ? dp_wr_data_muxed_nibbles[135:132] : dp_wr_data_muxed_nibbles[131:128];
// data[127:0]
assign dram_io_data_out[127:124] = dram_fail_over_mask[30] ? dp_wr_data_muxed_nibbles[123:120] : dp_wr_data_muxed_nibbles[127:124];
assign dram_io_data_out[123:120] = dram_fail_over_mask[29] ? dp_wr_data_muxed_nibbles[119:116] : dp_wr_data_muxed_nibbles[123:120];
assign dram_io_data_out[119:116] = dram_fail_over_mask[28] ? dp_wr_data_muxed_nibbles[115:112] : dp_wr_data_muxed_nibbles[119:116];
assign dram_io_data_out[115:112] = dram_fail_over_mask[27] ? dp_wr_data_muxed_nibbles[111:108] : dp_wr_data_muxed_nibbles[115:112];
assign dram_io_data_out[111:108] = dram_fail_over_mask[26] ? dp_wr_data_muxed_nibbles[107:104] : dp_wr_data_muxed_nibbles[111:108];
assign dram_io_data_out[107:104] = dram_fail_over_mask[25] ? dp_wr_data_muxed_nibbles[103:100] : dp_wr_data_muxed_nibbles[107:104];
assign dram_io_data_out[103:100] = dram_fail_over_mask[24] ? dp_wr_data_muxed_nibbles[99:96] : dp_wr_data_muxed_nibbles[103:100];
assign dram_io_data_out[99:96] = dram_fail_over_mask[23] ? dp_wr_data_muxed_nibbles[95:92] : dp_wr_data_muxed_nibbles[99:96];
assign dram_io_data_out[95:92] = dram_fail_over_mask[22] ? dp_wr_data_muxed_nibbles[91:88] : dp_wr_data_muxed_nibbles[95:92];
assign dram_io_data_out[91:88] = dram_fail_over_mask[21] ? dp_wr_data_muxed_nibbles[87:84] : dp_wr_data_muxed_nibbles[91:88];
assign dram_io_data_out[87:84] = dram_fail_over_mask[20] ? dp_wr_data_muxed_nibbles[83:80] : dp_wr_data_muxed_nibbles[87:84];
assign dram_io_data_out[83:80] = dram_fail_over_mask[19] ? dp_wr_data_muxed_nibbles[79:76] : dp_wr_data_muxed_nibbles[83:80];
assign dram_io_data_out[79:76] = dram_fail_over_mask[18] ? dp_wr_data_muxed_nibbles[75:72] : dp_wr_data_muxed_nibbles[79:76];
assign dram_io_data_out[75:72] = dram_fail_over_mask[17] ? dp_wr_data_muxed_nibbles[71:68] : dp_wr_data_muxed_nibbles[75:72];
assign dram_io_data_out[71:68] = dram_fail_over_mask[16] ? dp_wr_data_muxed_nibbles[67:64] : dp_wr_data_muxed_nibbles[71:68];
assign dram_io_data_out[67:64] = dram_fail_over_mask[15] ? dp_wr_data_muxed_nibbles[63:60] : dp_wr_data_muxed_nibbles[67:64];
assign dram_io_data_out[63:60] = dram_fail_over_mask[14] ? dp_wr_data_muxed_nibbles[59:56] : dp_wr_data_muxed_nibbles[63:60];
assign dram_io_data_out[59:56] = dram_fail_over_mask[13] ? dp_wr_data_muxed_nibbles[55:52] : dp_wr_data_muxed_nibbles[59:56];
assign dram_io_data_out[55:52] = dram_fail_over_mask[12] ? dp_wr_data_muxed_nibbles[51:48] : dp_wr_data_muxed_nibbles[55:52];
assign dram_io_data_out[51:48] = dram_fail_over_mask[11] ? dp_wr_data_muxed_nibbles[47:44] : dp_wr_data_muxed_nibbles[51:48];
assign dram_io_data_out[47:44] = dram_fail_over_mask[10] ? dp_wr_data_muxed_nibbles[43:40] : dp_wr_data_muxed_nibbles[47:44];
assign dram_io_data_out[43:40] = dram_fail_over_mask[9] ? dp_wr_data_muxed_nibbles[39:36] : dp_wr_data_muxed_nibbles[43:40];
assign dram_io_data_out[39:36] = dram_fail_over_mask[8] ? dp_wr_data_muxed_nibbles[35:32] : dp_wr_data_muxed_nibbles[39:36];
assign dram_io_data_out[35:32] = dram_fail_over_mask[7] ? dp_wr_data_muxed_nibbles[31:28] : dp_wr_data_muxed_nibbles[35:32];
assign dram_io_data_out[31:28] = dram_fail_over_mask[6] ? dp_wr_data_muxed_nibbles[27:24] : dp_wr_data_muxed_nibbles[31:28];
assign dram_io_data_out[27:24] = dram_fail_over_mask[5] ? dp_wr_data_muxed_nibbles[23:20] : dp_wr_data_muxed_nibbles[27:24];
assign dram_io_data_out[23:20] = dram_fail_over_mask[4] ? dp_wr_data_muxed_nibbles[19:16] : dp_wr_data_muxed_nibbles[23:20];
assign dram_io_data_out[19:16] = dram_fail_over_mask[3] ? dp_wr_data_muxed_nibbles[15:12] : dp_wr_data_muxed_nibbles[19:16];
assign dram_io_data_out[15:12] = dram_fail_over_mask[2] ? dp_wr_data_muxed_nibbles[11:8] : dp_wr_data_muxed_nibbles[15:12];
assign dram_io_data_out[11:8] = dram_fail_over_mask[1] ? dp_wr_data_muxed_nibbles[7:4] : dp_wr_data_muxed_nibbles[11:8];
assign dram_io_data_out[7:4] = dram_fail_over_mask[0] ? dp_wr_data_muxed_nibbles[3:0] : dp_wr_data_muxed_nibbles[7:4];
assign dram_io_data_out[3:0] = dp_wr_data_muxed_nibbles[3:0];
// Counter to generate data valid for 2 consecutive cycles from one cycle pulse.
wire dp_data_vld_cnt_in;
wire dp_data_vld_cnt;
wire dp_data_valid_in;
assign dp_data_vld_cnt_in = dp_data_vld_cnt + 1'b1;
assign dp_data_valid_in = io_dram_data_valid | (|dp_data_vld_cnt);
dffrle_ns #(1) ff_data_valid_cnt(
.din(dp_data_vld_cnt_in),
.q(dp_data_vld_cnt),
.rst_l(rst_l),
.en(dp_data_valid_in),
.clk(clk));
dffrl_ns #(1) ff_l2_data_valid(
.din(dp_data_valid_in),
.q(dp_data_valid),
.rst_l(rst_l),
.clk(clk));
// Forwarding data from pad to L2 cpu clk domain
// Before that we have implement the reverse of fail over mode mux we introduced.
wire [255:0] dp_rd_data_muxed_nibbles;
wire [31:0] dp_rd_ecc_muxed_nibbles;
// ecc[31:16]
assign dp_rd_ecc_muxed_nibbles[31:28] = dram_fail_over_mask[32] ? io_dram_ecc_in[27:24] : io_dram_ecc_in[31:28];
assign dp_rd_ecc_muxed_nibbles[27:24] = dram_fail_over_mask[33] ? io_dram_ecc_in[23:20] : io_dram_ecc_in[27:24];
assign dp_rd_ecc_muxed_nibbles[23:20] = dram_fail_over_mask[34] ? io_dram_ecc_in[19:16] : io_dram_ecc_in[23:20];
assign dp_rd_ecc_muxed_nibbles[19:16] = io_dram_ecc_in[19:16];
// data[255:128]
assign dp_rd_data_muxed_nibbles[255:252] = dram_fail_over_mask[31] ? io_dram_ecc_in[31:28] : io_dram_data_in[255:252];
assign dp_rd_data_muxed_nibbles[251:248] = dram_fail_over_mask[30] ? io_dram_data_in[255:252] : io_dram_data_in[251:248];
assign dp_rd_data_muxed_nibbles[247:244] = dram_fail_over_mask[29] ? io_dram_data_in[251:248] : io_dram_data_in[247:244];
assign dp_rd_data_muxed_nibbles[243:240] = dram_fail_over_mask[28] ? io_dram_data_in[247:244] : io_dram_data_in[243:240];
assign dp_rd_data_muxed_nibbles[239:236] = dram_fail_over_mask[27] ? io_dram_data_in[243:240] : io_dram_data_in[239:236];
assign dp_rd_data_muxed_nibbles[235:232] = dram_fail_over_mask[26] ? io_dram_data_in[239:236] : io_dram_data_in[235:232];
assign dp_rd_data_muxed_nibbles[231:228] = dram_fail_over_mask[25] ? io_dram_data_in[235:232] : io_dram_data_in[231:228];
assign dp_rd_data_muxed_nibbles[227:224] = dram_fail_over_mask[24] ? io_dram_data_in[231:228] : io_dram_data_in[227:224];
assign dp_rd_data_muxed_nibbles[223:220] = dram_fail_over_mask[23] ? io_dram_data_in[227:224] : io_dram_data_in[223:220];
assign dp_rd_data_muxed_nibbles[219:216] = dram_fail_over_mask[22] ? io_dram_data_in[223:220] : io_dram_data_in[219:216];
assign dp_rd_data_muxed_nibbles[215:212] = dram_fail_over_mask[21] ? io_dram_data_in[219:216] : io_dram_data_in[215:212];
assign dp_rd_data_muxed_nibbles[211:208] = dram_fail_over_mask[20] ? io_dram_data_in[215:212] : io_dram_data_in[211:208];
assign dp_rd_data_muxed_nibbles[207:204] = dram_fail_over_mask[19] ? io_dram_data_in[211:208] : io_dram_data_in[207:204];
assign dp_rd_data_muxed_nibbles[203:200] = dram_fail_over_mask[18] ? io_dram_data_in[207:204] : io_dram_data_in[203:200];
assign dp_rd_data_muxed_nibbles[199:196] = dram_fail_over_mask[17] ? io_dram_data_in[203:200] : io_dram_data_in[199:196];
assign dp_rd_data_muxed_nibbles[195:192] = dram_fail_over_mask[16] ? io_dram_data_in[199:196] : io_dram_data_in[195:192];
assign dp_rd_data_muxed_nibbles[191:188] = dram_fail_over_mask[15] ? io_dram_data_in[195:192] : io_dram_data_in[191:188];
assign dp_rd_data_muxed_nibbles[187:184] = dram_fail_over_mask[14] ? io_dram_data_in[191:188] : io_dram_data_in[187:184];
assign dp_rd_data_muxed_nibbles[183:180] = dram_fail_over_mask[13] ? io_dram_data_in[187:184] : io_dram_data_in[183:180];
assign dp_rd_data_muxed_nibbles[179:176] = dram_fail_over_mask[12] ? io_dram_data_in[183:180] : io_dram_data_in[179:176];
assign dp_rd_data_muxed_nibbles[175:172] = dram_fail_over_mask[11] ? io_dram_data_in[179:176] : io_dram_data_in[175:172];
assign dp_rd_data_muxed_nibbles[171:168] = dram_fail_over_mask[10] ? io_dram_data_in[175:172] : io_dram_data_in[171:168];
assign dp_rd_data_muxed_nibbles[167:164] = dram_fail_over_mask[9] ? io_dram_data_in[171:168] : io_dram_data_in[167:164];
assign dp_rd_data_muxed_nibbles[163:160] = dram_fail_over_mask[8] ? io_dram_data_in[167:164] : io_dram_data_in[163:160];
assign dp_rd_data_muxed_nibbles[159:156] = dram_fail_over_mask[7] ? io_dram_data_in[163:160] : io_dram_data_in[159:156];
assign dp_rd_data_muxed_nibbles[155:152] = dram_fail_over_mask[6] ? io_dram_data_in[159:156] : io_dram_data_in[155:152];
assign dp_rd_data_muxed_nibbles[151:148] = dram_fail_over_mask[5] ? io_dram_data_in[155:152] : io_dram_data_in[151:148];
assign dp_rd_data_muxed_nibbles[147:144] = dram_fail_over_mask[4] ? io_dram_data_in[151:148] : io_dram_data_in[147:144];
assign dp_rd_data_muxed_nibbles[143:140] = dram_fail_over_mask[3] ? io_dram_data_in[147:144] : io_dram_data_in[143:140];
assign dp_rd_data_muxed_nibbles[139:136] = dram_fail_over_mask[2] ? io_dram_data_in[143:140] : io_dram_data_in[139:136];
assign dp_rd_data_muxed_nibbles[135:132] = dram_fail_over_mask[1] ? io_dram_data_in[139:136] : io_dram_data_in[135:132];
assign dp_rd_data_muxed_nibbles[131:128] = dram_fail_over_mask[0] ? io_dram_data_in[135:132] : io_dram_data_in[131:128];
// ecc[15:0]
assign dp_rd_ecc_muxed_nibbles[15:12] = dram_fail_over_mask[32] ? io_dram_ecc_in[11:8] : io_dram_ecc_in[15:12];
assign dp_rd_ecc_muxed_nibbles[11:8] = dram_fail_over_mask[33] ? io_dram_ecc_in[7:4] : io_dram_ecc_in[11:8];
assign dp_rd_ecc_muxed_nibbles[7:4] = dram_fail_over_mask[34] ? io_dram_ecc_in[3:0] : io_dram_ecc_in[7:4];
assign dp_rd_ecc_muxed_nibbles[3:0] = io_dram_ecc_in[3:0];
// data[127:0]
assign dp_rd_data_muxed_nibbles[127:124] = dram_fail_over_mask[31] ? io_dram_ecc_in[15:12] : io_dram_data_in[127:124];
assign dp_rd_data_muxed_nibbles[123:120] = dram_fail_over_mask[30] ? io_dram_data_in[127:124] : io_dram_data_in[123:120];
assign dp_rd_data_muxed_nibbles[119:116] = dram_fail_over_mask[29] ? io_dram_data_in[123:120] : io_dram_data_in[119:116];
assign dp_rd_data_muxed_nibbles[115:112] = dram_fail_over_mask[28] ? io_dram_data_in[119:116] : io_dram_data_in[115:112];
assign dp_rd_data_muxed_nibbles[111:108] = dram_fail_over_mask[27] ? io_dram_data_in[115:112] : io_dram_data_in[111:108];
assign dp_rd_data_muxed_nibbles[107:104] = dram_fail_over_mask[26] ? io_dram_data_in[111:108] : io_dram_data_in[107:104];
assign dp_rd_data_muxed_nibbles[103:100] = dram_fail_over_mask[25] ? io_dram_data_in[107:104] : io_dram_data_in[103:100];
assign dp_rd_data_muxed_nibbles[99:96] = dram_fail_over_mask[24] ? io_dram_data_in[103:100] : io_dram_data_in[99:96];
assign dp_rd_data_muxed_nibbles[95:92] = dram_fail_over_mask[23] ? io_dram_data_in[99:96] : io_dram_data_in[95:92];
assign dp_rd_data_muxed_nibbles[91:88] = dram_fail_over_mask[22] ? io_dram_data_in[95:92] : io_dram_data_in[91:88];
assign dp_rd_data_muxed_nibbles[87:84] = dram_fail_over_mask[21] ? io_dram_data_in[91:88] : io_dram_data_in[87:84];
assign dp_rd_data_muxed_nibbles[83:80] = dram_fail_over_mask[20] ? io_dram_data_in[87:84] : io_dram_data_in[83:80];
assign dp_rd_data_muxed_nibbles[79:76] = dram_fail_over_mask[19] ? io_dram_data_in[83:80] : io_dram_data_in[79:76];
assign dp_rd_data_muxed_nibbles[75:72] = dram_fail_over_mask[18] ? io_dram_data_in[79:76] : io_dram_data_in[75:72];
assign dp_rd_data_muxed_nibbles[71:68] = dram_fail_over_mask[17] ? io_dram_data_in[75:72] : io_dram_data_in[71:68];
assign dp_rd_data_muxed_nibbles[67:64] = dram_fail_over_mask[16] ? io_dram_data_in[71:68] : io_dram_data_in[67:64];
assign dp_rd_data_muxed_nibbles[63:60] = dram_fail_over_mask[15] ? io_dram_data_in[67:64] : io_dram_data_in[63:60];
assign dp_rd_data_muxed_nibbles[59:56] = dram_fail_over_mask[14] ? io_dram_data_in[63:60] : io_dram_data_in[59:56];
assign dp_rd_data_muxed_nibbles[55:52] = dram_fail_over_mask[13] ? io_dram_data_in[59:56] : io_dram_data_in[55:52];
assign dp_rd_data_muxed_nibbles[51:48] = dram_fail_over_mask[12] ? io_dram_data_in[55:52] : io_dram_data_in[51:48];
assign dp_rd_data_muxed_nibbles[47:44] = dram_fail_over_mask[11] ? io_dram_data_in[51:48] : io_dram_data_in[47:44];
assign dp_rd_data_muxed_nibbles[43:40] = dram_fail_over_mask[10] ? io_dram_data_in[47:44] : io_dram_data_in[43:40];
assign dp_rd_data_muxed_nibbles[39:36] = dram_fail_over_mask[9] ? io_dram_data_in[43:40] : io_dram_data_in[39:36];
assign dp_rd_data_muxed_nibbles[35:32] = dram_fail_over_mask[8] ? io_dram_data_in[39:36] : io_dram_data_in[35:32];
assign dp_rd_data_muxed_nibbles[31:28] = dram_fail_over_mask[7] ? io_dram_data_in[35:32] : io_dram_data_in[31:28];
assign dp_rd_data_muxed_nibbles[27:24] = dram_fail_over_mask[6] ? io_dram_data_in[31:28] : io_dram_data_in[27:24];
assign dp_rd_data_muxed_nibbles[23:20] = dram_fail_over_mask[5] ? io_dram_data_in[27:24] : io_dram_data_in[23:20];
assign dp_rd_data_muxed_nibbles[19:16] = dram_fail_over_mask[4] ? io_dram_data_in[23:20] : io_dram_data_in[19:16];
assign dp_rd_data_muxed_nibbles[15:12] = dram_fail_over_mask[3] ? io_dram_data_in[19:16] : io_dram_data_in[15:12];
assign dp_rd_data_muxed_nibbles[11:8] = dram_fail_over_mask[2] ? io_dram_data_in[15:12] : io_dram_data_in[11:8];
assign dp_rd_data_muxed_nibbles[7:4] = dram_fail_over_mask[1] ? io_dram_data_in[11:8] : io_dram_data_in[7:4];
assign dp_rd_data_muxed_nibbles[3:0] = dram_fail_over_mask[0] ? io_dram_data_in[7:4] : io_dram_data_in[3:0];
dff_ns #(288) ff_l2_data(
.din({dp_rd_ecc_muxed_nibbles[31:0], dp_rd_data_muxed_nibbles[255:0]}),
.q({dp_ecc_in[31:0], dp_data_in[255:0]}),
.clk(clk));
endmodule
|
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main #(
parameter v98ea37 = 240000,
parameter v315560 = 25,
parameter v0f02ae = -2
) (
input v68e749,
input vclk,
output [7:0] vb5f8d6,
output vbad421
);
localparam p3 = v98ea37;
localparam p7 = v0f02ae;
localparam p10 = v315560;
wire [0:7] w0;
wire w1;
wire w2;
wire [0:2] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w8;
wire w9;
wire [0:7] w11;
wire [0:7] w12;
wire [0:7] w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
wire w19;
wire w20;
wire w21;
wire w22;
wire w23;
wire w24;
wire w25;
wire w26;
wire [0:7] w27;
wire w28;
wire w29;
wire [0:7] w30;
wire [0:7] w31;
wire w32;
wire w33;
wire w34;
wire w35;
wire w36;
wire w37;
wire [0:7] w38;
wire [0:7] w39;
wire [0:7] w40;
wire [0:7] w41;
assign vb5f8d6 = w0;
assign w2 = v68e749;
assign vbad421 = w20;
assign w21 = vclk;
assign w22 = vclk;
assign w23 = vclk;
assign w24 = vclk;
assign w25 = vclk;
assign w26 = vclk;
assign w22 = w21;
assign w23 = w21;
assign w23 = w22;
assign w24 = w21;
assign w24 = w22;
assign w24 = w23;
assign w25 = w21;
assign w25 = w22;
assign w25 = w23;
assign w25 = w24;
assign w26 = w21;
assign w26 = w22;
assign w26 = w23;
assign w26 = w24;
assign w26 = w25;
assign w29 = w28;
assign w30 = w5;
assign w31 = w5;
assign w31 = w30;
assign w32 = w17;
assign w34 = w33;
assign w35 = w33;
assign w35 = w34;
assign w36 = w33;
assign w36 = w34;
assign w36 = w35;
assign w39 = w6;
assign w40 = w6;
assign w40 = w39;
v75c864 v645c43 (
.va8064a(w0),
.v5a2634(w1),
.v1336f1(w4)
);
vfebcfe vd146ce (
.v9fb85f(w1)
);
vbce541 #(
.va04f5d(p3)
) v47bd3e (
.v4642b6(w16),
.v6dda25(w21)
);
v857d2e v449769 (
.v19a59f(w5),
.v6dda25(w22),
.vccca56(w29),
.vec26ff(w41)
);
v9c1f69 v71f96f (
.v1045ee(w4),
.vcc8c7c(w30)
);
vcb23aa ve224a5 (
.veb2f59(w5),
.v39966a(w40),
.v62bf25(w41)
);
v89d234 v55be45 (
.vb1c024(w6),
.v39f831(w8),
.vf892a0(w9),
.v41eb95(w23)
);
vcb23aa vec74fb (
.veb2f59(w6),
.v39966a(w27),
.v62bf25(w38)
);
vffc517 #(
.vc5c8ea(p7)
) v30a629 (
.va0aeac(w12)
);
v1bbb5b v64a91b (
.v9d2a6a(w8),
.v2a1cbe(w11),
.v2d3366(w35),
.v9d7ae8(w38)
);
v873425 v8ee855 (
.vcbab45(w9),
.v0e28cb(w28),
.v3ca442(w36)
);
vffc517 #(
.vc5c8ea(p10)
) v76838a (
.va0aeac(w11)
);
v89d234 v7825c7 (
.v39f831(w12),
.v41eb95(w24),
.vb1c024(w27),
.vf892a0(w33)
);
v78be07 va08ca8 (
.v2ce16c(w15),
.vcc8c7c(w39)
);
vb2762a vecb412 (
.v715730(w13),
.v4642b6(w14),
.vf191e6(w31)
);
vba518e vc58236 (
.v0e28cb(w14),
.v3ca442(w15),
.vcbab45(w37)
);
vba518e v50132d (
.v0e28cb(w16),
.vcbab45(w28),
.v3ca442(w32)
);
v4c1570 vf52c7c (
.v4642b6(w17),
.v6dda25(w25),
.v27dec4(w34),
.v92a149(w37)
);
v3676a0 v91794b (
.v0e28cb(w17),
.vcbab45(w18)
);
vba518e v496601 (
.v0e28cb(w18),
.v3ca442(w19),
.vcbab45(w33)
);
vda0861 vf481a4 (
.vffb58f(w13)
);
vd30ca9 vf07e0d (
.v9fb85f(w20)
);
v9791ec v66a109 (
.vd9601b(w2),
.v64879c(w19),
.vfde3d7(w26)
);
endmodule
//---- Top entity
module v75c864 (
input v5a2634,
input [2:0] v1336f1,
output [7:0] va8064a
);
wire w0;
wire [0:7] w1;
wire [0:2] w2;
assign w0 = v5a2634;
assign va8064a = w1;
assign w2 = v1336f1;
v75c864_v45bd49 v45bd49 (
.i(w0),
.o(w1),
.sel(w2)
);
endmodule
//---------------------------------------------------
//-- Demux-3-8
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Demultiplexor de 1 bit, de 3 a 8 (salida de bus)
//---------------------------------------------------
module v75c864_v45bd49 (
input i,
input [2:0] sel,
output [7:0] o
);
assign o = i << sel;
endmodule
//---- Top entity
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 1
//---------------------------------------------------
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule
//---- Top entity
module vbce541 #(
parameter va04f5d = 16777216
) (
input v6dda25,
output v4642b6
);
localparam p1 = va04f5d;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire w4;
wire w5;
assign v4642b6 = w0;
assign w5 = v6dda25;
assign w4 = w0;
vef98b5 #(
.vc5c8ea(p1)
) v4016e8 (
.ve70c2d(w3)
);
vd84ae0 v45b714 (
.v4642b6(w0),
.va89056(w2),
.v06bdfb(w3)
);
v97d607 v2299cf (
.v9e1c43(w2),
.ve556f1(w4),
.v6dda25(w5)
);
endmodule
//---------------------------------------------------
//-- sysclk_divN_24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- sysclk_divN_24bits: Generate a signal from the division of the system clock by N. (24-bits precision) (N = 2,3,4,..,0x1000000))
//---------------------------------------------------
//---- Top entity
module vef98b5 #(
parameter vc5c8ea = 1
) (
output [23:0] ve70c2d
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign ve70c2d = w1;
vef98b5_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-k-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits k-1 constant (Input values: 1,2,...,h1000000). It returns the value input by the user minus 1. Outputs: 0,1,2,...,FFFFFF
//---------------------------------------------------
module vef98b5_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE-1;
endmodule
//---- Top entity
module vd84ae0 (
input [23:0] v06bdfb,
input [23:0] va89056,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:23] w4;
wire [0:23] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire [0:7] w9;
wire [0:7] w10;
wire [0:7] w11;
assign v4642b6 = w0;
assign w4 = v06bdfb;
assign w5 = va89056;
vb2762a vb6832a (
.v4642b6(w1),
.v715730(w8),
.vf191e6(w11)
);
vb2762a v302658 (
.v4642b6(w2),
.v715730(w7),
.vf191e6(w10)
);
vae245c v9196c7 (
.vcbab45(w0),
.v3ca442(w1),
.v0e28cb(w2),
.v033bf6(w3)
);
v6fef69 vb1e577 (
.v9804b7(w5),
.vd83cb2(w9),
.v243fb2(w10),
.va2a3a1(w11)
);
v6fef69 v62b64f (
.v9804b7(w4),
.vd83cb2(w6),
.v243fb2(w7),
.va2a3a1(w8)
);
vb2762a v9a65c6 (
.v4642b6(w3),
.v715730(w6),
.vf191e6(w9)
);
endmodule
//---------------------------------------------------
//-- comp2-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-24bit: Comparator of two 24-bit numbers
//---------------------------------------------------
//---- Top entity
module vb2762a (
input [7:0] v715730,
input [7:0] vf191e6,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w3 = v715730;
assign w4 = vf191e6;
v438230 v577a36 (
.v4642b6(w2),
.v693354(w6),
.v5369cd(w8)
);
vba518e v707c6e (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w2)
);
v6bdcd9 v921a9f (
.vcc8c7c(w4),
.v651522(w7),
.v2cc41f(w8)
);
v6bdcd9 v8cfa4d (
.vcc8c7c(w3),
.v651522(w5),
.v2cc41f(w6)
);
v438230 vfc1765 (
.v4642b6(w1),
.v693354(w5),
.v5369cd(w7)
);
endmodule
//---------------------------------------------------
//-- comp2-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-8bit: Comparator of two 8-bit numbers
//---------------------------------------------------
//---- Top entity
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15b v09a5a5 (
.v4642b6(w3),
.v27dec4(w12),
.v6848e9(w14)
);
v23b15b vc1b29d (
.v4642b6(w4),
.v27dec4(w11),
.v6848e9(w13)
);
v23b15b vcd27ce (
.v4642b6(w5),
.v27dec4(w9),
.v6848e9(w10)
);
vc4f23a vea9c80 (
.v985fcb(w1),
.v4f1fd3(w7),
.vda577d(w9),
.v3f8943(w11),
.v64d863(w12)
);
vc4f23a va7dcdc (
.v985fcb(w2),
.v4f1fd3(w8),
.vda577d(w10),
.v3f8943(w13),
.v64d863(w14)
);
v23b15b va0849c (
.v4642b6(w6),
.v27dec4(w7),
.v6848e9(w8)
);
veffd42 v6e3e65 (
.vcbab45(w0),
.v3ca442(w3),
.v0e28cb(w4),
.v033bf6(w5),
.v9eb652(w6)
);
endmodule
//---------------------------------------------------
//-- comp2-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-4bit: Comparator of two 4-bit numbers
//---------------------------------------------------
//---- Top entity
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule
//---------------------------------------------------
//-- comp2-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-1bit: Comparator of two 1-bit numbers
//---------------------------------------------------
//---- Top entity
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- XOR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- XOR gate: two bits input xor gate
//---------------------------------------------------
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
//---- Top entity
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.i(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Split-all: Split the 4-bits bus into its wires
//---------------------------------------------------
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0e28cb(w3),
.vcbab45(w6)
);
vba518e vdcc53d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w5)
);
vba518e v17ac22 (
.vcbab45(w4),
.v0e28cb(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- AND4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- AND2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Two bits input And gate
//---------------------------------------------------
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule
//---- Top entity
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of the same size
//---------------------------------------------------
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module vae245c (
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v033bf6;
assign w1 = v0e28cb;
assign w2 = v3ca442;
assign vcbab45 = w4;
vba518e v19b5b0 (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w3)
);
vba518e vf3ef0f (
.v3ca442(w2),
.v0e28cb(w3),
.vcbab45(w4)
);
endmodule
//---------------------------------------------------
//-- AND3
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v6fef69 (
input [23:0] v9804b7,
output [7:0] vd83cb2,
output [7:0] v243fb2,
output [7:0] va2a3a1
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:23] w3;
assign v243fb2 = w0;
assign vd83cb2 = w1;
assign va2a3a1 = w2;
assign w3 = v9804b7;
v6fef69_v9a2a06 v9a2a06 (
.o1(w0),
.o2(w1),
.o0(w2),
.i(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-one-third: Split the 24-bits bus into three buses of the same size
//---------------------------------------------------
module v6fef69_v9a2a06 (
input [23:0] i,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v97d607 (
input v6dda25,
input ve556f1,
output [23:0] v9e1c43,
output ve37344
);
wire w0;
wire [0:23] w1;
wire [0:23] w2;
wire w3;
wire [0:23] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign v9e1c43 = w4;
assign ve37344 = w5;
assign w4 = w1;
v5495b5 v5e4c9c (
.v782748(w0),
.vb02eea(w1),
.v15c6e6(w2),
.v6dda25(w3)
);
v9c4559 v62e821 (
.v005b83(w1),
.v53d485(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 24-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module v5495b5 (
input v6dda25,
input v782748,
input [23:0] v15c6e6,
output [23:0] vb02eea
);
wire [0:23] w0;
wire [0:23] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
assign vb02eea = w0;
assign w1 = v15c6e6;
assign w8 = v6dda25;
assign w9 = v6dda25;
assign w10 = v6dda25;
assign w11 = v782748;
assign w12 = v782748;
assign w13 = v782748;
assign w9 = w8;
assign w10 = w8;
assign w10 = w9;
assign w12 = w11;
assign w13 = w11;
assign w13 = w12;
v6fef69 vad6f1d (
.v9804b7(w1),
.va2a3a1(w5),
.v243fb2(w6),
.vd83cb2(w7)
);
v33e50d vba7365 (
.v6d326e(w0),
.v77c6e9(w2),
.vf7d213(w3),
.vba04ee(w4)
);
vcf4344 v13ddeb (
.vc1f0d2(w2),
.vd85d4e(w5),
.v6dda25(w10),
.v782748(w13)
);
vcf4344 v08e1bd (
.vc1f0d2(w3),
.vd85d4e(w6),
.v6dda25(w9),
.v782748(w12)
);
vcf4344 v5c3b0f (
.vc1f0d2(w4),
.vd85d4e(w7),
.v6dda25(w8),
.v782748(w11)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x24
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x24: 24 D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v33e50d (
input [7:0] vba04ee,
input [7:0] vf7d213,
input [7:0] v77c6e9,
output [23:0] v6d326e
);
wire [0:23] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
assign v6d326e = w0;
assign w1 = vf7d213;
assign w2 = v77c6e9;
assign w3 = vba04ee;
v33e50d_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2),
.i2(w3)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-one-third
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-one-third: Join the three buses into an 24-bits Bus
//---------------------------------------------------
module v33e50d_v9a2a06 (
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [23:0] o
);
assign o = {i2, i1, i0};
endmodule
//---- Top entity
module vcf4344 (
input v6dda25,
input v782748,
input [7:0] vd85d4e,
output [7:0] vc1f0d2
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w2 = vd85d4e;
assign vc1f0d2 = w3;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = v782748;
assign w9 = v782748;
assign w7 = w6;
assign w9 = w8;
v5c75f6 vbdef88 (
.v50034e(w0),
.v4de61b(w1),
.v6dda25(w7),
.v782748(w9)
);
v6bdcd9 vc95779 (
.v2cc41f(w1),
.vcc8c7c(w2),
.v651522(w4)
);
vafb28f v618315 (
.v3c88fc(w0),
.va9ac17(w3),
.v515fe7(w5)
);
v5c75f6 v6188f9 (
.v4de61b(w4),
.v50034e(w5),
.v6dda25(w6),
.v782748(w8)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x08: Eight D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
assign v50034e = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
vc4f23a v4b1225 (
.v3f8943(w2),
.v64d863(w3),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v6491fd (
.v03aaf0(w0),
.vee8a83(w1),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v2be0f8 v10a04f (
.v4642b6(w0),
.vf354ee(w3),
.vd53b77(w13),
.v27dec4(w17)
);
v2be0f8 v7d9648 (
.v4642b6(w1),
.vf354ee(w2),
.vd53b77(w12),
.v27dec4(w16)
);
v2be0f8 v004b14 (
.vf354ee(w4),
.v4642b6(w5),
.vd53b77(w11),
.v27dec4(w15)
);
v2be0f8 v8aa818 (
.vf354ee(w8),
.v4642b6(w9),
.vd53b77(w10),
.v27dec4(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x04: Three D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.i2(w2),
.i3(w3),
.o(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Join-all: Join all the wires into a 4-bits Bus
//---------------------------------------------------
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),
.v0e28cb(w2)
);
vba518e vfe8158 (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v053dc2 #(
.v71e305(p5)
) vd104a4 (
.vf54559(w0),
.ve8318d(w4),
.va4102a(w6)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0
//---------------------------------------------------
//---- Top entity
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- DFF
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- D Flip-flop (verilog implementation)
//---------------------------------------------------
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule
//---- Top entity
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Join-half: Join the two same halves into an 8-bits Bus
//---------------------------------------------------
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v9c4559 #(
parameter v6c5139 = 1
) (
input [23:0] v005b83,
output v4642b6,
output [23:0] v53d485
);
localparam p1 = v6c5139;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
assign v4642b6 = w0;
assign w2 = v005b83;
assign v53d485 = w3;
v44c099 #(
.vd73390(p1)
) v8c0045 (
.v4642b6(w0),
.vd90f46(w2),
.v8826c0(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-24bit: Increment a 24-bits number by one
//---------------------------------------------------
//---- Top entity
module v44c099 #(
parameter vd73390 = 0
) (
input [23:0] vd90f46,
output v4642b6,
output [23:0] v8826c0
);
localparam p1 = vd73390;
wire w0;
wire [0:23] w2;
wire [0:23] w3;
wire [0:23] w4;
assign v4642b6 = w0;
assign v8826c0 = w2;
assign w3 = vd90f46;
v4c802f #(
.vc5c8ea(p1)
) ve78914 (
.v8513f7(w4)
);
v91404d v19ed8b (
.v4642b6(w0),
.vb5c06c(w2),
.v7959e8(w3),
.vb5a2f2(w4)
);
endmodule
//---------------------------------------------------
//-- AdderK-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-24bit: Adder of 24-bit operand and 24-bit constant
//---------------------------------------------------
//---- Top entity
module v4c802f #(
parameter vc5c8ea = 0
) (
output [23:0] v8513f7
);
localparam p0 = vc5c8ea;
wire [0:23] w1;
assign v8513f7 = w1;
v4c802f_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 24-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 24-bits generic constant
//---------------------------------------------------
module v4c802f_v465065 #(
parameter VALUE = 0
) (
output [23:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v91404d (
input [23:0] vb5a2f2,
input [23:0] v7959e8,
output v4642b6,
output [23:0] vb5c06c
);
wire w0;
wire [0:7] w1;
wire [0:7] w2;
wire w3;
wire w4;
wire [0:15] w5;
wire [0:23] w6;
wire [0:15] w7;
wire [0:23] w8;
wire [0:15] w9;
wire [0:7] w10;
wire [0:23] w11;
wire [0:7] w12;
wire [0:7] w13;
wire [0:7] w14;
wire [0:7] w15;
wire [0:7] w16;
wire [0:7] w17;
assign v4642b6 = w4;
assign w6 = v7959e8;
assign w8 = vb5a2f2;
assign vb5c06c = w11;
vcb23aa v8e0bba (
.v4642b6(w0),
.v62bf25(w2),
.v39966a(w16),
.veb2f59(w17)
);
vc3c498 v917bbf (
.vb9cfc3(w0),
.veeaa8e(w1),
.v4642b6(w3),
.v45c6ee(w14),
.v20212e(w15)
);
v8cc49c v03c3e3 (
.vb334ae(w1),
.v2b8a97(w2),
.v14a530(w5)
);
vab13f0 v43653c (
.vb18564(w6),
.vf0a06e(w7),
.v5246f6(w17)
);
v306ca3 v177126 (
.v91b9c1(w7),
.vef5eee(w13),
.vd3ef3b(w15)
);
vab13f0 vf15711 (
.vb18564(w8),
.vf0a06e(w9),
.v5246f6(w16)
);
v306ca3 vf9ed57 (
.v91b9c1(w9),
.vef5eee(w12),
.vd3ef3b(w14)
);
vc3c498 vf0db78 (
.vb9cfc3(w3),
.v4642b6(w4),
.veeaa8e(w10),
.v45c6ee(w12),
.v20212e(w13)
);
va52e3b v67022b (
.vbf8961(w5),
.vf7d213(w10),
.v6d326e(w11)
);
endmodule
//---------------------------------------------------
//-- Adder-24bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-24bits: Adder of two operands of 24 bits
//---------------------------------------------------
//---- Top entity
module vcb23aa (
input [7:0] v39966a,
input [7:0] veb2f59,
output v4642b6,
output [7:0] v62bf25
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:7] w4;
wire w5;
wire w6;
wire [0:3] w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
assign w0 = veb2f59;
assign w1 = v39966a;
assign v62bf25 = w4;
assign v4642b6 = w5;
v6bdcd9 vd88c66 (
.vcc8c7c(w0),
.v651522(w9),
.v2cc41f(w10)
);
v6bdcd9 v26a0bb (
.vcc8c7c(w1),
.v651522(w7),
.v2cc41f(w8)
);
v25966b v9ea427 (
.v817794(w3),
.v4642b6(w6),
.v0550b6(w8),
.v24708e(w10)
);
vafb28f vc75346 (
.v515fe7(w2),
.v3c88fc(w3),
.va9ac17(w4)
);
va1ce30 v40c17f (
.v817794(w2),
.v4642b6(w5),
.vb9cfc3(w6),
.v0550b6(w7),
.v24708e(w9)
);
endmodule
//---------------------------------------------------
//-- Adder-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-8bits: Adder of two operands of 8 bits
//---------------------------------------------------
//---- Top entity
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
v1ea21d vdbe125 (
.v4642b6(w0),
.v8e8a67(w2),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w14),
.v82de4f(w17)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w12),
.v82de4f(w16)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w13),
.vda577d(w16),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w11),
.vda577d(w12),
.v3f8943(w14),
.v64d863(w15)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w11),
.v82de4f(w13)
);
endmodule
//---------------------------------------------------
//-- Adder-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-4bits: Adder of two operands of 4 bits
//---------------------------------------------------
//---- Top entity
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)
);
vd30ca9 v23ebb6 (
.v9fb85f(w2)
);
endmodule
//---------------------------------------------------
//-- Adder-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-1bit: Adder of two operands of 1 bit
//---------------------------------------------------
//---- Top entity
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w8 = v82de4f;
assign w9 = v82de4f;
assign w10 = v0ef266;
assign w11 = v0ef266;
assign w2 = w0;
assign w7 = w6;
assign w9 = w8;
assign w11 = w10;
vd12401 v2e3d9f (
.vcbab45(w0),
.v0e28cb(w7),
.v3ca442(w9)
);
vd12401 vb50462 (
.v0e28cb(w0),
.vcbab45(w1),
.v3ca442(w11)
);
vba518e v4882f4 (
.v3ca442(w2),
.vcbab45(w3),
.v0e28cb(w10)
);
vba518e v8fcf41 (
.vcbab45(w4),
.v0e28cb(w6),
.v3ca442(w8)
);
v873425 vc5b8b9 (
.v3ca442(w3),
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- AdderC-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-1bit: Adder of two operands of 1 bit plus the carry in
//---------------------------------------------------
//---- Top entity
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- OR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR2: Two bits input OR gate
//---------------------------------------------------
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule
//---- Top entity
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 0
//---------------------------------------------------
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule
//---- Top entity
module va1ce30 (
input [3:0] v0550b6,
input [3:0] v24708e,
input vb9cfc3,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
wire w19;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
assign w11 = vb9cfc3;
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w13),
.v82de4f(w17)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w14),
.vda577d(w17),
.v3f8943(w18),
.v64d863(w19)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w12),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w12),
.v82de4f(w14)
);
vad119b v3599be (
.v4642b6(w0),
.v8e8a67(w2),
.v0ef266(w11),
.v27dec4(w16),
.v82de4f(w19)
);
endmodule
//---------------------------------------------------
//-- AdderC-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-4bits: Adder of two operands of 4 bits and Carry in
//---------------------------------------------------
//---- Top entity
module vc3c498 (
input [7:0] v45c6ee,
input [7:0] v20212e,
input vb9cfc3,
output v4642b6,
output [7:0] veeaa8e
);
wire w0;
wire w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire [0:3] w9;
wire [0:3] w10;
wire [0:3] w11;
assign w1 = vb9cfc3;
assign w2 = v45c6ee;
assign w3 = v20212e;
assign veeaa8e = w4;
assign v4642b6 = w7;
v6bdcd9 v8d795a (
.vcc8c7c(w3),
.v651522(w10),
.v2cc41f(w11)
);
v6bdcd9 v23dbc5 (
.vcc8c7c(w2),
.v651522(w8),
.v2cc41f(w9)
);
vafb28f vef3a58 (
.va9ac17(w4),
.v3c88fc(w5),
.v515fe7(w6)
);
va1ce30 v0ff71a (
.v4642b6(w0),
.vb9cfc3(w1),
.v817794(w5),
.v0550b6(w9),
.v24708e(w11)
);
va1ce30 v12f94f (
.vb9cfc3(w0),
.v817794(w6),
.v4642b6(w7),
.v0550b6(w8),
.v24708e(w10)
);
endmodule
//---------------------------------------------------
//-- AdderC-8bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-8bits: Adder of two operands of 8 bits and Carry in
//---------------------------------------------------
//---- Top entity
module v8cc49c (
input [7:0] vb334ae,
input [7:0] v2b8a97,
output [15:0] v14a530
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign v14a530 = w0;
assign w1 = v2b8a97;
assign w2 = vb334ae;
v8cc49c_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Join-half: Join the two same halves into an 16-bits Bus
//---------------------------------------------------
module v8cc49c_v9a2a06 (
input [7:0] i1,
input [7:0] i0,
output [15:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vab13f0 (
input [23:0] vb18564,
output [15:0] vf0a06e,
output [7:0] v5246f6
);
wire [0:23] w0;
wire [0:15] w1;
wire [0:7] w2;
assign w0 = vb18564;
assign vf0a06e = w1;
assign v5246f6 = w2;
vab13f0_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Split-16-8
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Split-16-8: Split the 24-bits bus into two buses of 16 and 8 wires
//---------------------------------------------------
module vab13f0_v9a2a06 (
input [23:0] i,
output [15:0] o1,
output [7:0] o0
);
assign o1 = i[23:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v306ca3 (
input [15:0] v91b9c1,
output [7:0] vef5eee,
output [7:0] vd3ef3b
);
wire [0:15] w0;
wire [0:7] w1;
wire [0:7] w2;
assign w0 = v91b9c1;
assign vef5eee = w1;
assign vd3ef3b = w2;
v306ca3_v9a2a06 v9a2a06 (
.i(w0),
.o1(w1),
.o0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus16-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Split-half: Split the 16-bits bus into two buses of the same size
//---------------------------------------------------
module v306ca3_v9a2a06 (
input [15:0] i,
output [7:0] o1,
output [7:0] o0
);
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module va52e3b (
input [7:0] vf7d213,
input [15:0] vbf8961,
output [23:0] v6d326e
);
wire [0:15] w0;
wire [0:23] w1;
wire [0:7] w2;
assign w0 = vbf8961;
assign v6d326e = w1;
assign w2 = vf7d213;
va52e3b_v9a2a06 v9a2a06 (
.i0(w0),
.o(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus24-Join-8-16 CLONE
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus24-Join-8-16: Join the two buses into an 24-bits Bus
//---------------------------------------------------
module va52e3b_v9a2a06 (
input [7:0] i1,
input [15:0] i0,
output [23:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v857d2e (
input v6dda25,
input [7:0] vec26ff,
input vccca56,
output [7:0] v19a59f
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = vec26ff;
assign v19a59f = w1;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = vccca56;
assign w9 = vccca56;
assign w7 = w6;
assign w9 = w8;
v6bdcd9 v8e04d7 (
.vcc8c7c(w0),
.v651522(w2),
.v2cc41f(w4)
);
vafb28f vdbcc53 (
.va9ac17(w1),
.v515fe7(w3),
.v3c88fc(w5)
);
v370cd6 v732df5 (
.v2856c0(w2),
.v7891f9(w3),
.v6dda25(w6),
.vccca56(w8)
);
v370cd6 v21c6af (
.v2856c0(w4),
.v7891f9(w5),
.v6dda25(w7),
.vccca56(w9)
);
endmodule
//---------------------------------------------------
//-- Reg-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x08: 8-bits register
//---------------------------------------------------
//---- Top entity
module v370cd6 (
input v6dda25,
input [3:0] v2856c0,
input vccca56,
output [3:0] v7891f9
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v2856c0;
assign v7891f9 = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = vccca56;
assign w15 = vccca56;
assign w16 = vccca56;
assign w17 = vccca56;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
v22cb98 v1ba30c (
.v27dec4(w0),
.v4642b6(w2),
.ve4a668(w12),
.vd793aa(w16)
);
v22cb98 v38f79d (
.v27dec4(w1),
.v4642b6(w3),
.ve4a668(w13),
.vd793aa(w17)
);
v22cb98 v009467 (
.v27dec4(w4),
.v4642b6(w5),
.ve4a668(w11),
.vd793aa(w15)
);
vc4f23a vf2e2c0 (
.v3f8943(w0),
.v64d863(w1),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v947047 (
.vee8a83(w2),
.v03aaf0(w3),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v22cb98 v3a0f4c (
.v27dec4(w8),
.v4642b6(w9),
.ve4a668(w10),
.vd793aa(w14)
);
endmodule
//---------------------------------------------------
//-- Reg-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x04: 4-bits register
//---------------------------------------------------
//---- Top entity
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 (
.v030ad0(w0),
.vb192d0(w3),
.v27dec4(w4),
.v2d3366(w6)
);
v053dc2 #(
.v71e305(p1)
) v89c757 (
.vf54559(w0),
.va4102a(w2),
.ve8318d(w4)
);
endmodule
//---------------------------------------------------
//-- 1-bit-reg
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg: 1-Bit register
//---------------------------------------------------
//---- Top entity
module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule
//---------------------------------------------------
//-- MuxF-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels). Fippled version
//---------------------------------------------------
//---- Top entity
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w4)
);
vba518e v569873 (
.vcbab45(w1),
.v3ca442(w2),
.v0e28cb(w6)
);
v3676a0 v1f00ae (
.v0e28cb(w3),
.vcbab45(w5)
);
vba518e vc8527f (
.vcbab45(w4),
.v3ca442(w5),
.v0e28cb(w7)
);
endmodule
//---------------------------------------------------
//-- Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels)
//---------------------------------------------------
//---- Top entity
module v9c1f69 (
input [7:0] vcc8c7c,
output [2:0] v1045ee,
output [4:0] v52d10b
);
wire [0:7] w0;
wire [0:4] w1;
wire [0:2] w2;
assign w0 = vcc8c7c;
assign v52d10b = w1;
assign v1045ee = w2;
v9c1f69_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-3-5
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-3-5: Split the 8-bits bus into two buses of 3 and 5 wires
//---------------------------------------------------
module v9c1f69_v9a2a06 (
input [7:0] i,
output [2:0] o1,
output [4:0] o0
);
assign o1 = i[7:5];
assign o0 = i[4:0];
endmodule
//---- Top entity
module v89d234 #(
parameter v422d28 = 0
) (
input v41eb95,
input [7:0] v39f831,
input vf892a0,
output [7:0] vb1c024
);
localparam p0 = v422d28;
wire [0:7] w1;
wire [0:7] w2;
wire w3;
wire w4;
assign vb1c024 = w1;
assign w2 = v39f831;
assign w3 = vf892a0;
assign w4 = v41eb95;
v89d234_v9148cb #(
.INI(p0)
) v9148cb (
.q(w1),
.d(w2),
.load(w3),
.clk(w4)
);
endmodule
//---------------------------------------------------
//-- Registro
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Registro de 8 bits
//---------------------------------------------------
module v89d234_v9148cb #(
parameter INI = 0
) (
input clk,
input [7:0] d,
input load,
output [7:0] q
);
localparam N = 8;
reg [N-1:0] q = INI;
always @(posedge clk)
if (load)
q <= d;
endmodule
//---- Top entity
module vffc517 #(
parameter vc5c8ea = 0
) (
output [7:0] va0aeac
);
localparam p0 = vc5c8ea;
wire [0:7] w1;
assign va0aeac = w1;
vffc517_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 8-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 8-bits generic constant (0-255)
//---------------------------------------------------
module vffc517_v465065 #(
parameter VALUE = 0
) (
output [7:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v1bbb5b (
input [7:0] v2a1cbe,
input [7:0] v9d7ae8,
input v2d3366,
output [7:0] v9d2a6a
);
wire [0:3] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire [0:3] w10;
assign v9d2a6a = w1;
assign w2 = v2a1cbe;
assign w3 = v9d7ae8;
assign w8 = v2d3366;
assign w9 = v2d3366;
assign w9 = w8;
v952eda v54aed2 (
.v6833fd(w0),
.v54ac99(w7),
.v2d3366(w9),
.ve2616d(w10)
);
vafb28f v117a88 (
.v3c88fc(w0),
.va9ac17(w1),
.v515fe7(w4)
);
v6bdcd9 v9f32ae (
.vcc8c7c(w2),
.v651522(w5),
.v2cc41f(w7)
);
v6bdcd9 v9881c7 (
.vcc8c7c(w3),
.v651522(w6),
.v2cc41f(w10)
);
v952eda v34a43a (
.v6833fd(w4),
.v54ac99(w5),
.ve2616d(w6),
.v2d3366(w8)
);
endmodule
//---------------------------------------------------
//-- 8-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (8-bit channels)
//---------------------------------------------------
//---- Top entity
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign v6833fd = w3;
assign w5 = ve2616d;
assign w6 = v54ac99;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
vd0c4e5 v6d94c9 (
.v030ad0(w0),
.v2d3366(w11),
.v27dec4(w15),
.vb192d0(w17)
);
vd0c4e5 vebe465 (
.v030ad0(w1),
.v2d3366(w12),
.v27dec4(w16),
.vb192d0(w18)
);
vd0c4e5 ve1c21f (
.v030ad0(w2),
.v2d3366(w10),
.v27dec4(w13),
.vb192d0(w14)
);
v84f0a1 va44bdf (
.vee8a83(w0),
.v03aaf0(w1),
.vf8041d(w2),
.v11bca5(w3),
.vd84a57(w4)
);
vd0c4e5 v2ebff3 (
.v030ad0(w4),
.v27dec4(w7),
.vb192d0(w8),
.v2d3366(w9)
);
vc4f23a v3c3a57 (
.v985fcb(w5),
.v4f1fd3(w8),
.vda577d(w14),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a vd6d480 (
.v985fcb(w6),
.v4f1fd3(w7),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
endmodule
//---------------------------------------------------
//-- 4-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (4-bit channels)
//---------------------------------------------------
//---- Top entity
module v78be07 (
input [7:0] vcc8c7c,
output v2ce16c,
output [6:0] vdb77b6
);
wire [0:7] w0;
wire [0:6] w1;
wire w2;
assign w0 = vcc8c7c;
assign vdb77b6 = w1;
assign v2ce16c = w2;
v78be07_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-1-7
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of 1 and 7 wires
//---------------------------------------------------
module v78be07_v9a2a06 (
input [7:0] i,
output o1,
output [6:0] o0
);
assign o1 = i[7];
assign o0 = i[6:0];
endmodule
//---- Top entity
module v4c1570 #(
parameter v573b2a = 0
) (
input v6dda25,
input v27dec4,
input v92a149,
output v4642b6
);
localparam p0 = v573b2a;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w5 = v6dda25;
assign v4642b6 = w6;
assign w8 = v27dec4;
assign w9 = v92a149;
assign w7 = w6;
v053dc2 #(
.v71e305(p0)
) v24b497 (
.vf54559(w1),
.va4102a(w5),
.ve8318d(w6)
);
vd0c4e5 vda4b54 (
.v030ad0(w1),
.v27dec4(w2),
.vb192d0(w3),
.v2d3366(w8)
);
vfebcfe v2141a0 (
.v9fb85f(w2)
);
vd0c4e5 v75d8ff (
.v030ad0(w3),
.v27dec4(w4),
.vb192d0(w7),
.v2d3366(w9)
);
vd30ca9 va595cf (
.v9fb85f(w4)
);
endmodule
//---------------------------------------------------
//-- RS-FF-set
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- RS-FF-set. RS Flip-flop with priority set
//---------------------------------------------------
//---- Top entity
module vda0861 #(
parameter vfffc23 = 0
) (
output [7:0] vffb58f
);
localparam p0 = vfffc23;
wire [0:7] w1;
assign vffb58f = w1;
vffc517 #(
.vc5c8ea(p0)
) v778577 (
.va0aeac(w1)
);
endmodule
//---------------------------------------------------
//-- 8bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 8bits constant value: 0
//---------------------------------------------------
//---- Top entity
module v9791ec #(
parameter v9d2d5b = 0,
parameter v42e61f = 0
) (
input vfde3d7,
input vd9601b,
output v157a67,
output v64879c
);
localparam p4 = v42e61f;
wire w0;
wire w1;
wire w2;
wire w3;
wire w5;
wire w6;
assign w0 = vd9601b;
assign v157a67 = w1;
assign v64879c = w3;
assign w5 = vfde3d7;
assign w6 = vfde3d7;
assign w2 = w1;
assign w6 = w5;
v31e84e v9cfc0f (
.ve78ab8(w2),
.v3487af(w3),
.ved8395(w6)
);
v0b641d #(
.v803182(p4)
) v6ca512 (
.v27dec4(w0),
.v4642b6(w1),
.v25ab12(w5)
);
endmodule
//---------------------------------------------------
//-- Button-tic CLONE
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Button-tic: Configurable button that emits a tic when it is pressed
//---------------------------------------------------
//---- Top entity
module v31e84e (
input ved8395,
input ve78ab8,
output v3487af
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign w0 = ve78ab8;
assign w1 = ved8395;
assign w4 = ve78ab8;
assign v3487af = w5;
assign w4 = w0;
v053dc2 v1bde40 (
.vf54559(w0),
.va4102a(w1),
.ve8318d(w2)
);
v3676a0 v9d4cda (
.v0e28cb(w2),
.vcbab45(w3)
);
vba518e v57aa83 (
.v0e28cb(w3),
.v3ca442(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- Rising-edge-detector
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input
//---------------------------------------------------
//---- Top entity
module v0b641d #(
parameter v803182 = 0
) (
input v25ab12,
input v27dec4,
output v4642b6
);
localparam p1 = v803182;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign v4642b6 = w3;
assign w4 = v27dec4;
assign w5 = v25ab12;
assign w6 = v25ab12;
assign w6 = w5;
vf718a5 v5e6bb3 (
.v6a82dd(w2),
.vd4e5d7(w3),
.v444878(w6)
);
vdc93d6 v71ab2a (
.v3c12b5(w0),
.ve7f5e6(w4),
.v717e81(w5)
);
vad96dc #(
.v6a9fe4(p1)
) vc0a9e9 (
.v27dec4(w0),
.v4642b6(w2)
);
endmodule
//---------------------------------------------------
//-- Button
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Configurable button (pull-up on/off. Not on/off)
//---------------------------------------------------
//---- Top entity
module vf718a5 (
input v444878,
input v6a82dd,
output vd4e5d7
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign w2 = v444878;
assign w3 = v444878;
assign w4 = v444878;
assign vd4e5d7 = w5;
assign w6 = v6a82dd;
assign w7 = v6a82dd;
assign w3 = w2;
assign w4 = w2;
assign w4 = w3;
assign w7 = w6;
v93adf6 ve5d8ab (
.v9afc1f(w0),
.va4102a(w2),
.ve8318d(w5),
.vf54559(w6)
);
v413e4a v93d042 (
.ve37344(w0),
.ve556f1(w1),
.v6dda25(w3)
);
v332488 vf5eed3 (
.v3487af(w1),
.ved8395(w4),
.ve78ab8(w7)
);
endmodule
//---------------------------------------------------
//-- Debouncer-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Remove the rebound on a mechanical switch
//---------------------------------------------------
//---- Top entity
module v93adf6 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
input v9afc1f,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
wire w4;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
assign w4 = v9afc1f;
v93adf6_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3),
.load(w4)
);
endmodule
//---------------------------------------------------
//-- Reg-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 1bit register (implemented in verilog)
//---------------------------------------------------
module v93adf6_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
input load,
output q
);
reg q = INI;
always @(posedge clk)
if (load)
q <= d;
endmodule
//---- Top entity
module v413e4a (
input v6dda25,
input ve556f1,
output [15:0] v49911e,
output ve37344
);
wire w0;
wire [0:15] w1;
wire [0:15] w2;
wire w3;
wire [0:15] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign v49911e = w4;
assign ve37344 = w5;
assign w4 = w1;
vbc711b v8fa00b (
.v782748(w0),
.v3f90b8(w1),
.vc320da(w2),
.v6dda25(w3)
);
v8ecd59 v9392cd (
.v2f9d57(w1),
.vd7988b(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-16bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 16-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module vbc711b (
input v6dda25,
input v782748,
input [15:0] vc320da,
output [15:0] v3f90b8
);
wire [0:15] w0;
wire [0:15] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire [0:3] w8;
wire [0:3] w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w0 = vc320da;
assign v3f90b8 = w1;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
v5c75f6 vbdef88 (
.v4de61b(w2),
.v50034e(w6),
.v6dda25(w13),
.v782748(w17)
);
v5c75f6 v6188f9 (
.v4de61b(w3),
.v50034e(w7),
.v6dda25(w12),
.v782748(w16)
);
v852bc8 vd47660 (
.v91b9c1(w0),
.v527ffb(w2),
.v71a717(w3),
.v0b337e(w4),
.vfc89f9(w5)
);
v401a28 v3ef916 (
.v14a530(w1),
.vcc76e8(w6),
.vd531e6(w7),
.v7ef7d6(w8),
.v1447f2(w9)
);
v5c75f6 v9f7443 (
.v4de61b(w4),
.v50034e(w8),
.v6dda25(w11),
.v782748(w15)
);
v5c75f6 vd2d6b6 (
.v4de61b(w5),
.v50034e(w9),
.v6dda25(w10),
.v782748(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x16
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x16: 16 D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v852bc8 (
input [15:0] v91b9c1,
output [3:0] vfc89f9,
output [3:0] v0b337e,
output [3:0] v71a717,
output [3:0] v527ffb
);
wire [0:15] w0;
wire [0:3] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
assign w0 = v91b9c1;
assign v527ffb = w1;
assign v71a717 = w2;
assign v0b337e = w3;
assign vfc89f9 = w4;
v852bc8_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2),
.o2(w3),
.o3(w4)
);
endmodule
//---------------------------------------------------
//-- Bus16-Split-quarter
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Split-quarter: Split the 16-bits bus into four buses of the same size
//---------------------------------------------------
module v852bc8_v9a2a06 (
input [15:0] i,
output [3:0] o3,
output [3:0] o2,
output [3:0] o1,
output [3:0] o0
);
assign o3 = i[15:12];
assign o2 = i[11:8];
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module v401a28 (
input [3:0] v1447f2,
input [3:0] v7ef7d6,
input [3:0] vd531e6,
input [3:0] vcc76e8,
output [15:0] v14a530
);
wire [0:15] w0;
wire [0:3] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
assign v14a530 = w0;
assign w1 = vcc76e8;
assign w2 = vd531e6;
assign w3 = v7ef7d6;
assign w4 = v1447f2;
v401a28_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2),
.i2(w3),
.i3(w4)
);
endmodule
//---------------------------------------------------
//-- Bus16-Join-quarter
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus16-Join-quarter: Join the four same buses into an 16-bits Bus
//---------------------------------------------------
module v401a28_v9a2a06 (
input [3:0] i3,
input [3:0] i2,
input [3:0] i1,
input [3:0] i0,
output [15:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module v8ecd59 #(
parameter v6c5139 = 1
) (
input [15:0] v2f9d57,
output v4642b6,
output [15:0] vd7988b
);
localparam p1 = v6c5139;
wire w0;
wire [0:15] w2;
wire [0:15] w3;
assign v4642b6 = w0;
assign w2 = v2f9d57;
assign vd7988b = w3;
v265696 #(
.vd73390(p1)
) v76123a (
.v4642b6(w0),
.v36f2dd(w2),
.vc068fb(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-16bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-16bit: Increment a 16-bits number by one
//---------------------------------------------------
//---- Top entity
module v265696 #(
parameter vd73390 = 0
) (
input [15:0] v36f2dd,
output v4642b6,
output [15:0] vc068fb
);
localparam p1 = vd73390;
wire w0;
wire [0:15] w2;
wire [0:15] w3;
wire [0:15] w4;
assign v4642b6 = w0;
assign w3 = v36f2dd;
assign vc068fb = w4;
v651fa3 #(
.vc5c8ea(p1)
) vdd8fa2 (
.vcd9338(w2)
);
vbc66d7 vce7ab7 (
.v4642b6(w0),
.v1489e0(w2),
.v603a9a(w3),
.v2c4251(w4)
);
endmodule
//---------------------------------------------------
//-- AdderK-16bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-16bit: Adder of 16-bit operand and 16-bit constant
//---------------------------------------------------
//---- Top entity
module v651fa3 #(
parameter vc5c8ea = 0
) (
output [15:0] vcd9338
);
localparam p0 = vc5c8ea;
wire [0:15] w1;
assign vcd9338 = w1;
v651fa3_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 16-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 16-bits generic constant
//---------------------------------------------------
module v651fa3_v465065 #(
parameter VALUE = 0
) (
output [15:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module vbc66d7 (
input [15:0] v1489e0,
input [15:0] v603a9a,
output v4642b6,
output [15:0] v2c4251
);
wire w0;
wire w1;
wire [0:15] w2;
wire [0:15] w3;
wire [0:15] w4;
wire [0:7] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire [0:7] w9;
wire [0:7] w10;
assign v4642b6 = w0;
assign w2 = v603a9a;
assign w3 = v1489e0;
assign v2c4251 = w4;
v306ca3 v0a29fe (
.v91b9c1(w2),
.vef5eee(w9),
.vd3ef3b(w10)
);
v306ca3 vb0a6ce (
.v91b9c1(w3),
.vef5eee(w7),
.vd3ef3b(w8)
);
vcb23aa v8e0bba (
.v4642b6(w1),
.v62bf25(w6),
.v39966a(w8),
.veb2f59(w10)
);
vc3c498 v917bbf (
.v4642b6(w0),
.vb9cfc3(w1),
.veeaa8e(w5),
.v45c6ee(w7),
.v20212e(w9)
);
v8cc49c v03c3e3 (
.v14a530(w4),
.vb334ae(w5),
.v2b8a97(w6)
);
endmodule
//---------------------------------------------------
//-- Adder-16bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-16bits: Adder of two operands of 16 bits
//---------------------------------------------------
//---- Top entity
module v332488 (
input ved8395,
input ve78ab8,
output v3487af
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = ve78ab8;
assign w1 = ved8395;
assign v3487af = w2;
assign w4 = ve78ab8;
assign w4 = w0;
vd12401 v456da5 (
.vcbab45(w2),
.v0e28cb(w3),
.v3ca442(w4)
);
v053dc2 vdfab80 (
.vf54559(w0),
.va4102a(w1),
.ve8318d(w3)
);
endmodule
//---------------------------------------------------
//-- Edges-detector
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input
//---------------------------------------------------
//---- Top entity
module vdc93d6 (
input v717e81,
input ve7f5e6,
output v3c12b5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = ve7f5e6;
assign v3c12b5 = w2;
assign w3 = v717e81;
assign w4 = v717e81;
assign w4 = w3;
v053dc2 vbb75a1 (
.vf54559(w0),
.ve8318d(w1),
.va4102a(w4)
);
v053dc2 vf6c433 (
.vf54559(w1),
.ve8318d(w2),
.va4102a(w3)
);
endmodule
//---------------------------------------------------
//-- Sync-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Sync 1-bit input with the system clock domain
//---------------------------------------------------
//---- Top entity
module vad96dc #(
parameter v6a9fe4 = 0
) (
input v27dec4,
output v4642b6
);
localparam p0 = v6a9fe4;
wire w1;
wire w2;
wire w3;
assign w2 = v27dec4;
assign v4642b6 = w3;
vd12401 v5b01c7 (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w3)
);
v6b14d5 #(
.vc5c8ea(p0)
) v94e17e (
.v268bfc(w1)
);
endmodule
//---------------------------------------------------
//-- not-wire-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Select positive or negative logic for the input (0=positive, 1=negative)
//---------------------------------------------------
//---- Top entity
module v6b14d5 #(
parameter vc5c8ea = 0
) (
output v268bfc
);
localparam p0 = vc5c8ea;
wire w1;
assign v268bfc = w1;
v6b14d5_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 1-bit-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 1-bit generic constant (0/1)
//---------------------------------------------------
module v6b14d5_v465065 #(
parameter VALUE = 0
) (
output k
);
assign k = VALUE;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR3_1_V
`define SKY130_FD_SC_LP__XOR3_1_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR3_1_V
|
(*
Copyright 2014 Cornell University
Copyright 2015 Cornell University
Copyright 2016 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Websites: http://nuprl.org/html/verification/
http://nuprl.org/html/Nuprl2Coq
https://github.com/vrahli/NuprlInCoq
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export approx_star_props2.
Require Export computation6.
(** printing # $\times$ #×# *)
(** printing <=> $\Leftrightarrow$ #⇔# *)
(** printing $ $\times$ #×# *)
(** printing & $\times$ #×# *)
(* begin hide *)
Lemma range_utok_ren_nrut_subs_to_utok_ren {o} :
forall (sub1 sub2 : @Sub o) l1 l2,
nrut_sub l1 sub1
-> nrut_sub l2 sub2
-> length sub1 = length sub2
-> range_utok_ren (nrut_subs_to_utok_ren sub1 sub2)
= get_utokens_sub sub2.
Proof.
induction sub1; destruct sub2; introv nrut1 nrut2 len; simphyps; tcsp.
destruct a as [v1 t1]; destruct p as [v2 t2].
allrw @nrut_sub_cons; exrepnd; subst; allsimpl; cpx.
allrw @get_utokens_sub_cons; allsimpl.
erewrite IHsub1; eauto.
Qed.
Lemma dom_utok_ren_nrut_subs_to_utok_ren {o} :
forall (sub1 sub2 : @Sub o) l1 l2,
nrut_sub l1 sub1
-> nrut_sub l2 sub2
-> length sub1 = length sub2
-> dom_utok_ren (nrut_subs_to_utok_ren sub1 sub2)
= get_utokens_sub sub1.
Proof.
induction sub1; destruct sub2; introv nrut1 nrut2 len; simphyps; tcsp.
destruct a as [v1 t1]; destruct p as [v2 t2].
allrw @nrut_sub_cons; exrepnd; subst; allsimpl; cpx.
allrw @get_utokens_sub_cons; allsimpl.
erewrite IHsub1; eauto.
Qed.
Lemma approx_star_change_nrut_sub {o} :
forall lib (t1 t2 : @NTerm o) sub l sub' l',
nrut_sub l sub
-> nrut_sub l' sub'
-> dom_sub sub = dom_sub sub'
-> subset (get_utokens t1) l
-> subset (get_utokens t2) l
-> subset (get_utokens t1) l'
-> subset (get_utokens t2) l'
-> approx_star lib (lsubst t1 sub) (lsubst t2 sub)
-> approx_star lib (lsubst t1 sub') (lsubst t2 sub').
Proof.
introv nrut1 nrut2 eqdoms ss1 ss2 ss3 ss4 apr.
pose proof (length_dom sub) as len.
rw eqdoms in len; rw @length_dom in len.
pose proof (change_nr_ut_sub_in_lsubst_aux_approx_star
lib (lsubst t1 sub) (lsubst t2 sub)
(nrut_subs_to_utok_ren sub sub')) as h.
erewrite @range_utok_ren_nrut_subs_to_utok_ren in h; eauto.
erewrite @dom_utok_ren_nrut_subs_to_utok_ren in h; eauto.
repeat (autodimp h hyp); eauto 3 with slow.
- introv i j.
allrw in_diff; repnd.
apply get_utokens_lsubst in j0; allrw in_app_iff; repndors.
+ apply ss3 in j0.
unfold nrut_sub in nrut2; repnd.
apply nrut2 in j0; sp.
+ apply in_get_utokens_sub in j0; exrepnd.
apply in_sub_keep_first in j1; repnd.
apply sub_find_some in j2.
destruct j.
apply in_sub_eta in j2; repnd.
unfold get_utokens_sub; rw lin_flat_map.
eexists; dands; eauto.
- introv i j.
allrw in_diff; repnd.
apply get_utokens_lsubst in j0; allrw in_app_iff; repndors.
+ apply ss4 in j0.
unfold nrut_sub in nrut2; repnd.
apply nrut2 in j0; sp.
+ apply in_get_utokens_sub in j0; exrepnd.
apply in_sub_keep_first in j1; repnd.
apply sub_find_some in j2.
destruct j.
apply in_sub_eta in j2; repnd.
unfold get_utokens_sub; rw lin_flat_map.
eexists; dands; eauto.
- assert (disjoint (get_utokens_sub sub) (get_utokens t1)) as disj1.
{ introv i j.
apply ss1 in j; unfold nrut_sub in nrut1; repnd.
apply nrut1 in j; sp. }
assert (disjoint (get_utokens_sub sub) (get_utokens t2)) as disj2.
{ introv i j.
apply ss2 in j; unfold nrut_sub in nrut1; repnd.
apply nrut1 in j; sp. }
repeat (rw @lsubst_ren_utokens in h).
repeat (rw @ren_utokens_trivial in h;[|erewrite @dom_utok_ren_nrut_subs_to_utok_ren; eauto]).
erewrite @ren_utokens_sub_nrut_subs_to_utok_ren in h; eauto.
Qed.
Lemma alpha_eq_bterm_preserves_osize2 {p} :
forall bt1 bt2,
@alpha_eq_bterm p bt1 bt2
-> osize (get_nt bt1) = osize (get_nt bt2).
Proof.
introv Hal.
destruct bt1 as [lv1 nt1].
destruct bt2 as [lv2 nt2].
simpl; eapply alpha_eq_bterm_preserves_osize; eauto.
Qed.
Lemma lsubst_approx_star_congr_aux {p} :
forall lib b b' lvi lnta lnta',
approx_star lib b b'
-> length lvi = length lnta
-> length lvi = length lnta'
-> disjoint (bound_vars b ++ bound_vars b') (flat_map (@free_vars p) (lnta ++ lnta'))
-> bin_rel_nterm (approx_star lib) lnta lnta'
-> approx_star lib (lsubst_aux b (combine lvi lnta)) (lsubst_aux b' (combine lvi lnta')).
Proof.
nterm_ind1s b as [x|f ind|o lbt Hind] Case; introv Hap H1len H2len Hdis Hbin;
rw flat_map_app in Hdis; duplicate Hbin as Hbb;
apply @approx_rel_wf_sub with (lvi:=lvi) in Hbb; repnd.
- Case "vterm".
invertsn Hap. allsimpl.
dsub_find xa;
apply approx_open_lsubst_congr with (sub:= combine lvi lnta') in Hap;spcf;
lsubst_lsubst_aux_eq_hyp X99 Hap; simpl; simpl_vlist; clear X99;
lsubst_lsubst_aux_eq_hyp X99 Hap; simpl; simpl_vlist; clear X99;
allsimpl; revert Hap.
+ dsub_find xa'; [|provefalse; eauto with slow].
introv Hap. symmetry in Heqxa. symmetry in Heqxa'.
eapply sub_find_some2_first
in Heqxa; eauto. exrepnd. repnud Hbin. repnud Hbin.
dimp (Hbin n);[spc;fail|].
rewrite nth_indep with (d':= default_nterm) in Heqxa0; spc.
rewrite nth_indep with (d':= default_nterm) in Heqxa4; spc.
rw Heqxa0 in hyp.
rw Heqxa4 in hyp.
eapply approx_star_open_trans; eauto.
+ dsub_find xa'; [provefalse; eauto with slow | ].
introv. apply approx_open_implies_approx_star.
- Case "sterm".
allsimpl.
inversion Hap as [|? ? ? ? wf1 wf2 imp aop|]; subst; clear Hap.
econstructor; eauto.
apply (approx_open_lsubst_congr _ _ _ (combine lvi lnta')) in aop; eauto 3 with slow.
autorewrite with slow in *.
unfold lsubst in aop; boolvar; auto.
allrw disjoint_app_r; repnd.
allrw <- @sub_free_vars_is_flat_map_free_vars_range.
rw @sub_free_vars_combine in n; tcsp.
- Case "oterm".
allsimpl.
pose proof (approx_ot_change
lib
(flat_map free_vars lnta ++ flat_map free_vars lnta')
_ _ _ Hap) as Hao.
exrepnd.
rename lbtcv into lbt'. (* t' in paper *)
apply approx_open_lsubst_congr with (sub:= combine lvi lnta') in Hao0;spcf.
lsubst_lsubst_aux_eq_hyp X99 Hao0; simpl; simpl_vlist; clear X99;[].
lsubst_lsubst_aux_eq_hyp X99 Hao0; simpl; simpl_vlist; clear X99;[].
apply approx_star_open_trans with (b:=lsubst_aux (oterm o lbt') (combine lvi lnta'));spc;[].
allsimpl.
apply approx_open_relates_only_wf in Hao0. repnd.
apply approx_star_congruence2;spc;[].
clear Hao0 Hao4.
unfold approx_starbts, lblift_sub; allunfold @blift_sub;repeat(simpl_list).
dands; spcf.
exrepnd. GC.
introv Hlt. rw @selectbt_map;spc;[]. rw @selectbt_map;spc;[].
duplicate Hlt as Hlt99. apply Hao2 in Hlt.
destruct (dec_op_eq_fresh o) as [e|e].
+ pose proof (approx_star_btermd_fr
_ _ _ _
(flat_map free_vars lnta ++ flat_map free_vars lnta')
e
Hlt) as Hfb.
exrepnd.
exists lvn
(lsubst_aux nt1' (sub_filter (combine lvi lnta) lvn))
(lsubst_aux nt2' (sub_filter (combine lvi lnta') lvn)).
dimp (selectbt_in n lbt');spcf.
dimp (selectbt_in n lbt);spcf.
applydup @alpha_eq_bterm_preserves_osize2 in Hfb4.
(* needed to apply induction hyp later *)
apply (lsubst_alphabt_congr _ _ (combine lvi lnta'))
in Hfb5; [|allsimpl; spcls; disjoint_reasoningv;
apply disjoint_sym; eapply disjoint_flat_map_r in Hao1; eauto; fail].
apply (lsubst_alphabt_congr _ _ (combine lvi lnta))
in Hfb4; [|allsimpl; spcls; disjoint_reasoningv;
apply disjoint_sym in Hdis2;
eapply disjoint_flat_map_r in Hdis2; eauto with slow; fail].
dands; auto;[].
right.
pose proof (exists_nrut_sub
lvn
(get_utokens nt1'
++ get_utokens nt2'
++ flat_map get_utokens lnta
++ flat_map get_utokens lnta'))
as exnrut; exrepnd.
pose proof (approx_star_change_nrut_sub
lib nt1' nt2' sub (get_utokens nt1' ++ get_utokens nt2')
sub0
(get_utokens nt1'
++ get_utokens nt2'
++ flat_map get_utokens lnta
++ flat_map get_utokens lnta'))
as ch.
repeat (autodimp ch hh); tcsp; eauto 3 with slow.
destruct (selectbt lbt n) as [l1 t1].
destruct (selectbt lbt' n) as [l2 t2].
allsimpl.
pose proof (Hind t1 (lsubst nt1' sub0) l1) as h; repeat (autodimp h hh).
{ allrw; auto; rw @simple_osize_lsubst; eauto 3 with slow. }
pose proof (h (lsubst nt2' sub0) lvi lnta lnta') as q; clear h.
repeat (autodimp q hh).
{ repeat (rw @cl_lsubst_lsubst_aux; eauto 2 with slow).
repeat (erewrite bound_vars_lsubst_aux_nrut_sub; eauto).
rw flat_map_app; allrw disjoint_app_l; sp. }
repeat (rw @cl_lsubst_lsubst_aux in q; eauto 2 with slow).
pose proof (simple_lsubst_aux_lsubst_aux_sub_disj nt1' sub0 (combine lvi lnta)) as e1.
rw @sub_free_vars_combine in e1; auto.
rw <- exnrut0 in e1.
erewrite sub_bound_vars_nrut_sub in e1; eauto.
erewrite sub_free_vars_nrut_sub in e1; eauto.
allrw disjoint_app_r; allrw disjoint_app_l; repnd.
repeat (autodimp e1 hh).
pose proof (simple_lsubst_aux_lsubst_aux_sub_disj nt2' sub0 (combine lvi lnta')) as e2.
rw @sub_free_vars_combine in e2; auto.
rw <- exnrut0 in e2.
erewrite sub_bound_vars_nrut_sub in e2; eauto.
erewrite sub_free_vars_nrut_sub in e2; eauto.
allrw disjoint_app_r; allrw disjoint_app_l; repnd.
repeat (autodimp e2 hh).
rw @cl_lsubst_aux_sub_trivial in e1; eauto 2 with slow.
rw @cl_lsubst_aux_sub_trivial in e2; eauto 2 with slow.
rw <- e1 in q; rw <- e2 in q.
exists sub0; dands; auto.
{ repeat (rw @cl_lsubst_lsubst_aux; eauto 2 with slow). }
{ eapply nrut_sub_subset;[|exact exnrut1].
rw subset_app; dands; introv i; repeat (rw in_app_iff);
apply get_utokens_lsubst_aux in i; rw in_app_iff in i; repndors; tcsp;
apply in_get_utokens_sub in i; exrepnd; apply in_sub_keep_first in i0; repnd;
apply sub_find_some in i2; apply in_sub_filter in i2; repnd; apply in_combine in i3; repnd.
- right; right; left; rw lin_flat_map; eexists; dands; eauto.
- right; right; right; rw lin_flat_map; eexists; dands; eauto.
}
+ pose proof (approx_star_btermd
_ _ _ _
(flat_map free_vars lnta ++ flat_map free_vars lnta')
e
Hlt) as Hfb.
exrepnd.
exists lvn (lsubst_aux nt1' (sub_filter (combine lvi lnta) lvn))
(lsubst_aux nt2' (sub_filter (combine lvi lnta') lvn)).
dimp (selectbt_in n lbt');spcf.
dimp (selectbt_in n lbt);spcf.
applydup @alpha_eq_bterm_preserves_osize2 in Hfb2.
(* needed to apply induction hyp later *)
apply lsubst_alphabt_congr with (sub := (combine lvi lnta'))
in Hfb3; [| allsimpl; spcls; disjoint_reasoningv;
apply disjoint_sym; eapply disjoint_flat_map_r in Hao1; eauto; fail].
apply lsubst_alphabt_congr with (sub := (combine lvi lnta))
in Hfb2; [| allsimpl; spcls; disjoint_reasoningv;
apply disjoint_sym in Hdis2;
eapply disjoint_flat_map_r in Hdis2; eauto with slow; fail].
dands; auto;[].
left; dands; auto.
dimp (sub_filter_pair_dom lvn (approx_star lib) lvi lnta lnta' ); spcf.
exrepnd.
rename lnta'0 into lntf.
rename lntb' into lntf'.
rename lvi' into lvif.
rw hyp1.
rw hyp3.
destruct (selectbt lbt n) as [lv nt].
simpl in Hfb5.
eapply Hind with (nt:=nt); eauto; spc;[allrw; eauto 3 with slow|];[].
rw flat_map_app. disjoint_reasoningv; disjoint_sub_filter.
Qed.
Lemma get_utokens_sub_combine {o} :
forall vs (ts : list (@NTerm o)),
length vs = length ts
-> get_utokens_sub (combine vs ts) = flat_map get_utokens ts.
Proof.
induction vs; destruct ts; introv len; allsimpl; tcsp; cpx.
allrw @get_utokens_sub_cons.
rw IHvs; auto.
Qed.
Lemma change_dom_nrut_sub {o} :
forall (sub : @Sub o) l vs,
nrut_sub l sub
-> length vs = length sub
-> {sub' : Sub
& nrut_sub l sub'
# range sub = range sub'
# dom_sub sub' = vs }.
Proof.
introv nrut len.
exists (combine vs (range sub)).
rw @range_combine; allrw @length_range; auto.
rw @dom_sub_combine; allrw @length_range; auto.
dands; auto.
allunfold @nrut_sub; repnd.
rw @get_utokens_sub_combine; allrw @length_range; auto.
dands; auto.
introv i.
allapply in_combine; repnd.
apply in_range in i; exrepnd.
pose proof (nrut0 v0 t) as h; autodimp h hyp.
Qed.
Lemma cl_lsubst_approx_star_congr {o} :
forall lib (a b : @NTerm o) sub,
prog_sub sub
-> approx_star lib a b
-> approx_star lib (lsubst a sub) (lsubst_aux b sub).
Proof.
introv pr apr.
pose proof (lsubst_approx_star_congr_aux lib a b (dom_sub sub) (range sub) (range sub)) as h.
allrw @length_dom; allrw @length_range.
repeat (autodimp h hyp).
- rw flat_map_app.
allrw <- @sub_free_vars_is_flat_map_free_vars_range.
rw @sub_free_vars_if_cl_sub; simpl; eauto with slow.
- unfold bin_rel_nterm, binrel_list; dands; auto.
introv i.
apply approx_star_refl.
remember (nth n (range sub) default_nterm) as t.
assert (LIn t (range sub)) as k.
{ subst; apply nth_in; auto. }
apply in_range in k; exrepnd.
pose proof (pr v t) as h; autodimp h hyp.
destruct h as [c w]; auto.
- allrw <- @sub_eta; auto.
rw @cl_lsubst_lsubst_aux; eauto 2 with slow.
Qed.
(* we need it at least for subs with range as axiom for howe_lemma2 *)
Lemma approx_star_bterm_lsubst_congr {p} :
forall lib (bt1 bt2 : BTerm) sub op,
@prog_sub p sub
-> approx_star_bterm lib op bt1 bt2
-> approx_star_bterm
lib op
(lsubst_bterm_aux bt1 sub)
(lsubst_bterm_aux bt2 sub).
Proof.
introv Hpr Hs.
destruct (dec_op_eq_fresh op) as [d|d].
{
pose proof (approx_star_btermd_fr
_ _ _ _
(flat_map free_vars (range sub)) d Hs) as Hfb.
exrepnd.
allrw <- @sub_free_vars_is_flat_map_free_vars_range.
unfold approx_star_bterm, blift_sub.
exists lvn (lsubst nt1' (sub_filter sub lvn)) (lsubst nt2' (sub_filter sub lvn)).
dands; auto;
[|apply (lsubst_alphabt_congr _ _ sub) in Hfb4;
allsimpl; auto;
try (rw <- @cl_lsubst_lsubst_aux in Hfb4; eauto 3 with slow);
allrw <- @sub_free_vars_is_flat_map_free_vars_range;
rw @sub_free_vars_if_cl_sub; eauto with slow
|apply (lsubst_alphabt_congr _ _ sub) in Hfb5;
allsimpl; auto;
try (rw <- @cl_lsubst_lsubst_aux in Hfb5; eauto 3 with slow);
allrw <- @sub_free_vars_is_flat_map_free_vars_range;
rw @sub_free_vars_if_cl_sub; eauto with slow].
right.
pose proof (exists_nrut_sub
lvn
(get_utokens nt1'
++ get_utokens nt2'
++ get_utokens_sub sub))
as exnrut; exrepnd.
pose proof (approx_star_change_nrut_sub
lib nt1' nt2' sub0 (get_utokens nt1' ++ get_utokens nt2')
sub1
(get_utokens nt1'
++ get_utokens nt2'
++ get_utokens_sub sub))
as ch.
repeat (autodimp ch hh); tcsp; eauto 3 with slow.
destruct bt1 as [l1 t1].
destruct bt2 as [l2 t2].
allsimpl.
pose proof (cl_lsubst_approx_star_congr
lib (lsubst nt1' sub1) (lsubst nt2' sub1) sub) as q.
repeat (autodimp q hyp).
pose proof (simple_lsubst_aux_lsubst_aux_sub_disj nt1' sub1 sub) as e1.
repeat (rw @sub_free_vars_if_cl_sub in e1; eauto with slow).
repeat (autodimp e1 hh).
pose proof (simple_lsubst_aux_lsubst_aux_sub_disj nt2' sub1 sub) as e2.
repeat (rw @sub_free_vars_if_cl_sub in e2; eauto with slow).
repeat (autodimp e2 hh).
rw @cl_lsubst_aux_sub_trivial in e1; eauto 2 with slow.
rw @cl_lsubst_aux_sub_trivial in e2; eauto 2 with slow.
repeat (rw <- @cl_lsubst_lsubst_aux in e1; eauto with slow).
repeat (rw <- @cl_lsubst_lsubst_aux in e2; eauto with slow).
repeat (rw <- @cl_lsubst_lsubst_aux in q; eauto with slow).
rw <- e1 in q; rw <- e2 in q; clear e1 e2.
rw <- exnrut0 in q.
exists sub1; dands; auto.
{ eapply nrut_sub_subset;[|exact exnrut1].
rw subset_app; dands; introv i; repeat (rw in_app_iff);
apply get_utokens_lsubst in i; rw in_app_iff in i; repndors; tcsp;
apply in_get_utokens_sub in i; exrepnd; apply in_sub_keep_first in i0; repnd;
apply sub_find_some in i2; apply in_sub_filter in i2; repnd;
apply in_sub_eta in i3; repnd;
right; right; rw lin_flat_map; eexists; dands; eauto.
}
}
pose proof (approx_star_btermd
_ _ _ _
(flat_map free_vars (range sub)) d Hs) as Hfb.
exrepnd.
apply @lsubst_alphabt_congr with (sub := sub) in Hfb2;
[| change_to_lsubst_aux4; eauto; fail].
apply @lsubst_alphabt_congr with (sub := sub) in Hfb3;
[| change_to_lsubst_aux4; eauto; fail].
allsimpl.
exists lvn (lsubst_aux nt1' (sub_filter sub lvn))
(lsubst_aux nt2' (sub_filter sub lvn)).
dands; sp;[].
pose proof (sub_eta (sub_filter sub lvn)) as Xsfeta.
pose proof (sub_eta_length (sub_filter sub lvn)) as X1len.
remember (dom_sub (sub_filter sub lvn)) as lsvi.
remember (range (sub_filter sub lvn)) as lsnt.
rw Xsfeta.
left; dands; auto.
apply lsubst_approx_star_congr_aux;spc.
- rw flat_map_app.
(* the disjoint_sub_filter tactic needs the substitutions in eta form*)
pose proof (sub_eta sub ) as Xseta.
pose proof (sub_eta_length sub) as Xslen.
remember (dom_sub sub) as lvi.
remember (range sub) as lnt.
rw Xseta in Xsfeta.
disjoint_reasoningv; try disjoint_sub_filter.
- unfold bin_rel_nterm, binrel_list; dands; [sp | introv Hlt].
apply approx_star_refl. pose proof (nth_in _ _ _ default_nterm Hlt) as XX.
rw Heqlsnt in XX.
apply in_range in XX. exrepnd.
apply in_sub_filter in XX0. exrepnd.
apply Hpr in XX1.
rw Heqlsnt. inverts XX1. sp.
Qed.
(* end hide *)
(** %\noindent \\*% The following is a generalization of Howe's lemma 1 %\cite{Howe:1989}%.
He proved proved (needed) it for substitutions of length one.
We need it atleast for substitutions of length upto two because
the computation for [NSpread] performs a simultaneous subsitution
for two variables. We prove a more general version instead.
Apart from some uninteresting details about substitution, our
mechanized proof
is essentially the same as Howe's.
*)
Lemma lsubst_approx_star_congr {p} :
forall lib (t1 t2 : @NTerm p) (lvi : list NVar) (lnt1 lnt2 : list NTerm),
bin_rel_nterm (approx_star lib) lnt1 lnt2
-> length lvi = length lnt1
-> length lvi = length lnt2
-> approx_star lib t1 t2
-> approx_star lib (lsubst t1 (combine lvi lnt1)) (lsubst t2 (combine lvi lnt2)).
Proof.
introv Hsr H1l H2l Has.
pose proof (change_bvars_alpha_wspec
((flat_map free_vars lnt1)++(flat_map free_vars lnt2)) t1) as H1f.
exrepnd. rename ntcv into ct1.
pose proof (change_bvars_alpha_wspec
((flat_map free_vars lnt1)++(flat_map free_vars lnt2)) t2) as H2f.
exrepnd. rename ntcv into ct2.
assert (approx_star lib ct1 ct2) by eauto with slow. clear Has.
apply lsubst_alpha_congr2 with (sub:=(combine lvi lnt1)) in H1f0.
apply lsubst_alpha_congr2 with (sub:=(combine lvi lnt2)) in H2f0.
assert (approx_star lib (lsubst ct1 (combine lvi lnt1)) (lsubst ct2 (combine lvi lnt2)))
;[|eauto with slow; fail].
clear dependent t1. clear dependent t2.
change_to_lsubst_aux4; repeat(simpl_sub); disjoint_reasoningv.
apply lsubst_approx_star_congr_aux; spc;[].
spcls. rw flat_map_app. disjoint_reasoningv.
Qed.
(* begin hide *)
Lemma lsubst_approx_star_congr2 {p} : forall lib t1 t2 sub1 sub2,
sub_range_rel (@approx_star p lib) sub1 sub2
-> approx_star lib t1 t2
-> approx_star lib (lsubst t1 sub1) (lsubst t2 sub2).
Proof.
introv Hsr Has.
apply sub_range_rel_as_list in Hsr. exrepnd.
subst sub1. subst sub2.
apply lsubst_approx_star_congr; spc.
Qed.
(* weaker version than previous*)
Lemma lsubst_approx_star_congr3 {p} : forall lib t1 t2 sub,
@wf_sub p sub
-> approx_star lib t1 t2
-> approx_star lib (lsubst t1 sub) (lsubst t2 sub).
Proof.
introv Hw Has.
apply lsubst_approx_star_congr2; sp;[].
induction sub;allsimpl;spc.
- repnud Hw. repnud Hw. apply approx_star_refl. eapply Hw; left; eauto.
- apply IHsub. introv Hin. repnud Hw. repnud Hw. eapply Hw; right; eauto.
Qed.
Lemma approx_starbt_change {p} :
forall lib op bt1 bt2 (lvn : list NVar),
op <> NCan NFresh
-> approx_star_bterm lib op bt1 bt2
-> no_repeats lvn
-> length lvn = num_bvars bt1
-> disjoint lvn (free_vars_bterm bt1 ++ free_vars_bterm bt2)
-> {nt1',nt2' : @NTerm p
$ approx_star lib nt1' nt2'
# alpha_eq_bterm bt1 (bterm lvn nt1')
# alpha_eq_bterm bt2 (bterm lvn nt2')
(* # disjoint (lvn ++ (bound_vars nt1') ++ (bound_vars nt2')) lvn *)
}.
Proof.
introv d Hab Hnr Hlen Hdis.
invertsna Hab Hab.
exrepnd; repndors; exrepnd; tcsp; GC.
applydup @alphaeqbt_numbvars in Hab2.
allunfold @num_bvars. allsimpl.
dimp (alpha_bterm_pair_change3 _ _ _ _ _ lvn Hab2 Hab1); spcf;[].
exrepnd.
assert (approx_star lib nt1n nt2n) as XX by eauto with slow.
exists (lsubst nt1n (var_ren x lvn)).
exists (lsubst nt2n (var_ren x lvn)).
split; spc;[].
apply approx_star_lsubst_vars;spc.
Qed.
Lemma lsubst_aux_nest_same_str2 {p} :
forall t lvi lvio lnt lf,
length lvio=length lvi
-> length lvio=length lnt
-> no_repeats lvio
-> disjoint (lvio++(flat_map (@free_vars p) lnt)) (bound_vars t ++ lf)
-> disjoint lvio (remove_nvars lvi (free_vars t))
-> lsubst_aux (lsubst_aux t (filt_var_ren lvi lvio lf)) (filt_combine lvio lnt lf)
= lsubst_aux t (filt_combine lvi lnt lf).
Proof.
nterm_ind1s t as [v|f ind|o lbt Hind] Case;
introv Hl1 Hl2 Hnr Hdisb Hdisf; tcsp.
{ Case "vterm".
simpl. destructr (sub_find (@filt_var_ren p lvi lvio lf) v) as [s1st|n1n].
- apply symmetry in HeqHdeq. rename HeqHdeq into s1s.
apply sub_find_sub_filter_some in s1s. repnd.
apply sub_find_first in s1s0. exrepnd.
unfold var_ren in s1s1.
rewrite dom_sub_combine in s1s1;
[| rewrite map_length; congruence] .
unfold var_ren in s1s0.
rewrite length_combine_eq
in s1s0;[| rewrite map_length]; auto.
apply nth_var_ren_implies in s1s2;auto. exrepnd. rename vsr into vio.
simpl. rewrite s1s2. simpl.
destructr (sub_find (filt_combine lvio lnt lf) vio) as [s2st|n2n].
+ apply symmetry in HeqHdeq. rename HeqHdeq into s2s.
apply sub_find_sub_filter_some in s2s. repnd.
apply sub_find_first in s2s0. exrepnd.
unfold var_ren in s2s0. rewrite length_combine_eq
in s2s0;spc.
rw combine_nth in s2s2;spc. inverts s2s2 as s2s3 s2s4.
simpl. rewrite <- Hl1 in s1s0.
(** clear s2s1. it cannot rule out case when n>n0*)
pose proof (no_repeats_index_unique2
_ _ _ _ _ _ Hnr s1s0 s2s0 s1s4 s2s3) as X99.
destruct X99. GC. clear s1s2. clear s1st.
destructr (sub_find (filt_combine lvi lnt lf) v) as [s3st|n3n].
* apply symmetry in HeqHdeq. rename HeqHdeq into s3s.
apply sub_find_sub_filter_some in s3s. repnd.
apply sub_find_first in s3s0. exrepnd.
unfold var_ren in s3s0. rewrite length_combine_eq
in s3s0;spc.
rw combine_nth in s3s2;spc. inverts s3s2 as s3s3 s3s4.
simpl. rewrite Hl1 in s1s0.
allfold (@dom_sub p).
allunfold (@var_ren p). spcls.
assert (n0<n \/ n0=n \/ n<n0) as Htri by omega.
(dorn Htri);[|(dorn Htri)];
try (apply s1s1 in Htri); cpx;
try (apply s3s1 in Htri); cpx.
destruct Htri. GC. apply nth_select3 in s3s4;[| congruence].
apply nth_select3 in s2s4; congruence.
* rename HeqHdeq into n3n. symmetry in n3n.
apply sub_find_sub_filter_none in n3n. dorn n3n; [ |sp(**see s1s*)].
apply sub_find_none2 in n3n.
clear s1s1. apply nth_in2 in s1s3;[| congruence]. allunfold (@var_ren).
simpl. spcls. sp.
+ rename HeqHdeq into n2n. symmetry in n2n.
apply sub_find_sub_filter_none in n2n. dorn n2n.
* apply sub_find_none2 in n2n.
apply nth_in2 in s1s4;[| congruence]. allunfold (@var_ren).
simpl. spcls. sp.
* apply nth_in2 in s1s4;[| congruence].
assert (disjoint lvio lf) as X99 by disjoint_reasoningv.
apply X99 in s1s4; sp.
- allsimpl.
rw <- disjoint_remove_nvars_l in Hdisf.
apply disjoint_singleton_r in Hdisf.
allrw in_remove_nvars.
rw (not_over_and (LIn v lvio) (!LIn v lvi) (in_deq _ deq_nvar v lvio)) in Hdisf.
rw (not_over_not (LIn v lvi) (in_deq _ deq_nvar v lvi)) in Hdisf.
allfold @dom_sub.
assert ((dom_sub (combine lvi lnt)) = lvi) as Xrw by (spcls;sp).
rename HeqHdeq into n1n. symmetry in n1n.
unfold filt_var_ren in n1n.
unfold filt_combine.
allrw @sub_find_sub_filter_eq; boolvar; tcsp.
apply sub_find_none2 in n1n.
rw @dom_sub_var_ren in n1n; auto.
repndors; tcsp.
rw @sub_find_none_if;[|rw @dom_sub_combine; auto].
rw @sub_find_none_if;[|rw @dom_sub_combine; auto];tcsp.
}
{ Case "oterm". (**this part is easier!!*)
allsimpl. f_equal. rewrite map_map. eapply eq_maps; eauto.
intros bt Hinb. destruct bt as [lv nt].
unfold compose.
allsimpl. apply disjoint_app_r in Hdisb. repnd.
rename Hdisb into Hdisl.
rename Hdisb0 into Hdisb.
eapply disjoint_lbt_bt2 in Hdisb; eauto. repnd.
apply disjoint_app_l in Hdisb0. repnd.
simpl. f_equal.
unfold filt_var_ren. unfold filt_combine.
repeat(rewrite <- sub_filter_app_r).
eapply Hind; eauto 3 with slow;[disjoint_reasoningv|].
allrw <- disjoint_remove_nvars_l.
rw disjoint_flat_map_r in Hdisf. apply Hdisf in Hinb.
simpl in Hinb. rw <- disjoint_remove_nvars_l in Hinb.
apply remove_nvars_unchanged in Hdisb1.
rw remove_nvars_comm in Hinb.
rewrite Hdisb1 in Hinb. trivial.
}
Qed.
Lemma lsubst_nest_same_str2 {p} :
forall t lvi lvio lnt lf,
length lvio=length lvi
-> length lvio=length lnt
-> no_repeats lvio
-> disjoint (lvio++(flat_map (@free_vars p) lnt)) (bound_vars t ++ lf)
-> disjoint lvio (remove_nvars lvi (free_vars t))
-> lsubst (lsubst t (filt_var_ren lvi lvio lf)) (filt_combine lvio lnt lf)
= lsubst t (filt_combine lvi lnt lf).
Proof.
intros.
change_to_lsubst_aux4;
try(apply lsubst_aux_nest_same_str2;try(sp;fail));
apply disjoint_sym;
rw <- @disjoint_sub_as_flat_map;
try(apply sub_filter_sat).
- rw @disjoint_sub_as_flat_map; spcls; disjoint_reasoningv.
- rw @disjoint_sub_as_flat_map; spcls; disjoint_reasoningv.
- rw <- @lsubst_lsubst_aux; disjoint_reasoningv.
rw @boundvars_lsubst_vars2; spcls; disjoint_reasoningv.
+ rw @disjoint_sub_as_flat_map. spcls. sp.
+ apply allvars_sub_filter.
+ apply sub_filter_sat. rw @disjoint_sub_as_flat_map.
spcls. disjoint_reasoningv.
- rw @disjoint_sub_as_flat_map; spcls; disjoint_reasoningv.
Qed.
Lemma lsubst_nest_same2 {p} :
forall t lvi lvio lnt,
length lvio=length lvi
-> length lvio=length lnt
-> no_repeats lvio
-> disjoint (lvio++(flat_map (@free_vars p) lnt)) (bound_vars t)
-> disjoint lvio (remove_nvars lvi (free_vars t))
-> lsubst (lsubst t (var_ren lvi lvio)) (combine lvio lnt)
= lsubst t (combine lvi lnt).
Proof.
intros.
pose proof (sub_filter_nil_r (@var_ren p lvi lvio)) as K.
rewrite <- K. clear K.
pose proof (sub_filter_nil_r (combine lvio lnt)) as K.
rewrite <- K. clear K.
pose proof (sub_filter_nil_r (combine lvi lnt)) as K.
rewrite <- K. clear K.
apply lsubst_nest_same_str2; simpl; auto.
rewrite app_nil_r. auto.
Qed.
Lemma lsubst_nest_same_alpha2 {p} :
forall t lvi lvio lnt,
length lvio=length lvi
-> length lvio=length lnt
-> no_repeats lvio
-> disjoint lvio (remove_nvars lvi (free_vars t))
-> alpha_eq (lsubst (lsubst t (@var_ren p lvi lvio)) (combine lvio lnt))
(lsubst t (combine lvi lnt)).
Proof.
intros.
pose proof (change_bvars_alpha_wspec (lvio++(flat_map free_vars lnt)) t) as Hf.
exrepnd.
alpharws Hf0.
rw @lsubst_nest_same2;spc.
alpharws (alpha_eq_sym _ _ Hf0). sp.
Qed.
Lemma approx_starbt_change_fr {p} :
forall lib op bt1 bt2 (lvn : list NVar),
op = NCan NFresh
-> approx_star_bterm lib op bt1 bt2
-> no_repeats lvn
-> length lvn = num_bvars bt1
-> disjoint lvn (free_vars_bterm bt1 ++ free_vars_bterm bt2)
-> {sub : Sub
$ {nt1',nt2' : @NTerm p
$ approx_star lib (lsubst nt1' sub) (lsubst nt2' sub)
# nrut_sub (get_utokens nt1' ++ get_utokens nt2') sub
# lvn = dom_sub sub
# alpha_eq_bterm bt1 (bterm lvn nt1')
# alpha_eq_bterm bt2 (bterm lvn nt2')
(* # disjoint (lvn ++ (bound_vars nt1') ++ (bound_vars nt2')) lvn *)
}}.
Proof.
introv d Hab Hnr Hlen Hdis.
invertsna Hab Hab.
exrepnd; repndors; exrepnd; tcsp; GC.
applydup @alphaeqbt_numbvars in Hab2.
allunfold @num_bvars; allsimpl.
assert (length x = length sub) as len.
{ subst; allrw @length_dom; auto. }
dimp (alpha_bterm_pair_change3 _ _ _ _ _ lvn Hab2 Hab1); spcf;[].
exrepnd.
assert (approx_star lib (lsubst nt1n sub) (lsubst nt2n sub)) as XX by eauto with slow.
exists (combine lvn (range sub)).
exists (lsubst nt1n (var_ren x lvn)).
exists (lsubst nt2n (var_ren x lvn)).
rw @dom_sub_combine; allrw @length_range; auto; try omega.
subst; dands; tcsp.
- pose proof (lsubst_nest_same_alpha2 nt1n (dom_sub sub) lvn (range sub)) as nest1.
allrw @length_dom; allrw @length_range.
repeat (autodimp nest1 hyp); try omega.
{ apply alpha_eq_bterm_preserves_free_vars in Hab2; allsimpl.
rw disjoint_app_r in Hdis; repnd.
rw Hab2 in Hdis0.
apply alphaeq_preserves_free_vars in hyp0; rw <- hyp0; auto. }
rw <- @sub_eta in nest1.
pose proof (lsubst_nest_same_alpha2 nt2n (dom_sub sub) lvn (range sub)) as nest2.
allrw @length_dom; allrw @length_range.
repeat (autodimp nest2 hyp); try omega.
{ apply alpha_eq_bterm_preserves_free_vars in Hab1; allsimpl.
rw disjoint_app_r in Hdis; repnd.
rw Hab1 in Hdis.
apply alphaeq_preserves_free_vars in hyp2; rw <- hyp2; auto. }
rw <- @sub_eta in nest2.
pose proof (lsubst_alpha_congr2 nt1 nt1n sub hyp0) as as1.
pose proof (lsubst_alpha_congr2 nt2 nt2n sub hyp2) as as2.
eapply approx_star_alpha_fun_l;[|apply alpha_eq_sym; exact nest1].
eapply approx_star_alpha_fun_r;[|apply alpha_eq_sym; exact nest2].
eauto 3 with slow.
- apply alphaeq_preserves_utokens in hyp0.
apply alphaeq_preserves_utokens in hyp2.
repeat (rw @get_utokens_lsubst_allvars; eauto with slow).
rw <- hyp0; rw <- hyp2.
eapply nrut_sub_change_sub_same_range;[|exact Hab5].
rw @range_combine; auto; allrw @length_range; allrw @length_dom; auto; try omega.
Qed.
Lemma approx_star_open_bt_trans {pp} :
forall lib op (a b c : @BTerm pp),
approx_star_bterm lib op a b
-> approx_open_bterm lib b c
-> approx_star_bterm lib op a c.
Proof.
introv Has Hao.
applydup @blift_sub_numbvars in Has.
pose proof (fresh_vars
(num_bvars a)
(free_vars_bterm a ++ free_vars_bterm b ++ free_vars_bterm c))
as Hfr.
exrepnd.
destruct (dec_op_eq_fresh op) as [d|d].
- apply @approx_starbt_change_fr with (lvn:=lvn) in Has;exrepnd; spc;[| disjoint_reasoningv].
apply @approxbtd_change with (lvn:=lvn) in Hao;spc;[| disjoint_reasoningv].
assert (alpha_eq_bterm (bterm lvn nt1'0) (bterm lvn nt2')) as XX by eauto with slow.
apply alpha_eq_bterm_triv in XX.
unfold approx_open in p0.
rwhg XX p0.
fold (approx_open lib nt2' nt2'0) in p0.
dup p0 as ao.
pose proof (exists_nrut_sub
lvn
(get_utokens nt1'
++ get_utokens nt2'
++ get_utokens nt1'0
++ get_utokens nt2'0))
as exnrut; exrepnd.
pose proof (approx_star_change_nrut_sub
lib nt1' nt2' sub (get_utokens nt1' ++ get_utokens nt2')
sub0
(get_utokens nt1'
++ get_utokens nt2'
++ get_utokens nt1'0
++ get_utokens nt2'0))
as ch.
repeat (autodimp ch hh); tcsp; eauto 3 with slow.
apply (approx_open_lsubst_congr _ _ _ sub0) in p0; eauto 2 with slow.
eapply approx_star_open_trans in ch; eauto.
exists lvn nt1' nt2'0.
dands; tcsp.
right.
exists sub0; dands; tcsp.
eapply nrut_sub_subset;[|exact exnrut1]; eauto with slow.
- apply @approx_starbt_change with (lvn:=lvn) in Has;exrepnd; spc;[| disjoint_reasoningv].
apply @approxbtd_change with (lvn:=lvn) in Hao;spc;[| disjoint_reasoningv].
assert (alpha_eq_bterm (bterm lvn nt1'0) (bterm lvn nt2')) as XX by eauto with slow.
apply alpha_eq_bterm_triv in XX.
unfold approx_open in p0.
rwhg XX p0.
eapply approx_star_open_trans in Has1; eauto.
exists lvn nt1' nt2'0.
dands; tcsp.
Qed.
(* unlike lforall, this unfolds immediately to conjunctions
if the list is concrete. But, it might confuse tactics like eauto *)
Fixpoint lforall2 {T} (P : T -> [univ]) (l: list T) : [univ] :=
match l with
[] => True
| h::t => ((P h) # (lforall2 P t))
end.
Notation programs := (lforall2 isprogram).
(* end hide *)
(** %\noindent \\*% Howe implicitly uses the following lemma at least twice
in his proofs. It is essentially a more useful way
to eliminate (use/destruct) a hypothesis of the form
[approx_star (oterm o lbt) b].
The advantage here is that we additionally obtain the hypothesis
[isprogram (oterm o lbt')]. The [lbt'] that we obtain
by naive inductive destruction of [approx_star (oterm o lbt) b]
need not satisify this property. This additional property
simplifies many proofs. For example, in his proof of
Lemma 2 (shown below), when Howe says "by Lemma 1
and the definition of $\le$ on open terms, we may assume that
$\theta(\overline{t''})$ is closed", he is essentially using this lemma.
The proof of this lemma involves reasoning like that
used in the the proof
of [approx_open_trans].
Essentially, we substitute arbitrary closed terms for
free variables in [lbt'] obtained
by the inductive destruction so that it becomes closed and show that
this substitution has no effect when it gets applied to other terms
in the proof. %\\*%
*)
Lemma approx_star_otd {p} : forall lib o lbt b,
approx_star lib (oterm o lbt) b
-> isprogram b
-> isprogram (oterm o lbt) (* required near the end *)
-> {lbt' : (list (@BTerm p)) $ isprogram (oterm o lbt')
# approx_open lib (oterm o lbt') b
# length lbt = length lbt'
# approx_starbts lib o lbt lbt'}.
Proof.
introv Has Hisp Hispo.
invertsna Has Hapb.
rename lbt1' into lbt''. (* t'' in paper *)
unfold approx_open in Hapb1.
repnud Hapb1.
remember (oterm o lbt'') as tb.
pose proof (close_with_axiom tb Hapb2) as Hpr.
allsimpl. exrepnd.
dimp (Hapb1 (subst_axiom (free_vars tb))); spc;
eauto 2 with slow;[ |rw @lsubst_trivial2; auto].
remember (subst_axiom (free_vars tb)) as subc.
remember (lsubst tb subc) as tbc.
rw @lsubst_trivial2 in hyp; sp.
remember((fun t : BTerm =>
lsubst_bterm_aux t subc)) as fc.
exists (map fc lbt'').
lsubst_lsubst_aux_eq_hyp Heq Heqtbc.
rw Heqtbc in Hpr. subst tb.
simpl in Hpr.
rw <- Heqfc in Hpr.
dands; try( simpl_list); spc.
- apply approx_implies_approx_open. subst; spc.
- unfold approx_starbts; allunfold @lblift_sub; simpl_list; exrepnd.
dands; spcf. introv Hlt.
applydup Hapb0 in Hlt.
rw @selectbt_map; [| omega].
subst fc.
apply approx_star_bterm_lsubst_congr with (sub:=subc) in Hlt0; auto;[].
apply isprogram_ot_iff in Hispo. repnd.
apply selectbt_in in Hlt.
rw @lsubst_bterm_trivial in Hlt0; eauto with slow.
Qed.
Ltac prove_isprogram :=
match goal with
| [ |- isprogram _ ] =>
complete (repeat decomp_progh; show_hyps; eauto with extens;
repeat decomp_progc; eauto with extens)
| _ => idtac
end.
Lemma reduces_to_implies_approx_eauto {p} :
forall lib (t x : @NTerm p),
isprogram t -> reduces_to lib t x -> approx lib x t.
Proof.
introv Hp Hr.
apply reduces_to_implies_approx in Hr; sp.
Qed.
(** %\noindent \\* % We now prove Howe's lemma 2 %\cite{Howe:1989}%. Using the lemma
[approx_star_otd] above, this proof goes
pretty much exactly like Howe describes.
*)
Lemma howe_lemma2 {p} :
forall lib (c : CanonicalOp) (lbt : list BTerm) (b : @NTerm p),
let t:= oterm (Can c) lbt in
isprogram t
-> isprogram b
-> approx_star lib t b
-> {lbt' : (list BTerm)
& approx_starbts lib (Can c) lbt lbt'
# computes_to_value lib b (oterm (Can c) lbt')}.
Proof.
introv Hprt Hprb Hap.
apply approx_star_otd in Hap;spcf;[]. exrepnd.
rename lbt' into lbt''. (* t'' in paper *)
apply approx_open_approx in Hap2; spc.
invertsna Hap2 Hclose. repnud Hclose.
dimp (Hclose2 c lbt'');
eauto;[apply computes_to_value_isvalue_refl; constructor; eauto; fail|].
exrepnd.
apply clearbot_relbt in hyp0.
rename tr_subterms into lbt'. (*( t' in the paper proof *)
exists lbt'.
GC. (*clear Hclose*)
split; auto;[].
allunfold @lblift.
repeat (simpl_list). repnd. split; spcf;[].
introv Hlt.
applydup_clear Hap0 in Hlt.
dimp (hyp0 n); try omega;[].
clear hyp0.
eapply approx_star_open_bt_trans; eauto.
Qed.
Lemma howe_lemma2_seq {o} :
forall lib (f : @ntseq o) (b : @NTerm o),
isprogram (sterm f)
-> isprogram b
-> approx_star lib (sterm f) b
-> {f' : ntseq
& (forall n, approx_star lib (f n) (f' n))
# computes_to_seq lib b f'}.
Proof.
introv Hprt Hprb Hap.
inversion Hap as [|? ? ? ? wf1 wf2 imp aop|]; clear Hap; subst.
apply approx_open_approx in aop; eauto 3 with slow.
invertsna aop Hclose.
repnud Hclose.
dimp (Hclose4 f2); [apply reduces_to_symm|].
exrepnd.
eexists; dands;[|eauto].
introv; eauto 3 with slow.
pose proof (hyp0 n) as h; clear hyp0.
pose proof(imp n) as q; clear imp.
eapply approx_star_open_trans;[eauto|].
apply approx_implies_approx_open; auto.
apply remove_bot_approx; auto.
Qed.
Lemma howe_lemma2_implies_iscan {p} :
forall lib (t b : @NTerm p),
isprogram t
-> iscan t
-> isprogram b
-> approx_star lib t b
-> {v : NTerm & iscan v # (b =v>(lib) v) # approx_star lib t v}.
Proof.
introv ispt isct ispb apr.
apply iscan_implies in isct; repndors; exrepnd; subst.
- apply howe_lemma2 in apr; auto.
exrepnd.
eexists; dands; eauto.
allunfold @approx_starbts.
apply (apso _ _ _ _ lbt'); auto.
{ allunfold @lblift_sub; repnd; auto. }
apply approx_implies_approx_open.
apply reduces_to_implies_approx_eauto; prove_isprogram; eauto 3 with slow.
- apply howe_lemma2_seq in apr; auto.
exrepnd.
unfold computes_to_value.
unfold computes_to_seq in apr0.
applydup @reduces_to_preserves_program in apr0; auto.
eexists;dands;[|eauto| |]; simpl; eauto 3 with slow.
eapply apss;[| |eauto|]; eauto 3 with slow.
Qed.
Lemma howe_lemma2_exc {p} :
forall lib a (e b : @NTerm p),
isprogram (mk_exception a e)
-> isprogram b
-> approx_star lib (mk_exception a e) b
-> { a' , e' : NTerm
$ approx_star lib a a'
# approx_star lib e e'
# computes_to_exception lib a' b e'}.
Proof.
introv Hprt Hprb Hap.
apply approx_star_otd in Hap;spcf;[]. exrepnd.
rename lbt' into lbt''. (* t'' in paper *)
apply approx_open_approx in Hap2; spc.
invertsna Hap2 Hclose. repnud Hclose.
allsimpl; cpx.
applydup @isprogram_exception_implies in Hap1; exrepnd; cpx.
dimp (Hclose3 a0 t); try (complete (apply computes_to_exception_refl; sp)); exrepnd.
apply remove_bot_approx in hyp2.
apply remove_bot_approx in hyp1.
exists a' e'; sp.
- inversion Hap0 as [? f]; allsimpl; GC.
generalize (f 0); clear f; intro k; autodimp k hyp.
unfold selectbt in k; simpl in k.
destruct k as [vs k]; exrepnd; repndors; exrepnd; ginv.
inversion k1; subst; allsimpl; cpx.
inversion k2; subst; allsimpl; cpx.
allunfold @var_ren; allsimpl.
allrw @lsubst_nil; GC.
apply @approx_star_alpha_fun_l with (nt1 := nt1); auto;
try (complete (apply alpha_eq_sym; auto)).
apply @approx_star_open_trans with (b := nt2); auto.
eapply approx_open_alpha_rw_l_aux; eauto.
apply approx_implies_approx_open; auto.
- inversion Hap0 as [? f]; allsimpl; GC.
generalize (f 1); clear f; intro k; autodimp k hyp.
unfold selectbt in k; simpl in k.
destruct k as [vs k]; exrepnd; repndors; exrepnd; ginv.
inversion k1; subst; allsimpl; cpx.
inversion k2; subst; allsimpl; cpx.
allunfold @var_ren; allsimpl.
allrw @lsubst_nil; GC.
apply @approx_star_alpha_fun_l with (nt1 := nt1); auto;
try (complete (apply alpha_eq_sym; auto)).
apply @approx_star_open_trans with (b := nt2); auto.
eapply approx_open_alpha_rw_l_aux; eauto.
apply approx_implies_approx_open; auto.
Qed.
(*
Lemma howe_lemma2_mrk {p} :
forall lib m (b : @NTerm p),
isprogram b
-> approx_star lib (mk_marker m) b
-> computes_to_marker lib b m.
Proof.
introv Hprb Hap.
apply approx_star_otd in Hap;spcf;[|repeat constructor; simpl; complete sp]; exrepnd.
allsimpl; cpx; fold_terms.
apply approx_open_approx in Hap2; spc.
invertsna Hap2 Hclose.
repnud Hclose.
dimp (Hclose m).
apply compute_to_marker_mrk.
Qed.
*)
(** Informally, [howe_lemma2] looks a lot like the definition of [close_comput].
The only difference is that [close_comput] was
preserved when computation happens on the LHS argument.
Recall the [approx] can be considered as a greatest fixed point
of [close_comput]. If we could prove that [approx_star] is preserved
when computation happens on the LHS argument, a simple coinductive
argument will prove that [approx_star] implies
[approx] on closed terms.
Formally, we only need to prove the following lemma
%\footnote{Howe did not explicitly call it Lemma 3. But he proves it
while proving his theorem 1}% :
[[
Lemma howe_lemma3 : forall (a a' b : NTerm),
isprogram a
-> isprogram a'
-> isprogram b
-> computes_to_value a a'
-> approx_star a b
-> approx_star a' b.
]]
This proof will proceed by the induction on the number of steps that
[a] took to compute to the value [a']. Since variables don't compute to
anything, [a] must be of the form [oterm o lbt]. The proof then proceeds
by case analysis on [o]. Unlike the previous proofs about [approx],
which were uniform w.r.t the [Opid]s in the language and
only assumed that the computation system was lazy, this proof
requires reasoning about each [Opid] in the language.
Howe abstracts the remainder of the proof of this lemma into the
following condition (called extensionality) that has to be proved
for each [Opid] in the language. The last hypothesis ([Hind], the big one)
in this definition is essentially the induction hypothesis
in the proof of [howe_lemma3].
*)
Definition extensional_op_ind {p} lib k :=
forall (u u' v : @NTerm p),
isprogram u
-> isprogram u'
-> isprogram v
-> computes_to_val_like_in_max_k_steps lib u u' k
-> approx_star lib u v
-> approx_star lib u' v.
Definition extensional_op {p} (o : @Opid p) :=
forall
(lib : library)
(lbt lbt' : list BTerm)
(a : NTerm)
(k : nat)
(Hpa : isprogram a)
(Hpt : isprogram (oterm o lbt))
(Hpt' : isprogram (oterm o lbt'))
(Hcv : computes_to_val_like_in_max_k_steps lib (oterm o lbt) a (S k))
(Has : lblift_sub o (approx_star lib) lbt lbt')
(Hind : @extensional_op_ind p lib k),
approx_star lib a (oterm o lbt').
(** %\noindent \\*% It is immediately clear that all the canonical [Opid]s of
a lazy computation
system are extensional. In this case, we have [(oterm o lbt)= a] and
the conclusion is an immediate consequence of congruence of [approx_star].
*)
Lemma nuprl_extensional_can {p} :
forall cop, extensional_op (@Can p cop).
Proof.
introv Hpra Hprt Hprt' Hcv Has Hi.
apply computes_to_val_like_in_max_k_steps_can in Hcv; subst.
apply approx_star_congruence2;sp; eauto with slow.
Qed.
Lemma nuprl_extensional_exc {p} :
extensional_op (@Exc p).
Proof.
introv Hpra Hprt Hprt' Hcv Has Hi.
apply computes_to_val_like_in_max_k_steps_exc in Hcv; subst.
apply approx_star_congruence2;sp; eauto with slow.
Qed.
(** %\noindent% The next definition
is just compact and equivalent
restatement of [extensional_op_val] for
the paper.
Please ignore if you are reading
the technical report. Sorry! *)
Definition extensional_opc {p} (o : @Opid p) :=
forall lib
(lbt lbt' : list BTerm)
(a : NTerm)
(k:nat),
programs [a,(oterm o lbt),(oterm o lbt')]
-> computes_to_value_in_max_k_steps lib (S k) (oterm o lbt) a
-> lblift_sub o (approx_star lib) lbt lbt'
-> (forall (u u' v : @NTerm p),
programs [u,u',v]
-> computes_to_value_in_max_k_steps lib k u u'
-> approx_star lib u v
-> approx_star lib u' v)
-> approx_star lib a (oterm o lbt').
(* begin hide *)
Lemma approx_star_bterm_nobnd2 {p} :
forall lib op a b,
approx_star_bterm lib op (bterm [] a) (@bterm p [] b)
-> approx_star lib a b.
Proof.
introv Has.
apply approx_star_bterm_nobnd in Has; exrepnd; subst; cpx.
inversion Has1; subst; sp.
Qed.
Lemma notTrue_btchange {p} : (forall lv nt lvn,
length lv = length lvn ->
alpha_eq_bterm (bterm lv nt) (bterm lvn (lsubst nt (@var_ren p lv lvn))))
-> False.
Proof.
introv Hc.
pose proof (Hc [nvarx,nvary] (oterm (NCan (NArithOp ArithOpAdd)) [(bterm [] (vterm nvarx)),(bterm [] (vterm nvary))])
[nvarz,nvarz] eq_refl) as XX.
clear Hc.
unfold mk_apply,lsubst, nobnd in XX.
simpl in XX.
Abort. (* apply both sides to [1,2] and compute 1 step to get sth which is not alpha equal*)
(* see btchange_alpha for the correct version*)
(*
Lemma approx_star_btermd_samevar {p} :
forall lib op a lv bt,
approx_star_bterm lib op (bterm lv a) bt
-> {b : @NTerm p
$ alpha_eq_bterm bt (bterm lv b)
# approx_star lib a b }.
Proof.
introv Has.
destruct bt as [lvb b']; allsimpl.
apply (approx_star_btermd _ _ _ (lv++lvb)) in Has.
exrepnd.
pose proof (change_bvars_alpha_wspec (lv++lvb) a) as Hfa.
exrepnd. rename ntcv into a'. duplicate Hfa0.
apply @alpha_eq_bterm_congr with (lv:=lv) in Hfa0.
assert (alpha_eq_bterm (bterm lv a') (bterm lvn nt1'))
as Xa by eauto with slow.
pose proof (change_bvars_alpha_wspec (lvb++lv) b') as Hfb.
exrepnd. rename ntcv into b.
apply @alpha_eq_bterm_congr with (lv:=lvb) in Hfb0.
assert (alpha_eq_bterm (bterm lvb b) (bterm lvn nt2'))
as Xb by eauto with slow.
invertsna Xa Hb.
invertsna Xb Ha.
apply lsubst_alpha_congr2 with (sub:=var_ren lv3 lv) in Ha3.
rw @lsubst_nest_vars_same in Ha3;spc; disjoint_reasoningv;[].
rw @lsubst_nest_vars_same in Ha3;spc; disjoint_reasoningv;[].
apply lsubst_alpha_congr2 with (sub:=var_ren lv0 lv) in Hb3.
rw @lsubst_nest_vars_same in Hb3;spc; disjoint_reasoningv;[].
rw @lsubst_nest_vars_same in Hb3;spc; disjoint_reasoningv;[].
assert (alpha_eq a' (lsubst nt1' (var_ren lvn lv))) as Xa by eauto with slow.
clear Hb3.
apply approx_star_lsubst_vars with (lvi:=lvn) (lvo:=lv) in Has1;spc;[].
exists (lsubst nt2' (var_ren lvn lv)).
dands.
Focus 2. eauto with slow; fail.
Abort. (* probably not true ... see above*)
*)
Lemma approx_star_btermd_1var {p} :
forall lib op v a bt,
approx_star_bterm lib op (bterm [v] a) bt
-> {vr : NVar
$ {b : @NTerm p
$ bt = bterm [vr] b
# approx_star_bterm lib op (bterm [v] a) (bterm [vr] b) }}.
Proof.
introv Hab.
destruct bt as [lvb b].
applydup @blift_sub_numbvars in Hab.
allunfold @num_bvars; allsimpl.
alphahypsd.
exrepnd.
eexists; eexists; dands; eauto.
Qed.
Lemma approx_star_btermd_2var {p} :
forall lib op v1 v2 a bt,
approx_star_bterm lib op (bterm [v1, v2] a) bt
-> {v1r,v2r : NVar
$ {b : @NTerm p $ bt=(bterm [v1r,v2r] b)
# approx_star_bterm lib op (bterm [v1,v2] a) (bterm [v1r,v2r] b)}}.
Proof.
introv Hab.
destruct bt as [lvb b].
applydup @blift_sub_numbvars in Hab.
allunfold @num_bvars.
allsimpl.
alphahypsd.
exrepnd.
eexists; eexists; dands; eauto.
Qed.
(*
Lemma compute_apply_decompose : forall k lbt a,
computes_to_value_in_max_k_steps (S k) (oterm (NCan NApply) lbt) a
-> {v : NVar $ {la b arg : NTerm $ lbt = [(bterm [] la), (bterm [] arg)
# computes_to_value_in_max_k_steps k la (mk_lambda v b)
# computes_to_value_in_max_k_steps k la (mk_lambda v b)
] }} *)
Hint Resolve computek_preserves_program : slow.
Ltac lsubst_nest_tac :=
let X99 := fresh "X438590348" in
repeat match goal with
| [ H : (approx_star ?lib (lsubst (lsubst ?t1 (var_ren ?lv1 ?lvn)) (combine ?lvn ?lnt1)) ?rhs) |- _ ]
=> dimp (lsubst_nest_same_alpha t1 lv1 lvn lnt1);
spc;
disjoint_reasoningv;
rename H into X99;
assert (approx_star lib (lsubst t1 (combine lv1 lnt1)) rhs)
as H by eauto with slow; clear X99
| [ H : (approx_star ?lib ?lhs (lsubst (lsubst ?t1 (var_ren ?lv1 ?lvn)) (combine ?lvn ?lnt1))) |- _ ]
=> dimp (lsubst_nest_same_alpha t1 lv1 lvn lnt1);
spc;
disjoint_reasoningv;
rename H into X99;
assert (approx_star lib lhs (lsubst t1 (combine lv1 lnt1)))
as H by eauto with slow; clear X99
end.
(* end hide *)
(** We now begin to prove that the non-canonical [Opid]s of Nuprl are extensional.
The following corollary of Howe's lemma 1 ([lsubst_approx_star_congr]) will
be very useful in of the proofs for the
[Opid]s [NApply, NCbv, NDecide, NSpread].
*)
Lemma apply_bterm_approx_star_congr {p} :
forall lib op bt1 bt2 lnt1 lnt2,
op <> NCan NFresh
-> approx_star_bterm lib op bt1 bt2
-> bin_rel_nterm (@approx_star p lib) lnt1 lnt2 (*enforces that the lengths are equal*)
-> length lnt1 = num_bvars bt1 (*only required for simplicity*)
-> length lnt1 = length lnt2 (*only required for simplicity*)
-> approx_star lib (apply_bterm bt1 lnt1) (apply_bterm bt2 lnt2).
Proof.
introv d Ha0 Hbr H1len H2len.
applydup @blift_sub_numbvars in Ha0. allunfold @num_bvars.
apply (approx_star_btermd _ _ _ _ ((flat_map free_vars lnt1) ++ (flat_map free_vars lnt2))) in Ha0; auto.
allunfold @apply_bterm. allsimpl. exrepnd.
destruct bt1 as [lv1 t1].
destruct bt2 as [lv2 t2]. rename nt1' into nt1. rename nt2' into nt2.
rename lvn into lv.
pose proof (fresh_vars (length lv1) (all_vars nt1 ++ all_vars nt2
++ all_vars t1 ++ all_vars t2)).
exrepnd. simpl in Ha1.
apply @alphabt_change_var with (lv:=lvn) in Ha4; spc; [| disjoint_reasoningv; fail].
apply @alphabt_change_var with (lv:=lvn) in Ha3; spc;[| disjoint_reasoningv];[].
apply approx_star_lsubst_vars with (lvi:=lv) (lvo:=lvn) in Ha0;spc;[].
apply alpha_eq_sym in Ha6.
apply alpha_eq_sym in Ha7.
assert (approx_star lib
(lsubst t1 (var_ren lv1 lvn)) (lsubst t2 (var_ren lv2 lvn)))
as XX by eauto with slow. (* alpha replacement *)
allsimpl. clear Ha0.
apply @lsubst_approx_star_congr with
(lvi:=lvn) (lnt1:=lnt1) (lnt2:=lnt2) in XX;spc;[].
lsubst_nest_tac.
sp.
Qed.
(* Howe proved the extensionality of the [NApply] [Opid].
Crary%\cite{Crary98}% proved it for many others. Our [NDecide] and
[NCbv] are exactly same as his case and let-binding constructs.
Our proofs of extensionality of these [Opid]s are quite close to
their descriptions. We will only describe the proofs for
We will now describe the proof for [NSpread]
%\footnote{Crary's language has $\pi _1$ and $\pi _2$ constructs}%.
*)
(* begin hide *)
Lemma blift_nobnd_congr {p} : forall R t1 t2,
R t1 t2
-> @blift p R (bterm [] t1) (bterm [] t2).
Proof.
introv Ht.
exists (@nil NVar) t1 t2.
dands; eauto with slow.
Qed.
Lemma blift_sub_nobnd_congr {p} :
forall R op t1 t2,
R t1 t2
-> @blift_sub p op R (bterm [] t1) (bterm [] t2).
Proof.
introv Ht.
exists (@nil NVar) t1 t2; dands; eauto with slow.
destruct (dec_op_eq_fresh op) as [d|d]; tcsp.
right; exists ([] : @Sub p); simpl; allrw @lsubst_nil; dands; eauto with slow.
Qed.
Hint Unfold lblift lblift_sub : slow.
Hint Resolve approx_star_congruence2 blift_nobnd_congr blift_sub_nobnd_congr : slow.
Theorem approx_star_congruence3 {p} : forall lib o lbt1 lbt2,
approx_starbts lib o lbt1 lbt2
-> @isprogram p (oterm o lbt2)
-> approx_star lib (oterm o lbt1) (oterm o lbt2).
Proof.
introv Haps Hnt.
apply approx_star_congruence2; sp.
eauto with slow.
Qed.
Ltac prove_approx_star := unfold mk_apply;
match goal with
| [ |- approx_star _ ?t ?t] => apply approx_star_refl
| [ |- approx_star _ (oterm ?o _) (oterm ?o _)] =>
apply approx_star_congruence3
| [ |- isprogram _] => repeat(decomp_progc); eauto with slow
| [ |- approx_starbts _ _ _ _ ] =>
(unfold approx_starbts, lblift_sub; simpl; dands;[spc|];
let Hlt := fresh "XXHlt" in
let n := fresh "XXn" in
intros n Hlt;
( let rnum := (get_lt_rhs Hlt) in
fail_if_not_number rnum; (*fail if not a normal form*)
repeat (destruct n; try omega); unfold selectbt; simpl; unfold nobnd
))
| [ |- approx_star_bterm _ _ (bterm [] ?t1) (bterm [] ?t2)] =>
apply blift_sub_nobnd_congr
| [ |- blift_sub _ (approx_star _) (bterm [] ?t1) (bterm [] ?t2)] =>
apply blift_sub_nobnd_congr
end.
Ltac duplicateas H newname :=
let name := fresh newname
in remember H as name;
clears_last.
Ltac approxrelbtd :=
match goal with
| [H: 0 = length _ |- _ ] => symmetry in H; apply length0 in H; subst
| [H: 1 = length _ |- _ ] => symmetry in H; apply length1 in H; exrepnd; subst
| [H: 2 = length _ |- _ ] => symmetry in H; apply length2 in H; exrepnd; subst
| [H: 3 = length _ |- _ ] => symmetry in H; apply length3 in H; exrepnd; subst
| [H: 4 = length _ |- _ ] => symmetry in H; apply length4 in H; exrepnd; subst
| [H: _ = S (length _) |- _ ] => inverts H as H
| [H: (forall _:nat, (_< ?m) -> blift_sub _ _ _ _) |- _ ] =>
fail_if_not_number m;
(let XXX:= fresh H "0bt" in
assert (0<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simpl in XXX);
try (let XXX:= fresh H "1bt" in
assert (1<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simpl in XXX);
try (let XXX:= fresh H "2bt" in
assert (2<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simpl in XXX);
try (let XXX:= fresh H "3bt" in
assert (3<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simpl in XXX); clear H
| [H: approx_star_bterm _ _ (bterm [] _) (bterm [] _) |- _] => hide_hyp H
| [H: blift_sub _ (approx_star _) (bterm [] _) (bterm [] _) |- _] => hide_hyp H
| [H: approx_star_bterm _ _ (bterm [_] _) (bterm [_] _) |- _] => hide_hyp H
| [H: blift_sub _ (approx_star _) (bterm [_] _) (bterm [_] _) |- _] => hide_hyp H
| [H: approx_star_bterm _ _ (bterm [_,_] _) (bterm [_,_] _) |- _] => hide_hyp H
| [H: blift_sub _ (approx_star _) (bterm [_,_] _) (bterm [_,_] _) |- _] => hide_hyp H
| [H: approx_star_bterm _ _ (bterm [] ?nt) _ |- _] =>
apply approx_star_bterm_nobnd in H;
let ntr := fresh nt "r" in
(destruct H as [ntr H]);
repnd; subst
| [H: blift_sub _ (approx_star _) (bterm [] ?nt) _ |- _] =>
apply approx_star_bterm_nobnd in H;
let ntr := fresh nt "r" in
(destruct H as [ntr H]);
repnd; subst
| [H: approx_star_bterm _ _ (bterm [?v] ?nt) _ |- _] =>
apply approx_star_btermd_1var in H;
let vr := fresh v "r" in
let ntr := fresh nt "r" in
(destruct H as [vr H]; destruct H as [ntr H]);
repnd; subst
| [H: blift_sub _ (approx_star _) (bterm [?v] ?nt) _ |- _] =>
apply approx_star_btermd_1var in H;
let vr := fresh v "r" in
let ntr := fresh nt "r" in
(destruct H as [vr H]; destruct H as [ntr H]);
repnd; subst
| [H: approx_star_bterm _ _ (bterm [?v1, ?v2] ?nt) _ |- _] =>
apply approx_star_btermd_2var in H;
let v1r := fresh v1 "r" in
let v2r := fresh v2 "r" in
let ntr := fresh nt "r" in
(destruct H as [v1r H]; destruct H as [v2r H]; destruct H as [ntr H]);
repnd; subst
| [H: blift_sub _ (approx_star _) (bterm [?v1, ?v2] ?nt) _ |- _] =>
apply approx_star_btermd_2var in H;
let v1r := fresh v1 "r" in
let v2r := fresh v2 "r" in
let ntr := fresh nt "r" in
(destruct H as [v1r H]; destruct H as [v2r H]; destruct H as [ntr H]);
repnd; subst
| [H : approx_star_bterm _ _ (bterm ?lv ?a) (bterm ?lv ?b) |- _ ] =>
apply approx_star_samevar in H; subst
| [H : blift (approx_star _) (bterm ?lv ?a) (bterm ?lv ?b) |- _ ] =>
apply approx_star_samevar in H; subst
| [H : blift _ _ _ |- _ ] => unfold blift in H; exrepnd
end.
Hint Resolve compute_max_steps_eauto compute_max_steps_eauto2: extens.
Lemma reduces_to_implies_approx_open {p} :
forall lib t x,
@isprogram p t
-> reduces_to lib t x
-> approx_open lib x t # approx_open lib t x.
Proof.
introv Hp Hr. apply reduces_to_implies_approx in Hr; auto. repnd.
split; apply approx_implies_approx_open; auto.
Qed.
(*
We begin by proving extensionality of the [NApply] [Opid].
Our proof essentially follows Howe's proof. We will, however
describe the proof to describe some details specific to our
formalization, and also sketch the general recipe for such proofs.
%\footnote {In hind-sight, it seems possible to write an
automated tactic that can finish these proofs}.%
Also, the shape of [bargs] has to be
the one that
[(map (fun x => 0) pargs ++ map num_bvars npargs) = OpBindings (NCan op)].
Morevover, the head [Opid] of this canonical form
([v]) should be compatiable with [op].
For example, if [op = NApply],
[c] must be [NLambda]. Similarly, if [op = NDecide], [c] must either
be [NInl] or [NInr]. For [NCbv], [c] can be canonical [Opid].
One can look at the definition of the [compute_step]
function to find out such relations.
Often, [op] is called the elim form of the intro form [c].
*)
Definition get_bterms {p} (nt:@NTerm p) : list BTerm :=
match nt with
| vterm v => []
| sterm _ => []
| oterm o lbt => lbt
end.
(* use this to typecheck all the composite terms in the long comment below*)
(*
Definition v := nvarx.
Definition v1 := nvarx.
Definition v2 := nvarx.
Definition b := (vterm nvarx).
Definition bl := (vterm nvarx).
Definition br := (vterm nvarx).
Definition pi1 := (vterm nvarx).
Definition arg := (vterm nvarx).
Definition pi2 := (vterm nvarx).
Definition lbt := @nil BTerm.
Definition lbtc := @nil BTerm.
Definition lbt' := @nil BTerm.
Definition bargs := @nil BTerm.
Definition bargs' := @nil BTerm.
Definition pnt := @nil NTerm.
Definition pnt' := @nil NTerm.
Definition pntc := @nil NTerm.
Definition pntc' := @nil NTerm.
Definition op := NFix.
Definition cc := NLambda.
Definition f := fun l: list BTerm => (vterm nvarx).
*)
(* end hide *)
(** Howe and Crary prove extensionality of many non-canonical [Opid]s.
Our computation system has some new ones and the operational
semantics of some earlier ones like [NFix] is different.
We have formally proved that all [Opid]s in our system are extensional.
Instead of describing these proofs separately, we will describe the
general recipe. A reader who
wishes to delve into very concrete details can walk through
the coq proof
scripts for the extensionality lemmas.
In general, whenever a computation in which an arbitrary non-cononical term
[(oterm (NCan op) lbt)] computes to a value [a], [lbt] can be expressed as
[(map (bterm []) pnt)++bargs], where [pnt] are the principal arguments of [op].
The length of [pargs] depends on [op].
For [NCompOp] and [NCanTest], it is 2 and it is 1 for the rest.
The [S k] steps of computation from [(oterm (NCan op) (map (bterm []) pnt ++ bargs))]
to the value [a] (see hypothesis [Hcv] in [extensional_op])
can be split into the following three parts
that happen one after the other.
- Each element of [pnt] converges to some canonical [NTerm].
At the end of this stage, the overall term is of the form
[(oterm (NCan op) ((map (bterm []) pntc)++bargs))] such that
elements of [pnt] converge respectively to canonical elements of [pntc].
- One interesting step of computation happens by the interaction of
the canonical [Opid]s in [pntc] and the corresponding non-canonical [Opid]
[op]. Let the overall term after this step
be [t]. Let [llbt] be [(bargs ++ (flat_map get_bterms pntc))].
For the proof of [extensional_op (NCan op)], the key property
here is that [t] can always be written as some [f llbt] such that
[forall lbt1 lbt2, approx_starbts lbt1 lbt2 -> approx_star (f lbt1) (f lbt2)].
The details of this depend on the specific [op].
We consider all cases
one by one. The reader might want to revisit the definition of [compute_step]
to understand the claims below. [op=]
-- [NApply] : In this case, [pntc] is of the form
[[oterm (Can NLambda) [(bterm [v] b)]]] and [bargs] is of the form
[[bterm [] arg]] and [t= apply_bterm (bterm [v] b) [arg]]. For this
and the next 4 cases, the required property of [f] is a direct consequence
of the lemma [apply_bterm_approx_star_congr] above.
-- [NCbv] : [pntc] is of the form [[oterm (Can cc) lbtc]] and
[bargs] is of the form [bterm [v] b].
[t= apply_bterm (bterm [v] b) [(oterm (Can cc) lbtc)]].
-- [NSpread] : [pntc] is of the form
[[oterm (Can NPair) [bterm [] pi1,bterm [] pi2]]]
and [bargs] is of the form [bterm [v1,v2] b].
[t= apply_bterm (bterm [v1,v2] b) [pi1,pi2]]
-- [NDecide] : [pntc] is of the form
[[oterm (Can NInl) [bterm [] arg]]] or [[oterm (Can NInr) [bterm [] arg]]]
and [bargs] is of the form [[bterm [v] bl,bterm [v] br]]
and [t= apply_bterm (bterm [v] bl) [arg]] or
[t= apply_bterm (bterm [v] br) [arg]] depending on [pntc].
-- [NArithOp] : [pntc] is of the form
[[oterm (Can (Nint n1)) [], oterm (Can (Nint n2)) []]]
and [bargs] is []. [t = oterm (Can (Nint (n1+n2))) []]
The [f] in this case does not depend on any [BTerm]s
(there aren't any in this case)
and is hence a constant function.
The same reason applies for the three cases below.
-- [NCompOp] : and [bargs] is of the form [arg3, arg4].
[t] is either [arg3] or [arg4] depending only on the
head canonical [Opid]s of the [NTerm]s in [pntc]
-- [NCanTest] : exactly same as above.
- t converges to a.
One key observation here is that the second part of this
3-way split consumes exactly one step. Hence the the first and last
parts consume at most [k] steps and hence [Hind] (in the definition
of [extensional_op]) can be applied to
both these parts.
To prove [extensional_op op], we use the hypothesis [Has] to infer
that [lbt'] can also be expressed as [(map (bterm []) pnt')++bargs']
(see the lemma [blift_numbvars]) such that we have
[Hasp : bin_rel_nterm approx_star pnt pnt']
Applying [Hind] along with [Hasp] to the first stage of computation where
[pnt] converges pointwise to [pntc],
and we get
[Haspc : bin_rel_nterm approx_star pntc pnt'].
Next, we apply
[howe_lemma2] pointwise to [Haspc](* make a corollary? *), we get [pntc']
such that elements of [pnt'] converges to [pntc'] respectively
such that we have [Haspcc : bin_rel_nterm approx_star pntc pntc']
Next, the second stage of computation happens and we get that
[oterm (NCan op) ((map (bterm []) pntc')++bargs')] computes to some
[t'] in exactly one step. By the property of this
one step function [f] that we described casewise above,
we get [Hapt : approx_star t t'].
Finally, we apply [Hind] to the third stage again to get
[Hapa : approx_star a t'].
Since [oterm (NCan op) ((map (bterm []) pnt')++bargs')] reduced to
[t'], we use the lemma [reduces_to_implies_approx_open] above to get
[Hao : approx_open t' (oterm (NCan op) ((map (bterm []) pnt')++bargs'))]
Now, we can use [approx_star_open_trans] on [Hapa] and [Hao] to get
the desired conclusion of [extensional_op op].
The concrete Coq proofs of the extensionality lemmas below follow this overall recipe.
*)
Ltac splr :=
first [ complete sp
| complete (left; sp; splr)
| complete (right; sp; splr)
].
Ltac make_red_val_or_exc H h :=
let hyp := fresh h in
let T := type of H in
match T with
| reduces_in_atmost_k_steps ?lib ?t1 ?t2 ?k =>
assert (computes_to_val_or_exc_in_max_k_steps lib t1 t2 k)
as hyp
by (split; [ complete eauto
| splr
]
)
end.
Ltac make_red_val_like H h :=
let hyp := fresh h in
let T := type of H in
match T with
| reduces_in_atmost_k_steps ?lib ?t1 ?t2 ?k =>
assert (computes_to_val_like_in_max_k_steps lib t1 t2 k)
as hyp
by (split; [ complete eauto
| splr
]
)
end.
Lemma approx_star_exception {p} :
forall lib (a1 a2 e1 e2 : @NTerm p),
approx_star lib a1 a2
-> approx_star lib e1 e2
-> approx_star lib (mk_exception a1 e1) (mk_exception a2 e2).
Proof.
introv ap1 ap2.
apply approx_star_congruence; simpl; sp.
unfold approx_starbts, lblift_sub; simpl; dands; auto; introv j.
repeat (destruct n; cpx);
unfold selectbt; simpl; unfold blift_sub.
- exists ([] : list NVar) a1 a2; dands; auto; left; dands; tcsp; intro i; ginv.
- exists ([] : list NVar) e1 e2; dands; auto; left; dands; tcsp; intro i; ginv.
Qed.
(*
(* !! MOVE to computation4 *)
Lemma reduces_to_primarg_marker {o} :
forall lib nc m (l bs : list (@BTerm o)) v,
reduces_to lib (oterm (NCan nc) (nobnd (oterm (Mrk m) l) :: bs)) v
-> v = oterm (NCan nc) (nobnd (oterm (Mrk m) l) :: bs).
Proof.
introv comp.
unfold reduces_to in comp; exrepnd.
allapply @reduces_in_atmost_k_steps_primarg_marker; subst; auto.
Qed.
(* !! MOVE to approx *)
Lemma approx_ncan_primarg_marker {o} :
forall lib ncan m l bs (t : @NTerm o),
isprogram (oterm (NCan ncan) (nobnd (oterm (Mrk m) l) :: bs))
-> isprogram t
-> approx lib (oterm (NCan ncan) (nobnd (oterm (Mrk m) l) :: bs)) t.
Proof.
introv isp1 isp2.
unfold approx.
constructor.
unfold close_comput; repnd; dands; auto.
- unfold close_compute_val; introv comp.
unfold computes_to_value in comp; repnd.
apply reduces_to_primarg_marker in comp0; ginv.
- unfold close_compute_exc; introv comp.
unfold computes_to_exception in comp; repnd.
apply reduces_to_primarg_marker in comp; ginv.
- unfold close_compute_mrk; introv comp.
unfold computes_to_marker in comp; repnd.
apply reduces_to_primarg_marker in comp; ginv.
Qed.
*)
Lemma approx_star_nat {p} :
forall lib (t : @NTerm p) n,
isprogram t
-> approx_star lib (mk_nat n) t
-> computes_to_value lib t (mk_nat n).
Proof.
introv isp apr.
apply howe_lemma2 in apr; fold_terms; eauto 3 with slow.
exrepnd.
unfold approx_starbts, lblift_sub in apr1; allsimpl; repnd; cpx.
Qed.
Hint Resolve isprogram_mk_nseq : slow.
Lemma approx_star_nseq {p} :
forall lib (t : @NTerm p) s,
isprogram t
-> approx_star lib (mk_nseq s) t
-> computes_to_value lib t (mk_nseq s).
Proof.
introv isp apr.
apply howe_lemma2 in apr; fold_terms; eauto 3 with slow.
exrepnd.
unfold approx_starbts, lblift_sub in apr1; allsimpl; repnd; cpx.
Qed.
Lemma bin_rel_nterm_singleton {o} :
forall (a b : @NTerm o) R,
R a b -> bin_rel_nterm R [a] [b].
Proof.
introv h.
unfold bin_rel_nterm, binrel_list; dands; simpl; auto.
introv i; destruct n; try omega; auto.
Qed.
Hint Resolve bin_rel_nterm_singleton : slow.
(* !! Move to terms2 *)
Lemma isprogram_cbv_iff2 {p} :
forall (a : @NTerm p) v b,
isprogram (mk_cbv a v b)
<=> isprogram a # isprogram_bt (bterm [v] b).
Proof.
introv.
rw @isprogram_cbv_iff.
unfold isprogram_bt; simpl.
unfold closed_bt; simpl.
rw <- null_iff_nil.
rw null_remove_nvars.
rw subvars_prop.
split; intro k; repnd; dands; auto.
inversion k; sp.
Qed.
Lemma compute_step_cbv_iscan {o} :
forall lib (t : @NTerm o) v u,
iscan t
-> compute_step lib (mk_cbv t v u) = csuccess (subst u v t).
Proof.
introv isc.
apply iscan_implies in isc; repndors; exrepnd; subst; csunf; simpl;
unfold apply_bterm; simpl; auto.
Qed.
Lemma reduces_to_implies_approx_open1 {o} :
forall lib (t x : @NTerm o),
isprogram t
-> reduces_to lib t x
-> approx_open lib x t.
Proof.
introv isp r.
apply reduces_to_implies_approx_open in r; sp.
Qed.
Lemma compute_step_try_iscan {o} :
forall lib (t : @NTerm o) n v u,
iscan t
-> compute_step lib (mk_try t n v u)
= csuccess (mk_atom_eq n n t mk_bot).
Proof.
introv isc.
apply iscan_implies in isc; repndors; exrepnd; subst; csunf; simpl;
unfold apply_bterm; simpl; auto.
Qed.
Lemma approx_star_mk_atom_eq {o} :
forall lib (a1 a2 b1 b2 c1 c2 d1 d2 : @NTerm o),
approx_star lib a1 a2
-> approx_star lib b1 b2
-> approx_star lib c1 c2
-> approx_star lib d1 d2
-> approx_star lib (mk_atom_eq a1 b1 c1 d1) (mk_atom_eq a2 b2 c2 d2).
Proof.
introv apra aprb aprc aprd.
apply approx_star_congruence; simpl; unfold num_bvars; simpl; auto.
unfold approx_starbts, lblift_sub; simpl; dands; auto.
introv i.
unfold selectbt.
repeat (destruct n; simpl; try omega;
try (complete (apply blift_sub_nobnd_congr; auto))).
Qed.
Lemma no_change_after_val_like3 {o} :
forall lib (t : @NTerm o) k1 v1 k2,
reduces_in_atmost_k_steps lib t v1 k1
-> isprogram v1
-> isvalue_like v1
-> k1 <= k2
-> reduces_in_atmost_k_steps lib t v1 k2.
Proof.
introv r isp isv leq.
eapply no_change_after_val_like; eauto.
Qed.
Ltac extensional_ind H k hyp :=
match type of H with
| reduces_in_atmost_k_steps ?lib ?t ?v ?n =>
apply (no_change_after_val_like3 lib t n v k) in H;
auto;
make_red_val_like H hyp
end.
Lemma approx_star_bterm_numvars {o} :
forall lib op (b1 b2 : @BTerm o),
approx_star_bterm lib op b1 b2
-> num_bvars b1 = num_bvars b2.
Proof.
destruct b1, b2; introv ap.
unfold approx_star_bterm, blift_sub in ap; exrepnd.
inversion ap2; subst.
inversion ap0; subst.
unfold num_bvars; simpl; omega.
Qed.
Lemma approx_starbts_numvars {o} :
forall lib op (bs1 bs2 : list (@BTerm o)),
approx_starbts lib op bs1 bs2
-> map num_bvars bs1 = map num_bvars bs2.
Proof.
induction bs1; destruct bs2; intro ap; allsimpl; auto;
unfold approx_starbts, lblift_sub in ap; repnd; allsimpl; cpx.
pose proof (ap 0) as h; autodimp h hyp; [omega|].
unfold selectbt in h; allsimpl.
apply eq_cons; [ complete (eapply approx_star_bterm_numvars; eauto)|].
apply IHbs1.
unfold approx_starbts, lblift_sub; dands; auto; introv k.
pose proof (ap (S n)) as x; autodimp x hyp; omega.
Qed.
(*
Lemma extensional_apseq {p} : forall s : nseq, extensional_op (@NCan p (NApseq s)).
Proof.
introv Hpra Hprt Hprt' Hcv Has Hi.
applydup @compute_decompose_aux in Hcv; auto; exrepnd.
repndors; exrepnd; [|allsimpl; subst; repnd; complete ginv].
assert (m <= S k) as XX by omega.
repnud Hcv.
eapply reduces_atmost_split in XX; eauto.
remember (S k - m) as skm.
destruct skm; [omega|].
assert (skm <= k) by (subst; omega).
apply reduces_atmost_S in XX; exrepnd.
applydup @reduces_atmost_preserves_program in Hcv4; auto.
allapply @isprogram_cbv_implies; exrepnd; subst; cpx.
dorn Hcv0.
- apply iscan_implies in Hcv0; repndors; exrepnd; subst;
try (complete (csunf XX1; allsimpl; ginv));[].
csunf XX1; allsimpl.
apply compute_step_apseq_success in XX1; exrepnd; subst.
allrw <- @isprogram_apseq_iff.
apply reduces_in_atmost_k_steps_if_isvalue_like in XX0; eauto 2 with slow; subst.
apply no_change_after_value_ra with (k2:=k) in Hcv3; auto; [].
unfold lblift_sub in Has; repnd; allsimpl; cpx.
repeat(approxrelbtd); show_hyps.
allrw <- @isprogram_apseq_iff.
fold_terms.
make_red_val_like Hcv3 h.
pose proof (Hi la (mk_nat n) lar) as q.
repeat (autodimp q hyp).
apply howe_lemma2 in q; exrepnd; auto; prove_isprogram.
unfold approx_starbts, lblift_sub in q1; repnd; allsimpl; cpx.
clear q1.
fold_terms.
apply approx_open_implies_approx_star.
apply approx_implies_approx_open.
apply reduces_to_implies_approx_eauto; prove_isprogram.
unfold computes_to_value in q0; repnd.
eapply reduces_to_trans;[apply reduces_to_prinarg;exact q1|].
apply reduces_to_if_step; csunf; simpl.
rw @Znat.Nat2Z.id.
boolvar; try omega; auto.
- allapply @isprogram_apseq_implies; exrepnd; ginv.
apply isexc_implies in Hcv0; auto; exrepnd; subst.
csunf XX1; allsimpl; ginv.
apply reduces_atmost_exc in XX0; subst.
clear Hcv.
apply no_change_after_val_like with (k2:=k) in Hcv3; try splr.
duplicate Has.
unfold lblift_sub in Has; repnd; allsimpl.
repeat(approxrelbtd). show_hyps.
apply approx_star_bterm_nobnd2 in Has0bt.
make_red_val_like Hcv3 h.
unfold extensional_op_ind in Hi.
apply Hi with (v := a2) in h; auto; prove_isprogram.
apply howe_lemma2_exc in h; exrepnd; auto; prove_isprogram.
apply @approx_star_open_trans with (b := mk_exception a' e').
apply approx_star_exception; auto.
apply approx_implies_approx_open.
apply computes_to_exception_implies_approx; auto; prove_isprogram.
allrw @fold_cbv.
allrw @computes_to_exception_as_reduces_to.
apply @reduces_to_trans with (b := mk_apseq s (mk_exception a' e')).
apply reduces_to_prinarg; auto.
apply reduces_to_if_step; reflexivity.
Qed.
*)
(*
(* !! MOVE to computation4 *)
Lemma computes_to_val_like_in_max_k_steps_primarg_marker {o} :
forall (lib : @library o) k nc mrk l bs v,
computes_to_val_like_in_max_k_steps
lib
(oterm (NCan nc) (nobnd (oterm (Mrk mrk) l) :: bs))
v k
-> False.
Proof.
introv h.
unfold computes_to_val_like_in_max_k_steps in h; repnd.
apply reduces_in_atmost_k_steps_primarg_marker in h0; subst.
dorn h; sp.
Qed.
*)
(*
Lemma lblift_approx_star_implies_sub_range_rel {o} :
forall lib (bs1 bs2 : list (@BTerm o)) vars,
lblift (approx_star lib) bs1 bs2
-> sub_range_rel
(approx_star lib)
(mk_abs_subst vars bs1)
(mk_abs_subst vars bs2).
Proof.
induction bs1; destruct bs2; introv ap; allsimpl; auto.
- rw @mk_abs_subst_nil_r; simpl; auto.
- unfold lblift in ap; cpx.
- unfold lblift in ap; cpx.
- destruct vars; simpl; auto.
destruct a as [l1 t1]; destruct b as [l2 t2].
unfold lblift in ap; simpl in ap; repnd; cpx.
pose proof (ap 0) as h; autodimp h hyp; [omega|].
unfold selectbt in h; simpl in h.
unfold blift in h; exrepnd.
inversion h2; inversion h0; subst; allsimpl; cpx; GC.
destruct l1; destruct l2; allsimpl; cpx; GC.
allunfold @var_ren; allsimpl.
allrw @lsubst_nil.
dands; eauto with slow.
apply IHbs1.
unfold lblift; dands; auto; introv k.
pose proof (ap (S n0)) as x; autodimp x hyp; omega.
Qed.
*)
(*
Inductive so_approx_star {o} :
@library o -> @SOTerm o -> @SOTerm o -> [univ] :=
| soapsv:
forall lib v t2,
so_approx_open lib (sovar v ts1) t2
-> so_approx_star lib (sovar v ts2) t2
| soapso:
forall lib
(op : Opid) (t2: NTerm)
(lbt1 lbt1' : list BTerm),
length lbt1 = length lbt1'
-> lblift (approx_star lib) lbt1 lbt1'
-> approx_open lib (oterm op lbt1') t2
-> approx_star lib (oterm op lbt1) t2.
*)
(*
Lemma computes_to_val_or_exc_in_max_k_steps_marker {o} :
forall lib (k : nat) mrk (l : list (@BTerm o)) (v : NTerm),
computes_to_val_or_exc_in_max_k_steps lib (oterm (Mrk mrk) l) v k
-> False.
Proof.
introv comp.
unfold computes_to_val_or_exc_in_max_k_steps in comp; repnd.
apply reduces_in_atmost_k_steps_marker in comp0; subst.
dorn comp; sp.
Qed.
*)
(*
Lemma computes_to_val_like_in_max_k_steps_marker {o} :
forall lib (k : nat) mrk (l : list (@BTerm o)) (v : NTerm),
computes_to_val_like_in_max_k_steps lib (oterm (Mrk mrk) l) v k
-> v = oterm (Mrk mrk) l.
Proof.
induction k; introv comp.
- rw @computes_to_val_like_in_max_k_steps_0 in comp; repnd; auto.
- rw @computes_to_val_like_in_max_k_steps_S in comp; exrepnd.
simpl in comp1; ginv.
apply IHk in comp0; auto.
Qed.
Lemma nuprl_extensional_mrk {p} :
forall m : marker, @extensional_op p (Mrk m).
Proof.
introv.
unfold extensional_op.
introv isp1 isp2 isp3 comp ap ext.
apply computes_to_val_like_in_max_k_steps_marker in comp; subst.
apply ismrk_implies in isp2; tcsp; exrepnd.
inversion isp0; subst.
apply ismrk_implies in isp3; tcsp; exrepnd.
inversion isp2; subst; fold_terms.
apply (apso _ _ _ [] []); simpl; auto; fold_terms.
apply approx_implies_approx_open.
unfold approx; constructor.
unfold close_comput; dands; auto.
- unfold close_compute_val; introv comp.
unfold computes_to_value in comp; repnd.
apply reduces_to_marker in comp0; tcsp.
inversion comp0.
- unfold close_compute_exc; introv comp.
unfold computes_to_exception in comp; repnd.
apply reduces_to_marker in comp; tcsp.
inversion comp.
- unfold close_compute_mrk; introv comp.
unfold computes_to_marker in comp; repnd.
apply reduces_to_marker in comp; tcsp.
inversion comp; subst.
apply compute_to_marker_mrk.
Qed.
*)
Lemma computes_to_val_like_in_max_k_steps_parallel_implies2 {o} :
forall lib k (bs : list (@BTerm o)) v,
computes_to_val_like_in_max_k_steps lib (oterm (NCan NParallel) bs) v k
-> {x : NTerm
& {u : NTerm
& {bs' : list BTerm
& {m : nat
& k = S m
# bs = nobnd u :: bs'
# computes_to_val_like_in_max_k_steps lib u x m
# {c : CanonicalOp & {bs : list BTerm & x = oterm (Can c) bs # v = mk_axiom}}
[+]
(isexc x # x = v)}}}}.
Proof.
induction k; introv comp; simpl.
- allunfold @computes_to_val_like_in_max_k_steps.
rw @reduces_in_atmost_k_steps_0 in comp; repnd; subst.
unfold isvalue_like in comp; allsimpl; sp.
- rw @computes_to_val_like_in_max_k_steps_S in comp; exrepnd.
csunf comp1; allsimpl.
destruct bs as [|b bs]; ginv.
destruct b as [l t].
destruct l; ginv.
destruct t as [z|f|op bts]; ginv;[].
dopid op as [can|ncan|exc|abs] Case; ginv.
+ Case "Can".
apply compute_step_parallel_success in comp1; subst.
apply computes_to_val_like_in_max_k_steps_can_iff in comp0; subst.
exists (oterm (Can can) bts) (oterm (Can can) bts) bs k; dands; auto.
{ apply computes_to_val_like_in_max_k_steps_can_iff; sp. }
left; eexists; eexists; dands; eauto.
+ Case "NCan".
remember (compute_step lib (oterm (NCan ncan) bts)) as comp'; destruct comp'; ginv.
apply IHk in comp0; clear IHk; exrepnd; subst; allunfold @nobnd; ginv.
exists x (oterm (NCan ncan) bts) bs' (S m); dands; auto.
rw @computes_to_val_like_in_max_k_steps_S.
exists u; auto.
+ Case "Exc".
apply computes_to_val_like_in_max_k_steps_exc in comp0; subst.
exists (oterm Exc bts) (oterm Exc bts) bs k; dands; auto.
apply computes_to_val_like_in_max_k_steps_exc_iff; sp.
+ Case "Abs".
remember (compute_step lib (oterm (Abs abs) bts)) as comp'; destruct comp'; ginv.
apply IHk in comp0; clear IHk; exrepnd; subst.
allunfold @nobnd; ginv.
exists x (oterm (Abs abs) bts) bs' (S m); dands; auto.
rw @computes_to_val_like_in_max_k_steps_S.
exists u; auto.
Qed.
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_bram_v6.v
// Version : 2.3
//--
//-- Description: BlockRAM module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_bram_v6
#(
parameter DOB_REG = 0,// 1 use the output register 0 don't use the output register
parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP)
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = "NO_CHANGE";
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if (WIDTH == 72) begin : use_ramb36sdp
// use RAMB36SDP if the width is 72
RAMB36SDP #(
.DO_REG (DOB_REG)
)
ramb36sdp(
.WRCLK (user_clk_i),
.SSR (1'b0),
.WRADDR (waddr_i[ADDR_MSB:0]),
.DI (wdata_i[D_MSB:0]),
.DIP (wdata_i[DP_MSB:DP_LSB]),
.WREN (wen_i),
.WE ({8{wen_i}}),
.DBITERR (),
.ECCPARITY (),
.SBITERR (),
.RDCLK (user_clk_i),
.RDADDR (raddr_i[ADDR_MSB:0]),
.DO (rdata_o[D_MSB:0]),
.DOP (rdata_o[DP_MSB:DP_LSB]),
.RDEN (ren_i),
.REGCE (rce_i)
);
// use RAMB36's if the width is 4, 9, 18, or 36
end else if (WIDTH == 36) begin : use_ramb36
RAMB36 #(
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA (wdata_i[D_MSB:0]),
.DIPA (wdata_i[DP_MSB:DP_LSB]),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.DIB (32'b0),
.DIPB ( 4'b0),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB (rdata_o[D_MSB:0]),
.DOPB (rdata_o[DP_MSB:DP_LSB]),
.ENB (ren_i),
.REGCEB (rce_i)
);
end else if (WIDTH < 36 && WIDTH > 4) begin : use_ramb36
wire [31 - D_MSB - 1 : 0] dob_unused;
wire [ 4 - DPW - 1 : 0] dopb_unused;
RAMB36 #(
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
.DIPA ({{ 4 - DPW {1'b0}},wdata_i[DP_MSB:DP_LSB]}),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.DIB (32'b0),
.DIPB ( 4'b0),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB ({dob_unused, rdata_o[D_MSB:0]}),
.DOPB ({dopb_unused, rdata_o[DP_MSB:DP_LSB]}),
.ENB (ren_i),
.REGCEB (rce_i)
);
end else if (WIDTH == 4) begin : use_ramb36
wire [31 - D_MSB - 1 : 0] dob_unused;
RAMB36 #(
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
//.DIPA (wdata_i[DP_MSB:DP_LSB]),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB ({dob_unused,rdata_o[D_MSB:0]}),
//.DOPB (rdata_o[DP_MSB:DP_LSB]),
.ENB (ren_i),
.REGCEB (rce_i)
);
end // block: use_ramb36
endgenerate
endmodule // pcie_bram_v6
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBP_1_V
`define SKY130_FD_SC_HD__DLRBP_1_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBP_1_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ae
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ae.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_ae.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ae
//
// No user `defines in this module
module ent_ae
//
// Generated Module inst_ae
//
(
port_ae_2, // Use internally test2, no port generated
port_ae_5, // Bus, single bits go to outside
port_ae_6, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_i_ae, // Input Bus
sig_o_ae // Output Bus
);
// Generated Module Inputs:
input [4:0] port_ae_2;
input [3:0] port_ae_5;
input [3:0] port_ae_6;
input [5:0] sig_07;
input [8:2] sig_08;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output [7:0] sig_o_ae;
// Generated Wires:
wire [4:0] port_ae_2;
wire [3:0] port_ae_5;
wire [3:0] port_ae_6;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [6:0] sig_i_ae;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ae
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:07:47 05/24/2015
// Design Name:
// Module Name: divide_clock
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module divide_clock(
input in_clk,
input [15:0] divider_factor,
output reg out_clk
);
reg [31:0] m;
reg [31:0] divider;
reg [31:0] half_divider;
initial begin
m = 0;
divider = 2;
half_divider = 1;
end
always @(posedge in_clk) begin
if (m < divider - 1)
m <= m + 1;
else
m <= 0;
end
always @(in_clk) begin
if (divider_factor == 0)
out_clk <= in_clk;
else if (m < half_divider)
out_clk <= 1;
else
out_clk <= 0;
end
always @(posedge in_clk) begin
divider = 2**divider_factor;
half_divider = divider/2;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A2111O_PP_BLACKBOX_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111O_PP_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.68d
// \ \ Application: netgen
// / / Filename: uart_timesim.v
// /___/ /\ Timestamp: Mon Oct 27 22:57:58 2014
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -s 5 -pcf uart.pcf -sdf_anno true -sdf_path netgen/par -insert_glbl true -insert_pp_buffers true -w -dir netgen/par -ofmt verilog -sim uart.ncd uart_timesim.v
// Device : 3s100ecp132-5 (PRODUCTION 1.27 2013-06-08)
// Input file : uart.ncd
// Output file : C:\Users\James\Desktop\iDriveSync\IDrive-Sync\DSD LAB\uart\netgen\par\uart_timesim.v
// # of Modules : 1
// Design Name : uart
// Xilinx : C:\Xilinx\14.6\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module uart (
clk, reset, rx, fsm, tx, Led
);
input clk;
input reset;
input rx;
input fsm;
output tx;
output [7 : 0] Led;
wire \in/ld_shift_0 ;
wire clk_BUFGP;
wire reset_IBUF_1366;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1377 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1378 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1379 ;
wire N13;
wire rx_IBUF_1384;
wire \in/baud1/baud_1387 ;
wire \in/pstate_mux0000<2>4_1389 ;
wire \in/pstate_mux0000<2>10_0 ;
wire \in/in_two_1395 ;
wire \in/finish ;
wire \in/loaded_mux0000_0 ;
wire \in/pstate_mux0000<3>15_0 ;
wire \in/pstate_mux0000<3>2_1402 ;
wire \in/bitcounter_not0001_0 ;
wire \in/N13 ;
wire \in/bittime_0 ;
wire \in/empty ;
wire \in/full ;
wire \in/frame_ready_1417 ;
wire \out/bitcounter_not0001_0 ;
wire \out/N2 ;
wire \out/pstate_FSM_FFd2_1423 ;
wire \out/pstate_FSM_FFd1_1425 ;
wire \out/baud1/baud_cmp_eq0000822_0 ;
wire \out/baud1/baud_1432 ;
wire \out/N8_0 ;
wire N23;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1442 ;
wire \in/fifo1/N9_0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ;
wire N21;
wire N31_0;
wire \in/baud1/baud_cmp_eq0000810_0 ;
wire \in/baud1/baud_cmp_eq0000_0 ;
wire \in/fifo1/N01_0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1483 ;
wire \in/rd_fifo ;
wire \in/fifo1/N3_0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1488 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 ;
wire N46;
wire \in/load_1503 ;
wire \out/bittime_0 ;
wire N15_0;
wire N40_0;
wire N50_0;
wire pstate_FSM_FFd4_1516;
wire pstate_FSM_FFd2_1518;
wire N54_0;
wire \in/fifo1/N7_0 ;
wire N27_0;
wire \out/ld_shift ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_1532 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_1533 ;
wire \out/empty ;
wire N34_0;
wire N33;
wire \out/baud1/N01 ;
wire N29_0;
wire N9;
wire pstate_FSM_FFd3_1543;
wire \in/fifo1/N2_0 ;
wire \out/baud1/baud_cmp_eq0000_0 ;
wire N25;
wire \in/loaded_1548 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_0 ;
wire fsm_IBUF_1559;
wire N51;
wire N53;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168/O ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073_0 ;
wire \out/baud1/baud_cmp_eq0000810_1573 ;
wire \out/pstate_FSM_FFd1-In3_SW0/O ;
wire N38;
wire \Madd_data_add0000_xor<4>12_SW0/O ;
wire \Madd_data_add0000_xor<5>11_SW0/O ;
wire \Madd_data_add0000_xor<6>12_SW0/O ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000029/O ;
wire \in/baud1/baud_cmp_eq0000822/O ;
wire \in/fifo1/N5_0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005/O ;
wire \in/fifo1/N11_0 ;
wire \in/baud1/Madd_timer_addsub0000_cy[3] ;
wire \in/baud1/Madd_timer_addsub0000_cy<5>_0 ;
wire \out/baud1/Madd_timer_addsub0000_cy[3] ;
wire \out/baud1/Madd_timer_addsub0000_cy<5>_0 ;
wire \out/N7 ;
wire \out/shift_out_not0001_0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000021/O ;
wire \out/bitcounter_not0001_SW0/O ;
wire \in/pstate_mux0000<2>18/O ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O ;
wire \in/baud1/N01 ;
wire \in/dout<2>1/O ;
wire \Madd_data_add0000_lut<1>_0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_1610 ;
wire N11;
wire \in/control<2>/DYMUX_1690 ;
wire \in/control<2>/CLKINV_1687 ;
wire \in/control<2>/CEINV_1686 ;
wire \in/shift<5>/DXMUX_1717 ;
wire \in/shift<5>/DYMUX_1709 ;
wire \in/shift<5>/SRINV_1707 ;
wire \in/shift<5>/CLKINV_1706 ;
wire \in/shift<5>/CEINV_1705 ;
wire \in/control<0>/DYMUX_1647 ;
wire \in/control<0>/BYINV_1646 ;
wire \in/control<0>/CLKINV_1644 ;
wire \in/control<0>/CEINV_1643 ;
wire \in/shift<3>/DXMUX_1674 ;
wire \in/shift<3>/DYMUX_1666 ;
wire \in/shift<3>/SRINV_1664 ;
wire \in/shift<3>/CLKINV_1663 ;
wire \in/shift<3>/CEINV_1662 ;
wire \in/shift<1>/DXMUX_1631 ;
wire \in/shift<1>/DYMUX_1623 ;
wire \in/shift<1>/SRINV_1621 ;
wire \in/shift<1>/CLKINV_1620 ;
wire \in/shift<1>/CEINV_1619 ;
wire \in/bitcounter<3>/DXMUX_2360 ;
wire \in/Mcount_bitcounter3 ;
wire N21_pack_3;
wire \in/bitcounter<3>/CLKINV_2343 ;
wire \in/bitcounter<3>/CEINV_2342 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2299 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX_2290 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2280 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2279 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2278 ;
wire \out/baud1/baud_cmp_eq0000822_2130 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2219 ;
wire \in/fifo1/N9 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX_2205 ;
wire \in/fifo1/Result<1>1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2195 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2194 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2193 ;
wire \out/pstate_FSM_FFd1/DXMUX_2161 ;
wire \out/pstate_FSM_FFd1-In_2158 ;
wire N23_pack_2;
wire \out/pstate_FSM_FFd1/CLKINV_2145 ;
wire \in/bitcounter<0>/DXMUX_2040 ;
wire \in/Mcount_bitcounter ;
wire \in/bittime ;
wire \in/bitcounter<0>/CLKINV_2023 ;
wire \in/bitcounter<0>/CEINV_2022 ;
wire dout_1__and0001;
wire dout_1__and0000;
wire N31;
wire \in/baud1/baud_cmp_eq0000810_2380 ;
wire \in/fifo1/N01 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_2423 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ;
wire \in/baud1/baud/DYMUX_2401 ;
wire \in/baud1/baud/CLKINV_2398 ;
wire \in/baud1/baud/CEINV_2397 ;
wire \in/bitcounter_not0001 ;
wire \out/to_shift<1>/DXMUX_2451 ;
wire \out/to_shift<1>/DYMUX_2444 ;
wire \out/to_shift<1>/SRINV_2442 ;
wire \out/to_shift<1>/CLKINV_2441 ;
wire \out/to_shift<1>/CEINV_2440 ;
wire \out/bitcounter<0>/DXMUX_2113 ;
wire \out/Mcount_bitcounter ;
wire \out/N2_pack_2 ;
wire \out/bitcounter<0>/CLKINV_2096 ;
wire \out/bitcounter<0>/CEINV_2095 ;
wire \in/control<1>/DXMUX_2076 ;
wire \in/control_1_mux0000 ;
wire \in/control_2_not0001 ;
wire \in/control<1>/CLKINV_2057 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DXMUX_2264 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_2261 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DYMUX_2250 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV_2240 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV_2239 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV_2238 ;
wire \in/empty/DYMUX_2486 ;
wire \in/empty/CLKINV_2484 ;
wire \out/to_shift<3>/DXMUX_2520 ;
wire \out/to_shift<3>/DYMUX_2513 ;
wire \out/to_shift<3>/SRINV_2511 ;
wire \out/to_shift<3>/CLKINV_2510 ;
wire \out/to_shift<3>/CEINV_2509 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \in/fifo1/N3 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX_2789 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX_2782 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_2780 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_2779 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_2778 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DXMUX_2875 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BXINV_2874 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DYMUX_2868 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BYINV_2867 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/SRINV_2866 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/CLKINV_2865 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_2839 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_2830 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_2828 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_2827 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_2826 ;
wire \out/bitcounter<3>/DXMUX_3021 ;
wire \out/Mcount_bitcounter3 ;
wire N33_pack_2;
wire \out/bitcounter<3>/CLKINV_3005 ;
wire \out/bitcounter<3>/CEINV_3004 ;
wire \out/bittimer<0>/DXMUX_2639 ;
wire N15;
wire \out/bittimer<0>/DYMUX_2622 ;
wire \out/bittimer<0>/SRINV_2612 ;
wire \out/bittimer<0>/CLKINV_2611 ;
wire \out/bittimer<0>/CEINV_2610 ;
wire N40;
wire N50;
wire \pstate_FSM_FFd4/DYMUX_2926 ;
wire \pstate_FSM_FFd4/BYINV_2925 ;
wire \pstate_FSM_FFd4/SRINV_2924 ;
wire \pstate_FSM_FFd4/CLKINV_2923 ;
wire \out/to_shift<5>/DXMUX_2544 ;
wire \out/to_shift<5>/DYMUX_2537 ;
wire \out/to_shift<5>/SRINV_2535 ;
wire \out/to_shift<5>/CLKINV_2534 ;
wire \out/to_shift<5>/CEINV_2533 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX_2739 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX_2730 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_2728 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_2727 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_2726 ;
wire \in/loaded_not0001 ;
wire N46_pack_1;
wire \in/fifo1/N7 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_2813 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_2806 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_2804 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_2803 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_2802 ;
wire \in/bitcounter<2>/FFX/RST ;
wire \in/bitcounter<2>/DXMUX_2911 ;
wire \in/Mcount_bitcounter2 ;
wire N27;
wire \in/bitcounter<2>/CLKINV_2892 ;
wire \in/bitcounter<2>/CEINV_2891 ;
wire \out/bitcounter<3>/FFX/RSTAND_3027 ;
wire \out/pstate_FSM_FFd2/FFX/RST ;
wire \out/pstate_FSM_FFd2/DXMUX_2984 ;
wire \out/pstate_FSM_FFd2-In ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ;
wire \out/pstate_FSM_FFd2/CLKINV_2968 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \out/ld_shift_pack_1 ;
wire \out/to_shift<7>/DXMUX_2568 ;
wire \out/to_shift<7>/DYMUX_2561 ;
wire \out/to_shift<7>/SRINV_2559 ;
wire \out/to_shift<7>/CLKINV_2558 ;
wire \out/to_shift<7>/CEINV_2557 ;
wire \in/wr_control ;
wire N54;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DXMUX_2689 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DYMUX_2682 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV_2680 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV_2679 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV_2678 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX_2713 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX_2706 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_2704 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_2703 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_2702 ;
wire \out/bitcounter<2>/FFX/RST ;
wire \out/bitcounter<2>/DXMUX_3059 ;
wire \out/Mcount_bitcounter2 ;
wire N34;
wire \out/bitcounter<2>/CLKINV_3042 ;
wire \out/bitcounter<2>/CEINV_3041 ;
wire \in/frame_error<7>/DXMUX_1990 ;
wire \in/frame_error<7>/DYMUX_1981 ;
wire \in/frame_error<7>/SRINV_1979 ;
wire \in/frame_error<7>/CLKINV_1978 ;
wire \in/frame_error<7>/CEINV_1977 ;
wire \in/frame_error<3>/DXMUX_1934 ;
wire \in/frame_error<3>/DYMUX_1925 ;
wire \in/frame_error<3>/SRINV_1923 ;
wire \in/frame_error<3>/CLKINV_1922 ;
wire \in/frame_error<3>/CEINV_1921 ;
wire \in/pstate<1>/DXMUX_1768 ;
wire N13_pack_2;
wire \in/pstate<1>/CLKINV_1751 ;
wire \in/shift<9>/DXMUX_1844 ;
wire \in/shift<9>/DYMUX_1836 ;
wire \in/shift<9>/SRINV_1834 ;
wire \in/shift<9>/CLKINV_1833 ;
wire \in/shift<9>/CEINV_1832 ;
wire \in/pstate<2>/DXMUX_1907 ;
wire \in/pstate_mux0000<3>2_pack_1 ;
wire \in/pstate<2>/CLKINV_1889 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DXMUX_1736 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DYMUX_1731 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV_1729 ;
wire \in/pstate_mux0000<2>10_1822 ;
wire \in/pstate_mux0000<2>4_pack_1 ;
wire \in/shift<7>/DXMUX_1794 ;
wire \in/shift<7>/DYMUX_1786 ;
wire \in/shift<7>/SRINV_1784 ;
wire \in/shift<7>/CLKINV_1783 ;
wire \in/shift<7>/CEINV_1782 ;
wire \in/frame_error<1>/DXMUX_1871 ;
wire \in/frame_error<1>/DYMUX_1862 ;
wire \in/frame_error<1>/SRINV_1860 ;
wire \in/frame_error<1>/CLKINV_1859 ;
wire \in/frame_error<1>/CEINV_1858 ;
wire \in/frame_error<5>/DXMUX_1962 ;
wire \in/frame_error<5>/DYMUX_1953 ;
wire \in/frame_error<5>/SRINV_1951 ;
wire \in/frame_error<5>/CLKINV_1950 ;
wire \in/frame_error<5>/CEINV_1949 ;
wire \rx/INBUF ;
wire \fsm/INBUF ;
wire \reset/INBUF ;
wire \Led<0>/O ;
wire \tx/O ;
wire \Led<1>/O ;
wire \Led<7>/O ;
wire \pstate_FSM_FFd2/FFX/RST ;
wire \pstate_FSM_FFd2/DXMUX_3130 ;
wire \pstate_FSM_FFd2-In_3127 ;
wire N9_pack_2;
wire \pstate_FSM_FFd2/CLKINV_3112 ;
wire \in/fifo1/N2 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \in/pstate<5>/FFY/RST ;
wire \in/pstate<5>/DYMUX_3224 ;
wire \in/pstate<5>/CLKINV_3221 ;
wire \out/empty/DYMUX_3259 ;
wire \out/empty/CLKINV_3256 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_3240 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \Led<6>/O ;
wire \Led<5>/O ;
wire \clk/INBUF ;
wire \Led<3>/O ;
wire \out/baud1/timer<2>/FFX/RST ;
wire \out/baud1/timer<2>/DXMUX_3095 ;
wire N29;
wire \out/baud1/timer<2>/CLKINV_3077 ;
wire \Led<4>/O ;
wire \out/baud1/baud/FFY/RST ;
wire \out/baud1/baud/DYMUX_3170 ;
wire \out/baud1/baud/CLKINV_3167 ;
wire \out/baud1/baud/CEINV_3166 ;
wire \in/full/DYMUX_3248 ;
wire \in/full/CLKINV_3246 ;
wire \in/loaded/FFX/RST ;
wire \in/loaded/DXMUX_3209 ;
wire \in/loaded/FXMUX_3208 ;
wire \in/loaded_mux0000_3206 ;
wire N25_pack_1;
wire \in/loaded/CLKINVNOT ;
wire \in/loaded/CEINV_3191 ;
wire \Led<2>/O ;
wire \clk_BUFGP/BUFG/S_INVNOT ;
wire \clk_BUFGP/BUFG/I0_INV ;
wire \N51/F5MUX_3779 ;
wire N57;
wire \N51/BXINV_3772 ;
wire N56;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073_4089 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000029/O_pack_1 ;
wire \N53/F5MUX_3804 ;
wire N59;
wire \N53/BXINV_3797 ;
wire N58;
wire \data<3>/DXMUX_3749 ;
wire \data<3>/F5MUX_3747 ;
wire N61;
wire \data<3>/BXINV_3739 ;
wire N60;
wire \data<3>/CLKINV_3731 ;
wire \data<3>/CEINV_3730 ;
wire \out/baud1/timer<3>/DXMUX_3865 ;
wire \out/baud1/N01_pack_2 ;
wire \out/baud1/timer<3>/CLKINV_3849 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB3 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB2 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB1 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB31 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB30 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB29 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB28 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB27 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB26 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB23 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB22 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB21 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB20 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB19 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB18 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB15 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB14 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB13 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB12 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB11 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB10 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB7 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB6 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB5 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB4 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB3 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB2 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA3 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA2 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA1 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA31 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA30 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA29 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA28 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA27 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA26 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA25 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA24 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA23 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA22 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA21 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA20 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA19 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA18 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA17 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA16 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA15 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA14 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA13 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA12 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA11 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA10 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA9 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA8 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA7 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA6 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA5 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA4 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA3 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA2 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA1 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPA3 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPA2 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPA1 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPA0 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA31 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA30 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA29 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA28 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA27 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA26 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA25 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA24 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA23 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA22 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA21 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA20 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA19 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA18 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA17 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA16 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA15 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA14 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA13 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA12 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA11 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA10 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA9 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA8 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA7 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA6 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA5 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA4 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA3 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA2 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA1 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB3 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB2 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB31 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB30 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB29 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB28 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB27 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB26 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB25 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB23 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB22 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB21 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB20 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB19 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB18 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB15 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB14 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB13 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB12 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB11 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB10 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB7 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB6 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB5 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB4 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB3 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA3 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA2 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA31 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA30 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA29 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA28 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA27 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA26 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA25 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA24 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA23 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA22 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA21 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA20 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA19 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA18 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA17 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA16 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA15 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA14 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA13 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA12 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA11 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA10 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA9 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA8 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA7 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA6 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA5 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA4 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA3 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA2 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB3 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB2 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB0 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB31 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB30 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB29 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB28 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB27 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB26 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB25 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB24 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB23 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB22 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB21 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB20 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB19 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB18 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB17 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB16 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB15 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB14 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB13 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB12 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB11 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB10 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB9 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB8 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB7 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB6 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB5 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB4 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB3 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB2 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB0 ;
wire \out/N8 ;
wire \out/pstate_FSM_FFd1-In3_SW0/O_pack_1 ;
wire \data<5>/DXMUX_3963 ;
wire \data_add0000[5] ;
wire \Madd_data_add0000_xor<5>11_SW0/O_pack_1 ;
wire \data<5>/CLKINV_3947 ;
wire \data<5>/CEINV_3946 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_3833 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FXMUX_3832 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168/O_pack_1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_3818 ;
wire \data<4>/DXMUX_3926 ;
wire \data_add0000[4] ;
wire \Madd_data_add0000_xor<4>12_SW0/O_pack_1 ;
wire \data<4>/CLKINV_3909 ;
wire \data<4>/CEINV_3908 ;
wire \data<6>/DXMUX_4000 ;
wire \data_add0000[6] ;
wire \Madd_data_add0000_xor<6>12_SW0/O_pack_1 ;
wire \data<6>/CLKINV_3982 ;
wire \data<6>/CEINV_3981 ;
wire \out/baud1/baud_cmp_eq0000 ;
wire \out/baud1/baud_cmp_eq0000810_pack_1 ;
wire \data<7>/DXMUX_4061 ;
wire \data_add0000[7] ;
wire N38_pack_1;
wire \data<7>/CLKINV_4045 ;
wire \data<7>/CEINV_4044 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_4143 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_4142 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005/O_pack_2 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_4128 ;
wire \in/baud1/baud_cmp_eq0000 ;
wire \in/baud1/baud_cmp_eq0000822/O_pack_1 ;
wire \in/pstate_mux0000<3>15_4429 ;
wire \in/N13_pack_1 ;
wire \data<1>/DXMUX_4332 ;
wire \data_add0000[1] ;
wire \Madd_data_add0000_cy<0>_pack_2 ;
wire \data<1>/CLKINV_4315 ;
wire \data<1>/CEINV_4314 ;
wire \out/bitcounter<1>/DYMUX_4575 ;
wire \out/Mcount_bitcounter1 ;
wire \out/bitcounter<1>/CLKINV_4565 ;
wire \out/bitcounter<1>/CEINV_4564 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_4367 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or0000 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O_pack_2 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_4349 ;
wire \out/shift_out<3>/DXMUX_4748 ;
wire \out/shift_out<3>/DYMUX_4734 ;
wire \out/shift_out<3>/SRINV_4726 ;
wire \out/shift_out<3>/CLKINV_4725 ;
wire \out/shift_out<3>/CEINV_4724 ;
wire \in/bittimer<3>/DXMUX_4507 ;
wire \in/bittimer<3>/DYMUX_4492 ;
wire \in/bittimer<3>/SRINV_4483 ;
wire \in/bittimer<3>/CLKINV_4482 ;
wire \in/bittimer<3>/CEINV_4481 ;
wire \out/baud1/timer<1>/DXMUX_4550 ;
wire \out/baud1/timer<1>/DYMUX_4535 ;
wire \out/baud1/timer<1>/SRINV_4527 ;
wire \out/baud1/timer<1>/CLKINV_4526 ;
wire \out/shift_out<1>/DXMUX_4704 ;
wire \out/shift_out<1>/DYMUX_4690 ;
wire \out/shift_out<1>/SRINV_4681 ;
wire \out/shift_out<1>/CLKINV_4680 ;
wire \out/shift_out<1>/CEINV_4679 ;
wire \in/baud1/timer<0>/DXMUX_4401 ;
wire \in/baud1/N01_pack_2 ;
wire \in/baud1/timer<0>/CLKINV_4383 ;
wire \in/pstate<3>/DXMUX_4295 ;
wire \in/pstate_mux0000<2>18/O_pack_1 ;
wire \in/pstate<3>/CLKINV_4278 ;
wire \data<2>/DXMUX_4462 ;
wire \data_add0000[2] ;
wire \in/dout<2>1/O_pack_1 ;
wire \data<2>/CLKINV_4444 ;
wire \data<2>/CEINV_4443 ;
wire \out/baud1/timer<5>/DXMUX_4618 ;
wire \out/baud1/timer<5>/DYMUX_4604 ;
wire \out/baud1/timer<5>/SRINV_4595 ;
wire \out/baud1/timer<5>/CLKINV_4594 ;
wire \out/baud1/timer<7>/DXMUX_4660 ;
wire \out/baud1/timer<7>/DYMUX_4646 ;
wire \out/baud1/timer<7>/SRINV_4637 ;
wire \out/baud1/timer<7>/CLKINV_4636 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_4930 ;
wire \in/fifo1/Result<3>1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_4917 ;
wire \in/fifo1/Result<2>1 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_4908 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_4907 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_4906 ;
wire \trans<1>/DXMUX_5224 ;
wire Mcount_trans1;
wire \trans<1>/DYMUX_5210 ;
wire Mcount_trans;
wire \trans<1>/SRINV_5201 ;
wire \trans<1>/CLKINV_5200 ;
wire \data<0>/DYMUX_5042 ;
wire \data_add0000[0] ;
wire \data<0>/CLKINV_5032 ;
wire \data<0>/CEINV_5031 ;
wire \out/shift_out<7>/DXMUX_4836 ;
wire \out/shift_out<7>/DYMUX_4822 ;
wire \out/shift_out<7>/SRINV_4814 ;
wire \out/shift_out<7>/CLKINV_4813 ;
wire \out/shift_out<7>/CEINV_4812 ;
wire \out/shift_out<8>/DYMUX_4887 ;
wire \out/shift_out<8>/CLKINV_4877 ;
wire \out/shift_out<8>/CEINV_4876 ;
wire \out/shift_out<5>/DXMUX_4792 ;
wire \out/shift_out<5>/DYMUX_4778 ;
wire \out/shift_out<5>/SRINV_4770 ;
wire \out/shift_out<5>/CLKINV_4769 ;
wire \out/shift_out<5>/CEINV_4768 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_5084 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DYMUX_5070 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_5062 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_5061 ;
wire \out/bittimer<3>/DXMUX_5129 ;
wire \out/bittimer<3>/DYMUX_5114 ;
wire \out/bittimer<3>/SRINV_5105 ;
wire \out/bittimer<3>/CLKINV_5104 ;
wire \out/bittimer<3>/CEINV_5103 ;
wire \pstate_FSM_FFd3/DYMUX_5153 ;
wire \pstate_FSM_FFd3-In ;
wire \pstate_FSM_FFd3/CLKINV_5143 ;
wire \in/in_two/DYMUX_5185 ;
wire \in/Mshreg_in_two ;
wire \in/in_two/DIG_MUX_5174 ;
wire \in/in_two/CLKINV_5172 ;
wire \in/in_two/WSG ;
wire \in/in_two/SRINV_5168 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_5016 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_5001 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_4992 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_4991 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_4990 ;
wire \in/frame_error<8>/DYMUX_4861 ;
wire \in/frame_error_8_or0000 ;
wire \in/frame_error<8>/CLKINV_4850 ;
wire \in/frame_error<8>/CEINV_4849 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_4972 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_4959 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_4950 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_4949 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_4948 ;
wire \in/baud1/Madd_timer_addsub0000_cy[5] ;
wire \in/baud1/Madd_timer_addsub0000_cy<3>_pack_1 ;
wire \out/bitcounter_not0001_4264 ;
wire \out/bitcounter_not0001_SW0/O_pack_1 ;
wire \in/fifo1/N5 ;
wire \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000021/O_pack_1 ;
wire \out/baud1/Madd_timer_addsub0000_cy[5] ;
wire \out/baud1/Madd_timer_addsub0000_cy<3>_pack_1 ;
wire \out/shift_out_not0001 ;
wire \out/N7_pack_1 ;
wire \in/pstate<4>/DXMUX_5267 ;
wire \in/pstate<4>/DYMUX_5251 ;
wire \in/pstate<4>/GYMUX_5250 ;
wire \in/finish_pack_1 ;
wire \in/pstate<4>/SRINV_5243 ;
wire \in/pstate<4>/CLKINV_5242 ;
wire \in/baud1/timer<5>/DXMUX_5443 ;
wire \in/baud1/timer<5>/DYMUX_5429 ;
wire \in/baud1/timer<5>/SRINV_5420 ;
wire \in/baud1/timer<5>/CLKINV_5419 ;
wire \in/bitcounter<1>/DXMUX_5640 ;
wire \in/Mcount_bitcounter1 ;
wire N11_pack_2;
wire \in/bitcounter<1>/CLKINV_5622 ;
wire \in/bitcounter<1>/CEINV_5621 ;
wire \in/baud1/timer<3>/DXMUX_5401 ;
wire \in/baud1/timer<3>/DYMUX_5387 ;
wire \in/baud1/timer<3>/SRINV_5379 ;
wire \in/baud1/timer<3>/CLKINV_5378 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DYMUX_5337 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX_5336 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_5328 ;
wire \in/pstate<0>/DYMUX_5314 ;
wire \in/pstate<0>/CLKINV_5305 ;
wire \in/baud1/timer<7>/DXMUX_5485 ;
wire \in/baud1/timer<7>/DYMUX_5471 ;
wire \in/baud1/timer<7>/SRINV_5462 ;
wire \in/baud1/timer<7>/CLKINV_5461 ;
wire \in/baud1/timer<1>/DYMUX_5359 ;
wire \in/baud1/timer<1>/CLKINV_5349 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/DYMUX_5566 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/BYINV_5565 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CLKINV_5563 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CEINV_5562 ;
wire \addr_rx<1>_pack_1 ;
wire \dout<1>/DYMUX_5539 ;
wire \dout<1>/GYMUX_5538 ;
wire \dout<1>/CLKINV_5528 ;
wire \out/bittime ;
wire \in/load/DYMUX_5291 ;
wire \in/load/GYMUX_5290 ;
wire \in/ld_shift_5288 ;
wire \in/load/CLKINV_5282 ;
wire \in/fifo1/N11 ;
wire \in/rd_fifo_pack_1 ;
wire \in/bittimer<0>/DXMUX_5602 ;
wire \in/bittimer<0>/DYMUX_5593 ;
wire \in/bittimer<0>/SRINV_5583 ;
wire \in/bittimer<0>/CLKINV_5582 ;
wire \in/bittimer<0>/CEINV_5581 ;
wire \in/control<0>/FFY/RSTAND_1653 ;
wire \in/control<2>/FFY/RSTAND_1696 ;
wire \in/pstate<1>/FFX/RSTAND_1773 ;
wire \in/pstate<2>/FFX/RSTAND_1912 ;
wire \in/bitcounter<0>/FFX/RSTAND_2046 ;
wire \in/control<1>/FFX/RSTAND_2081 ;
wire \out/pstate_FSM_FFd1/FFX/RSTAND_2166 ;
wire \out/bitcounter<0>/FFX/RSTAND_2119 ;
wire \in/baud1/baud/FFY/RSTAND_2407 ;
wire \in/bitcounter<3>/FFX/RSTAND_2366 ;
wire \dout<1>/FFY/SET ;
wire \dout<1>/FFY/RSTAND_5546 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/FFY/SET ;
wire \in/bitcounter<1>/FFX/RSTAND_5646 ;
wire \out/empty/FFY/SET ;
wire \data<3>/FFX/SET ;
wire \data<5>/FFX/SET ;
wire \out/baud1/timer<3>/FFX/RSTAND_3870 ;
wire \data<4>/FFX/SET ;
wire \data<6>/FFX/SET ;
wire \data<7>/FFX/SET ;
wire \in/pstate<3>/FFX/RSTAND_4300 ;
wire \in/baud1/timer<0>/FFX/RSTAND_4406 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FFX/SET ;
wire \data<1>/FFX/SET ;
wire \data<2>/FFX/SET ;
wire \out/bitcounter<1>/FFY/RSTAND_4581 ;
wire \out/shift_out<8>/FFY/SET ;
wire \in/frame_error<8>/FFY/RSTAND_4867 ;
wire \data<0>/FFY/SET ;
wire \pstate_FSM_FFd3/FFY/RSTAND_5158 ;
wire \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FFY/SET ;
wire \in/load/FFY/RSTAND_5296 ;
wire \in/pstate<0>/FFY/SET ;
wire \in/baud1/timer<1>/FFY/RSTAND_5364 ;
wire \NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> ;
wire \NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> ;
wire \NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> ;
wire \NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<2> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> ;
wire \NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> ;
wire VCC;
wire GND;
wire \NLW_in/Mshreg_in_two/SRL16E_Q15_UNCONNECTED ;
wire [9 : 0] \in/shift ;
wire [2 : 0] \in/control ;
wire [5 : 0] \in/pstate ;
wire [3 : 0] \in/bittimer ;
wire [8 : 0] \in/frame_error ;
wire [3 : 0] \in/bitcounter ;
wire [3 : 0] \out/bitcounter ;
wire [7 : 0] \out/baud1/timer ;
wire [3 : 0] \out/bittimer ;
wire [3 : 0] \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [3 : 0] \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
wire [3 : 0] \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [3 : 0] \in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [3 : 0] \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [1 : 1] addr_rx;
wire [7 : 0] \in/dout_fifo ;
wire [7 : 0] \in/baud1/timer ;
wire [7 : 0] \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem ;
wire [7 : 0] \out/to_shift ;
wire [3 : 0] \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [1 : 0] trans;
wire [1 : 1] dout;
wire [7 : 0] data;
wire [8 : 0] \out/shift_out ;
wire [0 : 0] Madd_data_add0000_cy;
wire [3 : 1] \out/fifo1/Result ;
wire [3 : 1] \in/fifo1/Result ;
wire [3 : 1] \out/Result ;
wire [5 : 1] \in/pstate_mux0000 ;
wire [7 : 0] \out/baud1/timer_mux0000 ;
wire [8 : 0] \out/shift_out_mux0000 ;
wire [3 : 1] \in/Result ;
wire [7 : 0] \in/baud1/timer_mux0000 ;
wire [1 : 1] Madd_data_add0000_lut;
initial $sdf_annotate("netgen/par/uart_timesim.sdf");
X_BUF #(
.LOC ( "SLICE_X21Y13" ))
\in/control<2>/DYMUX (
.I(\in/control [0]),
.O(\in/control<2>/DYMUX_1690 )
);
X_BUF #(
.LOC ( "SLICE_X21Y13" ))
\in/control<2>/CLKINV (
.I(clk_BUFGP),
.O(\in/control<2>/CLKINV_1687 )
);
X_BUF #(
.LOC ( "SLICE_X21Y13" ))
\in/control<2>/CEINV (
.I(\in/control_2_not0001 ),
.O(\in/control<2>/CEINV_1686 )
);
X_BUF #(
.LOC ( "SLICE_X17Y21" ))
\in/shift<5>/DXMUX (
.I(\in/shift [6]),
.O(\in/shift<5>/DXMUX_1717 )
);
X_BUF #(
.LOC ( "SLICE_X17Y21" ))
\in/shift<5>/DYMUX (
.I(\in/shift [5]),
.O(\in/shift<5>/DYMUX_1709 )
);
X_BUF #(
.LOC ( "SLICE_X17Y21" ))
\in/shift<5>/SRINV (
.I(reset_IBUF_1366),
.O(\in/shift<5>/SRINV_1707 )
);
X_BUF #(
.LOC ( "SLICE_X17Y21" ))
\in/shift<5>/CLKINV (
.I(clk_BUFGP),
.O(\in/shift<5>/CLKINV_1706 )
);
X_BUF #(
.LOC ( "SLICE_X17Y21" ))
\in/shift<5>/CEINV (
.I(\in/ld_shift_0 ),
.O(\in/shift<5>/CEINV_1705 )
);
X_BUF #(
.LOC ( "SLICE_X21Y10" ))
\in/control<0>/DYMUX (
.I(\in/control<0>/BYINV_1646 ),
.O(\in/control<0>/DYMUX_1647 )
);
X_BUF #(
.LOC ( "SLICE_X21Y10" ))
\in/control<0>/BYINV (
.I(1'b1),
.O(\in/control<0>/BYINV_1646 )
);
X_BUF #(
.LOC ( "SLICE_X21Y10" ))
\in/control<0>/CLKINV (
.I(clk_BUFGP),
.O(\in/control<0>/CLKINV_1644 )
);
X_BUF #(
.LOC ( "SLICE_X21Y10" ))
\in/control<0>/CEINV (
.I(\in/wr_control ),
.O(\in/control<0>/CEINV_1643 )
);
X_BUF #(
.LOC ( "SLICE_X16Y20" ))
\in/shift<3>/DXMUX (
.I(\in/shift [4]),
.O(\in/shift<3>/DXMUX_1674 )
);
X_BUF #(
.LOC ( "SLICE_X16Y20" ))
\in/shift<3>/DYMUX (
.I(\in/shift [3]),
.O(\in/shift<3>/DYMUX_1666 )
);
X_BUF #(
.LOC ( "SLICE_X16Y20" ))
\in/shift<3>/SRINV (
.I(reset_IBUF_1366),
.O(\in/shift<3>/SRINV_1664 )
);
X_BUF #(
.LOC ( "SLICE_X16Y20" ))
\in/shift<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/shift<3>/CLKINV_1663 )
);
X_BUF #(
.LOC ( "SLICE_X16Y20" ))
\in/shift<3>/CEINV (
.I(\in/ld_shift_0 ),
.O(\in/shift<3>/CEINV_1662 )
);
X_BUF #(
.LOC ( "SLICE_X14Y20" ))
\in/shift<1>/DXMUX (
.I(\in/shift [2]),
.O(\in/shift<1>/DXMUX_1631 )
);
X_BUF #(
.LOC ( "SLICE_X14Y20" ))
\in/shift<1>/DYMUX (
.I(\in/shift [1]),
.O(\in/shift<1>/DYMUX_1623 )
);
X_BUF #(
.LOC ( "SLICE_X14Y20" ))
\in/shift<1>/SRINV (
.I(reset_IBUF_1366),
.O(\in/shift<1>/SRINV_1621 )
);
X_BUF #(
.LOC ( "SLICE_X14Y20" ))
\in/shift<1>/CLKINV (
.I(clk_BUFGP),
.O(\in/shift<1>/CLKINV_1620 )
);
X_BUF #(
.LOC ( "SLICE_X14Y20" ))
\in/shift<1>/CEINV (
.I(\in/ld_shift_0 ),
.O(\in/shift<1>/CEINV_1619 )
);
X_BUF #(
.LOC ( "SLICE_X21Y18" ))
\in/bitcounter<3>/DXMUX (
.I(\in/Mcount_bitcounter3 ),
.O(\in/bitcounter<3>/DXMUX_2360 )
);
X_BUF #(
.LOC ( "SLICE_X21Y18" ))
\in/bitcounter<3>/YUSED (
.I(N21_pack_3),
.O(N21)
);
X_BUF #(
.LOC ( "SLICE_X21Y18" ))
\in/bitcounter<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/bitcounter<3>/CLKINV_2343 )
);
X_BUF #(
.LOC ( "SLICE_X21Y18" ))
\in/bitcounter<3>/CEINV (
.I(\in/bitcounter_not0001_0 ),
.O(\in/bitcounter<3>/CEINV_2342 )
);
X_INV #(
.LOC ( "SLICE_X2Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2299 )
);
X_BUF #(
.LOC ( "SLICE_X2Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX (
.I(\out/fifo1/Result [1]),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX_2290 )
);
X_BUF #(
.LOC ( "SLICE_X2Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2280 )
);
X_BUF #(
.LOC ( "SLICE_X2Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2279 )
);
X_BUF #(
.LOC ( "SLICE_X2Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2278 )
);
X_BUF #(
.LOC ( "SLICE_X29Y31" ))
\out/baud1/baud_cmp_eq0000822/XUSED (
.I(\out/baud1/baud_cmp_eq0000822_2130 ),
.O(\out/baud1/baud_cmp_eq0000822_0 )
);
X_INV #(
.LOC ( "SLICE_X10Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2219 )
);
X_BUF #(
.LOC ( "SLICE_X10Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/XUSED (
.I(\in/fifo1/N9 ),
.O(\in/fifo1/N9_0 )
);
X_BUF #(
.LOC ( "SLICE_X10Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX (
.I(\in/fifo1/Result<1>1 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX_2205 )
);
X_BUF #(
.LOC ( "SLICE_X10Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV (
.I(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2195 )
);
X_BUF #(
.LOC ( "SLICE_X10Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2194 )
);
X_BUF #(
.LOC ( "SLICE_X10Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2193 )
);
X_BUF #(
.LOC ( "SLICE_X22Y35" ))
\out/pstate_FSM_FFd1/DXMUX (
.I(\out/pstate_FSM_FFd1-In_2158 ),
.O(\out/pstate_FSM_FFd1/DXMUX_2161 )
);
X_BUF #(
.LOC ( "SLICE_X22Y35" ))
\out/pstate_FSM_FFd1/YUSED (
.I(N23_pack_2),
.O(N23)
);
X_BUF #(
.LOC ( "SLICE_X22Y35" ))
\out/pstate_FSM_FFd1/CLKINV (
.I(clk_BUFGP),
.O(\out/pstate_FSM_FFd1/CLKINV_2145 )
);
X_BUF #(
.LOC ( "SLICE_X22Y18" ))
\in/bitcounter<0>/DXMUX (
.I(\in/Mcount_bitcounter ),
.O(\in/bitcounter<0>/DXMUX_2040 )
);
X_BUF #(
.LOC ( "SLICE_X22Y18" ))
\in/bitcounter<0>/YUSED (
.I(\in/bittime ),
.O(\in/bittime_0 )
);
X_BUF #(
.LOC ( "SLICE_X22Y18" ))
\in/bitcounter<0>/CLKINV (
.I(clk_BUFGP),
.O(\in/bitcounter<0>/CLKINV_2023 )
);
X_BUF #(
.LOC ( "SLICE_X22Y18" ))
\in/bitcounter<0>/CEINV (
.I(\in/bitcounter_not0001_0 ),
.O(\in/bitcounter<0>/CEINV_2022 )
);
X_BUF #(
.LOC ( "SLICE_X31Y23" ))
\N31/XUSED (
.I(N31),
.O(N31_0)
);
X_BUF #(
.LOC ( "SLICE_X31Y23" ))
\N31/YUSED (
.I(\in/baud1/baud_cmp_eq0000810_2380 ),
.O(\in/baud1/baud_cmp_eq0000810_0 )
);
X_BUF #(
.LOC ( "SLICE_X8Y2" ))
\in/fifo1/N01/XUSED (
.I(\in/fifo1/N01 ),
.O(\in/fifo1/N01_0 )
);
X_BUF #(
.LOC ( "SLICE_X8Y2" ))
\in/fifo1/N01/YUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_2423 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_0 )
);
X_INV #(
.LOC ( "SLICE_X24Y22" ))
\in/baud1/baud/DYMUX (
.I(\in/baud1/baud_1387 ),
.O(\in/baud1/baud/DYMUX_2401 )
);
X_BUF #(
.LOC ( "SLICE_X24Y22" ))
\in/baud1/baud/CLKINV (
.I(clk_BUFGP),
.O(\in/baud1/baud/CLKINV_2398 )
);
X_BUF #(
.LOC ( "SLICE_X24Y22" ))
\in/baud1/baud/CEINV (
.I(\in/baud1/baud_cmp_eq0000_0 ),
.O(\in/baud1/baud/CEINV_2397 )
);
X_BUF #(
.LOC ( "SLICE_X21Y20" ))
\in/bitcounter_not0001/YUSED (
.I(\in/bitcounter_not0001 ),
.O(\in/bitcounter_not0001_0 )
);
X_BUF #(
.LOC ( "SLICE_X6Y40" ))
\out/to_shift<1>/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [1]),
.O(\out/to_shift<1>/DXMUX_2451 )
);
X_BUF #(
.LOC ( "SLICE_X6Y40" ))
\out/to_shift<1>/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [0]),
.O(\out/to_shift<1>/DYMUX_2444 )
);
X_BUF #(
.LOC ( "SLICE_X6Y40" ))
\out/to_shift<1>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ),
.O(\out/to_shift<1>/SRINV_2442 )
);
X_BUF #(
.LOC ( "SLICE_X6Y40" ))
\out/to_shift<1>/CLKINV (
.I(clk_BUFGP),
.O(\out/to_shift<1>/CLKINV_2441 )
);
X_BUF #(
.LOC ( "SLICE_X6Y40" ))
\out/to_shift<1>/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ),
.O(\out/to_shift<1>/CEINV_2440 )
);
X_BUF #(
.LOC ( "SLICE_X27Y36" ))
\out/bitcounter<0>/DXMUX (
.I(\out/Mcount_bitcounter ),
.O(\out/bitcounter<0>/DXMUX_2113 )
);
X_BUF #(
.LOC ( "SLICE_X27Y36" ))
\out/bitcounter<0>/YUSED (
.I(\out/N2_pack_2 ),
.O(\out/N2 )
);
X_BUF #(
.LOC ( "SLICE_X27Y36" ))
\out/bitcounter<0>/CLKINV (
.I(clk_BUFGP),
.O(\out/bitcounter<0>/CLKINV_2096 )
);
X_BUF #(
.LOC ( "SLICE_X27Y36" ))
\out/bitcounter<0>/CEINV (
.I(\out/bitcounter_not0001_0 ),
.O(\out/bitcounter<0>/CEINV_2095 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\in/control<1>/DXMUX (
.I(\in/control_1_mux0000 ),
.O(\in/control<1>/DXMUX_2076 )
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\in/control<1>/CLKINV (
.I(clk_BUFGP),
.O(\in/control<1>/CLKINV_2057 )
);
X_INV #(
.LOC ( "SLICE_X9Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DXMUX_2264 )
);
X_BUF #(
.LOC ( "SLICE_X9Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/XUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_2261 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_0 )
);
X_BUF #(
.LOC ( "SLICE_X9Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DYMUX (
.I(\in/fifo1/Result [1]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DYMUX_2250 )
);
X_BUF #(
.LOC ( "SLICE_X9Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV (
.I(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV_2240 )
);
X_BUF #(
.LOC ( "SLICE_X9Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV_2239 )
);
X_BUF #(
.LOC ( "SLICE_X9Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV_2238 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\in/empty/DYMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FXMUX_3832 ),
.O(\in/empty/DYMUX_2486 )
);
X_BUF #(
.LOC ( "SLICE_X12Y2" ))
\in/empty/CLKINV (
.I(clk_BUFGP),
.O(\in/empty/CLKINV_2484 )
);
X_BUF #(
.LOC ( "SLICE_X8Y40" ))
\out/to_shift<3>/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [3]),
.O(\out/to_shift<3>/DXMUX_2520 )
);
X_BUF #(
.LOC ( "SLICE_X8Y40" ))
\out/to_shift<3>/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [2]),
.O(\out/to_shift<3>/DYMUX_2513 )
);
X_BUF #(
.LOC ( "SLICE_X8Y40" ))
\out/to_shift<3>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ),
.O(\out/to_shift<3>/SRINV_2511 )
);
X_BUF #(
.LOC ( "SLICE_X8Y40" ))
\out/to_shift<3>/CLKINV (
.I(clk_BUFGP),
.O(\out/to_shift<3>/CLKINV_2510 )
);
X_BUF #(
.LOC ( "SLICE_X8Y40" ))
\out/to_shift<3>/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ),
.O(\out/to_shift<3>/CEINV_2509 )
);
X_BUF #(
.LOC ( "SLICE_X12Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en/YUSED (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X11Y1" ))
\in/fifo1/N3/XUSED (
.I(\in/fifo1/N3 ),
.O(\in/fifo1/N3_0 )
);
X_BUF #(
.LOC ( "SLICE_X11Y1" ))
\in/fifo1/N3/YUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X8Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX_2789 )
);
X_BUF #(
.LOC ( "SLICE_X8Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX_2782 )
);
X_BUF #(
.LOC ( "SLICE_X8Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV (
.I(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_2780 )
);
X_BUF #(
.LOC ( "SLICE_X8Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_2779 )
);
X_BUF #(
.LOC ( "SLICE_X8Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_2778 )
);
X_BUF #(
.LOC ( "SLICE_X5Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BXINV_2874 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DXMUX_2875 )
);
X_BUF #(
.LOC ( "SLICE_X5Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BXINV (
.I(1'b0),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BXINV_2874 )
);
X_BUF #(
.LOC ( "SLICE_X5Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BYINV_2867 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DYMUX_2868 )
);
X_BUF #(
.LOC ( "SLICE_X5Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BYINV (
.I(1'b0),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/BYINV_2867 )
);
X_BUF #(
.LOC ( "SLICE_X5Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/SRINV_2866 )
);
X_BUF #(
.LOC ( "SLICE_X5Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/CLKINV_2865 )
);
X_BUF #(
.LOC ( "SLICE_X2Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_2839 )
);
X_BUF #(
.LOC ( "SLICE_X2Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_2830 )
);
X_BUF #(
.LOC ( "SLICE_X2Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_2828 )
);
X_BUF #(
.LOC ( "SLICE_X2Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_2827 )
);
X_BUF #(
.LOC ( "SLICE_X2Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_2826 )
);
X_BUF #(
.LOC ( "SLICE_X26Y37" ))
\out/bitcounter<3>/DXMUX (
.I(\out/Mcount_bitcounter3 ),
.O(\out/bitcounter<3>/DXMUX_3021 )
);
X_BUF #(
.LOC ( "SLICE_X26Y37" ))
\out/bitcounter<3>/YUSED (
.I(N33_pack_2),
.O(N33)
);
X_BUF #(
.LOC ( "SLICE_X26Y37" ))
\out/bitcounter<3>/CLKINV (
.I(clk_BUFGP),
.O(\out/bitcounter<3>/CLKINV_3005 )
);
X_BUF #(
.LOC ( "SLICE_X26Y37" ))
\out/bitcounter<3>/CEINV (
.I(\out/bitcounter_not0001_0 ),
.O(\out/bitcounter<3>/CEINV_3004 )
);
X_INV #(
.LOC ( "SLICE_X23Y35" ))
\out/bittimer<0>/DXMUX (
.I(\out/bittimer [0]),
.O(\out/bittimer<0>/DXMUX_2639 )
);
X_BUF #(
.LOC ( "SLICE_X23Y35" ))
\out/bittimer<0>/XUSED (
.I(N15),
.O(N15_0)
);
X_BUF #(
.LOC ( "SLICE_X23Y35" ))
\out/bittimer<0>/DYMUX (
.I(\out/Result [1]),
.O(\out/bittimer<0>/DYMUX_2622 )
);
X_BUF #(
.LOC ( "SLICE_X23Y35" ))
\out/bittimer<0>/SRINV (
.I(reset_IBUF_1366),
.O(\out/bittimer<0>/SRINV_2612 )
);
X_BUF #(
.LOC ( "SLICE_X23Y35" ))
\out/bittimer<0>/CLKINV (
.I(\out/baud1/baud_1432 ),
.O(\out/bittimer<0>/CLKINV_2611 )
);
X_BUF #(
.LOC ( "SLICE_X23Y35" ))
\out/bittimer<0>/CEINV (
.I(\out/bittime_0 ),
.O(\out/bittimer<0>/CEINV_2610 )
);
X_BUF #(
.LOC ( "SLICE_X12Y12" ))
\N40/XUSED (
.I(N40),
.O(N40_0)
);
X_BUF #(
.LOC ( "SLICE_X12Y12" ))
\N40/YUSED (
.I(N50),
.O(N50_0)
);
X_FF #(
.LOC ( "SLICE_X21Y11" ),
.INIT ( 1'b1 ))
pstate_FSM_FFd4 (
.I(\pstate_FSM_FFd4/DYMUX_2926 ),
.CE(VCC),
.CLK(\pstate_FSM_FFd4/CLKINV_2923 ),
.SET(\pstate_FSM_FFd4/SRINV_2924 ),
.RST(GND),
.O(pstate_FSM_FFd4_1516)
);
X_BUF #(
.LOC ( "SLICE_X21Y11" ))
\pstate_FSM_FFd4/DYMUX (
.I(\pstate_FSM_FFd4/BYINV_2925 ),
.O(\pstate_FSM_FFd4/DYMUX_2926 )
);
X_BUF #(
.LOC ( "SLICE_X21Y11" ))
\pstate_FSM_FFd4/BYINV (
.I(1'b0),
.O(\pstate_FSM_FFd4/BYINV_2925 )
);
X_BUF #(
.LOC ( "SLICE_X21Y11" ))
\pstate_FSM_FFd4/SRINV (
.I(reset_IBUF_1366),
.O(\pstate_FSM_FFd4/SRINV_2924 )
);
X_BUF #(
.LOC ( "SLICE_X21Y11" ))
\pstate_FSM_FFd4/CLKINV (
.I(clk_BUFGP),
.O(\pstate_FSM_FFd4/CLKINV_2923 )
);
X_LUT4 #(
.INIT ( 16'h9555 ),
.LOC ( "SLICE_X26Y37" ))
\out/Mcount_bitcounter_xor<3>1_SW0 (
.ADR0(\out/bitcounter [3]),
.ADR1(\out/bitcounter [1]),
.ADR2(\out/bitcounter [0]),
.ADR3(\out/bitcounter [2]),
.O(N33_pack_2)
);
X_BUF #(
.LOC ( "SLICE_X12Y30" ))
\out/to_shift<5>/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [5]),
.O(\out/to_shift<5>/DXMUX_2544 )
);
X_BUF #(
.LOC ( "SLICE_X12Y30" ))
\out/to_shift<5>/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [4]),
.O(\out/to_shift<5>/DYMUX_2537 )
);
X_BUF #(
.LOC ( "SLICE_X12Y30" ))
\out/to_shift<5>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ),
.O(\out/to_shift<5>/SRINV_2535 )
);
X_BUF #(
.LOC ( "SLICE_X12Y30" ))
\out/to_shift<5>/CLKINV (
.I(clk_BUFGP),
.O(\out/to_shift<5>/CLKINV_2534 )
);
X_BUF #(
.LOC ( "SLICE_X12Y30" ))
\out/to_shift<5>/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ),
.O(\out/to_shift<5>/CEINV_2533 )
);
X_BUF #(
.LOC ( "SLICE_X2Y31" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX_2739 )
);
X_BUF #(
.LOC ( "SLICE_X2Y31" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX_2730 )
);
X_BUF #(
.LOC ( "SLICE_X2Y31" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_2728 )
);
X_BUF #(
.LOC ( "SLICE_X2Y31" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_2727 )
);
X_BUF #(
.LOC ( "SLICE_X2Y31" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_2726 )
);
X_BUF #(
.LOC ( "SLICE_X23Y23" ))
\in/loaded_not0001/YUSED (
.I(N46_pack_1),
.O(N46)
);
X_BUF #(
.LOC ( "SLICE_X10Y2" ))
\in/fifo1/N7/XUSED (
.I(\in/fifo1/N7 ),
.O(\in/fifo1/N7_0 )
);
X_BUF #(
.LOC ( "SLICE_X7Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_2813 )
);
X_BUF #(
.LOC ( "SLICE_X7Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_2806 )
);
X_BUF #(
.LOC ( "SLICE_X7Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV (
.I(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_2804 )
);
X_BUF #(
.LOC ( "SLICE_X7Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_2803 )
);
X_BUF #(
.LOC ( "SLICE_X7Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_2802 )
);
X_BUF #(
.LOC ( "SLICE_X20Y19" ))
\in/bitcounter<2>/FFX/RSTOR (
.I(reset_IBUF_1366),
.O(\in/bitcounter<2>/FFX/RST )
);
X_FF #(
.LOC ( "SLICE_X20Y19" ),
.INIT ( 1'b0 ))
\in/bitcounter_2 (
.I(\in/bitcounter<2>/DXMUX_2911 ),
.CE(\in/bitcounter<2>/CEINV_2891 ),
.CLK(\in/bitcounter<2>/CLKINV_2892 ),
.SET(GND),
.RST(\in/bitcounter<2>/FFX/RST ),
.O(\in/bitcounter [2])
);
X_LUT4 #(
.INIT ( 16'hBBBB ),
.LOC ( "SLICE_X20Y19" ))
\in/bitcounter_not00011_SW0 (
.ADR0(\in/bitcounter [0]),
.ADR1(\in/pstate [2]),
.ADR2(VCC),
.ADR3(VCC),
.O(N27)
);
X_LUT4 #(
.INIT ( 16'h6A6A ),
.LOC ( "SLICE_X20Y19" ))
\in/Mcount_bitcounter_xor<2>11 (
.ADR0(\in/bitcounter [2]),
.ADR1(\in/bitcounter [0]),
.ADR2(\in/bitcounter [1]),
.ADR3(VCC),
.O(\in/Mcount_bitcounter2 )
);
X_BUF #(
.LOC ( "SLICE_X20Y19" ))
\in/bitcounter<2>/DXMUX (
.I(\in/Mcount_bitcounter2 ),
.O(\in/bitcounter<2>/DXMUX_2911 )
);
X_BUF #(
.LOC ( "SLICE_X20Y19" ))
\in/bitcounter<2>/YUSED (
.I(N27),
.O(N27_0)
);
X_BUF #(
.LOC ( "SLICE_X20Y19" ))
\in/bitcounter<2>/CLKINV (
.I(clk_BUFGP),
.O(\in/bitcounter<2>/CLKINV_2892 )
);
X_BUF #(
.LOC ( "SLICE_X20Y19" ))
\in/bitcounter<2>/CEINV (
.I(\in/bitcounter_not0001_0 ),
.O(\in/bitcounter<2>/CEINV_2891 )
);
X_LUT4 #(
.INIT ( 16'h0D2F ),
.LOC ( "SLICE_X26Y37" ))
\out/Mcount_bitcounter_xor<3>1 (
.ADR0(\out/pstate_FSM_FFd2_1423 ),
.ADR1(\out/pstate_FSM_FFd1_1425 ),
.ADR2(N33),
.ADR3(N34_0),
.O(\out/Mcount_bitcounter3 )
);
X_FF #(
.LOC ( "SLICE_X26Y37" ),
.INIT ( 1'b0 ))
\out/bitcounter_3 (
.I(\out/bitcounter<3>/DXMUX_3021 ),
.CE(\out/bitcounter<3>/CEINV_3004 ),
.CLK(\out/bitcounter<3>/CLKINV_3005 ),
.SET(GND),
.RST(\out/bitcounter<3>/FFX/RSTAND_3027 ),
.O(\out/bitcounter [3])
);
X_BUF #(
.LOC ( "SLICE_X26Y37" ))
\out/bitcounter<3>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\out/bitcounter<3>/FFX/RSTAND_3027 )
);
X_BUF #(
.LOC ( "SLICE_X12Y34" ))
\out/pstate_FSM_FFd2/FFX/RSTOR (
.I(reset_IBUF_1366),
.O(\out/pstate_FSM_FFd2/FFX/RST )
);
X_FF #(
.LOC ( "SLICE_X12Y34" ),
.INIT ( 1'b0 ))
\out/pstate_FSM_FFd2 (
.I(\out/pstate_FSM_FFd2/DXMUX_2984 ),
.CE(VCC),
.CLK(\out/pstate_FSM_FFd2/CLKINV_2968 ),
.SET(GND),
.RST(\out/pstate_FSM_FFd2/FFX/RST ),
.O(\out/pstate_FSM_FFd2_1423 )
);
X_LUT4 #(
.INIT ( 16'h222A ),
.LOC ( "SLICE_X12Y34" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/RAM_REGOUT_EN1 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_1532 ),
.ADR1(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_1533 ),
.ADR2(\out/pstate_FSM_FFd2_1423 ),
.ADR3(\out/empty ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en )
);
X_LUT4 #(
.INIT ( 16'hEEEF ),
.LOC ( "SLICE_X12Y34" ))
\out/pstate_FSM_FFd2-In1 (
.ADR0(\out/N8_0 ),
.ADR1(\out/pstate_FSM_FFd1_1425 ),
.ADR2(\out/pstate_FSM_FFd2_1423 ),
.ADR3(\out/empty ),
.O(\out/pstate_FSM_FFd2-In )
);
X_BUF #(
.LOC ( "SLICE_X12Y34" ))
\out/pstate_FSM_FFd2/DXMUX (
.I(\out/pstate_FSM_FFd2-In ),
.O(\out/pstate_FSM_FFd2/DXMUX_2984 )
);
X_BUF #(
.LOC ( "SLICE_X12Y34" ))
\out/pstate_FSM_FFd2/YUSED (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X12Y34" ))
\out/pstate_FSM_FFd2/CLKINV (
.I(clk_BUFGP),
.O(\out/pstate_FSM_FFd2/CLKINV_2968 )
);
X_LUT4 #(
.INIT ( 16'h0505 ),
.LOC ( "SLICE_X13Y32" ))
\out/shift_out_not000111 (
.ADR0(\out/pstate_FSM_FFd2_1423 ),
.ADR1(VCC),
.ADR2(\out/empty ),
.ADR3(VCC),
.O(\out/ld_shift_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h3133 ),
.LOC ( "SLICE_X13Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/RAM_RD_EN_FWFT1 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_1532 ),
.ADR1(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1488 ),
.ADR2(\out/ld_shift ),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_1533 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
X_BUF #(
.LOC ( "SLICE_X13Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en/XUSED (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X13Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en/YUSED (
.I(\out/ld_shift_pack_1 ),
.O(\out/ld_shift )
);
X_BUF #(
.LOC ( "SLICE_X13Y30" ))
\out/to_shift<7>/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [7]),
.O(\out/to_shift<7>/DXMUX_2568 )
);
X_BUF #(
.LOC ( "SLICE_X13Y30" ))
\out/to_shift<7>/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [6]),
.O(\out/to_shift<7>/DYMUX_2561 )
);
X_BUF #(
.LOC ( "SLICE_X13Y30" ))
\out/to_shift<7>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ),
.O(\out/to_shift<7>/SRINV_2559 )
);
X_BUF #(
.LOC ( "SLICE_X13Y30" ))
\out/to_shift<7>/CLKINV (
.I(clk_BUFGP),
.O(\out/to_shift<7>/CLKINV_2558 )
);
X_BUF #(
.LOC ( "SLICE_X13Y30" ))
\out/to_shift<7>/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en_0 ),
.O(\out/to_shift<7>/CEINV_2557 )
);
X_BUF #(
.LOC ( "SLICE_X17Y11" ))
\in/wr_control/YUSED (
.I(N54),
.O(N54_0)
);
X_BUF #(
.LOC ( "SLICE_X9Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DXMUX_2689 )
);
X_BUF #(
.LOC ( "SLICE_X9Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DYMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DYMUX_2682 )
);
X_BUF #(
.LOC ( "SLICE_X9Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV (
.I(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV_2680 )
);
X_BUF #(
.LOC ( "SLICE_X9Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV_2679 )
);
X_BUF #(
.LOC ( "SLICE_X9Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV_2678 )
);
X_BUF #(
.LOC ( "SLICE_X7Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX_2713 )
);
X_BUF #(
.LOC ( "SLICE_X7Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX_2706 )
);
X_BUF #(
.LOC ( "SLICE_X7Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV (
.I(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_2704 )
);
X_BUF #(
.LOC ( "SLICE_X7Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_2703 )
);
X_BUF #(
.LOC ( "SLICE_X7Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_2702 )
);
X_BUF #(
.LOC ( "SLICE_X26Y36" ))
\out/bitcounter<2>/FFX/RSTOR (
.I(reset_IBUF_1366),
.O(\out/bitcounter<2>/FFX/RST )
);
X_FF #(
.LOC ( "SLICE_X26Y36" ),
.INIT ( 1'b0 ))
\out/bitcounter_2 (
.I(\out/bitcounter<2>/DXMUX_3059 ),
.CE(\out/bitcounter<2>/CEINV_3041 ),
.CLK(\out/bitcounter<2>/CLKINV_3042 ),
.SET(GND),
.RST(\out/bitcounter<2>/FFX/RST ),
.O(\out/bitcounter [2])
);
X_LUT4 #(
.INIT ( 16'h955D ),
.LOC ( "SLICE_X26Y36" ))
\out/Mcount_bitcounter_xor<3>1_SW1 (
.ADR0(\out/bitcounter [3]),
.ADR1(\out/bitcounter [1]),
.ADR2(\out/bitcounter [0]),
.ADR3(\out/bitcounter [2]),
.O(N34)
);
X_LUT4 #(
.INIT ( 16'h6A6A ),
.LOC ( "SLICE_X26Y36" ))
\out/Mcount_bitcounter_xor<2>11 (
.ADR0(\out/bitcounter [2]),
.ADR1(\out/bitcounter [1]),
.ADR2(\out/bitcounter [0]),
.ADR3(VCC),
.O(\out/Mcount_bitcounter2 )
);
X_BUF #(
.LOC ( "SLICE_X26Y36" ))
\out/bitcounter<2>/DXMUX (
.I(\out/Mcount_bitcounter2 ),
.O(\out/bitcounter<2>/DXMUX_3059 )
);
X_BUF #(
.LOC ( "SLICE_X26Y36" ))
\out/bitcounter<2>/YUSED (
.I(N34),
.O(N34_0)
);
X_BUF #(
.LOC ( "SLICE_X26Y36" ))
\out/bitcounter<2>/CLKINV (
.I(clk_BUFGP),
.O(\out/bitcounter<2>/CLKINV_3042 )
);
X_BUF #(
.LOC ( "SLICE_X26Y36" ))
\out/bitcounter<2>/CEINV (
.I(\out/bitcounter_not0001_0 ),
.O(\out/bitcounter<2>/CEINV_3041 )
);
X_BUF #(
.LOC ( "SLICE_X3Y18" ))
\in/frame_error<7>/DXMUX (
.I(\in/shift [8]),
.O(\in/frame_error<7>/DXMUX_1990 )
);
X_BUF #(
.LOC ( "SLICE_X3Y18" ))
\in/frame_error<7>/DYMUX (
.I(\in/shift [7]),
.O(\in/frame_error<7>/DYMUX_1981 )
);
X_BUF #(
.LOC ( "SLICE_X3Y18" ))
\in/frame_error<7>/SRINV (
.I(reset_IBUF_1366),
.O(\in/frame_error<7>/SRINV_1979 )
);
X_BUF #(
.LOC ( "SLICE_X3Y18" ))
\in/frame_error<7>/CLKINV (
.I(clk_BUFGP),
.O(\in/frame_error<7>/CLKINV_1978 )
);
X_BUF #(
.LOC ( "SLICE_X3Y18" ))
\in/frame_error<7>/CEINV (
.I(\in/finish ),
.O(\in/frame_error<7>/CEINV_1977 )
);
X_BUF #(
.LOC ( "SLICE_X17Y18" ))
\in/frame_error<3>/DXMUX (
.I(\in/shift [4]),
.O(\in/frame_error<3>/DXMUX_1934 )
);
X_BUF #(
.LOC ( "SLICE_X17Y18" ))
\in/frame_error<3>/DYMUX (
.I(\in/shift [3]),
.O(\in/frame_error<3>/DYMUX_1925 )
);
X_BUF #(
.LOC ( "SLICE_X17Y18" ))
\in/frame_error<3>/SRINV (
.I(reset_IBUF_1366),
.O(\in/frame_error<3>/SRINV_1923 )
);
X_BUF #(
.LOC ( "SLICE_X17Y18" ))
\in/frame_error<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/frame_error<3>/CLKINV_1922 )
);
X_BUF #(
.LOC ( "SLICE_X17Y18" ))
\in/frame_error<3>/CEINV (
.I(\in/finish ),
.O(\in/frame_error<3>/CEINV_1921 )
);
X_BUF #(
.LOC ( "SLICE_X20Y21" ))
\in/pstate<1>/DXMUX (
.I(\in/pstate_mux0000 [4]),
.O(\in/pstate<1>/DXMUX_1768 )
);
X_BUF #(
.LOC ( "SLICE_X20Y21" ))
\in/pstate<1>/YUSED (
.I(N13_pack_2),
.O(N13)
);
X_BUF #(
.LOC ( "SLICE_X20Y21" ))
\in/pstate<1>/CLKINV (
.I(clk_BUFGP),
.O(\in/pstate<1>/CLKINV_1751 )
);
X_BUF #(
.LOC ( "SLICE_X17Y20" ))
\in/shift<9>/DXMUX (
.I(\in/in_two_1395 ),
.O(\in/shift<9>/DXMUX_1844 )
);
X_BUF #(
.LOC ( "SLICE_X17Y20" ))
\in/shift<9>/DYMUX (
.I(\in/shift [9]),
.O(\in/shift<9>/DYMUX_1836 )
);
X_BUF #(
.LOC ( "SLICE_X17Y20" ))
\in/shift<9>/SRINV (
.I(reset_IBUF_1366),
.O(\in/shift<9>/SRINV_1834 )
);
X_BUF #(
.LOC ( "SLICE_X17Y20" ))
\in/shift<9>/CLKINV (
.I(clk_BUFGP),
.O(\in/shift<9>/CLKINV_1833 )
);
X_BUF #(
.LOC ( "SLICE_X17Y20" ))
\in/shift<9>/CEINV (
.I(\in/ld_shift_0 ),
.O(\in/shift<9>/CEINV_1832 )
);
X_BUF #(
.LOC ( "SLICE_X20Y20" ))
\in/pstate<2>/DXMUX (
.I(\in/pstate_mux0000 [3]),
.O(\in/pstate<2>/DXMUX_1907 )
);
X_BUF #(
.LOC ( "SLICE_X20Y20" ))
\in/pstate<2>/YUSED (
.I(\in/pstate_mux0000<3>2_pack_1 ),
.O(\in/pstate_mux0000<3>2_1402 )
);
X_BUF #(
.LOC ( "SLICE_X20Y20" ))
\in/pstate<2>/CLKINV (
.I(clk_BUFGP),
.O(\in/pstate<2>/CLKINV_1889 )
);
X_BUF #(
.LOC ( "SLICE_X0Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1377 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DXMUX_1736 )
);
X_BUF #(
.LOC ( "SLICE_X0Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1378 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DYMUX_1731 )
);
X_BUF #(
.LOC ( "SLICE_X0Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV_1729 )
);
X_BUF #(
.LOC ( "SLICE_X25Y25" ))
\in/pstate_mux0000<2>10/XUSED (
.I(\in/pstate_mux0000<2>10_1822 ),
.O(\in/pstate_mux0000<2>10_0 )
);
X_BUF #(
.LOC ( "SLICE_X25Y25" ))
\in/pstate_mux0000<2>10/YUSED (
.I(\in/pstate_mux0000<2>4_pack_1 ),
.O(\in/pstate_mux0000<2>4_1389 )
);
X_BUF #(
.LOC ( "SLICE_X15Y21" ))
\in/shift<7>/DXMUX (
.I(\in/shift [8]),
.O(\in/shift<7>/DXMUX_1794 )
);
X_BUF #(
.LOC ( "SLICE_X15Y21" ))
\in/shift<7>/DYMUX (
.I(\in/shift [7]),
.O(\in/shift<7>/DYMUX_1786 )
);
X_BUF #(
.LOC ( "SLICE_X15Y21" ))
\in/shift<7>/SRINV (
.I(reset_IBUF_1366),
.O(\in/shift<7>/SRINV_1784 )
);
X_BUF #(
.LOC ( "SLICE_X15Y21" ))
\in/shift<7>/CLKINV (
.I(clk_BUFGP),
.O(\in/shift<7>/CLKINV_1783 )
);
X_BUF #(
.LOC ( "SLICE_X15Y21" ))
\in/shift<7>/CEINV (
.I(\in/ld_shift_0 ),
.O(\in/shift<7>/CEINV_1782 )
);
X_BUF #(
.LOC ( "SLICE_X15Y18" ))
\in/frame_error<1>/DXMUX (
.I(\in/shift [2]),
.O(\in/frame_error<1>/DXMUX_1871 )
);
X_BUF #(
.LOC ( "SLICE_X15Y18" ))
\in/frame_error<1>/DYMUX (
.I(\in/shift [1]),
.O(\in/frame_error<1>/DYMUX_1862 )
);
X_BUF #(
.LOC ( "SLICE_X15Y18" ))
\in/frame_error<1>/SRINV (
.I(reset_IBUF_1366),
.O(\in/frame_error<1>/SRINV_1860 )
);
X_BUF #(
.LOC ( "SLICE_X15Y18" ))
\in/frame_error<1>/CLKINV (
.I(clk_BUFGP),
.O(\in/frame_error<1>/CLKINV_1859 )
);
X_BUF #(
.LOC ( "SLICE_X15Y18" ))
\in/frame_error<1>/CEINV (
.I(\in/finish ),
.O(\in/frame_error<1>/CEINV_1858 )
);
X_BUF #(
.LOC ( "SLICE_X3Y19" ))
\in/frame_error<5>/DXMUX (
.I(\in/shift [6]),
.O(\in/frame_error<5>/DXMUX_1962 )
);
X_BUF #(
.LOC ( "SLICE_X3Y19" ))
\in/frame_error<5>/DYMUX (
.I(\in/shift [5]),
.O(\in/frame_error<5>/DYMUX_1953 )
);
X_BUF #(
.LOC ( "SLICE_X3Y19" ))
\in/frame_error<5>/SRINV (
.I(reset_IBUF_1366),
.O(\in/frame_error<5>/SRINV_1951 )
);
X_BUF #(
.LOC ( "SLICE_X3Y19" ))
\in/frame_error<5>/CLKINV (
.I(clk_BUFGP),
.O(\in/frame_error<5>/CLKINV_1950 )
);
X_BUF #(
.LOC ( "SLICE_X3Y19" ))
\in/frame_error<5>/CEINV (
.I(\in/finish ),
.O(\in/frame_error<5>/CEINV_1949 )
);
X_IPAD #(
.LOC ( "PAD2" ))
\rx/PAD (
.PAD(rx)
);
X_BUF #(
.LOC ( "PAD2" ))
rx_IBUF (
.I(rx),
.O(\rx/INBUF )
);
X_IPAD #(
.LOC ( "PAD83" ))
\fsm/PAD (
.PAD(fsm)
);
X_BUF #(
.LOC ( "PAD83" ))
fsm_IBUF (
.I(fsm),
.O(\fsm/INBUF )
);
X_IPAD #(
.LOC ( "IPAD60" ))
\reset/PAD (
.PAD(reset)
);
X_BUF #(
.LOC ( "IPAD60" ))
reset_IBUF (
.I(reset),
.O(\reset/INBUF )
);
X_OPAD #(
.LOC ( "PAD69" ))
\Led<0>/PAD (
.PAD(Led[0])
);
X_OBUF #(
.LOC ( "PAD69" ))
Led_0_OBUF (
.I(\Led<0>/O ),
.O(Led[0])
);
X_OPAD #(
.LOC ( "PAD108" ))
\tx/PAD (
.PAD(tx)
);
X_OBUF #(
.LOC ( "PAD108" ))
tx_OBUF (
.I(\tx/O ),
.O(tx)
);
X_OPAD #(
.LOC ( "PAD58" ))
\Led<1>/PAD (
.PAD(Led[1])
);
X_OBUF #(
.LOC ( "PAD58" ))
Led_1_OBUF (
.I(\Led<1>/O ),
.O(Led[1])
);
X_OPAD #(
.LOC ( "PAD96" ))
\Led<7>/PAD (
.PAD(Led[7])
);
X_OBUF #(
.LOC ( "PAD96" ))
Led_7_OBUF (
.I(\Led<7>/O ),
.O(Led[7])
);
X_LUT4 #(
.INIT ( 16'hAA00 ),
.LOC ( "SLICE_X15Y11" ))
\pstate_FSM_FFd2-In_SW0 (
.ADR0(pstate_FSM_FFd3_1543),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(dout[1]),
.O(N9_pack_2)
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\pstate_FSM_FFd2/FFX/RSTOR (
.I(reset_IBUF_1366),
.O(\pstate_FSM_FFd2/FFX/RST )
);
X_FF #(
.LOC ( "SLICE_X15Y11" ),
.INIT ( 1'b0 ))
pstate_FSM_FFd2 (
.I(\pstate_FSM_FFd2/DXMUX_3130 ),
.CE(VCC),
.CLK(\pstate_FSM_FFd2/CLKINV_3112 ),
.SET(GND),
.RST(\pstate_FSM_FFd2/FFX/RST ),
.O(pstate_FSM_FFd2_1518)
);
X_LUT4 #(
.INIT ( 16'hFF4C ),
.LOC ( "SLICE_X15Y11" ))
\pstate_FSM_FFd2-In (
.ADR0(trans[0]),
.ADR1(pstate_FSM_FFd2_1518),
.ADR2(trans[1]),
.ADR3(N9),
.O(\pstate_FSM_FFd2-In_3127 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\pstate_FSM_FFd2/DXMUX (
.I(\pstate_FSM_FFd2-In_3127 ),
.O(\pstate_FSM_FFd2/DXMUX_3130 )
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\pstate_FSM_FFd2/YUSED (
.I(N9_pack_2),
.O(N9)
);
X_BUF #(
.LOC ( "SLICE_X15Y11" ))
\pstate_FSM_FFd2/CLKINV (
.I(clk_BUFGP),
.O(\pstate_FSM_FFd2/CLKINV_3112 )
);
X_LUT4 #(
.INIT ( 16'h3300 ),
.LOC ( "SLICE_X12Y5" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.ADR0(VCC),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1442 ),
.ADR2(VCC),
.ADR3(\in/pstate [4]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
X_LUT4 #(
.INIT ( 16'hEAFA ),
.LOC ( "SLICE_X12Y5" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW0 (
.ADR0(\in/pstate [0]),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1442 ),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1483 ),
.ADR3(\in/pstate [4]),
.O(\in/fifo1/N2 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\in/fifo1/N2/XUSED (
.I(\in/fifo1/N2 ),
.O(\in/fifo1/N2_0 )
);
X_BUF #(
.LOC ( "SLICE_X12Y5" ))
\in/fifo1/N2/YUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\in/pstate<5>/FFY/RSTOR (
.I(reset_IBUF_1366),
.O(\in/pstate<5>/FFY/RST )
);
X_FF #(
.LOC ( "SLICE_X17Y15" ),
.INIT ( 1'b0 ))
\in/pstate_5 (
.I(\in/pstate<5>/DYMUX_3224 ),
.CE(VCC),
.CLK(\in/pstate<5>/CLKINV_3221 ),
.SET(GND),
.RST(\in/pstate<5>/FFY/RST ),
.O(\in/pstate [5])
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\in/pstate<5>/DYMUX (
.I(\in/control [2]),
.O(\in/pstate<5>/DYMUX_3224 )
);
X_BUF #(
.LOC ( "SLICE_X17Y15" ))
\in/pstate<5>/CLKINV (
.I(clk_BUFGP),
.O(\in/pstate<5>/CLKINV_3221 )
);
X_BUF #(
.LOC ( "SLICE_X13Y34" ))
\out/empty/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX_5336 ),
.O(\out/empty/DYMUX_3259 )
);
X_BUF #(
.LOC ( "SLICE_X13Y34" ))
\out/empty/CLKINV (
.I(clk_BUFGP),
.O(\out/empty/CLKINV_3256 )
);
X_LUT4 #(
.INIT ( 16'h0303 ),
.LOC ( "SLICE_X3Y31" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062 (
.ADR0(VCC),
.ADR1(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.ADR2(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR3(VCC),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_3240 )
);
X_BUF #(
.LOC ( "SLICE_X3Y31" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062/XUSED (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_3240 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_0 )
);
X_BUF #(
.LOC ( "SLICE_X10Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en/YUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 )
);
X_OPAD #(
.LOC ( "PAD70" ))
\Led<6>/PAD (
.PAD(Led[6])
);
X_OBUF #(
.LOC ( "PAD70" ))
Led_6_OBUF (
.I(\Led<6>/O ),
.O(Led[6])
);
X_OPAD #(
.LOC ( "PAD71" ))
\Led<5>/PAD (
.PAD(Led[5])
);
X_OBUF #(
.LOC ( "PAD71" ))
Led_5_OBUF (
.I(\Led<5>/O ),
.O(Led[5])
);
X_IPAD #(
.LOC ( "IPAD13" ))
\clk/PAD (
.PAD(clk)
);
X_BUF #(
.LOC ( "IPAD13" ))
\clk_BUFGP/IBUFG (
.I(clk),
.O(\clk/INBUF )
);
X_OPAD #(
.LOC ( "PAD65" ))
\Led<3>/PAD (
.PAD(Led[3])
);
X_OBUF #(
.LOC ( "PAD65" ))
Led_3_OBUF (
.I(\Led<3>/O ),
.O(Led[3])
);
X_BUF #(
.LOC ( "SLICE_X28Y33" ))
\out/baud1/timer<2>/FFX/RSTOR (
.I(reset_IBUF_1366),
.O(\out/baud1/timer<2>/FFX/RST )
);
X_FF #(
.LOC ( "SLICE_X28Y33" ),
.INIT ( 1'b0 ))
\out/baud1/timer_2 (
.I(\out/baud1/timer<2>/DXMUX_3095 ),
.CE(VCC),
.CLK(\out/baud1/timer<2>/CLKINV_3077 ),
.SET(GND),
.RST(\out/baud1/timer<2>/FFX/RST ),
.O(\out/baud1/timer [2])
);
X_LUT4 #(
.INIT ( 16'hC0C0 ),
.LOC ( "SLICE_X28Y33" ))
\out/baud1/timer_mux0000<4>_SW0 (
.ADR0(VCC),
.ADR1(\out/baud1/timer [1]),
.ADR2(\out/baud1/timer [0]),
.ADR3(VCC),
.O(N29)
);
X_LUT4 #(
.INIT ( 16'h6A00 ),
.LOC ( "SLICE_X28Y33" ))
\out/baud1/timer_mux0000<5>1 (
.ADR0(\out/baud1/timer [2]),
.ADR1(\out/baud1/timer [1]),
.ADR2(\out/baud1/timer [0]),
.ADR3(\out/baud1/N01 ),
.O(\out/baud1/timer_mux0000 [5])
);
X_BUF #(
.LOC ( "SLICE_X28Y33" ))
\out/baud1/timer<2>/DXMUX (
.I(\out/baud1/timer_mux0000 [5]),
.O(\out/baud1/timer<2>/DXMUX_3095 )
);
X_BUF #(
.LOC ( "SLICE_X28Y33" ))
\out/baud1/timer<2>/YUSED (
.I(N29),
.O(N29_0)
);
X_BUF #(
.LOC ( "SLICE_X28Y33" ))
\out/baud1/timer<2>/CLKINV (
.I(clk_BUFGP),
.O(\out/baud1/timer<2>/CLKINV_3077 )
);
X_OPAD #(
.LOC ( "PAD68" ))
\Led<4>/PAD (
.PAD(Led[4])
);
X_OBUF #(
.LOC ( "PAD68" ))
Led_4_OBUF (
.I(\Led<4>/O ),
.O(Led[4])
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\out/baud1/baud/FFY/RSTOR (
.I(reset_IBUF_1366),
.O(\out/baud1/baud/FFY/RST )
);
X_FF #(
.LOC ( "SLICE_X25Y34" ),
.INIT ( 1'b0 ))
\out/baud1/baud (
.I(\out/baud1/baud/DYMUX_3170 ),
.CE(\out/baud1/baud/CEINV_3166 ),
.CLK(\out/baud1/baud/CLKINV_3167 ),
.SET(GND),
.RST(\out/baud1/baud/FFY/RST ),
.O(\out/baud1/baud_1432 )
);
X_INV #(
.LOC ( "SLICE_X25Y34" ))
\out/baud1/baud/DYMUX (
.I(\out/baud1/baud_1432 ),
.O(\out/baud1/baud/DYMUX_3170 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\out/baud1/baud/CLKINV (
.I(clk_BUFGP),
.O(\out/baud1/baud/CLKINV_3167 )
);
X_BUF #(
.LOC ( "SLICE_X25Y34" ))
\out/baud1/baud/CEINV (
.I(\out/baud1/baud_cmp_eq0000_0 ),
.O(\out/baud1/baud/CEINV_3166 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\in/full/DYMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_4142 ),
.O(\in/full/DYMUX_3248 )
);
X_BUF #(
.LOC ( "SLICE_X16Y11" ))
\in/full/CLKINV (
.I(clk_BUFGP),
.O(\in/full/CLKINV_3246 )
);
X_LUT4 #(
.INIT ( 16'hFEFE ),
.LOC ( "SLICE_X23Y25" ))
\in/ld_shift_SW0 (
.ADR0(\in/bittimer [2]),
.ADR1(\in/bittimer [1]),
.ADR2(\in/bittimer [0]),
.ADR3(VCC),
.O(N25_pack_1)
);
X_LUT4 #(
.INIT ( 16'hFFEF ),
.LOC ( "SLICE_X23Y25" ))
\in/loaded_mux0000 (
.ADR0(\in/baud1/baud_1387 ),
.ADR1(\in/bittimer [3]),
.ADR2(\in/pstate [3]),
.ADR3(N25),
.O(\in/loaded_mux0000_3206 )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\in/loaded/FFX/RSTOR (
.I(reset_IBUF_1366),
.O(\in/loaded/FFX/RST )
);
X_FF #(
.LOC ( "SLICE_X23Y25" ),
.INIT ( 1'b0 ))
\in/loaded (
.I(\in/loaded/DXMUX_3209 ),
.CE(\in/loaded/CEINV_3191 ),
.CLK(\in/loaded/CLKINVNOT ),
.SET(GND),
.RST(\in/loaded/FFX/RST ),
.O(\in/loaded_1548 )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\in/loaded/DXMUX (
.I(\in/loaded/FXMUX_3208 ),
.O(\in/loaded/DXMUX_3209 )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\in/loaded/XUSED (
.I(\in/loaded/FXMUX_3208 ),
.O(\in/loaded_mux0000_0 )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\in/loaded/FXMUX (
.I(\in/loaded_mux0000_3206 ),
.O(\in/loaded/FXMUX_3208 )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\in/loaded/YUSED (
.I(N25_pack_1),
.O(N25)
);
X_INV #(
.LOC ( "SLICE_X23Y25" ))
\in/loaded/CLKINV (
.I(clk_BUFGP),
.O(\in/loaded/CLKINVNOT )
);
X_BUF #(
.LOC ( "SLICE_X23Y25" ))
\in/loaded/CEINV (
.I(\in/loaded_not0001 ),
.O(\in/loaded/CEINV_3191 )
);
X_OPAD #(
.LOC ( "PAD64" ))
\Led<2>/PAD (
.PAD(Led[2])
);
X_OBUF #(
.LOC ( "PAD64" ))
Led_2_OBUF (
.I(\Led<2>/O ),
.O(Led[2])
);
X_BUFGMUX #(
.LOC ( "BUFGMUX_X2Y11" ))
\clk_BUFGP/BUFG (
.I0(\clk_BUFGP/BUFG/I0_INV ),
.I1(GND),
.S(\clk_BUFGP/BUFG/S_INVNOT ),
.O(clk_BUFGP)
);
X_INV #(
.LOC ( "BUFGMUX_X2Y11" ))
\clk_BUFGP/BUFG/SINV (
.I(1'b1),
.O(\clk_BUFGP/BUFG/S_INVNOT )
);
X_BUF #(
.LOC ( "BUFGMUX_X2Y11" ))
\clk_BUFGP/BUFG/I0_USED (
.I(\clk/INBUF ),
.O(\clk_BUFGP/BUFG/I0_INV )
);
X_BUF #(
.LOC ( "SLICE_X19Y17" ))
\N51/XUSED (
.I(\N51/F5MUX_3779 ),
.O(N51)
);
X_MUX2 #(
.LOC ( "SLICE_X19Y17" ))
\N51/F5MUX (
.IA(N56),
.IB(N57),
.SEL(\N51/BXINV_3772 ),
.O(\N51/F5MUX_3779 )
);
X_BUF #(
.LOC ( "SLICE_X19Y17" ))
\N51/BXINV (
.I(\in/dout_fifo [2]),
.O(\N51/BXINV_3772 )
);
X_BUF #(
.LOC ( "SLICE_X11Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073/XUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073_4089 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073_0 )
);
X_BUF #(
.LOC ( "SLICE_X11Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073/YUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000029/O_pack_1 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000029/O )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\N53/XUSED (
.I(\N53/F5MUX_3804 ),
.O(N53)
);
X_MUX2 #(
.LOC ( "SLICE_X13Y11" ))
\N53/F5MUX (
.IA(N58),
.IB(N59),
.SEL(\N53/BXINV_3797 ),
.O(\N53/F5MUX_3804 )
);
X_BUF #(
.LOC ( "SLICE_X13Y11" ))
\N53/BXINV (
.I(\in/dout_fifo [2]),
.O(\N53/BXINV_3797 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\data<3>/DXMUX (
.I(\data<3>/F5MUX_3747 ),
.O(\data<3>/DXMUX_3749 )
);
X_MUX2 #(
.LOC ( "SLICE_X19Y13" ))
\data<3>/F5MUX (
.IA(N60),
.IB(N61),
.SEL(\data<3>/BXINV_3739 ),
.O(\data<3>/F5MUX_3747 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\data<3>/BXINV (
.I(addr_rx[1]),
.O(\data<3>/BXINV_3739 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\data<3>/CLKINV (
.I(clk_BUFGP),
.O(\data<3>/CLKINV_3731 )
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\data<3>/CEINV (
.I(\in/rd_fifo ),
.O(\data<3>/CEINV_3730 )
);
X_BUF #(
.LOC ( "SLICE_X28Y32" ))
\out/baud1/timer<3>/DXMUX (
.I(\out/baud1/timer_mux0000 [4]),
.O(\out/baud1/timer<3>/DXMUX_3865 )
);
X_BUF #(
.LOC ( "SLICE_X28Y32" ))
\out/baud1/timer<3>/YUSED (
.I(\out/baud1/N01_pack_2 ),
.O(\out/baud1/N01 )
);
X_BUF #(
.LOC ( "SLICE_X28Y32" ))
\out/baud1/timer<3>/CLKINV (
.I(clk_BUFGP),
.O(\out/baud1/timer<3>/CLKINV_3849 )
);
X_RAMB16_S36_S36 #(
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.WRITE_MODE_A ( "NO_CHANGE" ),
.WRITE_MODE_B ( "NO_CHANGE" ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.LOC ( "RAMB16_X0Y3" ),
.SETUP_ALL ( 227 ),
.SETUP_READ_FIRST ( 227 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram (
.CLKA(clk_BUFGP),
.CLKB(clk_BUFGP),
.ENA(1'b0),
.ENB(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 ),
.SSRA(1'b0),
.SSRB(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ),
.WEA(1'b0),
.WEB(1'b0),
.ADDRA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.ADDRB({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3>
,
\NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2>
,
\NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1>
,
\NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0>
}),
.DIA({
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA31
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA30
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA29
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA28
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA27
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA26
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA25
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA24
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA23
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA22
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA21
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA20
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA19
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA18
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA17
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA16
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA15
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA14
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA13
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA12
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA11
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA10
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA9
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA8
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA7
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA6
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA5
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA4
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA3
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA2
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA1
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA0
}),
.DIPA({
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPA3
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPA2
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPA1
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPA0
}),
.DIB({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
.DIPB({1'b0, 1'b0, 1'b0, 1'b0}),
.DOA({
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA31
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA30
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA29
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA28
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA27
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA26
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA25
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA24
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA23
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA22
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA21
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA20
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA19
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA18
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA17
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA16
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA15
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA14
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA13
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA12
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA11
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA10
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA9
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA8
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA7
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA6
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA5
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA4
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA3
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA2
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA1
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA0
}),
.DOPA({
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA3
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA2
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA1
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA0
}),
.DOB({
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB31
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB30
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB29
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB28
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB27
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB26
, \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [7],
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [6],
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB23
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB22
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB21
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB20
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB19
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB18
, \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [5],
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [4],
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB15
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB14
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB13
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB12
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB11
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB10
, \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [3],
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [2],
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB7
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB6
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB5
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB4
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB3
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB2
, \out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [1],
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [0]}),
.DOPB({
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB3
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB2
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB1
,
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB0
})
);
X_RAMB16_S36_S36 #(
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.WRITE_MODE_A ( "NO_CHANGE" ),
.WRITE_MODE_B ( "NO_CHANGE" ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.LOC ( "RAMB16_X0Y1" ),
.SETUP_ALL ( 227 ),
.SETUP_READ_FIRST ( 227 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram (
.CLKA(clk_BUFGP),
.CLKB(clk_BUFGP),
.ENA(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.ENB(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en_0 ),
.SSRA(1'b0),
.SSRB(\in/pstate [0]),
.WEA(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.WEB(1'b0),
.ADDRA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0>
}),
.ADDRB({1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0>
}),
.DIA({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25>
, \in/frame_error [7], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, \in/frame_error [6],
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16>
, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8>
, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<2>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1>
,
\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0>
}),
.DIPA({1'b0, 1'b0, 1'b0, 1'b0}),
.DIB({
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB31
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB30
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB29
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB28
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB27
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB26
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB25
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB24
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB23
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB22
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB21
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB20
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB19
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB18
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB17
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB16
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB15
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB14
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB13
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB12
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB11
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB10
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB9
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB8
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB7
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB6
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB5
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB4
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB3
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB2
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB1
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIB0
}),
.DIPB({
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB3
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB2
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB1
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIPB0
}),
.DOA({
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA31
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA30
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA29
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA28
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA27
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA26
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA25
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA24
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA23
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA22
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA21
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA20
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA19
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA18
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA17
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA16
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA15
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA14
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA13
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA12
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA11
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA10
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA9
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA8
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA7
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA6
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA5
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA4
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA3
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA2
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA1
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOA0
}),
.DOPA({
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA3
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA2
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA1
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPA0
}),
.DOB({
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB31
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB30
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB29
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB28
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB27
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB26
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB25
, \in/dout_fifo [7],
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB23
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB22
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB21
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB20
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB19
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB18
, \in/dout_fifo [6], \in/dout_fifo [5],
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB15
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB14
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB13
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB12
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB11
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB10
, \in/dout_fifo [4], \in/dout_fifo [3],
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB7
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB6
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB5
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB4
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOB3
, \in/dout_fifo [2], \in/dout_fifo [1], \in/dout_fifo [0]}),
.DOPB({
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB3
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB2
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB1
,
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DOPB0
})
);
X_BUF #(
.LOC ( "SLICE_X24Y37" ))
\out/N8/XUSED (
.I(\out/N8 ),
.O(\out/N8_0 )
);
X_BUF #(
.LOC ( "SLICE_X24Y37" ))
\out/N8/YUSED (
.I(\out/pstate_FSM_FFd1-In3_SW0/O_pack_1 ),
.O(\out/pstate_FSM_FFd1-In3_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\data<5>/DXMUX (
.I(\data_add0000[5] ),
.O(\data<5>/DXMUX_3963 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\data<5>/YUSED (
.I(\Madd_data_add0000_xor<5>11_SW0/O_pack_1 ),
.O(\Madd_data_add0000_xor<5>11_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\data<5>/CLKINV (
.I(clk_BUFGP),
.O(\data<5>/CLKINV_3947 )
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\data<5>/CEINV (
.I(\in/rd_fifo ),
.O(\data<5>/CEINV_3946 )
);
X_BUF #(
.LOC ( "SLICE_X11Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FXMUX_3832 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_3833 )
);
X_BUF #(
.LOC ( "SLICE_X11Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FXMUX_3832 )
);
X_BUF #(
.LOC ( "SLICE_X11Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/YUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168/O_pack_1 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168/O )
);
X_BUF #(
.LOC ( "SLICE_X11Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_3818 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\data<4>/DXMUX (
.I(\data_add0000[4] ),
.O(\data<4>/DXMUX_3926 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\data<4>/YUSED (
.I(\Madd_data_add0000_xor<4>12_SW0/O_pack_1 ),
.O(\Madd_data_add0000_xor<4>12_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\data<4>/CLKINV (
.I(clk_BUFGP),
.O(\data<4>/CLKINV_3909 )
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\data<4>/CEINV (
.I(\in/rd_fifo ),
.O(\data<4>/CEINV_3908 )
);
X_BUF #(
.LOC ( "SLICE_X12Y11" ))
\data<6>/DXMUX (
.I(\data_add0000[6] ),
.O(\data<6>/DXMUX_4000 )
);
X_BUF #(
.LOC ( "SLICE_X12Y11" ))
\data<6>/YUSED (
.I(\Madd_data_add0000_xor<6>12_SW0/O_pack_1 ),
.O(\Madd_data_add0000_xor<6>12_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X12Y11" ))
\data<6>/CLKINV (
.I(clk_BUFGP),
.O(\data<6>/CLKINV_3982 )
);
X_BUF #(
.LOC ( "SLICE_X12Y11" ))
\data<6>/CEINV (
.I(\in/rd_fifo ),
.O(\data<6>/CEINV_3981 )
);
X_BUF #(
.LOC ( "SLICE_X29Y32" ))
\out/baud1/baud_cmp_eq0000/XUSED (
.I(\out/baud1/baud_cmp_eq0000 ),
.O(\out/baud1/baud_cmp_eq0000_0 )
);
X_BUF #(
.LOC ( "SLICE_X29Y32" ))
\out/baud1/baud_cmp_eq0000/YUSED (
.I(\out/baud1/baud_cmp_eq0000810_pack_1 ),
.O(\out/baud1/baud_cmp_eq0000810_1573 )
);
X_BUF #(
.LOC ( "SLICE_X12Y13" ))
\data<7>/DXMUX (
.I(\data_add0000[7] ),
.O(\data<7>/DXMUX_4061 )
);
X_BUF #(
.LOC ( "SLICE_X12Y13" ))
\data<7>/YUSED (
.I(N38_pack_1),
.O(N38)
);
X_BUF #(
.LOC ( "SLICE_X12Y13" ))
\data<7>/CLKINV (
.I(clk_BUFGP),
.O(\data<7>/CLKINV_4045 )
);
X_BUF #(
.LOC ( "SLICE_X12Y13" ))
\data<7>/CEINV (
.I(\in/rd_fifo ),
.O(\data<7>/CEINV_4044 )
);
X_BUF #(
.LOC ( "SLICE_X13Y8" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_4142 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_4143 )
);
X_BUF #(
.LOC ( "SLICE_X13Y8" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/FXMUX_4142 )
);
X_BUF #(
.LOC ( "SLICE_X13Y8" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/YUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005/O_pack_2 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005/O )
);
X_BUF #(
.LOC ( "SLICE_X13Y8" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_4128 )
);
X_BUF #(
.LOC ( "SLICE_X28Y23" ))
\in/baud1/baud_cmp_eq0000/XUSED (
.I(\in/baud1/baud_cmp_eq0000 ),
.O(\in/baud1/baud_cmp_eq0000_0 )
);
X_BUF #(
.LOC ( "SLICE_X28Y23" ))
\in/baud1/baud_cmp_eq0000/YUSED (
.I(\in/baud1/baud_cmp_eq0000822/O_pack_1 ),
.O(\in/baud1/baud_cmp_eq0000822/O )
);
X_BUF #(
.LOC ( "SLICE_X20Y18" ))
\in/pstate_mux0000<3>15/XUSED (
.I(\in/pstate_mux0000<3>15_4429 ),
.O(\in/pstate_mux0000<3>15_0 )
);
X_BUF #(
.LOC ( "SLICE_X20Y18" ))
\in/pstate_mux0000<3>15/YUSED (
.I(\in/N13_pack_1 ),
.O(\in/N13 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\data<1>/DXMUX (
.I(\data_add0000[1] ),
.O(\data<1>/DXMUX_4332 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\data<1>/YUSED (
.I(\Madd_data_add0000_cy<0>_pack_2 ),
.O(Madd_data_add0000_cy[0])
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\data<1>/CLKINV (
.I(clk_BUFGP),
.O(\data<1>/CLKINV_4315 )
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\data<1>/CEINV (
.I(\in/rd_fifo ),
.O(\data<1>/CEINV_4314 )
);
X_BUF #(
.LOC ( "SLICE_X27Y37" ))
\out/bitcounter<1>/DYMUX (
.I(\out/Mcount_bitcounter1 ),
.O(\out/bitcounter<1>/DYMUX_4575 )
);
X_BUF #(
.LOC ( "SLICE_X27Y37" ))
\out/bitcounter<1>/CLKINV (
.I(clk_BUFGP),
.O(\out/bitcounter<1>/CLKINV_4565 )
);
X_BUF #(
.LOC ( "SLICE_X27Y37" ))
\out/bitcounter<1>/CEINV (
.I(\out/bitcounter_not0001_0 ),
.O(\out/bitcounter<1>/CEINV_4564 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or0000 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_4367 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/YUSED (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O_pack_2 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_4349 )
);
X_BUF #(
.LOC ( "SLICE_X9Y41" ))
\out/shift_out<3>/DXMUX (
.I(\out/shift_out_mux0000 [3]),
.O(\out/shift_out<3>/DXMUX_4748 )
);
X_BUF #(
.LOC ( "SLICE_X9Y41" ))
\out/shift_out<3>/DYMUX (
.I(\out/shift_out_mux0000 [2]),
.O(\out/shift_out<3>/DYMUX_4734 )
);
X_BUF #(
.LOC ( "SLICE_X9Y41" ))
\out/shift_out<3>/SRINV (
.I(reset_IBUF_1366),
.O(\out/shift_out<3>/SRINV_4726 )
);
X_BUF #(
.LOC ( "SLICE_X9Y41" ))
\out/shift_out<3>/CLKINV (
.I(clk_BUFGP),
.O(\out/shift_out<3>/CLKINV_4725 )
);
X_BUF #(
.LOC ( "SLICE_X9Y41" ))
\out/shift_out<3>/CEINV (
.I(\out/shift_out_not0001_0 ),
.O(\out/shift_out<3>/CEINV_4724 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\in/bittimer<3>/DXMUX (
.I(\in/Result [3]),
.O(\in/bittimer<3>/DXMUX_4507 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\in/bittimer<3>/DYMUX (
.I(\in/Result [2]),
.O(\in/bittimer<3>/DYMUX_4492 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\in/bittimer<3>/SRINV (
.I(reset_IBUF_1366),
.O(\in/bittimer<3>/SRINV_4483 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\in/bittimer<3>/CLKINV (
.I(\in/baud1/baud_1387 ),
.O(\in/bittimer<3>/CLKINV_4482 )
);
X_BUF #(
.LOC ( "SLICE_X23Y29" ))
\in/bittimer<3>/CEINV (
.I(\in/bittime_0 ),
.O(\in/bittimer<3>/CEINV_4481 )
);
X_BUF #(
.LOC ( "SLICE_X29Y33" ))
\out/baud1/timer<1>/DXMUX (
.I(\out/baud1/timer_mux0000 [6]),
.O(\out/baud1/timer<1>/DXMUX_4550 )
);
X_BUF #(
.LOC ( "SLICE_X29Y33" ))
\out/baud1/timer<1>/DYMUX (
.I(\out/baud1/timer_mux0000 [7]),
.O(\out/baud1/timer<1>/DYMUX_4535 )
);
X_BUF #(
.LOC ( "SLICE_X29Y33" ))
\out/baud1/timer<1>/SRINV (
.I(reset_IBUF_1366),
.O(\out/baud1/timer<1>/SRINV_4527 )
);
X_BUF #(
.LOC ( "SLICE_X29Y33" ))
\out/baud1/timer<1>/CLKINV (
.I(clk_BUFGP),
.O(\out/baud1/timer<1>/CLKINV_4526 )
);
X_BUF #(
.LOC ( "SLICE_X8Y41" ))
\out/shift_out<1>/DXMUX (
.I(\out/shift_out_mux0000 [1]),
.O(\out/shift_out<1>/DXMUX_4704 )
);
X_BUF #(
.LOC ( "SLICE_X8Y41" ))
\out/shift_out<1>/DYMUX (
.I(\out/shift_out_mux0000 [0]),
.O(\out/shift_out<1>/DYMUX_4690 )
);
X_BUF #(
.LOC ( "SLICE_X8Y41" ))
\out/shift_out<1>/SRINV (
.I(reset_IBUF_1366),
.O(\out/shift_out<1>/SRINV_4681 )
);
X_BUF #(
.LOC ( "SLICE_X8Y41" ))
\out/shift_out<1>/CLKINV (
.I(clk_BUFGP),
.O(\out/shift_out<1>/CLKINV_4680 )
);
X_BUF #(
.LOC ( "SLICE_X8Y41" ))
\out/shift_out<1>/CEINV (
.I(\out/shift_out_not0001_0 ),
.O(\out/shift_out<1>/CEINV_4679 )
);
X_BUF #(
.LOC ( "SLICE_X26Y22" ))
\in/baud1/timer<0>/DXMUX (
.I(\in/baud1/timer_mux0000 [7]),
.O(\in/baud1/timer<0>/DXMUX_4401 )
);
X_BUF #(
.LOC ( "SLICE_X26Y22" ))
\in/baud1/timer<0>/YUSED (
.I(\in/baud1/N01_pack_2 ),
.O(\in/baud1/N01 )
);
X_BUF #(
.LOC ( "SLICE_X26Y22" ))
\in/baud1/timer<0>/CLKINV (
.I(clk_BUFGP),
.O(\in/baud1/timer<0>/CLKINV_4383 )
);
X_BUF #(
.LOC ( "SLICE_X23Y19" ))
\in/pstate<3>/DXMUX (
.I(\in/pstate_mux0000 [2]),
.O(\in/pstate<3>/DXMUX_4295 )
);
X_BUF #(
.LOC ( "SLICE_X23Y19" ))
\in/pstate<3>/YUSED (
.I(\in/pstate_mux0000<2>18/O_pack_1 ),
.O(\in/pstate_mux0000<2>18/O )
);
X_BUF #(
.LOC ( "SLICE_X23Y19" ))
\in/pstate<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/pstate<3>/CLKINV_4278 )
);
X_BUF #(
.LOC ( "SLICE_X24Y6" ))
\data<2>/DXMUX (
.I(\data_add0000[2] ),
.O(\data<2>/DXMUX_4462 )
);
X_BUF #(
.LOC ( "SLICE_X24Y6" ))
\data<2>/YUSED (
.I(\in/dout<2>1/O_pack_1 ),
.O(\in/dout<2>1/O )
);
X_BUF #(
.LOC ( "SLICE_X24Y6" ))
\data<2>/CLKINV (
.I(clk_BUFGP),
.O(\data<2>/CLKINV_4444 )
);
X_BUF #(
.LOC ( "SLICE_X24Y6" ))
\data<2>/CEINV (
.I(\in/rd_fifo ),
.O(\data<2>/CEINV_4443 )
);
X_BUF #(
.LOC ( "SLICE_X28Y31" ))
\out/baud1/timer<5>/DXMUX (
.I(\out/baud1/timer_mux0000 [2]),
.O(\out/baud1/timer<5>/DXMUX_4618 )
);
X_BUF #(
.LOC ( "SLICE_X28Y31" ))
\out/baud1/timer<5>/DYMUX (
.I(\out/baud1/timer_mux0000 [3]),
.O(\out/baud1/timer<5>/DYMUX_4604 )
);
X_BUF #(
.LOC ( "SLICE_X28Y31" ))
\out/baud1/timer<5>/SRINV (
.I(reset_IBUF_1366),
.O(\out/baud1/timer<5>/SRINV_4595 )
);
X_BUF #(
.LOC ( "SLICE_X28Y31" ))
\out/baud1/timer<5>/CLKINV (
.I(clk_BUFGP),
.O(\out/baud1/timer<5>/CLKINV_4594 )
);
X_BUF #(
.LOC ( "SLICE_X30Y30" ))
\out/baud1/timer<7>/DXMUX (
.I(\out/baud1/timer_mux0000 [0]),
.O(\out/baud1/timer<7>/DXMUX_4660 )
);
X_BUF #(
.LOC ( "SLICE_X30Y30" ))
\out/baud1/timer<7>/DYMUX (
.I(\out/baud1/timer_mux0000 [1]),
.O(\out/baud1/timer<7>/DYMUX_4646 )
);
X_BUF #(
.LOC ( "SLICE_X30Y30" ))
\out/baud1/timer<7>/SRINV (
.I(reset_IBUF_1366),
.O(\out/baud1/timer<7>/SRINV_4637 )
);
X_BUF #(
.LOC ( "SLICE_X30Y30" ))
\out/baud1/timer<7>/CLKINV (
.I(clk_BUFGP),
.O(\out/baud1/timer<7>/CLKINV_4636 )
);
X_BUF #(
.LOC ( "SLICE_X6Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX (
.I(\in/fifo1/Result<3>1 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_4930 )
);
X_BUF #(
.LOC ( "SLICE_X6Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX (
.I(\in/fifo1/Result<2>1 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_4917 )
);
X_BUF #(
.LOC ( "SLICE_X6Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV (
.I(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_4908 )
);
X_BUF #(
.LOC ( "SLICE_X6Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_4907 )
);
X_BUF #(
.LOC ( "SLICE_X6Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_4906 )
);
X_BUF #(
.LOC ( "SLICE_X14Y10" ))
\trans<1>/DXMUX (
.I(Mcount_trans1),
.O(\trans<1>/DXMUX_5224 )
);
X_BUF #(
.LOC ( "SLICE_X14Y10" ))
\trans<1>/DYMUX (
.I(Mcount_trans),
.O(\trans<1>/DYMUX_5210 )
);
X_BUF #(
.LOC ( "SLICE_X14Y10" ))
\trans<1>/SRINV (
.I(reset_IBUF_1366),
.O(\trans<1>/SRINV_5201 )
);
X_BUF #(
.LOC ( "SLICE_X14Y10" ))
\trans<1>/CLKINV (
.I(clk_BUFGP),
.O(\trans<1>/CLKINV_5200 )
);
X_BUF #(
.LOC ( "SLICE_X24Y7" ))
\data<0>/DYMUX (
.I(\data_add0000[0] ),
.O(\data<0>/DYMUX_5042 )
);
X_BUF #(
.LOC ( "SLICE_X24Y7" ))
\data<0>/CLKINV (
.I(clk_BUFGP),
.O(\data<0>/CLKINV_5032 )
);
X_BUF #(
.LOC ( "SLICE_X24Y7" ))
\data<0>/CEINV (
.I(\in/rd_fifo ),
.O(\data<0>/CEINV_5031 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\out/shift_out<7>/DXMUX (
.I(\out/shift_out_mux0000 [7]),
.O(\out/shift_out<7>/DXMUX_4836 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\out/shift_out<7>/DYMUX (
.I(\out/shift_out_mux0000 [6]),
.O(\out/shift_out<7>/DYMUX_4822 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\out/shift_out<7>/SRINV (
.I(reset_IBUF_1366),
.O(\out/shift_out<7>/SRINV_4814 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\out/shift_out<7>/CLKINV (
.I(clk_BUFGP),
.O(\out/shift_out<7>/CLKINV_4813 )
);
X_BUF #(
.LOC ( "SLICE_X15Y33" ))
\out/shift_out<7>/CEINV (
.I(\out/shift_out_not0001_0 ),
.O(\out/shift_out<7>/CEINV_4812 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\out/shift_out<8>/DYMUX (
.I(\out/shift_out_mux0000 [8]),
.O(\out/shift_out<8>/DYMUX_4887 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\out/shift_out<8>/CLKINV (
.I(clk_BUFGP),
.O(\out/shift_out<8>/CLKINV_4877 )
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\out/shift_out<8>/CEINV (
.I(\out/shift_out_not0001_0 ),
.O(\out/shift_out<8>/CEINV_4876 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\out/shift_out<5>/DXMUX (
.I(\out/shift_out_mux0000 [5]),
.O(\out/shift_out<5>/DXMUX_4792 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\out/shift_out<5>/DYMUX (
.I(\out/shift_out_mux0000 [4]),
.O(\out/shift_out<5>/DYMUX_4778 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\out/shift_out<5>/SRINV (
.I(reset_IBUF_1366),
.O(\out/shift_out<5>/SRINV_4770 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\out/shift_out<5>/CLKINV (
.I(clk_BUFGP),
.O(\out/shift_out<5>/CLKINV_4769 )
);
X_BUF #(
.LOC ( "SLICE_X13Y38" ))
\out/shift_out<5>/CEINV (
.I(\out/shift_out_not0001_0 ),
.O(\out/shift_out<5>/CEINV_4768 )
);
X_BUF #(
.LOC ( "SLICE_X13Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_5084 )
);
X_BUF #(
.LOC ( "SLICE_X13Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DYMUX_5070 )
);
X_BUF #(
.LOC ( "SLICE_X13Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_5062 )
);
X_BUF #(
.LOC ( "SLICE_X13Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_5061 )
);
X_BUF #(
.LOC ( "SLICE_X22Y34" ))
\out/bittimer<3>/DXMUX (
.I(\out/Result [3]),
.O(\out/bittimer<3>/DXMUX_5129 )
);
X_BUF #(
.LOC ( "SLICE_X22Y34" ))
\out/bittimer<3>/DYMUX (
.I(\out/Result [2]),
.O(\out/bittimer<3>/DYMUX_5114 )
);
X_BUF #(
.LOC ( "SLICE_X22Y34" ))
\out/bittimer<3>/SRINV (
.I(reset_IBUF_1366),
.O(\out/bittimer<3>/SRINV_5105 )
);
X_BUF #(
.LOC ( "SLICE_X22Y34" ))
\out/bittimer<3>/CLKINV (
.I(\out/baud1/baud_1432 ),
.O(\out/bittimer<3>/CLKINV_5104 )
);
X_BUF #(
.LOC ( "SLICE_X22Y34" ))
\out/bittimer<3>/CEINV (
.I(\out/bittime_0 ),
.O(\out/bittimer<3>/CEINV_5103 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\pstate_FSM_FFd3/DYMUX (
.I(\pstate_FSM_FFd3-In ),
.O(\pstate_FSM_FFd3/DYMUX_5153 )
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\pstate_FSM_FFd3/CLKINV (
.I(clk_BUFGP),
.O(\pstate_FSM_FFd3/CLKINV_5143 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\in/in_two/DYMUX (
.I(\in/Mshreg_in_two ),
.O(\in/in_two/DYMUX_5185 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\in/in_two/DIG_MUX (
.I(rx_IBUF_1384),
.O(\in/in_two/DIG_MUX_5174 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\in/in_two/SRINV (
.I(1'b1),
.O(\in/in_two/SRINV_5168 )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\in/in_two/CLKINV (
.I(clk_BUFGP),
.O(\in/in_two/CLKINV_5172 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX (
.I(\out/fifo1/Result [3]),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_5016 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX (
.I(\out/fifo1/Result [2]),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_5001 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_4992 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_4991 )
);
X_BUF #(
.LOC ( "SLICE_X3Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_4990 )
);
X_BUF #(
.LOC ( "SLICE_X14Y19" ))
\in/frame_error<8>/DYMUX (
.I(\in/frame_error_8_or0000 ),
.O(\in/frame_error<8>/DYMUX_4861 )
);
X_BUF #(
.LOC ( "SLICE_X14Y19" ))
\in/frame_error<8>/CLKINV (
.I(clk_BUFGP),
.O(\in/frame_error<8>/CLKINV_4850 )
);
X_BUF #(
.LOC ( "SLICE_X14Y19" ))
\in/frame_error<8>/CEINV (
.I(\in/finish ),
.O(\in/frame_error<8>/CEINV_4849 )
);
X_BUF #(
.LOC ( "SLICE_X8Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX (
.I(\in/fifo1/Result [3]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_4972 )
);
X_BUF #(
.LOC ( "SLICE_X8Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX (
.I(\in/fifo1/Result [2]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_4959 )
);
X_BUF #(
.LOC ( "SLICE_X8Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV (
.I(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_4950 )
);
X_BUF #(
.LOC ( "SLICE_X8Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_4949 )
);
X_BUF #(
.LOC ( "SLICE_X8Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_4948 )
);
X_BUF #(
.LOC ( "SLICE_X31Y22" ))
\in/baud1/Madd_timer_addsub0000_cy<5>/XUSED (
.I(\in/baud1/Madd_timer_addsub0000_cy[5] ),
.O(\in/baud1/Madd_timer_addsub0000_cy<5>_0 )
);
X_BUF #(
.LOC ( "SLICE_X31Y22" ))
\in/baud1/Madd_timer_addsub0000_cy<5>/YUSED (
.I(\in/baud1/Madd_timer_addsub0000_cy<3>_pack_1 ),
.O(\in/baud1/Madd_timer_addsub0000_cy[3] )
);
X_BUF #(
.LOC ( "SLICE_X25Y37" ))
\out/bitcounter_not0001/XUSED (
.I(\out/bitcounter_not0001_4264 ),
.O(\out/bitcounter_not0001_0 )
);
X_BUF #(
.LOC ( "SLICE_X25Y37" ))
\out/bitcounter_not0001/YUSED (
.I(\out/bitcounter_not0001_SW0/O_pack_1 ),
.O(\out/bitcounter_not0001_SW0/O )
);
X_BUF #(
.LOC ( "SLICE_X12Y9" ))
\in/fifo1/N5/XUSED (
.I(\in/fifo1/N5 ),
.O(\in/fifo1/N5_0 )
);
X_BUF #(
.LOC ( "SLICE_X12Y9" ))
\in/fifo1/N5/YUSED (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000021/O_pack_1 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000021/O )
);
X_BUF #(
.LOC ( "SLICE_X29Y30" ))
\out/baud1/Madd_timer_addsub0000_cy<5>/XUSED (
.I(\out/baud1/Madd_timer_addsub0000_cy[5] ),
.O(\out/baud1/Madd_timer_addsub0000_cy<5>_0 )
);
X_BUF #(
.LOC ( "SLICE_X29Y30" ))
\out/baud1/Madd_timer_addsub0000_cy<5>/YUSED (
.I(\out/baud1/Madd_timer_addsub0000_cy<3>_pack_1 ),
.O(\out/baud1/Madd_timer_addsub0000_cy[3] )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\out/shift_out_not0001/XUSED (
.I(\out/shift_out_not0001 ),
.O(\out/shift_out_not0001_0 )
);
X_BUF #(
.LOC ( "SLICE_X23Y34" ))
\out/shift_out_not0001/YUSED (
.I(\out/N7_pack_1 ),
.O(\out/N7 )
);
X_BUF #(
.LOC ( "SLICE_X21Y19" ))
\in/pstate<4>/DXMUX (
.I(\in/pstate_mux0000 [1]),
.O(\in/pstate<4>/DXMUX_5267 )
);
X_BUF #(
.LOC ( "SLICE_X21Y19" ))
\in/pstate<4>/DYMUX (
.I(\in/pstate<4>/GYMUX_5250 ),
.O(\in/pstate<4>/DYMUX_5251 )
);
X_BUF #(
.LOC ( "SLICE_X21Y19" ))
\in/pstate<4>/YUSED (
.I(\in/pstate<4>/GYMUX_5250 ),
.O(\in/finish )
);
X_BUF #(
.LOC ( "SLICE_X21Y19" ))
\in/pstate<4>/GYMUX (
.I(\in/finish_pack_1 ),
.O(\in/pstate<4>/GYMUX_5250 )
);
X_BUF #(
.LOC ( "SLICE_X21Y19" ))
\in/pstate<4>/SRINV (
.I(reset_IBUF_1366),
.O(\in/pstate<4>/SRINV_5243 )
);
X_BUF #(
.LOC ( "SLICE_X21Y19" ))
\in/pstate<4>/CLKINV (
.I(clk_BUFGP),
.O(\in/pstate<4>/CLKINV_5242 )
);
X_BUF #(
.LOC ( "SLICE_X28Y22" ))
\in/baud1/timer<5>/DXMUX (
.I(\in/baud1/timer_mux0000 [2]),
.O(\in/baud1/timer<5>/DXMUX_5443 )
);
X_BUF #(
.LOC ( "SLICE_X28Y22" ))
\in/baud1/timer<5>/DYMUX (
.I(\in/baud1/timer_mux0000 [3]),
.O(\in/baud1/timer<5>/DYMUX_5429 )
);
X_BUF #(
.LOC ( "SLICE_X28Y22" ))
\in/baud1/timer<5>/SRINV (
.I(reset_IBUF_1366),
.O(\in/baud1/timer<5>/SRINV_5420 )
);
X_BUF #(
.LOC ( "SLICE_X28Y22" ))
\in/baud1/timer<5>/CLKINV (
.I(clk_BUFGP),
.O(\in/baud1/timer<5>/CLKINV_5419 )
);
X_BUF #(
.LOC ( "SLICE_X23Y18" ))
\in/bitcounter<1>/DXMUX (
.I(\in/Mcount_bitcounter1 ),
.O(\in/bitcounter<1>/DXMUX_5640 )
);
X_BUF #(
.LOC ( "SLICE_X23Y18" ))
\in/bitcounter<1>/YUSED (
.I(N11_pack_2),
.O(N11)
);
X_BUF #(
.LOC ( "SLICE_X23Y18" ))
\in/bitcounter<1>/CLKINV (
.I(clk_BUFGP),
.O(\in/bitcounter<1>/CLKINV_5622 )
);
X_BUF #(
.LOC ( "SLICE_X23Y18" ))
\in/bitcounter<1>/CEINV (
.I(\in/bitcounter_not0001_0 ),
.O(\in/bitcounter<1>/CEINV_5621 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\in/baud1/timer<3>/DXMUX (
.I(\in/baud1/timer_mux0000 [4]),
.O(\in/baud1/timer<3>/DXMUX_5401 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\in/baud1/timer<3>/DYMUX (
.I(\in/baud1/timer_mux0000 [5]),
.O(\in/baud1/timer<3>/DYMUX_5387 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\in/baud1/timer<3>/SRINV (
.I(reset_IBUF_1366),
.O(\in/baud1/timer<3>/SRINV_5379 )
);
X_BUF #(
.LOC ( "SLICE_X30Y22" ))
\in/baud1/timer<3>/CLKINV (
.I(clk_BUFGP),
.O(\in/baud1/timer<3>/CLKINV_5378 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX_5336 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DYMUX_5337 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/GYMUX_5336 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_5328 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\in/pstate<0>/DYMUX (
.I(\in/pstate_mux0000 [5]),
.O(\in/pstate<0>/DYMUX_5314 )
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\in/pstate<0>/CLKINV (
.I(clk_BUFGP),
.O(\in/pstate<0>/CLKINV_5305 )
);
X_BUF #(
.LOC ( "SLICE_X29Y22" ))
\in/baud1/timer<7>/DXMUX (
.I(\in/baud1/timer_mux0000 [0]),
.O(\in/baud1/timer<7>/DXMUX_5485 )
);
X_BUF #(
.LOC ( "SLICE_X29Y22" ))
\in/baud1/timer<7>/DYMUX (
.I(\in/baud1/timer_mux0000 [1]),
.O(\in/baud1/timer<7>/DYMUX_5471 )
);
X_BUF #(
.LOC ( "SLICE_X29Y22" ))
\in/baud1/timer<7>/SRINV (
.I(reset_IBUF_1366),
.O(\in/baud1/timer<7>/SRINV_5462 )
);
X_BUF #(
.LOC ( "SLICE_X29Y22" ))
\in/baud1/timer<7>/CLKINV (
.I(clk_BUFGP),
.O(\in/baud1/timer<7>/CLKINV_5461 )
);
X_BUF #(
.LOC ( "SLICE_X30Y23" ))
\in/baud1/timer<1>/DYMUX (
.I(\in/baud1/timer_mux0000 [6]),
.O(\in/baud1/timer<1>/DYMUX_5359 )
);
X_BUF #(
.LOC ( "SLICE_X30Y23" ))
\in/baud1/timer<1>/CLKINV (
.I(clk_BUFGP),
.O(\in/baud1/timer<1>/CLKINV_5349 )
);
X_BUF #(
.LOC ( "SLICE_X1Y41" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/DYMUX (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/BYINV_5565 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/DYMUX_5566 )
);
X_BUF #(
.LOC ( "SLICE_X1Y41" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/BYINV (
.I(1'b0),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/BYINV_5565 )
);
X_BUF #(
.LOC ( "SLICE_X1Y41" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CLKINV (
.I(clk_BUFGP),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CLKINV_5563 )
);
X_BUF #(
.LOC ( "SLICE_X1Y41" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CEINV (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1377 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CEINV_5562 )
);
X_BUF #(
.LOC ( "SLICE_X18Y11" ))
\dout<1>/XUSED (
.I(\addr_rx<1>_pack_1 ),
.O(addr_rx[1])
);
X_BUF #(
.LOC ( "SLICE_X18Y11" ))
\dout<1>/DYMUX (
.I(\dout<1>/GYMUX_5538 ),
.O(\dout<1>/DYMUX_5539 )
);
X_BUF #(
.LOC ( "SLICE_X18Y11" ))
\dout<1>/YUSED (
.I(\dout<1>/GYMUX_5538 ),
.O(\Madd_data_add0000_lut<1>_0 )
);
X_BUF #(
.LOC ( "SLICE_X18Y11" ))
\dout<1>/GYMUX (
.I(Madd_data_add0000_lut[1]),
.O(\dout<1>/GYMUX_5538 )
);
X_BUF #(
.LOC ( "SLICE_X18Y11" ))
\dout<1>/CLKINV (
.I(clk_BUFGP),
.O(\dout<1>/CLKINV_5528 )
);
X_BUF #(
.LOC ( "SLICE_X21Y35" ))
\out/bittime/YUSED (
.I(\out/bittime ),
.O(\out/bittime_0 )
);
X_BUF #(
.LOC ( "SLICE_X21Y24" ))
\in/load/DYMUX (
.I(\in/load/GYMUX_5290 ),
.O(\in/load/DYMUX_5291 )
);
X_BUF #(
.LOC ( "SLICE_X21Y24" ))
\in/load/YUSED (
.I(\in/load/GYMUX_5290 ),
.O(\in/ld_shift_0 )
);
X_BUF #(
.LOC ( "SLICE_X21Y24" ))
\in/load/GYMUX (
.I(\in/ld_shift_5288 ),
.O(\in/load/GYMUX_5290 )
);
X_BUF #(
.LOC ( "SLICE_X21Y24" ))
\in/load/CLKINV (
.I(clk_BUFGP),
.O(\in/load/CLKINV_5282 )
);
X_BUF #(
.LOC ( "SLICE_X14Y11" ))
\in/fifo1/N11/XUSED (
.I(\in/fifo1/N11 ),
.O(\in/fifo1/N11_0 )
);
X_BUF #(
.LOC ( "SLICE_X14Y11" ))
\in/fifo1/N11/YUSED (
.I(\in/rd_fifo_pack_1 ),
.O(\in/rd_fifo )
);
X_INV #(
.LOC ( "SLICE_X23Y27" ))
\in/bittimer<0>/DXMUX (
.I(\in/bittimer [0]),
.O(\in/bittimer<0>/DXMUX_5602 )
);
X_BUF #(
.LOC ( "SLICE_X23Y27" ))
\in/bittimer<0>/DYMUX (
.I(\in/Result [1]),
.O(\in/bittimer<0>/DYMUX_5593 )
);
X_BUF #(
.LOC ( "SLICE_X23Y27" ))
\in/bittimer<0>/SRINV (
.I(reset_IBUF_1366),
.O(\in/bittimer<0>/SRINV_5583 )
);
X_BUF #(
.LOC ( "SLICE_X23Y27" ))
\in/bittimer<0>/CLKINV (
.I(\in/baud1/baud_1387 ),
.O(\in/bittimer<0>/CLKINV_5582 )
);
X_BUF #(
.LOC ( "SLICE_X23Y27" ))
\in/bittimer<0>/CEINV (
.I(\in/bittime_0 ),
.O(\in/bittimer<0>/CEINV_5581 )
);
X_FF #(
.LOC ( "SLICE_X2Y31" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_0 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX_2730 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_2726 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_2727 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_2728 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0])
);
X_FF #(
.LOC ( "SLICE_X2Y30" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_2839 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_2826 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_2827 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_2828 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
X_LUT4 #(
.INIT ( 16'h3C3C ),
.LOC ( "SLICE_X10Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168_SW1 (
.ADR0(VCC),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.ADR3(VCC),
.O(\in/fifo1/N7 )
);
X_FF #(
.LOC ( "SLICE_X2Y30" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_2830 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_2826 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_2827 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_2828 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
X_SFF #(
.LOC ( "SLICE_X7Y3" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DYMUX_2806 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_2802 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_2803 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_2804 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
X_SFF #(
.LOC ( "SLICE_X8Y3" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DYMUX_2782 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_2778 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_2779 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_2780 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
X_SFF #(
.LOC ( "SLICE_X7Y3" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/DXMUX_2813 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CEINV_2802 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/CLKINV_2803 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<3>/SRINV_2804 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
X_FF #(
.LOC ( "SLICE_X2Y31" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_1 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX_2739 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_2726 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_2727 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_2728 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
X_SFF #(
.LOC ( "SLICE_X8Y3" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/DXMUX_2789 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CEINV_2778 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/CLKINV_2779 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<3>/SRINV_2780 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
X_LUT4 #(
.INIT ( 16'h70F0 ),
.LOC ( "SLICE_X17Y11" ))
\in/wr_control1 (
.ADR0(trans[0]),
.ADR1(pstate_FSM_FFd2_1518),
.ADR2(pstate_FSM_FFd4_1516),
.ADR3(trans[1]),
.O(\in/wr_control )
);
X_FF #(
.LOC ( "SLICE_X14Y20" ),
.INIT ( 1'b1 ))
\in/shift_0 (
.I(\in/shift<1>/DYMUX_1623 ),
.CE(\in/shift<1>/CEINV_1619 ),
.CLK(\in/shift<1>/CLKINV_1620 ),
.SET(\in/shift<1>/SRINV_1621 ),
.RST(GND),
.O(\in/shift [0])
);
X_FF #(
.LOC ( "SLICE_X14Y20" ),
.INIT ( 1'b1 ))
\in/shift_1 (
.I(\in/shift<1>/DXMUX_1631 ),
.CE(\in/shift<1>/CEINV_1619 ),
.CLK(\in/shift<1>/CLKINV_1620 ),
.SET(\in/shift<1>/SRINV_1621 ),
.RST(GND),
.O(\in/shift [1])
);
X_FF #(
.LOC ( "SLICE_X21Y10" ),
.INIT ( 1'b0 ))
\in/control_0 (
.I(\in/control<0>/DYMUX_1647 ),
.CE(\in/control<0>/CEINV_1643 ),
.CLK(\in/control<0>/CLKINV_1644 ),
.SET(GND),
.RST(\in/control<0>/FFY/RSTAND_1653 ),
.O(\in/control [0])
);
X_BUF #(
.LOC ( "SLICE_X21Y10" ))
\in/control<0>/FFY/RSTAND (
.I(reset_IBUF_1366),
.O(\in/control<0>/FFY/RSTAND_1653 )
);
X_FF #(
.LOC ( "SLICE_X16Y20" ),
.INIT ( 1'b1 ))
\in/shift_2 (
.I(\in/shift<3>/DYMUX_1666 ),
.CE(\in/shift<3>/CEINV_1662 ),
.CLK(\in/shift<3>/CLKINV_1663 ),
.SET(\in/shift<3>/SRINV_1664 ),
.RST(GND),
.O(\in/shift [2])
);
X_LUT4 #(
.INIT ( 16'h5450 ),
.LOC ( "SLICE_X20Y21" ))
\in/pstate_mux0000<4> (
.ADR0(\in/control [2]),
.ADR1(\in/pstate [0]),
.ADR2(N13),
.ADR3(\in/control [0]),
.O(\in/pstate_mux0000 [4])
);
X_FF #(
.LOC ( "SLICE_X15Y21" ),
.INIT ( 1'b1 ))
\in/shift_6 (
.I(\in/shift<7>/DYMUX_1786 ),
.CE(\in/shift<7>/CEINV_1782 ),
.CLK(\in/shift<7>/CLKINV_1783 ),
.SET(\in/shift<7>/SRINV_1784 ),
.RST(GND),
.O(\in/shift [6])
);
X_FF #(
.LOC ( "SLICE_X15Y21" ),
.INIT ( 1'b1 ))
\in/shift_7 (
.I(\in/shift<7>/DXMUX_1794 ),
.CE(\in/shift<7>/CEINV_1782 ),
.CLK(\in/shift<7>/CLKINV_1783 ),
.SET(\in/shift<7>/SRINV_1784 ),
.RST(GND),
.O(\in/shift [7])
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X0Y40" ),
.XON ( "FALSE" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DXMUX_1736 ),
.CE(VCC),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV_1729 ),
.SET(GND),
.RST(GND),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1379 )
);
X_FF #(
.LOC ( "SLICE_X17Y21" ),
.INIT ( 1'b1 ))
\in/shift_5 (
.I(\in/shift<5>/DXMUX_1717 ),
.CE(\in/shift<5>/CEINV_1705 ),
.CLK(\in/shift<5>/CLKINV_1706 ),
.SET(\in/shift<5>/SRINV_1707 ),
.RST(GND),
.O(\in/shift [5])
);
X_LUT4 #(
.INIT ( 16'hFCF0 ),
.LOC ( "SLICE_X20Y21" ))
\in/pstate_mux0000<4>_SW0 (
.ADR0(VCC),
.ADR1(rx_IBUF_1384),
.ADR2(\in/pstate [4]),
.ADR3(\in/pstate [1]),
.O(N13_pack_2)
);
X_FF #(
.LOC ( "SLICE_X21Y13" ),
.INIT ( 1'b0 ))
\in/control_2 (
.I(\in/control<2>/DYMUX_1690 ),
.CE(\in/control<2>/CEINV_1686 ),
.CLK(\in/control<2>/CLKINV_1687 ),
.SET(GND),
.RST(\in/control<2>/FFY/RSTAND_1696 ),
.O(\in/control [2])
);
X_BUF #(
.LOC ( "SLICE_X21Y13" ))
\in/control<2>/FFY/RSTAND (
.I(reset_IBUF_1366),
.O(\in/control<2>/FFY/RSTAND_1696 )
);
X_LUT4 #(
.INIT ( 16'hFFFE ),
.LOC ( "SLICE_X25Y25" ))
\in/pstate_mux0000<2>4 (
.ADR0(\in/bittimer [3]),
.ADR1(\in/bittimer [1]),
.ADR2(\in/bittimer [2]),
.ADR3(\in/bittimer [0]),
.O(\in/pstate_mux0000<2>4_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X16Y20" ),
.INIT ( 1'b1 ))
\in/shift_3 (
.I(\in/shift<3>/DXMUX_1674 ),
.CE(\in/shift<3>/CEINV_1662 ),
.CLK(\in/shift<3>/CLKINV_1663 ),
.SET(\in/shift<3>/SRINV_1664 ),
.RST(GND),
.O(\in/shift [3])
);
X_FF #(
.LOC ( "SLICE_X17Y21" ),
.INIT ( 1'b1 ))
\in/shift_4 (
.I(\in/shift<5>/DYMUX_1709 ),
.CE(\in/shift<5>/CEINV_1705 ),
.CLK(\in/shift<5>/CLKINV_1706 ),
.SET(\in/shift<5>/SRINV_1707 ),
.RST(GND),
.O(\in/shift [4])
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X0Y40" ),
.XON ( "FALSE" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/DYMUX_1731 ),
.CE(VCC),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2/CLKINV_1729 ),
.SET(GND),
.RST(GND),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1_1377 )
);
X_FF #(
.LOC ( "SLICE_X20Y21" ),
.INIT ( 1'b0 ))
\in/pstate_1 (
.I(\in/pstate<1>/DXMUX_1768 ),
.CE(VCC),
.CLK(\in/pstate<1>/CLKINV_1751 ),
.SET(GND),
.RST(\in/pstate<1>/FFX/RSTAND_1773 ),
.O(\in/pstate [1])
);
X_BUF #(
.LOC ( "SLICE_X20Y21" ))
\in/pstate<1>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\in/pstate<1>/FFX/RSTAND_1773 )
);
X_FF #(
.LOC ( "SLICE_X17Y20" ),
.INIT ( 1'b1 ))
\in/shift_8 (
.I(\in/shift<9>/DYMUX_1836 ),
.CE(\in/shift<9>/CEINV_1832 ),
.CLK(\in/shift<9>/CLKINV_1833 ),
.SET(\in/shift<9>/SRINV_1834 ),
.RST(GND),
.O(\in/shift [8])
);
X_FF #(
.LOC ( "SLICE_X17Y20" ),
.INIT ( 1'b1 ))
\in/shift_9 (
.I(\in/shift<9>/DXMUX_1844 ),
.CE(\in/shift<9>/CEINV_1832 ),
.CLK(\in/shift<9>/CLKINV_1833 ),
.SET(\in/shift<9>/SRINV_1834 ),
.RST(GND),
.O(\in/shift [9])
);
X_LUT4 #(
.INIT ( 16'h0F00 ),
.LOC ( "SLICE_X20Y20" ))
\in/pstate_mux0000<3>2 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(rx_IBUF_1384),
.ADR3(\in/pstate [1]),
.O(\in/pstate_mux0000<3>2_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h0F0B ),
.LOC ( "SLICE_X20Y20" ))
\in/pstate_mux0000<3>30 (
.ADR0(\in/pstate_mux0000<3>15_0 ),
.ADR1(\in/loaded_mux0000_0 ),
.ADR2(\in/control [2]),
.ADR3(\in/pstate_mux0000<3>2_1402 ),
.O(\in/pstate_mux0000 [3])
);
X_LUT4 #(
.INIT ( 16'hCC88 ),
.LOC ( "SLICE_X25Y25" ))
\in/pstate_mux0000<2>10 (
.ADR0(\in/baud1/baud_1387 ),
.ADR1(\in/pstate [3]),
.ADR2(VCC),
.ADR3(\in/pstate_mux0000<2>4_1389 ),
.O(\in/pstate_mux0000<2>10_1822 )
);
X_FF #(
.LOC ( "SLICE_X17Y18" ),
.INIT ( 1'b0 ))
\in/frame_error_2 (
.I(\in/frame_error<3>/DYMUX_1925 ),
.CE(\in/frame_error<3>/CEINV_1921 ),
.CLK(\in/frame_error<3>/CLKINV_1922 ),
.SET(GND),
.RST(\in/frame_error<3>/SRINV_1923 ),
.O(\in/frame_error [2])
);
X_FF #(
.LOC ( "SLICE_X17Y18" ),
.INIT ( 1'b0 ))
\in/frame_error_3 (
.I(\in/frame_error<3>/DXMUX_1934 ),
.CE(\in/frame_error<3>/CEINV_1921 ),
.CLK(\in/frame_error<3>/CLKINV_1922 ),
.SET(GND),
.RST(\in/frame_error<3>/SRINV_1923 ),
.O(\in/frame_error [3])
);
X_FF #(
.LOC ( "SLICE_X15Y18" ),
.INIT ( 1'b0 ))
\in/frame_error_1 (
.I(\in/frame_error<1>/DXMUX_1871 ),
.CE(\in/frame_error<1>/CEINV_1858 ),
.CLK(\in/frame_error<1>/CLKINV_1859 ),
.SET(GND),
.RST(\in/frame_error<1>/SRINV_1860 ),
.O(\in/frame_error [1])
);
X_FF #(
.LOC ( "SLICE_X5Y40" ),
.INIT ( 1'b1 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg_0 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DYMUX_2868 ),
.CE(VCC),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/CLKINV_2865 ),
.SET(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/SRINV_2866 ),
.RST(GND),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] )
);
X_FF #(
.LOC ( "SLICE_X15Y18" ),
.INIT ( 1'b0 ))
\in/frame_error_0 (
.I(\in/frame_error<1>/DYMUX_1862 ),
.CE(\in/frame_error<1>/CEINV_1858 ),
.CLK(\in/frame_error<1>/CLKINV_1859 ),
.SET(GND),
.RST(\in/frame_error<1>/SRINV_1860 ),
.O(\in/frame_error [0])
);
X_FF #(
.LOC ( "SLICE_X20Y20" ),
.INIT ( 1'b0 ))
\in/pstate_2 (
.I(\in/pstate<2>/DXMUX_1907 ),
.CE(VCC),
.CLK(\in/pstate<2>/CLKINV_1889 ),
.SET(GND),
.RST(\in/pstate<2>/FFX/RSTAND_1912 ),
.O(\in/pstate [2])
);
X_BUF #(
.LOC ( "SLICE_X20Y20" ))
\in/pstate<2>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\in/pstate<2>/FFX/RSTAND_1912 )
);
X_LUT4 #(
.INIT ( 16'hFFA8 ),
.LOC ( "SLICE_X22Y18" ))
\in/bittime1 (
.ADR0(\in/pstate [2]),
.ADR1(\in/N13 ),
.ADR2(\in/bitcounter [0]),
.ADR3(\in/pstate [3]),
.O(\in/bittime )
);
X_FF #(
.LOC ( "SLICE_X22Y18" ),
.INIT ( 1'b0 ))
\in/bitcounter_0 (
.I(\in/bitcounter<0>/DXMUX_2040 ),
.CE(\in/bitcounter<0>/CEINV_2022 ),
.CLK(\in/bitcounter<0>/CLKINV_2023 ),
.SET(GND),
.RST(\in/bitcounter<0>/FFX/RSTAND_2046 ),
.O(\in/bitcounter [0])
);
X_BUF #(
.LOC ( "SLICE_X22Y18" ))
\in/bitcounter<0>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\in/bitcounter<0>/FFX/RSTAND_2046 )
);
X_LUT4 #(
.INIT ( 16'h0F00 ),
.LOC ( "SLICE_X1Y40" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb1 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d2_1379 ),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1378 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_comb )
);
X_LUT4 #(
.INIT ( 16'hF555 ),
.LOC ( "SLICE_X19Y12" ))
\in/control_2_not00011 (
.ADR0(\in/control [0]),
.ADR1(VCC),
.ADR2(\in/full ),
.ADR3(\in/frame_ready_1417 ),
.O(\in/control_2_not0001 )
);
X_FF #(
.LOC ( "SLICE_X3Y19" ),
.INIT ( 1'b0 ))
\in/frame_error_5 (
.I(\in/frame_error<5>/DXMUX_1962 ),
.CE(\in/frame_error<5>/CEINV_1949 ),
.CLK(\in/frame_error<5>/CLKINV_1950 ),
.SET(GND),
.RST(\in/frame_error<5>/SRINV_1951 ),
.O(\in/frame_error [5])
);
X_FF #(
.LOC ( "SLICE_X19Y12" ),
.INIT ( 1'b0 ))
\in/control_1 (
.I(\in/control<1>/DXMUX_2076 ),
.CE(VCC),
.CLK(\in/control<1>/CLKINV_2057 ),
.SET(GND),
.RST(\in/control<1>/FFX/RSTAND_2081 ),
.O(\in/control [1])
);
X_BUF #(
.LOC ( "SLICE_X19Y12" ))
\in/control<1>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\in/control<1>/FFX/RSTAND_2081 )
);
X_LUT4 #(
.INIT ( 16'h00DD ),
.LOC ( "SLICE_X22Y18" ))
\in/Mcount_bitcounter_xor<0>11 (
.ADR0(\in/pstate [2]),
.ADR1(\in/N13 ),
.ADR2(VCC),
.ADR3(\in/bitcounter [0]),
.O(\in/Mcount_bitcounter )
);
X_LUT4 #(
.INIT ( 16'h2222 ),
.LOC ( "SLICE_X19Y12" ))
\in/control_1_mux00001 (
.ADR0(\in/control [0]),
.ADR1(\in/empty ),
.ADR2(VCC),
.ADR3(VCC),
.O(\in/control_1_mux0000 )
);
X_FF #(
.LOC ( "SLICE_X3Y18" ),
.INIT ( 1'b0 ))
\in/frame_error_7 (
.I(\in/frame_error<7>/DXMUX_1990 ),
.CE(\in/frame_error<7>/CEINV_1977 ),
.CLK(\in/frame_error<7>/CLKINV_1978 ),
.SET(GND),
.RST(\in/frame_error<7>/SRINV_1979 ),
.O(\in/frame_error [7])
);
X_FF #(
.LOC ( "SLICE_X3Y18" ),
.INIT ( 1'b0 ))
\in/frame_error_6 (
.I(\in/frame_error<7>/DYMUX_1981 ),
.CE(\in/frame_error<7>/CEINV_1977 ),
.CLK(\in/frame_error<7>/CLKINV_1978 ),
.SET(GND),
.RST(\in/frame_error<7>/SRINV_1979 ),
.O(\in/frame_error [6])
);
X_FF #(
.LOC ( "SLICE_X3Y19" ),
.INIT ( 1'b0 ))
\in/frame_error_4 (
.I(\in/frame_error<5>/DYMUX_1953 ),
.CE(\in/frame_error<5>/CEINV_1949 ),
.CLK(\in/frame_error<5>/CLKINV_1950 ),
.SET(GND),
.RST(\in/frame_error<5>/SRINV_1951 ),
.O(\in/frame_error [4])
);
X_LUT4 #(
.INIT ( 16'hA251 ),
.LOC ( "SLICE_X10Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073_SW0 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.ADR1(\in/pstate [4]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1442 ),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\in/fifo1/N9 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X10Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1>11 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\in/fifo1/Result<1>1 )
);
X_SFF #(
.LOC ( "SLICE_X10Y3" ),
.INIT ( 1'b1 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2219 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2193 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2194 ),
.SET(GND),
.RST(GND),
.SSET(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2195 ),
.SRST(GND),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
X_FF #(
.LOC ( "SLICE_X22Y35" ),
.INIT ( 1'b0 ))
\out/pstate_FSM_FFd1 (
.I(\out/pstate_FSM_FFd1/DXMUX_2161 ),
.CE(VCC),
.CLK(\out/pstate_FSM_FFd1/CLKINV_2145 ),
.SET(GND),
.RST(\out/pstate_FSM_FFd1/FFX/RSTAND_2166 ),
.O(\out/pstate_FSM_FFd1_1425 )
);
X_BUF #(
.LOC ( "SLICE_X22Y35" ))
\out/pstate_FSM_FFd1/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\out/pstate_FSM_FFd1/FFX/RSTAND_2166 )
);
X_LUT4 #(
.INIT ( 16'hEEC0 ),
.LOC ( "SLICE_X22Y35" ))
\out/pstate_FSM_FFd1-In (
.ADR0(\out/N8_0 ),
.ADR1(\out/pstate_FSM_FFd1_1425 ),
.ADR2(N23),
.ADR3(\out/baud1/baud_1432 ),
.O(\out/pstate_FSM_FFd1-In_2158 )
);
X_LUT4 #(
.INIT ( 16'h3131 ),
.LOC ( "SLICE_X27Y36" ))
\out/Mcount_bitcounter_xor<0>11 (
.ADR0(\out/bitcounter [1]),
.ADR1(\out/bitcounter [0]),
.ADR2(\out/N2 ),
.ADR3(VCC),
.O(\out/Mcount_bitcounter )
);
X_LUT4 #(
.INIT ( 16'hFFFE ),
.LOC ( "SLICE_X22Y35" ))
\out/pstate_FSM_FFd1-In_SW0 (
.ADR0(\out/bittimer [2]),
.ADR1(\out/bittimer [1]),
.ADR2(\out/bittimer [0]),
.ADR3(\out/bittimer [3]),
.O(N23_pack_2)
);
X_LUT4 #(
.INIT ( 16'hAAFF ),
.LOC ( "SLICE_X21Y20" ))
\in/bitcounter_not00012 (
.ADR0(\in/finish ),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\in/loaded_mux0000_0 ),
.O(\in/bitcounter_not0001 )
);
X_LUT4 #(
.INIT ( 16'h0002 ),
.LOC ( "SLICE_X29Y31" ))
\out/baud1/baud_cmp_eq0000822 (
.ADR0(\out/baud1/timer [4]),
.ADR1(\out/baud1/timer [7]),
.ADR2(\out/baud1/timer [6]),
.ADR3(\out/baud1/timer [5]),
.O(\out/baud1/baud_cmp_eq0000822_2130 )
);
X_SFF #(
.LOC ( "SLICE_X10Y3" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX_2205 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2193 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2194 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2195 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
X_LUT4 #(
.INIT ( 16'hFBFF ),
.LOC ( "SLICE_X27Y36" ))
\out/Mcount_bitcounter_xor<1>111 (
.ADR0(\out/bitcounter [2]),
.ADR1(\out/pstate_FSM_FFd2_1423 ),
.ADR2(\out/pstate_FSM_FFd1_1425 ),
.ADR3(\out/bitcounter [3]),
.O(\out/N2_pack_2 )
);
X_FF #(
.LOC ( "SLICE_X27Y36" ),
.INIT ( 1'b0 ))
\out/bitcounter_0 (
.I(\out/bitcounter<0>/DXMUX_2113 ),
.CE(\out/bitcounter<0>/CEINV_2095 ),
.CLK(\out/bitcounter<0>/CLKINV_2096 ),
.SET(GND),
.RST(\out/bitcounter<0>/FFX/RSTAND_2119 ),
.O(\out/bitcounter [0])
);
X_BUF #(
.LOC ( "SLICE_X27Y36" ))
\out/bitcounter<0>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\out/bitcounter<0>/FFX/RSTAND_2119 )
);
X_LUT4 #(
.INIT ( 16'h3500 ),
.LOC ( "SLICE_X19Y10" ))
dout_1__and00001 (
.ADR0(\in/dout_fifo [1]),
.ADR1(\in/control [1]),
.ADR2(addr_rx[1]),
.ADR3(reset_IBUF_1366),
.O(dout_1__and0000)
);
X_LUT4 #(
.INIT ( 16'hCA00 ),
.LOC ( "SLICE_X19Y10" ))
dout_1__and00011 (
.ADR0(\in/dout_fifo [1]),
.ADR1(\in/control [1]),
.ADR2(addr_rx[1]),
.ADR3(reset_IBUF_1366),
.O(dout_1__and0001)
);
X_FF #(
.LOC ( "SLICE_X2Y32" ),
.INIT ( 1'b1 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DXMUX_2299 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2278 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2279 ),
.SET(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2280 ),
.RST(GND),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
X_LUT4 #(
.INIT ( 16'hC0C0 ),
.LOC ( "SLICE_X31Y23" ))
\in/baud1/timer_mux0000<4>_SW0 (
.ADR0(VCC),
.ADR1(\in/baud1/timer [0]),
.ADR2(\in/baud1/timer [1]),
.ADR3(VCC),
.O(N31)
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X2Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1>11 (
.ADR0(VCC),
.ADR1(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.ADR2(VCC),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\out/fifo1/Result [1])
);
X_LUT4 #(
.INIT ( 16'h1000 ),
.LOC ( "SLICE_X31Y23" ))
\in/baud1/baud_cmp_eq0000810 (
.ADR0(\in/baud1/timer [2]),
.ADR1(\in/baud1/timer [0]),
.ADR2(\in/baud1/timer [1]),
.ADR3(\in/baud1/timer [3]),
.O(\in/baud1/baud_cmp_eq0000810_2380 )
);
X_FF #(
.LOC ( "SLICE_X24Y22" ),
.INIT ( 1'b0 ))
\in/baud1/baud (
.I(\in/baud1/baud/DYMUX_2401 ),
.CE(\in/baud1/baud/CEINV_2397 ),
.CLK(\in/baud1/baud/CLKINV_2398 ),
.SET(GND),
.RST(\in/baud1/baud/FFY/RSTAND_2407 ),
.O(\in/baud1/baud_1387 )
);
X_BUF #(
.LOC ( "SLICE_X24Y22" ))
\in/baud1/baud/FFY/RSTAND (
.I(reset_IBUF_1366),
.O(\in/baud1/baud/FFY/RSTAND_2407 )
);
X_SFF #(
.LOC ( "SLICE_X9Y3" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DYMUX_2250 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV_2238 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV_2239 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV_2240 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
X_LUT4 #(
.INIT ( 16'hA55D ),
.LOC ( "SLICE_X21Y18" ))
\in/Mcount_bitcounter_xor<3>1_SW0 (
.ADR0(\in/bitcounter [3]),
.ADR1(\in/pstate [2]),
.ADR2(\in/bitcounter [0]),
.ADR3(\in/bitcounter [2]),
.O(N21_pack_3)
);
X_FF #(
.LOC ( "SLICE_X2Y32" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/DYMUX_2290 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CEINV_2278 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/CLKINV_2279 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<0>/SRINV_2280 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
X_SFF #(
.LOC ( "SLICE_X9Y3" ),
.INIT ( 1'b1 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/DXMUX_2264 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CEINV_2238 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/CLKINV_2239 ),
.SET(GND),
.RST(GND),
.SSET(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<0>/SRINV_2240 ),
.SRST(GND),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
X_LUT4 #(
.INIT ( 16'h2E2E ),
.LOC ( "SLICE_X21Y18" ))
\in/Mcount_bitcounter_xor<3>1 (
.ADR0(\in/bitcounter [3]),
.ADR1(\in/bitcounter [1]),
.ADR2(N21),
.ADR3(VCC),
.O(\in/Mcount_bitcounter3 )
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X9Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1>11 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\in/fifo1/Result [1])
);
X_FF #(
.LOC ( "SLICE_X21Y18" ),
.INIT ( 1'b0 ))
\in/bitcounter_3 (
.I(\in/bitcounter<3>/DXMUX_2360 ),
.CE(\in/bitcounter<3>/CEINV_2342 ),
.CLK(\in/bitcounter<3>/CLKINV_2343 ),
.SET(GND),
.RST(\in/bitcounter<3>/FFX/RSTAND_2366 ),
.O(\in/bitcounter [3])
);
X_BUF #(
.LOC ( "SLICE_X21Y18" ))
\in/bitcounter<3>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\in/bitcounter<3>/FFX/RSTAND_2366 )
);
X_LUT4 #(
.INIT ( 16'h9009 ),
.LOC ( "SLICE_X9Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_2261 )
);
X_LUT4 #(
.INIT ( 16'h9009 ),
.LOC ( "SLICE_X8Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_2423 )
);
X_SFF #(
.LOC ( "SLICE_X6Y40" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 (
.I(\out/to_shift<1>/DXMUX_2451 ),
.CE(\out/to_shift<1>/CEINV_2440 ),
.CLK(\out/to_shift<1>/CLKINV_2441 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\out/to_shift<1>/SRINV_2442 ),
.O(\out/to_shift [1])
);
X_LUT4 #(
.INIT ( 16'h7DBE ),
.LOC ( "SLICE_X8Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168_SW0 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.O(\in/fifo1/N01 )
);
X_LUT4 #(
.INIT ( 16'hFF0C ),
.LOC ( "SLICE_X11Y1" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.ADR0(VCC),
.ADR1(\in/rd_fifo ),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1483 ),
.ADR3(\in/pstate [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
X_SFF #(
.LOC ( "SLICE_X8Y40" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 (
.I(\out/to_shift<3>/DXMUX_2520 ),
.CE(\out/to_shift<3>/CEINV_2509 ),
.CLK(\out/to_shift<3>/CLKINV_2510 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\out/to_shift<3>/SRINV_2511 ),
.O(\out/to_shift [3])
);
X_FF #(
.LOC ( "SLICE_X12Y2" ),
.INIT ( 1'b1 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i (
.I(\in/empty/DYMUX_2486 ),
.CE(VCC),
.CLK(\in/empty/CLKINV_2484 ),
.SET(GND),
.RST(GND),
.O(\in/empty )
);
X_LUT4 #(
.INIT ( 16'hFAFA ),
.LOC ( "SLICE_X11Y1" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000100_SW1 (
.ADR0(\in/pstate [0]),
.ADR1(VCC),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1483 ),
.ADR3(VCC),
.O(\in/fifo1/N3 )
);
X_LUT4 #(
.INIT ( 16'hAAFA ),
.LOC ( "SLICE_X12Y32" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[0] ),
.ADR1(VCC),
.ADR2(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1488 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
X_SFF #(
.LOC ( "SLICE_X8Y40" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 (
.I(\out/to_shift<3>/DYMUX_2513 ),
.CE(\out/to_shift<3>/CEINV_2509 ),
.CLK(\out/to_shift<3>/CLKINV_2510 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\out/to_shift<3>/SRINV_2511 ),
.O(\out/to_shift [2])
);
X_SFF #(
.LOC ( "SLICE_X6Y40" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 (
.I(\out/to_shift<1>/DYMUX_2444 ),
.CE(\out/to_shift<1>/CEINV_2440 ),
.CLK(\out/to_shift<1>/CLKINV_2441 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\out/to_shift<1>/SRINV_2442 ),
.O(\out/to_shift [0])
);
X_SFF #(
.LOC ( "SLICE_X12Y30" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 (
.I(\out/to_shift<5>/DYMUX_2537 ),
.CE(\out/to_shift<5>/CEINV_2533 ),
.CLK(\out/to_shift<5>/CLKINV_2534 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\out/to_shift<5>/SRINV_2535 ),
.O(\out/to_shift [4])
);
X_SFF #(
.LOC ( "SLICE_X12Y30" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 (
.I(\out/to_shift<5>/DXMUX_2544 ),
.CE(\out/to_shift<5>/CEINV_2533 ),
.CLK(\out/to_shift<5>/CLKINV_2534 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\out/to_shift<5>/SRINV_2535 ),
.O(\out/to_shift [5])
);
X_FF #(
.LOC ( "SLICE_X23Y35" ),
.INIT ( 1'b0 ))
\out/bittimer_0 (
.I(\out/bittimer<0>/DXMUX_2639 ),
.CE(\out/bittimer<0>/CEINV_2610 ),
.CLK(\out/bittimer<0>/CLKINV_2611 ),
.SET(GND),
.RST(\out/bittimer<0>/SRINV_2612 ),
.O(\out/bittimer [0])
);
X_SFF #(
.LOC ( "SLICE_X9Y2" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DYMUX_2682 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV_2678 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV_2679 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV_2680 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
X_FF #(
.LOC ( "SLICE_X23Y35" ),
.INIT ( 1'b0 ))
\out/bittimer_1 (
.I(\out/bittimer<0>/DYMUX_2622 ),
.CE(\out/bittimer<0>/CEINV_2610 ),
.CLK(\out/bittimer<0>/CLKINV_2611 ),
.SET(GND),
.RST(\out/bittimer<0>/SRINV_2612 ),
.O(\out/bittimer [1])
);
X_LUT4 #(
.INIT ( 16'hFFFA ),
.LOC ( "SLICE_X23Y35" ))
\out/bitcounter_not00011_SW0 (
.ADR0(\out/bittimer [1]),
.ADR1(VCC),
.ADR2(\out/bittimer [2]),
.ADR3(\out/bittimer [0]),
.O(N15)
);
X_FF #(
.LOC ( "SLICE_X5Y40" ),
.INIT ( 1'b1 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg_2 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/DXMUX_2875 ),
.CE(VCC),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/CLKINV_2865 ),
.SET(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg<2>/SRINV_2866 ),
.RST(GND),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] )
);
X_SFF #(
.LOC ( "SLICE_X9Y2" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/DXMUX_2689 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CEINV_2678 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/CLKINV_2679 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1<1>/SRINV_2680 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
X_LUT4 #(
.INIT ( 16'h7FFF ),
.LOC ( "SLICE_X17Y11" ))
\Madd_data_add0000_xor<4>111_SW4 (
.ADR0(trans[0]),
.ADR1(pstate_FSM_FFd2_1518),
.ADR2(\in/dout_fifo [6]),
.ADR3(trans[1]),
.O(N54)
);
X_LUT4 #(
.INIT ( 16'h55AA ),
.LOC ( "SLICE_X23Y35" ))
\out/Mcount_bittimer_xor<1>11 (
.ADR0(\out/bittimer [1]),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(\out/bittimer [0]),
.O(\out/Result [1])
);
X_LUT4 #(
.INIT ( 16'hCECC ),
.LOC ( "SLICE_X23Y23" ))
\in/loaded_not00011 (
.ADR0(N46),
.ADR1(\in/load_1503 ),
.ADR2(\in/baud1/baud_1387 ),
.ADR3(\in/pstate [3]),
.O(\in/loaded_not0001 )
);
X_LUT4 #(
.INIT ( 16'h00AA ),
.LOC ( "SLICE_X12Y12" ))
\Madd_data_add0000_xor<4>111_SW1 (
.ADR0(\in/dout_fifo [7]),
.ADR1(VCC),
.ADR2(VCC),
.ADR3(addr_rx[1]),
.O(N50)
);
X_LUT4 #(
.INIT ( 16'h2000 ),
.LOC ( "SLICE_X12Y12" ))
\Madd_data_add0000_xor<6>111_SW0 (
.ADR0(\in/dout_fifo [4]),
.ADR1(addr_rx[1]),
.ADR2(\in/dout_fifo [6]),
.ADR3(\in/dout_fifo [5]),
.O(N40)
);
X_SFF #(
.LOC ( "SLICE_X13Y30" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 (
.I(\out/to_shift<7>/DYMUX_2561 ),
.CE(\out/to_shift<7>/CEINV_2557 ),
.CLK(\out/to_shift<7>/CLKINV_2558 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\out/to_shift<7>/SRINV_2559 ),
.O(\out/to_shift [6])
);
X_LUT4 #(
.INIT ( 16'h0001 ),
.LOC ( "SLICE_X23Y23" ))
\in/loaded_mux0000_SW0 (
.ADR0(\in/bittimer [2]),
.ADR1(\in/bittimer [3]),
.ADR2(\in/bittimer [0]),
.ADR3(\in/bittimer [1]),
.O(N46_pack_1)
);
X_SFF #(
.LOC ( "SLICE_X13Y30" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 (
.I(\out/to_shift<7>/DXMUX_2568 ),
.CE(\out/to_shift<7>/CEINV_2557 ),
.CLK(\out/to_shift<7>/CLKINV_2558 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\out/to_shift<7>/SRINV_2559 ),
.O(\out/to_shift [7])
);
X_SFF #(
.LOC ( "SLICE_X7Y2" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_1 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DXMUX_2713 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_2702 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_2703 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_2704 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
X_SFF #(
.LOC ( "SLICE_X7Y2" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_0 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/DYMUX_2706 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CEINV_2702 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/CLKINV_2703 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1<1>/SRINV_2704 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0])
);
X_LUT4 #(
.INIT ( 16'hBFEF ),
.LOC ( "SLICE_X14Y11" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005_SW0 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1483 ),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.ADR2(\in/rd_fifo ),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O(\in/fifo1/N11 )
);
X_FF #(
.LOC ( "SLICE_X18Y11" ),
.INIT ( 1'b0 ))
dout_1 (
.I(\dout<1>/DYMUX_5539 ),
.CE(VCC),
.CLK(\dout<1>/CLKINV_5528 ),
.SET(\dout<1>/FFY/SET ),
.RST(\dout<1>/FFY/RSTAND_5546 ),
.O(dout[1])
);
X_BUF #(
.LOC ( "SLICE_X18Y11" ))
\dout<1>/FFY/SETOR (
.I(dout_1__and0001),
.O(\dout<1>/FFY/SET )
);
X_BUF #(
.LOC ( "SLICE_X18Y11" ))
\dout<1>/FFY/RSTAND (
.I(dout_1__and0000),
.O(\dout<1>/FFY/RSTAND_5546 )
);
X_LUT4 #(
.INIT ( 16'hF3C0 ),
.LOC ( "SLICE_X18Y11" ))
\in/dout<1>1 (
.ADR0(VCC),
.ADR1(addr_rx[1]),
.ADR2(\in/control [1]),
.ADR3(\in/dout_fifo [1]),
.O(Madd_data_add0000_lut[1])
);
X_FF #(
.MSGON ( "TRUE" ),
.LOC ( "SLICE_X1Y41" ),
.XON ( "FALSE" ),
.INIT ( 1'b1 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/DYMUX_5566 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CEINV_5562 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/CLKINV_5563 ),
.SET(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/FFY/SET ),
.RST(GND),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_1378 )
);
X_BUF #(
.LOC ( "SLICE_X1Y41" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/FFY/SETOR (
.I(reset_IBUF_1366),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg/FFY/SET )
);
X_LUT4 #(
.INIT ( 16'h33CC ),
.LOC ( "SLICE_X23Y27" ))
\in/Mcount_bittimer_xor<1>11 (
.ADR0(VCC),
.ADR1(\in/bittimer [1]),
.ADR2(VCC),
.ADR3(\in/bittimer [0]),
.O(\in/Result [1])
);
X_LUT4 #(
.INIT ( 16'h8080 ),
.LOC ( "SLICE_X14Y11" ))
rx_sel1 (
.ADR0(trans[1]),
.ADR1(trans[0]),
.ADR2(pstate_FSM_FFd2_1518),
.ADR3(VCC),
.O(\in/rd_fifo_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h77FF ),
.LOC ( "SLICE_X18Y11" ))
\addr_rx<1>1 (
.ADR0(trans[0]),
.ADR1(pstate_FSM_FFd2_1518),
.ADR2(VCC),
.ADR3(trans[1]),
.O(\addr_rx<1>_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h2288 ),
.LOC ( "SLICE_X29Y22" ))
\in/baud1/timer_mux0000<1>1 (
.ADR0(\in/baud1/N01 ),
.ADR1(\in/baud1/Madd_timer_addsub0000_cy<5>_0 ),
.ADR2(VCC),
.ADR3(\in/baud1/timer [6]),
.O(\in/baud1/timer_mux0000 [1])
);
X_FF #(
.LOC ( "SLICE_X29Y22" ),
.INIT ( 1'b0 ))
\in/baud1/timer_7 (
.I(\in/baud1/timer<7>/DXMUX_5485 ),
.CE(VCC),
.CLK(\in/baud1/timer<7>/CLKINV_5461 ),
.SET(GND),
.RST(\in/baud1/timer<7>/SRINV_5462 ),
.O(\in/baud1/timer [7])
);
X_FF #(
.LOC ( "SLICE_X23Y27" ),
.INIT ( 1'b0 ))
\in/bittimer_1 (
.I(\in/bittimer<0>/DYMUX_5593 ),
.CE(\in/bittimer<0>/CEINV_5581 ),
.CLK(\in/bittimer<0>/CLKINV_5582 ),
.SET(GND),
.RST(\in/bittimer<0>/SRINV_5583 ),
.O(\in/bittimer [1])
);
X_LUT4 #(
.INIT ( 16'h60A0 ),
.LOC ( "SLICE_X29Y22" ))
\in/baud1/timer_mux0000<0>1 (
.ADR0(\in/baud1/timer [7]),
.ADR1(\in/baud1/Madd_timer_addsub0000_cy<5>_0 ),
.ADR2(\in/baud1/N01 ),
.ADR3(\in/baud1/timer [6]),
.O(\in/baud1/timer_mux0000 [0])
);
X_FF #(
.LOC ( "SLICE_X29Y22" ),
.INIT ( 1'b0 ))
\in/baud1/timer_6 (
.I(\in/baud1/timer<7>/DYMUX_5471 ),
.CE(VCC),
.CLK(\in/baud1/timer<7>/CLKINV_5461 ),
.SET(GND),
.RST(\in/baud1/timer<7>/SRINV_5462 ),
.O(\in/baud1/timer [6])
);
X_LUT4 #(
.INIT ( 16'h00F0 ),
.LOC ( "SLICE_X23Y18" ))
\in/Mcount_bitcounter_xor<1>1_SW0 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(\in/pstate [2]),
.ADR3(\in/bitcounter [2]),
.O(N11_pack_2)
);
X_FF #(
.LOC ( "SLICE_X23Y18" ),
.INIT ( 1'b0 ))
\in/bitcounter_1 (
.I(\in/bitcounter<1>/DXMUX_5640 ),
.CE(\in/bitcounter<1>/CEINV_5621 ),
.CLK(\in/bitcounter<1>/CLKINV_5622 ),
.SET(GND),
.RST(\in/bitcounter<1>/FFX/RSTAND_5646 ),
.O(\in/bitcounter [1])
);
X_BUF #(
.LOC ( "SLICE_X23Y18" ))
\in/bitcounter<1>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\in/bitcounter<1>/FFX/RSTAND_5646 )
);
X_LUT4 #(
.INIT ( 16'h334C ),
.LOC ( "SLICE_X23Y18" ))
\in/Mcount_bitcounter_xor<1>1 (
.ADR0(\in/bitcounter [3]),
.ADR1(\in/bitcounter [1]),
.ADR2(N11),
.ADR3(\in/bitcounter [0]),
.O(\in/Mcount_bitcounter1 )
);
X_FF #(
.LOC ( "SLICE_X23Y27" ),
.INIT ( 1'b0 ))
\in/bittimer_0 (
.I(\in/bittimer<0>/DXMUX_5602 ),
.CE(\in/bittimer<0>/CEINV_5581 ),
.CLK(\in/bittimer<0>/CLKINV_5582 ),
.SET(GND),
.RST(\in/bittimer<0>/SRINV_5583 ),
.O(\in/bittimer [0])
);
X_LUT4 #(
.INIT ( 16'hFAFA ),
.LOC ( "SLICE_X21Y35" ))
\out/bittime1 (
.ADR0(\out/N8_0 ),
.ADR1(VCC),
.ADR2(\out/pstate_FSM_FFd1_1425 ),
.ADR3(VCC),
.O(\out/bittime )
);
X_FF #(
.LOC ( "SLICE_X16Y11" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.I(\in/full/DYMUX_3248 ),
.CE(VCC),
.CLK(\in/full/CLKINV_3246 ),
.SET(GND),
.RST(GND),
.O(\in/full )
);
X_LUT4 #(
.INIT ( 16'h3030 ),
.LOC ( "SLICE_X10Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/ram_rd_en_i1 (
.ADR0(VCC),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1483 ),
.ADR2(\in/rd_fifo ),
.ADR3(VCC),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
X_BUF #(
.LOC ( "PAD2" ))
\rx/IFF/IMUX (
.I(\rx/INBUF ),
.O(rx_IBUF_1384)
);
X_BUF #(
.LOC ( "PAD83" ))
\fsm/IFF/IMUX (
.I(\fsm/INBUF ),
.O(fsm_IBUF_1559)
);
X_FF #(
.LOC ( "SLICE_X13Y34" ),
.INIT ( 1'b1 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i (
.I(\out/empty/DYMUX_3259 ),
.CE(VCC),
.CLK(\out/empty/CLKINV_3256 ),
.SET(\out/empty/FFY/SET ),
.RST(GND),
.O(\out/empty )
);
X_BUF #(
.LOC ( "SLICE_X13Y34" ))
\out/empty/FFY/SETOR (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\out/empty/FFY/SET )
);
X_LUT4 #(
.INIT ( 16'h6AAA ),
.LOC ( "SLICE_X19Y13" ))
\Madd_data_add0000_xor<3>11_F (
.ADR0(\in/dout_fifo [3]),
.ADR1(\in/dout_fifo [0]),
.ADR2(\in/dout_fifo [2]),
.ADR3(\in/dout_fifo [1]),
.O(N60)
);
X_FF #(
.LOC ( "SLICE_X19Y13" ),
.INIT ( 1'b1 ))
data_3 (
.I(\data<3>/DXMUX_3749 ),
.CE(\data<3>/CEINV_3730 ),
.CLK(\data<3>/CLKINV_3731 ),
.SET(\data<3>/FFX/SET ),
.RST(GND),
.O(data[3])
);
X_BUF #(
.LOC ( "SLICE_X19Y13" ))
\data<3>/FFX/SETOR (
.I(reset_IBUF_1366),
.O(\data<3>/FFX/SET )
);
X_LUT4 #(
.INIT ( 16'h95C0 ),
.LOC ( "SLICE_X19Y17" ))
\Madd_data_add0000_xor<4>111_SW2_G (
.ADR0(addr_rx[1]),
.ADR1(\in/dout_fifo [3]),
.ADR2(\in/dout_fifo [1]),
.ADR3(\in/dout_fifo [7]),
.O(N57)
);
X_LUT4 #(
.INIT ( 16'h7FFF ),
.LOC ( "SLICE_X13Y11" ))
\Madd_data_add0000_xor<4>111_SW3_F (
.ADR0(\in/dout_fifo [6]),
.ADR1(pstate_FSM_FFd2_1518),
.ADR2(trans[0]),
.ADR3(trans[1]),
.O(N58)
);
X_LUT4 #(
.INIT ( 16'hF9F5 ),
.LOC ( "SLICE_X13Y11" ))
\Madd_data_add0000_xor<4>111_SW3_G (
.ADR0(\in/dout_fifo [6]),
.ADR1(\in/dout_fifo [1]),
.ADR2(addr_rx[1]),
.ADR3(\in/dout_fifo [3]),
.O(N59)
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X19Y17" ))
\Madd_data_add0000_xor<4>111_SW2_F (
.ADR0(trans[0]),
.ADR1(pstate_FSM_FFd2_1518),
.ADR2(trans[1]),
.ADR3(\in/dout_fifo [7]),
.O(N56)
);
X_LUT4 #(
.INIT ( 16'h8800 ),
.LOC ( "SLICE_X19Y13" ))
\Madd_data_add0000_xor<3>11_G (
.ADR0(\in/control [0]),
.ADR1(\in/control [2]),
.ADR2(VCC),
.ADR3(\in/control [1]),
.O(N61)
);
X_BUF #(
.LOC ( "IPAD60" ))
\reset/IFF/IMUX (
.I(\reset/INBUF ),
.O(reset_IBUF_1366)
);
X_LUT4 #(
.INIT ( 16'hFFDE ),
.LOC ( "SLICE_X11Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.ADR1(\in/fifo1/N01_0 ),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.ADR3(\in/fifo1/N7_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hA000 ),
.LOC ( "SLICE_X13Y10" ))
\Madd_data_add0000_xor<4>12_SW0 (
.ADR0(\in/dout_fifo [1]),
.ADR1(VCC),
.ADR2(\in/dout_fifo [2]),
.ADR3(\in/dout_fifo [3]),
.O(\Madd_data_add0000_xor<4>12_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h7077 ),
.LOC ( "SLICE_X28Y32" ))
\out/baud1/timer_mux0000<0>11 (
.ADR0(\out/baud1/baud_cmp_eq0000822_0 ),
.ADR1(\out/baud1/baud_cmp_eq0000810_1573 ),
.ADR2(\out/pstate_FSM_FFd2_1423 ),
.ADR3(\out/empty ),
.O(\out/baud1/N01_pack_2 )
);
X_LUT4 #(
.INIT ( 16'h6350 ),
.LOC ( "SLICE_X13Y10" ))
\Madd_data_add0000_xor<4>12 (
.ADR0(N38),
.ADR1(addr_rx[1]),
.ADR2(\Madd_data_add0000_xor<4>12_SW0/O ),
.ADR3(\in/dout_fifo [4]),
.O(\data_add0000[4] )
);
X_FF #(
.LOC ( "SLICE_X13Y12" ),
.INIT ( 1'b1 ))
data_5 (
.I(\data<5>/DXMUX_3963 ),
.CE(\data<5>/CEINV_3946 ),
.CLK(\data<5>/CLKINV_3947 ),
.SET(\data<5>/FFX/SET ),
.RST(GND),
.O(data[5])
);
X_BUF #(
.LOC ( "SLICE_X13Y12" ))
\data<5>/FFX/SETOR (
.I(reset_IBUF_1366),
.O(\data<5>/FFX/SET )
);
X_LUT4 #(
.INIT ( 16'hE0F0 ),
.LOC ( "SLICE_X24Y37" ))
\out/pstate_FSM_FFd1-In3 (
.ADR0(\out/bitcounter [0]),
.ADR1(\out/pstate_FSM_FFd1-In3_SW0/O ),
.ADR2(\out/pstate_FSM_FFd2_1423 ),
.ADR3(\out/bitcounter [3]),
.O(\out/N8 )
);
X_FF #(
.LOC ( "SLICE_X28Y32" ),
.INIT ( 1'b0 ))
\out/baud1/timer_3 (
.I(\out/baud1/timer<3>/DXMUX_3865 ),
.CE(VCC),
.CLK(\out/baud1/timer<3>/CLKINV_3849 ),
.SET(GND),
.RST(\out/baud1/timer<3>/FFX/RSTAND_3870 ),
.O(\out/baud1/timer [3])
);
X_BUF #(
.LOC ( "SLICE_X28Y32" ))
\out/baud1/timer<3>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\out/baud1/timer<3>/FFX/RSTAND_3870 )
);
X_LUT4 #(
.INIT ( 16'hFCEE ),
.LOC ( "SLICE_X11Y3" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000102 (
.ADR0(\in/fifo1/N2_0 ),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073_0 ),
.ADR2(\in/fifo1/N3_0 ),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00003168/O ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 )
);
X_FF #(
.LOC ( "SLICE_X11Y3" ),
.INIT ( 1'b1 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_3833 ),
.CE(VCC),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_3818 ),
.SET(GND),
.RST(GND),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1483 )
);
X_LUT4 #(
.INIT ( 16'h6C00 ),
.LOC ( "SLICE_X28Y32" ))
\out/baud1/timer_mux0000<4> (
.ADR0(\out/baud1/timer [2]),
.ADR1(\out/baud1/timer [3]),
.ADR2(N29_0),
.ADR3(\out/baud1/N01 ),
.O(\out/baud1/timer_mux0000 [4])
);
X_LUT4 #(
.INIT ( 16'h7FFF ),
.LOC ( "SLICE_X13Y12" ))
\Madd_data_add0000_xor<5>11_SW0 (
.ADR0(\in/dout_fifo [1]),
.ADR1(\in/dout_fifo [3]),
.ADR2(\in/dout_fifo [2]),
.ADR3(\in/dout_fifo [4]),
.O(\Madd_data_add0000_xor<5>11_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h5401 ),
.LOC ( "SLICE_X13Y12" ))
\Madd_data_add0000_xor<5>11 (
.ADR0(addr_rx[1]),
.ADR1(N38),
.ADR2(\Madd_data_add0000_xor<5>11_SW0/O ),
.ADR3(\in/dout_fifo [5]),
.O(\data_add0000[5] )
);
X_LUT4 #(
.INIT ( 16'hDDDD ),
.LOC ( "SLICE_X24Y37" ))
\out/pstate_FSM_FFd1-In3_SW0 (
.ADR0(\out/bitcounter [1]),
.ADR1(\out/bitcounter [2]),
.ADR2(VCC),
.ADR3(VCC),
.O(\out/pstate_FSM_FFd1-In3_SW0/O_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X13Y10" ),
.INIT ( 1'b1 ))
data_4 (
.I(\data<4>/DXMUX_3926 ),
.CE(\data<4>/CEINV_3908 ),
.CLK(\data<4>/CLKINV_3909 ),
.SET(\data<4>/FFX/SET ),
.RST(GND),
.O(data[4])
);
X_BUF #(
.LOC ( "SLICE_X13Y10" ))
\data<4>/FFX/SETOR (
.I(reset_IBUF_1366),
.O(\data<4>/FFX/SET )
);
X_LUT4 #(
.INIT ( 16'hCEC4 ),
.LOC ( "SLICE_X12Y13" ))
\Madd_data_add0000_xor<7>11 (
.ADR0(N40_0),
.ADR1(N50_0),
.ADR2(N38),
.ADR3(N51),
.O(\data_add0000[7] )
);
X_FF #(
.LOC ( "SLICE_X12Y11" ),
.INIT ( 1'b1 ))
data_6 (
.I(\data<6>/DXMUX_4000 ),
.CE(\data<6>/CEINV_3981 ),
.CLK(\data<6>/CLKINV_3982 ),
.SET(\data<6>/FFX/SET ),
.RST(GND),
.O(data[6])
);
X_BUF #(
.LOC ( "SLICE_X12Y11" ))
\data<6>/FFX/SETOR (
.I(reset_IBUF_1366),
.O(\data<6>/FFX/SET )
);
X_LUT4 #(
.INIT ( 16'h0E1F ),
.LOC ( "SLICE_X12Y11" ))
\Madd_data_add0000_xor<6>12 (
.ADR0(\Madd_data_add0000_xor<6>12_SW0/O ),
.ADR1(N38),
.ADR2(N54_0),
.ADR3(N53),
.O(\data_add0000[6] )
);
X_LUT4 #(
.INIT ( 16'hAAA8 ),
.LOC ( "SLICE_X13Y8" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1442 ),
.ADR1(\in/fifo1/N01_0 ),
.ADR2(\in/fifo1/N7_0 ),
.ADR3(\in/fifo1/N11_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'hA500 ),
.LOC ( "SLICE_X11Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000029 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR1(VCC),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.ADR3(\in/rd_fifo ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000029/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h0020 ),
.LOC ( "SLICE_X29Y32" ))
\out/baud1/baud_cmp_eq0000810 (
.ADR0(\out/baud1/timer [3]),
.ADR1(\out/baud1/timer [0]),
.ADR2(\out/baud1/timer [1]),
.ADR3(\out/baud1/timer [2]),
.O(\out/baud1/baud_cmp_eq0000810_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hC000 ),
.LOC ( "SLICE_X11Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073 (
.ADR0(VCC),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000056_0 ),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000029/O ),
.ADR3(\in/fifo1/N9_0 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux000073_4089 )
);
X_LUT4 #(
.INIT ( 16'h0010 ),
.LOC ( "SLICE_X28Y23" ))
\in/baud1/baud_cmp_eq0000822 (
.ADR0(\in/baud1/timer [6]),
.ADR1(\in/baud1/timer [5]),
.ADR2(\in/baud1/timer [4]),
.ADR3(\in/baud1/timer [7]),
.O(\in/baud1/baud_cmp_eq0000822/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hF000 ),
.LOC ( "SLICE_X28Y23" ))
\in/baud1/baud_cmp_eq0000823 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(\in/baud1/baud_cmp_eq0000822/O ),
.ADR3(\in/baud1/baud_cmp_eq0000810_0 ),
.O(\in/baud1/baud_cmp_eq0000 )
);
X_LUT4 #(
.INIT ( 16'h5504 ),
.LOC ( "SLICE_X13Y8" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000105 (
.ADR0(\in/pstate [0]),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000062_0 ),
.ADR2(\in/fifo1/N5_0 ),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00005/O ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
X_LUT4 #(
.INIT ( 16'h5F5F ),
.LOC ( "SLICE_X12Y11" ))
\Madd_data_add0000_xor<6>12_SW0 (
.ADR0(\in/dout_fifo [4]),
.ADR1(VCC),
.ADR2(\in/dout_fifo [5]),
.ADR3(VCC),
.O(\Madd_data_add0000_xor<6>12_SW0/O_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X12Y13" ),
.INIT ( 1'b1 ))
data_7 (
.I(\data<7>/DXMUX_4061 ),
.CE(\data<7>/CEINV_4044 ),
.CLK(\data<7>/CLKINV_4045 ),
.SET(\data<7>/FFX/SET ),
.RST(GND),
.O(data[7])
);
X_BUF #(
.LOC ( "SLICE_X12Y13" ))
\data<7>/FFX/SETOR (
.I(reset_IBUF_1366),
.O(\data<7>/FFX/SET )
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X31Y22" ))
\in/baud1/Madd_timer_addsub0000_cy<3>11 (
.ADR0(\in/baud1/timer [2]),
.ADR1(\in/baud1/timer [0]),
.ADR2(\in/baud1/timer [1]),
.ADR3(\in/baud1/timer [3]),
.O(\in/baud1/Madd_timer_addsub0000_cy<3>_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hF000 ),
.LOC ( "SLICE_X29Y32" ))
\out/baud1/baud_cmp_eq0000823 (
.ADR0(VCC),
.ADR1(VCC),
.ADR2(\out/baud1/baud_cmp_eq0000810_1573 ),
.ADR3(\out/baud1/baud_cmp_eq0000822_0 ),
.O(\out/baud1/baud_cmp_eq0000 )
);
X_LUT4 #(
.INIT ( 16'h7FFF ),
.LOC ( "SLICE_X12Y13" ))
\Madd_data_add0000_xor<4>111_SW0 (
.ADR0(pstate_FSM_FFd2_1518),
.ADR1(\in/dout_fifo [0]),
.ADR2(trans[0]),
.ADR3(trans[1]),
.O(N38_pack_1)
);
X_LUT4 #(
.INIT ( 16'hC431 ),
.LOC ( "SLICE_X12Y9" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000021 (
.ADR0(\in/rd_fifo ),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1483 ),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000021/O_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X13Y8" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/DXMUX_4143 ),
.CE(VCC),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i/CLKINV_4128 ),
.SET(GND),
.RST(GND),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_1442 )
);
X_LUT4 #(
.INIT ( 16'h8000 ),
.LOC ( "SLICE_X29Y30" ))
\out/baud1/Madd_timer_addsub0000_cy<3>11 (
.ADR0(\out/baud1/timer [2]),
.ADR1(\out/baud1/timer [1]),
.ADR2(\out/baud1/timer [3]),
.ADR3(\out/baud1/timer [0]),
.O(\out/baud1/Madd_timer_addsub0000_cy<3>_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hAEAA ),
.LOC ( "SLICE_X25Y37" ))
\out/bitcounter_not0001 (
.ADR0(\out/N7 ),
.ADR1(\out/pstate_FSM_FFd2_1423 ),
.ADR2(\out/pstate_FSM_FFd1_1425 ),
.ADR3(\out/bitcounter_not0001_SW0/O ),
.O(\out/bitcounter_not0001_4264 )
);
X_LUT4 #(
.INIT ( 16'hA000 ),
.LOC ( "SLICE_X29Y30" ))
\out/baud1/Madd_timer_addsub0000_cy<5>11 (
.ADR0(\out/baud1/timer [4]),
.ADR1(VCC),
.ADR2(\out/baud1/Madd_timer_addsub0000_cy[3] ),
.ADR3(\out/baud1/timer [5]),
.O(\out/baud1/Madd_timer_addsub0000_cy[5] )
);
X_LUT4 #(
.INIT ( 16'h6FFF ),
.LOC ( "SLICE_X12Y9" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000077_SW0 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux000021/O ),
.ADR3(\in/pstate [4]),
.O(\in/fifo1/N5 )
);
X_FF #(
.LOC ( "SLICE_X23Y19" ),
.INIT ( 1'b0 ))
\in/pstate_3 (
.I(\in/pstate<3>/DXMUX_4295 ),
.CE(VCC),
.CLK(\in/pstate<3>/CLKINV_4278 ),
.SET(GND),
.RST(\in/pstate<3>/FFX/RSTAND_4300 ),
.O(\in/pstate [3])
);
X_BUF #(
.LOC ( "SLICE_X23Y19" ))
\in/pstate<3>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\in/pstate<3>/FFX/RSTAND_4300 )
);
X_LUT4 #(
.INIT ( 16'hC000 ),
.LOC ( "SLICE_X31Y22" ))
\in/baud1/Madd_timer_addsub0000_cy<5>11 (
.ADR0(VCC),
.ADR1(\in/baud1/timer [5]),
.ADR2(\in/baud1/Madd_timer_addsub0000_cy[3] ),
.ADR3(\in/baud1/timer [4]),
.O(\in/baud1/Madd_timer_addsub0000_cy[5] )
);
X_LUT4 #(
.INIT ( 16'h0010 ),
.LOC ( "SLICE_X23Y34" ))
\out/bitcounter_not00011 (
.ADR0(\out/bittimer [3]),
.ADR1(N15_0),
.ADR2(\out/pstate_FSM_FFd1_1425 ),
.ADR3(\out/baud1/baud_1432 ),
.O(\out/N7_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h2D78 ),
.LOC ( "SLICE_X25Y6" ))
\Madd_data_add0000_xor<1>11 (
.ADR0(addr_rx[1]),
.ADR1(\in/control [1]),
.ADR2(Madd_data_add0000_cy[0]),
.ADR3(\in/dout_fifo [1]),
.O(\data_add0000[1] )
);
X_LUT4 #(
.INIT ( 16'hAFA0 ),
.LOC ( "SLICE_X25Y6" ))
\in/dout<0>1 (
.ADR0(\in/control [0]),
.ADR1(VCC),
.ADR2(addr_rx[1]),
.ADR3(\in/dout_fifo [0]),
.O(\Madd_data_add0000_cy<0>_pack_2 )
);
X_LUT4 #(
.INIT ( 16'hF1F1 ),
.LOC ( "SLICE_X23Y34" ))
\out/shift_out_not00012 (
.ADR0(\out/empty ),
.ADR1(\out/pstate_FSM_FFd2_1423 ),
.ADR2(\out/N7 ),
.ADR3(VCC),
.O(\out/shift_out_not0001 )
);
X_LUT4 #(
.INIT ( 16'h0200 ),
.LOC ( "SLICE_X25Y37" ))
\out/bitcounter_not0001_SW0 (
.ADR0(\out/bitcounter [3]),
.ADR1(\out/bitcounter [0]),
.ADR2(\out/bitcounter [2]),
.ADR3(\out/bitcounter [1]),
.O(\out/bitcounter_not0001_SW0/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h5544 ),
.LOC ( "SLICE_X23Y19" ))
\in/pstate_mux0000<2>31 (
.ADR0(\in/control [2]),
.ADR1(\in/pstate_mux0000<2>10_0 ),
.ADR2(VCC),
.ADR3(\in/pstate_mux0000<2>18/O ),
.O(\in/pstate_mux0000 [2])
);
X_LUT4 #(
.INIT ( 16'hC800 ),
.LOC ( "SLICE_X23Y19" ))
\in/pstate_mux0000<2>18 (
.ADR0(\in/bitcounter [0]),
.ADR1(\in/baud1/baud_1387 ),
.ADR2(\in/N13 ),
.ADR3(\in/pstate [2]),
.O(\in/pstate_mux0000<2>18/O_pack_1 )
);
X_LUT4 #(
.INIT ( 16'hAFFF ),
.LOC ( "SLICE_X20Y18" ))
\in/Mcount_bitcounter_xor<0>1111 (
.ADR0(\in/bitcounter [2]),
.ADR1(VCC),
.ADR2(\in/bitcounter [1]),
.ADR3(\in/bitcounter [3]),
.O(\in/N13_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X26Y22" ),
.INIT ( 1'b0 ))
\in/baud1/timer_0 (
.I(\in/baud1/timer<0>/DXMUX_4401 ),
.CE(VCC),
.CLK(\in/baud1/timer<0>/CLKINV_4383 ),
.SET(GND),
.RST(\in/baud1/timer<0>/FFX/RSTAND_4406 ),
.O(\in/baud1/timer [0])
);
X_BUF #(
.LOC ( "SLICE_X26Y22" ))
\in/baud1/timer<0>/FFX/RSTAND (
.I(reset_IBUF_1366),
.O(\in/baud1/timer<0>/FFX/RSTAND_4406 )
);
X_LUT4 #(
.INIT ( 16'h0400 ),
.LOC ( "SLICE_X3Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR1(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en_0 ),
.ADR2(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000062_0 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O_pack_2 )
);
X_LUT4 #(
.INIT ( 16'h0C08 ),
.LOC ( "SLICE_X20Y18" ))
\in/pstate_mux0000<3>15 (
.ADR0(\in/bitcounter [0]),
.ADR1(\in/pstate [2]),
.ADR2(\in/baud1/baud_1387 ),
.ADR3(\in/N13 ),
.O(\in/pstate_mux0000<3>15_4429 )
);
X_LUT4 #(
.INIT ( 16'h0007 ),
.LOC ( "SLICE_X26Y22" ))
\in/baud1/timer_mux0000<0>11 (
.ADR0(rx_IBUF_1384),
.ADR1(\in/pstate [1]),
.ADR2(\in/baud1/baud_cmp_eq0000_0 ),
.ADR3(\in/pstate [0]),
.O(\in/baud1/N01_pack_2 )
);
X_LUT4 #(
.INIT ( 16'hAAF0 ),
.LOC ( "SLICE_X24Y6" ))
\in/dout<2>1 (
.ADR0(\in/control [2]),
.ADR1(VCC),
.ADR2(\in/dout_fifo [2]),
.ADR3(addr_rx[1]),
.O(\in/dout<2>1/O_pack_1 )
);
X_FF #(
.LOC ( "SLICE_X3Y33" ),
.INIT ( 1'b1 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/DXMUX_4367 ),
.CE(VCC),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/CLKINV_4349 ),
.SET(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FFX/SET ),
.RST(GND),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1488 )
);
X_BUF #(
.LOC ( "SLICE_X3Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FFX/SETOR (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i/FFX/SET )
);
X_LUT4 #(
.INIT ( 16'h3300 ),
.LOC ( "SLICE_X26Y22" ))
\in/baud1/timer_mux0000<7>1 (
.ADR0(VCC),
.ADR1(\in/baud1/timer [0]),
.ADR2(VCC),
.ADR3(\in/baud1/N01 ),
.O(\in/baud1/timer_mux0000 [7])
);
X_FF #(
.LOC ( "SLICE_X25Y6" ),
.INIT ( 1'b1 ))
data_1 (
.I(\data<1>/DXMUX_4332 ),
.CE(\data<1>/CEINV_4314 ),
.CLK(\data<1>/CLKINV_4315 ),
.SET(\data<1>/FFX/SET ),
.RST(GND),
.O(data[1])
);
X_BUF #(
.LOC ( "SLICE_X25Y6" ))
\data<1>/FFX/SETOR (
.I(reset_IBUF_1366),
.O(\data<1>/FFX/SET )
);
X_FF #(
.LOC ( "SLICE_X24Y6" ),
.INIT ( 1'b1 ))
data_2 (
.I(\data<2>/DXMUX_4462 ),
.CE(\data<2>/CEINV_4443 ),
.CLK(\data<2>/CLKINV_4444 ),
.SET(\data<2>/FFX/SET ),
.RST(GND),
.O(data[2])
);
X_BUF #(
.LOC ( "SLICE_X24Y6" ))
\data<2>/FFX/SETOR (
.I(reset_IBUF_1366),
.O(\data<2>/FFX/SET )
);
X_LUT4 #(
.INIT ( 16'h66AA ),
.LOC ( "SLICE_X23Y29" ))
\in/Mcount_bittimer_xor<2>11 (
.ADR0(\in/bittimer [2]),
.ADR1(\in/bittimer [1]),
.ADR2(VCC),
.ADR3(\in/bittimer [0]),
.O(\in/Result [2])
);
X_FF #(
.LOC ( "SLICE_X23Y29" ),
.INIT ( 1'b0 ))
\in/bittimer_2 (
.I(\in/bittimer<3>/DYMUX_4492 ),
.CE(\in/bittimer<3>/CEINV_4481 ),
.CLK(\in/bittimer<3>/CLKINV_4482 ),
.SET(GND),
.RST(\in/bittimer<3>/SRINV_4483 ),
.O(\in/bittimer [2])
);
X_LUT4 #(
.INIT ( 16'h3FC0 ),
.LOC ( "SLICE_X24Y6" ))
\Madd_data_add0000_xor<2>11 (
.ADR0(VCC),
.ADR1(Madd_data_add0000_cy[0]),
.ADR2(\Madd_data_add0000_lut<1>_0 ),
.ADR3(\in/dout<2>1/O ),
.O(\data_add0000[2] )
);
X_LUT4 #(
.INIT ( 16'hFFCC ),
.LOC ( "SLICE_X3Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000092 (
.ADR0(VCC),
.ADR1(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1488 ),
.ADR2(VCC),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or000079/O ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_or0000 )
);
X_LUT4 #(
.INIT ( 16'h30C0 ),
.LOC ( "SLICE_X28Y31" ))
\out/baud1/timer_mux0000<3>1 (
.ADR0(VCC),
.ADR1(\out/baud1/Madd_timer_addsub0000_cy[3] ),
.ADR2(\out/baud1/N01 ),
.ADR3(\out/baud1/timer [4]),
.O(\out/baud1/timer_mux0000 [3])
);
X_FF #(
.LOC ( "SLICE_X27Y37" ),
.INIT ( 1'b0 ))
\out/bitcounter_1 (
.I(\out/bitcounter<1>/DYMUX_4575 ),
.CE(\out/bitcounter<1>/CEINV_4564 ),
.CLK(\out/bitcounter<1>/CLKINV_4565 ),
.SET(GND),
.RST(\out/bitcounter<1>/FFY/RSTAND_4581 ),
.O(\out/bitcounter [1])
);
X_BUF #(
.LOC ( "SLICE_X27Y37" ))
\out/bitcounter<1>/FFY/RSTAND (
.I(reset_IBUF_1366),
.O(\out/bitcounter<1>/FFY/RSTAND_4581 )
);
X_LUT4 #(
.INIT ( 16'h60A0 ),
.LOC ( "SLICE_X28Y31" ))
\out/baud1/timer_mux0000<2>1 (
.ADR0(\out/baud1/timer [5]),
.ADR1(\out/baud1/Madd_timer_addsub0000_cy[3] ),
.ADR2(\out/baud1/N01 ),
.ADR3(\out/baud1/timer [4]),
.O(\out/baud1/timer_mux0000 [2])
);
X_FF #(
.LOC ( "SLICE_X23Y29" ),
.INIT ( 1'b0 ))
\in/bittimer_3 (
.I(\in/bittimer<3>/DXMUX_4507 ),
.CE(\in/bittimer<3>/CEINV_4481 ),
.CLK(\in/bittimer<3>/CLKINV_4482 ),
.SET(GND),
.RST(\in/bittimer<3>/SRINV_4483 ),
.O(\in/bittimer [3])
);
X_LUT4 #(
.INIT ( 16'h78F0 ),
.LOC ( "SLICE_X23Y29" ))
\in/Mcount_bittimer_xor<3>11 (
.ADR0(\in/bittimer [2]),
.ADR1(\in/bittimer [1]),
.ADR2(\in/bittimer [3]),
.ADR3(\in/bittimer [0]),
.O(\in/Result [3])
);
X_LUT4 #(
.INIT ( 16'h0301 ),
.LOC ( "SLICE_X29Y33" ))
\out/baud1/timer_mux0000<7>1 (
.ADR0(\out/empty ),
.ADR1(\out/baud1/baud_cmp_eq0000_0 ),
.ADR2(\out/baud1/timer [0]),
.ADR3(\out/pstate_FSM_FFd2_1423 ),
.O(\out/baud1/timer_mux0000 [7])
);
X_LUT4 #(
.INIT ( 16'h2828 ),
.LOC ( "SLICE_X29Y33" ))
\out/baud1/timer_mux0000<6>1 (
.ADR0(\out/baud1/N01 ),
.ADR1(\out/baud1/timer [0]),
.ADR2(\out/baud1/timer [1]),
.ADR3(VCC),
.O(\out/baud1/timer_mux0000 [6])
);
X_LUT4 #(
.INIT ( 16'h6464 ),
.LOC ( "SLICE_X27Y37" ))
\out/Mcount_bitcounter_xor<1>12 (
.ADR0(\out/bitcounter [1]),
.ADR1(\out/bitcounter [0]),
.ADR2(\out/N2 ),
.ADR3(VCC),
.O(\out/Mcount_bitcounter1 )
);
X_FF #(
.LOC ( "SLICE_X28Y31" ),
.INIT ( 1'b0 ))
\out/baud1/timer_5 (
.I(\out/baud1/timer<5>/DXMUX_4618 ),
.CE(VCC),
.CLK(\out/baud1/timer<5>/CLKINV_4594 ),
.SET(GND),
.RST(\out/baud1/timer<5>/SRINV_4595 ),
.O(\out/baud1/timer [5])
);
X_FF #(
.LOC ( "SLICE_X29Y33" ),
.INIT ( 1'b0 ))
\out/baud1/timer_0 (
.I(\out/baud1/timer<1>/DYMUX_4535 ),
.CE(VCC),
.CLK(\out/baud1/timer<1>/CLKINV_4526 ),
.SET(GND),
.RST(\out/baud1/timer<1>/SRINV_4527 ),
.O(\out/baud1/timer [0])
);
X_FF #(
.LOC ( "SLICE_X28Y31" ),
.INIT ( 1'b0 ))
\out/baud1/timer_4 (
.I(\out/baud1/timer<5>/DYMUX_4604 ),
.CE(VCC),
.CLK(\out/baud1/timer<5>/CLKINV_4594 ),
.SET(GND),
.RST(\out/baud1/timer<5>/SRINV_4595 ),
.O(\out/baud1/timer [4])
);
X_LUT4 #(
.INIT ( 16'h30C0 ),
.LOC ( "SLICE_X30Y30" ))
\out/baud1/timer_mux0000<1>1 (
.ADR0(VCC),
.ADR1(\out/baud1/Madd_timer_addsub0000_cy<5>_0 ),
.ADR2(\out/baud1/N01 ),
.ADR3(\out/baud1/timer [6]),
.O(\out/baud1/timer_mux0000 [1])
);
X_FF #(
.LOC ( "SLICE_X29Y33" ),
.INIT ( 1'b0 ))
\out/baud1/timer_1 (
.I(\out/baud1/timer<1>/DXMUX_4550 ),
.CE(VCC),
.CLK(\out/baud1/timer<1>/CLKINV_4526 ),
.SET(GND),
.RST(\out/baud1/timer<1>/SRINV_4527 ),
.O(\out/baud1/timer [1])
);
X_FF #(
.LOC ( "SLICE_X30Y30" ),
.INIT ( 1'b0 ))
\out/baud1/timer_7 (
.I(\out/baud1/timer<7>/DXMUX_4660 ),
.CE(VCC),
.CLK(\out/baud1/timer<7>/CLKINV_4636 ),
.SET(GND),
.RST(\out/baud1/timer<7>/SRINV_4637 ),
.O(\out/baud1/timer [7])
);
X_LUT4 #(
.INIT ( 16'hFE04 ),
.LOC ( "SLICE_X9Y41" ))
\out/shift_out_mux0000<2>1 (
.ADR0(\out/pstate_FSM_FFd2_1423 ),
.ADR1(\out/to_shift [1]),
.ADR2(\out/empty ),
.ADR3(\out/shift_out [3]),
.O(\out/shift_out_mux0000 [2])
);
X_FF #(
.LOC ( "SLICE_X8Y41" ),
.INIT ( 1'b1 ))
\out/shift_out_0 (
.I(\out/shift_out<1>/DYMUX_4690 ),
.CE(\out/shift_out<1>/CEINV_4679 ),
.CLK(\out/shift_out<1>/CLKINV_4680 ),
.SET(\out/shift_out<1>/SRINV_4681 ),
.RST(GND),
.O(\out/shift_out [0])
);
X_FF #(
.LOC ( "SLICE_X9Y41" ),
.INIT ( 1'b1 ))
\out/shift_out_3 (
.I(\out/shift_out<3>/DXMUX_4748 ),
.CE(\out/shift_out<3>/CEINV_4724 ),
.CLK(\out/shift_out<3>/CLKINV_4725 ),
.SET(\out/shift_out<3>/SRINV_4726 ),
.RST(GND),
.O(\out/shift_out [3])
);
X_FF #(
.LOC ( "SLICE_X9Y41" ),
.INIT ( 1'b1 ))
\out/shift_out_2 (
.I(\out/shift_out<3>/DYMUX_4734 ),
.CE(\out/shift_out<3>/CEINV_4724 ),
.CLK(\out/shift_out<3>/CLKINV_4725 ),
.SET(\out/shift_out<3>/SRINV_4726 ),
.RST(GND),
.O(\out/shift_out [2])
);
X_LUT4 #(
.INIT ( 16'hCDC8 ),
.LOC ( "SLICE_X13Y38" ))
\out/shift_out_mux0000<4>1 (
.ADR0(\out/pstate_FSM_FFd2_1423 ),
.ADR1(\out/shift_out [5]),
.ADR2(\out/empty ),
.ADR3(\out/to_shift [3]),
.O(\out/shift_out_mux0000 [4])
);
X_LUT4 #(
.INIT ( 16'hF1E0 ),
.LOC ( "SLICE_X9Y41" ))
\out/shift_out_mux0000<3>1 (
.ADR0(\out/pstate_FSM_FFd2_1423 ),
.ADR1(\out/empty ),
.ADR2(\out/shift_out [4]),
.ADR3(\out/to_shift [2]),
.O(\out/shift_out_mux0000 [3])
);
X_LUT4 #(
.INIT ( 16'hF0C0 ),
.LOC ( "SLICE_X8Y41" ))
\out/shift_out_mux0000<0>1 (
.ADR0(VCC),
.ADR1(\out/empty ),
.ADR2(\out/shift_out [1]),
.ADR3(\out/pstate_FSM_FFd2_1423 ),
.O(\out/shift_out_mux0000 [0])
);
X_LUT4 #(
.INIT ( 16'h7800 ),
.LOC ( "SLICE_X30Y30" ))
\out/baud1/timer_mux0000<0>1 (
.ADR0(\out/baud1/timer [6]),
.ADR1(\out/baud1/Madd_timer_addsub0000_cy<5>_0 ),
.ADR2(\out/baud1/timer [7]),
.ADR3(\out/baud1/N01 ),
.O(\out/baud1/timer_mux0000 [0])
);
X_FF #(
.LOC ( "SLICE_X13Y38" ),
.INIT ( 1'b1 ))
\out/shift_out_4 (
.I(\out/shift_out<5>/DYMUX_4778 ),
.CE(\out/shift_out<5>/CEINV_4768 ),
.CLK(\out/shift_out<5>/CLKINV_4769 ),
.SET(\out/shift_out<5>/SRINV_4770 ),
.RST(GND),
.O(\out/shift_out [4])
);
X_FF #(
.LOC ( "SLICE_X30Y30" ),
.INIT ( 1'b0 ))
\out/baud1/timer_6 (
.I(\out/baud1/timer<7>/DYMUX_4646 ),
.CE(VCC),
.CLK(\out/baud1/timer<7>/CLKINV_4636 ),
.SET(GND),
.RST(\out/baud1/timer<7>/SRINV_4637 ),
.O(\out/baud1/timer [6])
);
X_FF #(
.LOC ( "SLICE_X8Y41" ),
.INIT ( 1'b1 ))
\out/shift_out_1 (
.I(\out/shift_out<1>/DXMUX_4704 ),
.CE(\out/shift_out<1>/CEINV_4679 ),
.CLK(\out/shift_out<1>/CLKINV_4680 ),
.SET(\out/shift_out<1>/SRINV_4681 ),
.RST(GND),
.O(\out/shift_out [1])
);
X_LUT4 #(
.INIT ( 16'hCCCA ),
.LOC ( "SLICE_X8Y41" ))
\out/shift_out_mux0000<1>2 (
.ADR0(\out/to_shift [0]),
.ADR1(\out/shift_out [2]),
.ADR2(\out/empty ),
.ADR3(\out/pstate_FSM_FFd2_1423 ),
.O(\out/shift_out_mux0000 [1])
);
X_LUT4 #(
.INIT ( 16'hFE04 ),
.LOC ( "SLICE_X13Y38" ))
\out/shift_out_mux0000<5>1 (
.ADR0(\out/pstate_FSM_FFd2_1423 ),
.ADR1(\out/to_shift [4]),
.ADR2(\out/empty ),
.ADR3(\out/shift_out [6]),
.O(\out/shift_out_mux0000 [5])
);
X_FF #(
.LOC ( "SLICE_X13Y38" ),
.INIT ( 1'b1 ))
\out/shift_out_5 (
.I(\out/shift_out<5>/DXMUX_4792 ),
.CE(\out/shift_out<5>/CEINV_4768 ),
.CLK(\out/shift_out<5>/CLKINV_4769 ),
.SET(\out/shift_out<5>/SRINV_4770 ),
.RST(GND),
.O(\out/shift_out [5])
);
X_SFF #(
.LOC ( "SLICE_X6Y2" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_4917 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_4906 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_4907 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_4908 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
X_FF #(
.LOC ( "SLICE_X15Y32" ),
.INIT ( 1'b1 ))
\out/shift_out_8 (
.I(\out/shift_out<8>/DYMUX_4887 ),
.CE(\out/shift_out<8>/CEINV_4876 ),
.CLK(\out/shift_out<8>/CLKINV_4877 ),
.SET(\out/shift_out<8>/FFY/SET ),
.RST(GND),
.O(\out/shift_out [8])
);
X_BUF #(
.LOC ( "SLICE_X15Y32" ))
\out/shift_out<8>/FFY/SETOR (
.I(reset_IBUF_1366),
.O(\out/shift_out<8>/FFY/SET )
);
X_SFF #(
.LOC ( "SLICE_X6Y2" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_4930 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_4906 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_4907 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_4908 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
X_LUT4 #(
.INIT ( 16'h6AAA ),
.LOC ( "SLICE_X6Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3>11 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\in/fifo1/Result<3>1 )
);
X_LUT4 #(
.INIT ( 16'h0C3F ),
.LOC ( "SLICE_X24Y7" ))
\Madd_data_add0000_xor<0>11 (
.ADR0(VCC),
.ADR1(addr_rx[1]),
.ADR2(\in/control [0]),
.ADR3(\in/dout_fifo [0]),
.O(\data_add0000[0] )
);
X_FF #(
.LOC ( "SLICE_X14Y19" ),
.INIT ( 1'b0 ))
\in/frame_error_8 (
.I(\in/frame_error<8>/DYMUX_4861 ),
.CE(\in/frame_error<8>/CEINV_4849 ),
.CLK(\in/frame_error<8>/CLKINV_4850 ),
.SET(GND),
.RST(\in/frame_error<8>/FFY/RSTAND_4867 ),
.O(\in/frame_error [8])
);
X_BUF #(
.LOC ( "SLICE_X14Y19" ))
\in/frame_error<8>/FFY/RSTAND (
.I(reset_IBUF_1366),
.O(\in/frame_error<8>/FFY/RSTAND_4867 )
);
X_LUT4 #(
.INIT ( 16'hCCCA ),
.LOC ( "SLICE_X15Y33" ))
\out/shift_out_mux0000<6>1 (
.ADR0(\out/to_shift [5]),
.ADR1(\out/shift_out [7]),
.ADR2(\out/pstate_FSM_FFd2_1423 ),
.ADR3(\out/empty ),
.O(\out/shift_out_mux0000 [6])
);
X_LUT4 #(
.INIT ( 16'hAAB8 ),
.LOC ( "SLICE_X15Y33" ))
\out/shift_out_mux0000<7>1 (
.ADR0(\out/shift_out [8]),
.ADR1(\out/empty ),
.ADR2(\out/to_shift [6]),
.ADR3(\out/pstate_FSM_FFd2_1423 ),
.O(\out/shift_out_mux0000 [7])
);
X_LUT4 #(
.INIT ( 16'hDDDD ),
.LOC ( "SLICE_X14Y19" ))
\in/frame_error_8_or00001 (
.ADR0(\in/shift [9]),
.ADR1(\in/shift [0]),
.ADR2(VCC),
.ADR3(VCC),
.O(\in/frame_error_8_or0000 )
);
X_LUT4 #(
.INIT ( 16'hFFFC ),
.LOC ( "SLICE_X15Y32" ))
\out/shift_out_mux0000<8>1 (
.ADR0(VCC),
.ADR1(\out/empty ),
.ADR2(\out/pstate_FSM_FFd2_1423 ),
.ADR3(\out/to_shift [7]),
.O(\out/shift_out_mux0000 [8])
);
X_LUT4 #(
.INIT ( 16'h5AF0 ),
.LOC ( "SLICE_X3Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2>11 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR1(VCC),
.ADR2(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\out/fifo1/Result [2])
);
X_LUT4 #(
.INIT ( 16'h3CF0 ),
.LOC ( "SLICE_X6Y2" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2>11 (
.ADR0(VCC),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\in/fifo1/Result<2>1 )
);
X_FF #(
.LOC ( "SLICE_X15Y33" ),
.INIT ( 1'b1 ))
\out/shift_out_7 (
.I(\out/shift_out<7>/DXMUX_4836 ),
.CE(\out/shift_out<7>/CEINV_4812 ),
.CLK(\out/shift_out<7>/CLKINV_4813 ),
.SET(\out/shift_out<7>/SRINV_4814 ),
.RST(GND),
.O(\out/shift_out [7])
);
X_FF #(
.LOC ( "SLICE_X15Y33" ),
.INIT ( 1'b1 ))
\out/shift_out_6 (
.I(\out/shift_out<7>/DYMUX_4822 ),
.CE(\out/shift_out<7>/CEINV_4812 ),
.CLK(\out/shift_out<7>/CLKINV_4813 ),
.SET(\out/shift_out<7>/SRINV_4814 ),
.RST(GND),
.O(\out/shift_out [6])
);
X_SFF #(
.LOC ( "SLICE_X8Y0" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DYMUX_4959 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_4948 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_4949 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_4950 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
X_SFF #(
.LOC ( "SLICE_X8Y0" ),
.INIT ( 1'b0 ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/DXMUX_4972 ),
.CE(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CEINV_4948 ),
.CLK(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/CLKINV_4949 ),
.SET(GND),
.RST(GND),
.SSET(GND),
.SRST(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count<3>/SRINV_4950 ),
.O(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
X_LUT4 #(
.INIT ( 16'h3CCC ),
.LOC ( "SLICE_X8Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2>11 (
.ADR0(VCC),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\in/fifo1/Result [2])
);
X_FF #(
.LOC ( "SLICE_X13Y33" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DYMUX_5070 ),
.CE(VCC),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_5061 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_5062 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_1532 )
);
X_FF #(
.LOC ( "SLICE_X13Y33" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/DXMUX_5084 ),
.CE(VCC),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/CLKINV_5061 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2/SRINV_5062 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_1533 )
);
X_LUT4 #(
.INIT ( 16'h3CCC ),
.LOC ( "SLICE_X22Y34" ))
\out/Mcount_bittimer_xor<2>11 (
.ADR0(VCC),
.ADR1(\out/bittimer [2]),
.ADR2(\out/bittimer [0]),
.ADR3(\out/bittimer [1]),
.O(\out/Result [2])
);
X_LUT4 #(
.INIT ( 16'h3B33 ),
.LOC ( "SLICE_X13Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_1532 ),
.ADR1(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_1488 ),
.ADR2(\out/ld_shift ),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_1533 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In )
);
X_FF #(
.LOC ( "SLICE_X3Y30" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DYMUX_5001 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_4990 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_4991 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_4992 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
X_LUT4 #(
.INIT ( 16'h6CCC ),
.LOC ( "SLICE_X3Y30" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3>11 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.ADR1(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.ADR2(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\out/fifo1/Result [3])
);
X_FF #(
.LOC ( "SLICE_X22Y34" ),
.INIT ( 1'b0 ))
\out/bittimer_2 (
.I(\out/bittimer<3>/DYMUX_5114 ),
.CE(\out/bittimer<3>/CEINV_5103 ),
.CLK(\out/bittimer<3>/CLKINV_5104 ),
.SET(GND),
.RST(\out/bittimer<3>/SRINV_5105 ),
.O(\out/bittimer [2])
);
X_FF #(
.LOC ( "SLICE_X24Y7" ),
.INIT ( 1'b1 ))
data_0 (
.I(\data<0>/DYMUX_5042 ),
.CE(\data<0>/CEINV_5031 ),
.CLK(\data<0>/CLKINV_5032 ),
.SET(\data<0>/FFY/SET ),
.RST(GND),
.O(data[0])
);
X_BUF #(
.LOC ( "SLICE_X24Y7" ))
\data<0>/FFY/SETOR (
.I(reset_IBUF_1366),
.O(\data<0>/FFY/SET )
);
X_LUT4 #(
.INIT ( 16'hFEAA ),
.LOC ( "SLICE_X13Y33" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In1 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_1532 ),
.ADR1(\out/pstate_FSM_FFd2_1423 ),
.ADR2(\out/empty ),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_1533 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In )
);
X_LUT4 #(
.INIT ( 16'h7F80 ),
.LOC ( "SLICE_X8Y0" ))
\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3>11 (
.ADR0(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.ADR1(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.ADR2(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.ADR3(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\in/fifo1/Result [3])
);
X_FF #(
.LOC ( "SLICE_X3Y30" ),
.INIT ( 1'b0 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/DXMUX_5016 ),
.CE(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CEINV_4990 ),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/CLKINV_4991 ),
.SET(GND),
.RST(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count<3>/SRINV_4992 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
X_LUT4 #(
.INIT ( 16'h3300 ),
.LOC ( "SLICE_X21Y19" ))
\in/pstate_mux0000<1>1 (
.ADR0(VCC),
.ADR1(\in/control [2]),
.ADR2(VCC),
.ADR3(\in/finish ),
.O(\in/pstate_mux0000 [1])
);
X_SRLC16E #(
.INIT ( 16'h0000 ),
.LOC ( "SLICE_X16Y23" ))
\in/Mshreg_in_two/SRL16E (
.A0(GND),
.A1(GND),
.A2(GND),
.A3(GND),
.D(\in/in_two/DIG_MUX_5174 ),
.CE(\in/in_two/WSG ),
.CLK(\in/in_two/CLKINV_5172 ),
.Q(\in/Mshreg_in_two ),
.Q15(\NLW_in/Mshreg_in_two/SRL16E_Q15_UNCONNECTED )
);
X_LUT4 #(
.INIT ( 16'h78F0 ),
.LOC ( "SLICE_X22Y34" ))
\out/Mcount_bittimer_xor<3>11 (
.ADR0(\out/bittimer [0]),
.ADR1(\out/bittimer [2]),
.ADR2(\out/bittimer [3]),
.ADR3(\out/bittimer [1]),
.O(\out/Result [3])
);
X_FF #(
.LOC ( "SLICE_X14Y10" ),
.INIT ( 1'b0 ))
trans_1 (
.I(\trans<1>/DXMUX_5224 ),
.CE(VCC),
.CLK(\trans<1>/CLKINV_5200 ),
.SET(GND),
.RST(\trans<1>/SRINV_5201 ),
.O(trans[1])
);
X_FF #(
.LOC ( "SLICE_X14Y10" ),
.INIT ( 1'b0 ))
trans_0 (
.I(\trans<1>/DYMUX_5210 ),
.CE(VCC),
.CLK(\trans<1>/CLKINV_5200 ),
.SET(GND),
.RST(\trans<1>/SRINV_5201 ),
.O(trans[0])
);
X_FF #(
.LOC ( "SLICE_X22Y34" ),
.INIT ( 1'b0 ))
\out/bittimer_3 (
.I(\out/bittimer<3>/DXMUX_5129 ),
.CE(\out/bittimer<3>/CEINV_5103 ),
.CLK(\out/bittimer<3>/CLKINV_5104 ),
.SET(GND),
.RST(\out/bittimer<3>/SRINV_5105 ),
.O(\out/bittimer [3])
);
X_FF #(
.LOC ( "SLICE_X21Y19" ),
.INIT ( 1'b0 ))
\in/frame_ready (
.I(\in/pstate<4>/DYMUX_5251 ),
.CE(VCC),
.CLK(\in/pstate<4>/CLKINV_5242 ),
.SET(GND),
.RST(\in/pstate<4>/SRINV_5243 ),
.O(\in/frame_ready_1417 )
);
X_FF #(
.LOC ( "SLICE_X19Y11" ),
.INIT ( 1'b0 ))
pstate_FSM_FFd3 (
.I(\pstate_FSM_FFd3/DYMUX_5153 ),
.CE(VCC),
.CLK(\pstate_FSM_FFd3/CLKINV_5143 ),
.SET(GND),
.RST(\pstate_FSM_FFd3/FFY/RSTAND_5158 ),
.O(pstate_FSM_FFd3_1543)
);
X_BUF #(
.LOC ( "SLICE_X19Y11" ))
\pstate_FSM_FFd3/FFY/RSTAND (
.I(reset_IBUF_1366),
.O(\pstate_FSM_FFd3/FFY/RSTAND_5158 )
);
X_LUT4 #(
.INIT ( 16'h143C ),
.LOC ( "SLICE_X14Y10" ))
\Mcount_trans_xor<1>11 (
.ADR0(dout[1]),
.ADR1(trans[0]),
.ADR2(trans[1]),
.ADR3(pstate_FSM_FFd3_1543),
.O(Mcount_trans1)
);
X_FF #(
.LOC ( "SLICE_X16Y23" ),
.INIT ( 1'b0 ))
\in/in_two (
.I(\in/in_two/DYMUX_5185 ),
.CE(VCC),
.CLK(\in/in_two/CLKINV_5172 ),
.SET(GND),
.RST(GND),
.O(\in/in_two_1395 )
);
X_LUT4 #(
.INIT ( 16'h0020 ),
.LOC ( "SLICE_X21Y19" ))
\in/bitcounter_not00011 (
.ADR0(\in/bitcounter [1]),
.ADR1(N27_0),
.ADR2(\in/bitcounter [3]),
.ADR3(\in/bitcounter [2]),
.O(\in/finish_pack_1 )
);
X_LUT4 #(
.INIT ( 16'h1133 ),
.LOC ( "SLICE_X14Y10" ))
\Mcount_trans_xor<0>11 (
.ADR0(dout[1]),
.ADR1(trans[0]),
.ADR2(VCC),
.ADR3(pstate_FSM_FFd3_1543),
.O(Mcount_trans)
);
X_LUT4 #(
.INIT ( 16'hF3F0 ),
.LOC ( "SLICE_X19Y11" ))
\pstate_FSM_FFd3-In1 (
.ADR0(VCC),
.ADR1(dout[1]),
.ADR2(pstate_FSM_FFd4_1516),
.ADR3(pstate_FSM_FFd3_1543),
.O(\pstate_FSM_FFd3-In )
);
X_LUT4 #(
.INIT ( 16'h3C00 ),
.LOC ( "SLICE_X30Y23" ))
\in/baud1/timer_mux0000<6>1 (
.ADR0(VCC),
.ADR1(\in/baud1/timer [1]),
.ADR2(\in/baud1/timer [0]),
.ADR3(\in/baud1/N01 ),
.O(\in/baud1/timer_mux0000 [6])
);
X_FF #(
.LOC ( "SLICE_X21Y19" ),
.INIT ( 1'b0 ))
\in/pstate_4 (
.I(\in/pstate<4>/DXMUX_5267 ),
.CE(VCC),
.CLK(\in/pstate<4>/CLKINV_5242 ),
.SET(GND),
.RST(\in/pstate<4>/SRINV_5243 ),
.O(\in/pstate [4])
);
X_FF #(
.LOC ( "SLICE_X30Y22" ),
.INIT ( 1'b0 ))
\in/baud1/timer_2 (
.I(\in/baud1/timer<3>/DYMUX_5387 ),
.CE(VCC),
.CLK(\in/baud1/timer<3>/CLKINV_5378 ),
.SET(GND),
.RST(\in/baud1/timer<3>/SRINV_5379 ),
.O(\in/baud1/timer [2])
);
X_LUT4 #(
.INIT ( 16'h60A0 ),
.LOC ( "SLICE_X30Y22" ))
\in/baud1/timer_mux0000<4> (
.ADR0(\in/baud1/timer [3]),
.ADR1(\in/baud1/timer [2]),
.ADR2(\in/baud1/N01 ),
.ADR3(N31_0),
.O(\in/baud1/timer_mux0000 [4])
);
X_FF #(
.LOC ( "SLICE_X30Y22" ),
.INIT ( 1'b0 ))
\in/baud1/timer_3 (
.I(\in/baud1/timer<3>/DXMUX_5401 ),
.CE(VCC),
.CLK(\in/baud1/timer<3>/CLKINV_5378 ),
.SET(GND),
.RST(\in/baud1/timer<3>/SRINV_5379 ),
.O(\in/baud1/timer [3])
);
X_LUT4 #(
.INIT ( 16'h4C80 ),
.LOC ( "SLICE_X30Y22" ))
\in/baud1/timer_mux0000<5>1 (
.ADR0(\in/baud1/timer [1]),
.ADR1(\in/baud1/N01 ),
.ADR2(\in/baud1/timer [0]),
.ADR3(\in/baud1/timer [2]),
.O(\in/baud1/timer_mux0000 [5])
);
X_FF #(
.LOC ( "SLICE_X13Y35" ),
.INIT ( 1'b1 ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/DYMUX_5337 ),
.CE(VCC),
.CLK(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/CLKINV_5328 ),
.SET(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FFY/SET ),
.RST(GND),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_1610 )
);
X_BUF #(
.LOC ( "SLICE_X13Y35" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FFY/SETOR (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/rd_rst_reg[2] ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb/FFY/SET )
);
X_FF #(
.LOC ( "SLICE_X21Y24" ),
.INIT ( 1'b0 ))
\in/load (
.I(\in/load/DYMUX_5291 ),
.CE(VCC),
.CLK(\in/load/CLKINV_5282 ),
.SET(GND),
.RST(\in/load/FFY/RSTAND_5296 ),
.O(\in/load_1503 )
);
X_BUF #(
.LOC ( "SLICE_X21Y24" ))
\in/load/FFY/RSTAND (
.I(reset_IBUF_1366),
.O(\in/load/FFY/RSTAND_5296 )
);
X_FF #(
.LOC ( "SLICE_X16Y15" ),
.INIT ( 1'b1 ))
\in/pstate_0 (
.I(\in/pstate<0>/DYMUX_5314 ),
.CE(VCC),
.CLK(\in/pstate<0>/CLKINV_5305 ),
.SET(\in/pstate<0>/FFY/SET ),
.RST(GND),
.O(\in/pstate [0])
);
X_BUF #(
.LOC ( "SLICE_X16Y15" ))
\in/pstate<0>/FFY/SETOR (
.I(reset_IBUF_1366),
.O(\in/pstate<0>/FFY/SET )
);
X_LUT4 #(
.INIT ( 16'h3302 ),
.LOC ( "SLICE_X16Y15" ))
\in/pstate_mux0000<5>1 (
.ADR0(\in/pstate [0]),
.ADR1(\in/control [2]),
.ADR2(\in/control [0]),
.ADR3(\in/pstate [5]),
.O(\in/pstate_mux0000 [5])
);
X_LUT4 #(
.INIT ( 16'hAF08 ),
.LOC ( "SLICE_X13Y35" ))
\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_or00001 (
.ADR0(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_1533 ),
.ADR1(\out/ld_shift ),
.ADR2(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_1532 ),
.ADR3(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_1610 ),
.O(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_or0000 )
);
X_LUT4 #(
.INIT ( 16'h0040 ),
.LOC ( "SLICE_X21Y24" ))
\in/ld_shift (
.ADR0(\in/loaded_1548 ),
.ADR1(\in/pstate [3]),
.ADR2(\in/bittimer [3]),
.ADR3(N25),
.O(\in/ld_shift_5288 )
);
X_FF #(
.LOC ( "SLICE_X30Y23" ),
.INIT ( 1'b0 ))
\in/baud1/timer_1 (
.I(\in/baud1/timer<1>/DYMUX_5359 ),
.CE(VCC),
.CLK(\in/baud1/timer<1>/CLKINV_5349 ),
.SET(GND),
.RST(\in/baud1/timer<1>/FFY/RSTAND_5364 ),
.O(\in/baud1/timer [1])
);
X_BUF #(
.LOC ( "SLICE_X30Y23" ))
\in/baud1/timer<1>/FFY/RSTAND (
.I(reset_IBUF_1366),
.O(\in/baud1/timer<1>/FFY/RSTAND_5364 )
);
X_FF #(
.LOC ( "SLICE_X28Y22" ),
.INIT ( 1'b0 ))
\in/baud1/timer_4 (
.I(\in/baud1/timer<5>/DYMUX_5429 ),
.CE(VCC),
.CLK(\in/baud1/timer<5>/CLKINV_5419 ),
.SET(GND),
.RST(\in/baud1/timer<5>/SRINV_5420 ),
.O(\in/baud1/timer [4])
);
X_FF #(
.LOC ( "SLICE_X28Y22" ),
.INIT ( 1'b0 ))
\in/baud1/timer_5 (
.I(\in/baud1/timer<5>/DXMUX_5443 ),
.CE(VCC),
.CLK(\in/baud1/timer<5>/CLKINV_5419 ),
.SET(GND),
.RST(\in/baud1/timer<5>/SRINV_5420 ),
.O(\in/baud1/timer [5])
);
X_LUT4 #(
.INIT ( 16'h6C00 ),
.LOC ( "SLICE_X28Y22" ))
\in/baud1/timer_mux0000<2>1 (
.ADR0(\in/baud1/timer [4]),
.ADR1(\in/baud1/timer [5]),
.ADR2(\in/baud1/Madd_timer_addsub0000_cy[3] ),
.ADR3(\in/baud1/N01 ),
.O(\in/baud1/timer_mux0000 [2])
);
X_LUT4 #(
.INIT ( 16'h5A00 ),
.LOC ( "SLICE_X28Y22" ))
\in/baud1/timer_mux0000<3>1 (
.ADR0(\in/baud1/timer [4]),
.ADR1(VCC),
.ADR2(\in/baud1/Madd_timer_addsub0000_cy[3] ),
.ADR3(\in/baud1/N01 ),
.O(\in/baud1/timer_mux0000 [3])
);
X_BUF #(
.LOC ( "PAD69" ))
\Led<0>/OUTPUT/OFF/OMUX (
.I(data[0]),
.O(\Led<0>/O )
);
X_BUF #(
.LOC ( "PAD108" ))
\tx/OUTPUT/OFF/OMUX (
.I(\out/shift_out [0]),
.O(\tx/O )
);
X_BUF #(
.LOC ( "PAD58" ))
\Led<1>/OUTPUT/OFF/OMUX (
.I(data[1]),
.O(\Led<1>/O )
);
X_BUF #(
.LOC ( "PAD96" ))
\Led<7>/OUTPUT/OFF/OMUX (
.I(data[7]),
.O(\Led<7>/O )
);
X_BUF #(
.LOC ( "PAD70" ))
\Led<6>/OUTPUT/OFF/OMUX (
.I(data[6]),
.O(\Led<6>/O )
);
X_BUF #(
.LOC ( "PAD71" ))
\Led<5>/OUTPUT/OFF/OMUX (
.I(data[5]),
.O(\Led<5>/O )
);
X_BUF #(
.LOC ( "PAD65" ))
\Led<3>/OUTPUT/OFF/OMUX (
.I(data[3]),
.O(\Led<3>/O )
);
X_BUF #(
.LOC ( "PAD68" ))
\Led<4>/OUTPUT/OFF/OMUX (
.I(data[4]),
.O(\Led<4>/O )
);
X_BUF #(
.LOC ( "PAD64" ))
\Led<2>/OUTPUT/OFF/OMUX (
.I(data[2]),
.O(\Led<2>/O )
);
X_BUF #(
.LOC ( "SLICE_X16Y23" ))
\in/Mshreg_in_two/SRL16E.CE/WSGAND (
.I(\in/in_two/SRINV_5168 ),
.O(\in/in_two/WSG )
);
X_BUF
\NlwBufferBlock_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O
(\NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> )
);
X_BUF
\NlwBufferBlock_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.O
(\NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> )
);
X_BUF
\NlwBufferBlock_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.O
(\NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> )
);
X_BUF
\NlwBufferBlock_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> (
.I(\out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.O
(\NlwBufferSignal_out/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<3> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<2> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<1> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRA<0> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<3> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<2> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<1> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> (
.I(\in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/ADDRB<0> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> (
.I(\in/frame_error [0]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<0> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> (
.I(\in/frame_error [1]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<1> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<2> (
.I(\in/frame_error [2]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<2> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> (
.I(\in/frame_error [3]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<8> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> (
.I(\in/frame_error [4]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<9> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> (
.I(\in/frame_error [5]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<16> )
);
X_BUF
\NlwBufferBlock_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> (
.I(\in/frame_error [8]),
.O
(\NlwBufferSignal_in/fifo1/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/DIA<25> )
);
X_ONE NlwBlock_uart_VCC (
.O(VCC)
);
X_ZERO NlwBlock_uart_GND (
.O(GND)
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__AND3B_FUNCTIONAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_FUNCTIONAL_PP_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:49:16 2016
/////////////////////////////////////////////////////////////
module ACA_II_N8_Q4 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24;
CLKAND2X2TS U18 ( .A(in1[0]), .B(in2[0]), .Y(n20) );
XOR2XLTS U19 ( .A(in1[3]), .B(in2[3]), .Y(n17) );
XOR2XLTS U20 ( .A(in1[5]), .B(in2[5]), .Y(n15) );
OAI211XLTS U21 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[4]), .C0(in1[4]), .Y(n22)
);
OAI211XLTS U22 ( .A0(in2[3]), .A1(in1[3]), .B0(in2[2]), .C0(in1[2]), .Y(n14)
);
AOI2BB1XLTS U23 ( .A0N(in1[0]), .A1N(in2[0]), .B0(n20), .Y(res[0]) );
OAI2BB1X1TS U24 ( .A0N(in1[3]), .A1N(in2[3]), .B0(n14), .Y(n19) );
XOR2XLTS U25 ( .A(n16), .B(n15), .Y(res[5]) );
XOR2XLTS U26 ( .A(n18), .B(n17), .Y(res[3]) );
CMPR32X2TS U27 ( .A(in2[4]), .B(in1[4]), .C(n19), .CO(n16), .S(res[4]) );
CMPR32X2TS U28 ( .A(in1[1]), .B(in2[1]), .C(n20), .CO(n21), .S(res[1]) );
CMPR32X2TS U29 ( .A(in1[2]), .B(in2[2]), .C(n21), .CO(n18), .S(res[2]) );
OAI2BB1X1TS U30 ( .A0N(in1[5]), .A1N(in2[5]), .B0(n22), .Y(n23) );
CMPR32X2TS U31 ( .A(in1[6]), .B(in2[6]), .C(n23), .CO(n24), .S(res[6]) );
CMPR32X2TS U32 ( .A(in1[7]), .B(in2[7]), .C(n24), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("ACA_II_N8_Q4_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22A_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O22A_FUNCTIONAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22A_FUNCTIONAL_V
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import Cpdt.CpdtTactics Cpdt.MoreSpecif.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(*
(** %\chapter{Proof by Reflection}% *)
*)
(** %\chapter{リフレクションによる証明}% *)
(**
(* The last chapter highlighted a very heuristic approach to proving. In this chapter, we will study an alternative technique,%\index{proof by reflection}% _proof by reflection_ %\cite{reflection}%. We will write, in Gallina, decision procedures with proofs of correctness, and we will appeal to these procedures in writing very short proofs. Such a proof is checked by running the decision procedure. The term _reflection_ applies because we will need to translate Gallina propositions into values of inductive types representing syntax, so that Gallina programs may analyze them, and translating such a term back to the original form is called _reflecting_ it. *)
最後の章では、証明に対する非常にヒューリスティックなアプローチが強調されていました。
この章では、代替の技術、
%\index{proof by reflection}%_proof by reflection_ ＿リフレクションによる証明＿
%\cite{reflection}% を検討します。
Gallinaによって、決定手続き(decision procedures、決定するための手続き)
を正しさの証明とともに書いて、
これらの手続きが非常に短い証明で書けることを示します(appeal)。
項の _reflection_ ＿リフレクション＿ は、
Gallinaの命題を構文が表す帰納型の値に変換する必要があるために、適用されます。
それで、Gallinaプログラムがそれらを解析し、
そのような項を元の形式に戻すことを ＿リフレクトする＿ (_reflecting_ it) と呼びます。
*)
(*
(** * Proving Evenness *)
*)
(** * 偶数であることの証明 *)
(**
(* Proving that particular natural number constants are even is certainly something we would rather have happen automatically. The Ltac-programming techniques that we learned in the last chapter make it easy to implement such a procedure. *)
特定の自然数の定数が偶数であることを証明することは、確かに自動的にできることです。
前章で学習したLtacプログラミング手法は、このような手順を簡単に実装できます。
*)
Inductive isEven : nat -> Prop :=
| Even_O : isEven O
| Even_SS : forall n, isEven n -> isEven (S (S n)).
(* begin thide *)
Ltac prove_even := repeat constructor.
(* end thide *)
Theorem even_256 : isEven 256.
prove_even.
Qed.
Print even_256.
(** %\vspace{-.15in}% [[
even_256 =
Even_SS
(Even_SS
(Even_SS
(Even_SS
]]
(*
%\noindent%...and so on. This procedure always works (at least on machines with infinite resources), but it has a serious drawback, which we see when we print the proof it generates that 256 is even. The final proof term has length super-linear in the input value. Coq's implicit arguments mechanism is hiding the values given for parameter [n] of [Even_SS], which is why the proof term only appears linear here. Also, proof terms are represented internally as syntax trees, with opportunity for sharing of node representations, but in this chapter we will measure proof term size as simple textual length or as the number of nodes in the term's syntax tree, two measures that are approximately equivalent. Sometimes apparently large proof terms have enough internal sharing that they take up less memory than we expect, but one avoids having to reason about such sharing by ensuring that the size of a sharing-free version of a term is low enough.
*)
%\noindent%
...等々。
この手順は常に（少なくとも無限のリソースを持つマシンでは）機能しますが、
重大な欠点があります。これは、256が偶数であるという証明を印刷(print)するときに表示されます。
最終的な証明項は、入力値に対して長さが超線形(super-linear)です。
Coqの暗黙的な引数の仕組みは、[Even_SS]のパラメータ[n]に与えられた値を隠しているので、
ここでは証明項はここでは線形にしか見えません。
(* suhara:
以下を実行すると納得できる：
Unset Printing Notations.
Set Printing Implicit.
Print even_256.
Set Printing Notations.
Unset Printing Implicit.
*)
また、証明項は内部的に構文木として表現され、ノード表現を共有する機会がありますが、
この章では、ほぼ同等の2つの尺度、証明文の長さを簡単なテキストの長さとして、
または、用語の構文木のノード数として測定します。
時には明らかに大きな証明項でも、内部では十分な共有を持っているため、
予想以上のメモリを消費することはありませんが、
共有のない(sharing-free)バージョンのサイズが十分に小さいことを保証することによって、
そのような共有を推論する必要はありません。
(*
Superlinear evenness proof terms seem like a shame, since we could write a trivial and trustworthy program to verify evenness of constants. The proof checker could simply call our program where needed.
*)
定数の偶数性を検証するための自明で信頼できるプログラムを書くことができるので、
超線形(Superlinear)な偶数性の証明項は残念なものに見えます。
証明チェッカーは、必要に応じて私たちのプログラムを単に呼び出すことができます。
(*
It is also unfortunate not to have static typing guarantees that our tactic always behaves appropriately. Other invocations of similar tactics might fail with dynamic type errors, and we would not know about the bugs behind these errors until we happened to attempt to prove complex enough goals.
*)
静的な型付けが、私たちのタクティクが常に適切に動作することを保証しないことも残念です。
同様の手法の他の呼び出しは、動的な型エラーで失敗する可能性があり、
十分に複雑なゴールを証明しようとするまで、
これらのエラーの背後にあるバグについてはわかりません。
(*
The techniques of proof by reflection address both complaints. We will be able to write proofs like in the example above with constant size overhead beyond the size of the input, and we will do it with verified decision procedures written in Gallina.
*)
リフレクションによる証明の手法は、両方の不満に対処します。
入力のサイズを超えて一定のサイズ(constant size)のオーバーヘッドを
持つ上記の例のような証明を書くことができ、
私たちはGallinaで書かれた検証された決定手続き(decision procedures)でそれを行います。
(*
For this example, we begin by using a type from the [MoreSpecif] module (included in the book source) to write a certified evenness checker. *)
この例では、[MoreSpecif] モジュール（この本のソースに含まれています）の型を使用して、
認証された偶数性のチェッカーを作成します。
*)
(* begin hide *)
(* begin thide *)
Definition paartial := partial.
(* end thide *)
(* end hide *)
(* suhara: src/MoreSpecif.v の partial 型 *)
Print partial.
(** %\vspace{-.15in}% [[
Inductive partial (P : Prop) : Set := Proved : P -> [P] | Uncertain : [P]
]]
(*
A [partial P] value is an optional proof of [P]. The notation [[P]] stands for [partial P]. *)
[partial P] の値は、[P]のオプショナルな証明です。 表記[[P]]は[partial P]の略です。
*)
(* suhara: 「オプション型」「オプショナルな型」に対応する「オプショナルな証明」
命題 [P]に対して、[t : P] であるとき、
それを [[]] で囲んだ、[[P]] には要素 [Proved t] と、[Uncertain P] がある。
なお、[Proved t] は [@Proved P t] の略である。
Check [True].
Check Proved I : [True].
Check @Proved True I : [True].
Check Uncertain True : [True].
Check [False].
Check @Proved False _. (* 存在しない値 *)
Check Uncertain False : [False].
Compute Proved Even_O : [isEven 0]. (* Yes *)
Compute @Proved (isEven 0) Even_O : [isEven 0]. (* Yes *)
Compute Uncertain (isEven 1) : [isEven 1]. (* No *)
*)
Local Open Scope partial_scope.
(**
(* We bring into scope some notations for the [partial] type. These overlap with some of the notations we have seen previously for specification types, so they were placed in a separate scope that needs separate opening. *)
私たちは[partial]型の表記をいくつか取り上げます。
これらは、以前に、型の記述(specification types)で見た表記法の
いくつかと重複しているため、別々に開くことが必要な別のスコープに配置されました。
(* suhara: 「specification types」 は、Subset.v で初出する。 *)
*)
(* begin thide *)
Definition check_even : forall n : nat, [isEven n].
Hint Constructors isEven.
refine (fix F (n : nat) : [isEven n] :=
match n with
| 0 => Yes
| 1 => No
| S (S n') => Reduce (F n')
end); auto.
Defined.
(**
(* The function [check_even] may be viewed as a _verified decision procedure_, because its type guarantees that it never returns %\coqdocnotation{%#<tt>#Yes#</tt>#%}% for inputs that are not even.
関数[check_even]は、その型が偶数でない入力に対して
%\coqdocnotation{%#<tt>#Yes#</tt>#%}%
を返さないことを保証するので、
_verified decision procedure_ ＿検証された決定手続き＿
とみなすことができるでしょう。
(* suhara: Reduce は、src/MoreSpecif.v で Notation として定義される。
Notation "'Reduce' x" := if x then Yes else No. *)
*)
(*
Now we can use dependent pattern-matching to write a function that performs a surprising feat. When given a [partial P], this function [partialOut] returns a proof of [P] if the [partial] value contains a proof, and it returns a (useless) proof of [True] otherwise. From the standpoint of ML and Haskell programming, it seems impossible to write such a type, but it is trivial with a [return] annotation. *)
これで、依存パターンマッチング(dependent pattern-matching)を使用して、
驚くべきことを行う関数を書くことができます。
[partialPut]が与えられている場合、[partialOut]は[partial]値に証明が含まれていれば[P]の証明を返し、
それ以外の場合は [True] の（使用しないuseless)の証明を返します。
MLとHaskellのプログラミングの観点からは、このような型を
書くことは不可能ですが、[return]アノテーションを使用すれば自明です。
*)
Definition partialOut (P : Prop) (x : [P]) :=
match x return (match x with
| Proved _ => P
| Uncertain => True
end) with
| Proved pf => pf
| Uncertain => I
end.
(* suhara:
Compute partialOut (@Proved True I). (* I : True、 P=True 本来の証明 *)
Compute partialOut (Uncertain False). (* I : True、 partialOut の機能 *)
Compute partialOut (@Proved (isEven 0) Even_O). (* Even_0 *)
Compute partialOut (Uncertain (isEven 1)). (* I *)
*)
(**
(* It may seem strange to define a function like this. However, it turns out to be very useful in writing a reflective version of our earlier [prove_even] tactic: *)
このような関数を定義するのは奇妙に思えるかもしれませんが、
以前の[prove_even]タクティクのリフレクティブのバージョンを書くのに非常に便利です：*）
*)
Ltac prove_even_reflective :=
match goal with
| [ |- isEven ?N] => exact (partialOut (check_even N))
end.
(* end thide *)
(**
(* We identify which natural number we are considering, and we "prove" its evenness by pulling the proof out of the appropriate [check_even] call. Recall that the %\index{tactics!exact}%[exact] tactic proves a proposition [P] when given a proof term of precisely type [P]. *)
どの自然数を考えているのかを決め、適切な[check_even]の呼び出しから証明を引き出すことによって、
その偶数性を「証明」します。
正確に型 [P] の証明項が与えられたとき、
%\index{tactics!exact}%[exact] タクティクは、
命題 [P] を証明します。
*)
Theorem even_256' : isEven 256.
prove_even_reflective.
Qed.
Print even_256'.
(** %\vspace{-.15in}% [[
even_256' = partialOut (check_even 256)
: isEven 256
]]
(*
We can see a constant wrapper around the object of the proof. For any even number, this form of proof will suffice. The size of the proof term is now linear in the number being checked, containing two repetitions of the unary form of that number, one of which is hidden above within the implicit argument to [partialOut].
*)
私たちは、証明のゴールの周りに一定のラッパーを見ることができます。
偶数の場合は、この形式の証明で十分です。
証明項のサイズは、チェックされている数では線形で、
(* suhara: 実際には check_even の refine の末尾再帰だけ *)
その数の単項式の2つの繰り返しが含まれています。
そのうちのひとつは[partialOut]の暗黙の引数の上に隠されています。
(* suhara:
Set Printing Implicit.
Print even_256'.
even_256' = @partialOut (isEven 256) (check_even 256)
*)
(*
What happens if we try the tactic with an odd number? *)
奇数でこのタクティクを試してみたらどうなりますか？
*)
Theorem even_255 : isEven 255.
(** %\vspace{-.275in}%[[
prove_even_reflective.
]]
<<
User error: No matching clauses for match goal
>>
(*
Thankfully, the tactic fails. To see more precisely what goes wrong, we can run manually the body of the [match].
*)
ありがたいことに、タクティクは失敗します。
間違ったことをより正確に見るために、[match]の本体を手動で実行することができます。
%\vspace{-.15in}%[[
exact (partialOut (check_even 255)).
]]
<<
Error: The term "partialOut (check_even 255)" has type
"match check_even 255 with
| Yes => isEven 255
| No => True
end" while it is expected to have type "isEven 255"
>>
(*
As usual, the type checker performs no reductions to simplify error messages. If we reduced the first term ourselves, we would see that [check_even 255] reduces to a %\coqdocnotation{%#<tt>#No#</tt>#%}%, so that the first term is equivalent to [True], which certainly does not unify with [isEven 255]. *)
いつものように、型チェッカーはエラーメッセージを単純化するために
リダクション(式の簡約)を実行しません。
最初の項を自分自身で簡約した場合、[check_even 255]は
%\coqdocnotation{%#<tt>#No#</tt>#%}%に簡約され、
最初の項
(* suhara: の partialOut の結果は I でその型 *)
は[True]と等しく、
(* suhara: exact の引数は I となり、Iの型[True]は、 *)
[isEven 255]とユニファイしないのは確かです。
(* suhara: 補足説明
(1) partialOut (check_even 255)) を手動で評価する。
@partialOut (isEven 255) (check_even 255) なので、
(1.1) partialOut の return のなかのmatchは、
match check_even 255 with
| Yes => isEven 255
| No => True
end
となる。check_even 255 は No なので、return のmatchは True になる。
(1.2) partialOut の本文のmatch
match (x) with
| Proved pf => pf
| Uncertain => I
end
で、x は [isEven 255] の値なので、Uncertain である。本体のmatchは I になる。
(1.1)と(1.2)から、partialOut (check_even 255) は I : True を返す。
(2) 最初の証明にもどって、
exact partialOut (check_even 255)) は exact I になる。
Theorem even_255 : isEven 255.
exact I.
I の型 isEven 255 ではないので、
exact I は、定理の証明になっておらず、エラーである。
*)
*)
Abort.
(**
(* Our tactic [prove_even_reflective] is reflective because it performs a proof search process (a trivial one, in this case) wholly within Gallina, where the only use of Ltac is to translate a goal into an appropriate use of [check_even]. *)
タクティク[prove_even_reflective]は、リフレクティブです。
なぜなら、Gallina内の証明検索のプロセス（この場合は自明なもの）を実行するために、
Ltacの唯一の使用は目標を[check_even]の適切な使用に変換するためです。
*)
(*
(** * Reifying the Syntax of a Trivial Tautology Language *)
*)
(** * 自明なトートロジーの言語の文法の具象化(reifying) *)
(* suhara: 具象化 https://ja.wikipedia.org/wiki/%E7%89%A9%E8%B1%A1%E5%8C%96 *)
(**
(* We might also like to have reflective proofs of trivial tautologies like this one: *)
このような自明なトートロジーのリフレクティブな証明をしたいかもしれません：
*)
Theorem true_galore : (True /\ True) -> (True \/ (True /\ (True -> True))).
(* suhara: crush でも証明できる。結果は同じである。 *)
tauto.
Qed.
(* begin hide *)
(* begin thide *)
Definition tg := (and_ind, or_introl).
(* end thide *)
(* end hide *)
Print true_galore.
(** %\vspace{-.15in}% [[
true_galore =
fun H : True /\ True =>
and_ind (fun _ _ : True => or_introl (True /\ (True -> True)) I) H
: True /\ True -> True \/ True /\ (True -> True)
]]
(*
As we might expect, the proof that [tauto] builds contains explicit applications of natural deduction rules. For large formulas, this can add a linear amount of proof size overhead, beyond the size of the input.
*)
予想されるように、[tauto] が作る証拠は、
自然演繹規則の明示的な応用が含まれています。
大きな式の場合、これは、入力のサイズを超える、
証明のサイズの線形量のオーバーヘッドを追加する可能性があります。
(*
To write a reflective procedure for this class of goals, we will need to get into the actual "reflection" part of "proof by reflection." It is impossible to case-analyze a [Prop] in any way in Gallina. We must%\index{reification}% _reify_ [Prop] into some type that we _can_ analyze. This inductive type is a good candidate: *)
このクラスのゴールに対してリフレクティブな手順を書くには、
「リフレクティブによる証明」の実際の「リフレクティブ」な部分に入る必要があります。
Gallinaのいかなるところでも、[Prop] を条件分析(case-analyze)することは不可能です。
[Prop] を %\index{reification}% _reify_ ＿具象化＿ して、解析できる型にする必要があります。
この帰納型は良い候補です：
*)
(* begin thide *)
Inductive taut : Set :=
| TautTrue : taut
| TautAnd : taut -> taut -> taut
| TautOr : taut -> taut -> taut
| TautImp : taut -> taut -> taut.
(**
(* We write a recursive function to _reflect_ this syntax back to [Prop]. Such functions are also called%\index{interpretation function}% _interpretation functions_, and we have used them in previous examples to give semantics to small programming languages. *)
この構文を _reflect_ ＿リフレクト＿ して [Prop]に戻すための再帰関数を書きます。
このような関数は
%\index{interpretation function}% _interpretation functions_ ＿翻訳関数＿
とも呼ばれ、前の例で、小さなプログラミング言語に意味論を与えるために使用しています。
(* suhara: あとで denotation function とも呼ばれる。 *)
*)
Fixpoint tautDenote (t : taut) : Prop :=
match t with
| TautTrue => True
| TautAnd t1 t2 => tautDenote t1 /\ tautDenote t2
| TautOr t1 t2 => tautDenote t1 \/ tautDenote t2
| TautImp t1 t2 => tautDenote t1 -> tautDenote t2
end.
(**
(* It is easy to prove that every formula in the range of [tautDenote] is true. *)
[tautDenote]の範囲のすべての式が真であることを証明するのは簡単です。
*)
Theorem tautTrue : forall t, tautDenote t.
induction t; crush.
Qed.
(**
(* To use [tautTrue] to prove particular formulas, we need to implement the syntax reification process. A recursive Ltac function does the job. *)
特定の式を証明するために[tautTrue]を使用するには、
その構文を具象化する手順(reification process)を実装する必要があります。
再帰的なLtac関数がその仕事をします。
*)
Ltac tautReify P :=
match P with
| True => TautTrue
| ?P1 /\ ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautAnd t1 t2)
| ?P1 \/ ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautOr t1 t2)
| ?P1 -> ?P2 =>
let t1 := tautReify P1 in
let t2 := tautReify P2 in
constr:(TautImp t1 t2)
end.
(**
(* With [tautReify] available, it is easy to finish our reflective tactic. We look at the goal formula, reify it, and apply [tautTrue] to the reified formula. *)
[tautReify]が利用可能なので、
リフレクティブなタクティクを終わらせるのは簡単です。
ゴールの式を見て、それを具象化(reify)し、その具象化した式に[tautTrue]を適用します。
*)
Ltac obvious :=
match goal with
| [ |- ?P ] =>
let t := tautReify P in
exact (tautTrue t)
end.
(**
(* We can verify that [obvious] solves our original example, with a proof term that does not mention details of the proof. *)
証明項の詳細は言及せずに、
[obvious] がもとの例を解くことを証明することができます。
*)
(* end thide *)
Theorem true_galore' : (True /\ True) -> (True \/ (True /\ (True -> True))).
(* suhara:
intros.
let p := tautReify (True \/ True /\ (True -> True)) in pose p as t.
Check tautTrue t : tautDenote t.
exact (tautTrue t).
Restart.
*)
obvious.
Qed.
Print true_galore'.
(** %\vspace{-.15in}% [[
true_galore' =
tautTrue
(TautImp (TautAnd TautTrue TautTrue)
(TautOr TautTrue (TautAnd TautTrue (TautImp TautTrue TautTrue))))
: True /\ True -> True \/ True /\ (True -> True)
]]
(*
It is worth considering how the reflective tactic improves on a pure-Ltac implementation. The formula reification process is just as ad-hoc as before, so we gain little there. In general, proofs will be more complicated than formula translation, and the "generic proof rule" that we apply here _is_ on much better formal footing than a recursive Ltac function. The dependent type of the proof guarantees that it "works" on any input formula. This benefit is in addition to the proof-size improvement that we have already seen.
*)
純粋なLtacによる実装で、リフレクティブなタクティクがどのように改善するかを考える価値があります。
式の具象化の手順は以前と同じようにアドホックなので、
そこではほとんど利益を得ることはできません。
一般に、証明は数式の変換よりも複雑になります。
ここで適用する「一般的な証明の規則 (generic proof rule)」は、
再帰的なLtac関数よりもはるかに優れた正式な基礎に当てはまります。
依存型の証明は、どの入力式でも「機能する」ことを保証します。
この利点は、すでに見てきた、証明のサイズの改善に加えられます。
(*
It may also be worth pointing out that our previous example of evenness testing used a function [partialOut] for sound handling of input goals that the verified decision procedure fails to prove. Here, we prove that our procedure [tautTrue] (recall that an inductive proof may be viewed as a recursive procedure) is able to prove any goal representable in [taut], so no extra step is necessary. *)
以前の例の偶数性のテストでは、
検証された決定手続きが証明できない入力ゴールを
健全に処理する(sound handling)ために関数[partialOut]を使用していたことを指摘する価値があります。
ここで、手続き [tautTrue]
（帰納的証明は再帰的手続きと見なすことができることを思い出してください）
は、[taut]で表現できるどんなゴールをも証明できるので、余分なステップは必要ありません。
*)
(*
(** * A Monoid Expression Simplifier *)
*)
(** * モノイド式の簡略化 *)
(**
(* Proof by reflection does not require encoding of all of the syntax in a goal. We can insert "variables" in our syntax types to allow injection of arbitrary pieces, even if we cannot apply specialized reasoning to them. In this section, we explore that possibility by writing a tactic for normalizing monoid equations. *)
リフレクションによる証明では、ゴールの中のすべての構文をエンコードする必要はありません。
特殊な推論を適用できない場合でも、任意の断片が注入(injection)を許すために、
構文の型に「変数」を挿入することができます。
その可能性を、モノイドの等式(monoid equations)を正規化するための
タクティクを書くことによって探求します。
*)
Section monoid.
Variable A : Set.
Variable e : A.
Variable f : A -> A -> A.
Infix "+" := f.
Hypothesis assoc : forall a b c, (a + b) + c = a + (b + c).
Hypothesis identl : forall a, e + a = a.
Hypothesis identr : forall a, a + e = a.
(**
(* We add variables and hypotheses characterizing an arbitrary instance of the algebraic structure of monoids. We have an associative binary operator and an identity element for it.
*)
モノイドの代数構造の任意のインスタンスを特徴付ける変数と仮説を追加します。
結合法則を満たす(associative)2項演算子とそれに対する単位元があります。
(*
It is easy to define an expression tree type for monoid expressions. A [Var] constructor is a "catch-all" case for subexpressions that we cannot model. These subexpressions could be actual Gallina variables, or they could just use functions that our tactic is unable to understand. *)
モノイドの式についての木の型の式を定義するのは簡単です。
[Var]コンストラクタは、私たちがモデル化できない部分式の「キャッチ・オール」ケースです。
これらの部分式は、実際のGallina変数であるべきで、また、
私たちのタクティクが理解できない関数を使うことができます。
*)
(* begin thide *)
Inductive mexp : Set :=
| Ident : mexp
| Var : A -> mexp
| Op : mexp -> mexp -> mexp.
(**
(* Next, we write an interpretation function. *)
次に、翻訳関数(interpretation function)を書きます。
*)
Fixpoint mdenote (me : mexp) : A :=
match me with
| Ident => e
| Var v => v
| Op me1 me2 => mdenote me1 + mdenote me2
end.
(**
(* We will normalize expressions by flattening them into lists, via associativity, so it is helpful to have a denotation function for lists of monoid values. *)
結合法則を使って(via associativity)式をリストにフラット化(flattening)することで式を
正規化するので、モノイドの値のリストのための表示関数(denotation function)があると便利です。
*)
Fixpoint mldenote (ls : list A) : A :=
match ls with
| nil => e
| x :: ls' => x + mldenote ls'
end.
(**
(* The flattening function itself is easy to implement. *)
フラット化関数は、それ自体、実装するのに簡単です。
*)
Fixpoint flatten (me : mexp) : list A :=
match me with
| Ident => nil
| Var x => x :: nil
| Op me1 me2 => flatten me1 ++ flatten me2
end.
(**
(* This function has a straightforward correctness proof in terms of our [denote] functions. *)
この関数は、私たちの [表示(denote)] 関数に関して簡単な正当性証明を持っています。
*)
Lemma flatten_correct' : forall ml2 ml1,
mldenote ml1 + mldenote ml2 = mldenote (ml1 ++ ml2).
induction ml1; crush.
Qed.
Theorem flatten_correct : forall me, mdenote me = mldenote (flatten me).
Hint Resolve flatten_correct'.
induction me; crush.
Qed.
(**
(* Now it is easy to prove a theorem that will be the main tool behind our simplification tactic. *)
簡約化タクティクの主な道具となる定理を証明するのは簡単です。
*)
Theorem monoid_reflect : forall me1 me2,
mldenote (flatten me1) = mldenote (flatten me2)
-> mdenote me1 = mdenote me2.
intros; repeat rewrite flatten_correct; assumption.
Qed.
(**
(* We implement reification into the [mexp] type. *)
[mexp] 型への具象化を実装します。
*)
Ltac reify me :=
match me with
| e => Ident
| ?me1 + ?me2 =>
let r1 := reify me1 in
let r2 := reify me2 in
constr:(Op r1 r2)
| _ => constr:(Var me)
end.
(**
(* The final [monoid] tactic works on goals that equate two monoid terms. We reify each and change the goal to refer to the reified versions, finishing off by applying [monoid_reflect] and simplifying uses of [mldenote]. Recall that the %\index{tactics!change}%[change] tactic replaces a conclusion formula with another that is definitionally equal to it. *)
最終的な[monoid]タクティクは、モノイドの項のふたつからなる等式のゴールに作用します。
それぞれを具象化(reify)し、[monoid_reflect]を適用し、[mldenote]使って簡単化することで、
ゴールが具現化したバージョンを参照するように変更します。
%\index {tactics!change}%[change] タクティクは、
結論の式を定義として等しいものに置き換えることを思い出してください。
*)
Ltac monoid :=
match goal with
| [ |- ?me1 = ?me2 ] =>
let r1 := reify me1 in
let r2 := reify me2 in
change (mdenote r1 = mdenote r2);
apply monoid_reflect; simpl
end.
(**
(* We can make short work of theorems like this one: *)
このような定理の短い作業をすることができます：
*)
(* end thide *)
Theorem t1 : forall a b c d, a + b + c + d = a + (b + c) + d.
intros; monoid.
(** [[
============================
a + (b + (c + (d + e))) = a + (b + (c + (d + e)))
]]
(*
Our tactic has canonicalized both sides of the equality, such that we can finish the proof by reflexivity. *)
monoidタクティクは、等式の両辺を正準化(canonicalized)しているので、
反射性(reflexivity)によって証明を完成させることができます。
*)
reflexivity.
Qed.
(**
(* It is interesting to look at the form of the proof. *)
証明の形式(the form)を見るのは面白いです。
*)
Print t1.
(** %\vspace{-.15in}% [[
t1 =
fun a b c d : A =>
monoid_reflect (Op (Op (Op (Var a) (Var b)) (Var c)) (Var d))
(Op (Op (Var a) (Op (Var b) (Var c))) (Var d))
(eq_refl (a + (b + (c + (d + e)))))
: forall a b c d : A, a + b + c + d = a + (b + c) + d
]]
(*
The proof term contains only restatements of the equality operands in reified form, followed by a use of reflexivity on the shared canonical form. *)
証明項は、具現化された形式の等式のオペランドの再記述だけを含み、
共有された(shared)正準形(canonical form)への反射性の使用が続きます。
*)
End monoid.
(**
(* Extensions of this basic approach are used in the implementations of the %\index{tactics!ring}%[ring] and %\index{tactics!field}%[field] tactics that come packaged with Coq. *)
この基本的なアプローチの拡張は、Coqでパッケージ化された、
%\index{tactics!ring}%[ring] と %\index{tactics!field}%[field] タクティク
の実装で使われています。
*)
(*
(** * A Smarter Tautology Solver *)
*)
(** * 賢いトートロジー・ソルバー *)
(**
(* Now we are ready to revisit our earlier tautology solver example. We want to broaden the scope of the tactic to include formulas whose truth is not syntactically apparent. We will want to allow injection of arbitrary formulas, like we allowed arbitrary monoid expressions in the last example. Since we are working in a richer theory, it is important to be able to use equalities between different injected formulas. For instance, we cannot prove [P -> P] by translating the formula into a value like [Imp (Var P) (Var P)], because a Gallina function has no way of comparing the two [P]s for equality.
*)
これで、以前のトートロジー・ソルバーの例を再検討する準備が整いました。
私たちは、真理が構文的に明らかでない式を含むようにタクティクの範囲を広げたいと考えています。
最後の例で任意のモノイド式を許可したのと同じように、
任意の式の注入(injection)を許可したいと思うでしょう。
私たちはより豊かな理論で作業しているので、
注入された異なる式の間で等値を使用できることが重要です。
例えば、Gallina関数は、ふたつの[P]が等しいかどうかを比較する方法がないため、
式を[Imp (Var P) (Var P)]のような値に変換することによって[P -> P]を証明することはできません。
(* suhara: 「注入」 に単射(injection)の意味はあるか？
後で [Prop]から[Formula]への injection という。 *)
(*
To arrive at a nice implementation satisfying these criteria, we introduce the %\index{tactics!quote}%[quote] tactic and its associated library. *)
これらの基準を満たす素晴らしい実装に到達するために、
%\index{tactics!quote}%[quote]
タクティクとそれに関連するライブラリを紹介します。
*)
Require Import Quote.
(* begin thide *)
Inductive formula : Set :=
| Atomic : index -> formula (* suhara: 原始論理式 *)
| Truth : formula
| Falsehood : formula
| And : formula -> formula -> formula
| Or : formula -> formula -> formula
| Imp : formula -> formula -> formula.
(* end thide *)
(**
(* The type %\index{Gallina terms!index}%[index] comes from the [Quote] library and represents a countable variable type. The rest of [formula]'s definition should be old hat by now.
%\index{Gallina terms!index}%[index] 型は、[Quote]ライブラリからのものであり、
可算の変数の型を表します。
残りの[formula]の定義は、今のところ以前のまま(old hat)でなければなりません。
*)
(* The [quote] tactic will implement injection from [Prop] into [formula] for us, but it is not quite as smart as we might like. In particular, it wants to treat function types specially, so it gets confused if function types are part of the structure we want to encode syntactically. To trick [quote] into not noticing our uses of function types to express logical implication, we will need to declare a wrapper definition for implication, as we did in the last chapter. *)
[quote] タクティクは[Prop]から[Formula]への単射(injection)を実装しますが、
望むほどスマートではありません。
特に、関数型を特別に扱いたいので、
関数型が構文的に符号化したい構造体の一部であれば混乱(confused)します。
論理的な意味を表現するために関数型を使用することに気づかないように
[quote]することをトリックするには、
最後の章で行ったように、含意のラッパー定義を宣言する必要があります。
*)
Definition imp (P1 P2 : Prop) := P1 -> P2.
Infix "-->" := imp (no associativity, at level 95).
(**
(* Now we can define our denotation function. *)
ここでは、表示関数(denotation function)を定義することができます。
(* suhara: 翻訳関数 interpretation function とも呼ばれる。 see. tautDenote *)
*)
Definition asgn := varmap Prop. (* suhara: varmap は plugins/quote/Quote.v *)
(* begin thide *)
Fixpoint formulaDenote (atomics : asgn) (f : formula) : Prop :=
match f with
| Atomic v => varmap_find False v atomics
| Truth => True
| Falsehood => False
| And f1 f2 => formulaDenote atomics f1 /\ formulaDenote atomics f2
| Or f1 f2 => formulaDenote atomics f1 \/ formulaDenote atomics f2
| Imp f1 f2 => formulaDenote atomics f1 --> formulaDenote atomics f2
end.
(* end thide *)
(**
(* The %\index{Gallina terms!varmap}%[varmap] type family implements maps from [index] values. In this case, we define an assignment as a map from variables to [Prop]s. Our interpretation function [formulaDenote] works with an assignment, and we use the [varmap_find] function to consult the assignment in the [Atomic] case. The first argument to [varmap_find] is a default value, in case the variable is not found. *)
%\index{Gallina terms!varmap}%[varmap] のファミリーは、
[index] の値から map を実装します。
この場合、変数から [Prop] への map として代入を定義します。
翻訳関数(interpretation function) [formulaDenote]は代入として動作し、
[varmap_find]関数を使って[Atomic]の場合の代入を調べます。
[varmap_find]の最初の引数は、変数が見つからない場合のデフォルト値です。
*)
(* suhara: [varmap] ファミリーの使用例。
Print index.
(*
Inductive index : Set :=
| Left_idx : index -> index
| Right_idx : index -> index
| End_idx : index
*)
Print varmap.
(*
Inductive varmap (A : Type) : Type :=
| Empty_vm : varmap A
| Node_vm : A -> varmap A -> varmap A -> varmap A
*)
Variable ap0 : Prop.
Variable ap1 : Prop.
Variable ap2 : Prop.
Definition av0 := End_idx : index.
Definition av1 := Left_idx End_idx : index.
Definition av2 := Right_idx End_idx : index.
Definition av3 := Right_idx (Right_idx End_idx) : index.
Definition aas := (Node_vm ap0 (* End_idx *)
(Node_vm ap1 (* Left_idx End_idx *)
(Empty_vm Prop)
(Empty_vm Prop))
(Node_vm ap2 (* Right_idx End_idx *)
(Empty_vm Prop)
(Empty_vm Prop)))
: asgn.
Compute varmap_find False av0 aas. (* ap0 *)
Compute varmap_find False av1 aas. (* ap1 *)
Compute varmap_find False av2 aas. (* ap2 *)
Compute varmap_find False av3 aas. (* False *)
asgn は、変数とその値の対応（代入）である。あとで出てくる
環境を示す変数のリスト(set index)とは異なる。
*)
Section my_tauto.
Variable atomics : asgn.
Definition holds (v : index) := varmap_find False v atomics.
(**
(* We define some shorthand for a particular variable being true, and now we are ready to define some helpful functions based on the [ListSet] module of the standard library, which (unsurprisingly) presents a view of lists as sets. *)
特定の変数が真であるためにいくつかの省略形を定義し、
標準ライブラリの[ListSet]モジュールに基づいて、
（驚くことではありませんが）リストを集合として見ることを提供する、
便利な関数を定義する準備が整いました。
*)
Require Import ListSet. (* suhara: set_add の定義 *)
Definition index_eq : forall x y : index, {x = y} + {x <> y}.
decide equality.
Defined.
Definition add (s : set index) (v : index) := set_add index_eq v s.
(* suhara: 環境sに、変数vを追加する。 *)
Definition In_dec : forall v (s : set index), {In v s} + {~ In v s}.
Local Open Scope specif_scope.
intro; refine (fix F (s : set index) : {In v s} + {~ In v s} :=
match s with
| nil => No
| v' :: s' => index_eq v' v || F s'
end); crush.
Defined.
(**
(* We define what it means for all members of an index set to represent true propositions, and we prove some lemmas about this notion. *)
index の集合のすべてのメンバーに対して真となる命題を表わすもの
(* suhara: この場合はallTrue *)を定義し、
この表記についてのいくつかの補題を証明します。
*)
Fixpoint allTrue (s : set index) : Prop :=
match s with
| nil => True
| v :: s' => holds v /\ allTrue s'
end.
Theorem allTrue_add : forall v s,
allTrue s
-> holds v
-> allTrue (add s v).
induction s; crush;
match goal with
| [ |- context[if ?E then _ else _] ] => destruct E
end; crush.
Qed.
Theorem allTrue_In : forall v s,
allTrue s
-> set_In v s
-> varmap_find False v atomics.
induction s; crush.
Qed.
Hint Resolve allTrue_add allTrue_In.
Local Open Scope partial_scope.
(**
(* Now we can write a function [forward] that implements deconstruction of hypotheses, expanding a compound formula into a set of sets of atomic formulas covering all possible cases introduced with use of [Or]. To handle consideration of multiple cases, the function takes in a continuation argument, which will be called once for each case.
*)
ここで、仮説の分解(deconstruction)を実装する関数 [forward] を書くことができ、
複合式を、[Or]を使って導入された可能性のあるすべての場合(case)をカバーする
一連のアトミックな論理式の集合に
展開することができます。
(* suhara:
どこに展開されるのかよくわからない。
atomic formula と言っているけれど、
Or で並べられた論理式なので、原始論理式ではなく「節」と呼ぶべきであろう。
formula型で導入された Atomic とは異なる。
*)
複数のケースの考慮を処理するために、この関数は継続引数(continuation argument
(* suhara: 継続渡しの引数 *))を取ります。
これはそれぞれのケースに対して1回呼び出されます。
(*
The [forward] function has a dependent type, in the style of Chapter 6, guaranteeing correctness. The arguments to [forward] are a goal formula [f], a set [known] of atomic formulas that we may assume are true, a hypothesis formula [hyp], and a success continuation [cont] that we call when we have extended [known] to hold new truths implied by [hyp]. *)
[forward]関数は、第6章のスタイルで依存性の型を持ち、正確さを保証します。
[forward]のへの引数は、ゴールの式[f]、
真であると仮定してもよい原子式の集合[known]、
仮定の式[hyp]、
および、[hyp]によって含意される新しい真実を保持するために
[known] を拡張するときに呼び出す次への継続(success continuation) [cont] です。
*)
Definition forward : forall (f : formula) (known : set index) (hyp : formula)
(cont : forall known', [allTrue known' -> formulaDenote atomics f]),
[allTrue known -> formulaDenote atomics hyp -> formulaDenote atomics f].
refine (fix F (f : formula) (known : set index) (hyp : formula)
(cont : forall known', [allTrue known' -> formulaDenote atomics f])
: [allTrue known -> formulaDenote atomics hyp -> formulaDenote atomics f] :=
match hyp with
| Atomic v => Reduce (cont (add known v))
| Truth => Reduce (cont known)
| Falsehood => Yes
| And h1 h2 =>
Reduce (F (Imp h2 f) known h1 (fun known' =>
Reduce (F f known' h2 cont)))
| Or h1 h2 => F f known h1 cont && F f known h2 cont
| Imp _ _ => Reduce (cont known)
end); crush.
Defined.
(**
(* A [backward] function implements analysis of the final goal. It calls [forward] to handle implications. *)
[backward]関数は、最終のゴールの分析を実装します。
含意を扱うために[forward]を呼び出します。
*)
(* begin thide *)
Definition backward : forall (known : set index) (f : formula),
[allTrue known -> formulaDenote atomics f].
refine (fix F (known : set index) (f : formula)
: [allTrue known -> formulaDenote atomics f] :=
match f with
| Atomic v => Reduce (In_dec v known)
| Truth => Yes
| Falsehood => No
| And f1 f2 => F known f1 && F known f2
| Or f1 f2 => F known f1 || F known f2
| Imp f1 f2 => forward f2 known f1 (fun known' => F known' f2)
end); crush; eauto.
Defined.
(* end thide *)
(**
(* A simple wrapper around [backward] gives us the usual type of a partial decision procedure. *)
[backward]の周りの単純なラッパーは、部分的な決定のための手続きの通常のタイプを与えます。
(* suhara: partial は部分関数だが、decision は決定性ではないと思う *)
*)
Definition my_tauto : forall f : formula, [formulaDenote atomics f].
(* begin thide *)
intro; refine (Reduce (backward nil f)); crush.
Defined.
(* end thide *)
End my_tauto.
(**
(* Our final tactic implementation is now fairly straightforward. First, we [intro] all quantifiers that do not bind [Prop]s. Then we call the [quote] tactic, which implements the reification for us. Finally, we are able to construct an exact proof via [partialOut] and the [my_tauto] Gallina function. *)
最終的なタクティクの実装はかなり簡単です。
まず、[Prop] の束縛しないすべての量化子を [intro] します。
次に、具象化を実装する[quote]タクティクを呼び出します。
最後に、[partialOut]と[my_tauto] のGallina関数を使用して正確な証明を構築します。
(* suhara: exact の中のmy_tautoは、関数呼び出し。 *)
*)
Ltac my_tauto :=
repeat match goal with
| [ |- forall x : ?P, _ ] =>
match type of P with
| Prop => fail 1 (* suhara: 2階論理は扱わない？ *)
| _ => intro
end
end;
quote formulaDenote;
match goal with
| [ |- formulaDenote ?m ?f ] => exact (partialOut (my_tauto m f))
end.
(* end thide *)
(**
(* A few examples demonstrate how the tactic works. *)
いくつかの例は、タクティクがどのように機能するかを示しています。
*)
Theorem mt1 : True.
my_tauto.
Qed.
Print mt1.
(** %\vspace{-.15in}% [[
mt1 = partialOut (my_tauto (Empty_vm Prop) Truth)
: True
]]
(*
We see [my_tauto] applied with an empty [varmap], since every subformula is handled by [formulaDenote]. *)
すべての部分式は[formulaDenote]によって処理されるため、
[my_tauto]に空の[varmap] (* suhara: (Empty_vm Prop) *) が適用されていることがわかります。
*)
(* suhara:
Compute my_tauto (Empty_vm Prop) Truth. (* YES *)
*)
Theorem mt2 : forall x y : nat, x = y --> x = y.
my_tauto.
Qed.
(* suhara: nvm はなんのためにあるのか？ *)
(* begin hide *)
(* begin thide *)
Definition nvm := (Node_vm, Empty_vm, End_idx, Left_idx, Right_idx).
(* end thide *)
(* end hide *)
Print mt2.
(** %\vspace{-.15in}% [[
mt2 =
fun x y : nat =>
partialOut
(my_tauto (Node_vm (x = y) (Empty_vm Prop) (Empty_vm Prop))
(Imp (Atomic End_idx) (Atomic End_idx)))
: forall x y : nat, x = y --> x = y
]]
(*
Crucially, both instances of [x = y] are represented with the same index, [End_idx]. The value of this index only needs to appear once in the [varmap], whose form reveals that [varmap]s are represented as binary trees, where [index] values denote paths from tree roots to leaves. *)
重要なことに、[x = y]の両方のインスタンスは同じインデックス[End_idx]で表されます。
このインデックスの値は[varmap]に1回だけ現れなければならず、
[varmap]は、
[index] の値が木の根から葉までのパスを示す、
二進木(binary trees) として表現されます。
*)
(*
Variables x y : nat.
Compute (my_tauto (Node_vm (x = y) (Empty_vm Prop) (Empty_vm Prop))
(Imp (Atomic End_idx) (Atomic End_idx))). (* YES *)
*)
Theorem mt3 : forall x y z,
(x < y /\ y > z) \/ (y > z /\ x < S y)
--> y > z /\ (x < y \/ x < S y).
my_tauto.
Qed.
Print mt3.
(** %\vspace{-.15in}% [[
fun x y z : nat =>
partialOut
(my_tauto
(Node_vm (x < S y) (Node_vm (x < y) (Empty_vm Prop) (Empty_vm Prop))
(Node_vm (y > z) (Empty_vm Prop) (Empty_vm Prop)))
(Imp
(Or (And (Atomic (Left_idx End_idx)) (Atomic (Right_idx End_idx)))
(And (Atomic (Right_idx End_idx)) (Atomic End_idx)))
(And (Atomic (Right_idx End_idx))
(Or (Atomic (Left_idx End_idx)) (Atomic End_idx)))))
: forall x y z : nat,
x < y /\ y > z \/ y > z /\ x < S y --> y > z /\ (x < y \/ x < S y)
]]
(*
Our goal contained three distinct atomic formulas, and we see that a three-element [varmap] is generated.
*)
ゴールにはみっつの異なる原子式が含まれていて、
3要素の「varmap」が生成されていることがわかります。
(*
It can be interesting to observe differences between the level of repetition in proof terms generated by [my_tauto] and [tauto] for especially trivial theorems. *)
特に自明な定理のために[my_tauto]と[tauto]によって生成される証明項の反復の
レベルの違いを観察することは面白いかもしれません。
*)
Theorem mt4 : True /\ True /\ True /\ True /\ True /\ True /\ False --> False.
my_tauto.
Qed.
Print mt4.
(** %\vspace{-.15in}% [[
mt4 =
partialOut
(my_tauto (Empty_vm Prop)
(Imp
(And Truth
(And Truth
(And Truth (And Truth (And Truth (And Truth Falsehood))))))
Falsehood))
: True /\ True /\ True /\ True /\ True /\ True /\ False --> False
]]
*)
Theorem mt4' : True /\ True /\ True /\ True /\ True /\ True /\ False -> False.
tauto.
Qed.
(* suhara: これも必要か？ *)
(* begin hide *)
(* begin thide *)
Definition fi := False_ind.
(* end thide *)
(* end hide *)
Print mt4'.
(** %\vspace{-.15in}% [[
mt4' =
fun H : True /\ True /\ True /\ True /\ True /\ True /\ False =>
and_ind
(fun (_ : True) (H1 : True /\ True /\ True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H3 : True /\ True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H5 : True /\ True /\ True /\ False) =>
and_ind
(fun (_ : True) (H7 : True /\ True /\ False) =>
and_ind
(fun (_ : True) (H9 : True /\ False) =>
and_ind (fun (_ : True) (H11 : False) => False_ind False H11)
H9) H7) H5) H3) H1) H
: True /\ True /\ True /\ True /\ True /\ True /\ False -> False
]]
(*
The traditional [tauto] tactic introduces a quadratic blow-up in the size of the proof term, whereas proofs produced by [my_tauto] always have linear size. *)
伝統的な[tauto]タクティクは、
証明項のサイズの2次(quadratic)的な「爆発(blow-up)」を導入するのに対し、(* suhara: O(n2) *)
[my_tauto]によって生成される証明は常に線形の大きさを持ちます。(* suhara: O(n) *)
*)
(*
(** ** Manual Reification of Terms with Variables *)
*)
(** ** 変数を持つ項の手動の具象化 *)
(* begin thide *)
(**
(* The action of the [quote] tactic above may seem like magic. Somehow it performs equality comparison between subterms of arbitrary types, so that these subterms may be represented with the same reified variable. While [quote] is implemented in OCaml, we can code the reification process completely in Ltac, as well. To make our job simpler, we will represent variables as [nat]s, indexing into a simple list of variable values that may be referenced.
*)
上記の[quote] タクティクの動作は手品のように見えます。
どういうわけか、それは任意の型の副項(subterms)どうしが等しいかどうかの比較(equality comparison)
を実行するので、これらの副項は同じ具象化された(reified)変数でされるでしょう。
[quote]はOCamlで実装されていますが、具象化のプロセス(reification process)
をLtacで完全にコードすることができます。
仕事をより簡単にするために、変数を[nat]として表現し、
参照される変数の値からなる単純なリストにインデックスを付けます。
(* suhara: 変数を表現する[nat]のインデックスでリストを参照することで、値を得る。
これに対して、[varmap]ファミリは、二分木を使っていた。 *)
(*
Step one of the process is to crawl over a term, building a duplicate-free list of all values that appear in positions we will encode as variables. A useful helper function adds an element to a list, preventing duplicates. Note how we use Ltac pattern matching to implement an equality test on Gallina terms; this is simple syntactic equality, not even the richer definitional equality. We also represent lists as nested tuples, to allow different list elements to have different Gallina types. *)
プロセスの最初のステップは、項をクロールし、
エンコードする位置に表示されるすべての値の重複のないリストを変数として構築することです。
便利な補助関数(helper function)は、重複を防止ながら、要素をリストに追加ます。
Ltacのパターンマッチングを使用してGallina項についての等値のテスト
(equality test)を実装する方法に注意してください。
これは単純な文法的な等値(syntactic equality)であり、
より豊かな定義による等値(definitional equality)ではありません。
また、異なるリストの要素が異なるGallinaに型を持つことを可能にするために、
ネストされたタプルとしてリストを表現します。
*)
Ltac inList x xs :=
match xs with
| tt => false
| (x, _) => true
| (_, ?xs') => inList x xs'
end.
Ltac addToList x xs :=
let b := inList x xs in
match b with
| true => xs
| false => constr:((x, xs))
end.
(**
(* Now we can write our recursive function to calculate the list of variable values we will want to use to represent a term. *)
ここで、項を表すために使用する変数値のリストを計算する再帰関数を書くことができます。
*)
Ltac allVars xs e :=
match e with
| True => xs
| False => xs
| ?e1 /\ ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| ?e1 \/ ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| ?e1 -> ?e2 =>
let xs := allVars xs e1 in
allVars xs e2
| _ => addToList e xs
end.
(**
(* We will also need a way to map a value to its position in a list. *)
値をリストの内の位置にマップする方法も必要です。
*)
Ltac lookup x xs :=
match xs with
| (x, _) => O
| (_, ?xs') =>
let n := lookup x xs' in
constr:(S n)
end.
(**
(* The next building block is a procedure for reifying a term, given a list of all allowed variable values. We are free to make this procedure partial, where tactic failure may be triggered upon attempting to reify a term containing subterms not included in the list of variables. The type of the output term is a copy of [formula] where [index] is replaced by [nat], in the type of the constructor for atomic formulas. *)
次の構成要素(building block)は、許可されたすべての変数値のリストを指定して、
項を具象化する手順です。
変数のリストに含まれていない副項(subterm)を含む項の具象化を試みると、
タクティクの失敗が引き起こされる可能性があるため、
この手続きは部分的(partial)になります(free to make this procedure partial)。
出力項の型は、[index]が[nat]に置き換えられた[formula]のコピーで、
アトミックな式のコンストラクタの型です。
*)
Inductive formula' : Set :=
| Atomic' : nat -> formula'
| Truth' : formula'
| Falsehood' : formula'
| And' : formula' -> formula' -> formula'
| Or' : formula' -> formula' -> formula'
| Imp' : formula' -> formula' -> formula'.
(**
(* Note that, when we write our own Ltac procedure, we can work directly with the normal [->] operator, rather than needing to introduce a wrapper for it. *)
私たち自身のLtac手続きを書くときは、ラッパーを導入する必要はなく、
通常の[->]演算子で直接作業することができます。
(* suhara: quote のためには --> が必要だったが、ここでは不要である *)
*)
Ltac reifyTerm xs e :=
match e with
| True => Truth'
| False => Falsehood'
| ?e1 /\ ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(And' p1 p2)
| ?e1 \/ ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(Or' p1 p2)
| ?e1 -> ?e2 =>
let p1 := reifyTerm xs e1 in
let p2 := reifyTerm xs e2 in
constr:(Imp' p1 p2)
| _ =>
let n := lookup e xs in
constr:(Atomic' n)
end.
(**
(* Finally, we bring all the pieces together. *)
最後に、すべての作品をまとめています。
*)
Ltac reify :=
match goal with
| [ |- ?G ] => let xs := allVars tt G in
let p := reifyTerm xs G in
pose p
end.
(**
(* A quick test verifies that we are doing reification correctly. *)
クイックテストは、私たちが正しく具象化(reification)を行っていることを検証します。
*)
Theorem mt3' : forall x y z,
(x < y /\ y > z) \/ (y > z /\ x < S y)
-> y > z /\ (x < y \/ x < S y).
do 3 intro; reify.
(**
(* Our simple tactic adds the translated term as a new variable:
*)
私たちの簡単なタクティクは、変換された項を新しい変数として追加します：
[[
f := Imp'
(Or' (And' (Atomic' 2) (Atomic' 1)) (And' (Atomic' 1) (Atomic' 0)))
(And' (Atomic' 1) (Or' (Atomic' 2) (Atomic' 0))) : formula'
]]
*)
Abort.
(**
(* More work would be needed to complete the reflective tactic, as we must connect our new syntax type with the real meanings of formulas, but the details are the same as in our prior implementation with [quote]. *)
新しい構文型と式の実際の意味を結びつけなければならないので、
リフレクティブなタクティクを完成させるためにはもっと多くの作業が必要ですが、
詳細は以前の[quote]による実装と同じです。
*)
(* end thide *)
(* suhara: quote をみなおす。
Theorem mt3'' : forall x y z,
(x < y /\ y > z) \/ (y > z /\ x < S y)
--> y > z /\ (x < y \/ x < S y).
intros.
quote formulaDenote.
(* ここまででは、my_tauto, backward, forward は不要である。 *)
(* 奇妙なのは、formulaDenote が、formulaからPropの関数であるのに、
ここでは、Prop から formula へ変換していることである。 *)
Abort.
Coq manual から：
10.3 quote
The tactic quote allows using Barendregt's so-called 2-level approach
without writing any ML code. Suppose you have a language L of
'abstract terms' and a type A of 'concrete terms' and a function f : L-> A.
If L is a simple inductive datatype and f a simple fixpoint,
quote f will replace the head of current goal by a convertible term of
the form (f t). L must have a constructor of type: A -> L.
抽象的な項Lから具体的な項A への関数 f : L->A があり、
Lが帰納型で、fが再帰関数なら、quote f は、現在のゴールを(f t)から変換する。
Lは、A->L型のコンストラクタが必要である。
つまり、formulaDenote : formula -> Prop に対して、
quote formulaDenote は、ゴールに対して、Prop -> formula を実行する。
これに対して、reify は ゴールに対して、直接、Prop -> formula をおこなうタクティクである。
*)
(*
(** * Building a Reification Tactic that Recurses Under Binders *)
*)
(** * 束縛のもとで再帰する具象化タクティクを作る *)
(**
(* All of our examples so far have stayed away from reifying the syntax of terms that use such features as quantifiers and [fun] function abstractions. Such cases are complicated by the fact that different subterms may be allowed to reference different sets of free variables. Some cleverness is needed to clear this hurdle, but a few simple patterns will suffice. Consider this example of a simple dependently typed term language, where a function abstraction body is represented conveniently with a Coq function. *)
これまでのすべての例では、量化子や、[fun]による関数抽象などの項の構文を具現化する形式
から離れていました。
そのような場合は、
異なる副項が自由変数の異なる集合を参照することを許されるという事実によって複雑になります。
このようなハードルを解消するためにはいくつかの巧妙さが必要ですが、
すこしの単純なパターンで十分です。
関数抽象の本体が便利にCoqの関数で表されている単純な依存型の言語の例を考えてみましょう。
*)
Inductive type : Type :=
| Nat : type
| NatFunc : type -> type.
Inductive term : type -> Type :=
| Const : nat -> term Nat
| Plus : term Nat -> term Nat -> term Nat
| Abs : forall t, (nat -> term t) -> term (NatFunc t).
Fixpoint typeDenote (t : type) : Type :=
match t with
| Nat => nat
| NatFunc t => nat -> typeDenote t
end.
Fixpoint termDenote t (e : term t) : typeDenote t :=
match e with
| Const n => n
| Plus e1 e2 => termDenote e1 + termDenote e2
| Abs _ e1 => fun x => termDenote (e1 x)
end.
(**
(* Here is a %\%naive%{}% first attempt at a reification tactic. *)
ここでは、具象化のタクティクで素朴(%\%naive%{}%)な最初の試みがあります。
*)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac refl' e :=
match e with
| ?E1 + ?E2 =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(Plus r1 r2)
| fun x : nat => ?E1 =>
let r1 := refl' E1 in
constr:(Abs (fun x => r1 x))
| _ => constr:(Const e)
end.
(**
(* Recall that a regular Ltac pattern variable [?X] only matches terms that _do not mention new variables introduced within the pattern_. In our %\%naive%{}% implementation, the case for matching function abstractions matches the function body in a way that prevents it from mentioning the function argument! Our code above plays fast and loose with the function body in a way that leads to independent problems, but we could change the code so that it indeed handles function abstractions that ignore their arguments.
正規のLtacのパターン変数[?X]は、
＿パターン内に導入された新しい変数について言及していない項＿
にのみマッチすることを想起してください。
(* suhara: fun x => ?E1 と fun a => F a はマッチしない。E1 = F a にならない。
ここでいう新しく導入された変数とは、a にあたる *)
素朴(%\%naive%{}%)な実装では、
関数の引数に言及することを妨げる方法です！
上記のコードは、独立した問題を引き起こすような方法で、
関数本体を高速かつ緩やかに実行しますが、コードを変更して、
引数を無視する関数抽象を実際に処理できるようにします。
*)
(*
To handle functions in general, we will use the pattern variable form [@?X], which allows [X] to mention newly introduced variables that are declared explicitly. A use of [@?X] must be followed by a list of the local variables that may be mentioned. The variable [X] then comes to stand for a Gallina function over the values of those variables. For instance: *)
関数を一般的に扱うために、パターンの変数の形式 [@?X]を使用して、
明示的に宣言された新しく導入された変数について[X]が言及するようにします。
[@?X]の使用のあとには、言及する可能性のあるローカル変数のリストを続ける必要があります。
(* suhara: fun x => @?E1 x と fun a => F a はマッチする。E1 = F になる。 *)
変数[X]は、それらの変数の値に渡ってGallina関数を表します。 例えば：
*)
Reset refl'.
(* begin hide *)
Reset red_herring.
Definition red_herring := O.
(* end hide *)
Ltac refl' e :=
match e with
| ?E1 + ?E2 =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(Plus r1 r2)
| fun x : nat => @?E1 x => (* suhara: @をつける。 *)
let r1 := refl' E1 in
constr:(Abs r1)
| _ => constr:(Const e)
end.
(**
(* Now, in the abstraction case, we bind [E1] as a function from an [x] value to the value of the abstraction body. Unfortunately, our recursive call there is not destined for success. It will match the same abstraction pattern and trigger another recursive call, and so on through infinite recursion. One last refactoring yields a working procedure. The key idea is to consider every input to [refl'] as _a function over the values of variables introduced during recursion_. *)
抽象化の場合[E1]を、[x]の値から抽象化した本体の値への関数に、束縛します。
残念ながら、再帰呼び出しは成功すると決まったわけではありません。
同じ抽象パターンに一致し、別の再帰呼び出しを実行するなど、無限再帰を使用します。
最後の具象化によって作業手順が得られます。
重要なアイデアは、[refl']へのすべての入力を
＿再帰中に導入された変数の値に対する関数＿ として考えることです。
*)
Reset refl'.
(* begin hide *)
Reset red_herring.
(* end hide *)
Ltac refl' e :=
match eval simpl in e with
| fun x : ?T => @?E1 x + @?E2 x =>
let r1 := refl' E1 in
let r2 := refl' E2 in
constr:(fun x => Plus (r1 x) (r2 x)) (* suhara: 返値を関数にする。 *)
| fun (x : ?T) (y : nat) => @?E1 x y =>
let r1 := refl' (fun p : T * nat => E1 (fst p) (snd p)) in
constr:(fun u => Abs (fun v => r1 (u, v))) (* suhara: 返値を関数にする。 *)
| _ => constr:(fun x => Const (e x)) (* suhara: 返値を関数にする。 *)
end.
(**
(* Note how now even the addition case works in terms of functions, with [@?X] patterns. The abstraction case introduces a new variable by extending the type used to represent the free variables. In particular, the argument to [refl'] used type [T] to represent all free variables. We extend the type to [T * nat] for the type representing free variable values within the abstraction body. A bit of bookkeeping with pairs and their projections produces an appropriate version of the abstraction body to pass in a recursive call. To ensure that all this repackaging of terms does not interfere with pattern matching, we add an extra [simpl] reduction on the function argument, in the first line of the body of [refl'].
*)
[@?X]のパターンでは、関数の形で加算の場合でもどのように動作するのか注意してください。
抽象化の場合、自由変数を表すために使用される型を拡張することによって新しい変数が導入されます。
すべての自由変数を表すために[T]型を使用しました。
抽象化の本体内の自由変数値を表す型の型を[T * nat]に拡張します。
ペアとその射影(projection)による
少しのブックキーピング(a bit of bookkeeping)は、
再帰呼び出しで渡す抽象本体の適切なバージョンを生成します。
このような項の再パッケージングがすべてパターンマッチングを妨げないようにするために、
[refl']の本体の最初の行に関数引数を追加します。
(*
Now one more tactic provides an example of how to apply reification. Let us consider goals that are equalities between terms that can be reified. We want to change such goals into equalities between appropriate calls to [termDenote]. *)
今やもうひとつのタクティクが、具象化を適用する方法の例を提供します。
具象化できる項どうしの等式であるゴールを考えてみましょう。
このようなゴールを[termDenote]への適切な呼び出しの間で等式に変更したいと考えています。
*)
Ltac refl :=
match goal with
| [ |- ?E1 = ?E2 ] =>
let E1' := refl' (fun _ : unit => E1) in
let E2' := refl' (fun _ : unit => E2) in
change (termDenote (E1' tt) = termDenote (E2' tt));
cbv beta iota delta [fst snd]
end.
Goal (fun (x y : nat) => x + y + 13) = (fun (_ z : nat) => z).
refl.
(** %\vspace{-.15in}%[[
============================
termDenote
(Abs
(fun y : nat =>
Abs (fun y0 : nat => Plus (Plus (Const y) (Const y0)) (Const 13)))) =
termDenote (Abs (fun _ : nat => Abs (fun y0 : nat => Const y0)))
]]
*)
Abort.
(**
(* Our encoding here uses Coq functions to represent binding within the terms we reify, which makes it difficult to implement certain functions over reified terms. An alternative would be to represent variables with numbers. This can be done by writing a slightly smarter reification function that identifies variable references by detecting when term arguments are just compositions of [fst] and [snd]; from the order of the compositions we may read off the variable number. We leave the details as an exercise (though not a trivial one!) for the reader. *)
ここでのエンコーディングは、Coqの関数を使用して、妥当な条件で束縛を表現しているため、
特定の関数機能を実現するのが難しくなります。
また、変数を数値で表現する方法もあります。
これは、項の引数が[fst]と[snd]の合成だけであることを検出することによって、
変数参照を識別する若干スマートな具象化関数を書くことによって行うことができます。
構成の順序から、変数の数値を読み取ることができます。
読者のために詳細を練習問題（しかし、自明なものではありません！）として残しています。
*)
(* END *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DLRBP_FUNCTIONAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_ms__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_ms__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_FUNCTIONAL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Wed Jul 16 10:16:52 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:14 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.19 2003/07/09 07:52:44 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
'timescale 1ns / 1ns;
//
//
// Start of Generated Module rtl of ent_ba
//
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Tue Jul 22 11:18:49 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:14 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.21 2003/07/17 12:10:43 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps;
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Tue Aug 12 16:53:17 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:14 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.24 2003/08/11 07:16:25 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Mon Sep 8 17:52:50 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:14 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Wed Oct 8 09:51:06 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:14 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Wed Oct 8 10:24:03 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:14 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Mon Oct 13 09:32:34 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:14 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Thu Nov 6 15:57:35 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:14 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.17 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Fri Jul 15 12:55:13 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// nios_solo.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_solo (
input wire clk_clk, // clk.clk
input wire dummy_export, // dummy.export
input wire io_ack, // io.ack
input wire [7:0] io_rdata, // .rdata
output wire io_read, // .read
output wire [7:0] io_wdata, // .wdata
output wire io_write, // .write
output wire [19:0] io_address, // .address
input wire io_irq, // .irq
input wire io_u2p_ack, // io_u2p.ack
input wire [7:0] io_u2p_rdata, // .rdata
output wire io_u2p_read, // .read
output wire [7:0] io_u2p_wdata, // .wdata
output wire io_u2p_write, // .write
output wire [19:0] io_u2p_address, // .address
input wire io_u2p_irq, // .irq
output wire [25:0] mem_mem_req_address, // mem.mem_req_address
output wire [3:0] mem_mem_req_byte_en, // .mem_req_byte_en
output wire mem_mem_req_read_writen, // .mem_req_read_writen
output wire mem_mem_req_request, // .mem_req_request
output wire [7:0] mem_mem_req_tag, // .mem_req_tag
output wire [31:0] mem_mem_req_wdata, // .mem_req_wdata
input wire [7:0] mem_mem_resp_dack_tag, // .mem_resp_dack_tag
input wire [31:0] mem_mem_resp_data, // .mem_resp_data
input wire [7:0] mem_mem_resp_rack_tag, // .mem_resp_rack_tag
input wire reset_reset_n // reset.reset_n
);
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [31:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [29:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire [7:0] mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata; // io_bridge_0:avs_readdata -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdata
wire mm_interconnect_0_io_bridge_0_avalon_slave_0_waitrequest; // io_bridge_0:avs_ready -> mm_interconnect_0:io_bridge_0_avalon_slave_0_waitrequest
wire [19:0] mm_interconnect_0_io_bridge_0_avalon_slave_0_address; // mm_interconnect_0:io_bridge_0_avalon_slave_0_address -> io_bridge_0:avs_address
wire mm_interconnect_0_io_bridge_0_avalon_slave_0_read; // mm_interconnect_0:io_bridge_0_avalon_slave_0_read -> io_bridge_0:avs_read
wire mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid; // io_bridge_0:avs_readdatavalid -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdatavalid
wire mm_interconnect_0_io_bridge_0_avalon_slave_0_write; // mm_interconnect_0:io_bridge_0_avalon_slave_0_write -> io_bridge_0:avs_write
wire [7:0] mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata; // mm_interconnect_0:io_bridge_0_avalon_slave_0_writedata -> io_bridge_0:avs_writedata
wire [7:0] mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata; // io_bridge_1:avs_readdata -> mm_interconnect_0:io_bridge_1_avalon_slave_0_readdata
wire mm_interconnect_0_io_bridge_1_avalon_slave_0_waitrequest; // io_bridge_1:avs_ready -> mm_interconnect_0:io_bridge_1_avalon_slave_0_waitrequest
wire [19:0] mm_interconnect_0_io_bridge_1_avalon_slave_0_address; // mm_interconnect_0:io_bridge_1_avalon_slave_0_address -> io_bridge_1:avs_address
wire mm_interconnect_0_io_bridge_1_avalon_slave_0_read; // mm_interconnect_0:io_bridge_1_avalon_slave_0_read -> io_bridge_1:avs_read
wire mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid; // io_bridge_1:avs_readdatavalid -> mm_interconnect_0:io_bridge_1_avalon_slave_0_readdatavalid
wire mm_interconnect_0_io_bridge_1_avalon_slave_0_write; // mm_interconnect_0:io_bridge_1_avalon_slave_0_write -> io_bridge_1:avs_write
wire [7:0] mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata; // mm_interconnect_0:io_bridge_1_avalon_slave_0_writedata -> io_bridge_1:avs_writedata
wire [31:0] mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata; // avalon2mem_0:avs_readdata -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_readdata
wire mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest; // avalon2mem_0:avs_waitrequest -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_waitrequest
wire [25:0] mm_interconnect_0_avalon2mem_0_avalon_slave_0_address; // mm_interconnect_0:avalon2mem_0_avalon_slave_0_address -> avalon2mem_0:avs_address
wire mm_interconnect_0_avalon2mem_0_avalon_slave_0_read; // mm_interconnect_0:avalon2mem_0_avalon_slave_0_read -> avalon2mem_0:avs_read
wire [3:0] mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable; // mm_interconnect_0:avalon2mem_0_avalon_slave_0_byteenable -> avalon2mem_0:avs_byteenable
wire mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid; // avalon2mem_0:avs_readdatavalid -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_readdatavalid
wire mm_interconnect_0_avalon2mem_0_avalon_slave_0_write; // mm_interconnect_0:avalon2mem_0_avalon_slave_0_write -> avalon2mem_0:avs_write
wire [31:0] mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata; // mm_interconnect_0:avalon2mem_0_avalon_slave_0_writedata -> avalon2mem_0:avs_writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [8:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire irq_mapper_receiver0_irq; // io_bridge_0:avs_irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // io_bridge_1:avs_irq -> irq_mapper:receiver1_irq
wire irq_mapper_receiver2_irq; // pio_0:irq -> irq_mapper:receiver2_irq
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [avalon2mem_0:reset, io_bridge_0:reset, io_bridge_1:reset, irq_mapper:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, onchip_memory2_0:reset, pio_0:reset_n, rst_translator:in_reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
avalon_to_mem32_bridge #(
.g_tag (8'b01011011)
) avalon2mem_0 (
.reset (rst_controller_reset_out_reset), // reset.reset
.avs_read (mm_interconnect_0_avalon2mem_0_avalon_slave_0_read), // avalon_slave_0.read
.avs_write (mm_interconnect_0_avalon2mem_0_avalon_slave_0_write), // .write
.avs_address (mm_interconnect_0_avalon2mem_0_avalon_slave_0_address), // .address
.avs_writedata (mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata), // .writedata
.avs_byteenable (mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable), // .byteenable
.avs_waitrequest (mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest), // .waitrequest
.avs_readdata (mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata), // .readdata
.avs_readdatavalid (mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid), // .readdatavalid
.clock (clk_clk), // clock.clk
.mem_req_address (mem_mem_req_address), // mem.mem_req_address
.mem_req_byte_en (mem_mem_req_byte_en), // .mem_req_byte_en
.mem_req_read_writen (mem_mem_req_read_writen), // .mem_req_read_writen
.mem_req_request (mem_mem_req_request), // .mem_req_request
.mem_req_tag (mem_mem_req_tag), // .mem_req_tag
.mem_req_wdata (mem_mem_req_wdata), // .mem_req_wdata
.mem_resp_dack_tag (mem_mem_resp_dack_tag), // .mem_resp_dack_tag
.mem_resp_data (mem_mem_resp_data), // .mem_resp_data
.mem_resp_rack_tag (mem_mem_resp_rack_tag) // .mem_resp_rack_tag
);
avalon_to_io_bridge io_bridge_0 (
.reset (rst_controller_reset_out_reset), // reset.reset
.avs_read (mm_interconnect_0_io_bridge_0_avalon_slave_0_read), // avalon_slave_0.read
.avs_write (mm_interconnect_0_io_bridge_0_avalon_slave_0_write), // .write
.avs_address (mm_interconnect_0_io_bridge_0_avalon_slave_0_address), // .address
.avs_writedata (mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata), // .writedata
.avs_ready (mm_interconnect_0_io_bridge_0_avalon_slave_0_waitrequest), // .waitrequest_n
.avs_readdata (mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata), // .readdata
.avs_readdatavalid (mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid), // .readdatavalid
.clock (clk_clk), // clock.clk
.io_ack (io_ack), // io.ack
.io_rdata (io_rdata), // .rdata
.io_read (io_read), // .read
.io_wdata (io_wdata), // .wdata
.io_write (io_write), // .write
.io_address (io_address), // .address
.io_irq (io_irq), // .irq
.avs_irq (irq_mapper_receiver0_irq) // irq.irq
);
avalon_to_io_bridge io_bridge_1 (
.reset (rst_controller_reset_out_reset), // reset.reset
.avs_read (mm_interconnect_0_io_bridge_1_avalon_slave_0_read), // avalon_slave_0.read
.avs_write (mm_interconnect_0_io_bridge_1_avalon_slave_0_write), // .write
.avs_address (mm_interconnect_0_io_bridge_1_avalon_slave_0_address), // .address
.avs_writedata (mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata), // .writedata
.avs_ready (mm_interconnect_0_io_bridge_1_avalon_slave_0_waitrequest), // .waitrequest_n
.avs_readdata (mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata), // .readdata
.avs_readdatavalid (mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid), // .readdatavalid
.clock (clk_clk), // clock.clk
.io_ack (io_u2p_ack), // io.ack
.io_rdata (io_u2p_rdata), // .rdata
.io_read (io_u2p_read), // .read
.io_wdata (io_u2p_wdata), // .wdata
.io_write (io_u2p_write), // .write
.io_address (io_u2p_address), // .address
.io_irq (io_u2p_irq), // .irq
.avs_irq (irq_mapper_receiver1_irq) // irq.irq
);
nios_solo_nios2_gen2_0 nios2_gen2_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
nios_solo_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
nios_solo_pio_0 pio_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.in_port (dummy_export), // external_connection.export
.irq (irq_mapper_receiver2_irq) // irq.irq
);
nios_solo_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.avalon2mem_0_avalon_slave_0_address (mm_interconnect_0_avalon2mem_0_avalon_slave_0_address), // avalon2mem_0_avalon_slave_0.address
.avalon2mem_0_avalon_slave_0_write (mm_interconnect_0_avalon2mem_0_avalon_slave_0_write), // .write
.avalon2mem_0_avalon_slave_0_read (mm_interconnect_0_avalon2mem_0_avalon_slave_0_read), // .read
.avalon2mem_0_avalon_slave_0_readdata (mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata), // .readdata
.avalon2mem_0_avalon_slave_0_writedata (mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata), // .writedata
.avalon2mem_0_avalon_slave_0_byteenable (mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable), // .byteenable
.avalon2mem_0_avalon_slave_0_readdatavalid (mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid), // .readdatavalid
.avalon2mem_0_avalon_slave_0_waitrequest (mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest), // .waitrequest
.io_bridge_0_avalon_slave_0_address (mm_interconnect_0_io_bridge_0_avalon_slave_0_address), // io_bridge_0_avalon_slave_0.address
.io_bridge_0_avalon_slave_0_write (mm_interconnect_0_io_bridge_0_avalon_slave_0_write), // .write
.io_bridge_0_avalon_slave_0_read (mm_interconnect_0_io_bridge_0_avalon_slave_0_read), // .read
.io_bridge_0_avalon_slave_0_readdata (mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata), // .readdata
.io_bridge_0_avalon_slave_0_writedata (mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata), // .writedata
.io_bridge_0_avalon_slave_0_readdatavalid (mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid), // .readdatavalid
.io_bridge_0_avalon_slave_0_waitrequest (~mm_interconnect_0_io_bridge_0_avalon_slave_0_waitrequest), // .waitrequest
.io_bridge_1_avalon_slave_0_address (mm_interconnect_0_io_bridge_1_avalon_slave_0_address), // io_bridge_1_avalon_slave_0.address
.io_bridge_1_avalon_slave_0_write (mm_interconnect_0_io_bridge_1_avalon_slave_0_write), // .write
.io_bridge_1_avalon_slave_0_read (mm_interconnect_0_io_bridge_1_avalon_slave_0_read), // .read
.io_bridge_1_avalon_slave_0_readdata (mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata), // .readdata
.io_bridge_1_avalon_slave_0_writedata (mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata), // .writedata
.io_bridge_1_avalon_slave_0_readdatavalid (mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid), // .readdatavalid
.io_bridge_1_avalon_slave_0_waitrequest (~mm_interconnect_0_io_bridge_1_avalon_slave_0_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect) // .chipselect
);
nios_solo_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : user_logic.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Newton Core ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : newton.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : newton.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : August 19, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Remove temp signal ** //
// ** 2. Bit ReOrdering function change to for loop ** //
// ** 3. Modify IP2Bus_Data_int mux logic ** //
// ** 4. Modify IP2Bus_WrAck to include WrAck from BRAM ** //
// ** ** //
// ** File : user_logic.v ** //
// ** Revision : 3 ** //
// ** Author : kaylangu ** //
// ** Date : August 21, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Changed file name to user_logic.v to match EDK ** //
// ** ** //
// ** File : user_logic.v ** //
// ** Revision : 4 ** //
// ** Author : kaylangu ** //
// ** Date : August 23, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. changed the six 16-bit BRAM to three 32-bit wide BRAM ** //
// ** ** //
// ** File : user_logic.v ** //
// ** Revision : 5 ** //
// ** Author : kaylangu ** //
// ** Date : September 2, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Un-ReOrder the bits ** //
// ** 2. Change address of BRAM to Bus2IP_Addr[20:29] ** //
// ** 3. Fix ordering of input and output signals to match EDK ** //
// ** 4. RAM2IP_RdAck changed to one clock pulse ** //
// ** 5. Delay CS signal to output data when RdAck is high ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module user_logic
(Bus2IP_Clk,
Bus2IP_Reset,
Bus2IP_Addr,
Bus2IP_CS,
Bus2IP_RNW,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error,
IP2Bus_IntrEvent,
IP2WFIFO_RdReq,
WFIFO2IP_Data,
WFIFO2IP_RdAck,
WFIFO2IP_AlmostEmpty,
WFIFO2IP_Empty
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter C_SLV_AWIDTH = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_NUM_REG = 4;
parameter C_NUM_MEM = 3;
parameter C_NUM_INTR = 1;
// DATA TYPE - INPUTS AND OUTPUTS
input Bus2IP_Clk; // Bus to IP clock
input Bus2IP_Reset; // Bus to IP reset
input [0 : C_SLV_AWIDTH-1] Bus2IP_Addr; // Bus to IP address bus
input [0 : C_NUM_MEM-1] Bus2IP_CS; // Bus to IP chip select for user logic memory selection
input Bus2IP_RNW; // Bus to IP read/not write
input [0 : C_SLV_DWIDTH-1] Bus2IP_Data; // Bus to IP data bus
input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE; // Bus to IP byte enables
input [0 : C_NUM_REG-1] Bus2IP_RdCE; // Bus to IP read chip enable
input [0 : C_NUM_REG-1] Bus2IP_WrCE; // Bus to IP write chip enable
output [0 : C_SLV_DWIDTH-1] IP2Bus_Data; // IP to Bus data bus
output IP2Bus_RdAck; // IP to Bus read transfer acknowledgement
output IP2Bus_WrAck; // IP to Bus write transfer acknowledgement
output IP2Bus_Error; // IP to Bus error response
output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent; // IP to Bus interrupt event
output IP2WFIFO_RdReq; // IP to WFIFO : IP read request
input [0 : C_SLV_DWIDTH-1] WFIFO2IP_Data; // WFIFO to IP : WFIFO read data
input WFIFO2IP_RdAck; // WFIFO to IP : WFIFO read acknowledge
input WFIFO2IP_AlmostEmpty; // WFIFO to IP : WFIFO almost empty
input WFIFO2IP_Empty; // WFIFO to IP : WFIFO empty
// DATA TYPE - WIRES
wire [9:0] CPTR; // Pointer to BRAM Address
wire SYNC;
wire [15:0] RealOut1;
wire [15:0] ImagOut1;
wire [15:0] RealOut2;
wire [15:0] ImagOut2;
wire [15:0] RealOut3;
wire [15:0] ImagOut3;
wire FIR_WE;
wire [0:C_NUM_MEM-1] RAM_WE;
wire iReg2IP_RdAck;
wire iReg2IP_WrAck;
wire RAM2IP_WrAck;
wire [10:0] CPTR_1;
// For bit reordering
wire [31:0] Bus2IP_Data_int;
wire [31:0] WFIFO2IP_Data_int;
wire [31:0] iReg2IP_Data_int;
wire [0:31] iReg2IP_Data;
wire [31:0] RAM2IP_Data_int; // Data from BRAM
wire [31:0] RAM2IP_Data_int0; // Data from BRAM0
wire [31:0] RAM2IP_Data_int1; // Data from BRAM1
wire [31:0] RAM2IP_Data_int2; // Data from BRAM2
// DATA TYPE - REG
wire RAM2IP_RdAck_int;
reg RAM2IP_RdAck_dly1;
wire RAM2IP_RdAck;
reg [31:0] IP2Bus_Data_int;
reg [0:3] Bus2IP_CS_dly1;
//**************************************************************************//
//* Bit ReOrdering *//
//**************************************************************************//
assign Bus2IP_Data_int[31:0] = fnBitReordering031to310(Bus2IP_Data[0:31]);
assign WFIFO2IP_Data_int[31:0] = fnBitReordering031to310(WFIFO2IP_Data[0:31]);
assign iReg2IP_Data_int[31:0] = fnBitReordering031to310(iReg2IP_Data[0:31]);
assign IP2Bus_Data[0:31] = fnBitReordering310to031(IP2Bus_Data_int[31:0]);
//**************************************************************************//
//* BRAM Logic *//
//**************************************************************************//
// WRITE
assign RAM_WE[0:C_NUM_MEM-1] = Bus2IP_CS[0:C_NUM_MEM-1]&{(C_NUM_MEM){~Bus2IP_RNW}};
// READ
// always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
// if (Bus2IP_Reset !== 1'b0)
// RAM2IP_RdAck <= 1'b0;
// else
assign RAM2IP_RdAck_int = |Bus2IP_CS[0:C_NUM_MEM-1] & Bus2IP_RNW;
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 0)
RAM2IP_RdAck_dly1 <= 1'b0;
else
RAM2IP_RdAck_dly1 <= RAM2IP_RdAck_int;
assign RAM2IP_RdAck = RAM2IP_RdAck_int & RAM2IP_RdAck_dly1;
assign RAM2IP_WrAck = |RAM_WE[0:C_NUM_MEM-1];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
Bus2IP_CS_dly1[0:2] <= 3'b000;
else
Bus2IP_CS_dly1[0:2] <= Bus2IP_CS[0:2];
assign RAM2IP_Data_int[31:0] = RAM2IP_Data_int0[31:0] & {(32){Bus2IP_CS_dly1[0]}} |
RAM2IP_Data_int1[31:0] & {(32){Bus2IP_CS_dly1[1]}} |
RAM2IP_Data_int2[31:0] & {(32){Bus2IP_CS_dly1[2]}} ;
//**************************************************************************//
//* Outputs *//
//**************************************************************************//
assign IP2WFIFO_RdReq = ~WFIFO2IP_Empty;
assign CPTR[9:0] = CPTR_1[9:0]; // Choosing bits 9:0 to output to BRAM
always @ (/*AS*/RAM2IP_Data_int or RAM2IP_RdAck or iReg2IP_Data_int
or iReg2IP_RdAck)
begin
if (RAM2IP_RdAck)
IP2Bus_Data_int[31:0] = RAM2IP_Data_int[31:0];
else if (iReg2IP_RdAck)
IP2Bus_Data_int[31:0] = iReg2IP_Data_int[31:0];
else
IP2Bus_Data_int[31:0] = 32'd0;
end
assign IP2Bus_RdAck = RAM2IP_RdAck | iReg2IP_RdAck;
assign IP2Bus_WrAck = RAM2IP_WrAck | iReg2IP_WrAck;
assign IP2Bus_Error = iReg2IP_RdAck & RAM2IP_RdAck;
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
iReg iReg
(//Inputs
.Bus2IP_Clk (Bus2IP_Clk),
.Bus2IP_Reset (Bus2IP_Reset),
.Bus2IP_RdCE (Bus2IP_RdCE[0:3]),
.Bus2IP_WrCE (Bus2IP_WrCE[0:3]),
.Bus2IP_Data (Bus2IP_Data[0:C_SLV_DWIDTH-1]),
.WFIFO_WE (WFIFO2IP_RdAck),
.FIR_WE (FIR_WE),
//Outputs
.iReg_intr (IP2Bus_IntrEvent),
.iReg2IP_RdAck (iReg2IP_RdAck),
.IP2Bus_WrAck (iReg2IP_WrAck),
.IP2Bus_Data (iReg2IP_Data[0:C_SLV_DWIDTH-1]),
.CPTR (CPTR_1[10:0]),
.SYNC (SYNC)
);
QM_FIR QM_FIR
(//Inputs
.CLK (Bus2IP_Clk),
.ARST (Bus2IP_Reset),
.Constant (WFIFO2IP_Data_int[15:0]), //using lower 16 bits
.InputValid (WFIFO2IP_RdAck),
.Sync (SYNC),
//Outputs
.RealOut1 (RealOut1[15:0]),
.ImagOut1 (ImagOut1[15:0]),
.RealOut2 (RealOut2[15:0]),
.ImagOut2 (ImagOut2[15:0]),
.RealOut3 (RealOut3[15:0]),
.ImagOut3 (ImagOut3[15:0]),
.DataValid_R (FIR_WE)
);
BRAM BRAM0
(//Inputs
.clka (Bus2IP_Clk),
.addra (CPTR[9:0]),
.dina ({ImagOut1[15:0],RealOut1[15:0]}),
.wea (FIR_WE),
.clkb (Bus2IP_Clk),
.addrb (Bus2IP_Addr[20:29]), //Original 32-bit
.dinb (Bus2IP_Data_int[31:0]),
.web (RAM_WE[0]),
//Outputs
.doutb (RAM2IP_Data_int0[31:0])
);
BRAM BRAM1
(//Inputs
.clka (Bus2IP_Clk),
.addra (CPTR[9:0]),
.dina ({ImagOut2[15:0],RealOut2[15:0]}),
.wea (FIR_WE),
.clkb (Bus2IP_Clk),
.addrb (Bus2IP_Addr[20:29]), //Original 32-bit
.dinb (Bus2IP_Data_int[31:0]),
.web (RAM_WE[1]),
//Outputs
.doutb (RAM2IP_Data_int1[31:0])
);
BRAM BRAM2
(//Inputs
.clka (Bus2IP_Clk),
.addra (CPTR[9:0]),
.dina ({ImagOut3[15:0],RealOut3[15:0]}),
.wea (FIR_WE),
.clkb (Bus2IP_Clk),
.addrb (Bus2IP_Addr[20:29]),
.dinb (Bus2IP_Data_int[31:0]),
.web (RAM_WE[2]),
//Outputs
.doutb (RAM2IP_Data_int2[31:0])
);
//**************************************************************************//
//* Bit ReOrddering Functions *//
//**************************************************************************//
function [31:0] fnBitReordering031to310; // From [0:31] to [31:0]
input [0:31] Data1;
integer i;
begin
for (i=0;i<32;i=i+1)
fnBitReordering031to310[i] = Data1[31-i];
end
endfunction // fnBitReordering031to310
function [0:31] fnBitReordering310to031; // From [31:0] to [0:31]
input [31:0] Data1;
integer i;
begin
for (i=0;i<32;i=i+1)
fnBitReordering310to031[i] = Data1[31-i];
end
endfunction // fnBitReordering310to031
endmodule // user_logic
// Copyright(C) 2004 by Xilinx, Inc. All rights reserved.
// This text/file contains proprietary, confidential
// information of Xilinx, Inc., is distributed under license
// from Xilinx, Inc., and may be used, copied and/or
// disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you
// a license to use this text/file solely for design, simulation,
// implementation and creation of design files limited
// to Xilinx devices or technologies. Use with non-Xilinx
// devices or technologies is expressly prohibited and
// immediately terminates your license unless covered by
// a separate agreement.
//
// Xilinx is providing this design, code, or information
// "as is" solely for use in developing programs and
// solutions for Xilinx devices. By providing this design,
// code, or information as one possible implementation of
// this feature, application or standard, Xilinx is making no
// representation that this implementation is free from any
// claims of infringement. You are responsible for
// obtaining any rights you may require for your implementation.
// Xilinx expressly disclaims any warranty whatsoever with
// respect to the adequacy of the implementation, including
// but not limited to any warranties or representations that this
// implementation is free from claims of infringement, implied
// warranties of merchantability or fitness for a particular
// purpose.
//
// Xilinx products are not intended for use in life support
// appliances, devices, or systems. Use in such applications are
// expressly prohibited.
//
// This copyright and support notice must be retained as part
// of this text at all times. (c) Copyright 1995-2004 Xilinx, Inc.
// All rights reserved.
/**************************************************************************
* $RCSfile: BLKMEMDP_V6_3.v,v $ $Revision: 1.1.2.1 $ $Date: 2005/08/01 18:40:58 $
**************************************************************************
* Dual Port Block Memory - Verilog Behavioral Model
* ************************************************************************
*
*
*************************************************************************
* Filename: BLKMEMDP_V6_3.v
*
* Description: The Verilog behavioral model for the Dual Port Block Memory
*
* ***********************************************************************
*/
`timescale 1ns/10ps
`celldefine
`define c_dp_rom 4
`define c_dp_ram 2
`define c_write_first 0
`define c_read_first 1
`define c_no_change 2
module BLKMEMDP_V6_3(DOUTA, DOUTB, ADDRA, CLKA, DINA, ENA, SINITA, WEA, NDA, RFDA, RDYA, ADDRB, CLKB, DINB, ENB, SINITB, WEB,NDB, RFDB, RDYB);
parameter c_addra_width = 11 ;
parameter c_addrb_width = 9 ;
parameter c_default_data = "0"; // indicates string of hex characters used to initialize memory
parameter c_depth_a = 2048 ;
parameter c_depth_b = 512 ;
parameter c_enable_rlocs = 0 ; // core includes placement constraints
parameter c_has_default_data = 1;
parameter c_has_dina = 1 ; // indicate port A has data input pins
parameter c_has_dinb = 1 ; // indicate port B has data input pins
parameter c_has_douta = 1 ; // indicates port A has output
parameter c_has_doutb = 1 ; // indicates port B has output
parameter c_has_ena = 1 ; // indicates port A has a ENA pin
parameter c_has_enb = 1 ; // indicates port B has a ENB pin
parameter c_has_limit_data_pitch = 1 ;
parameter c_has_nda = 0 ; // Port A has a new data pin
parameter c_has_ndb = 0 ; // Port B has a new data pin
parameter c_has_rdya = 0 ; // Port A has result ready pin
parameter c_has_rdyb = 0 ; // Port B has result ready pin
parameter c_has_rfda = 0 ; // Port A has ready for data pin
parameter c_has_rfdb = 0 ; // Port B has ready for data pin
parameter c_has_sinita = 1 ; // indicates port A has a SINITA pin
parameter c_has_sinitb = 1 ; // indicates port B has a SINITB pin
parameter c_has_wea = 1 ; // indicates port A has a WEA pin
parameter c_has_web = 1 ; // indicates port B has a WEB pin
parameter c_limit_data_pitch = 16 ;
parameter c_mem_init_file = "null.mif"; // controls which .mif file used to initialize memory
parameter c_pipe_stages_a = 0 ; // indicates the number of pipe stages needed in port A
parameter c_pipe_stages_b = 0 ; // indicates the number of pipe stages needed in port B
parameter c_reg_inputsa = 0 ; // indicates we, addr, and din of port A are registered
parameter c_reg_inputsb = 0 ; // indicates we, addr, and din of port B are registered
parameter c_sim_collision_check = "NONE";
parameter c_sinita_value = "0000"; // indicates string of hex used to initialize A output registers
parameter c_sinitb_value = "0000"; // indicates string of hex used to initialize B output resisters
parameter c_width_a = 8 ;
parameter c_width_b = 32 ;
parameter c_write_modea = 2; // controls which write modes shall be used
parameter c_write_modeb = 2; // controls which write modes shall be used
// New Generics for Primitive Selection and Pin Polarity
parameter c_ybottom_addr = "1024";
parameter c_yclka_is_rising = 1; // controls the active edge of the CLKA Pin
parameter c_yclkb_is_rising = 1; // controls the active edge of the CLKB Pin
parameter c_yena_is_high = 1; // controls the polarity of the ENA Pin
parameter c_yenb_is_high = 1; // controls the polarity of the ENB Pin
parameter c_yhierarchy = "hierarchy1";
parameter c_ymake_bmm = 0;
parameter c_yprimitive_type = "4kx4"; // Indicates which primitive should be used to build the
// memory if c_yuse_single_primitive=1
parameter c_ysinita_is_high = 1; // controls the polarity of the SINITA Pin
parameter c_ysinitb_is_high = 1; // controls the polarity of the SINITB Pin
parameter c_ytop_addr = "0";
parameter c_yuse_single_primitive = 0; // controls whether the Memory is build out of a
// user selected primitive or is built from multiple
// primitives with the "optimize for area" algorithm used
parameter c_ywea_is_high = 1; // controls the polarity of the WEA Pin
parameter c_yweb_is_high = 1; // controls the polarity of the WEB Pin
parameter c_yydisable_warnings = 1; //1=no warnings, 0=print warnings
// IO ports
output [c_width_a-1:0] DOUTA;
input [c_addra_width-1:0] ADDRA;
input [c_width_a-1:0] DINA;
input ENA, CLKA, WEA, SINITA, NDA;
output RFDA, RDYA;
output [c_width_b-1:0] DOUTB;
input [c_addrb_width-1:0] ADDRB;
input [c_width_b-1:0] DINB;
input ENB, CLKB, WEB, SINITB, NDB;
output RFDB, RDYB;
// internal signals
reg [c_width_a-1:0] douta_mux_out ; // output of multiplexer --
wire [c_width_a-1:0] DOUTA = douta_mux_out;
reg RFDA, RDYA ;
reg [c_width_b-1:0] doutb_mux_out ; // output of multiplexer --
wire [c_width_b-1:0] DOUTB = doutb_mux_out;
reg RFDB, RDYB;
reg [c_width_a-1:0] douta_out_q; // registered output of douta_out
reg [c_width_a-1:0] doa_out; // output of Port A RAM
reg [c_width_a-1:0] douta_out; // output of pipeline mux for port A
reg [c_width_b-1:0] doutb_out_q ; // registered output for doutb_out
reg [c_width_b-1:0] dob_out; // output of Port B RAM
reg [c_width_b-1:0] doutb_out ; // output of pipeline mux for port B
reg [c_depth_a*c_width_a-1 : 0] mem;
reg [24:0] count ;
reg [1:0] wr_mode_a, wr_mode_b;
reg [(c_width_a-1) : 0] pipelinea [0 : c_pipe_stages_a];
reg [(c_width_b-1) : 0] pipelineb [0 : c_pipe_stages_b];
reg sub_rdy_a[0 : c_pipe_stages_a];
reg sub_rdy_b[0 : c_pipe_stages_b];
reg [10:0] ci, cj;
reg [10:0] dmi, dmj, dni, dnj, doi, doj, dai, daj, dbi, dbj, dci, dcj, ddi, ddj;
reg [10:0] pmi, pmj, pni, pnj, poi, poj, pai, paj, pbi, pbj, pci, pcj, pdi, pdj;
integer ai, aj, ak, al, am, an, ap ;
integer bi, bj, bk, bl, bm, bn, bp ;
integer i, j, k, l, m, n, p;
wire [c_addra_width-1:0] addra_i = ADDRA;
reg [c_width_a-1:0] dia_int ;
reg [c_width_a-1:0] dia_q ;
wire [c_width_a-1:0] dia_i ;
wire ena_int ;
reg ena_q ;
wire clka_int ;
reg wea_int ;
wire wea_i ;
reg wea_q ;
wire ssra_int ;
wire nda_int ;
wire nda_i ;
reg rfda_int ;
reg rdya_int ;
reg nda_q ;
reg new_data_a ;
reg new_data_a_q ;
reg [c_addra_width-1:0] addra_q;
reg [c_addra_width-1:0] addra_int;
reg [c_width_a-1:0] sinita_value ; // initialization value for output registers of Port A
wire [c_addrb_width-1:0] addrb_i = ADDRB;
reg [c_width_b-1:0] dib_int ;
reg [c_width_b-1:0] dib_q ;
wire [c_width_b-1:0] dib_i ;
wire enb_int ;
reg enb_q ;
wire clkb_int ;
reg web_int ;
wire web_i ;
reg web_q ;
wire ssrb_int ;
wire ndb_int ;
wire ndb_i ;
reg rfdb_int ;
reg rdyb_int ;
reg ndb_q ;
reg new_data_b ;
reg new_data_b_q ;
reg [c_addrb_width-1:0] addrb_q ;
reg [c_addrb_width-1:0] addrb_int ;
reg [c_width_b-1:0] sinitb_value ; // initialization value for output registers of Port B
// variables used to initialize memory contents to default values.
reg [c_width_a-1:0] bitval ;
reg [c_width_a-1:0] ram_temp [0:c_depth_a-1] ;
reg [c_width_a-1:0] default_data ;
// variables used to detect address collision on dual port Rams
reg recovery_a, recovery_b;
reg address_collision;
wire clka_enable_pp = ena_int && wea_int && enb_int && address_collision
&& c_yclka_is_rising && c_yclkb_is_rising;
wire clkb_enable_pp = enb_int && web_int && ena_int && address_collision
&& c_yclka_is_rising && c_yclkb_is_rising;
wire collision_posa_posb = clka_enable_pp || clkb_enable_pp;
// For posedge clka and negedge clkb
wire clka_enable_pn = ena_int && wea_int && enb_int && address_collision
&& c_yclka_is_rising && (!c_yclkb_is_rising);
wire clkb_enable_pn = enb_int && web_int && ena_int && address_collision
&& c_yclka_is_rising && (!c_yclkb_is_rising);
wire collision_posa_negb = clka_enable_pn || clkb_enable_pn;
// For negedge clka and posedge clkb
wire clka_enable_np = ena_int && wea_int && enb_int && address_collision
&& (!c_yclka_is_rising) && c_yclkb_is_rising;
wire clkb_enable_np = enb_int && web_int && ena_int && address_collision
&& (!c_yclka_is_rising) && c_yclkb_is_rising;
wire collision_nega_posb = clka_enable_np || clkb_enable_np;
// For negedge clka and clkb
wire clka_enable_nn = ena_int && wea_int && enb_int && address_collision
&& (!c_yclka_is_rising) && (!c_yclkb_is_rising);
wire clkb_enable_nn = enb_int && web_int && ena_int && address_collision
&& (!c_yclka_is_rising) && (!c_yclkb_is_rising);
wire collision_nega_negb = clka_enable_nn || clkb_enable_nn;
// tri0 GSR = glbl.GSR;
assign dia_i = (c_has_dina === 1)?DINA:'b0;
assign ena_int = defval(ENA, c_has_ena, 1, c_yena_is_high);
assign ssra_int = defval(SINITA, c_has_sinita, 0, c_ysinita_is_high);
assign nda_i = defval(NDA, c_has_nda, 1, 1);
assign clka_int = defval(CLKA, 1, 1, c_yclka_is_rising);
assign dib_i = (c_has_dinb === 1)?DINB:'b0;
assign enb_int = defval(ENB, c_has_enb, 1, c_yenb_is_high);
assign ssrb_int = defval(SINITB, c_has_sinitb, 0, c_ysinitb_is_high);
assign ndb_i = defval(NDB, c_has_ndb, 1, 1);
assign clkb_int = defval(CLKB, 1, 1, c_yclkb_is_rising);
// RAM/ROM functionality
assign wea_i = defval(WEA, c_has_wea, 0, c_ywea_is_high);
assign web_i = defval(WEB, c_has_web, 0, c_yweb_is_high);
function defval;
input i;
input hassig;
input val;
input active_high;
begin
if(hassig == 1)
begin
if (active_high == 1)
defval = i;
else
defval = ~i;
end
else
defval = val;
end
endfunction
function max;
input a;
input b;
begin
max = (a > b) ? a : b;
end
endfunction
function a_is_X;
input [c_width_a-1 : 0] i;
integer j ;
begin
a_is_X = 1'b0;
for(j = 0; j < c_width_a; j = j + 1)
begin
if(i[j] === 1'bx)
a_is_X = 1'b1;
end // loop
end
endfunction
function b_is_X;
input [c_width_b-1 : 0] i;
integer j ;
begin
b_is_X = 1'b0;
for(j = 0; j < c_width_b; j = j + 1)
begin
if(i[j] === 1'bx)
b_is_X = 1'b1;
end // loop
end
endfunction
function [c_width_a-1:0] hexstr_conv;
input [(c_width_a*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=c_width_a-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
if (c_yydisable_warnings == 0) begin
$display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time);
end
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < c_width_a)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
function [c_width_b-1:0] hexstr_conv_b;
input [(c_width_b*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv_b = 'b0;
for( i=c_width_b-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
if (c_yydisable_warnings == 0) begin
$display("ERROR in %m at time %t: NOT A HEX CHARACTER",$time);
end
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < c_width_b)
begin
hexstr_conv_b[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
// Initialize memory contents to 0 for now .
initial begin
sinita_value = 'b0 ;
sinitb_value = 'b0 ;
default_data = hexstr_conv(c_default_data);
if (c_has_sinita == 1 )
sinita_value = hexstr_conv(c_sinita_value);
if (c_has_sinitb == 1 )
sinitb_value = hexstr_conv_b(c_sinitb_value);
for(i = 0; i < c_depth_a; i = i + 1)
ram_temp[i] = default_data;
if (c_has_default_data == 0)
$readmemb(c_mem_init_file, ram_temp) ;
for(i = 0; i < c_depth_a; i = i + 1)
for(j = 0; j < c_width_a; j = j + 1)
begin
bitval = (1'b1 << j);
mem[(i*c_width_a) + j] = (ram_temp[i] & bitval) >> j;
end
recovery_a = 0;
recovery_b = 0;
for (k = 0; k <= c_pipe_stages_a; k = k + 1)
pipelinea[k] = sinita_value ;
for (l = 0; l <= c_pipe_stages_b; l = l + 1)
pipelineb[l] = sinitb_value ;
for (m = 0; m <= c_pipe_stages_a; m = m + 1)
sub_rdy_a[m] = 0 ;
for (n = 0; n <= c_pipe_stages_b; n = n + 1)
sub_rdy_b[n] = 0 ;
doa_out = sinita_value ;
dob_out = sinitb_value ;
nda_q = 0;
ndb_q = 0;
new_data_a_q = 0 ;
new_data_b_q = 0 ;
dia_q = 0;
dib_q = 0;
addra_q = 0;
addrb_q = 0;
wea_q = 0;
web_q = 0;
#1 douta_out = sinita_value;
#1 doutb_out = sinitb_value;
#1 rdya_int = 0;
#1 rdyb_int = 0;
end
always @(addra_int or addrb_int) begin // check address collision
address_collision <= 1'b0;
for (ci = 0; ci < c_width_a; ci = ci + 1) begin // absolute address A
for (cj = 0; cj < c_width_b; cj = cj + 1) begin // absolute address B
if ((addra_int * c_width_a + ci) == (addrb_int * c_width_b + cj)) begin
address_collision <= 1'b1;
end
end
end
end
/***********************************************************************************************************
* The following 3 always blocks handle memory inputs for the case of an address collision on ADDRA and ADDRB
***********************************************************************************************************/
always @(posedge recovery_a or posedge recovery_b) begin
if (((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01)) ||
((wr_mode_a != 2'b01) && (wr_mode_b != 2'b01))) begin
if (wea_int == 1 && web_int == 1) begin
if (addra_int < c_depth_a)
for (dmi = 0; dmi < c_width_a; dmi = dmi + 1) begin
for (dmj = 0; dmj < c_width_b; dmj = dmj + 1) begin
if ((addra_int * c_width_a + dmi) == (addrb_int * c_width_b + dmj)) begin
//Fixed read-first collision
// mem[addra_int * c_width_a + dmi] <= 1'bX;
if ((wr_mode_a == 2'b01) && (wr_mode_b == 2'b01))
begin
doa_out[dmi] <= 1'bX;
dob_out[dmj] <= 1'bX;
end
else
mem[addra_int * c_width_a + dmi] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range
//or
//Write Mode PortA is not "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #1: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
end
recovery_a <= 0;
recovery_b <= 0;
end
always @(posedge recovery_a or posedge recovery_b) begin
if ((wr_mode_a == 2'b01) && (wr_mode_b != 2'b01)) begin
if (wea_int == 1 && web_int == 1) begin
if (addra_int < c_depth_a)
for (dni = 0; dni < c_width_a; dni = dni + 1) begin
for (dnj = 0; dnj < c_width_b; dnj = dnj + 1) begin
if ((addra_int * c_width_a + dni) == (addrb_int * c_width_b + dnj)) begin
mem[addra_int * c_width_a + dni] <= dia_int[dni];
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Read First" and Write Mode PortB is not "Read First" and WEA = 1 and WEB = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #2: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
end
end
always @(posedge recovery_a or posedge recovery_b) begin
if ((wr_mode_a != 2'b01) && (wr_mode_b == 2'b01)) begin
if (wea_int == 1 && web_int == 1) begin
if (addrb_int < c_depth_b)
for (doi = 0; doi < c_width_a; doi = doi + 1) begin
for (doj = 0; doj < c_width_b; doj = doj + 1) begin
if ((addra_int * c_width_a + doi) == (addrb_int * c_width_b + doj)) begin
mem[addrb_int * c_width_b + doj] <= dib_int[doj];
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is not "Read First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #3: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; // assign data bus to X
end
end
end
end
/***********************************************************************************************************
*The following 4 always blocks handle memory outputs for the case of an address collision on ADDRA and ADDRB
***********************************************************************************************************/
always @(posedge recovery_a or posedge recovery_b) begin
if ((wr_mode_b == 2'b00) || (wr_mode_b == 2'b10)) begin
if ((wea_int == 0) && (web_int == 1) && (ssra_int == 0)) begin
if (addra_int < c_depth_a)
for (dai = 0; dai < c_width_a; dai = dai + 1) begin
for (daj = 0; daj < c_width_b; daj = daj + 1) begin
if ((addra_int * c_width_a + dai) == (addrb_int * c_width_b + daj)) begin
doa_out[dai] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortB is "Write First" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
//or
//Write Mode PortB is "No Change" and WEA = 0 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #4: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
end
end
always @(posedge recovery_a or posedge recovery_b) begin
if ((wr_mode_a == 2'b00) || (wr_mode_a == 2'b10)) begin
if ((wea_int == 1) && (web_int == 0) && (ssrb_int == 0)) begin
if (addrb_int < c_depth_b)
for (dbi = 0; dbi < c_width_a; dbi = dbi + 1) begin
for (dbj = 0; dbj < c_width_b; dbj = dbj + 1) begin
if ((addra_int * c_width_a + dbi) == (addrb_int * c_width_b + dbj)) begin
dob_out[dbj] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Write First" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range
//or
//Write Mode PortA is "No Change" and WEA = 1 and WEB = 0 and SINITB = 0 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #5: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; // assign data bus to X
end
end
end
end
always @(posedge recovery_a or posedge recovery_b) begin
if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
((wr_mode_a != 2'b10) && (wr_mode_b == 2'b10)) ||
((wr_mode_a == 2'b01) && (wr_mode_b == 2'b00))) begin
if ((wea_int == 1) && (web_int == 1) && (ssra_int == 0)) begin
if (addra_int < c_depth_a)
for (dci = 0; dci < c_width_a; dci = dci + 1) begin
for (dcj = 0; dcj < c_width_b; dcj = dcj + 1) begin
if ((addra_int * c_width_a + dci) == (addrb_int * c_width_b + dcj)) begin
doa_out[dci] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
//or
//Write Mode PortA is not "No Change" and Write Mode PortB is "No Change" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
//or
//Write Mode PortA is "Read First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITA = 0 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #6: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
end
end
always @(posedge recovery_a or posedge recovery_b) begin
if (((wr_mode_a == 2'b00) && (wr_mode_b == 2'b00)) ||
((wr_mode_a == 2'b10) && (wr_mode_b != 2'b10)) ||
((wr_mode_a == 2'b00) && (wr_mode_b == 2'b01))) begin
if ((wea_int == 1) && (web_int == 1) && (ssrb_int == 0)) begin
if (addrb_int < c_depth_b)
for (ddi = 0; ddi < c_width_a; ddi = ddi + 1) begin
for (ddj = 0; ddj < c_width_b; ddj = ddj + 1) begin
if ((addra_int * c_width_a + ddi) == (addrb_int * c_width_b + ddj)) begin
dob_out[ddj] <= 1'bX;
end
end
end
else begin
//Warning Condition:
//Write Mode PortA is "Write First" and Write Mode PortB is "Write First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range
//or
//Write Mode PortA is "No Change" and Write Mode PortB is not "No Change" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range
//or
//Write Mode PortA is "Write First" and Write Mode PortB is "Read First" and WEA = 1 and WEB = 1 and SINITB = 0 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #7: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; // assign data bus to X
end
end
end
end
// Parity Section is deleted
initial begin
case (c_write_modea)
`c_write_first : wr_mode_a <= 2'b00;
`c_read_first : wr_mode_a <= 2'b01;
`c_no_change : wr_mode_a <= 2'b10;
default : begin
if (c_yydisable_warnings == 0) begin
$display("Error in %m at time %t: c_write_modea = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modea);
end
$finish;
end
endcase
end
initial begin
case (c_write_modeb)
`c_write_first : wr_mode_b <= 2'b00;
`c_read_first : wr_mode_b <= 2'b01;
`c_no_change : wr_mode_b <= 2'b10;
default : begin
if (c_yydisable_warnings == 0) begin
$display("Error in %m at time %t: c_write_modeb = %s is not WRITE_FIRST, READ_FIRST or NO_CHANGE.",$time, c_write_modeb);
end
$finish;
end
endcase
end
// Port A
// Generate ouput control signals for Port A: RFDA and RDYA
always @ (rfda_int or rdya_int)
begin
if (c_has_rfda == 1)
RFDA = rfda_int ;
else
RFDA = 1'b0 ;
if ((c_has_rdya == 1) && (c_has_nda == 1) && (c_has_rfda == 1) )
RDYA = rdya_int;
else
RDYA = 1'b0 ;
end
always @ (ena_int )
begin
if (ena_int == 1'b1)
rfda_int <= 1'b1 ;
else
rfda_int <= 1'b0 ;
end
// Gate nd signal with en
assign nda_int = ena_int && nda_i ;
// Register hanshaking signals for port A
always @ (posedge clka_int)
begin
if (ena_int == 1'b1)
begin
if (ssra_int == 1'b1)
nda_q <= 1'b0 ;
else
nda_q <= nda_int ;
end
else
nda_q <= nda_q ;
end
// Register data/ address / we inputs for port A
always @ (posedge clka_int)
begin
if (ena_int == 1'b1)
begin
dia_q <= dia_i ;
addra_q <= addra_i ;
wea_q <= wea_i ;
end
end
// Select registered or non-registered write enable for Port A
always @ ( wea_i or wea_q )
begin
if (c_reg_inputsa == 1)
wea_int = wea_q ;
else
wea_int = wea_i ;
end
// Select registered or non-registered data/address/nd inputs for Port A
always @ ( dia_i or dia_q )
begin
if ( c_reg_inputsa == 1)
dia_int = dia_q;
else
dia_int = dia_i;
end
always @ ( addra_i or addra_q or nda_q or nda_int )
begin
if ( c_reg_inputsa == 1)
begin
addra_int = addra_q ;
if ((wea_q == 1'b1) && (c_write_modea == 2))
new_data_a = 1'b0 ;
else
new_data_a = nda_q ;
end
else
begin
addra_int = addra_i;
if ((wea_i == 1'b1) && (c_write_modea == 2))
new_data_a = 1'b0 ;
else
new_data_a = nda_int ;
end
end
// Register the new_data signal for Port A to track the synchronous RAM output
always @(posedge clka_int)
begin
if (ena_int == 1'b1)
begin
if (ssra_int == 1'b1)
new_data_a_q <= 1'b0 ;
else
// Do not update RDYA if write mode is no_change and wea=1
//if (!(c_write_modea == 2 && wea_int == 1)) begin
// rii1 : 10/20 Make dual port behavior the same as single port
new_data_a_q <= new_data_a ;
//end
end
end
// Generate data outputs for Port A
/***************************************************************
*The following always block assigns the value for the DOUTA bus
***************************************************************/
always @(posedge clka_int) begin
if (ena_int == 1'b1) begin
if (ssra_int == 1'b1) begin
// for ( ai = 0; ai < c_width_a; ai = ai + 1)
// doa_out[ai] <= sinita_value[ai];
doa_out <= sinita_value;
end
else begin
//The following IF block assigns the output for a write operation
if (wea_int == 1'b1) begin
if (wr_mode_a == 2'b00) begin
if (addra_int < c_depth_a)
// for ( aj = 0; aj < c_width_a; aj = aj + 1)
// doa_out[aj] <= dia_int[aj] ;
doa_out <= dia_int ;
else begin
//Warning Condition (Error occurs on rising edge of CLKA):
//Write Mode PortA is "Write First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #8: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; // assign data bus to X
end
end
else if (wr_mode_a == 2'b01) begin
if (addra_int < c_depth_a)
// for ( ak = 0; ak < c_width_a; ak = ak + 1)
// doa_out[ak] <= mem[(addra_int*c_width_a) + ak];
doa_out <= mem >> (addra_int*c_width_a);
else begin
//Warning Condition (Error occurs on rising edge of CLKA):
//Write Mode PortA is "Read First" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #9: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; //assign data bus to X
end
end
else begin
if (addra_int < c_depth_a)
doa_out <= doa_out;
else begin
//Warning Condition (Error occurs on rising edge of CLKA):
//Write Mode PortA is "No Change" and ENA = 1 and SINITA = 0 and WEA = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #10: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; //assign data bus to X
end
end
end
//The following ELSE block assigns the output for a read operation
else begin
if (addra_int < c_depth_a)
// for ( al = 0; al < c_width_a; al = al + 1)
// doa_out[al] <= mem[(addra_int*c_width_a) + al];
doa_out <= mem >> (addra_int*c_width_a);
else begin
if (c_has_douta == 1)//New IF statement to remove read errors when port is write only
begin
//Warning Condition (Error occurs on rising edge of CLKA):
//ENA = 1 and SINITA = 0 and WEA = 0 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #11: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; //assign data bus to X
end
end
end
end
end
end
/***************************************************************************************
*The following always block assigns the DINA bus to the memory during a write operation
***************************************************************************************/
always @(posedge clka_int) begin
if (ena_int == 1'b1 && wea_int == 1'b1) begin
if (addra_int < c_depth_a)
for ( am = 0; am < c_width_a; am = am + 1)
mem[(addra_int*c_width_a) + am] <= dia_int[am];
else begin
//Warning Condition (Error occurs on rising edge of CLKA):
//ENA = 1 and WEA = 1 and ADDRA out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #12: Warning in %m at time %t: Port A address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addra_int,addra_int,c_depth_a-1);
end
doa_out <= {c_width_a{1'bX}}; //assign data bus to X
end
end
end
// output pipelines for Port A
always @(posedge clka_int) begin
if (ena_int == 1'b1 && c_pipe_stages_a > 0)
begin
for (i = c_pipe_stages_a; i >= 1; i = i -1 )
begin
if (ssra_int == 1'b1 && ena_int == 1'b1 )
begin
pipelinea[i] <= sinita_value ;
sub_rdy_a[i] <= 0 ;
end
else
begin
// Do not change output when no_change and web=1
// if (!(c_write_modea == 2 && wea_int == 1)) begin
if (i==1)
pipelinea[i] <= doa_out ;
else
pipelinea[i] <= pipelinea[i-1] ;
// end // if (!(c_write_modea == 2 && wea_int == 1))
if (i==1)
sub_rdy_a[i] <= new_data_a_q ;
else
sub_rdy_a[i] <= sub_rdy_a[i-1] ;
end
end
end
end
// Select pipeline output if c_pipe_stages_a > 0
always @( pipelinea[c_pipe_stages_a] or sub_rdy_a[c_pipe_stages_a] or new_data_a_q or doa_out ) begin
if (c_pipe_stages_a == 0 )
begin
douta_out = doa_out ;
rdya_int = new_data_a_q;
end
else
begin
douta_out = pipelinea[c_pipe_stages_a];
rdya_int = sub_rdy_a[c_pipe_stages_a];
end
end
// Select Port A data outputs based on c_has_douta parameter
always @( douta_out ) begin
if ( c_has_douta == 1)
douta_mux_out = douta_out ;
else
douta_mux_out = 0 ;
end
// Port B
// Generate output control signals for Port B: RFDB and RDYB
always @ (rfdb_int or rdyb_int)
begin
if (c_has_rfdb == 1)
RFDB = rfdb_int ;
else
RFDB = 1'b0 ;
if ((c_has_rdyb == 1) && (c_has_ndb == 1) && (c_has_rfdb == 1) )
RDYB = rdyb_int;
else
RDYB = 1'b0 ;
end
always @ (enb_int )
begin
if ( enb_int == 1'b1 )
rfdb_int = 1'b1 ;
else
rfdb_int = 1'b0 ;
end
// Gate nd signal with en
assign ndb_int = enb_int && ndb_i ;
// Register hanshaking signals for port B
always @ (posedge clkb_int)
begin
if (enb_int == 1'b1)
begin
if (ssrb_int == 1'b1)
ndb_q <= 1'b0 ;
else
ndb_q <= ndb_int ;
end
else
ndb_q <= ndb_q;
end
// Register data / address / we inputs for port B
always @ (posedge clkb_int)
begin
if (enb_int == 1'b1)
begin
dib_q <= dib_i ;
addrb_q <= addrb_i ;
web_q <= web_i ;
end
end
// Select registered or non-registered write enable for port B
always @ (web_i or web_q )
begin
if (c_reg_inputsb == 1)
web_int = web_q ;
else
web_int = web_i ;
end
// Select registered or non-registered data/address/nd inputs for Port B
always @ ( dib_i or dib_q )
begin
if ( c_reg_inputsb == 1)
dib_int = dib_q;
else
dib_int = dib_i;
end
always @ ( addrb_i or addrb_q or ndb_q or ndb_int or web_q or web_i)
begin
if ( c_reg_inputsb == 1)
begin
addrb_int = addrb_q ;
if ((web_q == 1'b1) && (c_write_modeb == 2))
new_data_b = 1'b0 ;
else
new_data_b = ndb_q ;
end
else
begin
addrb_int = addrb_i;
if ((web_i == 1'b1) && (c_write_modeb == 2))
new_data_b = 1'b0 ;
else
new_data_b = ndb_int ;
end
end
// Register the new_data signal for Port B to track the synchronous RAM output
always @(posedge clkb_int)
begin
if (enb_int == 1'b1 )
begin
if (ssrb_int == 1'b1)
new_data_b_q <= 1'b0 ;
else
// Do not update RDYB if write mode is no_change and web=1
//if (!(c_write_modeb == 2 && web_int == 1)) begin
// rii1 : 10/20 Make dual port behavior the same as single port
new_data_b_q <= new_data_b ;
//end
end
end
// Generate data outputs for Port B
/***************************************************************
*The following always block assigns the value for the DOUTB bus
***************************************************************/
always @(posedge clkb_int) begin
if (enb_int == 1'b1) begin
if (ssrb_int == 1'b1) begin
// for (bi = 0; bi < c_width_b; bi = bi + 1)
// dob_out[bi] <= sinitb_value[bi];
dob_out <= sinitb_value;
end
else begin
//The following IF block assigns the output for a write operation
if (web_int == 1'b1) begin
if (wr_mode_b == 2'b00) begin
if (addrb_int < c_depth_b)
// for (bj = 0; bj < c_width_b; bj = bj + 1)
// dob_out[bj] <= dib_int[bj];
dob_out <= dib_int;
else begin
//Warning Condition (Error occurs on rising edge of CLKB):
//Write Mode PortB is "Write First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #13: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; //assign data bus to X
end
end
else if (wr_mode_b == 2'b01) begin
if (addrb_int < c_depth_b)
// for (bk = 0; bk < c_width_b; bk = bk + 1)
// dob_out[bk] <= mem[(addrb_int*c_width_b) + bk];
dob_out <= mem >> (addrb_int*c_width_b);
else begin
//Warning Condition (Error occurs on rising edge of CLKB):
//Write Mode PortB is "Read First" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #14: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; //assign data bus to X
end
end
else begin
if (addrb_int < c_depth_b)
dob_out <= dob_out ;
else begin
//Warning Condition (Error occurs on rising edge of CLKB):
//Write Mode PortB is "No Change" and ENB = 1 and SINITB = 0 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #15: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; //assign data bus to X
end
end
end
//The following ELSE block assigns the output for a read operation
else begin
if (addrb_int < c_depth_b)
// for (bl = 0; bl < c_width_b; bl = bl + 1)
// dob_out[bl] <= mem[(addrb_int*c_width_b) + bl];
dob_out <= mem >> (addrb_int*c_width_b);
else begin
if (c_has_doutb == 1)//New IF statement to remove read errors when port is write only
begin
//Warning Condition (Error occurs on rising edge of CLKB):
//ENB = 1 and SINITB = 0 and WEB = 0 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #16: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; //assign data bus to X
end
end
end
end
end
end
/***************************************************************************************
*The following always block assigns the DINA bus to the memory during a write operation
***************************************************************************************/
always @(posedge clkb_int) begin
if (enb_int == 1'b1 && web_int == 1'b1) begin
if (addrb_int < c_depth_b)
for (bm = 0; bm < c_width_b; bm = bm + 1)
mem[(addrb_int*c_width_b) + bm] <= dib_int[bm];
else begin
//Warning Condition (Error occurs on rising edge of CLKB):
//ENB = 1 and WEB = 1 and ADDRB out of the valid range
if (c_yydisable_warnings == 0) begin
$display("Invalid Address Warning #17: Warning in %m at time %t: Port B address %d (%b) of block memory invalid. Valid depth configured as 0 to %d",$time,addrb_int,addrb_int,c_depth_b-1);
end
dob_out <= {c_width_b{1'bX}}; // assign data bus to X
end
end
end
// output pipelines for Port B
always @(posedge clkb_int) begin
if (enb_int == 1'b1 && c_pipe_stages_b > 0)
begin
for (j = c_pipe_stages_b; j >= 1; j = j -1 )
begin
if (ssrb_int == 1'b1 && enb_int == 1'b1 )
begin
pipelineb[j] <= sinitb_value ;
sub_rdy_b[j] <= 0 ;
end
else
begin
// Do not change output when no_change and web=1
// if (!(c_write_modeb == 2 && web_int == 1)) begin
if (j==1)
pipelineb[j] <= dob_out ;
else
pipelineb[j] <= pipelineb[j-1] ;
// end
if (j==1)
sub_rdy_b[j] <= new_data_b_q ;
else
sub_rdy_b[j] <= sub_rdy_b[j-1] ;
end
end
end
end
// Select pipeline for B if c_pipe_stages_b > 0
always @(pipelineb[c_pipe_stages_b] or sub_rdy_b[c_pipe_stages_b] or new_data_b_q or dob_out) begin
if ( c_pipe_stages_b == 0 )
begin
doutb_out = dob_out ;
rdyb_int = new_data_b_q;
end
else
begin
rdyb_int = sub_rdy_b[c_pipe_stages_b];
doutb_out = pipelineb[c_pipe_stages_b];
end
end
// Select Port B data outputs based on c_has_doutb parameter
always @( doutb_out) begin
if ( c_has_doutb == 1)
doutb_mux_out = doutb_out ;
else
doutb_mux_out = 0 ;
end
specify
// when both CLKA and CLKB are active on the positive edge
$recovery (posedge CLKB, posedge CLKA &&& collision_posa_posb, 1, recovery_b);
$recovery (posedge CLKA, posedge CLKB &&& collision_posa_posb, 1, recovery_a);
// when both CLKA active on positive edge and CLKB are active on the negative edge
$recovery (negedge CLKB, posedge CLKA &&& collision_posa_negb, 1, recovery_b);
$recovery (posedge CLKA, negedge CLKB &&& collision_posa_negb, 1, recovery_a);
// when both CLKA active on negative edge and CLKB are active on the positive edge
$recovery (posedge CLKB, negedge CLKA &&& collision_nega_posb, 1, recovery_b);
$recovery (negedge CLKA, posedge CLKB &&& collision_nega_posb, 1, recovery_a);
// when both CLKA and CLKB are active on the negative edge
$recovery (negedge CLKB, negedge CLKA &&& collision_nega_negb, 1, recovery_b);
$recovery (negedge CLKA, negedge CLKB &&& collision_nega_negb, 1, recovery_a);
endspecify
endmodule // BLKMEMDP_V6_3
//*********************************************************************************//
// ** General Information ** //
// ******************************************************************************* //
// ** Module : LkupTbl1.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Date : 2008-08-08 ** //
// ** Description: This is the sine/cosine lookup table for Channel 1. ** //
// ** Center Frequency: 12.5MHz ** //
// ** Sampling Frequency: 60MHz ** //
// ** Python file: LUT.py ** //
//*********************************************************************************//
`timescale 1 ns / 100 ps
module LkupTbl1
(//Outputs
cosine,
sine,
//Input
CLK,
ARST,
cntr
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
output reg [15:0] sine ;
output reg [15:0] cosine ;
input CLK ;
input ARST ;
input [4:0] cntr ;
//******************************************************************************//
//* Look-Up Table *//
//******************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
sine = 'b0000000000000000; // Reset to 0
cosine = 'b0000000000000000; // Reset to 0
end
else
begin
case (cntr)
0: // theta=0.0000
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b0100000000000000; // 1.0000
end
1: // theta=1.3090
begin
sine = 'b0011110111010001; // 0.9659
cosine = 'b0001000010010000; // 0.2588
end
2: // theta=2.6180
begin
sine = 'b0001111111111111; // 0.5000
cosine = 'b1100100010010100; // -0.8660
end
3: // theta=3.9270
begin
sine = 'b1101001010111111; // -0.7071
cosine = 'b1101001010111111; // -0.7071
end
4: // theta=5.2360
begin
sine = 'b1100100010010100; // -0.8660
cosine = 'b0010000000000000; // 0.5000
end
5: // theta=0.2618
begin
sine = 'b0001000010010000; // 0.2588
cosine = 'b0011110111010001; // 0.9659
end
6: // theta=1.5708
begin
sine = 'b0100000000000000; // 1.0000
cosine = 'b0000000000000000; // 0.0000
end
7: // theta=2.8798
begin
sine = 'b0001000010010000; // 0.2588
cosine = 'b1100001000101111; // -0.9659
end
8: // theta=4.1888
begin
sine = 'b1100100010010100; // -0.8660
cosine = 'b1110000000000001; // -0.5000
end
9: // theta=5.4978
begin
sine = 'b1101001010111111; // -0.7071
cosine = 'b0010110101000001; // 0.7071
end
10: // theta=0.5236
begin
sine = 'b0001111111111111; // 0.5000
cosine = 'b0011011101101100; // 0.8660
end
11: // theta=1.8326
begin
sine = 'b0011110111010001; // 0.9659
cosine = 'b1110111101110000; // -0.2588
end
12: // theta=3.1416
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b1100000000000000; // -1.0000
end
13: // theta=4.4506
begin
sine = 'b1100001000101111; // -0.9659
cosine = 'b1110111101110000; // -0.2588
end
14: // theta=5.7596
begin
sine = 'b1110000000000000; // -0.5000
cosine = 'b0011011101101100; // 0.8660
end
15: // theta=0.7854
begin
sine = 'b0010110101000001; // 0.7071
cosine = 'b0010110101000001; // 0.7071
end
16: // theta=2.0944
begin
sine = 'b0011011101101100; // 0.8660
cosine = 'b1110000000000000; // -0.5000
end
17: // theta=3.4034
begin
sine = 'b1110111101110000; // -0.2588
cosine = 'b1100001000101111; // -0.9659
end
18: // theta=4.7124
begin
sine = 'b1100000000000000; // -1.0000
cosine = 'b0000000000000000; // -0.0000
end
19: // theta=6.0214
begin
sine = 'b1110111101110000; // -0.2588
cosine = 'b0011110111010001; // 0.9659
end
20: // theta=1.0472
begin
sine = 'b0011011101101100; // 0.8660
cosine = 'b0010000000000000; // 0.5000
end
21: // theta=2.3562
begin
sine = 'b0010110101000001; // 0.7071
cosine = 'b1101001010111111; // -0.7071
end
22: // theta=3.6652
begin
sine = 'b1110000000000001; // -0.5000
cosine = 'b1100100010010100; // -0.8660
end
23: // theta=4.9742
begin
sine = 'b1100001000101111; // -0.9659
cosine = 'b0001000010010000; // 0.2588
end
default:
begin
sine = 'b0000000000000000; // 0
cosine = 'b0000000000000000; // 0
end
endcase
end
endmodule
//*********************************************************************************//
// ** General Information ** //
// ******************************************************************************* //
// ** Module : LkupTbl2.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Date : 2008-08-08 ** //
// ** Description: This is the sine/cosine lookup table for noise channel ** //
// ** Center Frequency: 15MHz ** //
// ** Sampling Frequency: 60MHz ** //
// ** Python file: LUT.py ** //
//*********************************************************************************//
`timescale 1 ns / 100 ps
module LkupTbl2
(//Outputs
cosine,
sine,
//Input
CLK,
ARST,
cntr
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
output reg [15:0] sine ;
output reg [15:0] cosine ;
input CLK ;
input ARST ;
input [1:0] cntr ;
//******************************************************************************//
//* Look-Up Table *//
//******************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
sine = 'b0000000000000000; // Reset to 0
cosine = 'b0000000000000000; // Reset to 0
end
else
begin
case (cntr)
0: // theta=0.0000
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b0100000000000000; // 1.0000
end
1: // theta=1.5708
begin
sine = 'b0100000000000000; // 1.0000
cosine = 'b0000000000000000; // 0.0000
end
2: // theta=3.1416
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b1100000000000000; // -1.0000
end
3: // theta=4.7124
begin
sine = 'b1100000000000000; // -1.0000
cosine = 'b0000000000000000; // -0.0000
end
default:
begin
sine = 'b0000000000000000; // 0
cosine = 'b0000000000000000; // 0
end
endcase
end
endmodule
//*********************************************************************************//
// ** General Information ** //
// ******************************************************************************* //
// ** Module : LkupTbl3.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Date : 2008-08-08 ** //
// ** Description: This is the sine/cosine lookup table for Channel 2. ** //
// ** Center Frequency: 17.5MHz ** //
// ** Sampling Frequency: 60MHz ** //
// ** Python file: LUT.py ** //
//*********************************************************************************//
`timescale 1 ns / 100 ps
module LkupTbl3
(//Outputs
cosine,
sine,
//Input
CLK,
ARST,
cntr
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
output reg [15:0] sine ;
output reg [15:0] cosine ;
input CLK ;
input ARST ;
input [4:0] cntr ;
//******************************************************************************//
//* Look-Up Table *//
//******************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
sine = 'b0000000000000000; // Reset to 0
cosine = 'b0000000000000000; // Reset to 0
end
else
begin
case (cntr)
0: // theta=0.0000
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b0100000000000000; // 1.0000
end
1: // theta=1.8326
begin
sine = 'b0011110111010001; // 0.9659
cosine = 'b1110111101110000; // -0.2588
end
2: // theta=3.6652
begin
sine = 'b1110000000000001; // -0.5000
cosine = 'b1100100010010100; // -0.8660
end
3: // theta=5.4978
begin
sine = 'b1101001010111111; // -0.7071
cosine = 'b0010110101000001; // 0.7071
end
4: // theta=1.0472
begin
sine = 'b0011011101101100; // 0.8660
cosine = 'b0010000000000000; // 0.5000
end
5: // theta=2.8798
begin
sine = 'b0001000010010000; // 0.2588
cosine = 'b1100001000101111; // -0.9659
end
6: // theta=4.7124
begin
sine = 'b1100000000000000; // -1.0000
cosine = 'b0000000000000000; // -0.0000
end
7: // theta=0.2618
begin
sine = 'b0001000010010000; // 0.2588
cosine = 'b0011110111010001; // 0.9659
end
8: // theta=2.0944
begin
sine = 'b0011011101101100; // 0.8660
cosine = 'b1110000000000001; // -0.5000
end
9: // theta=3.9270
begin
sine = 'b1101001010111111; // -0.7071
cosine = 'b1101001010111111; // -0.7071
end
10: // theta=5.7596
begin
sine = 'b1110000000000000; // -0.5000
cosine = 'b0011011101101100; // 0.8660
end
11: // theta=1.3090
begin
sine = 'b0011110111010001; // 0.9659
cosine = 'b0001000010010000; // 0.2588
end
12: // theta=3.1416
begin
sine = 'b0000000000000000; // 0.0000
cosine = 'b1100000000000000; // -1.0000
end
13: // theta=4.9742
begin
sine = 'b1100001000101111; // -0.9659
cosine = 'b0001000010010000; // 0.2588
end
14: // theta=0.5236
begin
sine = 'b0001111111111111; // 0.5000
cosine = 'b0011011101101100; // 0.8660
end
15: // theta=2.3562
begin
sine = 'b0010110101000001; // 0.7071
cosine = 'b1101001010111111; // -0.7071
end
16: // theta=4.1888
begin
sine = 'b1100100010010100; // -0.8660
cosine = 'b1110000000000000; // -0.5000
end
17: // theta=6.0214
begin
sine = 'b1110111101110000; // -0.2588
cosine = 'b0011110111010001; // 0.9659
end
18: // theta=1.5708
begin
sine = 'b0100000000000000; // 1.0000
cosine = 'b0000000000000000; // -0.0000
end
19: // theta=3.4034
begin
sine = 'b1110111101110000; // -0.2588
cosine = 'b1100001000101111; // -0.9659
end
20: // theta=5.2360
begin
sine = 'b1100100010010100; // -0.8660
cosine = 'b0001111111111111; // 0.5000
end
21: // theta=0.7854
begin
sine = 'b0010110101000001; // 0.7071
cosine = 'b0010110101000001; // 0.7071
end
22: // theta=2.6180
begin
sine = 'b0010000000000000; // 0.5000
cosine = 'b1100100010010100; // -0.8660
end
23: // theta=4.4506
begin
sine = 'b1100001000101111; // -0.9659
cosine = 'b1110111101110000; // -0.2588
end
default:
begin
sine = 'b0000000000000000; // 0
cosine = 'b0000000000000000; // 0
end
endcase
end
endmodule
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : MAC1.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Multiplier-Accumulator Module ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : MAC1.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module MAC1
(// Inputs
CLK , // Clock
ARST , // Reset
filterCoef , // Filter Coeficients
InData , // Input Data
input_Valid , // Input Valid
initialize , // Initialize
// Outputs
OutData , // Output Data
output_Valid // Output Valid
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter IWIDTH = 16; // Input bit width
parameter OWIDTH = 32; // Output bit width
parameter AWIDTH = 32; // Internal bit width
parameter NTAPS = 15; // Total number of taps including zeros
parameter NTAPSr = 15; // Real number of taps in the filter
parameter CNTWIDTH = 4 ; // Count bit width, depends on number of taps
parameter NMULT = 1 ; // Number of clocks it takes for multiplier
// to generate an answer
// DATA TYPE - INPUTS AND OUTPUTS
input CLK ; // 60MHz Clock
input ARST ;
input input_Valid ;
input initialize ;
input signed [(IWIDTH-1):0] InData, filterCoef ;
output signed [(OWIDTH-1):0] OutData ;
output output_Valid ;
// DATA TYPE - REGISTERS
reg signed [(AWIDTH-1):0] mult, accum ;
reg input_Valid0 ;
reg initialize1 ;
reg output_Valid_1 ;
wire output_Valid ;
reg [CNTWIDTH-1:0] count ;
// DATA TYPE - WIRES
wire signed [(AWIDTH-1):0] accum_tmp ;
wire [CNTWIDTH-1:0] taps ;
assign taps = (NTAPS == NTAPSr) ? 0: (NTAPS - NTAPS + NTAPSr) ;
//**************************************************************************//
//* Input Buffers *//
//**************************************************************************//
always @(posedge CLK or posedge ARST)
if (ARST) input_Valid0 <= 1'b0 ;
else input_Valid0 <= input_Valid ;
always @(posedge CLK or posedge ARST)
if (ARST) initialize1 <= 1'b0 ;
else initialize1 <= initialize ;
//**************************************************************************//
//* Multiply-Accumulate *//
//**************************************************************************//
// Multiplier
always @(posedge CLK or posedge ARST)
if (ARST) mult[(AWIDTH-1):0] <= {(AWIDTH-1){1'b0}} ;
else mult[(AWIDTH-1):0] <= filterCoef*InData ;
assign accum_tmp[(AWIDTH-1):0] = mult[(AWIDTH-1):0] + accum[(AWIDTH-1):0];
// Accumulator
always @(posedge CLK or posedge ARST)// or initialize)
if (ARST) accum[(OWIDTH-1):0] <= {(OWIDTH){1'b0}} ;
else accum[(OWIDTH-1):0] <= (initialize1) ?
mult[(AWIDTH-1):0] :
(input_Valid0 ? accum_tmp[(AWIDTH-1):0]
: accum[(AWIDTH-1):0]) ;
//**************************************************************************//
//* Counters *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST) count[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else count[CNTWIDTH-1:0] <= initialize ?
0 :
input_Valid0 + count[CNTWIDTH-1:0] ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @(posedge CLK or posedge ARST)
if (ARST) output_Valid_1 <= 1'b0 ;
else output_Valid_1 <= (count[CNTWIDTH-1:0]==(NTAPSr-1+NMULT-1)) ;
assign output_Valid = output_Valid_1 & (count[CNTWIDTH-1:0]==taps) ;
assign OutData[(OWIDTH-1):0] = accum[(OWIDTH-1):0] ;
endmodule //MAC1// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : QM.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Quadrature Modulation. ** //
// ** Using sin/cos look up table. ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : QM.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module QM
(// Inputs
CLK ,
ARST ,
Sync ,
Constant ,
InputValid ,
//Outputs
Real1 ,
Imag1 ,
Real2 ,
Imag2 ,
Real3 ,
Imag3 ,
OutputValid
// tp_1 //To print out QM output, use this as the DataValid
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter OWIDTH = 16 ; // output bit width
parameter IWIDTH = 16 ; // input bit width
parameter MAXCNT1 = 23 ; // Counter up to repeating for ch1&2
parameter MAXCNT2 = 3 ; // Counter up to repeating for ch3
parameter CNTWIDTH1 = 5 ; // counter bit width for ch1 & ch2
parameter CNTWIDTH2 = 2 ; // counter bit width for ch3 (noise)
// DATA TYPE - INPUTS AND OUTPUTS
input signed [IWIDTH-1:0] Constant ;
input CLK ;
input ARST ;
input InputValid ;
input Sync ;
output reg signed [OWIDTH-1:0] Real1 ;
output reg signed [OWIDTH-1:0] Real2 ;
output reg signed [OWIDTH-1:0] Real3 ;
output reg signed [OWIDTH-1:0] Imag1 ;
output reg signed [OWIDTH-1:0] Imag2 ;
output reg signed [OWIDTH-1:0] Imag3 ;
output reg OutputValid ;
// output tp_1 ; // only used to print results from
// test bench
// DATA TYPE - REGISTERS
reg [CNTWIDTH1-1:0] counter1 ;
reg [CNTWIDTH2-1:0] counter2 ;
reg signed [IWIDTH-1:0] Constant1 ;
reg OutputValid1;
// DATA TYPE - WIRES
wire signed [31:0] Real_1 ;
wire signed [31:0] Real_2 ;
wire signed [31:0] Real_3 ;
wire signed [31:0] Imag_1 ;
wire signed [31:0] Imag_2 ;
wire signed [31:0] Imag_3 ;
wire signed [15:0] Cosine1 ;
wire signed [15:0] Cosine2 ;
wire signed [15:0] Cosine3 ;
wire signed [15:0] Sine1 ;
wire signed [15:0] Sine2 ;
wire signed [15:0] Sine3 ;
//**************************************************************************//
//* Counters *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
counter1[CNTWIDTH1-1:0] <= {(CNTWIDTH1){1'b0}};
counter2[CNTWIDTH2-1:0] <= {(CNTWIDTH2){1'b0}};
end
else if (Sync)
begin
counter1[CNTWIDTH1-1:0] <= {(CNTWIDTH1){1'b0}};
counter2[CNTWIDTH2-1:0] <= {(CNTWIDTH2){1'b0}};
end
else
begin
counter1[CNTWIDTH1-1:0] <= InputValid ?
(counter1[CNTWIDTH1-1:0] == MAXCNT1) ? 0
: (counter1[CNTWIDTH1-1:0] + 1)
: counter1[CNTWIDTH1-1:0];
counter2[CNTWIDTH2-1:0] <= InputValid ?
(counter2[CNTWIDTH2-1:0] == MAXCNT2) ? 0
: (counter2[CNTWIDTH2-1:0] + 1)
: counter2[CNTWIDTH2-1:0];
end
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
OutputValid <= 1'b0 ;
OutputValid1 <= 1'b0 ;
Constant1[15:0] <= 16'sb0000_0000_0000_0000 ;
end
else
begin
OutputValid <= OutputValid1 ;
OutputValid1 <= InputValid ;
Constant1[15:0] <= Constant[15:0] ;
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
Real1[15:0] <= {(16){1'b0}} ;
Imag1[15:0] <= {(16){1'b0}} ;
Real2[15:0] <= {(16){1'b0}} ;
Imag2[15:0] <= {(16){1'b0}} ;
Real3[15:0] <= {(16){1'b0}} ;
Imag3[15:0] <= {(16){1'b0}} ;
end
else
begin
Real1[15:0] <= Real_1[29:14];
Imag1[15:0] <= Imag_1[29:14];
Real2[15:0] <= Real_2[29:14];
Imag2[15:0] <= Imag_2[29:14];
Real3[15:0] <= Real_3[29:14];
Imag3[15:0] <= Imag_3[29:14];
end
assign Real_1[31:0] = Cosine1 * Constant1 ;
assign Imag_1[31:0] = Sine1 * Constant1 ;
assign Real_2[31:0] = Cosine2 * Constant1 ;
assign Imag_2[31:0] = Sine2 * Constant1 ;
assign Real_3[31:0] = Cosine3 * Constant1 ;
assign Imag_3[31:0] = Sine3 * Constant1 ;
assign tp_1 = OutputValid1 ;
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
LkupTbl1 LkupTbl1 // Channel1 Sin/Cos Table Lookup
(.cntr (counter1), // Bus [9 : 0]
.CLK (CLK),
.ARST (ARST),
.sine (Sine1), // Bus [15 : 0]
.cosine (Cosine1) // Bus [15:0]
);
LkupTbl2 LkupTbl2 // Noise Sin/Cos Table Lookup
(.cntr (counter2), // Bus [9 : 0]
.CLK (CLK),
.ARST (ARST),
.sine (Sine2), // Bus [15 : 0]
.cosine (Cosine2) // Bus [15:0]
);
LkupTbl3 LkupTbl3 // Channel2 Sin/Cos Table Lookup
(.cntr (counter1), // Bus [9 : 0]
.CLK (CLK),
.ARST (ARST),
.sine (Sine3), // Bus [15 : 0]
.cosine (Cosine3) // Bus [15:0]
);
endmodule // QM
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : QM_FIR.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Original Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Quadrature Modulation and Polyphase Decimation. ** //
// ** This module gives both the real part and the ** //
// ** ofimaginary part the along with their polyphase ** //
// ** decimation. ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : QM_FIR.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module QM_FIR
(//Inputs
CLK ,
ARST ,
Sync ,
Constant ,
InputValid ,
//Ouputs
RealOut1 ,
ImagOut1 ,
RealOut2 ,
ImagOut2 ,
RealOut3 ,
ImagOut3 ,
DataValid_R,
DataValid_I
);
//*****************************************************************************//
//* Declarations *//
//*****************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
output signed [15:0] RealOut1, RealOut2, RealOut3;
output signed [15:0] ImagOut1, ImagOut2, ImagOut3;
output DataValid_R;
output DataValid_I;
input signed [15:0] Constant;
input CLK;
input ARST;
input Sync;
input InputValid;
// DATA TYPE - WIRES
wire OutputValid_QM;
wire signed [15:0] Real1, Real2, Real3;
wire signed [15:0] Imag1, Imag2, Imag3;
//*****************************************************************************//
//* Submodules *//
//*****************************************************************************//
//Quadrature Modulation
QM QM
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.Constant (Constant),
.InputValid (InputValid),
//Outputs
.Real1 (Real1), // Channel1 Real
.Imag1 (Imag1), // Channel1 Imag
.Real2 (Real2), // Noise Channel Real
.Imag2 (Imag2), // Noise Channel Imag
.Real3 (Real3), // Channel2 Real
.Imag3 (Imag3), // Channel2 Imag
.OutputValid (OutputValid_QM)
//.tp_1(tp_1) // To print out QM output, use this as the DataValid
);
//Firdecim 1st channel Real Filter
firdecim firdecimR1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Real1),
//Outputs
.SigOut (RealOut1),
.DataValid (DataValid_R)
);
//Firdecim 1st channel Imaginary Filter
firdecim firdecimI1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Imag1),
//Outputs
.SigOut (ImagOut1),
.DataValid (DataValid_I)
);
//Firdecim noise channel Real Filter
firdecim firdecimR2
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Real2),
//Outputs
.SigOut (RealOut2)
//.DataValid (DataValid_R)
);
//Firdecim noise channel Imaginary Filter
firdecim firdecimI2
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Imag2),
//Outputs
.SigOut (ImagOut2)
//.DataValid (DataValid_I)
);
//Firdecim 2nd channel Real Filter
firdecim firdecimR3
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Real3),
//Outputs
.SigOut (RealOut3)
//.DataValid (DataValid_R)
);
//Firdecim 2nd channel Imaginary Filter
firdecim firdecimI3
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (OutputValid_QM),
.SigIn (Imag3),
//Outputs
.SigOut (ImagOut3)
//.DataValid (DataValid_I)
);
endmodule // QM_FIR
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter: 3 stages. ** //
// ** FIRDECIM1: M = 5, L = 15 ** //
// ** FIRDECIM1: M = 5, L = 20 ** //
// ** FIRDECIM1: M = 2, L = 50 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim
(//Outputs
SigOut, // Third Stage Output
DataValid,// Third Stage DataValid
//Inputs
CLK,
ARST,
InputValid,
Sync,
SigIn
);
//******************************************************************************//
//* Declarations *//
//******************************************************************************//
//DATA TYPE - INPUTS AND OUTPUTS
output signed [15:0] SigOut ;
output DataValid;
input CLK;
input ARST;
input Sync;
input InputValid;
input signed [15:0] SigIn;
// DATA TYPE - WIRES
wire signed [31:0] SigOut1, SigOut_tmp, SigOut2;
//******************************************************************************//
//* Output Buffers *//
//******************************************************************************//
assign SigOut[15:0] = SigOut_tmp[29:14];
//******************************************************************************//
//* Submodules *//
//******************************************************************************//
// First firdecim filter
firdecim_m5_n15 firdecim1
(//Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (InputValid),
.SigIn (SigIn),
//Outputs
.DataValid (DataValid1),
.SigOut (SigOut1)
);
// Second firdecim filter
firdecim_m5_n20 firdecim2
(// Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (DataValid1),
.SigIn (SigOut1[29:14]),
// Outputs
.DataValid (DataValid2),
.SigOut (SigOut2[31:0])
);
// Third firdecim filter
firdecim_m2_n50 firdecim3
(// Inputs
.CLK (CLK),
.ARST (ARST),
.Sync (Sync),
.InputValid (DataValid2),
.SigIn (SigOut2[29:14]),
// Outputs
.DataValid (DataValid),
.SigOut (SigOut_tmp[31:0])
);
endmodule // firdecim
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m2_n50.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter ** //
// ** M = 2, L = 50 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim_m2_n50.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim_m2_n50
(// Input
CLK,
ARST,
Sync,
InputValid,
SigIn,
// Output
DataValid,
SigOut
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter e49 = 16'sb0000_0000_0010_1001;
parameter e48 = 16'sb0000_0000_0001_0010;
parameter e47 = 16'sb1111_1111_1010_0000;
parameter e46 = 16'sb1111_1111_0011_1100;
parameter e45 = 16'sb1111_1111_1000_1011;
parameter e44 = 16'sb0000_0000_0100_1010;
parameter e43 = 16'sb0000_0000_0110_1011;
parameter e42 = 16'sb1111_1111_1010_1110;
parameter e41 = 16'sb1111_1111_0100_1101;
parameter e40 = 16'sb0000_0000_0010_0000;
parameter e39 = 16'sb0000_0000_1110_1110;
parameter e38 = 16'sb0000_0000_0010_1101;
parameter e37 = 16'sb1111_1110_1101_1101;
parameter e36 = 16'sb1111_1111_0101_1000;
parameter e35 = 16'sb0000_0001_0011_1100;
parameter e34 = 16'sb0000_0001_0101_0100;
parameter e33 = 16'sb1111_1110_1101_1011;
parameter e32 = 16'sb1111_1101_1100_0101;
parameter e31 = 16'sb0000_0000_1011_1100;
parameter e30 = 16'sb0000_0011_0111_1011;
parameter e29 = 16'sb0000_0000_0100_1000;
parameter e28 = 16'sb1111_1010_0111_0101;
parameter e27 = 16'sb1111_1100_1111_1001;
parameter e26 = 16'sb0000_1011_1000_1111;
parameter e25 = 16'sb0001_1010_0110_0111;
parameter e24 = 16'sb0001_1010_0110_0111;
parameter e23 = 16'sb0000_1011_1000_1111;
parameter e22 = 16'sb1111_1100_1111_1001;
parameter e21 = 16'sb1111_1010_0111_0101;
parameter e20 = 16'sb0000_0000_0100_1000;
parameter e19 = 16'sb0000_0011_0111_1011;
parameter e18 = 16'sb0000_0000_1011_1100;
parameter e17 = 16'sb1111_1101_1100_0101;
parameter e16 = 16'sb1111_1110_1101_1011;
parameter e15 = 16'sb0000_0001_0101_0100;
parameter e14 = 16'sb0000_0001_0011_1100;
parameter e13 = 16'sb1111_1111_0101_1000;
parameter e12 = 16'sb1111_1110_1101_1101;
parameter e11 = 16'sb0000_0000_0010_1101;
parameter e10 = 16'sb0000_0000_1110_1110;
parameter e9 = 16'sb0000_0000_0010_0000;
parameter e8 = 16'sb1111_1111_0100_1101;
parameter e7 = 16'sb1111_1111_1010_1110;
parameter e6 = 16'sb0000_0000_0110_1011;
parameter e5 = 16'sb0000_0000_0100_1010;
parameter e4 = 16'sb1111_1111_1000_1011;
parameter e3 = 16'sb1111_1111_0011_1100;
parameter e2 = 16'sb1111_1111_1010_0000;
parameter e1 = 16'sb0000_0000_0001_0010;
parameter e0 = 16'sb0000_0000_0010_1001;
parameter OWIDTH = 32 ; // output bit width
parameter IWIDTH = 16 ; // input bit width
parameter AWIDTH = 32 ; // internal bit width
parameter NTAPS = 50 ; // number of filter taps
parameter ACCUMCNTWIDTH = 5 ; // accumulator count bit width
parameter CNTWIDTH = 6 ; // counter bit width
parameter NACCUM = 25 ; // numbers of accumulators
// DATA TYPE - INPUTS AND OUTPUTS
output reg signed [OWIDTH-1:0] SigOut ;
output reg DataValid ;
input CLK ; // 60MHz Clock
input ARST ;
input InputValid ;
input signed [IWIDTH-1:0] SigIn ;
input Sync ;
// DATA TYPE - REGISTERS
reg signed [IWIDTH-1:0] coe49 ;
reg signed [IWIDTH-1:0] coe48 ;
reg signed [IWIDTH-1:0] coe47 ;
reg signed [IWIDTH-1:0] coe46 ;
reg signed [IWIDTH-1:0] coe45 ;
reg signed [IWIDTH-1:0] coe44 ;
reg signed [IWIDTH-1:0] coe43 ;
reg signed [IWIDTH-1:0] coe42 ;
reg signed [IWIDTH-1:0] coe41 ;
reg signed [IWIDTH-1:0] coe40 ;
reg signed [IWIDTH-1:0] coe39 ;
reg signed [IWIDTH-1:0] coe38 ;
reg signed [IWIDTH-1:0] coe37 ;
reg signed [IWIDTH-1:0] coe36 ;
reg signed [IWIDTH-1:0] coe35 ;
reg signed [IWIDTH-1:0] coe34 ;
reg signed [IWIDTH-1:0] coe33 ;
reg signed [IWIDTH-1:0] coe32 ;
reg signed [IWIDTH-1:0] coe31 ;
reg signed [IWIDTH-1:0] coe30 ;
reg signed [IWIDTH-1:0] coe29 ;
reg signed [IWIDTH-1:0] coe28 ;
reg signed [IWIDTH-1:0] coe27 ;
reg signed [IWIDTH-1:0] coe26 ;
reg signed [IWIDTH-1:0] coe25 ;
reg signed [IWIDTH-1:0] coe24 ;
reg signed [IWIDTH-1:0] coe23 ;
reg signed [IWIDTH-1:0] coe22 ;
reg signed [IWIDTH-1:0] coe21 ;
reg signed [IWIDTH-1:0] coe20 ;
reg signed [IWIDTH-1:0] coe19 ;
reg signed [IWIDTH-1:0] coe18 ;
reg signed [IWIDTH-1:0] coe17 ;
reg signed [IWIDTH-1:0] coe16 ;
reg signed [IWIDTH-1:0] coe15 ;
reg signed [IWIDTH-1:0] coe14 ;
reg signed [IWIDTH-1:0] coe13 ;
reg signed [IWIDTH-1:0] coe12 ;
reg signed [IWIDTH-1:0] coe11 ;
reg signed [IWIDTH-1:0] coe10 ;
reg signed [IWIDTH-1:0] coe9 ;
reg signed [IWIDTH-1:0] coe8 ;
reg signed [IWIDTH-1:0] coe7 ;
reg signed [IWIDTH-1:0] coe6 ;
reg signed [IWIDTH-1:0] coe5 ;
reg signed [IWIDTH-1:0] coe4 ;
reg signed [IWIDTH-1:0] coe3 ;
reg signed [IWIDTH-1:0] coe2 ;
reg signed [IWIDTH-1:0] coe1 ;
reg signed [IWIDTH-1:0] coe0 ;
reg [CNTWIDTH-1:0] count ;
reg [CNTWIDTH-1:0] count1 ;
reg [ACCUMCNTWIDTH-1:0] accum_cnt ; //Counter to keep track of which
//accumulator is being accessed.
reg InputValid0 ;
reg InputValid1;
reg signed [IWIDTH-1:0] SigIn1 ;
reg signed [IWIDTH-1:0] SigIn2 ;
reg signed [AWIDTH-1:0] mult ;
reg signed [AWIDTH-1:0] accum1 ; //First accumulator
reg signed [AWIDTH-1:0] accum2 ; //Second accumulator
reg signed [AWIDTH-1:0] accum3 ; //Rhird accumulator
reg signed [AWIDTH-1:0] accum4 ; //Fourth accumulator
reg signed [AWIDTH-1:0] accum5 ; //Fifth accumulator
reg signed [AWIDTH-1:0] accum6 ; //Sixth accumulator
reg signed [AWIDTH-1:0] accum7 ; //Seventh accumulator
reg signed [AWIDTH-1:0] accum8 ; //Eigth accumulator
reg signed [AWIDTH-1:0] accum9 ; //Ninth accumulator
reg signed [AWIDTH-1:0] accum10 ; //Tenth accumulator
reg signed [AWIDTH-1:0] accum11 ; //Eleventh accumulator
reg signed [AWIDTH-1:0] accum12 ; //Twelve accumulator
reg signed [AWIDTH-1:0] accum13 ; //Thirteenth accumulator
reg signed [AWIDTH-1:0] accum14 ; //Fourteenth accumulator
reg signed [AWIDTH-1:0] accum15 ; //Fifteenth accumulator
reg signed [AWIDTH-1:0] accum16 ; //Sixteenth accumulator
reg signed [AWIDTH-1:0] accum17 ; //Seventeenth accumulator
reg signed [AWIDTH-1:0] accum18 ; //Eighteenth accumulator
reg signed [AWIDTH-1:0] accum19 ; //Ninteenth accumulator
reg signed [AWIDTH-1:0] accum20 ; //20th accumulator
reg signed [AWIDTH-1:0] accum21 ; //21st accumulator
reg signed [AWIDTH-1:0] accum22 ; //22nd accumulator
reg signed [AWIDTH-1:0] accum23 ; //23rd accumulator
reg signed [AWIDTH-1:0] accum24 ; //24th accumulator
reg signed [AWIDTH-1:0] accum25 ; //25th accumulator
reg signed [IWIDTH-1:0] coef1 ;
reg signed [IWIDTH-1:0] coef2 ;
reg signed [IWIDTH-1:0] coef3 ;
reg signed [IWIDTH-1:0] coef4 ;
reg signed [IWIDTH-1:0] coef ;
reg [ACCUMCNTWIDTH-1:0] accum_cnt1 ;
// DATA TYPE - WIRES
wire valid ;
wire valid1 ;
wire valid2 ;
wire valid3 ;
wire valid4 ;
wire valid5 ;
wire valid6 ;
wire valid7 ;
wire valid8 ;
wire valid9 ;
wire valid10 ;
wire valid11 ;
wire valid12 ;
wire valid13 ;
wire valid14 ;
wire valid15 ;
wire valid16 ;
wire valid17 ;
wire valid18 ;
wire valid19 ;
wire valid20 ;
wire valid21 ;
wire valid22 ;
wire valid23 ;
wire valid24 ;
wire valid25 ;
//**************************************************************************//
//* Input Buffers *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
InputValid0 <= 1'b0 ;
InputValid1 <= 1'b0 ;
end
else
begin
InputValid0 <= InputValid1;
InputValid1 <= InputValid ;
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
SigIn1[IWIDTH-1:0] <= {(IWIDTH){1'b0}} ;
SigIn2[IWIDTH-1:0] <= {(IWIDTH){1'b0}};
end
else
begin
SigIn2[IWIDTH-1:0] <= SigIn[IWIDTH-1:0];
SigIn1[IWIDTH-1:0] <= SigIn2[IWIDTH-1:0];
end
//**************************************************************************//
//* Coefficient Rotation / Selector *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
coef1[IWIDTH-1:0] <= {(IWIDTH){1'b0}} ;
else
case (accum_cnt[2:0])
3'b000: coef1[IWIDTH-1:0] <= coe0[IWIDTH-1:0];
3'b001: coef1[IWIDTH-1:0] <= coe2[IWIDTH-1:0];
3'b010: coef1[IWIDTH-1:0] <= coe4[IWIDTH-1:0];
3'b011: coef1[IWIDTH-1:0] <= coe6[IWIDTH-1:0];
3'b100: coef1[IWIDTH-1:0] <= coe8[IWIDTH-1:0];
3'b101: coef1[IWIDTH-1:0] <= coe10[IWIDTH-1:0];
3'b110: coef1[IWIDTH-1:0] <= coe12[IWIDTH-1:0];
3'b111: coef1[IWIDTH-1:0] <= coe14[IWIDTH-1:0];
endcase // case (accum_cnt[2:0])
always @ (posedge CLK or posedge ARST)
if (ARST)
coef2[IWIDTH-1:0] <= {(IWIDTH){1'b0}};
else
case (accum_cnt[2:0])
3'b000: coef2[IWIDTH-1:0] <= coe16[IWIDTH-1:0];
3'b001: coef2[IWIDTH-1:0] <= coe18[IWIDTH-1:0];
3'b010: coef2[IWIDTH-1:0] <= coe20[IWIDTH-1:0];
3'b011: coef2[IWIDTH-1:0] <= coe22[IWIDTH-1:0];
3'b100: coef2[IWIDTH-1:0] <= coe24[IWIDTH-1:0];
3'b101: coef2[IWIDTH-1:0] <= coe26[IWIDTH-1:0];
3'b110: coef2[IWIDTH-1:0] <= coe28[IWIDTH-1:0];
3'b111: coef2[IWIDTH-1:0] <= coe30[IWIDTH-1:0];
endcase // case (accumt_cnt[2:0])
always @ (posedge CLK or posedge ARST)
if (ARST)
coef3[IWIDTH-1:0] <= {(IWIDTH){1'b0}};
else
case (accum_cnt[2:0])
3'b000: coef3[IWIDTH-1:0] <= coe32[IWIDTH-1:0];
3'b001: coef3[IWIDTH-1:0] <= coe34[IWIDTH-1:0];
3'b010: coef3[IWIDTH-1:0] <= coe36[IWIDTH-1:0];
3'b011: coef3[IWIDTH-1:0] <= coe38[IWIDTH-1:0];
3'b100: coef3[IWIDTH-1:0] <= coe40[IWIDTH-1:0];
3'b101: coef3[IWIDTH-1:0] <= coe42[IWIDTH-1:0];
3'b110: coef3[IWIDTH-1:0] <= coe44[IWIDTH-1:0];
3'b111: coef3[IWIDTH-1:0] <= coe46[IWIDTH-1:0];
endcase // case (accumt_cnt[2:0])
always @ (posedge CLK or posedge ARST)
if (ARST) coef4[IWIDTH-1:0] <= {(IWIDTH){1'b0}} ;
else coef4[IWIDTH-1:0] <= coe48[IWIDTH-1:0] ;
always @ (accum_cnt1 or coef1 or coef2 or coef3 or coef4)
begin
case (accum_cnt1[4:3])
2'b00: coef[IWIDTH-1:0] = coef1[IWIDTH-1:0];
2'b01: coef[IWIDTH-1:0] = coef2[IWIDTH-1:0];
2'b10: coef[IWIDTH-1:0] = coef3[IWIDTH-1:0];
2'b11: coef[IWIDTH-1:0] = coef4[IWIDTH-1:0];
default: coef[IWIDTH-1:0] = coef4[IWIDTH-1:0];
endcase // case (accum_cnt[4:3])
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe49[IWIDTH-1:0] <= e48 ;
coe48[IWIDTH-1:0] <= e47 ;
coe47[IWIDTH-1:0] <= e46 ;
coe46[IWIDTH-1:0] <= e45 ;
coe45[IWIDTH-1:0] <= e44 ;
coe44[IWIDTH-1:0] <= e43 ;
coe43[IWIDTH-1:0] <= e42 ;
coe42[IWIDTH-1:0] <= e41 ;
coe41[IWIDTH-1:0] <= e40 ;
coe40[IWIDTH-1:0] <= e39 ;
coe39[IWIDTH-1:0] <= e38 ;
coe38[IWIDTH-1:0] <= e37 ;
coe37[IWIDTH-1:0] <= e36 ;
coe36[IWIDTH-1:0] <= e35 ;
coe35[IWIDTH-1:0] <= e34 ;
coe34[IWIDTH-1:0] <= e33 ;
coe33[IWIDTH-1:0] <= e32 ;
coe32[IWIDTH-1:0] <= e31 ;
coe31[IWIDTH-1:0] <= e30 ;
coe30[IWIDTH-1:0] <= e29 ;
coe29[IWIDTH-1:0] <= e28 ;
coe28[IWIDTH-1:0] <= e27 ;
coe27[IWIDTH-1:0] <= e26 ;
coe26[IWIDTH-1:0] <= e25 ;
coe25[IWIDTH-1:0] <= e24 ;
coe24[IWIDTH-1:0] <= e23 ;
coe23[IWIDTH-1:0] <= e22 ;
coe22[IWIDTH-1:0] <= e21 ;
coe21[IWIDTH-1:0] <= e20 ;
coe20[IWIDTH-1:0] <= e19 ;
coe19[IWIDTH-1:0] <= e18 ;
coe18[IWIDTH-1:0] <= e17 ;
coe17[IWIDTH-1:0] <= e16 ;
coe16[IWIDTH-1:0] <= e15 ;
coe15[IWIDTH-1:0] <= e14 ;
coe14[IWIDTH-1:0] <= e13 ;
coe13[IWIDTH-1:0] <= e12 ;
coe12[IWIDTH-1:0] <= e11 ;
coe11[IWIDTH-1:0] <= e10 ;
coe10[IWIDTH-1:0] <= e9 ;
coe9[IWIDTH-1:0] <= e8 ;
coe8[IWIDTH-1:0] <= e7 ;
coe7[IWIDTH-1:0] <= e6 ;
coe6[IWIDTH-1:0] <= e5 ;
coe5[IWIDTH-1:0] <= e4 ;
coe4[IWIDTH-1:0] <= e3 ;
coe3[IWIDTH-1:0] <= e2 ;
coe2[IWIDTH-1:0] <= e1 ;
coe1[IWIDTH-1:0] <= e0 ;
coe0[IWIDTH-1:0] <= e49 ;
end // if (ARST)
else if (Sync)
begin
coe49[IWIDTH-1:0] <= e48 ;
coe48[IWIDTH-1:0] <= e47 ;
coe47[IWIDTH-1:0] <= e46 ;
coe46[IWIDTH-1:0] <= e45 ;
coe45[IWIDTH-1:0] <= e44 ;
coe44[IWIDTH-1:0] <= e43 ;
coe43[IWIDTH-1:0] <= e42 ;
coe42[IWIDTH-1:0] <= e41 ;
coe41[IWIDTH-1:0] <= e40 ;
coe40[IWIDTH-1:0] <= e39 ;
coe39[IWIDTH-1:0] <= e38 ;
coe38[IWIDTH-1:0] <= e37 ;
coe37[IWIDTH-1:0] <= e36 ;
coe36[IWIDTH-1:0] <= e35 ;
coe35[IWIDTH-1:0] <= e34 ;
coe34[IWIDTH-1:0] <= e33 ;
coe33[IWIDTH-1:0] <= e32 ;
coe32[IWIDTH-1:0] <= e31 ;
coe31[IWIDTH-1:0] <= e30 ;
coe30[IWIDTH-1:0] <= e29 ;
coe29[IWIDTH-1:0] <= e28 ;
coe28[IWIDTH-1:0] <= e27 ;
coe27[IWIDTH-1:0] <= e26 ;
coe26[IWIDTH-1:0] <= e25 ;
coe25[IWIDTH-1:0] <= e24 ;
coe24[IWIDTH-1:0] <= e23 ;
coe23[IWIDTH-1:0] <= e22 ;
coe22[IWIDTH-1:0] <= e21 ;
coe21[IWIDTH-1:0] <= e20 ;
coe20[IWIDTH-1:0] <= e19 ;
coe19[IWIDTH-1:0] <= e18 ;
coe18[IWIDTH-1:0] <= e17 ;
coe17[IWIDTH-1:0] <= e16 ;
coe16[IWIDTH-1:0] <= e15 ;
coe15[IWIDTH-1:0] <= e14 ;
coe14[IWIDTH-1:0] <= e13 ;
coe13[IWIDTH-1:0] <= e12 ;
coe12[IWIDTH-1:0] <= e11 ;
coe11[IWIDTH-1:0] <= e10 ;
coe10[IWIDTH-1:0] <= e9 ;
coe9[IWIDTH-1:0] <= e8 ;
coe8[IWIDTH-1:0] <= e7 ;
coe7[IWIDTH-1:0] <= e6 ;
coe6[IWIDTH-1:0] <= e5 ;
coe5[IWIDTH-1:0] <= e4 ;
coe4[IWIDTH-1:0] <= e3 ;
coe3[IWIDTH-1:0] <= e2 ;
coe2[IWIDTH-1:0] <= e1 ;
coe1[IWIDTH-1:0] <= e0 ;
coe0[IWIDTH-1:0] <= e49 ;
end
else if (InputValid)
begin
coe49[IWIDTH-1:0] <= coe0[IWIDTH-1:0];
coe48[IWIDTH-1:0] <= coe49[IWIDTH-1:0] ;
coe47[IWIDTH-1:0] <= coe48[IWIDTH-1:0] ;
coe46[IWIDTH-1:0] <= coe47[IWIDTH-1:0] ;
coe45[IWIDTH-1:0] <= coe46[IWIDTH-1:0] ;
coe44[IWIDTH-1:0] <= coe45[IWIDTH-1:0] ;
coe43[IWIDTH-1:0] <= coe44[IWIDTH-1:0] ;
coe42[IWIDTH-1:0] <= coe43[IWIDTH-1:0] ;
coe41[IWIDTH-1:0] <= coe42[IWIDTH-1:0] ;
coe40[IWIDTH-1:0] <= coe41[IWIDTH-1:0] ;
coe39[IWIDTH-1:0] <= coe40[IWIDTH-1:0] ;
coe38[IWIDTH-1:0] <= coe39[IWIDTH-1:0] ;
coe37[IWIDTH-1:0] <= coe38[IWIDTH-1:0] ;
coe36[IWIDTH-1:0] <= coe37[IWIDTH-1:0] ;
coe35[IWIDTH-1:0] <= coe36[IWIDTH-1:0] ;
coe34[IWIDTH-1:0] <= coe35[IWIDTH-1:0] ;
coe33[IWIDTH-1:0] <= coe34[IWIDTH-1:0] ;
coe32[IWIDTH-1:0] <= coe33[IWIDTH-1:0] ;
coe31[IWIDTH-1:0] <= coe32[IWIDTH-1:0] ;
coe30[IWIDTH-1:0] <= coe31[IWIDTH-1:0] ;
coe29[IWIDTH-1:0] <= coe30[IWIDTH-1:0] ;
coe28[IWIDTH-1:0] <= coe29[IWIDTH-1:0] ;
coe27[IWIDTH-1:0] <= coe28[IWIDTH-1:0] ;
coe26[IWIDTH-1:0] <= coe27[IWIDTH-1:0] ;
coe25[IWIDTH-1:0] <= coe26[IWIDTH-1:0] ;
coe24[IWIDTH-1:0] <= coe25[IWIDTH-1:0] ;
coe23[IWIDTH-1:0] <= coe24[IWIDTH-1:0] ;
coe22[IWIDTH-1:0] <= coe23[IWIDTH-1:0] ;
coe21[IWIDTH-1:0] <= coe22[IWIDTH-1:0] ;
coe20[IWIDTH-1:0] <= coe21[IWIDTH-1:0] ;
coe19[IWIDTH-1:0] <= coe20[IWIDTH-1:0] ;
coe18[IWIDTH-1:0] <= coe19[IWIDTH-1:0] ;
coe17[IWIDTH-1:0] <= coe18[IWIDTH-1:0] ;
coe16[IWIDTH-1:0] <= coe17[IWIDTH-1:0] ;
coe15[IWIDTH-1:0] <= coe16[IWIDTH-1:0] ;
coe14[IWIDTH-1:0] <= coe15[IWIDTH-1:0] ;
coe13[IWIDTH-1:0] <= coe14[IWIDTH-1:0] ;
coe12[IWIDTH-1:0] <= coe13[IWIDTH-1:0] ;
coe11[IWIDTH-1:0] <= coe12[IWIDTH-1:0] ;
coe10[IWIDTH-1:0] <= coe11[IWIDTH-1:0] ;
coe9[IWIDTH-1:0] <= coe10[IWIDTH-1:0] ;
coe8[IWIDTH-1:0] <= coe9[IWIDTH-1:0] ;
coe7[IWIDTH-1:0] <= coe8[IWIDTH-1:0] ;
coe6[IWIDTH-1:0] <= coe7[IWIDTH-1:0] ;
coe5[IWIDTH-1:0] <= coe6[IWIDTH-1:0] ;
coe4[IWIDTH-1:0] <= coe5[IWIDTH-1:0] ;
coe3[IWIDTH-1:0] <= coe4[IWIDTH-1:0] ;
coe2[IWIDTH-1:0] <= coe3[IWIDTH-1:0] ;
coe1[IWIDTH-1:0] <= coe2[IWIDTH-1:0] ;
coe0[IWIDTH-1:0] <= coe1[IWIDTH-1:0] ;
end // else: !if(ARST)
//**************************************************************************//
//* Counters *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
accum_cnt[ACCUMCNTWIDTH-1:0] <= {(ACCUMCNTWIDTH){1'b0}} ;
else
accum_cnt[ACCUMCNTWIDTH-1:0] <= (InputValid & ~InputValid0) ?
0:
(accum_cnt == NACCUM+1) ? (NACCUM+1)
: accum_cnt[ACCUMCNTWIDTH-1:0] + 1 ;
always @ (posedge CLK or posedge ARST)
if (ARST)
count1[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else if (InputValid & ~InputValid1)
count1[CNTWIDTH-1:0] <= (count[CNTWIDTH-1:0] == NTAPS-1) ? 0
: count[CNTWIDTH-1:0] + 1 ;
always @ (posedge CLK or posedge ARST)
if (ARST) accum_cnt1[ACCUMCNTWIDTH-1:0] <= {(ACCUMCNTWIDTH){1'b0}} ;
else accum_cnt1[ACCUMCNTWIDTH-1:0] <= accum_cnt[ACCUMCNTWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST) count[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else count[CNTWIDTH-1:0] <= count1[CNTWIDTH-1:0] ;
//**************************************************************************//
//* Coefficient Rotation / Selector *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST) mult[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else mult[AWIDTH-1:0] <= coef * SigIn1 ; // Signed multiplication
always @ (posedge CLK or posedge ARST)
if (ARST)
accum1[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 1)
accum1[AWIDTH-1:0] <= (count == 1) ? mult
: mult[AWIDTH-1:0] + accum1[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum2[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 2)
accum2[AWIDTH-1:0] <= (count == 49) ? mult
: mult[AWIDTH-1:0] + accum2[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum3[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 3)
accum3[AWIDTH-1:0] <= (count == 47) ? mult
: mult[AWIDTH-1:0] + accum3[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum4[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 4)
accum4[AWIDTH-1:0] <= (count == 45) ? mult
: mult[AWIDTH-1:0] + accum4[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum5[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 5)
accum5[AWIDTH-1:0] <= (count == 43) ? mult
: mult[AWIDTH-1:0] + accum5[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum6[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 6)
accum6[AWIDTH-1:0] <= (count == 41) ? mult
: mult[AWIDTH-1:0] + accum6[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum7[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 7)
accum7[AWIDTH-1:0] <= (count == 39) ? mult
: mult[AWIDTH-1:0] + accum7[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum8[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 8)
accum8[AWIDTH-1:0] <= (count == 37) ? mult
: mult[AWIDTH-1:0] + accum8[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum9[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] ==9)
accum9[AWIDTH-1:0] <= (count == 35) ? mult
: mult[AWIDTH-1:0] + accum9[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum10[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] ==10)
accum10[AWIDTH-1:0] <= (count == 33) ? mult
: mult[AWIDTH-1:0] + accum10[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum11[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 11)
accum11[AWIDTH-1:0] <= (count == 31) ? mult
: mult[AWIDTH-1:0] + accum11[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum12[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 12)
accum12[AWIDTH-1:0] <= (count == 29) ? mult
: mult[AWIDTH-1:0] + accum12[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum13[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 13)
accum13[AWIDTH-1:0] <= (count == 27) ? mult
: mult[AWIDTH-1:0] + accum13[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum14[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 14)
accum14[AWIDTH-1:0] <= (count == 25) ? mult
: mult[AWIDTH-1:0] + accum14[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum15[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 15)
accum15[AWIDTH-1:0] <= (count == 23) ? mult
: mult[AWIDTH-1:0] + accum15[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum16[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 16)
accum16[AWIDTH-1:0] <= (count == 21) ? mult
: mult[AWIDTH-1:0] + accum16[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum17[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 17)
accum17[AWIDTH-1:0] <= (count == 19) ? mult
: mult[AWIDTH-1:0] + accum17[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum18[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] ==18)
accum18[AWIDTH-1:0] <= (count == 17) ? mult
: mult[AWIDTH-1:0] + accum18[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum19[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 19)
accum19[AWIDTH-1:0] <= (count == 15) ? mult
: mult[AWIDTH-1:0] + accum19[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum20[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 20)
accum20[AWIDTH-1:0] <= (count == 13) ? mult
: mult[AWIDTH-1:0] + accum20[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum21[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 21)
accum21[AWIDTH-1:0] <= (count == 11) ? mult
: mult[AWIDTH-1:0] + accum21[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum22[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 22)
accum22[AWIDTH-1:0] <= (count == 9) ? mult
: mult[AWIDTH-1:0] + accum22[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum23[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 23)
accum23[AWIDTH-1:0] <= (count == 7) ? mult
: mult[AWIDTH-1:0] + accum23[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum24[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 24)
accum24[AWIDTH-1:0] <= (count == 5) ? mult
: mult[AWIDTH-1:0] + accum24[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum25[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt1[ACCUMCNTWIDTH-1:0] == 0)
accum25[AWIDTH-1:0] <= (count == 4) ? mult
: mult[AWIDTH-1:0] + accum25[AWIDTH-1:0] ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
assign valid1 = (count[CNTWIDTH-1:0] == 1) & (accum_cnt1 == 1) ;
assign valid2 = (count[CNTWIDTH-1:0] == 49) & (accum_cnt1 == 1) ;
assign valid3 = (count[CNTWIDTH-1:0] == 47) & (accum_cnt1 == 1) ;
assign valid4 = (count[CNTWIDTH-1:0] == 45) & (accum_cnt1 == 1) ;
assign valid5 = (count[CNTWIDTH-1:0] == 43) & (accum_cnt1 == 1) ;
assign valid6 = (count[CNTWIDTH-1:0] == 41) & (accum_cnt1 == 1) ;
assign valid7 = (count[CNTWIDTH-1:0] == 39) & (accum_cnt1 == 1) ;
assign valid8 = (count[CNTWIDTH-1:0] == 37) & (accum_cnt1 == 1) ;
assign valid9 = (count[CNTWIDTH-1:0] == 35) & (accum_cnt1 == 1) ;
assign valid10 = (count[CNTWIDTH-1:0] == 33) & (accum_cnt1 == 1) ;
assign valid11 = (count[CNTWIDTH-1:0] == 31) & (accum_cnt1 == 1) ;
assign valid12 = (count[CNTWIDTH-1:0] == 29) & (accum_cnt1 == 1) ;
assign valid13 = (count[CNTWIDTH-1:0] == 27) & (accum_cnt1 == 1) ;
assign valid14 = (count[CNTWIDTH-1:0] == 25) & (accum_cnt1 == 1) ;
assign valid15 = (count[CNTWIDTH-1:0] == 23) & (accum_cnt1 == 1) ;
assign valid16 = (count[CNTWIDTH-1:0] == 21) & (accum_cnt1 == 1) ;
assign valid17 = (count[CNTWIDTH-1:0] == 19) & (accum_cnt1 == 1) ;
assign valid18 = (count[CNTWIDTH-1:0] == 17) & (accum_cnt1 == 1) ;
assign valid19 = (count[CNTWIDTH-1:0] == 15) & (accum_cnt1 == 1) ;
assign valid20 = (count[CNTWIDTH-1:0] == 13) & (accum_cnt1 == 1) ;
assign valid21 = (count[CNTWIDTH-1:0] == 11) & (accum_cnt1 == 1) ;
assign valid22 = (count[CNTWIDTH-1:0] == 9) & (accum_cnt1 == 1) ;
assign valid23 = (count[CNTWIDTH-1:0] == 7) & (accum_cnt1 == 1) ;
assign valid24 = (count[CNTWIDTH-1:0] == 5) & (accum_cnt1 == 1) ;
assign valid25 = (count[CNTWIDTH-1:0] == 3) & (accum_cnt1 == 1) ;
assign valid = valid1 | valid2 | valid3 | valid4 | valid5 | valid6 |
valid7 | valid8 | valid9 | valid10 | valid11 | valid12 |
valid13 | valid14 | valid15 | valid16 | valid17 | valid18 |
valid19 | valid20 | valid21 | valid22 | valid23 | valid24 |
valid25;
always @ (posedge CLK or posedge ARST)
if (ARST)
SigOut[OWIDTH-1:0] <= {(OWIDTH){1'b0}} ;
else if (valid)
SigOut[OWIDTH-1:0] <= (accum1[AWIDTH-1:0] & {(AWIDTH){ valid1 }}) |
(accum2[AWIDTH-1:0] & {(AWIDTH){ valid2 }}) |
(accum3[AWIDTH-1:0] & {(AWIDTH){ valid3 }}) |
(accum4[AWIDTH-1:0] & {(AWIDTH){ valid4 }}) |
(accum5[AWIDTH-1:0] & {(AWIDTH){ valid5 }}) |
(accum6[AWIDTH-1:0] & {(AWIDTH){ valid6 }}) |
(accum7[AWIDTH-1:0] & {(AWIDTH){ valid7 }}) |
(accum8[AWIDTH-1:0] & {(AWIDTH){ valid8 }}) |
(accum9[AWIDTH-1:0] & {(AWIDTH){ valid9 }}) |
(accum10[AWIDTH-1:0] & {(AWIDTH){ valid10 }}) |
(accum11[AWIDTH-1:0] & {(AWIDTH){ valid11 }}) |
(accum12[AWIDTH-1:0] & {(AWIDTH){ valid12 }}) |
(accum13[AWIDTH-1:0] & {(AWIDTH){ valid13 }}) |
(accum14[AWIDTH-1:0] & {(AWIDTH){ valid14 }}) |
(accum15[AWIDTH-1:0] & {(AWIDTH){ valid15 }}) |
(accum16[AWIDTH-1:0] & {(AWIDTH){ valid16 }}) |
(accum17[AWIDTH-1:0] & {(AWIDTH){ valid17 }}) |
(accum18[AWIDTH-1:0] & {(AWIDTH){ valid18 }}) |
(accum19[AWIDTH-1:0] & {(AWIDTH){ valid19 }}) |
(accum20[AWIDTH-1:0] & {(AWIDTH){ valid20 }}) |
(accum21[AWIDTH-1:0] & {(AWIDTH){ valid21 }}) |
(accum22[AWIDTH-1:0] & {(AWIDTH){ valid22 }}) |
(accum23[AWIDTH-1:0] & {(AWIDTH){ valid23 }}) |
(accum24[AWIDTH-1:0] & {(AWIDTH){ valid24 }}) |
(accum25[AWIDTH-1:0] & {(AWIDTH){ valid25 }}) ;
always @ (posedge CLK or posedge ARST)
if (ARST) DataValid <= 1'b0 ;
else DataValid <= valid;
endmodule //firdecim_m2_n50// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m5_n15.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter ** //
// ** M = 5, L = 15 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim_m5_n15
(// Outputs
SigOut, DataValid,
// Inputs
CLK, ARST, InputValid, SigIn, Sync
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter e14 = 16'sb0000_0000_0001_1111;
parameter e13 = 16'sb0000_0000_1000_1101;
parameter e12 = 16'sb0000_0001_1000_0010;
parameter e11 = 16'sb0000_0011_0001_1110;
parameter e10 = 16'sb0000_0101_0011_1111;
parameter e9 = 16'sb0000_0111_0111_1000;
parameter e8 = 16'sb0000_1001_0010_1011;
parameter e7 = 16'sb0000_1001_1100_1111;
parameter e6 = 16'sb0000_1001_0010_1011;
parameter e5 = 16'sb0000_0111_0111_1000;
parameter e4 = 16'sb0000_0101_0011_1111;
parameter e3 = 16'sb0000_0011_0001_1110;
parameter e2 = 16'sb0000_0001_1000_0010;
parameter e1 = 16'sb0000_0000_1000_1101;
parameter e0 = 16'sb0000_0000_0001_1111;
parameter OWIDTH = 32 ; // output bit width
parameter IWIDTH = 16 ; // input bit width
parameter NTAPS = 15 ; // number of taps in the filter
parameter CNTWIDTH = 4 ; // counter bit width
// DATA TYPE - INPUTS AND OUTPUTS
output reg signed [OWIDTH-1:0] SigOut ;
output reg DataValid ;
input CLK ; // 60MHz Clock
input ARST ;
input InputValid ;
input signed [IWIDTH-1:0] SigIn ;
input Sync ;
// DATA TYPE - REGISTERS
reg signed [IWIDTH-1:0] coe14 ;
reg signed [IWIDTH-1:0] coe13 ;
reg signed [IWIDTH-1:0] coe12 ;
reg signed [IWIDTH-1:0] coe11 ;
reg signed [IWIDTH-1:0] coe10 ;
reg signed [IWIDTH-1:0] coe9 ;
reg signed [IWIDTH-1:0] coe8 ;
reg signed [IWIDTH-1:0] coe7 ;
reg signed [IWIDTH-1:0] coe6 ;
reg signed [IWIDTH-1:0] coe5 ;
reg signed [IWIDTH-1:0] coe4 ;
reg signed [IWIDTH-1:0] coe3 ;
reg signed [IWIDTH-1:0] coe2 ;
reg signed [IWIDTH-1:0] coe1 ;
reg signed [IWIDTH-1:0] coe0 ;
reg [CNTWIDTH-1:0] count ;
// DATA TYPE - WIRES
wire signed [OWIDTH-1:0] SigOut1 ;
wire signed [OWIDTH-1:0] SigOut2 ;
wire signed [OWIDTH-1:0] SigOut3 ;
wire initialize1 ;
wire initialize2 ;
wire initialize3 ;
wire DataValid1 ;
wire DataValid2 ;
wire DataValid3 ;
//**************************************************************************//
//* Coefficient Rotation *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe14[IWIDTH-1:0] <= e14 ;
coe13[IWIDTH-1:0] <= e13 ;
coe12[IWIDTH-1:0] <= e12 ;
coe11[IWIDTH-1:0] <= e11 ;
coe10[IWIDTH-1:0] <= e10 ;
coe9[IWIDTH-1:0] <= e9 ;
coe8[IWIDTH-1:0] <= e8 ;
coe7[IWIDTH-1:0] <= e7 ;
coe6[IWIDTH-1:0] <= e6 ;
coe5[IWIDTH-1:0] <= e5 ;
coe4[IWIDTH-1:0] <= e4 ;
coe3[IWIDTH-1:0] <= e3 ;
coe2[IWIDTH-1:0] <= e2 ;
coe1[IWIDTH-1:0] <= e1 ;
coe0[IWIDTH-1:0] <= e0 ;
end // if (ARST)
else if (Sync)
begin
coe14[IWIDTH-1:0] <= e14 ;
coe13[IWIDTH-1:0] <= e13 ;
coe12[IWIDTH-1:0] <= e12 ;
coe11[IWIDTH-1:0] <= e11 ;
coe10[IWIDTH-1:0] <= e10 ;
coe9[IWIDTH-1:0] <= e9 ;
coe8[IWIDTH-1:0] <= e8 ;
coe7[IWIDTH-1:0] <= e7 ;
coe6[IWIDTH-1:0] <= e6 ;
coe5[IWIDTH-1:0] <= e5 ;
coe4[IWIDTH-1:0] <= e4 ;
coe3[IWIDTH-1:0] <= e3 ;
coe2[IWIDTH-1:0] <= e2 ;
coe1[IWIDTH-1:0] <= e1 ;
coe0[IWIDTH-1:0] <= e0 ;
end
else if (InputValid)
begin
coe14[IWIDTH-1:0] <= coe0[IWIDTH-1:0] ;
coe13[IWIDTH-1:0] <= coe14[IWIDTH-1:0] ;
coe12[IWIDTH-1:0] <= coe13[IWIDTH-1:0] ;
coe11[IWIDTH-1:0] <= coe12[IWIDTH-1:0] ;
coe10[IWIDTH-1:0] <= coe11[IWIDTH-1:0] ;
coe9[IWIDTH-1:0] <= coe10[IWIDTH-1:0] ;
coe8[IWIDTH-1:0] <= coe9[IWIDTH-1:0] ;
coe7[IWIDTH-1:0] <= coe8[IWIDTH-1:0] ;
coe6[IWIDTH-1:0] <= coe7[IWIDTH-1:0] ;
coe5[IWIDTH-1:0] <= coe6[IWIDTH-1:0] ;
coe4[IWIDTH-1:0] <= coe5[IWIDTH-1:0] ;
coe3[IWIDTH-1:0] <= coe4[IWIDTH-1:0] ;
coe2[IWIDTH-1:0] <= coe3[IWIDTH-1:0] ;
coe1[IWIDTH-1:0] <= coe2[IWIDTH-1:0] ;
coe0[IWIDTH-1:0] <= coe1[IWIDTH-1:0] ;
end
//**************************************************************************//
//* Counter *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
count[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else if (InputValid)
count[CNTWIDTH-1:0] <= (count[CNTWIDTH-1:0] == (NTAPS-1)) ? 0 :
count[CNTWIDTH-1:0] + 1 ;
//**************************************************************************//
//* Reset each MAC *//
//**************************************************************************//
assign initialize1 = (count == 0) ;
assign initialize2 = (count == 5) ;
assign initialize3 = (count == 10) ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
SigOut[OWIDTH-1:0] <= {(OWIDTH){1'b0}};
else if (DataValid1 | DataValid2 | DataValid3)
SigOut[OWIDTH-1:0] <= {(OWIDTH){DataValid1}} & SigOut1 |
{(OWIDTH){DataValid2}} & SigOut2 |
{(OWIDTH){DataValid3}} & SigOut3 ;
always @ (posedge CLK or posedge ARST)
if (ARST) DataValid <= 1'b0 ;
else DataValid <= (DataValid1 | DataValid2 | DataValid3) ;
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
//First MAC
MAC1 MAC1_a
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe0), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize1), // Initialize
//Outputs
.OutData (SigOut1), // Output Data
.output_Valid (DataValid1) // Output Valid
);
// Second MAC
MAC1 MAC1_b
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe10), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize2), // Initialize
//Outputs
.OutData (SigOut2), // Output Data
.output_Valid (DataValid2) // Output Valid
);
// Third MAC
MAC1 MAC1_c
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe5), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize3), // Initialize
//Outputs
.OutData (SigOut3), // Output Data
.output_Valid (DataValid3) // Output Valid
);
endmodule // firdecim_m5_n15
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m5_n20.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter ** //
// ** M = 5, L = 20 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim_m5_n20.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim_m5_n20
(// Input
CLK,
ARST,
Sync,
InputValid,
SigIn,
// Ouput
DataValid,
SigOut
);
//****************************************************************************//
//* Declarations *//
//****************************************************************************//
// DATA TYPE - PARAMETERS
parameter e19 = 16'sb1111_1111_1011_1000;
parameter e18 = 16'sb1111_1111_1000_0110;
parameter e17 = 16'sb1111_1111_0110_1110;
parameter e16 = 16'sb1111_1111_1011_1110;
parameter e15 = 16'sb0000_0000_1011_0011;
parameter e14 = 16'sb0000_0010_0110_1101;
parameter e13 = 16'sb0000_0100_1100_0101;
parameter e12 = 16'sb0000_0111_0101_0101;
parameter e11 = 16'sb0000_1001_1000_0111;
parameter e10 = 16'sb0000_1010_1100_1101;
parameter e9 = 16'sb0000_1010_1100_1101;
parameter e8 = 16'sb0000_1001_1000_0111;
parameter e7 = 16'sb0000_0111_0101_0101;
parameter e6 = 16'sb0000_0100_1100_0101;
parameter e5 = 16'sb0000_0010_0110_1101;
parameter e4 = 16'sb0000_0000_1011_0011;
parameter e3 = 16'sb1111_1111_1011_1110;
parameter e2 = 16'sb1111_1111_0110_1110;
parameter e1 = 16'sb1111_1111_1000_0110;
parameter e0 = 16'sb1111_1111_1011_1000;
parameter OWIDTH = 32 ; // output bit width
parameter IWIDTH = 16 ; // input bit width
parameter AWIDTH = 32 ; // internal bit width
parameter NTAPS = 20 ; // number of filter taps
parameter ACCUMCNTWIDTH = 3 ; // accumulator count bit width
parameter CNTWIDTH = 5 ; // counter bit width
parameter NACCUM = 4 ; // numbers of accumulators
// DATA TYPE - INPUTS AND OUTPUTS
output reg signed [OWIDTH-1:0] SigOut ;
output reg DataValid ;
input CLK ; // 60MHz Clock
input ARST ;
input InputValid ;
input Sync ;
input signed [IWIDTH-1:0] SigIn ;
// DATA TYPE - REGISTERS
reg signed [IWIDTH-1:0] coe19 ;
reg signed [IWIDTH-1:0] coe18 ;
reg signed [IWIDTH-1:0] coe17 ;
reg signed [IWIDTH-1:0] coe16 ;
reg signed [IWIDTH-1:0] coe15 ;
reg signed [IWIDTH-1:0] coe14 ;
reg signed [IWIDTH-1:0] coe13 ;
reg signed [IWIDTH-1:0] coe12 ;
reg signed [IWIDTH-1:0] coe11 ;
reg signed [IWIDTH-1:0] coe10 ;
reg signed [IWIDTH-1:0] coe9 ;
reg signed [IWIDTH-1:0] coe8 ;
reg signed [IWIDTH-1:0] coe7 ;
reg signed [IWIDTH-1:0] coe6 ;
reg signed [IWIDTH-1:0] coe5 ;
reg signed [IWIDTH-1:0] coe4 ;
reg signed [IWIDTH-1:0] coe3 ;
reg signed [IWIDTH-1:0] coe2 ;
reg signed [IWIDTH-1:0] coe1 ;
reg signed [IWIDTH-1:0] coe0 ;
reg [CNTWIDTH-1:0] count ;
reg [ACCUMCNTWIDTH-1:0] accum_cnt ; //Counter to keep track of which
//accumulator is being accessed.
reg signed [IWIDTH-1:0] SigIn1 ;
reg InputValid0 ;
reg signed [AWIDTH-1:0] mult ;
reg signed [AWIDTH-1:0] accum1 ; //First accumulator
reg signed [AWIDTH-1:0] accum2 ; //Second accumulator
reg signed [AWIDTH-1:0] accum3 ; //Third accumulator
reg signed [AWIDTH-1:0] accum4 ; //Fourth accumulator
// DATA TYPE - NETS
wire signed [IWIDTH-1:0] coef ; //Coefficient to be used in the
//multiplier.
wire valid ;
wire valid1 ;
wire valid2 ;
wire valid3 ;
wire valid4 ;
//****************************************************************************//
//* Input Buffers *//
//****************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST) InputValid0 <= 1'b0 ;
else InputValid0 <= InputValid ;
always @ (posedge CLK or posedge ARST)
if (ARST) SigIn1[IWIDTH-1:0] <= {(IWIDTH){1'b0}} ;
else SigIn1[IWIDTH-1:0] <= SigIn[IWIDTH-1:0];
//****************************************************************************//
//* Coefficient Rotation / Selector *//
//****************************************************************************//
assign coef[IWIDTH-1:0] = (accum_cnt[ACCUMCNTWIDTH-1:0] == 0) ? coe0[IWIDTH-1:0] :
((accum_cnt[ACCUMCNTWIDTH-1:0] == 1) ? coe5[IWIDTH-1:0] :
((accum_cnt[ACCUMCNTWIDTH-1:0] == 2) ? coe10[IWIDTH-1:0]
: coe15[IWIDTH-1:0])) ;
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe19[IWIDTH-1:0] <= e18 ;
coe18[IWIDTH-1:0] <= e17 ;
coe17[IWIDTH-1:0] <= e16 ;
coe16[IWIDTH-1:0] <= e15 ;
coe15[IWIDTH-1:0] <= e14 ;
coe14[IWIDTH-1:0] <= e13 ;
coe13[IWIDTH-1:0] <= e12 ;
coe12[IWIDTH-1:0] <= e11 ;
coe11[IWIDTH-1:0] <= e10 ;
coe10[IWIDTH-1:0] <= e9 ;
coe9[IWIDTH-1:0] <= e8 ;
coe8[IWIDTH-1:0] <= e7 ;
coe7[IWIDTH-1:0] <= e6 ;
coe6[IWIDTH-1:0] <= e5 ;
coe5[IWIDTH-1:0] <= e4 ;
coe4[IWIDTH-1:0] <= e3 ;
coe3[IWIDTH-1:0] <= e2 ;
coe2[IWIDTH-1:0] <= e1 ;
coe1[IWIDTH-1:0] <= e0 ;
coe0[IWIDTH-1:0] <= e19 ;
end // if (ARST)
else if (Sync)
begin
coe19[IWIDTH-1:0] <= e18 ;
coe18[IWIDTH-1:0] <= e17 ;
coe17[IWIDTH-1:0] <= e16 ;
coe16[IWIDTH-1:0] <= e15 ;
coe15[IWIDTH-1:0] <= e14 ;
coe14[IWIDTH-1:0] <= e13 ;
coe13[IWIDTH-1:0] <= e12 ;
coe12[IWIDTH-1:0] <= e11 ;
coe11[IWIDTH-1:0] <= e10 ;
coe10[IWIDTH-1:0] <= e9 ;
coe9[IWIDTH-1:0] <= e8 ;
coe8[IWIDTH-1:0] <= e7 ;
coe7[IWIDTH-1:0] <= e6 ;
coe6[IWIDTH-1:0] <= e5 ;
coe5[IWIDTH-1:0] <= e4 ;
coe4[IWIDTH-1:0] <= e3 ;
coe3[IWIDTH-1:0] <= e2 ;
coe2[IWIDTH-1:0] <= e1 ;
coe1[IWIDTH-1:0] <= e0 ;
coe0[IWIDTH-1:0] <= e19 ;
end
else if (InputValid)
begin
coe19[IWIDTH-1:0] <= coe0[IWIDTH-1:0] ;
coe18[IWIDTH-1:0] <= coe19[IWIDTH-1:0] ;
coe17[IWIDTH-1:0] <= coe18[IWIDTH-1:0] ;
coe16[IWIDTH-1:0] <= coe17[IWIDTH-1:0] ;
coe15[IWIDTH-1:0] <= coe16[IWIDTH-1:0] ;
coe14[IWIDTH-1:0] <= coe15[IWIDTH-1:0] ;
coe13[IWIDTH-1:0] <= coe14[IWIDTH-1:0] ;
coe12[IWIDTH-1:0] <= coe13[IWIDTH-1:0] ;
coe11[IWIDTH-1:0] <= coe12[IWIDTH-1:0] ;
coe10[IWIDTH-1:0] <= coe11[IWIDTH-1:0] ;
coe9[IWIDTH-1:0] <= coe10[IWIDTH-1:0] ;
coe8[IWIDTH-1:0] <= coe9[IWIDTH-1:0] ;
coe7[IWIDTH-1:0] <= coe8[IWIDTH-1:0] ;
coe6[IWIDTH-1:0] <= coe7[IWIDTH-1:0] ;
coe5[IWIDTH-1:0] <= coe6[IWIDTH-1:0] ;
coe4[IWIDTH-1:0] <= coe5[IWIDTH-1:0] ;
coe3[IWIDTH-1:0] <= coe4[IWIDTH-1:0] ;
coe2[IWIDTH-1:0] <= coe3[IWIDTH-1:0] ;
coe1[IWIDTH-1:0] <= coe2[IWIDTH-1:0] ;
coe0[IWIDTH-1:0] <= coe1[IWIDTH-1:0] ;
end // else: !if(ARST)
//****************************************************************************//
//* Counters *//
//****************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
accum_cnt[ACCUMCNTWIDTH-1:0] <= {(ACCUMCNTWIDTH){1'b0}} ;
else
accum_cnt[ACCUMCNTWIDTH-1:0] <= (InputValid & ~InputValid0) ?
0:
(accum_cnt == NACCUM+1) ? (NACCUM+1)
: accum_cnt[ACCUMCNTWIDTH-1:0] + 1 ;
always @ (posedge CLK or posedge ARST)
if (ARST)
count[CNTWIDTH-1:0] <= {(CNTWIDTH){1'b0}} ;
else if (InputValid & ~InputValid0)
count[CNTWIDTH-1:0] <= (count[CNTWIDTH-1:0] == NTAPS-1) ? 0
: count[CNTWIDTH-1:0] + 1 ;
//****************************************************************************//
//* Multiplier - Accumulator *//
//****************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST) mult[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else mult[AWIDTH-1:0] <= coef* SigIn1 ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum1[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt[ACCUMCNTWIDTH-1:0] == 1)
accum1[AWIDTH-1:0] <= (count == 1) ? mult
: mult[AWIDTH-1:0] + accum1[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum2[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt[ACCUMCNTWIDTH-1:0] == 2)
accum2[AWIDTH-1:0] <= (count == 16) ? mult
: mult[AWIDTH-1:0] + accum2[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum3[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt[ACCUMCNTWIDTH-1:0] == 3)
accum3[AWIDTH-1:0] <= (count == 11) ? mult
: mult[AWIDTH-1:0] + accum3[AWIDTH-1:0] ;
always @ (posedge CLK or posedge ARST)
if (ARST)
accum4[AWIDTH-1:0] <= {(AWIDTH){1'b0}} ;
else if (accum_cnt[ACCUMCNTWIDTH-1:0] == 4)
accum4[AWIDTH-1:0] <= (count == 6) ? mult
: mult[AWIDTH-1:0] + accum4[AWIDTH-1:0] ;
//****************************************************************************//
//* Output Buffers *//
//****************************************************************************//
assign valid1 = (count[CNTWIDTH-1:0] == 1) & (accum_cnt == 0) ;
assign valid2 = (count[CNTWIDTH-1:0] == 16) & (accum_cnt == 0) ;
assign valid3 = (count[CNTWIDTH-1:0] == 11) & (accum_cnt == 0) ;
assign valid4 = (count[CNTWIDTH-1:0] == 6) & (accum_cnt == 0) ;
assign valid = valid1 | valid2 | valid3 | valid4 ;
always @ (posedge CLK or posedge ARST)
if (ARST)
SigOut[OWIDTH-1:0] <= {(OWIDTH){1'b0}} ;
else if (valid)
SigOut[OWIDTH-1:0] <= (accum1[AWIDTH-1:0] & {(AWIDTH){ valid1 }}) |
(accum2[AWIDTH-1:0] & {(AWIDTH){ valid2 }}) |
(accum3[AWIDTH-1:0] & {(AWIDTH){ valid3 }}) |
(accum4[AWIDTH-1:0] & {(AWIDTH){ valid4 }}) ;
always @ (posedge CLK or posedge ARST)
if (ARST) DataValid <= 1'b0 ;
else DataValid <= valid;
endmodule // firdecim_m5_n20
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : iReg.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 5, 2008 ** //
// ** Description : Internal Register for Newton core ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 5, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : August 19, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Register 0 functional modification ** //
// ** 2. Bit ReOrdering function change to for loop ** //
// ** 3. Register 1 and Register 2 counter modify to use ** //
// ** Write Enable bits ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module iReg
(// Outputs
iReg_intr, iReg2IP_RdAck, IP2Bus_WrAck, CPTR, IP2Bus_Data, SYNC,
// Inputs
Bus2IP_Clk, Bus2IP_Reset, Bus2IP_RdCE, Bus2IP_WrCE, Bus2IP_Data,
WFIFO_WE, FIR_WE
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter r0setclr = 31; // Register 0 set/clr bit
parameter initWM = 16'hFFFF;
parameter ModuleVersion = 2;
// DATA TYPE - INPUTS AND OUTPUTS
input Bus2IP_Clk; // 100MHz Clock from BUS
input Bus2IP_Reset; // Asynchronous Reset (positive logic)
input [0:3] Bus2IP_RdCE; // Register Read Enable (from Bus)
input [0:3] Bus2IP_WrCE; // Register Write Enable (from Bus)
input [0:31] Bus2IP_Data; // Data from Bus to IP
input WFIFO_WE; // Write Enable Signal from FIFO
input FIR_WE; // Write Signal from QM_FIR
output reg iReg_intr; // Interrupt Signal
output iReg2IP_RdAck;// Read Acknowledgement
output IP2Bus_WrAck; // Write Acknowledgement
output reg [10:0] CPTR; // Data from IP to bus
output [0:31] IP2Bus_Data; // Pointer to BRAM
output reg SYNC; // Resets QM counter to zero and Reset FIR coef registers
// to initial values
// DATA TYPE - INTERNAL REG
reg OVFL_MSK; // Overflow Mask
reg WMI_MSK; // WMI Mask
reg OVFL; // Overflow for CPTR
reg WMI; // Watermark Interrupt
reg [9:0] SPTR; // Load to CPTR when SYNC is asserted
reg [31:0] ICNT; // Counts the numbers of inputs
reg [15:0] OCNT_WM; // Output counter watermark
reg [15:0] OCNT_int; // Counts the numbers of outputs
reg [7:0] VERSION; // Current Module version number
reg [31:0] IP2Bus_Data_int; // Internal IP2Bus_Data
reg FIR_WE_dly1;
// DATA TYPE - INTERNAL WIRES
wire [31:0] ESCR;
wire [31:0] WPTR;
wire [31:0] OCNT;
wire [31:0] Bus2IP_Data_int; // Internal Bus2IP_Data_int
wire setclr;
//**************************************************************************//
//* Reversing Bit ReOrdering *//
//**************************************************************************//
assign Bus2IP_Data_int[31:0] = fnBitReordering031to310(Bus2IP_Data[0:31]);
assign IP2Bus_Data[0:31] = fnBitReordering310to031(IP2Bus_Data_int[31:0]);
//**************************************************************************//
//* REG 0 *//
//**************************************************************************//
assign setclr = Bus2IP_WrCE[0] & Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
OVFL_MSK <= 1'b0;
else if (Bus2IP_WrCE[0] & Bus2IP_Data_int[18])
OVFL_MSK <= Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
WMI_MSK <= 1'b0;
else if (Bus2IP_WrCE[0] & Bus2IP_Data_int[17])
WMI_MSK <= Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
OVFL <= 1'b0;
else if (CPTR[10] == 1'b1) // BRAM pointer overflows
OVFL <= 1'b1;
else if (Bus2IP_WrCE[0] & Bus2IP_Data_int[2])
OVFL <= Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
FIR_WE_dly1 <= 1'b0;
else
FIR_WE_dly1 <= FIR_WE;
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
WMI <= 1'b0;
else if (FIR_WE_dly1 & (OCNT_int[15:0] == OCNT_WM[15:0])) // Output counter overflows
WMI <= 1'b1;
else if (Bus2IP_WrCE[0] & Bus2IP_Data_int[1])
WMI <= Bus2IP_Data_int[r0setclr];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
SYNC <= 1'b0;
else
SYNC <= setclr & Bus2IP_Data_int[0];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0 )
VERSION[7:0] <= 8'd0;
else
VERSION[7:0] <= ModuleVersion;
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
iReg_intr <= 1'b0;
else
iReg_intr <= (WMI & ~WMI_MSK) | (OVFL & ~OVFL_MSK);
// Read out
assign ESCR[31:0] = {setclr, 12'd0, OVFL_MSK, WMI_MSK, 1'b0,
VERSION[7:0], 5'd0, OVFL, WMI, 1'b0};
//**************************************************************************//
//* REG 1 *//
//**************************************************************************//
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
SPTR[9:0] <= 10'd0;
else if (Bus2IP_WrCE[1])
SPTR[9:0] <= Bus2IP_Data_int[25:16];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
CPTR[10:0] <= 11'd0;
else if (SYNC == 1'b1)
begin
CPTR[9:0] <= SPTR[9:0];
CPTR[10] <= 1'b0;
end
else if (OVFL == 1'b1)
CPTR[10] <= 1'b0;
else
CPTR[10:0] <= CPTR[10:0] + FIR_WE; //Pointer to BRAM address
// Readout
assign WPTR[31:0] = {6'd0, SPTR[9:0], 6'd0, CPTR[9:0]};
//**************************************************************************//
//* REG 2 *//
//**************************************************************************//
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
ICNT[31:0] <= 32'd0;
else if (Bus2IP_WrCE[2])
ICNT[31:0] <= Bus2IP_Data_int[31:0];
else
ICNT[31:0] <= ICNT[31:0] + WFIFO_WE;
//**************************************************************************//
//* REG 3 *//
//**************************************************************************//
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
OCNT_WM[15:0] <= initWM;
else if (Bus2IP_WrCE[3])
OCNT_WM[15:0] <= Bus2IP_Data_int[31:16];
always @ (posedge Bus2IP_Clk or posedge Bus2IP_Reset)
if (Bus2IP_Reset !== 1'b0)
OCNT_int[15:0] <= 16'd0;
else if (Bus2IP_WrCE[3])
OCNT_int[15:0] <= Bus2IP_Data_int[15:0];
else
OCNT_int[15:0] <= OCNT_int[15:0] + FIR_WE;
// Read out
assign OCNT[31:0] = {OCNT_WM[15:0], OCNT_int[15:0]};
//**************************************************************************//
//* Read Out *//
//**************************************************************************//
always @ (/*AS*/Bus2IP_RdCE or ESCR or ICNT or OCNT or WPTR)
begin
IP2Bus_Data_int[31:0] = 32'b0;
case (1'b1)
Bus2IP_RdCE[0] : IP2Bus_Data_int[31:0] = ESCR[31:0];
Bus2IP_RdCE[1] : IP2Bus_Data_int[31:0] = WPTR[31:0];
Bus2IP_RdCE[2] : IP2Bus_Data_int[31:0] = ICNT[31:0];
Bus2IP_RdCE[3] : IP2Bus_Data_int[31:0] = OCNT[31:0];
endcase // case (1'b1)
end
assign iReg2IP_RdAck = |Bus2IP_RdCE[0:3];
assign IP2Bus_WrAck = |Bus2IP_WrCE[0:3];
//**************************************************************************//
//* Bit ReOrdering Functions *//
//**************************************************************************//
function [31:0] fnBitReordering031to310; // From [0:31] to [31:0]
input [0:31] Data1;
integer i;
begin
for (i=0;i<32;i=i+1)
fnBitReordering031to310[i] = Data1[31-i];
end
endfunction // fnBitReordering031to310
function [0:31] fnBitReordering310to031; // From [31:0] to [0:31]
input [31:0] Data1;
integer i;
begin
for (i=0;i<32;i=i+1)
fnBitReordering310to031[i] = Data1[31-i];
end
endfunction // fnBitReordering310to031
endmodule // iReg
|
// (C) 2001-2019 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/19.1std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2018/11/07 $
// $Author: psgswbuild $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
(** %\maketitle% *)
(** * Introduction
%\citet{DeGroote06}% demonstrates how to give a dynamic
interpretation to formulae in higher order logic, not by, as is
done in most works on dynamic semantics, giving a non-standard
model-theoretic interpretation of such formulae, but rather by
giving a systematic syntactic translation of these formulae into
other formulae which, when interpreted in the standard way, are
equivalent to the dynamic interpretation of the original formulae.
This is achieved by lifting the types of expressions to be
functions from left contexts (representing information about
already established discourse referents) to functions from right
contexts (representing discourse continuations) to truth values.
The goal of this short note is to show that the dynamic translation
of %\citet{DeGroote06}% can be factored into the composition of two
simpler parts; a left-context translation and a right-context
translation, or, more precisely, a semantics dealing with dynamism
without discourse referents, and a semantics dealing with discourse
referents without dynamism.
This is a literate Coq document, with source code available on the
web at %\url{https://github.com/gkobele/decomposing-montague}%.
*)
(* begin hide *)
Section obj.
(* end hide *)
(** * The formal language *)
(** I begin by defining the basic structures of the language. This
will serve both as a metalanguage (the target language of the
translations) and also as an object language (the source languages of
the translations).
The basic idea of a translation procedure is that an uninterpreted
object language is translated into a language that is already
understand, the meta-language. The same syntactic forms will be used
(a simple fragment of the lambda calculus) for both. This offers a
sort of _modularity_ of semantic description. From the semanticist's
perspective, this means that certain aspects of meaning can be
systematically ignored, knowing that the semantic terms actually
written down are (via the translation process) notational shorthands
for richer meaning representations. More speculatively, one might
conjecture that each successive translation might have some sort of
deeper reality, perhaps recapitulating the stages of a learner's
semantic language acquisition, or perhaps even as reflective of
different levels of deep semantic analysis of a sentence made as
needed during language processing.
The language is typed, with two basic types; [e] and [t]. Nothing
is assumed about expressions of type [e]; in particular, no expression
of the language will have a type ending in [e]. *)
(* begin hide *)
Variable e : Set.
(* end hide *)
(** In contrast, the type [t], is viewed as the type of complete
propositions, is the locus of recursion in this language. Thus, [and]
is a binary term forming operator. There are infinitely many
inhabitants of type [t], many of which are intuitively semantically
equivalent. There are constants [true] and [false], boolean
connectives [and], [or] and [not], term forming operators [p n] and [r
n] (the [n]th unary and binary relations respectively), and
generalized quantifiers [some], [all] and [pro] (representing a
pronoun). These provide the basic alphabet for building semantic
terms (of type [t]). With the exception of [pro], these can be
interpreted in the usual way in higher order models. [pro] is not
(intended to be understood as) a term in the meta-language, and will
only be given a meaning during the translation process.
%\citet{DeGroote06}% also has a constant _who_, which is however
definable as usual in terms of property conjunction: %\(\textbf{who}\
P\ Q = \lambda x. P x \wedge Q x\)%. *)
Inductive t : Set :=
| true : t
| false : t
| p : nat -> e -> t
| r : nat -> e -> e -> t
| and : t -> t -> t
| or : t -> t -> t
| imply : t -> t -> t
| not : t -> t
| some : (e -> t) -> t
| all : (e -> t) -> t
| pro : (e -> t) -> t.
(** printing false %\ensuremath{\bot}% *)
(** printing true %\ensuremath{\top}% *)
(** printing not %\ensuremath{\neg}% *)
(** printing and %\ensuremath{\wedge}% *)
(** printing or %\ensuremath{\vee}% *)
(** printing imply %\ensuremath{\leadsto}% *)
(** printing some %\textbf{some}% *)
(** printing all %\textbf{all}% *)
(* begin hide *)
Notation "phi 'und' psi" := (and phi psi) (at level 55).
Notation "phi 'oder' psi" := (or phi psi) (at level 60).
Notation "phi 'impl' psi" := (imply phi psi) (at level 65).
Notation "'farmer'" := (p 0).
Notation "'donkey'" := (p 1).
Notation "'laugh'" := (p 2).
Notation "'bray'" := (p 3).
Notation "'own'" := (r 0).
Notation "'beat'" := (r 1).
(* end hide *)
(** printing und %\ensuremath{\wedge}% *)
(** printing oder %\ensuremath{\vee}% *)
(** printing impl %\ensuremath{\leadsto}% *)
(** printing farmer %\textsf{farmer}% *)
(** printing donkey %\textsf{donkey}% *)
(** printing laugh %\textsf{laugh}% *)
(** printing bray %\textsf{bray}% *)
(** printing own %\textsf{own}% *)
(** printing beat %\textsf{beat}% *)
(** To make terms more readable, I introduce familiar notation, as shown in figure %\ref{fig:notation}%.
%\begin{figure}\centering
$\begin{array}{|ll|ll|}\hline%
[true] %& \textit{true} &%
[farmer] %& \textit{p} 0 \\%
[false] %& \textit{false} &%
[donkey] %& \textit{p} 1 \\%
[not] %& \textit{not} &%
[laugh] %& \textit{p} 2 \\%
[and] %& \textit{and} &%
[bray] %& \textit{p} 3 \\%
[or] %& \textit{or} &%
[own] %& \textit{r} 0 \\%
[imply] %& \textit{imply} &%
[beat] %& \textit{r} 1 \\\hline
\end{array}$
\caption{Abbreviations for constants}
\label{fig:notation}
\end{figure}%
*)
Example Every_donkey_brayed : all (fun x => donkey x impl bray x) = all (fun x => (p 1 x) impl (p 3 x)).
Proof.
reflexivity.
Qed.
(** The intended interpretation of terms of type [t] is of course in
an algebra (boolean or heyting) where [true] is understood as truth
(the top element of the algebra), and [false] as falsity (the bottom
element of the algebra). The connective symbols are to be understood
as appropriate operations in the algebra (meet, join, and complement
if in a boolean algebra, and meet, join and relative complement in a
heyting algebra). Although this setup is independent of one's
particular choice of logic (classical or intuitionistic), classical
logic is more familiar in linguistics, and generates a coarser
equivalence relation over terms. I will write $\phi \equiv \psi$ to
indicate that $\phi$ is classically equivalent to $\psi$. *)
(* begin hide *)
Inductive t_to_Prop (phi : t) : Prop :=
| t_to_Prop_constructor : t_to_Prop phi.
Fixpoint eval_phi phi : Prop :=
match phi with
| true => True
| false => False
| not psi => (eval_phi psi) -> False
| psi und eta => (eval_phi psi) /\ (eval_phi eta)
| psi oder eta => (eval_phi psi) \/ (eval_phi eta)
| psi impl eta => (eval_phi psi) -> (eval_phi eta)
| some P => (forall (a : e), ((eval_phi (P a)) -> False)) -> False
| all P => (forall (a : e), eval_phi (P a))
| psi => t_to_Prop psi
end.
Notation "phi 'equiv' psi" := (eval_phi phi <-> eval_phi psi) (at level 69).
(* end hide *)
(** printing equiv %\ensuremath{\mathrel{\equiv}}% *)
(** printing eta %\ensuremath{\eta}% *)
(** printing phi %\ensuremath{\phi}% *)
(** printing psi %\ensuremath{\psi}% *)
(** printing chi %\ensuremath{\chi}% *)
(* begin hide *)
Fixpoint repeat_type (n : nat) (i : Type) (o : Type) : Type :=
match n with
| O => o
| S m => i -> repeat_type m i o
end.
Notation "e ^^ n" := (repeat_type n e) (at level 30).
(* end hide *)
(** The notation [i^^n o] abbreviates the type
$\underbrace{i \rightarrow \cdots \rightarrow i}_{n\ times}
\rightarrow o$. *)
(* begin hide *)
Section dyn.
(* end hide *)
(** * Dynamism *)
(** In this section, dynamism is introduced to the system
above. Although the dynamic properties of connectives are
typically argued for based on the behaviour of pronouns, the
statement of the dynamic properties of connectives needn't make
reference to pronouns, which is exploited here.
The intuitive understanding of the dynamic meaning of a sentence is
as explicating its contribution to the discourse; it specifies how
the meaning of the upcoming discourse is influenced by its own
meaning. Accordingly the dynamic type $\Omega$ of a sentence is [t ->
t]; a function which modifies the meaning of an upcoming discourse.
*)
(* begin hide *)
Definition Omega := t -> t.
(* end hide *)
(** printing Omega %\ensuremath{\Omega}% *)
(** Dynamic translations of terms of type [t] into terms of type [Omega]
are now defined. These terms of type [Omega] are intended to capture in
an intuitive way the _dynamic_ meaning of the original terms of type
[t]. *)
(** Atomic sentences, qua n-ary predicates, are simply conjoined with
the discourse continuation. That is, the meaning of a discourse
consisting of only atomic sentences is hereby stipulated to be their
conjunction. *)
Fixpoint atom_d_tr (n : nat) : (e^^n) t -> (e^^n) Omega :=
match n with
| O => fun atom phi => atom und phi
| S m => fun atom x => atom_d_tr m (atom x)
end.
Example dynamic_beats : atom_d_tr 2 beat = fun x y phi => beat x y und phi.
Proof.
reflexivity.
Qed.
(** The atomic sentences [true] and [false], representing the always true and
always false sentences, obtain from the general treatment of atomic
sentences above the meanings [fun phi => true und phi] and [fun phi => false und phi]
respectively, which are semantically equivalent to the identity
function and the constant false function respectively. To simplify
the statement of the main result, the translations of [true] and [false] are
simply taken to be these simpler functions. *)
Definition true_d_tr : Omega := fun phi => phi.
Example true_id : forall phi, atom_d_tr O true phi equiv true_d_tr phi.
Proof.
simpl; intuition.
Qed.
Definition false_d_tr : Omega := fun _ => false.
Example false_false : forall phi, atom_d_tr O false phi equiv false_d_tr phi.
Proof.
simpl; intuition.
Qed.
(** Connectives are classified as externally dynamic just in case a
discourse referent introduced internally to them is accessible
externally. They are internally dynamic just in case a discourse
referent introduced inside of one conjunct is accessible in the other.
As conjunction is externally dynamic, the discourse continuation of
a conjunction should be in the scope of both conjuncts. As it is
also internally dynamic, the second conjunct should be in the scope
of the first. The discoure continuation of the first conjunct [P]
is thus the result of continuing the second conjunct [Q] with the
discourse continuation of the entire coordination, [phi]. In other
words, a discourse [P und Q. D] is interpreted as [P. Q. D].*)
Definition and_d_tr : Omega -> Omega -> Omega :=
fun (P Q : Omega) (phi : t) => P (Q phi).
(** Negation is externally static (i.e. not externally dynamic); so
the discourse continuation of a negated expression [P] must not be
in its scope. Instead, the negated expression [P] is given a
trivial discourse continuation, [true], and its negation is treated as
an atomic proposition; i.e. it is conjoined with the remainder of
the discourse. *)
Definition not_d_tr : Omega -> Omega :=
fun (P : Omega) => atom_d_tr 0 (not (P true)).
Example not_d_tr_externally_static :
forall (P : Omega) (phi : t), not_d_tr P phi = not (P true) und phi.
Proof.
reflexivity.
Qed.
(** The other dynamic connectives will be defined in terms of dynamic
conjunction and dynamic negation. Dynamic behaviour, whether internal
or external, will implicate a dynamic conjunction, and static
behaviour a dynamic negation.
Implication is externally static, but internally dynamic from
antecedent [P] to consequent [Q]. This is captured by its
classically valid reformulation in terms of [and] and [not]:
%\( P \rightarrow Q \equiv \neg (P \wedge \neg Q)\)% *)
Definition imp_d_tr : Omega -> Omega -> Omega :=
fun (P Q : Omega) => not_d_tr (and_d_tr P (not_d_tr Q)).
(** The dynamic behaviour of disjunction is less clear
%\citep{GroenendijkStokhof91}% . Sentences like: "Either this house
doesn't have a bathroom, or it is hidden" suggest that disjunction
should be (at least) internally dynamic, however it is common to
assume that disjunction is in fact completely static. This is in fact
predicted by its classical reformulation in terms of negation and
conjunction: %\( P \vee Q \equiv \neg (\neg P \wedge \neg Q)\)% *)
Definition or_d_tr : Omega -> Omega -> Omega :=
fun (P Q : Omega) => not_d_tr (and_d_tr (not_d_tr P) (not_d_tr Q)).
(** The generic treatment of dynamic GQs has it that the discourse
continuation of the entire sentence is moved into the scope of the
GQ. *)
Definition quant_d_tr (q : (e -> t) -> t) : (e -> Omega) -> Omega :=
fun (P : e -> Omega) (phi : t) => q (fun x => P x phi).
(** Exceptionally, from this perspective, universal quantification is
externally static, which is captured by its de Morgan reformulation in
terms of existential quantification: %\( \forall x.P x \equiv \neg \exists x.\neg P x \)% *)
Definition all_d_tr : (e -> Omega) -> Omega :=
fun (P : e -> Omega) => not_d_tr (quant_d_tr some (fun x => not_d_tr (P x))).
(** These definitions allow for a concise statement of the translation
[d_tr] (mnemonic for _dynamic_ translation) from terms of type [t],
with their dynamic potential _implicit_ into terms of type [Omega] with
their dynamic meanings made _explicit_. We see that the translation
[d_tr] is just a homomorphism. *)
Fixpoint d_tr (phi : t) : Omega :=
match phi with
| true => true_d_tr
| false => false_d_tr
| p n x => atom_d_tr 1 (p n) x
| r n x y => atom_d_tr 2 (r n) x y
| not psi => not_d_tr (d_tr psi)
| psi und chi => and_d_tr (d_tr psi) (d_tr chi)
| psi oder chi => or_d_tr (d_tr psi) (d_tr chi)
| psi impl chi => imp_d_tr (d_tr psi) (d_tr chi)
| pro P => quant_d_tr pro (fun x => d_tr (P x))
| some P => quant_d_tr some (fun x => d_tr (P x))
| all P => all_d_tr (fun x => d_tr (P x))
end.
(** This translation, as can be seen by the examples to follow, allows
existentials to dynamically extend their scope over upcoming
sentences, while disallowing universals from doing the same. *)
Example Some_farmer_laughed :
forall phi : t,
d_tr (some (fun x => farmer x und laugh x)) phi
equiv some (fun x => farmer x und laugh x und phi).
Proof.
simpl; intuition;
repeat (match goal with
| [ H : _ -> False |- _ ] => (apply H; clear H)
| [ a : e, H : forall (a : e), _ -> False |- _ ] => apply (H a); clear H
end; intuition).
Qed.
Example Every_farmer_laughed :
forall phi : t,
d_tr (all (fun x => farmer x impl laugh x)) phi
equiv (all (fun x : e => farmer x impl laugh x)) und phi.
Proof.
simpl;
intuition;
match goal with
| [ H : _ -> False |- _ ] => apply H
end;
intuition.
Qed.
(* begin hide *)
End dyn.
(* end hide *)
(* begin hide *)
Section contexts.
(* end hide *)
(** * Contexts *)
(** Here we present an interpretation of context-independent sentences
into context _dependent_ ones. This does not presuppose (or
introduce) dynamism.
Following %\citet{DeGroote06}%, we introduce a new type $\gamma$
for contexts. *)
(* begin hide *)
Variable gamma : Set.
(* end hide *)
(** printing gamma %\ensuremath{\gamma}% *)
(** This type is _abstract_, in the sense that its properties will be
given axiomatically; _anything_ that satisfies these properties may be
used as a context. We require only that we can interact with objects
of type [gamma] in two ways. First, that a context may be updated
with an individual to obtain a new context. *)
Variable update : e -> gamma -> gamma.
(** The notation $x\mathrel{\hbox{\tt ::}}c$ will abbreviate the more cumbersome [update x c].*)
(* begin hide *)
Notation "x 'upd' l" := (update x l) (at level 45).
(* end hide *)
(** printing upd %\ensuremath{\mathrel{\hbox{\tt ::}}}% *)
(** And second, that salient individuals may be retrieved from a
context. *)
Variable sel : gamma -> e.
(** In particular, [sel] should be thought of as a placeholder for
one's favourite pronoun resolution algorithm; in this view, the job
of semantics is to give the appropriate input to the pronoun
resolution algorithm, but the inner workings of this algorithm are
semantically opaque. %\citet{DeGroote06}% takes for concreteness
[gamma] to be the type of lists of individuals, updating to be
achieved by adding an individual to a list, and selection to be
retrieving some element of a list. *)
(** Terms of type [t] will be viewed as having implicit contexts. We
will define a translation from terms of type [t] which makes their
contexts, context updating, and context passing explicit. *)
(** Contexts are incorporated by adding a context parameter to every
atomic type. *)
Definition G := gamma -> t.
Definition E := gamma -> e.
(** Thus a term of type [t] will be translated into one of type [G],
and one of type [e] will be translated into one of type [E]. *)
(** Inherently context insenstitive [n]-ary connectives, functions,
and predicates can be lifted to context sensitive ones by simply
distributing the context to their context-sensitive arguments. *)
Fixpoint distr_g_tr {A B : Type} (n : nat) : (gamma -> (A ^^ n) B) -> ((gamma -> A) ^^ n) (gamma -> B) :=
match n as n0 return (gamma -> (A ^^ n0) B) -> ((gamma -> A) ^^ n0) (gamma -> B) with
| O => fun xx => xx
| S m => fun xx phi => distr_g_tr m (fun c : gamma => xx c (phi c))
end.
Definition lift_g_tr {A B : Type} (n : nat) (m : (A ^^ n) B) : ((gamma -> A) ^^ n) (gamma -> B) :=
@distr_g_tr A B n (fun _ => m).
Example contextual_individual (j : e) : lift_g_tr (A := e) 0 j = (fun _ => j).
Proof.
reflexivity.
Qed.
Example contextual_beats : lift_g_tr 2 beat = fun x y c => beat (x c) (y c).
Proof.
reflexivity.
Qed.
(** A pronoun [pro] is translated as a generalized quantifier
generated from the (context-sensitive) individual [sel]. *)
Definition pro_g_tr : (E -> G) -> G := fun P => P sel.
(** The individual argument to the property of a GQ is a lifted
context-insensitive variable. The context passed to this property
is enriched with the unlifted variable. *)
Definition quant_g_tr (gq : (e -> t) -> t) : (E -> G) -> G :=
fun P (c : gamma) => gq (fun x => P (lift_g_tr (A := e) 0 x) (x upd c)).
(** The function [g_tr] (mnemonic for _gamma_ translation) makes
explicit the implicit context manipulation in terms of type [t]. *)
Fixpoint g_tr (phi : t) : G :=
match phi with
| true => lift_g_tr (A := t) 0 true
| false => lift_g_tr (A := t) 0 false
| not psi => lift_g_tr 1 not (g_tr psi)
| psi und chi => lift_g_tr 2 and (g_tr psi) (g_tr chi)
| psi impl chi => lift_g_tr 2 imply (g_tr psi) (g_tr chi)
| psi oder chi => lift_g_tr 2 or (g_tr psi) (g_tr chi)
| p n a => lift_g_tr 1 (p n) (lift_g_tr (A := e) 0 a)
| r n a b => lift_g_tr 2 (r n) (lift_g_tr (A := e) 0 a) (lift_g_tr (A := e) 0 b)
| some P => quant_g_tr some (fun (x : E) (c : gamma) => g_tr (P (x c)) c)
| all P => quant_g_tr all (fun (x : E) (c : gamma) => g_tr (P (x c)) c)
| pro P => pro_g_tr (fun (x : E) (c : gamma) => g_tr (P (x c)) c)
end.
(** In the example below, which is the translation of the sentence _he
laughed_ into context-sensitive terms, note that the referent of the
pronoun _he_ must be found in the context of utterance [c]. *)
Example he_laughed :
forall (c : gamma), g_tr (pro laugh) c = laugh (sel c).
Proof.
reflexivity.
Qed.
(** In the following example, the translation of the sentence _some
farmer owned it_, note that the referent of _it_ is to be found in the
context of utterance [c] which has been updated with a discourse
referent [x] which is a farmer. Of course, for multiple reasons (the
pronoun is incompatible with the animacy of the farmer, and the
pronoun is syntactically too local) the pronoun should not in this
case be resolved to the discourse referent [x]. *)
Example some_farmer_owned_it :
forall (c : gamma), g_tr (some (fun x => farmer x und (pro (fun y => own y x)))) c
= some (fun x : e => farmer x und own (sel (x upd c)) x).
Proof.
reflexivity.
Qed.
(* begin hide *)
End contexts.
(* end hide *)
(* begin hide *)
Section deGroote.
(* end hide *)
(** * De Groote's Montagovian Dynamics *)
(* Next I recall %\citeauthor{deGroote}%'s dynamic approach with
contexts, which I show in a later theorem to be equivalent to the
composition of [g_tr] with [d_tr] *)
(* begin hide *)
Variable gamma : Set.
Variable update : e -> gamma -> gamma.
Variable sel : gamma -> e.
Notation "x 'upd' l" := (update x l) (at level 60, right associativity).
(* end hide *)
(** printing upd %\ensuremath{\mathrel{\hbox{\tt ::}}}% *)
(** The type of a sentence $\omega$ is defined to be [gamma -> (gamma -> t) -> t]; a function from a context [gamma] to the type [(gamma -> t) -> t] of the _continuation_ of a context.
*)
(* begin hide *)
Definition oomega := gamma -> (gamma -> t) -> t.
(* end hide *)
(** printing oomega %\ensuremath{\omega}% *)
(** Atomic predicates do not modify their context; they simply conjoin
their static meaning with the meaning of the discourse
continuation in the context.*)
Definition pred_dg_tr (n : nat) : e -> oomega :=
fun (x : e) (c : gamma) (phi : gamma -> t) => (p n x) und (phi c).
Definition rel_dg_tr (n : nat) : e -> e -> oomega :=
fun (x y : e) (c : gamma) (phi : gamma -> t) => (r n x y) und (phi c).
(** %\citeauthor{DeGroote06}% treats verbs as taking generalized
quantifiers as arguments, as opposed to individuals (in contrast to
nouns). This decision is orthogonal to the question of interest here,
and requires a richer setup than present in his
%\citeyear{DeGroote06}% paper to treat the composition of semantic
translations. *)
(** While %\citet{DeGroote06}% does not deal explicitly with
sentential connectives, his later work (as described by
%\citet{LebedevaPhD}%) does, and is as follows. *)
Definition and_dg_tr : oomega -> oomega -> oomega :=
fun (P Q : oomega) (c : gamma) (phi : gamma -> t) => P c (fun d => Q d phi).
Definition not_dg_tr : oomega -> oomega :=
fun (P : oomega) (c : gamma) (phi : gamma -> t) => (not (P c (fun _ => true))) und (phi c).
Definition or_dg_tr : oomega -> oomega -> oomega :=
fun (P Q : oomega) => not_dg_tr (and_dg_tr (not_dg_tr P) (not_dg_tr Q)).
Definition imply_dg_tr : oomega -> oomega -> oomega :=
fun (P Q : oomega) => not_dg_tr (and_dg_tr P (not_dg_tr Q)).
Definition some_dg_tr : (e -> oomega) -> oomega :=
fun (P : e -> oomega) (c : gamma) (phi : gamma -> t) => some (fun (x : e) => P x (x upd c) phi).
Definition every_dg_tr : (e -> oomega) -> oomega :=
fun (P : e -> oomega) => not_dg_tr (some_dg_tr (fun x => not_dg_tr (P x))).
Definition pro_dg_tr : (e -> oomega) -> oomega :=
fun (P : e -> oomega) (c : gamma) (phi : gamma -> t) => P (sel c) c phi.
(** The function [dg_tr] (short for `De Groote' translation), makes
the implicit dynamism and context manipulation in terms explicit.*)
Fixpoint dg_tr (f : t) : oomega :=
match f with
| true => fun c phi => phi c
| false => fun _ _ => false
| P und Q => and_dg_tr (dg_tr P) (dg_tr Q)
| P oder Q => or_dg_tr (dg_tr P) (dg_tr Q)
| P impl Q => imply_dg_tr (dg_tr P) (dg_tr Q)
| not P => not_dg_tr (dg_tr P)
| some P => some_dg_tr (fun x => dg_tr (P x))
| all P => every_dg_tr (fun x => dg_tr (P x))
| p n x => pred_dg_tr n x
| r n x y => rel_dg_tr n x y
| pro P => pro_dg_tr (fun x => dg_tr (P x))
end.
Example if_a_farmer_owns_a_donkey_he_beats_it : forall c phi,
dg_tr ((some (fun x => farmer x und some (fun y => donkey y und own y x))) impl pro (fun u => pro (fun v => beat v u))) c phi
equiv
((all (fun x : e => farmer x impl
all (fun y : e => (donkey y und own y x) impl
beat (sel (y upd x upd c)) (sel (y upd x upd c)))))
und phi c).
Proof.
simpl; intuition.
repeat (match goal with
| [ H : _ -> False |- _ ] => apply H
end;
intuition).
Qed.
(* begin hide *)
End deGroote.
(* end hide *)
(* begin hide *)
Section deGroote_equiv_g_d.
(* end hide *)
(** * The equivalence *)
(** The translations must be restricted so as to use the same type [gamma] and same accessor functions [update] and [sel]. *)
(* begin hide *)
Variable gamma : Set.
Variable update : e -> gamma -> gamma.
Variable sel : gamma -> e.
Notation "x 'upd' l" := (update x l) (at level 60).
(* end hide *)
(** printing upd %\ensuremath{\mathrel{\hbox{\tt ::}}}% *)
Definition g_trans := g_tr gamma update sel.
Definition dg_trans := dg_tr gamma update sel.
(** In order to prove the equivalence between de Groote's translation
and the composition of the gamma and dynamic translations, I assume
that functions are extensional; that two functions are identical iff
they compute the same input-output relation. *)
Hypothesis fun_ext : forall (A B : Set) (f g : A -> B), (forall x, f x = g x) -> f = g.
(* begin hide *)
Hint Resolve fun_ext : dG_d_g.
Lemma add_some : forall (P Q : e -> t), P = Q -> some P = some Q.
Proof.
intros; subst; reflexivity.
Qed.
Hint Resolve add_some : dG_d_g.
Lemma add_and : forall phi phi' chi chi', phi = phi' -> chi = chi' -> and phi chi = and phi' chi'.
Proof.
intros; subst; reflexivity.
Qed.
Hint Resolve add_and : dG_d_g.
Lemma add_not : forall phi phi', phi = phi' -> not phi = not phi'.
Proof.
intros; subst; reflexivity.
Qed.
Hint Resolve add_not : dG_d_g.
Ltac rewriteEq1 :=
match goal with
| [ H : forall _, _ = _ |- _ ] => rewrite H
end.
Hint Extern 3 => rewriteEq1 : dG_d_g.
Ltac rewriteEq2 :=
match goal with
| [ H : forall _ _, _ = _ |- _ ] => rewrite H
end.
Hint Extern 3 => rewriteEq2 : dG_d_g.
Ltac unfoldAll :=
simpl; unfold atom_d_tr, distr_g_tr, lift_g_tr, quant_g_tr, some_dg_tr, not_d_tr,
not_dg_tr, imply_dg_tr, every_dg_tr, and_d_tr,
and_dg_tr, pro_dg_tr, pro_g_tr, or_dg_tr, or_d_tr;
simpl; unfold atom_d_tr, distr_g_tr,
quant_g_tr, some_dg_tr, not_d_tr,
not_dg_tr, imply_dg_tr, every_dg_tr, and_d_tr,
and_dg_tr, pro_dg_tr, pro_g_tr, or_dg_tr, or_d_tr.
Hint Extern 1 => unfoldAll : dG_d_g.
Ltac applyFunExt := apply fun_ext; intro.
Hint Extern 3 => applyFunExt : dG_d_g.
(* end hide *)
(** The main theorem states that, for any formula [phi] of type [t],
the context-change poential of the contextification of its dynamic
translation is identical to the context-change potential of de
Groote's translation of it.
*)
Theorem dg_g_d :
forall (phi psi : t), g_trans ((d_tr phi) psi) = fun c => (dg_trans phi) c (g_trans psi).
(** %\begin{proof}% This is proven by induction on [phi], followed by simple but tedious case analysis. %\end{proof}%*)
Proof.
induction phi;
auto 8 with dG_d_g.
Qed.
(** One peculiarity about the statement of the theorem concerns the
function [g_trans] on the right hand side of the equation. This is
because the discourse context desired on the left hand side ([psi]) is
of type [t], whereas that desired on the right ([g_trans psi]) is of
type [gamma -> t]. In order for the theorem to make sense, both sides
must be given the same discourse continuation. The term [g_trans] on
the right of the equation coerces a term of type [t] into one of type
[gamma -> t]. In essence, the theorem says only that [g_trans] composed
with [d_tr] has the same effect on a discourse configuration of type
[t] that [dg_trans] has on its image under [g_trans].
In practice, this is not much of a restriction, as for any discourse
[phi], the theorem implies that both left and right sides are
interpreted identically in the empty discourse continuation. *)
Corollary dg_g_d_true :
forall (phi : t), g_trans (d_tr phi true) = fun c => dg_trans phi c (fun _ => true).
Proof.
intros phi;
rewrite (dg_g_d phi);
reflexivity.
Qed.
(* begin hide *)
End deGroote_equiv_g_d.
(* end hide *)
(* begin hide *)
End obj.
(* end hide *)
(** * Conclusion
The simple perspective offered by %\citet{DeGroote06}% on dynamism and
dynamic updating has been shown to be decomposible into two simpler
and logically independent parts. His %\citeyear{DeGroote06}% system,
modeled here, involves an mapping of _second-order_ terms in a source
language into those in a target language. This amounts to a
tree-to-term homomorphism, and allows %\citeauthor{DeGroote06}% to
avoid defining %\(\lambda\)%-homomorphisms. This has been improved
upon in later work %\citep{LebedevaPhD}%, where the source language is
made higher order. In order to have a simple statement of the two
parts that De Groote's system can be factored into (dynamism and
context-sensitivity), I have departed from his original presentation
in some ways. In particular, I have presented the source and target
languages as one and the same, whereas %\citeauthor{DeGroote06}%
treats the source language as properly syntactic, and the target
language as properly semantic. Collapsing source and target languages
has the aesthetically unpleasant consequence of introducing a
%`%meaningless%'% term, [pro], into the language. While the same
could have been done with the term %\textbf{who}%, I have chosen to
leave it out of the language altogether, as it plays no illustrative
semantic role. The second difference concerns the type of verbal
elements in the source language, where, for %\citeauthor{DeGroote06}%,
they take generalized quantifier denoting expressions as arguments:
%\(\den{\texttt{beat}} := \lambda X,Y.X(\lambda x.Y(\lambda
y.%[beat]%\ x\ y))\)%. This is made very simple in his presentation
by treating %\texttt{beat}% as a constant in a language different from
that of [beat]. This is not available to me, as both [g_tr] and
[d_tr] should be defined independently of each other, and therefore
must operate on the same source language, whence at least [d_tr] must
map one language to itself. While this is a salient theoretical
decision regarding the proper treatment of quantifier scope, it does
not matter for the decomposition of %\citeauthor{DeGroote06}%'s
translation into the two simpler ones given here.
*)
|
// Library - static, Cell - th34w22, View - schematic
// LAST TIME SAVED: May 23 17:04:57 2014
// NETLIST TIME: May 23 17:05:16 2014
`timescale 1ns / 1ns
module th34w22 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th34w22";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N9 ( .d(net32), .g(b), .s(net42), .b(cds_globals.gnd_));
nfet_b N8 ( .d(net42), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N7 ( .d(net32), .g(a), .s(net42), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net36), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(y), .s(net36), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net32), .g(b), .s(net36), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net36), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net32), .g(a), .s(net36), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net54), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N0 ( .d(net32), .g(a), .s(net54), .b(cds_globals.gnd_));
pfet_b P9 ( .b(cds_globals.vdd_), .g(b), .s(net38), .d(net32));
pfet_b P8 ( .b(cds_globals.vdd_), .g(a), .s(net38), .d(net32));
pfet_b P7 ( .b(cds_globals.vdd_), .g(c), .s(net53), .d(net38));
pfet_b P6 ( .b(cds_globals.vdd_), .g(d), .s(net52), .d(net53));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net52));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net25));
pfet_b P3 ( .b(cds_globals.vdd_), .g(a), .s(net55), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(b), .s(net25), .d(net55));
pfet_b P1 ( .b(cds_globals.vdd_), .g(c), .s(net56), .d(net25));
pfet_b P0 ( .b(cds_globals.vdd_), .g(d), .s(cds_globals.vdd_),
.d(net56));
inv I2 ( y, net32);
endmodule
|
//-----------------------------------------------------------------
// System Generator version 2015.2 Verilog source file.
//
// Copyright(C) 2013 by Xilinx, Inc. All rights reserved. This
// text/file contains proprietary, confidential information of Xilinx,
// Inc., is distributed under license from Xilinx, Inc., and may be used,
// copied and/or disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
// this text/file solely for design, simulation, implementation and
// creation of design files limited to Xilinx devices or technologies.
// Use with non-Xilinx devices or technologies is expressly prohibited
// and immediately terminates your license unless covered by a separate
// agreement.
//
// Xilinx is providing this design, code, or information "as is" solely
// for use in developing programs and solutions for Xilinx devices. By
// providing this design, code, or information as one possible
// implementation of this feature, application or standard, Xilinx is
// making no representation that this implementation is free from any
// claims of infringement. You are responsible for obtaining any rights
// you may require for your implementation. Xilinx expressly disclaims
// any warranty whatsoever with respect to the adequacy of the
// implementation, including but not limited to warranties of
// merchantability or fitness for a particular purpose.
//
// Xilinx products are not intended for use in life support appliances,
// devices, or systems. Use in such applications is expressly prohibited.
//
// Any modifications that are made to the source code are done at the user's
// sole risk and will be unsupported.
//
// This copyright and support notice must be retained as part of this
// text at all times. (c) Copyright 1995-2013 Xilinx, Inc. All rights
// reserved.
//-----------------------------------------------------------------
`include "conv_pkg.v"
`timescale 1 ns / 10 ps
module sysgen_constant_22a1de7646 (
output [(8 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 8'b00000001;
endmodule
`timescale 1 ns / 10 ps
module sysgen_inverter_2b67cf67d8 (
input [(1 - 1):0] ip,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire ip_1_26;
reg op_mem_22_20[0:(1 - 1)];
initial
begin
op_mem_22_20[0] = 1'b0;
end
wire op_mem_22_20_front_din;
wire op_mem_22_20_back;
wire op_mem_22_20_push_front_pop_back_en;
localparam [(1 - 1):0] const_value = 1'b1;
wire internal_ip_12_1_bitnot;
assign ip_1_26 = ip;
assign op_mem_22_20_back = op_mem_22_20[0];
always @(posedge clk)
begin:proc_op_mem_22_20
integer i;
if (((ce == 1'b1) && (op_mem_22_20_push_front_pop_back_en == 1'b1)))
begin
op_mem_22_20[0] <= op_mem_22_20_front_din;
end
end
assign internal_ip_12_1_bitnot = ~ip_1_26;
assign op_mem_22_20_push_front_pop_back_en = 1'b0;
assign op = internal_ip_12_1_bitnot;
endmodule
`timescale 1 ns / 10 ps
module sysgen_logical_314198b867 (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire fully_2_1_bit;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign fully_2_1_bit = d0_1_24 | d1_1_27;
assign y = fully_2_1_bit;
endmodule
`timescale 1 ns / 10 ps
module sysgen_logical_c8c764286e (
input [(1 - 1):0] d0,
input [(1 - 1):0] d1,
output [(1 - 1):0] y,
input clk,
input ce,
input clr);
wire d0_1_24;
wire d1_1_27;
wire fully_2_1_bit;
assign d0_1_24 = d0;
assign d1_1_27 = d1;
assign fully_2_1_bit = d0_1_24 & d1_1_27;
assign y = fully_2_1_bit;
endmodule
`timescale 1 ns / 10 ps
module sysgen_reinterpret_3cf0316996 (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr);
wire [(16 - 1):0] input_port_1_40;
wire signed [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule
`timescale 1 ns / 10 ps
module syntheses_xlslice (x, y);
//Parameter Definitions
parameter new_msb= 9;
parameter new_lsb= 1;
parameter x_width= 16;
parameter y_width= 8;
//Port Declartions
input [x_width-1:0] x;
output [y_width-1:0] y;
assign y = x[new_msb:new_lsb];
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_0ba576828b (
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 1'b0;
endmodule
`timescale 1 ns / 10 ps
module sysgen_concat_a5b25208fa (
input [(16 - 1):0] in0,
input [(16 - 1):0] in1,
output [(32 - 1):0] y,
input clk,
input ce,
input clr);
wire [(16 - 1):0] in0_1_23;
wire [(16 - 1):0] in1_1_27;
wire [(32 - 1):0] y_2_1_concat;
assign in0_1_23 = in0;
assign in1_1_27 = in1;
assign y_2_1_concat = {in0_1_23, in1_1_27};
assign y = y_2_1_concat;
endmodule
`timescale 1 ns / 10 ps
module syntheses_xlconvert (din, clk, ce, clr, en, dout);
//Parameter Definitions
parameter din_width= 16;
parameter din_bin_pt= 4;
parameter din_arith= `xlUnsigned;
parameter dout_width= 8;
parameter dout_bin_pt= 2;
parameter dout_arith= `xlUnsigned;
parameter en_width = 1;
parameter en_bin_pt = 0;
parameter en_arith = `xlUnsigned;
parameter bool_conversion = 0;
parameter latency = 0;
parameter quantization= `xlTruncate;
parameter overflow= `xlWrap;
//Port Declartions
input [din_width-1:0] din;
input clk, ce, clr;
input [en_width-1:0] en;
output [dout_width-1:0] dout;
//Wire Declartions
wire [dout_width-1:0] result;
wire internal_ce;
assign internal_ce = ce & en[0];
generate
if (bool_conversion == 1)
begin:bool_converion_generate
assign result = din;
end
else
begin:std_conversion
convert_type #(din_width,
din_bin_pt,
din_arith,
dout_width,
dout_bin_pt,
dout_arith,
quantization,
overflow)
conv_udp (.inp(din), .res(result));
end
endgenerate
generate
if (latency > 0)
begin:latency_test
synth_reg # (dout_width, latency)
reg1 (
.i(result),
.ce(internal_ce),
.clr(clr),
.clk(clk),
.o(dout));
end
else
begin:latency0
assign dout = result;
end
endgenerate
endmodule
`timescale 1 ns / 10 ps
module sysgen_reinterpret_debcca8ae2 (
input [(16 - 1):0] input_port,
output [(16 - 1):0] output_port,
input clk,
input ce,
input clr);
wire signed [(16 - 1):0] input_port_1_40;
wire [(16 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule
`timescale 1 ns / 10 ps
module sysgen_reinterpret_d4ce6da086 (
input [(34 - 1):0] input_port,
output [(34 - 1):0] output_port,
input clk,
input ce,
input clr);
wire signed [(34 - 1):0] input_port_1_40;
wire [(34 - 1):0] output_port_5_5_force;
assign input_port_1_40 = input_port;
assign output_port_5_5_force = input_port_1_40;
assign output_port = output_port_5_5_force;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_737c6ebc01 (
output [(4 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 4'b1111;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_1e52d3a74c (
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 1'b1;
endmodule
`timescale 1 ns / 10 ps
module sysgen_delay_73dbdd2749 (
input [(1 - 1):0] d,
input [(1 - 1):0] en,
input [(1 - 1):0] rst,
output [(1 - 1):0] q,
input clk,
input ce,
input clr);
wire d_1_22;
wire en_1_25;
wire rst_1_29;
wire op_mem_0_8_24_next;
reg op_mem_0_8_24 = 1'b0;
wire op_mem_0_8_24_rst;
wire op_mem_0_8_24_en;
localparam [(1 - 1):0] const_value = 1'b1;
reg op_mem_0_join_10_5;
reg op_mem_0_join_10_5_en;
reg op_mem_0_join_10_5_rst;
assign d_1_22 = d;
assign en_1_25 = en;
assign rst_1_29 = rst;
always @(posedge clk)
begin:proc_op_mem_0_8_24
if (((ce == 1'b1) && (op_mem_0_8_24_rst == 1'b1)))
begin
op_mem_0_8_24 <= 1'b0;
end
else if (((ce == 1'b1) && (op_mem_0_8_24_en == 1'b1)))
begin
op_mem_0_8_24 <= op_mem_0_8_24_next;
end
end
always @(d_1_22 or en_1_25 or rst_1_29)
begin:proc_if_10_5
if (rst_1_29)
begin
op_mem_0_join_10_5_rst = 1'b1;
end
else if (en_1_25)
begin
op_mem_0_join_10_5_rst = 1'b0;
end
else
begin
op_mem_0_join_10_5_rst = 1'b0;
end
if (en_1_25)
begin
op_mem_0_join_10_5_en = 1'b1;
end
else
begin
op_mem_0_join_10_5_en = 1'b0;
end
op_mem_0_join_10_5 = d_1_22;
end
assign op_mem_0_8_24_next = d_1_22;
assign op_mem_0_8_24_rst = op_mem_0_join_10_5_rst;
assign op_mem_0_8_24_en = op_mem_0_join_10_5_en;
assign q = op_mem_0_8_24;
endmodule
`timescale 1 ns / 10 ps
module sysgen_relational_423687f16e (
input [(4 - 1):0] a,
input [(4 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(4 - 1):0] a_1_31;
wire [(4 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule
`timescale 1 ns / 10 ps
module sysgen_relational_d2df5a549c (
input [(8 - 1):0] a,
input [(8 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(8 - 1):0] a_1_31;
wire [(8 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule
`timescale 1 ns / 10 ps
module sysgen_relational_9a0006bb82 (
input [(2 - 1):0] a,
input [(2 - 1):0] b,
output [(1 - 1):0] op,
input clk,
input ce,
input clr);
wire [(2 - 1):0] a_1_31;
wire [(2 - 1):0] b_1_34;
localparam [(1 - 1):0] const_value = 1'b1;
wire result_12_3_rel;
assign a_1_31 = a;
assign b_1_34 = b;
assign result_12_3_rel = a_1_31 == b_1_34;
assign op = result_12_3_rel;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_f0483638dd (
output [(8 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 8'b11001000;
endmodule
`timescale 1 ns / 10 ps
module sysgen_constant_34ca42c161 (
output [(2 - 1):0] op,
input clk,
input ce,
input clr);
assign op = 2'b11;
endmodule
//-----------------------------------------------------------------
// System Generator version 13.2 VERILOG source file.
//
// Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
// text/file contains proprietary, confidential information of Xilinx,
// Inc., is distributed under license from Xilinx, Inc., and may be used,
// copied and/or disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
// this text/file solely for design, simulation, implementation and
// creation of design files limited to Xilinx devices or technologies.
// Use with non-Xilinx devices or technologies is expressly prohibited
// and immediately terminates your license unless covered by a separate
// agreement.
//
// Xilinx is providing this design, code, or information "as is" solely
// for use in developing programs and solutions for Xilinx devices. By
// providing this design, code, or information as one possible
// implementation of this feature, application or standard, Xilinx is
// making no representation that this implementation is free from any
// claims of infringement. You are responsible for obtaining any rights
// you may require for your implementation. Xilinx expressly disclaims
// any warranty whatsoever with respect to the adequacy of the
// implementation, including but not limited to warranties of
// merchantability or fitness for a particular purpose.
//
// Xilinx products are not intended for use in life support appliances,
// devices, or systems. Use in such applications is expressly prohibited.
//
// Any modifications that are made to the source code are done at the user's
// sole risk and will be unsupported.
//
// This copyright and support notice must be retained as part of this
// text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
// reserved.
//-----------------------------------------------------------------
module syntheses_xlaxififogen(
s_aclk,
ce,
aresetn,
axis_underflow,
axis_overflow,
axis_data_count,
axis_prog_full_thresh,
axis_prog_empty_thresh,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
s_axis_tvalid,
s_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
m_axis_tvalid,
m_axis_tready
);
parameter core_name0 = "";
parameter has_aresetn = -1;
parameter tdata_width = -1;
parameter tdest_width = -1;
parameter tstrb_width = -1;
parameter tkeep_width = -1;
parameter tid_width = -1;
parameter tuser_width = -1;
parameter depth_bits = -1;
input ce;
input s_aclk;
input aresetn;
output axis_underflow;
output axis_overflow;
output [depth_bits-1:0] axis_data_count;
input [depth_bits-2:0] axis_prog_full_thresh;
input [depth_bits-2:0] axis_prog_empty_thresh;
input [tdata_width-1:0] s_axis_tdata;
input [tstrb_width-1:0] s_axis_tstrb;
input [tkeep_width-1:0] s_axis_tkeep;
input s_axis_tlast;
input [tid_width-1:0] s_axis_tid;
input [tdest_width-1:0] s_axis_tdest;
input [tuser_width-1:0] s_axis_tuser;
input s_axis_tvalid;
output s_axis_tready;
output [tdata_width-1:0] m_axis_tdata;
output [tstrb_width-1:0] m_axis_tstrb;
output [tkeep_width-1:0] m_axis_tkeep;
output m_axis_tlast;
output [tid_width-1:0] m_axis_tid;
output [tdest_width-1:0] m_axis_tdest;
output [tuser_width-1:0] m_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
wire srst;
reg reset_gen1 = 1'b0;
reg reset_gen_d1 = 1'b0;
reg reset_gen_d2 = 1'b0;
always @(posedge s_aclk)
begin
reset_gen1 <= 1'b1;
reset_gen_d1 <= reset_gen1;
reset_gen_d2 <= reset_gen_d1;
end
generate
if(has_aresetn == 0)
begin:if_block
assign srst = reset_gen_d2;
end
else
begin:else_block
assign srst = ~((~aresetn) & ce);
end
endgenerate
generate
if (core_name0 == "syntheses_fifo_generator_v12_0_0")
begin:comp0
syntheses_fifo_generator_v12_0_0 core_instance0 (
.s_aclk(s_aclk),
.s_aresetn(srst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid (s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.m_axis_tdata(m_axis_tdata),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid (m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready)
);
end
endgenerate
endmodule
module syntheses_xlcounter_free (ce, clr, clk, op, up, load, din, en, rst);
parameter core_name0= "";
parameter op_width= 5;
parameter op_arith= `xlSigned;
input ce, clr, clk;
input up, load;
input [op_width-1:0] din;
input en, rst;
output [op_width-1:0] op;
parameter [(8*op_width)-1:0] oneStr = { op_width{"1"}};
wire core_sinit;
wire core_ce;
wire [op_width-1:0] op_net;
assign core_ce = ce & en;
assign core_sinit = (clr | rst) & ce;
assign op = op_net;
generate
if (core_name0 == "syntheses_c_counter_binary_v12_0_0")
begin:comp0
syntheses_c_counter_binary_v12_0_0 core_instance0 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
if (core_name0 == "syntheses_c_counter_binary_v12_0_1")
begin:comp1
syntheses_c_counter_binary_v12_0_1 core_instance1 (
.CLK(clk),
.CE(core_ce),
.SINIT(core_sinit),
.Q(op_net)
);
end
endgenerate
endmodule
`timescale 1 ns / 10 ps
module xlfast_fourier_transform_e88bcbd69f6fa35c516aded21de2b91c (ce,clk,event_data_in_channel_halt,event_data_out_channel_halt,event_frame_started,event_status_channel_halt,event_tlast_missing,event_tlast_unexpected,m_axis_data_tdata_xn_im_0,m_axis_data_tdata_xn_re_0,m_axis_data_tlast,m_axis_data_tready,m_axis_data_tvalid,rst,s_axis_config_tdata_fwd_inv,s_axis_config_tready,s_axis_config_tvalid,s_axis_data_tdata_xn_im_0,s_axis_data_tdata_xn_re_0,s_axis_data_tlast,s_axis_data_tready,s_axis_data_tvalid);
input ce;
input clk;
output event_data_in_channel_halt;
output event_data_out_channel_halt;
output event_frame_started;
output event_status_channel_halt;
output event_tlast_missing;
output event_tlast_unexpected;
output[20:0] m_axis_data_tdata_xn_im_0;
output[20:0] m_axis_data_tdata_xn_re_0;
output m_axis_data_tlast;
input m_axis_data_tready;
output m_axis_data_tvalid;
input rst;
input[0:0] s_axis_config_tdata_fwd_inv;
output s_axis_config_tready;
input s_axis_config_tvalid;
input[15:0] s_axis_data_tdata_xn_im_0;
input[15:0] s_axis_data_tdata_xn_re_0;
input s_axis_data_tlast;
output s_axis_data_tready;
input s_axis_data_tvalid;
wire aresetn_net;
wire[47:0] m_axis_data_tdata_net;
wire[7:0] s_axis_config_tdata_net;
wire[31:0] s_axis_data_tdata_net;
assign aresetn_net = rst | (~ ce);
assign m_axis_data_tdata_xn_im_0 = m_axis_data_tdata_net[44 : 24];
assign m_axis_data_tdata_xn_re_0 = m_axis_data_tdata_net[20 : 0];
assign s_axis_config_tdata_net[7 : 1] = 7'b0;
assign s_axis_config_tdata_net[0 : 0] = s_axis_config_tdata_fwd_inv;
assign s_axis_data_tdata_net[31 : 16] = s_axis_data_tdata_xn_im_0;
assign s_axis_data_tdata_net[15 : 0] = s_axis_data_tdata_xn_re_0;
syntheses_xfft_v9_0_0 syntheses_xfft_v9_0_0_instance(
.aclk(clk),
.aclken(ce),
.aresetn(aresetn_net),
.event_data_in_channel_halt(event_data_in_channel_halt),
.event_data_out_channel_halt(event_data_out_channel_halt),
.event_frame_started(event_frame_started),
.event_status_channel_halt(event_status_channel_halt),
.event_tlast_missing(event_tlast_missing),
.event_tlast_unexpected(event_tlast_unexpected),
.m_axis_data_tdata(m_axis_data_tdata_net),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tvalid(m_axis_data_tvalid),
.s_axis_config_tdata(s_axis_config_tdata_net),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tvalid(s_axis_config_tvalid),
.s_axis_data_tdata(s_axis_data_tdata_net),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tvalid(s_axis_data_tvalid)
);
endmodule
`timescale 1 ns / 10 ps
module xlfir_compiler_83c7faa393ba9a5579d28bd87829549a (ce,clk,event_s_config_tlast_missing,event_s_config_tlast_unexpected,event_s_data_tlast_missing,event_s_data_tlast_unexpected,m_axis_data_tdata_path0,m_axis_data_tdata_path1,m_axis_data_tlast,m_axis_data_tready,m_axis_data_tvalid,rst,s_axis_config_tdata_fsel,s_axis_config_tlast,s_axis_config_tready,s_axis_config_tvalid,s_axis_data_tdata_path0,s_axis_data_tdata_path1,s_axis_data_tlast,s_axis_data_tready,s_axis_data_tvalid,src_ce,src_clk);
input ce;
input clk;
output event_s_config_tlast_missing;
output event_s_config_tlast_unexpected;
output event_s_data_tlast_missing;
output event_s_data_tlast_unexpected;
output[33:0] m_axis_data_tdata_path0;
output[33:0] m_axis_data_tdata_path1;
output m_axis_data_tlast;
input m_axis_data_tready;
output m_axis_data_tvalid;
input rst;
input[3:0] s_axis_config_tdata_fsel;
input s_axis_config_tlast;
output s_axis_config_tready;
input s_axis_config_tvalid;
input[17:0] s_axis_data_tdata_path0;
input[17:0] s_axis_data_tdata_path1;
input s_axis_data_tlast;
output s_axis_data_tready;
input s_axis_data_tvalid;
input src_ce;
input src_clk;
wire aresetn_net;
wire[79:0] m_axis_data_tdata_net;
wire[7:0] s_axis_config_tdata_net;
wire[47:0] s_axis_data_tdata_net;
assign aresetn_net = rst | (~ ce);
assign m_axis_data_tdata_path1 = m_axis_data_tdata_net[73 : 40];
assign m_axis_data_tdata_path0 = m_axis_data_tdata_net[33 : 0];
assign s_axis_config_tdata_net[7 : 4] = 4'b0;
assign s_axis_config_tdata_net[3 : 0] = s_axis_config_tdata_fsel;
assign s_axis_data_tdata_net[47 : 42] = 6'b0;
assign s_axis_data_tdata_net[41 : 24] = s_axis_data_tdata_path1;
assign s_axis_data_tdata_net[23 : 18] = 6'b0;
assign s_axis_data_tdata_net[17 : 0] = s_axis_data_tdata_path0;
syntheses_fir_compiler_v7_2_0 syntheses_fir_compiler_v7_2_0_instance(
.aclk(clk),
.aclken(ce),
.aresetn(aresetn_net),
.event_s_config_tlast_missing(event_s_config_tlast_missing),
.event_s_config_tlast_unexpected(event_s_config_tlast_unexpected),
.event_s_data_tlast_missing(event_s_data_tlast_missing),
.event_s_data_tlast_unexpected(event_s_data_tlast_unexpected),
.m_axis_data_tdata(m_axis_data_tdata_net),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tvalid(m_axis_data_tvalid),
.s_axis_config_tdata(s_axis_config_tdata_net),
.s_axis_config_tlast(s_axis_config_tlast),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tvalid(s_axis_config_tvalid),
.s_axis_data_tdata(s_axis_data_tdata_net),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tvalid(s_axis_data_tvalid)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_TB_V
`define SKY130_FD_SC_MS__A2111O_TB_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2111o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a2111o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_TB_V
|
/* b2d.v - A decoder from 4-bit input to 7seg Displays
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module b2d(SW,HEX0,HEX1,HEX2,HEX3);
// Input Port(s)
input [17:0] SW;
// Output Port(s)
output [0:6] HEX0,HEX1,HEX2,HEX3;
b2d_7seg B0 (SW[3:0], HEX0);
b2d_7seg B1 (SW[7:4], HEX1);
b2d_7seg B2 (SW[11:8], HEX2);
b2d_7seg B3 (SW[15:12], HEX3);
endmodule
/*
***************************************************************
Truth Table "A 4-to-7 Decoder"
+--- +----+----+----+----+-----+----+----+----+----+-----+------+
|SW15|SW14|SW13|SW12|HEX0|HEX1 |HEX2|HEX3|HEX4|HEX5|HEX6 | BCD |
+--- +----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 2 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 3 |
+--- +----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 4 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 5 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 6 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 7 |
+--- +----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 9 |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | E |
+----+----+----+----+----+-----+----+----+----+----+-----+------+
HEX3 [0:6]
+----------0---------+
||+----------------+|| HEX3[0] = (~SW[15] & ~SW[14] & ~SW[13] & SW[12])
|||| ||||
|||| ||||
|||| ||||
|||| ||||
||5| ||1|
|||| ||||
|||| ||||
|||| ||||
|||| ||||
|||+------6-------++||
|||+--------------++||
|||| ||||
|||| ||||
|||| ||||
|4|| ||2|
|||| ||||
|||| ||||
|||| ||||
|||| ||||
||+--------3-------+||
+--------------------+
*****************************************************************
*/
module b2d_7seg (X,SSD);
input [3:0] X;
output [0:6] SSD;
assign SSD[0] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]));
assign SSD[1] = ((~X[3] & X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & ~X[0]) | (X[3] & ~X[2] & X[1] & ~X[0]) | (X[3] & ~X[2] & X[1] & X[0]) | (X[3] & X[2] & X[1] & X[0]) | (X[3] & X[2] & X[1] & ~X[0]) | (X[3] & X[2] & ~X[1] & ~X[0]) | (X[3] & X[2] & ~X[1] & X[0]));
assign SSD[2] = ((~X[3] & ~X[2] & X[1] & ~X[0]) | (X[3] & ~X[2] & X[1] & ~X[0]) | (X[3] & ~X[2] & X[1] & X[0]) | (X[3] & X[2] & X[1] & X[0]) | (X[3] & X[2] & X[1] & ~X[0]) | (X[3] & X[2] & ~X[1] & ~X[0]) | (X[3] & X[2] & ~X[1] & X[0]));
assign SSD[3] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[4] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & ~X[1] & X[0]) | (X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[5] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & X[1] & ~X[0]) | (~X[3] & ~X[2] & X[1] & X[0]) | (~X[3] & X[2] & X[1] & X[0]));
assign SSD[6] = ((~X[3] & ~X[2] & ~X[1] & X[0]) | (~X[3] & ~X[2] & ~X[1] & ~X[0]) | (~X[3] & X[2] & X[1] & X[0]));
endmodule
|
//Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller Timer
//
// File : alt_ddrx_timer.v
//
// Abstract : Keep track of all DDR specific timing informations
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_timers #
( parameter
// memory interface bus sizing parameters
MEM_IF_CHIP_BITS = 2,
MEM_IF_CS_WIDTH = 4,
MEM_IF_ROW_WIDTH = 16, // max supported row bits
MEM_IF_BA_WIDTH = 3, // max supported bank bits
MEM_TYPE = "DDR3",
MEM_IF_RD_TO_WR_TURNAROUND_OCT = 0,
MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0,
DWIDTH_RATIO = 2, // 2 - fullrate, 4 - halfrate
MEMORY_BURSTLENGTH = 8,
// controller settings
CTL_LOOK_AHEAD_DEPTH = 6, // 6 in halfrate and 8 in fullrate
CTL_CMD_QUEUE_DEPTH = 8,
CTL_USR_REFRESH = 0, // enabled user refresh
// timing parameters width
CAS_WR_LAT_BUS_WIDTH = 4, // max will be 8 in DDR3
ADD_LAT_BUS_WIDTH = 3, // max will be 6 in DDR2
TCL_BUS_WIDTH = 4, // max will be 11 in DDR3
TRRD_BUS_WIDTH = 4, // 2 - 8
TFAW_BUS_WIDTH = 6, // 6 - 32
TRFC_BUS_WIDTH = 8, // 12 - 140?
TREFI_BUS_WIDTH = 13, // 780 - 6240
TRCD_BUS_WIDTH = 4, // 2 - 11
TRP_BUS_WIDTH = 4, // 2 - 11
TWR_BUS_WIDTH = 4, // 2 - 12
TWTR_BUS_WIDTH = 4, // 1 - 10
TRTP_BUS_WIDTH = 4, // 2 - 8
TRAS_BUS_WIDTH = 5, // 4 - 29
TRC_BUS_WIDTH = 6, // 8 - 40
AUTO_PD_BUS_WIDTH = 16 // same as CSR
)
(
// port connections
ctl_clk,
ctl_reset_n,
// look ahead ports
can_read_current,
can_write_current,
can_activate_current,
can_precharge_current,
can_read, // [1:0], cmd0 and cmd-1
can_write, // [1:0], cmd0 and cmd-1
can_activate, // [CTL_LOOK_AHEAD_DEPTH-1:0]
can_precharge, // [CTL_LOOK_AHEAD_DEPTH-1:0]
can_precharge_all, // for precharge all
can_lmr, // [MEM_IF_CS_WIDTH - 1 : 0]
can_exit_power_saving_mode, // [MEM_IF_CS_WIDTH - 1 : 0]
// periodic auto-refresh interface
can_refresh, // [MEM_IF_CS_WIDTH - 1 : 0]
auto_refresh_req, // refresh timer has expired,
auto_refresh_chip, // [MEM_IF_CS_WIDTH - 1 : 0]
// power-down interface
can_enter_power_down, // [MEM_IF_CS_WIDTH - 1 : 0]
power_down_req, // power down timer has expired
// user self-refresh interface
zq_cal_req,
can_self_rfsh, // [MEM_IF_CS_WIDTH - 1 : 0]
// indicate to state machine Additive Latency is on
can_al_activate_write,
can_al_activate_read,
add_lat_on,
// Per cmd entry inputs and outputs, currently set to 4, might increase to 7 or more
cmd0_is_valid,
cmd0_chip_addr,
cmd0_bank_addr,
cmd0_is_a_write,
cmd0_is_a_read,
cmd0_multicast_req,
cmd1_is_valid,
cmd1_chip_addr,
cmd1_bank_addr,
cmd1_is_a_write,
cmd1_is_a_read,
cmd1_multicast_req,
cmd2_is_valid,
cmd2_chip_addr,
cmd2_bank_addr,
cmd2_is_a_write,
cmd2_is_a_read,
cmd2_multicast_req,
cmd3_is_valid,
cmd3_chip_addr,
cmd3_bank_addr,
cmd3_is_a_write,
cmd3_is_a_read,
cmd3_multicast_req,
cmd4_is_valid,
cmd4_chip_addr,
cmd4_bank_addr,
cmd4_is_a_write,
cmd4_is_a_read,
cmd4_multicast_req,
cmd5_is_valid,
cmd5_chip_addr,
cmd5_bank_addr,
cmd5_is_a_write,
cmd5_is_a_read,
cmd5_multicast_req,
cmd6_is_valid,
cmd6_chip_addr,
cmd6_bank_addr,
cmd6_is_a_write,
cmd6_is_a_read,
cmd6_multicast_req,
cmd7_is_valid,
cmd7_chip_addr,
cmd7_bank_addr,
cmd7_is_a_write,
cmd7_is_a_read,
cmd7_multicast_req,
// used for current command
current_chip_addr,
current_bank_addr,
current_is_a_write,
current_is_a_read,
current_multicast_req,
cmd_fifo_empty,
local_init_done,
// state machine command outputs
ecc_fetch_error_addr,
fetch,
flush1,
flush2,
flush3,
do_write,
do_read,
do_activate,
do_precharge,
do_auto_precharge,
do_precharge_all,
do_refresh,
do_power_down,
do_self_rfsh,
do_lmr,
do_burst_chop,
// require to_chip (CS_WIDTH) as well for ARF, SRF and PDN
to_chip,
to_bank_addr,
// timing parameters
mem_cas_wr_lat,
mem_add_lat,
mem_tcl,
mem_trrd,
mem_tfaw,
mem_trfc,
mem_trefi,
mem_trcd,
mem_trp,
mem_twr,
mem_twtr,
mem_trtp,
mem_tras,
mem_trc,
mem_auto_pd_cycles
);
input ctl_clk;
input ctl_reset_n;
// look ahead ports
output can_read_current;
output can_write_current;
output can_activate_current;
output can_precharge_current;
output [1 : 0] can_read;
output [1 : 0] can_write;
output [CTL_LOOK_AHEAD_DEPTH - 1 : 0] can_activate;
output [CTL_LOOK_AHEAD_DEPTH - 1 : 0] can_precharge;
output [MEM_IF_CS_WIDTH - 1 : 0] can_precharge_all;
output [MEM_IF_CS_WIDTH - 1 : 0] can_lmr;
output [MEM_IF_CS_WIDTH - 1 : 0] can_exit_power_saving_mode;
// periodic auto-refresh interface
output auto_refresh_req;
output [MEM_IF_CS_WIDTH - 1 : 0] auto_refresh_chip;
output [MEM_IF_CS_WIDTH - 1 : 0] can_refresh;
// power-down interface
output power_down_req;
output [MEM_IF_CS_WIDTH - 1 : 0] can_enter_power_down;
// user self-refresh interface
output zq_cal_req;
output [MEM_IF_CS_WIDTH - 1 : 0] can_self_rfsh;
output can_al_activate_write;
output can_al_activate_read;
output add_lat_on;
// Per cmd entry inputs and outputs; currently set to 4; might increase to 7 or more
input cmd0_is_valid;
input cmd0_is_a_write;
input cmd0_is_a_read;
input cmd0_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd0_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd0_bank_addr;
input cmd1_is_valid;
input cmd1_is_a_write;
input cmd1_is_a_read;
input cmd1_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd1_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd1_bank_addr;
input cmd2_is_valid;
input cmd2_is_a_write;
input cmd2_is_a_read;
input cmd2_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd2_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd2_bank_addr;
input cmd3_is_valid;
input cmd3_is_a_write;
input cmd3_is_a_read;
input cmd3_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd3_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd3_bank_addr;
input cmd4_is_valid;
input cmd4_is_a_write;
input cmd4_is_a_read;
input cmd4_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd4_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd4_bank_addr;
input cmd5_is_valid;
input cmd5_is_a_write;
input cmd5_is_a_read;
input cmd5_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd5_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd5_bank_addr;
input cmd6_is_valid;
input cmd6_is_a_write;
input cmd6_is_a_read;
input cmd6_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd6_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd6_bank_addr;
input cmd7_is_valid;
input cmd7_is_a_write;
input cmd7_is_a_read;
input cmd7_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd7_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd7_bank_addr;
input current_is_a_write;
input current_is_a_read;
input current_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] current_chip_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] current_bank_addr;
input cmd_fifo_empty;
input local_init_done;
// state machine command outputs
input ecc_fetch_error_addr;
input fetch;
input flush1;
input flush2;
input flush3;
input do_write;
input do_read;
input do_activate;
input do_precharge;
input do_auto_precharge;
input do_precharge_all;
input do_refresh;
input do_power_down;
input do_self_rfsh;
input do_lmr;
input do_burst_chop;
input [MEM_IF_CS_WIDTH - 1 : 0] to_chip;
input [MEM_IF_BA_WIDTH - 1 : 0] to_bank_addr;
input [CAS_WR_LAT_BUS_WIDTH - 1 : 0] mem_cas_wr_lat;
input [ADD_LAT_BUS_WIDTH - 1 : 0] mem_add_lat;
input [TCL_BUS_WIDTH - 1 : 0] mem_tcl;
input [TRRD_BUS_WIDTH - 1 : 0] mem_trrd;
input [TFAW_BUS_WIDTH - 1 : 0] mem_tfaw;
input [TRFC_BUS_WIDTH - 1 : 0] mem_trfc;
input [TREFI_BUS_WIDTH - 1 : 0] mem_trefi;
input [TRCD_BUS_WIDTH - 1 : 0] mem_trcd;
input [TRP_BUS_WIDTH - 1 : 0] mem_trp;
input [TWR_BUS_WIDTH - 1 : 0] mem_twr;
input [TWTR_BUS_WIDTH - 1 : 0] mem_twtr;
input [TRTP_BUS_WIDTH - 1 : 0] mem_trtp;
input [TRAS_BUS_WIDTH - 1 : 0] mem_tras;
input [TRC_BUS_WIDTH - 1 : 0] mem_trc;
input [AUTO_PD_BUS_WIDTH - 1 : 0] mem_auto_pd_cycles;
/*------------------------------------------------------------------------------
Timing Parameters
------------------------------------------------------------------------------*/
// timing parameters
localparam BURST_LENGTH_BUS_WIDTH = 4;
localparam TMRD_BUS_WIDTH = 3;
localparam TMOD_BUS_WIDTH = 4;
localparam SELF_RFSH_EXIT_CYCLES_BUS_WIDTH = 10;
localparam BANK_ACTIVATE_WIDTH = TRCD_BUS_WIDTH;
localparam ACT_TO_PCH_WIDTH = TRAS_BUS_WIDTH;
localparam ACT_TO_ACT_WIDTH = TRC_BUS_WIDTH;
localparam RD_TO_RD_WIDTH = 3; // max tCCD is 4
localparam RD_TO_WR_WIDTH = 5; // max of 10? (roughly because in DDR3, cas_lat - cas_wr_lat + 6)
localparam RD_TO_WR_BC_WIDTH = 4; // max of 8? (roughly because in DDR3, cas_lat - cas_wr_lat + 4)
localparam RD_TO_PCH_WIDTH = 4; // max of 11 (add_lat (max of 6) + tRTP (max of 5))
localparam WR_TO_WR_WIDTH = 3; // max tCCD is 4
localparam WR_TO_RD_WIDTH = 5; // max of 28 (add_lat (max of 6) + cas_wr_lat (max of 8) + 4 + tWTR (max of 10))
localparam WR_TO_PCH_WIDTH = 5; // max of 24 (add_lat (max of 6) + cas_wr_lat (max of 8) + 4 + tWR (max of 6))
localparam PCH_TO_ACT_WIDTH = TRP_BUS_WIDTH;
localparam RD_AP_TO_ACT_WIDTH = 5; // max of 22 (add_lat (max of 6) + tRTP (max of 5) + tRP (max of 11))
localparam WR_AP_TO_ACT_WIDTH = 6; // max of 35 (add_lat (max of 6) + cas_wr_lat (max of 8) + 4 + tWR (max of 6) + tRP (max of 11))
localparam ARF_TO_VALID_WIDTH = TRFC_BUS_WIDTH;
localparam PDN_TO_VALID_WIDTH = 2; // currently pdn_to_valid is 3
localparam SRF_TO_VALID_WIDTH = SELF_RFSH_EXIT_CYCLES_BUS_WIDTH;
localparam LMR_TO_LMR_WIDTH = TMRD_BUS_WIDTH;
localparam LMR_TO_VALID_WIDTH = TMOD_BUS_WIDTH;
localparam ARF_PERIOD_WIDTH = TREFI_BUS_WIDTH;
localparam PDN_PERIOD_WIDTH = AUTO_PD_BUS_WIDTH;
localparam ACT_TO_ACT_DIFF_BANK_WIDTH = TRRD_BUS_WIDTH;
localparam FOUR_ACT_TO_ACT_WIDTH = TFAW_BUS_WIDTH;
localparam FINISH_WRITE_WIDTH = 5; // temp
wire [BURST_LENGTH_BUS_WIDTH - 1 : 0] mem_burst_length = MEMORY_BURSTLENGTH;
wire [TMRD_BUS_WIDTH - 1 : 0] mem_tmrd = 4;
wire [TMOD_BUS_WIDTH - 1 : 0] mem_tmod = 12;
wire [SELF_RFSH_EXIT_CYCLES_BUS_WIDTH - 1 : 0] mem_self_rfsh_exit_cycles = (MEM_TYPE == "DDR3") ? 512 : 200;
wire [RD_TO_WR_WIDTH - 1 : 0] mem_rd_to_wr_turnaround_oct = MEM_IF_RD_TO_WR_TURNAROUND_OCT;
wire [WR_TO_RD_WIDTH - 1 : 0] mem_wr_to_rd_turnaround_oct = MEM_IF_WR_TO_RD_TURNAROUND_OCT;
reg can_al_activate_write;
reg can_al_activate_read;
reg add_lat_on;
// activate
reg [BANK_ACTIVATE_WIDTH - 1 : 0] bank_active;
reg [ACT_TO_PCH_WIDTH - 1 : 0] act_to_pch;
reg [ACT_TO_ACT_WIDTH - 1 : 0] act_to_act;
// read
reg [RD_TO_RD_WIDTH - 1 : 0] rd_to_rd;
reg [RD_TO_WR_WIDTH - 1 : 0] rd_to_wr;
reg [RD_TO_WR_BC_WIDTH - 1 : 0] rd_to_wr_bc; // Burst chop support, only affects DDR3 RD - WR
reg [RD_TO_PCH_WIDTH - 1 : 0] rd_to_pch;
// write
reg [WR_TO_WR_WIDTH - 1 : 0] wr_to_wr;
reg [WR_TO_RD_WIDTH - 1 : 0] wr_to_rd;
reg [WR_TO_RD_WIDTH - 1 : 0] wr_to_rd_diff_chips;
reg [WR_TO_PCH_WIDTH - 1 : 0] wr_to_pch;
reg [WR_TO_PCH_WIDTH - 1 : 0] wr_to_rd_to_pch_all;
// precharge
reg [PCH_TO_ACT_WIDTH - 1 : 0] pch_to_act;
reg [PCH_TO_ACT_WIDTH - 1 : 0] pch_all_to_act;
// auto precharge
reg [RD_AP_TO_ACT_WIDTH - 1 : 0] rd_ap_to_act; // Missing
reg [WR_AP_TO_ACT_WIDTH - 1 : 0] wr_ap_to_act; // Missing
// others
reg [ARF_TO_VALID_WIDTH - 1 : 0] arf_to_valid; // tRFC
reg [PDN_TO_VALID_WIDTH - 1 : 0] pdn_to_valid; // power down exit time, not used currently
reg [SRF_TO_VALID_WIDTH - 1 : 0] srf_to_valid; // self refresh exit time
reg [SRF_TO_VALID_WIDTH - 1 : 0] srf_to_zq; // self refresh to ZQ calibration
reg [LMR_TO_LMR_WIDTH - 1 : 0] lmr_to_lmr; // tMRD
reg [LMR_TO_VALID_WIDTH - 1 : 0] lmr_to_valid; // tMOD
reg [ARF_PERIOD_WIDTH - 1 : 0] arf_period; // tREFI
reg [PDN_PERIOD_WIDTH - 1 : 0] pdn_period; // will request power down if controller is idle for X number of clock cycles
reg [ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] act_to_act_diff_bank; // tRRD
reg [FOUR_ACT_TO_ACT_WIDTH - 1 : 0] four_act_to_act; // tFAW
// required to monitor read and writes and make sure all data has benn transfered before enabling can power down/refresh/self refresh/lmr
reg [FINISH_WRITE_WIDTH - 1 : 0] finish_write;
reg [FINISH_WRITE_WIDTH - 1 : 0] finish_read;
// more/less than N signal, this signal will be used in timer block, this will reduce timing violation
// because we will abstract away the comparator and set the compared value in a register
reg more_than_2_bank_active;
reg more_than_2_act_to_pch;
reg more_than_2_act_to_act;
reg more_than_2_rd_to_rd;
reg more_than_2_rd_to_wr;
reg more_than_2_rd_to_wr_bc;
reg more_than_2_rd_to_pch;
reg more_than_2_wr_to_wr;
reg more_than_2_wr_to_rd;
reg more_than_2_wr_to_pch;
reg more_than_2_pch_to_act;
reg more_than_2_rd_ap_to_act;
reg more_than_2_wr_ap_to_act;
reg more_than_2_arf_to_valid;
reg more_than_2_pdn_to_valid;
reg more_than_2_srf_to_valid;
reg more_than_2_lmr_to_lmr;
reg more_than_2_lmr_to_valid;
reg more_than_2_arf_period;
reg more_than_2_pdn_period;
reg more_than_2_act_to_act_diff_bank;
reg more_than_2_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_2_bank_active <= 1'b0;
more_than_2_act_to_pch <= 1'b0;
more_than_2_act_to_act <= 1'b0;
more_than_2_rd_to_rd <= 1'b0;
more_than_2_rd_to_wr <= 1'b0;
more_than_2_rd_to_wr_bc <= 1'b0;
more_than_2_rd_to_pch <= 1'b0;
more_than_2_wr_to_wr <= 1'b0;
more_than_2_wr_to_rd <= 1'b0;
more_than_2_wr_to_pch <= 1'b0;
more_than_2_pch_to_act <= 1'b0;
more_than_2_rd_ap_to_act <= 1'b0;
more_than_2_wr_ap_to_act <= 1'b0;
more_than_2_arf_to_valid <= 1'b0;
more_than_2_pdn_to_valid <= 1'b0;
more_than_2_srf_to_valid <= 1'b0;
more_than_2_lmr_to_lmr <= 1'b0;
more_than_2_lmr_to_valid <= 1'b0;
more_than_2_arf_period <= 1'b0;
more_than_2_pdn_period <= 1'b0;
more_than_2_act_to_act_diff_bank <= 1'b0;
more_than_2_four_act_to_act <= 1'b0;
end
else
begin
// bank_active
if (bank_active >= 2)
more_than_2_bank_active <= 1'b1;
else
more_than_2_bank_active <= 1'b0;
// act_to_pch
if (act_to_pch >= 2)
more_than_2_act_to_pch <= 1'b1;
else
more_than_2_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act >= 2)
more_than_2_act_to_act <= 1'b1;
else
more_than_2_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd >= 2)
more_than_2_rd_to_rd <= 1'b1;
else
more_than_2_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr >= 2)
more_than_2_rd_to_wr <= 1'b1;
else
more_than_2_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc >= 2)
more_than_2_rd_to_wr_bc <= 1'b1;
else
more_than_2_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch >= 2)
more_than_2_rd_to_pch <= 1'b1;
else
more_than_2_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr >= 2)
more_than_2_wr_to_wr <= 1'b1;
else
more_than_2_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd >= 2)
more_than_2_wr_to_rd <= 1'b1;
else
more_than_2_wr_to_rd <= 1'b0;
// wr_to_pch
if (wr_to_pch >= 2)
more_than_2_wr_to_pch <= 1'b1;
else
more_than_2_wr_to_pch <= 1'b0;
// pch_to_act
if (pch_to_act >= 2)
more_than_2_pch_to_act <= 1'b1;
else
more_than_2_pch_to_act <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act >= 2)
more_than_2_rd_ap_to_act <= 1'b1;
else
more_than_2_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act >= 2)
more_than_2_wr_ap_to_act <= 1'b1;
else
more_than_2_wr_ap_to_act <= 1'b0;
// arf_to_valid
if (arf_to_valid >= 2)
more_than_2_arf_to_valid <= 1'b1;
else
more_than_2_arf_to_valid <= 1'b0;
// pdn_to_valid
if (pdn_to_valid >= 2)
more_than_2_pdn_to_valid <= 1'b1;
else
more_than_2_pdn_to_valid <= 1'b0;
// srf_to_valid
if (srf_to_valid >= 2)
more_than_2_srf_to_valid <= 1'b1;
else
more_than_2_srf_to_valid <= 1'b0;
// lmr_to_lmr
if (lmr_to_lmr >= 2)
more_than_2_lmr_to_lmr <= 1'b1;
else
more_than_2_lmr_to_lmr <= 1'b0;
// lmr_to_valid
if (lmr_to_valid >= 2)
more_than_2_lmr_to_valid <= 1'b1;
else
more_than_2_lmr_to_valid <= 1'b0;
// arf_period
if (arf_period >= 2)
more_than_2_arf_period <= 1'b1;
else
more_than_2_arf_period <= 1'b0;
// pdn_period
if (pdn_period >= 2)
more_than_2_pdn_period <= 1'b1;
else
more_than_2_pdn_period <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank >= 2)
more_than_2_act_to_act_diff_bank <= 1'b1;
else
more_than_2_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act >= 2)
more_than_2_four_act_to_act <= 1'b1;
else
more_than_2_four_act_to_act <= 1'b0;
end
end
reg less_than_2_bank_active;
reg less_than_2_act_to_pch;
reg less_than_2_act_to_act;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_rd_to_pch;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_wr_to_pch;
reg less_than_2_pch_to_act;
reg less_than_2_rd_ap_to_act;
reg less_than_2_wr_ap_to_act;
reg less_than_2_arf_to_valid;
reg less_than_2_pdn_to_valid;
reg less_than_2_srf_to_valid;
reg less_than_2_lmr_to_lmr;
reg less_than_2_lmr_to_valid;
reg less_than_2_arf_period;
reg less_than_2_pdn_period;
reg less_than_2_act_to_act_diff_bank;
reg less_than_2_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_bank_active <= 1'b0;
less_than_2_act_to_pch <= 1'b0;
less_than_2_act_to_act <= 1'b0;
less_than_2_rd_to_rd <= 1'b0;
less_than_2_rd_to_wr <= 1'b0;
less_than_2_rd_to_wr_bc <= 1'b0;
less_than_2_rd_to_pch <= 1'b0;
less_than_2_wr_to_wr <= 1'b0;
less_than_2_wr_to_rd <= 1'b0;
less_than_2_wr_to_pch <= 1'b0;
less_than_2_pch_to_act <= 1'b0;
less_than_2_rd_ap_to_act <= 1'b0;
less_than_2_wr_ap_to_act <= 1'b0;
less_than_2_arf_to_valid <= 1'b0;
less_than_2_pdn_to_valid <= 1'b0;
less_than_2_srf_to_valid <= 1'b0;
less_than_2_lmr_to_lmr <= 1'b0;
less_than_2_lmr_to_valid <= 1'b0;
less_than_2_arf_period <= 1'b0;
less_than_2_pdn_period <= 1'b0;
less_than_2_act_to_act_diff_bank <= 1'b0;
less_than_2_four_act_to_act <= 1'b0;
end
else
begin
// bank_active
if (bank_active <= 2)
less_than_2_bank_active <= 1'b1;
else
less_than_2_bank_active <= 1'b0;
// act_to_pch
if (act_to_pch <= 2)
less_than_2_act_to_pch <= 1'b1;
else
less_than_2_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act <= 2)
less_than_2_act_to_act <= 1'b1;
else
less_than_2_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch <= 2)
less_than_2_rd_to_pch <= 1'b1;
else
less_than_2_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
// wr_to_pch
if (wr_to_pch <= 2)
less_than_2_wr_to_pch <= 1'b1;
else
less_than_2_wr_to_pch <= 1'b0;
// pch_to_act
if (pch_to_act <= 2)
less_than_2_pch_to_act <= 1'b1;
else
less_than_2_pch_to_act <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act <= 2)
less_than_2_rd_ap_to_act <= 1'b1;
else
less_than_2_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act <= 2)
less_than_2_wr_ap_to_act <= 1'b1;
else
less_than_2_wr_ap_to_act <= 1'b0;
// arf_to_valid
if (arf_to_valid <= 2)
less_than_2_arf_to_valid <= 1'b1;
else
less_than_2_arf_to_valid <= 1'b0;
// pdn_to_valid
if (pdn_to_valid <= 2)
less_than_2_pdn_to_valid <= 1'b1;
else
less_than_2_pdn_to_valid <= 1'b0;
// srf_to_valid
if (srf_to_valid <= 2)
less_than_2_srf_to_valid <= 1'b1;
else
less_than_2_srf_to_valid <= 1'b0;
// lmr_to_lmr
if (lmr_to_lmr <= 2)
less_than_2_lmr_to_lmr <= 1'b1;
else
less_than_2_lmr_to_lmr <= 1'b0;
// lmr_to_valid
if (lmr_to_valid <= 2)
less_than_2_lmr_to_valid <= 1'b1;
else
less_than_2_lmr_to_valid <= 1'b0;
// arf_period
if (arf_period <= 2)
less_than_2_arf_period <= 1'b1;
else
less_than_2_arf_period <= 1'b0;
// pdn_period
if (pdn_period <= 2)
less_than_2_pdn_period <= 1'b1;
else
less_than_2_pdn_period <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act <= 2)
less_than_2_four_act_to_act <= 1'b1;
else
less_than_2_four_act_to_act <= 1'b0;
end
end
reg more_than_3_bank_active;
reg more_than_3_act_to_pch;
reg more_than_3_act_to_act;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_rd_to_pch;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_wr_to_pch;
reg more_than_3_pch_to_act;
reg more_than_3_rd_ap_to_act;
reg more_than_3_wr_ap_to_act;
reg more_than_3_arf_to_valid;
reg more_than_3_pdn_to_valid;
reg more_than_3_srf_to_valid;
reg more_than_3_lmr_to_lmr;
reg more_than_3_lmr_to_valid;
reg more_than_3_arf_period;
reg more_than_3_pdn_period;
reg more_than_3_act_to_act_diff_bank;
reg more_than_3_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_bank_active <= 1'b0;
more_than_3_act_to_pch <= 1'b0;
more_than_3_act_to_act <= 1'b0;
more_than_3_rd_to_rd <= 1'b0;
more_than_3_rd_to_wr <= 1'b0;
more_than_3_rd_to_wr_bc <= 1'b0;
more_than_3_rd_to_pch <= 1'b0;
more_than_3_wr_to_wr <= 1'b0;
more_than_3_wr_to_rd <= 1'b0;
more_than_3_wr_to_pch <= 1'b0;
more_than_3_pch_to_act <= 1'b0;
more_than_3_rd_ap_to_act <= 1'b0;
more_than_3_wr_ap_to_act <= 1'b0;
more_than_3_arf_to_valid <= 1'b0;
more_than_3_pdn_to_valid <= 1'b0;
more_than_3_srf_to_valid <= 1'b0;
more_than_3_lmr_to_lmr <= 1'b0;
more_than_3_lmr_to_valid <= 1'b0;
more_than_3_arf_period <= 1'b0;
more_than_3_pdn_period <= 1'b0;
more_than_3_act_to_act_diff_bank <= 1'b0;
more_than_3_four_act_to_act <= 1'b0;
end
else
begin
// bank_active
if (bank_active >= 3)
more_than_3_bank_active <= 1'b1;
else
more_than_3_bank_active <= 1'b0;
// act_to_pch
if (act_to_pch >= 3)
more_than_3_act_to_pch <= 1'b1;
else
more_than_3_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act >= 3)
more_than_3_act_to_act <= 1'b1;
else
more_than_3_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch >= 3)
more_than_3_rd_to_pch <= 1'b1;
else
more_than_3_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
// wr_to_pch
if (wr_to_pch >= 3)
more_than_3_wr_to_pch <= 1'b1;
else
more_than_3_wr_to_pch <= 1'b0;
// pch_to_act
if (pch_to_act >= 3)
more_than_3_pch_to_act <= 1'b1;
else
more_than_3_pch_to_act <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act >= 3)
more_than_3_rd_ap_to_act <= 1'b1;
else
more_than_3_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act >= 3)
more_than_3_wr_ap_to_act <= 1'b1;
else
more_than_3_wr_ap_to_act <= 1'b0;
// arf_to_valid
if (arf_to_valid >= 3)
more_than_3_arf_to_valid <= 1'b1;
else
more_than_3_arf_to_valid <= 1'b0;
// pdn_to_valid
if (pdn_to_valid >= 3)
more_than_3_pdn_to_valid <= 1'b1;
else
more_than_3_pdn_to_valid <= 1'b0;
// srf_to_valid
if (srf_to_valid >= 3)
more_than_3_srf_to_valid <= 1'b1;
else
more_than_3_srf_to_valid <= 1'b0;
// lmr_to_lmr
if (lmr_to_lmr >= 3)
more_than_3_lmr_to_lmr <= 1'b1;
else
more_than_3_lmr_to_lmr <= 1'b0;
// lmr_to_valid
if (lmr_to_valid >= 3)
more_than_3_lmr_to_valid <= 1'b1;
else
more_than_3_lmr_to_valid <= 1'b0;
// arf_period
if (arf_period >= 3)
more_than_3_arf_period <= 1'b1;
else
more_than_3_arf_period <= 1'b0;
// pdn_period
if (pdn_period >= 3)
more_than_3_pdn_period <= 1'b1;
else
more_than_3_pdn_period <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank >= 3)
more_than_3_act_to_act_diff_bank <= 1'b1;
else
more_than_3_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act >= 3)
more_than_3_four_act_to_act <= 1'b1;
else
more_than_3_four_act_to_act <= 1'b0;
end
end
reg less_than_3_bank_active;
reg less_than_3_act_to_pch;
reg less_than_3_act_to_act;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_rd_to_pch;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_wr_to_rd_diff_chips;
reg less_than_3_wr_to_pch;
reg less_than_3_pch_to_act;
reg less_than_3_wr_to_rd_to_pch_all; // added to fix wr - rd - pch all bug
reg less_than_3_rd_ap_to_act;
reg less_than_3_wr_ap_to_act;
reg less_than_3_arf_to_valid;
reg less_than_3_pdn_to_valid;
reg less_than_3_srf_to_valid;
reg less_than_3_lmr_to_lmr;
reg less_than_3_lmr_to_valid;
reg less_than_3_arf_period;
reg less_than_3_pdn_period;
reg less_than_3_act_to_act_diff_bank;
reg less_than_3_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_bank_active <= 1'b0;
less_than_3_act_to_pch <= 1'b0;
less_than_3_act_to_act <= 1'b0;
less_than_3_rd_to_rd <= 1'b0;
less_than_3_rd_to_wr <= 1'b0;
less_than_3_rd_to_wr_bc <= 1'b0;
less_than_3_rd_to_pch <= 1'b0;
less_than_3_wr_to_wr <= 1'b0;
less_than_3_wr_to_rd <= 1'b0;
less_than_3_wr_to_rd_diff_chips <= 1'b0;
less_than_3_wr_to_pch <= 1'b0;
less_than_3_wr_to_rd_to_pch_all <= 1'b0;
less_than_3_pch_to_act <= 1'b0;
less_than_3_rd_ap_to_act <= 1'b0;
less_than_3_wr_ap_to_act <= 1'b0;
less_than_3_arf_to_valid <= 1'b0;
less_than_3_pdn_to_valid <= 1'b0;
less_than_3_srf_to_valid <= 1'b0;
less_than_3_lmr_to_lmr <= 1'b0;
less_than_3_lmr_to_valid <= 1'b0;
less_than_3_arf_period <= 1'b0;
less_than_3_pdn_period <= 1'b0;
less_than_3_act_to_act_diff_bank <= 1'b0;
less_than_3_four_act_to_act <= 1'b0;
end
else
begin
// bank_active
if (bank_active <= 3)
less_than_3_bank_active <= 1'b1;
else
less_than_3_bank_active <= 1'b0;
// act_to_pch
if (act_to_pch <= 3)
less_than_3_act_to_pch <= 1'b1;
else
less_than_3_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act <= 3)
less_than_3_act_to_act <= 1'b1;
else
less_than_3_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch <= 3)
less_than_3_rd_to_pch <= 1'b1;
else
less_than_3_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
// wr_to_rd_diff_chips
if (wr_to_rd_diff_chips <= 3)
less_than_3_wr_to_rd_diff_chips <= 1'b1;
else
less_than_3_wr_to_rd_diff_chips <= 1'b0;
// wr_to_pch
if (wr_to_pch <= 3)
less_than_3_wr_to_pch <= 1'b1;
else
less_than_3_wr_to_pch <= 1'b0;
// wr_to_rd_to_pch_all
if (wr_to_rd_to_pch_all <= 3)
less_than_3_wr_to_rd_to_pch_all <= 1'b1;
else
less_than_3_wr_to_rd_to_pch_all <= 1'b0;
// pch_to_act
if (pch_to_act <= 3)
less_than_3_pch_to_act <= 1'b1;
else
less_than_3_pch_to_act <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act <= 3)
less_than_3_rd_ap_to_act <= 1'b1;
else
less_than_3_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act <= 3)
less_than_3_wr_ap_to_act <= 1'b1;
else
less_than_3_wr_ap_to_act <= 1'b0;
// arf_to_valid
if (arf_to_valid <= 3)
less_than_3_arf_to_valid <= 1'b1;
else
less_than_3_arf_to_valid <= 1'b0;
// pdn_to_valid
if (pdn_to_valid <= 3)
less_than_3_pdn_to_valid <= 1'b1;
else
less_than_3_pdn_to_valid <= 1'b0;
// srf_to_valid
if (srf_to_valid <= 3)
less_than_3_srf_to_valid <= 1'b1;
else
less_than_3_srf_to_valid <= 1'b0;
// lmr_to_lmr
if (lmr_to_lmr <= 3)
less_than_3_lmr_to_lmr <= 1'b1;
else
less_than_3_lmr_to_lmr <= 1'b0;
// lmr_to_valid
if (lmr_to_valid <= 3)
less_than_3_lmr_to_valid <= 1'b1;
else
less_than_3_lmr_to_valid <= 1'b0;
// arf_period
if (arf_period <= 3)
less_than_3_arf_period <= 1'b1;
else
less_than_3_arf_period <= 1'b0;
// pdn_period
if (pdn_period <= 3)
less_than_3_pdn_period <= 1'b1;
else
less_than_3_pdn_period <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act <= 3)
less_than_3_four_act_to_act <= 1'b1;
else
less_than_3_four_act_to_act <= 1'b0;
end
end
reg more_than_4_bank_active;
reg more_than_4_act_to_pch;
reg more_than_4_act_to_act;
reg more_than_4_rd_to_rd;
reg more_than_4_rd_to_wr;
reg more_than_4_rd_to_wr_bc;
reg more_than_4_rd_to_pch;
reg more_than_4_wr_to_wr;
reg more_than_4_wr_to_rd;
reg more_than_4_wr_to_pch;
reg more_than_4_pch_to_act;
reg more_than_4_rd_ap_to_act;
reg more_than_4_wr_ap_to_act;
reg more_than_4_arf_to_valid;
reg more_than_4_pdn_to_valid;
reg more_than_4_srf_to_valid;
reg more_than_4_lmr_to_lmr;
reg more_than_4_lmr_to_valid;
reg more_than_4_arf_period;
reg more_than_4_pdn_period;
reg more_than_4_act_to_act_diff_bank;
reg more_than_4_four_act_to_act;
reg more_than_4_pch_all_to_act; // special signal for DDR2, to monitor tRPA
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_4_bank_active <= 1'b0;
more_than_4_act_to_pch <= 1'b0;
more_than_4_act_to_act <= 1'b0;
more_than_4_rd_to_rd <= 1'b0;
more_than_4_rd_to_wr <= 1'b0;
more_than_4_rd_to_wr_bc <= 1'b0;
more_than_4_rd_to_pch <= 1'b0;
more_than_4_wr_to_wr <= 1'b0;
more_than_4_wr_to_rd <= 1'b0;
more_than_4_wr_to_pch <= 1'b0;
more_than_4_pch_to_act <= 1'b0;
more_than_4_rd_ap_to_act <= 1'b0;
more_than_4_wr_ap_to_act <= 1'b0;
more_than_4_arf_to_valid <= 1'b0;
more_than_4_pdn_to_valid <= 1'b0;
more_than_4_srf_to_valid <= 1'b0;
more_than_4_lmr_to_lmr <= 1'b0;
more_than_4_lmr_to_valid <= 1'b0;
more_than_4_arf_period <= 1'b0;
more_than_4_pdn_period <= 1'b0;
more_than_4_act_to_act_diff_bank <= 1'b0;
more_than_4_four_act_to_act <= 1'b0;
more_than_4_pch_all_to_act <= 1'b0;
end
else
begin
// bank_active
if (bank_active >= 4)
more_than_4_bank_active <= 1'b1;
else
more_than_4_bank_active <= 1'b0;
// act_to_pch
if (act_to_pch >= 4)
more_than_4_act_to_pch <= 1'b1;
else
more_than_4_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act >= 4)
more_than_4_act_to_act <= 1'b1;
else
more_than_4_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd >= 4)
more_than_4_rd_to_rd <= 1'b1;
else
more_than_4_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr >= 4)
more_than_4_rd_to_wr <= 1'b1;
else
more_than_4_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc >= 4)
more_than_4_rd_to_wr_bc <= 1'b1;
else
more_than_4_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch >= 4)
more_than_4_rd_to_pch <= 1'b1;
else
more_than_4_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr >= 4)
more_than_4_wr_to_wr <= 1'b1;
else
more_than_4_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd >= 4)
more_than_4_wr_to_rd <= 1'b1;
else
more_than_4_wr_to_rd <= 1'b0;
// wr_to_pch
if (wr_to_pch >= 4)
more_than_4_wr_to_pch <= 1'b1;
else
more_than_4_wr_to_pch <= 1'b0;
// pch_to_act
if (pch_to_act >= 4)
more_than_4_pch_to_act <= 1'b1;
else
more_than_4_pch_to_act <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act >= 4)
more_than_4_rd_ap_to_act <= 1'b1;
else
more_than_4_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act >= 4)
more_than_4_wr_ap_to_act <= 1'b1;
else
more_than_4_wr_ap_to_act <= 1'b0;
// arf_to_valid
if (arf_to_valid >= 4)
more_than_4_arf_to_valid <= 1'b1;
else
more_than_4_arf_to_valid <= 1'b0;
// pdn_to_valid
if (pdn_to_valid >= 4)
more_than_4_pdn_to_valid <= 1'b1;
else
more_than_4_pdn_to_valid <= 1'b0;
// srf_to_valid
if (srf_to_valid >= 4)
more_than_4_srf_to_valid <= 1'b1;
else
more_than_4_srf_to_valid <= 1'b0;
// lmr_to_lmr
if (lmr_to_lmr >= 4)
more_than_4_lmr_to_lmr <= 1'b1;
else
more_than_4_lmr_to_lmr <= 1'b0;
// lmr_to_valid
if (lmr_to_valid >= 4)
more_than_4_lmr_to_valid <= 1'b1;
else
more_than_4_lmr_to_valid <= 1'b0;
// arf_period
if (arf_period >= 4)
more_than_4_arf_period <= 1'b1;
else
more_than_4_arf_period <= 1'b0;
// pdn_period
if (pdn_period >= 4)
more_than_4_pdn_period <= 1'b1;
else
more_than_4_pdn_period <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank >= 4)
more_than_4_act_to_act_diff_bank <= 1'b1;
else
more_than_4_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act >= 4)
more_than_4_four_act_to_act <= 1'b1;
else
more_than_4_four_act_to_act <= 1'b0;
if (pch_all_to_act >= 4)
more_than_4_pch_all_to_act <= 1'b1;
else
more_than_4_pch_all_to_act <= 1'b0;
end
end
reg less_than_4_bank_active;
reg less_than_4_act_to_pch;
reg less_than_4_act_to_act;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_rd_to_pch;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_wr_to_rd_diff_chips;
reg less_than_4_wr_to_pch;
reg less_than_4_pch_to_act;
reg less_than_4_wr_to_rd_to_pch_all; // added to fix wr - rd - pch all bug
reg less_than_4_rd_ap_to_act;
reg less_than_4_wr_ap_to_act;
reg less_than_4_arf_to_valid;
reg less_than_4_pdn_to_valid;
reg less_than_4_srf_to_valid;
reg less_than_4_lmr_to_lmr;
reg less_than_4_lmr_to_valid;
reg less_than_4_arf_period;
reg less_than_4_pdn_period;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_bank_active <= 1'b0;
less_than_4_act_to_pch <= 1'b0;
less_than_4_act_to_act <= 1'b0;
less_than_4_rd_to_rd <= 1'b0;
less_than_4_rd_to_wr <= 1'b0;
less_than_4_rd_to_wr_bc <= 1'b0;
less_than_4_rd_to_pch <= 1'b0;
less_than_4_wr_to_wr <= 1'b0;
less_than_4_wr_to_rd <= 1'b0;
less_than_4_wr_to_rd_diff_chips <= 1'b0;
less_than_4_wr_to_pch <= 1'b0;
less_than_4_wr_to_rd_to_pch_all <= 1'b0;
less_than_4_pch_to_act <= 1'b0;
less_than_4_rd_ap_to_act <= 1'b0;
less_than_4_wr_ap_to_act <= 1'b0;
less_than_4_arf_to_valid <= 1'b0;
less_than_4_pdn_to_valid <= 1'b0;
less_than_4_srf_to_valid <= 1'b0;
less_than_4_lmr_to_lmr <= 1'b0;
less_than_4_lmr_to_valid <= 1'b0;
less_than_4_arf_period <= 1'b0;
less_than_4_pdn_period <= 1'b0;
less_than_4_act_to_act_diff_bank <= 1'b0;
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
// bank_active
if (bank_active <= 4)
less_than_4_bank_active <= 1'b1;
else
less_than_4_bank_active <= 1'b0;
// act_to_pch
if (act_to_pch <= 4)
less_than_4_act_to_pch <= 1'b1;
else
less_than_4_act_to_pch <= 1'b0;
// act_to_act
if (act_to_act <= 4)
less_than_4_act_to_act <= 1'b1;
else
less_than_4_act_to_act <= 1'b0;
// rd_to_rd
if (rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
// rd_to_wr
if (rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
// rd_to_wr_bc
if (rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
// rd_to_pch
if (rd_to_pch <= 4)
less_than_4_rd_to_pch <= 1'b1;
else
less_than_4_rd_to_pch <= 1'b0;
// wr_to_wr
if (wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
// wr_to_rd
if (wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
// wr_to_rd_diff_chips
if (wr_to_rd_diff_chips <= 4)
less_than_4_wr_to_rd_diff_chips <= 1'b1;
else
less_than_4_wr_to_rd_diff_chips <= 1'b0;
// wr_to_pch
if (wr_to_pch <= 4)
less_than_4_wr_to_pch <= 1'b1;
else
less_than_4_wr_to_pch <= 1'b0;
// wr_to_rd_to_pch_all
if (wr_to_rd_to_pch_all <= 4)
less_than_4_wr_to_rd_to_pch_all <= 1'b1;
else
less_than_4_wr_to_rd_to_pch_all <= 1'b0;
// pch_to_act
if (pch_to_act <= 4)
less_than_4_pch_to_act <= 1'b1;
else
less_than_4_pch_to_act <= 1'b0;
// rd_ap_to_act
if (rd_ap_to_act <= 4)
less_than_4_rd_ap_to_act <= 1'b1;
else
less_than_4_rd_ap_to_act <= 1'b0;
// wr_ap_to_act
if (wr_ap_to_act <= 4)
less_than_4_wr_ap_to_act <= 1'b1;
else
less_than_4_wr_ap_to_act <= 1'b0;
// arf_to_valid
if (arf_to_valid <= 4)
less_than_4_arf_to_valid <= 1'b1;
else
less_than_4_arf_to_valid <= 1'b0;
// pdn_to_valid
if (pdn_to_valid <= 4)
less_than_4_pdn_to_valid <= 1'b1;
else
less_than_4_pdn_to_valid <= 1'b0;
// srf_to_valid
if (srf_to_valid <= 4)
less_than_4_srf_to_valid <= 1'b1;
else
less_than_4_srf_to_valid <= 1'b0;
// lmr_to_lmr
if (lmr_to_lmr <= 4)
less_than_4_lmr_to_lmr <= 1'b1;
else
less_than_4_lmr_to_lmr <= 1'b0;
// lmr_to_valid
if (lmr_to_valid <= 4)
less_than_4_lmr_to_valid <= 1'b1;
else
less_than_4_lmr_to_valid <= 1'b0;
// arf_period
if (arf_period <= 4)
less_than_4_arf_period <= 1'b1;
else
less_than_4_arf_period <= 1'b0;
// pdn_period
if (pdn_period <= 4)
less_than_4_pdn_period <= 1'b1;
else
less_than_4_pdn_period <= 1'b0;
// act_to_act_diff_bank
if (act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
// four_act_to_act
if (four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
reg more_than_5_bank_active;
reg more_than_5_pch_to_act;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_5_bank_active <= 1'b0;
more_than_5_pch_to_act <= 1'b0;
end
else
begin
if (bank_active >= 5)
more_than_5_bank_active <= 1'b1;
else
more_than_5_bank_active <= 1'b0;
if (pch_to_act >= 5)
more_than_5_pch_to_act <= 1'b1;
else
more_than_5_pch_to_act <= 1'b0;
end
end
// compare wr_to_rd_to_pch_all with rd_to_pch
reg compare_wr_to_rd_to_pch_all;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_wr_to_rd_to_pch_all <= 1'b0;
end
else
begin
if (wr_to_rd_to_pch_all > rd_to_pch)
compare_wr_to_rd_to_pch_all <= 1'b1;
else
compare_wr_to_rd_to_pch_all <= 1'b0;
end
end
// DIV is a divider for our timinf parameters, DIV will be '1' in fullrate and '2' in halfrate
localparam DIV = DWIDTH_RATIO / 2;
// All timing parameters will be divided by DIV and added with modulo of DIV
// This is to maximize out timing parameter in our halfrate memory controller
// eg: if we have 5 + 4 + 3 = 12 which is an odd number, the desired value we need in halfrate is 6
// we don't want to divide all timing parameters in Java by '2'
// because this will result in 3 + 2 + 2 = 7 (5/2 gives 3 because we don't want any floating points in RTL)
// Common timing parameters
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bank_active <= 0;
act_to_pch <= 0;
act_to_act <= 0;
pch_to_act <= 0;
pch_all_to_act <= 0;
arf_to_valid <= 0;
pdn_to_valid <= 0;
srf_to_valid <= 0;
arf_period <= 0;
pdn_period <= 0;
act_to_act_diff_bank <= 0;
four_act_to_act <= 0;
rd_ap_to_act <= 0;
wr_ap_to_act <= 0;
wr_to_rd_to_pch_all <= 0;
end
else
begin
bank_active <= (mem_trcd / DIV) + (mem_trcd % DIV) - 1; // ACT to RD/WR - tRCD (minus '1' because state machine requires another extra clock cycle for pre-processing)
act_to_pch <= (mem_tras / DIV) + (mem_tras % DIV); // ACT to PCH - tRAS
act_to_act <= (mem_trc / DIV) + (mem_trc % DIV); // ACT to ACT (same bank) - tRC
pch_to_act <= (mem_trp / DIV) + (mem_trp % DIV); // PCH to ACT - tRP
pch_all_to_act <= ((mem_trp + 1) / DIV) + ((mem_trp + 1) % DIV); // PCH All to ACT - tRPA
arf_to_valid <= (mem_trfc / DIV) + (mem_trfc % DIV); // ARF to VALID - tRFC
pdn_to_valid <= (3 / DIV) + (3 % DIV); // PDN to VALID - normally 3 clock cycles
srf_to_valid <= (mem_self_rfsh_exit_cycles / DIV) + (mem_self_rfsh_exit_cycles % DIV); // SRF to VALID - normally 200 clock cycles
arf_period <= (mem_trefi / DIV) + (mem_trefi % DIV); // ARF period - tREFI
pdn_period <= (mem_auto_pd_cycles / DIV) + (mem_auto_pd_cycles % DIV); // PDN count after CMD_QUEUE is empty - spepcified by users, 10 maybe?
act_to_act_diff_bank <= (mem_trrd / DIV) + (mem_trrd % DIV); // ACT to ACT (diff banks) - tRRD
four_act_to_act <= (mem_tfaw / DIV) + (mem_tfaw % DIV) - 4; // Valid window for 4 ACT - tFAW (minus '4' because of the tFAW logic)
rd_ap_to_act <= rd_to_pch + pch_to_act; // RD with auto precharge to ACT
wr_ap_to_act <= wr_to_pch + pch_to_act; // WR with auto precharge to ACT
if (wr_to_pch > wr_to_rd)
wr_to_rd_to_pch_all <= wr_to_pch - wr_to_rd; // this is required to fix wr - rd - pch all bug (see RD state in alt_ddrx_timers_fsm)
else
wr_to_rd_to_pch_all <= 0;
end
end
// Memory specific timing parameters
generate
if (MEM_TYPE == "DDR")
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_to_rd <= 0;
rd_to_wr <= 0;
rd_to_pch <= 0;
wr_to_wr <= 0;
wr_to_rd <= 0;
wr_to_pch <= 0;
lmr_to_lmr <= 0;
lmr_to_valid <= 0;
finish_write <= 0;
finish_read <= 0;
wr_to_rd_diff_chips <= 0;
end
else
begin
rd_to_rd <= (2 / DIV); // RD to RD - tCCD
rd_to_wr <= ((mem_tcl + (mem_burst_length / 2) + mem_rd_to_wr_turnaround_oct) / DIV) + ((mem_tcl + (mem_burst_length / 2) + mem_rd_to_wr_turnaround_oct) % DIV); // RD to WR - CAS + (BL/2)
rd_to_pch <= ((mem_burst_length / 2) / DIV); // RD to PCH - (BL/2)
wr_to_wr <= (2 / DIV); // WR to WR - tCCD
wr_to_rd <= ((1 + (mem_burst_length / 2) + mem_twtr + mem_wr_to_rd_turnaround_oct) / DIV) + ((1 + (mem_burst_length / 2) + mem_twtr + mem_wr_to_rd_turnaround_oct) % DIV); // WR to RD - WL + (BL/2) + tWTR (WL is always 1 in DDR)
wr_to_pch <= ((1 + (mem_burst_length / 2) + mem_twr) / DIV) + ((1 + (mem_burst_length / 2) + mem_twr) % DIV); // WR to PCH - WL + (BL/2) + tWR
wr_to_rd_diff_chips <= (((mem_burst_length / 2) + 3 + mem_wr_to_rd_turnaround_oct) / DIV) + (((mem_burst_length / 2) + 3 + mem_wr_to_rd_turnaround_oct) % DIV); // WR to RD different rank - (WL - RL) + (BL/2) + 2 (dead cycles)
lmr_to_lmr <= (mem_tmrd / DIV) + (mem_tmrd % DIV); // LMR to LMR - tMRD
lmr_to_valid <= (mem_tmrd / DIV) + (mem_tmrd % DIV); // LMR to LMR - tMRD as well because there is no tMOD (LMR to VALID) in DDR
finish_write <= wr_to_pch + pch_to_act;
finish_read <= rd_to_pch + pch_to_act;
end
end
end
else if (MEM_TYPE == "DDR2")
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_to_rd <= 0;
rd_to_wr <= 0;
rd_to_pch <= 0;
wr_to_wr <= 0;
wr_to_rd <= 0;
wr_to_pch <= 0;
lmr_to_lmr <= 0;
lmr_to_valid <= 0;
finish_write <= 0;
finish_read <= 0;
wr_to_rd_diff_chips <= 0;
end
else
begin
rd_to_rd <= (4 / DIV); // tCCD is 2 but we set to 4 because we do burst length of 8
rd_to_wr <= (((mem_burst_length / 2) + 2 + mem_rd_to_wr_turnaround_oct) / DIV) + (((mem_burst_length / 2) + 2 + mem_rd_to_wr_turnaround_oct) % DIV);
rd_to_pch <= ((mem_add_lat + (mem_burst_length / 2) - 2 + max(mem_trtp, 2)) / DIV) + ((mem_add_lat + (mem_burst_length / 2) - 2 + max(mem_trtp, 2)) % DIV);
wr_to_wr <= (4 / DIV); // tCCD is 2 but we set to 4 because we do burst length of 8
wr_to_rd <= ((mem_tcl - 1 + (mem_burst_length / 2) + mem_twtr + mem_wr_to_rd_turnaround_oct) / DIV) + ((mem_tcl - 1 + (mem_burst_length / 2) + mem_twtr + mem_wr_to_rd_turnaround_oct) % DIV); // removed add lat because write and read is CAS command (add lat)
wr_to_pch <= ((mem_add_lat + mem_tcl - 1 + (mem_burst_length / 2) + mem_twr) / DIV) + ((mem_add_lat + mem_tcl - 1 + (mem_burst_length / 2) + mem_twr) % DIV);
wr_to_rd_diff_chips <= (((mem_burst_length / 2) + 1 + mem_wr_to_rd_turnaround_oct) / DIV) + (((mem_burst_length / 2) + 1 + mem_wr_to_rd_turnaround_oct) % DIV);
lmr_to_lmr <= (mem_tmrd / DIV) + (mem_tmrd % DIV);
lmr_to_valid <= (mem_tmod / DIV) + (mem_tmod % DIV);
finish_write <= wr_to_pch + pch_to_act;
finish_read <= rd_to_pch + pch_to_act;
end
end
end
else if (MEM_TYPE == "DDR3")
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rd_to_rd <= 0;
rd_to_wr <= 0;
rd_to_wr_bc <= 0;
rd_to_pch <= 0;
wr_to_wr <= 0;
wr_to_rd <= 0;
wr_to_pch <= 0;
lmr_to_lmr <= 0;
lmr_to_valid <= 0;
finish_write <= 0;
finish_read <= 0;
wr_to_rd_diff_chips <= 0;
srf_to_zq <= 0; // DDR3 specific
end
else
begin
rd_to_rd <= (4 / DIV);
rd_to_wr <= ((mem_tcl - mem_cas_wr_lat + 4 + 2 + mem_rd_to_wr_turnaround_oct) / DIV) + ((mem_tcl - mem_cas_wr_lat + 4 + 2 + mem_rd_to_wr_turnaround_oct) % DIV); // cas lat - cas wr lat + tCCD + 2
rd_to_wr_bc <= ((mem_tcl - mem_cas_wr_lat + 2 + 2 + mem_rd_to_wr_turnaround_oct) / DIV) + ((mem_tcl - mem_cas_wr_lat + 2 + 2 + mem_rd_to_wr_turnaround_oct) % DIV); // tCCD/2 <= 2
rd_to_pch <= ((mem_add_lat + max(mem_trtp, 4)) / DIV) + ((mem_add_lat + max(mem_trtp, 4)) % DIV);
wr_to_wr <= (4 / DIV);
wr_to_rd <= ((mem_cas_wr_lat + (mem_burst_length / 2) + max(mem_twtr, 4) + mem_wr_to_rd_turnaround_oct) / DIV) + ((mem_cas_wr_lat + (mem_burst_length / 2) + max(mem_twtr, 4) + mem_wr_to_rd_turnaround_oct) % DIV); // reported by Denali, WR to RD delay is add_lat + cas_wr_lat + (bl/2) + max(tCCD or tWTR)
wr_to_pch <= ((mem_add_lat + mem_cas_wr_lat + (mem_burst_length / 2) + mem_twr) / DIV) + ((mem_add_lat + mem_cas_wr_lat + (mem_burst_length / 2) + mem_twr) % DIV);
wr_to_rd_diff_chips <= (((mem_cas_wr_lat - mem_tcl) + (mem_burst_length / 2) + 2 + mem_wr_to_rd_turnaround_oct) / DIV) + (((mem_cas_wr_lat - mem_tcl) + (mem_burst_length / 2) + 2 + mem_wr_to_rd_turnaround_oct) % DIV);
lmr_to_lmr <= (mem_tmrd / DIV) + (mem_tmrd % DIV);
lmr_to_valid <= (mem_tmod / DIV) + (mem_tmod % DIV);
finish_write <= wr_to_pch + pch_to_act;
finish_read <= rd_to_pch + pch_to_act;
srf_to_zq <= (256 / DIV);
end
end
end
endgenerate
// function to determine max of 2 inputs
function reg [WR_TO_RD_WIDTH - 1 : 0] max;
input [WR_TO_RD_WIDTH - 1 : 0] value1;
input [WR_TO_RD_WIDTH - 1 : 0] value2;
begin
if (value1 > value2)
max = value1;
else
max = value2;
end
endfunction
// indicate additive latency is on to state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
add_lat_on <= 1'b0;
end
else
begin
if (mem_add_lat == 0)
begin
if (bank_active == 0)
add_lat_on <= 1'b1;
else
add_lat_on <= 1'b0;
end
else
begin
// if AL is greater than tRCD-1, then we can do back to back activate-read/write
if (mem_add_lat >= (mem_trcd - 1))
add_lat_on <= 1'b1;
else
add_lat_on <= 1'b0;
end
end
end
// states for our DQS bus monitor state machine
localparam IDLE = 32'h49444C45;
localparam WR = 32'h20205752;
localparam RD = 32'h20205244;
// width parameters for our counters
localparam RD_WR_COUNTER_WIDTH = 7;
localparam ACTIVATE_COUNTER_WIDTH = 6; // 8-32
localparam PDN_COUNTER_WIDTH = AUTO_PD_BUS_WIDTH;
localparam ARF_COUNTER_WIDTH = TREFI_BUS_WIDTH;
reg [31 : 0] state;
reg [RD_WR_COUNTER_WIDTH - 1 : 0] cnt;
reg dqs_ready;
reg doing_burst_chop;
reg read_dqs_ready;
reg write_dqs_ready;
reg [MEM_IF_CS_WIDTH - 1 : 0] write_to_read_finish_twtr;
reg [WR_TO_RD_WIDTH - 1 : 0] twtr_cnt [MEM_IF_CS_WIDTH - 1 : 0];
reg [MEM_IF_CS_WIDTH - 1 : 0] to_chip_r1;
// Num of CSs * Num of Banks
reg [2 ** MEM_IF_BA_WIDTH - 1 : 0] bus_do_precharge_all [MEM_IF_CS_WIDTH - 1 : 0];
reg [2 ** MEM_IF_BA_WIDTH - 1 : 0] bus_do_refresh [MEM_IF_CS_WIDTH - 1 : 0];
reg [2 ** MEM_IF_BA_WIDTH - 1 : 0] bus_do_power_down [MEM_IF_CS_WIDTH - 1 : 0];
reg [2 ** MEM_IF_BA_WIDTH - 1 : 0] bus_do_self_rfsh [MEM_IF_CS_WIDTH - 1 : 0];
reg [2 ** MEM_IF_BA_WIDTH - 1 : 0] bus_do_lmr [MEM_IF_CS_WIDTH - 1 : 0];
reg [2 ** MEM_IF_BA_WIDTH - 1 : 0] do_enable [MEM_IF_CS_WIDTH - 1 : 0];
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_activate;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_precharge;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_write;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_read;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_refresh;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_power_down;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_self_rfsh;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_cmd_do_activate_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_cmd_do_precharge_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_cmd_do_write_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_cmd_do_read_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_cmd_do_refresh_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_cmd_do_power_down_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_cmd_do_self_rfsh_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_activate_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_precharge_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_write_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_read_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_refresh_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_power_down_r1;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_self_rfsh_r1;
reg [CTL_LOOK_AHEAD_DEPTH : 0] bus_can_read_reg;
reg [CTL_LOOK_AHEAD_DEPTH : 0] bus_can_write_reg;
reg [CTL_LOOK_AHEAD_DEPTH : 0] bus_can_activate_reg;
reg [CTL_LOOK_AHEAD_DEPTH : 0] bus_can_precharge_reg;
reg [MEM_IF_CS_WIDTH - 1 : 0] delay_can_exit_power_saving_mode;
reg [MEM_IF_CS_WIDTH - 1 : 0] non_delay_can_exit_power_saving_mode;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_can_refresh;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_can_enter_power_down;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_can_exit_power_saving_mode;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_can_exit_power_saving_mode_r1;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_can_self_rfsh;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_can_lmr;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_zq_cal_req;
reg [MEM_IF_CS_WIDTH - 1 : 0] can_precharge_all;
reg [MEM_IF_CS_WIDTH - 1 : 0] can_refresh;
reg [MEM_IF_CS_WIDTH - 1 : 0] can_enter_power_down;
reg [MEM_IF_CS_WIDTH - 1 : 0] can_exit_power_saving_mode;
reg [MEM_IF_CS_WIDTH - 1 : 0] can_self_rfsh;
reg [MEM_IF_CS_WIDTH - 1 : 0] can_lmr;
reg zq_cal_req;
reg [MEM_IF_CS_WIDTH - 1 : 0] act_diff_bank;
reg [MEM_IF_CS_WIDTH - 1 : 0] act_valid_window;
reg do_power_down_r1;
reg no_command;
reg no_command_r1;
reg power_down_req;
reg [PDN_COUNTER_WIDTH : 0] power_down_cnt;
wire auto_refresh_req;
reg [MEM_IF_CS_WIDTH - 1 : 0] auto_refresh_chip;
reg [ARF_COUNTER_WIDTH - 1 : 0] auto_refresh_cnt [MEM_IF_CS_WIDTH - 1 : 0];
reg doing_write;
reg doing_read;
reg enable_chip_request;
reg enable_chip_request_ddr2;
reg [FINISH_WRITE_WIDTH - 1 : 0] chip_request_cnt;
reg [MEM_IF_CS_WIDTH - 1 : 0] doing_auto_pch;
reg [MEM_IF_CS_WIDTH - 1 : 0] enable_chip_request_trc_done;
reg [ACT_TO_ACT_WIDTH - 1 : 0] trc_cnt [MEM_IF_CS_WIDTH - 1 : 0];
reg [CTL_CMD_QUEUE_DEPTH : 0] int_cmd_is_valid;
reg int_cmd_is_valid_r1;
reg cmd_cache;
reg ecc_fetch_error_addr_r1;
reg fetch_r1;
reg [1 : 0] flush;
reg chip_change;
reg prev_multicast_req;
reg [MEM_IF_CHIP_BITS - 1 : 0] prev_chip_addr;
reg can_read_current;
reg can_write_current;
reg [1 : 0] can_read;
reg [1 : 0] can_write;
reg can_activate_current;
reg can_precharge_current;
wire [CTL_LOOK_AHEAD_DEPTH - 1 : 0] can_activate;
wire [CTL_LOOK_AHEAD_DEPTH - 1 : 0] can_precharge;
reg [CTL_CMD_QUEUE_DEPTH - 1 : 0] int_can_activate;
reg [CTL_CMD_QUEUE_DEPTH - 1 : 0] int_can_precharge;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_bus_can_read_reg;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_bus_can_write_reg;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_bus_can_activate_reg;
reg [CTL_CMD_QUEUE_DEPTH : 0] int_bus_can_precharge_reg;
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_read [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_write [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_activate [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_activate_chip [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_precharge [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_refresh [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_power_down [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_self_rfsh [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_can_lmr [MEM_IF_CS_WIDTH - 1 : 0];
wire [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bus_zq_cal_req [MEM_IF_CS_WIDTH - 1 : 0];
wire [(CTL_CMD_QUEUE_DEPTH + 1) * MEM_IF_BA_WIDTH - 1 : 0] cmd_bank_addr;
wire [(CTL_CMD_QUEUE_DEPTH + 1) * MEM_IF_CHIP_BITS - 1 : 0] cmd_chip_addr;
wire [CTL_CMD_QUEUE_DEPTH : 0] cmd_is_valid;
wire [CTL_CMD_QUEUE_DEPTH : 0] multicast_req;
wire [CTL_CMD_QUEUE_DEPTH : 0] is_a_write;
wire [CTL_CMD_QUEUE_DEPTH : 0] is_a_read;
wire [CTL_CMD_QUEUE_DEPTH : 0] cmd_multicast_req;
//assign cmd_addr = {cmd7_addr, cmd6_addr, cmd5_addr, cmd4_addr, cmd3_addr, cmd2_addr, cmd1_addr, cmd0_addr, current_addr};
assign cmd_chip_addr = {cmd7_chip_addr, cmd6_chip_addr, cmd5_chip_addr, cmd4_chip_addr, cmd3_chip_addr, cmd2_chip_addr, cmd1_chip_addr, cmd0_chip_addr, current_chip_addr};
assign cmd_bank_addr = {cmd7_bank_addr, cmd6_bank_addr, cmd5_bank_addr, cmd4_bank_addr, cmd3_bank_addr, cmd2_bank_addr, cmd1_bank_addr, cmd0_bank_addr, current_bank_addr};
assign cmd_is_valid = {cmd7_is_valid, cmd6_is_valid, cmd5_is_valid, cmd4_is_valid, cmd3_is_valid, cmd2_is_valid, cmd1_is_valid, cmd0_is_valid, 1'b0}; // current signal doesn't have valid signal
assign multicast_req = {cmd7_multicast_req, cmd6_multicast_req, cmd5_multicast_req, cmd4_multicast_req, cmd3_multicast_req, cmd2_multicast_req, cmd1_multicast_req, cmd0_multicast_req, current_multicast_req};
assign is_a_write = {cmd7_is_a_write, cmd6_is_a_write, cmd5_is_a_write, cmd4_is_a_write, cmd3_is_a_write, cmd2_is_a_write, cmd1_is_a_write, cmd0_is_a_write, current_is_a_write};
assign is_a_read = {cmd7_is_a_read, cmd6_is_a_read, cmd5_is_a_read, cmd4_is_a_read, cmd3_is_a_read, cmd2_is_a_read, cmd1_is_a_read, cmd0_is_a_read, current_is_a_read};
// we only need to assert multicast request during write because during read with multicast (supported in the future) state machine will choose one of the chip to read
assign cmd_multicast_req = multicast_req & is_a_write;
/*------------------------------------------------------------------------------
Input Bus
------------------------------------------------------------------------------*/
// This signal will indicate the banks specific state machine whether the current do signal is valid
generate
genvar z_outer;
genvar z_inner;
for (z_outer = 0;z_outer < MEM_IF_CS_WIDTH;z_outer = z_outer + 1)
begin : input_do_signal_fanout_per_chip
for (z_inner = 0;z_inner < 2 ** MEM_IF_BA_WIDTH; z_inner = z_inner + 1)
begin : input_do_signal_fanout_per_bank
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
do_enable [z_outer][z_inner] <= 1'b0;
else
begin
if (to_chip [z_outer] && z_inner == to_bank_addr)
do_enable [z_outer][z_inner] <= 1'b1;
else
do_enable [z_outer][z_inner] <= 1'b0;
end
end
end
end
endgenerate
reg do_write_r1;
reg do_read_r1;
reg do_activate_r1;
reg do_precharge_r1;
reg do_auto_precharge_r1;
reg do_precharge_all_r1;
reg do_refresh_r1;
reg do_self_rfsh_r1;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_write_r1 <= 1'b0;
do_read_r1 <= 1'b0;
do_activate_r1 <= 1'b0;
do_precharge_r1 <= 1'b0;
do_auto_precharge_r1 <= 1'b0;
do_precharge_all_r1 <= 1'b0;
do_refresh_r1 <= 1'b0;
do_self_rfsh_r1 <= 1'b0;
end
else
begin
do_write_r1 <= do_write;
do_read_r1 <= do_read;
do_activate_r1 <= do_activate;
do_precharge_r1 <= do_precharge;
do_auto_precharge_r1 <= do_auto_precharge;
do_precharge_all_r1 <= do_precharge_all;
do_refresh_r1 <= do_refresh;
do_self_rfsh_r1 <= do_self_rfsh;
end
end
// Fanout of refresh and power down signal to one bank per chip only (first bank), this is to reduce number of resource used in this design
// Quartus will optimize away registers and ALUTs which are not used (not connected)
generate
genvar w;
for (w = 0;w < MEM_IF_CS_WIDTH; w = w + 1)
begin : input_signal_fanout_per_chip
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bus_do_precharge_all [w][2 ** MEM_IF_BA_WIDTH - 1 : 0] <= 0;
end
else
begin
if (do_precharge_all && to_chip[w])
bus_do_precharge_all [w][2 ** MEM_IF_BA_WIDTH - 1 : 0] <= {(2 ** MEM_IF_BA_WIDTH){1'b1}};
else
bus_do_precharge_all [w][2 ** MEM_IF_BA_WIDTH - 1 : 0] <= 0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
bus_do_refresh [w][0] <= 1'b0;
bus_do_power_down [w][0] <= 1'b0;
bus_do_self_rfsh [w][0] <= 1'b0;
bus_do_lmr [w][0] <= 1'b0;
end
else
begin
if (do_refresh && to_chip[w])
bus_do_refresh [w][0] <= 1'b1;
else
bus_do_refresh [w][0] <= 1'b0;
if (do_power_down && to_chip[w])
bus_do_power_down [w][0] <= 1'b1;
else
bus_do_power_down [w][0] <= 1'b0;
if (do_self_rfsh && to_chip[w])
bus_do_self_rfsh [w][0] <= 1'b1;
else
bus_do_self_rfsh [w][0] <= 1'b0;
if (do_lmr && to_chip[w])
bus_do_lmr [w][0] <= 1'b1;
else
bus_do_lmr [w][0] <= 1'b0;
end
end
end
endgenerate
// Fanout of do activate, precharge, read and write signal for current and command queue
// will use these signals to manipulate can signals to state machine
generate
genvar p;
for (p = 0;p < CTL_LOOK_AHEAD_DEPTH + 1;p = p + 1)
begin : input_do_signal_fanout_per_cmd
wire [MEM_IF_BA_WIDTH - 1 : 0] bank_addr = cmd_bank_addr [(p + 1) * MEM_IF_BA_WIDTH - 1 : p * MEM_IF_BA_WIDTH];
wire [MEM_IF_CHIP_BITS - 1 : 0] chip_addr = cmd_chip_addr [(p + 1) * MEM_IF_CHIP_BITS - 1 : p * MEM_IF_CHIP_BITS];
always @ (*)
begin
// do_activate
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_activate && to_bank_addr == bank_addr)
cmd_do_activate [p] = 1'b1;
else
cmd_do_activate [p] = 1'b0;
end
else
begin
if (do_activate && to_chip [chip_addr] && to_bank_addr == bank_addr)
cmd_do_activate [p] = 1'b1;
else
cmd_do_activate [p] = 1'b0;
end
// do_precharge
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (((do_auto_precharge || do_precharge) && to_bank_addr == bank_addr) || do_precharge_all)
cmd_do_precharge [p] = 1'b1;
else
cmd_do_precharge [p] = 1'b0;
end
else
begin
if ((((do_auto_precharge || do_precharge) && to_bank_addr == bank_addr) || do_precharge_all) && to_chip [chip_addr])
cmd_do_precharge [p] = 1'b1;
else
cmd_do_precharge [p] = 1'b0;
end
// do_write
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_write && to_bank_addr == bank_addr)
cmd_do_write [p] = 1'b1;
else
cmd_do_write [p] = 1'b0;
end
else
begin
if (do_write && to_chip [chip_addr] && to_bank_addr == bank_addr)
cmd_do_write [p] = 1'b1;
else
cmd_do_write [p] = 1'b0;
end
// do_read
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_read && to_bank_addr == bank_addr)
cmd_do_read [p] = 1'b1;
else
cmd_do_read [p] = 1'b0;
end
else
begin
if (do_read && to_chip [chip_addr] && to_bank_addr == bank_addr)
cmd_do_read [p] = 1'b1;
else
cmd_do_read [p] = 1'b0;
end
// do_refresh
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_refresh)
cmd_do_refresh [p] = 1'b1;
else
cmd_do_refresh [p] = 1'b0;
end
else
begin
if (do_refresh && to_chip [chip_addr])
cmd_do_refresh [p] = 1'b1;
else
cmd_do_refresh [p] = 1'b0;
end
// do_power_down
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_power_down)
cmd_do_power_down [p] = 1'b1;
else
cmd_do_power_down [p] = 1'b0;
end
else
begin
if (do_power_down && to_chip [chip_addr])
cmd_do_power_down [p] = 1'b1;
else
cmd_do_power_down [p] = 1'b0;
end
// do_self_rfsh
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_self_rfsh)
cmd_do_self_rfsh [p] = 1'b1;
else
cmd_do_self_rfsh [p] = 1'b0;
end
else
begin
if (do_self_rfsh && to_chip [chip_addr])
cmd_do_self_rfsh [p] = 1'b1;
else
cmd_do_self_rfsh [p] = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_cmd_do_activate_r1 [p] <= 1'b0;
int_cmd_do_precharge_r1 [p] <= 1'b0;
int_cmd_do_write_r1 [p] <= 1'b0;
int_cmd_do_read_r1 [p] <= 1'b0;
int_cmd_do_refresh_r1 [p] <= 1'b0;
int_cmd_do_power_down_r1 [p] <= 1'b0;
int_cmd_do_self_rfsh_r1 [p] <= 1'b0;
end
else
begin
// do_activate
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_activate && to_bank_addr == bank_addr)
int_cmd_do_activate_r1 [p] <= 1'b1;
else
int_cmd_do_activate_r1 [p] <= 1'b0;
end
else
begin
if (do_activate && to_chip [chip_addr] && to_bank_addr == bank_addr)
int_cmd_do_activate_r1 [p] <= 1'b1;
else
int_cmd_do_activate_r1 [p] <= 1'b0;
end
// do_precharge
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (((do_auto_precharge || do_precharge) && to_bank_addr == bank_addr) || do_precharge_all)
int_cmd_do_precharge_r1 [p] <= 1'b1;
else
int_cmd_do_precharge_r1 [p] <= 1'b0;
end
else
begin
if ((((do_auto_precharge || do_precharge) && to_bank_addr == bank_addr) || do_precharge_all) && to_chip [chip_addr])
int_cmd_do_precharge_r1 [p] <= 1'b1;
else
int_cmd_do_precharge_r1 [p] <= 1'b0;
end
// do_write
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_write && to_bank_addr == bank_addr)
int_cmd_do_write_r1 [p] <= 1'b1;
else
int_cmd_do_write_r1 [p] <= 1'b0;
end
else
begin
if (do_write && to_chip [chip_addr] && to_bank_addr == bank_addr)
int_cmd_do_write_r1 [p] <= 1'b1;
else
int_cmd_do_write_r1 [p] <= 1'b0;
end
// do_read
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_read && to_bank_addr == bank_addr)
int_cmd_do_read_r1 [p] <= 1'b1;
else
int_cmd_do_read_r1 [p] <= 1'b0;
end
else
begin
if (do_read && to_chip [chip_addr] && to_bank_addr == bank_addr)
int_cmd_do_read_r1 [p] <= 1'b1;
else
int_cmd_do_read_r1 [p] <= 1'b0;
end
// do_refresh
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_refresh)
int_cmd_do_refresh_r1 [p] = 1'b1;
else
int_cmd_do_refresh_r1 [p] = 1'b0;
end
else
begin
if (do_refresh && to_chip [chip_addr])
int_cmd_do_refresh_r1 [p] = 1'b1;
else
int_cmd_do_refresh_r1 [p] = 1'b0;
end
// do_power_down
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_power_down)
int_cmd_do_power_down_r1 [p] = 1'b1;
else
int_cmd_do_power_down_r1 [p] = 1'b0;
end
else
begin
if (do_power_down && to_chip [chip_addr])
int_cmd_do_power_down_r1 [p] = 1'b1;
else
int_cmd_do_power_down_r1 [p] = 1'b0;
end
// do_self_rfsh
if (cmd_multicast_req [p]) // don't care to_chip during multicast
begin
if (do_self_rfsh)
int_cmd_do_self_rfsh_r1 [p] = 1'b1;
else
int_cmd_do_self_rfsh_r1 [p] = 1'b0;
end
else
begin
if (do_self_rfsh && to_chip [chip_addr])
int_cmd_do_self_rfsh_r1 [p] = 1'b1;
else
int_cmd_do_self_rfsh_r1 [p] = 1'b0;
end
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Output Bus
------------------------------------------------------------------------------*/
assign can_activate = int_can_activate [CTL_LOOK_AHEAD_DEPTH - 1 : 0];
assign can_precharge = int_can_precharge [CTL_LOOK_AHEAD_DEPTH - 1 : 0];
/*------------------------------------------------------------------------------
Caching the outputs
------------------------------------------------------------------------------*/
always @ (*)
begin
if (cmd_cache)
begin
if (flush == 2'b01)
begin
can_read_current = int_bus_can_read_reg [2];
can_read [0] = int_bus_can_read_reg [3];
can_read [1] = int_bus_can_read_reg [4];
can_write_current = int_bus_can_write_reg [2];
can_write [0] = int_bus_can_write_reg [3];
can_write [1] = int_bus_can_write_reg [4];
// cmd do signal (registered version)
cmd_do_activate_r1 [0] = int_cmd_do_activate_r1 [2];
cmd_do_activate_r1 [1] = int_cmd_do_activate_r1 [3];
cmd_do_activate_r1 [2] = int_cmd_do_activate_r1 [4];
cmd_do_activate_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [5];
cmd_do_activate_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [6];
cmd_do_activate_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [7];
cmd_do_activate_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [8];
cmd_do_activate_r1 [7] = 1'b0;
cmd_do_activate_r1 [8] = 1'b0;
cmd_do_precharge_r1 [0] = int_cmd_do_precharge_r1 [2];
cmd_do_precharge_r1 [1] = int_cmd_do_precharge_r1 [3];
cmd_do_precharge_r1 [2] = int_cmd_do_precharge_r1 [4];
cmd_do_precharge_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [5];
cmd_do_precharge_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [6];
cmd_do_precharge_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [7];
cmd_do_precharge_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [8];
cmd_do_precharge_r1 [7] = 1'b0;
cmd_do_precharge_r1 [8] = 1'b0;
cmd_do_write_r1 [0] = int_cmd_do_write_r1 [2];
cmd_do_write_r1 [1] = int_cmd_do_write_r1 [3];
cmd_do_write_r1 [2] = int_cmd_do_write_r1 [4];
cmd_do_write_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [5];
cmd_do_write_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [6];
cmd_do_write_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [7];
cmd_do_write_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [8];
cmd_do_write_r1 [7] = 1'b0;
cmd_do_write_r1 [8] = 1'b0;
cmd_do_read_r1 [0] = int_cmd_do_read_r1 [2];
cmd_do_read_r1 [1] = int_cmd_do_read_r1 [3];
cmd_do_read_r1 [2] = int_cmd_do_read_r1 [4];
cmd_do_read_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [5];
cmd_do_read_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [6];
cmd_do_read_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [7];
cmd_do_read_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [8];
cmd_do_read_r1 [7] = 1'b0;
cmd_do_read_r1 [8] = 1'b0;
//cmd_do_refresh_r1 [0] = int_cmd_do_refresh_r1 [2];
//cmd_do_refresh_r1 [1] = int_cmd_do_refresh_r1 [3];
//cmd_do_refresh_r1 [2] = int_cmd_do_refresh_r1 [4];
//cmd_do_refresh_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [5];
//cmd_do_refresh_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [6];
//cmd_do_refresh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [7];
//cmd_do_refresh_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [8];
//cmd_do_refresh_r1 [7] = 1'b0;
//cmd_do_refresh_r1 [8] = 1'b0;
//
//cmd_do_power_down_r1 [0] = int_cmd_do_power_down_r1 [2];
//cmd_do_power_down_r1 [1] = int_cmd_do_power_down_r1 [3];
//cmd_do_power_down_r1 [2] = int_cmd_do_power_down_r1 [4];
//cmd_do_power_down_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [5];
//cmd_do_power_down_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [6];
//cmd_do_power_down_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [7];
//cmd_do_power_down_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [8];
//cmd_do_power_down_r1 [7] = 1'b0;
//cmd_do_power_down_r1 [8] = 1'b0;
//
//cmd_do_self_rfsh_r1 [0] = int_cmd_do_self_rfsh_r1 [2];
//cmd_do_self_rfsh_r1 [1] = int_cmd_do_self_rfsh_r1 [3];
//cmd_do_self_rfsh_r1 [2] = int_cmd_do_self_rfsh_r1 [4];
//cmd_do_self_rfsh_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [5];
//cmd_do_self_rfsh_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [6];
//cmd_do_self_rfsh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [7];
//cmd_do_self_rfsh_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [8];
//cmd_do_self_rfsh_r1 [7] = 1'b0;
//cmd_do_self_rfsh_r1 [8] = 1'b0;
end
else if (flush == 2'b10)
begin
can_read_current = int_bus_can_read_reg [3];
can_read [0] = int_bus_can_read_reg [4];
can_read [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_read_reg [5];
can_write_current = int_bus_can_write_reg [3];
can_write [0] = int_bus_can_write_reg [4];
can_write [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_write_reg [5];
// cmd do signal (registered version)
cmd_do_activate_r1 [0] = int_cmd_do_activate_r1 [3];
cmd_do_activate_r1 [1] = int_cmd_do_activate_r1 [4];
cmd_do_activate_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [5];
cmd_do_activate_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [6];
cmd_do_activate_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [7];
cmd_do_activate_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [8];
cmd_do_activate_r1 [6] = 1'b0;
cmd_do_activate_r1 [7] = 1'b0;
cmd_do_activate_r1 [8] = 1'b0;
cmd_do_precharge_r1 [0] = int_cmd_do_precharge_r1 [3];
cmd_do_precharge_r1 [1] = int_cmd_do_precharge_r1 [4];
cmd_do_precharge_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [5];
cmd_do_precharge_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [6];
cmd_do_precharge_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [7];
cmd_do_precharge_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [8];
cmd_do_precharge_r1 [6] = 1'b0;
cmd_do_precharge_r1 [7] = 1'b0;
cmd_do_precharge_r1 [8] = 1'b0;
cmd_do_write_r1 [0] = int_cmd_do_write_r1 [3];
cmd_do_write_r1 [1] = int_cmd_do_write_r1 [4];
cmd_do_write_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [5];
cmd_do_write_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [6];
cmd_do_write_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [7];
cmd_do_write_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [8];
cmd_do_write_r1 [6] = 1'b0;
cmd_do_write_r1 [7] = 1'b0;
cmd_do_write_r1 [8] = 1'b0;
cmd_do_read_r1 [0] = int_cmd_do_read_r1 [3];
cmd_do_read_r1 [1] = int_cmd_do_read_r1 [4];
cmd_do_read_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [5];
cmd_do_read_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [6];
cmd_do_read_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [7];
cmd_do_read_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [8];
cmd_do_read_r1 [6] = 1'b0;
cmd_do_read_r1 [7] = 1'b0;
cmd_do_read_r1 [8] = 1'b0;
//cmd_do_refresh_r1 [0] = int_cmd_do_refresh_r1 [3];
//cmd_do_refresh_r1 [1] = int_cmd_do_refresh_r1 [4];
//cmd_do_refresh_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [5];
//cmd_do_refresh_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [6];
//cmd_do_refresh_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [7];
//cmd_do_refresh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [8];
//cmd_do_refresh_r1 [6] = 1'b0;
//cmd_do_refresh_r1 [7] = 1'b0;
//cmd_do_refresh_r1 [8] = 1'b0;
//
//cmd_do_power_down_r1 [0] = int_cmd_do_power_down_r1 [3];
//cmd_do_power_down_r1 [1] = int_cmd_do_power_down_r1 [4];
//cmd_do_power_down_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [5];
//cmd_do_power_down_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [6];
//cmd_do_power_down_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [7];
//cmd_do_power_down_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [8];
//cmd_do_power_down_r1 [6] = 1'b0;
//cmd_do_power_down_r1 [7] = 1'b0;
//cmd_do_power_down_r1 [8] = 1'b0;
//
//cmd_do_self_rfsh_r1 [0] = int_cmd_do_self_rfsh_r1 [3];
//cmd_do_self_rfsh_r1 [1] = int_cmd_do_self_rfsh_r1 [4];
//cmd_do_self_rfsh_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [5];
//cmd_do_self_rfsh_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [6];
//cmd_do_self_rfsh_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [7];
//cmd_do_self_rfsh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [8];
//cmd_do_self_rfsh_r1 [6] = 1'b0;
//cmd_do_self_rfsh_r1 [7] = 1'b0;
//cmd_do_self_rfsh_r1 [8] = 1'b0;
end
else if (flush == 2'b11)
begin
can_read_current = int_bus_can_read_reg [4];
can_read [0] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_read_reg [5];
can_read [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_read_reg [6];
can_write_current = int_bus_can_write_reg [4];
can_write [0] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_write_reg [5];
can_write [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_write_reg [6];
// cmd do signal (registered version)
cmd_do_activate_r1 [0] = int_cmd_do_activate_r1 [4];
cmd_do_activate_r1 [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [5];
cmd_do_activate_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [6];
cmd_do_activate_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [7];
cmd_do_activate_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [8];
cmd_do_activate_r1 [5] = 1'b0;
cmd_do_activate_r1 [6] = 1'b0;
cmd_do_activate_r1 [7] = 1'b0;
cmd_do_activate_r1 [8] = 1'b0;
cmd_do_precharge_r1 [0] = int_cmd_do_precharge_r1 [4];
cmd_do_precharge_r1 [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [5];
cmd_do_precharge_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [6];
cmd_do_precharge_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [7];
cmd_do_precharge_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [8];
cmd_do_precharge_r1 [5] = 1'b0;
cmd_do_precharge_r1 [6] = 1'b0;
cmd_do_precharge_r1 [7] = 1'b0;
cmd_do_precharge_r1 [8] = 1'b0;
cmd_do_write_r1 [0] = int_cmd_do_write_r1 [4];
cmd_do_write_r1 [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [5];
cmd_do_write_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [6];
cmd_do_write_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [7];
cmd_do_write_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [8];
cmd_do_write_r1 [5] = 1'b0;
cmd_do_write_r1 [6] = 1'b0;
cmd_do_write_r1 [7] = 1'b0;
cmd_do_write_r1 [8] = 1'b0;
cmd_do_read_r1 [0] = int_cmd_do_read_r1 [4];
cmd_do_read_r1 [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [5];
cmd_do_read_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [6];
cmd_do_read_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [7];
cmd_do_read_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [8];
cmd_do_read_r1 [5] = 1'b0;
cmd_do_read_r1 [6] = 1'b0;
cmd_do_read_r1 [7] = 1'b0;
cmd_do_read_r1 [8] = 1'b0;
//cmd_do_refresh_r1 [0] = int_cmd_do_refresh_r1 [4];
//cmd_do_refresh_r1 [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [5];
//cmd_do_refresh_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [6];
//cmd_do_refresh_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [7];
//cmd_do_refresh_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [8];
//cmd_do_refresh_r1 [5] = 1'b0;
//cmd_do_refresh_r1 [6] = 1'b0;
//cmd_do_refresh_r1 [7] = 1'b0;
//cmd_do_refresh_r1 [8] = 1'b0;
//
//cmd_do_power_down_r1 [0] = int_cmd_do_power_down_r1 [4];
//cmd_do_power_down_r1 [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [5];
//cmd_do_power_down_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [6];
//cmd_do_power_down_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [7];
//cmd_do_power_down_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [8];
//cmd_do_power_down_r1 [5] = 1'b0;
//cmd_do_power_down_r1 [6] = 1'b0;
//cmd_do_power_down_r1 [7] = 1'b0;
//cmd_do_power_down_r1 [8] = 1'b0;
//
//cmd_do_self_rfsh_r1 [0] = int_cmd_do_self_rfsh_r1 [4];
//cmd_do_self_rfsh_r1 [1] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [5];
//cmd_do_self_rfsh_r1 [2] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [6];
//cmd_do_self_rfsh_r1 [3] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [7];
//cmd_do_self_rfsh_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [8];
//cmd_do_self_rfsh_r1 [5] = 1'b0;
//cmd_do_self_rfsh_r1 [6] = 1'b0;
//cmd_do_self_rfsh_r1 [7] = 1'b0;
//cmd_do_self_rfsh_r1 [8] = 1'b0;
end
else
begin
can_read_current = int_bus_can_read_reg [1];
can_read [0] = int_bus_can_read_reg [2];
can_read [1] = int_bus_can_read_reg [3];
can_write_current = int_bus_can_write_reg [1];
can_write [0] = int_bus_can_write_reg [2];
can_write [1] = int_bus_can_write_reg [3];
// cmd do signal (registered version)
cmd_do_activate_r1 [0] = int_cmd_do_activate_r1 [1];
cmd_do_activate_r1 [1] = int_cmd_do_activate_r1 [2];
cmd_do_activate_r1 [2] = int_cmd_do_activate_r1 [3];
cmd_do_activate_r1 [3] = int_cmd_do_activate_r1 [4];
cmd_do_activate_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [5];
cmd_do_activate_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [6];
cmd_do_activate_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [7];
cmd_do_activate_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [8];
cmd_do_activate_r1 [8] = 1'b0;
cmd_do_precharge_r1 [0] = int_cmd_do_precharge_r1 [1];
cmd_do_precharge_r1 [1] = int_cmd_do_precharge_r1 [2];
cmd_do_precharge_r1 [2] = int_cmd_do_precharge_r1 [3];
cmd_do_precharge_r1 [3] = int_cmd_do_precharge_r1 [4];
cmd_do_precharge_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [5];
cmd_do_precharge_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [6];
cmd_do_precharge_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [7];
cmd_do_precharge_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [8];
cmd_do_precharge_r1 [8] = 1'b0;
cmd_do_write_r1 [0] = int_cmd_do_write_r1 [1];
cmd_do_write_r1 [1] = int_cmd_do_write_r1 [2];
cmd_do_write_r1 [2] = int_cmd_do_write_r1 [3];
cmd_do_write_r1 [3] = int_cmd_do_write_r1 [4];
cmd_do_write_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [5];
cmd_do_write_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [6];
cmd_do_write_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [7];
cmd_do_write_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [8];
cmd_do_write_r1 [8] = 1'b0;
cmd_do_read_r1 [0] = int_cmd_do_read_r1 [1];
cmd_do_read_r1 [1] = int_cmd_do_read_r1 [2];
cmd_do_read_r1 [2] = int_cmd_do_read_r1 [3];
cmd_do_read_r1 [3] = int_cmd_do_read_r1 [4];
cmd_do_read_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [5];
cmd_do_read_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [6];
cmd_do_read_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [7];
cmd_do_read_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [8];
cmd_do_read_r1 [8] = 1'b0;
//cmd_do_refresh_r1 [0] = int_cmd_do_refresh_r1 [1];
//cmd_do_refresh_r1 [1] = int_cmd_do_refresh_r1 [2];
//cmd_do_refresh_r1 [2] = int_cmd_do_refresh_r1 [3];
//cmd_do_refresh_r1 [3] = int_cmd_do_refresh_r1 [4];
//cmd_do_refresh_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [5];
//cmd_do_refresh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [6];
//cmd_do_refresh_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [7];
//cmd_do_refresh_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [8];
//cmd_do_refresh_r1 [8] = 1'b0;
//
//cmd_do_power_down_r1 [0] = int_cmd_do_power_down_r1 [1];
//cmd_do_power_down_r1 [1] = int_cmd_do_power_down_r1 [2];
//cmd_do_power_down_r1 [2] = int_cmd_do_power_down_r1 [3];
//cmd_do_power_down_r1 [3] = int_cmd_do_power_down_r1 [4];
//cmd_do_power_down_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [5];
//cmd_do_power_down_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [6];
//cmd_do_power_down_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [7];
//cmd_do_power_down_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [8];
//cmd_do_power_down_r1 [8] = 1'b0;
//
//cmd_do_self_rfsh_r1 [0] = int_cmd_do_self_rfsh_r1 [1];
//cmd_do_self_rfsh_r1 [1] = int_cmd_do_self_rfsh_r1 [2];
//cmd_do_self_rfsh_r1 [2] = int_cmd_do_self_rfsh_r1 [3];
//cmd_do_self_rfsh_r1 [3] = int_cmd_do_self_rfsh_r1 [4];
//cmd_do_self_rfsh_r1 [4] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [5];
//cmd_do_self_rfsh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [6];
//cmd_do_self_rfsh_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [7];
//cmd_do_self_rfsh_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [8];
//cmd_do_self_rfsh_r1 [8] = 1'b0;
end
end
else
begin
can_read_current = int_bus_can_read_reg [0];
can_read [0] = int_bus_can_read_reg [1];
can_read [1] = int_bus_can_read_reg [2];
can_write_current = int_bus_can_write_reg [0];
can_write [0] = int_bus_can_write_reg [1];
can_write [1] = int_bus_can_write_reg [2];
// cmd do signal (registered version)
cmd_do_activate_r1 [0] = int_cmd_do_activate_r1 [0];
cmd_do_activate_r1 [1] = int_cmd_do_activate_r1 [1];
cmd_do_activate_r1 [2] = int_cmd_do_activate_r1 [2];
cmd_do_activate_r1 [3] = int_cmd_do_activate_r1 [3];
cmd_do_activate_r1 [4] = int_cmd_do_activate_r1 [4];
cmd_do_activate_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [5];
cmd_do_activate_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_r1 [6];
cmd_do_activate_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [7];
cmd_do_activate_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_r1 [8];
cmd_do_precharge_r1 [0] = int_cmd_do_precharge_r1 [0];
cmd_do_precharge_r1 [1] = int_cmd_do_precharge_r1 [1];
cmd_do_precharge_r1 [2] = int_cmd_do_precharge_r1 [2];
cmd_do_precharge_r1 [3] = int_cmd_do_precharge_r1 [3];
cmd_do_precharge_r1 [4] = int_cmd_do_precharge_r1 [4];
cmd_do_precharge_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [5];
cmd_do_precharge_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_r1 [6];
cmd_do_precharge_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [7];
cmd_do_precharge_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_r1 [8];
cmd_do_write_r1 [0] = int_cmd_do_write_r1 [0];
cmd_do_write_r1 [1] = int_cmd_do_write_r1 [1];
cmd_do_write_r1 [2] = int_cmd_do_write_r1 [2];
cmd_do_write_r1 [3] = int_cmd_do_write_r1 [3];
cmd_do_write_r1 [4] = int_cmd_do_write_r1 [4];
cmd_do_write_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [5];
cmd_do_write_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_write_r1 [6];
cmd_do_write_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [7];
cmd_do_write_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_write_r1 [8];
cmd_do_read_r1 [0] = int_cmd_do_read_r1 [0];
cmd_do_read_r1 [1] = int_cmd_do_read_r1 [1];
cmd_do_read_r1 [2] = int_cmd_do_read_r1 [2];
cmd_do_read_r1 [3] = int_cmd_do_read_r1 [3];
cmd_do_read_r1 [4] = int_cmd_do_read_r1 [4];
cmd_do_read_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [5];
cmd_do_read_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_read_r1 [6];
cmd_do_read_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [7];
cmd_do_read_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_read_r1 [8];
//cmd_do_refresh_r1 [0] = int_cmd_do_refresh_r1 [0];
//cmd_do_refresh_r1 [1] = int_cmd_do_refresh_r1 [1];
//cmd_do_refresh_r1 [2] = int_cmd_do_refresh_r1 [2];
//cmd_do_refresh_r1 [3] = int_cmd_do_refresh_r1 [3];
//cmd_do_refresh_r1 [4] = int_cmd_do_refresh_r1 [4];
//cmd_do_refresh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [5];
//cmd_do_refresh_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [6];
//cmd_do_refresh_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [7];
//cmd_do_refresh_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [8];
//
//cmd_do_power_down_r1 [0] = int_cmd_do_power_down_r1 [0];
//cmd_do_power_down_r1 [1] = int_cmd_do_power_down_r1 [1];
//cmd_do_power_down_r1 [2] = int_cmd_do_power_down_r1 [2];
//cmd_do_power_down_r1 [3] = int_cmd_do_power_down_r1 [3];
//cmd_do_power_down_r1 [4] = int_cmd_do_power_down_r1 [4];
//cmd_do_power_down_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [5];
//cmd_do_power_down_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [6];
//cmd_do_power_down_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [7];
//cmd_do_power_down_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [8];
//
//cmd_do_self_rfsh_r1 [0] = int_cmd_do_self_rfsh_r1 [0];
//cmd_do_self_rfsh_r1 [1] = int_cmd_do_self_rfsh_r1 [1];
//cmd_do_self_rfsh_r1 [2] = int_cmd_do_self_rfsh_r1 [2];
//cmd_do_self_rfsh_r1 [3] = int_cmd_do_self_rfsh_r1 [3];
//cmd_do_self_rfsh_r1 [4] = int_cmd_do_self_rfsh_r1 [4];
//cmd_do_self_rfsh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [5];
//cmd_do_self_rfsh_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [6];
//cmd_do_self_rfsh_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [7];
//cmd_do_self_rfsh_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [8];
end
// there is no need to cache these information
// the fastest a fetch/flush could happen after do_refresh, power_down and self_rfsh
// is one cycle after do command, which means cmd_cache two cycle after do command
// we will only need these information during and one cycle after the do command
cmd_do_refresh_r1 [0] = int_cmd_do_refresh_r1 [0];
cmd_do_refresh_r1 [1] = int_cmd_do_refresh_r1 [1];
cmd_do_refresh_r1 [2] = int_cmd_do_refresh_r1 [2];
cmd_do_refresh_r1 [3] = int_cmd_do_refresh_r1 [3];
cmd_do_refresh_r1 [4] = int_cmd_do_refresh_r1 [4];
cmd_do_refresh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [5];
cmd_do_refresh_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_refresh_r1 [6];
cmd_do_refresh_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [7];
cmd_do_refresh_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_refresh_r1 [8];
cmd_do_power_down_r1 [0] = int_cmd_do_power_down_r1 [0];
cmd_do_power_down_r1 [1] = int_cmd_do_power_down_r1 [1];
cmd_do_power_down_r1 [2] = int_cmd_do_power_down_r1 [2];
cmd_do_power_down_r1 [3] = int_cmd_do_power_down_r1 [3];
cmd_do_power_down_r1 [4] = int_cmd_do_power_down_r1 [4];
cmd_do_power_down_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [5];
cmd_do_power_down_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_power_down_r1 [6];
cmd_do_power_down_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [7];
cmd_do_power_down_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_power_down_r1 [8];
cmd_do_self_rfsh_r1 [0] = int_cmd_do_self_rfsh_r1 [0];
cmd_do_self_rfsh_r1 [1] = int_cmd_do_self_rfsh_r1 [1];
cmd_do_self_rfsh_r1 [2] = int_cmd_do_self_rfsh_r1 [2];
cmd_do_self_rfsh_r1 [3] = int_cmd_do_self_rfsh_r1 [3];
cmd_do_self_rfsh_r1 [4] = int_cmd_do_self_rfsh_r1 [4];
cmd_do_self_rfsh_r1 [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [5];
cmd_do_self_rfsh_r1 [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_self_rfsh_r1 [6];
cmd_do_self_rfsh_r1 [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [7];
cmd_do_self_rfsh_r1 [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_self_rfsh_r1 [8];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
can_precharge_current <= 0;
int_can_precharge <= 0;
end
else if (fetch)
begin
if (flush1)
begin
can_activate_current <= int_bus_can_activate_reg [2];
int_can_activate [0] <= int_bus_can_activate_reg [3];
int_can_activate [1] <= int_bus_can_activate_reg [4];
int_can_activate [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [5];
int_can_activate [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [6];
int_can_activate [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [7];
int_can_activate [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [8];
int_can_activate [6] <= 1'b0;
int_can_activate [7] <= 1'b0;
can_precharge_current <= int_bus_can_precharge_reg [2];
int_can_precharge [0] <= int_bus_can_precharge_reg [3];
int_can_precharge [1] <= int_bus_can_precharge_reg [4];
int_can_precharge [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [5];
int_can_precharge [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [6];
int_can_precharge [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [7];
int_can_precharge [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [8];
int_can_precharge [6] <= 1'b0;
int_can_precharge [7] <= 1'b0;
end
else if (flush2)
begin
can_activate_current <= int_bus_can_activate_reg [3];
int_can_activate [0] <= int_bus_can_activate_reg [4];
int_can_activate [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [5];
int_can_activate [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [6];
int_can_activate [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [7];
int_can_activate [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [8];
int_can_activate [5] <= 1'b0;
int_can_activate [6] <= 1'b0;
int_can_activate [7] <= 1'b0;
can_precharge_current <= int_bus_can_precharge_reg [3];
int_can_precharge [0] <= int_bus_can_precharge_reg [4];
int_can_precharge [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [5];
int_can_precharge [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [6];
int_can_precharge [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [7];
int_can_precharge [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [8];
int_can_precharge [5] <= 1'b0;
int_can_precharge [6] <= 1'b0;
int_can_precharge [7] <= 1'b0;
end
else if (flush3)
begin
can_activate_current <= int_bus_can_activate_reg [4];
int_can_activate [0] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [5];
int_can_activate [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [6];
int_can_activate [2] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [7];
int_can_activate [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [8];
int_can_activate [4] <= 1'b0;
int_can_activate [5] <= 1'b0;
int_can_activate [6] <= 1'b0;
int_can_activate [7] <= 1'b0;
can_precharge_current <= int_bus_can_precharge_reg [4];
int_can_precharge [0] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [5];
int_can_precharge [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [6];
int_can_precharge [2] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [7];
int_can_precharge [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [8];
int_can_precharge [4] <= 1'b0;
int_can_precharge [5] <= 1'b0;
int_can_precharge [6] <= 1'b0;
int_can_precharge [7] <= 1'b0;
end
else
begin
can_activate_current <= int_bus_can_activate_reg [1];
int_can_activate [0] <= int_bus_can_activate_reg [2];
int_can_activate [1] <= int_bus_can_activate_reg [3];
int_can_activate [2] <= int_bus_can_activate_reg [4];
int_can_activate [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [5];
int_can_activate [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [6];
int_can_activate [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [7];
int_can_activate [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [8];
int_can_activate [7] <= 1'b0;
can_precharge_current <= int_bus_can_precharge_reg [1];
int_can_precharge [0] <= int_bus_can_precharge_reg [2];
int_can_precharge [1] <= int_bus_can_precharge_reg [3];
int_can_precharge [2] <= int_bus_can_precharge_reg [4];
int_can_precharge [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [5];
int_can_precharge [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [6];
int_can_precharge [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [7];
int_can_precharge [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [8];
int_can_precharge [7] <= 1'b0;
end
end
else
begin
can_activate_current <= int_bus_can_activate_reg [0];
int_can_activate [0] <= int_bus_can_activate_reg [1];
int_can_activate [1] <= int_bus_can_activate_reg [2];
int_can_activate [2] <= int_bus_can_activate_reg [3];
int_can_activate [3] <= int_bus_can_activate_reg [4];
int_can_activate [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [5];
int_can_activate [5] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_activate_reg [6];
int_can_activate [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [7];
int_can_activate [7] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_activate_reg [8];
can_precharge_current <= int_bus_can_precharge_reg [0];
int_can_precharge [0] <= int_bus_can_precharge_reg [1];
int_can_precharge [1] <= int_bus_can_precharge_reg [2];
int_can_precharge [2] <= int_bus_can_precharge_reg [3];
int_can_precharge [3] <= int_bus_can_precharge_reg [4];
int_can_precharge [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [5];
int_can_precharge [5] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_bus_can_precharge_reg [6];
int_can_precharge [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [7];
int_can_precharge [7] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_bus_can_precharge_reg [8];
end
end
// Determine the flush value
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
flush <= 2'b00;
end
else if (fetch)
begin
if (flush1)
flush <= 2'b01;
else if (flush2)
flush <= 2'b10;
else if (flush3)
flush <= 2'b11;
else
flush <= 2'b00;
end
else
begin
// the following case is to prevent caching the wrong data during flush with no fetch state
// eg: when there is flush1 with no fetch, we should only move the data by one command instead of 2
if (flush1)
flush <= 2'b00;
else if (flush2)
flush <= 2'b01;
else if (flush3)
flush <= 2'b01;
else
flush <= 2'b00;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_fetch_error_addr_r1 <= 1'b0;
fetch_r1 <= 1'b0;
end
else
begin
ecc_fetch_error_addr_r1 <= ecc_fetch_error_addr;
fetch_r1 <= fetch;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cmd_cache <= 1'b0;
end
else
begin
if (fetch || flush1 || flush2 || flush3)
cmd_cache <= 1'b1;
else
cmd_cache <= 1'b0;
end
end
// cmd valid signal to mask off can signals
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_cmd_is_valid_r1 <= 1'b0;
end
else
begin
int_cmd_is_valid_r1 <= int_cmd_is_valid [0];
end
end
always @ (*)
begin
int_cmd_is_valid [CTL_CMD_QUEUE_DEPTH : 1] = cmd_is_valid [CTL_CMD_QUEUE_DEPTH : 1];
if (fetch)
int_cmd_is_valid [0] = 1'b0;
else if (fetch_r1)
int_cmd_is_valid [0] = 1'b1;
else if (ecc_fetch_error_addr)
int_cmd_is_valid [0] = 1'b0;
else if (ecc_fetch_error_addr_r1)
int_cmd_is_valid [0] = 1'b1;
else
int_cmd_is_valid [0] = int_cmd_is_valid_r1;
end
/*------------------------------------------------------------------------------
Can registers
------------------------------------------------------------------------------*/
// We will modify can signal at the input side of the register instead of the output side
// because this will increase fmax performance
// Previously the value in modified in the output of bank specific state machine, it is better to have x * number of lookahead
// compared to y * number of total banks of logics although x is slightly larger than y
generate
genvar y;
genvar y_inner;
for (y = 0;y < CTL_LOOK_AHEAD_DEPTH + 1;y = y + 1)
begin : output_signal_fanout_per_cmd
wire [MEM_IF_BA_WIDTH - 1 : 0] bank_addr = cmd_bank_addr [(y + 1) * MEM_IF_BA_WIDTH - 1 : y * MEM_IF_BA_WIDTH];
wire [MEM_IF_CHIP_BITS - 1 : 0] chip_addr = cmd_chip_addr [(y + 1) * MEM_IF_CHIP_BITS - 1 : y * MEM_IF_CHIP_BITS];
// multicast signals
wire [MEM_IF_CS_WIDTH - 1 : 0] multicast_write_per_chip;
wire [MEM_IF_CS_WIDTH - 1 : 0] multicast_activate_per_chip;
wire [MEM_IF_CS_WIDTH - 1 : 0] multicast_precharge_per_chip;
wire [MEM_IF_CS_WIDTH - 1 : 0] multicast_activate_chip_per_chip;
wire can_multicast_write = &multicast_write_per_chip;
wire can_multicast_activate = &multicast_activate_per_chip;
wire can_multicast_precharge = &multicast_precharge_per_chip;
wire can_multicast_activate_chip = &multicast_activate_chip_per_chip;
for (y_inner = 0;y_inner < MEM_IF_CS_WIDTH;y_inner = y_inner + 1)
begin : multicast_signal_per_chip
wire [MEM_IF_CHIP_BITS - 1 : 0] chip_addr = y_inner;
wire [MEM_IF_BA_WIDTH - 1 : 0] bank_addr = cmd_bank_addr [(y + 1) * MEM_IF_BA_WIDTH - 1 : y * MEM_IF_BA_WIDTH];
assign multicast_write_per_chip [y_inner] = bus_can_write [chip_addr][bank_addr];
assign multicast_activate_per_chip [y_inner] = bus_can_activate [chip_addr][bank_addr];
assign multicast_precharge_per_chip [y_inner] = bus_can_precharge [chip_addr][bank_addr];
assign multicast_activate_chip_per_chip [y_inner] = bus_can_activate_chip [chip_addr][0];
end
always @ (*)
begin
int_bus_can_activate_reg [y] = bus_can_activate_reg [y];
int_bus_can_precharge_reg [y] = bus_can_precharge_reg [y];
int_bus_can_read_reg [y] = bus_can_read_reg [y];
int_bus_can_write_reg [y] = bus_can_write_reg [y];
end
// can read
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
bus_can_read_reg [y] <= 1'b0;
else
begin
if (cmd_do_activate [y] && more_than_4_bank_active) // if we want to optimize activate to read/write, we should use additive latency
bus_can_read_reg [y] <= 1'b0;
else if (cmd_do_activate_r1 [y] && more_than_5_bank_active)
bus_can_read_reg [y] <= 1'b0;
else if (cmd_do_precharge [y] || cmd_do_precharge_r1 [y])
bus_can_read_reg [y] <= 1'b0;
else if (do_read && more_than_4_rd_to_rd) // use do_read because read/write is monitored based on dqs bus usage (will ignore bank address)
bus_can_read_reg [y] <= 1'b0;
else if (!chip_change && do_write && more_than_4_wr_to_rd) // use do_write because read/write is monitored based on dqs bus usage (will ignore bank address)
bus_can_read_reg [y] <= 1'b0;
//else if (chip_change && do_write && less_than_3_wr_to_rd_diff_chips) // we can assert can read when there is a write to read different ranks
// bus_can_read_reg [y] <= 1'b1 & write_to_read_finish_twtr [chip_addr] & read_dqs_ready & int_cmd_is_valid [y];
else if ((cmd_do_activate [y] || cmd_do_activate_r1 [y]) && less_than_2_bank_active) // to increase tRCD efficiency
bus_can_read_reg [y] <= 1'b1 & write_to_read_finish_twtr [chip_addr] & read_dqs_ready & int_cmd_is_valid [y];
else
// write_to_read_finish_twtr signal is used to make sure previous write actually finish
// tWTR before allowing current read to proceed to avoid timing violation
// see DQS bus monitor for more information
bus_can_read_reg [y] <= bus_can_read [chip_addr][bank_addr] & write_to_read_finish_twtr [chip_addr] & read_dqs_ready & int_cmd_is_valid [y];
end
end
// can write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
bus_can_write_reg [y] <= 1'b0;
else
begin
if (cmd_do_activate [y] && more_than_4_bank_active) // if we want to optimize activate to read/write, we should use additive latency
bus_can_write_reg [y] <= 1'b0;
else if (cmd_do_activate_r1 [y] && more_than_5_bank_active)
bus_can_write_reg [y] <= 1'b0;
else if (cmd_do_precharge [y] || cmd_do_precharge_r1 [y])
bus_can_write_reg [y] <= 1'b0;
else if (do_read) // use do_read because read/write is monitored based on dqs bus usage (will ignore bank address)
begin
if (do_burst_chop && more_than_4_rd_to_wr_bc)
bus_can_write_reg [y] <= 1'b0;
else if (!do_burst_chop && more_than_4_rd_to_wr)
bus_can_write_reg [y] <= 1'b0;
end
else if (do_write && more_than_4_wr_to_wr) // use do_write because read/write is monitored based on dqs bus usage (will ignore bank address)
bus_can_write_reg [y] <= 1'b0;
else if ((cmd_do_activate [y] || cmd_do_activate_r1 [y]) && less_than_2_bank_active) // to increase tRCD efficiency
bus_can_write_reg [y] <= 1'b1 & write_dqs_ready & int_cmd_is_valid [y];
else
begin
if (cmd_multicast_req [y]) // when cmd is multicast
bus_can_write_reg [y] <= can_multicast_write & write_dqs_ready & int_cmd_is_valid [y];
else
bus_can_write_reg [y] <= bus_can_write [chip_addr][bank_addr] & write_dqs_ready & int_cmd_is_valid [y];
end
end
end
// can activate
always @ (*)
begin
///if (!ctl_reset_n)
/// bus_can_activate_reg [y] <= 1'b0;
///else
begin
if (cmd_do_activate [y] || cmd_do_activate_r1 [y])
bus_can_activate_reg [y] <= 1'b0;
else if (do_activate && to_chip [chip_addr] && more_than_3_act_to_act_diff_bank) // we do not allow back-to-back activates
bus_can_activate_reg [y] <= 1'b0;
else if (do_activate && cmd_multicast_req [y] && more_than_3_act_to_act_diff_bank) // we do not allow back-to-back activates
// this is to cover multicast cases, when there is a non-multicast activate
// to a multicast activate, we don't need to check for to_chip
bus_can_activate_reg [y] <= 1'b0;
else if (cmd_do_precharge [y] && more_than_3_pch_to_act)
bus_can_activate_reg [y] <= 1'b0;
else if (cmd_do_precharge_r1 [y] && more_than_4_pch_to_act)
bus_can_activate_reg [y] <= 1'b0;
//else if ((do_refresh && to_chip [chip_addr]) || (do_refresh_r1 && to_chip_r1 [chip_addr]))
// bus_can_activate_reg [y] <= 1'b0;
//else if ((do_power_down && to_chip [chip_addr]) || (do_power_down_r1 && to_chip_r1 [chip_addr]))
// bus_can_activate_reg [y] <= 1'b0;
//else if ((do_self_rfsh && to_chip [chip_addr]) || (do_self_rfsh_r1 && to_chip_r1 [chip_addr]))
// bus_can_activate_reg [y] <= 1'b0;
else if (cmd_do_refresh [y] || cmd_do_refresh_r1 [y])
bus_can_activate_reg [y] <= 1'b0;
else if (cmd_do_power_down [y] || cmd_do_power_down_r1 [y])
bus_can_activate_reg [y] <= 1'b0;
else if (cmd_do_self_rfsh [y] || cmd_do_self_rfsh_r1 [y])
bus_can_activate_reg [y] <= 1'b0;
else
begin
if (cmd_multicast_req [y]) // when cmd is multicast
// during multicast command, we shouldn't check for chip specific information
// all information should be "AND-ed" and checked
bus_can_activate_reg [y] <= can_multicast_activate & can_multicast_activate_chip & (&act_diff_bank) & (&act_valid_window) & int_cmd_is_valid [y];
else
bus_can_activate_reg [y] <= bus_can_activate [chip_addr][bank_addr] & bus_can_activate_chip [chip_addr][0] & act_diff_bank [chip_addr] & act_valid_window [chip_addr] & int_cmd_is_valid [y];
end
end
end
// can precharge
always @ (*)
begin
///if (!ctl_reset_n)
/// bus_can_precharge_reg [y] <= 1'b0;
///else
begin
if (cmd_do_activate [y] || cmd_do_activate_r1 [y]) // will impact activate to precharge efficiency, most probably during refreshes and power down
bus_can_precharge_reg [y] <= 1'b0;
else if (cmd_do_precharge [y] || cmd_do_precharge_r1 [y]) // we do not wish controller to do back-to-back precharge, this might impact precharge to precharge all efficiency as well
bus_can_precharge_reg [y] <= 1'b0;
else if (cmd_do_read [y] && more_than_3_rd_to_pch)
bus_can_precharge_reg [y] <= 1'b0;
else if (cmd_do_read_r1 [y] && more_than_4_rd_to_pch)
bus_can_precharge_reg [y] <= 1'b0;
else if (cmd_do_write [y] && more_than_3_wr_to_pch)
bus_can_precharge_reg [y] <= 1'b0;
else if (cmd_do_write_r1 [y] && more_than_4_wr_to_pch)
bus_can_precharge_reg [y] <= 1'b0;
else
begin
if (cmd_multicast_req [y]) // when cmd is multicast
// during multicast request, we will need to make sure if there was a self refresh command
// to another chip, we will need to de-assert can_precharge as well to prevent self refresh exit violation
bus_can_precharge_reg [y] <= can_multicast_precharge & can_multicast_activate_chip & int_cmd_is_valid [y];
else
bus_can_precharge_reg [y] <= bus_can_precharge [chip_addr][bank_addr] & int_cmd_is_valid [y];
end
end
end
end
endgenerate
// register to_chip
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
to_chip_r1 <= 0;
end
else
begin
to_chip_r1 <= to_chip;
end
end
// special can activate signal when add latency is ON
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
can_al_activate_write <= 1'b0;
can_al_activate_read <= 1'b0;
end
else
begin
if (do_read && more_than_4_rd_to_wr)
can_al_activate_write <= 1'b0;
else
can_al_activate_write <= write_dqs_ready;
if (do_write && more_than_4_wr_to_rd)
can_al_activate_read <= 1'b0;
else
can_al_activate_read <= read_dqs_ready & write_to_read_finish_twtr [cmd_chip_addr [MEM_IF_CHIP_BITS - 1 : 0]];
end
end
generate
genvar v;
for (v = 0;v < MEM_IF_CS_WIDTH;v = v + 1)
begin : output_signal_fanout_per_chip
// 2 version for halfrate and fullrate
always @ (*)
begin
non_delay_can_exit_power_saving_mode [v] = int_can_exit_power_saving_mode [v];
delay_can_exit_power_saving_mode [v] = int_can_exit_power_saving_mode_r1 [v];
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_can_exit_power_saving_mode_r1 [v] <= 1'b0;
else
int_can_exit_power_saving_mode_r1 [v] <= int_can_exit_power_saving_mode [v];
end
// can precharge all
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
can_precharge_all [v] <= 1'b0;
end
else
begin
if (do_activate && to_chip [v]) // there is no need to check for timing because tRAS is a large value
can_precharge_all [v] <= 1'b0;
else if (do_activate_r1 && to_chip_r1 [v]) // there is no need to check for timing because tRAS is a large value
can_precharge_all [v] <= 1'b0;
else if ((do_precharge || do_precharge_all) && to_chip [v])
can_precharge_all [v] <= 1'b0;
else if ((do_precharge_r1 || do_precharge_all_r1) && to_chip_r1 [v])
can_precharge_all [v] <= 1'b0;
else if (do_read && to_chip [v] && more_than_3_rd_to_pch)
can_precharge_all [v] <= 1'b0;
else if (do_read_r1 && to_chip_r1 [v] && more_than_3_rd_to_pch)
can_precharge_all [v] <= 1'b0;
else if (do_write && to_chip [v] && more_than_3_wr_to_pch)
can_precharge_all [v] <= 1'b0;
else if (do_write_r1 && to_chip_r1 [v] && more_than_3_wr_to_pch)
can_precharge_all [v] <= 1'b0;
else
can_precharge_all [v] <= &bus_can_precharge [v][2 ** MEM_IF_BA_WIDTH - 1 : 0];
end
end
// can auto refresh
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_can_refresh [v] <= 1'b0;
else
begin
if ((do_precharge || do_precharge_all) && to_chip [v])
begin
if (more_than_3_pch_to_act && MEM_TYPE != "DDR2")
int_can_refresh [v] <= 1'b0;
else if (more_than_2_pch_to_act && MEM_TYPE == "DDR2") // check for more than 2 when mem type is DDR2 because of tRPA = tRP + 1
int_can_refresh [v] <= 1'b0;
else
int_can_refresh [v] <= bus_can_refresh [v][0] & enable_chip_request & enable_chip_request_trc_done [v] & enable_chip_request_ddr2;
end
else if ((do_precharge_r1 || do_precharge_all_r1) && to_chip_r1 [v])
begin
if (more_than_4_pch_to_act && MEM_TYPE != "DDR2")
int_can_refresh [v] <= 1'b0;
else if (more_than_3_pch_to_act && MEM_TYPE == "DDR2") // check for more than 3 when mem type is DDR2 because of tRPA = tRP + 1
int_can_refresh [v] <= 1'b0;
else
int_can_refresh [v] <= bus_can_refresh [v][0] & enable_chip_request & enable_chip_request_trc_done [v] & enable_chip_request_ddr2;
end
else if (do_read || do_read_r1 || do_write || do_write_r1)
int_can_refresh [v] <= 1'b0;
else if (do_power_down) // this will cause some in-efficiency
int_can_refresh [v] <= 1'b0;
else if ((do_refresh && to_chip [v]) || (do_refresh_r1 && to_chip_r1 [v])) // this is required to avoid back to back refreshes to the similar chip
int_can_refresh [v] <= 1'b0;
else
int_can_refresh [v] <= bus_can_refresh [v][0] & enable_chip_request & enable_chip_request_trc_done [v] & enable_chip_request_ddr2;
end
end
// can enter power down
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_can_enter_power_down [v] <= 1'b0;
else
begin
if ((do_precharge || do_precharge_all) && to_chip [v]) // we can go into power down right after a precharge all
int_can_enter_power_down [v] <= 1'b1 & enable_chip_request;
else if (do_read || do_read_r1 || do_write || do_write_r1)
int_can_enter_power_down [v] <= 1'b0;
else
int_can_enter_power_down [v] <= bus_can_power_down [v][0] & enable_chip_request & enable_chip_request_trc_done [v] & enable_chip_request_ddr2;
end
end
// can self refresh
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_can_self_rfsh [v] <= 1'b0;
else
begin
if ((do_precharge || do_precharge_all) && to_chip [v] && more_than_3_pch_to_act)
int_can_self_rfsh [v] <= 1'b0;
else if ((do_precharge_r1 || do_precharge_all_r1) && to_chip_r1 [v] && more_than_4_pch_to_act)
int_can_self_rfsh [v] <= 1'b0;
else if (do_refresh && to_chip [v] && more_than_3_arf_to_valid)
int_can_self_rfsh [v] <= 1'b0;
else if (do_refresh_r1 && to_chip_r1 [v] && more_than_4_arf_to_valid)
int_can_self_rfsh [v] <= 1'b0;
else if (do_power_down && to_chip [v]) // do not allow self refresh entry after and power down, required at least 3 clock cycles
int_can_self_rfsh [v] <= 1'b0;
else if (do_power_down_r1 && to_chip_r1 [v]) // do not allow self refresh entry after and power down, required at least 3 clock cycles
int_can_self_rfsh [v] <= 1'b0;
else if (do_read || do_read_r1 || do_write || do_write_r1)
int_can_self_rfsh [v] <= 1'b0;
else
int_can_self_rfsh [v] <= bus_can_self_rfsh [v][0] & enable_chip_request & enable_chip_request_trc_done [v] & enable_chip_request_ddr2;
end
end
// can exit power saving mode, power down, self refresh needs at least 3 memory clock cycles before exiting
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_exit_power_saving_mode [v] <= 1'b0;
end
else
begin
if (do_power_down && !do_power_down_r1) // positive edge detector
int_can_exit_power_saving_mode [v] <= 1'b1;
else if (!do_power_down && do_power_down_r1) // negative edge detector
int_can_exit_power_saving_mode [v] <= 1'b0;
else if (do_self_rfsh && !do_self_rfsh_r1) // positive edge detector
int_can_exit_power_saving_mode [v] <= 1'b1;
else if (!do_self_rfsh && do_self_rfsh_r1) // positive edge detector
int_can_exit_power_saving_mode [v] <= 1'b0;
end
end
// can lmr
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_can_lmr [v] <= 1'b0;
else
begin
if ((do_precharge || do_precharge_all) && to_chip [v] && more_than_3_pch_to_act)
int_can_lmr [v] <= 1'b0;
else if (do_read || do_write)
int_can_lmr [v] <= 1'b0;
else
int_can_lmr [v] <= bus_can_lmr [v][0] & enable_chip_request;
end
end
// zq calibration request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_zq_cal_req [v] <= 1'b0;
end
else
begin
int_zq_cal_req [v] <= bus_zq_cal_req [v][0];
end
end
end
endgenerate
generate
if (MEM_TYPE == "DDR2")
begin
reg [PCH_TO_ACT_WIDTH - 1 : 0] pch_all_cnt;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pch_all_cnt <= 0;
end
else
begin
if (do_precharge_all)
pch_all_cnt <= 4;
else if (pch_all_cnt != {PCH_TO_ACT_WIDTH{1'b1}})
pch_all_cnt <= pch_all_cnt + 1'b1;
end
end
// specific for DDR2 only, tRPA precharge all timing value which is tRP + 1
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
enable_chip_request_ddr2 <= 1'b0;
end
else
begin
if (do_precharge_all && more_than_4_pch_all_to_act)
enable_chip_request_ddr2 <= 1'b0;
else if (pch_all_cnt >= pch_all_to_act)
enable_chip_request_ddr2 <= 1'b1;
else
enable_chip_request_ddr2 <= 1'b0;
end
end
end
else
begin
// set to always high when mem type is not DDR2
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
enable_chip_request_ddr2 <= 1'b1;
else
enable_chip_request_ddr2 <= 1'b1;
end
end
endgenerate
always @ (*)
begin
can_refresh = int_can_refresh;
can_enter_power_down = int_can_enter_power_down;
can_self_rfsh = int_can_self_rfsh;
end
// in halfrate, we only delay exit power down by 2 cycle because it is equal to 4 memory clocks
generate
if (DWIDTH_RATIO == 2) // fullrate
begin
always @ (*)
begin
can_exit_power_saving_mode = delay_can_exit_power_saving_mode;
end
end
else if (DWIDTH_RATIO == 4) // halfrate
begin
always @ (*)
begin
can_exit_power_saving_mode = non_delay_can_exit_power_saving_mode;
end
end
endgenerate
// keep track of read/write
// we will need to keep track of auto precharge as well to avoid violating tRAS
// this will cause in-efficiency in every power down entry when there was a read/write
// with auto_precharge command
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_write <= 1'b0;
doing_read <= 1'b0;
end
else
begin
if (do_write)
begin
doing_write <= 1'b1;
doing_read <= 1'b0;
end
else if (do_read)
begin
doing_write <= 1'b0;
doing_read <= 1'b1;
end
end
end
// counter used to track clock cycle count after read/write request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
chip_request_cnt <= 0;
end
else
begin
if (do_read || do_write)
chip_request_cnt <= 4;
else if (chip_request_cnt != {FINISH_WRITE_WIDTH{1'b1}})
chip_request_cnt <= chip_request_cnt + 1'b1;
end
end
// this signal will de-assert can self refresh/refresh/power down and lmr signal so that it will wait will read/write finish
// this should be per chip basis but currently we are only monitoring read/write on global basis
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
enable_chip_request <= 1'b0;
end
else
begin
if (do_read || do_write) // de-assert right after read/write
enable_chip_request <= 1'b0;
else if (doing_write && chip_request_cnt > finish_write)
enable_chip_request <= 1'b1;
else if (doing_read && chip_request_cnt > finish_read)
enable_chip_request <= 1'b1;
else if (chip_request_cnt > finish_write) // default state and finish_write should be larger than finish_read
enable_chip_request <= 1'b1;
else
enable_chip_request <= 1'b0;
end
end
// require tRC counter to monito each activate to make sure
// internal precharge during auto precharge read/write are finished
// before enabling can refresh, power down or self refresh
// see logic below for more information (enable_chip_request_auto_pch_done)
generate
genvar d;
for (d = 0;d < MEM_IF_CS_WIDTH;d = d + 1)
begin : trc_cnt_per_chip
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
trc_cnt [d] <= 0;
end
else
begin
if (do_activate && to_chip [d])
trc_cnt [d] <= 5;
else if (trc_cnt [d] != {ACT_TO_ACT_WIDTH{1'b1}})
trc_cnt [d] <= trc_cnt [d] + 1'b1;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_auto_pch [d] <= 1'b0;
end
else
begin
if (to_chip [d])
begin
if (do_write)
begin
if (do_auto_precharge)
doing_auto_pch [d] <= 1'b1;
else
doing_auto_pch [d] <= 1'b0;
end
else if (do_read)
begin
if (do_auto_precharge)
doing_auto_pch [d] <= 1'b1;
else
doing_auto_pch [d] <= 1'b0;
end
end
end
end
// this signal is required to monitor read/write with auto precharge to power down, refresh entry
// we will need to wait till internal precharge is done before asserting can_power_down
// this signal must be used with enable_chip_request, because this signal is a simplified version
// of enable_chip_request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
enable_chip_request_trc_done [d] <= 1'b0;
end
else
begin
if (doing_auto_pch [d]) // we will only de-assert this signal when there is auto precharge
begin
if (trc_cnt [d] > act_to_act) // must be larger than tRC
enable_chip_request_trc_done [d] <= 1'b1;
else
enable_chip_request_trc_done [d] <= 1'b0;
end
else
enable_chip_request_trc_done [d] <= 1'b1;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Self Refresh Request
------------------------------------------------------------------------------*/
// zq calibration request
generate
if (MEM_TYPE == "DDR3")
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
zq_cal_req <= 1'b0;
end
else
begin
zq_cal_req <= |int_zq_cal_req;
end
end
end
else // set to zero when memory type is not DDR3
begin
wire zero = 1'b0;
always @ (*)
begin
zq_cal_req <= zero;
end
end
endgenerate
/*------------------------------------------------------------------------------
Auto Refresh Request
------------------------------------------------------------------------------*/
generate
genvar c;
if (!CTL_USR_REFRESH)
begin
for (c = 0; c < MEM_IF_CS_WIDTH; c = c + 1)
begin : auto_refresh_logic_per_chip
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
auto_refresh_cnt[c] <= 0;
end
else
begin
if (do_refresh & to_chip[c])
auto_refresh_cnt[c] <= 3;
else if (auto_refresh_cnt[c] != {ARF_COUNTER_WIDTH{1'b1}})
auto_refresh_cnt[c] <= auto_refresh_cnt[c] + 1'b1;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
auto_refresh_chip[c] <= 1'b0;
end
else
begin
if (do_refresh & to_chip[c])
auto_refresh_chip[c] <= 1'b0;
else if (auto_refresh_cnt[c] >= arf_period)
auto_refresh_chip[c] <= 1'b1;
else
auto_refresh_chip[c] <= 1'b0;
end
end
end
assign auto_refresh_req = |auto_refresh_chip;
end
else
begin
assign auto_refresh_req = 0;
end
endgenerate
/*------------------------------------------------------------------------------
Power Down Request
------------------------------------------------------------------------------*/
// only start power down request after init done
always @ (*)
begin
if (local_init_done)
no_command = cmd_fifo_empty;
else
no_command = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
no_command_r1 <= 1'b0;
end
else
begin
no_command_r1 <= no_command;
end
end
// do_power_down register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_power_down_r1 <= 0;
end
else
begin
do_power_down_r1 <= do_power_down;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_cnt <= 0;
end
else
begin
if (!no_command && no_command_r1)
power_down_cnt <= 3;
else if (no_command && power_down_cnt != {PDN_COUNTER_WIDTH{1'b1}})
power_down_cnt <= power_down_cnt + 1'b1;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
power_down_req <= 1'b0;
end
else
begin
if (pdn_period == 0) // when auto power down cycles is set to '0', auto power down mode will be disabled
power_down_req <= 1'b0;
else
begin
if (!cmd_fifo_empty) // we need to make sure power down request to go low as fast as possible to avoid unnecessary power down
power_down_req <= 1'b0;
else if (power_down_cnt >= pdn_period)
power_down_req <= 1'b1;
else
power_down_req <= 1'b0;
end
end
end
/*------------------------------------------------------------------------------
ACT Command Monitor
------------------------------------------------------------------------------*/
generate
genvar t;
for (t = 0;t < MEM_IF_CS_WIDTH;t = t + 1)
begin : act_command_monitor
reg [2 : 0] act_command_cnt;
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_cnt;
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_cnt_valid;
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] diff_count_r1;
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] diff_count_r2;
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] diff_count_r3;
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] diff_sum_2;
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] diff_sum_3;
reg do_act_reg;
reg int_act_valid_window;
if (MEM_TYPE == "DDR") // there is no tFAW in DDR
begin
wire one = 1'b1;
always @ (*)
begin
act_valid_window [t] = one;
end
end
else
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_cnt_valid <= 0;
end
else
begin
if (do_activate && to_chip [t])
act_cnt_valid <= 1;
else if (act_cnt_valid != {ACTIVATE_COUNTER_WIDTH{1'b1}})
act_cnt_valid <= act_cnt_valid + 1'b1;
end
end
// tFAW, four ACT valid window
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_command_cnt <= 0;
end
else
begin
if (act_cnt_valid >= four_act_to_act)
begin
if (do_activate)
act_command_cnt <= 1;
else
act_command_cnt <= 0;
end
else if (do_activate && act_command_cnt != 3'b100)
act_command_cnt <= act_command_cnt + 1'b1;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
diff_count_r1 <= 0;
diff_count_r2 <= 0;
diff_count_r3 <= 0;
diff_sum_2 <= 0;
diff_sum_3 <= 0;
end
else
begin
diff_sum_2 <= diff_count_r1 + diff_count_r2 + act_cnt_valid;
diff_sum_3 <= diff_count_r1 + diff_count_r2 + diff_count_r3 + act_cnt_valid;
if (do_activate && to_chip [t])
begin
diff_count_r1 <= act_cnt_valid;
diff_count_r2 <= diff_count_r1;
diff_count_r3 <= diff_count_r2;
end
end
end
// monitor activate for tFAW
always @ (*)
begin
if (do_activate && to_chip [t] && (act_command_cnt == 3 || act_command_cnt == 4)) // during 3th or 4th activate
if (diff_sum_2 <= four_act_to_act)
act_valid_window [t] = 1'b0;
else
act_valid_window [t] = int_act_valid_window;
else
act_valid_window [t] = int_act_valid_window;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_act_valid_window <= 1'b1;
do_act_reg <= 1'b0;
end
else
begin
if (((do_activate && to_chip [t]) || do_act_reg) && (act_command_cnt == 3 || act_command_cnt == 4)) // during 4th activate and one clock cycle later
begin
if (do_act_reg)
do_act_reg <= 1'b0;
else
do_act_reg <= 1'b1;
if (diff_sum_2 < four_act_to_act)
int_act_valid_window <= 1'b0;
else
int_act_valid_window <= 1'b1;
end
else if (act_command_cnt == 4)
begin
if (diff_sum_3 < four_act_to_act)
int_act_valid_window <= 1'b0;
else
int_act_valid_window <= 1'b1;
end
else
int_act_valid_window <= 1'b1;
end
end
end
// ACT counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_cnt <= 0;
end
else
begin
if (do_activate && to_chip [t])
act_cnt <= 4;
else if (act_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
act_cnt <= act_cnt + 1'b1;
end
end
// tRRD, ACT to ACT diff banks
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_diff_bank [t] <= 1'b0;
end
else
begin
if (do_activate && to_chip [t])
begin
if (more_than_4_act_to_act_diff_bank)
act_diff_bank [t] <= 1'b0;
else
act_diff_bank [t] <= 1'b1;
end
else if (act_cnt >= act_to_act_diff_bank)
act_diff_bank [t] <= 1'b1;
else
act_diff_bank [t] <= 1'b0;
end
end
end
endgenerate
/*------------------------------------------------------------------------------
Read / Write Command Monitor
------------------------------------------------------------------------------*/
// store current chip address into previous chip address for comparison later
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
prev_chip_addr <= 0;
end
else
begin
if (fetch)
prev_chip_addr <= current_chip_addr;
end
end
// store current multicast request for comparison later
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
prev_multicast_req <= 1'b0;
end
else
begin
if (fetch)
prev_multicast_req <= current_multicast_req;
end
end
// compare current chip addr wirt prev chip addr
// during the following case, do not assert chip change:
// - wr with multicast to read with multicast
// - wr with multicast to read with no multicast
// - wr with no multicast to read with multicast
always @ (*)
begin
if (!fetch && prev_chip_addr != current_chip_addr && !(prev_multicast_req || current_multicast_req))
chip_change = 1'b1;
else if (fetch && current_chip_addr != cmd0_chip_addr && !(current_multicast_req || cmd0_multicast_req))
chip_change = 1'b1;
else
chip_change = 1'b0;
end
// general counter for dqs bus monitor
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cnt <= 0;
end
else
begin
if (do_write || do_read)
cnt <= 5;
else if (cnt != {RD_WR_COUNTER_WIDTH{1'b1}})
cnt <= cnt + 1'b1;
end
end
// write to read, tWTR monitor
generate
genvar m;
for (m = 0;m < MEM_IF_CS_WIDTH;m = m + 1)
begin: tWTR_counter_per_chip
// tWTR counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
twtr_cnt [m] <= 0;
end
else
begin
if (do_write && to_chip [m])
twtr_cnt [m] <= 5;
else if (twtr_cnt [m] != {WR_TO_RD_WIDTH{1'b1}})
twtr_cnt [m] <= twtr_cnt [m] + 1'b1;
end
end
// this signal will indicate previous write to a particular chip has met tWTR
// this will be used in can_read logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
write_to_read_finish_twtr [m] <= 1'b0;
end
else
begin
if (twtr_cnt [m] >= wr_to_rd)
write_to_read_finish_twtr [m] <= 1'b1;
else
write_to_read_finish_twtr [m] <= 1'b0;
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_chop <= 1'b0;
end
else
begin
if (do_read || do_write)
begin
if (do_burst_chop)
doing_burst_chop <= 1'b1;
else
doing_burst_chop <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
state <= IDLE;
read_dqs_ready <= 1'b0;
write_dqs_ready <= 1'b0;
end
else
begin
case (state)
IDLE :
begin
if (do_write)
begin
state <= WR;
if (less_than_4_wr_to_rd)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
if (less_than_4_wr_to_wr)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
else if (do_read)
begin
state <= RD;
if (less_than_4_rd_to_rd)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
if (!do_burst_chop)
begin
if (less_than_4_rd_to_wr)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
else // BC4 OTF
begin
if (less_than_4_rd_to_wr_bc)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
end
else
begin
state <= IDLE;
read_dqs_ready <= 1'b1;
write_dqs_ready <= 1'b1;
end
end
WR :
begin
if (do_write)
begin
state <= WR;
if (chip_change && less_than_4_wr_to_rd_diff_chips)
read_dqs_ready <= 1'b1;
else if (less_than_4_wr_to_rd)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
if (less_than_4_wr_to_wr)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
else if (do_read)
begin
state <= RD;
if (less_than_4_rd_to_rd)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
if (!do_burst_chop)
begin
if (less_than_4_rd_to_wr)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
else // BC4 OTF
begin
if (less_than_4_rd_to_wr_bc)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
end
else
begin
// if there will be a wr to rd to different chipselects
// we will maximize the efficiency by not checking for twtr
if (chip_change)
begin
if (cnt >= wr_to_rd_diff_chips)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
end
else
begin
if (cnt >= wr_to_rd)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
end
if (cnt >= wr_to_wr)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
end
RD :
begin
if (do_write)
begin
state <= WR;
if (chip_change && less_than_4_wr_to_rd_diff_chips)
read_dqs_ready <= 1'b1;
else if (less_than_4_wr_to_rd)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
if (less_than_4_wr_to_wr)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
else if (do_read)
begin
state <= RD;
if (less_than_4_rd_to_rd)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
if (!do_burst_chop)
begin
if (less_than_4_rd_to_wr)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
else // BC4 OTF
begin
if (less_than_4_rd_to_wr_bc)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
end
else
begin
if (cnt >= rd_to_rd)
read_dqs_ready <= 1'b1;
else
read_dqs_ready <= 1'b0;
if (!doing_burst_chop)
begin
if (cnt >= rd_to_wr)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
else
begin
if (cnt >= rd_to_wr_bc)
write_dqs_ready <= 1'b1;
else
write_dqs_ready <= 1'b0;
end
end
end
default :
state <= IDLE;
endcase
end
end
/*------------------------------------------------------------------------------
Banks Specific Process
------------------------------------------------------------------------------*/
generate
genvar x_outer;
genvar x_inner;
for (x_outer = 0;x_outer < MEM_IF_CS_WIDTH; x_outer = x_outer + 1)
begin : bank_specific_state_machine_per_chip
for (x_inner = 0;x_inner < 2 ** MEM_IF_BA_WIDTH; x_inner = x_inner + 1)
begin : bank_specific_state_machine_per_bank
alt_ddrx_timers_fsm #
(
.BANK_ACTIVATE_WIDTH (BANK_ACTIVATE_WIDTH ),
.ACT_TO_PCH_WIDTH (ACT_TO_PCH_WIDTH ),
.ACT_TO_ACT_WIDTH (ACT_TO_ACT_WIDTH ),
.RD_TO_RD_WIDTH (RD_TO_RD_WIDTH ),
.RD_TO_WR_WIDTH (RD_TO_WR_WIDTH ),
.RD_TO_PCH_WIDTH (RD_TO_PCH_WIDTH ),
.WR_TO_WR_WIDTH (WR_TO_WR_WIDTH ),
.WR_TO_RD_WIDTH (WR_TO_RD_WIDTH ),
.WR_TO_PCH_WIDTH (WR_TO_PCH_WIDTH ),
.PCH_TO_ACT_WIDTH (PCH_TO_ACT_WIDTH ),
.RD_AP_TO_ACT_WIDTH (RD_AP_TO_ACT_WIDTH ),
.WR_AP_TO_ACT_WIDTH (WR_AP_TO_ACT_WIDTH ),
.ARF_TO_VALID_WIDTH (ARF_TO_VALID_WIDTH ),
.PDN_TO_VALID_WIDTH (PDN_TO_VALID_WIDTH ),
.SRF_TO_VALID_WIDTH (SRF_TO_VALID_WIDTH ),
.LMR_TO_LMR_WIDTH (LMR_TO_LMR_WIDTH ),
.LMR_TO_VALID_WIDTH (LMR_TO_VALID_WIDTH )
)
fsm_inst
(
// inputs
.ctl_clk (ctl_clk ),
.ctl_reset_n (ctl_reset_n ),
.do_write (do_write_r1 ),
.do_read (do_read_r1 ),
.do_activate (do_activate_r1 ),
.do_precharge (do_precharge_r1 ),
.do_auto_precharge (do_auto_precharge_r1 ),
.do_precharge_all (bus_do_precharge_all [x_outer][x_inner]),
.do_refresh (bus_do_refresh [x_outer][x_inner]),
.do_power_down (bus_do_power_down [x_outer][x_inner]),
.do_self_rfsh (bus_do_self_rfsh [x_outer][x_inner]),
.do_lmr (bus_do_lmr [x_outer][x_inner]),
.do_enable (do_enable [x_outer][x_inner]),
// timing parameters
.bank_active (bank_active ),
.act_to_pch (act_to_pch ),
.act_to_act (act_to_act ),
.rd_to_rd (rd_to_rd ),
.rd_to_wr (rd_to_wr ),
.rd_to_pch (rd_to_pch ),
.wr_to_wr (wr_to_wr ),
.wr_to_rd (wr_to_rd ),
.wr_to_pch (wr_to_pch ),
.wr_to_rd_to_pch_all (wr_to_rd_to_pch_all ),
.pch_to_act (pch_to_act ),
.rd_ap_to_act (rd_ap_to_act ),
.wr_ap_to_act (wr_ap_to_act ),
.arf_to_valid (arf_to_valid ),
.pdn_to_valid (pdn_to_valid ),
.srf_to_valid (srf_to_valid ),
.srf_to_zq (srf_to_zq ),
.lmr_to_lmr (lmr_to_lmr ),
.lmr_to_valid (lmr_to_valid ),
.less_than_2_bank_active (less_than_2_bank_active ),
.less_than_2_act_to_pch (less_than_2_act_to_pch ),
.less_than_2_act_to_act (less_than_2_act_to_act ),
.less_than_2_rd_to_rd (less_than_2_rd_to_rd ),
.less_than_2_rd_to_wr (less_than_2_rd_to_wr ),
.less_than_2_rd_to_pch (less_than_2_rd_to_pch ),
.less_than_2_wr_to_wr (less_than_2_wr_to_wr ),
.less_than_2_wr_to_rd (less_than_2_wr_to_rd ),
.less_than_2_wr_to_pch (less_than_2_wr_to_pch ),
.less_than_2_pch_to_act (less_than_2_pch_to_act ),
.less_than_2_rd_ap_to_act (less_than_2_rd_ap_to_act ),
.less_than_2_wr_ap_to_act (less_than_2_wr_ap_to_act ),
.less_than_2_arf_to_valid (less_than_2_arf_to_valid ),
.less_than_2_pdn_to_valid (less_than_2_pdn_to_valid ),
.less_than_2_srf_to_valid (less_than_2_srf_to_valid ),
.less_than_2_lmr_to_lmr (less_than_2_lmr_to_lmr ),
.less_than_2_lmr_to_valid (less_than_2_lmr_to_valid ),
.less_than_3_bank_active (less_than_3_bank_active ),
.less_than_3_act_to_pch (less_than_3_act_to_pch ),
.less_than_3_act_to_act (less_than_3_act_to_act ),
.less_than_3_rd_to_rd (less_than_3_rd_to_rd ),
.less_than_3_rd_to_wr (less_than_3_rd_to_wr ),
.less_than_3_rd_to_pch (less_than_3_rd_to_pch ),
.less_than_3_wr_to_wr (less_than_3_wr_to_wr ),
.less_than_3_wr_to_rd (less_than_3_wr_to_rd ),
.less_than_3_wr_to_pch (less_than_3_wr_to_pch ),
.less_than_3_wr_to_rd_to_pch_all (less_than_3_wr_to_rd_to_pch_all ),
.less_than_3_pch_to_act (less_than_3_pch_to_act ),
.less_than_3_rd_ap_to_act (less_than_3_rd_ap_to_act ),
.less_than_3_wr_ap_to_act (less_than_3_wr_ap_to_act ),
.less_than_3_arf_to_valid (less_than_3_arf_to_valid ),
.less_than_3_pdn_to_valid (less_than_3_pdn_to_valid ),
.less_than_3_srf_to_valid (less_than_3_srf_to_valid ),
.less_than_3_lmr_to_lmr (less_than_3_lmr_to_lmr ),
.less_than_3_lmr_to_valid (less_than_3_lmr_to_valid ),
.less_than_4_bank_active (less_than_4_bank_active ),
.less_than_4_act_to_pch (less_than_4_act_to_pch ),
.less_than_4_act_to_act (less_than_4_act_to_act ),
.less_than_4_rd_to_rd (less_than_4_rd_to_rd ),
.less_than_4_rd_to_wr (less_than_4_rd_to_wr ),
.less_than_4_rd_to_pch (less_than_4_rd_to_pch ),
.less_than_4_wr_to_wr (less_than_4_wr_to_wr ),
.less_than_4_wr_to_rd (less_than_4_wr_to_rd ),
.less_than_4_wr_to_pch (less_than_4_wr_to_pch ),
.less_than_4_wr_to_rd_to_pch_all (less_than_4_wr_to_rd_to_pch_all ),
.less_than_4_pch_to_act (less_than_4_pch_to_act ),
.less_than_4_rd_ap_to_act (less_than_4_rd_ap_to_act ),
.less_than_4_wr_ap_to_act (less_than_4_wr_ap_to_act ),
.less_than_4_arf_to_valid (less_than_4_arf_to_valid ),
.less_than_4_pdn_to_valid (less_than_4_pdn_to_valid ),
.less_than_4_srf_to_valid (less_than_4_srf_to_valid ),
.less_than_4_lmr_to_lmr (less_than_4_lmr_to_lmr ),
.less_than_4_lmr_to_valid (less_than_4_lmr_to_valid ),
.more_than_2_bank_active (more_than_2_bank_active ),
.more_than_2_act_to_pch (more_than_2_act_to_pch ),
.more_than_2_act_to_act (more_than_2_act_to_act ),
.more_than_2_rd_to_rd (more_than_2_rd_to_rd ),
.more_than_2_rd_to_wr (more_than_2_rd_to_wr ),
.more_than_2_rd_to_pch (more_than_2_rd_to_pch ),
.more_than_2_wr_to_wr (more_than_2_wr_to_wr ),
.more_than_2_wr_to_rd (more_than_2_wr_to_rd ),
.more_than_2_wr_to_pch (more_than_2_wr_to_pch ),
.more_than_2_pch_to_act (more_than_2_pch_to_act ),
.more_than_2_rd_ap_to_act (more_than_2_rd_ap_to_act ),
.more_than_2_wr_ap_to_act (more_than_2_wr_ap_to_act ),
.more_than_2_arf_to_valid (more_than_2_arf_to_valid ),
.more_than_2_pdn_to_valid (more_than_2_pdn_to_valid ),
.more_than_2_srf_to_valid (more_than_2_srf_to_valid ),
.more_than_2_lmr_to_lmr (more_than_2_lmr_to_lmr ),
.more_than_2_lmr_to_valid (more_than_2_lmr_to_valid ),
.more_than_3_bank_active (more_than_3_bank_active ),
.more_than_3_act_to_pch (more_than_3_act_to_pch ),
.more_than_3_act_to_act (more_than_3_act_to_act ),
.more_than_3_rd_to_rd (more_than_3_rd_to_rd ),
.more_than_3_rd_to_wr (more_than_3_rd_to_wr ),
.more_than_3_rd_to_pch (more_than_3_rd_to_pch ),
.more_than_3_wr_to_wr (more_than_3_wr_to_wr ),
.more_than_3_wr_to_rd (more_than_3_wr_to_rd ),
.more_than_3_wr_to_pch (more_than_3_wr_to_pch ),
.more_than_3_pch_to_act (more_than_3_pch_to_act ),
.more_than_3_rd_ap_to_act (more_than_3_rd_ap_to_act ),
.more_than_3_wr_ap_to_act (more_than_3_wr_ap_to_act ),
.more_than_3_arf_to_valid (more_than_3_arf_to_valid ),
.more_than_3_pdn_to_valid (more_than_3_pdn_to_valid ),
.more_than_3_srf_to_valid (more_than_3_srf_to_valid ),
.more_than_3_lmr_to_lmr (more_than_3_lmr_to_lmr ),
.more_than_3_lmr_to_valid (more_than_3_lmr_to_valid ),
.more_than_5_pch_to_act (more_than_5_pch_to_act ),
.compare_wr_to_rd_to_pch_all (compare_wr_to_rd_to_pch_all ),
// outputs
.int_can_activate (bus_can_activate [x_outer][x_inner]),
.int_can_activate_chip (bus_can_activate_chip [x_outer][x_inner]),
.int_can_precharge (bus_can_precharge [x_outer][x_inner]),
.int_can_read (bus_can_read [x_outer][x_inner]),
.int_can_write (bus_can_write [x_outer][x_inner]),
.int_can_refresh (bus_can_refresh [x_outer][x_inner]),
.int_can_power_down (bus_can_power_down [x_outer][x_inner]),
.int_can_self_rfsh (bus_can_self_rfsh [x_outer][x_inner]),
.int_can_lmr (bus_can_lmr [x_outer][x_inner]),
.int_zq_cal_req (bus_zq_cal_req [x_outer][x_inner])
);
end
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_16k.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_16k.v //
// Description : Implements 16 KB Dual Ported Memory //
// - Output Regs are always enabled //
// - if NO_DECODE_LOGIC = TRUE -> 8xRAMB18E1 in TDP mode //
// - if INTERFACE_SPEED = 500 MHz -> 8xRAMB18E1 in TDP mode //
// - if INTERFACE_SPEED = 250 MHz -> 4xRAMB36E1 in SDP mode //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_16k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_16k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
)
(
input clk_i, // user clock
input reset_i, // bram reset
input [9:0] waddr0_i, // write address
input [9:0] waddr1_i, // write address
input [9:0] waddr2_i, // write address
input [9:0] waddr3_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input [7:0] wen_i, // write enable
input [9:0] raddr0_i, // write address
input [9:0] raddr1_i, // write address
input [9:0] raddr2_i, // write address
input [9:0] raddr3_i, // write address
output [127:0] rdata_o, // read data
output [15:0] rdop_o, // read parity
input [7:0] ren_i // read enable
);
// Local Params
localparam TCQ = 1;
genvar i;
wire [79:0] waddr;
wire [79:0] raddr;
wire [7:0] wen;
wire [7:0] ren;
wire [255:0] rdata_w;
wire [31:0] rdop_w;
wire [255:0] wdata_w;
wire [31:0] wdip_w;
reg raddr0_q = 1'b0;
reg raddr0_qq = 1'b0;
assign wen = {wen_i[7], wen_i[6], wen_i[5], wen_i[4], wen_i[3], wen_i[2], wen_i[1], wen_i[0]};
assign ren = {ren_i[7], ren_i[6], ren_i[5], ren_i[4], ren_i[3], ren_i[2], ren_i[1], ren_i[0]};
generate
if ((INTERFACE_SPEED == "500 MHZ") || (NO_DECODE_LOGIC == "TRUE")) begin : SPEED_500MHz_OR_NO_DECODE_LOGIC
assign waddr = {waddr3_i, waddr3_i, waddr2_i, waddr2_i, waddr1_i, waddr1_i, waddr0_i, waddr0_i};
assign raddr = {raddr3_i, raddr3_i, raddr2_i, raddr2_i, raddr1_i, raddr1_i, raddr0_i, raddr0_i};
for (i = 0; i < 8; i = i + 1) begin : RAMB18E1
RAMB18E1 #(
.SIM_DEVICE ("7SERIES"),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.SRVAL_A ( 18'h00000 ),
.INIT_FILE ( "NONE" ),
.RAM_MODE ( "TDP" ),
.READ_WIDTH_A ( 18 ),
.READ_WIDTH_B ( 18 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.INIT_A ( 18'h00000 ),
.INIT_B ( 18'h00000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 18 ),
.WRITE_WIDTH_B ( 18 ),
.SRVAL_B ( 18'h00000 ))
u_fifo (
.CLKARDCLK(clk_i),
.CLKBWRCLK(clk_i),
.ENARDEN(1'b1),
.ENBWREN(ren[i]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1 ),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.ADDRARDADDR({waddr[(10*i)+9:(10*i)+0], 4'b0}),
.ADDRBWRADDR({raddr[(10*i)+9:(10*i)+0], 4'b0}),
.DIADI(wdata_i[(16*i)+15:(16*i)+0]),
.DIPADIP(wdip_i[(2*i)+1:(2*i)+0]),
.DIBDI({16'b0}),
.DIPBDIP(2'b0),
.DOADO(),
.DOBDO(rdata_o[(16*i)+15:(16*i)+0]),
.DOPADOP(),
.DOPBDOP(rdop_o[(2*i)+1:(2*i)+0]),
.WEA({wen[i], wen[i]}),
.WEBWE({1'b0, 1'b0, 1'b0, 1'b0})
);
end
end else begin : SPEED_250MHz
always @(posedge clk_i) begin
if (reset_i) begin
raddr0_q <= #(TCQ) 1'b0;
raddr0_qq <= #(TCQ) 1'b0;
end else begin
raddr0_q <= #(TCQ) raddr0_i[9];
raddr0_qq <= #(TCQ) raddr0_q;
end
end
assign rdata_o = raddr0_qq ? rdata_w[255:128] : rdata_w[127:0];
assign rdop_o = raddr0_qq ? rdop_w[31:16] : rdop_w[15:0];
assign wdata_w = {wdata_i, wdata_i};
assign wdip_w = {wdip_i, wdip_i};
assign waddr = {44'b0, waddr0_i[8:0], waddr1_i[8:0], waddr2_i[8:0], waddr3_i[8:0]};
assign raddr = {44'b0, raddr0_i[8:0], raddr1_i[8:0], raddr2_i[8:0], raddr3_i[8:0]};
for (i = 0; i < 4; i = i + 1) begin : RAMB36E1
RAMB36E1 #(
.SIM_DEVICE ("7SERIES"),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.INIT_FILE ( "NONE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.RAM_MODE ( "SDP" ),
.RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ),
.READ_WIDTH_A ( 72 ),
.READ_WIDTH_B ( 0 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 0 ),
.WRITE_WIDTH_B ( 72 )
)
u_fifo (
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA( ),
.CASCADEOUTB( ),
.CLKARDCLK(clk_i),
.CLKBWRCLK(clk_i),
.DBITERR( ),
.ENARDEN(((i > 1) ? (raddr0_i[9] & ren[2*i]) : (~raddr0_i[9] & ren[2*i]))),
.ENBWREN(1'b1 ),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.REGCEAREGCE(1'b1 ),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR( ),
.ADDRARDADDR({1'b1 , raddr[(9*i)+8:(9*i)+0], 6'b0}),
.ADDRBWRADDR({1'b1 , waddr[(9*i)+8:(9*i)+0], 6'b0}),
.DIADI(wdata_w[(2*32*i)+31:(2*32*i)+0]),
.DIBDI(wdata_w[(2*32*i)+63:(2*32*i)+32]),
.DIPADIP(wdip_w[(2*4*i)+3:(2*4*i)+0]),
.DIPBDIP(wdip_w[(2*4*i)+7:(2*4*i)+4]),
.DOADO(rdata_w[(2*32*i)+31:(2*32*i)+0]),
.DOBDO(rdata_w[(2*32*i)+63:(2*32*i)+32]),
.DOPADOP(rdop_w[(2*4*i)+3:(2*4*i)+0]),
.DOPBDOP(rdop_w[(2*4*i)+7:(2*4*i)+4]),
.ECCPARITY(),
.RDADDRECC(),
.WEA(4'b0),
.WEBWE({8{((i > 1) ? (waddr0_i[9] & wen[2*i]) : (~waddr0_i[9] & wen[2*i]))}})
);
end
end
endgenerate
endmodule // pcie_bram_7vx_16k
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: tlu_incr64.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: 64b incr macro
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module tlu_incr64 ( in, out );
input [63:0] in;
output [63:0] out; // result of increment
assign out = in + 64'h01;
endmodule // tlu_incr64
|
/**
* @module regfile
* @author sabertazimi
* @email [email protected]
* @brief register files for MIPS CPU, contains 32 D flip-flop registers
* @param DATA_WIDTH data width
* @input clk clock signal
* @input we write enable signal
* @input raddrA read address (No.register) for A out port
* @input raddrB read address (No.register) for B out port
* @input waddr write address (No.register) for wdata (in port)
* @input wdata data to write into regfile
* @output regA A port output
* @output regB B port output
*/
module regfile
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input we,
input [4:0] raddrA,
input [4:0] raddrB,
input [4:0] waddr,
input [DATA_WIDTH-1:0] wdata,
output [DATA_WIDTH-1:0] regA,
output [DATA_WIDTH-1:0] regB,
output [DATA_WIDTH-1:0] v0_data,
output [DATA_WIDTH-1:0] a0_data
);
`include "defines.vh"
reg [4:0] i;
reg [DATA_WIDTH-1:0] regfile [0:31]; ///< three ported regfile contains 32 registers
initial begin
i <= 0;
end
always @ (posedge clk) begin
if (rst) begin
for (i = 0; i < 31; i = i + 1)
begin
regfile[i] <= 0;
end
end else if (we && waddr != 0) begin
regfile[waddr] <= wdata;
end
end
assign regA = (raddrA != 0) ? regfile[raddrA] : 0;
assign regB = (raddrB != 0) ? regfile[raddrB] : 0;
assign v0_data = regfile[`V0];
assign a0_data = regfile[`A0];
endmodule // regfile
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 6-2-2021
*/
/*
NFRQ formula in the App:
Output rate is 55kHz but for NFRQ=1 the formula states that
the noise is 111kHz, twice the output rate per channel. The
reason must be the inversion of the LFSR data
That would suggest that the noise for LEFT and RIGHT are
different but the rest of the system suggest that LEFT and
RIGHT outputs are calculated at the same time, based on the
same OP output.
I have not been able to measure noise in actual chip because
operator 31 does not produce any output on my two chips. This
module is based on NukeYKT's work
*/
module jt51_noise(
input rst,
input clk,
input cen, // phi 1
input [ 4:0] cycles,
// Noise Frequency
input [ 4:0] nfrq,
// Noise envelope
input [ 9:0] eg, // serial signal in the original design
input op31_no,
output out,
output reg [11:0] mix
);
reg update, nfrq_met;
reg [ 4:0] cnt;
reg [15:0] lfsr;
reg last_lfsr0;
wire all1, fb;
wire mix_sgn;
assign out = lfsr[0];
// period counter
always @(posedge clk, posedge rst) begin
if( rst ) begin
cnt <= 5'b0;
end else if(cen) begin
if( &cycles[3:0] ) begin
cnt <= update ? 5'd0 : (cnt+5'd1);
end
update <= nfrq_met;
nfrq_met <= ~nfrq == cnt;
end
end
// LFSR
assign fb = update ? ~((all1 & ~last_lfsr0) | (lfsr[2]^last_lfsr0))
: ~lfsr[0];
assign all1 = &lfsr;
always @(posedge clk, posedge rst) begin
if( rst ) begin
lfsr <= 16'hffff;
last_lfsr0 <= 1'b0;
end else if(cen) begin
lfsr <= { fb, lfsr[15:1] };
if(update) last_lfsr0 <= ~lfsr[0];
end
end
// Noise mix
assign mix_sgn = /*eg!=10'd0 ^*/ ~out;
always @(posedge clk, posedge rst) begin
if( rst ) begin
mix <= 12'd0;
end else if( op31_no && cen ) begin
mix <= { mix_sgn, eg[9:2] ^ {8{out}}, {3{mix_sgn}} };
end
end
endmodule
|
//==================================================================================================
// Filename : antares_reg_file.v
// Created On : Tue Sep 1 10:29:48 2015
// Last Modified : Sat Nov 07 12:15:25 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : 32 General Purpose Registers (GPR)
// WARNING: This register file DO NOT HAVE A RESET.
//==================================================================================================
module antares_reg_file (
input clk,
input [4:0] gpr_ra_a,
input [4:0] gpr_ra_b,
input [4:0] gpr_wa,
input [31:0] gpr_wd,
input gpr_we,
output [31:0] gpr_rd_a,
output [31:0] gpr_rd_b
);
// Register file of 32 32-bit registers. Register 0 is always 0
reg [31:0] registers [1:31];
// Clocked write
always @ ( posedge clk ) begin
if(gpr_wa != 5'b0)
registers[gpr_wa] <= (gpr_we) ? gpr_wd : registers[gpr_wa];
end
// Combinatorial read (no delay). Register 0 is read as 0 always.
assign gpr_rd_a = (gpr_ra_a == 5'b0) ? 32'b0 : registers[gpr_ra_a];
assign gpr_rd_b = (gpr_ra_b == 5'b0) ? 32'b0 : registers[gpr_ra_b];
endmodule // antares_reg_file
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__OR4_BEHAVIORAL_PP_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , D, C, B, A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
`define SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_1_V
`define SKY130_FD_SC_HS__OR3_1_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:12:35 06/03/2016
// Design Name:
// Module Name: Banderas_Alarma
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Banderas_Alarma(
input [7:0] Segundos,
input [7:0] Minutos,
input [7:0] Horas,
input [7:0] Segundos_RTC,
input [7:0] Minutos_RTC,
input [7:0] Horas_RTC,
input [7:0] Estado,
input [7:0] Guardar,
input clk,
input reset,
output reg [7:0] Flag_Pico
);
always @(posedge clk)
if (reset)
begin
Flag_Pico <= 8'd0;
end
else
if ((Guardar == 8'h70)&&(Estado == 8'h75))
begin
if ((Segundos_RTC == Segundos )&& (Minutos_RTC == Minutos) && (Horas_RTC == Horas ) && (Segundos_RTC != 8'h00) && (Minutos_RTC != 8'h00) && (Horas_RTC != 8'h00))
begin
Flag_Pico <= 8'd1;
end
else
begin
Flag_Pico <= 8'd0;
end
end
else
begin
Flag_Pico <= Flag_Pico;
end
endmodule
|
/*
* Author : Tom Stanway-Mayers
* Description : RV32I Instruction Decoder
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
`include "riscv_defs.v"
module merlin_rv32i_decoder
(
// instruction decoder interface
// ingress side
input wire [31:0] ins_i,
// egress side
output reg ins_err_o,
output reg fencei_o,
output reg wfi_o,
output reg jump_o,
output reg ecall_o,
output reg trap_rtn_o,
output wire [1:0] trap_rtn_mode_o,
output reg [`RV_ZONE_RANGE] zone_o,
output reg regd_tgt_o,
output wire [4:0] regd_addr_o,
output reg regs1_rd_o,
output wire [4:0] regs1_addr_o,
output reg regs2_rd_o,
output wire [4:0] regs2_addr_o,
output reg [`RV_XLEN-1:0] imm_o,
output reg link_o,
output reg sels1_pc_o,
output reg sel_csr_wr_data_imm_o,
output reg sels2_imm_o,
output reg selcmps2_imm_o,
output reg [`RV_ALUOP_RANGE] aluop_o,
output wire [2:0] funct3_o,
output reg csr_rd_o,
output reg csr_wr_o,
output wire [11:0] csr_addr_o,
output reg conditional_o
);
//--------------------------------------------------------------
// global
// instruction type decoder
parameter C_IMM_TYPE_UDEF = 3'd0; // This is really "don't care"
parameter C_IMM_TYPE_R = 3'd0;
parameter C_IMM_TYPE_I = 3'd1;
parameter C_IMM_TYPE_I_ZIMM = 3'd2;
parameter C_IMM_TYPE_S = 3'd3;
parameter C_IMM_TYPE_SB = 3'd4;
parameter C_IMM_TYPE_U = 3'd5;
parameter C_IMM_TYPE_UJ = 3'd6;
parameter C_IMM_TYPE_MISC_MEM = 3'd7;
//
wire [6:0] opcode;
wire [2:0] funct3;
wire [6:0] funct7;
wire [4:0] regd_addr;
wire [4:0] regs1_addr;
reg [2:0] ins_type;
// immediate generation
reg [`RV_XLEN-1:0] sign_imm;
//--------------------------------------------------------------
//--------------------------------------------------------------
// global
//--------------------------------------------------------------
assign trap_rtn_mode_o = ins_i[29:28];
assign regd_addr_o = regd_addr;
assign regs1_addr_o = regs1_addr;
assign regs2_addr_o = ins_i[24:20];
assign funct3_o = funct3;
assign csr_addr_o = ins_i[31:20];
//--------------------------------------------------------------
// instruction type decode
//--------------------------------------------------------------
assign opcode = ins_i[ 6: 0];
assign funct3 = ins_i[14:12];
assign funct7 = ins_i[31:25];
assign regd_addr = ins_i[11: 7];
assign regs1_addr = ins_i[19:15];
//
always @ (*) begin
ins_err_o = 1'b0;
fencei_o = 1'b0;
wfi_o = 1'b0;
jump_o = 1'b0;
ecall_o = 1'b0;
trap_rtn_o = 1'b0;
zone_o = `RV_ZONE_NONE;
regd_tgt_o = 1'b0;
regs1_rd_o = 1'b0;
regs2_rd_o = 1'b0;
aluop_o = `RV_ALUOP_ADD; // NOTE: don't actually care
link_o = 1'b0;
sels1_pc_o = 1'b0;
sels2_imm_o = 1'b0;
selcmps2_imm_o = 1'b0;
sel_csr_wr_data_imm_o = 1'b0;
csr_rd_o = 1'b0;
csr_wr_o = 1'b0;
conditional_o = 1'b0;
ins_type = C_IMM_TYPE_UDEF;
//
case (opcode)
`RV_MAJOR_OPCODE_LUI : begin // lui
ins_type = C_IMM_TYPE_U;
zone_o = `RV_ZONE_REGFILE;
regd_tgt_o = 1'b1;
aluop_o = `RV_ALUOP_MOV;
sels2_imm_o = 1'b1;
end
`RV_MAJOR_OPCODE_AUIPC : begin // auipc
ins_type = C_IMM_TYPE_U;
zone_o = `RV_ZONE_REGFILE;
regd_tgt_o = 1'b1;
aluop_o = `RV_ALUOP_ADD;
sels1_pc_o = 1'b1;
sels2_imm_o = 1'b1;
end
`RV_MAJOR_OPCODE_JAL : begin // jal
ins_type = C_IMM_TYPE_UJ;
jump_o = 1'b1;
zone_o = `RV_ZONE_REGFILE;
regd_tgt_o = 1'b1;
aluop_o = `RV_ALUOP_ADD;
link_o = 1'b1;
sels1_pc_o = 1'b1;
sels2_imm_o = 1'b1;
end
`RV_MAJOR_OPCODE_JALR : begin // jalr
ins_type = C_IMM_TYPE_I;
jump_o = 1'b1;
zone_o = `RV_ZONE_REGFILE;
regd_tgt_o = 1'b1;
regs1_rd_o = 1'b1;
aluop_o = `RV_ALUOP_ADD;
link_o = 1'b1;
sels2_imm_o = 1'b1;
if (funct3 != 3'b0) begin
ins_err_o = 1'b1;
end
end
`RV_MAJOR_OPCODE_BRANCH : begin // branch
ins_type = C_IMM_TYPE_SB;
jump_o = 1'b1;
regs1_rd_o = 1'b1;
regs2_rd_o = 1'b1;
aluop_o = `RV_ALUOP_ADD;
sels1_pc_o = 1'b1;
sels2_imm_o = 1'b1;
conditional_o = 1'b1;
if (funct3 != 3'b000 &&
funct3 != 3'b001 &&
funct3 != 3'b100 &&
funct3 != 3'b101 &&
funct3 != 3'b110 &&
funct3 != 3'b111) begin
ins_err_o = 1'b1;
end
end
`RV_MAJOR_OPCODE_LOAD : begin // load
ins_type = C_IMM_TYPE_I;
zone_o = `RV_ZONE_LOADQ;
regd_tgt_o = 1'b1;
regs1_rd_o = 1'b1;
aluop_o = `RV_ALUOP_ADD;
sels2_imm_o = 1'b1;
if (funct3 != 3'b000 &&
funct3 != 3'b001 &&
funct3 != 3'b010 &&
funct3 != 3'b100 &&
funct3 != 3'b101) begin
ins_err_o = 1'b1;
end
end
`RV_MAJOR_OPCODE_STORE : begin // store
ins_type = C_IMM_TYPE_S;
regs1_rd_o = 1'b1;
regs2_rd_o = 1'b1;
zone_o = `RV_ZONE_STOREQ;
aluop_o = `RV_ALUOP_ADD;
sels2_imm_o = 1'b1;
if (funct3 != 3'b000 &&
funct3 != 3'b001 &&
funct3 != 3'b010) begin
ins_err_o = 1'b1;
end
end
`RV_MAJOR_OPCODE_OPIMM : begin // op-imm
ins_type = C_IMM_TYPE_I;
zone_o = `RV_ZONE_REGFILE;
regd_tgt_o = 1'b1;
regs1_rd_o = 1'b1;
sels2_imm_o = 1'b1;
case (funct3)
`RV_MINOR_OPCODE_ADDSUB : begin
aluop_o = `RV_ALUOP_ADD;
end
`RV_MINOR_OPCODE_SLL : begin
aluop_o = `RV_ALUOP_SLL;
if (funct7 != 7'b0000000) begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_SLT : begin
aluop_o = `RV_ALUOP_SLT;
selcmps2_imm_o = 1'b1;
end
`RV_MINOR_OPCODE_SLTU : begin
aluop_o = `RV_ALUOP_SLTU;
selcmps2_imm_o = 1'b1;
end
`RV_MINOR_OPCODE_XOR : begin
aluop_o = `RV_ALUOP_XOR;
end
`RV_MINOR_OPCODE_SRLSRA : begin
if (funct7 == 7'b0000000) begin
aluop_o = `RV_ALUOP_SRL;
end else if (funct7 == 7'b0100000) begin
aluop_o = `RV_ALUOP_SRA;
end else begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_OR : begin
aluop_o = `RV_ALUOP_OR;
end
`RV_MINOR_OPCODE_AND : begin
aluop_o = `RV_ALUOP_AND;
end
default : begin
ins_err_o = 1'b1;
end
endcase
end
`RV_MAJOR_OPCODE_OP : begin // op
ins_type = C_IMM_TYPE_R;
zone_o = `RV_ZONE_REGFILE;
regd_tgt_o = 1'b1;
regs1_rd_o = 1'b1;
regs2_rd_o = 1'b1;
case (funct3)
`RV_MINOR_OPCODE_ADDSUB : begin
if (funct7 == 7'b0000000) begin
aluop_o = `RV_ALUOP_ADD;
end else if (funct7 == 7'b0100000) begin
aluop_o = `RV_ALUOP_SUB;
end else begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_SLL : begin
aluop_o = `RV_ALUOP_SLL;
if (funct7 != 7'b0000000) begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_SLT : begin
aluop_o = `RV_ALUOP_SLT;
if (funct7 != 7'b0000000) begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_SLTU : begin
aluop_o = `RV_ALUOP_SLTU;
if (funct7 != 7'b0000000) begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_XOR : begin
aluop_o = `RV_ALUOP_XOR;
if (funct7 != 7'b0000000) begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_SRLSRA : begin
if (funct7 == 7'b0000000) begin
aluop_o = `RV_ALUOP_SRL;
end else if (funct7 == 7'b0100000) begin
aluop_o = `RV_ALUOP_SRA;
end else begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_OR : begin
aluop_o = `RV_ALUOP_OR;
if (funct7 != 7'b0000000) begin
ins_err_o = 1'b1;
end
end
`RV_MINOR_OPCODE_AND : begin
aluop_o = `RV_ALUOP_AND;
if (funct7 != 7'b0000000) begin
ins_err_o = 1'b1;
end
end
default : begin
ins_err_o = 1'b1;
end
endcase
end
`RV_MAJOR_OPCODE_MISCMEM : begin // misc-mem
ins_type = C_IMM_TYPE_MISC_MEM;
// NOTE: for now, any fence is treated as a fence.i
if (funct3 == 3'b000 && ins_i[31:28] == 4'b0 && regs1_addr == 5'b0 && regd_addr == 5'b0) begin // fence TODO - see above note
fencei_o = 1'b1;
end else if (funct3 == 3'b001 && ins_i[31:15] == 17'b0 && regd_addr == 5'b0) begin // fence.i
fencei_o = 1'b1;
end else begin
ins_err_o = 1'b1;
end
end
`RV_MAJOR_OPCODE_SYSTEM : begin // system
if (funct3 == `RV_MINOR_OPCODE_PRIV) begin
if (regd_addr == 5'b0) begin
if (funct7 == 7'b0001001) begin // TODO SFENCE.VMA
ins_err_o = 1'b1;
end else if (regs1_addr == 5'b0) begin
if (ins_i[31:20] == 12'h000) begin // ECALL
ecall_o = 1'b1;
end else if (ins_i[31:20] == 12'h001) begin // TODO EBREAK
end else if (ins_i[31:30] == 2'b0 && ins_i[27:20] == 8'h02) begin // TRAP RETURN
trap_rtn_o = 1'b1;
end else if (ins_i[31:20] == 12'h105) begin
wfi_o = 1'b1;
end else begin
ins_err_o = 1'b1;
end
end else begin
ins_err_o = 1'b1;
end
end else begin
ins_err_o = 1'b1;
end
end else if (funct3 == 3'b001 ||
funct3 == 3'b010 ||
funct3 == 3'b011) begin // CSR access with rs1
zone_o = `RV_ZONE_REGFILE;
regd_tgt_o = 1'b1;
regs1_rd_o = 1'b1;
if (regd_addr != 5'b0) begin
csr_rd_o = 1'b1;
end
if (regs1_addr != 5'b0 || funct3 == 3'b001) begin
csr_wr_o = 1'b1;
end
end else if (funct3 == 3'b101 ||
funct3 == 3'b110 ||
funct3 == 3'b111) begin // CSR access with zimm
ins_type = C_IMM_TYPE_I_ZIMM;
zone_o = `RV_ZONE_REGFILE;
regd_tgt_o = 1'b1;
sel_csr_wr_data_imm_o = 1'b1;
if (regd_addr != 5'b0) begin
csr_rd_o = 1'b1;
end
if (regs1_addr != 5'b0 || funct3 == 3'b101) begin
csr_wr_o = 1'b1;
end
end else begin
ins_err_o = 1'b1;
end
end
default : begin
ins_err_o = 1'b1;
end
endcase
end
//--------------------------------------------------------------
// immediate generation
//--------------------------------------------------------------
always @ (*) begin
if (ins_i[31]) begin
sign_imm = { `RV_XLEN {1'b1} };
end else begin
sign_imm = { `RV_XLEN {1'b0} };
end
//
case (ins_type)
C_IMM_TYPE_I : imm_o = { sign_imm[`RV_XLEN-1:11], ins_i[30:20] };
C_IMM_TYPE_I_ZIMM : imm_o = { { `RV_XLEN-5 {1'b0} }, ins_i[19:15] };
C_IMM_TYPE_S : imm_o = { sign_imm[`RV_XLEN-1:11], ins_i[30:25], ins_i[11:7] };
C_IMM_TYPE_SB : imm_o = { sign_imm[`RV_XLEN-1:12], ins_i[7], ins_i[30:25], ins_i[11:8], 1'b0 };
C_IMM_TYPE_U : imm_o = { sign_imm[`RV_XLEN-1:31], ins_i[30:12], 12'b0 };
C_IMM_TYPE_UJ : imm_o = { sign_imm[`RV_XLEN-1:20], ins_i[19:12], ins_i[20], ins_i[30:21], 1'b0 };
default : imm_o = { `RV_XLEN {1'b0} }; // NOTE don't care
endcase
end
endmodule
|
module globalbranchpredictor(clk,pcsrcd,pcsrcd2,pcd,pcbranchd,pcbranchd2,originalpc,pcnext,clrbp);
input clk;
input [1:0] pcsrcd,pcsrcd2;
input [63:0] originalpc;
input [31:0] pcbranchd,pcbranchd2, pcd;
output reg [31:0] pcnext;
output reg clrbp;
reg [71:0] branchtargetbuffer[127:0];
reg [31:0] pcstorage;
reg [1:0] global;
//66 bits, first 32 bits address, next 32 bits predicted address, 2 bits T/NT
integer i;
reg foundflag, pcdfoundflag; // foundflag for Prediction, pcdfoundflag for mispredictions
initial begin
global = 2'b00;
for (i=0; i<128; i=i+1) begin
branchtargetbuffer[i] = 72'bx;
end
end
integer j=0;
integer count=0;
integer recorder;
always @(negedge clk) begin
// IF Stage
foundflag = 1'b0;
pcdfoundflag = 1'b0;
for (i=0; i<128; i=i+1) begin
if (pcd==branchtargetbuffer[i][71:40]) begin
pcdfoundflag = 1'b1;
recorder = i;
end
if (originalpc[63:32]==branchtargetbuffer[i][71:40] ) begin
case(global)
2'b00: begin
if (!branchtargetbuffer[i][7]) begin
pcstorage = originalpc[63:32];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b01: begin
if (!branchtargetbuffer[i][5]) begin
pcstorage = originalpc[63:32];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b10: begin
if (!branchtargetbuffer[i][3]) begin
pcstorage = originalpc[63:32];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b11: begin
if (!branchtargetbuffer[i][1]) begin
pcstorage = originalpc[63:32];
pcnext = branchtargetbuffer[i][39:8];
end
end
endcase
foundflag = 1'b1;
recorder = i;
end
else if (originalpc[31:0]==branchtargetbuffer[i][71:40] ) begin
case(global)
2'b00: begin
if (!branchtargetbuffer[i][7]) begin
pcstorage = originalpc[31:0];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b01: begin
if (!branchtargetbuffer[i][5]) begin
pcstorage = originalpc[31:0];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b10: begin
if (!branchtargetbuffer[i][3]) begin
pcstorage = originalpc[31:0];
pcnext = branchtargetbuffer[i][39:8];
end
end
2'b11: begin
if (!branchtargetbuffer[i][1]) begin
pcstorage = originalpc[31:0];
pcnext = branchtargetbuffer[i][39:8];
end
end
endcase
foundflag = 1'b1;
recorder = i;
end
end
// ID and EX Stages
// found? - Yes
if (foundflag) begin
clrbp = 1'b0;
// Update the existing buffer to a higher taken
case(global)
2'b00: begin
global = 2'b00;
case(branchtargetbuffer[recorder][7:6])
2'b00: branchtargetbuffer[recorder][7:6] = 2'b00;
2'b01: branchtargetbuffer[recorder][7:6] = 2'b00;
2'b10: branchtargetbuffer[recorder][7:6] = 2'b01;
2'b11: branchtargetbuffer[recorder][7:6] = 2'b10;
endcase
end
2'b01: begin
global = 2'b00;
case(branchtargetbuffer[recorder][5:4])
2'b00: branchtargetbuffer[recorder][5:4] = 2'b00;
2'b01: branchtargetbuffer[recorder][5:4] = 2'b00;
2'b10: branchtargetbuffer[recorder][5:4] = 2'b01;
2'b11: branchtargetbuffer[recorder][5:4] = 2'b10;
endcase
end
2'b10: begin
global = 2'b01;
case(branchtargetbuffer[recorder][3:2])
2'b00: branchtargetbuffer[recorder][3:2] = 2'b00;
2'b01: branchtargetbuffer[recorder][3:2] = 2'b00;
2'b10: branchtargetbuffer[recorder][3:2] = 2'b01;
2'b11: branchtargetbuffer[recorder][3:2] = 2'b10;
endcase
end
2'b11: begin
global = 2'b10;
case(branchtargetbuffer[recorder][1:0])
2'b00: branchtargetbuffer[recorder][1:0] = 2'b00;
2'b01: branchtargetbuffer[recorder][1:0] = 2'b00;
2'b10: branchtargetbuffer[recorder][1:0] = 2'b01;
2'b11: branchtargetbuffer[recorder][1:0] = 2'b10;
endcase
end
endcase
end
// Misprediction
else if (!pcsrcd[0] && pcdfoundflag) begin
// Put back old count and issue a clr signal to pipefd
clrbp = 1'b1;
pcnext = pcstorage;
// Update the existing buffer to a lower taken
case(global)
2'b00: begin
global = 2'b01;
case(branchtargetbuffer[recorder][7:6])
2'b00: branchtargetbuffer[recorder][7:6] = 2'b01;
2'b01: branchtargetbuffer[recorder][7:6] = 2'b10;
2'b10: branchtargetbuffer[recorder][7:6] = 2'b11;
2'b11: branchtargetbuffer[recorder][7:6] = 2'b11;
endcase
end
2'b01: begin
global = 2'b11;
case(branchtargetbuffer[recorder][5:4])
2'b00: branchtargetbuffer[recorder][5:4] = 2'b01;
2'b01: branchtargetbuffer[recorder][5:4] = 2'b10;
2'b10: branchtargetbuffer[recorder][5:4] = 2'b11;
2'b11: branchtargetbuffer[recorder][5:4] = 2'b11;
endcase
end
2'b10: begin
global = 2'b01;
case(branchtargetbuffer[recorder][3:2])
2'b00: branchtargetbuffer[recorder][3:2] = 2'b01;
2'b01: branchtargetbuffer[recorder][3:2] = 2'b10;
2'b10: branchtargetbuffer[recorder][3:2] = 2'b11;
2'b11: branchtargetbuffer[recorder][3:2] = 2'b11;
endcase
end
2'b11: begin
global = 2'b11;
case(branchtargetbuffer[recorder][1:0])
2'b00: branchtargetbuffer[recorder][1:0] = 2'b01;
2'b01: branchtargetbuffer[recorder][1:0] = 2'b10;
2'b10: branchtargetbuffer[recorder][1:0] = 2'b11;
2'b11: branchtargetbuffer[recorder][1:0] = 2'b11;
endcase
end
endcase
end
//found? - No
else begin
if (pcsrcd[0]) begin//branch taken
// Write into buffer at next available spot
branchtargetbuffer[count][7:0] = 8'b0;
branchtargetbuffer[count][39:8] = pcbranchd;
branchtargetbuffer[count][71:40] = pcd;
pcnext = pcbranchd;
clrbp = 1'b0;
count = count + 1;
if (count > 127)
count = 0;
case(global)
2'b00: global=2'b00;
2'b01: global=2'b10;
2'b10: global=2'b00;
2'b11: global=2'b10;
endcase
end
else if (pcsrcd2[0]) begin//branch taken
// Write into buffer at next available spot
branchtargetbuffer[count][7:0] = 8'b0;
branchtargetbuffer[count][39:8] = pcbranchd2;
branchtargetbuffer[count][71:40] = pcd;
pcnext = pcbranchd2;
clrbp = 1'b0;
count = count + 1;
if (count > 127)
count = 0;
case(global)
2'b00: global=2'b00;
2'b01: global=2'b10;
2'b10: global=2'b00;
2'b11: global=2'b10;
endcase
end
else begin//branch not taken
clrbp = 1'b0;
pcnext = originalpc[63:32];
case(global)
2'b00: global=2'b01;
2'b01: global=2'b11;
2'b10: global=2'b01;
2'b11: global=2'b11;
endcase
end
end
end
endmodule
|
// part of NeoGS project
//
// (c) NedoPC 2013
//
// mp3 data dma controller
module dma_mp3
(
input wire clk,
input wire rst_n,
output wire [ 7:0] md_din, // mp3 data interface
output wire md_start, //
input wire md_rdy, //
input wire md_dreq, //
// signals for ports.v
//
input wire [7:0] din, // input and output from ports.v
output reg [7:0] dout,
//
input wire module_select, // =1 - module selected for read-write operations from ports.v
input wire write_strobe, // one-cycle positive write strobe - writes to the selected registers from din
//
input wire [1:0] regsel, // 2'b00 - high address, 2'b01 - middle address, 2'b10 - low address, 2'b11 - control register
// signals for DMA controller/DMA sequencer
//
output reg [21:0] dma_addr,
input wire [7:0] dma_rd, // data read from DMA
output wire dma_rnw,
//
output reg dma_req,
input wire dma_ack,
input wire dma_end,
output wire int_req
);
reg dma_on;
wire dma_finish;
wire w511;
wire rdone;
reg [3:0] state,next_state;
assign int_req = dma_finish;
assign dma_rnw = 1'b1;
localparam _HAD = 2'b00; // high address
localparam _MAD = 2'b01; // mid address
localparam _LAD = 2'b10; // low address
localparam _CST = 2'b11; // control and status
// control dout bus
always @*
case( regsel[1:0] )
_HAD: dout = { 2'b00, dma_addr[21:16] };
_MAD: dout = dma_addr[15:8];
_LAD: dout = dma_addr[7:0];
_CST: dout = { dma_on, 7'bXXX_XXXX };
endcase
// dma_on control
always @(posedge clk, negedge rst_n)
if( !rst_n )
dma_on <= 1'b0;
else if( dma_finish )
dma_on <= 1'b0;
else if( module_select && write_strobe && (regsel==_CST) )
dma_on <= din[7];
// dma_addr control
always @(posedge clk)
if( dma_req && dma_ack && dma_on )
dma_addr <= dma_addr + 22'd1; // increment on successfull DMA transfer
else if( module_select && write_strobe )
begin
if( regsel==_HAD )
dma_addr[21:16] <= din[5:0];
else if( regsel==_MAD )
dma_addr[15:8] <= din[7:0];
else if( regsel==_LAD )
dma_addr[7:0] <= din[7:0];
end
localparam _IDLE = 4'd0;
localparam _START = 4'd1;
localparam _DMARD = 4'd2;
localparam _MP3W1 = 4'd3;
localparam _MP3W2 = 4'd4;
localparam _MP3W3 = 4'd5;
localparam _STOP = 4'd6;
always @(posedge clk, negedge dma_on)
if( !dma_on )
state <= _IDLE;
else
state <= next_state;
always @*
case( state )
_IDLE: next_state = _START;
_START: next_state = _DMARD;
_DMARD:begin
if( dma_req )
next_state = _DMARD;
else
next_state = _MP3W1;
end
_MP3W1: next_state = _MP3W2;
_MP3W2:begin
if( md_rdy && md_dreq )
next_state = _MP3W3;
else
next_state = _MP3W2;
end
_MP3W3:begin
if( rdone )
next_state = _STOP;
else
next_state = _MP3W2;
end
_STOP: next_state = _STOP;
endcase
assign md_start = ( state==_MP3W3 );
assign dma_finish = ( state==_STOP );
always @(posedge clk, negedge dma_on)
if( !dma_on )
dma_req <= 1'b0;
else if( state==_START )
dma_req <= 1'b1;
else if( dma_ack && w511 )
dma_req <= 1'b0;
dma_fifo_oneshot dma_fifo_oneshot
(
.clk (clk ),
.rst_n(dma_on),
.wr_stb( dma_end ),
.rd_stb( md_start || state==_MP3W1 ),
.wdone( ),
.rdone(rdone),
.empty( ),
.w511 (w511 ),
.wd(dma_rd),
.rd(md_din)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_ua_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_ua_dp
(/*AUTOARG*/
// Outputs
so, vuad_array_wr_data_c4, vuad_dp_used_c2, vuad_dp_alloc_c2,
used_rd_parity_c2, alloc_rd_parity_c2, diag_rd_ua_out,
// Inputs
rclk, si, se, lru_way_sel_c3, fill_way_c3, hit_wayvld_c3,
bistordiag_ua_data, vuad_evict_c3, wr64_inst_c3, vuad_sel_c2,
vuad_sel_c2orc3, vuad_sel_c4, vuad_sel_rd, vuad_sel_c2_d1,
bistordiag_wr_ua_c4, sel_ua_wr_data_byp, alloc_set_cond_c3,
alloc_rst_cond_c3, fbctl_vuad_bypassed_c3, vuad_array_rd_data_c1
) ;
input rclk;
input si, se;
output so;
// 100+ pins on the right.
input [11:0] lru_way_sel_c3; // Right
input [11:0] fill_way_c3; // Right
input [11:0] hit_wayvld_c3; // Right
input [25:0] bistordiag_ua_data; // Right
// Right
input vuad_evict_c3;
input wr64_inst_c3;
// Right
input vuad_sel_c2;
input vuad_sel_c2orc3;
input vuad_sel_c4;
input vuad_sel_rd;
input vuad_sel_c2_d1;
input bistordiag_wr_ua_c4;
input sel_ua_wr_data_byp;
input alloc_set_cond_c3;
input alloc_rst_cond_c3;
input fbctl_vuad_bypassed_c3;
// Bottom
input [51:26] vuad_array_rd_data_c1 ;
output [51:26] vuad_array_wr_data_c4; // Bottom
output [11:0] vuad_dp_used_c2; // Top
output [11:0] vuad_dp_alloc_c2; // Top
output used_rd_parity_c2; // Right
output alloc_rd_parity_c2; // Right
output [25:0] diag_rd_ua_out ; // Right
wire [11:0] used_rd_byp_c2;
wire [11:0] used_rd_c2;
wire [11:0] used_byp_c1;
wire [11:0] used_byp_c3_in;
wire [11:0] used_c1;
wire [11:0] used_c2;
wire [11:0] used_c3;
wire [11:0] used_c4;
wire [11:0] used_wr_data_c5;
wire [11:0] used_wr_data_c6;
wire [11:0] alloc_rd_byp_c2;
wire [11:0] alloc_rd_c2;
wire [11:0] alloc_byp_c1;
wire [11:0] alloc_byp_c2_in;
wire [11:0] alloc_byp_c3_in;
wire [11:0] alloc_c1;
wire [11:0] alloc_c2;
wire [11:0] alloc_c3;
wire [11:0] alloc_c4;
wire [11:0] alloc_wr_data_c5;
wire [11:0] alloc_wr_data_c6;
wire [1:0] parity_rd_byp_c2, parity_rd_c2;
wire [1:0] parity_wr_c3,parity_wr_data_c4, parity_wr_data_c5, parity_wr_data_c6;
wire [11:0] used_byp_c2c3;
wire [11:0] used_byp_c4c5;
wire [11:0] alloc_byp_c2c3;
wire [11:0] alloc_byp_c4c5;
////////////////////////////////////////////////////////////////////////////////
// USED BIT ( Use leftmost 16 dp pitches for the used bit)
////////////////////////////////////////////////////////////////////////////////
// Row 17
mux2ds #(12) mux_used_c1 // 2-1 mux flop
(.dout (used_c1[11:0]),
.in0 (vuad_array_rd_data_c1[50:39]), .sel0 (vuad_sel_rd),
.in1 (used_byp_c1[11:0]), .sel1 (~vuad_sel_rd)
) ;
dff_s #(12) ff_used_c2
(.q (used_c2[11:0]), .din (used_c1[11:0]),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row16
dff_s #(13) ff_used_rd_c2 // vuad rd data c2 flop
(.q ({parity_rd_byp_c2[1],used_rd_byp_c2[11:0]}),
.din ({vuad_array_rd_data_c1[51],vuad_array_rd_data_c1[50:39]}),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row 15
assign vuad_dp_used_c2 = used_c2 ; // Top Drive using a 40X driver.
//Row14
mux2ds #(13) mux_used_rd_c2 // rd data mux
(.dout ({parity_rd_c2[1],used_rd_c2[11:0]}),
.in0 ({parity_wr_data_c6[1],used_wr_data_c6[11:0]}),
.sel0 (sel_ua_wr_data_byp),
.in1 ({parity_rd_byp_c2[1],used_rd_byp_c2[11:0]}),
.sel1 (~sel_ua_wr_data_byp)
) ;
//Row 13
// Combinational row. Use a 20x Buffer
assign diag_rd_ua_out[25] = parity_rd_c2[1];
assign diag_rd_ua_out[23:12] = used_rd_c2[11:0];
// Row 12
mux2ds #(12) mux_used_byp_c2c3 // Bypass mux c2/c3 to c1
(.dout (used_byp_c2c3[11:0]),
.in0 (used_c2[11:0]), .sel0 (vuad_sel_c2),
.in1 (used_byp_c3_in[11:0]), .sel1 (~vuad_sel_c2)
) ;
// final bypass mux can be here.
// ROw11
mux2ds #(12) mux_used_byp_c1 // Bypass mux without the critical component
(.dout (used_byp_c1[11:0]),
.in0 (used_byp_c2c3[11:0]), .sel0 (vuad_sel_c2orc3),
.in1 (used_byp_c4c5[11:0]), .sel1 (~vuad_sel_c2orc3)
) ;
//Row 10
zzpar16 parity_used_rd ( .z(used_rd_parity_c2),
.d({3'b0,parity_rd_c2[1],used_rd_c2[11:0]})
);
// Row9
dff_s #(12) ff_used_c3
(.q (used_c3[11:0]), .din (used_c2[11:0]),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row8
assign used_byp_c3_in =
(used_c3 | fill_way_c3 | hit_wayvld_c3 ) &
~( ({12{vuad_evict_c3}} & lru_way_sel_c3) |
({12{wr64_inst_c3}} & hit_wayvld_c3) |
({12{&(used_c3|alloc_c3)}}) // all ways are used or allocated.
);
// Row 7 (empty)
//Row6
zzpar16 parity_used_wr ( .z(parity_wr_c3[1]),
.d({4'b0,used_byp_c3_in[11:0]})
);
//Row5
dff_s #(13) ff_used_c4 // vuad C4 flop
(.q ({parity_wr_data_c4[1],used_c4[11:0]}),
.din ({parity_wr_c3[1],used_byp_c3_in[11:0]}),
.clk (rclk), .se(se), .si (), .so ()
) ;
//Row4
mux2ds #(13) mux_wr_array_used_c4
(.dout (vuad_array_wr_data_c4[51:39]),
.in0 ({parity_wr_data_c4[1], used_c4[11:0]}),
.sel0 (~bistordiag_wr_ua_c4),
.in1 (bistordiag_ua_data[25:13]),
.sel1 (bistordiag_wr_ua_c4)
) ;
//Row3
mux2ds #(12) mux_used_byp_c4c5 // Bypass mux c4/c5 to c1
(.dout (used_byp_c4c5[11:0]),
.in0 (used_c4[11:0]), .sel0 (vuad_sel_c4),
.in1 (used_wr_data_c5[11:0]), .sel1 (~vuad_sel_c4)
) ;
// Row 2
dff_s #(13) ff_used_wr_c5 // Vuad C5 flop
(.q ({parity_wr_data_c5[1],used_wr_data_c5[11:0]}),
.din ({parity_wr_data_c4[1],used_c4[11:0]}),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row 1
dff_s #(13) ff_used_wr_c6 // Vuad C6 flop
(.q ({parity_wr_data_c6[1],used_wr_data_c6[11:0]}),
.din ({parity_wr_data_c5[1],used_wr_data_c5[11:0]}),
.clk (rclk), .se(se), .si (), .so ()
) ;
////////////////////////////////////////////////////////////////////////////////
// ALLOC bit ( use the right 16 dp pitches )
////////////////////////////////////////////////////////////////////////////////
// Row17
// Use a 2-1 mux flop here to reduce setup
//
mux2ds #(12) mux_alloc_c1
(.dout (alloc_c1[11:0]),
.in0 (vuad_array_rd_data_c1[37:26]), .sel0 (vuad_sel_rd),
.in1 (alloc_byp_c1[11:0]), .sel1 (~vuad_sel_rd)
) ;
dff_s #(12) ff_alloc_c2
(.q (alloc_c2[11:0]), .din (alloc_c1[11:0]),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row16
dff_s #(13) ff_alloc_rd_c2 // vuad rd data c2 flop
(.q ({parity_rd_byp_c2[0],alloc_rd_byp_c2[11:0]}),
.din ({vuad_array_rd_data_c1[38],vuad_array_rd_data_c1[37:26]}),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row 15
assign vuad_dp_alloc_c2 = alloc_c2 ; // Top Drive using a 40X driver.
// Row14
mux2ds #(13) mux_alloc_rd_c2 // rd data mux
(.dout ({parity_rd_c2[0],alloc_rd_c2[11:0]}),
.in0 ({parity_wr_data_c6[0],alloc_wr_data_c6[11:0]}),
.sel0 (sel_ua_wr_data_byp),
.in1 ({parity_rd_byp_c2[0],alloc_rd_byp_c2[11:0]}),
.sel1 (~sel_ua_wr_data_byp)
) ;
// Row13
// Combinational row. Use a 20x Buffer
assign diag_rd_ua_out[24] = parity_rd_c2[0];
assign diag_rd_ua_out[11:0] = alloc_rd_c2[11:0];
// CHAnge: POST_3.4
// IN the following mux2, alloc_byp_c2 was replaced by
// alloc_byp_c2_in
// Row 12
mux2ds #(12) mux_alloc_byp_c2c3 // Bypass mux c2/c3 to c1
(.dout (alloc_byp_c2c3[11:0]),
.in0 (alloc_byp_c2_in[11:0]), .sel0 (vuad_sel_c2),
.in1 (alloc_byp_c3_in[11:0]), .sel1 (~vuad_sel_c2)
) ;
// final bypass mux can be here.
// ROw11
mux2ds #(12) mux_alloc_byp_c1 // Bypass mux without the critical component
(.dout (alloc_byp_c1[11:0]),
.in0 (alloc_byp_c2c3[11:0]), .sel0 (vuad_sel_c2orc3),
.in1 (alloc_byp_c4c5[11:0]), .sel1 (~vuad_sel_c2orc3)
) ;
//Row 10
zzpar16 parity_dir_rd ( .z(alloc_rd_parity_c2),
.d({3'b0,parity_rd_c2[0],alloc_rd_c2[11:0]})
);
// Row 9
// Use a 2-1 mux flop here to reduce setup and area
mux2ds #(12) mux_alloc_byp_c2_in
(.dout (alloc_byp_c2_in[11:0]),
.in0 (alloc_c2[11:0]), .sel0 (~vuad_sel_c2_d1),
.in1 (alloc_byp_c3_in[11:0]), .sel1 (vuad_sel_c2_d1)
) ;
dff_s #(12) ff_alloc_c3
(.q (alloc_c3[11:0]), .din (alloc_byp_c2_in[11:0]),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row8
assign alloc_byp_c3_in = ( alloc_c3 |
({12{alloc_set_cond_c3}} & hit_wayvld_c3) |
({12{vuad_evict_c3}} & lru_way_sel_c3) ) &
~( ({12{alloc_rst_cond_c3}} & hit_wayvld_c3) |
({12{fbctl_vuad_bypassed_c3}} & fill_way_c3)
);
//Row 7 is empty.
// Row6
zzpar16 parity_dir_wr ( .z(parity_wr_c3[0]),
.d({4'b0,alloc_byp_c3_in[11:0]})
);
// Row5
dff_s #(13) ff_alloc_c4 // vuad C4 flop
(.q ({parity_wr_data_c4[0],alloc_c4[11:0]}),
.din ({parity_wr_c3[0],alloc_byp_c3_in[11:0]}),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row4
mux2ds #(13) mux_wr_array_alloc_c4
(.dout (vuad_array_wr_data_c4[38:26]),
.in0 ({parity_wr_data_c4[0], alloc_c4[11:0]}),
.sel0 (~bistordiag_wr_ua_c4),
.in1 (bistordiag_ua_data[12:0]),
.sel1 (bistordiag_wr_ua_c4)
) ;
// Row3
mux2ds #(12) mux_alloc_byp_c4c5 // Bypass mux c4/c5 to c1
(.dout (alloc_byp_c4c5[11:0]),
.in0 (alloc_c4[11:0]), .sel0 (vuad_sel_c4),
.in1 (alloc_wr_data_c5[11:0]), .sel1 (~vuad_sel_c4)
) ;
// Row 2
dff_s #(13) ff_alloc_wr_c5 // Vuad C5 flop
(.q ({parity_wr_data_c5[0],alloc_wr_data_c5[11:0]}),
.din ({parity_wr_data_c4[0],alloc_c4[11:0]}),
.clk (rclk), .se(se), .si (), .so ()
) ;
// Row1
dff_s #(13) ff_alloc_wr_c6 // Vuad C6 flop
(.q ({parity_wr_data_c6[0],alloc_wr_data_c6[11:0]}),
.din ({parity_wr_data_c5[0],alloc_wr_data_c5[11:0]}),
.clk (rclk), .se(se), .si (), .so ()
) ;
endmodule
|
//-----------------------------------------------------------------------------
// system_nfa_accept_samples_generic_hw_top_1_wrapper.v
//-----------------------------------------------------------------------------
module system_nfa_accept_samples_generic_hw_top_1_wrapper
(
aclk,
aresetn,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
nfa_finals_buckets_MPLB_Clk,
nfa_finals_buckets_MPLB_Rst,
nfa_finals_buckets_M_request,
nfa_finals_buckets_M_priority,
nfa_finals_buckets_M_busLock,
nfa_finals_buckets_M_RNW,
nfa_finals_buckets_M_BE,
nfa_finals_buckets_M_MSize,
nfa_finals_buckets_M_size,
nfa_finals_buckets_M_type,
nfa_finals_buckets_M_TAttribute,
nfa_finals_buckets_M_lockErr,
nfa_finals_buckets_M_abort,
nfa_finals_buckets_M_UABus,
nfa_finals_buckets_M_ABus,
nfa_finals_buckets_M_wrDBus,
nfa_finals_buckets_M_wrBurst,
nfa_finals_buckets_M_rdBurst,
nfa_finals_buckets_PLB_MAddrAck,
nfa_finals_buckets_PLB_MSSize,
nfa_finals_buckets_PLB_MRearbitrate,
nfa_finals_buckets_PLB_MTimeout,
nfa_finals_buckets_PLB_MBusy,
nfa_finals_buckets_PLB_MRdErr,
nfa_finals_buckets_PLB_MWrErr,
nfa_finals_buckets_PLB_MIRQ,
nfa_finals_buckets_PLB_MRdDBus,
nfa_finals_buckets_PLB_MRdWdAddr,
nfa_finals_buckets_PLB_MRdDAck,
nfa_finals_buckets_PLB_MRdBTerm,
nfa_finals_buckets_PLB_MWrDAck,
nfa_finals_buckets_PLB_MWrBTerm,
nfa_forward_buckets_MPLB_Clk,
nfa_forward_buckets_MPLB_Rst,
nfa_forward_buckets_M_request,
nfa_forward_buckets_M_priority,
nfa_forward_buckets_M_busLock,
nfa_forward_buckets_M_RNW,
nfa_forward_buckets_M_BE,
nfa_forward_buckets_M_MSize,
nfa_forward_buckets_M_size,
nfa_forward_buckets_M_type,
nfa_forward_buckets_M_TAttribute,
nfa_forward_buckets_M_lockErr,
nfa_forward_buckets_M_abort,
nfa_forward_buckets_M_UABus,
nfa_forward_buckets_M_ABus,
nfa_forward_buckets_M_wrDBus,
nfa_forward_buckets_M_wrBurst,
nfa_forward_buckets_M_rdBurst,
nfa_forward_buckets_PLB_MAddrAck,
nfa_forward_buckets_PLB_MSSize,
nfa_forward_buckets_PLB_MRearbitrate,
nfa_forward_buckets_PLB_MTimeout,
nfa_forward_buckets_PLB_MBusy,
nfa_forward_buckets_PLB_MRdErr,
nfa_forward_buckets_PLB_MWrErr,
nfa_forward_buckets_PLB_MIRQ,
nfa_forward_buckets_PLB_MRdDBus,
nfa_forward_buckets_PLB_MRdWdAddr,
nfa_forward_buckets_PLB_MRdDAck,
nfa_forward_buckets_PLB_MRdBTerm,
nfa_forward_buckets_PLB_MWrDAck,
nfa_forward_buckets_PLB_MWrBTerm,
nfa_initials_buckets_MPLB_Clk,
nfa_initials_buckets_MPLB_Rst,
nfa_initials_buckets_M_request,
nfa_initials_buckets_M_priority,
nfa_initials_buckets_M_busLock,
nfa_initials_buckets_M_RNW,
nfa_initials_buckets_M_BE,
nfa_initials_buckets_M_MSize,
nfa_initials_buckets_M_size,
nfa_initials_buckets_M_type,
nfa_initials_buckets_M_TAttribute,
nfa_initials_buckets_M_lockErr,
nfa_initials_buckets_M_abort,
nfa_initials_buckets_M_UABus,
nfa_initials_buckets_M_ABus,
nfa_initials_buckets_M_wrDBus,
nfa_initials_buckets_M_wrBurst,
nfa_initials_buckets_M_rdBurst,
nfa_initials_buckets_PLB_MAddrAck,
nfa_initials_buckets_PLB_MSSize,
nfa_initials_buckets_PLB_MRearbitrate,
nfa_initials_buckets_PLB_MTimeout,
nfa_initials_buckets_PLB_MBusy,
nfa_initials_buckets_PLB_MRdErr,
nfa_initials_buckets_PLB_MWrErr,
nfa_initials_buckets_PLB_MIRQ,
nfa_initials_buckets_PLB_MRdDBus,
nfa_initials_buckets_PLB_MRdWdAddr,
nfa_initials_buckets_PLB_MRdDAck,
nfa_initials_buckets_PLB_MRdBTerm,
nfa_initials_buckets_PLB_MWrDAck,
nfa_initials_buckets_PLB_MWrBTerm,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ
);
input aclk;
input aresetn;
input indices_MPLB_Clk;
input indices_MPLB_Rst;
output indices_M_request;
output [0:1] indices_M_priority;
output indices_M_busLock;
output indices_M_RNW;
output [0:7] indices_M_BE;
output [0:1] indices_M_MSize;
output [0:3] indices_M_size;
output [0:2] indices_M_type;
output [0:15] indices_M_TAttribute;
output indices_M_lockErr;
output indices_M_abort;
output [0:31] indices_M_UABus;
output [0:31] indices_M_ABus;
output [0:63] indices_M_wrDBus;
output indices_M_wrBurst;
output indices_M_rdBurst;
input indices_PLB_MAddrAck;
input [0:1] indices_PLB_MSSize;
input indices_PLB_MRearbitrate;
input indices_PLB_MTimeout;
input indices_PLB_MBusy;
input indices_PLB_MRdErr;
input indices_PLB_MWrErr;
input indices_PLB_MIRQ;
input [0:63] indices_PLB_MRdDBus;
input [0:3] indices_PLB_MRdWdAddr;
input indices_PLB_MRdDAck;
input indices_PLB_MRdBTerm;
input indices_PLB_MWrDAck;
input indices_PLB_MWrBTerm;
input nfa_finals_buckets_MPLB_Clk;
input nfa_finals_buckets_MPLB_Rst;
output nfa_finals_buckets_M_request;
output [0:1] nfa_finals_buckets_M_priority;
output nfa_finals_buckets_M_busLock;
output nfa_finals_buckets_M_RNW;
output [0:7] nfa_finals_buckets_M_BE;
output [0:1] nfa_finals_buckets_M_MSize;
output [0:3] nfa_finals_buckets_M_size;
output [0:2] nfa_finals_buckets_M_type;
output [0:15] nfa_finals_buckets_M_TAttribute;
output nfa_finals_buckets_M_lockErr;
output nfa_finals_buckets_M_abort;
output [0:31] nfa_finals_buckets_M_UABus;
output [0:31] nfa_finals_buckets_M_ABus;
output [0:63] nfa_finals_buckets_M_wrDBus;
output nfa_finals_buckets_M_wrBurst;
output nfa_finals_buckets_M_rdBurst;
input nfa_finals_buckets_PLB_MAddrAck;
input [0:1] nfa_finals_buckets_PLB_MSSize;
input nfa_finals_buckets_PLB_MRearbitrate;
input nfa_finals_buckets_PLB_MTimeout;
input nfa_finals_buckets_PLB_MBusy;
input nfa_finals_buckets_PLB_MRdErr;
input nfa_finals_buckets_PLB_MWrErr;
input nfa_finals_buckets_PLB_MIRQ;
input [0:63] nfa_finals_buckets_PLB_MRdDBus;
input [0:3] nfa_finals_buckets_PLB_MRdWdAddr;
input nfa_finals_buckets_PLB_MRdDAck;
input nfa_finals_buckets_PLB_MRdBTerm;
input nfa_finals_buckets_PLB_MWrDAck;
input nfa_finals_buckets_PLB_MWrBTerm;
input nfa_forward_buckets_MPLB_Clk;
input nfa_forward_buckets_MPLB_Rst;
output nfa_forward_buckets_M_request;
output [0:1] nfa_forward_buckets_M_priority;
output nfa_forward_buckets_M_busLock;
output nfa_forward_buckets_M_RNW;
output [0:7] nfa_forward_buckets_M_BE;
output [0:1] nfa_forward_buckets_M_MSize;
output [0:3] nfa_forward_buckets_M_size;
output [0:2] nfa_forward_buckets_M_type;
output [0:15] nfa_forward_buckets_M_TAttribute;
output nfa_forward_buckets_M_lockErr;
output nfa_forward_buckets_M_abort;
output [0:31] nfa_forward_buckets_M_UABus;
output [0:31] nfa_forward_buckets_M_ABus;
output [0:63] nfa_forward_buckets_M_wrDBus;
output nfa_forward_buckets_M_wrBurst;
output nfa_forward_buckets_M_rdBurst;
input nfa_forward_buckets_PLB_MAddrAck;
input [0:1] nfa_forward_buckets_PLB_MSSize;
input nfa_forward_buckets_PLB_MRearbitrate;
input nfa_forward_buckets_PLB_MTimeout;
input nfa_forward_buckets_PLB_MBusy;
input nfa_forward_buckets_PLB_MRdErr;
input nfa_forward_buckets_PLB_MWrErr;
input nfa_forward_buckets_PLB_MIRQ;
input [0:63] nfa_forward_buckets_PLB_MRdDBus;
input [0:3] nfa_forward_buckets_PLB_MRdWdAddr;
input nfa_forward_buckets_PLB_MRdDAck;
input nfa_forward_buckets_PLB_MRdBTerm;
input nfa_forward_buckets_PLB_MWrDAck;
input nfa_forward_buckets_PLB_MWrBTerm;
input nfa_initials_buckets_MPLB_Clk;
input nfa_initials_buckets_MPLB_Rst;
output nfa_initials_buckets_M_request;
output [0:1] nfa_initials_buckets_M_priority;
output nfa_initials_buckets_M_busLock;
output nfa_initials_buckets_M_RNW;
output [0:7] nfa_initials_buckets_M_BE;
output [0:1] nfa_initials_buckets_M_MSize;
output [0:3] nfa_initials_buckets_M_size;
output [0:2] nfa_initials_buckets_M_type;
output [0:15] nfa_initials_buckets_M_TAttribute;
output nfa_initials_buckets_M_lockErr;
output nfa_initials_buckets_M_abort;
output [0:31] nfa_initials_buckets_M_UABus;
output [0:31] nfa_initials_buckets_M_ABus;
output [0:63] nfa_initials_buckets_M_wrDBus;
output nfa_initials_buckets_M_wrBurst;
output nfa_initials_buckets_M_rdBurst;
input nfa_initials_buckets_PLB_MAddrAck;
input [0:1] nfa_initials_buckets_PLB_MSSize;
input nfa_initials_buckets_PLB_MRearbitrate;
input nfa_initials_buckets_PLB_MTimeout;
input nfa_initials_buckets_PLB_MBusy;
input nfa_initials_buckets_PLB_MRdErr;
input nfa_initials_buckets_PLB_MWrErr;
input nfa_initials_buckets_PLB_MIRQ;
input [0:63] nfa_initials_buckets_PLB_MRdDBus;
input [0:3] nfa_initials_buckets_PLB_MRdWdAddr;
input nfa_initials_buckets_PLB_MRdDAck;
input nfa_initials_buckets_PLB_MRdBTerm;
input nfa_initials_buckets_PLB_MWrDAck;
input nfa_initials_buckets_PLB_MWrBTerm;
input sample_buffer_MPLB_Clk;
input sample_buffer_MPLB_Rst;
output sample_buffer_M_request;
output [0:1] sample_buffer_M_priority;
output sample_buffer_M_busLock;
output sample_buffer_M_RNW;
output [0:7] sample_buffer_M_BE;
output [0:1] sample_buffer_M_MSize;
output [0:3] sample_buffer_M_size;
output [0:2] sample_buffer_M_type;
output [0:15] sample_buffer_M_TAttribute;
output sample_buffer_M_lockErr;
output sample_buffer_M_abort;
output [0:31] sample_buffer_M_UABus;
output [0:31] sample_buffer_M_ABus;
output [0:63] sample_buffer_M_wrDBus;
output sample_buffer_M_wrBurst;
output sample_buffer_M_rdBurst;
input sample_buffer_PLB_MAddrAck;
input [0:1] sample_buffer_PLB_MSSize;
input sample_buffer_PLB_MRearbitrate;
input sample_buffer_PLB_MTimeout;
input sample_buffer_PLB_MBusy;
input sample_buffer_PLB_MRdErr;
input sample_buffer_PLB_MWrErr;
input sample_buffer_PLB_MIRQ;
input [0:63] sample_buffer_PLB_MRdDBus;
input [0:3] sample_buffer_PLB_MRdWdAddr;
input sample_buffer_PLB_MRdDAck;
input sample_buffer_PLB_MRdBTerm;
input sample_buffer_PLB_MWrDAck;
input sample_buffer_PLB_MWrBTerm;
input splb_slv0_SPLB_Clk;
input splb_slv0_SPLB_Rst;
input [0:31] splb_slv0_PLB_ABus;
input [0:31] splb_slv0_PLB_UABus;
input splb_slv0_PLB_PAValid;
input splb_slv0_PLB_SAValid;
input splb_slv0_PLB_rdPrim;
input splb_slv0_PLB_wrPrim;
input [0:2] splb_slv0_PLB_masterID;
input splb_slv0_PLB_abort;
input splb_slv0_PLB_busLock;
input splb_slv0_PLB_RNW;
input [0:7] splb_slv0_PLB_BE;
input [0:1] splb_slv0_PLB_MSize;
input [0:3] splb_slv0_PLB_size;
input [0:2] splb_slv0_PLB_type;
input splb_slv0_PLB_lockErr;
input [0:63] splb_slv0_PLB_wrDBus;
input splb_slv0_PLB_wrBurst;
input splb_slv0_PLB_rdBurst;
input splb_slv0_PLB_wrPendReq;
input splb_slv0_PLB_rdPendReq;
input [0:1] splb_slv0_PLB_wrPendPri;
input [0:1] splb_slv0_PLB_rdPendPri;
input [0:1] splb_slv0_PLB_reqPri;
input [0:15] splb_slv0_PLB_TAttribute;
output splb_slv0_Sl_addrAck;
output [0:1] splb_slv0_Sl_SSize;
output splb_slv0_Sl_wait;
output splb_slv0_Sl_rearbitrate;
output splb_slv0_Sl_wrDAck;
output splb_slv0_Sl_wrComp;
output splb_slv0_Sl_wrBTerm;
output [0:63] splb_slv0_Sl_rdDBus;
output [0:3] splb_slv0_Sl_rdWdAddr;
output splb_slv0_Sl_rdDAck;
output splb_slv0_Sl_rdComp;
output splb_slv0_Sl_rdBTerm;
output [0:5] splb_slv0_Sl_MBusy;
output [0:5] splb_slv0_Sl_MWrErr;
output [0:5] splb_slv0_Sl_MRdErr;
output [0:5] splb_slv0_Sl_MIRQ;
nfa_accept_samples_generic_hw_top
#(
.RESET_ACTIVE_LOW ( 1 ),
.C_indices_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_indices_AWIDTH ( 32 ),
.C_indices_DWIDTH ( 64 ),
.C_indices_NATIVE_DWIDTH ( 64 ),
.C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_finals_buckets_AWIDTH ( 32 ),
.C_nfa_finals_buckets_DWIDTH ( 64 ),
.C_nfa_finals_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_forward_buckets_AWIDTH ( 32 ),
.C_nfa_forward_buckets_DWIDTH ( 64 ),
.C_nfa_forward_buckets_NATIVE_DWIDTH ( 64 ),
.C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_nfa_initials_buckets_AWIDTH ( 32 ),
.C_nfa_initials_buckets_DWIDTH ( 64 ),
.C_nfa_initials_buckets_NATIVE_DWIDTH ( 64 ),
.C_sample_buffer_REMOTE_DESTINATION_ADDRESS ( 32'h00000000 ),
.C_sample_buffer_AWIDTH ( 32 ),
.C_sample_buffer_DWIDTH ( 64 ),
.C_sample_buffer_NATIVE_DWIDTH ( 64 ),
.C_SPLB_SLV0_BASEADDR ( 32'hD1000000 ),
.C_SPLB_SLV0_HIGHADDR ( 32'hD10000FF ),
.C_SPLB_SLV0_AWIDTH ( 32 ),
.C_SPLB_SLV0_DWIDTH ( 64 ),
.C_SPLB_SLV0_NUM_MASTERS ( 6 ),
.C_SPLB_SLV0_MID_WIDTH ( 3 ),
.C_SPLB_SLV0_NATIVE_DWIDTH ( 32 ),
.C_SPLB_SLV0_P2P ( 0 ),
.C_SPLB_SLV0_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SLV0_SMALLEST_MASTER ( 32 ),
.C_SPLB_SLV0_INCLUDE_DPHASE_TIMER ( 0 )
)
nfa_accept_samples_generic_hw_top_1 (
.aclk ( aclk ),
.aresetn ( aresetn ),
.indices_MPLB_Clk ( indices_MPLB_Clk ),
.indices_MPLB_Rst ( indices_MPLB_Rst ),
.indices_M_request ( indices_M_request ),
.indices_M_priority ( indices_M_priority ),
.indices_M_busLock ( indices_M_busLock ),
.indices_M_RNW ( indices_M_RNW ),
.indices_M_BE ( indices_M_BE ),
.indices_M_MSize ( indices_M_MSize ),
.indices_M_size ( indices_M_size ),
.indices_M_type ( indices_M_type ),
.indices_M_TAttribute ( indices_M_TAttribute ),
.indices_M_lockErr ( indices_M_lockErr ),
.indices_M_abort ( indices_M_abort ),
.indices_M_UABus ( indices_M_UABus ),
.indices_M_ABus ( indices_M_ABus ),
.indices_M_wrDBus ( indices_M_wrDBus ),
.indices_M_wrBurst ( indices_M_wrBurst ),
.indices_M_rdBurst ( indices_M_rdBurst ),
.indices_PLB_MAddrAck ( indices_PLB_MAddrAck ),
.indices_PLB_MSSize ( indices_PLB_MSSize ),
.indices_PLB_MRearbitrate ( indices_PLB_MRearbitrate ),
.indices_PLB_MTimeout ( indices_PLB_MTimeout ),
.indices_PLB_MBusy ( indices_PLB_MBusy ),
.indices_PLB_MRdErr ( indices_PLB_MRdErr ),
.indices_PLB_MWrErr ( indices_PLB_MWrErr ),
.indices_PLB_MIRQ ( indices_PLB_MIRQ ),
.indices_PLB_MRdDBus ( indices_PLB_MRdDBus ),
.indices_PLB_MRdWdAddr ( indices_PLB_MRdWdAddr ),
.indices_PLB_MRdDAck ( indices_PLB_MRdDAck ),
.indices_PLB_MRdBTerm ( indices_PLB_MRdBTerm ),
.indices_PLB_MWrDAck ( indices_PLB_MWrDAck ),
.indices_PLB_MWrBTerm ( indices_PLB_MWrBTerm ),
.nfa_finals_buckets_MPLB_Clk ( nfa_finals_buckets_MPLB_Clk ),
.nfa_finals_buckets_MPLB_Rst ( nfa_finals_buckets_MPLB_Rst ),
.nfa_finals_buckets_M_request ( nfa_finals_buckets_M_request ),
.nfa_finals_buckets_M_priority ( nfa_finals_buckets_M_priority ),
.nfa_finals_buckets_M_busLock ( nfa_finals_buckets_M_busLock ),
.nfa_finals_buckets_M_RNW ( nfa_finals_buckets_M_RNW ),
.nfa_finals_buckets_M_BE ( nfa_finals_buckets_M_BE ),
.nfa_finals_buckets_M_MSize ( nfa_finals_buckets_M_MSize ),
.nfa_finals_buckets_M_size ( nfa_finals_buckets_M_size ),
.nfa_finals_buckets_M_type ( nfa_finals_buckets_M_type ),
.nfa_finals_buckets_M_TAttribute ( nfa_finals_buckets_M_TAttribute ),
.nfa_finals_buckets_M_lockErr ( nfa_finals_buckets_M_lockErr ),
.nfa_finals_buckets_M_abort ( nfa_finals_buckets_M_abort ),
.nfa_finals_buckets_M_UABus ( nfa_finals_buckets_M_UABus ),
.nfa_finals_buckets_M_ABus ( nfa_finals_buckets_M_ABus ),
.nfa_finals_buckets_M_wrDBus ( nfa_finals_buckets_M_wrDBus ),
.nfa_finals_buckets_M_wrBurst ( nfa_finals_buckets_M_wrBurst ),
.nfa_finals_buckets_M_rdBurst ( nfa_finals_buckets_M_rdBurst ),
.nfa_finals_buckets_PLB_MAddrAck ( nfa_finals_buckets_PLB_MAddrAck ),
.nfa_finals_buckets_PLB_MSSize ( nfa_finals_buckets_PLB_MSSize ),
.nfa_finals_buckets_PLB_MRearbitrate ( nfa_finals_buckets_PLB_MRearbitrate ),
.nfa_finals_buckets_PLB_MTimeout ( nfa_finals_buckets_PLB_MTimeout ),
.nfa_finals_buckets_PLB_MBusy ( nfa_finals_buckets_PLB_MBusy ),
.nfa_finals_buckets_PLB_MRdErr ( nfa_finals_buckets_PLB_MRdErr ),
.nfa_finals_buckets_PLB_MWrErr ( nfa_finals_buckets_PLB_MWrErr ),
.nfa_finals_buckets_PLB_MIRQ ( nfa_finals_buckets_PLB_MIRQ ),
.nfa_finals_buckets_PLB_MRdDBus ( nfa_finals_buckets_PLB_MRdDBus ),
.nfa_finals_buckets_PLB_MRdWdAddr ( nfa_finals_buckets_PLB_MRdWdAddr ),
.nfa_finals_buckets_PLB_MRdDAck ( nfa_finals_buckets_PLB_MRdDAck ),
.nfa_finals_buckets_PLB_MRdBTerm ( nfa_finals_buckets_PLB_MRdBTerm ),
.nfa_finals_buckets_PLB_MWrDAck ( nfa_finals_buckets_PLB_MWrDAck ),
.nfa_finals_buckets_PLB_MWrBTerm ( nfa_finals_buckets_PLB_MWrBTerm ),
.nfa_forward_buckets_MPLB_Clk ( nfa_forward_buckets_MPLB_Clk ),
.nfa_forward_buckets_MPLB_Rst ( nfa_forward_buckets_MPLB_Rst ),
.nfa_forward_buckets_M_request ( nfa_forward_buckets_M_request ),
.nfa_forward_buckets_M_priority ( nfa_forward_buckets_M_priority ),
.nfa_forward_buckets_M_busLock ( nfa_forward_buckets_M_busLock ),
.nfa_forward_buckets_M_RNW ( nfa_forward_buckets_M_RNW ),
.nfa_forward_buckets_M_BE ( nfa_forward_buckets_M_BE ),
.nfa_forward_buckets_M_MSize ( nfa_forward_buckets_M_MSize ),
.nfa_forward_buckets_M_size ( nfa_forward_buckets_M_size ),
.nfa_forward_buckets_M_type ( nfa_forward_buckets_M_type ),
.nfa_forward_buckets_M_TAttribute ( nfa_forward_buckets_M_TAttribute ),
.nfa_forward_buckets_M_lockErr ( nfa_forward_buckets_M_lockErr ),
.nfa_forward_buckets_M_abort ( nfa_forward_buckets_M_abort ),
.nfa_forward_buckets_M_UABus ( nfa_forward_buckets_M_UABus ),
.nfa_forward_buckets_M_ABus ( nfa_forward_buckets_M_ABus ),
.nfa_forward_buckets_M_wrDBus ( nfa_forward_buckets_M_wrDBus ),
.nfa_forward_buckets_M_wrBurst ( nfa_forward_buckets_M_wrBurst ),
.nfa_forward_buckets_M_rdBurst ( nfa_forward_buckets_M_rdBurst ),
.nfa_forward_buckets_PLB_MAddrAck ( nfa_forward_buckets_PLB_MAddrAck ),
.nfa_forward_buckets_PLB_MSSize ( nfa_forward_buckets_PLB_MSSize ),
.nfa_forward_buckets_PLB_MRearbitrate ( nfa_forward_buckets_PLB_MRearbitrate ),
.nfa_forward_buckets_PLB_MTimeout ( nfa_forward_buckets_PLB_MTimeout ),
.nfa_forward_buckets_PLB_MBusy ( nfa_forward_buckets_PLB_MBusy ),
.nfa_forward_buckets_PLB_MRdErr ( nfa_forward_buckets_PLB_MRdErr ),
.nfa_forward_buckets_PLB_MWrErr ( nfa_forward_buckets_PLB_MWrErr ),
.nfa_forward_buckets_PLB_MIRQ ( nfa_forward_buckets_PLB_MIRQ ),
.nfa_forward_buckets_PLB_MRdDBus ( nfa_forward_buckets_PLB_MRdDBus ),
.nfa_forward_buckets_PLB_MRdWdAddr ( nfa_forward_buckets_PLB_MRdWdAddr ),
.nfa_forward_buckets_PLB_MRdDAck ( nfa_forward_buckets_PLB_MRdDAck ),
.nfa_forward_buckets_PLB_MRdBTerm ( nfa_forward_buckets_PLB_MRdBTerm ),
.nfa_forward_buckets_PLB_MWrDAck ( nfa_forward_buckets_PLB_MWrDAck ),
.nfa_forward_buckets_PLB_MWrBTerm ( nfa_forward_buckets_PLB_MWrBTerm ),
.nfa_initials_buckets_MPLB_Clk ( nfa_initials_buckets_MPLB_Clk ),
.nfa_initials_buckets_MPLB_Rst ( nfa_initials_buckets_MPLB_Rst ),
.nfa_initials_buckets_M_request ( nfa_initials_buckets_M_request ),
.nfa_initials_buckets_M_priority ( nfa_initials_buckets_M_priority ),
.nfa_initials_buckets_M_busLock ( nfa_initials_buckets_M_busLock ),
.nfa_initials_buckets_M_RNW ( nfa_initials_buckets_M_RNW ),
.nfa_initials_buckets_M_BE ( nfa_initials_buckets_M_BE ),
.nfa_initials_buckets_M_MSize ( nfa_initials_buckets_M_MSize ),
.nfa_initials_buckets_M_size ( nfa_initials_buckets_M_size ),
.nfa_initials_buckets_M_type ( nfa_initials_buckets_M_type ),
.nfa_initials_buckets_M_TAttribute ( nfa_initials_buckets_M_TAttribute ),
.nfa_initials_buckets_M_lockErr ( nfa_initials_buckets_M_lockErr ),
.nfa_initials_buckets_M_abort ( nfa_initials_buckets_M_abort ),
.nfa_initials_buckets_M_UABus ( nfa_initials_buckets_M_UABus ),
.nfa_initials_buckets_M_ABus ( nfa_initials_buckets_M_ABus ),
.nfa_initials_buckets_M_wrDBus ( nfa_initials_buckets_M_wrDBus ),
.nfa_initials_buckets_M_wrBurst ( nfa_initials_buckets_M_wrBurst ),
.nfa_initials_buckets_M_rdBurst ( nfa_initials_buckets_M_rdBurst ),
.nfa_initials_buckets_PLB_MAddrAck ( nfa_initials_buckets_PLB_MAddrAck ),
.nfa_initials_buckets_PLB_MSSize ( nfa_initials_buckets_PLB_MSSize ),
.nfa_initials_buckets_PLB_MRearbitrate ( nfa_initials_buckets_PLB_MRearbitrate ),
.nfa_initials_buckets_PLB_MTimeout ( nfa_initials_buckets_PLB_MTimeout ),
.nfa_initials_buckets_PLB_MBusy ( nfa_initials_buckets_PLB_MBusy ),
.nfa_initials_buckets_PLB_MRdErr ( nfa_initials_buckets_PLB_MRdErr ),
.nfa_initials_buckets_PLB_MWrErr ( nfa_initials_buckets_PLB_MWrErr ),
.nfa_initials_buckets_PLB_MIRQ ( nfa_initials_buckets_PLB_MIRQ ),
.nfa_initials_buckets_PLB_MRdDBus ( nfa_initials_buckets_PLB_MRdDBus ),
.nfa_initials_buckets_PLB_MRdWdAddr ( nfa_initials_buckets_PLB_MRdWdAddr ),
.nfa_initials_buckets_PLB_MRdDAck ( nfa_initials_buckets_PLB_MRdDAck ),
.nfa_initials_buckets_PLB_MRdBTerm ( nfa_initials_buckets_PLB_MRdBTerm ),
.nfa_initials_buckets_PLB_MWrDAck ( nfa_initials_buckets_PLB_MWrDAck ),
.nfa_initials_buckets_PLB_MWrBTerm ( nfa_initials_buckets_PLB_MWrBTerm ),
.sample_buffer_MPLB_Clk ( sample_buffer_MPLB_Clk ),
.sample_buffer_MPLB_Rst ( sample_buffer_MPLB_Rst ),
.sample_buffer_M_request ( sample_buffer_M_request ),
.sample_buffer_M_priority ( sample_buffer_M_priority ),
.sample_buffer_M_busLock ( sample_buffer_M_busLock ),
.sample_buffer_M_RNW ( sample_buffer_M_RNW ),
.sample_buffer_M_BE ( sample_buffer_M_BE ),
.sample_buffer_M_MSize ( sample_buffer_M_MSize ),
.sample_buffer_M_size ( sample_buffer_M_size ),
.sample_buffer_M_type ( sample_buffer_M_type ),
.sample_buffer_M_TAttribute ( sample_buffer_M_TAttribute ),
.sample_buffer_M_lockErr ( sample_buffer_M_lockErr ),
.sample_buffer_M_abort ( sample_buffer_M_abort ),
.sample_buffer_M_UABus ( sample_buffer_M_UABus ),
.sample_buffer_M_ABus ( sample_buffer_M_ABus ),
.sample_buffer_M_wrDBus ( sample_buffer_M_wrDBus ),
.sample_buffer_M_wrBurst ( sample_buffer_M_wrBurst ),
.sample_buffer_M_rdBurst ( sample_buffer_M_rdBurst ),
.sample_buffer_PLB_MAddrAck ( sample_buffer_PLB_MAddrAck ),
.sample_buffer_PLB_MSSize ( sample_buffer_PLB_MSSize ),
.sample_buffer_PLB_MRearbitrate ( sample_buffer_PLB_MRearbitrate ),
.sample_buffer_PLB_MTimeout ( sample_buffer_PLB_MTimeout ),
.sample_buffer_PLB_MBusy ( sample_buffer_PLB_MBusy ),
.sample_buffer_PLB_MRdErr ( sample_buffer_PLB_MRdErr ),
.sample_buffer_PLB_MWrErr ( sample_buffer_PLB_MWrErr ),
.sample_buffer_PLB_MIRQ ( sample_buffer_PLB_MIRQ ),
.sample_buffer_PLB_MRdDBus ( sample_buffer_PLB_MRdDBus ),
.sample_buffer_PLB_MRdWdAddr ( sample_buffer_PLB_MRdWdAddr ),
.sample_buffer_PLB_MRdDAck ( sample_buffer_PLB_MRdDAck ),
.sample_buffer_PLB_MRdBTerm ( sample_buffer_PLB_MRdBTerm ),
.sample_buffer_PLB_MWrDAck ( sample_buffer_PLB_MWrDAck ),
.sample_buffer_PLB_MWrBTerm ( sample_buffer_PLB_MWrBTerm ),
.splb_slv0_SPLB_Clk ( splb_slv0_SPLB_Clk ),
.splb_slv0_SPLB_Rst ( splb_slv0_SPLB_Rst ),
.splb_slv0_PLB_ABus ( splb_slv0_PLB_ABus ),
.splb_slv0_PLB_UABus ( splb_slv0_PLB_UABus ),
.splb_slv0_PLB_PAValid ( splb_slv0_PLB_PAValid ),
.splb_slv0_PLB_SAValid ( splb_slv0_PLB_SAValid ),
.splb_slv0_PLB_rdPrim ( splb_slv0_PLB_rdPrim ),
.splb_slv0_PLB_wrPrim ( splb_slv0_PLB_wrPrim ),
.splb_slv0_PLB_masterID ( splb_slv0_PLB_masterID ),
.splb_slv0_PLB_abort ( splb_slv0_PLB_abort ),
.splb_slv0_PLB_busLock ( splb_slv0_PLB_busLock ),
.splb_slv0_PLB_RNW ( splb_slv0_PLB_RNW ),
.splb_slv0_PLB_BE ( splb_slv0_PLB_BE ),
.splb_slv0_PLB_MSize ( splb_slv0_PLB_MSize ),
.splb_slv0_PLB_size ( splb_slv0_PLB_size ),
.splb_slv0_PLB_type ( splb_slv0_PLB_type ),
.splb_slv0_PLB_lockErr ( splb_slv0_PLB_lockErr ),
.splb_slv0_PLB_wrDBus ( splb_slv0_PLB_wrDBus ),
.splb_slv0_PLB_wrBurst ( splb_slv0_PLB_wrBurst ),
.splb_slv0_PLB_rdBurst ( splb_slv0_PLB_rdBurst ),
.splb_slv0_PLB_wrPendReq ( splb_slv0_PLB_wrPendReq ),
.splb_slv0_PLB_rdPendReq ( splb_slv0_PLB_rdPendReq ),
.splb_slv0_PLB_wrPendPri ( splb_slv0_PLB_wrPendPri ),
.splb_slv0_PLB_rdPendPri ( splb_slv0_PLB_rdPendPri ),
.splb_slv0_PLB_reqPri ( splb_slv0_PLB_reqPri ),
.splb_slv0_PLB_TAttribute ( splb_slv0_PLB_TAttribute ),
.splb_slv0_Sl_addrAck ( splb_slv0_Sl_addrAck ),
.splb_slv0_Sl_SSize ( splb_slv0_Sl_SSize ),
.splb_slv0_Sl_wait ( splb_slv0_Sl_wait ),
.splb_slv0_Sl_rearbitrate ( splb_slv0_Sl_rearbitrate ),
.splb_slv0_Sl_wrDAck ( splb_slv0_Sl_wrDAck ),
.splb_slv0_Sl_wrComp ( splb_slv0_Sl_wrComp ),
.splb_slv0_Sl_wrBTerm ( splb_slv0_Sl_wrBTerm ),
.splb_slv0_Sl_rdDBus ( splb_slv0_Sl_rdDBus ),
.splb_slv0_Sl_rdWdAddr ( splb_slv0_Sl_rdWdAddr ),
.splb_slv0_Sl_rdDAck ( splb_slv0_Sl_rdDAck ),
.splb_slv0_Sl_rdComp ( splb_slv0_Sl_rdComp ),
.splb_slv0_Sl_rdBTerm ( splb_slv0_Sl_rdBTerm ),
.splb_slv0_Sl_MBusy ( splb_slv0_Sl_MBusy ),
.splb_slv0_Sl_MWrErr ( splb_slv0_Sl_MWrErr ),
.splb_slv0_Sl_MRdErr ( splb_slv0_Sl_MRdErr ),
.splb_slv0_Sl_MIRQ ( splb_slv0_Sl_MIRQ )
);
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2013, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : top.v
// Author : Yibo FAN
// Created : 2013-12-24
// Description : top of encoder
//
//-------------------------------------------------------------------
//
// Modified : 2014-07-17 by HLL
// Description : lcu size changed into 64x64 (prediction to 64x64 block remains to be added)
// Modified : 2014-08-23 by HLL
// Description : optional mode for minimal tu size added
// Modified : 2014-09-11 by HLL
// Description : chroma supported
// Modified : 2014-09-18 by HLL
// Description : coe_mem bank write and read supported, cabac added
// Modified : 2014-09-22 by HLL
// Description : separated reconstruction and cover signals supported by intra
// (cover signals could come later than reconstruction signals instead of simultaneously, which gives time for partition decision)
// Modified : 2014-09-23 by HLL
// Description : rec_mem bank write and read supported, db added
// Modified : 2014-10-13 by HLL
// Description : cbf added
// Modified : 2014-10-14 by HLL
// Description : partition added
// Modified : 2014-09-15 by HLL
// Description : partition supported by h265_intra
// Modified : 2014-10-16 by HLL
// Description : mode added
// Modified : 2014-10-17 by HLL
// Description : mode_uv supported by h265_intra
// Modified : 2014-10-19 by HLL
// Description : mode_uv in h265_intra fetched from cur_mb
// Modified : 2014-10-21 by HLL
// Description : rdcost added
// Modified : 2014-11-30 by HLL
// Description : cabac renewed
// Modified : 2015-01-23 by HLL
// Description : updated for external fetch
// Modified : 2015-03-11 by HLL
// Description : bug removed (qp for tq didn't change according to "QPC" when doing prediction to chroma)
// Modified : 2015-03-12 by HLL
// Description : bug removed (the ping-pong buffers in mem_buf controlled by sys_start instead of pre_start)
// Modified : 2015-03-21 by HLL
// Description : fime added (tested with 8 (P) frames)
// Modified : 2015-03-26 by HLL
// Description : fme added (tested with 8 (P) frames)
// Modified : 2015-04-25 by HLL
// Description : mc added (tested with 8 (P) frames)
// Modified : 2015-04-29 by HLL
// Description : db connected to mc (tested with 8 (P) frames)
// Modified : 2015-06-30 by HLL
// Description : db renewed (sao supported, fetch interface added)
// Modified : 2015-08-18 by HLL
// Description : db wires connected to i/o
// Modified : 2015-08-31 by HLL
// Description : mvd added
// Modified : 2015-09-02 by HLL
// Description : mvd connected to cabac
// cabac renewed (sao function added)
// (tested with 8 P_frames and 10 I_frames)
// (small bugs(?) detected in cabac, not fixed yet)
// unnecessary fake statements removed
// Modified : 2015-09-05 by HLL
// Description : db_wdone_o replaced with db_done_o
// Modified : 2015-10-11 by HLL
// Description : define TEST_FETCH changed to NO_FETCH
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module top (
// global
clk ,
rst_n ,
// INTRA_CUR_IF
intra_cur_4x4_x_o ,
intra_cur_4x4_y_o ,
intra_cur_idx_o ,
intra_cur_sel_o ,
intra_cur_size_o ,
intra_cur_ren_o ,
intra_cur_data_i ,
// INTRA_MODE_IF
intra_md_ren_o ,
intra_md_addr_o ,
intra_md_data_i ,
// FIME_MV_IF
fime_mv_x_i ,
fime_mv_y_i ,
// FIME_CUR_IF
fime_cur_4x4_x_o ,
fime_cur_4x4_y_o ,
fime_cur_idx_o ,
fime_cur_sel_o ,
fime_cur_size_o ,
fime_cur_ren_o ,
fime_cur_data_i ,
// FIME_REF_IF
fime_ref_x_o ,
fime_ref_y_o ,
fime_ref_ren_o ,
fime_ref_data_i ,
// FME_CUR_IF
fme_cur_4x4_x_o ,
fme_cur_4x4_y_o ,
fme_cur_idx_o ,
fme_cur_sel_o ,
fme_cur_size_o ,
fme_cur_ren_o ,
fme_cur_data_i ,
// FME_REF_IF
fme_ref_x_o ,
fme_ref_y_o ,
fme_ref_ren_o ,
fme_ref_data_i ,
// MC_REF_IF
mc_ref_x_o ,
mc_ref_y_o ,
mc_ref_ren_o ,
mc_ref_sel_o ,
mc_ref_data_i ,
// DB_FETCH_IF
db_wen_o ,
db_w4x4_x_o ,
db_w4x4_y_o ,
db_wprevious_o ,
db_done_o ,
db_wsel_o ,
db_wdata_o ,
db_ren_o ,
db_r4x4_o ,
db_ridx_o ,
db_rdata_i ,
// ORIGINAL SIGNALS
sys_x_total_i ,
sys_y_total_i ,
sys_mode_i ,
sys_type_i ,
sys_qp_i ,
sys_start_i ,
sys_done_o ,
pre_min_size_i ,
rinc_o ,
rvalid_i ,
rdata_i ,
winc_o ,
wdata_o ,
wfull_i
);
//*** PARAMETER ****************************************************************
localparam INTRA = 0 ,
INTER = 1 ;
//*** INPUT/OUTPUT DECLARATION *************************************************
input clk ; //clock
input rst_n ; //reset signal
// INTRA_CUR_IF
output [3 : 0] intra_cur_4x4_x_o ;
output [3 : 0] intra_cur_4x4_y_o ;
output [4 : 0] intra_cur_idx_o ;
output intra_cur_sel_o ;
output [1 : 0] intra_cur_size_o ;
output intra_cur_ren_o ;
input [`PIXEL_WIDTH*32-1 : 0] intra_cur_data_i ;
// INTRA_MODE_IF
output intra_md_ren_o ;
output [9 : 0] intra_md_addr_o ;
input [5 : 0] intra_md_data_i ;
// FIME_MV_IF
input [9-1 : 0] fime_mv_x_i ;
input [9-1 : 0] fime_mv_y_i ;
// FIME_CUR_IF
output [4-1 : 0] fime_cur_4x4_x_o ;
output [4-1 : 0] fime_cur_4x4_y_o ;
output [5-1 : 0] fime_cur_idx_o ;
output fime_cur_sel_o ;
output [2-1 : 0] fime_cur_size_o ;
output fime_cur_ren_o ;
input [64*`PIXEL_WIDTH-1 : 0] fime_cur_data_i ;
// FIME_REF_IF
output [5-1 : 0] fime_ref_x_o ;
output [7-1 : 0] fime_ref_y_o ;
output fime_ref_ren_o ;
input [64*`PIXEL_WIDTH-1 : 0] fime_ref_data_i ;
// FME_CUR_IF
output [4-1 : 0] fme_cur_4x4_x_o ;
output [4-1 : 0] fme_cur_4x4_y_o ;
output [5-1 : 0] fme_cur_idx_o ;
output fme_cur_sel_o ;
output [2-1 : 0] fme_cur_size_o ;
output fme_cur_ren_o ;
input [32*`PIXEL_WIDTH-1 : 0] fme_cur_data_i ;
// FME_REF_IF
output [7-1 : 0] fme_ref_x_o ;
output [7-1 : 0] fme_ref_y_o ;
output fme_ref_ren_o ;
input [64*`PIXEL_WIDTH-1 : 0] fme_ref_data_i ;
// MC_REF_IF
output [6-1 : 0] mc_ref_x_o ;
output [6-1 : 0] mc_ref_y_o ;
output mc_ref_ren_o ;
output mc_ref_sel_o ;
input [8*`PIXEL_WIDTH-1 : 0] mc_ref_data_i ;
// DB_FETCH_IF
output [1-1 : 0] db_wen_o ; // db write enable
output [5-1 : 0] db_w4x4_x_o ; // db write 4x4 block index in x
output [5-1 : 0] db_w4x4_y_o ; // db write 4x4 block index in y
output [1-1 : 0] db_wprevious_o ; // db write previous lcu data
output [1-1 : 0] db_done_o ; // db done
output [2-1 : 0] db_wsel_o ; // db write 4x4 block sel : 0x:luma, 10: u, 11:v
output [16*`PIXEL_WIDTH-1 : 0] db_wdata_o ; // db write 4x4 block data
output [1-1 : 0] db_ren_o ; // db read enable
output [5-1 : 0] db_r4x4_o ; // db_read 4x4 block index
output [2-1 : 0] db_ridx_o ; // db read pixel index in the block
input [16*`PIXEL_WIDTH-1 : 0] db_rdata_i ; // db read 4x4 block data
// sys if
input [`PIC_X_WIDTH-1 : 0] sys_x_total_i ; // Total LCU number-1 in X
input [`PIC_Y_WIDTH-1 : 0] sys_y_total_i ; // Total LCU number-1 in y
input sys_mode_i ; // Encoder Mode
input [5 : 0] sys_qp_i ; // QP assigned to CMB
input sys_start_i ; // Start to encoder a Frame
input sys_type_i ; // Encoder Type
output sys_done_o ; // Frame encoding Done
input pre_min_size_i ; // minimal tu size
// raw input if
output rinc_o ; // read data enable
input rvalid_i ; // read data valid
input [`PIXEL_WIDTH*8-1 : 0] rdata_i ; // read data
// stream output if
output winc_o ; // write bs enable
output [7 : 0] wdata_o ; // write bs data
input wfull_i ; // outside buffer FULL!
//*** WIRE & REG DECLARATION ***************************************************
//------------------ u_top_ctrl -----------------//
wire intra_start , ec_start , fime_start , fme_start , mc_start ;
wire intra_done , ec_done , fime_done , fme_done , mc_done ;
wire [`PIC_X_WIDTH-1 : 0] intra_x , ec_x , fime_x , fme_x , mc_x ;
wire [`PIC_Y_WIDTH-1 : 0] intra_y , ec_y , fime_y , fme_y , mc_y ;
reg [5 : 0] intra_qp , ec_qp , fime_qp , fme_qp , mc_qp ;
wire [5 : 0] tq_qp ;
reg sel_r ;
reg [1 : 0] sel_mod_3_r ;
//------------------- u_cur_mb ------------------//
wire [1 : 0] fme_cmb_bank ; // 0x: luma, 10: cb; 11:cr
wire fme_cmb_ren ; // cmb read enable
wire [1 : 0] fme_cmb_size ; // cmb read size (00:4x4 01:8x8 10:16x16 11:32x32)
wire [3 : 0] fme_cmb_4x4_x ; // cmb read block top_left 4x4 x
wire [3 : 0] fme_cmb_4x4_y ; // cmb read block top_left 4x4 y
wire [4 : 0] fme_cmb_idx ; // read index ({blk_index, line_number})
wire [`PIXEL_WIDTH*32-1 : 0] fme_cmb_data ; // pixel data
wire tq_cmb_sel ; // 0: luma, 1:chroma
wire tq_cmb_ren ; // cmb read enable
wire [1 : 0] tq_cmb_size ; // cmb read size (00:4x4 01:8x8 10:16x16 11:32x32)
wire [3 : 0] tq_cmb_4x4_x ; // cmb read block top_left 4x4 x
wire [3 : 0] tq_cmb_4x4_y ; // cmb read block top_left 4x4 y
wire [4 : 0] tq_cmb_idx ; // read index ({blk_index, line_number})
wire [`PIXEL_WIDTH*32-1 : 0] tq_cmb_data ; // pixel data
wire intra_md_ren ;
wire [9 : 0] intra_md_addr ;
wire [5 : 0] intra_md_data ;
//-------------------- u_intra -------------------
wire intra_ipre_en ; // tq data enable
wire [1 : 0] intra_ipre_sel ; // 0x: luma, 10: cb; 11:cr
wire [1 : 0] intra_ipre_size ; // tq tu size (00:4x4 01:8x8 10:16x16 11:32
wire [3 : 0] intra_ipre_4x4_x ; // tq 4x4 block index x in LCU
wire [3 : 0] intra_ipre_4x4_y ; // tq 4x4 block index y in LCU
wire [`PIXEL_WIDTH*16-1 : 0] intra_ipre_data ; // tq predicted pixels
wire [5 : 0] intra_ipre_mode ; // tq prediction mode
//--------------------- u_fime --------------------
wire curif_en_w ; // current LCU load enabale signal
wire [5 : 0] curif_num_w ; // current LCU row number to load (64 rows)
wire [`PIXEL_WIDTH*64-1 : 0] curif_data_w ; // current LCU row data
wire [41 : 0] fmeif_partition_w ; // CU partition info (16+4+1) * 2
wire [5 : 0] fmeif_cu_num_w ; // 8x8 CU number
wire [`FMV_WIDTH*2-1 : 0] fmeif_mv_w ; // 8x8 PU MVs
wire fmeif_en_w ; // 8x8 PU dump enable signal
wire [`FMV_WIDTH-1 : 0] fmeif_mv_x_w ;
wire [`FMV_WIDTH-1 : 0] fmeif_mv_y_w ;
reg [41 : 0] fmeif_partition_r ;
//--------------------- u_fme ---------------------//
wire [41 : 0] fimeif_partition_w ; // ime partition info
wire [1-1 : 0] fimeif_mv_rden_w ; // imv read enable
wire [6-1 : 0] fimeif_mv_rdaddr_w ; // imv sram read address
wire [2*`FMV_WIDTH-1 : 0] fimeif_mv_data_w ; // imv from fime
wire [2*`FMV_WIDTH-1 : 0] fimeif_mv_data_w_0 ;
wire [2*`FMV_WIDTH-1 : 0] fimeif_mv_data_w_1 ;
wire [1-1 : 0] mcif_mv_rden_w ; // half fmv write back enable
wire [6-1 : 0] mcif_mv_rdaddr_w ; // half fmv write back address
reg [2*`FMV_WIDTH-1 : 0] mcif_mv_rddata_w ; // half fmv
wire mcif_mv_wren_w ; // fmv sram write enable
wire [6-1 : 0] mcif_mv_wraddr_w ; // fmv sram write address
wire [2*`FMV_WIDTH-1 : 0] mcif_mv_wrdata_w ; // fmv data
wire [32*`PIXEL_WIDTH-1 : 0] mcif_pre_pixel_w ;
wire [4-1 : 0] mcif_pre_wren_w ;
wire [7-1 : 0] mcif_pre_addr_w ;
reg [1-1 : 0] fme_mv_mem_0_rden_w ;
reg [6-1 : 0] fme_mv_mem_0_rdaddr_w ;
wire [2*`FMV_WIDTH-1 : 0] fme_mv_mem_0_rddata_w ;
reg fme_mv_mem_0_wren_w ;
reg [6-1 : 0] fme_mv_mem_0_wraddr_w ;
reg [2*`FMV_WIDTH-1 : 0] fme_mv_mem_0_wrdata_w ;
reg [1-1 : 0] fme_mv_mem_1_rden_w ;
reg [6-1 : 0] fme_mv_mem_1_rdaddr_w ;
wire [2*`FMV_WIDTH-1 : 0] fme_mv_mem_1_rddata_w ;
reg fme_mv_mem_1_wren_w ;
reg [6-1 : 0] fme_mv_mem_1_wraddr_w ;
reg [2*`FMV_WIDTH-1 : 0] fme_mv_mem_1_wrdata_w ;
reg [1-1 : 0] fme_mv_mem_2_rden_w ;
reg [6-1 : 0] fme_mv_mem_2_rdaddr_w ;
wire [2*`FMV_WIDTH-1 : 0] fme_mv_mem_2_rddata_w ;
reg fme_mv_mem_2_wren_w ;
reg [6-1 : 0] fme_mv_mem_2_wraddr_w ;
reg [2*`FMV_WIDTH-1 : 0] fme_mv_mem_2_wrdata_w ;
//---------------------- u_mc ---------------------//
wire mc_mv_rden_w ;
wire [6-1 : 0] mc_mv_rdaddr_w ;
reg [2*`FMV_WIDTH-1 : 0] mc_mv_w ;
reg [41 : 0] mc_partition_r ;
wire mc_ppre_en ;
wire [1 : 0] mc_ppre_sel ;
wire [1 : 0] mc_ppre_size ;
wire [3 : 0] mc_ppre_4x4_x ;
wire [3 : 0] mc_ppre_4x4_y ;
wire [`PIXEL_WIDTH*16-1 : 0] mc_ppre_data ;
wire [5 : 0] mc_ppre_mode ;
wire [4-1 : 0] fme_rec_mem_0_wen_i ;
wire [8-1 : 0] fme_rec_mem_0_addr_i ;
wire [32*`PIXEL_WIDTH-1 : 0] fme_rec_mem_0_wdata_i ;
wire [4-1 : 0] fme_rec_mem_1_wen_i ;
wire [8-1 : 0] fme_rec_mem_1_addr_i ;
wire [32*`PIXEL_WIDTH-1 : 0] fme_rec_mem_1_wdata_i ;
wire [4-1 : 0] mc_pre_wren_w ;
wire [7-1 : 0] mc_pre_wraddr_w ;
wire [32*`PIXEL_WIDTH-1 : 0] mc_pre_wrdata_w ;
wire mc_mvd_wen_w ;
wire [`CU_DEPTH*2-1 : 0] mc_mvd_waddr_w ;
wire [`MVD_WIDTH*2 : 0] mc_mvd_wdata_w ;
wire mc_mvd_mem_0_wren_w ;
wire [`CU_DEPTH*2-1 : 0] mc_mvd_mem_0_wraddr_w ;
wire [`MVD_WIDTH*2 : 0] mc_mvd_mem_0_wrdata_w ;
wire mc_mvd_mem_1_wren_w ;
wire [`CU_DEPTH*2-1 : 0] mc_mvd_mem_1_wraddr_w ;
wire [`MVD_WIDTH*2 : 0] mc_mvd_mem_1_wrdata_w ;
wire [1-1 : 0] mc_pred_ren_w ;
wire [2-1 : 0] mc_pred_size_w ;
wire [4-1 : 0] mc_pred_4x4_x_w ;
wire [4-1 : 0] mc_pred_4x4_y_w ;
wire [5-1 : 0] mc_pred_4x4_idx_w ;
wire [32*`PIXEL_WIDTH-1 : 0] mc_pred_rdata_w ;
wire [32*`PIXEL_WIDTH-1 : 0] mc_pred_rdata_0_w ;
wire [32*`PIXEL_WIDTH-1 : 0] mc_pred_rdata_1_w ;
//------------------- u_mem_buf -------------------//
wire rec_cov ; // reconstructed pixel cover flag
wire rec_val ;
wire [4 : 0] rec_idx ;
wire [`PIXEL_WIDTH*32-1 : 0] rec_data ;
wire [`LCU_SIZE*`LCU_SIZE/16-1 : 0] tq_cbf_luma ;
wire [`LCU_SIZE*`LCU_SIZE/64-1 : 0] tq_cbf_cb ;
wire [`LCU_SIZE*`LCU_SIZE/64-1 : 0] tq_cbf_cr ;
//-------------------- u_md --------------------//
wire [1 : 0] pre_bank ; // memory bank sel for coeff. & rec.
wire [1 : 0] ec_bank ; // memory bank sel for cabac
wire [1 : 0] db_bank ; // memory bank sel for deblocking filter
wire pre_cbank ; // memory bank sel for chroma
wire ec_cbank ; // memory bank sel for chroma
wire db_cbank ; // memory bank sel for chroma
wire md_mb_type ; // 1: I MB, 0: P/B MB
wire [20 : 0] md_mb_partition ; // CU partition mode
wire [((2^`CU_DEPTH)^2)*6-1 : 0] md_i_mode ; // intra mode info
wire [169 : 0] md_p_mode ; // Inter PU partition mode for every CU size
//-------------------- u_tq --------------------//
// Residual
wire tq_res_en ; // tq data input enable
wire [1 : 0] tq_res_sel ; // 0x: luma, 10: cb; 11:cr
wire [1 : 0] tq_res_size ; // tq input tu size (00:4x4 01:8x8 10:16x16 11:32x32)
wire [4 : 0] tq_res_idx ; // tq input row pixel index
wire [(`PIXEL_WIDTH+1)*32-1 : 0] tq_res_data ; // tq input residuals
// Reconstructed
wire tq_rec_val ; // tq data output valid
wire [4 : 0] tq_rec_idx ; // tq output row pixel index
wire [(`PIXEL_WIDTH+1)*32-1 : 0] tq_rec_data ; // tq output reconstructed pixels
// Coefficient
wire tq_cef_en ; // tq coefficient enable
wire tq_cef_rw ; // tq coefficient read/write, 1: write; 0: read
wire [4 : 0] tq_cef_idx ; // tq coefficient row pixel index
wire [`COEFF_WIDTH*32-1 : 0] tq_cef_wdata ; // tq coefficient write values
wire [`COEFF_WIDTH*32-1 : 0] tq_cef_rdata ; // tq coefficient read values
// to be delete
wire tq_cef_ren ;
wire [4 : 0] tq_cef_ridx ;
wire tq_cef_wen ;
wire [4 : 0] tq_cef_widx ;
wire ipre_en ;
wire [1 : 0] ipre_sel ;
wire [1 : 0] ipre_size ;
wire [3 : 0] ipre_4x4_x ;
wire [3 : 0] ipre_4x4_y ;
wire [`PIXEL_WIDTH*16-1 : 0] ipre_data ;
wire [5 : 0] ipre_mode ;
//---------------------- u_ec ---------------------//
reg [41 : 0] ec_partition_r ;
wire ec_mb_type ; // 1: I MB, 0: P/B MB
wire [20 : 0] ec_mb_partition ; // CU partition mode
wire [((2^`CU_DEPTH)^2)*6-1 : 0] ec_i_mode ; // intra mode info
wire [169 : 0] ec_p_mode ; // Inter PU partition mode for every CU size
wire ec_mvd_ren_w ; // Inter MVD MEM IF
wire [`CU_DEPTH*2-1 : 0] ec_mvd_raddr_w ;
wire [`MVD_WIDTH*2 : 0] ec_mvd_rdata_w ;
wire [`CU_DEPTH*2-1 : 0] mc_mvd_mem_0_rdaddr_w ;
wire [`MVD_WIDTH*2 : 0] mc_mvd_mem_0_rddata_w ;
wire [`CU_DEPTH*2-1 : 0] mc_mvd_mem_1_rdaddr_w ;
wire [`MVD_WIDTH*2 : 0] mc_mvd_mem_1_rddata_w ;
wire ec_mem_ren ;
wire [1 : 0] ec_mem_sel ;
wire [8 : 0] ec_mem_raddr ;
wire [`COEFF_WIDTH*16-1 : 0] ec_mem_rdata ;
wire [`LCU_SIZE*`LCU_SIZE/16-1 : 0] ec_cbf_luma ;
wire [`LCU_SIZE*`LCU_SIZE/16-1 : 0] ec_cbf_cb ;
wire [`LCU_SIZE*`LCU_SIZE/16-1 : 0] ec_cbf_cr ;
//---------------------- u_db ---------------------//
reg [41 : 0] db_inter_partition_r ;
wire [20 : 0] db_intra_partition_w ;
wire db_mv_rden_w ;
wire [7-1 : 0] db_mv_rdaddr_ori_w ;
wire [6-1 : 0] db_mv_rdaddr_w ;
reg [2*`FMV_WIDTH-1 : 0] db_mv_w ;
wire db_mem_ren ;
wire [8 : 0] db_mem_raddr ;
wire [`PIXEL_WIDTH*16-1 : 0] db_mem_rdata ;
wire db_mb_en ;
wire db_mb_rw ;
wire [8 : 0] db_mb_addr ;
reg [128-1 : 0] db_rdata ;
wire [128-1 : 0] db_mb_data_o ;
wire [20 : 0] partition_old ;
wire [20 : 0] partition_cur ;
wire lm_md_renab ;
wire [5 : 0] lm_md_raddr ;
wire [23 : 0] lm_md_rdata ;
wire cm_md_renab ;
wire [3 : 0] cm_md_raddr ;
wire [23 : 0] cm_md_rdata ;
//*** MAIN BODY ****************************************************************
//-------------------------------------------------------------------
//
// Global Signals
//
//-------------------------------------------------------------------
// intra_qp
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
intra_qp <= 0 ;
else if( sys_start_i ) begin
intra_qp <= sys_qp_i ;
end
end
// ec_qp
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
ec_qp <= 0 ;
else if( sys_start_i ) begin
if( sys_type_i==INTRA )
ec_qp <= intra_qp ;
else begin
ec_qp <= mc_qp ;
end
end
end
// fime_qp
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
fime_qp <= 0 ;
else if( sys_start_i ) begin
fime_qp <= sys_qp_i ;
end
end
// fme_qp
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
fme_qp <= 0 ;
else if( sys_start_i ) begin
fme_qp <= fime_qp ;
end
end
// mc_qp
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
mc_qp <= 0 ;
else if( sys_start_i ) begin
mc_qp <= fme_qp ;
end
end
// sel_r
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
sel_r <= 0 ;
else if( sys_start_i ) begin
sel_r <= !sel_r ;
end
end
// sel_mod_3_r
always @(posedge clk or negedge rst_n )begin
if( !rst_n )
sel_mod_3_r <= 0 ;
else if( sys_start_i ) begin
if( sel_mod_3_r==2 )
sel_mod_3_r <= 0 ;
else begin
sel_mod_3_r <= sel_mod_3_r + 1 ;
end
end
end
//--------------------------------------------------------------------
//
// Top module controller
//
//--------------------------------------------------------------------
top_ctrl u_top_ctrl(
.clk ( clk ),
.rst_n ( rst_n ),
.sys_x_total_i ( sys_x_total_i ),
.sys_y_total_i ( sys_y_total_i ),
.sys_mode_i ( sys_mode_i ),
.sys_type_i ( sys_type_i ),
.enc_start_i ( sys_start_i ),
.enc_done_o ( sys_done_o ),
.intra_start_o ( intra_start ),
.ec_start_o ( ec_start ),
.fime_start_o ( fime_start ),
.fme_start_o ( fme_start ),
.mc_start_o ( mc_start ),
.intra_done_i ( intra_done ),
.ec_done_i ( ec_done ),
.fime_done_i ( fime_done ),
.fme_done_i ( fme_done ),
.mc_done_i ( mc_done ),
.db_done_i ( db_done ),
.intra_x_o ( intra_x ),
.intra_y_o ( intra_y ),
.ec_x_o ( ec_x ),
.ec_y_o ( ec_y ),
.fime_x_o ( fime_x ),
.fime_y_o ( fime_y ),
.fme_x_o ( fme_x ),
.fme_y_o ( fme_y ),
.mc_x_o ( mc_x ),
.mc_y_o ( mc_y )
);
//-------------------------------------------------------------------
//
// Intra Block
//
//-------------------------------------------------------------------
intra_top u_intra_top(
.clk ( clk ),
.rst_n ( rst_n ),
// ctrl if
.pre_min_size_i ( pre_min_size_i ),
.uv_partition_i ( partition_cur ),
.mb_x_total_i ( sys_x_total_i ),
.mb_x_i ( intra_x ),
.mb_y_i ( intra_y ),
.start_i ( intra_start ),
.done_o ( intra_done ),
// pre mode if
.md_rden_o ( intra_md_ren_o ),
.md_raddr_o ( intra_md_addr_o ),
.md_rdata_i ( intra_md_data_i ),
// tq pred if
.pre_en_o ( intra_ipre_en ),
.pre_sel_o ( intra_ipre_sel ),
.pre_size_o ( intra_ipre_size ),
.pre_4x4_x_o ( intra_ipre_4x4_x ),
.pre_4x4_y_o ( intra_ipre_4x4_y ),
.pre_data_o ( intra_ipre_data ),
.pre_mode_o ( intra_ipre_mode ),
// tq rec if
.rec_val_i ( rec_val & (sys_type_i==INTRA) ),
.rec_idx_i ( rec_idx ),
.rec_data_i ( rec_data ),
// pt if
.cover_valid_i ( cover_valid ),
.cover_value_i ( cover_value )
);
//-------------------------------------------------------------------
//
// FIME Block
//
//-------------------------------------------------------------------
assign fime_cur_4x4_x_o = 0 ;
assign fime_cur_4x4_y_o = curif_num_w[5]<<3 ;
assign fime_cur_idx_o = curif_num_w[4:0] ;
assign fime_cur_sel_o = 0 ;
assign fime_cur_size_o = 2'b11 ;
assign fime_cur_ren_o = curif_en_w ;
assign curif_data_w = fime_cur_data_i ;
ime_top u_ime_top(
// global
.clk ( clk ),
.rstn ( rst_n ),
// sys
.sysif_cmb_x_i ( fime_x ),
.sysif_cmb_y_i ( fime_y ),
.sysif_qp_i ( fime_qp ),
.sysif_start_i ( fime_start ),
.sysif_done_o ( fime_done ),
// cur_if
.curif_en_o ( curif_en_w ),
.curif_num_o ( curif_num_w ),
.curif_data_i ( curif_data_w ),
// fetch_if
.fetchif_ref_x_o ( fime_ref_x_o ),
.fetchif_ref_y_o ( fime_ref_y_o ),
.fetchif_load_o ( fime_ref_ren_o ),
.fetchif_data_i ( fime_ref_data_i ),
// fme_if
.fmeif_partition_o ( fmeif_partition_w ),
.fmeif_cu_num_o ( fmeif_cu_num_w ),
.fmeif_mv_o ( fmeif_mv_w ),
.fmeif_en_o ( fmeif_en_w )
);
// mask the donnot-care bit
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
fmeif_partition_r <= 42'b0 ;
else if( sys_start_i ) begin
fmeif_partition_r <= 42'b0 ;
fmeif_partition_r[1:0] <= fmeif_partition_w[1:0];
if( fmeif_partition_w[1:0]==2'b11 ) begin
fmeif_partition_r[9:2] <= fmeif_partition_w[9:2];
if( fmeif_partition_w[3:2]==2'b11 ) begin
fmeif_partition_r[17:10] <= fmeif_partition_w[17:10];
end
if( fmeif_partition_w[5:4]==2'b11 ) begin
fmeif_partition_r[25:18] <= fmeif_partition_w[25:18];
end
if( fmeif_partition_w[7:6]==2'b11 ) begin
fmeif_partition_r[33:26] <= fmeif_partition_w[33:26];
end
if( fmeif_partition_w[9:8]==2'b11 ) begin
fmeif_partition_r[41:34] <= fmeif_partition_w[41:34];
end
end
end
end
// mv_mem
assign fmeif_mv_y_w = {(fmeif_mv_w[1*`IMV_WIDTH-1:0*`IMV_WIDTH]-12),2'b0} ;
assign fmeif_mv_x_w = {(fmeif_mv_w[2*`IMV_WIDTH-1:1*`IMV_WIDTH]-12),2'b0} ;
rf_2p #(
.Word_Width ( 2*`FMV_WIDTH ),
.Addr_Width ( 6 )
) fime_mv_mem_0 (
.clkb ( clk ),
.cenb_i ( 1'b0 ),
.wenb_i ( !(fmeif_en_w&( sel_r)) ),
.addrb_i ( fmeif_cu_num_w ),
.datab_i ( { fmeif_mv_x_w
,fmeif_mv_y_w
} ),
.clka ( clk ),
.cena_i ( 1'b0 ),
.addra_i ( { fimeif_mv_rdaddr_w[5]
,fimeif_mv_rdaddr_w[2]
,fimeif_mv_rdaddr_w[4]
,fimeif_mv_rdaddr_w[1]
,fimeif_mv_rdaddr_w[3]
,fimeif_mv_rdaddr_w[0]
} ),
.dataa_o ( fimeif_mv_data_w_0 )
);
rf_2p #(
.Word_Width ( 2*`FMV_WIDTH ),
.Addr_Width ( 6 )
) fime_mv_mem_1 (
.clkb ( clk ),
.cenb_i ( 1'b0 ),
.wenb_i ( !(fmeif_en_w&(!sel_r)) ),
.addrb_i ( fmeif_cu_num_w ),
.datab_i ( { fmeif_mv_x_w
,fmeif_mv_y_w
} ),
.clka ( clk ),
.cena_i ( 1'b0 ),
.addra_i ( { fimeif_mv_rdaddr_w[5]
,fimeif_mv_rdaddr_w[2]
,fimeif_mv_rdaddr_w[4]
,fimeif_mv_rdaddr_w[1]
,fimeif_mv_rdaddr_w[3]
,fimeif_mv_rdaddr_w[0]
} ),
.dataa_o ( fimeif_mv_data_w_1 )
);
//-------------------------------------------------------------------
//
// FME Block
//
//-------------------------------------------------------------------
assign fme_cur_sel_o = 1'b0 ;
assign fme_cur_size_o = 2'b01 ;
// change the order
assign fimeif_partition_w = { fmeif_partition_r[11:10] ,fmeif_partition_r[11+2:10+2] ,fmeif_partition_r[11+4:10+4] ,fmeif_partition_r[11+6:10+6]
,fmeif_partition_r[19:18] ,fmeif_partition_r[19+2:18+2] ,fmeif_partition_r[19+4:18+4] ,fmeif_partition_r[19+6:18+6]
,fmeif_partition_r[27:26] ,fmeif_partition_r[27+2:26+2] ,fmeif_partition_r[27+4:26+4] ,fmeif_partition_r[27+6:26+6]
,fmeif_partition_r[35:34] ,fmeif_partition_r[35+2:34+2] ,fmeif_partition_r[35+4:34+4] ,fmeif_partition_r[35+6:34+6]
,fmeif_partition_r[03:02] ,fmeif_partition_r[03+2:02+2] ,fmeif_partition_r[03+4:02+4] ,fmeif_partition_r[03+6:02+6]
,fmeif_partition_r[01:00]
};
assign fimeif_mv_data_w = sel_r ? fimeif_mv_data_w_1 : fimeif_mv_data_w_0 ;
fme_top u_fme_top(
.clk ( clk ),
.rstn ( rst_n ),
.sysif_cmb_x_i ( fme_x ),
.sysif_cmb_y_i ( fme_y ),
.sysif_qp_i ( fme_qp ),
.sysif_start_i ( fme_start ),
.sysif_done_o ( fme_done ),
.fimeif_partition_i ( fimeif_partition_w ),
.fimeif_mv_rden_o ( fimeif_mv_rden_w ),
.fimeif_mv_rdaddr_o ( fimeif_mv_rdaddr_w ),
.fimeif_mv_data_i ( fimeif_mv_data_w ),
.cur_rden_o ( fme_cur_ren_o ),
.cur_4x4_idx_o ( fme_cur_idx_o ),
.cur_4x4_x_o ( fme_cur_4x4_x_o ),
.cur_4x4_y_o ( fme_cur_4x4_y_o ),
.cur_pel_i ( fme_cur_data_i ),
.ref_rden_o ( fme_ref_ren_o ),
.ref_idx_x_o ( fme_ref_x_o ),
.ref_idx_y_o ( fme_ref_y_o ),
.ref_pel_i ( fme_ref_data_i ),
.mcif_mv_rden_o ( mcif_mv_rden_w ),
.mcif_mv_rdaddr_o ( mcif_mv_rdaddr_w ),
.mcif_mv_data_i ( mcif_mv_rddata_w ),
.mcif_mv_wren_o ( mcif_mv_wren_w ),
.mcif_mv_wraddr_o ( mcif_mv_wraddr_w ),
.mcif_mv_data_o ( mcif_mv_wrdata_w ),
.mcif_pre_pixel_o ( mcif_pre_pixel_w ),
.mcif_pre_wren_o ( mcif_pre_wren_w ),
.mcif_pre_addr_o ( mcif_pre_addr_w )
);
// rec_mem
assign fme_rec_mem_0_wen_i = ( sel_r) ? mcif_pre_wren_w : mc_pre_wren_w ;
assign fme_rec_mem_0_addr_i = ( sel_r) ? {1'b0,mcif_pre_addr_w} : {1'b0,mc_pre_wraddr_w} ;
assign fme_rec_mem_0_wdata_i = ( sel_r) ? mcif_pre_pixel_w : mc_pre_wrdata_w ;
assign fme_rec_mem_1_wen_i = (!sel_r) ? mcif_pre_wren_w : mc_pre_wren_w ;
assign fme_rec_mem_1_addr_i = (!sel_r) ? {1'b0,mcif_pre_addr_w} : {1'b0,mc_pre_wraddr_w} ;
assign fme_rec_mem_1_wdata_i = (!sel_r) ? mcif_pre_pixel_w : mc_pre_wrdata_w ;
mem_lipo_1p_bw fme_rec_mem_0 (
.clk ( clk ),
.rst_n ( rst_n ),
.a_wen_i ( fme_rec_mem_0_wen_i ),
.a_addr_i ( fme_rec_mem_0_addr_i ),
.a_wdata_i ( fme_rec_mem_0_wdata_i ),
.b_ren_i ( mc_pred_ren_w ),
.b_sel_i ( 1'b0 ),
.b_size_i ( mc_pred_size_w ),
.b_4x4_x_i ( mc_pred_4x4_x_w ),
.b_4x4_y_i ( mc_pred_4x4_y_w ),
.b_idx_i ( mc_pred_4x4_idx_w ),
.b_rdata_o ( mc_pred_rdata_0_w )
);
mem_lipo_1p_bw fme_rec_mem_1 (
.clk ( clk ),
.rst_n ( rst_n ),
.a_wen_i ( fme_rec_mem_1_wen_i ),
.a_addr_i ( fme_rec_mem_1_addr_i ),
.a_wdata_i ( fme_rec_mem_1_wdata_i ),
.b_ren_i ( mc_pred_ren_w ),
.b_sel_i ( 1'b0 ),
.b_size_i ( mc_pred_size_w ),
.b_4x4_x_i ( mc_pred_4x4_x_w ),
.b_4x4_y_i ( mc_pred_4x4_y_w ),
.b_idx_i ( mc_pred_4x4_idx_w ),
.b_rdata_o ( mc_pred_rdata_1_w )
);
// mv_mem
always @(*) begin
fme_mv_mem_0_rdaddr_w = 0 ;
fme_mv_mem_0_wren_w = 0 ;
fme_mv_mem_0_wraddr_w = 0 ;
fme_mv_mem_0_wrdata_w = 0 ;
case( sel_mod_3_r )
0 : begin fme_mv_mem_0_rdaddr_w = mcif_mv_rdaddr_w ;
fme_mv_mem_0_wren_w = mcif_mv_wren_w ;
fme_mv_mem_0_wraddr_w = mcif_mv_wraddr_w ;
fme_mv_mem_0_wrdata_w = mcif_mv_wrdata_w ;
end
1 : begin fme_mv_mem_0_rdaddr_w = mc_mv_rdaddr_w ;
end
2 : begin fme_mv_mem_0_rdaddr_w = db_mv_rdaddr_w ;
end
endcase
end
always @(*) begin
fme_mv_mem_1_rdaddr_w = 0 ;
fme_mv_mem_1_wren_w = 0 ;
fme_mv_mem_1_wraddr_w = 0 ;
fme_mv_mem_1_wrdata_w = 0 ;
case( sel_mod_3_r )
1 : begin fme_mv_mem_1_rdaddr_w = mcif_mv_rdaddr_w ;
fme_mv_mem_1_wren_w = mcif_mv_wren_w ;
fme_mv_mem_1_wraddr_w = mcif_mv_wraddr_w ;
fme_mv_mem_1_wrdata_w = mcif_mv_wrdata_w ;
end
2 : begin fme_mv_mem_1_rdaddr_w = mc_mv_rdaddr_w ;
end
0 : begin fme_mv_mem_1_rdaddr_w = db_mv_rdaddr_w ;
end
endcase
end
always @(*) begin
fme_mv_mem_2_rdaddr_w = 0 ;
fme_mv_mem_2_wren_w = 0 ;
fme_mv_mem_2_wraddr_w = 0 ;
fme_mv_mem_2_wrdata_w = 0 ;
case( sel_mod_3_r )
2 : begin fme_mv_mem_2_rdaddr_w = mcif_mv_rdaddr_w ;
fme_mv_mem_2_wren_w = mcif_mv_wren_w ;
fme_mv_mem_2_wraddr_w = mcif_mv_wraddr_w ;
fme_mv_mem_2_wrdata_w = mcif_mv_wrdata_w ;
end
0 : begin fme_mv_mem_2_rdaddr_w = mc_mv_rdaddr_w ;
end
1 : begin fme_mv_mem_2_rdaddr_w = db_mv_rdaddr_w ;
end
endcase
end
always @(*) begin
mcif_mv_rddata_w = 0 ;
case( sel_mod_3_r )
0 : mcif_mv_rddata_w = fme_mv_mem_0_rddata_w ;
1 : mcif_mv_rddata_w = fme_mv_mem_1_rddata_w ;
2 : mcif_mv_rddata_w = fme_mv_mem_2_rddata_w ;
endcase
end
rf_2p #(
.Word_Width ( 2*`FMV_WIDTH ),
.Addr_Width ( 6 )
) fme_mv_mem_0 (
.clka ( clk ),
.cena_i ( 1'b0 ),
.addra_i ( fme_mv_mem_0_rdaddr_w ),
.dataa_o ( fme_mv_mem_0_rddata_w ),
.clkb ( clk ),
.cenb_i ( 1'b0 ),
.wenb_i ( !fme_mv_mem_0_wren_w ),
.addrb_i ( fme_mv_mem_0_wraddr_w ),
.datab_i ( fme_mv_mem_0_wrdata_w )
);
rf_2p #(
.Word_Width ( 2*`FMV_WIDTH ),
.Addr_Width ( 6 )
) fme_mv_mem_1 (
.clka ( clk ),
.cena_i ( 1'b0 ),
.addra_i ( fme_mv_mem_1_rdaddr_w ),
.dataa_o ( fme_mv_mem_1_rddata_w ),
.clkb ( clk ),
.cenb_i ( 1'b0 ),
.wenb_i ( !fme_mv_mem_1_wren_w ),
.addrb_i ( fme_mv_mem_1_wraddr_w ),
.datab_i ( fme_mv_mem_1_wrdata_w )
);
rf_2p #(
.Word_Width ( 2*`FMV_WIDTH ),
.Addr_Width ( 6 )
) fme_mv_mem_2 (
.clka ( clk ),
.cena_i ( 1'b0 ),
.addra_i ( fme_mv_mem_2_rdaddr_w ),
.dataa_o ( fme_mv_mem_2_rddata_w ),
.clkb ( clk ),
.cenb_i ( 1'b0 ),
.wenb_i ( !fme_mv_mem_2_wren_w ),
.addrb_i ( fme_mv_mem_2_wraddr_w ),
.datab_i ( fme_mv_mem_2_wrdata_w )
);
//-------------------------------------------------------------------
//
// MC Block
//
//-------------------------------------------------------------------
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
mc_partition_r <= 42'b0 ;
else if( sys_start_i ) begin
mc_partition_r <= fimeif_partition_w ;
end
end
always @(*) begin
mc_mv_w = 0 ;
case( sel_mod_3_r )
1 : mc_mv_w = fme_mv_mem_0_rddata_w ;
2 : mc_mv_w = fme_mv_mem_1_rddata_w ;
0 : mc_mv_w = fme_mv_mem_2_rddata_w ;
endcase
end
assign mc_pred_rdata_w = sel_r ? mc_pred_rdata_1_w : mc_pred_rdata_0_w ;
mc_top u_mc_top(
.clk ( clk ),
.rstn ( rst_n ),
.mb_x_total_i ( sys_x_total_i ),
.mb_y_total_i ( sys_y_total_i ),
.sysif_cmb_x_i ( mc_x ),
.sysif_cmb_y_i ( mc_y ),
.sysif_qp_i ( mc_qp ),
.sysif_start_i ( mc_start ),
.sysif_done_o ( mc_done ),
.fetchif_rden_o ( mc_ref_ren_o ),
.fetchif_idx_x_o ( mc_ref_x_o ),
.fetchif_idx_y_o ( mc_ref_y_o ),
.fetchif_sel_o ( mc_ref_sel_o ),
.fetchif_pel_i ( mc_ref_data_i ),
.fmeif_partition_i ( mc_partition_r ),
.fmeif_mv_i ( mc_mv_w ),
.fmeif_mv_rden_o ( mc_mv_rden_w ),
.fmeif_mv_rdaddr_o ( mc_mv_rdaddr_w ),
.pred_wrdata_o ( mc_pre_wrdata_w ),
.pred_wren_o ( mc_pre_wren_w ),
.pred_wraddr_o ( mc_pre_wraddr_w ),
.pred_ren_o ( mc_pred_ren_w ),
.pred_size_o ( mc_pred_size_w ),
.pred_4x4_x_o ( mc_pred_4x4_x_w ),
.pred_4x4_y_o ( mc_pred_4x4_y_w ),
.pred_4x4_idx_o ( mc_pred_4x4_idx_w ),
.pred_rdata_i ( mc_pred_rdata_w ),
.mvd_wen_o ( mc_mvd_wen_w ),
.mvd_waddr_o ( mc_mvd_waddr_w ),
.mvd_wdata_o ( mc_mvd_wdata_w ),
.pre_start_o ( ),
.pre_en_o ( mc_ppre_en ),
.pre_sel_o ( mc_ppre_sel ),
.pre_size_o ( mc_ppre_size ),
.pre_4x4_x_o ( mc_ppre_4x4_x ),
.pre_4x4_y_o ( mc_ppre_4x4_y ),
.pre_data_o ( mc_ppre_data ),
.rec_val_i ( rec_val & (sys_type_i==INTER) ),
.rec_idx_i ( rec_idx )
);
assign mc_mvd_mem_0_wren_w = sel_r ? mc_mvd_wen_w : 0 ;
assign mc_mvd_mem_0_wraddr_w = sel_r ? mc_mvd_waddr_w : 0 ;
assign mc_mvd_mem_0_wrdata_w = sel_r ? mc_mvd_wdata_w : 0 ;
assign mc_mvd_mem_1_wren_w = sel_r ? 0 : mc_mvd_wen_w ;
assign mc_mvd_mem_1_wraddr_w = sel_r ? 0 : mc_mvd_waddr_w ;
assign mc_mvd_mem_1_wrdata_w = sel_r ? 0 : mc_mvd_wdata_w ;
assign mc_mvd_mem_0_rdaddr_w = ec_mvd_raddr_w ;
assign mc_mvd_mem_1_rdaddr_w = ec_mvd_raddr_w ;
rf_2p #(
.Word_Width ( 2*(`MVD_WIDTH)+1 ),
.Addr_Width ( 6 )
) mc_mvd_mem_0 (
.clka ( clk ),
.cena_i ( 1'b0 ),
.addra_i ( mc_mvd_mem_0_rdaddr_w ),
.dataa_o ( mc_mvd_mem_0_rddata_w ),
.clkb ( clk ),
.cenb_i ( 1'b0 ),
.wenb_i (!mc_mvd_mem_0_wren_w ),
.addrb_i ( mc_mvd_mem_0_wraddr_w ),
.datab_i ( mc_mvd_mem_0_wrdata_w )
);
rf_2p #(
.Word_Width ( 2*(`MVD_WIDTH)+1 ),
.Addr_Width ( 6 )
) mc_mvd_mem_1 (
.clka ( clk ),
.cena_i ( 1'b0 ),
.addra_i ( mc_mvd_mem_1_rdaddr_w ),
.dataa_o ( mc_mvd_mem_1_rddata_w ),
.clkb ( clk ),
.cenb_i ( 1'b0 ),
.wenb_i (!mc_mvd_mem_1_wren_w ),
.addrb_i ( mc_mvd_mem_1_wraddr_w ),
.datab_i ( mc_mvd_mem_1_wrdata_w )
);
//-------------------------------------------------------------------
//
// MEM BUF Block
//
//-------------------------------------------------------------------
assign pre_bank = 'd0 ;
assign ec_bank = 'd0 ;
assign db_bank = 'd0 ;
assign pre_cbank = 'd0 ;
assign ec_cbank = 'd0 ;
assign db_cbank = 'd0 ;
assign ipre_en = ( sys_type_i==INTRA ) ? intra_ipre_en : mc_ppre_en ;
assign ipre_sel = ( sys_type_i==INTRA ) ? intra_ipre_sel : mc_ppre_sel ;
assign ipre_size = ( sys_type_i==INTRA ) ? intra_ipre_size : mc_ppre_size ;
assign ipre_4x4_x = ( sys_type_i==INTRA ) ? intra_ipre_4x4_x : mc_ppre_4x4_x ;
assign ipre_4x4_y = ( sys_type_i==INTRA ) ? intra_ipre_4x4_y : mc_ppre_4x4_y ;
assign ipre_data = ( sys_type_i==INTRA ) ? intra_ipre_data : mc_ppre_data ;
assign ipre_mode = ( sys_type_i==INTRA ) ? intra_ipre_mode : mc_ppre_mode ;
mem_buf u_mem_buf (
.clk ( clk ),
.rst_n ( rst_n ),
.pre_start_i ( sys_start_i ),
.pre_type_i ( sys_type_i ),
.pre_bank_i ( pre_bank ),
.ec_bank_i ( ec_bank ),
.db_bank_i ( db_bank ),
.pre_cbank_i ( pre_cbank ),
.ec_cbank_i ( ec_cbank ),
.db_cbank_i ( db_cbank ),
.cmb_sel_o ( intra_cur_sel_o ),
.cmb_ren_o ( intra_cur_ren_o ),
.cmb_size_o ( intra_cur_size_o ),
.cmb_4x4_x_o ( intra_cur_4x4_x_o ),
.cmb_4x4_y_o ( intra_cur_4x4_y_o ),
.cmb_idx_o ( intra_cur_idx_o ),
.cmb_data_i ( intra_cur_data_i ),
.ipre_min_size_i ( pre_min_size_i ),
.ipre_en_i ( ipre_en ),
.ipre_sel_i ( ipre_sel ),
.ipre_size_i ( ipre_size ),
.ipre_4x4_x_i ( ipre_4x4_x ),
.ipre_4x4_y_i ( ipre_4x4_y ),
.ipre_data_i ( ipre_data ),
.ipre_mode_i ( ipre_mode ),
.ipre_qp_i ( intra_qp ),
.tq_res_en_o ( tq_res_en ),
.tq_res_sel_o ( tq_res_sel ),
.tq_res_size_o ( tq_res_size ),
.tq_res_idx_o ( tq_res_idx ),
.tq_res_data_o ( tq_res_data ),
.tq_rec_val_i ( tq_rec_val ),
.tq_rec_idx_i ( tq_rec_idx ),
.tq_rec_data_i ( tq_rec_data ),
.tq_cef_en_i ( tq_cef_en ),
.tq_cef_rw_i ( tq_cef_rw ),
.tq_cef_idx_i ( tq_cef_idx ),
.tq_cef_data_i ( tq_cef_wdata ),
.tq_cef_data_o ( tq_cef_rdata ),
.rec_val_o ( rec_val ),
.rec_idx_o ( rec_idx ),
.rec_data_o ( rec_data ),
.cover_valid_o ( cover_valid ),
.cover_value_o ( cover_value ),
.db_mem_ren_i ( 1'b1 ), // !!!
.db_mem_raddr_i ( db_mem_raddr ),
.db_mem_rdata_o ( db_mem_rdata ),
.ec_mem_ren_i ( 1'b1 ), // !!!
.ec_mem_sel_i ( ec_mem_sel ),
.ec_mem_raddr_i ( ec_mem_raddr ),
.ec_mem_rdata_o ( ec_mem_rdata ),
.ec_cbf_luma_o ( ec_cbf_luma ),
.ec_cbf_cb_o ( ec_cbf_cb ),
.ec_cbf_cr_o ( ec_cbf_cr ),
.partition_old_o ( partition_old ),
.partition_cur_o ( partition_cur ),
.lm_md_renab_i ( lm_md_renab ),
.lm_md_raddr_i ( lm_md_raddr ),
.lm_md_rdata_o ( lm_md_rdata ),
.cm_md_renab_i ( cm_md_renab ),
.cm_md_raddr_i ( cm_md_raddr ),
.cm_md_rdata_o ( cm_md_rdata )
);
//-------------------------------------------------------------------
//
// Mode Decision
//
//-------------------------------------------------------------------
md u_md (
.clk ( clk ),
.rst_n ( rst_n ),
.ipre_bank_o ( pre_bank ),
.ec_bank_o ( ec_bank ),
.db_bank_o ( db_bank ),
.cef_wen_i ( tq_cef_wen ),
.cef_widx_i ( tq_cef_widx ),
.cef_data_i ( tq_cef_wdata ),
.ec_mb_type_o ( ec_mb_type ),
.ec_mb_partition_o ( ec_mb_partition ),
.ec_i_mode_o ( ec_i_mode ),
.ec_p_mode_o ( ec_p_mode ),
.db_non_zero_count_o ( db_non_zero_count )
);
//-------------------------------------------------------------------
//
// TQ Block
//
//-------------------------------------------------------------------
assign tq_qp = ( sys_type_i==INTRA ) ? intra_qp : mc_qp ;
assign tq_cef_en = tq_cef_ren | tq_cef_wen ;
assign tq_cef_rw = tq_cef_wen ? 1'b1: 1'b0 ;
assign tq_cef_idx = tq_cef_wen ? tq_cef_widx : tq_cef_ridx ;
reg [5 : 0] tq_qp_c ;
wire [5 : 0] tq_qp_w ;
always @(*) begin
tq_qp_c = tq_qp ;
if( tq_qp>43 )
tq_qp_c = tq_qp-6 ;
else if( tq_qp<30 )
tq_qp_c = tq_qp ;
else begin
case( tq_qp )
30 : tq_qp_c = 6'd29 ;
31 : tq_qp_c = 6'd30 ;
32 : tq_qp_c = 6'd31 ;
33 : tq_qp_c = 6'd32 ;
34 : tq_qp_c = 6'd33 ;
35 : tq_qp_c = 6'd33 ;
36 : tq_qp_c = 6'd34 ;
37 : tq_qp_c = 6'd34 ;
38 : tq_qp_c = 6'd35 ;
39 : tq_qp_c = 6'd35 ;
40 : tq_qp_c = 6'd36 ;
41 : tq_qp_c = 6'd36 ;
42 : tq_qp_c = 6'd37 ;
43 : tq_qp_c = 6'd37 ;
default : tq_qp_c = 6'hxx ;
endcase
end
end
assign tq_qp_w = ( tq_res_sel==2'b00 ) ? tq_qp : tq_qp_c ; // still missing inter one
tq_top u_tq_top(
.clk ( clk ),
.rst ( rst_n ),
.type_i ( sys_type_i ),
.qp_i ( tq_qp_w ),
.tq_en_i ( tq_res_en ),
.tq_sel_i ( tq_res_sel ),
.tq_size_i ( tq_res_size ),
.tq_idx_i ( tq_res_idx ),
.tq_res_i ( tq_res_data ),
.rec_val_o ( tq_rec_val ),
.rec_idx_o ( tq_rec_idx ),
.rec_data_o ( tq_rec_data ),
.cef_ren_o ( tq_cef_ren ),
.cef_ridx_o ( tq_cef_ridx ),
.cef_data_i ( tq_cef_rdata ),
.cef_wen_o ( tq_cef_wen ),
.cef_widx_o ( tq_cef_widx ),
.cef_data_o ( tq_cef_wdata )
);
//-------------------------------------------------------------------
//
// entropy coding module
//
//-------------------------------------------------------------------
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
ec_partition_r <= 42'b0 ;
else if( sys_start_i ) begin
ec_partition_r <= mc_partition_r ;
end
end
assign ec_mvd_rdata_w = sel_r ? mc_mvd_mem_1_rddata_w : mc_mvd_mem_0_rddata_w ;
cabac_top u_cabac_top(
.clk ( clk ),
.rst_n ( rst_n ),
.mb_x_total_i ( sys_x_total_i ),
.mb_y_total_i ( sys_y_total_i ),
.mb_x_i ( ec_x ),
.mb_y_i ( ec_y ),
.mb_type_i ( (sys_type_i==INTRA) ),
.sao_i ( 62'b0 ),
.qp_i ( ec_qp ),
.param_qp_i ( (sys_type_i==INTRA) ? (ec_qp) : (ec_qp+5'd3) ),
.start_i ( ec_start ),
.done_o ( ec_done ),
.slice_done_o ( ec_slice_done ),
.tq_ren_o ( ec_mem_ren ),
.coeff_type_o ( ec_mem_sel ),
.tq_raddr_o ( ec_mem_raddr ),
.tq_rdata_i ( ec_mem_rdata ),
.tq_cbf_luma_i ( ec_cbf_luma ),
.tq_cbf_cb_i ( ec_cbf_cb ),
.tq_cbf_cr_i ( ec_cbf_cr ),
.mb_partition_i ( {64'b0 ,partition_old } ),
.cu_luma_mode_ren_o ( lm_md_renab ),
.cu_luma_mode_raddr_o ( lm_md_raddr ),
.luma_mode_i ( lm_md_rdata ),
.cu_chroma_mode_ren_o ( cm_md_renab ),
.cu_chroma_mode_raddr_o ( cm_md_raddr ),
.chroma_mode_i ( 24'h924924 ),
.merge_flag_i ( 85'd0 ),
.merge_idx_i ( 256'd0 ),
.cu_skip_flag_i ( 85'd0 ),
.mb_p_pu_mode_i ( {{(170-42){1'b0}},ec_partition_r} ),
.mb_mvd_ren_o ( ec_mvd_ren_w ),
.mb_mvd_raddr_o ( ec_mvd_raddr_w ),
.mb_mvd_rdata_i ( ec_mvd_rdata_w ),
.bs_val_o ( winc_o ),
.bs_data_o ( wdata_o ),
.bs_wait_i ( 1'd1 )
);
//-------------------------------------------------------------------
//
// deblocking module
//
//-------------------------------------------------------------------
reg [2*`FMV_WIDTH-1 : 0] mb_mv_rdata ;
reg [128-1 : 0] tq_ori_data ;
always @(posedge clk or negedge rst_n ) begin
if( !rst_n )
db_inter_partition_r <= 42'b0 ;
else if( sys_start_i ) begin
db_inter_partition_r <= mc_partition_r ;
end
end
assign db_intra_partition_w = (sys_type_i==INTRA) ? partition_old
: { db_inter_partition_r[41]&db_inter_partition_r[40]
,db_inter_partition_r[39]&db_inter_partition_r[38]
,db_inter_partition_r[37]&db_inter_partition_r[36]
,db_inter_partition_r[35]&db_inter_partition_r[34]
,db_inter_partition_r[33]&db_inter_partition_r[32]
,db_inter_partition_r[31]&db_inter_partition_r[30]
,db_inter_partition_r[29]&db_inter_partition_r[28]
,db_inter_partition_r[27]&db_inter_partition_r[26]
,db_inter_partition_r[25]&db_inter_partition_r[24]
,db_inter_partition_r[23]&db_inter_partition_r[22]
,db_inter_partition_r[21]&db_inter_partition_r[20]
,db_inter_partition_r[19]&db_inter_partition_r[18]
,db_inter_partition_r[17]&db_inter_partition_r[16]
,db_inter_partition_r[15]&db_inter_partition_r[14]
,db_inter_partition_r[13]&db_inter_partition_r[12]
,db_inter_partition_r[11]&db_inter_partition_r[10]
,db_inter_partition_r[09]&db_inter_partition_r[08]
,db_inter_partition_r[07]&db_inter_partition_r[06]
,db_inter_partition_r[05]&db_inter_partition_r[04]
,db_inter_partition_r[03]&db_inter_partition_r[02]
,db_inter_partition_r[01]&db_inter_partition_r[00]
};
always @(*) begin
db_mv_w = 0 ;
case( sel_mod_3_r )
2 : db_mv_w = { fme_mv_mem_0_rddata_w[9:0] ,fme_mv_mem_0_rddata_w[19:10] };
0 : db_mv_w = { fme_mv_mem_1_rddata_w[9:0] ,fme_mv_mem_1_rddata_w[19:10] };
1 : db_mv_w = { fme_mv_mem_2_rddata_w[9:0] ,fme_mv_mem_2_rddata_w[19:10] };
endcase
end
assign db_mv_rdaddr_w = { db_mv_rdaddr_ori_w[5]
,db_mv_rdaddr_ori_w[3]
,db_mv_rdaddr_ori_w[1]
,db_mv_rdaddr_ori_w[4]
,db_mv_rdaddr_ori_w[2]
,db_mv_rdaddr_ori_w[0]
};
db_top u_db_top(
.clk ( clk ),
.rst_n ( rst_n ),
.mb_x_total_i ( sys_x_total_i ),
.mb_y_total_i ( sys_y_total_i ),
.mb_x_i ( ec_x ),
.mb_y_i ( ec_y ),
.qp_i ( ec_qp ),
.start_i ( ec_start ),
.done_o ( db_done ),
.mb_type_i ( sys_type_i==INTRA ),
.mb_partition_i ( db_intra_partition_w ),
.mb_p_pu_mode_i ( db_inter_partition_r ),
.mb_cbf_i ( ec_cbf_luma ),
.mb_cbf_u_i ( (sys_type_i==INTRA) ? ec_cbf_cb : ec_cbf_cr ),
.mb_cbf_v_i ( (sys_type_i==INTRA) ? ec_cbf_cr : ec_cbf_cb ),
.mb_mv_ren_o ( db_mv_rden_w ),
.mb_mv_raddr_o ( db_mv_rdaddr_ori_w ),
.mb_mv_rdata_i ( db_mv_w ),
.tq_ren_o ( db_mem_ren ),
.tq_raddr_o ( db_mem_raddr ),
.tq_rdata_i ( db_mem_rdata ),
.tq_ori_data_i ( tq_ori_data ), // fake (for sao)
.db_wen_o ( db_wen_o ),
.db_w4x4_x_o ( db_w4x4_x_o ),
.db_w4x4_y_o ( db_w4x4_y_o ),
.db_wprevious_o ( db_wprevious_o ),
.db_wdone_o ( db_wdone_o ),
.db_wsel_o ( db_wsel_o ),
.db_wdata_o ( db_wdata_o ),
.mb_db_ren_o ( db_ren_o ),
.mb_db_r4x4_o ( db_r4x4_o ),
.mb_db_ridx_o ( db_ridx_o ),
.mb_db_en_o ( db_mb_en ), // for db auto check
.mb_db_rw_o ( db_mb_rw ), // for db auto check
.mb_db_addr_o ( db_mb_addr ), // for db auto check
.mb_db_data_o ( db_mb_data_o ), // for db auto check
`ifdef NO_FETCH
.mb_db_data_i ( db_rdata ) // fake
`else
.mb_db_data_i ( db_rdata_i )
`endif
);
assign db_done_o = db_done ;
//*** FOR DEBUG ****************************************************************
/*
reg [`PIC_X_WIDTH-1 : 0] db_x_total_r ;
reg [`PIC_Y_WIDTH-1 : 0] db_y_total_r ;
reg [`PIC_X_WIDTH-1 : 0] db_x_r ;
reg [`PIC_Y_WIDTH-1 : 0] db_y_r ;
reg [6-1 : 0] db_qp_r ;
reg [21-1 : 0] db_mb_partition_r ;
reg [42-1 : 0] mb_p_pu_mode_r ;
reg [256-1 : 0] mb_cbf_r ;
reg [16-1 : 0] mb_cbf_top_r ;
reg [256-1 : 0] mb_cbf_u_r ;
reg [256-1 : 0] mb_cbf_v_r ;
reg [128-1 : 0] yuv_top[0:31] ;
reg [128-1 : 0] yuv_in[0:383] ;
reg [128-1 : 0] yuv_out[0:383] ;
reg [128-1 : 0] yuv_check[0:383] ;
reg [4*32-1 : 0] tq_rdata ;
integer f ,i, tp ;
integer fp_i_input ;
integer fp_i_check ;
integer fp_p_input ;
integer fp_p_check ;
reg [8 : 0] in ;
reg [8 : 0] index ;
reg [19 : 0] mv[0:71] ;
reg [19 : 0] mv_dat ;
reg [128-1 : 0] pixels ;
// configure db_top
initial begin
fp_i_input = $fopen( "./tv/db_i_check_i.dat" ,"r" );
fp_i_check = $fopen( "./tv/db_i_check_o.dat" ,"r" );
fp_p_input = $fopen( "./tv/db_p_check_i.dat" ,"r" );
fp_p_check = $fopen( "./tv/db_p_check_o.dat" ,"r" );
db_qp_r = 6'h16 ;
db_mb_partition_r = 21'd0 ;
mb_p_pu_mode_r = 42'd0 ;
mb_cbf_r = 256'd0 ;
mb_cbf_top_r = 16'd0 ;
mb_cbf_u_r = 256'd0 ;
mb_cbf_v_r = 256'd0 ;
forever begin
@(posedge ec_start)
db_start_task ;
`ifdef DB_AUTO_CHECK
check_task ;
`endif
end
end
// read top reference
always @(posedge clk) begin
db_rdata <= db_ren_o ? 'dx : yuv_top[db_r4x4_o] ;
end
// read current rec
always @(posedge clk) begin
tq_rdata <= db_mem_ren ? 'dx : yuv_in[db_mem_raddr];
end
// read mv data
always @(posedge clk) begin
mb_mv_rdata <= db_mv_rden_w ? 'dx : mv[db_mv_rdaddr_ori_w];
end
// dump data
always @(posedge clk) begin
if(!db_mb_en&&db_mb_rw)begin
yuv_out[db_mb_addr] <= db_mb_data_o ;
end
end
// db_start_task
task db_start_task ;
begin
if( sys_type_i == INTRA ) begin
f = $fscanf( fp_i_input ,"%h" ,db_x_total_r );
f = $fscanf( fp_i_input ,"%h" ,db_y_total_r );
f = $fscanf( fp_i_input ,"%h" ,db_x_r );
f = $fscanf( fp_i_input ,"%h" ,db_y_r );
f = $fscanf( fp_i_input ,"%h" ,db_qp_r );
f = $fscanf( fp_i_input ,"%b" ,tp );
f = $fscanf( fp_i_input ,"%b" ,db_mb_partition_r );
f = $fscanf( fp_i_input ,"%b" ,mb_p_pu_mode_r );
f = $fscanf( fp_i_input ,"%b" ,mb_cbf_r );
f = $fscanf( fp_i_input ,"%b" ,mb_cbf_top_r );
f = $fscanf( fp_i_input ,"%b" ,mb_cbf_u_r );
f = $fscanf( fp_i_input ,"%b" ,mb_cbf_v_r );
end
else begin
f = $fscanf( fp_p_input ,"%h" ,db_x_total_r );
f = $fscanf( fp_p_input ,"%h" ,db_y_total_r );
f = $fscanf( fp_p_input ,"%h" ,db_x_r );
f = $fscanf( fp_p_input ,"%h" ,db_y_r );
f = $fscanf( fp_p_input ,"%h" ,db_qp_r );
f = $fscanf( fp_p_input ,"%b" ,tp );
f = $fscanf( fp_p_input ,"%b" ,db_mb_partition_r );
f = $fscanf( fp_p_input ,"%b" ,mb_p_pu_mode_r );
f = $fscanf( fp_p_input ,"%b" ,mb_cbf_r );
f = $fscanf( fp_p_input ,"%b" ,mb_cbf_top_r );
f = $fscanf( fp_p_input ,"%b" ,mb_cbf_u_r );
f = $fscanf( fp_p_input ,"%b" ,mb_cbf_v_r );
end
// current lcu mv
for ( i=0 ;i<64 ;i=i+1 ) begin
in = i ;
index = getmvindex( in[5:0] );
if( sys_type_i == INTRA )
f = $fscanf( fp_i_input ,"%h" ,mv_dat );
else begin
f = $fscanf( fp_p_input ,"%h" ,mv_dat );
end
mv[index[5:0]] = mv_dat ;
end
// top lcu mv
for ( i=0 ;i<8 ;i=i+1 ) begin
if( sys_type_i == INTRA )
f = $fscanf( fp_i_input ,"%h" ,mv_dat );
else begin
f = $fscanf( fp_p_input ,"%h" ,mv_dat );
end
mv[i+64] = mv_dat ;
end
// current lcu pixels
for( i=0 ;i<384 ;i=i+1 ) begin
in = i ;
index = getindex( in );
if( sys_type_i == INTRA )
f = $fscanf( fp_i_input ,"%h" ,pixels );
else begin
f = $fscanf( fp_p_input ,"%h" ,pixels );
end
yuv_in[index] = pixels ;
end
// top lcu pixels
for( i=0 ;i<32 ;i=i+1 ) begin
if( sys_type_i == INTRA )
f = $fscanf( fp_i_input ,"%h" ,pixels );
else begin
f = $fscanf( fp_p_input ,"%h" ,pixels );
end
yuv_top[i] = pixels ;
end
// wait for done
@(posedge db_done );
end
endtask
// check task
task check_task;
begin
for( i=0 ;i<384 ;i=i+1 ) begin
in = i ;
index = getindex( in );
if( sys_type_i == INTRA )
f = $fscanf( fp_i_check ,"%h" ,pixels );
else begin
f = $fscanf( fp_p_check ,"%h" ,pixels );
end
yuv_check[i] = pixels;
end
for( i=0 ;i<384 ;i=i+1 ) begin
in = i ;
index = getindex( in );
pixels = yuv_out[index];
if( (yuv_out[index]!==yuv_check[i]) && (i<256||(i>255 && i%8!=7)) ) begin
$display( "DB Error : %5d" ,i );
$display( "right: %h\nwrong: %h" ,yuv_check[index] ,yuv_out[i] );
#1000 ; $finish ;
end
end
end
endtask
// getindex
function [8:0] getindex ;
input [8:0] in ;
begin
if( in<256 ) begin
case( in[6:0] )
'd0 : getindex[6:0] = 'd0 ;
'd1 : getindex[6:0] = 'd1 ;
'd2 : getindex[6:0] = 'd4 ;
'd3 : getindex[6:0] = 'd5 ;
'd4 : getindex[6:0] = 'd16 ;
'd5 : getindex[6:0] = 'd17 ;
'd6 : getindex[6:0] = 'd20 ;
'd7 : getindex[6:0] = 'd21 ;
'd8 : getindex[6:0] = 'd64 ;
'd9 : getindex[6:0] = 'd65 ;
'd10 : getindex[6:0] = 'd68 ;
'd11 : getindex[6:0] = 'd69 ;
'd12 : getindex[6:0] = 'd80 ;
'd13 : getindex[6:0] = 'd81 ;
'd14 : getindex[6:0] = 'd84 ;
'd15 : getindex[6:0] = 'd85 ;
'd16 : getindex[6:0] = 'd2 ;
'd17 : getindex[6:0] = 'd3 ;
'd18 : getindex[6:0] = 'd6 ;
'd19 : getindex[6:0] = 'd7 ;
'd20 : getindex[6:0] = 'd18 ;
'd21 : getindex[6:0] = 'd19 ;
'd22 : getindex[6:0] = 'd22 ;
'd23 : getindex[6:0] = 'd23 ;
'd24 : getindex[6:0] = 'd66 ;
'd25 : getindex[6:0] = 'd67 ;
'd26 : getindex[6:0] = 'd70 ;
'd27 : getindex[6:0] = 'd71 ;
'd28 : getindex[6:0] = 'd82 ;
'd29 : getindex[6:0] = 'd83 ;
'd30 : getindex[6:0] = 'd86 ;
'd31 : getindex[6:0] = 'd87 ;
'd32 : getindex[6:0] = 'd8 ;
'd33 : getindex[6:0] = 'd9 ;
'd34 : getindex[6:0] = 'd12 ;
'd35 : getindex[6:0] = 'd13 ;
'd36 : getindex[6:0] = 'd24 ;
'd37 : getindex[6:0] = 'd25 ;
'd38 : getindex[6:0] = 'd28 ;
'd39 : getindex[6:0] = 'd29 ;
'd40 : getindex[6:0] = 'd72 ;
'd41 : getindex[6:0] = 'd73 ;
'd42 : getindex[6:0] = 'd76 ;
'd43 : getindex[6:0] = 'd77 ;
'd44 : getindex[6:0] = 'd88 ;
'd45 : getindex[6:0] = 'd89 ;
'd46 : getindex[6:0] = 'd92 ;
'd47 : getindex[6:0] = 'd93 ;
'd48 : getindex[6:0] = 'd10 ;
'd49 : getindex[6:0] = 'd11 ;
'd50 : getindex[6:0] = 'd14 ;
'd51 : getindex[6:0] = 'd15 ;
'd52 : getindex[6:0] = 'd26 ;
'd53 : getindex[6:0] = 'd27 ;
'd54 : getindex[6:0] = 'd30 ;
'd55 : getindex[6:0] = 'd31 ;
'd56 : getindex[6:0] = 'd74 ;
'd57 : getindex[6:0] = 'd75 ;
'd58 : getindex[6:0] = 'd78 ;
'd59 : getindex[6:0] = 'd79 ;
'd60 : getindex[6:0] = 'd90 ;
'd61 : getindex[6:0] = 'd91 ;
'd62 : getindex[6:0] = 'd94 ;
'd63 : getindex[6:0] = 'd95 ;
'd64 : getindex[6:0] = 'd32 ;
'd65 : getindex[6:0] = 'd33 ;
'd66 : getindex[6:0] = 'd36 ;
'd67 : getindex[6:0] = 'd37 ;
'd68 : getindex[6:0] = 'd48 ;
'd69 : getindex[6:0] = 'd49 ;
'd70 : getindex[6:0] = 'd52 ;
'd71 : getindex[6:0] = 'd53 ;
'd72 : getindex[6:0] = 'd96 ;
'd73 : getindex[6:0] = 'd97 ;
'd74 : getindex[6:0] = 'd100 ;
'd75 : getindex[6:0] = 'd101 ;
'd76 : getindex[6:0] = 'd112 ;
'd77 : getindex[6:0] = 'd113 ;
'd78 : getindex[6:0] = 'd116 ;
'd79 : getindex[6:0] = 'd117 ;
'd80 : getindex[6:0] = 'd34 ;
'd81 : getindex[6:0] = 'd35 ;
'd82 : getindex[6:0] = 'd38 ;
'd83 : getindex[6:0] = 'd39 ;
'd84 : getindex[6:0] = 'd50 ;
'd85 : getindex[6:0] = 'd51 ;
'd86 : getindex[6:0] = 'd54 ;
'd87 : getindex[6:0] = 'd55 ;
'd88 : getindex[6:0] = 'd98 ;
'd89 : getindex[6:0] = 'd99 ;
'd90 : getindex[6:0] = 'd102 ;
'd91 : getindex[6:0] = 'd103 ;
'd92 : getindex[6:0] = 'd114 ;
'd93 : getindex[6:0] = 'd115 ;
'd94 : getindex[6:0] = 'd118 ;
'd95 : getindex[6:0] = 'd119 ;
'd96 : getindex[6:0] = 'd40 ;
'd97 : getindex[6:0] = 'd41 ;
'd98 : getindex[6:0] = 'd44 ;
'd99 : getindex[6:0] = 'd45 ;
'd100 : getindex[6:0] = 'd56 ;
'd101 : getindex[6:0] = 'd57 ;
'd102 : getindex[6:0] = 'd60 ;
'd103 : getindex[6:0] = 'd61 ;
'd104 : getindex[6:0] = 'd104 ;
'd105 : getindex[6:0] = 'd105 ;
'd106 : getindex[6:0] = 'd108 ;
'd107 : getindex[6:0] = 'd109 ;
'd108 : getindex[6:0] = 'd120 ;
'd109 : getindex[6:0] = 'd121 ;
'd110 : getindex[6:0] = 'd124 ;
'd111 : getindex[6:0] = 'd125 ;
'd112 : getindex[6:0] = 'd42 ;
'd113 : getindex[6:0] = 'd43 ;
'd114 : getindex[6:0] = 'd46 ;
'd115 : getindex[6:0] = 'd47 ;
'd116 : getindex[6:0] = 'd58 ;
'd117 : getindex[6:0] = 'd59 ;
'd118 : getindex[6:0] = 'd62 ;
'd119 : getindex[6:0] = 'd63 ;
'd120 : getindex[6:0] = 'd106 ;
'd121 : getindex[6:0] = 'd107 ;
'd122 : getindex[6:0] = 'd110 ;
'd123 : getindex[6:0] = 'd111 ;
'd124 : getindex[6:0] = 'd122 ;
'd125 : getindex[6:0] = 'd123 ;
'd126 : getindex[6:0] = 'd126 ;
'd127 : getindex[6:0] = 'd127 ;
default : getindex[6:0] = 'd0 ;
endcase
getindex[8:7] = in[8:7] ;
end
else begin
case( in[5:0] )
'd0 : getindex[5:0] = 'd0 + 00 ;
'd1 : getindex[5:0] = 'd1 + 00 ;
'd2 : getindex[5:0] = 'd4 + 00 ;
'd3 : getindex[5:0] = 'd5 + 00 ;
'd4 : getindex[5:0] = 'd16 + 00 ;
'd5 : getindex[5:0] = 'd17 + 00 ;
'd6 : getindex[5:0] = 'd20 + 00 ;
'd7 : getindex[5:0] = 'd21 + 00 ;
'd8 : getindex[5:0] = 'd0 + 02 ;
'd9 : getindex[5:0] = 'd1 + 02 ;
'd10 : getindex[5:0] = 'd4 + 02 ;
'd11 : getindex[5:0] = 'd5 + 02 ;
'd12 : getindex[5:0] = 'd16 + 02 ;
'd13 : getindex[5:0] = 'd17 + 02 ;
'd14 : getindex[5:0] = 'd20 + 02 ;
'd15 : getindex[5:0] = 'd21 + 02 ;
'd16 : getindex[5:0] = 'd0 + 08 ;
'd17 : getindex[5:0] = 'd1 + 08 ;
'd18 : getindex[5:0] = 'd4 + 08 ;
'd19 : getindex[5:0] = 'd5 + 08 ;
'd20 : getindex[5:0] = 'd16 + 08 ;
'd21 : getindex[5:0] = 'd17 + 08 ;
'd22 : getindex[5:0] = 'd20 + 08 ;
'd23 : getindex[5:0] = 'd21 + 08 ;
'd24 : getindex[5:0] = 'd0 + 10 ;
'd25 : getindex[5:0] = 'd1 + 10 ;
'd26 : getindex[5:0] = 'd4 + 10 ;
'd27 : getindex[5:0] = 'd5 + 10 ;
'd28 : getindex[5:0] = 'd16 + 10 ;
'd29 : getindex[5:0] = 'd17 + 10 ;
'd30 : getindex[5:0] = 'd20 + 10 ;
'd31 : getindex[5:0] = 'd21 + 10 ;
'd32 : getindex[5:0] = 'd0 + 32 ;
'd33 : getindex[5:0] = 'd1 + 32 ;
'd34 : getindex[5:0] = 'd4 + 32 ;
'd35 : getindex[5:0] = 'd5 + 32 ;
'd36 : getindex[5:0] = 'd16 + 32 ;
'd37 : getindex[5:0] = 'd17 + 32 ;
'd38 : getindex[5:0] = 'd20 + 32 ;
'd39 : getindex[5:0] = 'd21 + 32 ;
'd40 : getindex[5:0] = 'd0 + 34 ;
'd41 : getindex[5:0] = 'd1 + 34 ;
'd42 : getindex[5:0] = 'd4 + 34 ;
'd43 : getindex[5:0] = 'd5 + 34 ;
'd44 : getindex[5:0] = 'd16 + 34 ;
'd45 : getindex[5:0] = 'd17 + 34 ;
'd46 : getindex[5:0] = 'd20 + 34 ;
'd47 : getindex[5:0] = 'd21 + 34 ;
'd48 : getindex[5:0] = 'd0 + 40 ;
'd49 : getindex[5:0] = 'd1 + 40 ;
'd50 : getindex[5:0] = 'd4 + 40 ;
'd51 : getindex[5:0] = 'd5 + 40 ;
'd52 : getindex[5:0] = 'd16 + 40 ;
'd53 : getindex[5:0] = 'd17 + 40 ;
'd54 : getindex[5:0] = 'd20 + 40 ;
'd55 : getindex[5:0] = 'd21 + 40 ;
'd56 : getindex[5:0] = 'd0 + 42 ;
'd57 : getindex[5:0] = 'd1 + 42 ;
'd58 : getindex[5:0] = 'd4 + 42 ;
'd59 : getindex[5:0] = 'd5 + 42 ;
'd60 : getindex[5:0] = 'd16 + 42 ;
'd61 : getindex[5:0] = 'd17 + 42 ;
'd62 : getindex[5:0] = 'd20 + 42 ;
'd63 : getindex[5:0] = 'd21 + 42 ;
endcase
getindex[8:6] = in[8:6] ;
end
end
endfunction
// getmvindex
function [5:0] getmvindex ;
input [5:0] in ;
begin
case( in[4:0] )
'd0 : getmvindex[4:0] = 'd0 ;
'd1 : getmvindex[4:0] = 'd1 ;
'd2 : getmvindex[4:0] = 'd4 ;
'd3 : getmvindex[4:0] = 'd5 ;
'd4 : getmvindex[4:0] = 'd16 ;
'd5 : getmvindex[4:0] = 'd17 ;
'd6 : getmvindex[4:0] = 'd20 ;
'd7 : getmvindex[4:0] = 'd21 ;
'd8 : getmvindex[4:0] = 'd2 ;
'd9 : getmvindex[4:0] = 'd3 ;
'd10 : getmvindex[4:0] = 'd6 ;
'd11 : getmvindex[4:0] = 'd7 ;
'd12 : getmvindex[4:0] = 'd18 ;
'd13 : getmvindex[4:0] = 'd19 ;
'd14 : getmvindex[4:0] = 'd22 ;
'd15 : getmvindex[4:0] = 'd23 ;
'd16 : getmvindex[4:0] = 'd8 ;
'd17 : getmvindex[4:0] = 'd9 ;
'd18 : getmvindex[4:0] = 'd12 ;
'd19 : getmvindex[4:0] = 'd13 ;
'd20 : getmvindex[4:0] = 'd24 ;
'd21 : getmvindex[4:0] = 'd25 ;
'd22 : getmvindex[4:0] = 'd28 ;
'd23 : getmvindex[4:0] = 'd29 ;
'd24 : getmvindex[4:0] = 'd10 ;
'd25 : getmvindex[4:0] = 'd11 ;
'd26 : getmvindex[4:0] = 'd14 ;
'd27 : getmvindex[4:0] = 'd15 ;
'd28 : getmvindex[4:0] = 'd26 ;
'd29 : getmvindex[4:0] = 'd27 ;
'd30 : getmvindex[4:0] = 'd30 ;
'd31 : getmvindex[4:0] = 'd31 ;
default : getmvindex[4:0] = 'd0 ;
endcase
case(in[5])
1'b0 : getmvindex[5] = 'd0 ;
default : getmvindex[5] = 'd1 ;
endcase
end
endfunction
*/
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: scdata_rep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module scdata_rep(/*AUTOARG*/
// Outputs
sctag_scdata_col_offset_c2_buf, sctag_scdata_fb_hit_c3_buf,
sctag_scdata_fbrd_c3_buf, sctag_scdata_rd_wr_c2_buf,
sctag_scdata_set_c2_buf, sctag_scdata_stdecc_c2_buf,
sctag_scdata_way_sel_c2_buf, sctag_scdata_word_en_c2_buf,
scdata_sctag_decc_c6,
// Inputs
sctag_scdata_col_offset_c2, sctag_scdata_fb_hit_c3,
sctag_scdata_fbrd_c3, sctag_scdata_rd_wr_c2, sctag_scdata_set_c2,
sctag_scdata_stdecc_c2, sctag_scdata_way_sel_c2,
sctag_scdata_word_en_c2, scdata_sctag_decc_c6_ctr
);
input [3:0] sctag_scdata_col_offset_c2;
input sctag_scdata_fb_hit_c3;
input sctag_scdata_fbrd_c3;
input sctag_scdata_rd_wr_c2;
input [9:0] sctag_scdata_set_c2;
input [77:0] sctag_scdata_stdecc_c2;
input [11:0] sctag_scdata_way_sel_c2;
input [15:0] sctag_scdata_word_en_c2;
input [155:0] scdata_sctag_decc_c6_ctr;
output [3:0] sctag_scdata_col_offset_c2_buf;
output sctag_scdata_fb_hit_c3_buf;
output sctag_scdata_fbrd_c3_buf;
output sctag_scdata_rd_wr_c2_buf;
output [9:0] sctag_scdata_set_c2_buf;
output [77:0] sctag_scdata_stdecc_c2_buf;
output [11:0] sctag_scdata_way_sel_c2_buf;
output [15:0] sctag_scdata_word_en_c2_buf;
output [155:0] scdata_sctag_decc_c6;
assign sctag_scdata_col_offset_c2_buf = sctag_scdata_col_offset_c2;
assign sctag_scdata_fb_hit_c3_buf = sctag_scdata_fb_hit_c3;
assign sctag_scdata_fbrd_c3_buf = sctag_scdata_fbrd_c3;
assign sctag_scdata_rd_wr_c2_buf = sctag_scdata_rd_wr_c2;
assign sctag_scdata_set_c2_buf = sctag_scdata_set_c2;
assign sctag_scdata_stdecc_c2_buf = sctag_scdata_stdecc_c2;
assign sctag_scdata_way_sel_c2_buf = sctag_scdata_way_sel_c2;
assign sctag_scdata_word_en_c2_buf = sctag_scdata_word_en_c2;
assign scdata_sctag_decc_c6 = scdata_sctag_decc_c6_ctr;
endmodule // scdata_rep
|
`include "constants.vh"
`include "alu_ops.vh"
`include "rv32_opcodes.vh"
`default_nettype none
module rs_branch_ent
(
//Memory
input wire clk,
input wire reset,
input wire busy,
input wire [`ADDR_LEN-1:0] wpc,
input wire [`DATA_LEN-1:0] wsrc1,
input wire [`DATA_LEN-1:0] wsrc2,
input wire wvalid1,
input wire wvalid2,
input wire [`DATA_LEN-1:0] wimm,
input wire [`RRF_SEL-1:0] wrrftag,
input wire wdstval,
input wire [`ALU_OP_WIDTH-1:0] walu_op,
input wire [`SPECTAG_LEN-1:0] wspectag,
input wire [`GSH_BHR_LEN-1:0] wbhr,
input wire wprcond,
input wire [`ADDR_LEN-1:0] wpraddr,
input wire [6:0] wopcode,
input wire we,
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire ready,
output reg [`ADDR_LEN-1:0] pc,
output reg [`DATA_LEN-1:0] imm,
output reg [`RRF_SEL-1:0] rrftag,
output reg dstval,
output reg [`ALU_OP_WIDTH-1:0] alu_op,
output reg [`SPECTAG_LEN-1:0] spectag,
output reg [`GSH_BHR_LEN-1:0] bhr,
output reg prcond,
output reg [`ADDR_LEN-1:0] praddr,
output reg [6:0] opcode,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
reg [`DATA_LEN-1:0] src1;
reg [`DATA_LEN-1:0] src2;
reg valid1;
reg valid2;
wire [`DATA_LEN-1:0] nextsrc1;
wire [`DATA_LEN-1:0] nextsrc2;
wire nextvalid1;
wire nextvalid2;
assign ready = busy & valid1 & valid2;
assign ex_src1 = ~valid1 & nextvalid1 ?
nextsrc1 : src1;
assign ex_src2 = ~valid2 & nextvalid2 ?
nextsrc2 : src2;
always @ (posedge clk) begin
if (reset) begin
pc <= 0;
imm <= 0;
rrftag <= 0;
dstval <= 0;
alu_op <= 0;
spectag <= 0;
bhr <= 0;
prcond <= 0;
praddr <= 0;
opcode <= 0;
src1 <= 0;
src2 <= 0;
valid1 <= 0;
valid2 <= 0;
end else if (we) begin
pc <= wpc;
imm <= wimm;
rrftag <= wrrftag;
dstval <= wdstval;
alu_op <= walu_op;
spectag <= wspectag;
bhr <= wbhr;
prcond <= wprcond;
praddr <= wpraddr;
opcode <= wopcode;
src1 <= wsrc1;
src2 <= wsrc2;
valid1 <= wvalid1;
valid2 <= wvalid2;
end else begin // if (we)
src1 <= nextsrc1;
src2 <= nextsrc2;
valid1 <= nextvalid1;
valid2 <= nextvalid2;
end
end
src_manager srcmng1(
.opr(src1),
.opr_rdy(valid1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc1),
.resolved(nextvalid1)
);
src_manager srcmng2(
.opr(src2),
.opr_rdy(valid2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc2),
.resolved(nextvalid2)
);
endmodule // rs_branch
module rs_branch
(
//System
input wire clk,
input wire reset,
output reg [`BRANCH_ENT_NUM-1:0] busyvec,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prtag,
input wire [`SPECTAG_LEN-1:0] specfixtag,
output wire [`BRANCH_ENT_NUM-1:0] prbusyvec_next,
//WriteSignal
input wire clearbusy, //Issue
input wire [`BRANCH_ENT_SEL-1:0] issueaddr, //= raddr, clsbsyadr
input wire we1, //alloc1
input wire we2, //alloc2
input wire [`BRANCH_ENT_SEL-1:0] waddr1, //allocent1
input wire [`BRANCH_ENT_SEL-1:0] waddr2, //allocent2
//WriteSignal1
input wire [`ADDR_LEN-1:0] wpc_1,
input wire [`DATA_LEN-1:0] wsrc1_1,
input wire [`DATA_LEN-1:0] wsrc2_1,
input wire wvalid1_1,
input wire wvalid2_1,
input wire [`DATA_LEN-1:0] wimm_1,
input wire [`RRF_SEL-1:0] wrrftag_1,
input wire wdstval_1,
input wire [`ALU_OP_WIDTH-1:0] walu_op_1,
input wire [`SPECTAG_LEN-1:0] wspectag_1,
input wire wspecbit_1,
input wire [`GSH_BHR_LEN-1:0] wbhr_1,
input wire wprcond_1,
input wire [`ADDR_LEN-1:0] wpraddr_1,
input wire [6:0] wopcode_1,
//WriteSignal2
input wire [`ADDR_LEN-1:0] wpc_2,
input wire [`DATA_LEN-1:0] wsrc1_2,
input wire [`DATA_LEN-1:0] wsrc2_2,
input wire wvalid1_2,
input wire wvalid2_2,
input wire [`DATA_LEN-1:0] wimm_2,
input wire [`RRF_SEL-1:0] wrrftag_2,
input wire wdstval_2,
input wire [`ALU_OP_WIDTH-1:0] walu_op_2,
input wire [`SPECTAG_LEN-1:0] wspectag_2,
input wire wspecbit_2,
input wire [`GSH_BHR_LEN-1:0] wbhr_2,
input wire wprcond_2,
input wire [`ADDR_LEN-1:0] wpraddr_2,
input wire [6:0] wopcode_2,
//ReadSignal
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire [`BRANCH_ENT_NUM-1:0] ready,
output wire [`ADDR_LEN-1:0] pc,
output wire [`DATA_LEN-1:0] imm,
output wire [`RRF_SEL-1:0] rrftag,
output wire dstval,
output wire [`ALU_OP_WIDTH-1:0] alu_op,
output wire [`SPECTAG_LEN-1:0] spectag,
output wire specbit,
output wire [`GSH_BHR_LEN-1:0] bhr,
output wire prcond,
output wire [`ADDR_LEN-1:0] praddr,
output wire [6:0] opcode,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
//_0
wire [`DATA_LEN-1:0] ex_src1_0;
wire [`DATA_LEN-1:0] ex_src2_0;
wire ready_0;
wire [`ADDR_LEN-1:0] pc_0;
wire [`DATA_LEN-1:0] imm_0;
wire [`RRF_SEL-1:0] rrftag_0;
wire dstval_0;
wire [`ALU_OP_WIDTH-1:0] alu_op_0;
wire [`SPECTAG_LEN-1:0] spectag_0;
wire [`GSH_BHR_LEN-1:0] bhr_0;
wire prcond_0;
wire [`ADDR_LEN-1:0] praddr_0;
wire [6:0] opcode_0;
//_1
wire [`DATA_LEN-1:0] ex_src1_1;
wire [`DATA_LEN-1:0] ex_src2_1;
wire ready_1;
wire [`ADDR_LEN-1:0] pc_1;
wire [`DATA_LEN-1:0] imm_1;
wire [`RRF_SEL-1:0] rrftag_1;
wire dstval_1;
wire [`ALU_OP_WIDTH-1:0] alu_op_1;
wire [`SPECTAG_LEN-1:0] spectag_1;
wire [`GSH_BHR_LEN-1:0] bhr_1;
wire prcond_1;
wire [`ADDR_LEN-1:0] praddr_1;
wire [6:0] opcode_1;
//_2
wire [`DATA_LEN-1:0] ex_src1_2;
wire [`DATA_LEN-1:0] ex_src2_2;
wire ready_2;
wire [`ADDR_LEN-1:0] pc_2;
wire [`DATA_LEN-1:0] imm_2;
wire [`RRF_SEL-1:0] rrftag_2;
wire dstval_2;
wire [`ALU_OP_WIDTH-1:0] alu_op_2;
wire [`SPECTAG_LEN-1:0] spectag_2;
wire [`GSH_BHR_LEN-1:0] bhr_2;
wire prcond_2;
wire [`ADDR_LEN-1:0] praddr_2;
wire [6:0] opcode_2;
//_3
wire [`DATA_LEN-1:0] ex_src1_3;
wire [`DATA_LEN-1:0] ex_src2_3;
wire ready_3;
wire [`ADDR_LEN-1:0] pc_3;
wire [`DATA_LEN-1:0] imm_3;
wire [`RRF_SEL-1:0] rrftag_3;
wire dstval_3;
wire [`ALU_OP_WIDTH-1:0] alu_op_3;
wire [`SPECTAG_LEN-1:0] spectag_3;
wire [`GSH_BHR_LEN-1:0] bhr_3;
wire prcond_3;
wire [`ADDR_LEN-1:0] praddr_3;
wire [6:0] opcode_3;
reg [`BRANCH_ENT_NUM-1:0] specbitvec;
wire [`BRANCH_ENT_NUM-1:0] inv_vector =
{(spectag_3 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_2 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_1 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_0 & specfixtag) == 0 ? 1'b1 : 1'b0};
wire [`BRANCH_ENT_NUM-1:0] inv_vector_spec =
{(spectag_3 == prtag) ? 1'b0 : 1'b1,
(spectag_2 == prtag) ? 1'b0 : 1'b1,
(spectag_1 == prtag) ? 1'b0 : 1'b1,
(spectag_0 == prtag) ? 1'b0 : 1'b1};
wire [`BRANCH_ENT_NUM-1:0] specbitvec_next =
(inv_vector_spec & specbitvec);
/* |
(we1 & wspecbit_1 ? (`BRANCH_ENT_SEL'b1 << waddr1) : 0) |
(we2 & wspecbit_2 ? (`BRANCH_ENT_SEL'b1 << waddr2) : 0);
*/
assign specbit = prsuccess ?
specbitvec_next[issueaddr] : specbitvec[issueaddr];
assign ready = {ready_3, ready_2, ready_1, ready_0};
assign prbusyvec_next = inv_vector & busyvec;
always @ (posedge clk) begin
if (reset) begin
busyvec <= 0;
specbitvec <= 0;
end else begin
if (prmiss) begin
busyvec <= prbusyvec_next;
specbitvec <= 0;
end else if (prsuccess) begin
specbitvec <= specbitvec_next;
/*
if (we1) begin
busyvec[waddr1] <= 1'b1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
end
*/
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end else begin
if (we1) begin
busyvec[waddr1] <= 1'b1;
specbitvec[waddr1] <= wspecbit_1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
specbitvec[waddr2] <= wspecbit_2;
end
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end
end
end
rs_branch_ent ent0(
.clk(clk),
.reset(reset),
.busy(busyvec[0]),
.wpc((we1 && (waddr1 == 0)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 0)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 0)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 0)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 0)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 0)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 0)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 0)) ? wdstval_1 : wdstval_2),
.walu_op((we1 && (waddr1 == 0)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 0)) ? wspectag_1 : wspectag_2),
.wbhr((we1 && (waddr1 == 0)) ? wbhr_1 : wbhr_2),
.wpraddr((we1 && (waddr1 == 0)) ? wpraddr_1 : wpraddr_2),
.wprcond((we1 && (waddr1 == 0)) ? wprcond_1 : wprcond_2),
.wopcode((we1 && (waddr1 == 0)) ? wopcode_1 : wopcode_2),
.we((we1 && (waddr1 == 0)) || (we2 && (waddr2 == 0))),
.ex_src1(ex_src1_0),
.ex_src2(ex_src2_0),
.ready(ready_0),
.pc(pc_0),
.imm(imm_0),
.rrftag(rrftag_0),
.dstval(dstval_0),
.alu_op(alu_op_0),
.spectag(spectag_0),
.bhr(bhr_0),
.prcond(prcond_0),
.praddr(praddr_0),
.opcode(opcode_0),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_branch_ent ent1(
.clk(clk),
.reset(reset),
.busy(busyvec[1]),
.wpc((we1 && (waddr1 == 1)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 1)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 1)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 1)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 1)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 1)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2),
.walu_op((we1 && (waddr1 == 1)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2),
.wbhr((we1 && (waddr1 == 1)) ? wbhr_1 : wbhr_2),
.wpraddr((we1 && (waddr1 == 1)) ? wpraddr_1 : wpraddr_2),
.wprcond((we1 && (waddr1 == 1)) ? wprcond_1 : wprcond_2),
.wopcode((we1 && (waddr1 == 1)) ? wopcode_1 : wopcode_2),
.we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))),
.ex_src1(ex_src1_1),
.ex_src2(ex_src2_1),
.ready(ready_1),
.pc(pc_1),
.imm(imm_1),
.rrftag(rrftag_1),
.dstval(dstval_1),
.alu_op(alu_op_1),
.spectag(spectag_1),
.bhr(bhr_1),
.prcond(prcond_1),
.praddr(praddr_1),
.opcode(opcode_1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_branch_ent ent2(
.clk(clk),
.reset(reset),
.busy(busyvec[2]),
.wpc((we1 && (waddr1 == 2)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 2)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 2)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 2)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 2)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 2)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 2)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 2)) ? wdstval_1 : wdstval_2),
.walu_op((we1 && (waddr1 == 2)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 2)) ? wspectag_1 : wspectag_2),
.wbhr((we1 && (waddr1 == 2)) ? wbhr_1 : wbhr_2),
.wpraddr((we1 && (waddr1 == 2)) ? wpraddr_1 : wpraddr_2),
.wprcond((we1 && (waddr1 == 2)) ? wprcond_1 : wprcond_2),
.wopcode((we1 && (waddr1 == 2)) ? wopcode_1 : wopcode_2),
.we((we1 && (waddr1 == 2)) || (we2 && (waddr2 == 2))),
.ex_src1(ex_src1_2),
.ex_src2(ex_src2_2),
.ready(ready_2),
.pc(pc_2),
.imm(imm_2),
.rrftag(rrftag_2),
.dstval(dstval_2),
.alu_op(alu_op_2),
.spectag(spectag_2),
.bhr(bhr_2),
.prcond(prcond_2),
.praddr(praddr_2),
.opcode(opcode_2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_branch_ent ent3(
.clk(clk),
.reset(reset),
.busy(busyvec[3]),
.wpc((we1 && (waddr1 == 3)) ? wpc_1 : wpc_2),
.wsrc1((we1 && (waddr1 == 3)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 3)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 3)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 3)) ? wvalid2_1 : wvalid2_2),
.wimm((we1 && (waddr1 == 3)) ? wimm_1 : wimm_2),
.wrrftag((we1 && (waddr1 == 3)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 3)) ? wdstval_1 : wdstval_2),
.walu_op((we1 && (waddr1 == 3)) ? walu_op_1 : walu_op_2),
.wspectag((we1 && (waddr1 == 3)) ? wspectag_1 : wspectag_2),
.wbhr((we1 && (waddr1 == 3)) ? wbhr_1 : wbhr_2),
.wpraddr((we1 && (waddr1 == 3)) ? wpraddr_1 : wpraddr_2),
.wprcond((we1 && (waddr1 == 3)) ? wprcond_1 : wprcond_2),
.wopcode((we1 && (waddr1 == 3)) ? wopcode_1 : wopcode_2),
.we((we1 && (waddr1 == 3)) || (we2 && (waddr2 == 3))),
.ex_src1(ex_src1_3),
.ex_src2(ex_src2_3),
.ready(ready_3),
.pc(pc_3),
.imm(imm_3),
.rrftag(rrftag_3),
.dstval(dstval_3),
.alu_op(alu_op_3),
.spectag(spectag_3),
.bhr(bhr_3),
.prcond(prcond_3),
.praddr(praddr_3),
.opcode(opcode_3),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
assign ex_src1 = (issueaddr == 0) ? ex_src1_0 :
(issueaddr == 1) ? ex_src1_1 :
(issueaddr == 2) ? ex_src1_2 : ex_src1_3;
assign ex_src2 = (issueaddr == 0) ? ex_src2_0 :
(issueaddr == 1) ? ex_src2_1 :
(issueaddr == 2) ? ex_src2_2 : ex_src2_3;
assign pc = (issueaddr == 0) ? pc_0 :
(issueaddr == 1) ? pc_1 :
(issueaddr == 2) ? pc_2 : pc_3;
assign imm = (issueaddr == 0) ? imm_0 :
(issueaddr == 1) ? imm_1 :
(issueaddr == 2) ? imm_2 : imm_3;
assign rrftag = (issueaddr == 0) ? rrftag_0 :
(issueaddr == 1) ? rrftag_1 :
(issueaddr == 2) ? rrftag_2 : rrftag_3;
assign dstval = (issueaddr == 0) ? dstval_0 :
(issueaddr == 1) ? dstval_1 :
(issueaddr == 2) ? dstval_2 : dstval_3;
assign alu_op = (issueaddr == 0) ? alu_op_0 :
(issueaddr == 1) ? alu_op_1 :
(issueaddr == 2) ? alu_op_2 : alu_op_3;
assign spectag = (issueaddr == 0) ? spectag_0 :
(issueaddr == 1) ? spectag_1 :
(issueaddr == 2) ? spectag_2 : spectag_3;
assign bhr = (issueaddr == 0) ? bhr_0 :
(issueaddr == 1) ? bhr_1 :
(issueaddr == 2) ? bhr_2 : bhr_3;
assign prcond = (issueaddr == 0) ? prcond_0 :
(issueaddr == 1) ? prcond_1 :
(issueaddr == 2) ? prcond_2 : prcond_3;
assign praddr = (issueaddr == 0) ? praddr_0 :
(issueaddr == 1) ? praddr_1 :
(issueaddr == 2) ? praddr_2 : praddr_3;
assign opcode = (issueaddr == 0) ? opcode_0 :
(issueaddr == 1) ? opcode_1 :
(issueaddr == 2) ? opcode_2 : opcode_3;
endmodule // rs_branch
`default_nettype wire
|
/*
* PicoRV32 -- A Small RISC-V (RV32I) Processor Core
*
* Copyright (C) 2015 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`timescale 1 ns / 1 ps
// `default_nettype none
// `define DEBUGNETS
// `define DEBUGREGS
// `define DEBUGASM
// `define DEBUG
`ifdef DEBUG
`define debug(debug_command) debug_command
`else
`define debug(debug_command)
`endif
`ifdef FORMAL
`define FORMAL_KEEP (* keep *)
`define assert(assert_expr) assert(assert_expr)
`else
`ifdef DEBUGNETS
`define FORMAL_KEEP (* keep *)
`else
`define FORMAL_KEEP
`endif
`define assert(assert_expr) empty_statement
`endif
// uncomment this for register file in extra module
// `define PICORV32_REGS picorv32_regs
// this macro can be used to check if the verilog files in your
// design are read in the correct order.
`define PICORV32_V
/***************************************************************
* picorv32
***************************************************************/
module picorv32 #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] LATCHED_MEM_RDATA = 0,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output reg trap,
output reg mem_valid,
output reg mem_instr,
input mem_ready,
output reg [31:0] mem_addr,
output reg [31:0] mem_wdata,
output reg [ 3:0] mem_wstrb,
input [31:0] mem_rdata,
// Look-Ahead Interface
output mem_la_read,
output mem_la_write,
output [31:0] mem_la_addr,
output reg [31:0] mem_la_wdata,
output reg [ 3:0] mem_la_wstrb,
// Pico Co-Processor Interface (PCPI)
output reg pcpi_valid,
output reg [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ Interface
input [31:0] irq,
output reg [31:0] eoi,
`ifdef RISCV_FORMAL
output reg rvfi_valid,
output reg [63:0] rvfi_order,
output reg [31:0] rvfi_insn,
output reg rvfi_trap,
output reg rvfi_halt,
output reg rvfi_intr,
output reg [ 4:0] rvfi_rs1_addr,
output reg [ 4:0] rvfi_rs2_addr,
output reg [31:0] rvfi_rs1_rdata,
output reg [31:0] rvfi_rs2_rdata,
output reg [ 4:0] rvfi_rd_addr,
output reg [31:0] rvfi_rd_wdata,
output reg [31:0] rvfi_pc_rdata,
output reg [31:0] rvfi_pc_wdata,
output reg [31:0] rvfi_mem_addr,
output reg [ 3:0] rvfi_mem_rmask,
output reg [ 3:0] rvfi_mem_wmask,
output reg [31:0] rvfi_mem_rdata,
output reg [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output reg trace_valid,
output reg [35:0] trace_data
);
localparam integer irq_timer = 0;
localparam integer irq_ebreak = 1;
localparam integer irq_buserror = 2;
localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0};
localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0};
reg [63:0] count_cycle, count_instr;
reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
reg [4:0] reg_sh;
reg [31:0] next_insn_opcode;
reg [31:0] dbg_insn_opcode;
reg [31:0] dbg_insn_addr;
wire dbg_mem_valid = mem_valid;
wire dbg_mem_instr = mem_instr;
wire dbg_mem_ready = mem_ready;
wire [31:0] dbg_mem_addr = mem_addr;
wire [31:0] dbg_mem_wdata = mem_wdata;
wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
wire [31:0] dbg_mem_rdata = mem_rdata;
assign pcpi_rs1 = reg_op1;
assign pcpi_rs2 = reg_op2;
wire [31:0] next_pc;
reg irq_delay;
reg irq_active;
reg [31:0] irq_mask;
reg [31:0] irq_pending;
reg [31:0] timer;
`ifndef PICORV32_REGS
reg [31:0] cpuregs [0:regfile_size-1];
integer i;
initial begin
if (REGS_INIT_ZERO) begin
for (i = 0; i < regfile_size; i = i+1)
cpuregs[i] = 0;
end
end
`endif
task empty_statement;
// This task is used by the `assert directive in non-formal mode to
// avoid empty statement (which are unsupported by plain Verilog syntax).
begin end
endtask
`ifdef DEBUGREGS
wire [31:0] dbg_reg_x0 = 0;
wire [31:0] dbg_reg_x1 = cpuregs[1];
wire [31:0] dbg_reg_x2 = cpuregs[2];
wire [31:0] dbg_reg_x3 = cpuregs[3];
wire [31:0] dbg_reg_x4 = cpuregs[4];
wire [31:0] dbg_reg_x5 = cpuregs[5];
wire [31:0] dbg_reg_x6 = cpuregs[6];
wire [31:0] dbg_reg_x7 = cpuregs[7];
wire [31:0] dbg_reg_x8 = cpuregs[8];
wire [31:0] dbg_reg_x9 = cpuregs[9];
wire [31:0] dbg_reg_x10 = cpuregs[10];
wire [31:0] dbg_reg_x11 = cpuregs[11];
wire [31:0] dbg_reg_x12 = cpuregs[12];
wire [31:0] dbg_reg_x13 = cpuregs[13];
wire [31:0] dbg_reg_x14 = cpuregs[14];
wire [31:0] dbg_reg_x15 = cpuregs[15];
wire [31:0] dbg_reg_x16 = cpuregs[16];
wire [31:0] dbg_reg_x17 = cpuregs[17];
wire [31:0] dbg_reg_x18 = cpuregs[18];
wire [31:0] dbg_reg_x19 = cpuregs[19];
wire [31:0] dbg_reg_x20 = cpuregs[20];
wire [31:0] dbg_reg_x21 = cpuregs[21];
wire [31:0] dbg_reg_x22 = cpuregs[22];
wire [31:0] dbg_reg_x23 = cpuregs[23];
wire [31:0] dbg_reg_x24 = cpuregs[24];
wire [31:0] dbg_reg_x25 = cpuregs[25];
wire [31:0] dbg_reg_x26 = cpuregs[26];
wire [31:0] dbg_reg_x27 = cpuregs[27];
wire [31:0] dbg_reg_x28 = cpuregs[28];
wire [31:0] dbg_reg_x29 = cpuregs[29];
wire [31:0] dbg_reg_x30 = cpuregs[30];
wire [31:0] dbg_reg_x31 = cpuregs[31];
`endif
// Internal PCPI Cores
wire pcpi_mul_wr;
wire [31:0] pcpi_mul_rd;
wire pcpi_mul_wait;
wire pcpi_mul_ready;
wire pcpi_div_wr;
wire [31:0] pcpi_div_rd;
wire pcpi_div_wait;
wire pcpi_div_ready;
reg pcpi_int_wr;
reg [31:0] pcpi_int_rd;
reg pcpi_int_wait;
reg pcpi_int_ready;
generate if (ENABLE_FAST_MUL) begin
picorv32_pcpi_fast_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else if (ENABLE_MUL) begin
picorv32_pcpi_mul pcpi_mul (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_mul_wr ),
.pcpi_rd (pcpi_mul_rd ),
.pcpi_wait (pcpi_mul_wait ),
.pcpi_ready(pcpi_mul_ready )
);
end else begin
assign pcpi_mul_wr = 0;
assign pcpi_mul_rd = 32'bx;
assign pcpi_mul_wait = 0;
assign pcpi_mul_ready = 0;
end endgenerate
generate if (ENABLE_DIV) begin
picorv32_pcpi_div pcpi_div (
.clk (clk ),
.resetn (resetn ),
.pcpi_valid(pcpi_valid ),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_div_wr ),
.pcpi_rd (pcpi_div_rd ),
.pcpi_wait (pcpi_div_wait ),
.pcpi_ready(pcpi_div_ready )
);
end else begin
assign pcpi_div_wr = 0;
assign pcpi_div_rd = 32'bx;
assign pcpi_div_wait = 0;
assign pcpi_div_ready = 0;
end endgenerate
always @* begin
pcpi_int_wr = 0;
pcpi_int_rd = 32'bx;
pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait};
pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
(* parallel_case *)
case (1'b1)
ENABLE_PCPI && pcpi_ready: begin
pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
end
(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
pcpi_int_wr = pcpi_mul_wr;
pcpi_int_rd = pcpi_mul_rd;
end
ENABLE_DIV && pcpi_div_ready: begin
pcpi_int_wr = pcpi_div_wr;
pcpi_int_rd = pcpi_div_rd;
end
endcase
end
// Memory Interface
reg [1:0] mem_state;
reg [1:0] mem_wordsize;
reg [31:0] mem_rdata_word;
reg [31:0] mem_rdata_q;
reg mem_do_prefetch;
reg mem_do_rinst;
reg mem_do_rdata;
reg mem_do_wdata;
wire mem_xfer;
reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
reg prefetched_high_word;
reg clear_prefetched_high_word;
reg [15:0] mem_16bit_buffer;
wire [31:0] mem_rdata_latched_noshuffle;
wire [31:0] mem_rdata_latched;
wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
assign mem_la_write = resetn && !mem_state && mem_do_wdata;
assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
always @(posedge clk) begin
if (!resetn) begin
mem_la_firstword_reg <= 0;
last_mem_valid <= 0;
end else begin
if (!last_mem_valid)
mem_la_firstword_reg <= mem_la_firstword;
last_mem_valid <= mem_valid && !mem_ready;
end
end
always @* begin
(* full_case *)
case (mem_wordsize)
0: begin
mem_la_wdata = reg_op2;
mem_la_wstrb = 4'b1111;
mem_rdata_word = mem_rdata;
end
1: begin
mem_la_wdata = {2{reg_op2[15:0]}};
mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
case (reg_op1[1])
1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
endcase
end
2: begin
mem_la_wdata = {4{reg_op2[7:0]}};
mem_la_wstrb = 4'b0001 << reg_op1[1:0];
case (reg_op1[1:0])
2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
endcase
end
endcase
end
always @(posedge clk) begin
if (mem_xfer) begin
mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
end
if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
end
3'b010: begin // C.LW
mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b 110: begin // C.SW
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b 000: begin // C.ADDI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 010: begin // C.LI
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
3'b 011: begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
end else begin // C.LUI
mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
end
3'b100: begin
if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
mem_rdata_q[31:25] <= 7'b0100000;
mem_rdata_q[14:12] <= 3'b 101;
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
end
end
3'b 110: begin // C.BEQZ
mem_rdata_q[14:12] <= 3'b000;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
3'b 111: begin // C.BNEZ
mem_rdata_q[14:12] <= 3'b001;
{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
mem_rdata_q[31:25] <= 7'b0000000;
mem_rdata_q[14:12] <= 3'b 001;
end
3'b010: begin // C.LWSP
mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:20] <= 12'b0;
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
mem_rdata_q[14:12] <= 3'b000;
mem_rdata_q[31:25] <= 7'b0000000;
end
end
3'b110: begin // C.SWSP
{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
mem_rdata_q[14:12] <= 3'b 010;
end
endcase
end
endcase
end
end
always @(posedge clk) begin
if (resetn && !trap) begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
`assert(!mem_do_wdata);
if (mem_do_prefetch || mem_do_rinst)
`assert(!mem_do_rdata);
if (mem_do_rdata)
`assert(!mem_do_prefetch && !mem_do_rinst);
if (mem_do_wdata)
`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
if (mem_state == 2 || mem_state == 3)
`assert(mem_valid || mem_do_prefetch);
end
end
always @(posedge clk) begin
if (!resetn || trap) begin
if (!resetn)
mem_state <= 0;
if (!resetn || mem_ready)
mem_valid <= 0;
mem_la_secondword <= 0;
prefetched_high_word <= 0;
end else begin
if (mem_la_read || mem_la_write) begin
mem_addr <= mem_la_addr;
mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
end
if (mem_la_write) begin
mem_wdata <= mem_la_wdata;
end
case (mem_state)
0: begin
if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
mem_valid <= !mem_la_use_prefetched_high_word;
mem_instr <= mem_do_prefetch || mem_do_rinst;
mem_wstrb <= 0;
mem_state <= 1;
end
if (mem_do_wdata) begin
mem_valid <= 1;
mem_instr <= 0;
mem_state <= 2;
end
end
1: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
`assert(mem_valid == !mem_la_use_prefetched_high_word);
`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
if (mem_xfer) begin
if (COMPRESSED_ISA && mem_la_read) begin
mem_valid <= 1;
mem_la_secondword <= 1;
if (!mem_la_use_prefetched_high_word)
mem_16bit_buffer <= mem_rdata[31:16];
end else begin
mem_valid <= 0;
mem_la_secondword <= 0;
if (COMPRESSED_ISA && !mem_do_rdata) begin
if (~&mem_rdata[1:0] || mem_la_secondword) begin
mem_16bit_buffer <= mem_rdata[31:16];
prefetched_high_word <= 1;
end else begin
prefetched_high_word <= 0;
end
end
mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
end
end
end
2: begin
`assert(mem_wstrb != 0);
`assert(mem_do_wdata);
if (mem_xfer) begin
mem_valid <= 0;
mem_state <= 0;
end
end
3: begin
`assert(mem_wstrb == 0);
`assert(mem_do_prefetch);
if (mem_do_rinst) begin
mem_state <= 0;
end
end
endcase
end
if (clear_prefetched_high_word)
prefetched_high_word <= 0;
end
// Instruction Decoder
reg instr_lui, instr_auipc, instr_jal, instr_jalr;
reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak;
reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
wire instr_trap;
reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2;
reg [31:0] decoded_imm, decoded_imm_uj;
reg decoder_trigger;
reg decoder_trigger_q;
reg decoder_pseudo_trigger;
reg decoder_pseudo_trigger_q;
reg compressed_instr;
reg is_lui_auipc_jal;
reg is_lb_lh_lw_lbu_lhu;
reg is_slli_srli_srai;
reg is_jalr_addi_slti_sltiu_xori_ori_andi;
reg is_sb_sh_sw;
reg is_sll_srl_sra;
reg is_lui_auipc_jal_jalr_addi_add_sub;
reg is_slti_blt_slt;
reg is_sltiu_bltu_sltu;
reg is_beq_bne_blt_bge_bltu_bgeu;
reg is_lbu_lhu_lw;
reg is_alu_reg_imm;
reg is_alu_reg_reg;
reg is_compare;
assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh,
instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
reg [63:0] new_ascii_instr;
`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
`FORMAL_KEEP reg [31:0] dbg_insn_imm;
`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
`FORMAL_KEEP reg [4:0] dbg_insn_rd;
`FORMAL_KEEP reg [31:0] dbg_rs1val;
`FORMAL_KEEP reg [31:0] dbg_rs2val;
`FORMAL_KEEP reg dbg_rs1val_valid;
`FORMAL_KEEP reg dbg_rs2val_valid;
always @* begin
new_ascii_instr = "";
if (instr_lui) new_ascii_instr = "lui";
if (instr_auipc) new_ascii_instr = "auipc";
if (instr_jal) new_ascii_instr = "jal";
if (instr_jalr) new_ascii_instr = "jalr";
if (instr_beq) new_ascii_instr = "beq";
if (instr_bne) new_ascii_instr = "bne";
if (instr_blt) new_ascii_instr = "blt";
if (instr_bge) new_ascii_instr = "bge";
if (instr_bltu) new_ascii_instr = "bltu";
if (instr_bgeu) new_ascii_instr = "bgeu";
if (instr_lb) new_ascii_instr = "lb";
if (instr_lh) new_ascii_instr = "lh";
if (instr_lw) new_ascii_instr = "lw";
if (instr_lbu) new_ascii_instr = "lbu";
if (instr_lhu) new_ascii_instr = "lhu";
if (instr_sb) new_ascii_instr = "sb";
if (instr_sh) new_ascii_instr = "sh";
if (instr_sw) new_ascii_instr = "sw";
if (instr_addi) new_ascii_instr = "addi";
if (instr_slti) new_ascii_instr = "slti";
if (instr_sltiu) new_ascii_instr = "sltiu";
if (instr_xori) new_ascii_instr = "xori";
if (instr_ori) new_ascii_instr = "ori";
if (instr_andi) new_ascii_instr = "andi";
if (instr_slli) new_ascii_instr = "slli";
if (instr_srli) new_ascii_instr = "srli";
if (instr_srai) new_ascii_instr = "srai";
if (instr_add) new_ascii_instr = "add";
if (instr_sub) new_ascii_instr = "sub";
if (instr_sll) new_ascii_instr = "sll";
if (instr_slt) new_ascii_instr = "slt";
if (instr_sltu) new_ascii_instr = "sltu";
if (instr_xor) new_ascii_instr = "xor";
if (instr_srl) new_ascii_instr = "srl";
if (instr_sra) new_ascii_instr = "sra";
if (instr_or) new_ascii_instr = "or";
if (instr_and) new_ascii_instr = "and";
if (instr_rdcycle) new_ascii_instr = "rdcycle";
if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
if (instr_rdinstr) new_ascii_instr = "rdinstr";
if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
if (instr_getq) new_ascii_instr = "getq";
if (instr_setq) new_ascii_instr = "setq";
if (instr_retirq) new_ascii_instr = "retirq";
if (instr_maskirq) new_ascii_instr = "maskirq";
if (instr_waitirq) new_ascii_instr = "waitirq";
if (instr_timer) new_ascii_instr = "timer";
end
reg [63:0] q_ascii_instr;
reg [31:0] q_insn_imm;
reg [31:0] q_insn_opcode;
reg [4:0] q_insn_rs1;
reg [4:0] q_insn_rs2;
reg [4:0] q_insn_rd;
reg dbg_next;
wire launch_next_insn;
reg dbg_valid_insn;
reg [63:0] cached_ascii_instr;
reg [31:0] cached_insn_imm;
reg [31:0] cached_insn_opcode;
reg [4:0] cached_insn_rs1;
reg [4:0] cached_insn_rs2;
reg [4:0] cached_insn_rd;
always @(posedge clk) begin
q_ascii_instr <= dbg_ascii_instr;
q_insn_imm <= dbg_insn_imm;
q_insn_opcode <= dbg_insn_opcode;
q_insn_rs1 <= dbg_insn_rs1;
q_insn_rs2 <= dbg_insn_rs2;
q_insn_rd <= dbg_insn_rd;
dbg_next <= launch_next_insn;
if (!resetn || trap)
dbg_valid_insn <= 0;
else if (launch_next_insn)
dbg_valid_insn <= 1;
if (decoder_trigger_q) begin
cached_ascii_instr <= new_ascii_instr;
cached_insn_imm <= decoded_imm;
if (&next_insn_opcode[1:0])
cached_insn_opcode <= next_insn_opcode;
else
cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
cached_insn_rs1 <= decoded_rs1;
cached_insn_rs2 <= decoded_rs2;
cached_insn_rd <= decoded_rd;
end
if (launch_next_insn) begin
dbg_insn_addr <= next_pc;
end
end
always @* begin
dbg_ascii_instr = q_ascii_instr;
dbg_insn_imm = q_insn_imm;
dbg_insn_opcode = q_insn_opcode;
dbg_insn_rs1 = q_insn_rs1;
dbg_insn_rs2 = q_insn_rs2;
dbg_insn_rd = q_insn_rd;
if (dbg_next) begin
if (decoder_pseudo_trigger_q) begin
dbg_ascii_instr = cached_ascii_instr;
dbg_insn_imm = cached_insn_imm;
dbg_insn_opcode = cached_insn_opcode;
dbg_insn_rs1 = cached_insn_rs1;
dbg_insn_rs2 = cached_insn_rs2;
dbg_insn_rd = cached_insn_rd;
end else begin
dbg_ascii_instr = new_ascii_instr;
if (&next_insn_opcode[1:0])
dbg_insn_opcode = next_insn_opcode;
else
dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
dbg_insn_imm = decoded_imm;
dbg_insn_rs1 = decoded_rs1;
dbg_insn_rs2 = decoded_rs2;
dbg_insn_rd = decoded_rd;
end
end
end
`ifdef DEBUGASM
always @(posedge clk) begin
if (dbg_next) begin
$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
end
end
`endif
`ifdef DEBUG
always @(posedge clk) begin
if (dbg_next) begin
if (&dbg_insn_opcode[1:0])
$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
else
$display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
end
end
`endif
always @(posedge clk) begin
is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
if (mem_do_rinst && mem_done) begin
instr_lui <= mem_rdata_latched[6:0] == 7'b0110111;
instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111;
instr_jal <= mem_rdata_latched[6:0] == 7'b1101111;
instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011;
is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011;
is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011;
is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011;
{ decoded_imm_uj[31:20], decoded_imm_uj[10:1], decoded_imm_uj[11], decoded_imm_uj[19:12], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[19:15];
decoded_rs2 <= mem_rdata_latched[24:20];
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
decoded_rs1[regindex_bits-1] <= 1; // instr_getq
if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
compressed_instr <= 0;
if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
compressed_instr <= 1;
decoded_rd <= 0;
decoded_rs1 <= 0;
decoded_rs2 <= 0;
{ decoded_imm_uj[31:11], decoded_imm_uj[4], decoded_imm_uj[9:8], decoded_imm_uj[10], decoded_imm_uj[6],
decoded_imm_uj[7], decoded_imm_uj[3:1], decoded_imm_uj[5], decoded_imm_uj[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
case (mem_rdata_latched[1:0])
2'b00: begin // Quadrant 0
case (mem_rdata_latched[15:13])
3'b000: begin // C.ADDI4SPN
is_alu_reg_imm <= |mem_rdata_latched[12:5];
decoded_rs1 <= 2;
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b010: begin // C.LW
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rd <= 8 + mem_rdata_latched[4:2];
end
3'b110: begin // C.SW
is_sb_sh_sw <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
endcase
end
2'b01: begin // Quadrant 1
case (mem_rdata_latched[15:13])
3'b000: begin // C.NOP / C.ADDI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end
3'b001: begin // C.JAL
instr_jal <= 1;
decoded_rd <= 1;
end
3'b 010: begin // C.LI
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
3'b 011: begin
if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
end else begin // C.LUI
instr_lui <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
end
end
end
3'b100: begin
if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
is_alu_reg_imm <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
end
if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
is_alu_reg_reg <= 1;
decoded_rd <= 8 + mem_rdata_latched[9:7];
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 8 + mem_rdata_latched[4:2];
end
end
3'b101: begin // C.J
instr_jal <= 1;
end
3'b110: begin // C.BEQZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
3'b111: begin // C.BNEZ
is_beq_bne_blt_bge_bltu_bgeu <= 1;
decoded_rs1 <= 8 + mem_rdata_latched[9:7];
decoded_rs2 <= 0;
end
endcase
end
2'b10: begin // Quadrant 2
case (mem_rdata_latched[15:13])
3'b000: begin // C.SLLI
if (!mem_rdata_latched[12]) begin
is_alu_reg_imm <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
end
end
3'b010: begin // C.LWSP
if (mem_rdata_latched[11:7]) begin
is_lb_lh_lw_lbu_lhu <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 2;
end
end
3'b100: begin
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
instr_jalr <= 1;
decoded_rd <= 0;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= 0;
decoded_rs2 <= mem_rdata_latched[6:2];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
instr_jalr <= 1;
decoded_rd <= 1;
decoded_rs1 <= mem_rdata_latched[11:7];
end
if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
is_alu_reg_reg <= 1;
decoded_rd <= mem_rdata_latched[11:7];
decoded_rs1 <= mem_rdata_latched[11:7];
decoded_rs2 <= mem_rdata_latched[6:2];
end
end
3'b110: begin // C.SWSP
is_sb_sh_sw <= 1;
decoded_rs1 <= 2;
decoded_rs2 <= mem_rdata_latched[6:2];
end
endcase
end
endcase
end
end
if (decoder_trigger && !decoder_pseudo_trigger) begin
pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
(mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
is_slli_srli_srai <= is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
mem_rdata_q[14:12] == 3'b000,
mem_rdata_q[14:12] == 3'b010,
mem_rdata_q[14:12] == 3'b011,
mem_rdata_q[14:12] == 3'b100,
mem_rdata_q[14:12] == 3'b110,
mem_rdata_q[14:12] == 3'b111
};
is_sll_srl_sra <= is_alu_reg_reg && |{
mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
};
is_lui_auipc_jal_jalr_addi_add_sub <= 0;
is_compare <= 0;
(* parallel_case *)
case (1'b1)
instr_jal:
decoded_imm <= decoded_imm_uj;
|{instr_lui, instr_auipc}:
decoded_imm <= mem_rdata_q[31:12] << 12;
|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
decoded_imm <= $signed(mem_rdata_q[31:20]);
is_beq_bne_blt_bge_bltu_bgeu:
decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
is_sb_sh_sw:
decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
default:
decoded_imm <= 1'bx;
endcase
end
if (!resetn) begin
is_beq_bne_blt_bge_bltu_bgeu <= 0;
is_compare <= 0;
instr_beq <= 0;
instr_bne <= 0;
instr_blt <= 0;
instr_bge <= 0;
instr_bltu <= 0;
instr_bgeu <= 0;
instr_addi <= 0;
instr_slti <= 0;
instr_sltiu <= 0;
instr_xori <= 0;
instr_ori <= 0;
instr_andi <= 0;
instr_add <= 0;
instr_sub <= 0;
instr_sll <= 0;
instr_slt <= 0;
instr_sltu <= 0;
instr_xor <= 0;
instr_srl <= 0;
instr_sra <= 0;
instr_or <= 0;
instr_and <= 0;
end
end
// Main State Machine
localparam cpu_state_trap = 8'b10000000;
localparam cpu_state_fetch = 8'b01000000;
localparam cpu_state_ld_rs1 = 8'b00100000;
localparam cpu_state_ld_rs2 = 8'b00010000;
localparam cpu_state_exec = 8'b00001000;
localparam cpu_state_shift = 8'b00000100;
localparam cpu_state_stmem = 8'b00000010;
localparam cpu_state_ldmem = 8'b00000001;
reg [7:0] cpu_state;
reg [1:0] irq_state;
`FORMAL_KEEP reg [127:0] dbg_ascii_state;
always @* begin
dbg_ascii_state = "";
if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap";
if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch";
if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec";
if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift";
if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem";
if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem";
end
reg set_mem_do_rinst;
reg set_mem_do_rdata;
reg set_mem_do_wdata;
reg latched_store;
reg latched_stalu;
reg latched_branch;
reg latched_compr;
reg latched_trace;
reg latched_is_lu;
reg latched_is_lh;
reg latched_is_lb;
reg [regindex_bits-1:0] latched_rd;
reg [31:0] current_pc;
assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
reg [3:0] pcpi_timeout_counter;
reg pcpi_timeout;
reg [31:0] next_irq_pending;
reg do_waitirq;
reg [31:0] alu_out, alu_out_q;
reg alu_out_0, alu_out_0_q;
reg alu_wait, alu_wait_2;
reg [31:0] alu_add_sub;
reg [31:0] alu_shl, alu_shr;
reg alu_eq, alu_ltu, alu_lts;
generate if (TWO_CYCLE_ALU) begin
always @(posedge clk) begin
alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq <= reg_op1 == reg_op2;
alu_lts <= $signed(reg_op1) < $signed(reg_op2);
alu_ltu <= reg_op1 < reg_op2;
alu_shl <= reg_op1 << reg_op2[4:0];
alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end else begin
always @* begin
alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
alu_eq = reg_op1 == reg_op2;
alu_lts = $signed(reg_op1) < $signed(reg_op2);
alu_ltu = reg_op1 < reg_op2;
alu_shl = reg_op1 << reg_op2[4:0];
alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
end
end endgenerate
always @* begin
alu_out_0 = 'bx;
(* parallel_case, full_case *)
case (1'b1)
instr_beq:
alu_out_0 = alu_eq;
instr_bne:
alu_out_0 = !alu_eq;
instr_bge:
alu_out_0 = !alu_lts;
instr_bgeu:
alu_out_0 = !alu_ltu;
is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_lts;
is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
alu_out_0 = alu_ltu;
endcase
alu_out = 'bx;
(* parallel_case, full_case *)
case (1'b1)
is_lui_auipc_jal_jalr_addi_add_sub:
alu_out = alu_add_sub;
is_compare:
alu_out = alu_out_0;
instr_xori || instr_xor:
alu_out = reg_op1 ^ reg_op2;
instr_ori || instr_or:
alu_out = reg_op1 | reg_op2;
instr_andi || instr_and:
alu_out = reg_op1 & reg_op2;
BARREL_SHIFTER && (instr_sll || instr_slli):
alu_out = alu_shl;
BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
alu_out = alu_shr;
endcase
`ifdef RISCV_FORMAL_BLACKBOX_ALU
alu_out_0 = $anyseq;
alu_out = $anyseq;
`endif
end
reg clear_prefetched_high_word_q;
always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
always @* begin
clear_prefetched_high_word = clear_prefetched_high_word_q;
if (!prefetched_high_word)
clear_prefetched_high_word = 0;
if (latched_branch || irq_state || !resetn)
clear_prefetched_high_word = COMPRESSED_ISA;
end
reg cpuregs_write;
reg [31:0] cpuregs_wrdata;
reg [31:0] cpuregs_rs1;
reg [31:0] cpuregs_rs2;
reg [regindex_bits-1:0] decoded_rs;
always @* begin
cpuregs_write = 0;
cpuregs_wrdata = 'bx;
if (cpu_state == cpu_state_fetch) begin
(* parallel_case *)
case (1'b1)
latched_branch: begin
cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
cpuregs_write = 1;
end
latched_store && !latched_branch: begin
cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[0]: begin
cpuregs_wrdata = reg_next_pc | latched_compr;
cpuregs_write = 1;
end
ENABLE_IRQ && irq_state[1]: begin
cpuregs_wrdata = irq_pending & ~irq_mask;
cpuregs_write = 1;
end
endcase
end
end
`ifndef PICORV32_REGS
always @(posedge clk) begin
if (resetn && cpuregs_write && latched_rd)
cpuregs[latched_rd] <= cpuregs_wrdata;
end
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
`else
cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
`endif
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
`ifndef RISCV_FORMAL_BLACKBOX_REGS
cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
`else
cpuregs_rs1 = decoded_rs ? $anyseq : 0;
`endif
cpuregs_rs2 = cpuregs_rs1;
end
end
`else
wire[31:0] cpuregs_rdata1;
wire [31:0] cpuregs_rdata2;
wire [5:0] cpuregs_waddr = latched_rd;
wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
`PICORV32_REGS cpuregs (
.clk(clk),
.wen(resetn && cpuregs_write && latched_rd),
.waddr(cpuregs_waddr),
.raddr1(cpuregs_raddr1),
.raddr2(cpuregs_raddr2),
.wdata(cpuregs_wrdata),
.rdata1(cpuregs_rdata1),
.rdata2(cpuregs_rdata2)
);
always @* begin
decoded_rs = 'bx;
if (ENABLE_REGS_DUALPORT) begin
cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
end else begin
decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
cpuregs_rs2 = cpuregs_rs1;
end
end
`endif
assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
always @(posedge clk) begin
trap <= 0;
reg_sh <= 'bx;
reg_out <= 'bx;
set_mem_do_rinst = 0;
set_mem_do_rdata = 0;
set_mem_do_wdata = 0;
alu_out_0_q <= alu_out_0;
alu_out_q <= alu_out;
alu_wait <= 0;
alu_wait_2 <= 0;
if (launch_next_insn) begin
dbg_rs1val <= 'bx;
dbg_rs2val <= 'bx;
dbg_rs1val_valid <= 0;
dbg_rs2val_valid <= 0;
end
if (WITH_PCPI && CATCH_ILLINSN) begin
if (resetn && pcpi_valid && !pcpi_int_wait) begin
if (pcpi_timeout_counter)
pcpi_timeout_counter <= pcpi_timeout_counter - 1;
end else
pcpi_timeout_counter <= ~0;
pcpi_timeout <= !pcpi_timeout_counter;
end
if (ENABLE_COUNTERS) begin
count_cycle <= resetn ? count_cycle + 1 : 0;
if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
end else begin
count_cycle <= 'bx;
count_instr <= 'bx;
end
next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
if (timer - 1 == 0)
next_irq_pending[irq_timer] = 1;
timer <= timer - 1;
end
if (ENABLE_IRQ) begin
next_irq_pending = next_irq_pending | irq;
end
decoder_trigger <= mem_do_rinst && mem_done;
decoder_trigger_q <= decoder_trigger;
decoder_pseudo_trigger <= 0;
decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
do_waitirq <= 0;
trace_valid <= 0;
if (!ENABLE_TRACE)
trace_data <= 'bx;
if (!resetn) begin
reg_pc <= PROGADDR_RESET;
reg_next_pc <= PROGADDR_RESET;
if (ENABLE_COUNTERS)
count_instr <= 0;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_trace <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
pcpi_valid <= 0;
pcpi_timeout <= 0;
irq_active <= 0;
irq_delay <= 0;
irq_mask <= ~0;
next_irq_pending = 0;
irq_state <= 0;
eoi <= 0;
timer <= 0;
if (~STACKADDR) begin
latched_store <= 1;
latched_rd <= 2;
reg_out <= STACKADDR;
end
cpu_state <= cpu_state_fetch;
end else
(* parallel_case, full_case *)
case (cpu_state)
cpu_state_trap: begin
trap <= 1;
end
cpu_state_fetch: begin
mem_do_rinst <= !decoder_trigger && !do_waitirq;
mem_wordsize <= 0;
current_pc = reg_next_pc;
(* parallel_case *)
case (1'b1)
latched_branch: begin
current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
`debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
end
latched_store && !latched_branch: begin
`debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
end
ENABLE_IRQ && irq_state[0]: begin
current_pc = PROGADDR_IRQ;
irq_active <= 1;
mem_do_rinst <= 1;
end
ENABLE_IRQ && irq_state[1]: begin
eoi <= irq_pending & ~irq_mask;
next_irq_pending = next_irq_pending & irq_mask;
end
endcase
if (ENABLE_TRACE && latched_trace) begin
latched_trace <= 0;
trace_valid <= 1;
if (latched_branch)
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
else
trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
end
reg_pc <= current_pc;
reg_next_pc <= current_pc;
latched_store <= 0;
latched_stalu <= 0;
latched_branch <= 0;
latched_is_lu <= 0;
latched_is_lh <= 0;
latched_is_lb <= 0;
latched_rd <= decoded_rd;
latched_compr <= compressed_instr;
if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
irq_state <=
irq_state == 2'b00 ? 2'b01 :
irq_state == 2'b01 ? 2'b10 : 2'b00;
latched_compr <= latched_compr;
if (ENABLE_IRQ_QREGS)
latched_rd <= irqregs_offset | irq_state[0];
else
latched_rd <= irq_state[0] ? 4 : 3;
end else
if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
if (irq_pending) begin
latched_store <= 1;
reg_out <= irq_pending;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
mem_do_rinst <= 1;
end else
do_waitirq <= 1;
end else
if (decoder_trigger) begin
`debug($display("-- %-0t", $time);)
irq_delay <= irq_active;
reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
if (ENABLE_TRACE)
latched_trace <= 1;
if (ENABLE_COUNTERS) begin
count_instr <= count_instr + 1;
if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
end
if (instr_jal) begin
mem_do_rinst <= 1;
reg_next_pc <= current_pc + decoded_imm_uj;
latched_branch <= 1;
end else begin
mem_do_rinst <= 0;
mem_do_prefetch <= !instr_jalr && !instr_retirq;
cpu_state <= cpu_state_ld_rs1;
end
end
end
cpu_state_ld_rs1: begin
reg_op1 <= 'bx;
reg_op2 <= 'bx;
(* parallel_case *)
case (1'b1)
(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
if (WITH_PCPI) begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
pcpi_valid <= 1;
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end else begin
cpu_state <= cpu_state_ld_rs2;
end
end else begin
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
(* parallel_case, full_case *)
case (1'b1)
instr_rdcycle:
reg_out <= count_cycle[31:0];
instr_rdcycleh && ENABLE_COUNTERS64:
reg_out <= count_cycle[63:32];
instr_rdinstr:
reg_out <= count_instr[31:0];
instr_rdinstrh && ENABLE_COUNTERS64:
reg_out <= count_instr[63:32];
endcase
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
is_lui_auipc_jal: begin
reg_op1 <= instr_lui ? 0 : reg_pc;
reg_op2 <= decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
latched_rd <= latched_rd | irqregs_offset;
latched_store <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_retirq: begin
eoi <= 0;
irq_active <= 0;
latched_branch <= 1;
latched_store <= 1;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && instr_maskirq: begin
latched_store <= 1;
reg_out <= irq_mask;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
irq_mask <= cpuregs_rs1 | MASKED_IRQ;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
latched_store <= 1;
reg_out <= timer;
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
timer <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_fetch;
end
is_lb_lh_lw_lbu_lhu && !instr_trap: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
cpu_state <= cpu_state_ldmem;
mem_do_rinst <= 1;
end
is_slli_srli_srai && !BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_sh <= decoded_rs2;
cpu_state <= cpu_state_shift;
end
is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
if (TWO_CYCLE_ALU)
alu_wait <= 1;
else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
default: begin
`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
reg_op1 <= cpuregs_rs1;
dbg_rs1val <= cpuregs_rs1;
dbg_rs1val_valid <= 1;
if (ENABLE_REGS_DUALPORT) begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end else
cpu_state <= cpu_state_ld_rs2;
end
endcase
end
cpu_state_ld_rs2: begin
`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
reg_sh <= cpuregs_rs2;
reg_op2 <= cpuregs_rs2;
dbg_rs2val <= cpuregs_rs2;
dbg_rs2val_valid <= 1;
(* parallel_case *)
case (1'b1)
WITH_PCPI && instr_trap: begin
pcpi_valid <= 1;
if (pcpi_int_ready) begin
mem_do_rinst <= 1;
pcpi_valid <= 0;
reg_out <= pcpi_int_rd;
latched_store <= pcpi_int_wr;
cpu_state <= cpu_state_fetch;
end else
if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
pcpi_valid <= 0;
`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
next_irq_pending[irq_ebreak] = 1;
cpu_state <= cpu_state_fetch;
end else
cpu_state <= cpu_state_trap;
end
end
is_sb_sh_sw: begin
cpu_state <= cpu_state_stmem;
mem_do_rinst <= 1;
end
is_sll_srl_sra && !BARREL_SHIFTER: begin
cpu_state <= cpu_state_shift;
end
default: begin
if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
alu_wait <= 1;
end else
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_exec;
end
endcase
end
cpu_state_exec: begin
reg_out <= reg_pc + decoded_imm;
if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
alu_wait <= alu_wait_2;
end else
if (is_beq_bne_blt_bge_bltu_bgeu) begin
latched_rd <= 0;
latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
if (mem_done)
cpu_state <= cpu_state_fetch;
if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
decoder_trigger <= 0;
set_mem_do_rinst = 1;
end
end else begin
latched_branch <= instr_jalr;
latched_store <= 1;
latched_stalu <= 1;
cpu_state <= cpu_state_fetch;
end
end
cpu_state_shift: begin
latched_store <= 1;
if (reg_sh == 0) begin
reg_out <= reg_op1;
mem_do_rinst <= mem_do_prefetch;
cpu_state <= cpu_state_fetch;
end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
endcase
reg_sh <= reg_sh - 4;
end else begin
(* parallel_case, full_case *)
case (1'b1)
instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
endcase
reg_sh <= reg_sh - 1;
end
end
cpu_state_stmem: begin
if (ENABLE_TRACE)
reg_out <= reg_op2;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_wdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_sb: mem_wordsize <= 2;
instr_sh: mem_wordsize <= 1;
instr_sw: mem_wordsize <= 0;
endcase
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_wdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
cpu_state <= cpu_state_fetch;
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
end
end
end
cpu_state_ldmem: begin
latched_store <= 1;
if (!mem_do_prefetch || mem_done) begin
if (!mem_do_rdata) begin
(* parallel_case, full_case *)
case (1'b1)
instr_lb || instr_lbu: mem_wordsize <= 2;
instr_lh || instr_lhu: mem_wordsize <= 1;
instr_lw: mem_wordsize <= 0;
endcase
latched_is_lu <= is_lbu_lhu_lw;
latched_is_lh <= instr_lh;
latched_is_lb <= instr_lb;
if (ENABLE_TRACE) begin
trace_valid <= 1;
trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
end
reg_op1 <= reg_op1 + decoded_imm;
set_mem_do_rdata = 1;
end
if (!mem_do_prefetch && mem_done) begin
(* parallel_case, full_case *)
case (1'b1)
latched_is_lu: reg_out <= mem_rdata_word;
latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
endcase
decoder_trigger <= 1;
decoder_pseudo_trigger <= 1;
cpu_state <= cpu_state_fetch;
end
end
end
endcase
if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (mem_wordsize == 1 && reg_op1[0] != 0) begin
`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
end
if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
next_irq_pending[irq_buserror] = 1;
end else
cpu_state <= cpu_state_trap;
end
if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
cpu_state <= cpu_state_trap;
end
if (!resetn || mem_done) begin
mem_do_prefetch <= 0;
mem_do_rinst <= 0;
mem_do_rdata <= 0;
mem_do_wdata <= 0;
end
if (set_mem_do_rinst)
mem_do_rinst <= 1;
if (set_mem_do_rdata)
mem_do_rdata <= 1;
if (set_mem_do_wdata)
mem_do_wdata <= 1;
irq_pending <= next_irq_pending & ~MASKED_IRQ;
if (!CATCH_MISALIGN) begin
if (COMPRESSED_ISA) begin
reg_pc[0] <= 0;
reg_next_pc[0] <= 0;
end else begin
reg_pc[1:0] <= 0;
reg_next_pc[1:0] <= 0;
end
end
current_pc = 'bx;
end
`ifdef RISCV_FORMAL
reg dbg_irq_call;
reg dbg_irq_enter;
reg [31:0] dbg_irq_ret;
always @(posedge clk) begin
rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
rvfi_insn <= dbg_insn_opcode;
rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
rvfi_pc_rdata <= dbg_insn_addr;
rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
rvfi_trap <= trap;
rvfi_halt <= trap;
rvfi_intr <= dbg_irq_enter;
if (!resetn) begin
dbg_irq_call <= 0;
dbg_irq_enter <= 0;
end else
if (rvfi_valid) begin
dbg_irq_call <= 0;
dbg_irq_enter <= dbg_irq_call;
end else
if (irq_state == 1) begin
dbg_irq_call <= 1;
dbg_irq_ret <= next_pc;
end
if (!resetn) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end else
if (cpuregs_write && !irq_state) begin
rvfi_rd_addr <= latched_rd;
rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
end else
if (rvfi_valid) begin
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
casez (dbg_insn_opcode)
32'b 0000000_?????_000??_???_?????_0001011: begin // getq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
32'b 0000001_?????_?????_???_000??_0001011: begin // setq
rvfi_rd_addr <= 0;
rvfi_rd_wdata <= 0;
end
32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
rvfi_rs1_addr <= 0;
rvfi_rs1_rdata <= 0;
end
endcase
if (!dbg_irq_call) begin
if (dbg_mem_instr) begin
rvfi_mem_addr <= 0;
rvfi_mem_rmask <= 0;
rvfi_mem_wmask <= 0;
rvfi_mem_rdata <= 0;
rvfi_mem_wdata <= 0;
end else
if (dbg_mem_valid && dbg_mem_ready) begin
rvfi_mem_addr <= dbg_mem_addr;
rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
rvfi_mem_wmask <= dbg_mem_wstrb;
rvfi_mem_rdata <= dbg_mem_rdata;
rvfi_mem_wdata <= dbg_mem_wdata;
end
end
end
always @* begin
rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
end
`endif
// Formal Verification
`ifdef FORMAL
reg [3:0] last_mem_nowait;
always @(posedge clk)
last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
// stall the memory interface for max 4 cycles
restrict property (|last_mem_nowait || mem_ready || !mem_valid);
// resetn low in first cycle, after that resetn high
restrict property (resetn != $initstate);
// this just makes it much easier to read traces. uncomment as needed.
// assume property (mem_valid || !mem_ready);
reg ok;
always @* begin
if (resetn) begin
// instruction fetches are read-only
if (mem_valid && mem_instr)
assert (mem_wstrb == 0);
// cpu_state must be valid
ok = 0;
if (cpu_state == cpu_state_trap) ok = 1;
if (cpu_state == cpu_state_fetch) ok = 1;
if (cpu_state == cpu_state_ld_rs1) ok = 1;
if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
if (cpu_state == cpu_state_exec) ok = 1;
if (cpu_state == cpu_state_shift) ok = 1;
if (cpu_state == cpu_state_stmem) ok = 1;
if (cpu_state == cpu_state_ldmem) ok = 1;
assert (ok);
end
end
reg last_mem_la_read = 0;
reg last_mem_la_write = 0;
reg [31:0] last_mem_la_addr;
reg [31:0] last_mem_la_wdata;
reg [3:0] last_mem_la_wstrb = 0;
always @(posedge clk) begin
last_mem_la_read <= mem_la_read;
last_mem_la_write <= mem_la_write;
last_mem_la_addr <= mem_la_addr;
last_mem_la_wdata <= mem_la_wdata;
last_mem_la_wstrb <= mem_la_wstrb;
if (last_mem_la_read) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wstrb == 0);
end
if (last_mem_la_write) begin
assert(mem_valid);
assert(mem_addr == last_mem_la_addr);
assert(mem_wdata == last_mem_la_wdata);
assert(mem_wstrb == last_mem_la_wstrb);
end
if (mem_la_read || mem_la_write) begin
assert(!mem_valid || mem_ready);
end
end
`endif
endmodule
// This is a simple example implementation of PICORV32_REGS.
// Use the PICORV32_REGS mechanism if you want to use custom
// memory resources to implement the processor register file.
// Note that your implementation must match the requirements of
// the PicoRV32 configuration. (e.g. QREGS, etc)
module picorv32_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:30];
always @(posedge clk)
if (wen) regs[~waddr[4:0]] <= wdata;
assign rdata1 = regs[~raddr1[4:0]];
assign rdata2 = regs[~raddr2[4:0]];
endmodule
/***************************************************************
* picorv32_pcpi_mul
***************************************************************/
module picorv32_pcpi_mul #(
parameter STEPS_AT_ONCE = 1,
parameter CARRY_CHAIN = 4
) (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,
output reg [31:0] pcpi_rd,
output reg pcpi_wait,
output reg pcpi_ready
);
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
wire instr_rs2_signed = |{instr_mulh};
reg pcpi_wait_q;
wire mul_start = pcpi_wait && !pcpi_wait_q;
always @(posedge clk) begin
instr_mul <= 0;
instr_mulh <= 0;
instr_mulhsu <= 0;
instr_mulhu <= 0;
if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
case (pcpi_insn[14:12])
3'b000: instr_mul <= 1;
3'b001: instr_mulh <= 1;
3'b010: instr_mulhsu <= 1;
3'b011: instr_mulhu <= 1;
endcase
end
pcpi_wait <= instr_any_mul;
pcpi_wait_q <= pcpi_wait;
end
reg [63:0] rs1, rs2, rd, rdx;
reg [63:0] next_rs1, next_rs2, this_rs2;
reg [63:0] next_rd, next_rdx, next_rdt;
reg [6:0] mul_counter;
reg mul_waiting;
reg mul_finish;
integer i, j;
// carry save accumulator
always @* begin
next_rd = rd;
next_rdx = rdx;
next_rs1 = rs1;
next_rs2 = rs2;
for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
this_rs2 = next_rs1[0] ? next_rs2 : 0;
if (CARRY_CHAIN == 0) begin
next_rdt = next_rd ^ next_rdx ^ this_rs2;
next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
next_rd = next_rdt;
end else begin
next_rdt = 0;
for (j = 0; j < 64; j = j + CARRY_CHAIN)
{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
next_rdx = next_rdt << 1;
end
next_rs1 = next_rs1 >> 1;
next_rs2 = next_rs2 << 1;
end
end
always @(posedge clk) begin
mul_finish <= 0;
if (!resetn) begin
mul_waiting <= 1;
end else
if (mul_waiting) begin
if (instr_rs1_signed)
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed)
rs2 <= $signed(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
rd <= 0;
rdx <= 0;
mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
mul_waiting <= !mul_start;
end else begin
rd <= next_rd;
rdx <= next_rdx;
rs1 <= next_rs1;
rs2 <= next_rs2;
mul_counter <= mul_counter - STEPS_AT_ONCE;
if (mul_counter[6]) begin
mul_finish <= 1;
mul_waiting <= 1;
end
end
end
always @(posedge clk) begin
pcpi_wr <= 0;
pcpi_ready <= 0;
if (mul_finish && resetn) begin
pcpi_wr <= 1;
pcpi_ready <= 1;
pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
end
end
endmodule
module picorv32_pcpi_fast_mul #(
parameter EXTRA_MUL_FFS = 0,
parameter EXTRA_INSN_FFS = 0,
parameter MUL_CLKGATE = 0
) (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output pcpi_wr,
output [31:0] pcpi_rd,
output pcpi_wait,
output pcpi_ready
);
reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
wire instr_rs2_signed = |{instr_mulh};
reg shift_out;
reg [3:0] active;
reg [32:0] rs1, rs2, rs1_q, rs2_q;
reg [63:0] rd, rd_q;
wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
reg pcpi_insn_valid_q;
always @* begin
instr_mul = 0;
instr_mulh = 0;
instr_mulhsu = 0;
instr_mulhu = 0;
if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
case (pcpi_insn[14:12])
3'b000: instr_mul = 1;
3'b001: instr_mulh = 1;
3'b010: instr_mulhsu = 1;
3'b011: instr_mulhu = 1;
endcase
end
end
always @(posedge clk) begin
pcpi_insn_valid_q <= pcpi_insn_valid;
if (!MUL_CLKGATE || active[0]) begin
rs1_q <= rs1;
rs2_q <= rs2;
end
if (!MUL_CLKGATE || active[1]) begin
rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
end
if (!MUL_CLKGATE || active[2]) begin
rd_q <= rd;
end
end
always @(posedge clk) begin
if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
if (instr_rs1_signed)
rs1 <= $signed(pcpi_rs1);
else
rs1 <= $unsigned(pcpi_rs1);
if (instr_rs2_signed)
rs2 <= $signed(pcpi_rs2);
else
rs2 <= $unsigned(pcpi_rs2);
active[0] <= 1;
end else begin
active[0] <= 0;
end
active[3:1] <= active;
shift_out <= instr_any_mulh;
if (!resetn)
active <= 0;
end
assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
assign pcpi_wait = 0;
assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
`ifdef RISCV_FORMAL_ALTOPS
assign pcpi_rd =
instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
`else
assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
`endif
endmodule
/***************************************************************
* picorv32_pcpi_div
***************************************************************/
module picorv32_pcpi_div (
input clk, resetn,
input pcpi_valid,
input [31:0] pcpi_insn,
input [31:0] pcpi_rs1,
input [31:0] pcpi_rs2,
output reg pcpi_wr,
output reg [31:0] pcpi_rd,
output reg pcpi_wait,
output reg pcpi_ready
);
reg instr_div, instr_divu, instr_rem, instr_remu;
wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
reg pcpi_wait_q;
wire start = pcpi_wait && !pcpi_wait_q;
always @(posedge clk) begin
instr_div <= 0;
instr_divu <= 0;
instr_rem <= 0;
instr_remu <= 0;
if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
case (pcpi_insn[14:12])
3'b100: instr_div <= 1;
3'b101: instr_divu <= 1;
3'b110: instr_rem <= 1;
3'b111: instr_remu <= 1;
endcase
end
pcpi_wait <= instr_any_div_rem && resetn;
pcpi_wait_q <= pcpi_wait && resetn;
end
reg [31:0] dividend;
reg [62:0] divisor;
reg [31:0] quotient;
reg [31:0] quotient_msk;
reg running;
reg outsign;
always @(posedge clk) begin
pcpi_ready <= 0;
pcpi_wr <= 0;
pcpi_rd <= 'bx;
if (!resetn) begin
running <= 0;
end else
if (start) begin
running <= 1;
dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
quotient <= 0;
quotient_msk <= 1 << 31;
end else
if (!quotient_msk && running) begin
running <= 0;
pcpi_ready <= 1;
pcpi_wr <= 1;
`ifdef RISCV_FORMAL_ALTOPS
case (1)
instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
endcase
`else
if (instr_div || instr_divu)
pcpi_rd <= outsign ? -quotient : quotient;
else
pcpi_rd <= outsign ? -dividend : dividend;
`endif
end else begin
if (divisor <= dividend) begin
dividend <= dividend - divisor;
quotient <= quotient | quotient_msk;
end
divisor <= divisor >> 1;
`ifdef RISCV_FORMAL_ALTOPS
quotient_msk <= quotient_msk >> 5;
`else
quotient_msk <= quotient_msk >> 1;
`endif
end
end
endmodule
/***************************************************************
* picorv32_axi
***************************************************************/
module picorv32_axi #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
input clk, resetn,
output trap,
// AXI4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_rdata;
picorv32_axi_adapter axi_adapter (
.clk (clk ),
.resetn (resetn ),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr ),
.mem_axi_awprot (mem_axi_awprot ),
.mem_axi_wvalid (mem_axi_wvalid ),
.mem_axi_wready (mem_axi_wready ),
.mem_axi_wdata (mem_axi_wdata ),
.mem_axi_wstrb (mem_axi_wstrb ),
.mem_axi_bvalid (mem_axi_bvalid ),
.mem_axi_bready (mem_axi_bready ),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr ),
.mem_axi_arprot (mem_axi_arprot ),
.mem_axi_rvalid (mem_axi_rvalid ),
.mem_axi_rready (mem_axi_rready ),
.mem_axi_rdata (mem_axi_rdata ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
endmodule
/***************************************************************
* picorv32_axi_adapter
***************************************************************/
module picorv32_axi_adapter (
input clk, resetn,
// AXI4-lite master memory interface
output mem_axi_awvalid,
input mem_axi_awready,
output [31:0] mem_axi_awaddr,
output [ 2:0] mem_axi_awprot,
output mem_axi_wvalid,
input mem_axi_wready,
output [31:0] mem_axi_wdata,
output [ 3:0] mem_axi_wstrb,
input mem_axi_bvalid,
output mem_axi_bready,
output mem_axi_arvalid,
input mem_axi_arready,
output [31:0] mem_axi_araddr,
output [ 2:0] mem_axi_arprot,
input mem_axi_rvalid,
output mem_axi_rready,
input [31:0] mem_axi_rdata,
// Native PicoRV32 memory interface
input mem_valid,
input mem_instr,
output mem_ready,
input [31:0] mem_addr,
input [31:0] mem_wdata,
input [ 3:0] mem_wstrb,
output [31:0] mem_rdata
);
reg ack_awvalid;
reg ack_arvalid;
reg ack_wvalid;
reg xfer_done;
assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
assign mem_axi_awaddr = mem_addr;
assign mem_axi_awprot = 0;
assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
assign mem_axi_araddr = mem_addr;
assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
assign mem_axi_wdata = mem_wdata;
assign mem_axi_wstrb = mem_wstrb;
assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
assign mem_axi_bready = mem_valid && |mem_wstrb;
assign mem_axi_rready = mem_valid && !mem_wstrb;
assign mem_rdata = mem_axi_rdata;
always @(posedge clk) begin
if (!resetn) begin
ack_awvalid <= 0;
end else begin
xfer_done <= mem_valid && mem_ready;
if (mem_axi_awready && mem_axi_awvalid)
ack_awvalid <= 1;
if (mem_axi_arready && mem_axi_arvalid)
ack_arvalid <= 1;
if (mem_axi_wready && mem_axi_wvalid)
ack_wvalid <= 1;
if (xfer_done || !mem_valid) begin
ack_awvalid <= 0;
ack_arvalid <= 0;
ack_wvalid <= 0;
end
end
end
endmodule
/***************************************************************
* picorv32_wb
***************************************************************/
module picorv32_wb #(
parameter [ 0:0] ENABLE_COUNTERS = 1,
parameter [ 0:0] ENABLE_COUNTERS64 = 1,
parameter [ 0:0] ENABLE_REGS_16_31 = 1,
parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
parameter [ 0:0] TWO_STAGE_SHIFT = 1,
parameter [ 0:0] BARREL_SHIFTER = 0,
parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
parameter [ 0:0] TWO_CYCLE_ALU = 0,
parameter [ 0:0] COMPRESSED_ISA = 0,
parameter [ 0:0] CATCH_MISALIGN = 1,
parameter [ 0:0] CATCH_ILLINSN = 1,
parameter [ 0:0] ENABLE_PCPI = 0,
parameter [ 0:0] ENABLE_MUL = 0,
parameter [ 0:0] ENABLE_FAST_MUL = 0,
parameter [ 0:0] ENABLE_DIV = 0,
parameter [ 0:0] ENABLE_IRQ = 0,
parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
parameter [ 0:0] ENABLE_TRACE = 0,
parameter [ 0:0] REGS_INIT_ZERO = 0,
parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
parameter [31:0] STACKADDR = 32'h ffff_ffff
) (
output trap,
// Wishbone interfaces
input wb_rst_i,
input wb_clk_i,
output reg [31:0] wbm_adr_o,
output reg [31:0] wbm_dat_o,
input [31:0] wbm_dat_i,
output reg wbm_we_o,
output reg [3:0] wbm_sel_o,
output reg wbm_stb_o,
input wbm_ack_i,
output reg wbm_cyc_o,
// Pico Co-Processor Interface (PCPI)
output pcpi_valid,
output [31:0] pcpi_insn,
output [31:0] pcpi_rs1,
output [31:0] pcpi_rs2,
input pcpi_wr,
input [31:0] pcpi_rd,
input pcpi_wait,
input pcpi_ready,
// IRQ interface
input [31:0] irq,
output [31:0] eoi,
`ifdef RISCV_FORMAL
output rvfi_valid,
output [63:0] rvfi_order,
output [31:0] rvfi_insn,
output rvfi_trap,
output rvfi_halt,
output rvfi_intr,
output [ 4:0] rvfi_rs1_addr,
output [ 4:0] rvfi_rs2_addr,
output [31:0] rvfi_rs1_rdata,
output [31:0] rvfi_rs2_rdata,
output [ 4:0] rvfi_rd_addr,
output [31:0] rvfi_rd_wdata,
output [31:0] rvfi_pc_rdata,
output [31:0] rvfi_pc_wdata,
output [31:0] rvfi_mem_addr,
output [ 3:0] rvfi_mem_rmask,
output [ 3:0] rvfi_mem_wmask,
output [31:0] rvfi_mem_rdata,
output [31:0] rvfi_mem_wdata,
`endif
// Trace Interface
output trace_valid,
output [35:0] trace_data,
output mem_instr
);
wire mem_valid;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [ 3:0] mem_wstrb;
reg mem_ready;
reg [31:0] mem_rdata;
wire clk;
wire resetn;
assign clk = wb_clk_i;
assign resetn = ~wb_rst_i;
picorv32 #(
.ENABLE_COUNTERS (ENABLE_COUNTERS ),
.ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ),
.ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ),
.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
.TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ),
.BARREL_SHIFTER (BARREL_SHIFTER ),
.TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ),
.TWO_CYCLE_ALU (TWO_CYCLE_ALU ),
.COMPRESSED_ISA (COMPRESSED_ISA ),
.CATCH_MISALIGN (CATCH_MISALIGN ),
.CATCH_ILLINSN (CATCH_ILLINSN ),
.ENABLE_PCPI (ENABLE_PCPI ),
.ENABLE_MUL (ENABLE_MUL ),
.ENABLE_FAST_MUL (ENABLE_FAST_MUL ),
.ENABLE_DIV (ENABLE_DIV ),
.ENABLE_IRQ (ENABLE_IRQ ),
.ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ),
.ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ),
.ENABLE_TRACE (ENABLE_TRACE ),
.REGS_INIT_ZERO (REGS_INIT_ZERO ),
.MASKED_IRQ (MASKED_IRQ ),
.LATCHED_IRQ (LATCHED_IRQ ),
.PROGADDR_RESET (PROGADDR_RESET ),
.PROGADDR_IRQ (PROGADDR_IRQ ),
.STACKADDR (STACKADDR )
) picorv32_core (
.clk (clk ),
.resetn (resetn),
.trap (trap ),
.mem_valid(mem_valid),
.mem_addr (mem_addr ),
.mem_wdata(mem_wdata),
.mem_wstrb(mem_wstrb),
.mem_instr(mem_instr),
.mem_ready(mem_ready),
.mem_rdata(mem_rdata),
.pcpi_valid(pcpi_valid),
.pcpi_insn (pcpi_insn ),
.pcpi_rs1 (pcpi_rs1 ),
.pcpi_rs2 (pcpi_rs2 ),
.pcpi_wr (pcpi_wr ),
.pcpi_rd (pcpi_rd ),
.pcpi_wait (pcpi_wait ),
.pcpi_ready(pcpi_ready),
.irq(irq),
.eoi(eoi),
`ifdef RISCV_FORMAL
.rvfi_valid (rvfi_valid ),
.rvfi_order (rvfi_order ),
.rvfi_insn (rvfi_insn ),
.rvfi_trap (rvfi_trap ),
.rvfi_halt (rvfi_halt ),
.rvfi_intr (rvfi_intr ),
.rvfi_rs1_addr (rvfi_rs1_addr ),
.rvfi_rs2_addr (rvfi_rs2_addr ),
.rvfi_rs1_rdata(rvfi_rs1_rdata),
.rvfi_rs2_rdata(rvfi_rs2_rdata),
.rvfi_rd_addr (rvfi_rd_addr ),
.rvfi_rd_wdata (rvfi_rd_wdata ),
.rvfi_pc_rdata (rvfi_pc_rdata ),
.rvfi_pc_wdata (rvfi_pc_wdata ),
.rvfi_mem_addr (rvfi_mem_addr ),
.rvfi_mem_rmask(rvfi_mem_rmask),
.rvfi_mem_wmask(rvfi_mem_wmask),
.rvfi_mem_rdata(rvfi_mem_rdata),
.rvfi_mem_wdata(rvfi_mem_wdata),
`endif
.trace_valid(trace_valid),
.trace_data (trace_data)
);
localparam IDLE = 2'b00;
localparam WBSTART = 2'b01;
localparam WBEND = 2'b10;
reg [1:0] state;
wire we;
assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
always @(posedge wb_clk_i) begin
if (wb_rst_i) begin
wbm_adr_o <= 0;
wbm_dat_o <= 0;
wbm_we_o <= 0;
wbm_sel_o <= 0;
wbm_stb_o <= 0;
wbm_cyc_o <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
if (mem_valid) begin
wbm_adr_o <= mem_addr;
wbm_dat_o <= mem_wdata;
wbm_we_o <= we;
wbm_sel_o <= mem_wstrb;
wbm_stb_o <= 1'b1;
wbm_cyc_o <= 1'b1;
state <= WBSTART;
end else begin
mem_ready <= 1'b0;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBSTART:begin
if (wbm_ack_i) begin
mem_rdata <= wbm_dat_i;
mem_ready <= 1'b1;
state <= WBEND;
wbm_stb_o <= 1'b0;
wbm_cyc_o <= 1'b0;
wbm_we_o <= 1'b0;
end
end
WBEND: begin
mem_ready <= 1'b0;
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2b (
VPWR,
VGND,
Y ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
// Local signals
wire Y not0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_PP_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="feedforward,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=9.395400,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=36,HLS_SYN_DSP=45,HLS_SYN_FF=7119,HLS_SYN_LUT=10499}" *)
module feedforward (
ap_clk,
ap_rst_n,
P_config_V_TDATA,
P_config_V_TVALID,
P_config_V_TREADY,
P_WandB_TDATA,
P_WandB_TVALID,
P_WandB_TREADY,
P_uOut_TDATA,
P_uOut_TVALID,
P_uOut_TREADY,
P_netIn_TDATA,
P_netIn_TVALID,
P_netIn_TREADY,
P_netOut_V_TDATA,
P_netOut_V_TVALID,
P_netOut_V_TREADY,
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP,
interrupt
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 167'b1;
parameter ap_ST_st2_fsm_1 = 167'b10;
parameter ap_ST_st3_fsm_2 = 167'b100;
parameter ap_ST_st4_fsm_3 = 167'b1000;
parameter ap_ST_st5_fsm_4 = 167'b10000;
parameter ap_ST_st6_fsm_5 = 167'b100000;
parameter ap_ST_st7_fsm_6 = 167'b1000000;
parameter ap_ST_st8_fsm_7 = 167'b10000000;
parameter ap_ST_st9_fsm_8 = 167'b100000000;
parameter ap_ST_st10_fsm_9 = 167'b1000000000;
parameter ap_ST_st11_fsm_10 = 167'b10000000000;
parameter ap_ST_st12_fsm_11 = 167'b100000000000;
parameter ap_ST_st13_fsm_12 = 167'b1000000000000;
parameter ap_ST_st14_fsm_13 = 167'b10000000000000;
parameter ap_ST_st15_fsm_14 = 167'b100000000000000;
parameter ap_ST_st16_fsm_15 = 167'b1000000000000000;
parameter ap_ST_st17_fsm_16 = 167'b10000000000000000;
parameter ap_ST_st18_fsm_17 = 167'b100000000000000000;
parameter ap_ST_st19_fsm_18 = 167'b1000000000000000000;
parameter ap_ST_st20_fsm_19 = 167'b10000000000000000000;
parameter ap_ST_st21_fsm_20 = 167'b100000000000000000000;
parameter ap_ST_st22_fsm_21 = 167'b1000000000000000000000;
parameter ap_ST_st23_fsm_22 = 167'b10000000000000000000000;
parameter ap_ST_st24_fsm_23 = 167'b100000000000000000000000;
parameter ap_ST_st25_fsm_24 = 167'b1000000000000000000000000;
parameter ap_ST_st26_fsm_25 = 167'b10000000000000000000000000;
parameter ap_ST_st27_fsm_26 = 167'b100000000000000000000000000;
parameter ap_ST_st28_fsm_27 = 167'b1000000000000000000000000000;
parameter ap_ST_st29_fsm_28 = 167'b10000000000000000000000000000;
parameter ap_ST_st30_fsm_29 = 167'b100000000000000000000000000000;
parameter ap_ST_st31_fsm_30 = 167'b1000000000000000000000000000000;
parameter ap_ST_st32_fsm_31 = 167'b10000000000000000000000000000000;
parameter ap_ST_st33_fsm_32 = 167'b100000000000000000000000000000000;
parameter ap_ST_st34_fsm_33 = 167'b1000000000000000000000000000000000;
parameter ap_ST_st35_fsm_34 = 167'b10000000000000000000000000000000000;
parameter ap_ST_st36_fsm_35 = 167'b100000000000000000000000000000000000;
parameter ap_ST_st37_fsm_36 = 167'b1000000000000000000000000000000000000;
parameter ap_ST_st38_fsm_37 = 167'b10000000000000000000000000000000000000;
parameter ap_ST_st39_fsm_38 = 167'b100000000000000000000000000000000000000;
parameter ap_ST_st40_fsm_39 = 167'b1000000000000000000000000000000000000000;
parameter ap_ST_st41_fsm_40 = 167'b10000000000000000000000000000000000000000;
parameter ap_ST_st42_fsm_41 = 167'b100000000000000000000000000000000000000000;
parameter ap_ST_st43_fsm_42 = 167'b1000000000000000000000000000000000000000000;
parameter ap_ST_st44_fsm_43 = 167'b10000000000000000000000000000000000000000000;
parameter ap_ST_st45_fsm_44 = 167'b100000000000000000000000000000000000000000000;
parameter ap_ST_st46_fsm_45 = 167'b1000000000000000000000000000000000000000000000;
parameter ap_ST_st47_fsm_46 = 167'b10000000000000000000000000000000000000000000000;
parameter ap_ST_st48_fsm_47 = 167'b100000000000000000000000000000000000000000000000;
parameter ap_ST_st49_fsm_48 = 167'b1000000000000000000000000000000000000000000000000;
parameter ap_ST_st50_fsm_49 = 167'b10000000000000000000000000000000000000000000000000;
parameter ap_ST_st51_fsm_50 = 167'b100000000000000000000000000000000000000000000000000;
parameter ap_ST_st52_fsm_51 = 167'b1000000000000000000000000000000000000000000000000000;
parameter ap_ST_st53_fsm_52 = 167'b10000000000000000000000000000000000000000000000000000;
parameter ap_ST_st54_fsm_53 = 167'b100000000000000000000000000000000000000000000000000000;
parameter ap_ST_st55_fsm_54 = 167'b1000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st56_fsm_55 = 167'b10000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st57_fsm_56 = 167'b100000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st58_fsm_57 = 167'b1000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st59_fsm_58 = 167'b10000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st60_fsm_59 = 167'b100000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st61_fsm_60 = 167'b1000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st62_fsm_61 = 167'b10000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st63_fsm_62 = 167'b100000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st64_fsm_63 = 167'b1000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st65_fsm_64 = 167'b10000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st66_fsm_65 = 167'b100000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st67_fsm_66 = 167'b1000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st68_fsm_67 = 167'b10000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st69_fsm_68 = 167'b100000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st70_fsm_69 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st71_fsm_70 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st72_fsm_71 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st73_fsm_72 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st74_fsm_73 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st75_fsm_74 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st76_fsm_75 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st77_fsm_76 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st78_fsm_77 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st79_fsm_78 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st80_fsm_79 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st81_fsm_80 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st82_fsm_81 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st83_fsm_82 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st84_fsm_83 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st85_fsm_84 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st86_fsm_85 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st87_fsm_86 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st88_fsm_87 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st89_fsm_88 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st90_fsm_89 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st91_fsm_90 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st92_fsm_91 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st93_fsm_92 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st94_fsm_93 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st95_fsm_94 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st96_fsm_95 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st97_fsm_96 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st98_fsm_97 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st99_fsm_98 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st100_fsm_99 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st101_fsm_100 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st102_fsm_101 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st103_fsm_102 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st104_fsm_103 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st105_fsm_104 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st106_fsm_105 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st107_fsm_106 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st108_fsm_107 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st109_fsm_108 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st110_fsm_109 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st111_fsm_110 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st112_fsm_111 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st113_fsm_112 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st114_fsm_113 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st115_fsm_114 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st116_fsm_115 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st117_fsm_116 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st118_fsm_117 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st119_fsm_118 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st120_fsm_119 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st121_fsm_120 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st122_fsm_121 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st123_fsm_122 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st124_fsm_123 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st125_fsm_124 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st126_fsm_125 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st127_fsm_126 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st128_fsm_127 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st129_fsm_128 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st130_fsm_129 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st131_fsm_130 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st132_fsm_131 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st133_fsm_132 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st134_fsm_133 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st135_fsm_134 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st136_fsm_135 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st137_fsm_136 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st138_fsm_137 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st139_fsm_138 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st140_fsm_139 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st141_fsm_140 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st142_fsm_141 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st143_fsm_142 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st144_fsm_143 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st145_fsm_144 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st146_fsm_145 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st147_fsm_146 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st148_fsm_147 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st149_fsm_148 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st150_fsm_149 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st151_fsm_150 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st152_fsm_151 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st153_fsm_152 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st154_fsm_153 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st155_fsm_154 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st156_fsm_155 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st157_fsm_156 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st158_fsm_157 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st159_fsm_158 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st160_fsm_159 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st161_fsm_160 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st162_fsm_161 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st163_fsm_162 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st164_fsm_163 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st165_fsm_164 = 167'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st166_fsm_165 = 167'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st167_fsm_166 = 167'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv8_0 = 8'b00000000;
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter ap_const_int64_8 = 8;
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 6;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_50 = 32'b1010000;
parameter ap_const_lv32_7A = 32'b1111010;
parameter ap_const_lv32_9C = 32'b10011100;
parameter ap_const_lv32_11 = 32'b10001;
parameter ap_const_lv32_5C = 32'b1011100;
parameter ap_const_lv32_B = 32'b1011;
parameter ap_const_lv32_56 = 32'b1010110;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv32_5B = 32'b1011011;
parameter ap_const_lv32_16 = 32'b10110;
parameter ap_const_lv32_2D = 32'b101101;
parameter ap_const_lv32_61 = 32'b1100001;
parameter ap_const_lv32_28 = 32'b101000;
parameter ap_const_lv32_73 = 32'b1110011;
parameter ap_const_lv32_4C = 32'b1001100;
parameter ap_const_lv32_99 = 32'b10011001;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_const_lv32_4E = 32'b1001110;
parameter ap_const_lv32_4F = 32'b1001111;
parameter ap_const_lv32_78 = 32'b1111000;
parameter ap_const_lv32_79 = 32'b1111001;
parameter ap_const_lv32_9B = 32'b10011011;
parameter ap_const_lv32_9D = 32'b10011101;
parameter ap_const_lv32_9E = 32'b10011110;
parameter ap_const_lv32_9F = 32'b10011111;
parameter ap_const_lv32_A0 = 32'b10100000;
parameter ap_const_lv32_A2 = 32'b10100010;
parameter ap_const_lv32_A3 = 32'b10100011;
parameter ap_const_lv32_A4 = 32'b10100100;
parameter ap_const_lv32_A5 = 32'b10100101;
parameter ap_const_lv8_1 = 8'b1;
parameter ap_const_lv32_4D = 32'b1001101;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_9A = 32'b10011010;
parameter ap_const_lv14_0 = 14'b00000000000000;
parameter ap_const_lv32_A1 = 32'b10100001;
parameter ap_const_lv9_0 = 9'b000000000;
parameter ap_const_lv3_1 = 3'b1;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv3_3 = 3'b11;
parameter ap_const_lv3_2 = 3'b10;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv32_74 = 32'b1110100;
parameter ap_const_lv64_3FF0000000000000 = 64'b11111111110000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_C = 32'b1100;
parameter ap_const_lv32_12 = 32'b10010;
parameter ap_const_lv32_29 = 32'b101001;
parameter ap_const_lv32_57 = 32'b1010111;
parameter ap_const_lv32_5D = 32'b1011101;
parameter ap_const_lv32_2E = 32'b101110;
parameter ap_const_lv32_7B = 32'b1111011;
parameter ap_const_lv32_62 = 32'b1100010;
parameter ap_const_lv8_2 = 8'b10;
parameter ap_const_lv8_3 = 8'b11;
parameter ap_const_lv15_23 = 15'b100011;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_const_lv9_23 = 9'b100011;
parameter ap_const_lv9_1FF = 9'b111111111;
parameter ap_const_lv16_23 = 16'b100011;
parameter ap_const_lv9_1FE = 9'b111111110;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv64_8000000000000000 = 64'b1000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv8_4 = 8'b100;
parameter ap_const_lv32_34 = 32'b110100;
parameter ap_const_lv32_3E = 32'b111110;
parameter ap_const_lv11_7FF = 11'b11111111111;
parameter ap_const_lv52_0 = 52'b0000000000000000000000000000000000000000000000000000;
parameter ap_const_lv14_23 = 14'b100011;
parameter ap_const_lv2_3 = 2'b11;
parameter ap_const_lv9_1 = 9'b1;
parameter ap_const_lv14_5 = 14'b101;
parameter ap_const_lv14_2 = 14'b10;
parameter ap_const_lv32_A6 = 32'b10100110;
parameter ap_const_lv5_2 = 5'b10;
parameter ap_true = 1'b1;
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (C_S_AXI_AXILITES_DATA_WIDTH / ap_const_int64_8);
parameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8);
input ap_clk;
input ap_rst_n;
input [7:0] P_config_V_TDATA;
input P_config_V_TVALID;
output P_config_V_TREADY;
input [63:0] P_WandB_TDATA;
input P_WandB_TVALID;
output P_WandB_TREADY;
output [63:0] P_uOut_TDATA;
output P_uOut_TVALID;
input P_uOut_TREADY;
input [63:0] P_netIn_TDATA;
input P_netIn_TVALID;
output P_netIn_TREADY;
output [7:0] P_netOut_V_TDATA;
output P_netOut_V_TVALID;
input P_netOut_V_TREADY;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_WDATA;
input [C_S_AXI_AXILITES_WSTRB_WIDTH - 1 : 0] s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_RDATA;
output [1:0] s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0] s_axi_AXILiteS_BRESP;
output interrupt;
reg P_config_V_TREADY;
reg P_WandB_TREADY;
reg P_uOut_TVALID;
reg P_netIn_TREADY;
reg P_netOut_V_TVALID;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [166:0] ap_CS_fsm = 167'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_185;
reg ap_ready;
wire [7:0] P_mode_V;
reg [7:0] ST_numLayer_V = 8'b00000000;
reg [7:0] ST_layerSize_V_0 = 8'b00000000;
reg [7:0] ST_layerSize_V_3 = 8'b00000000;
reg [7:0] ST_layerSize_V_1 = 8'b00000000;
reg [7:0] ST_layerSize_V_2 = 8'b00000000;
reg [12:0] ST_WandB_address0;
reg ST_WandB_ce0;
reg ST_WandB_we0;
wire [63:0] ST_WandB_d0;
wire [63:0] ST_WandB_q0;
wire [7:0] ap_return;
wire feedforward_AXILiteS_s_axi_U_ap_dummy_ce;
wire [63:0] p_uOut_q0;
reg [63:0] reg_578;
reg ap_sig_cseq_ST_st6_fsm_5;
reg ap_sig_bdd_268;
reg ap_sig_cseq_ST_st81_fsm_80;
reg ap_sig_bdd_275;
reg ap_sig_cseq_ST_st123_fsm_122;
reg ap_sig_bdd_283;
reg ap_sig_cseq_ST_st157_fsm_156;
reg ap_sig_bdd_291;
reg [63:0] reg_585;
reg ap_sig_cseq_ST_st18_fsm_17;
reg ap_sig_bdd_300;
reg ap_sig_cseq_ST_st93_fsm_92;
reg ap_sig_bdd_309;
wire [63:0] grp_fu_543_p2;
reg [63:0] reg_591;
reg ap_sig_cseq_ST_st12_fsm_11;
reg ap_sig_bdd_319;
reg ap_sig_cseq_ST_st87_fsm_86;
reg ap_sig_bdd_326;
wire [63:0] grp_fu_535_p2;
reg ap_sig_cseq_ST_st17_fsm_16;
reg ap_sig_bdd_336;
reg ap_sig_cseq_ST_st92_fsm_91;
reg ap_sig_bdd_343;
reg [63:0] reg_602;
reg ap_sig_cseq_ST_st23_fsm_22;
reg ap_sig_bdd_352;
reg ap_sig_cseq_ST_st46_fsm_45;
reg ap_sig_bdd_359;
reg ap_sig_cseq_ST_st98_fsm_97;
reg ap_sig_bdd_367;
wire [63:0] grp_fu_557_p2;
reg [63:0] reg_608;
reg ap_sig_cseq_ST_st41_fsm_40;
reg ap_sig_bdd_377;
reg ap_sig_cseq_ST_st116_fsm_115;
reg ap_sig_bdd_384;
wire [63:0] grp_fu_547_p2;
reg [63:0] reg_615;
reg ap_sig_cseq_ST_st77_fsm_76;
reg ap_sig_bdd_394;
reg ap_sig_cseq_ST_st154_fsm_153;
reg ap_sig_bdd_401;
reg [7:0] P_mode_V_read_reg_1453;
wire [0:0] tmp_fu_620_p2;
reg ap_sig_bdd_414;
reg [7:0] ST_numLayer_V_load_reg_1461;
reg [7:0] ST_layerSize_V_0_load_reg_1472;
wire [0:0] tmp_1_fu_630_p2;
reg [7:0] P_config_V_read_reg_1477;
wire [7:0] i_8_fu_647_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_435;
wire [0:0] exitcond1_fu_642_p2;
reg ap_sig_bdd_441;
wire [31:0] tmp_59_cast_fu_673_p1;
reg [31:0] tmp_59_cast_reg_1493;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_451;
wire [0:0] tmp_7_fu_658_p2;
wire [1:0] tmp_24_fu_677_p1;
reg [1:0] tmp_24_reg_1498;
wire [8:0] tmp_29_fu_691_p2;
reg [8:0] tmp_29_reg_1503;
wire [1:0] tmp_31_fu_697_p1;
reg [1:0] tmp_31_reg_1508;
wire [8:0] tmp_36_fu_720_p1;
reg [8:0] tmp_36_reg_1513;
wire signed [32:0] tmp_61_cast_fu_724_p1;
reg signed [32:0] tmp_61_cast_reg_1520;
wire [1:0] tmp_39_fu_728_p1;
reg [1:0] tmp_39_reg_1525;
wire [8:0] tmp_41_fu_738_p2;
reg [8:0] tmp_41_reg_1530;
wire [1:0] tmp_42_fu_744_p1;
reg [1:0] tmp_42_reg_1535;
wire [31:0] j_5_fu_771_p2;
reg [31:0] j_5_reg_1543;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_481;
wire [7:0] tmp_20_fu_777_p6;
reg [7:0] tmp_20_reg_1548;
wire [0:0] tmp_16_fu_765_p2;
wire [13:0] tmp_54_fu_824_p2;
reg [13:0] tmp_54_reg_1554;
reg [7:0] p_uOut_addr_1_reg_1560;
wire [7:0] i_10_fu_830_p2;
wire [7:0] k_3_fu_841_p2;
reg [7:0] k_3_reg_1573;
reg ap_sig_cseq_ST_st5_fsm_4;
reg ap_sig_bdd_503;
wire [0:0] exitcond3_fu_836_p2;
wire [63:0] tmp_25_fu_898_p1;
reg ap_sig_cseq_ST_st24_fsm_23;
reg ap_sig_bdd_523;
wire [7:0] tmp_17_fu_903_p6;
reg [7:0] tmp_17_reg_1598;
reg ap_sig_cseq_ST_st79_fsm_78;
reg ap_sig_bdd_532;
wire [31:0] i_12_fu_926_p2;
reg [31:0] i_12_reg_1607;
wire [7:0] tmp_22_fu_932_p6;
reg [7:0] tmp_22_reg_1612;
wire [0:0] tmp_19_fu_920_p2;
wire [13:0] tmp_58_fu_983_p2;
reg [13:0] tmp_58_reg_1618;
reg [7:0] p_uOut_addr_3_reg_1624;
wire [7:0] j_6_fu_994_p2;
reg [7:0] j_6_reg_1632;
reg ap_sig_cseq_ST_st80_fsm_79;
reg ap_sig_bdd_553;
wire [0:0] exitcond4_fu_989_p2;
reg ap_sig_cseq_ST_st121_fsm_120;
reg ap_sig_bdd_572;
wire [7:0] i_11_fu_1046_p2;
reg [7:0] i_11_reg_1660;
reg ap_sig_cseq_ST_st122_fsm_121;
reg ap_sig_bdd_581;
reg [7:0] p_uOut_addr_5_reg_1665;
wire [0:0] exitcond5_fu_1041_p2;
reg ap_sig_cseq_ST_st156_fsm_155;
reg ap_sig_bdd_595;
wire [0:0] tmp_38_fu_1071_p2;
reg ap_sig_ioackin_P_netOut_V_TREADY;
wire [63:0] p_uOut_q1;
reg [63:0] p_uOut_load_4_reg_1686;
wire [0:0] tmp_51_fu_1181_p2;
reg [0:0] tmp_51_reg_1692;
reg ap_sig_cseq_ST_st158_fsm_157;
reg ap_sig_bdd_617;
wire [7:0] p_netOut_V_1_fu_1187_p3;
reg ap_sig_cseq_ST_st159_fsm_158;
reg ap_sig_bdd_626;
wire [7:0] i_15_fu_1194_p2;
wire [8:0] tmp_66_fu_1200_p1;
reg [8:0] tmp_66_reg_1707;
reg ap_sig_cseq_ST_st160_fsm_159;
reg ap_sig_bdd_637;
wire [13:0] next_mul_fu_1204_p2;
reg [13:0] next_mul_reg_1712;
wire [7:0] i_14_fu_1215_p2;
reg [7:0] i_14_reg_1720;
wire [7:0] tmp_40_fu_1225_p6;
reg [7:0] tmp_40_reg_1725;
wire [0:0] exitcond6_fu_1210_p2;
wire [7:0] j_7_fu_1244_p2;
reg [7:0] j_7_reg_1733;
reg ap_sig_cseq_ST_st161_fsm_160;
reg ap_sig_bdd_655;
wire [0:0] exitcond_fu_1239_p2;
wire [13:0] tmp_s_fu_1273_p2;
reg [13:0] tmp_s_reg_1746;
reg ap_sig_cseq_ST_st163_fsm_162;
reg ap_sig_bdd_669;
wire [0:0] tmp_8_fu_1264_p2;
wire [7:0] ST_layerSize_V_load_1_phi_fu_1303_p3;
reg [7:0] ST_layerSize_V_load_1_phi_reg_1751;
wire [8:0] tmp_10_fu_1335_p2;
reg [8:0] tmp_10_reg_1756;
wire [7:0] j_4_fu_1346_p2;
reg [7:0] j_4_reg_1764;
reg ap_sig_cseq_ST_st164_fsm_163;
reg ap_sig_bdd_686;
wire [13:0] tmp_21_fu_1373_p2;
reg [13:0] tmp_21_reg_1769;
wire [0:0] exitcond2_fu_1341_p2;
wire [7:0] i_9_fu_1379_p2;
wire [8:0] k_2_fu_1404_p2;
reg ap_sig_cseq_ST_st165_fsm_164;
reg ap_sig_bdd_704;
wire [0:0] exitcond8_fu_1399_p2;
reg ap_sig_bdd_710;
wire [7:0] i_7_fu_1415_p2;
reg ap_sig_cseq_ST_st166_fsm_165;
reg ap_sig_bdd_720;
wire [0:0] exitcond7_fu_1410_p2;
reg ap_sig_bdd_725;
reg [7:0] p_uOut_address0;
reg p_uOut_ce0;
reg p_uOut_we0;
reg [63:0] p_uOut_d0;
reg [7:0] p_uOut_address1;
reg p_uOut_ce1;
reg [7:0] i_2_reg_297;
reg [7:0] i_3_reg_308;
reg [31:0] j_1_reg_320;
reg ap_sig_cseq_ST_st78_fsm_77;
reg ap_sig_bdd_754;
reg [63:0] sum_reg_331;
reg [7:0] k_1_reg_343;
reg [63:0] sumsoft_reg_354;
reg [31:0] i_4_reg_366;
reg [63:0] sum_1_reg_377;
reg [7:0] j_2_reg_389;
reg [7:0] i_5_reg_400;
reg ap_sig_cseq_ST_st155_fsm_154;
reg ap_sig_bdd_776;
reg [7:0] p_s_reg_411;
wire [0:0] tmp_35_fu_1066_p2;
reg [7:0] p_netOut_V_reg_424;
reg [7:0] i_6_reg_436;
reg [13:0] phi_mul_reg_447;
reg [7:0] j_3_reg_458;
reg ap_sig_cseq_ST_st162_fsm_161;
reg ap_sig_bdd_805;
reg ap_sig_ioackin_P_uOut_TREADY;
reg [7:0] i_1_reg_469;
reg [7:0] j_reg_481;
reg [8:0] k_reg_492;
reg [7:0] i_reg_503;
reg [2:0] agg_result_V_reg_514;
wire [63:0] tmp_6_fu_653_p1;
wire signed [63:0] tmp_64_cast_fu_795_p1;
wire [63:0] tmp_73_cast_fu_860_p1;
wire signed [63:0] tmp_74_cast_fu_870_p1;
wire [63:0] tmp_72_cast_fu_883_p1;
wire signed [63:0] tmp_68_cast_fu_954_p1;
wire [63:0] tmp_76_cast_fu_1013_p1;
wire signed [63:0] tmp_77_cast_fu_1023_p1;
wire [63:0] tmp_75_cast_fu_1036_p1;
wire signed [63:0] tmp_78_cast_fu_1061_p1;
wire signed [63:0] tmp_80_cast_fu_1085_p1;
wire signed [63:0] tmp_81_cast_fu_1099_p1;
wire [63:0] tmp_82_cast_fu_1259_p1;
wire [63:0] tmp_63_cast_fu_1394_p1;
wire [1:0] tmp_3_fu_1421_p1;
reg ap_reg_ioackin_P_netOut_V_TREADY = 1'b0;
reg ap_reg_ioackin_P_uOut_TREADY = 1'b0;
reg ap_sig_cseq_ST_st117_fsm_116;
reg ap_sig_bdd_929;
reg [63:0] grp_fu_535_p0;
reg [63:0] grp_fu_535_p1;
reg ap_sig_cseq_ST_st13_fsm_12;
reg ap_sig_bdd_954;
reg ap_sig_cseq_ST_st19_fsm_18;
reg ap_sig_bdd_961;
reg ap_sig_cseq_ST_st42_fsm_41;
reg ap_sig_bdd_969;
reg ap_sig_cseq_ST_st88_fsm_87;
reg ap_sig_bdd_976;
reg ap_sig_cseq_ST_st94_fsm_93;
reg ap_sig_bdd_983;
reg [63:0] grp_fu_547_p0;
reg [63:0] grp_fu_547_p1;
reg ap_sig_cseq_ST_st47_fsm_46;
reg ap_sig_bdd_1012;
reg ap_sig_cseq_ST_st124_fsm_123;
reg ap_sig_bdd_1019;
reg [63:0] grp_fu_557_p1;
reg ap_sig_cseq_ST_st99_fsm_98;
reg ap_sig_bdd_1029;
wire [7:0] tmp_23_fu_667_p1;
wire [14:0] tmp_23_fu_667_p2;
wire [7:0] tmp_4_fu_681_p2;
wire [7:0] tmp_29_fu_691_p1;
wire [8:0] lhs_V_1_cast_fu_701_p1;
wire [8:0] r_V_fu_704_p2;
wire signed [8:0] tmp_33_fu_714_p1;
wire [15:0] tmp_33_fu_714_p2;
wire signed [8:0] r_V_1_fu_732_p2;
wire [7:0] tmp_14_fu_748_p6;
wire [31:0] tmp_15_fu_761_p1;
wire [31:0] tmp_46_fu_790_p2;
wire [8:0] tmp_52_fu_800_p1;
wire [11:0] tmp_53_fu_812_p1;
wire [13:0] p_shl2_cast_fu_804_p3;
wire [13:0] p_shl3_cast_fu_816_p3;
wire [13:0] tmp_29_cast_fu_851_p1;
wire [13:0] tmp_61_fu_855_p2;
wire [8:0] tmp_29_cast1_fu_847_p1;
wire [8:0] tmp_62_fu_865_p2;
wire [13:0] tmp_24_cast_fu_875_p1;
wire [13:0] tmp_60_fu_878_p2;
wire [63:0] tmp_38_to_int_fu_888_p1;
wire [63:0] tmp_38_neg_fu_892_p2;
wire [31:0] tmp_18_fu_916_p1;
wire signed [32:0] tmp_23_cast_fu_945_p1;
wire [32:0] tmp_55_fu_949_p2;
wire [8:0] tmp_56_fu_959_p1;
wire [11:0] tmp_57_fu_971_p1;
wire [13:0] p_shl4_cast_fu_963_p3;
wire [13:0] p_shl5_cast_fu_975_p3;
wire [13:0] tmp_33_cast_fu_1004_p1;
wire [13:0] tmp_64_fu_1008_p2;
wire [8:0] tmp_33_cast1_fu_1000_p1;
wire [8:0] tmp_65_fu_1018_p2;
wire [13:0] tmp_31_cast_fu_1028_p1;
wire [13:0] tmp_63_fu_1031_p2;
wire [8:0] tmp_36_cast_fu_1052_p1;
wire [8:0] tmp_59_fu_1056_p2;
wire [8:0] tmp_41_cast_fu_1076_p1;
wire [8:0] tmp_68_fu_1080_p2;
wire [8:0] tmp_42_cast_fu_1090_p1;
wire [8:0] tmp_69_fu_1094_p2;
wire [63:0] p_uOut_load_3_to_int_fu_1104_p1;
wire [63:0] p_uOut_load_4_to_int_fu_1122_p1;
wire [10:0] tmp_43_fu_1108_p4;
wire [51:0] tmp_70_fu_1118_p1;
wire [0:0] notrhs_fu_1145_p2;
wire [0:0] notlhs_fu_1139_p2;
wire [10:0] tmp_45_fu_1125_p4;
wire [51:0] tmp_71_fu_1135_p1;
wire [0:0] notrhs1_fu_1163_p2;
wire [0:0] notlhs1_fu_1157_p2;
wire [0:0] tmp_47_fu_1151_p2;
wire [0:0] tmp_48_fu_1169_p2;
wire [0:0] tmp_49_fu_1175_p2;
wire [0:0] tmp_50_fu_553_p2;
wire [1:0] tmp_40_fu_1225_p5;
wire [8:0] tmp_52_cast_fu_1250_p1;
wire [8:0] tmp_72_fu_1254_p2;
wire [7:0] tmp_s_fu_1273_p1;
wire [1:0] tmp_5_fu_1279_p1;
wire [0:0] sel_tmp_fu_1283_p2;
wire [0:0] sel_tmp2_fu_1297_p2;
wire [7:0] sel_tmp1_fu_1289_p3;
wire [1:0] tmp_2_fu_1317_p5;
wire [7:0] tmp_2_fu_1317_p6;
wire [8:0] tmp_9_fu_1331_p1;
wire [13:0] tmp_cast_fu_1352_p1;
wire [13:0] tmp_11_fu_1356_p2;
wire [13:0] tmp_12_fu_1361_p2;
wire [13:0] tmp_13_fu_1367_p2;
wire [13:0] tmp_12_cast_fu_1385_p1;
wire [13:0] tmp_44_fu_1389_p2;
reg ap_sig_cseq_ST_st167_fsm_166;
reg ap_sig_bdd_1384;
wire grp_fu_535_ce;
wire grp_fu_543_ce;
wire grp_fu_547_ce;
wire [4:0] tmp_50_fu_553_opcode;
wire grp_fu_557_ce;
reg [166:0] ap_NS_fsm;
wire [14:0] tmp_23_fu_667_p10;
wire [8:0] tmp_29_fu_691_p10;
wire [13:0] tmp_s_fu_1273_p10;
reg ap_sig_bdd_909;
feedforward_ST_WandB #(
.DataWidth( 64 ),
.AddressRange( 5040 ),
.AddressWidth( 13 ))
ST_WandB_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( ST_WandB_address0 ),
.ce0( ST_WandB_ce0 ),
.we0( ST_WandB_we0 ),
.d0( ST_WandB_d0 ),
.q0( ST_WandB_q0 )
);
feedforward_AXILiteS_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_AXILITES_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_AXILITES_DATA_WIDTH ))
feedforward_AXILiteS_s_axi_U(
.AWVALID( s_axi_AXILiteS_AWVALID ),
.AWREADY( s_axi_AXILiteS_AWREADY ),
.AWADDR( s_axi_AXILiteS_AWADDR ),
.WVALID( s_axi_AXILiteS_WVALID ),
.WREADY( s_axi_AXILiteS_WREADY ),
.WDATA( s_axi_AXILiteS_WDATA ),
.WSTRB( s_axi_AXILiteS_WSTRB ),
.ARVALID( s_axi_AXILiteS_ARVALID ),
.ARREADY( s_axi_AXILiteS_ARREADY ),
.ARADDR( s_axi_AXILiteS_ARADDR ),
.RVALID( s_axi_AXILiteS_RVALID ),
.RREADY( s_axi_AXILiteS_RREADY ),
.RDATA( s_axi_AXILiteS_RDATA ),
.RRESP( s_axi_AXILiteS_RRESP ),
.BVALID( s_axi_AXILiteS_BVALID ),
.BREADY( s_axi_AXILiteS_BREADY ),
.BRESP( s_axi_AXILiteS_BRESP ),
.ACLK( ap_clk ),
.ARESET( ap_rst_n_inv ),
.ACLK_EN( feedforward_AXILiteS_s_axi_U_ap_dummy_ce ),
.ap_start( ap_start ),
.interrupt( interrupt ),
.ap_ready( ap_ready ),
.ap_done( ap_done ),
.ap_idle( ap_idle ),
.ap_return( ap_return ),
.P_mode_V( P_mode_V )
);
feedforward_p_uOut #(
.DataWidth( 64 ),
.AddressRange( 140 ),
.AddressWidth( 8 ))
p_uOut_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( p_uOut_address0 ),
.ce0( p_uOut_ce0 ),
.we0( p_uOut_we0 ),
.d0( p_uOut_d0 ),
.q0( p_uOut_q0 ),
.address1( p_uOut_address1 ),
.ce1( p_uOut_ce1 ),
.q1( p_uOut_q1 )
);
feedforward_dadd_64ns_64ns_64_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
feedforward_dadd_64ns_64ns_64_5_full_dsp_U0(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_535_p0 ),
.din1( grp_fu_535_p1 ),
.ce( grp_fu_535_ce ),
.dout( grp_fu_535_p2 )
);
feedforward_dmul_64ns_64ns_64_6_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 6 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
feedforward_dmul_64ns_64ns_64_6_max_dsp_U1(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( reg_578 ),
.din1( reg_585 ),
.ce( grp_fu_543_ce ),
.dout( grp_fu_543_p2 )
);
feedforward_ddiv_64ns_64ns_64_31 #(
.ID( 1 ),
.NUM_STAGE( 31 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
feedforward_ddiv_64ns_64ns_64_31_U2(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_547_p0 ),
.din1( grp_fu_547_p1 ),
.ce( grp_fu_547_ce ),
.dout( grp_fu_547_p2 )
);
feedforward_dcmp_64ns_64ns_1_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 1 ))
feedforward_dcmp_64ns_64ns_1_1_U3(
.din0( reg_578 ),
.din1( p_uOut_load_4_reg_1686 ),
.opcode( tmp_50_fu_553_opcode ),
.dout( tmp_50_fu_553_p2 )
);
feedforward_dexp_64ns_64ns_64_18_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 18 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
feedforward_dexp_64ns_64ns_64_18_full_dsp_U4(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( ap_const_lv64_0 ),
.din1( grp_fu_557_p1 ),
.ce( grp_fu_557_ce ),
.dout( grp_fu_557_p2 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U5(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_24_reg_1498 ),
.dout( tmp_14_fu_748_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U6(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_31_reg_1508 ),
.dout( tmp_20_fu_777_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U7(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_39_reg_1525 ),
.dout( tmp_17_fu_903_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U8(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_42_reg_1535 ),
.dout( tmp_22_fu_932_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U9(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_40_fu_1225_p5 ),
.dout( tmp_40_fu_1225_p6 )
);
feedforward_mux_4to1_sel2_8_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din1_WIDTH( 8 ),
.din2_WIDTH( 8 ),
.din3_WIDTH( 8 ),
.din4_WIDTH( 8 ),
.din5_WIDTH( 2 ),
.dout_WIDTH( 8 ))
feedforward_mux_4to1_sel2_8_1_U10(
.din1( ST_layerSize_V_0 ),
.din2( ST_layerSize_V_1 ),
.din3( ST_layerSize_V_2 ),
.din4( ST_layerSize_V_3 ),
.din5( tmp_2_fu_1317_p5 ),
.dout( tmp_2_fu_1317_p6 )
);
always @ (posedge ap_clk) begin : ap_ret_ap_CS_fsm
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin : ap_ret_ap_reg_ioackin_P_netOut_V_TREADY
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
end else begin
if (ap_sig_bdd_909) begin
if (~((ap_const_lv1_0 == tmp_38_fu_1071_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY))) begin
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_0;
end else if ((ap_const_logic_1 == P_netOut_V_TREADY)) begin
ap_reg_ioackin_P_netOut_V_TREADY <= ap_const_logic_1;
end
end
end
end
always @ (posedge ap_clk) begin : ap_ret_ap_reg_ioackin_P_uOut_TREADY
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st162_fsm_161)) begin
if (~(ap_const_logic_0 == ap_sig_ioackin_P_uOut_TREADY)) begin
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_0;
end else if ((ap_const_logic_1 == P_uOut_TREADY)) begin
ap_reg_ioackin_P_uOut_TREADY <= ap_const_logic_1;
end
end
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165) & ~ap_sig_bdd_725 & ~(ap_const_lv1_0 == exitcond7_fu_1410_p2))) begin
agg_result_V_reg_514 <= ap_const_lv3_2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st163_fsm_162) & (ap_const_lv1_0 == tmp_8_fu_1264_p2))) begin
agg_result_V_reg_514 <= ap_const_lv3_3;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st160_fsm_159) & ~(ap_const_lv1_0 == exitcond6_fu_1210_p2))) begin
agg_result_V_reg_514 <= ap_const_lv3_4;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155) & (ap_const_lv1_0 == tmp_38_fu_1071_p2) & ~((ap_const_lv1_0 == tmp_38_fu_1071_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)))) begin
agg_result_V_reg_514 <= ap_const_lv3_1;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & (tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414 & ~(ap_const_lv1_0 == tmp_1_fu_630_p2))) begin
i_1_reg_469 <= ap_const_lv8_1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st164_fsm_163) & ~(ap_const_lv1_0 == exitcond2_fu_1341_p2))) begin
i_1_reg_469 <= i_9_fu_1379_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & (tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414 & (ap_const_lv1_0 == tmp_1_fu_630_p2))) begin
i_2_reg_297 <= ap_const_lv8_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_642_p2) & ~ap_sig_bdd_441)) begin
i_2_reg_297 <= i_8_fu_647_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_441 & ~(ap_const_lv1_0 == exitcond1_fu_642_p2))) begin
i_3_reg_308 <= ap_const_lv8_1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & (ap_const_lv1_0 == tmp_16_fu_765_p2))) begin
i_3_reg_308 <= i_10_fu_830_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_7_fu_658_p2))) begin
i_4_reg_366 <= ap_const_lv32_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st121_fsm_120)) begin
i_4_reg_366 <= i_12_reg_1607;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) & (ap_const_lv1_0 == tmp_19_fu_920_p2))) begin
i_5_reg_400 <= ap_const_lv8_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st155_fsm_154)) begin
i_5_reg_400 <= i_11_reg_1660;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st161_fsm_160) & ~(ap_const_lv1_0 == exitcond_fu_1239_p2))) begin
i_6_reg_436 <= i_14_reg_1720;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121) & ~(ap_const_lv1_0 == exitcond5_fu_1041_p2) & ~(ap_const_lv1_0 == tmp_35_fu_1066_p2))) begin
i_6_reg_436 <= ap_const_lv8_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165) & (ap_const_lv1_0 == exitcond7_fu_1410_p2) & ~ap_sig_bdd_725)) begin
i_reg_503 <= i_7_fu_1415_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414)) begin
i_reg_503 <= ap_const_lv8_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~(ap_const_lv1_0 == tmp_7_fu_658_p2))) begin
j_1_reg_320 <= ap_const_lv32_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77)) begin
j_1_reg_320 <= j_5_reg_1543;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) & ~(ap_const_lv1_0 == tmp_19_fu_920_p2))) begin
j_2_reg_389 <= ap_const_lv8_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st92_fsm_91)) begin
j_2_reg_389 <= j_6_reg_1632;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st160_fsm_159) & (ap_const_lv1_0 == exitcond6_fu_1210_p2))) begin
j_3_reg_458 <= ap_const_lv8_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st162_fsm_161) & ~(ap_const_logic_0 == ap_sig_ioackin_P_uOut_TREADY))) begin
j_3_reg_458 <= j_7_reg_1733;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164) & ~ap_sig_bdd_710 & ~(ap_const_lv1_0 == exitcond8_fu_1399_p2))) begin
j_reg_481 <= j_4_reg_1764;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st163_fsm_162) & ~(ap_const_lv1_0 == tmp_8_fu_1264_p2))) begin
j_reg_481 <= ap_const_lv8_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(ap_const_lv1_0 == tmp_16_fu_765_p2))) begin
k_1_reg_343 <= ap_const_lv8_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16)) begin
k_1_reg_343 <= k_3_reg_1573;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st164_fsm_163) & (ap_const_lv1_0 == exitcond2_fu_1341_p2))) begin
k_reg_492 <= ap_const_lv9_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164) & (ap_const_lv1_0 == exitcond8_fu_1399_p2) & ~ap_sig_bdd_710)) begin
k_reg_492 <= k_2_fu_1404_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121) & (ap_const_lv1_0 == tmp_35_fu_1066_p2) & ~(ap_const_lv1_0 == exitcond5_fu_1041_p2))) begin
p_netOut_V_reg_424 <= ap_const_lv8_1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st159_fsm_158)) begin
p_netOut_V_reg_424 <= i_15_fu_1194_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121) & (ap_const_lv1_0 == tmp_35_fu_1066_p2) & ~(ap_const_lv1_0 == exitcond5_fu_1041_p2))) begin
p_s_reg_411 <= ap_const_lv8_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st159_fsm_158)) begin
p_s_reg_411 <= p_netOut_V_1_fu_1187_p3;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st161_fsm_160) & ~(ap_const_lv1_0 == exitcond_fu_1239_p2))) begin
phi_mul_reg_447 <= next_mul_reg_1712;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121) & ~(ap_const_lv1_0 == exitcond5_fu_1041_p2) & ~(ap_const_lv1_0 == tmp_35_fu_1066_p2))) begin
phi_mul_reg_447 <= ap_const_lv14_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) & ~(ap_const_lv1_0 == tmp_19_fu_920_p2))) begin
sum_1_reg_377 <= ap_const_lv64_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st92_fsm_91)) begin
sum_1_reg_377 <= grp_fu_535_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(ap_const_lv1_0 == tmp_16_fu_765_p2))) begin
sum_reg_331 <= ap_const_lv64_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16)) begin
sum_reg_331 <= grp_fu_535_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_7_fu_658_p2))) begin
sumsoft_reg_354 <= ap_const_lv64_0;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st121_fsm_120)) begin
sumsoft_reg_354 <= grp_fu_535_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414)) begin
P_config_V_read_reg_1477 <= P_config_V_TDATA;
ST_numLayer_V <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_414)) begin
P_mode_V_read_reg_1453 <= P_mode_V;
ST_numLayer_V_load_reg_1461 <= ST_numLayer_V;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165) & (ap_const_lv1_0 == exitcond7_fu_1410_p2) & ~ap_sig_bdd_725 & (tmp_3_fu_1421_p1 == ap_const_lv2_0))) begin
ST_layerSize_V_0 <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & (tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414 & (ap_const_lv1_0 == tmp_1_fu_630_p2))) begin
ST_layerSize_V_0_load_reg_1472 <= ST_layerSize_V_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165) & (ap_const_lv1_0 == exitcond7_fu_1410_p2) & ~ap_sig_bdd_725 & (tmp_3_fu_1421_p1 == ap_const_lv2_1))) begin
ST_layerSize_V_1 <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165) & (ap_const_lv1_0 == exitcond7_fu_1410_p2) & ~ap_sig_bdd_725 & (tmp_3_fu_1421_p1 == ap_const_lv2_2))) begin
ST_layerSize_V_2 <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165) & (ap_const_lv1_0 == exitcond7_fu_1410_p2) & ~ap_sig_bdd_725 & ~(tmp_3_fu_1421_p1 == ap_const_lv2_2) & ~(tmp_3_fu_1421_p1 == ap_const_lv2_1) & ~(tmp_3_fu_1421_p1 == ap_const_lv2_0))) begin
ST_layerSize_V_3 <= P_config_V_TDATA;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st163_fsm_162) & ~(ap_const_lv1_0 == tmp_8_fu_1264_p2))) begin
ST_layerSize_V_load_1_phi_reg_1751 <= ST_layerSize_V_load_1_phi_fu_1303_p3;
tmp_10_reg_1756 <= tmp_10_fu_1335_p2;
tmp_s_reg_1746 <= tmp_s_fu_1273_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121)) begin
i_11_reg_1660 <= i_11_fu_1046_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78)) begin
i_12_reg_1607 <= i_12_fu_926_p2;
tmp_17_reg_1598 <= tmp_17_fu_903_p6;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st160_fsm_159)) begin
i_14_reg_1720 <= i_14_fu_1215_p2;
next_mul_reg_1712 <= next_mul_fu_1204_p2;
tmp_66_reg_1707 <= tmp_66_fu_1200_p1;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st164_fsm_163)) begin
j_4_reg_1764 <= j_4_fu_1346_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) begin
j_5_reg_1543 <= j_5_fu_771_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79)) begin
j_6_reg_1632 <= j_6_fu_994_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st161_fsm_160)) begin
j_7_reg_1733 <= j_7_fu_1244_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
k_3_reg_1573 <= k_3_fu_841_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) & ~(ap_const_lv1_0 == tmp_16_fu_765_p2))) begin
p_uOut_addr_1_reg_1560 <= tmp_64_cast_fu_795_p1;
tmp_20_reg_1548 <= tmp_20_fu_777_p6;
tmp_54_reg_1554[13 : 2] <= tmp_54_fu_824_p2[13 : 2];
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78) & ~(ap_const_lv1_0 == tmp_19_fu_920_p2))) begin
p_uOut_addr_3_reg_1624 <= tmp_68_cast_fu_954_p1;
tmp_22_reg_1612 <= tmp_22_fu_932_p6;
tmp_58_reg_1618[13 : 2] <= tmp_58_fu_983_p2[13 : 2];
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121) & (ap_const_lv1_0 == exitcond5_fu_1041_p2))) begin
p_uOut_addr_5_reg_1665 <= tmp_78_cast_fu_1061_p1;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st157_fsm_156)) begin
p_uOut_load_4_reg_1686 <= p_uOut_q1;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) | (ap_const_logic_1 == ap_sig_cseq_ST_st81_fsm_80) | (ap_const_logic_1 == ap_sig_cseq_ST_st123_fsm_122) | (ap_const_logic_1 == ap_sig_cseq_ST_st157_fsm_156))) begin
reg_578 <= p_uOut_q0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) | (ap_const_logic_1 == ap_sig_cseq_ST_st81_fsm_80) | (ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17) | (ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92))) begin
reg_585 <= ST_WandB_q0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11) | (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86))) begin
reg_591 <= grp_fu_543_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st23_fsm_22) | (ap_const_logic_1 == ap_sig_cseq_ST_st46_fsm_45) | (ap_const_logic_1 == ap_sig_cseq_ST_st98_fsm_97))) begin
reg_602 <= grp_fu_535_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st41_fsm_40) | (ap_const_logic_1 == ap_sig_cseq_ST_st116_fsm_115))) begin
reg_608 <= grp_fu_557_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st77_fsm_76) | (ap_const_logic_1 == ap_sig_cseq_ST_st154_fsm_153))) begin
reg_615 <= grp_fu_547_p2;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st164_fsm_163) & (ap_const_lv1_0 == exitcond2_fu_1341_p2))) begin
tmp_21_reg_1769[13 : 2] <= tmp_21_fu_1373_p2[13 : 2];
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~(ap_const_lv1_0 == tmp_7_fu_658_p2))) begin
tmp_24_reg_1498 <= tmp_24_fu_677_p1;
tmp_29_reg_1503 <= tmp_29_fu_691_p2;
tmp_31_reg_1508 <= tmp_31_fu_697_p1;
tmp_59_cast_reg_1493[14 : 0] <= tmp_59_cast_fu_673_p1[14 : 0];
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == tmp_7_fu_658_p2))) begin
tmp_36_reg_1513 <= tmp_36_fu_720_p1;
tmp_39_reg_1525 <= tmp_39_fu_728_p1;
tmp_41_reg_1530 <= tmp_41_fu_738_p2;
tmp_42_reg_1535 <= tmp_42_fu_744_p1;
tmp_61_cast_reg_1520 <= tmp_61_cast_fu_724_p1;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st160_fsm_159) & (ap_const_lv1_0 == exitcond6_fu_1210_p2))) begin
tmp_40_reg_1725 <= tmp_40_fu_1225_p6;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st158_fsm_157)) begin
tmp_51_reg_1692 <= tmp_51_fu_1181_p2;
end
end
always @ (ap_sig_cseq_ST_st165_fsm_164 or exitcond8_fu_1399_p2 or ap_sig_bdd_710) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164) & (ap_const_lv1_0 == exitcond8_fu_1399_p2) & ~ap_sig_bdd_710)) begin
P_WandB_TREADY = ap_const_logic_1;
end else begin
P_WandB_TREADY = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st1_fsm_0 or tmp_fu_620_p2 or ap_sig_bdd_414 or ap_sig_cseq_ST_st166_fsm_165 or exitcond7_fu_1410_p2 or ap_sig_bdd_725) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414) | ((ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165) & (ap_const_lv1_0 == exitcond7_fu_1410_p2) & ~ap_sig_bdd_725))) begin
P_config_V_TREADY = ap_const_logic_1;
end else begin
P_config_V_TREADY = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or exitcond1_fu_642_p2 or ap_sig_bdd_441) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_642_p2) & ~ap_sig_bdd_441)) begin
P_netIn_TREADY = ap_const_logic_1;
end else begin
P_netIn_TREADY = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st156_fsm_155 or tmp_38_fu_1071_p2 or ap_reg_ioackin_P_netOut_V_TREADY) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155) & (ap_const_lv1_0 == tmp_38_fu_1071_p2) & (ap_const_logic_0 == ap_reg_ioackin_P_netOut_V_TREADY))) begin
P_netOut_V_TVALID = ap_const_logic_1;
end else begin
P_netOut_V_TVALID = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st162_fsm_161 or ap_reg_ioackin_P_uOut_TREADY) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st162_fsm_161) & (ap_const_logic_0 == ap_reg_ioackin_P_uOut_TREADY))) begin
P_uOut_TVALID = ap_const_logic_1;
end else begin
P_uOut_TVALID = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st5_fsm_4 or exitcond3_fu_836_p2 or ap_sig_cseq_ST_st80_fsm_79 or exitcond4_fu_989_p2 or ap_sig_cseq_ST_st165_fsm_164 or tmp_73_cast_fu_860_p1 or tmp_72_cast_fu_883_p1 or tmp_76_cast_fu_1013_p1 or tmp_75_cast_fu_1036_p1 or tmp_63_cast_fu_1394_p1) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164)) begin
ST_WandB_address0 = tmp_63_cast_fu_1394_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) & ~(ap_const_lv1_0 == exitcond4_fu_989_p2))) begin
ST_WandB_address0 = tmp_75_cast_fu_1036_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) & (ap_const_lv1_0 == exitcond4_fu_989_p2))) begin
ST_WandB_address0 = tmp_76_cast_fu_1013_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & ~(ap_const_lv1_0 == exitcond3_fu_836_p2))) begin
ST_WandB_address0 = tmp_72_cast_fu_883_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == exitcond3_fu_836_p2))) begin
ST_WandB_address0 = tmp_73_cast_fu_860_p1;
end else begin
ST_WandB_address0 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st5_fsm_4 or exitcond3_fu_836_p2 or ap_sig_cseq_ST_st80_fsm_79 or exitcond4_fu_989_p2 or ap_sig_cseq_ST_st165_fsm_164 or ap_sig_bdd_710) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & (ap_const_lv1_0 == exitcond3_fu_836_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) & ~(ap_const_lv1_0 == exitcond3_fu_836_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) & (ap_const_lv1_0 == exitcond4_fu_989_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) & ~(ap_const_lv1_0 == exitcond4_fu_989_p2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164) & ~ap_sig_bdd_710))) begin
ST_WandB_ce0 = ap_const_logic_1;
end else begin
ST_WandB_ce0 = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st165_fsm_164 or exitcond8_fu_1399_p2 or ap_sig_bdd_710) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164) & (ap_const_lv1_0 == exitcond8_fu_1399_p2) & ~ap_sig_bdd_710)) begin
ST_WandB_we0 = ap_const_logic_1;
end else begin
ST_WandB_we0 = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st167_fsm_166) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st167_fsm_166)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0) begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st167_fsm_166) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st167_fsm_166)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_384) begin
if (ap_sig_bdd_384) begin
ap_sig_cseq_ST_st116_fsm_115 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st116_fsm_115 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_929) begin
if (ap_sig_bdd_929) begin
ap_sig_cseq_ST_st117_fsm_116 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st117_fsm_116 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_572) begin
if (ap_sig_bdd_572) begin
ap_sig_cseq_ST_st121_fsm_120 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st121_fsm_120 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_581) begin
if (ap_sig_bdd_581) begin
ap_sig_cseq_ST_st122_fsm_121 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st122_fsm_121 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_283) begin
if (ap_sig_bdd_283) begin
ap_sig_cseq_ST_st123_fsm_122 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st123_fsm_122 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_1019) begin
if (ap_sig_bdd_1019) begin
ap_sig_cseq_ST_st124_fsm_123 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st124_fsm_123 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_319) begin
if (ap_sig_bdd_319) begin
ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_954) begin
if (ap_sig_bdd_954) begin
ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_401) begin
if (ap_sig_bdd_401) begin
ap_sig_cseq_ST_st154_fsm_153 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st154_fsm_153 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_776) begin
if (ap_sig_bdd_776) begin
ap_sig_cseq_ST_st155_fsm_154 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st155_fsm_154 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_595) begin
if (ap_sig_bdd_595) begin
ap_sig_cseq_ST_st156_fsm_155 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st156_fsm_155 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_291) begin
if (ap_sig_bdd_291) begin
ap_sig_cseq_ST_st157_fsm_156 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st157_fsm_156 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_617) begin
if (ap_sig_bdd_617) begin
ap_sig_cseq_ST_st158_fsm_157 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st158_fsm_157 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_626) begin
if (ap_sig_bdd_626) begin
ap_sig_cseq_ST_st159_fsm_158 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st159_fsm_158 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_637) begin
if (ap_sig_bdd_637) begin
ap_sig_cseq_ST_st160_fsm_159 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st160_fsm_159 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_655) begin
if (ap_sig_bdd_655) begin
ap_sig_cseq_ST_st161_fsm_160 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st161_fsm_160 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_805) begin
if (ap_sig_bdd_805) begin
ap_sig_cseq_ST_st162_fsm_161 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st162_fsm_161 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_669) begin
if (ap_sig_bdd_669) begin
ap_sig_cseq_ST_st163_fsm_162 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st163_fsm_162 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_686) begin
if (ap_sig_bdd_686) begin
ap_sig_cseq_ST_st164_fsm_163 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st164_fsm_163 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_704) begin
if (ap_sig_bdd_704) begin
ap_sig_cseq_ST_st165_fsm_164 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st165_fsm_164 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_720) begin
if (ap_sig_bdd_720) begin
ap_sig_cseq_ST_st166_fsm_165 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st166_fsm_165 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_1384) begin
if (ap_sig_bdd_1384) begin
ap_sig_cseq_ST_st167_fsm_166 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st167_fsm_166 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_336) begin
if (ap_sig_bdd_336) begin
ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_300) begin
if (ap_sig_bdd_300) begin
ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_961) begin
if (ap_sig_bdd_961) begin
ap_sig_cseq_ST_st19_fsm_18 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st19_fsm_18 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_185) begin
if (ap_sig_bdd_185) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_352) begin
if (ap_sig_bdd_352) begin
ap_sig_cseq_ST_st23_fsm_22 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st23_fsm_22 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_523) begin
if (ap_sig_bdd_523) begin
ap_sig_cseq_ST_st24_fsm_23 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st24_fsm_23 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_435) begin
if (ap_sig_bdd_435) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_451) begin
if (ap_sig_bdd_451) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_377) begin
if (ap_sig_bdd_377) begin
ap_sig_cseq_ST_st41_fsm_40 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st41_fsm_40 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_969) begin
if (ap_sig_bdd_969) begin
ap_sig_cseq_ST_st42_fsm_41 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st42_fsm_41 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_359) begin
if (ap_sig_bdd_359) begin
ap_sig_cseq_ST_st46_fsm_45 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st46_fsm_45 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_1012) begin
if (ap_sig_bdd_1012) begin
ap_sig_cseq_ST_st47_fsm_46 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st47_fsm_46 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_481) begin
if (ap_sig_bdd_481) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_503) begin
if (ap_sig_bdd_503) begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_268) begin
if (ap_sig_bdd_268) begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_394) begin
if (ap_sig_bdd_394) begin
ap_sig_cseq_ST_st77_fsm_76 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st77_fsm_76 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_754) begin
if (ap_sig_bdd_754) begin
ap_sig_cseq_ST_st78_fsm_77 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st78_fsm_77 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_532) begin
if (ap_sig_bdd_532) begin
ap_sig_cseq_ST_st79_fsm_78 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st79_fsm_78 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_553) begin
if (ap_sig_bdd_553) begin
ap_sig_cseq_ST_st80_fsm_79 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st80_fsm_79 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_275) begin
if (ap_sig_bdd_275) begin
ap_sig_cseq_ST_st81_fsm_80 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st81_fsm_80 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_326) begin
if (ap_sig_bdd_326) begin
ap_sig_cseq_ST_st87_fsm_86 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st87_fsm_86 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_976) begin
if (ap_sig_bdd_976) begin
ap_sig_cseq_ST_st88_fsm_87 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st88_fsm_87 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_343) begin
if (ap_sig_bdd_343) begin
ap_sig_cseq_ST_st92_fsm_91 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st92_fsm_91 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_309) begin
if (ap_sig_bdd_309) begin
ap_sig_cseq_ST_st93_fsm_92 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st93_fsm_92 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_983) begin
if (ap_sig_bdd_983) begin
ap_sig_cseq_ST_st94_fsm_93 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st94_fsm_93 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_367) begin
if (ap_sig_bdd_367) begin
ap_sig_cseq_ST_st98_fsm_97 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st98_fsm_97 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_1029) begin
if (ap_sig_bdd_1029) begin
ap_sig_cseq_ST_st99_fsm_98 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st99_fsm_98 = ap_const_logic_0;
end
end
always @ (P_netOut_V_TREADY or ap_reg_ioackin_P_netOut_V_TREADY) begin
if ((ap_const_logic_0 == ap_reg_ioackin_P_netOut_V_TREADY)) begin
ap_sig_ioackin_P_netOut_V_TREADY = P_netOut_V_TREADY;
end else begin
ap_sig_ioackin_P_netOut_V_TREADY = ap_const_logic_1;
end
end
always @ (P_uOut_TREADY or ap_reg_ioackin_P_uOut_TREADY) begin
if ((ap_const_logic_0 == ap_reg_ioackin_P_uOut_TREADY)) begin
ap_sig_ioackin_P_uOut_TREADY = P_uOut_TREADY;
end else begin
ap_sig_ioackin_P_uOut_TREADY = ap_const_logic_1;
end
end
always @ (reg_608 or sum_reg_331 or sumsoft_reg_354 or sum_1_reg_377 or ap_sig_cseq_ST_st117_fsm_116 or ap_sig_cseq_ST_st13_fsm_12 or ap_sig_cseq_ST_st19_fsm_18 or ap_sig_cseq_ST_st42_fsm_41 or ap_sig_cseq_ST_st88_fsm_87 or ap_sig_cseq_ST_st94_fsm_93) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st117_fsm_116)) begin
grp_fu_535_p0 = sumsoft_reg_354;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87) | (ap_const_logic_1 == ap_sig_cseq_ST_st94_fsm_93))) begin
grp_fu_535_p0 = sum_1_reg_377;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st42_fsm_41)) begin
grp_fu_535_p0 = reg_608;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12) | (ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18))) begin
grp_fu_535_p0 = sum_reg_331;
end else begin
grp_fu_535_p0 = 'bx;
end
end
always @ (reg_585 or reg_591 or reg_608 or ap_sig_cseq_ST_st117_fsm_116 or ap_sig_cseq_ST_st13_fsm_12 or ap_sig_cseq_ST_st19_fsm_18 or ap_sig_cseq_ST_st42_fsm_41 or ap_sig_cseq_ST_st88_fsm_87 or ap_sig_cseq_ST_st94_fsm_93) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st117_fsm_116)) begin
grp_fu_535_p1 = reg_608;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st42_fsm_41)) begin
grp_fu_535_p1 = ap_const_lv64_3FF0000000000000;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18) | (ap_const_logic_1 == ap_sig_cseq_ST_st94_fsm_93))) begin
grp_fu_535_p1 = reg_585;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12) | (ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87))) begin
grp_fu_535_p1 = reg_591;
end else begin
grp_fu_535_p1 = 'bx;
end
end
always @ (reg_578 or ap_sig_cseq_ST_st47_fsm_46 or ap_sig_cseq_ST_st124_fsm_123) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st124_fsm_123)) begin
grp_fu_547_p0 = reg_578;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st47_fsm_46)) begin
grp_fu_547_p0 = ap_const_lv64_3FF0000000000000;
end else begin
grp_fu_547_p0 = 'bx;
end
end
always @ (reg_602 or sumsoft_reg_354 or ap_sig_cseq_ST_st47_fsm_46 or ap_sig_cseq_ST_st124_fsm_123) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st124_fsm_123)) begin
grp_fu_547_p1 = sumsoft_reg_354;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st47_fsm_46)) begin
grp_fu_547_p1 = reg_602;
end else begin
grp_fu_547_p1 = 'bx;
end
end
always @ (reg_602 or tmp_25_fu_898_p1 or ap_sig_cseq_ST_st24_fsm_23 or ap_sig_cseq_ST_st99_fsm_98) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st99_fsm_98)) begin
grp_fu_557_p1 = reg_602;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st24_fsm_23)) begin
grp_fu_557_p1 = tmp_25_fu_898_p1;
end else begin
grp_fu_557_p1 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or p_uOut_addr_1_reg_1560 or ap_sig_cseq_ST_st5_fsm_4 or p_uOut_addr_3_reg_1624 or ap_sig_cseq_ST_st80_fsm_79 or ap_sig_cseq_ST_st122_fsm_121 or p_uOut_addr_5_reg_1665 or ap_sig_cseq_ST_st156_fsm_155 or ap_sig_cseq_ST_st78_fsm_77 or ap_sig_cseq_ST_st155_fsm_154 or tmp_6_fu_653_p1 or tmp_74_cast_fu_870_p1 or tmp_77_cast_fu_1023_p1 or tmp_78_cast_fu_1061_p1 or tmp_80_cast_fu_1085_p1 or ap_sig_cseq_ST_st117_fsm_116) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st155_fsm_154)) begin
p_uOut_address0 = p_uOut_addr_5_reg_1665;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st117_fsm_116)) begin
p_uOut_address0 = p_uOut_addr_3_reg_1624;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77)) begin
p_uOut_address0 = p_uOut_addr_1_reg_1560;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
p_uOut_address0 = tmp_6_fu_653_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155)) begin
p_uOut_address0 = tmp_80_cast_fu_1085_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121)) begin
p_uOut_address0 = tmp_78_cast_fu_1061_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79)) begin
p_uOut_address0 = tmp_77_cast_fu_1023_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) begin
p_uOut_address0 = tmp_74_cast_fu_870_p1;
end else begin
p_uOut_address0 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st156_fsm_155 or ap_sig_cseq_ST_st161_fsm_160 or tmp_81_cast_fu_1099_p1 or tmp_82_cast_fu_1259_p1) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st161_fsm_160)) begin
p_uOut_address1 = tmp_82_cast_fu_1259_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155)) begin
p_uOut_address1 = tmp_81_cast_fu_1099_p1;
end else begin
p_uOut_address1 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or ap_sig_bdd_441 or ap_sig_cseq_ST_st5_fsm_4 or ap_sig_cseq_ST_st80_fsm_79 or ap_sig_cseq_ST_st122_fsm_121 or ap_sig_cseq_ST_st156_fsm_155 or tmp_38_fu_1071_p2 or ap_sig_ioackin_P_netOut_V_TREADY or ap_sig_cseq_ST_st78_fsm_77 or ap_sig_cseq_ST_st155_fsm_154 or ap_sig_cseq_ST_st117_fsm_116) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_441) | (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4) | (ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79) | (ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121) | ((ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155) & ~((ap_const_lv1_0 == tmp_38_fu_1071_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY))) | (ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77) | (ap_const_logic_1 == ap_sig_cseq_ST_st155_fsm_154) | (ap_const_logic_1 == ap_sig_cseq_ST_st117_fsm_116))) begin
p_uOut_ce0 = ap_const_logic_1;
end else begin
p_uOut_ce0 = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st156_fsm_155 or tmp_38_fu_1071_p2 or ap_sig_ioackin_P_netOut_V_TREADY or ap_sig_cseq_ST_st161_fsm_160) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155) & ~((ap_const_lv1_0 == tmp_38_fu_1071_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY))) | (ap_const_logic_1 == ap_sig_cseq_ST_st161_fsm_160))) begin
p_uOut_ce1 = ap_const_logic_1;
end else begin
p_uOut_ce1 = ap_const_logic_0;
end
end
always @ (P_netIn_TDATA or reg_608 or reg_615 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_cseq_ST_st78_fsm_77 or ap_sig_cseq_ST_st155_fsm_154 or ap_sig_cseq_ST_st117_fsm_116) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st117_fsm_116)) begin
p_uOut_d0 = reg_608;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77) | (ap_const_logic_1 == ap_sig_cseq_ST_st155_fsm_154))) begin
p_uOut_d0 = reg_615;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
p_uOut_d0 = P_netIn_TDATA;
end else begin
p_uOut_d0 = 'bx;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or exitcond1_fu_642_p2 or ap_sig_bdd_441 or ap_sig_cseq_ST_st78_fsm_77 or ap_sig_cseq_ST_st155_fsm_154 or ap_sig_cseq_ST_st117_fsm_116) begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond1_fu_642_p2) & ~ap_sig_bdd_441) | (ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77) | (ap_const_logic_1 == ap_sig_cseq_ST_st155_fsm_154) | (ap_const_logic_1 == ap_sig_cseq_ST_st117_fsm_116))) begin
p_uOut_we0 = ap_const_logic_1;
end else begin
p_uOut_we0 = ap_const_logic_0;
end
end
always @ (ap_CS_fsm or tmp_fu_620_p2 or ap_sig_bdd_414 or tmp_1_fu_630_p2 or exitcond1_fu_642_p2 or ap_sig_bdd_441 or tmp_7_fu_658_p2 or tmp_16_fu_765_p2 or exitcond3_fu_836_p2 or tmp_19_fu_920_p2 or exitcond4_fu_989_p2 or exitcond5_fu_1041_p2 or tmp_38_fu_1071_p2 or ap_sig_ioackin_P_netOut_V_TREADY or exitcond6_fu_1210_p2 or exitcond_fu_1239_p2 or tmp_8_fu_1264_p2 or exitcond2_fu_1341_p2 or exitcond8_fu_1399_p2 or ap_sig_bdd_710 or exitcond7_fu_1410_p2 or ap_sig_bdd_725 or tmp_35_fu_1066_p2 or ap_sig_ioackin_P_uOut_TREADY) begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if ((~(tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414)) begin
ap_NS_fsm = ap_ST_st166_fsm_165;
end else if (((tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414 & (ap_const_lv1_0 == tmp_1_fu_630_p2))) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if (((tmp_fu_620_p2 == ap_const_lv1_0) & ~ap_sig_bdd_414 & ~(ap_const_lv1_0 == tmp_1_fu_630_p2))) begin
ap_NS_fsm = ap_ST_st163_fsm_162;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (((ap_const_lv1_0 == exitcond1_fu_642_p2) & ~ap_sig_bdd_441)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if ((~ap_sig_bdd_441 & ~(ap_const_lv1_0 == exitcond1_fu_642_p2))) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
if ((ap_const_lv1_0 == tmp_7_fu_658_p2)) begin
ap_NS_fsm = ap_ST_st79_fsm_78;
end else begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
end
ap_ST_st4_fsm_3 :
begin
if ((ap_const_lv1_0 == tmp_16_fu_765_p2)) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
end
ap_ST_st5_fsm_4 :
begin
if (~(ap_const_lv1_0 == exitcond3_fu_836_p2)) begin
ap_NS_fsm = ap_ST_st18_fsm_17;
end else begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end
end
ap_ST_st6_fsm_5 :
begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end
ap_ST_st7_fsm_6 :
begin
ap_NS_fsm = ap_ST_st8_fsm_7;
end
ap_ST_st8_fsm_7 :
begin
ap_NS_fsm = ap_ST_st9_fsm_8;
end
ap_ST_st9_fsm_8 :
begin
ap_NS_fsm = ap_ST_st10_fsm_9;
end
ap_ST_st10_fsm_9 :
begin
ap_NS_fsm = ap_ST_st11_fsm_10;
end
ap_ST_st11_fsm_10 :
begin
ap_NS_fsm = ap_ST_st12_fsm_11;
end
ap_ST_st12_fsm_11 :
begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st13_fsm_12 :
begin
ap_NS_fsm = ap_ST_st14_fsm_13;
end
ap_ST_st14_fsm_13 :
begin
ap_NS_fsm = ap_ST_st15_fsm_14;
end
ap_ST_st15_fsm_14 :
begin
ap_NS_fsm = ap_ST_st16_fsm_15;
end
ap_ST_st16_fsm_15 :
begin
ap_NS_fsm = ap_ST_st17_fsm_16;
end
ap_ST_st17_fsm_16 :
begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
ap_ST_st18_fsm_17 :
begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end
ap_ST_st19_fsm_18 :
begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end
ap_ST_st20_fsm_19 :
begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end
ap_ST_st21_fsm_20 :
begin
ap_NS_fsm = ap_ST_st22_fsm_21;
end
ap_ST_st22_fsm_21 :
begin
ap_NS_fsm = ap_ST_st23_fsm_22;
end
ap_ST_st23_fsm_22 :
begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end
ap_ST_st24_fsm_23 :
begin
ap_NS_fsm = ap_ST_st25_fsm_24;
end
ap_ST_st25_fsm_24 :
begin
ap_NS_fsm = ap_ST_st26_fsm_25;
end
ap_ST_st26_fsm_25 :
begin
ap_NS_fsm = ap_ST_st27_fsm_26;
end
ap_ST_st27_fsm_26 :
begin
ap_NS_fsm = ap_ST_st28_fsm_27;
end
ap_ST_st28_fsm_27 :
begin
ap_NS_fsm = ap_ST_st29_fsm_28;
end
ap_ST_st29_fsm_28 :
begin
ap_NS_fsm = ap_ST_st30_fsm_29;
end
ap_ST_st30_fsm_29 :
begin
ap_NS_fsm = ap_ST_st31_fsm_30;
end
ap_ST_st31_fsm_30 :
begin
ap_NS_fsm = ap_ST_st32_fsm_31;
end
ap_ST_st32_fsm_31 :
begin
ap_NS_fsm = ap_ST_st33_fsm_32;
end
ap_ST_st33_fsm_32 :
begin
ap_NS_fsm = ap_ST_st34_fsm_33;
end
ap_ST_st34_fsm_33 :
begin
ap_NS_fsm = ap_ST_st35_fsm_34;
end
ap_ST_st35_fsm_34 :
begin
ap_NS_fsm = ap_ST_st36_fsm_35;
end
ap_ST_st36_fsm_35 :
begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end
ap_ST_st37_fsm_36 :
begin
ap_NS_fsm = ap_ST_st38_fsm_37;
end
ap_ST_st38_fsm_37 :
begin
ap_NS_fsm = ap_ST_st39_fsm_38;
end
ap_ST_st39_fsm_38 :
begin
ap_NS_fsm = ap_ST_st40_fsm_39;
end
ap_ST_st40_fsm_39 :
begin
ap_NS_fsm = ap_ST_st41_fsm_40;
end
ap_ST_st41_fsm_40 :
begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end
ap_ST_st42_fsm_41 :
begin
ap_NS_fsm = ap_ST_st43_fsm_42;
end
ap_ST_st43_fsm_42 :
begin
ap_NS_fsm = ap_ST_st44_fsm_43;
end
ap_ST_st44_fsm_43 :
begin
ap_NS_fsm = ap_ST_st45_fsm_44;
end
ap_ST_st45_fsm_44 :
begin
ap_NS_fsm = ap_ST_st46_fsm_45;
end
ap_ST_st46_fsm_45 :
begin
ap_NS_fsm = ap_ST_st47_fsm_46;
end
ap_ST_st47_fsm_46 :
begin
ap_NS_fsm = ap_ST_st48_fsm_47;
end
ap_ST_st48_fsm_47 :
begin
ap_NS_fsm = ap_ST_st49_fsm_48;
end
ap_ST_st49_fsm_48 :
begin
ap_NS_fsm = ap_ST_st50_fsm_49;
end
ap_ST_st50_fsm_49 :
begin
ap_NS_fsm = ap_ST_st51_fsm_50;
end
ap_ST_st51_fsm_50 :
begin
ap_NS_fsm = ap_ST_st52_fsm_51;
end
ap_ST_st52_fsm_51 :
begin
ap_NS_fsm = ap_ST_st53_fsm_52;
end
ap_ST_st53_fsm_52 :
begin
ap_NS_fsm = ap_ST_st54_fsm_53;
end
ap_ST_st54_fsm_53 :
begin
ap_NS_fsm = ap_ST_st55_fsm_54;
end
ap_ST_st55_fsm_54 :
begin
ap_NS_fsm = ap_ST_st56_fsm_55;
end
ap_ST_st56_fsm_55 :
begin
ap_NS_fsm = ap_ST_st57_fsm_56;
end
ap_ST_st57_fsm_56 :
begin
ap_NS_fsm = ap_ST_st58_fsm_57;
end
ap_ST_st58_fsm_57 :
begin
ap_NS_fsm = ap_ST_st59_fsm_58;
end
ap_ST_st59_fsm_58 :
begin
ap_NS_fsm = ap_ST_st60_fsm_59;
end
ap_ST_st60_fsm_59 :
begin
ap_NS_fsm = ap_ST_st61_fsm_60;
end
ap_ST_st61_fsm_60 :
begin
ap_NS_fsm = ap_ST_st62_fsm_61;
end
ap_ST_st62_fsm_61 :
begin
ap_NS_fsm = ap_ST_st63_fsm_62;
end
ap_ST_st63_fsm_62 :
begin
ap_NS_fsm = ap_ST_st64_fsm_63;
end
ap_ST_st64_fsm_63 :
begin
ap_NS_fsm = ap_ST_st65_fsm_64;
end
ap_ST_st65_fsm_64 :
begin
ap_NS_fsm = ap_ST_st66_fsm_65;
end
ap_ST_st66_fsm_65 :
begin
ap_NS_fsm = ap_ST_st67_fsm_66;
end
ap_ST_st67_fsm_66 :
begin
ap_NS_fsm = ap_ST_st68_fsm_67;
end
ap_ST_st68_fsm_67 :
begin
ap_NS_fsm = ap_ST_st69_fsm_68;
end
ap_ST_st69_fsm_68 :
begin
ap_NS_fsm = ap_ST_st70_fsm_69;
end
ap_ST_st70_fsm_69 :
begin
ap_NS_fsm = ap_ST_st71_fsm_70;
end
ap_ST_st71_fsm_70 :
begin
ap_NS_fsm = ap_ST_st72_fsm_71;
end
ap_ST_st72_fsm_71 :
begin
ap_NS_fsm = ap_ST_st73_fsm_72;
end
ap_ST_st73_fsm_72 :
begin
ap_NS_fsm = ap_ST_st74_fsm_73;
end
ap_ST_st74_fsm_73 :
begin
ap_NS_fsm = ap_ST_st75_fsm_74;
end
ap_ST_st75_fsm_74 :
begin
ap_NS_fsm = ap_ST_st76_fsm_75;
end
ap_ST_st76_fsm_75 :
begin
ap_NS_fsm = ap_ST_st77_fsm_76;
end
ap_ST_st77_fsm_76 :
begin
ap_NS_fsm = ap_ST_st78_fsm_77;
end
ap_ST_st78_fsm_77 :
begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
ap_ST_st79_fsm_78 :
begin
if (~(ap_const_lv1_0 == tmp_19_fu_920_p2)) begin
ap_NS_fsm = ap_ST_st80_fsm_79;
end else begin
ap_NS_fsm = ap_ST_st122_fsm_121;
end
end
ap_ST_st80_fsm_79 :
begin
if (~(ap_const_lv1_0 == exitcond4_fu_989_p2)) begin
ap_NS_fsm = ap_ST_st93_fsm_92;
end else begin
ap_NS_fsm = ap_ST_st81_fsm_80;
end
end
ap_ST_st81_fsm_80 :
begin
ap_NS_fsm = ap_ST_st82_fsm_81;
end
ap_ST_st82_fsm_81 :
begin
ap_NS_fsm = ap_ST_st83_fsm_82;
end
ap_ST_st83_fsm_82 :
begin
ap_NS_fsm = ap_ST_st84_fsm_83;
end
ap_ST_st84_fsm_83 :
begin
ap_NS_fsm = ap_ST_st85_fsm_84;
end
ap_ST_st85_fsm_84 :
begin
ap_NS_fsm = ap_ST_st86_fsm_85;
end
ap_ST_st86_fsm_85 :
begin
ap_NS_fsm = ap_ST_st87_fsm_86;
end
ap_ST_st87_fsm_86 :
begin
ap_NS_fsm = ap_ST_st88_fsm_87;
end
ap_ST_st88_fsm_87 :
begin
ap_NS_fsm = ap_ST_st89_fsm_88;
end
ap_ST_st89_fsm_88 :
begin
ap_NS_fsm = ap_ST_st90_fsm_89;
end
ap_ST_st90_fsm_89 :
begin
ap_NS_fsm = ap_ST_st91_fsm_90;
end
ap_ST_st91_fsm_90 :
begin
ap_NS_fsm = ap_ST_st92_fsm_91;
end
ap_ST_st92_fsm_91 :
begin
ap_NS_fsm = ap_ST_st80_fsm_79;
end
ap_ST_st93_fsm_92 :
begin
ap_NS_fsm = ap_ST_st94_fsm_93;
end
ap_ST_st94_fsm_93 :
begin
ap_NS_fsm = ap_ST_st95_fsm_94;
end
ap_ST_st95_fsm_94 :
begin
ap_NS_fsm = ap_ST_st96_fsm_95;
end
ap_ST_st96_fsm_95 :
begin
ap_NS_fsm = ap_ST_st97_fsm_96;
end
ap_ST_st97_fsm_96 :
begin
ap_NS_fsm = ap_ST_st98_fsm_97;
end
ap_ST_st98_fsm_97 :
begin
ap_NS_fsm = ap_ST_st99_fsm_98;
end
ap_ST_st99_fsm_98 :
begin
ap_NS_fsm = ap_ST_st100_fsm_99;
end
ap_ST_st100_fsm_99 :
begin
ap_NS_fsm = ap_ST_st101_fsm_100;
end
ap_ST_st101_fsm_100 :
begin
ap_NS_fsm = ap_ST_st102_fsm_101;
end
ap_ST_st102_fsm_101 :
begin
ap_NS_fsm = ap_ST_st103_fsm_102;
end
ap_ST_st103_fsm_102 :
begin
ap_NS_fsm = ap_ST_st104_fsm_103;
end
ap_ST_st104_fsm_103 :
begin
ap_NS_fsm = ap_ST_st105_fsm_104;
end
ap_ST_st105_fsm_104 :
begin
ap_NS_fsm = ap_ST_st106_fsm_105;
end
ap_ST_st106_fsm_105 :
begin
ap_NS_fsm = ap_ST_st107_fsm_106;
end
ap_ST_st107_fsm_106 :
begin
ap_NS_fsm = ap_ST_st108_fsm_107;
end
ap_ST_st108_fsm_107 :
begin
ap_NS_fsm = ap_ST_st109_fsm_108;
end
ap_ST_st109_fsm_108 :
begin
ap_NS_fsm = ap_ST_st110_fsm_109;
end
ap_ST_st110_fsm_109 :
begin
ap_NS_fsm = ap_ST_st111_fsm_110;
end
ap_ST_st111_fsm_110 :
begin
ap_NS_fsm = ap_ST_st112_fsm_111;
end
ap_ST_st112_fsm_111 :
begin
ap_NS_fsm = ap_ST_st113_fsm_112;
end
ap_ST_st113_fsm_112 :
begin
ap_NS_fsm = ap_ST_st114_fsm_113;
end
ap_ST_st114_fsm_113 :
begin
ap_NS_fsm = ap_ST_st115_fsm_114;
end
ap_ST_st115_fsm_114 :
begin
ap_NS_fsm = ap_ST_st116_fsm_115;
end
ap_ST_st116_fsm_115 :
begin
ap_NS_fsm = ap_ST_st117_fsm_116;
end
ap_ST_st117_fsm_116 :
begin
ap_NS_fsm = ap_ST_st118_fsm_117;
end
ap_ST_st118_fsm_117 :
begin
ap_NS_fsm = ap_ST_st119_fsm_118;
end
ap_ST_st119_fsm_118 :
begin
ap_NS_fsm = ap_ST_st120_fsm_119;
end
ap_ST_st120_fsm_119 :
begin
ap_NS_fsm = ap_ST_st121_fsm_120;
end
ap_ST_st121_fsm_120 :
begin
ap_NS_fsm = ap_ST_st79_fsm_78;
end
ap_ST_st122_fsm_121 :
begin
if ((~(ap_const_lv1_0 == exitcond5_fu_1041_p2) & ~(ap_const_lv1_0 == tmp_35_fu_1066_p2))) begin
ap_NS_fsm = ap_ST_st160_fsm_159;
end else if (((ap_const_lv1_0 == tmp_35_fu_1066_p2) & ~(ap_const_lv1_0 == exitcond5_fu_1041_p2))) begin
ap_NS_fsm = ap_ST_st156_fsm_155;
end else begin
ap_NS_fsm = ap_ST_st123_fsm_122;
end
end
ap_ST_st123_fsm_122 :
begin
ap_NS_fsm = ap_ST_st124_fsm_123;
end
ap_ST_st124_fsm_123 :
begin
ap_NS_fsm = ap_ST_st125_fsm_124;
end
ap_ST_st125_fsm_124 :
begin
ap_NS_fsm = ap_ST_st126_fsm_125;
end
ap_ST_st126_fsm_125 :
begin
ap_NS_fsm = ap_ST_st127_fsm_126;
end
ap_ST_st127_fsm_126 :
begin
ap_NS_fsm = ap_ST_st128_fsm_127;
end
ap_ST_st128_fsm_127 :
begin
ap_NS_fsm = ap_ST_st129_fsm_128;
end
ap_ST_st129_fsm_128 :
begin
ap_NS_fsm = ap_ST_st130_fsm_129;
end
ap_ST_st130_fsm_129 :
begin
ap_NS_fsm = ap_ST_st131_fsm_130;
end
ap_ST_st131_fsm_130 :
begin
ap_NS_fsm = ap_ST_st132_fsm_131;
end
ap_ST_st132_fsm_131 :
begin
ap_NS_fsm = ap_ST_st133_fsm_132;
end
ap_ST_st133_fsm_132 :
begin
ap_NS_fsm = ap_ST_st134_fsm_133;
end
ap_ST_st134_fsm_133 :
begin
ap_NS_fsm = ap_ST_st135_fsm_134;
end
ap_ST_st135_fsm_134 :
begin
ap_NS_fsm = ap_ST_st136_fsm_135;
end
ap_ST_st136_fsm_135 :
begin
ap_NS_fsm = ap_ST_st137_fsm_136;
end
ap_ST_st137_fsm_136 :
begin
ap_NS_fsm = ap_ST_st138_fsm_137;
end
ap_ST_st138_fsm_137 :
begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end
ap_ST_st139_fsm_138 :
begin
ap_NS_fsm = ap_ST_st140_fsm_139;
end
ap_ST_st140_fsm_139 :
begin
ap_NS_fsm = ap_ST_st141_fsm_140;
end
ap_ST_st141_fsm_140 :
begin
ap_NS_fsm = ap_ST_st142_fsm_141;
end
ap_ST_st142_fsm_141 :
begin
ap_NS_fsm = ap_ST_st143_fsm_142;
end
ap_ST_st143_fsm_142 :
begin
ap_NS_fsm = ap_ST_st144_fsm_143;
end
ap_ST_st144_fsm_143 :
begin
ap_NS_fsm = ap_ST_st145_fsm_144;
end
ap_ST_st145_fsm_144 :
begin
ap_NS_fsm = ap_ST_st146_fsm_145;
end
ap_ST_st146_fsm_145 :
begin
ap_NS_fsm = ap_ST_st147_fsm_146;
end
ap_ST_st147_fsm_146 :
begin
ap_NS_fsm = ap_ST_st148_fsm_147;
end
ap_ST_st148_fsm_147 :
begin
ap_NS_fsm = ap_ST_st149_fsm_148;
end
ap_ST_st149_fsm_148 :
begin
ap_NS_fsm = ap_ST_st150_fsm_149;
end
ap_ST_st150_fsm_149 :
begin
ap_NS_fsm = ap_ST_st151_fsm_150;
end
ap_ST_st151_fsm_150 :
begin
ap_NS_fsm = ap_ST_st152_fsm_151;
end
ap_ST_st152_fsm_151 :
begin
ap_NS_fsm = ap_ST_st153_fsm_152;
end
ap_ST_st153_fsm_152 :
begin
ap_NS_fsm = ap_ST_st154_fsm_153;
end
ap_ST_st154_fsm_153 :
begin
ap_NS_fsm = ap_ST_st155_fsm_154;
end
ap_ST_st155_fsm_154 :
begin
ap_NS_fsm = ap_ST_st122_fsm_121;
end
ap_ST_st156_fsm_155 :
begin
if (((ap_const_lv1_0 == tmp_38_fu_1071_p2) & ~((ap_const_lv1_0 == tmp_38_fu_1071_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)))) begin
ap_NS_fsm = ap_ST_st167_fsm_166;
end else if ((~((ap_const_lv1_0 == tmp_38_fu_1071_p2) & (ap_const_logic_0 == ap_sig_ioackin_P_netOut_V_TREADY)) & ~(ap_const_lv1_0 == tmp_38_fu_1071_p2))) begin
ap_NS_fsm = ap_ST_st157_fsm_156;
end else begin
ap_NS_fsm = ap_ST_st156_fsm_155;
end
end
ap_ST_st157_fsm_156 :
begin
ap_NS_fsm = ap_ST_st158_fsm_157;
end
ap_ST_st158_fsm_157 :
begin
ap_NS_fsm = ap_ST_st159_fsm_158;
end
ap_ST_st159_fsm_158 :
begin
ap_NS_fsm = ap_ST_st156_fsm_155;
end
ap_ST_st160_fsm_159 :
begin
if ((ap_const_lv1_0 == exitcond6_fu_1210_p2)) begin
ap_NS_fsm = ap_ST_st161_fsm_160;
end else begin
ap_NS_fsm = ap_ST_st167_fsm_166;
end
end
ap_ST_st161_fsm_160 :
begin
if ((ap_const_lv1_0 == exitcond_fu_1239_p2)) begin
ap_NS_fsm = ap_ST_st162_fsm_161;
end else begin
ap_NS_fsm = ap_ST_st160_fsm_159;
end
end
ap_ST_st162_fsm_161 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_P_uOut_TREADY)) begin
ap_NS_fsm = ap_ST_st161_fsm_160;
end else begin
ap_NS_fsm = ap_ST_st162_fsm_161;
end
end
ap_ST_st163_fsm_162 :
begin
if (~(ap_const_lv1_0 == tmp_8_fu_1264_p2)) begin
ap_NS_fsm = ap_ST_st164_fsm_163;
end else begin
ap_NS_fsm = ap_ST_st167_fsm_166;
end
end
ap_ST_st164_fsm_163 :
begin
if (~(ap_const_lv1_0 == exitcond2_fu_1341_p2)) begin
ap_NS_fsm = ap_ST_st163_fsm_162;
end else begin
ap_NS_fsm = ap_ST_st165_fsm_164;
end
end
ap_ST_st165_fsm_164 :
begin
if (((ap_const_lv1_0 == exitcond8_fu_1399_p2) & ~ap_sig_bdd_710)) begin
ap_NS_fsm = ap_ST_st165_fsm_164;
end else if ((~ap_sig_bdd_710 & ~(ap_const_lv1_0 == exitcond8_fu_1399_p2))) begin
ap_NS_fsm = ap_ST_st164_fsm_163;
end else begin
ap_NS_fsm = ap_ST_st165_fsm_164;
end
end
ap_ST_st166_fsm_165 :
begin
if (((ap_const_lv1_0 == exitcond7_fu_1410_p2) & ~ap_sig_bdd_725)) begin
ap_NS_fsm = ap_ST_st166_fsm_165;
end else if ((~ap_sig_bdd_725 & ~(ap_const_lv1_0 == exitcond7_fu_1410_p2))) begin
ap_NS_fsm = ap_ST_st167_fsm_166;
end else begin
ap_NS_fsm = ap_ST_st166_fsm_165;
end
end
ap_ST_st167_fsm_166 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign P_netOut_V_TDATA = p_s_reg_411;
assign P_uOut_TDATA = p_uOut_q1;
assign ST_WandB_d0 = P_WandB_TDATA;
assign ST_layerSize_V_load_1_phi_fu_1303_p3 = ((sel_tmp2_fu_1297_p2[0:0] === 1'b1) ? ST_layerSize_V_2 : sel_tmp1_fu_1289_p3);
assign ap_return = agg_result_V_reg_514;
always @ (ap_rst_n) begin
ap_rst_n_inv = ~ap_rst_n;
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_1012 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2E]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_1019 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7B]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_1029 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_62]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_1384 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A6]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_185 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_268 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_275 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_50]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_283 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7A]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_291 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9C]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_300 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_309 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5C]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_319 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_326 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_56]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_336 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_343 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5B]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_352 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_16]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_359 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2D]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_367 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_61]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_377 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_28]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_384 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_73]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_394 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4C]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_401 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_99]);
end
always @ (ap_start or P_config_V_TVALID or tmp_fu_620_p2) begin
ap_sig_bdd_414 = (((P_config_V_TVALID == ap_const_logic_0) & ~(tmp_fu_620_p2 == ap_const_lv1_0)) | (ap_start == ap_const_logic_0));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_435 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
always @ (P_netIn_TVALID or exitcond1_fu_642_p2) begin
ap_sig_bdd_441 = ((P_netIn_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond1_fu_642_p2));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_451 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_481 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_503 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_523 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_17]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_532 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4E]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_553 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4F]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_572 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_78]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_581 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_79]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_595 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9B]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_617 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9D]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_626 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9E]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_637 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9F]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_655 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A0]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_669 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A2]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_686 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A3]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_704 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A4]);
end
always @ (P_WandB_TVALID or exitcond8_fu_1399_p2) begin
ap_sig_bdd_710 = ((P_WandB_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond8_fu_1399_p2));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_720 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A5]);
end
always @ (P_config_V_TVALID or exitcond7_fu_1410_p2) begin
ap_sig_bdd_725 = ((P_config_V_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond7_fu_1410_p2));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_754 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4D]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_776 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9A]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_805 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A1]);
end
always @ (ap_sig_cseq_ST_st156_fsm_155 or tmp_38_fu_1071_p2) begin
ap_sig_bdd_909 = ((ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155) & (ap_const_lv1_0 == tmp_38_fu_1071_p2));
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_929 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_74]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_954 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_961 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_969 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_29]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_976 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_57]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_983 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5D]);
end
assign exitcond1_fu_642_p2 = (i_2_reg_297 == ST_layerSize_V_0_load_reg_1472? 1'b1: 1'b0);
assign exitcond2_fu_1341_p2 = (j_reg_481 == ST_layerSize_V_load_1_phi_reg_1751? 1'b1: 1'b0);
assign exitcond3_fu_836_p2 = (k_1_reg_343 == tmp_20_reg_1548? 1'b1: 1'b0);
assign exitcond4_fu_989_p2 = (j_2_reg_389 == tmp_22_reg_1612? 1'b1: 1'b0);
assign exitcond5_fu_1041_p2 = (i_5_reg_400 == tmp_17_reg_1598? 1'b1: 1'b0);
assign exitcond6_fu_1210_p2 = (i_6_reg_436 == ST_numLayer_V_load_reg_1461? 1'b1: 1'b0);
assign exitcond7_fu_1410_p2 = (i_reg_503 == P_config_V_read_reg_1477? 1'b1: 1'b0);
assign exitcond8_fu_1399_p2 = (k_reg_492 == tmp_10_reg_1756? 1'b1: 1'b0);
assign exitcond_fu_1239_p2 = (j_3_reg_458 == tmp_40_reg_1725? 1'b1: 1'b0);
assign feedforward_AXILiteS_s_axi_U_ap_dummy_ce = ap_const_logic_1;
assign grp_fu_535_ce = ap_const_logic_1;
assign grp_fu_543_ce = ap_const_logic_1;
assign grp_fu_547_ce = ap_const_logic_1;
assign grp_fu_557_ce = ap_const_logic_1;
assign i_10_fu_830_p2 = (i_3_reg_308 + ap_const_lv8_1);
assign i_11_fu_1046_p2 = (i_5_reg_400 + ap_const_lv8_1);
assign i_12_fu_926_p2 = (i_4_reg_366 + ap_const_lv32_1);
assign i_14_fu_1215_p2 = (ap_const_lv8_1 + i_6_reg_436);
assign i_15_fu_1194_p2 = (ap_const_lv8_1 + p_netOut_V_reg_424);
assign i_7_fu_1415_p2 = (i_reg_503 + ap_const_lv8_1);
assign i_8_fu_647_p2 = (i_2_reg_297 + ap_const_lv8_1);
assign i_9_fu_1379_p2 = (i_1_reg_469 + ap_const_lv8_1);
assign j_4_fu_1346_p2 = (j_reg_481 + ap_const_lv8_1);
assign j_5_fu_771_p2 = (j_1_reg_320 + ap_const_lv32_1);
assign j_6_fu_994_p2 = (j_2_reg_389 + ap_const_lv8_1);
assign j_7_fu_1244_p2 = (j_3_reg_458 + ap_const_lv8_1);
assign k_2_fu_1404_p2 = (k_reg_492 + ap_const_lv9_1);
assign k_3_fu_841_p2 = (k_1_reg_343 + ap_const_lv8_1);
assign lhs_V_1_cast_fu_701_p1 = ST_numLayer_V_load_reg_1461;
assign next_mul_fu_1204_p2 = (ap_const_lv14_23 + phi_mul_reg_447);
assign notlhs1_fu_1157_p2 = (tmp_45_fu_1125_p4 != ap_const_lv11_7FF? 1'b1: 1'b0);
assign notlhs_fu_1139_p2 = (tmp_43_fu_1108_p4 != ap_const_lv11_7FF? 1'b1: 1'b0);
assign notrhs1_fu_1163_p2 = (tmp_71_fu_1135_p1 == ap_const_lv52_0? 1'b1: 1'b0);
assign notrhs_fu_1145_p2 = (tmp_70_fu_1118_p1 == ap_const_lv52_0? 1'b1: 1'b0);
assign p_netOut_V_1_fu_1187_p3 = ((tmp_51_reg_1692[0:0] === 1'b1) ? p_netOut_V_reg_424 : p_s_reg_411);
assign p_shl2_cast_fu_804_p3 = {{tmp_52_fu_800_p1}, {ap_const_lv5_0}};
assign p_shl3_cast_fu_816_p3 = {{tmp_53_fu_812_p1}, {ap_const_lv2_0}};
assign p_shl4_cast_fu_963_p3 = {{tmp_56_fu_959_p1}, {ap_const_lv5_0}};
assign p_shl5_cast_fu_975_p3 = {{tmp_57_fu_971_p1}, {ap_const_lv2_0}};
assign p_uOut_load_3_to_int_fu_1104_p1 = reg_578;
assign p_uOut_load_4_to_int_fu_1122_p1 = p_uOut_load_4_reg_1686;
assign r_V_1_fu_732_p2 = ($signed(ap_const_lv9_1FE) + $signed(lhs_V_1_cast_fu_701_p1));
assign r_V_fu_704_p2 = ($signed(ap_const_lv9_1FF) + $signed(lhs_V_1_cast_fu_701_p1));
assign sel_tmp1_fu_1289_p3 = ((sel_tmp_fu_1283_p2[0:0] === 1'b1) ? ST_layerSize_V_1 : ST_layerSize_V_3);
assign sel_tmp2_fu_1297_p2 = (tmp_5_fu_1279_p1 == ap_const_lv2_2? 1'b1: 1'b0);
assign sel_tmp_fu_1283_p2 = (tmp_5_fu_1279_p1 == ap_const_lv2_1? 1'b1: 1'b0);
assign tmp_10_fu_1335_p2 = (ap_const_lv9_1 + tmp_9_fu_1331_p1);
assign tmp_11_fu_1356_p2 = (tmp_cast_fu_1352_p1 + tmp_s_reg_1746);
assign tmp_12_cast_fu_1385_p1 = k_reg_492;
assign tmp_12_fu_1361_p2 = tmp_11_fu_1356_p2 << ap_const_lv14_5;
assign tmp_13_fu_1367_p2 = tmp_11_fu_1356_p2 << ap_const_lv14_2;
assign tmp_15_fu_761_p1 = tmp_14_fu_748_p6;
assign tmp_16_fu_765_p2 = ($signed(j_1_reg_320) < $signed(tmp_15_fu_761_p1)? 1'b1: 1'b0);
assign tmp_18_fu_916_p1 = tmp_17_fu_903_p6;
assign tmp_19_fu_920_p2 = ($signed(i_4_reg_366) < $signed(tmp_18_fu_916_p1)? 1'b1: 1'b0);
assign tmp_1_fu_630_p2 = (P_mode_V == ap_const_lv8_3? 1'b1: 1'b0);
assign tmp_21_fu_1373_p2 = (tmp_12_fu_1361_p2 + tmp_13_fu_1367_p2);
assign tmp_23_cast_fu_945_p1 = $signed(i_4_reg_366);
assign tmp_23_fu_667_p1 = tmp_23_fu_667_p10;
assign tmp_23_fu_667_p10 = i_3_reg_308;
assign tmp_23_fu_667_p2 = (ap_const_lv15_23 * tmp_23_fu_667_p1);
assign tmp_24_cast_fu_875_p1 = tmp_20_reg_1548;
assign tmp_24_fu_677_p1 = i_3_reg_308[1:0];
assign tmp_25_fu_898_p1 = tmp_38_neg_fu_892_p2;
assign tmp_29_cast1_fu_847_p1 = k_1_reg_343;
assign tmp_29_cast_fu_851_p1 = k_1_reg_343;
assign tmp_29_fu_691_p1 = tmp_29_fu_691_p10;
assign tmp_29_fu_691_p10 = tmp_4_fu_681_p2;
assign tmp_29_fu_691_p2 = (ap_const_lv9_23 * tmp_29_fu_691_p1);
assign tmp_2_fu_1317_p5 = ($signed(ap_const_lv2_3) + $signed(tmp_5_fu_1279_p1));
assign tmp_31_cast_fu_1028_p1 = tmp_22_reg_1612;
assign tmp_31_fu_697_p1 = tmp_4_fu_681_p2[1:0];
assign tmp_33_cast1_fu_1000_p1 = j_2_reg_389;
assign tmp_33_cast_fu_1004_p1 = j_2_reg_389;
assign tmp_33_fu_714_p1 = r_V_fu_704_p2;
assign tmp_33_fu_714_p2 = ($signed({{1'b0}, {ap_const_lv16_23}}) * $signed(tmp_33_fu_714_p1));
assign tmp_35_fu_1066_p2 = (P_mode_V_read_reg_1453 == ap_const_lv8_4? 1'b1: 1'b0);
assign tmp_36_cast_fu_1052_p1 = i_5_reg_400;
assign tmp_36_fu_720_p1 = tmp_33_fu_714_p2[8:0];
assign tmp_38_fu_1071_p2 = (p_netOut_V_reg_424 < tmp_17_reg_1598? 1'b1: 1'b0);
assign tmp_38_neg_fu_892_p2 = (tmp_38_to_int_fu_888_p1 ^ ap_const_lv64_8000000000000000);
assign tmp_38_to_int_fu_888_p1 = reg_602;
assign tmp_39_fu_728_p1 = r_V_fu_704_p2[1:0];
assign tmp_3_fu_1421_p1 = i_reg_503[1:0];
assign tmp_40_fu_1225_p5 = i_6_reg_436[1:0];
assign tmp_41_cast_fu_1076_p1 = p_netOut_V_reg_424;
assign tmp_41_fu_738_p2 = ($signed({{1'b0}, {ap_const_lv9_23}}) * $signed(r_V_1_fu_732_p2));
assign tmp_42_cast_fu_1090_p1 = p_s_reg_411;
assign tmp_42_fu_744_p1 = r_V_1_fu_732_p2[1:0];
assign tmp_43_fu_1108_p4 = {{p_uOut_load_3_to_int_fu_1104_p1[ap_const_lv32_3E : ap_const_lv32_34]}};
assign tmp_44_fu_1389_p2 = (tmp_21_reg_1769 + tmp_12_cast_fu_1385_p1);
assign tmp_45_fu_1125_p4 = {{p_uOut_load_4_to_int_fu_1122_p1[ap_const_lv32_3E : ap_const_lv32_34]}};
assign tmp_46_fu_790_p2 = (j_1_reg_320 + tmp_59_cast_reg_1493);
assign tmp_47_fu_1151_p2 = (notrhs_fu_1145_p2 | notlhs_fu_1139_p2);
assign tmp_48_fu_1169_p2 = (notrhs1_fu_1163_p2 | notlhs1_fu_1157_p2);
assign tmp_49_fu_1175_p2 = (tmp_47_fu_1151_p2 & tmp_48_fu_1169_p2);
assign tmp_4_fu_681_p2 = ($signed(ap_const_lv8_FF) + $signed(i_3_reg_308));
assign tmp_50_fu_553_opcode = ap_const_lv5_2;
assign tmp_51_fu_1181_p2 = (tmp_49_fu_1175_p2 & tmp_50_fu_553_p2);
assign tmp_52_cast_fu_1250_p1 = j_3_reg_458;
assign tmp_52_fu_800_p1 = tmp_46_fu_790_p2[8:0];
assign tmp_53_fu_812_p1 = tmp_46_fu_790_p2[11:0];
assign tmp_54_fu_824_p2 = (p_shl2_cast_fu_804_p3 + p_shl3_cast_fu_816_p3);
assign tmp_55_fu_949_p2 = ($signed(tmp_23_cast_fu_945_p1) + $signed(tmp_61_cast_reg_1520));
assign tmp_56_fu_959_p1 = tmp_55_fu_949_p2[8:0];
assign tmp_57_fu_971_p1 = tmp_55_fu_949_p2[11:0];
assign tmp_58_fu_983_p2 = (p_shl4_cast_fu_963_p3 + p_shl5_cast_fu_975_p3);
assign tmp_59_cast_fu_673_p1 = tmp_23_fu_667_p2;
assign tmp_59_fu_1056_p2 = (tmp_36_reg_1513 + tmp_36_cast_fu_1052_p1);
assign tmp_5_fu_1279_p1 = i_1_reg_469[1:0];
assign tmp_60_fu_878_p2 = (tmp_54_reg_1554 + tmp_24_cast_fu_875_p1);
assign tmp_61_cast_fu_724_p1 = $signed(tmp_33_fu_714_p2);
assign tmp_61_fu_855_p2 = (tmp_54_reg_1554 + tmp_29_cast_fu_851_p1);
assign tmp_62_fu_865_p2 = (tmp_29_reg_1503 + tmp_29_cast1_fu_847_p1);
assign tmp_63_cast_fu_1394_p1 = tmp_44_fu_1389_p2;
assign tmp_63_fu_1031_p2 = (tmp_58_reg_1618 + tmp_31_cast_fu_1028_p1);
assign tmp_64_cast_fu_795_p1 = $signed(tmp_46_fu_790_p2);
assign tmp_64_fu_1008_p2 = (tmp_58_reg_1618 + tmp_33_cast_fu_1004_p1);
assign tmp_65_fu_1018_p2 = (tmp_41_reg_1530 + tmp_33_cast1_fu_1000_p1);
assign tmp_66_fu_1200_p1 = phi_mul_reg_447[8:0];
assign tmp_68_cast_fu_954_p1 = $signed(tmp_55_fu_949_p2);
assign tmp_68_fu_1080_p2 = (tmp_36_reg_1513 + tmp_41_cast_fu_1076_p1);
assign tmp_69_fu_1094_p2 = (tmp_36_reg_1513 + tmp_42_cast_fu_1090_p1);
assign tmp_6_fu_653_p1 = i_2_reg_297;
assign tmp_70_fu_1118_p1 = p_uOut_load_3_to_int_fu_1104_p1[51:0];
assign tmp_71_fu_1135_p1 = p_uOut_load_4_to_int_fu_1122_p1[51:0];
assign tmp_72_cast_fu_883_p1 = tmp_60_fu_878_p2;
assign tmp_72_fu_1254_p2 = (tmp_66_reg_1707 + tmp_52_cast_fu_1250_p1);
assign tmp_73_cast_fu_860_p1 = tmp_61_fu_855_p2;
assign tmp_74_cast_fu_870_p1 = $signed(tmp_62_fu_865_p2);
assign tmp_75_cast_fu_1036_p1 = tmp_63_fu_1031_p2;
assign tmp_76_cast_fu_1013_p1 = tmp_64_fu_1008_p2;
assign tmp_77_cast_fu_1023_p1 = $signed(tmp_65_fu_1018_p2);
assign tmp_78_cast_fu_1061_p1 = $signed(tmp_59_fu_1056_p2);
assign tmp_7_fu_658_p2 = (i_3_reg_308 < ST_numLayer_V_load_reg_1461? 1'b1: 1'b0);
assign tmp_80_cast_fu_1085_p1 = $signed(tmp_68_fu_1080_p2);
assign tmp_81_cast_fu_1099_p1 = $signed(tmp_69_fu_1094_p2);
assign tmp_82_cast_fu_1259_p1 = tmp_72_fu_1254_p2;
assign tmp_8_fu_1264_p2 = (i_1_reg_469 < ST_numLayer_V_load_reg_1461? 1'b1: 1'b0);
assign tmp_9_fu_1331_p1 = tmp_2_fu_1317_p6;
assign tmp_cast_fu_1352_p1 = j_reg_481;
assign tmp_fu_620_p2 = (P_mode_V == ap_const_lv8_2? 1'b1: 1'b0);
assign tmp_s_fu_1273_p1 = tmp_s_fu_1273_p10;
assign tmp_s_fu_1273_p10 = i_1_reg_469;
assign tmp_s_fu_1273_p2 = (ap_const_lv14_23 * tmp_s_fu_1273_p1);
always @ (posedge ap_clk) begin
tmp_59_cast_reg_1493[31:15] <= 17'b00000000000000000;
tmp_54_reg_1554[1:0] <= 2'b00;
tmp_58_reg_1618[1:0] <= 2'b00;
tmp_21_reg_1769[1:0] <= 2'b00;
end
endmodule //feedforward
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`include "constants.vh"
module ram_sync_nolatch_2r1w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
input [BRAM_ADDR_WIDTH-1:0] waddr,
input [BRAM_DATA_WIDTH-1:0] wdata,
input we
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
integer i;
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
always @ (posedge clk) begin
if (we)
mem[waddr] <= wdata;
end
endmodule // ram_sync_nolatch_2r1w
module ram_sync_nolatch_2r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
reg [BRAM_DATA_WIDTH-1:0] mem [0:DATA_DEPTH-1];
assign rdata1 = mem[raddr1];
assign rdata2 = mem[raddr2];
always @ (posedge clk) begin
if (we1)
mem[waddr1] <= wdata1;
if (we2)
mem[waddr2] <= wdata2;
end
endmodule // ram_sync_nolatch_2r2w
module ram_sync_nolatch_4r1w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input [BRAM_ADDR_WIDTH-1:0] waddr,
input [BRAM_DATA_WIDTH-1:0] wdata,
input we
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_nolatch_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
ram_sync_nolatch_2r1w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr(waddr),
.wdata(wdata),
.we(we)
);
endmodule //ram_sync_nolatch_4r1w
module ram_sync_nolatch_4r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_nolatch_4r2w
module ram_sync_nolatch_6r2w(
input clk,
input [BRAM_ADDR_WIDTH-1:0] raddr1,
input [BRAM_ADDR_WIDTH-1:0] raddr2,
input [BRAM_ADDR_WIDTH-1:0] raddr3,
input [BRAM_ADDR_WIDTH-1:0] raddr4,
input [BRAM_ADDR_WIDTH-1:0] raddr5,
input [BRAM_ADDR_WIDTH-1:0] raddr6,
output wire [BRAM_DATA_WIDTH-1:0] rdata1,
output wire [BRAM_DATA_WIDTH-1:0] rdata2,
output wire [BRAM_DATA_WIDTH-1:0] rdata3,
output wire [BRAM_DATA_WIDTH-1:0] rdata4,
output wire [BRAM_DATA_WIDTH-1:0] rdata5,
output wire [BRAM_DATA_WIDTH-1:0] rdata6,
input [BRAM_ADDR_WIDTH-1:0] waddr1,
input [BRAM_ADDR_WIDTH-1:0] waddr2,
input [BRAM_DATA_WIDTH-1:0] wdata1,
input [BRAM_DATA_WIDTH-1:0] wdata2,
input we1,
input we2
);
parameter BRAM_ADDR_WIDTH = `ADDR_LEN;
parameter BRAM_DATA_WIDTH = `DATA_LEN;
parameter DATA_DEPTH = 32;
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem0(
.clk(clk),
.raddr1(raddr1),
.raddr2(raddr2),
.rdata1(rdata1),
.rdata2(rdata2),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem1(
.clk(clk),
.raddr1(raddr3),
.raddr2(raddr4),
.rdata1(rdata3),
.rdata2(rdata4),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
ram_sync_nolatch_2r2w
#(BRAM_ADDR_WIDTH, BRAM_DATA_WIDTH, DATA_DEPTH)
mem2(
.clk(clk),
.raddr1(raddr5),
.raddr2(raddr6),
.rdata1(rdata5),
.rdata2(rdata6),
.waddr1(waddr1),
.waddr2(waddr2),
.wdata1(wdata1),
.wdata2(wdata2),
.we1(we1),
.we2(we2)
);
endmodule // ram_sync_nolatch_6r2w
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:24:28 10/17/2015
// Design Name:
// Module Name: rx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rx
#(
parameter DBIT = 8 , //databits
SB_TICK = 16 //ticks for sample bits
)
(
input wire clk, reset, //boton1, //
input wire rx, s_tick, //rx -> bit entrante, s_tick -> 16 ticks por intervalo, para muestrear un bit
output reg rx_done_tick, //se pone en 1 un ciclo despues de que la palabra de 8 bits es recibida
output wire [DBIT-1:0] dout //buffer de datos, para leer la palabra recibida
);
// symbolic state declaration
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
//signal declaration
reg [1:0] state_reg, state_next; //Estado actual y siguiente de la unidad rx
reg [3:0] s_reg, s_next; //cuenta el numero de ticks recibidos
reg [2:0] n_reg, n_next; //cuenta el numero de bits de datos recibidos
reg [DBIT-1:0] b_reg, b_next; //registro para almacenar los bits recibidos
//body
//FSMD state & data registers
always @(posedge clk, posedge reset)//, posedge boton1)
if (reset) //resetear la UART receive
begin
state_reg <= idle;
s_reg <= 0;
n_reg <= 0;
b_reg <= 8'b10101010;
end
//else if (boton1)
// begin
// state_reg <= start;
// s_reg <= 0;
// n_reg <= 0;
// b_reg <= 8'b1111_0000;
// end
else
begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end
//FSMD next-state logic
always @*
begin
state_next = state_reg; //mantiene el estado de los registros
rx_done_tick = 1'b0;
s_next = s_reg;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle: //antes de comenzar a recibir datos
if (~rx) //si rx es 0, bit de start
begin
state_next = start; //siguiente estado: start
s_next = 0; //pongo a cero el contador s
end
start: //estado: comienzo de trama
if (s_tick) //si llego un tick..
if (s_reg==7) //si se alcanzaron los 7 ticks, estamos al medio del bit start
begin
state_next = data; //pasa al siguiente estado: recibir los datos
s_next = 0; //pone el contador de ticks a cero
n_next = 0; //pone el contador de cant de datos recibidos a cero
end
else //si no, aumenta cantidad de ticks en 1
s_next = s_reg + 4'b0001;
data: //estado: recibiendo datos
if (s_tick) //si llego un tick..
if (s_reg==15) //si llegamos a los 15 ticks..
begin
s_next = 0; //se reinicia el contador de ticks
b_next = {rx, b_reg[DBIT-1:1]}; //se almacena el bit recibido
if (n_reg==(DBIT-1)) //si ya se recibieron todos los bits..
state_next = stop; //proximo estado: stop
else //si no llegamos a los 8 bits recibidos..
n_next = n_reg + 3'b001; //se aumenta la cant de bits recibidos en 1
end
else //si no llegamos a los 15 ticks recibidos
s_next = s_reg + 4'b0001; //se aumenta la cant de ticks recib en 1
stop: //estado: stop, fin de trama
if (s_tick) //si recibimos un tick..
if (s_reg==(SB_TICK-1)) //si la cantidad de ticks recibidos es 15
begin
state_next = idle; //proximo estado: esperando a recibir nuevo dato
rx_done_tick = 1'b1; //dato listo en buffer, para ser leido
end
else //si no..
s_next = s_reg + 4'b0001; //aumentamos la cant de ticks recib en 1
endcase
end
//output
assign dout = b_reg; //asigna registro contenedor de los datos recibidos
//al buffer de salida
endmodule
|
/**
# XcvrSpi #
Simple SPI transceiver with FIFOs. 8 bit interface, but continously clocks out
data. CS stays asserted until TX FIFO is empty.
*/
///////////////////////////////////////////////////////////////////////////
// MODULE DECLARATION
///////////////////////////////////////////////////////////////////////////
module XcvrSpiSlave #(
parameter LOG2_DEPTH = 4
)
(
// INPUTS
input clk, ///< System Clock
input rst, ///< Reset, synchronous and active high
// Data Interface Inputs
input [7:0] dataIn, ///< Data to send
input write, ///< Strobe to write to TX FIFO
input read, ///< Strove to read from RX FIFO
input cpol, ///< SPI data polarity
input cpha, ///< SPI clock phase
// SPI Signals
input nCs, ///< ~Chip select
input sck, ///< SPI clock
input miso, ///< Master in, slave out
output mosi, ///< Master out, slave in
// FIFO Status
output txDataPresent, ///< When high, interface has data to send back
output txHalfFull, ///< TX FIFO is getting full
output txFull, ///< TX FIFO is full
output rxDataPresent, ///< RX FIFO has data available
output rxHalfFull, ///< RX FIFO is getting full
output rxFull, ///< RX FIFO is full
// Data Interface Outputs
output [7:0] dataOut ///< Data received
);
///////////////////////////////////////////////////////////////////////////
// SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
wire [7:0] txData;
wire [7:0] rxData;
reg [7:0] dataInReg;
reg [7:0] dataOutReg;
reg [7:0] shiftReg;
reg [2:0] spiCount;
reg busy;
reg dataOutReady;
reg mosiCapture;
reg sckD1;
reg txRead;
reg rxWrite;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
// TX FIFO
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
txFifo (
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(write), ///< Write strobe (1 clk)
.read(txRead), ///< Read strobe (1 clk)
.dataIn(dataIn), ///< [7:0] Data to write
// Outputs
.dataOut(txData), ///< [7:0] Data from FIFO
.dataPresent(txDataPresent), ///< Data is present in FIFO
.halfFull(txHalfFull), ///< FIFO is half full
.full(txFull) ///< FIFO is full
);
end
else begin
// Create a simple busy bit and register the data to be sent
assign txData = dataInReg;
assign txDataPresent = busy;
assign txHalfFull = busy;
assign txFull = busy;
always @(posedge clk) begin
if (write) begin
dataInReg <= dataIn;
end
busy <= busy ? (~txRead & busy) : write;
end
end
// RX FIFO
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
rxFifo (
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(rxWrite), ///< Write strobe (1 clk)
.read(read), ///< Read strobe (1 clk)
.dataIn(rxData), ///< [7:0] Data to write
// Outputs
.dataOut(dataOut), ///< [7:0] Data from FIFO
.dataPresent(rxDataPresent), ///< Data is present in FIFO
.halfFull(rxHalfFull), ///< FIFO is half full
.full(rxFull) ///< FIFO is full
);
end
else begin
// Create a simple rxReady bit and register received data
assign dataOut = dataOutReg;
assign rxDataPresent = dataOutReady;
assign rxHalfFull = dataOutReady;
assign rxFull = dataOutReady;
always @(posedge clk) begin
if (rxWrite) begin
dataOutReg <= rxData;
end
dataOutReady <= dataOutReady ? (dataOutReady & ~read) : rxWrite;
end
end
initial begin
dataOutReg = 'b0;
dataInReg = 'b0;
shiftReg = 'd0;
spiCount = 'd7;
busy = 1'b0;
dataOutReady = 1'b0;
mosiCapture = 1'b0;
sckD1 = 1'b0;
txRead = 1'b0;
rxWrite = 1'b0;
end
assign miso = shiftReg[7]; // Slave out is MSB of shift register
assign rxData = {shiftReg[6:0], mosiCapture};
always @(posedge clk) begin
sckD1 <= sck;
if (nCs) begin
spiCount <= 'd7;
shiftReg <= txData;
txRead <= 1'b0;
rxWrite <= 1'b0;
end
else if ((sck ^sckD1) && !(sck ^ cpol ^ cpha)) begin
spiCount <= spiCount - 'd1;
if (spiCount == 'd0) begin
shiftReg <= txData;
txRead <= 1'b1;
end
else begin
shiftReg <= {shiftReg[6:0], mosiCapture};
txRead <= 1'b0;
end
end
else begin
spiCount <= spiCount;
shiftReg <= shiftReg;
txRead <= 1'b0;
end
// MISO data capture
if ((sck ^ sckD1) && (sck ^ cpol ^ cpha)) begin
mosiCapture <= mosi;
if (spiCount == 'd0) begin
rxWrite <= 1'b1;
end
else begin
rxWrite <= 1'b0;
end
end
else begin
mosiCapture <= mosiCapture;
rxWrite <= 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_TB_V
`define SKY130_FD_SC_HDLL__O21A_TB_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hdll__o21a dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_1_V
`define SKY130_FD_SC_LS__OR4B_1_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_1 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_1 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_1_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2014 , Atsushi Sasaki
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: tdm_to_i2s_converter.v
//
// *Module Description:
// TDM to I2S Converter
//
// *Author(s):
// - Atsushi Sasaki, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 1.00 $
// $LastChangedBy: Atsushi Sasaki $
// $LastChangedDate: 2014-06-06 $
//----------------------------------------------------------------------------
module tdm_to_i2s_converter(
rst_i,
sck_i,
fsync_i,
dat_i,
mck_o,
bck_o,
lrck_o,
dat_o
);
//
// Parameters
//
//
// I/O Ports
//
input rst_i;
input sck_i;
input fsync_i;
input dat_i;
output mck_o;
output bck_o;
output lrck_o;
output reg [3:0] dat_o;
//
// Wires, Registers
//
assign rst = rst_i;
//
// Modules
//
// Shifted Frame Sync
reg s_fsync;
always @ (posedge sck_i or posedge rst) begin
if(rst) begin
s_fsync <= 1'b0;
end
else begin
s_fsync <= fsync_i;
end
end
// Bit Counter
reg [8:0] bit_cnt;
always @ (negedge sck_i or posedge rst) begin
if(rst) begin
bit_cnt <= 9'b111111111;
end
else begin
if(s_fsync) begin
bit_cnt <= {~bit_cnt[8], 8'b0};
end
else begin
bit_cnt <= bit_cnt + 1'b1;
end
end
end
// Input Data Assign
reg [63:0] dat_0_a, dat_0_b;
reg [63:0] dat_1_a, dat_1_b;
reg [63:0] dat_2_a, dat_2_b;
reg [63:0] dat_3_a, dat_3_b;
always @ (posedge sck_i or posedge rst) begin
if(rst) begin
dat_0_a <= 64'b0;
dat_1_a <= 64'b0;
dat_2_a <= 64'b0;
dat_3_a <= 64'b0;
dat_0_b <= 64'b0;
dat_1_b <= 64'b0;
dat_2_b <= 64'b0;
dat_3_b <= 64'b0;
end
else begin
if(bit_cnt[8]) begin
case(bit_cnt[7:6])
2'b00:
begin
dat_0_a[63-bit_cnt[5:0]] <= dat_i;
end
2'b01:
begin
dat_1_a[63-bit_cnt[5:0]] <= dat_i;
end
2'b10:
begin
dat_2_a[63-bit_cnt[5:0]] <= dat_i;
end
2'b11:
begin
dat_3_a[63-bit_cnt[5:0]] <= dat_i;
end
endcase
end
else begin
case(bit_cnt[7:6])
2'b00:
begin
dat_0_b[63-bit_cnt[5:0]] <= dat_i;
end
2'b01:
begin
dat_1_b[63-bit_cnt[5:0]] <= dat_i;
end
2'b10:
begin
dat_2_b[63-bit_cnt[5:0]] <= dat_i;
end
2'b11:
begin
dat_3_b[63-bit_cnt[5:0]] <= dat_i;
end
endcase
end
end
end
// I2S Clock Generator
assign mck_o = sck_i;
assign bck_o = bit_cnt[1];
assign lrck_o = bit_cnt[7];
always @ (negedge bck_o or posedge rst) begin
if(rst) begin
dat_o <= 4'b0;
end
else begin
if(bit_cnt[8]) begin
dat_o <= {dat_3_b[63-bit_cnt[7:2]], dat_2_b[63-bit_cnt[7:2]], dat_1_b[63-bit_cnt[7:2]], dat_0_b[63-bit_cnt[7:2]]};
end
else begin
dat_o <= {dat_3_a[63-bit_cnt[7:2]], dat_2_a[63-bit_cnt[7:2]], dat_1_a[63-bit_cnt[7:2]], dat_0_a[63-bit_cnt[7:2]]};
end
end
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : soc_template.v
// Description : Wishbone based SoC template
// Author : Philip Tracton
// Created On : Sun Jul 24 20:47:25 2016
// Last Modified By: Philip Tracton
// Last Modified On: Sun Jul 24 20:47:25 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module soc_template (/*AUTOARG*/
// Outputs
uart_tx,
// Inputs
clk_sys_i, reset_sys_i, uart_rx
) ;
//
// System Interface
//
input clk_sys_i;
input reset_sys_i;
//
// UART Interface
//
input uart_rx;
output wire uart_tx;
/*AUTOWIRE*/
/*AUTOREG*/
//
// Bus Matrix
//
wire clk_i;
wire rst_i;
wire wb_clk_i = clk_i;
wire wb_rst_i = rst_i;
assign wb_clk = wb_clk_i;
assign wb_rst = wb_rst_i;
`include "soc_bus_matrix.vh"
wire VDD = 1;
wire VSS = 0;
assign wb_s2m_ram_rty = 0;
assign wb_s2m_rom_rty = 0;
assign wb_s2m_debug_rty =0;
assign wb_s2m_uart_rty = 0;
assign wb_s2m_uart_err =0;
assign wb_s2m_debug_dat = 0;
assign wb_s2m_debug_err = 0;
assign wb_s2m_debug_ack = 0;
//
// Wishbone CPU
//
wire [31:0] interrupts;
wire uart_interrupt;
assign interrupts [0] = 0;
assign interrupts [1] = 0;
assign interrupts [2] = uart_interrupt;
assign interrupts [3] = 0;
assign interrupts [4] = 0;
assign interrupts [5] = 0;
assign interrupts [6] = 0;
assign interrupts [7] = 0;
assign interrupts [8] = 0;
assign interrupts [9] = 0;
assign interrupts [10] = 0;
assign interrupts [11] = 0;
assign interrupts [12] = 0;
assign interrupts [13] = 0;
assign interrupts [14] = 0;
assign interrupts [15] = 0;
assign interrupts [16] = 0;
assign interrupts [17] = 0;
assign interrupts [18] = 0;
assign interrupts [19] = 0;
assign interrupts [20] = 0;
assign interrupts [21] = 0;
assign interrupts [22] = 0;
assign interrupts [23] = 0;
assign interrupts [24] = 0;
assign interrupts [25] = 0;
assign interrupts [26] = 0;
assign interrupts [27] = 0;
assign interrupts [28] = 0;
assign interrupts [29] = 0;
assign interrupts [30] = 0;
assign interrupts [31] = 0;
wishbone_cpu cpu_wrapper(
// Outputs
.iwbm_adr_o(wb_m2s_iwmb_adr),
.iwbm_stb_o(wb_m2s_iwmb_stb),
.iwbm_cyc_o(wb_m2s_iwmb_cyc),
.iwbm_sel_o(wb_m2s_iwmb_sel),
.iwbm_we_o(wb_m2s_iwmb_we),
.iwbm_cti_o(wb_m2s_iwmb_cti),
.iwbm_bte_o(wb_m2s_iwmb_bte),
.iwbm_dat_o(wb_m2s_iwmb_dat),
.dwbm_adr_o(wb_m2s_dwmb_adr),
.dwbm_stb_o(wb_m2s_dwmb_stb),
.dwbm_cyc_o(wb_m2s_dwmb_cyc),
.dwbm_sel_o(wb_m2s_dwmb_sel),
.dwbm_we_o(wb_m2s_dwmb_we),
.dwbm_cti_o(wb_m2s_dwmb_cti),
.dwbm_bte_o(wb_m2s_dwmb_bte),
.dwbm_dat_o(wb_m2s_dwmb_dat),
.dbg_lss_o(),
.dbg_is_o(),
.dbg_wp_o(),
.dbg_bp_o(),
.dbg_dat_o(),
.dbg_ack_o(),
// Inputs
.clk_i(clk_i),
.rst_i(rst_i),
.interrupts(interrupts),
.iwbm_err_i(wb_s2m_iwmb_err),
.iwbm_ack_i(wb_s2m_iwmb_ack),
.iwbm_dat_i(wb_s2m_iwmb_dat),
.iwbm_rty_i(wb_s2m_iwmb_rty),
// .iwbm_rty_i(1'b0),
.dwbm_err_i(wb_s2m_dwmb_err),
.dwbm_ack_i(wb_s2m_dwmb_ack),
.dwbm_dat_i(wb_s2m_dwmb_dat),
.dwbm_rty_i(wb_s2m_dwmb_rty),
// .dwbm_rty_i(1'b0),
.dbg_stall_i(VSS),
.dbg_ewt_i(VSS),
.dbg_stb_i(VSS),
.dbg_we_i(VSS),
.dbg_sel_i(VSS),
.dbg_cti_i({3{VSS}}),
.dbg_bte_i(VSS),
.dbg_lock_i(VSS),
.dbg_cyc_i(VSS),
.dbg_adr_i({32{VSS}}),
.dbg_dat_i({32{VSS}})
) ;
system_controller sys_con(
// Outputs
.clk_i(clk_i),
.rst_i(rst_i),
.nrst_i(nrst_i),
// Inputs
.clk_sys_i(clk_sys_i),
.rst_sys_i(reset_sys_i)
);
//
// System SRAM
//
wb_ram #(.depth(32768))
ram0(
.wb_clk_i(clk_i),
.wb_rst_i(rst_i),
.wb_adr_i(wb_m2s_ram_adr[14:0]),
.wb_dat_i(wb_m2s_ram_dat),
.wb_sel_i(wb_m2s_ram_sel),
.wb_we_i(wb_m2s_ram_we),
.wb_bte_i(wb_m2s_ram_bte),
.wb_cti_i(wb_m2s_ram_cti),
.wb_cyc_i(wb_m2s_ram_cyc),
.wb_stb_i(wb_m2s_ram_stb),
.wb_ack_o(wb_s2m_ram_ack),
.wb_err_o(wb_s2m_ram_err),
.wb_dat_o(wb_s2m_ram_dat)
);
//
// System ROM
//
wb_rom #(.depth(32768))
rom0(
.wb_clk_i(clk_i),
.wb_rst_i(rst_i),
.wb_adr_i(wb_m2s_rom_adr[14:0]),
.wb_dat_i(wb_m2s_rom_dat),
.wb_sel_i(wb_m2s_rom_sel),
// .wb_we_i(VSS),
.wb_bte_i(wb_m2s_rom_bte),
.wb_cti_i(wb_m2s_rom_cti),
.wb_cyc_i(wb_m2s_rom_cyc),
.wb_stb_i(wb_m2s_rom_stb),
.wb_ack_o(wb_s2m_rom_ack),
.wb_err_o(wb_s2m_rom_err),
.wb_dat_o(wb_s2m_rom_dat)
);
//
// UART
//
uart_top uart0(
.wb_clk_i(wb_clk_i),
// Wishbone signals
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_m2s_uart_adr[4:0]),
.wb_dat_i(wb_m2s_uart_dat),
.wb_dat_o(wb_s2m_uart_dat),
.wb_we_i(wb_m2s_uart_we),
.wb_stb_i(wb_m2s_uart_stb),
.wb_cyc_i(wb_m2s_uart_cyc),
.wb_ack_o(wb_s2m_uart_ack),
.wb_sel_i(wb_m2s_uart_sel),
.int_o(uart_interrupt), // interrupt request
// UART signals
// serial input/output
.stx_pad_o(uart_tx),
.srx_pad_i(uart_rx),
// modem signals
.rts_pad_o(),
.cts_pad_i(1'b0),
.dtr_pad_o(),
.dsr_pad_i(1'b0),
.ri_pad_i(1'b0),
.dcd_pad_i(1'b0),
.baud_o()
);
//`ifdef SIMULATION
wire [31:0] trigger_reg;
fw_interface fw_if(
// Outputs
.wb_ack_o(wb_s2m_fw_interface_ack),
.wb_rty_o(wb_s2m_fw_interface_rty),
.wb_err_o(wb_s2m_fw_interface_err),
.wb_dat_o(wb_s2m_fw_interface_dat),
.trigger_reg(trigger_reg),
// Inputs
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_m2s_fw_interface_adr),
.wb_dat_i(wb_m2s_fw_interface_dat),
.wb_sel_i(wb_m2s_fw_interface_sel),
.wb_we_i(wb_m2s_fw_interface_we),
.wb_bte_i(wb_m2s_fw_interface_bte),
.wb_cti_i(wb_m2s_fw_interface_cti),
.wb_cyc_i(wb_m2s_fw_interface_cyc),
.wb_stb_i(wb_m2s_fw_interface_stb),
.interrupts(interrupts)
) ;
/* -----\/----- EXCLUDED -----\/-----
`else // !`ifdef SIMULATION
assign wb_s2m_fw_interface_ack = 0;
assign wb_s2m_fw_interface_err = 0;
assign wb_s2m_fw_interface_dat = 0;
`endif
-----/\----- EXCLUDED -----/\----- */
endmodule // soc_template
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Antecedent does not have consequent");
end
end
end
assign fire_2state_1 = ((antecedent_expr == 1'b1) && (consequent_expr == 1'b0));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1, fire_xcheck_2;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"antecedent_expr contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"consequent_expr contains X or Z");
end
end
end
wire valid_antecedent_expr = ((antecedent_expr ^ antecedent_expr) == 1'b0);
wire valid_consequent_expr = ((consequent_expr ^ consequent_expr) == 1'b0);
always @ (valid_antecedent_expr or consequent_expr) begin
if (valid_antecedent_expr || consequent_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1; // antecedent X when consequent is 0
end
end
always @ (antecedent_expr or valid_consequent_expr) begin
if ((antecedent_expr == 1'b0) || valid_consequent_expr) begin
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_2 = 1'b1; // consequent X when antecedent is 1
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("antecedent covered"); // basic
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (antecedent_expr == 1'b1));
`endif // OVL_COVER_ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD_TB_V
`define SKY130_FD_SC_LP__BUSHOLD_TB_V
/**
* bushold: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates output driver).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bushold.v"
module top();
// Inputs are registered
reg RESET;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
RESET = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 RESET = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 RESET = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 RESET = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 RESET = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 RESET = 1'bx;
end
sky130_fd_sc_lp__bushold dut (.RESET(RESET), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD_TB_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; [email protected]. All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcd7seg.v: BCD 7-segment Decoder //
// //
// Ameer M.S. Abdelhadi ([email protected]; [email protected]), Sept. 2012 //
////////////////////////////////////////////////////////////////////////////////////
module bcd7seg (
input [3:0] bcd,
output reg [6:0] seg
);
always @(*) begin
case(bcd)
4'h0 : seg = 7'b1000000;
4'h1 : seg = 7'b1111001;
4'h2 : seg = 7'b0100100;
4'h3 : seg = 7'b0110000;
4'h4 : seg = 7'b0011001;
4'h5 : seg = 7'b0010010;
4'h6 : seg = 7'b0000010;
4'h7 : seg = 7'b1111000;
4'h8 : seg = 7'b0000000;
4'h9 : seg = 7'b0011000;
default: seg = 7'bXXXXXXX;
endcase
end
endmodule
|
// XXX Icarus can't handle parameters being use in the header
`timescale 1ns/10ps
module simpledpram(clock,
wraddress, wrdata, wren,
rdaddress, rddata);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 7;
parameter INIT_FILE = "somefile.mif";
parameter OFFSET = 0;
input clock;
input [(ADDR_WIDTH-1):0] rdaddress;
output reg [(DATA_WIDTH-1):0] rddata;
input [(DATA_WIDTH-1):0] wrdata;
input wren;
input [(ADDR_WIDTH-1):0] wraddress;
// Declare the RAM variable
(* ram_init_file = INIT_FILE *)
reg [DATA_WIDTH-1:0] ram[(1 << ADDR_WIDTH)-1:0];
parameter debug = 0;
always @ (posedge clock) begin
// Write
if (wren)
ram[wraddress] <= wrdata;
if (debug & wren)
$display("%x: ram[%x] (was %x) <= %x", OFFSET, wraddress,
ram[wraddress],
wrdata);
// Read (if rdaddress == wraddress, return OLD data). To return
// NEW data, use = (blocking write) rather than <= (non-blocking write)
// in the write assignment. NOTE: NEW data may require extra bypass
// logic around the RAM.
rddata <= ram[rdaddress];
end
initial #0 $readmemh({INIT_FILE,".data"}, ram);
endmodule
|
`timescale 1ns/1ps
module test_spi_master;
reg clk;
reg spi_tx_rd_en_256;
reg spi_rx_rd_en_256;
reg spi_rd_rst_256;
reg mode_rd_select_256;
wire sm_rd_sck_256;
wire sm_rd_mosi_256;
wire sm_rd_miso_256;
wire sm_rd_cs_n_256;
wire spi_receive_rd_status_256;
spi_ctrl_reduced #(.DATA_LENGTH(256)) spi_ctrl_reduced_instance_256(
.clk(clk),
.rst_n(spi_rd_rst_256),
.sck(sm_rd_sck_256),
.mosi(sm_rd_mosi_256),
.miso(sm_rd_miso_256),
.cs_n(sm_rd_cs_n_256),
.spi_tx_en(spi_tx_rd_en_256),
.spi_rx_en(spi_rx_rd_en_256),
.mode_select(mode_rd_select_256),
.receive_status(spi_receive_rd_status_256)
);
initial
begin
spi_rd_rst_256 = 1'b0;
spi_tx_rd_en_256 = 1'b1;
spi_rx_rd_en_256 = 1'b1;
mode_rd_select_256 = 1'b0;
clk = 0;
#10 spi_rd_rst_256 = 1;
#100000000
$stop;
end
always begin
//50M HZ about 20ns one cycle
#10 clk = ! clk;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4_1_V
`define SKY130_FD_SC_MS__AND4_1_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4_1_V
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
nope
[] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
nope
[] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** If fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
Check ([3 + 4] ++ nil).
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| O => nil
| S count' => n :: repeat n count'
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
intros. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
intros. reflexivity. Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros. induction s. reflexivity.
simpl. rewrite IHs. reflexivity.
Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros. induction l.
reflexivity.
simpl. rewrite rev_snoc, IHl. reflexivity.
Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros. induction l1.
reflexivity.
simpl. rewrite IHl1. reflexivity.
Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => ([], [])
| (x , y) :: t => (x :: fst (split t) , y :: snd (split t))
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
intros. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| nil => None
| h :: t => Some h
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
intros. reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
intros. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z :=
match p with
| (x , y) => f x y
end.
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
intros. reflexivity. Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros. destruct p. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun x => andb (evenb x) (ble_nat 7 x)) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
intros. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
intros. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l , filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
intros. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
intros. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_snoc : forall (X Y : Type) (f : X -> Y) (x : X) (l : list X),
map f (snoc l x) = snoc (map f l) (f x).
Proof.
intros. induction l.
reflexivity.
simpl. rewrite IHl. reflexivity.
Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros. induction l.
reflexivity.
simpl. rewrite map_snoc, IHl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => f h ++ flat_map f t
end.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
intros. reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
intros. reflexivity.
Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros.
unfold override. rewrite H0, H. reflexivity.
Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
intros. induction l.
reflexivity.
simpl. rewrite <- IHl. unfold fold_length. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x z => f x :: z) l [].
(** Write down a theorem in Coq stating that [fold_map] is correct,
and prove it. *)
Theorem fold_map_correct : forall (X Y : Type) (f : X -> Y) (l : list X),
fold_map f l = map f l.
Proof.
intros. induction l.
reflexivity.
simpl. rewrite <- IHl. unfold fold_map. reflexivity.
Qed.
(** [] *)
(* $Date: 2013-09-26 14:40:26 -0400 (Thu, 26 Sep 2013) $ *)
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_70x256.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_70x256 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [69:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [69:0] q;
output rdempty;
output wrfull;
wire sub_wire0;
wire sub_wire1;
wire [69:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [69:0] q = sub_wire2[69:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone III",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 70,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "70"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "70"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "70"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 70 0 INPUT NODEFVAL data[69..0]
// Retrieval info: USED_PORT: q 0 0 70 0 OUTPUT NODEFVAL q[69..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 70 0 data 0 0 70 0
// Retrieval info: CONNECT: q 0 0 70 0 @q 0 0 70 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_70x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2LV_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFHV2LV_BLACKBOX_V
/**
* lsbufhv2lv: Level-shift buffer, low voltage-to-low voltage.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbufhv2lv (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2LV_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_LS__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_PP_SYMBOL_V
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module tiny(clk, reset, sel, addr, w, data, out, done);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [197:0] data;
output [197:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
wire [197:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [197:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [197:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for muxer */
wire [197:0] muxer0_out, muxer1_out;
/* for ROM */
wire [8:0] rom_addr;
wire [25:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select
select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
rom
rom0 (clk, rom_addr, rom_q);
FSM
fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
const
const0 (clk, ram_a_addr, const0_out, const0_effective),
const1 (clk, ram_b_addr, const1_out, const1_effective);
ram
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
muxer
muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
PE
pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[193:0], muxer0_out[193:0], ram_b_data_in[193:0]);
assign ram_b_data_in[197:194] = 0;
endmodule
module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
module muxer(from_ram, from_const, const_effective, out);
input [197:0] from_ram, from_const;
input const_effective;
output [197:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_LP_V
`define SKY130_FD_SC_LP__EINVN_LP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog wrapper for einvn with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__einvn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_lp (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__einvn_lp (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_LP_V
|
// ik_swift_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1.1 166 at 2014.05.05.12:42:31
`timescale 1 ps / 1 ps
module ik_swift_hps_0 #(
parameter F2S_Width = 2,
parameter S2F_Width = 2
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire f2h_axi_clk, // f2h_axi_clock.clk
input wire [7:0] f2h_AWID, // f2h_axi_slave.awid
input wire [31:0] f2h_AWADDR, // .awaddr
input wire [3:0] f2h_AWLEN, // .awlen
input wire [2:0] f2h_AWSIZE, // .awsize
input wire [1:0] f2h_AWBURST, // .awburst
input wire [1:0] f2h_AWLOCK, // .awlock
input wire [3:0] f2h_AWCACHE, // .awcache
input wire [2:0] f2h_AWPROT, // .awprot
input wire f2h_AWVALID, // .awvalid
output wire f2h_AWREADY, // .awready
input wire [4:0] f2h_AWUSER, // .awuser
input wire [7:0] f2h_WID, // .wid
input wire [63:0] f2h_WDATA, // .wdata
input wire [7:0] f2h_WSTRB, // .wstrb
input wire f2h_WLAST, // .wlast
input wire f2h_WVALID, // .wvalid
output wire f2h_WREADY, // .wready
output wire [7:0] f2h_BID, // .bid
output wire [1:0] f2h_BRESP, // .bresp
output wire f2h_BVALID, // .bvalid
input wire f2h_BREADY, // .bready
input wire [7:0] f2h_ARID, // .arid
input wire [31:0] f2h_ARADDR, // .araddr
input wire [3:0] f2h_ARLEN, // .arlen
input wire [2:0] f2h_ARSIZE, // .arsize
input wire [1:0] f2h_ARBURST, // .arburst
input wire [1:0] f2h_ARLOCK, // .arlock
input wire [3:0] f2h_ARCACHE, // .arcache
input wire [2:0] f2h_ARPROT, // .arprot
input wire f2h_ARVALID, // .arvalid
output wire f2h_ARREADY, // .arready
input wire [4:0] f2h_ARUSER, // .aruser
output wire [7:0] f2h_RID, // .rid
output wire [63:0] f2h_RDATA, // .rdata
output wire [1:0] f2h_RRESP, // .rresp
output wire f2h_RLAST, // .rlast
output wire f2h_RVALID, // .rvalid
input wire f2h_RREADY, // .rready
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [63:0] h2f_WDATA, // .wdata
output wire [7:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [63:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
input wire [31:0] f2h_irq_p0, // f2h_irq0.irq
input wire [31:0] f2h_irq_p1, // f2h_irq1.irq
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim0_inst_CLK, // .hps_io_spim0_inst_CLK
output wire hps_io_spim0_inst_MOSI, // .hps_io_spim0_inst_MOSI
input wire hps_io_spim0_inst_MISO, // .hps_io_spim0_inst_MISO
output wire hps_io_spim0_inst_SS0, // .hps_io_spim0_inst_SS0
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL // .hps_io_i2c1_inst_SCL
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
ik_swift_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.f2h_axi_clk (f2h_axi_clk), // f2h_axi_clock.clk
.f2h_AWID (f2h_AWID), // f2h_axi_slave.awid
.f2h_AWADDR (f2h_AWADDR), // .awaddr
.f2h_AWLEN (f2h_AWLEN), // .awlen
.f2h_AWSIZE (f2h_AWSIZE), // .awsize
.f2h_AWBURST (f2h_AWBURST), // .awburst
.f2h_AWLOCK (f2h_AWLOCK), // .awlock
.f2h_AWCACHE (f2h_AWCACHE), // .awcache
.f2h_AWPROT (f2h_AWPROT), // .awprot
.f2h_AWVALID (f2h_AWVALID), // .awvalid
.f2h_AWREADY (f2h_AWREADY), // .awready
.f2h_AWUSER (f2h_AWUSER), // .awuser
.f2h_WID (f2h_WID), // .wid
.f2h_WDATA (f2h_WDATA), // .wdata
.f2h_WSTRB (f2h_WSTRB), // .wstrb
.f2h_WLAST (f2h_WLAST), // .wlast
.f2h_WVALID (f2h_WVALID), // .wvalid
.f2h_WREADY (f2h_WREADY), // .wready
.f2h_BID (f2h_BID), // .bid
.f2h_BRESP (f2h_BRESP), // .bresp
.f2h_BVALID (f2h_BVALID), // .bvalid
.f2h_BREADY (f2h_BREADY), // .bready
.f2h_ARID (f2h_ARID), // .arid
.f2h_ARADDR (f2h_ARADDR), // .araddr
.f2h_ARLEN (f2h_ARLEN), // .arlen
.f2h_ARSIZE (f2h_ARSIZE), // .arsize
.f2h_ARBURST (f2h_ARBURST), // .arburst
.f2h_ARLOCK (f2h_ARLOCK), // .arlock
.f2h_ARCACHE (f2h_ARCACHE), // .arcache
.f2h_ARPROT (f2h_ARPROT), // .arprot
.f2h_ARVALID (f2h_ARVALID), // .arvalid
.f2h_ARREADY (f2h_ARREADY), // .arready
.f2h_ARUSER (f2h_ARUSER), // .aruser
.f2h_RID (f2h_RID), // .rid
.f2h_RDATA (f2h_RDATA), // .rdata
.f2h_RRESP (f2h_RRESP), // .rresp
.f2h_RLAST (f2h_RLAST), // .rlast
.f2h_RVALID (f2h_RVALID), // .rvalid
.f2h_RREADY (f2h_RREADY), // .rready
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY), // .rready
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY), // .rready
.f2h_irq_p0 (f2h_irq_p0), // f2h_irq0.irq
.f2h_irq_p1 (f2h_irq_p1) // f2h_irq1.irq
);
ik_swift_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim0_inst_CLK (hps_io_spim0_inst_CLK), // .hps_io_spim0_inst_CLK
.hps_io_spim0_inst_MOSI (hps_io_spim0_inst_MOSI), // .hps_io_spim0_inst_MOSI
.hps_io_spim0_inst_MISO (hps_io_spim0_inst_MISO), // .hps_io_spim0_inst_MISO
.hps_io_spim0_inst_SS0 (hps_io_spim0_inst_SS0), // .hps_io_spim0_inst_SS0
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL) // .hps_io_i2c1_inst_SCL
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRBP_BLACKBOX_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrbp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// A simple adder/substracter width preconfigured input ports width and turn-around value
// Output = A - B_constant or A + B_constant
// Constraints: Awidth >= Bwidth
`timescale 1ns/1ps
module ad_addsub (
clk,
A,
Amax,
out,
CE
);
// parameters
parameter A_WIDTH = 32;
parameter CONST_VALUE = 32'h1;
parameter ADD_SUB = 0;
localparam ADDER = 0;
localparam SUBSTRACTER = 1;
// I/O definitions
input clk;
input [(A_WIDTH-1):0] A;
input [(A_WIDTH-1):0] Amax;
output [(A_WIDTH-1):0] out;
input CE;
// registers
reg [(A_WIDTH-1):0] out = 'b0;
reg [A_WIDTH:0] out_d = 'b0;
reg [A_WIDTH:0] out_d2 = 'b0;
reg [(A_WIDTH-1):0] A_d = 'b0;
reg [(A_WIDTH-1):0] A_d2 = 'b0;
reg [(A_WIDTH-1):0] Amax_d = 'b0;
reg [(A_WIDTH-1):0] Amax_d2 = 'b0;
// constant regs
reg [(A_WIDTH-1):0] B_reg = CONST_VALUE;
// latch the inputs
always @(posedge clk) begin
A_d <= A;
A_d2 <= A_d;
Amax_d <= Amax;
Amax_d2 <= Amax_d;
end
// ADDER/SUBSTRACTER
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
out_d <= A_d + B_reg;
end else begin
out_d <= A_d - B_reg;
end
end
// Resolve
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
if ( out_d > Amax_d2 ) begin
out_d2 <= out_d - Amax_d2;
end else begin
out_d2 <= out_d;
end
end else begin // SUBSTRACTER
if ( out_d[A_WIDTH] == 1'b1 ) begin
out_d2 <= Amax_d2 + out_d;
end else begin
out_d2 <= out_d;
end
end
end
// output logic
always @(posedge clk) begin
if ( CE ) begin
out <= out_d2;
end else begin
out <= 'b0;
end
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 5
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "zqynq_lab_1_design_processing_system7_0_2,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_AC\
P_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_\
WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=2,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg484,C_GP0_EN_MODIFIABLE_TXN=1,C_GP\
1_EN_MODIFIABLE_TXN=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_processing_system7_0_2 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [1 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(2),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"),
.C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"),
.C_PACKAGE_NAME("clg484"),
.C_GP0_EN_MODIFIABLE_TXN(1),
.C_GP1_EN_MODIFIABLE_TXN(1)
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\chapter{Proof Search in Ltac}% *)
(** We have seen many examples of proof automation so far, some with tantalizing code snippets from Ltac, Coq's domain-specific language for proof search procedures. This chapter aims to give a bottom-up presentation of the features of Ltac, focusing in particular on the Ltac %\index{tactics!match}%[match] construct, which supports a novel approach to backtracking search. First, though, we will run through some useful automation tactics that are built into Coq. They are described in detail in the manual, so we only outline what is possible. *)
(** * Some Built-In Automation Tactics *)
(** A number of tactics are called repeatedly by [crush]. The %\index{tactics!intuition}%[intuition] tactic simplifies propositional structure of goals. The %\index{tactics!congruence}%[congruence] tactic applies the rules of equality and congruence closure, plus properties of constructors of inductive types. The %\index{tactics!omega}%[omega] tactic provides a complete decision procedure for a theory that is called %\index{linear arithmetic}%quantifier-free linear arithmetic or %\index{Presburger arithmetic}%Presburger arithmetic, depending on whom you ask. That is, [omega] proves any goal that follows from looking only at parts of that goal that can be interpreted as propositional formulas whose atomic formulas are basic comparison operations on natural numbers or integers, with operands built from constants, variables, addition, and subtraction (with multiplication by a constant available as a shorthand for addition or subtraction).
The %\index{tactics!ring}%[ring] tactic solves goals by appealing to the axioms of rings or semi-rings (as in algebra), depending on the type involved. Coq developments may declare new types to be parts of rings and semi-rings by proving the associated axioms. There is a similar tactic [field] for simplifying values in fields by conversion to fractions over rings. Both [ring] and [field] can only solve goals that are equalities. The %\index{tactics!fourier}%[fourier] tactic uses Fourier's method to prove inequalities over real numbers, which are axiomatized in the Coq standard library.
The%\index{setoids}% _setoid_ facility makes it possible to register new equivalence relations to be understood by tactics like [rewrite]. For instance, [Prop] is registered as a setoid with the equivalence relation "if and only if." The ability to register new setoids can be very useful in proofs of a kind common in math, where all reasoning is done after "modding out by a relation."
There are several other built-in "black box" automation tactics, which one can learn about by perusing the Coq manual. The real promise of Coq, though, is in the coding of problem-specific tactics with Ltac. *)
(** * Ltac Programming Basics *)
(** We have already seen many examples of Ltac programs. In the rest of this chapter, we attempt to give a thorough introduction to the important features and design patterns.
One common use for [match] tactics is identification of subjects for case analysis, as we see in this tactic definition. *)
(* begin thide *)
Ltac find_if :=
match goal with
| [ |- if ?X then _ else _ ] => destruct X
end.
(* end thide *)
(** The tactic checks if the conclusion is an [if], [destruct]ing the test expression if so. Certain classes of theorem are trivial to prove automatically with such a tactic. *)
Theorem hmm : forall (a b c : bool),
if a
then if b
then True
else True
else if c
then True
else True.
(* begin thide *)
intros; repeat find_if; constructor.
Qed.
(* end thide *)
(** The %\index{tactics!repeat}%[repeat] that we use here is called a%\index{tactical}% _tactical_, or tactic combinator. The behavior of [repeat t] is to loop through running [t], running [t] on all generated subgoals, running [t] on _their_ generated subgoals, and so on. When [t] fails at any point in this search tree, that particular subgoal is left to be handled by later tactics. Thus, it is important never to use [repeat] with a tactic that always succeeds.
Another very useful Ltac building block is%\index{context patterns}% _context patterns_. *)
(* begin thide *)
Ltac find_if_inside :=
match goal with
| [ |- context[if ?X then _ else _] ] => destruct X
end.
(* end thide *)
(** The behavior of this tactic is to find any subterm of the conclusion that is an [if] and then [destruct] the test expression. This version subsumes [find_if]. *)
Theorem hmm' : forall (a b c : bool),
if a
then if b
then True
else True
else if c
then True
else True.
(* begin thide *)
intros; repeat find_if_inside; constructor.
Qed.
(* end thide *)
(** We can also use [find_if_inside] to prove goals that [find_if] does not simplify sufficiently. *)
Theorem hmm2 : forall (a b : bool),
(if a then 42 else 42) = (if b then 42 else 42).
(* begin thide *)
intros; repeat find_if_inside; reflexivity.
Qed.
(* end thide *)
(** Many decision procedures can be coded in Ltac via "[repeat match] loops." For instance, we can implement a subset of the functionality of [tauto]. *)
(* begin thide *)
Ltac my_tauto :=
repeat match goal with
| [ H : ?P |- ?P ] => exact H
| [ |- True ] => constructor
| [ |- _ /\ _ ] => constructor
| [ |- _ -> _ ] => intro
| [ H : False |- _ ] => destruct H
| [ H : _ /\ _ |- _ ] => destruct H
| [ H : _ \/ _ |- _ ] => destruct H
| [ H1 : ?P -> ?Q, H2 : ?P |- _ ] => specialize (H1 H2)
end.
(* end thide *)
(** Since [match] patterns can share unification variables between hypothesis and conclusion patterns, it is easy to figure out when the conclusion matches a hypothesis. The %\index{tactics!exact}%[exact] tactic solves a goal completely when given a proof term of the proper type.
It is also trivial to implement the introduction rules (in the sense of %\index{natural deduction}%natural deduction%~\cite{TAPLNatDed}%) for a few of the connectives. Implementing elimination rules is only a little more work, since we must give a name for a hypothesis to [destruct].
The last rule implements modus ponens, using a tactic %\index{tactics!specialize}%[specialize] which will replace a hypothesis with a version that is specialized to a provided set of arguments (for quantified variables or local hypotheses from implications). By convention, when the argument to [specialize] is an application of a hypothesis [H] to a set of arguments, the result of the specialization replaces [H]. For other terms, the outcome is the same as with [generalize]. *)
Section propositional.
Variables P Q R : Prop.
Theorem propositional : (P \/ Q \/ False) /\ (P -> Q) -> True /\ Q.
(* begin thide *)
my_tauto.
Qed.
(* end thide *)
End propositional.
(** It was relatively easy to implement modus ponens, because we do not lose information by clearing every implication that we use. If we want to implement a similarly complete procedure for quantifier instantiation, we need a way to ensure that a particular proposition is not already included among our hypotheses. To do that effectively, we first need to learn a bit more about the semantics of [match].
It is tempting to assume that [match] works like it does in ML. In fact, there are a few critical differences in its behavior. One is that we may include arbitrary expressions in patterns, instead of being restricted to variables and constructors. Another is that the same variable may appear multiple times, inducing an implicit equality constraint.
There is a related pair of two other differences that are much more important than the others. The [match] construct has a _backtracking semantics for failure_. In ML, pattern matching works by finding the first pattern to match and then executing its body. If the body raises an exception, then the overall match raises the same exception. In Coq, failures in case bodies instead trigger continued search through the list of cases.
For instance, this (unnecessarily verbose) proof script works: *)
Theorem m1 : True.
match goal with
| [ |- _ ] => intro
| [ |- True ] => constructor
end.
(* begin thide *)
Qed.
(* end thide *)
(** The first case matches trivially, but its body tactic fails, since the conclusion does not begin with a quantifier or implication. In a similar ML match, the whole pattern-match would fail. In Coq, we backtrack and try the next pattern, which also matches. Its body tactic succeeds, so the overall tactic succeeds as well.
The example shows how failure can move to a different pattern within a [match]. Failure can also trigger an attempt to find _a different way of matching a single pattern_. Consider another example: *)
Theorem m2 : forall P Q R : Prop, P -> Q -> R -> Q.
intros; match goal with
| [ H : _ |- _ ] => idtac H
end.
(** Coq prints "[H1]". By applying %\index{tactics!idtac}%[idtac] with an argument, a convenient debugging tool for "leaking information out of [match]es," we see that this [match] first tries binding [H] to [H1], which cannot be used to prove [Q]. Nonetheless, the following variation on the tactic succeeds at proving the goal: *)
(* begin thide *)
match goal with
| [ H : _ |- _ ] => exact H
end.
Qed.
(* end thide *)
(** The tactic first unifies [H] with [H1], as before, but [exact H] fails in that case, so the tactic engine searches for more possible values of [H]. Eventually, it arrives at the correct value, so that [exact H] and the overall tactic succeed. *)
(** Now we are equipped to implement a tactic for checking that a proposition is not among our hypotheses: *)
(* begin thide *)
Ltac notHyp P :=
match goal with
| [ _ : P |- _ ] => fail 1
| _ =>
match P with
| ?P1 /\ ?P2 => first [ notHyp P1 | notHyp P2 | fail 2 ]
| _ => idtac
end
end.
(* end thide *)
(** We use the equality checking that is built into pattern-matching to see if there is a hypothesis that matches the proposition exactly. If so, we use the %\index{tactics!fail}%[fail] tactic. Without arguments, [fail] signals normal tactic failure, as you might expect. When [fail] is passed an argument [n], [n] is used to count outwards through the enclosing cases of backtracking search. In this case, [fail 1] says "fail not just in this pattern-matching branch, but for the whole [match]." The second case will never be tried when the [fail 1] is reached.
This second case, used when [P] matches no hypothesis, checks if [P] is a conjunction. Other simplifications may have split conjunctions into their component formulas, so we need to check that at least one of those components is also not represented. To achieve this, we apply the %\index{tactics!first}%[first] tactical, which takes a list of tactics and continues down the list until one of them does not fail. The [fail 2] at the end says to [fail] both the [first] and the [match] wrapped around it.
The body of the [?P1 /\ ?P2] case guarantees that, if it is reached, we either succeed completely or fail completely. Thus, if we reach the wildcard case, [P] is not a conjunction. We use %\index{tactics!idtac}%[idtac], a tactic that would be silly to apply on its own, since its effect is to succeed at doing nothing. Nonetheless, [idtac] is a useful placeholder for cases like what we see here.
With the non-presence check implemented, it is easy to build a tactic that takes as input a proof term and adds its conclusion as a new hypothesis, only if that conclusion is not already present, failing otherwise. *)
(* begin thide *)
Ltac extend pf :=
let t := type of pf in
notHyp t; generalize pf; intro.
(* end thide *)
(** We see the useful %\index{tactics!type of}%[type of] operator of Ltac. This operator could not be implemented in Gallina, but it is easy to support in Ltac. We end up with [t] bound to the type of [pf]. We check that [t] is not already present. If so, we use a [generalize]/[intro] combo to add a new hypothesis proved by [pf]. The tactic %\index{tactics!generalize}%[generalize] takes as input a term [t] (for instance, a proof of some proposition) and then changes the conclusion from [G] to [T -> G], where [T] is the type of [t] (for instance, the proposition proved by the proof [t]).
With these tactics defined, we can write a tactic [completer] for, among other things, adding to the context all consequences of a set of simple first-order formulas. *)
(* begin thide *)
Ltac completer :=
repeat match goal with
| [ |- _ /\ _ ] => constructor
| [ H : _ /\ _ |- _ ] => destruct H
| [ H : ?P -> ?Q, H' : ?P |- _ ] => specialize (H H')
| [ |- forall x, _ ] => intro
| [ H : forall x, ?P x -> _, H' : ?P ?X |- _ ] => extend (H X H')
end.
(* end thide *)
(** We use the same kind of conjunction and implication handling as previously. Note that, since [->] is the special non-dependent case of [forall], the fourth rule handles [intro] for implications, too.
In the fifth rule, when we find a [forall] fact [H] with a premise matching one of our hypotheses, we add the appropriate instantiation of [H]'s conclusion, if we have not already added it.
We can check that [completer] is working properly, with a theorem that introduces a spurious variable whose didactic purpose we will come to shortly. *)
Section firstorder.
Variable A : Set.
Variables P Q R S : A -> Prop.
Hypothesis H1 : forall x, P x -> Q x /\ R x.
Hypothesis H2 : forall x, R x -> S x.
Theorem fo : forall (y x : A), P x -> S x.
(* begin thide *)
completer.
(** [[
y : A
x : A
H : P x
H0 : Q x
H3 : R x
H4 : S x
============================
S x
]]
*)
assumption.
Qed.
(* end thide *)
End firstorder.
(** We narrowly avoided a subtle pitfall in our definition of [completer]. Let us try another definition that even seems preferable to the original, to the untrained eye. (We change the second [match] case a bit to make the tactic smart enough to handle some subtleties of Ltac behavior that had not been exercised previously.) *)
(* begin thide *)
Ltac completer' :=
repeat match goal with
| [ |- _ /\ _ ] => constructor
| [ H : ?P /\ ?Q |- _ ] => destruct H;
repeat match goal with
| [ H' : P /\ Q |- _ ] => clear H'
end
| [ H : ?P -> _, H' : ?P |- _ ] => specialize (H H')
| [ |- forall x, _ ] => intro
| [ H : forall x, ?P x -> _, H' : ?P ?X |- _ ] => extend (H X H')
end.
(* end thide *)
(** The only other difference is in the modus ponens rule, where we have replaced an unused unification variable [?Q] with a wildcard. Let us try our example again with this version: *)
Section firstorder'.
Variable A : Set.
Variables P Q R S : A -> Prop.
Hypothesis H1 : forall x, P x -> Q x /\ R x.
Hypothesis H2 : forall x, R x -> S x.
Theorem fo' : forall (y x : A), P x -> S x.
completer'.
(** [[
y : A
H1 : P y -> Q y /\ R y
H2 : R y -> S y
x : A
H : P x
============================
S x
]]
The quantified theorems have been instantiated with [y] instead of [x], reducing a provable goal to one that is unprovable. Our code in the last [match] case for [completer'] is careful only to instantiate quantifiers along with suitable hypotheses, so why were incorrect choices made?
*)
Abort.
(* end thide *)
End firstorder'.
(** A few examples should illustrate the issue. Here we see a [match]-based proof that works fine: *)
Theorem t1 : forall x : nat, x = x.
match goal with
| [ |- forall x, _ ] => trivial
end.
(* begin thide *)
Qed.
(* end thide *)
(** This one fails. *)
(* begin thide *)
Theorem t1' : forall x : nat, x = x.
(** %\vspace{-.25in}%[[
match goal with
| [ |- forall x, ?P ] => trivial
end.
]]
<<
User error: No matching clauses for match goal
>>
*)
Abort.
(* end thide *)
(** The problem is that unification variables may not contain locally bound variables. In this case, [?P] would need to be bound to [x = x], which contains the local quantified variable [x]. By using a wildcard in the earlier version, we avoided this restriction. To understand why this restriction affects the behavior of the [completer] tactic, recall that, in Coq, implication is shorthand for degenerate universal quantification where the quantified variable is not used. Nonetheless, in an Ltac pattern, Coq is happy to match a wildcard implication against a universal quantification.
The Coq 8.2 release includes a special pattern form for a unification variable with an explicit set of free variables. That unification variable is then bound to a function from the free variables to the "real" value. In Coq 8.1 and earlier, there is no such workaround. We will see an example of this fancier binding form in Section 15.5.
No matter which Coq version you use, it is important to be aware of this restriction. As we have alluded to, the restriction is the culprit behind the surprising behavior of [completer']. We unintentionally match quantified facts with the modus ponens rule, circumventing the check that a suitably matching hypothesis is available and leading to different behavior, where wrong quantifier instantiations are chosen. Our earlier [completer] tactic uses a modus ponens rule that matches the implication conclusion with a variable, which blocks matching against non-trivial universal quantifiers.
Actually, the behavior demonstrated here applies to Coq version 8.4, but not 8.4pl1. The latter version will allow regular Ltac pattern variables to match terms that contain locally bound variables, but a tactic failure occurs if that variable is later used as a Gallina term. *)
(** * Functional Programming in Ltac *)
(* EX: Write a list length function in Ltac. *)
(** Ltac supports quite convenient functional programming, with a Lisp-with-syntax kind of flavor. However, there are a few syntactic conventions involved in getting programs to be accepted. The Ltac syntax is optimized for tactic-writing, so one has to deal with some inconveniences in writing more standard functional programs.
To illustrate, let us try to write a simple list length function. We start out writing it just as in Gallina, simply replacing [Fixpoint] (and its annotations) with [Ltac].
[[
Ltac length ls :=
match ls with
| nil => O
| _ :: ls' => S (length ls')
end.
]]
<<
Error: The reference ls' was not found in the current environment
>>
At this point, we hopefully remember that pattern variable names must be prefixed by question marks in Ltac.
[[
Ltac length ls :=
match ls with
| nil => O
| _ :: ?ls' => S (length ls')
end.
]]
<<
Error: The reference S was not found in the current environment
>>
The problem is that Ltac treats the expression [S (length ls')] as an invocation of a tactic [S] with argument [length ls']. We need to use a special annotation to "escape into" the Gallina parsing nonterminal.%\index{tactics!constr}% *)
(* begin thide *)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac length ls :=
match ls with
| nil => O
| _ :: ?ls' => constr:(S (length ls'))
end.
(** This definition is accepted. It can be a little awkward to test Ltac definitions like this one. Here is one method. *)
Goal False.
let n := length (1 :: 2 :: 3 :: nil) in
pose n.
(** [[
n := S (length (2 :: 3 :: nil)) : nat
============================
False
]]
We use the %\index{tactics!pose}%[pose] tactic, which extends the proof context with a new variable that is set equal to a particular term. We could also have used [idtac n] in place of [pose n], which would have printed the result without changing the context.
The value of [n] only has the length calculation unrolled one step. What has happened here is that, by escaping into the [constr] nonterminal, we referred to the [length] function of Gallina, rather than the [length] Ltac function that we are defining. *)
Abort.
Reset length.
(* begin hide *)
Reset red_herring.
(* end hide *)
(** The thing to remember is that Gallina terms built by tactics must be bound explicitly via [let] or a similar technique, rather than inserting Ltac calls directly in other Gallina terms. *)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac length ls :=
match ls with
| nil => O
| _ :: ?ls' =>
let ls'' := length ls' in
constr:(S ls'')
end.
Goal False.
let n := length (1 :: 2 :: 3 :: nil) in
pose n.
(** [[
n := 3 : nat
============================
False
]]
*)
Abort.
(* end thide *)
(* EX: Write a list map function in Ltac. *)
(* begin hide *)
(* begin thide *)
Definition mapp := (map, list).
(* end thide *)
(* end hide *)
(** We can also use anonymous function expressions and local function definitions in Ltac, as this example of a standard list [map] function shows. *)
(* begin thide *)
Ltac map T f :=
let rec map' ls :=
match ls with
| nil => constr:(@nil T)
| ?x :: ?ls' =>
let x' := f x in
let ls'' := map' ls' in
constr:(x' :: ls'')
end in
map'.
(** Ltac functions can have no implicit arguments. It may seem surprising that we need to pass [T], the carried type of the output list, explicitly. We cannot just use [type of f], because [f] is an Ltac term, not a Gallina term, and Ltac programs are dynamically typed. The function [f] could use very syntactic methods to decide to return differently typed terms for different inputs. We also could not replace [constr:(@nil T)] with [constr:nil], because we have no strongly typed context to use to infer the parameter to [nil]. Luckily, we do have sufficient context within [constr:(x' :: ls'')].
Sometimes we need to employ the opposite direction of "nonterminal escape," when we want to pass a complicated tactic expression as an argument to another tactic, as we might want to do in invoking %\coqdocvar{%#<tt>#map#</tt>#%}%. *)
Goal False.
let ls := map (nat * nat)%type ltac:(fun x => constr:(x, x)) (1 :: 2 :: 3 :: nil) in
pose ls.
(** [[
l := (1, 1) :: (2, 2) :: (3, 3) :: nil : list (nat * nat)
============================
False
]]
*)
Abort.
(* end thide *)
(** Each position within an Ltac script has a default applicable non-terminal, where [constr] and [ltac] are the main options worth thinking about, standing respectively for terms of Gallina and Ltac. The explicit colon notation can always be used to override the default non-terminal choice, though code being parsed as Gallina can no longer use such overrides. Within the [ltac] non-terminal, top-level function applications are treated as applications in Ltac, not Gallina; but the _arguments_ to such functions are parsed with [constr] by default. This choice may seem strange, until we realize that we have been relying on it all along in all the proof scripts we write! For instance, the [apply] tactic is an Ltac function, and it is natural to interpret its argument as a term of Gallina, not Ltac. We use an [ltac] prefix to parse Ltac function arguments as Ltac terms themselves, as in the call to %\coqdocvar{%#<tt>#map#</tt>#%}% above. For some simple cases, Ltac terms may be passed without an extra prefix. For instance, an identifier that has an Ltac meaning but no Gallina meaning will be interpreted in Ltac automatically.
One other gotcha shows up when we want to debug our Ltac functional programs. We might expect the following code to work, to give us a version of %\coqdocvar{%#<tt>#length#</tt>#%}% that prints a debug trace of the arguments it is called with. *)
(* begin thide *)
Reset length.
(* begin hide *)
Reset red_herring.
(* end hide *)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac length ls :=
idtac ls;
match ls with
| nil => O
| _ :: ?ls' =>
let ls'' := length ls' in
constr:(S ls'')
end.
(** Coq accepts the tactic definition, but the code is fatally flawed and will always lead to dynamic type errors. *)
Goal False.
(** %\vspace{-.15in}%[[
let n := length (1 :: 2 :: 3 :: nil) in
pose n.
]]
<<
Error: variable n should be bound to a term.
>> *)
Abort.
(** What is going wrong here? The answer has to do with the dual status of Ltac as both a purely functional and an imperative programming language. The basic programming language is purely functional, but tactic scripts are one "datatype" that can be returned by such programs, and Coq will run such a script using an imperative semantics that mutates proof states. Readers familiar with %\index{monad}\index{Haskell}%monadic programming in Haskell%~\cite{Monads,IO}% may recognize a similarity. Haskell programs with side effects can be thought of as pure programs that return _the code of programs in an imperative language_, where some out-of-band mechanism takes responsibility for running these derived programs. In this way, Haskell remains pure, while supporting usual input-output side effects and more. Ltac uses the same basic mechanism, but in a dynamically typed setting. Here the embedded imperative language includes all the tactics we have been applying so far.
Even basic [idtac] is an embedded imperative program, so we may not automatically mix it with purely functional code. In fact, a semicolon operator alone marks a span of Ltac code as an embedded tactic script. This makes some amount of sense, since pure functional languages have no need for sequencing: since they lack side effects, there is no reason to run an expression and then just throw away its value and move on to another expression.
An alternate explanation that avoids an analogy to Haskell monads (admittedly a tricky concept in its own right) is: An Ltac tactic program returns a function that, when run later, will perform the desired proof modification. These functions are distinct from other types of data, like numbers or Gallina terms. The prior, correctly working version of [length] computed solely with Gallina terms, but the new one is implicitly returning a tactic function, as indicated by the use of [idtac] and semicolon. However, the new version's recursive call to [length] is structured to expect a Gallina term, not a tactic function, as output. As a result, we have a basic dynamic type error, perhaps obscured by the involvement of first-class tactic scripts.
The solution is like in Haskell: we must "monadify" our pure program to give it access to side effects. The trouble is that the embedded tactic language has no [return] construct. Proof scripts are about proving theorems, not calculating results. We can apply a somewhat awkward workaround that requires translating our program into%\index{continuation-passing style}% _continuation-passing style_ %\cite{continuations}%, a program structuring idea popular in functional programming. *)
Reset length.
(* begin hide *)
Reset red_herring.
(* end hide *)
Ltac length ls k :=
idtac ls;
match ls with
| nil => k O
| _ :: ?ls' => length ls' ltac:(fun n => k (S n))
end.
(* end thide *)
(** The new [length] takes a new input: a _continuation_ [k], which is a function to be called to continue whatever proving process we were in the middle of when we called %\coqdocvar{%#<tt>#length#</tt>#%}%. The argument passed to [k] may be thought of as the return value of %\coqdocvar{%#<tt>#length#</tt>#%}%. *)
(* begin thide *)
Goal False.
length (1 :: 2 :: 3 :: nil) ltac:(fun n => pose n).
(** [[
(1 :: 2 :: 3 :: nil)
(2 :: 3 :: nil)
(3 :: nil)
nil
]]
*)
Abort.
(* end thide *)
(** We see exactly the trace of function arguments that we expected initially, and an examination of the proof state afterward would show that variable [n] has been added with value [3].
Considering the comparison with Haskell's IO monad, there is an important subtlety that deserves to be mentioned. A Haskell IO computation represents (theoretically speaking, at least) a transformer from one state of the real world to another, plus a pure value to return. Some of the state can be very specific to the program, as in the case of heap-allocated mutable references, but some can be along the lines of the favorite example "launch missile," where the program has a side effect on the real world that is not possible to undo.
In contrast, Ltac scripts can be thought of as controlling just two simple kinds of mutable state. First, there is the current sequence of proof subgoals. Second, there is a partial assignment of discovered values to unification variables introduced by proof search (for instance, by [eauto], as we saw in the previous chapter). Crucially, _every mutation of this state can be undone_ during backtracking introduced by [match], [auto], and other built-in Ltac constructs. Ltac proof scripts have state, but it is purely local, and all changes to it are reversible, which is a very useful semantics for proof search. *)
(** * Recursive Proof Search *)
(** Deciding how to instantiate quantifiers is one of the hardest parts of automated first-order theorem proving. For a given problem, we can consider all possible bounded-length sequences of quantifier instantiations, applying only propositional reasoning at the end. This is probably a bad idea for almost all goals, but it makes for a nice example of recursive proof search procedures in Ltac.
We can consider the maximum "dependency chain" length for a first-order proof. We define the chain length for a hypothesis to be 0, and the chain length for an instantiation of a quantified fact to be one greater than the length for that fact. The tactic [inster n] is meant to try all possible proofs with chain length at most [n]. *)
(* begin thide *)
Ltac inster n :=
intuition;
match n with
| S ?n' =>
match goal with
| [ H : forall x : ?T, _, y : ?T |- _ ] => generalize (H y); inster n'
end
end.
(* end thide *)
(** The tactic begins by applying propositional simplification. Next, it checks if any chain length remains, failing if not. Otherwise, it tries all possible ways of instantiating quantified hypotheses with properly typed local variables. It is critical to realize that, if the recursive call [inster n'] fails, then the [match goal] just seeks out another way of unifying its pattern against proof state. Thus, this small amount of code provides an elegant demonstration of how backtracking [match] enables exhaustive search.
We can verify the efficacy of [inster] with two short examples. The built-in [firstorder] tactic (with no extra arguments) is able to prove the first but not the second. *)
Section test_inster.
Variable A : Set.
Variables P Q : A -> Prop.
Variable f : A -> A.
Variable g : A -> A -> A.
Hypothesis H1 : forall x y, P (g x y) -> Q (f x).
Theorem test_inster : forall x, P (g x x) -> Q (f x).
inster 2.
Qed.
Hypothesis H3 : forall u v, P u /\ P v /\ u <> v -> P (g u v).
Hypothesis H4 : forall u, Q (f u) -> P u /\ P (f u).
Theorem test_inster2 : forall x y, x <> y -> P x -> Q (f y) -> Q (f x).
inster 3.
Qed.
End test_inster.
(** The style employed in the definition of [inster] can seem very counterintuitive to functional programmers. Usually, functional programs accumulate state changes in explicit arguments to recursive functions. In Ltac, the state of the current subgoal is always implicit. Nonetheless, recalling the discussion at the end of the last section, in contrast to general imperative programming, it is easy to undo any changes to this state, and indeed such "undoing" happens automatically at failures within [match]es. In this way, Ltac programming is similar to programming in Haskell with a stateful failure monad that supports a composition operator along the lines of the [first] tactical.
Functional programming purists may react indignantly to the suggestion of programming this way. Nonetheless, as with other kinds of "monadic programming," many problems are much simpler to solve with Ltac than they would be with explicit, pure proof manipulation in ML or Haskell. To demonstrate, we will write a basic simplification procedure for logical implications.
This procedure is inspired by one for separation logic%~\cite{separation}%, where conjuncts in formulas are thought of as "resources," such that we lose no completeness by "crossing out" equal conjuncts on the two sides of an implication. This process is complicated by the fact that, for reasons of modularity, our formulas can have arbitrary nested tree structure (branching at conjunctions) and may include existential quantifiers. It is helpful for the matching process to "go under" quantifiers and in fact decide how to instantiate existential quantifiers in the conclusion.
To distinguish the implications that our tactic handles from the implications that will show up as "plumbing" in various lemmas, we define a wrapper definition, a notation, and a tactic. *)
Definition imp (P1 P2 : Prop) := P1 -> P2.
Infix "-->" := imp (no associativity, at level 95).
Ltac imp := unfold imp; firstorder.
(** These lemmas about [imp] will be useful in the tactic that we will write. *)
Theorem and_True_prem : forall P Q,
(P /\ True --> Q)
-> (P --> Q).
imp.
Qed.
Theorem and_True_conc : forall P Q,
(P --> Q /\ True)
-> (P --> Q).
imp.
Qed.
Theorem pick_prem1 : forall P Q R S,
(P /\ (Q /\ R) --> S)
-> ((P /\ Q) /\ R --> S).
imp.
Qed.
Theorem pick_prem2 : forall P Q R S,
(Q /\ (P /\ R) --> S)
-> ((P /\ Q) /\ R --> S).
imp.
Qed.
Theorem comm_prem : forall P Q R,
(P /\ Q --> R)
-> (Q /\ P --> R).
imp.
Qed.
Theorem pick_conc1 : forall P Q R S,
(S --> P /\ (Q /\ R))
-> (S --> (P /\ Q) /\ R).
imp.
Qed.
Theorem pick_conc2 : forall P Q R S,
(S --> Q /\ (P /\ R))
-> (S --> (P /\ Q) /\ R).
imp.
Qed.
Theorem comm_conc : forall P Q R,
(R --> P /\ Q)
-> (R --> Q /\ P).
imp.
Qed.
(** The first order of business in crafting our [matcher] tactic will be auxiliary support for searching through formula trees. The [search_prem] tactic implements running its tactic argument [tac] on every subformula of an [imp] premise. As it traverses a tree, [search_prem] applies some of the above lemmas to rewrite the goal to bring different subformulas to the head of the goal. That is, for every subformula [P] of the implication premise, we want [P] to "have a turn," where the premise is rearranged into the form [P /\ Q] for some [Q]. The tactic [tac] should expect to see a goal in this form and focus its attention on the first conjunct of the premise. *)
Ltac search_prem tac :=
let rec search P :=
tac
|| (apply and_True_prem; tac)
|| match P with
| ?P1 /\ ?P2 =>
(apply pick_prem1; search P1)
|| (apply pick_prem2; search P2)
end
in match goal with
| [ |- ?P /\ _ --> _ ] => search P
| [ |- _ /\ ?P --> _ ] => apply comm_prem; search P
| [ |- _ --> _ ] => progress (tac || (apply and_True_prem; tac))
end.
(** To understand how [search_prem] works, we turn first to the final [match]. If the premise begins with a conjunction, we call the [search] procedure on each of the conjuncts, or only the first conjunct, if that already yields a case where [tac] does not fail. The call [search P] expects and maintains the invariant that the premise is of the form [P /\ Q] for some [Q]. We pass [P] explicitly as a kind of decreasing induction measure, to avoid looping forever when [tac] always fails. The second [match] case calls a commutativity lemma to realize this invariant, before passing control to [search]. The final [match] case tries applying [tac] directly and then, if that fails, changes the form of the goal by adding an extraneous [True] conjunct and calls [tac] again. The %\index{tactics!progress}%[progress] tactical fails when its argument tactic succeeds without changing the current subgoal.
The [search] function itself tries the same tricks as in the last case of the final [match], using the [||] operator as a shorthand for trying one tactic and then, if the first fails, trying another. Additionally, if neither works, it checks if [P] is a conjunction. If so, it calls itself recursively on each conjunct, first applying associativity/commutativity lemmas to maintain the goal-form invariant.
We will also want a dual function [search_conc], which does tree search through an [imp] conclusion. *)
Ltac search_conc tac :=
let rec search P :=
tac
|| (apply and_True_conc; tac)
|| match P with
| ?P1 /\ ?P2 =>
(apply pick_conc1; search P1)
|| (apply pick_conc2; search P2)
end
in match goal with
| [ |- _ --> ?P /\ _ ] => search P
| [ |- _ --> _ /\ ?P ] => apply comm_conc; search P
| [ |- _ --> _ ] => progress (tac || (apply and_True_conc; tac))
end.
(** Now we can prove a number of lemmas that are suitable for application by our search tactics. A lemma that is meant to handle a premise should have the form [P /\ Q --> R] for some interesting [P], and a lemma that is meant to handle a conclusion should have the form [P --> Q /\ R] for some interesting [Q]. *)
(* begin thide *)
Theorem False_prem : forall P Q,
False /\ P --> Q.
imp.
Qed.
Theorem True_conc : forall P Q : Prop,
(P --> Q)
-> (P --> True /\ Q).
imp.
Qed.
Theorem Match : forall P Q R : Prop,
(Q --> R)
-> (P /\ Q --> P /\ R).
imp.
Qed.
Theorem ex_prem : forall (T : Type) (P : T -> Prop) (Q R : Prop),
(forall x, P x /\ Q --> R)
-> (ex P /\ Q --> R).
imp.
Qed.
Theorem ex_conc : forall (T : Type) (P : T -> Prop) (Q R : Prop) x,
(Q --> P x /\ R)
-> (Q --> ex P /\ R).
imp.
Qed.
(** We will also want a "base case" lemma for finishing proofs where cancellation has removed every constituent of the conclusion. *)
Theorem imp_True : forall P,
P --> True.
imp.
Qed.
(** Our final [matcher] tactic is now straightforward. First, we [intros] all variables into scope. Then we attempt simple premise simplifications, finishing the proof upon finding [False] and eliminating any existential quantifiers that we find. After that, we search through the conclusion. We remove [True] conjuncts, remove existential quantifiers by introducing unification variables for their bound variables, and search for matching premises to cancel. Finally, when no more progress is made, we see if the goal has become trivial and can be solved by [imp_True]. In each case, we use the tactic %\index{tactics!simple apply}%[simple apply] in place of [apply] to use a simpler, less expensive unification algorithm. *)
Ltac matcher :=
intros;
repeat search_prem ltac:(simple apply False_prem || (simple apply ex_prem; intro));
repeat search_conc ltac:(simple apply True_conc || simple eapply ex_conc
|| search_prem ltac:(simple apply Match));
try simple apply imp_True.
(* end thide *)
(** Our tactic succeeds at proving a simple example. *)
Theorem t2 : forall P Q : Prop,
Q /\ (P /\ False) /\ P --> P /\ Q.
matcher.
Qed.
(** In the generated proof, we find a trace of the workings of the search tactics. *)
Print t2.
(** %\vspace{-.15in}% [[
t2 =
fun P Q : Prop =>
comm_prem (pick_prem1 (pick_prem2 (False_prem (P:=P /\ P /\ Q) (P /\ Q))))
: forall P Q : Prop, Q /\ (P /\ False) /\ P --> P /\ Q
]]
%\smallskip{}%We can also see that [matcher] is well-suited for cases where some human intervention is needed after the automation finishes. *)
Theorem t3 : forall P Q R : Prop,
P /\ Q --> Q /\ R /\ P.
matcher.
(** [[
============================
True --> R
]]
Our tactic canceled those conjuncts that it was able to cancel, leaving a simplified subgoal for us, much as [intuition] does. *)
Abort.
(** The [matcher] tactic even succeeds at guessing quantifier instantiations. It is the unification that occurs in uses of the [Match] lemma that does the real work here. *)
Theorem t4 : forall (P : nat -> Prop) Q, (exists x, P x /\ Q) --> Q /\ (exists x, P x).
matcher.
Qed.
Print t4.
(** %\vspace{-.15in}% [[
t4 =
fun (P : nat -> Prop) (Q : Prop) =>
and_True_prem
(ex_prem (P:=fun x : nat => P x /\ Q)
(fun x : nat =>
pick_prem2
(Match (P:=Q)
(and_True_conc
(ex_conc (fun x0 : nat => P x0) x
(Match (P:=P x) (imp_True (P:=True))))))))
: forall (P : nat -> Prop) (Q : Prop),
(exists x : nat, P x /\ Q) --> Q /\ (exists x : nat, P x)
]]
This proof term is a mouthful, and we can be glad that we did not build it manually! *)
(** * Creating Unification Variables *)
(** A final useful ingredient in tactic crafting is the ability to allocate new unification variables explicitly. Tactics like [eauto] introduce unification variables internally to support flexible proof search. While [eauto] and its relatives do _backward_ reasoning, we often want to do similar _forward_ reasoning, where unification variables can be useful for similar reasons.
For example, we can write a tactic that instantiates the quantifiers of a universally quantified hypothesis. The tactic should not need to know what the appropriate instantiations are; rather, we want these choices filled with placeholders. We hope that, when we apply the specialized hypothesis later, syntactic unification will determine concrete values.
Before we are ready to write a tactic, we can try out its ingredients one at a time. *)
Theorem t5 : (forall x : nat, S x > x) -> 2 > 1.
intros.
(** [[
H : forall x : nat, S x > x
============================
2 > 1
]]
To instantiate [H] generically, we first need to name the value to be used for [x].%\index{tactics!evar}% *)
evar (y : nat).
(** [[
H : forall x : nat, S x > x
y := ?279 : nat
============================
2 > 1
]]
The proof context is extended with a new variable [y], which has been assigned to be equal to a fresh unification variable [?279]. We want to instantiate [H] with [?279]. To get ahold of the new unification variable, rather than just its alias [y], we perform a trivial unfolding in the expression [y], using the %\index{tactics!eval}%[eval] Ltac construct, which works with the same reduction strategies that we have seen in tactics (e.g., [simpl], [compute], etc.). *)
let y' := eval unfold y in y in
clear y; specialize (H y').
(** [[
H : S ?279 > ?279
============================
2 > 1
]]
Our instantiation was successful. We can finish the proof by using [apply]'s unification to figure out the proper value of [?279]. *)
apply H.
Qed.
(** Now we can write a tactic that encapsulates the pattern we just employed, instantiating all quantifiers of a particular hypothesis. *)
(* begin hide *)
Definition red_herring := O.
(* end hide *)
Ltac insterU H :=
repeat match type of H with
| forall x : ?T, _ =>
let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end.
Theorem t5' : (forall x : nat, S x > x) -> 2 > 1.
intro H; insterU H; apply H.
Qed.
(** This particular example is somewhat silly, since [apply] by itself would have solved the goal originally. Separate forward reasoning is more useful on hypotheses that end in existential quantifications. Before we go through an example, it is useful to define a variant of [insterU] that does not clear the base hypothesis we pass to it. We use the Ltac construct %\index{tactics!fresh}%[fresh] to generate a hypothesis name that is not already used, based on a string suggesting a good name. *)
Ltac insterKeep H :=
let H' := fresh "H'" in
generalize H; intro H'; insterU H'.
Section t6.
Variables A B : Type.
Variable P : A -> B -> Prop.
Variable f : A -> A -> A.
Variable g : B -> B -> B.
Hypothesis H1 : forall v, exists u, P v u.
Hypothesis H2 : forall v1 u1 v2 u2,
P v1 u1
-> P v2 u2
-> P (f v1 v2) (g u1 u2).
Theorem t6 : forall v1 v2, exists u1, exists u2, P (f v1 v2) (g u1 u2).
intros.
(** Neither [eauto] nor [firstorder] is clever enough to prove this goal. We can help out by doing some of the work with quantifiers ourselves, abbreviating the proof with the %\index{tactics!do}%[do] tactical for repetition of a tactic a set number of times. *)
do 2 insterKeep H1.
(** Our proof state is extended with two generic instances of [H1].
[[
H' : exists u : B, P ?4289 u
H'0 : exists u : B, P ?4288 u
============================
exists u1 : B, exists u2 : B, P (f v1 v2) (g u1 u2)
]]
Normal [eauto] still cannot prove the goal, so we eliminate the two new existential quantifiers. (Recall that [ex] is the underlying type family to which uses of the [exists] syntax are compiled.) *)
repeat match goal with
| [ H : ex _ |- _ ] => destruct H
end.
(** Now the goal is simple enough to solve by logic programming. *)
eauto.
Qed.
End t6.
(** Our [insterU] tactic does not fare so well with quantified hypotheses that also contain implications. We can see the problem in a slight modification of the last example. We introduce a new unary predicate [Q] and use it to state an additional requirement of our hypothesis [H1]. *)
Section t7.
Variables A B : Type.
Variable Q : A -> Prop.
Variable P : A -> B -> Prop.
Variable f : A -> A -> A.
Variable g : B -> B -> B.
Hypothesis H1 : forall v, Q v -> exists u, P v u.
Hypothesis H2 : forall v1 u1 v2 u2,
P v1 u1
-> P v2 u2
-> P (f v1 v2) (g u1 u2).
Theorem t7 : forall v1 v2, Q v1 -> Q v2 -> exists u1, exists u2, P (f v1 v2) (g u1 u2).
intros; do 2 insterKeep H1;
repeat match goal with
| [ H : ex _ |- _ ] => destruct H
end; eauto.
(** This proof script does not hit any errors until the very end, when an error message like this one is displayed.
<<
No more subgoals but non-instantiated existential variables :
Existential 1 =
>>
%\vspace{-.35in}%[[
?4384 : [A : Type
B : Type
Q : A -> Prop
P : A -> B -> Prop
f : A -> A -> A
g : B -> B -> B
H1 : forall v : A, Q v -> exists u : B, P v u
H2 : forall (v1 : A) (u1 : B) (v2 : A) (u2 : B),
P v1 u1 -> P v2 u2 -> P (f v1 v2) (g u1 u2)
v1 : A
v2 : A
H : Q v1
H0 : Q v2
H' : Q v2 -> exists u : B, P v2 u |- Q v2]
]]
There is another similar line about a different existential variable. Here, "existential variable" means what we have also called "unification variable." In the course of the proof, some unification variable [?4384] was introduced but never unified. Unification variables are just a device to structure proof search; the language of Gallina proof terms does not include them. Thus, we cannot produce a proof term without instantiating the variable.
The error message shows that [?4384] is meant to be a proof of [Q v2] in a particular proof state, whose variables and hypotheses are displayed. It turns out that [?4384] was created by [insterU], as the value of a proof to pass to [H1]. Recall that, in Gallina, implication is just a degenerate case of [forall] quantification, so the [insterU] code to match against [forall] also matched the implication. Since any proof of [Q v2] is as good as any other in this context, there was never any opportunity to use unification to determine exactly which proof is appropriate. We expect similar problems with any implications in arguments to [insterU]. *)
Abort.
End t7.
Reset insterU.
(* begin hide *)
Reset red_herring.
(* end hide *)
(** We can redefine [insterU] to treat implications differently. In particular, we pattern-match on the type of the type [T] in [forall x : ?T, ...]. If [T] has type [Prop], then [x]'s instantiation should be thought of as a proof. Thus, instead of picking a new unification variable for it, we instead apply a user-supplied tactic [tac]. It is important that we end this special [Prop] case with [|| fail 1], so that, if [tac] fails to prove [T], we abort the instantiation, rather than continuing on to the default quantifier handling. Also recall that the tactic form %\index{tactics!solve}%[solve [ t ]] fails if [t] does not completely solve the goal. *)
Ltac insterU tac H :=
repeat match type of H with
| forall x : ?T, _ =>
match type of T with
| Prop =>
(let H' := fresh "H'" in
assert (H' : T) by solve [ tac ];
specialize (H H'); clear H')
|| fail 1
| _ =>
let x := fresh "x" in
evar (x : T);
let x' := eval unfold x in x in
clear x; specialize (H x')
end
end.
Ltac insterKeep tac H :=
let H' := fresh "H'" in
generalize H; intro H'; insterU tac H'.
Section t7.
Variables A B : Type.
Variable Q : A -> Prop.
Variable P : A -> B -> Prop.
Variable f : A -> A -> A.
Variable g : B -> B -> B.
Hypothesis H1 : forall v, Q v -> exists u, P v u.
Hypothesis H2 : forall v1 u1 v2 u2,
P v1 u1
-> P v2 u2
-> P (f v1 v2) (g u1 u2).
Theorem t6 : forall v1 v2, Q v1 -> Q v2 -> exists u1, exists u2, P (f v1 v2) (g u1 u2).
(** We can prove the goal by calling [insterKeep] with a tactic that tries to find and apply a [Q] hypothesis over a variable about which we do not yet know any [P] facts. We need to begin this tactic code with [idtac; ] to get around a strange limitation in Coq's proof engine, where a first-class tactic argument may not begin with a [match]. *)
intros; do 2 insterKeep ltac:(idtac; match goal with
| [ H : Q ?v |- _ ] =>
match goal with
| [ _ : context[P v _] |- _ ] => fail 1
| _ => apply H
end
end) H1;
repeat match goal with
| [ H : ex _ |- _ ] => destruct H
end; eauto.
Qed.
End t7.
(** It is often useful to instantiate existential variables explicitly. A built-in tactic provides one way of doing so. *)
Theorem t8 : exists p : nat * nat, fst p = 3.
econstructor; instantiate (1 := (3, 2)); reflexivity.
Qed.
(** The [1] above is identifying an existential variable appearing in the current goal, with the last existential appearing assigned number 1, the second-last assigned number 2, and so on. The named existential is replaced everywhere by the term to the right of the [:=].
The %\index{tactics!instantiate}%[instantiate] tactic can be convenient for exploratory proving, but it leads to very brittle proof scripts that are unlikely to adapt to changing theorem statements. It is often more helpful to have a tactic that can be used to assign a value to a term that is known to be an existential. By employing a roundabout implementation technique, we can build a tactic that generalizes this functionality. In particular, our tactic [equate] will assert that two terms are equal. If one of the terms happens to be an existential, then it will be replaced everywhere with the other term. *)
Ltac equate x y :=
let dummy := constr:(eq_refl x : x = y) in idtac.
(** This tactic fails if it is not possible to prove [x = y] by [eq_refl]. We check the proof only for its unification side effects, ignoring the associated variable [dummy]. With [equate], we can build a less brittle version of the prior example. *)
Theorem t9 : exists p : nat * nat, fst p = 3.
econstructor; match goal with
| [ |- fst ?x = 3 ] => equate x (3, 2)
end; reflexivity.
Qed.
(** This technique is even more useful within recursive and iterative tactics that are meant to solve broad classes of goals. *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_4_V
`define SKY130_FD_SC_LS__A211OI_4_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211oi_4 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_4_V
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// Internal DMA Engine ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_idma.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_idma.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.8 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.7 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.6 2001/11/03 03:26:22 rudi
//
// - Fixed several interrupt and error condition reporting bugs
//
// Revision 1.5 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
//
// Revision 1.4 2001/09/23 08:39:33 rudi
//
// Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ...
//
// Revision 1.3 2001/09/19 14:38:57 rudi
//
// Fixed TxValid handling bug.
//
// Revision 1.2 2001/09/13 13:14:02 rudi
//
// Fixed a problem that would sometimes prevent the core to come out of
// reset and immediately be operational ...
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.2 2001/03/31 13:00:51 rudi
//
// - Added Core configuration
// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
// - Modified WISHBONE interface and sync logic
// - Moved SSRAM outside the core (added interface)
// - Many small bug fixes ...
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
// Changed all revisions to revision 1.0. This is because OpenCores CVS
// interface could not handle the original '0.1' revision ....
//
// Revision 0.1.0.1 2001/02/28 08:10:50 rudi
// Initial Release
//
//
`include "usbf_defines.v"
module usbf_idma( clk, rst,
// Packet Disassembler/Assembler interface
rx_data_st, rx_data_valid, rx_data_done,
send_data, tx_data_st, rd_next,
// Protocol Engine
rx_dma_en, tx_dma_en,
abort, idma_done,
buf_size, dma_en,
send_zero_length,
// Register File Manager Interface
adr, size, sizu_c,
// Memory Arb interface
madr, mdout, mdin, mwe, mreq, mack
);
parameter SSRAM_HADR = 14;
// Packet Disassembler/Assembler interface
input clk, rst;
input [7:0] rx_data_st;
input rx_data_valid;
input rx_data_done;
output send_data;
output [7:0] tx_data_st;
input rd_next;
// Protocol Engine
input rx_dma_en; // Allows the data to be stored
input tx_dma_en; // Allows for data to be retrieved
input abort; // Abort Transfer (time_out, crc_err or rx_error)
output idma_done; // DMA is done
input [13:0] buf_size; // Actual buffer size
input dma_en; // External DMA enabled
input send_zero_length;
// Register File Manager Interface
input [SSRAM_HADR + 2:0] adr; // Byte Address
input [13:0] size; // Size in bytes
output [10:0] sizu_c; // Up and Down counting size registers, used to update
// Memory Arb interface
output [SSRAM_HADR:0] madr; // word address
output [31:0] mdout;
input [31:0] mdin;
output mwe;
output mreq;
input mack;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter [7:0]
IDLE = 8'b00000001,
WAIT_MRD = 8'b00000010,
MEM_WR = 8'b00000100,
MEM_WR1 = 8'b00001000,
MEM_WR2 = 8'b00010000,
MEM_RD1 = 8'b00100000,
MEM_RD2 = 8'b01000000,
MEM_RD3 = 8'b10000000;
reg [7:0] state, next_state;
reg tx_dma_en_r, rx_dma_en_r;
reg [SSRAM_HADR:0] adr_cw; // Internal word address counter
reg [2:0] adr_cb; // Internal byte address counter
reg [SSRAM_HADR:0] adrw_next; // next address
reg [SSRAM_HADR:0] adrw_next1; // next address (after overrun check)
reg [SSRAM_HADR:0] last_buf_adr; // Last Buffer Address
reg [2:0] adrb_next; // next byte address
reg [13:0] sizd_c; // Internal size counter
reg [10:0] sizu_c; // Internal size counter
wire adr_incw;
wire adr_incb;
wire siz_dec;
wire siz_inc;
reg word_done; // Indicates that a word has been
// assembled
reg mreq_d; // Memory request from State Machine
reg [31:0] dtmp_r; // Temp data assembly register
reg [31:0] dout_r; // Data output register
reg mwe_d; // Memory Write enable
reg dtmp_sel; // Selects tmp data register for pre-fetch
reg sizd_is_zero; // Indicates when all bytes have been
// transferred
wire sizd_is_zero_d;
reg [7:0] tx_data_st; // Data output to packet assembler
reg [31:0] rd_buf0, rd_buf1; // Mem Rd. buffers for TX
reg rd_first; // Indicates initial fill of buffers
reg idma_done; // DMA transfer is done
reg mack_r;
wire send_data; // Enable UTMI Transmitter
reg send_data_r;
reg word_done_r;
reg wr_last;
reg wr_last_en;
reg wr_done;
reg wr_done_r;
reg dtmp_sel_r;
reg mwe;
reg rx_data_done_r2;
wire fill_buf0, fill_buf1;
wire adrb_is_3;
reg rx_data_done_r;
reg rx_data_valid_r;
reg [7:0] rx_data_st_r;
reg send_zero_length_r;
///////////////////////////////////////////////////////////////////
//
// Memory Arb interface
//
// Memory Request
assign mreq = (mreq_d & !mack_r) | word_done_r;
// Output Data
assign mdout = dout_r;
// Memory Address
assign madr = adr_cw;
always @(posedge clk)
mwe <= mwe_d;
always @(posedge clk)
mack_r <= mreq & mack;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
rx_data_valid_r <= rx_data_valid;
always @(posedge clk)
rx_data_st_r <= rx_data_st;
always @(posedge clk)
rx_data_done_r <= rx_data_done;
always @(posedge clk)
rx_data_done_r2 <= rx_data_done_r;
// Generate one cycle pulses for tx and rx dma enable
always @(posedge clk)
tx_dma_en_r <= tx_dma_en;
always @(posedge clk)
rx_dma_en_r <= rx_dma_en;
always @(posedge clk)
send_zero_length_r <= send_zero_length;
// address counter
always @(posedge clk)
if(rx_dma_en_r || tx_dma_en_r) adr_cw <= adr[SSRAM_HADR + 2:2];
else adr_cw <= adrw_next1;
always @(posedge clk)
last_buf_adr <= adr + { {SSRAM_HADR+2-13{1'b0}}, buf_size };
always @(dma_en or adrw_next or last_buf_adr)
if(adrw_next == last_buf_adr && dma_en) adrw_next1 = {SSRAM_HADR+1{1'b0}};
else adrw_next1 = adrw_next;
always @(adr_incw or adr_cw)
if(adr_incw) adrw_next = adr_cw + {{SSRAM_HADR{1'b0}}, 1'b1};
else adrw_next = adr_cw;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) adr_cb <= 3'h0;
//to the prefered high reset
if(rst) adr_cb <= 3'h0;
else
if(rx_dma_en_r || tx_dma_en_r) adr_cb <= adr[2:0];
else adr_cb <= adrb_next;
always @(adr_incb or adr_cb)
if(adr_incb) adrb_next = adr_cb + 3'h1;
else adrb_next = adr_cb;
assign adr_incb = rx_data_valid_r | rd_next;
assign adr_incw = !dtmp_sel_r & mack_r;
// Size Counter (counting backward from input size)
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) sizd_c <= 14'h3fff;
//to the prefered high reset
if(rst) sizd_c <= 14'h3fff;
else
if(tx_dma_en || tx_dma_en_r) sizd_c <= size;
else
if(siz_dec) sizd_c <= sizd_c - 14'h1;
assign siz_dec = (rd_first & mack_r) | (rd_next & (sizd_c != 14'h0));
assign sizd_is_zero_d = sizd_c == 14'h0;
always @(posedge clk)
sizd_is_zero <= sizd_is_zero_d;
// Size Counter (counting up from zero)
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) sizu_c <= 11'h0;
//to the prefered high reset
if(rst) sizu_c <= 11'h0;
else
// Do I need to add "abort" in the next line ???
if(rx_dma_en_r) sizu_c <= 11'h0;
else
if(siz_inc) sizu_c <= sizu_c + 11'h1;
assign siz_inc = rx_data_valid_r;
// DMA Done Indicator
always @(posedge clk)
idma_done <= (rx_data_done_r | sizd_is_zero_d); // & !tx_dma_en;
///////////////////////////////////////////////////////////////////
//
// RX Logic
//
always @(posedge clk)
dtmp_sel_r <= dtmp_sel;
// Memory data input
always @(posedge clk)
if(dtmp_sel_r) dtmp_r <= mdin;
else
if(rx_data_valid_r)
begin
if(adr_cb[1:0] == 2'h0) dtmp_r[07:00] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h1) dtmp_r[15:08] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h2) dtmp_r[23:16] <= rx_data_st_r;
if(adr_cb[1:0] == 2'h3) dtmp_r[31:24] <= rx_data_st_r;
end
always @(posedge clk)
word_done <= ((adr_cb[1:0] == 2'h3) & rx_data_valid_r) | wr_last;
always @(posedge clk)
word_done_r <= word_done & !word_done_r;
// Store output data and address when we got a word
always @(posedge clk)
if(word_done) dout_r <= dtmp_r;
always @(posedge clk)
wr_last <= (adr_cb[1:0] != 2'h0) & !rx_data_valid_r & wr_last_en;
always @(posedge clk)
wr_done_r <= rx_data_done_r;
always @(posedge clk)
wr_done <= wr_done_r;
///////////////////////////////////////////////////////////////////
//
// TX Logic
//
// Fill TX Buffers
always @(posedge clk)
if(fill_buf0) rd_buf0 <= mdin;
always @(posedge clk)
if(fill_buf1) rd_buf1 <= mdin;
always @(adrb_next or rd_buf0 or rd_buf1)
case(adrb_next[2:0]) // synopsys full_case parallel_case
3'h0: tx_data_st = rd_buf0[07:00];
3'h1: tx_data_st = rd_buf0[15:08];
3'h2: tx_data_st = rd_buf0[23:16];
3'h3: tx_data_st = rd_buf0[31:24];
3'h4: tx_data_st = rd_buf1[07:00];
3'h5: tx_data_st = rd_buf1[15:08];
3'h6: tx_data_st = rd_buf1[23:16];
3'h7: tx_data_st = rd_buf1[31:24];
endcase
assign fill_buf0 = !adr_cw[0] & mack_r;
assign fill_buf1 = adr_cw[0] & mack_r;
assign adrb_is_3 = adr_cb[1:0] == 2'h3;
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) send_data_r <= 1'b0;
//to the prefered high reset
if(rst) send_data_r <= 1'b0;
else
if(rd_first) send_data_r <= 1'b1;
else
if(((sizd_c==14'h1) && rd_next) || sizd_is_zero_d) send_data_r <= 1'b0;
assign send_data = send_data_r | send_zero_length_r;
///////////////////////////////////////////////////////////////////
//
// IDMA Load/Store State Machine
//
// store incoming data to memory until rx_data done
// First pre-fetch data from memory, so that bytes can be stuffed properly
`ifdef USBF_ASYNC_RESET
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) state <= IDLE;
//to the prefered high reset
if(rst) state <= IDLE;
else state <= next_state;
always @(state or mack_r or abort or rx_dma_en_r or tx_dma_en_r or
sizd_is_zero or wr_last or wr_done or rx_data_done_r2 or
rd_next or adrb_is_3 or send_zero_length_r)
begin
next_state = state; // Default do not change state
mreq_d = 1'b0;
mwe_d = 1'b0;
rd_first = 1'b0;
dtmp_sel = 1'b0;
wr_last_en = 1'b0;
case(state) // synopsys full_case parallel_case
IDLE:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered IDLE state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(rst)
begin
if(rx_dma_en_r === 1'bx) $display("ERROR: IDMA: IDLE: rx_dma_en_r is unknown. (%t)", $time);
if(tx_dma_en_r === 1'bx) $display("ERROR: IDMA: IDLE: tx_dma_en_r is unknown. (%t)", $time);
if(abort === 1'bx) $display("ERROR: IDMA: IDLE: abort is unknown. (%t)", $time);
end
`endif
// synopsys translate_on
if(rx_dma_en_r && !abort)
begin
next_state = WAIT_MRD;
end
if(tx_dma_en_r && !abort && !send_zero_length_r)
begin
next_state = MEM_RD1;
end
end
WAIT_MRD: // Pre-fetch a word from memory
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered WAIT_MRD state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: WAIT_MRD: abort is unknown. (%t)", $time);
if(mack_r === 1'bx) $display("ERROR: IDMA: WAIT_MRD: mack_r is unknown. (%t)", $time);
`endif
// synopsys translate_on
if(abort) next_state = IDLE;
else
if(mack_r) next_state = MEM_WR;
else
begin
dtmp_sel = 1'b1;
mreq_d = 1'b1;
end
end
MEM_WR:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_WR state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_WR: abort is unknown. (%t)", $time);
if(rx_data_done_r2 === 1'bx) $display("ERROR: IDMA: MEM_WR: rx_data_done_r2 is unknown. (%t)", $time);
`endif
// synopsys translate_on
mwe_d = 1'b1;
if(abort) next_state = IDLE;
else
if(rx_data_done_r2)
begin
wr_last_en = 1'b1;
next_state = MEM_WR1;
end
end
MEM_WR1:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_WR1 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_WR1: abort is unknown. (%t)", $time);
if(wr_last === 1'bx) $display("ERROR: IDMA: MEM_WR1: wr_last is unknown. (%t)", $time);
if(wr_done === 1'bx) $display("ERROR: IDMA: MEM_WR1: wr_done is unknown. (%t)", $time);
`endif
// synopsys translate_on
mwe_d = 1'b1;
wr_last_en = 1'b1;
if(abort) next_state = IDLE;
else
if(wr_last) next_state = MEM_WR2;
else
if(wr_done) next_state = IDLE;
end
MEM_WR2:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_WR2 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_WR2: mack_r is unknown. (%t)", $time);
`endif
// synopsys translate_on
mwe_d = 1'b1;
if(mack_r) next_state = IDLE;
end
MEM_RD1:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_RD1 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD1: abort is unknown. (%t)", $time);
if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_RD1: mack_r is unknown. (%t)", $time);
`endif
// synopsys translate_on
mreq_d = 1'b1;
if(mack_r) rd_first = 1'b1;
if(abort) next_state = IDLE;
else
if(mack_r) next_state = MEM_RD2;
end
MEM_RD2:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_RD2 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD2: abort is unknown. (%t)", $time);
if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_RD2: mack_r is unknown. (%t)", $time);
`endif
// synopsys translate_on
mreq_d = 1'b1;
if(abort) next_state = IDLE;
else
if(mack_r) next_state = MEM_RD3;
end
MEM_RD3:
begin
// synopsys translate_off
`ifdef USBF_VERBOSE_DEBUG
$display("IDMA: Entered MEM_RD3 state (%t)", $time);
`endif
`ifdef USBF_DEBUG
if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD3: abort is unknown. (%t)", $time);
if(sizd_is_zero===1'bx) $display("ERROR: IDMA: MEM_RD3: sizd_is_zero is unknown. (%t)", $time);
if(adrb_is_3 === 1'bx) $display("ERROR: IDMA: MEM_RD3: adrb_is_3 is unknown. (%t)", $time);
if(rd_next === 1'bx) $display("ERROR: IDMA: MEM_RD3: rd_next is unknown. (%t)", $time);
`endif
// synopsys translate_on
if(sizd_is_zero || abort) next_state = IDLE;
else
if(adrb_is_3 && rd_next) next_state = MEM_RD2;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 30.06.2017 12:49:49
// Design Name:
// Module Name: singlecycleprocessor
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module singlecycleprocessor(
input clk, reset
);
wire [31:0] PCPlus4F2D, PCPlus4D2E;
wire [31:0] PCBranchM2F, PCBranchE2M;
wire [31:0] instruction;
wire [31:0] RFRead1D2E, RFRead2D2E;
wire [31:0] ImmSeD2E;
wire [31:0] ResultW2D;
wire [27:0] WAInstrD2F;
wire [4:0] rtD2E, rdD2E, WriteRegW2D;
wire [2:0] ALUControlD2E;
wire PCSrcM2F, JumpD2F, RegWriteD2E, MemToRegD2E, MemWriteD2E, BranchD2E, ALUSrcD2E, RegDstD2E;
wire RegWriteW2D;
wire [31:0] ReadDataM2W, ALUResultOutM2W;
wire [4:0] WriteRegM2W;
wire RegWriteM2W, MemToRegM2W;
wire [31:0] ALUResultE2M, WriteDataE2M;
wire [4:0] WriteRegE2M;
wire RegWriteE2M, MemToRegE2M, BranchE2M, ZerowireE2M, MemWriteE2M;
instructionfetch IF(
.PCPlus4F( PCPlus4F2D ),
.instruction( instruction ),
.PCBranchF( PCBranchM2F ),
.WAinstrF( WAInstrD2F ),
.clk( clk ),
.reset( reset ),
.JumpF( JumpD2F ),
.PCSrcF( PCSrcM2F )
);
instructiondecode ID(
.read1( RFRead1D2E ),
.read2( RFRead2D2E ),
.immediateSE( ImmSeD2E ),
.PCPlus4D2( PCPlus4D2E ),
.WAinstrD( WAInstrD2F ),
.rt( rtD2E ),
.rd( rdD2E ),
.ALUControlD( ALUControlD2E ),
.RegWriteD( RegWriteD2E ),
.MemToRegD( MemToRegD2E ),
.MemWriteD( MemWriteD2E ),
.BranchD( BranchD2E ),
.ALUSrcD( ALUSrcD2E ),
.RegDstD( RegDstD2E ),
.JumpD( JumpD2F ),
.PCPlus4D1( PCPlus4F2D ),
.instruction( instruction ),
.ResultW( ResultW2D ),
.WriteRegW( WriteRegW2D ),
.RegWriteW( RegWriteW2D ),
.clk( clk )
);
execute EX(
.ALUResult( ALUResultE2M ),
.PCBranchE( PCBranchE2M ),
.WriteDataE( WriteDataE2M ),
.WriteRegE( WriteRegE2M ),
.RegWriteE2( RegWriteE2M ), .MemToRegE2( MemToRegE2M ), .MemWriteE2( MemWriteE2M ), .BranchE2( BranchE2M ),
.ZerowireE( ZerowireE2M ),
.PCPlus4E( PCPlus4D2E ),
.srcA( RFRead1D2E ), .RegRead2( RFRead2D2E ), .SignImmE( ImmSeD2E ),
.rt( rtD2E ), .rd( rdD2E ),
.ALUControlE( ALUControlD2E ),
.ALUSrcE( ALUSrcD2E ), .RegDstE( RegDstD2E ),
.RegWriteE1( RegWriteD2E ), .MemToRegE1( MemToRegD2E ), .MemWriteE1( MemWriteD2E ), .BranchE1( BranchD2E )
);
memoryaccess MEM(
.ReadDataM( ReadDataM2W ),
.ALUResultOut( ALUResultOutM2W ),
.PCBranchM2( PCBranchM2F ),
.WriteRegM2( WriteRegM2W ),
.RegWriteM2( RegWriteM2W ),
.MemToRegM2( MemToRegM2W ),
.PCSrcM( PCSrcM2F ),
.WriteDataM( WriteDataE2M ),
.ALUResultIn( ALUResultE2M ),
.PCBranchM1( PCBranchE2M ),
.WriteRegM1( WriteRegE2M ),
.BranchM( BranchE2M ),
.MemWriteM( MemWriteE2M ),
.MemToRegM1( MemToRegE2M ),
.RegWriteM1( RegWriteE2M ),
.ZerowireM( ZerowireE2M ),
.clk( clk )
);
writeback WB(
.ResultW( ResultW2D ),
.WriteRegW2( WriteRegW2D ),
.RegWriteW2( RegWriteW2D ),
.ReadDataW( ReadDataM2W ),
.ALUResultW( ALUResultOutM2W ),
.WriteRegW1( WriteRegM2W ),
.MemToRegW( MemToRegM2W ),
.RegWriteW1( RegWriteM2W )
);
assign PCSrcM2F = BranchE2M & ZerowireE2M;
initial begin
$display(singlecycleprocessor.IF.PC);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_1_V
`define SKY130_FD_SC_LP__O41A_1_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_1 (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41a_1 (
X ,
A1,
A2,
A3,
A4,
B1
);
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_1_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage3.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module stage3 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/phd.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/phd.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage3_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:14:12 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165;
NAND2XLTS U62 ( .A(n49), .B(n133), .Y(n135) );
NAND2XLTS U63 ( .A(n48), .B(n136), .Y(n138) );
NOR2X4TS U64 ( .A(n70), .B(n75), .Y(n134) );
NAND2X4TS U65 ( .A(n132), .B(n99), .Y(n71) );
OR2X2TS U66 ( .A(n102), .B(in1[15]), .Y(n99) );
BUFX3TS U67 ( .A(n77), .Y(n75) );
OA21XLTS U68 ( .A0(n163), .A1(in1[3]), .B0(in1[2]), .Y(n152) );
NOR2X4TS U69 ( .A(n77), .B(n133), .Y(n76) );
OR2X2TS U70 ( .A(n105), .B(in1[14]), .Y(n49) );
AND2X2TS U71 ( .A(in1[0]), .B(in2[0]), .Y(n160) );
INVX3TS U72 ( .A(n46), .Y(n74) );
CLKXOR2X2TS U73 ( .A(n107), .B(in2[13]), .Y(n108) );
NOR2XLTS U74 ( .A(n106), .B(n145), .Y(n107) );
NOR2XLTS U75 ( .A(n111), .B(n145), .Y(n112) );
NAND2XLTS U76 ( .A(n122), .B(add_sub), .Y(n123) );
INVX2TS U77 ( .A(n130), .Y(n62) );
INVX2TS U78 ( .A(in1[7]), .Y(n61) );
NOR2X2TS U79 ( .A(n115), .B(n145), .Y(n116) );
NAND2X6TS U80 ( .A(n88), .B(in1[5]), .Y(n87) );
INVX6TS U81 ( .A(n92), .Y(n88) );
NAND2X6TS U82 ( .A(n69), .B(in1[4]), .Y(n92) );
NOR2X2TS U83 ( .A(n119), .B(n145), .Y(n90) );
INVX4TS U84 ( .A(add_sub), .Y(n145) );
INVX8TS U85 ( .A(in2[4]), .Y(n93) );
CLKINVX3TS U86 ( .A(in2[6]), .Y(n78) );
NOR2X1TS U87 ( .A(n122), .B(in2[10]), .Y(n111) );
OAI21XLTS U88 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n149) );
XNOR2X2TS U89 ( .A(n110), .B(in2[12]), .Y(n127) );
AND2X8TS U90 ( .A(n137), .B(n48), .Y(n46) );
OR2X4TS U91 ( .A(n108), .B(in1[13]), .Y(n48) );
NAND2BX2TS U92 ( .AN(n55), .B(n127), .Y(n52) );
NAND2X4TS U93 ( .A(n62), .B(n61), .Y(n60) );
NAND2X4TS U94 ( .A(n113), .B(n84), .Y(n122) );
NOR2X4TS U95 ( .A(n120), .B(in2[8]), .Y(n113) );
NAND2X6TS U96 ( .A(n76), .B(n74), .Y(n73) );
AND2X2TS U97 ( .A(n99), .B(n131), .Y(n47) );
NAND2X2TS U98 ( .A(n102), .B(in1[15]), .Y(n131) );
NAND2X2TS U99 ( .A(n105), .B(in1[14]), .Y(n133) );
XNOR2X2TS U100 ( .A(n101), .B(in2[15]), .Y(n102) );
NAND2X2TS U101 ( .A(n108), .B(in1[13]), .Y(n136) );
XNOR2X2TS U102 ( .A(n104), .B(in2[14]), .Y(n105) );
NAND2X6TS U103 ( .A(n64), .B(n60), .Y(n59) );
NAND2X2TS U104 ( .A(n103), .B(add_sub), .Y(n104) );
OAI21X2TS U105 ( .A0(n103), .A1(in2[14]), .B0(add_sub), .Y(n101) );
NAND2BX2TS U106 ( .AN(in2[13]), .B(n106), .Y(n103) );
NAND2X2TS U107 ( .A(n111), .B(n83), .Y(n109) );
XOR2X1TS U108 ( .A(n157), .B(n156), .Y(res[5]) );
XOR2X1TS U109 ( .A(n165), .B(n164), .Y(res[3]) );
XOR2XLTS U110 ( .A(n154), .B(n153), .Y(res[4]) );
XOR2XLTS U111 ( .A(n160), .B(n148), .Y(res[1]) );
NAND2X6TS U112 ( .A(n50), .B(add_sub), .Y(n117) );
XOR2X1TS U113 ( .A(n163), .B(in1[3]), .Y(n164) );
OAI21X1TS U114 ( .A0(n160), .A1(in1[1]), .B0(n158), .Y(n159) );
NAND2X6TS U115 ( .A(n80), .B(n51), .Y(n50) );
XOR2X1TS U116 ( .A(n158), .B(in1[1]), .Y(n148) );
AOI2BB1XLTS U117 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n160), .Y(res[0]) );
INVX3TS U118 ( .A(in2[5]), .Y(n98) );
INVX16TS U119 ( .A(in2[2]), .Y(n95) );
NAND2X4TS U120 ( .A(n118), .B(add_sub), .Y(n94) );
NAND2X4TS U121 ( .A(n59), .B(n58), .Y(n144) );
NAND4X8TS U122 ( .A(n96), .B(n100), .C(n146), .D(n95), .Y(n118) );
NOR2X8TS U123 ( .A(n137), .B(n136), .Y(n77) );
NAND2X8TS U124 ( .A(n53), .B(n52), .Y(n137) );
NAND3X8TS U125 ( .A(n93), .B(n146), .C(n95), .Y(n82) );
XOR2X2TS U126 ( .A(n132), .B(n47), .Y(res[15]) );
NAND2BX4TS U127 ( .AN(in2[7]), .B(n115), .Y(n120) );
NOR2X4TS U128 ( .A(n109), .B(in2[12]), .Y(n106) );
OR3X1TS U129 ( .A(in2[2]), .B(in2[0]), .C(in2[1]), .Y(n150) );
NOR2X4TS U130 ( .A(n82), .B(n81), .Y(n119) );
NAND2X4TS U131 ( .A(n96), .B(n100), .Y(n81) );
CLKINVX3TS U132 ( .A(n82), .Y(n51) );
INVX2TS U133 ( .A(in2[11]), .Y(n83) );
NAND2X1TS U134 ( .A(n130), .B(in1[7]), .Y(n58) );
INVX2TS U135 ( .A(in2[9]), .Y(n84) );
INVX2TS U136 ( .A(in1[12]), .Y(n55) );
BUFX3TS U137 ( .A(n46), .Y(n70) );
XNOR2X1TS U138 ( .A(n155), .B(in1[5]), .Y(n156) );
NOR2BX1TS U139 ( .AN(n86), .B(n154), .Y(n85) );
INVX2TS U140 ( .A(in1[6]), .Y(n68) );
XOR2XLTS U141 ( .A(n64), .B(n63), .Y(res[7]) );
XOR2X1TS U142 ( .A(n130), .B(in1[7]), .Y(n63) );
XOR2X1TS U143 ( .A(n126), .B(n56), .Y(res[12]) );
XNOR2X1TS U144 ( .A(n138), .B(n137), .Y(res[13]) );
AFHCINX4TS U145 ( .CIN(n141), .B(n142), .A(in1[9]), .S(res[9]), .CO(n140) );
XNOR2X2TS U146 ( .A(n151), .B(in2[3]), .Y(n163) );
XOR2X1TS U147 ( .A(n127), .B(in1[12]), .Y(n56) );
INVX2TS U148 ( .A(n127), .Y(n54) );
NAND2X2TS U149 ( .A(n109), .B(add_sub), .Y(n110) );
OR2X8TS U150 ( .A(n125), .B(in1[6]), .Y(n67) );
NAND2X8TS U151 ( .A(n72), .B(n73), .Y(n132) );
OAI2BB1X4TS U152 ( .A0N(n55), .A1N(n54), .B0(n126), .Y(n53) );
XNOR2X1TS U153 ( .A(n124), .B(n57), .Y(res[6]) );
XOR2X1TS U154 ( .A(n125), .B(n68), .Y(n57) );
NAND2X8TS U155 ( .A(n66), .B(n65), .Y(n64) );
NAND2X2TS U156 ( .A(n125), .B(in1[6]), .Y(n65) );
NAND2X8TS U157 ( .A(n124), .B(n67), .Y(n66) );
OR2X1TS U158 ( .A(n69), .B(in1[4]), .Y(n86) );
XNOR2X1TS U159 ( .A(n69), .B(in1[4]), .Y(n153) );
XOR2X4TS U160 ( .A(n94), .B(n93), .Y(n69) );
OAI21X2TS U161 ( .A0(n132), .A1(n131), .B0(n71), .Y(res[16]) );
OAI21X4TS U162 ( .A0(n46), .A1(n77), .B0(n49), .Y(n72) );
INVX16TS U163 ( .A(in2[1]), .Y(n146) );
NAND4X8TS U164 ( .A(n98), .B(n96), .C(n78), .D(n100), .Y(n79) );
NOR2X8TS U165 ( .A(n82), .B(n79), .Y(n115) );
NOR2X8TS U166 ( .A(n81), .B(in2[5]), .Y(n80) );
NOR2BX1TS U167 ( .AN(n92), .B(n85), .Y(n157) );
NAND2X8TS U168 ( .A(n89), .B(n87), .Y(n124) );
NAND2X8TS U169 ( .A(n91), .B(n155), .Y(n89) );
XOR2X4TS U170 ( .A(n90), .B(in2[5]), .Y(n155) );
NAND2X8TS U171 ( .A(n92), .B(n97), .Y(n91) );
INVX12TS U172 ( .A(in2[3]), .Y(n96) );
INVX16TS U173 ( .A(in2[0]), .Y(n100) );
INVX2TS U174 ( .A(in1[5]), .Y(n97) );
XOR2X2TS U175 ( .A(n135), .B(n134), .Y(res[14]) );
ADDFHX4TS U176 ( .A(n140), .B(in1[10]), .CI(n139), .CO(n128), .S(res[10]) );
XOR2X4TS U177 ( .A(n116), .B(in2[7]), .Y(n130) );
NOR2XLTS U178 ( .A(n145), .B(n100), .Y(n147) );
XOR2X1TS U179 ( .A(n114), .B(in2[9]), .Y(n142) );
CLKXOR2X2TS U180 ( .A(n112), .B(in2[11]), .Y(n129) );
NOR2X1TS U181 ( .A(n113), .B(n145), .Y(n114) );
XNOR2X4TS U182 ( .A(n117), .B(in2[6]), .Y(n125) );
NAND2X1TS U183 ( .A(n120), .B(add_sub), .Y(n121) );
XNOR2X1TS U184 ( .A(n121), .B(in2[8]), .Y(n143) );
XNOR2X1TS U185 ( .A(n123), .B(in2[10]), .Y(n139) );
ADDFHX4TS U186 ( .A(n129), .B(in1[11]), .CI(n128), .CO(n126), .S(res[11]) );
AFHCONX2TS U187 ( .A(in1[8]), .B(n144), .CI(n143), .CON(n141), .S(res[8]) );
XNOR2X1TS U188 ( .A(n147), .B(n146), .Y(n158) );
XNOR2X1TS U189 ( .A(n149), .B(in2[2]), .Y(n161) );
NAND2X1TS U190 ( .A(add_sub), .B(n150), .Y(n151) );
AOI22X1TS U191 ( .A0(n161), .A1(n152), .B0(in1[3]), .B1(n163), .Y(n154) );
OAI2BB1X1TS U192 ( .A0N(n160), .A1N(in1[1]), .B0(n159), .Y(n162) );
CMPR32X2TS U193 ( .A(in1[2]), .B(n162), .C(n161), .CO(n165), .S(res[2]) );
initial $sdf_annotate("Approx_adder_GeArN8R2P2_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_4_V
`define SKY130_FD_SC_LS__A311O_4_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_4_V
|
/*******************************************************************************
* Module: fifo_same_clock
* Date:2014-05-20
* Author: Andrey Filippov
* Description: Configurable synchronous FIFO using the same clock for read and write
*
* Copyright (c) 2014 Elphel, Inc.
* fifo_same_clock.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fifo_same_clock.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
`include "system_defines.vh"
//`define DEBUG_FIFO 1
module fifo_same_clock
#(
parameter integer DATA_WIDTH=16,
parameter integer DATA_DEPTH=4
)
(
input rst, // reset, active high
input clk, // clock - positive edge
input sync_rst, // synchronously reset fifo;
input we, // write enable
input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data
output [DATA_WIDTH-1:0] data_out, // output data
output nempty, // FIFO has some data
output reg half_full // FIFO half full
`ifdef DEBUG_FIFO
,output reg under, // debug outputs - under - attempt to read from empty
output reg over, // overwritten
output reg [DATA_DEPTH-1:0] wcount,
output reg [DATA_DEPTH-1:0] rcount,
output [DATA_DEPTH-1:0] num_in_fifo
`endif
);
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_read_i.raddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
// Do not understand - why?
reg [DATA_DEPTH-1:0] fill=0; // RAM fill
reg [DATA_WIDTH-1:0] inreg;
reg [DATA_WIDTH-1:0] outreg;
reg [DATA_DEPTH-1:0] ra;
reg [DATA_DEPTH-1:0] wa;
// wire [DATA_DEPTH-1:0] next_fill;
reg wem;
wire rem;
reg out_full=0; //output register full
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg ram_nempty;
// assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
assign rem= ram_nempty && (re || !out_full);
assign data_out=outreg;
assign nempty=out_full;
`ifdef DEBUG_FIFO
assign num_in_fifo=fill[DATA_DEPTH-1:0];
`endif
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else if (sync_rst) fill <= 0;
// else fill <= next_fill;
else if ( wem && ~rem) fill <= fill + 1;
else if (~wem && rem) fill <= fill - 1;
if (rst) wem <= 0;
else if (sync_rst) wem <= 0;
else wem <= we;
if (rst) ram_nempty <= 0;
else if (sync_rst) ram_nempty <= 0;
// else ram_nempty <= (next_fill != 0);
// else ram_nempty <= wem || (|fill[DATA_DEPTH-1:1]) || (fill[0] && !rem);
else ram_nempty <= (|fill[DATA_DEPTH-1:1]) || (fill[0] && wem) || ((fill[0] || wem) && !rem) ;
if (rst) wa <= 0;
else if (sync_rst) wa <= 0;
else if (wem) wa <= wa+1;
if (rst) ra <= 0;
else if (sync_rst) ra <= 0;
else if (rem) ra <= ra+1;
else if (!ram_nempty) ra <= wa; // Just recover from bit errors
if (rst) out_full <= 0;
else if (sync_rst) out_full <= 0;
else if (rem && ~re) out_full <= 1;
else if (re && ~rem) out_full <= 0;
`ifdef DEBUG_FIFO
if (rst) wcount <= 0;
else if (sync_rst) wcount <= 0;
else if (we) wcount <= wcount + 1;
if (rst) rcount <= 0;
else if (sync_rst) rcount <= 0;
else if (re) rcount <= rcount + 1;
`endif
end
// no reset elements
always @ (posedge clk) begin
half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
if (wem) ram[wa] <= inreg;
if (we) inreg <= data_in;
if (rem) outreg <= ram[ra];
`ifdef DEBUG_FIFO
under <= ~we & re & ~nempty; // underrun error
over <= we & ~re & (fill == (1<< (DATA_DEPTH-1))); // overrun error
`endif
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DIODE_PP_SYMBOL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__diode (
//# {{power|Power}}
input DIODE,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_PP_SYMBOL_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:31 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_sim_netlist.v
// Design : ip_design_zed_audio_ctrl_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
(\DataTx_R_reg[0] ,
\DataTx_R_reg[0]_0 ,
\DataTx_R_reg[0]_1 ,
\DataTx_R_reg[0]_2 ,
\DataTx_R_reg[0]_3 ,
\DataTx_R_reg[0]_4 ,
data_rdy_bit_reg,
D,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
\s_axi_rdata_i_reg[31] ,
s_axi_rvalid_i_reg,
s_axi_bvalid_i_reg,
S_AXI_ACLK,
Q,
S_AXI_ARVALID,
s_axi_bvalid_i_reg_0,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ,
S_AXI_WVALID_0,
\state_reg[1] ,
S_AXI_ARESETN,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
\DataTx_R_reg[31] ,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ,
S_AXI_RREADY,
s_axi_rvalid_i_reg_0,
S_AXI_BREADY,
s_axi_bvalid_i_reg_1);
output \DataTx_R_reg[0] ;
output \DataTx_R_reg[0]_0 ;
output \DataTx_R_reg[0]_1 ;
output \DataTx_R_reg[0]_2 ;
output \DataTx_R_reg[0]_3 ;
output \DataTx_R_reg[0]_4 ;
output data_rdy_bit_reg;
output [1:0]D;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]\s_axi_rdata_i_reg[31] ;
output s_axi_rvalid_i_reg;
output s_axi_bvalid_i_reg;
input S_AXI_ACLK;
input [1:0]Q;
input S_AXI_ARVALID;
input s_axi_bvalid_i_reg_0;
input [0:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
input S_AXI_WVALID_0;
input \state_reg[1] ;
input S_AXI_ARESETN;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]\DataTx_R_reg[31] ;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
input S_AXI_RREADY;
input s_axi_rvalid_i_reg_0;
input S_AXI_BREADY;
input s_axi_bvalid_i_reg_1;
wire Bus_RNW_reg_i_1_n_0;
wire [1:0]D;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire \DataTx_R_reg[0] ;
wire \DataTx_R_reg[0]_0 ;
wire \DataTx_R_reg[0]_1 ;
wire \DataTx_R_reg[0]_2 ;
wire \DataTx_R_reg[0]_3 ;
wire \DataTx_R_reg[0]_4 ;
wire [31:0]\DataTx_R_reg[31] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
wire [0:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ;
wire [1:0]Q;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARREADY_INST_0_i_1_n_0;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_RREADY;
wire S_AXI_WVALID;
wire S_AXI_WVALID_0;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire ce_expnd_i_4;
wire cs_ce_clr;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
wire s_axi_bvalid_i0;
wire s_axi_bvalid_i_reg;
wire s_axi_bvalid_i_reg_0;
wire s_axi_bvalid_i_reg_1;
wire \s_axi_rdata_i[0]_i_2_n_0 ;
wire \s_axi_rdata_i[0]_i_3_n_0 ;
wire \s_axi_rdata_i[0]_i_4_n_0 ;
wire \s_axi_rdata_i[10]_i_2_n_0 ;
wire \s_axi_rdata_i[11]_i_2_n_0 ;
wire \s_axi_rdata_i[12]_i_2_n_0 ;
wire \s_axi_rdata_i[13]_i_2_n_0 ;
wire \s_axi_rdata_i[14]_i_2_n_0 ;
wire \s_axi_rdata_i[15]_i_2_n_0 ;
wire \s_axi_rdata_i[16]_i_2_n_0 ;
wire \s_axi_rdata_i[17]_i_2_n_0 ;
wire \s_axi_rdata_i[18]_i_2_n_0 ;
wire \s_axi_rdata_i[19]_i_2_n_0 ;
wire \s_axi_rdata_i[1]_i_2_n_0 ;
wire \s_axi_rdata_i[20]_i_2_n_0 ;
wire \s_axi_rdata_i[21]_i_2_n_0 ;
wire \s_axi_rdata_i[22]_i_2_n_0 ;
wire \s_axi_rdata_i[23]_i_2_n_0 ;
wire \s_axi_rdata_i[23]_i_3_n_0 ;
wire \s_axi_rdata_i[23]_i_4_n_0 ;
wire \s_axi_rdata_i[2]_i_2_n_0 ;
wire \s_axi_rdata_i[3]_i_2_n_0 ;
wire \s_axi_rdata_i[4]_i_2_n_0 ;
wire \s_axi_rdata_i[5]_i_2_n_0 ;
wire \s_axi_rdata_i[6]_i_2_n_0 ;
wire \s_axi_rdata_i[7]_i_2_n_0 ;
wire \s_axi_rdata_i[8]_i_2_n_0 ;
wire \s_axi_rdata_i[9]_i_2_n_0 ;
wire [31:0]\s_axi_rdata_i_reg[31] ;
wire s_axi_rvalid_i0;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire start;
wire \state_reg[1] ;
LUT6 #(
.INIT(64'hFEFFFFFF02020202))
Bus_RNW_reg_i_1
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_AWVALID),
.I4(S_AXI_WVALID),
.I5(\DataTx_R_reg[0]_4 ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\DataTx_R_reg[0]_4 ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000004))
\DataTx_L[31]_i_1
(.I0(\DataTx_R_reg[0]_0 ),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[0]_4 ),
.I3(\DataTx_R_reg[0]_2 ),
.I4(\DataTx_R_reg[0]_3 ),
.I5(\DataTx_R_reg[0] ),
.O(\DataTx_L_reg[0] ));
LUT6 #(
.INIT(64'h0000000000000004))
\DataTx_R[31]_i_1
(.I0(\DataTx_R_reg[0]_1 ),
.I1(\DataTx_R_reg[0]_0 ),
.I2(\DataTx_R_reg[0]_4 ),
.I3(\DataTx_R_reg[0]_2 ),
.I4(\DataTx_R_reg[0]_3 ),
.I5(\DataTx_R_reg[0] ),
.O(E));
LUT6 #(
.INIT(64'h020202020202FF02))
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_4));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_4),
.Q(\DataTx_R_reg[0]_3 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h08080808FF080808))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_3));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_3),
.Q(\DataTx_R_reg[0]_2 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'h08080808FF080808))
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[1]),
.I2(S_AXI_ARADDR[0]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[1]),
.I5(S_AXI_AWADDR[0]),
.O(ce_expnd_i_2));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_2),
.Q(\DataTx_R_reg[0]_1 ),
.R(cs_ce_clr));
LUT6 #(
.INIT(64'hFF80808080808080))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ),
.I1(S_AXI_ARADDR[0]),
.I2(S_AXI_ARADDR[1]),
.I3(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ),
.I4(S_AXI_AWADDR[0]),
.I5(S_AXI_AWADDR[1]),
.O(ce_expnd_i_1));
LUT4 #(
.INIT(16'h0002))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_ARADDR[2]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3
(.I0(S_AXI_ARVALID),
.I1(S_AXI_WVALID),
.I2(S_AXI_AWVALID),
.I3(Q[1]),
.I4(Q[0]),
.I5(S_AXI_AWADDR[2]),
.O(\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_1),
.Q(\DataTx_R_reg[0]_0 ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hFD))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(S_AXI_ARESETN),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I2(S_AXI_ARREADY_INST_0_i_1_n_0),
.O(cs_ce_clr));
LUT5 #(
.INIT(32'h03020202))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2
(.I0(S_AXI_ARVALID),
.I1(Q[0]),
.I2(Q[1]),
.I3(S_AXI_AWVALID),
.I4(S_AXI_WVALID),
.O(start));
LUT5 #(
.INIT(32'hAAAAAEAA))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ),
.I2(S_AXI_AWADDR[1]),
.I3(S_AXI_AWADDR[2]),
.I4(S_AXI_AWADDR[0]),
.O(ce_expnd_i_0));
LUT6 #(
.INIT(64'h0000000000000400))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4
(.I0(S_AXI_ARADDR[0]),
.I1(S_AXI_ARADDR[2]),
.I2(S_AXI_ARADDR[1]),
.I3(S_AXI_ARVALID),
.I4(Q[0]),
.I5(Q[1]),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0 ));
LUT5 #(
.INIT(32'h00001000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5
(.I0(Q[0]),
.I1(Q[1]),
.I2(S_AXI_AWVALID),
.I3(S_AXI_WVALID),
.I4(S_AXI_ARVALID),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(S_AXI_ACLK),
.CE(start),
.D(ce_expnd_i_0),
.Q(\DataTx_R_reg[0] ),
.R(cs_ce_clr));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF8))
S_AXI_ARREADY_INST_0
(.I0(\DataTx_R_reg[0]_4 ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.O(S_AXI_ARREADY));
LUT5 #(
.INIT(32'hFFFFFFFE))
S_AXI_ARREADY_INST_0_i_1
(.I0(\DataTx_R_reg[0] ),
.I1(\DataTx_R_reg[0]_3 ),
.I2(\DataTx_R_reg[0]_2 ),
.I3(\DataTx_R_reg[0]_0 ),
.I4(\DataTx_R_reg[0]_1 ),
.O(S_AXI_ARREADY_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hF4))
S_AXI_AWREADY_INST_0
(.I0(\DataTx_R_reg[0]_4 ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.O(S_AXI_AWREADY));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFFFE))
data_rdy_bit_i_2
(.I0(\DataTx_R_reg[0] ),
.I1(\DataTx_R_reg[0]_3 ),
.I2(\DataTx_R_reg[0]_2 ),
.I3(\DataTx_R_reg[0]_4 ),
.O(data_rdy_bit_reg_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFEFFFF))
data_rdy_bit_i_3
(.I0(\DataTx_R_reg[0]_3 ),
.I1(\DataTx_R_reg[0]_2 ),
.I2(\DataTx_R_reg[0]_1 ),
.I3(\DataTx_R_reg[0]_0 ),
.I4(\DataTx_R_reg[0] ),
.I5(\DataTx_R_reg[0]_4 ),
.O(data_rdy_bit_reg));
LUT3 #(
.INIT(8'hBA))
s_axi_bvalid_i_i_1
(.I0(s_axi_bvalid_i0),
.I1(S_AXI_BREADY),
.I2(s_axi_bvalid_i_reg_1),
.O(s_axi_bvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000AE00))
s_axi_bvalid_i_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\DataTx_R_reg[0]_4 ),
.I3(Q[1]),
.I4(Q[0]),
.O(s_axi_bvalid_i0));
LUT6 #(
.INIT(64'hFFAAEAAAEAAAEAAA))
\s_axi_rdata_i[0]_i_1
(.I0(\s_axi_rdata_i[0]_i_2_n_0 ),
.I1(data_rdy_bit),
.I2(\DataTx_R_reg[0] ),
.I3(\s_axi_rdata_i[0]_i_3_n_0 ),
.I4(\DataTx_R_reg[0]_0 ),
.I5(\DataTx_R_reg[31] [0]),
.O(\s_axi_rdata_i_reg[31] [0]));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_rdata_i[0]_i_2
(.I0(\s_axi_rdata_i[0]_i_4_n_0 ),
.I1(\DataTx_L_reg[31] [0]),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [0]),
.I4(\DataRx_L_reg[23] [0]),
.I5(\s_axi_rdata_i[23]_i_2_n_0 ),
.O(\s_axi_rdata_i[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\s_axi_rdata_i[0]_i_3
(.I0(\DataTx_R_reg[0]_4 ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.O(\s_axi_rdata_i[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[0]_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_1 ),
.O(\s_axi_rdata_i[0]_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[10]_i_1
(.I0(\DataRx_L_reg[23] [10]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [10]),
.I4(\s_axi_rdata_i[10]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [10]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[10]_i_2
(.I0(\DataTx_L_reg[31] [10]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [10]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[11]_i_1
(.I0(\DataRx_L_reg[23] [11]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [11]),
.I4(\s_axi_rdata_i[11]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [11]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[11]_i_2
(.I0(\DataTx_L_reg[31] [11]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [11]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[11]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[12]_i_1
(.I0(\DataRx_L_reg[23] [12]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [12]),
.I4(\s_axi_rdata_i[12]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [12]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[12]_i_2
(.I0(\DataTx_L_reg[31] [12]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [12]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[13]_i_1
(.I0(\DataRx_L_reg[23] [13]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [13]),
.I4(\s_axi_rdata_i[13]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [13]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[13]_i_2
(.I0(\DataTx_L_reg[31] [13]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [13]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[14]_i_1
(.I0(\DataRx_L_reg[23] [14]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [14]),
.I4(\s_axi_rdata_i[14]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [14]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[14]_i_2
(.I0(\DataTx_L_reg[31] [14]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [14]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[15]_i_1
(.I0(\DataRx_L_reg[23] [15]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [15]),
.I4(\s_axi_rdata_i[15]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [15]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[15]_i_2
(.I0(\DataTx_L_reg[31] [15]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [15]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[16]_i_1
(.I0(\DataRx_L_reg[23] [16]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [16]),
.I4(\s_axi_rdata_i[16]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [16]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[16]_i_2
(.I0(\DataTx_L_reg[31] [16]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [16]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[16]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[17]_i_1
(.I0(\DataRx_L_reg[23] [17]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [17]),
.I4(\s_axi_rdata_i[17]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [17]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[17]_i_2
(.I0(\DataTx_L_reg[31] [17]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [17]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[17]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[18]_i_1
(.I0(\DataRx_L_reg[23] [18]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [18]),
.I4(\s_axi_rdata_i[18]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [18]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[18]_i_2
(.I0(\DataTx_L_reg[31] [18]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [18]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[18]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[19]_i_1
(.I0(\DataRx_L_reg[23] [19]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [19]),
.I4(\s_axi_rdata_i[19]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [19]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[19]_i_2
(.I0(\DataTx_L_reg[31] [19]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [19]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[19]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[1]_i_1
(.I0(\DataRx_L_reg[23] [1]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [1]),
.I4(\s_axi_rdata_i[1]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [1]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[1]_i_2
(.I0(\DataTx_L_reg[31] [1]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [1]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[20]_i_1
(.I0(\DataRx_L_reg[23] [20]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [20]),
.I4(\s_axi_rdata_i[20]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [20]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[20]_i_2
(.I0(\DataTx_L_reg[31] [20]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [20]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[20]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[21]_i_1
(.I0(\DataRx_L_reg[23] [21]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [21]),
.I4(\s_axi_rdata_i[21]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [21]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[21]_i_2
(.I0(\DataTx_L_reg[31] [21]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [21]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[21]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[22]_i_1
(.I0(\DataRx_L_reg[23] [22]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [22]),
.I4(\s_axi_rdata_i[22]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [22]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[22]_i_2
(.I0(\DataTx_L_reg[31] [22]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [22]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[22]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[23]_i_1
(.I0(\DataRx_L_reg[23] [23]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [23]),
.I4(\s_axi_rdata_i[23]_i_4_n_0 ),
.O(\s_axi_rdata_i_reg[31] [23]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[23]_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_3 ),
.O(\s_axi_rdata_i[23]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h80))
\s_axi_rdata_i[23]_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I1(\DataTx_R_reg[0]_4 ),
.I2(\DataTx_R_reg[0]_2 ),
.O(\s_axi_rdata_i[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[23]_i_4
(.I0(\DataTx_L_reg[31] [23]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [23]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[23]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[24]_i_1
(.I0(\DataTx_L_reg[31] [24]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [24]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [24]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[25]_i_1
(.I0(\DataTx_L_reg[31] [25]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [25]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [25]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[26]_i_1
(.I0(\DataTx_L_reg[31] [26]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [26]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [26]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[27]_i_1
(.I0(\DataTx_L_reg[31] [27]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [27]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [27]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[28]_i_1
(.I0(\DataTx_L_reg[31] [28]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [28]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [28]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[29]_i_1
(.I0(\DataTx_L_reg[31] [29]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [29]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [29]));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[2]_i_1
(.I0(\DataRx_L_reg[23] [2]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [2]),
.I4(\s_axi_rdata_i[2]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [2]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[2]_i_2
(.I0(\DataTx_L_reg[31] [2]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [2]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[30]_i_1
(.I0(\DataTx_L_reg[31] [30]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [30]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [30]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[31]_i_2
(.I0(\DataTx_L_reg[31] [31]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [31]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i_reg[31] [31]));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[3]_i_1
(.I0(\DataRx_L_reg[23] [3]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [3]),
.I4(\s_axi_rdata_i[3]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [3]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[3]_i_2
(.I0(\DataTx_L_reg[31] [3]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [3]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[4]_i_1
(.I0(\DataRx_L_reg[23] [4]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [4]),
.I4(\s_axi_rdata_i[4]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [4]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[4]_i_2
(.I0(\DataTx_L_reg[31] [4]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [4]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[5]_i_1
(.I0(\DataRx_L_reg[23] [5]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [5]),
.I4(\s_axi_rdata_i[5]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [5]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[5]_i_2
(.I0(\DataTx_L_reg[31] [5]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [5]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[6]_i_1
(.I0(\DataRx_L_reg[23] [6]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [6]),
.I4(\s_axi_rdata_i[6]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [6]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[6]_i_2
(.I0(\DataTx_L_reg[31] [6]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [6]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[7]_i_1
(.I0(\DataRx_L_reg[23] [7]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [7]),
.I4(\s_axi_rdata_i[7]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [7]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[7]_i_2
(.I0(\DataTx_L_reg[31] [7]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [7]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[8]_i_1
(.I0(\DataRx_L_reg[23] [8]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [8]),
.I4(\s_axi_rdata_i[8]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [8]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[8]_i_2
(.I0(\DataTx_L_reg[31] [8]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [8]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFFF888))
\s_axi_rdata_i[9]_i_1
(.I0(\DataRx_L_reg[23] [9]),
.I1(\s_axi_rdata_i[23]_i_2_n_0 ),
.I2(\s_axi_rdata_i[23]_i_3_n_0 ),
.I3(\DataRx_R_reg[23] [9]),
.I4(\s_axi_rdata_i[9]_i_2_n_0 ),
.O(\s_axi_rdata_i_reg[31] [9]));
LUT6 #(
.INIT(64'hF800000088000000))
\s_axi_rdata_i[9]_i_2
(.I0(\DataTx_L_reg[31] [9]),
.I1(\DataTx_R_reg[0]_1 ),
.I2(\DataTx_R_reg[31] [9]),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I4(\DataTx_R_reg[0]_4 ),
.I5(\DataTx_R_reg[0]_0 ),
.O(\s_axi_rdata_i[9]_i_2_n_0 ));
LUT3 #(
.INIT(8'hBA))
s_axi_rvalid_i_i_1
(.I0(s_axi_rvalid_i0),
.I1(S_AXI_RREADY),
.I2(s_axi_rvalid_i_reg_0),
.O(s_axi_rvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0000EA00))
s_axi_rvalid_i_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] ),
.I1(S_AXI_ARREADY_INST_0_i_1_n_0),
.I2(\DataTx_R_reg[0]_4 ),
.I3(Q[0]),
.I4(Q[1]),
.O(s_axi_rvalid_i0));
LUT4 #(
.INIT(16'hFFF4))
\state[0]_i_1
(.I0(Q[1]),
.I1(S_AXI_ARVALID),
.I2(s_axi_bvalid_i0),
.I3(s_axi_bvalid_i_reg_0),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF4454))
\state[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(S_AXI_WVALID_0),
.I3(S_AXI_ARVALID),
.I4(\state_reg[1] ),
.I5(s_axi_rvalid_i0),
.O(D[1]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
Bus_RNW_reg,
S_AXI_RVALID,
S_AXI_BVALID,
data_rdy_bit_reg,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
S_AXI_RDATA,
S_AXI_ACLK,
SR,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
Q,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] );
output \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
output Bus_RNW_reg;
output S_AXI_RVALID;
output S_AXI_BVALID;
output data_rdy_bit_reg;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]S_AXI_RDATA;
input S_AXI_ACLK;
input [0:0]SR;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]Q;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire Bus_RNW_reg;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [31:0]Q;
wire [0:0]SR;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire S_AXI_WVALID;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment I_SLAVE_ATTACHMENT
(.\DataRx_L_reg[23] (\DataRx_L_reg[23] ),
.\DataRx_R_reg[23] (\DataRx_R_reg[23] ),
.\DataTx_L_reg[0] (\DataTx_L_reg[0] ),
.\DataTx_L_reg[31] (\DataTx_L_reg[31] ),
.\DataTx_R_reg[0] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\DataTx_R_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\DataTx_R_reg[0]_1 (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\DataTx_R_reg[0]_2 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\DataTx_R_reg[0]_3 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\DataTx_R_reg[0]_4 (Bus_RNW_reg),
.E(E),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.Q(Q),
.SR(SR),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WVALID(S_AXI_WVALID),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(data_rdy_bit_reg),
.data_rdy_bit_reg_0(data_rdy_bit_reg_0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl
(out,
S_AXI_RDATA,
S_AXI_AWREADY,
S_AXI_ARREADY,
S_AXI_BVALID,
S_AXI_RVALID,
SDATA_O,
S_AXI_ACLK,
SDATA_I,
S_AXI_WDATA,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID);
output [1:0]out;
output [31:0]S_AXI_RDATA;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output S_AXI_BVALID;
output S_AXI_RVALID;
output SDATA_O;
input S_AXI_ACLK;
input SDATA_I;
input [31:0]S_AXI_WDATA;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
wire AXI_LITE_IPIF_I_n_11;
wire AXI_LITE_IPIF_I_n_12;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_8;
wire [23:0]DataRx_L;
wire [23:0]DataRx_R;
wire [31:0]DataTx_L;
wire [31:0]DataTx_R;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire SDATA_I;
wire SDATA_O;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire [31:0]S_AXI_WDATA;
wire S_AXI_WVALID;
wire USER_LOGIC_I_n_0;
wire USER_LOGIC_I_n_69;
wire data_rdy_bit;
wire [1:0]out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\DataRx_L_reg[23] (DataRx_L),
.\DataRx_R_reg[23] (DataRx_R),
.\DataTx_L_reg[0] (AXI_LITE_IPIF_I_n_12),
.\DataTx_L_reg[31] (DataTx_L),
.E(AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (USER_LOGIC_I_n_0),
.Q(DataTx_R),
.SR(USER_LOGIC_I_n_69),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WVALID(S_AXI_WVALID),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(AXI_LITE_IPIF_I_n_8),
.data_rdy_bit_reg_0(AXI_LITE_IPIF_I_n_13));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic USER_LOGIC_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.E(AXI_LITE_IPIF_I_n_12),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (AXI_LITE_IPIF_I_n_8),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (AXI_LITE_IPIF_I_n_11),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (AXI_LITE_IPIF_I_n_13),
.Q(out),
.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.SR(USER_LOGIC_I_n_69),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_WDATA(S_AXI_WDATA),
.data_rdy_bit(data_rdy_bit),
.\s_axi_rdata_i_reg[23] (DataRx_L),
.\s_axi_rdata_i_reg[23]_0 (DataRx_R),
.\s_axi_rdata_i_reg[24] (USER_LOGIC_I_n_0),
.\s_axi_rdata_i_reg[31] (DataTx_L),
.\s_axi_rdata_i_reg[31]_0 (DataTx_R));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser
(lrclk_d1,
sclk_d1,
E,
\rdata_reg_reg[23]_0 ,
\bit_cntr_reg[4]_0 ,
sdata_reg_reg,
\FSM_onehot_iis_state_reg[0] ,
data_rdy_bit_reg,
\FSM_onehot_iis_state_reg[0]_0 ,
\DataRx_L_reg[23] ,
\DataRx_R_reg[23] ,
Q,
S_AXI_ACLK,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
out,
data_rdy_bit,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
S_AXI_ARESETN,
SDATA_I);
output lrclk_d1;
output sclk_d1;
output [0:0]E;
output [0:0]\rdata_reg_reg[23]_0 ;
output [0:0]\bit_cntr_reg[4]_0 ;
output sdata_reg_reg;
output \FSM_onehot_iis_state_reg[0] ;
output data_rdy_bit_reg;
output \FSM_onehot_iis_state_reg[0]_0 ;
output [23:0]\DataRx_L_reg[23] ;
output [23:0]\DataRx_R_reg[23] ;
input [1:0]Q;
input S_AXI_ACLK;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input [2:0]out;
input data_rdy_bit;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input S_AXI_ARESETN;
input SDATA_I;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]E;
wire \FSM_onehot_iis_state_reg[0] ;
wire \FSM_onehot_iis_state_reg[0]_0 ;
wire \FSM_sequential_iis_state[0]_i_1_n_0 ;
wire \FSM_sequential_iis_state[1]_i_1_n_0 ;
wire \FSM_sequential_iis_state[2]_i_1_n_0 ;
wire \FSM_sequential_iis_state[2]_i_2_n_0 ;
wire \FSM_sequential_iis_state[2]_i_3_n_0 ;
wire \FSM_sequential_iis_state[2]_i_4_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [1:0]Q;
wire SDATA_I;
wire S_AXI_ACLK;
wire S_AXI_ARESETN;
wire \bit_cntr[4]_i_1_n_0 ;
wire [0:0]\bit_cntr_reg[4]_0 ;
wire [4:0]bit_cntr_reg__0;
wire bit_rdy;
wire data_rdy_bit;
wire data_rdy_bit_i_4_n_0;
wire data_rdy_bit_reg;
wire eqOp;
(* RTL_KEEP = "yes" *) wire [2:0]iis_state;
wire ldata_reg;
wire ldata_reg0;
wire lrclk_d1;
wire [2:0]out;
wire [4:0]plusOp__1;
wire rdata_reg0;
wire [0:0]\rdata_reg_reg[23]_0 ;
wire sclk_d1;
wire sdata_reg_reg;
LUT4 #(
.INIT(16'h0080))
\DataRx_L[23]_i_1
(.I0(eqOp),
.I1(iis_state[2]),
.I2(iis_state[1]),
.I3(iis_state[0]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000020))
\DataRx_L[23]_i_2
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[4]),
.I3(bit_cntr_reg__0[1]),
.I4(bit_cntr_reg__0[2]),
.O(eqOp));
LUT3 #(
.INIT(8'h40))
\FSM_onehot_iis_state[4]_i_3
(.I0(lrclk_d1),
.I1(Q[1]),
.I2(out[1]),
.O(\FSM_onehot_iis_state_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hDF))
\FSM_onehot_iis_state[4]_i_5
(.I0(lrclk_d1),
.I1(Q[1]),
.I2(out[0]),
.O(\FSM_onehot_iis_state_reg[0] ));
LUT6 #(
.INIT(64'h75777F7745444044))
\FSM_sequential_iis_state[0]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[0]),
.O(\FSM_sequential_iis_state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3A7B3F7B0A480048))
\FSM_sequential_iis_state[1]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[1]),
.O(\FSM_sequential_iis_state[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3FB33FB30F800080))
\FSM_sequential_iis_state[2]_i_1
(.I0(iis_state[0]),
.I1(\FSM_sequential_iis_state[2]_i_2_n_0 ),
.I2(iis_state[1]),
.I3(iis_state[2]),
.I4(\FSM_sequential_iis_state[2]_i_3_n_0 ),
.I5(iis_state[2]),
.O(\FSM_sequential_iis_state[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFA33FF000A330F))
\FSM_sequential_iis_state[2]_i_2
(.I0(bit_rdy),
.I1(\FSM_sequential_iis_state[2]_i_4_n_0 ),
.I2(iis_state[2]),
.I3(iis_state[0]),
.I4(iis_state[1]),
.I5(eqOp),
.O(\FSM_sequential_iis_state[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h22A222A2EEAE22A2))
\FSM_sequential_iis_state[2]_i_3
(.I0(bit_rdy),
.I1(iis_state[2]),
.I2(iis_state[0]),
.I3(iis_state[1]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\FSM_sequential_iis_state[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hB))
\FSM_sequential_iis_state[2]_i_4
(.I0(Q[1]),
.I1(lrclk_d1),
.O(\FSM_sequential_iis_state[2]_i_4_n_0 ));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[0]_i_1_n_0 ),
.Q(iis_state[0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[1]_i_1_n_0 ),
.Q(iis_state[1]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_sequential_iis_state_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_sequential_iis_state[2]_i_1_n_0 ),
.Q(iis_state[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\bit_cntr[0]_i_1
(.I0(bit_cntr_reg__0[0]),
.O(plusOp__1[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\bit_cntr[1]_i_1
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\bit_cntr[2]_i_1
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h6CCC))
\bit_cntr[3]_i_1
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[3]),
.I2(bit_cntr_reg__0[0]),
.I3(bit_cntr_reg__0[2]),
.O(plusOp__1[3]));
LUT3 #(
.INIT(8'hD7))
\bit_cntr[4]_i_1
(.I0(iis_state[1]),
.I1(iis_state[0]),
.I2(iis_state[2]),
.O(\bit_cntr[4]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\bit_cntr[4]_i_2
(.I0(Q[0]),
.I1(sclk_d1),
.O(bit_rdy));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h2))
\bit_cntr[4]_i_2__0
(.I0(sclk_d1),
.I1(Q[0]),
.O(\bit_cntr_reg[4]_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h78F0F0F0))
\bit_cntr[4]_i_3
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[2]),
.I2(bit_cntr_reg__0[4]),
.I3(bit_cntr_reg__0[1]),
.I4(bit_cntr_reg__0[0]),
.O(plusOp__1[4]));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[0]),
.Q(bit_cntr_reg__0[0]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[1]),
.Q(bit_cntr_reg__0[1]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[2]),
.Q(bit_cntr_reg__0[2]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[3]),
.Q(bit_cntr_reg__0[3]),
.R(\bit_cntr[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(bit_rdy),
.D(plusOp__1[4]),
.Q(bit_cntr_reg__0[4]),
.R(\bit_cntr[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCC00EA0000000000))
data_rdy_bit_i_1
(.I0(data_rdy_bit),
.I1(E),
.I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.I4(data_rdy_bit_i_4_n_0),
.I5(S_AXI_ARESETN),
.O(data_rdy_bit_reg));
LUT6 #(
.INIT(64'h0000000090000000))
data_rdy_bit_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I2(eqOp),
.I3(iis_state[2]),
.I4(iis_state[1]),
.I5(iis_state[0]),
.O(data_rdy_bit_i_4_n_0));
LUT3 #(
.INIT(8'h01))
\ldata_reg[23]_i_1
(.I0(iis_state[1]),
.I1(iis_state[0]),
.I2(iis_state[2]),
.O(ldata_reg));
LUT5 #(
.INIT(32'h00004000))
\ldata_reg[23]_i_2
(.I0(iis_state[2]),
.I1(iis_state[0]),
.I2(iis_state[1]),
.I3(Q[0]),
.I4(sclk_d1),
.O(ldata_reg0));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(SDATA_I),
.Q(\DataRx_L_reg[23] [0]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [9]),
.Q(\DataRx_L_reg[23] [10]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [10]),
.Q(\DataRx_L_reg[23] [11]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [11]),
.Q(\DataRx_L_reg[23] [12]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [12]),
.Q(\DataRx_L_reg[23] [13]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [13]),
.Q(\DataRx_L_reg[23] [14]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [14]),
.Q(\DataRx_L_reg[23] [15]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [15]),
.Q(\DataRx_L_reg[23] [16]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [16]),
.Q(\DataRx_L_reg[23] [17]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [17]),
.Q(\DataRx_L_reg[23] [18]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [18]),
.Q(\DataRx_L_reg[23] [19]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [0]),
.Q(\DataRx_L_reg[23] [1]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [19]),
.Q(\DataRx_L_reg[23] [20]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [20]),
.Q(\DataRx_L_reg[23] [21]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [21]),
.Q(\DataRx_L_reg[23] [22]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [22]),
.Q(\DataRx_L_reg[23] [23]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [1]),
.Q(\DataRx_L_reg[23] [2]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [2]),
.Q(\DataRx_L_reg[23] [3]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [3]),
.Q(\DataRx_L_reg[23] [4]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [4]),
.Q(\DataRx_L_reg[23] [5]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [5]),
.Q(\DataRx_L_reg[23] [6]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [6]),
.Q(\DataRx_L_reg[23] [7]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [7]),
.Q(\DataRx_L_reg[23] [8]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(ldata_reg0),
.D(\DataRx_L_reg[23] [8]),
.Q(\DataRx_L_reg[23] [9]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
lrclk_d1_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Q[1]),
.Q(lrclk_d1),
.R(1'b0));
LUT5 #(
.INIT(32'h00004000))
\rdata_reg[23]_i_1
(.I0(iis_state[0]),
.I1(iis_state[1]),
.I2(iis_state[2]),
.I3(Q[0]),
.I4(sclk_d1),
.O(rdata_reg0));
LUT6 #(
.INIT(64'h4040FF4040404040))
\rdata_reg[23]_i_1__0
(.I0(Q[0]),
.I1(sclk_d1),
.I2(out[2]),
.I3(out[0]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\rdata_reg_reg[23]_0 ));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(SDATA_I),
.Q(\DataRx_R_reg[23] [0]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [9]),
.Q(\DataRx_R_reg[23] [10]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [10]),
.Q(\DataRx_R_reg[23] [11]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [11]),
.Q(\DataRx_R_reg[23] [12]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [12]),
.Q(\DataRx_R_reg[23] [13]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [13]),
.Q(\DataRx_R_reg[23] [14]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [14]),
.Q(\DataRx_R_reg[23] [15]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [15]),
.Q(\DataRx_R_reg[23] [16]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [16]),
.Q(\DataRx_R_reg[23] [17]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [17]),
.Q(\DataRx_R_reg[23] [18]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [18]),
.Q(\DataRx_R_reg[23] [19]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [0]),
.Q(\DataRx_R_reg[23] [1]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [19]),
.Q(\DataRx_R_reg[23] [20]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [20]),
.Q(\DataRx_R_reg[23] [21]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [21]),
.Q(\DataRx_R_reg[23] [22]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [22]),
.Q(\DataRx_R_reg[23] [23]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [1]),
.Q(\DataRx_R_reg[23] [2]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [2]),
.Q(\DataRx_R_reg[23] [3]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [3]),
.Q(\DataRx_R_reg[23] [4]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [4]),
.Q(\DataRx_R_reg[23] [5]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [5]),
.Q(\DataRx_R_reg[23] [6]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [6]),
.Q(\DataRx_R_reg[23] [7]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [7]),
.Q(\DataRx_R_reg[23] [8]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(rdata_reg0),
.D(\DataRx_R_reg[23] [8]),
.Q(\DataRx_R_reg[23] [9]),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
sclk_d1_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Q[0]),
.Q(sclk_d1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hB))
sdata_reg_i_2
(.I0(Q[0]),
.I1(sclk_d1),
.O(sdata_reg_reg));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser
(SDATA_O,
out,
S_AXI_ACLK,
Q,
sclk_d1,
lrclk_d1,
\DataTx_L_reg[23] ,
\DataTx_R_reg[23] ,
\clk_cntr_reg[4] ,
lrclk_d1_reg,
lrclk_d1_reg_0,
E,
sclk_d1_reg);
output SDATA_O;
output [2:0]out;
input S_AXI_ACLK;
input [1:0]Q;
input sclk_d1;
input lrclk_d1;
input [23:0]\DataTx_L_reg[23] ;
input [23:0]\DataTx_R_reg[23] ;
input \clk_cntr_reg[4] ;
input lrclk_d1_reg;
input lrclk_d1_reg_0;
input [0:0]E;
input [0:0]sclk_d1_reg;
wire [23:0]\DataTx_L_reg[23] ;
wire [23:0]\DataTx_R_reg[23] ;
wire [0:0]E;
wire \FSM_onehot_iis_state[1]_i_1_n_0 ;
wire \FSM_onehot_iis_state[2]_i_1_n_0 ;
wire \FSM_onehot_iis_state[3]_i_1_n_0 ;
wire \FSM_onehot_iis_state[4]_i_1_n_0 ;
wire \FSM_onehot_iis_state[4]_i_2_n_0 ;
wire [1:0]Q;
wire SDATA_O;
wire S_AXI_ACLK;
wire \bit_cntr[4]_i_1__0_n_0 ;
wire [4:0]bit_cntr_reg__0;
wire \clk_cntr_reg[4] ;
wire eqOp;
(* RTL_KEEP = "yes" *) wire ldata_reg;
wire \ldata_reg[0]_i_1_n_0 ;
wire \ldata_reg[10]_i_1_n_0 ;
wire \ldata_reg[11]_i_1_n_0 ;
wire \ldata_reg[12]_i_1_n_0 ;
wire \ldata_reg[13]_i_1_n_0 ;
wire \ldata_reg[14]_i_1_n_0 ;
wire \ldata_reg[15]_i_1_n_0 ;
wire \ldata_reg[16]_i_1_n_0 ;
wire \ldata_reg[17]_i_1_n_0 ;
wire \ldata_reg[18]_i_1_n_0 ;
wire \ldata_reg[19]_i_1_n_0 ;
wire \ldata_reg[1]_i_1_n_0 ;
wire \ldata_reg[20]_i_1_n_0 ;
wire \ldata_reg[21]_i_1_n_0 ;
wire \ldata_reg[22]_i_1_n_0 ;
wire \ldata_reg[23]_i_1__0_n_0 ;
wire \ldata_reg[23]_i_2__0_n_0 ;
wire \ldata_reg[2]_i_1_n_0 ;
wire \ldata_reg[3]_i_1_n_0 ;
wire \ldata_reg[4]_i_1_n_0 ;
wire \ldata_reg[5]_i_1_n_0 ;
wire \ldata_reg[6]_i_1_n_0 ;
wire \ldata_reg[7]_i_1_n_0 ;
wire \ldata_reg[8]_i_1_n_0 ;
wire \ldata_reg[9]_i_1_n_0 ;
wire \ldata_reg_reg_n_0_[0] ;
wire \ldata_reg_reg_n_0_[10] ;
wire \ldata_reg_reg_n_0_[11] ;
wire \ldata_reg_reg_n_0_[12] ;
wire \ldata_reg_reg_n_0_[13] ;
wire \ldata_reg_reg_n_0_[14] ;
wire \ldata_reg_reg_n_0_[15] ;
wire \ldata_reg_reg_n_0_[16] ;
wire \ldata_reg_reg_n_0_[17] ;
wire \ldata_reg_reg_n_0_[18] ;
wire \ldata_reg_reg_n_0_[19] ;
wire \ldata_reg_reg_n_0_[1] ;
wire \ldata_reg_reg_n_0_[20] ;
wire \ldata_reg_reg_n_0_[21] ;
wire \ldata_reg_reg_n_0_[22] ;
wire \ldata_reg_reg_n_0_[2] ;
wire \ldata_reg_reg_n_0_[3] ;
wire \ldata_reg_reg_n_0_[4] ;
wire \ldata_reg_reg_n_0_[5] ;
wire \ldata_reg_reg_n_0_[6] ;
wire \ldata_reg_reg_n_0_[7] ;
wire \ldata_reg_reg_n_0_[8] ;
wire \ldata_reg_reg_n_0_[9] ;
wire lrclk_d1;
wire lrclk_d1_reg;
wire lrclk_d1_reg_0;
(* RTL_KEEP = "yes" *) wire [2:0]out;
(* RTL_KEEP = "yes" *) wire p_0_in2_in;
wire [23:0]p_1_in;
wire p_2_in;
wire [4:0]plusOp__2;
wire \rdata_reg_reg_n_0_[0] ;
wire \rdata_reg_reg_n_0_[10] ;
wire \rdata_reg_reg_n_0_[11] ;
wire \rdata_reg_reg_n_0_[12] ;
wire \rdata_reg_reg_n_0_[13] ;
wire \rdata_reg_reg_n_0_[14] ;
wire \rdata_reg_reg_n_0_[15] ;
wire \rdata_reg_reg_n_0_[16] ;
wire \rdata_reg_reg_n_0_[17] ;
wire \rdata_reg_reg_n_0_[18] ;
wire \rdata_reg_reg_n_0_[19] ;
wire \rdata_reg_reg_n_0_[1] ;
wire \rdata_reg_reg_n_0_[20] ;
wire \rdata_reg_reg_n_0_[21] ;
wire \rdata_reg_reg_n_0_[22] ;
wire \rdata_reg_reg_n_0_[23] ;
wire \rdata_reg_reg_n_0_[2] ;
wire \rdata_reg_reg_n_0_[3] ;
wire \rdata_reg_reg_n_0_[4] ;
wire \rdata_reg_reg_n_0_[5] ;
wire \rdata_reg_reg_n_0_[6] ;
wire \rdata_reg_reg_n_0_[7] ;
wire \rdata_reg_reg_n_0_[8] ;
wire \rdata_reg_reg_n_0_[9] ;
wire sclk_d1;
wire [0:0]sclk_d1_reg;
wire sdata_reg_i_1_n_0;
LUT5 #(
.INIT(32'hAAAAAABA))
\FSM_onehot_iis_state[1]_i_1
(.I0(ldata_reg),
.I1(p_0_in2_in),
.I2(out[2]),
.I3(out[1]),
.I4(out[0]),
.O(\FSM_onehot_iis_state[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0ACA))
\FSM_onehot_iis_state[2]_i_1
(.I0(p_0_in2_in),
.I1(out[0]),
.I2(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.I3(ldata_reg),
.O(\FSM_onehot_iis_state[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\FSM_onehot_iis_state[3]_i_1
(.I0(p_0_in2_in),
.I1(ldata_reg),
.I2(out[0]),
.O(\FSM_onehot_iis_state[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFEEFFFFFEEEFFFF))
\FSM_onehot_iis_state[4]_i_1
(.I0(ldata_reg),
.I1(lrclk_d1_reg),
.I2(out[2]),
.I3(eqOp),
.I4(lrclk_d1_reg_0),
.I5(p_0_in2_in),
.O(\FSM_onehot_iis_state[4]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0010))
\FSM_onehot_iis_state[4]_i_2
(.I0(ldata_reg),
.I1(p_0_in2_in),
.I2(out[1]),
.I3(out[0]),
.O(\FSM_onehot_iis_state[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h02000000))
\FSM_onehot_iis_state[4]_i_4
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.I2(bit_cntr_reg__0[2]),
.I3(bit_cntr_reg__0[4]),
.I4(bit_cntr_reg__0[3]),
.O(eqOp));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b1))
\FSM_onehot_iis_state_reg[0]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(1'b0),
.Q(ldata_reg),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[1]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[1]_i_1_n_0 ),
.Q(out[0]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(\FSM_onehot_iis_state[2]_i_1_n_0 ),
.Q(p_0_in2_in),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[3]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[3]_i_1_n_0 ),
.Q(out[1]),
.R(1'b0));
(* FSM_ENCODED_STATES = "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000" *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_iis_state_reg[4]
(.C(S_AXI_ACLK),
.CE(\FSM_onehot_iis_state[4]_i_1_n_0 ),
.D(\FSM_onehot_iis_state[4]_i_2_n_0 ),
.Q(out[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT1 #(
.INIT(2'h1))
\bit_cntr[0]_i_1__0
(.I0(bit_cntr_reg__0[0]),
.O(plusOp__2[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\bit_cntr[1]_i_1__0
(.I0(bit_cntr_reg__0[0]),
.I1(bit_cntr_reg__0[1]),
.O(plusOp__2[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h78))
\bit_cntr[2]_i_1__0
(.I0(bit_cntr_reg__0[1]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[2]),
.O(plusOp__2[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\bit_cntr[3]_i_1__0
(.I0(bit_cntr_reg__0[2]),
.I1(bit_cntr_reg__0[0]),
.I2(bit_cntr_reg__0[1]),
.I3(bit_cntr_reg__0[3]),
.O(plusOp__2[3]));
LUT2 #(
.INIT(4'h1))
\bit_cntr[4]_i_1__0
(.I0(out[2]),
.I1(p_0_in2_in),
.O(\bit_cntr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h7FFF8000))
\bit_cntr[4]_i_3__0
(.I0(bit_cntr_reg__0[3]),
.I1(bit_cntr_reg__0[1]),
.I2(bit_cntr_reg__0[0]),
.I3(bit_cntr_reg__0[2]),
.I4(bit_cntr_reg__0[4]),
.O(plusOp__2[4]));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[0]),
.Q(bit_cntr_reg__0[0]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[1]),
.Q(bit_cntr_reg__0[1]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[2]),
.Q(bit_cntr_reg__0[2]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[3]),
.Q(bit_cntr_reg__0[3]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\bit_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(sclk_d1_reg),
.D(plusOp__2[4]),
.Q(bit_cntr_reg__0[4]),
.R(\bit_cntr[4]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'h0800))
\ldata_reg[0]_i_1
(.I0(\DataTx_L_reg[23] [0]),
.I1(out[0]),
.I2(Q[1]),
.I3(lrclk_d1),
.O(\ldata_reg[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[10]_i_1
(.I0(\ldata_reg_reg_n_0_[9] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [10]),
.O(\ldata_reg[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[11]_i_1
(.I0(\ldata_reg_reg_n_0_[10] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [11]),
.O(\ldata_reg[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[12]_i_1
(.I0(\ldata_reg_reg_n_0_[11] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [12]),
.O(\ldata_reg[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[13]_i_1
(.I0(\ldata_reg_reg_n_0_[12] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [13]),
.O(\ldata_reg[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[14]_i_1
(.I0(\ldata_reg_reg_n_0_[13] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [14]),
.O(\ldata_reg[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[15]_i_1
(.I0(\ldata_reg_reg_n_0_[14] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [15]),
.O(\ldata_reg[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[16]_i_1
(.I0(\ldata_reg_reg_n_0_[15] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [16]),
.O(\ldata_reg[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[17]_i_1
(.I0(\ldata_reg_reg_n_0_[16] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [17]),
.O(\ldata_reg[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[18]_i_1
(.I0(\ldata_reg_reg_n_0_[17] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [18]),
.O(\ldata_reg[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[19]_i_1
(.I0(\ldata_reg_reg_n_0_[18] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [19]),
.O(\ldata_reg[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[1]_i_1
(.I0(\ldata_reg_reg_n_0_[0] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [1]),
.O(\ldata_reg[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[20]_i_1
(.I0(\ldata_reg_reg_n_0_[19] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [20]),
.O(\ldata_reg[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[21]_i_1
(.I0(\ldata_reg_reg_n_0_[20] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [21]),
.O(\ldata_reg[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[22]_i_1
(.I0(\ldata_reg_reg_n_0_[21] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [22]),
.O(\ldata_reg[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'h2020FF2020202020))
\ldata_reg[23]_i_1__0
(.I0(p_0_in2_in),
.I1(Q[0]),
.I2(sclk_d1),
.I3(out[0]),
.I4(Q[1]),
.I5(lrclk_d1),
.O(\ldata_reg[23]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[23]_i_2__0
(.I0(\ldata_reg_reg_n_0_[22] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [23]),
.O(\ldata_reg[23]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[2]_i_1
(.I0(\ldata_reg_reg_n_0_[1] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [2]),
.O(\ldata_reg[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[3]_i_1
(.I0(\ldata_reg_reg_n_0_[2] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [3]),
.O(\ldata_reg[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[4]_i_1
(.I0(\ldata_reg_reg_n_0_[3] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [4]),
.O(\ldata_reg[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[5]_i_1
(.I0(\ldata_reg_reg_n_0_[4] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [5]),
.O(\ldata_reg[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[6]_i_1
(.I0(\ldata_reg_reg_n_0_[5] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [6]),
.O(\ldata_reg[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[7]_i_1
(.I0(\ldata_reg_reg_n_0_[6] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [7]),
.O(\ldata_reg[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[8]_i_1
(.I0(\ldata_reg_reg_n_0_[7] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [8]),
.O(\ldata_reg[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hAEAAA2AA))
\ldata_reg[9]_i_1
(.I0(\ldata_reg_reg_n_0_[8] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_L_reg[23] [9]),
.O(\ldata_reg[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[0]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[0] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[10]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[10] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[11]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[11] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[12]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[12] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[13]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[13] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[14]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[14] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[15]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[15] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[16]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[16] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[17]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[17] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[18]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[18] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[19]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[19] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[1]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[1] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[20]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[20] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[21]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[21] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[22]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[22] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[23]_i_2__0_n_0 ),
.Q(p_2_in),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[2]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[2] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[3]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[3] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[4]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[4] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[5]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[5] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[6]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[6] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[7]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[7] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[8]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[8] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\ldata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(\ldata_reg[23]_i_1__0_n_0 ),
.D(\ldata_reg[9]_i_1_n_0 ),
.Q(\ldata_reg_reg_n_0_[9] ),
.R(ldata_reg));
LUT4 #(
.INIT(16'h0800))
\rdata_reg[0]_i_1
(.I0(\DataTx_R_reg[23] [0]),
.I1(out[0]),
.I2(Q[1]),
.I3(lrclk_d1),
.O(p_1_in[0]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[10]_i_1
(.I0(\rdata_reg_reg_n_0_[9] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [10]),
.O(p_1_in[10]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[11]_i_1
(.I0(\rdata_reg_reg_n_0_[10] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [11]),
.O(p_1_in[11]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[12]_i_1
(.I0(\rdata_reg_reg_n_0_[11] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [12]),
.O(p_1_in[12]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[13]_i_1
(.I0(\rdata_reg_reg_n_0_[12] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [13]),
.O(p_1_in[13]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[14]_i_1
(.I0(\rdata_reg_reg_n_0_[13] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [14]),
.O(p_1_in[14]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[15]_i_1
(.I0(\rdata_reg_reg_n_0_[14] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [15]),
.O(p_1_in[15]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[16]_i_1
(.I0(\rdata_reg_reg_n_0_[15] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [16]),
.O(p_1_in[16]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[17]_i_1
(.I0(\rdata_reg_reg_n_0_[16] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [17]),
.O(p_1_in[17]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[18]_i_1
(.I0(\rdata_reg_reg_n_0_[17] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [18]),
.O(p_1_in[18]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[19]_i_1
(.I0(\rdata_reg_reg_n_0_[18] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [19]),
.O(p_1_in[19]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[1]_i_1
(.I0(\rdata_reg_reg_n_0_[0] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [1]),
.O(p_1_in[1]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[20]_i_1
(.I0(\rdata_reg_reg_n_0_[19] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [20]),
.O(p_1_in[20]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[21]_i_1
(.I0(\rdata_reg_reg_n_0_[20] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [21]),
.O(p_1_in[21]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[22]_i_1
(.I0(\rdata_reg_reg_n_0_[21] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [22]),
.O(p_1_in[22]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[23]_i_2
(.I0(\rdata_reg_reg_n_0_[22] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [23]),
.O(p_1_in[23]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[2]_i_1
(.I0(\rdata_reg_reg_n_0_[1] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [2]),
.O(p_1_in[2]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[3]_i_1
(.I0(\rdata_reg_reg_n_0_[2] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [3]),
.O(p_1_in[3]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[4]_i_1
(.I0(\rdata_reg_reg_n_0_[3] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [4]),
.O(p_1_in[4]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[5]_i_1
(.I0(\rdata_reg_reg_n_0_[4] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [5]),
.O(p_1_in[5]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[6]_i_1
(.I0(\rdata_reg_reg_n_0_[5] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [6]),
.O(p_1_in[6]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[7]_i_1
(.I0(\rdata_reg_reg_n_0_[6] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [7]),
.O(p_1_in[7]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[8]_i_1
(.I0(\rdata_reg_reg_n_0_[7] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [8]),
.O(p_1_in[8]));
LUT5 #(
.INIT(32'hAEAAA2AA))
\rdata_reg[9]_i_1
(.I0(\rdata_reg_reg_n_0_[8] ),
.I1(lrclk_d1),
.I2(Q[1]),
.I3(out[0]),
.I4(\DataTx_R_reg[23] [9]),
.O(p_1_in[9]));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[0]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[0]),
.Q(\rdata_reg_reg_n_0_[0] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[10]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[10]),
.Q(\rdata_reg_reg_n_0_[10] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[11]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[11]),
.Q(\rdata_reg_reg_n_0_[11] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[12]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[12]),
.Q(\rdata_reg_reg_n_0_[12] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[13]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[13]),
.Q(\rdata_reg_reg_n_0_[13] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[14]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[14]),
.Q(\rdata_reg_reg_n_0_[14] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[15]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[15]),
.Q(\rdata_reg_reg_n_0_[15] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[16]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[16]),
.Q(\rdata_reg_reg_n_0_[16] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[17]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[17]),
.Q(\rdata_reg_reg_n_0_[17] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[18]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[18]),
.Q(\rdata_reg_reg_n_0_[18] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[19]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[19]),
.Q(\rdata_reg_reg_n_0_[19] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[1]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[1]),
.Q(\rdata_reg_reg_n_0_[1] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[20]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[20]),
.Q(\rdata_reg_reg_n_0_[20] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[21]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[21]),
.Q(\rdata_reg_reg_n_0_[21] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[22]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[22]),
.Q(\rdata_reg_reg_n_0_[22] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[23]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[23]),
.Q(\rdata_reg_reg_n_0_[23] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[2]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[2]),
.Q(\rdata_reg_reg_n_0_[2] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[3]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[3]),
.Q(\rdata_reg_reg_n_0_[3] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[4]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[4]),
.Q(\rdata_reg_reg_n_0_[4] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[5]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[5]),
.Q(\rdata_reg_reg_n_0_[5] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[6]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[6]),
.Q(\rdata_reg_reg_n_0_[6] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[7]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[7]),
.Q(\rdata_reg_reg_n_0_[7] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[8]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[8]),
.Q(\rdata_reg_reg_n_0_[8] ),
.R(ldata_reg));
FDRE #(
.INIT(1'b0))
\rdata_reg_reg[9]
(.C(S_AXI_ACLK),
.CE(E),
.D(p_1_in[9]),
.Q(\rdata_reg_reg_n_0_[9] ),
.R(ldata_reg));
LUT6 #(
.INIT(64'hFFFFCCAF0000CCA0))
sdata_reg_i_1
(.I0(\rdata_reg_reg_n_0_[23] ),
.I1(p_2_in),
.I2(out[2]),
.I3(p_0_in2_in),
.I4(\clk_cntr_reg[4] ),
.I5(SDATA_O),
.O(sdata_reg_i_1_n_0));
FDRE #(
.INIT(1'b0))
sdata_reg_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(sdata_reg_i_1_n_0),
.Q(SDATA_O),
.R(ldata_reg));
endmodule
(* CHECK_LICENSE_TYPE = "ip_design_zed_audio_ctrl_0_0,i2s_ctrl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "i2s_ctrl,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(BCLK,
LRCLK,
SDATA_I,
SDATA_O,
S_AXI_ACLK,
S_AXI_ARESETN,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_BREADY,
S_AXI_ARADDR,
S_AXI_ARVALID,
S_AXI_RREADY,
S_AXI_ARREADY,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RVALID,
S_AXI_WREADY,
S_AXI_BRESP,
S_AXI_BVALID,
S_AXI_AWREADY);
output BCLK;
output LRCLK;
input SDATA_I;
output SDATA_O;
(* max_fanout = "10000" *) (* sigis = "Clk" *) (* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK" *)
(* x_interface_parameter = "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input S_AXI_ACLK;
(* max_fanout = "10000" *) (* sigis = "Rst" *) (* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST" *)
(* x_interface_parameter = "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW" *) input S_AXI_ARESETN;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]S_AXI_AWADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input S_AXI_AWVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]S_AXI_WDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]S_AXI_WSTRB;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input S_AXI_WVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input S_AXI_BREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]S_AXI_ARADDR;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input S_AXI_ARVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input S_AXI_RREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output S_AXI_ARREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]S_AXI_RDATA;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]S_AXI_RRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output S_AXI_RVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output S_AXI_WREADY;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]S_AXI_BRESP;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output S_AXI_BVALID;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output S_AXI_AWREADY;
wire \<const0> ;
wire BCLK;
wire LRCLK;
wire SDATA_I;
wire SDATA_O;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire S_AXI_ACLK;
wire [31:0]S_AXI_ARADDR;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [31:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire [31:0]S_AXI_WDATA;
wire S_AXI_WVALID;
assign S_AXI_BRESP[1] = \<const0> ;
assign S_AXI_BRESP[0] = \<const0> ;
assign S_AXI_RRESP[1] = \<const0> ;
assign S_AXI_RRESP[0] = \<const0> ;
assign S_AXI_WREADY = S_AXI_AWREADY;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl U0
(.SDATA_I(SDATA_I),
.SDATA_O(SDATA_O),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR[4:2]),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR[4:2]),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WVALID(S_AXI_WVALID),
.out({LRCLK,BCLK}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
(\DataTx_R_reg[0] ,
\DataTx_R_reg[0]_0 ,
\DataTx_R_reg[0]_1 ,
\DataTx_R_reg[0]_2 ,
\DataTx_R_reg[0]_3 ,
\DataTx_R_reg[0]_4 ,
S_AXI_RVALID,
S_AXI_BVALID,
data_rdy_bit_reg,
S_AXI_AWREADY,
S_AXI_ARREADY,
E,
\DataTx_L_reg[0] ,
data_rdy_bit_reg_0,
S_AXI_RDATA,
S_AXI_ACLK,
SR,
S_AXI_ARVALID,
S_AXI_ARESETN,
S_AXI_BREADY,
S_AXI_RREADY,
S_AXI_ARADDR,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_WVALID,
data_rdy_bit,
Q,
\DataTx_L_reg[31] ,
\DataRx_R_reg[23] ,
\DataRx_L_reg[23] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] );
output \DataTx_R_reg[0] ;
output \DataTx_R_reg[0]_0 ;
output \DataTx_R_reg[0]_1 ;
output \DataTx_R_reg[0]_2 ;
output \DataTx_R_reg[0]_3 ;
output \DataTx_R_reg[0]_4 ;
output S_AXI_RVALID;
output S_AXI_BVALID;
output data_rdy_bit_reg;
output S_AXI_AWREADY;
output S_AXI_ARREADY;
output [0:0]E;
output [0:0]\DataTx_L_reg[0] ;
output data_rdy_bit_reg_0;
output [31:0]S_AXI_RDATA;
input S_AXI_ACLK;
input [0:0]SR;
input S_AXI_ARVALID;
input S_AXI_ARESETN;
input S_AXI_BREADY;
input S_AXI_RREADY;
input [2:0]S_AXI_ARADDR;
input [2:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input data_rdy_bit;
input [31:0]Q;
input [31:0]\DataTx_L_reg[31] ;
input [23:0]\DataRx_R_reg[23] ;
input [23:0]\DataRx_L_reg[23] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire [23:0]\DataRx_L_reg[23] ;
wire [23:0]\DataRx_R_reg[23] ;
wire [0:0]\DataTx_L_reg[0] ;
wire [31:0]\DataTx_L_reg[31] ;
wire \DataTx_R_reg[0] ;
wire \DataTx_R_reg[0]_0 ;
wire \DataTx_R_reg[0]_1 ;
wire \DataTx_R_reg[0]_2 ;
wire \DataTx_R_reg[0]_3 ;
wire \DataTx_R_reg[0]_4 ;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ;
wire \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ;
wire [31:0]IP2Bus_Data;
wire I_DECODER_n_46;
wire I_DECODER_n_47;
wire I_DECODER_n_7;
wire I_DECODER_n_8;
wire [31:0]Q;
wire [0:0]SR;
wire S_AXI_ACLK;
wire [2:0]S_AXI_ARADDR;
wire S_AXI_ARESETN;
wire S_AXI_ARREADY;
wire S_AXI_ARVALID;
wire [2:0]S_AXI_AWADDR;
wire S_AXI_AWREADY;
wire S_AXI_AWVALID;
wire S_AXI_BREADY;
wire S_AXI_BVALID;
wire [31:0]S_AXI_RDATA;
wire S_AXI_RREADY;
wire S_AXI_RVALID;
wire S_AXI_WVALID;
wire data_rdy_bit;
wire data_rdy_bit_reg;
wire data_rdy_bit_reg_0;
wire p_2_out;
wire [3:0]plusOp;
wire rst;
wire s_axi_rdata_i;
wire [1:0]state;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
wire timeout;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(p_2_out));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.I3(timeout),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2] ),
.R(p_2_out));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp[3]),
.Q(timeout),
.R(p_2_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder I_DECODER
(.D({I_DECODER_n_7,I_DECODER_n_8}),
.\DataRx_L_reg[23] (\DataRx_L_reg[23] ),
.\DataRx_R_reg[23] (\DataRx_R_reg[23] ),
.\DataTx_L_reg[0] (\DataTx_L_reg[0] ),
.\DataTx_L_reg[31] (\DataTx_L_reg[31] ),
.\DataTx_R_reg[0] (\DataTx_R_reg[0] ),
.\DataTx_R_reg[0]_0 (\DataTx_R_reg[0]_0 ),
.\DataTx_R_reg[0]_1 (\DataTx_R_reg[0]_1 ),
.\DataTx_R_reg[0]_2 (\DataTx_R_reg[0]_2 ),
.\DataTx_R_reg[0]_3 (\DataTx_R_reg[0]_3 ),
.\DataTx_R_reg[0]_4 (\DataTx_R_reg[0]_4 ),
.\DataTx_R_reg[31] (Q),
.E(E),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3] (timeout),
.Q(state),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WVALID_0(\state[1]_i_2_n_0 ),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(data_rdy_bit_reg),
.data_rdy_bit_reg_0(data_rdy_bit_reg_0),
.s_axi_bvalid_i_reg(I_DECODER_n_47),
.s_axi_bvalid_i_reg_0(\state[0]_i_2_n_0 ),
.s_axi_bvalid_i_reg_1(S_AXI_BVALID),
.\s_axi_rdata_i_reg[31] (IP2Bus_Data),
.s_axi_rvalid_i_reg(I_DECODER_n_46),
.s_axi_rvalid_i_reg_0(S_AXI_RVALID),
.\state_reg[1] (\state[1]_i_3_n_0 ));
FDRE rst_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(SR),
.Q(rst),
.R(1'b0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_47),
.Q(S_AXI_BVALID),
.R(rst));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[0]),
.Q(S_AXI_RDATA[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[10]),
.Q(S_AXI_RDATA[10]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[11]),
.Q(S_AXI_RDATA[11]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[12]),
.Q(S_AXI_RDATA[12]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[13]),
.Q(S_AXI_RDATA[13]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[14]),
.Q(S_AXI_RDATA[14]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[15]),
.Q(S_AXI_RDATA[15]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[16]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[16]),
.Q(S_AXI_RDATA[16]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[17]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[17]),
.Q(S_AXI_RDATA[17]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[18]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[18]),
.Q(S_AXI_RDATA[18]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[19]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[19]),
.Q(S_AXI_RDATA[19]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[1]),
.Q(S_AXI_RDATA[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[20]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[20]),
.Q(S_AXI_RDATA[20]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[21]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[21]),
.Q(S_AXI_RDATA[21]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[22]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[22]),
.Q(S_AXI_RDATA[22]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[23]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[23]),
.Q(S_AXI_RDATA[23]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[24]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[24]),
.Q(S_AXI_RDATA[24]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[25]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[25]),
.Q(S_AXI_RDATA[25]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[26]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[26]),
.Q(S_AXI_RDATA[26]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[27]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[27]),
.Q(S_AXI_RDATA[27]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[28]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[28]),
.Q(S_AXI_RDATA[28]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[29]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[29]),
.Q(S_AXI_RDATA[29]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[2]),
.Q(S_AXI_RDATA[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[30]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[30]),
.Q(S_AXI_RDATA[30]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[31]),
.Q(S_AXI_RDATA[31]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[3]),
.Q(S_AXI_RDATA[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[4]),
.Q(S_AXI_RDATA[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[5]),
.Q(S_AXI_RDATA[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[6]),
.Q(S_AXI_RDATA[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[7]),
.Q(S_AXI_RDATA[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[8]),
.Q(S_AXI_RDATA[8]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(S_AXI_ACLK),
.CE(s_axi_rdata_i),
.D(IP2Bus_Data[9]),
.Q(S_AXI_RDATA[9]),
.R(rst));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_46),
.Q(S_AXI_RVALID),
.R(rst));
LUT6 #(
.INIT(64'h07770000FFFF0000))
\state[0]_i_2
(.I0(S_AXI_BVALID),
.I1(S_AXI_BREADY),
.I2(S_AXI_RREADY),
.I3(S_AXI_RVALID),
.I4(state[0]),
.I5(state[1]),
.O(\state[0]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_2
(.I0(S_AXI_AWVALID),
.I1(S_AXI_WVALID),
.O(\state[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h002A2A2A))
\state[1]_i_3
(.I0(state[1]),
.I1(S_AXI_RVALID),
.I2(S_AXI_RREADY),
.I3(S_AXI_BREADY),
.I4(S_AXI_BVALID),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_8),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(I_DECODER_n_7),
.Q(state[1]),
.R(rst));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic
(\s_axi_rdata_i_reg[24] ,
Q,
data_rdy_bit,
SDATA_O,
\s_axi_rdata_i_reg[31] ,
\s_axi_rdata_i_reg[31]_0 ,
SR,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[23]_0 ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ,
S_AXI_ACLK,
S_AXI_ARESETN,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
SDATA_I,
E,
S_AXI_WDATA,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] );
output \s_axi_rdata_i_reg[24] ;
output [1:0]Q;
output data_rdy_bit;
output SDATA_O;
output [31:0]\s_axi_rdata_i_reg[31] ;
output [31:0]\s_axi_rdata_i_reg[31]_0 ;
output [0:0]SR;
output [23:0]\s_axi_rdata_i_reg[23] ;
output [23:0]\s_axi_rdata_i_reg[23]_0 ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
input S_AXI_ACLK;
input S_AXI_ARESETN;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input SDATA_I;
input [0:0]E;
input [31:0]S_AXI_WDATA;
input [0:0]\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire Bus_RNW_reg;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire [0:0]\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire Inst_iis_deser_n_3;
wire Inst_iis_deser_n_33;
wire Inst_iis_deser_n_34;
wire Inst_iis_deser_n_35;
wire Inst_iis_deser_n_36;
wire Inst_iis_deser_n_37;
wire Inst_iis_deser_n_38;
wire Inst_iis_deser_n_39;
wire Inst_iis_deser_n_40;
wire Inst_iis_deser_n_41;
wire Inst_iis_deser_n_42;
wire Inst_iis_deser_n_43;
wire Inst_iis_deser_n_44;
wire Inst_iis_deser_n_45;
wire Inst_iis_deser_n_46;
wire Inst_iis_deser_n_47;
wire Inst_iis_deser_n_48;
wire Inst_iis_deser_n_49;
wire Inst_iis_deser_n_5;
wire Inst_iis_deser_n_50;
wire Inst_iis_deser_n_51;
wire Inst_iis_deser_n_52;
wire Inst_iis_deser_n_53;
wire Inst_iis_deser_n_54;
wire Inst_iis_deser_n_55;
wire Inst_iis_deser_n_56;
wire Inst_iis_deser_n_6;
wire Inst_iis_deser_n_7;
wire Inst_iis_deser_n_8;
wire Inst_iis_ser_n_1;
wire Inst_iis_ser_n_2;
wire [1:0]Q;
wire SDATA_I;
wire SDATA_O;
wire [0:0]SR;
wire S_AXI_ACLK;
wire S_AXI_ARESETN;
wire [31:0]S_AXI_WDATA;
wire \clk_cntr[10]_i_2_n_0 ;
wire \clk_cntr_reg_n_0_[0] ;
wire \clk_cntr_reg_n_0_[1] ;
wire \clk_cntr_reg_n_0_[2] ;
wire \clk_cntr_reg_n_0_[3] ;
wire \clk_cntr_reg_n_0_[5] ;
wire \clk_cntr_reg_n_0_[6] ;
wire \clk_cntr_reg_n_0_[7] ;
wire \clk_cntr_reg_n_0_[8] ;
wire \clk_cntr_reg_n_0_[9] ;
wire data_rdy;
wire data_rdy_bit;
wire [23:0]ldata_reg;
wire lrclk_d1;
wire p_0_in4_in;
wire [10:0]plusOp__0;
wire [23:0]\s_axi_rdata_i_reg[23] ;
wire [23:0]\s_axi_rdata_i_reg[23]_0 ;
wire \s_axi_rdata_i_reg[24] ;
wire [31:0]\s_axi_rdata_i_reg[31] ;
wire [31:0]\s_axi_rdata_i_reg[31]_0 ;
wire sclk_d1;
wire write_bit;
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[0]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[0]),
.Q(\s_axi_rdata_i_reg[23] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[10]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[10]),
.Q(\s_axi_rdata_i_reg[23] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[11]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[11]),
.Q(\s_axi_rdata_i_reg[23] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[12]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[12]),
.Q(\s_axi_rdata_i_reg[23] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[13]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[13]),
.Q(\s_axi_rdata_i_reg[23] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[14]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[14]),
.Q(\s_axi_rdata_i_reg[23] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[15]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[15]),
.Q(\s_axi_rdata_i_reg[23] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[16]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[16]),
.Q(\s_axi_rdata_i_reg[23] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[17]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[17]),
.Q(\s_axi_rdata_i_reg[23] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[18]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[18]),
.Q(\s_axi_rdata_i_reg[23] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[19]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[19]),
.Q(\s_axi_rdata_i_reg[23] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[1]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[1]),
.Q(\s_axi_rdata_i_reg[23] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[20]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[20]),
.Q(\s_axi_rdata_i_reg[23] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[21]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[21]),
.Q(\s_axi_rdata_i_reg[23] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[22]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[22]),
.Q(\s_axi_rdata_i_reg[23] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[23]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[23]),
.Q(\s_axi_rdata_i_reg[23] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[2]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[2]),
.Q(\s_axi_rdata_i_reg[23] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[3]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[3]),
.Q(\s_axi_rdata_i_reg[23] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[4]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[4]),
.Q(\s_axi_rdata_i_reg[23] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[5]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[5]),
.Q(\s_axi_rdata_i_reg[23] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[6]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[6]),
.Q(\s_axi_rdata_i_reg[23] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[7]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[7]),
.Q(\s_axi_rdata_i_reg[23] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[8]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[8]),
.Q(\s_axi_rdata_i_reg[23] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_L_reg[9]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(ldata_reg[9]),
.Q(\s_axi_rdata_i_reg[23] [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[0]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_56),
.Q(\s_axi_rdata_i_reg[23]_0 [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[10]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_46),
.Q(\s_axi_rdata_i_reg[23]_0 [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[11]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_45),
.Q(\s_axi_rdata_i_reg[23]_0 [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[12]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_44),
.Q(\s_axi_rdata_i_reg[23]_0 [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[13]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_43),
.Q(\s_axi_rdata_i_reg[23]_0 [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[14]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_42),
.Q(\s_axi_rdata_i_reg[23]_0 [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[15]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_41),
.Q(\s_axi_rdata_i_reg[23]_0 [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[16]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_40),
.Q(\s_axi_rdata_i_reg[23]_0 [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[17]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_39),
.Q(\s_axi_rdata_i_reg[23]_0 [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[18]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_38),
.Q(\s_axi_rdata_i_reg[23]_0 [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[19]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_37),
.Q(\s_axi_rdata_i_reg[23]_0 [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[1]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_55),
.Q(\s_axi_rdata_i_reg[23]_0 [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[20]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_36),
.Q(\s_axi_rdata_i_reg[23]_0 [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[21]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_35),
.Q(\s_axi_rdata_i_reg[23]_0 [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[22]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_34),
.Q(\s_axi_rdata_i_reg[23]_0 [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[23]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_33),
.Q(\s_axi_rdata_i_reg[23]_0 [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[2]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_54),
.Q(\s_axi_rdata_i_reg[23]_0 [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[3]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_53),
.Q(\s_axi_rdata_i_reg[23]_0 [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[4]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_52),
.Q(\s_axi_rdata_i_reg[23]_0 [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[5]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_51),
.Q(\s_axi_rdata_i_reg[23]_0 [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[6]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_50),
.Q(\s_axi_rdata_i_reg[23]_0 [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[7]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_49),
.Q(\s_axi_rdata_i_reg[23]_0 [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[8]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_48),
.Q(\s_axi_rdata_i_reg[23]_0 [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataRx_R_reg[9]
(.C(S_AXI_ACLK),
.CE(data_rdy),
.D(Inst_iis_deser_n_47),
.Q(\s_axi_rdata_i_reg[23]_0 [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[0]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[0]),
.Q(\s_axi_rdata_i_reg[31] [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[10]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[10]),
.Q(\s_axi_rdata_i_reg[31] [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[11]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[11]),
.Q(\s_axi_rdata_i_reg[31] [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[12]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[12]),
.Q(\s_axi_rdata_i_reg[31] [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[13]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[13]),
.Q(\s_axi_rdata_i_reg[31] [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[14]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[14]),
.Q(\s_axi_rdata_i_reg[31] [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[15]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[15]),
.Q(\s_axi_rdata_i_reg[31] [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[16]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[16]),
.Q(\s_axi_rdata_i_reg[31] [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[17]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[17]),
.Q(\s_axi_rdata_i_reg[31] [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[18]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[18]),
.Q(\s_axi_rdata_i_reg[31] [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[19]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[19]),
.Q(\s_axi_rdata_i_reg[31] [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[1]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[1]),
.Q(\s_axi_rdata_i_reg[31] [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[20]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[20]),
.Q(\s_axi_rdata_i_reg[31] [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[21]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[21]),
.Q(\s_axi_rdata_i_reg[31] [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[22]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[22]),
.Q(\s_axi_rdata_i_reg[31] [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[23]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[23]),
.Q(\s_axi_rdata_i_reg[31] [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[24]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[24]),
.Q(\s_axi_rdata_i_reg[31] [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[25]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[25]),
.Q(\s_axi_rdata_i_reg[31] [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[26]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[26]),
.Q(\s_axi_rdata_i_reg[31] [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[27]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[27]),
.Q(\s_axi_rdata_i_reg[31] [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[28]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[28]),
.Q(\s_axi_rdata_i_reg[31] [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[29]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[29]),
.Q(\s_axi_rdata_i_reg[31] [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[2]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[2]),
.Q(\s_axi_rdata_i_reg[31] [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[30]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[30]),
.Q(\s_axi_rdata_i_reg[31] [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[31]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[31]),
.Q(\s_axi_rdata_i_reg[31] [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[3]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[3]),
.Q(\s_axi_rdata_i_reg[31] [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[4]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[4]),
.Q(\s_axi_rdata_i_reg[31] [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[5]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[5]),
.Q(\s_axi_rdata_i_reg[31] [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[6]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[6]),
.Q(\s_axi_rdata_i_reg[31] [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[7]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[7]),
.Q(\s_axi_rdata_i_reg[31] [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[8]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[8]),
.Q(\s_axi_rdata_i_reg[31] [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_L_reg[9]
(.C(S_AXI_ACLK),
.CE(E),
.D(S_AXI_WDATA[9]),
.Q(\s_axi_rdata_i_reg[31] [9]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[0]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[0]),
.Q(\s_axi_rdata_i_reg[31]_0 [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[10]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[10]),
.Q(\s_axi_rdata_i_reg[31]_0 [10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[11]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[11]),
.Q(\s_axi_rdata_i_reg[31]_0 [11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[12]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[12]),
.Q(\s_axi_rdata_i_reg[31]_0 [12]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[13]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[13]),
.Q(\s_axi_rdata_i_reg[31]_0 [13]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[14]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[14]),
.Q(\s_axi_rdata_i_reg[31]_0 [14]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[15]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[15]),
.Q(\s_axi_rdata_i_reg[31]_0 [15]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[16]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[16]),
.Q(\s_axi_rdata_i_reg[31]_0 [16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[17]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[17]),
.Q(\s_axi_rdata_i_reg[31]_0 [17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[18]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[18]),
.Q(\s_axi_rdata_i_reg[31]_0 [18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[19]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[19]),
.Q(\s_axi_rdata_i_reg[31]_0 [19]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[1]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[1]),
.Q(\s_axi_rdata_i_reg[31]_0 [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[20]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[20]),
.Q(\s_axi_rdata_i_reg[31]_0 [20]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[21]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[21]),
.Q(\s_axi_rdata_i_reg[31]_0 [21]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[22]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[22]),
.Q(\s_axi_rdata_i_reg[31]_0 [22]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[23]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[23]),
.Q(\s_axi_rdata_i_reg[31]_0 [23]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[24]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[24]),
.Q(\s_axi_rdata_i_reg[31]_0 [24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[25]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[25]),
.Q(\s_axi_rdata_i_reg[31]_0 [25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[26]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[26]),
.Q(\s_axi_rdata_i_reg[31]_0 [26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[27]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[27]),
.Q(\s_axi_rdata_i_reg[31]_0 [27]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[28]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[28]),
.Q(\s_axi_rdata_i_reg[31]_0 [28]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[29]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[29]),
.Q(\s_axi_rdata_i_reg[31]_0 [29]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[2]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[2]),
.Q(\s_axi_rdata_i_reg[31]_0 [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[30]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[30]),
.Q(\s_axi_rdata_i_reg[31]_0 [30]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[31]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[31]),
.Q(\s_axi_rdata_i_reg[31]_0 [31]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[3]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[3]),
.Q(\s_axi_rdata_i_reg[31]_0 [3]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[4]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[4]),
.Q(\s_axi_rdata_i_reg[31]_0 [4]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[5]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[5]),
.Q(\s_axi_rdata_i_reg[31]_0 [5]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[6]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[6]),
.Q(\s_axi_rdata_i_reg[31]_0 [6]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[7]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[7]),
.Q(\s_axi_rdata_i_reg[31]_0 [7]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[8]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[8]),
.Q(\s_axi_rdata_i_reg[31]_0 [8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\DataTx_R_reg[9]
(.C(S_AXI_ACLK),
.CE(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.D(S_AXI_WDATA[9]),
.Q(\s_axi_rdata_i_reg[31]_0 [9]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser Inst_iis_deser
(.\DataRx_L_reg[23] (ldata_reg),
.\DataRx_R_reg[23] ({Inst_iis_deser_n_33,Inst_iis_deser_n_34,Inst_iis_deser_n_35,Inst_iis_deser_n_36,Inst_iis_deser_n_37,Inst_iis_deser_n_38,Inst_iis_deser_n_39,Inst_iis_deser_n_40,Inst_iis_deser_n_41,Inst_iis_deser_n_42,Inst_iis_deser_n_43,Inst_iis_deser_n_44,Inst_iis_deser_n_45,Inst_iis_deser_n_46,Inst_iis_deser_n_47,Inst_iis_deser_n_48,Inst_iis_deser_n_49,Inst_iis_deser_n_50,Inst_iis_deser_n_51,Inst_iis_deser_n_52,Inst_iis_deser_n_53,Inst_iis_deser_n_54,Inst_iis_deser_n_55,Inst_iis_deser_n_56}),
.E(data_rdy),
.\FSM_onehot_iis_state_reg[0] (Inst_iis_deser_n_6),
.\FSM_onehot_iis_state_reg[0]_0 (Inst_iis_deser_n_8),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.Q(Q),
.SDATA_I(SDATA_I),
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.\bit_cntr_reg[4]_0 (write_bit),
.data_rdy_bit(data_rdy_bit),
.data_rdy_bit_reg(Inst_iis_deser_n_7),
.lrclk_d1(lrclk_d1),
.out({Inst_iis_ser_n_1,Inst_iis_ser_n_2,p_0_in4_in}),
.\rdata_reg_reg[23]_0 (Inst_iis_deser_n_3),
.sclk_d1(sclk_d1),
.sdata_reg_reg(Inst_iis_deser_n_5));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser Inst_iis_ser
(.\DataTx_L_reg[23] (\s_axi_rdata_i_reg[31] [23:0]),
.\DataTx_R_reg[23] (\s_axi_rdata_i_reg[31]_0 [23:0]),
.E(Inst_iis_deser_n_3),
.Q(Q),
.SDATA_O(SDATA_O),
.S_AXI_ACLK(S_AXI_ACLK),
.\clk_cntr_reg[4] (Inst_iis_deser_n_5),
.lrclk_d1(lrclk_d1),
.lrclk_d1_reg(Inst_iis_deser_n_8),
.lrclk_d1_reg_0(Inst_iis_deser_n_6),
.out({Inst_iis_ser_n_1,Inst_iis_ser_n_2,p_0_in4_in}),
.sclk_d1(sclk_d1),
.sclk_d1_reg(write_bit));
LUT1 #(
.INIT(2'h1))
\clk_cntr[0]_i_1
(.I0(\clk_cntr_reg_n_0_[0] ),
.O(plusOp__0[0]));
LUT6 #(
.INIT(64'hF7FFFFFF08000000))
\clk_cntr[10]_i_1
(.I0(\clk_cntr_reg_n_0_[9] ),
.I1(\clk_cntr_reg_n_0_[7] ),
.I2(\clk_cntr[10]_i_2_n_0 ),
.I3(\clk_cntr_reg_n_0_[6] ),
.I4(\clk_cntr_reg_n_0_[8] ),
.I5(Q[1]),
.O(plusOp__0[10]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\clk_cntr[10]_i_2
(.I0(Q[0]),
.I1(\clk_cntr_reg_n_0_[2] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[1] ),
.I4(\clk_cntr_reg_n_0_[3] ),
.I5(\clk_cntr_reg_n_0_[5] ),
.O(\clk_cntr[10]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\clk_cntr[1]_i_1
(.I0(\clk_cntr_reg_n_0_[0] ),
.I1(\clk_cntr_reg_n_0_[1] ),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h78))
\clk_cntr[2]_i_1
(.I0(\clk_cntr_reg_n_0_[1] ),
.I1(\clk_cntr_reg_n_0_[0] ),
.I2(\clk_cntr_reg_n_0_[2] ),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h7F80))
\clk_cntr[3]_i_1
(.I0(\clk_cntr_reg_n_0_[2] ),
.I1(\clk_cntr_reg_n_0_[0] ),
.I2(\clk_cntr_reg_n_0_[1] ),
.I3(\clk_cntr_reg_n_0_[3] ),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h7FFF8000))
\clk_cntr[4]_i_1
(.I0(\clk_cntr_reg_n_0_[3] ),
.I1(\clk_cntr_reg_n_0_[1] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[2] ),
.I4(Q[0]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\clk_cntr[5]_i_1
(.I0(Q[0]),
.I1(\clk_cntr_reg_n_0_[2] ),
.I2(\clk_cntr_reg_n_0_[0] ),
.I3(\clk_cntr_reg_n_0_[1] ),
.I4(\clk_cntr_reg_n_0_[3] ),
.I5(\clk_cntr_reg_n_0_[5] ),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\clk_cntr[6]_i_1
(.I0(\clk_cntr[10]_i_2_n_0 ),
.I1(\clk_cntr_reg_n_0_[6] ),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hD2))
\clk_cntr[7]_i_1
(.I0(\clk_cntr_reg_n_0_[6] ),
.I1(\clk_cntr[10]_i_2_n_0 ),
.I2(\clk_cntr_reg_n_0_[7] ),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hDF20))
\clk_cntr[8]_i_1
(.I0(\clk_cntr_reg_n_0_[7] ),
.I1(\clk_cntr[10]_i_2_n_0 ),
.I2(\clk_cntr_reg_n_0_[6] ),
.I3(\clk_cntr_reg_n_0_[8] ),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hF7FF0800))
\clk_cntr[9]_i_1
(.I0(\clk_cntr_reg_n_0_[8] ),
.I1(\clk_cntr_reg_n_0_[6] ),
.I2(\clk_cntr[10]_i_2_n_0 ),
.I3(\clk_cntr_reg_n_0_[7] ),
.I4(\clk_cntr_reg_n_0_[9] ),
.O(plusOp__0[9]));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[0]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[0]),
.Q(\clk_cntr_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[10]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[10]),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[1]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[1]),
.Q(\clk_cntr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[2]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[2]),
.Q(\clk_cntr_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[3]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[3]),
.Q(\clk_cntr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[4]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[4]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[5]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[5]),
.Q(\clk_cntr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[6]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[6]),
.Q(\clk_cntr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[7]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[7]),
.Q(\clk_cntr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[8]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[8]),
.Q(\clk_cntr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\clk_cntr_reg[9]
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(plusOp__0[9]),
.Q(\clk_cntr_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
data_rdy_bit_reg
(.C(S_AXI_ACLK),
.CE(1'b1),
.D(Inst_iis_deser_n_7),
.Q(data_rdy_bit),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
rst_i_1
(.I0(S_AXI_ARESETN),
.O(SR));
LUT6 #(
.INIT(64'h0000000400040448))
slv_ip2bus_data
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(Bus_RNW_reg),
.I2(\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I4(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.I5(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(\s_axi_rdata_i_reg[24] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module uart_log_module (
// inputs:
clk,
data,
strobe,
valid
)
;
input clk;
input [ 7: 0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen ("uart_log_module.txt");
always @(posedge clk) begin
if (valid && strobe) begin
// Send \n (linefeed) instead of \r (^M, Carriage Return)...
$fwrite (text_handle, "%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush (text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module uart_tx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
do_force_break,
reset_n,
status_wr_strobe,
tx_data,
tx_wr_strobe,
// outputs:
tx_overrun,
tx_ready,
tx_shift_empty,
txd
)
;
output tx_overrun;
output tx_ready;
output tx_shift_empty;
output txd;
input [ 8: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input do_force_break;
input reset_n;
input status_wr_strobe;
input [ 7: 0] tx_data;
input tx_wr_strobe;
reg baud_clk_en;
reg [ 8: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg do_load_shifter;
wire do_shift;
reg pre_txd;
wire shift_done;
wire [ 9: 0] tx_load_val;
reg tx_overrun;
reg tx_ready;
reg tx_shift_empty;
wire tx_shift_reg_out;
wire [ 9: 0] tx_shift_register_contents;
wire tx_wr_strobe_onset;
reg txd;
wire [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in;
reg [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_wr_strobe_onset = tx_wr_strobe && begintransfer;
assign tx_load_val = {{1 {1'b1}},
tx_data,
1'b0};
assign shift_done = ~(|tx_shift_register_contents);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_load_shifter <= 0;
else if (clk_en)
do_load_shifter <= (~tx_ready) && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_ready <= 1'b1;
else if (clk_en)
if (tx_wr_strobe_onset)
tx_ready <= 0;
else if (do_load_shifter)
tx_ready <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
tx_overrun <= 0;
else if (~tx_ready && tx_wr_strobe_onset)
tx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_shift_empty <= 1'b1;
else if (clk_en)
tx_shift_empty <= tx_ready && shift_done;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || do_load_shifter)
baud_rate_counter <= baud_divisor;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
baud_clk_en <= baud_rate_counter_is_zero;
end
assign do_shift = baud_clk_en &&
(~shift_done) &&
(~do_load_shifter);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pre_txd <= 1;
else if (~shift_done)
pre_txd <= tx_shift_reg_out;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
txd <= 1;
else if (clk_en)
txd <= pre_txd & ~do_force_break;
end
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= 0;
else if (clk_en)
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in;
end
assign unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in = (do_load_shifter)? tx_load_val :
(do_shift)? {1'b0,
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9 : 1]} :
unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_shift_register_contents = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out;
assign tx_shift_reg_out = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module uart_rx_stimulus_source_character_source_rom_module (
// inputs:
clk,
incr_addr,
reset_n,
// outputs:
new_rom,
q,
safe
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 7: 0] q;
output safe;
input clk;
input incr_addr;
input reset_n;
reg [ 10: 0] address;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [1023: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
reg pre;
wire [ 7: 0] q;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign q = mem_array[address];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_pre <= 0;
d2_pre <= 0;
d3_pre <= 0;
d4_pre <= 0;
d5_pre <= 0;
d6_pre <= 0;
d7_pre <= 0;
d8_pre <= 0;
d9_pre <= 0;
new_rom <= 0;
end
else
begin
d1_pre <= pre;
d2_pre <= d1_pre;
d3_pre <= d2_pre;
d4_pre <= d3_pre;
d5_pre <= d4_pre;
d6_pre <= d5_pre;
d7_pre <= d6_pre;
d8_pre <= d7_pre;
d9_pre <= d8_pre;
new_rom <= d9_pre;
end
end
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b0 ; // '
assign safe = (address < mutex[1]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin // dont worry about null _stream.dat file
address <= 0;
mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
if (incr_addr && safe) address <= address + 1;
if (mutex[0] && !safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
mutex_handle = $fopen ("uart_input_data_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared!");
end else begin
// sleep until next reset, do not bash mutex.
wait (!reset_n);
end
end // OK to bash mutex.
if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
if (mutex_handle) begin
$readmemh ("uart_input_data_mutex.dat", mutex);
end
if (mutex[0] && !safe) begin
// read stream into mem_array after current characters are gone!
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemh("uart_input_data_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module uart_rx_stimulus_source (
// inputs:
baud_divisor,
clk,
clk_en,
reset_n,
rx_char_ready,
rxd,
// outputs:
source_rxd
)
;
output source_rxd;
input [ 8: 0] baud_divisor;
input clk;
input clk_en;
input reset_n;
input rx_char_ready;
input rxd;
reg [ 7: 0] d1_stim_data;
reg delayed_unxrx_char_readyxx0;
wire do_send_stim_data;
wire new_rom_pulse;
wire pickup_pulse;
wire safe;
wire source_rxd;
wire [ 7: 0] stim_data;
wire unused_empty;
wire unused_overrun;
wire unused_ready;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//stimulus_transmitter, which is an e_instance
uart_tx stimulus_transmitter
(
.baud_divisor (baud_divisor),
.begintransfer (do_send_stim_data),
.clk (clk),
.clk_en (clk_en),
.do_force_break (1'b0),
.reset_n (reset_n),
.status_wr_strobe (1'b0),
.tx_data (d1_stim_data),
.tx_overrun (unused_overrun),
.tx_ready (unused_ready),
.tx_shift_empty (unused_empty),
.tx_wr_strobe (1'b1),
.txd (source_rxd)
);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_stim_data <= 0;
else if (do_send_stim_data)
d1_stim_data <= stim_data;
end
//uart_rx_stimulus_source_character_source_rom, which is an e_drom
uart_rx_stimulus_source_character_source_rom_module uart_rx_stimulus_source_character_source_rom
(
.clk (clk),
.incr_addr (do_send_stim_data),
.new_rom (new_rom_pulse),
.q (stim_data),
.reset_n (reset_n),
.safe (safe)
);
//delayed_unxrx_char_readyxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_char_readyxx0 <= 0;
else if (clk_en)
delayed_unxrx_char_readyxx0 <= rx_char_ready;
end
assign pickup_pulse = ~(rx_char_ready) & (delayed_unxrx_char_readyxx0);
assign do_send_stim_data = (pickup_pulse || new_rom_pulse) && safe;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign source_rxd = rxd;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module uart_rx (
// inputs:
baud_divisor,
begintransfer,
clk,
clk_en,
reset_n,
rx_rd_strobe,
rxd,
status_wr_strobe,
// outputs:
break_detect,
framing_error,
parity_error,
rx_char_ready,
rx_data,
rx_overrun
)
;
output break_detect;
output framing_error;
output parity_error;
output rx_char_ready;
output [ 7: 0] rx_data;
output rx_overrun;
input [ 8: 0] baud_divisor;
input begintransfer;
input clk;
input clk_en;
input reset_n;
input rx_rd_strobe;
input rxd;
input status_wr_strobe;
reg baud_clk_en;
wire [ 8: 0] baud_load_value;
reg [ 8: 0] baud_rate_counter;
wire baud_rate_counter_is_zero;
reg break_detect;
reg delayed_unxrx_in_processxx3;
reg delayed_unxsync_rxdxx1;
reg delayed_unxsync_rxdxx2;
reg do_start_rx;
reg framing_error;
wire got_new_char;
wire [ 7: 0] half_bit_cell_divisor;
wire is_break;
wire is_framing_error;
wire parity_error;
wire [ 7: 0] raw_data_in;
reg rx_char_ready;
reg [ 7: 0] rx_data;
wire rx_in_process;
reg rx_overrun;
wire rx_rd_strobe_onset;
wire rxd_edge;
wire rxd_falling;
wire [ 9: 0] rxd_shift_reg;
wire sample_enable;
wire shift_reg_start_bit_n;
wire source_rxd;
wire stop_bit;
wire sync_rxd;
wire unused_start_bit;
wire [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;
reg [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
uart_rx_stimulus_source the_uart_rx_stimulus_source
(
.baud_divisor (baud_divisor),
.clk (clk),
.clk_en (clk_en),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rxd (rxd),
.source_rxd (source_rxd)
);
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (source_rxd),
.dout (sync_rxd),
.reset_n (reset_n)
);
defparam the_altera_std_synchronizer.depth = 2;
//delayed_unxsync_rxdxx1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx1 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx1 <= sync_rxd;
end
assign rxd_falling = ~(sync_rxd) & (delayed_unxsync_rxdxx1);
//delayed_unxsync_rxdxx2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxsync_rxdxx2 <= 0;
else if (clk_en)
delayed_unxsync_rxdxx2 <= sync_rxd;
end
assign rxd_edge = (sync_rxd) ^ (delayed_unxsync_rxdxx2);
assign rx_rd_strobe_onset = rx_rd_strobe && begintransfer;
assign half_bit_cell_divisor = baud_divisor[8 : 1];
assign baud_load_value = (rxd_edge)? half_bit_cell_divisor :
baud_divisor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_rate_counter <= 0;
else if (clk_en)
if (baud_rate_counter_is_zero || rxd_edge)
baud_rate_counter <= baud_load_value;
else
baud_rate_counter <= baud_rate_counter - 1;
end
assign baud_rate_counter_is_zero = baud_rate_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
baud_clk_en <= 0;
else if (clk_en)
if (rxd_edge)
baud_clk_en <= 0;
else
baud_clk_en <= baud_rate_counter_is_zero;
end
assign sample_enable = baud_clk_en && rx_in_process;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_start_rx <= 0;
else if (clk_en)
if (~rx_in_process && rxd_falling)
do_start_rx <= 1;
else
do_start_rx <= 0;
end
assign rx_in_process = shift_reg_start_bit_n;
assign {stop_bit,
raw_data_in,
unused_start_bit} = rxd_shift_reg;
assign is_break = ~(|rxd_shift_reg);
assign is_framing_error = ~stop_bit && ~is_break;
//delayed_unxrx_in_processxx3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxrx_in_processxx3 <= 0;
else if (clk_en)
delayed_unxrx_in_processxx3 <= rx_in_process;
end
assign got_new_char = ~(rx_in_process) & (delayed_unxrx_in_processxx3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_data <= 0;
else if (got_new_char)
rx_data <= raw_data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
framing_error <= 0;
else if (clk_en)
if (status_wr_strobe)
framing_error <= 0;
else if (got_new_char && is_framing_error)
framing_error <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
break_detect <= 0;
else if (clk_en)
if (status_wr_strobe)
break_detect <= 0;
else if (got_new_char && is_break)
break_detect <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_overrun <= 0;
else if (clk_en)
if (status_wr_strobe)
rx_overrun <= 0;
else if (got_new_char && rx_char_ready)
rx_overrun <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rx_char_ready <= 0;
else if (clk_en)
if (rx_rd_strobe_onset)
rx_char_ready <= 0;
else if (got_new_char)
rx_char_ready <= -1;
end
assign parity_error = 0;
//_reg, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= 0;
else if (clk_en)
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in;
end
assign unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in = (do_start_rx)? {10{1'b1}} :
(sample_enable)? {sync_rxd,
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9 : 1]} :
unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
assign rxd_shift_reg = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out;
assign shift_reg_start_bit_n = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module uart_regs (
// inputs:
address,
break_detect,
chipselect,
clk,
clk_en,
framing_error,
parity_error,
read_n,
reset_n,
rx_char_ready,
rx_data,
rx_overrun,
tx_overrun,
tx_ready,
tx_shift_empty,
write_n,
writedata,
// outputs:
baud_divisor,
dataavailable,
do_force_break,
irq,
readdata,
readyfordata,
rx_rd_strobe,
status_wr_strobe,
tx_data,
tx_wr_strobe
)
;
output [ 8: 0] baud_divisor;
output dataavailable;
output do_force_break;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output rx_rd_strobe;
output status_wr_strobe;
output [ 7: 0] tx_data;
output tx_wr_strobe;
input [ 2: 0] address;
input break_detect;
input chipselect;
input clk;
input clk_en;
input framing_error;
input parity_error;
input read_n;
input reset_n;
input rx_char_ready;
input [ 7: 0] rx_data;
input rx_overrun;
input tx_overrun;
input tx_ready;
input tx_shift_empty;
input write_n;
input [ 15: 0] writedata;
wire any_error;
wire [ 8: 0] baud_divisor;
reg [ 9: 0] control_reg;
wire control_wr_strobe;
wire cts_status_bit;
reg d1_rx_char_ready;
reg d1_tx_ready;
wire dataavailable;
wire dcts_status_bit;
reg delayed_unxtx_readyxx4;
wire [ 8: 0] divisor_constant;
wire do_force_break;
wire do_write_char;
wire eop_status_bit;
wire ie_any_error;
wire ie_break_detect;
wire ie_framing_error;
wire ie_parity_error;
wire ie_rx_char_ready;
wire ie_rx_overrun;
wire ie_tx_overrun;
wire ie_tx_ready;
wire ie_tx_shift_empty;
reg irq;
wire qualified_irq;
reg [ 15: 0] readdata;
wire readyfordata;
wire rx_rd_strobe;
wire [ 15: 0] selected_read_data;
wire [ 12: 0] status_reg;
wire status_wr_strobe;
reg [ 7: 0] tx_data;
wire tx_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= selected_read_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq <= 0;
else if (clk_en)
irq <= qualified_irq;
end
assign rx_rd_strobe = chipselect && ~read_n && (address == 3'd0);
assign tx_wr_strobe = chipselect && ~write_n && (address == 3'd1);
assign status_wr_strobe = chipselect && ~write_n && (address == 3'd2);
assign control_wr_strobe = chipselect && ~write_n && (address == 3'd3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_data <= 0;
else if (tx_wr_strobe)
tx_data <= writedata[7 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg <= 0;
else if (control_wr_strobe)
control_reg <= writedata[9 : 0];
end
assign baud_divisor = divisor_constant;
assign cts_status_bit = 0;
assign dcts_status_bit = 0;
assign {do_force_break,
ie_any_error,
ie_rx_char_ready,
ie_tx_ready,
ie_tx_shift_empty,
ie_tx_overrun,
ie_rx_overrun,
ie_break_detect,
ie_framing_error,
ie_parity_error} = control_reg;
assign any_error = tx_overrun ||
rx_overrun ||
parity_error ||
framing_error ||
break_detect;
assign status_reg = {eop_status_bit,
cts_status_bit,
dcts_status_bit,
1'b0,
any_error,
rx_char_ready,
tx_ready,
tx_shift_empty,
tx_overrun,
rx_overrun,
break_detect,
framing_error,
parity_error};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_rx_char_ready <= 0;
else if (clk_en)
d1_rx_char_ready <= rx_char_ready;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_tx_ready <= 0;
else if (clk_en)
d1_tx_ready <= tx_ready;
end
assign dataavailable = d1_rx_char_ready;
assign readyfordata = d1_tx_ready;
assign eop_status_bit = 1'b0;
assign selected_read_data = ({16 {(address == 3'd0)}} & rx_data) |
({16 {(address == 3'd1)}} & tx_data) |
({16 {(address == 3'd2)}} & status_reg) |
({16 {(address == 3'd3)}} & control_reg);
assign qualified_irq = (ie_any_error && any_error ) ||
(ie_tx_shift_empty && tx_shift_empty ) ||
(ie_tx_overrun && tx_overrun ) ||
(ie_rx_overrun && rx_overrun ) ||
(ie_break_detect && break_detect ) ||
(ie_framing_error && framing_error ) ||
(ie_parity_error && parity_error ) ||
(ie_rx_char_ready && rx_char_ready ) ||
(ie_tx_ready && tx_ready );
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//delayed_unxtx_readyxx4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxtx_readyxx4 <= 0;
else if (clk_en)
delayed_unxtx_readyxx4 <= tx_ready;
end
assign do_write_char = (tx_ready) & ~(delayed_unxtx_readyxx4);
always @(posedge clk)
begin
if (do_write_char)
$write("%c", tx_data);
end
assign divisor_constant = 4;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign divisor_constant = 434;
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module uart (
// inputs:
address,
begintransfer,
chipselect,
clk,
read_n,
reset_n,
rxd,
write_n,
writedata,
// outputs:
dataavailable,
irq,
readdata,
readyfordata,
txd
)
/* synthesis altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" */ ;
output dataavailable;
output irq;
output [ 15: 0] readdata;
output readyfordata;
output txd;
input [ 2: 0] address;
input begintransfer;
input chipselect;
input clk;
input read_n;
input reset_n;
input rxd;
input write_n;
input [ 15: 0] writedata;
wire [ 8: 0] baud_divisor;
wire break_detect;
wire clk_en;
wire dataavailable;
wire do_force_break;
wire framing_error;
wire irq;
wire parity_error;
wire [ 15: 0] readdata;
wire readyfordata;
wire rx_char_ready;
wire [ 7: 0] rx_data;
wire rx_overrun;
wire rx_rd_strobe;
wire status_wr_strobe;
wire [ 7: 0] tx_data;
wire tx_overrun;
wire tx_ready;
wire tx_shift_empty;
wire tx_wr_strobe;
wire txd;
assign clk_en = 1;
uart_tx the_uart_tx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.clk (clk),
.clk_en (clk_en),
.do_force_break (do_force_break),
.reset_n (reset_n),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.txd (txd)
);
uart_rx the_uart_rx
(
.baud_divisor (baud_divisor),
.begintransfer (begintransfer),
.break_detect (break_detect),
.clk (clk),
.clk_en (clk_en),
.framing_error (framing_error),
.parity_error (parity_error),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.rxd (rxd),
.status_wr_strobe (status_wr_strobe)
);
uart_regs the_uart_regs
(
.address (address),
.baud_divisor (baud_divisor),
.break_detect (break_detect),
.chipselect (chipselect),
.clk (clk),
.clk_en (clk_en),
.dataavailable (dataavailable),
.do_force_break (do_force_break),
.framing_error (framing_error),
.irq (irq),
.parity_error (parity_error),
.read_n (read_n),
.readdata (readdata),
.readyfordata (readyfordata),
.reset_n (reset_n),
.rx_char_ready (rx_char_ready),
.rx_data (rx_data),
.rx_overrun (rx_overrun),
.rx_rd_strobe (rx_rd_strobe),
.status_wr_strobe (status_wr_strobe),
.tx_data (tx_data),
.tx_overrun (tx_overrun),
.tx_ready (tx_ready),
.tx_shift_empty (tx_shift_empty),
.tx_wr_strobe (tx_wr_strobe),
.write_n (write_n),
.writedata (writedata)
);
//s1, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//uart_log, which is an e_log
uart_log_module uart_log
(
.clk (clk),
.data (tx_data),
.strobe (tx_wr_strobe),
.valid (~tx_ready)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O41A_PP_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o41a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_PP_SYMBOL_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Thu Jul 18 09:15:11 2019
//Host : graviton running 64-bit Devuan GNU/Linux ascii
//Command : generate_target cpu_wrapper.bd
//Design : cpu_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module cpu_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
EPC_INTF_addr,
EPC_INTF_ads,
EPC_INTF_be,
EPC_INTF_burst,
EPC_INTF_clk,
EPC_INTF_cs_n,
EPC_INTF_rd_n,
EPC_INTF_rdy,
EPC_INTF_rnw,
EPC_INTF_rst,
EPC_INTF_wr_n,
FCLK_CLK0,
FCLK_RESET0_N,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
Int0,
Int1,
Int2,
Int3,
OCXO_CLK100,
OCXO_RESETN,
UART_0_rxd,
UART_0_txd,
Vp_Vn_v_n,
Vp_Vn_v_p,
epc_intf_data_io,
gpio_tri_io,
iic_0_scl_io,
iic_0_sda_io,
iic_1_scl_io,
iic_1_sda_io,
iic_scl_io,
iic_sda_io);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
output [0:31]EPC_INTF_addr;
output EPC_INTF_ads;
output [0:3]EPC_INTF_be;
output EPC_INTF_burst;
input EPC_INTF_clk;
output [0:0]EPC_INTF_cs_n;
output EPC_INTF_rd_n;
input [0:0]EPC_INTF_rdy;
output EPC_INTF_rnw;
input EPC_INTF_rst;
output EPC_INTF_wr_n;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [0:0]Int0;
input [0:0]Int1;
input [0:0]Int2;
input [0:0]Int3;
input OCXO_CLK100;
output [0:0]OCXO_RESETN;
input UART_0_rxd;
output UART_0_txd;
input Vp_Vn_v_n;
input Vp_Vn_v_p;
inout [31:0]epc_intf_data_io;
inout [15:0]gpio_tri_io;
inout iic_0_scl_io;
inout iic_0_sda_io;
inout iic_1_scl_io;
inout iic_1_sda_io;
inout iic_scl_io;
inout iic_sda_io;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire [0:31]EPC_INTF_addr;
wire EPC_INTF_ads;
wire [0:3]EPC_INTF_be;
wire EPC_INTF_burst;
wire EPC_INTF_clk;
wire [0:0]EPC_INTF_cs_n;
wire EPC_INTF_rd_n;
wire [0:0]EPC_INTF_rdy;
wire EPC_INTF_rnw;
wire EPC_INTF_rst;
wire EPC_INTF_wr_n;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [0:0]Int0;
wire [0:0]Int1;
wire [0:0]Int2;
wire [0:0]Int3;
wire OCXO_CLK100;
wire [0:0]OCXO_RESETN;
wire UART_0_rxd;
wire UART_0_txd;
wire Vp_Vn_v_n;
wire Vp_Vn_v_p;
wire [0:0]epc_intf_data_i_0;
wire [1:1]epc_intf_data_i_1;
wire [10:10]epc_intf_data_i_10;
wire [11:11]epc_intf_data_i_11;
wire [12:12]epc_intf_data_i_12;
wire [13:13]epc_intf_data_i_13;
wire [14:14]epc_intf_data_i_14;
wire [15:15]epc_intf_data_i_15;
wire [16:16]epc_intf_data_i_16;
wire [17:17]epc_intf_data_i_17;
wire [18:18]epc_intf_data_i_18;
wire [19:19]epc_intf_data_i_19;
wire [2:2]epc_intf_data_i_2;
wire [20:20]epc_intf_data_i_20;
wire [21:21]epc_intf_data_i_21;
wire [22:22]epc_intf_data_i_22;
wire [23:23]epc_intf_data_i_23;
wire [24:24]epc_intf_data_i_24;
wire [25:25]epc_intf_data_i_25;
wire [26:26]epc_intf_data_i_26;
wire [27:27]epc_intf_data_i_27;
wire [28:28]epc_intf_data_i_28;
wire [29:29]epc_intf_data_i_29;
wire [3:3]epc_intf_data_i_3;
wire [30:30]epc_intf_data_i_30;
wire [31:31]epc_intf_data_i_31;
wire [4:4]epc_intf_data_i_4;
wire [5:5]epc_intf_data_i_5;
wire [6:6]epc_intf_data_i_6;
wire [7:7]epc_intf_data_i_7;
wire [8:8]epc_intf_data_i_8;
wire [9:9]epc_intf_data_i_9;
wire [0:0]epc_intf_data_io_0;
wire [1:1]epc_intf_data_io_1;
wire [10:10]epc_intf_data_io_10;
wire [11:11]epc_intf_data_io_11;
wire [12:12]epc_intf_data_io_12;
wire [13:13]epc_intf_data_io_13;
wire [14:14]epc_intf_data_io_14;
wire [15:15]epc_intf_data_io_15;
wire [16:16]epc_intf_data_io_16;
wire [17:17]epc_intf_data_io_17;
wire [18:18]epc_intf_data_io_18;
wire [19:19]epc_intf_data_io_19;
wire [2:2]epc_intf_data_io_2;
wire [20:20]epc_intf_data_io_20;
wire [21:21]epc_intf_data_io_21;
wire [22:22]epc_intf_data_io_22;
wire [23:23]epc_intf_data_io_23;
wire [24:24]epc_intf_data_io_24;
wire [25:25]epc_intf_data_io_25;
wire [26:26]epc_intf_data_io_26;
wire [27:27]epc_intf_data_io_27;
wire [28:28]epc_intf_data_io_28;
wire [29:29]epc_intf_data_io_29;
wire [3:3]epc_intf_data_io_3;
wire [30:30]epc_intf_data_io_30;
wire [31:31]epc_intf_data_io_31;
wire [4:4]epc_intf_data_io_4;
wire [5:5]epc_intf_data_io_5;
wire [6:6]epc_intf_data_io_6;
wire [7:7]epc_intf_data_io_7;
wire [8:8]epc_intf_data_io_8;
wire [9:9]epc_intf_data_io_9;
wire [0:0]epc_intf_data_o_0;
wire [1:1]epc_intf_data_o_1;
wire [10:10]epc_intf_data_o_10;
wire [11:11]epc_intf_data_o_11;
wire [12:12]epc_intf_data_o_12;
wire [13:13]epc_intf_data_o_13;
wire [14:14]epc_intf_data_o_14;
wire [15:15]epc_intf_data_o_15;
wire [16:16]epc_intf_data_o_16;
wire [17:17]epc_intf_data_o_17;
wire [18:18]epc_intf_data_o_18;
wire [19:19]epc_intf_data_o_19;
wire [2:2]epc_intf_data_o_2;
wire [20:20]epc_intf_data_o_20;
wire [21:21]epc_intf_data_o_21;
wire [22:22]epc_intf_data_o_22;
wire [23:23]epc_intf_data_o_23;
wire [24:24]epc_intf_data_o_24;
wire [25:25]epc_intf_data_o_25;
wire [26:26]epc_intf_data_o_26;
wire [27:27]epc_intf_data_o_27;
wire [28:28]epc_intf_data_o_28;
wire [29:29]epc_intf_data_o_29;
wire [3:3]epc_intf_data_o_3;
wire [30:30]epc_intf_data_o_30;
wire [31:31]epc_intf_data_o_31;
wire [4:4]epc_intf_data_o_4;
wire [5:5]epc_intf_data_o_5;
wire [6:6]epc_intf_data_o_6;
wire [7:7]epc_intf_data_o_7;
wire [8:8]epc_intf_data_o_8;
wire [9:9]epc_intf_data_o_9;
wire [0:0]epc_intf_data_t_0;
wire [1:1]epc_intf_data_t_1;
wire [10:10]epc_intf_data_t_10;
wire [11:11]epc_intf_data_t_11;
wire [12:12]epc_intf_data_t_12;
wire [13:13]epc_intf_data_t_13;
wire [14:14]epc_intf_data_t_14;
wire [15:15]epc_intf_data_t_15;
wire [16:16]epc_intf_data_t_16;
wire [17:17]epc_intf_data_t_17;
wire [18:18]epc_intf_data_t_18;
wire [19:19]epc_intf_data_t_19;
wire [2:2]epc_intf_data_t_2;
wire [20:20]epc_intf_data_t_20;
wire [21:21]epc_intf_data_t_21;
wire [22:22]epc_intf_data_t_22;
wire [23:23]epc_intf_data_t_23;
wire [24:24]epc_intf_data_t_24;
wire [25:25]epc_intf_data_t_25;
wire [26:26]epc_intf_data_t_26;
wire [27:27]epc_intf_data_t_27;
wire [28:28]epc_intf_data_t_28;
wire [29:29]epc_intf_data_t_29;
wire [3:3]epc_intf_data_t_3;
wire [30:30]epc_intf_data_t_30;
wire [31:31]epc_intf_data_t_31;
wire [4:4]epc_intf_data_t_4;
wire [5:5]epc_intf_data_t_5;
wire [6:6]epc_intf_data_t_6;
wire [7:7]epc_intf_data_t_7;
wire [8:8]epc_intf_data_t_8;
wire [9:9]epc_intf_data_t_9;
wire [0:0]gpio_tri_i_0;
wire [1:1]gpio_tri_i_1;
wire [10:10]gpio_tri_i_10;
wire [11:11]gpio_tri_i_11;
wire [12:12]gpio_tri_i_12;
wire [13:13]gpio_tri_i_13;
wire [14:14]gpio_tri_i_14;
wire [15:15]gpio_tri_i_15;
wire [2:2]gpio_tri_i_2;
wire [3:3]gpio_tri_i_3;
wire [4:4]gpio_tri_i_4;
wire [5:5]gpio_tri_i_5;
wire [6:6]gpio_tri_i_6;
wire [7:7]gpio_tri_i_7;
wire [8:8]gpio_tri_i_8;
wire [9:9]gpio_tri_i_9;
wire [0:0]gpio_tri_io_0;
wire [1:1]gpio_tri_io_1;
wire [10:10]gpio_tri_io_10;
wire [11:11]gpio_tri_io_11;
wire [12:12]gpio_tri_io_12;
wire [13:13]gpio_tri_io_13;
wire [14:14]gpio_tri_io_14;
wire [15:15]gpio_tri_io_15;
wire [2:2]gpio_tri_io_2;
wire [3:3]gpio_tri_io_3;
wire [4:4]gpio_tri_io_4;
wire [5:5]gpio_tri_io_5;
wire [6:6]gpio_tri_io_6;
wire [7:7]gpio_tri_io_7;
wire [8:8]gpio_tri_io_8;
wire [9:9]gpio_tri_io_9;
wire [0:0]gpio_tri_o_0;
wire [1:1]gpio_tri_o_1;
wire [10:10]gpio_tri_o_10;
wire [11:11]gpio_tri_o_11;
wire [12:12]gpio_tri_o_12;
wire [13:13]gpio_tri_o_13;
wire [14:14]gpio_tri_o_14;
wire [15:15]gpio_tri_o_15;
wire [2:2]gpio_tri_o_2;
wire [3:3]gpio_tri_o_3;
wire [4:4]gpio_tri_o_4;
wire [5:5]gpio_tri_o_5;
wire [6:6]gpio_tri_o_6;
wire [7:7]gpio_tri_o_7;
wire [8:8]gpio_tri_o_8;
wire [9:9]gpio_tri_o_9;
wire [0:0]gpio_tri_t_0;
wire [1:1]gpio_tri_t_1;
wire [10:10]gpio_tri_t_10;
wire [11:11]gpio_tri_t_11;
wire [12:12]gpio_tri_t_12;
wire [13:13]gpio_tri_t_13;
wire [14:14]gpio_tri_t_14;
wire [15:15]gpio_tri_t_15;
wire [2:2]gpio_tri_t_2;
wire [3:3]gpio_tri_t_3;
wire [4:4]gpio_tri_t_4;
wire [5:5]gpio_tri_t_5;
wire [6:6]gpio_tri_t_6;
wire [7:7]gpio_tri_t_7;
wire [8:8]gpio_tri_t_8;
wire [9:9]gpio_tri_t_9;
wire iic_0_scl_i;
wire iic_0_scl_io;
wire iic_0_scl_o;
wire iic_0_scl_t;
wire iic_0_sda_i;
wire iic_0_sda_io;
wire iic_0_sda_o;
wire iic_0_sda_t;
wire iic_1_scl_i;
wire iic_1_scl_io;
wire iic_1_scl_o;
wire iic_1_scl_t;
wire iic_1_sda_i;
wire iic_1_sda_io;
wire iic_1_sda_o;
wire iic_1_sda_t;
wire iic_scl_i;
wire iic_scl_io;
wire iic_scl_o;
wire iic_scl_t;
wire iic_sda_i;
wire iic_sda_io;
wire iic_sda_o;
wire iic_sda_t;
cpu cpu_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.EPC_INTF_addr(EPC_INTF_addr),
.EPC_INTF_ads(EPC_INTF_ads),
.EPC_INTF_be(EPC_INTF_be),
.EPC_INTF_burst(EPC_INTF_burst),
.EPC_INTF_clk(EPC_INTF_clk),
.EPC_INTF_cs_n(EPC_INTF_cs_n),
.EPC_INTF_data_i({epc_intf_data_i_0,epc_intf_data_i_1,epc_intf_data_i_2,epc_intf_data_i_3,epc_intf_data_i_4,epc_intf_data_i_5,epc_intf_data_i_6,epc_intf_data_i_7,epc_intf_data_i_8,epc_intf_data_i_9,epc_intf_data_i_10,epc_intf_data_i_11,epc_intf_data_i_12,epc_intf_data_i_13,epc_intf_data_i_14,epc_intf_data_i_15,epc_intf_data_i_16,epc_intf_data_i_17,epc_intf_data_i_18,epc_intf_data_i_19,epc_intf_data_i_20,epc_intf_data_i_21,epc_intf_data_i_22,epc_intf_data_i_23,epc_intf_data_i_24,epc_intf_data_i_25,epc_intf_data_i_26,epc_intf_data_i_27,epc_intf_data_i_28,epc_intf_data_i_29,epc_intf_data_i_30,epc_intf_data_i_31}),
.EPC_INTF_data_o({epc_intf_data_o_0,epc_intf_data_o_1,epc_intf_data_o_2,epc_intf_data_o_3,epc_intf_data_o_4,epc_intf_data_o_5,epc_intf_data_o_6,epc_intf_data_o_7,epc_intf_data_o_8,epc_intf_data_o_9,epc_intf_data_o_10,epc_intf_data_o_11,epc_intf_data_o_12,epc_intf_data_o_13,epc_intf_data_o_14,epc_intf_data_o_15,epc_intf_data_o_16,epc_intf_data_o_17,epc_intf_data_o_18,epc_intf_data_o_19,epc_intf_data_o_20,epc_intf_data_o_21,epc_intf_data_o_22,epc_intf_data_o_23,epc_intf_data_o_24,epc_intf_data_o_25,epc_intf_data_o_26,epc_intf_data_o_27,epc_intf_data_o_28,epc_intf_data_o_29,epc_intf_data_o_30,epc_intf_data_o_31}),
.EPC_INTF_data_t({epc_intf_data_t_0,epc_intf_data_t_1,epc_intf_data_t_2,epc_intf_data_t_3,epc_intf_data_t_4,epc_intf_data_t_5,epc_intf_data_t_6,epc_intf_data_t_7,epc_intf_data_t_8,epc_intf_data_t_9,epc_intf_data_t_10,epc_intf_data_t_11,epc_intf_data_t_12,epc_intf_data_t_13,epc_intf_data_t_14,epc_intf_data_t_15,epc_intf_data_t_16,epc_intf_data_t_17,epc_intf_data_t_18,epc_intf_data_t_19,epc_intf_data_t_20,epc_intf_data_t_21,epc_intf_data_t_22,epc_intf_data_t_23,epc_intf_data_t_24,epc_intf_data_t_25,epc_intf_data_t_26,epc_intf_data_t_27,epc_intf_data_t_28,epc_intf_data_t_29,epc_intf_data_t_30,epc_intf_data_t_31}),
.EPC_INTF_rd_n(EPC_INTF_rd_n),
.EPC_INTF_rdy(EPC_INTF_rdy),
.EPC_INTF_rnw(EPC_INTF_rnw),
.EPC_INTF_rst(EPC_INTF_rst),
.EPC_INTF_wr_n(EPC_INTF_wr_n),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.GPIO_tri_i({gpio_tri_i_15,gpio_tri_i_14,gpio_tri_i_13,gpio_tri_i_12,gpio_tri_i_11,gpio_tri_i_10,gpio_tri_i_9,gpio_tri_i_8,gpio_tri_i_7,gpio_tri_i_6,gpio_tri_i_5,gpio_tri_i_4,gpio_tri_i_3,gpio_tri_i_2,gpio_tri_i_1,gpio_tri_i_0}),
.GPIO_tri_o({gpio_tri_o_15,gpio_tri_o_14,gpio_tri_o_13,gpio_tri_o_12,gpio_tri_o_11,gpio_tri_o_10,gpio_tri_o_9,gpio_tri_o_8,gpio_tri_o_7,gpio_tri_o_6,gpio_tri_o_5,gpio_tri_o_4,gpio_tri_o_3,gpio_tri_o_2,gpio_tri_o_1,gpio_tri_o_0}),
.GPIO_tri_t({gpio_tri_t_15,gpio_tri_t_14,gpio_tri_t_13,gpio_tri_t_12,gpio_tri_t_11,gpio_tri_t_10,gpio_tri_t_9,gpio_tri_t_8,gpio_tri_t_7,gpio_tri_t_6,gpio_tri_t_5,gpio_tri_t_4,gpio_tri_t_3,gpio_tri_t_2,gpio_tri_t_1,gpio_tri_t_0}),
.IIC_0_scl_i(iic_0_scl_i),
.IIC_0_scl_o(iic_0_scl_o),
.IIC_0_scl_t(iic_0_scl_t),
.IIC_0_sda_i(iic_0_sda_i),
.IIC_0_sda_o(iic_0_sda_o),
.IIC_0_sda_t(iic_0_sda_t),
.IIC_1_scl_i(iic_1_scl_i),
.IIC_1_scl_o(iic_1_scl_o),
.IIC_1_scl_t(iic_1_scl_t),
.IIC_1_sda_i(iic_1_sda_i),
.IIC_1_sda_o(iic_1_sda_o),
.IIC_1_sda_t(iic_1_sda_t),
.IIC_scl_i(iic_scl_i),
.IIC_scl_o(iic_scl_o),
.IIC_scl_t(iic_scl_t),
.IIC_sda_i(iic_sda_i),
.IIC_sda_o(iic_sda_o),
.IIC_sda_t(iic_sda_t),
.Int0(Int0),
.Int1(Int1),
.Int2(Int2),
.Int3(Int3),
.OCXO_CLK100(OCXO_CLK100),
.OCXO_RESETN(OCXO_RESETN),
.UART_0_rxd(UART_0_rxd),
.UART_0_txd(UART_0_txd),
.Vp_Vn_v_n(Vp_Vn_v_n),
.Vp_Vn_v_p(Vp_Vn_v_p));
IOBUF epc_intf_data_iobuf_0
(.I(epc_intf_data_o_0),
.IO(epc_intf_data_io[0]),
.O(epc_intf_data_i_0),
.T(epc_intf_data_t_0));
IOBUF epc_intf_data_iobuf_1
(.I(epc_intf_data_o_1),
.IO(epc_intf_data_io[1]),
.O(epc_intf_data_i_1),
.T(epc_intf_data_t_1));
IOBUF epc_intf_data_iobuf_10
(.I(epc_intf_data_o_10),
.IO(epc_intf_data_io[10]),
.O(epc_intf_data_i_10),
.T(epc_intf_data_t_10));
IOBUF epc_intf_data_iobuf_11
(.I(epc_intf_data_o_11),
.IO(epc_intf_data_io[11]),
.O(epc_intf_data_i_11),
.T(epc_intf_data_t_11));
IOBUF epc_intf_data_iobuf_12
(.I(epc_intf_data_o_12),
.IO(epc_intf_data_io[12]),
.O(epc_intf_data_i_12),
.T(epc_intf_data_t_12));
IOBUF epc_intf_data_iobuf_13
(.I(epc_intf_data_o_13),
.IO(epc_intf_data_io[13]),
.O(epc_intf_data_i_13),
.T(epc_intf_data_t_13));
IOBUF epc_intf_data_iobuf_14
(.I(epc_intf_data_o_14),
.IO(epc_intf_data_io[14]),
.O(epc_intf_data_i_14),
.T(epc_intf_data_t_14));
IOBUF epc_intf_data_iobuf_15
(.I(epc_intf_data_o_15),
.IO(epc_intf_data_io[15]),
.O(epc_intf_data_i_15),
.T(epc_intf_data_t_15));
IOBUF epc_intf_data_iobuf_16
(.I(epc_intf_data_o_16),
.IO(epc_intf_data_io[16]),
.O(epc_intf_data_i_16),
.T(epc_intf_data_t_16));
IOBUF epc_intf_data_iobuf_17
(.I(epc_intf_data_o_17),
.IO(epc_intf_data_io[17]),
.O(epc_intf_data_i_17),
.T(epc_intf_data_t_17));
IOBUF epc_intf_data_iobuf_18
(.I(epc_intf_data_o_18),
.IO(epc_intf_data_io[18]),
.O(epc_intf_data_i_18),
.T(epc_intf_data_t_18));
IOBUF epc_intf_data_iobuf_19
(.I(epc_intf_data_o_19),
.IO(epc_intf_data_io[19]),
.O(epc_intf_data_i_19),
.T(epc_intf_data_t_19));
IOBUF epc_intf_data_iobuf_2
(.I(epc_intf_data_o_2),
.IO(epc_intf_data_io[2]),
.O(epc_intf_data_i_2),
.T(epc_intf_data_t_2));
IOBUF epc_intf_data_iobuf_20
(.I(epc_intf_data_o_20),
.IO(epc_intf_data_io[20]),
.O(epc_intf_data_i_20),
.T(epc_intf_data_t_20));
IOBUF epc_intf_data_iobuf_21
(.I(epc_intf_data_o_21),
.IO(epc_intf_data_io[21]),
.O(epc_intf_data_i_21),
.T(epc_intf_data_t_21));
IOBUF epc_intf_data_iobuf_22
(.I(epc_intf_data_o_22),
.IO(epc_intf_data_io[22]),
.O(epc_intf_data_i_22),
.T(epc_intf_data_t_22));
IOBUF epc_intf_data_iobuf_23
(.I(epc_intf_data_o_23),
.IO(epc_intf_data_io[23]),
.O(epc_intf_data_i_23),
.T(epc_intf_data_t_23));
IOBUF epc_intf_data_iobuf_24
(.I(epc_intf_data_o_24),
.IO(epc_intf_data_io[24]),
.O(epc_intf_data_i_24),
.T(epc_intf_data_t_24));
IOBUF epc_intf_data_iobuf_25
(.I(epc_intf_data_o_25),
.IO(epc_intf_data_io[25]),
.O(epc_intf_data_i_25),
.T(epc_intf_data_t_25));
IOBUF epc_intf_data_iobuf_26
(.I(epc_intf_data_o_26),
.IO(epc_intf_data_io[26]),
.O(epc_intf_data_i_26),
.T(epc_intf_data_t_26));
IOBUF epc_intf_data_iobuf_27
(.I(epc_intf_data_o_27),
.IO(epc_intf_data_io[27]),
.O(epc_intf_data_i_27),
.T(epc_intf_data_t_27));
IOBUF epc_intf_data_iobuf_28
(.I(epc_intf_data_o_28),
.IO(epc_intf_data_io[28]),
.O(epc_intf_data_i_28),
.T(epc_intf_data_t_28));
IOBUF epc_intf_data_iobuf_29
(.I(epc_intf_data_o_29),
.IO(epc_intf_data_io[29]),
.O(epc_intf_data_i_29),
.T(epc_intf_data_t_29));
IOBUF epc_intf_data_iobuf_3
(.I(epc_intf_data_o_3),
.IO(epc_intf_data_io[3]),
.O(epc_intf_data_i_3),
.T(epc_intf_data_t_3));
IOBUF epc_intf_data_iobuf_30
(.I(epc_intf_data_o_30),
.IO(epc_intf_data_io[30]),
.O(epc_intf_data_i_30),
.T(epc_intf_data_t_30));
IOBUF epc_intf_data_iobuf_31
(.I(epc_intf_data_o_31),
.IO(epc_intf_data_io[31]),
.O(epc_intf_data_i_31),
.T(epc_intf_data_t_31));
IOBUF epc_intf_data_iobuf_4
(.I(epc_intf_data_o_4),
.IO(epc_intf_data_io[4]),
.O(epc_intf_data_i_4),
.T(epc_intf_data_t_4));
IOBUF epc_intf_data_iobuf_5
(.I(epc_intf_data_o_5),
.IO(epc_intf_data_io[5]),
.O(epc_intf_data_i_5),
.T(epc_intf_data_t_5));
IOBUF epc_intf_data_iobuf_6
(.I(epc_intf_data_o_6),
.IO(epc_intf_data_io[6]),
.O(epc_intf_data_i_6),
.T(epc_intf_data_t_6));
IOBUF epc_intf_data_iobuf_7
(.I(epc_intf_data_o_7),
.IO(epc_intf_data_io[7]),
.O(epc_intf_data_i_7),
.T(epc_intf_data_t_7));
IOBUF epc_intf_data_iobuf_8
(.I(epc_intf_data_o_8),
.IO(epc_intf_data_io[8]),
.O(epc_intf_data_i_8),
.T(epc_intf_data_t_8));
IOBUF epc_intf_data_iobuf_9
(.I(epc_intf_data_o_9),
.IO(epc_intf_data_io[9]),
.O(epc_intf_data_i_9),
.T(epc_intf_data_t_9));
IOBUF gpio_tri_iobuf_0
(.I(gpio_tri_o_0),
.IO(gpio_tri_io[0]),
.O(gpio_tri_i_0),
.T(gpio_tri_t_0));
IOBUF gpio_tri_iobuf_1
(.I(gpio_tri_o_1),
.IO(gpio_tri_io[1]),
.O(gpio_tri_i_1),
.T(gpio_tri_t_1));
IOBUF gpio_tri_iobuf_10
(.I(gpio_tri_o_10),
.IO(gpio_tri_io[10]),
.O(gpio_tri_i_10),
.T(gpio_tri_t_10));
IOBUF gpio_tri_iobuf_11
(.I(gpio_tri_o_11),
.IO(gpio_tri_io[11]),
.O(gpio_tri_i_11),
.T(gpio_tri_t_11));
IOBUF gpio_tri_iobuf_12
(.I(gpio_tri_o_12),
.IO(gpio_tri_io[12]),
.O(gpio_tri_i_12),
.T(gpio_tri_t_12));
IOBUF gpio_tri_iobuf_13
(.I(gpio_tri_o_13),
.IO(gpio_tri_io[13]),
.O(gpio_tri_i_13),
.T(gpio_tri_t_13));
IOBUF gpio_tri_iobuf_14
(.I(gpio_tri_o_14),
.IO(gpio_tri_io[14]),
.O(gpio_tri_i_14),
.T(gpio_tri_t_14));
IOBUF gpio_tri_iobuf_15
(.I(gpio_tri_o_15),
.IO(gpio_tri_io[15]),
.O(gpio_tri_i_15),
.T(gpio_tri_t_15));
IOBUF gpio_tri_iobuf_2
(.I(gpio_tri_o_2),
.IO(gpio_tri_io[2]),
.O(gpio_tri_i_2),
.T(gpio_tri_t_2));
IOBUF gpio_tri_iobuf_3
(.I(gpio_tri_o_3),
.IO(gpio_tri_io[3]),
.O(gpio_tri_i_3),
.T(gpio_tri_t_3));
IOBUF gpio_tri_iobuf_4
(.I(gpio_tri_o_4),
.IO(gpio_tri_io[4]),
.O(gpio_tri_i_4),
.T(gpio_tri_t_4));
IOBUF gpio_tri_iobuf_5
(.I(gpio_tri_o_5),
.IO(gpio_tri_io[5]),
.O(gpio_tri_i_5),
.T(gpio_tri_t_5));
IOBUF gpio_tri_iobuf_6
(.I(gpio_tri_o_6),
.IO(gpio_tri_io[6]),
.O(gpio_tri_i_6),
.T(gpio_tri_t_6));
IOBUF gpio_tri_iobuf_7
(.I(gpio_tri_o_7),
.IO(gpio_tri_io[7]),
.O(gpio_tri_i_7),
.T(gpio_tri_t_7));
IOBUF gpio_tri_iobuf_8
(.I(gpio_tri_o_8),
.IO(gpio_tri_io[8]),
.O(gpio_tri_i_8),
.T(gpio_tri_t_8));
IOBUF gpio_tri_iobuf_9
(.I(gpio_tri_o_9),
.IO(gpio_tri_io[9]),
.O(gpio_tri_i_9),
.T(gpio_tri_t_9));
IOBUF iic_0_scl_iobuf
(.I(iic_0_scl_o),
.IO(iic_0_scl_io),
.O(iic_0_scl_i),
.T(iic_0_scl_t));
IOBUF iic_0_sda_iobuf
(.I(iic_0_sda_o),
.IO(iic_0_sda_io),
.O(iic_0_sda_i),
.T(iic_0_sda_t));
IOBUF iic_1_scl_iobuf
(.I(iic_1_scl_o),
.IO(iic_1_scl_io),
.O(iic_1_scl_i),
.T(iic_1_scl_t));
IOBUF iic_1_sda_iobuf
(.I(iic_1_sda_o),
.IO(iic_1_sda_io),
.O(iic_1_sda_i),
.T(iic_1_sda_t));
IOBUF iic_scl_iobuf
(.I(iic_scl_o),
.IO(iic_scl_io),
.O(iic_scl_i),
.T(iic_scl_t));
IOBUF iic_sda_iobuf
(.I(iic_sda_o),
.IO(iic_sda_io),
.O(iic_sda_i),
.T(iic_sda_t));
endmodule
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4-Stream 10GBASE-R frame transmitter (AXI in, 10GBASE-R out)
*/
module axis_baser_tx_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE,
parameter PTP_TAG_WIDTH = 16,
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_tx_data,
output wire [HDR_WIDTH-1:0] encoded_tx_hdr,
/*
* PTP
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts,
output wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag,
output wire m_axis_ptp_ts_valid,
/*
* Configuration
*/
input wire [7:0] ifg_delay,
/*
* Status
*/
output wire [1:0] start_packet,
output wire error_underflow
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
localparam MIN_FL_NOCRC = MIN_FRAME_LENGTH-4;
localparam MIN_FL_NOCRC_MS = MIN_FL_NOCRC & 16'hfff8;
localparam MIN_FL_NOCRC_LS = MIN_FL_NOCRC & 16'h0007;
localparam [7:0]
ETH_PRE = 8'h55,
ETH_SFD = 8'hD5;
localparam [6:0]
CTRL_IDLE = 7'h00,
CTRL_LPI = 7'h06,
CTRL_ERROR = 7'h1e,
CTRL_RES_0 = 7'h2d,
CTRL_RES_1 = 7'h33,
CTRL_RES_2 = 7'h4b,
CTRL_RES_3 = 7'h55,
CTRL_RES_4 = 7'h66,
CTRL_RES_5 = 7'h78;
localparam [3:0]
O_SEQ_OS = 4'h0,
O_SIG_OS = 4'hf;
localparam [1:0]
SYNC_DATA = 2'b10,
SYNC_CTRL = 2'b01;
localparam [7:0]
BLOCK_TYPE_CTRL = 8'h1e, // C7 C6 C5 C4 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_4 = 8'h2d, // D7 D6 D5 O4 C3 C2 C1 C0 BT
BLOCK_TYPE_START_4 = 8'h33, // D7 D6 D5 C3 C2 C1 C0 BT
BLOCK_TYPE_OS_START = 8'h66, // D7 D6 D5 O0 D3 D2 D1 BT
BLOCK_TYPE_OS_04 = 8'h55, // D7 D6 D5 O4 O0 D3 D2 D1 BT
BLOCK_TYPE_START_0 = 8'h78, // D7 D6 D5 D4 D3 D2 D1 BT
BLOCK_TYPE_OS_0 = 8'h4b, // C7 C6 C5 C4 O0 D3 D2 D1 BT
BLOCK_TYPE_TERM_0 = 8'h87, // C7 C6 C5 C4 C3 C2 C1 BT
BLOCK_TYPE_TERM_1 = 8'h99, // C7 C6 C5 C4 C3 C2 D0 BT
BLOCK_TYPE_TERM_2 = 8'haa, // C7 C6 C5 C4 C3 D1 D0 BT
BLOCK_TYPE_TERM_3 = 8'hb4, // C7 C6 C5 C4 D2 D1 D0 BT
BLOCK_TYPE_TERM_4 = 8'hcc, // C7 C6 C5 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_5 = 8'hd2, // C7 C6 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_6 = 8'he1, // C7 D5 D4 D3 D2 D1 D0 BT
BLOCK_TYPE_TERM_7 = 8'hff; // D6 D5 D4 D3 D2 D1 D0 BT
localparam [3:0]
OUTPUT_TYPE_IDLE = 4'd0,
OUTPUT_TYPE_ERROR = 4'd1,
OUTPUT_TYPE_START_0 = 4'd2,
OUTPUT_TYPE_START_4 = 4'd3,
OUTPUT_TYPE_DATA = 4'd4,
OUTPUT_TYPE_TERM_0 = 4'd8,
OUTPUT_TYPE_TERM_1 = 4'd9,
OUTPUT_TYPE_TERM_2 = 4'd10,
OUTPUT_TYPE_TERM_3 = 4'd11,
OUTPUT_TYPE_TERM_4 = 4'd12,
OUTPUT_TYPE_TERM_5 = 4'd13,
OUTPUT_TYPE_TERM_6 = 4'd14,
OUTPUT_TYPE_TERM_7 = 4'd15;
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1,
STATE_PAD = 3'd2,
STATE_FCS_1 = 3'd3,
STATE_FCS_2 = 3'd4,
STATE_IFG = 3'd5,
STATE_WAIT_END = 3'd6;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg swap_lanes;
reg unswap_lanes;
reg lanes_swapped = 1'b0;
reg [31:0] swap_data = 32'd0;
reg delay_type_valid = 1'b0;
reg [3:0] delay_type = OUTPUT_TYPE_IDLE;
reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
reg [DATA_WIDTH-1:0] s_tdata_reg = {DATA_WIDTH{1'b0}}, s_tdata_next;
reg [7:0] s_tkeep_reg = 8'd0, s_tkeep_next;
reg [DATA_WIDTH-1:0] fcs_output_data_0;
reg [DATA_WIDTH-1:0] fcs_output_data_1;
reg [3:0] fcs_output_type_0;
reg [3:0] fcs_output_type_1;
reg [7:0] ifg_offset;
reg extra_cycle;
reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
reg [7:0] ifg_count_reg = 8'd0, ifg_count_next;
reg [1:0] deficit_idle_count_reg = 2'd0, deficit_idle_count_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [PTP_TS_WIDTH-1:0] m_axis_ptp_ts_reg = 0, m_axis_ptp_ts_next;
reg [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag_reg = 0, m_axis_ptp_ts_tag_next;
reg m_axis_ptp_ts_valid_reg = 1'b0, m_axis_ptp_ts_valid_next;
reg m_axis_ptp_ts_valid_int_reg = 1'b0, m_axis_ptp_ts_valid_int_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next4;
wire [31:0] crc_next5;
wire [31:0] crc_next6;
wire [31:0] crc_next7;
reg [DATA_WIDTH-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
reg [HDR_WIDTH-1:0] encoded_tx_hdr_reg = SYNC_CTRL;
reg [DATA_WIDTH-1:0] output_data_reg = {DATA_WIDTH{1'b0}}, output_data_next;
reg [3:0] output_type_reg = OUTPUT_TYPE_IDLE, output_type_next;
reg [1:0] start_packet_reg = 2'b00, start_packet_next;
reg error_underflow_reg = 1'b0, error_underflow_next;
assign s_axis_tready = s_axis_tready_reg;
assign encoded_tx_data = encoded_tx_data_reg;
assign encoded_tx_hdr = encoded_tx_hdr_reg;
assign m_axis_ptp_ts = PTP_TS_ENABLE ? m_axis_ptp_ts_reg : 0;
assign m_axis_ptp_ts_tag = PTP_TAG_ENABLE ? m_axis_ptp_ts_tag_reg : 0;
assign m_axis_ptp_ts_valid = PTP_TS_ENABLE || PTP_TAG_ENABLE ? m_axis_ptp_ts_valid_reg : 1'b0;
assign start_packet = start_packet_reg;
assign error_underflow = error_underflow_reg;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(s_tdata_reg[7:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(s_tdata_reg[15:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(s_tdata_reg[23:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(s_tdata_reg[31:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(40),
.STYLE("AUTO")
)
eth_crc_40 (
.data_in(s_tdata_reg[39:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next4)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(48),
.STYLE("AUTO")
)
eth_crc_48 (
.data_in(s_tdata_reg[47:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next5)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(56),
.STYLE("AUTO")
)
eth_crc_56 (
.data_in(s_tdata_reg[55:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next6)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(s_tdata_reg[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
// Mask input data
integer j;
always @* begin
for (j = 0; j < 8; j = j + 1) begin
s_axis_tdata_masked[j*8 +: 8] = s_axis_tkeep[j] ? s_axis_tdata[j*8 +: 8] : 8'd0;
end
end
// FCS cycle calculation
always @* begin
casez (s_tkeep_reg)
8'bzzzzzz01: begin
fcs_output_data_0 = {24'd0, ~crc_next0[31:0], s_tdata_reg[7:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_5;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd3;
extra_cycle = 1'b0;
end
8'bzzzzz011: begin
fcs_output_data_0 = {16'd0, ~crc_next1[31:0], s_tdata_reg[15:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_6;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd2;
extra_cycle = 1'b0;
end
8'bzzzz0111: begin
fcs_output_data_0 = {8'd0, ~crc_next2[31:0], s_tdata_reg[23:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_TERM_7;
fcs_output_type_1 = OUTPUT_TYPE_IDLE;
ifg_offset = 8'd1;
extra_cycle = 1'b0;
end
8'bzzz01111: begin
fcs_output_data_0 = {~crc_next3[31:0], s_tdata_reg[31:0]};
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_0;
ifg_offset = 8'd8;
extra_cycle = 1'b1;
end
8'bzz011111: begin
fcs_output_data_0 = {~crc_next4[23:0], s_tdata_reg[39:0]};
fcs_output_data_1 = {56'd0, ~crc_next4[31:24]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_1;
ifg_offset = 8'd7;
extra_cycle = 1'b1;
end
8'bz0111111: begin
fcs_output_data_0 = {~crc_next5[15:0], s_tdata_reg[47:0]};
fcs_output_data_1 = {48'd0, ~crc_next5[31:16]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_2;
ifg_offset = 8'd6;
extra_cycle = 1'b1;
end
8'b01111111: begin
fcs_output_data_0 = {~crc_next6[7:0], s_tdata_reg[55:0]};
fcs_output_data_1 = {40'd0, ~crc_next6[31:8]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_3;
ifg_offset = 8'd5;
extra_cycle = 1'b1;
end
8'b11111111: begin
fcs_output_data_0 = s_tdata_reg;
fcs_output_data_1 = {32'd0, ~crc_next7[31:0]};
fcs_output_type_0 = OUTPUT_TYPE_DATA;
fcs_output_type_1 = OUTPUT_TYPE_TERM_4;
ifg_offset = 8'd4;
extra_cycle = 1'b1;
end
default: begin
fcs_output_data_0 = 64'd0;
fcs_output_data_1 = 64'd0;
fcs_output_type_0 = OUTPUT_TYPE_ERROR;
fcs_output_type_1 = OUTPUT_TYPE_ERROR;
ifg_offset = 8'd0;
extra_cycle = 1'b1;
end
endcase
end
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
swap_lanes = 1'b0;
unswap_lanes = 1'b0;
frame_ptr_next = frame_ptr_reg;
ifg_count_next = ifg_count_reg;
deficit_idle_count_next = deficit_idle_count_reg;
s_axis_tready_next = 1'b0;
s_tdata_next = s_tdata_reg;
s_tkeep_next = s_tkeep_reg;
m_axis_ptp_ts_next = m_axis_ptp_ts_reg;
m_axis_ptp_ts_tag_next = m_axis_ptp_ts_tag_reg;
m_axis_ptp_ts_valid_next = 1'b0;
m_axis_ptp_ts_valid_int_next = 1'b0;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
start_packet_next = 2'b00;
error_underflow_next = 1'b0;
if (m_axis_ptp_ts_valid_int_reg) begin
m_axis_ptp_ts_valid_next = 1'b1;
if (PTP_TS_WIDTH == 96 && $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000) > 0) begin
// ns field rollover
m_axis_ptp_ts_next[45:16] = $signed({1'b0, m_axis_ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
m_axis_ptp_ts_next[95:48] = m_axis_ptp_ts_reg[95:48] + 1;
end
end
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 16'd8;
reset_crc = 1'b1;
s_axis_tready_next = 1'b1;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_IDLE;
s_tdata_next = s_axis_tdata_masked;
s_tkeep_next = s_axis_tkeep;
if (s_axis_tvalid) begin
// XGMII start and preamble
if (ifg_count_reg > 8'd0) begin
// need to send more idles - swap lanes
swap_lanes = 1'b1;
if (PTP_TS_WIDTH == 96) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (((PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS) * 3) >> 1);
end
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_int_next = 1'b1;
start_packet_next = 2'b10;
end else begin
// no more idles - unswap
unswap_lanes = 1'b1;
if (PTP_TS_WIDTH == 96) begin
m_axis_ptp_ts_next[45:0] = ptp_ts[45:0] + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
m_axis_ptp_ts_next[95:48] = ptp_ts[95:48];
end else begin
m_axis_ptp_ts_next = ptp_ts + (PTP_PERIOD_NS * 2**16 + PTP_PERIOD_FNS);
end
m_axis_ptp_ts_tag_next = s_axis_tuser >> 1;
m_axis_ptp_ts_valid_int_next = 1'b1;
start_packet_next = 2'b01;
end
output_data_next = {ETH_SFD, {7{ETH_PRE}}};
output_type_next = OUTPUT_TYPE_START_0;
s_axis_tready_next = 1'b1;
state_next = STATE_PAYLOAD;
end else begin
ifg_count_next = 8'd0;
deficit_idle_count_next = 2'd0;
unswap_lanes = 1'b1;
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
update_crc = 1'b1;
s_axis_tready_next = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd8;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
s_tdata_next = s_axis_tdata_masked;
s_tkeep_next = s_axis_tkeep;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
frame_ptr_next = frame_ptr_reg + keep2count(s_axis_tkeep);
s_axis_tready_next = 1'b0;
if (s_axis_tuser[0]) begin
output_type_next = OUTPUT_TYPE_ERROR;
frame_ptr_next = 16'd0;
ifg_count_next = 8'd8;
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b0;
if (ENABLE_PADDING && (frame_ptr_reg < MIN_FL_NOCRC_MS || (frame_ptr_reg == MIN_FL_NOCRC_MS && keep2count(s_axis_tkeep) < MIN_FL_NOCRC_LS))) begin
s_tkeep_next = 8'hff;
frame_ptr_next = frame_ptr_reg + 16'd8;
if (frame_ptr_reg < (MIN_FL_NOCRC_LS > 0 ? MIN_FL_NOCRC_MS : MIN_FL_NOCRC_MS-8)) begin
state_next = STATE_PAD;
end else begin
s_tkeep_next = 8'hff >> ((8-MIN_FL_NOCRC_LS) % 8);
state_next = STATE_FCS_1;
end
end else begin
state_next = STATE_FCS_1;
end
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
// tvalid deassert, fail frame
output_type_next = OUTPUT_TYPE_ERROR;
frame_ptr_next = 16'd0;
ifg_count_next = 8'd8;
error_underflow_next = 1'b1;
state_next = STATE_WAIT_END;
end
end
STATE_PAD: begin
// pad frame to MIN_FRAME_LENGTH
s_axis_tready_next = 1'b0;
output_data_next = s_tdata_reg;
output_type_next = OUTPUT_TYPE_DATA;
s_tdata_next = 64'd0;
s_tkeep_next = 8'hff;
update_crc = 1'b1;
frame_ptr_next = frame_ptr_reg + 16'd8;
if (frame_ptr_reg < (MIN_FL_NOCRC_LS > 0 ? MIN_FL_NOCRC_MS : MIN_FL_NOCRC_MS-8)) begin
state_next = STATE_PAD;
end else begin
s_tkeep_next = 8'hff >> ((8-MIN_FL_NOCRC_LS) % 8);
state_next = STATE_FCS_1;
end
end
STATE_FCS_1: begin
// last cycle
s_axis_tready_next = 1'b0;
output_data_next = fcs_output_data_0;
output_type_next = fcs_output_type_0;
frame_ptr_next = 16'd0;
ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (lanes_swapped ? 8'd4 : 8'd0) + deficit_idle_count_reg;
if (extra_cycle) begin
state_next = STATE_FCS_2;
end else begin
state_next = STATE_IFG;
end
end
STATE_FCS_2: begin
// last cycle
s_axis_tready_next = 1'b0;
output_data_next = fcs_output_data_1;
output_type_next = fcs_output_type_1;
reset_crc = 1'b1;
frame_ptr_next = 16'd0;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end
STATE_IFG: begin
// send IFG
if (ifg_count_reg > 8'd8) begin
ifg_count_next = ifg_count_reg - 8'd8;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end
STATE_WAIT_END: begin
// wait for end of frame
s_axis_tready_next = 1'b1;
if (ifg_count_reg > 8'd4) begin
ifg_count_next = ifg_count_reg - 8'd4;
end else begin
ifg_count_next = 8'd0;
end
reset_crc = 1'b1;
if (s_axis_tvalid) begin
if (s_axis_tlast) begin
s_axis_tready_next = 1'b0;
if (ENABLE_DIC) begin
if (ifg_count_next > 8'd7) begin
state_next = STATE_IFG;
end else begin
if (ifg_count_next >= 8'd4) begin
deficit_idle_count_next = ifg_count_next - 8'd4;
end else begin
deficit_idle_count_next = ifg_count_next;
ifg_count_next = 8'd0;
end
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end else begin
if (ifg_count_next > 8'd4) begin
state_next = STATE_IFG;
end else begin
s_axis_tready_next = 1'b1;
state_next = STATE_IDLE;
end
end
end else begin
state_next = STATE_WAIT_END;
end
end else begin
state_next = STATE_WAIT_END;
end
end
endcase
end
always @(posedge clk) begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
ifg_count_reg <= ifg_count_next;
deficit_idle_count_reg <= deficit_idle_count_next;
s_tdata_reg <= s_tdata_next;
s_tkeep_reg <= s_tkeep_next;
s_axis_tready_reg <= s_axis_tready_next;
m_axis_ptp_ts_reg <= m_axis_ptp_ts_next;
m_axis_ptp_ts_tag_reg <= m_axis_ptp_ts_tag_next;
m_axis_ptp_ts_valid_reg <= m_axis_ptp_ts_valid_next;
m_axis_ptp_ts_valid_int_reg <= m_axis_ptp_ts_valid_int_next;
start_packet_reg <= start_packet_next;
error_underflow_reg <= error_underflow_next;
delay_type_valid <= 1'b0;
delay_type <= output_type_next ^ 4'd4;
swap_data <= output_data_next[63:32];
if (swap_lanes || (lanes_swapped && !unswap_lanes)) begin
lanes_swapped <= 1'b1;
output_data_reg <= {output_data_next[31:0], swap_data};
if (delay_type_valid) begin
output_type_reg <= delay_type;
end else if (output_type_next == OUTPUT_TYPE_START_0) begin
output_type_reg <= OUTPUT_TYPE_START_4;
end else if (output_type_next[3]) begin
// OUTPUT_TYPE_TERM_*
if (output_type_next[2]) begin
delay_type_valid <= 1'b1;
output_type_reg <= OUTPUT_TYPE_DATA;
end else begin
output_type_reg <= output_type_next ^ 4'd4;
end
end else begin
output_type_reg <= output_type_next;
end
end else begin
lanes_swapped <= 1'b0;
output_data_reg <= output_data_next;
output_type_reg <= output_type_next;
end
case (output_type_reg)
OUTPUT_TYPE_IDLE: begin
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_ERROR: begin
encoded_tx_data_reg <= {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_START_0: begin
encoded_tx_data_reg <= {output_data_reg[63:8], BLOCK_TYPE_START_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_START_4: begin
encoded_tx_data_reg <= {output_data_reg[63:40], 4'd0, {4{CTRL_IDLE}}, BLOCK_TYPE_START_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_DATA: begin
encoded_tx_data_reg <= output_data_reg;
encoded_tx_hdr_reg <= SYNC_DATA;
end
OUTPUT_TYPE_TERM_0: begin
encoded_tx_data_reg <= {{7{CTRL_IDLE}}, 7'd0, BLOCK_TYPE_TERM_0};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_1: begin
encoded_tx_data_reg <= {{6{CTRL_IDLE}}, 6'd0, output_data_reg[7:0], BLOCK_TYPE_TERM_1};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_2: begin
encoded_tx_data_reg <= {{5{CTRL_IDLE}}, 5'd0, output_data_reg[15:0], BLOCK_TYPE_TERM_2};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_3: begin
encoded_tx_data_reg <= {{4{CTRL_IDLE}}, 4'd0, output_data_reg[23:0], BLOCK_TYPE_TERM_3};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_4: begin
encoded_tx_data_reg <= {{3{CTRL_IDLE}}, 3'd0, output_data_reg[31:0], BLOCK_TYPE_TERM_4};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_5: begin
encoded_tx_data_reg <= {{2{CTRL_IDLE}}, 2'd0, output_data_reg[39:0], BLOCK_TYPE_TERM_5};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_6: begin
encoded_tx_data_reg <= {{1{CTRL_IDLE}}, 1'd0, output_data_reg[47:0], BLOCK_TYPE_TERM_6};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
OUTPUT_TYPE_TERM_7: begin
encoded_tx_data_reg <= {output_data_reg[55:0], BLOCK_TYPE_TERM_7};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
default: begin
encoded_tx_data_reg <= {{8{CTRL_ERROR}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
end
endcase
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next7;
end
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 16'd0;
ifg_count_reg <= 8'd0;
deficit_idle_count_reg <= 2'd0;
s_axis_tready_reg <= 1'b0;
m_axis_ptp_ts_valid_reg <= 1'b0;
m_axis_ptp_ts_valid_int_reg <= 1'b0;
encoded_tx_data_reg <= {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
encoded_tx_hdr_reg <= SYNC_CTRL;
output_data_reg <= {DATA_WIDTH{1'b0}};
output_type_reg <= OUTPUT_TYPE_IDLE;
start_packet_reg <= 2'b00;
error_underflow_reg <= 1'b0;
crc_state <= 32'hFFFFFFFF;
lanes_swapped <= 1'b0;
delay_type_valid <= 1'b0;
delay_type <= OUTPUT_TYPE_IDLE;
end
end
endmodule
`resetall
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Behavioral memory model
*/
`include "common.vh"
`include "ocp_const.vh"
/*
* RAM
*/
module memory #(
parameter MEMWORDS = 1048576 /* Memory size (number of data words) */
)
(
clk,
nrst,
/* OCP interface */
i_MAddr,
i_MCmd,
i_MData,
i_MByteEn,
o_SCmdAccept,
o_SData,
o_SResp
);
/* Inputs and outputs */
input wire clk;
input wire nrst;
input wire [`ADDR_WIDTH-1:0] i_MAddr;
input wire [2:0] i_MCmd;
input wire [`DATA_WIDTH-1:0] i_MData;
input wire [`BEN_WIDTH-1:0] i_MByteEn;
output wire o_SCmdAccept;
output reg [`DATA_WIDTH-1:0] o_SData;
output reg [1:0] o_SResp;
/* RAM */
reg [`DATA_WIDTH-1:0] mem[0:MEMWORDS-1];
integer i;
/* Preinit memory */
initial
begin : memory_init
`ifndef VERILATOR
reg [65536*8-1:0] filepath;
`else
reg [256*8-1:0] filepath;
/** Verilator limits string length to 64 words (256*8/32 = 64) **/
`endif
for(i=0; i<MEMWORDS; i=i+1) begin
mem[i] = 0;
end
if($value$plusargs("MEMORY_FILE=%s", filepath))
begin
$readmemh(filepath, mem);
end
else
begin
`ifdef MEMORY_IMAGE
$readmemh(`MEMORY_IMAGE, mem);
`endif
end
end
assign o_SCmdAccept = 1'b1; /* Always accept command */
/* Bus logic */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
o_SData <= { (`DATA_WIDTH){1'b0} };
o_SResp <= `OCP_RESP_NULL;
end
else
begin
/* verilator lint_off WIDTH */
case(i_MCmd)
`OCP_CMD_WRITE: begin
if(i_MAddr[`ADDR_WIDTH-1:2] < MEMWORDS)
begin
if(i_MByteEn[0]) mem[i_MAddr[`ADDR_WIDTH-1:2]][7:0] <= i_MData[7:0];
if(i_MByteEn[1]) mem[i_MAddr[`ADDR_WIDTH-1:2]][15:8] <= i_MData[15:8];
if(i_MByteEn[2]) mem[i_MAddr[`ADDR_WIDTH-1:2]][23:16] <= i_MData[23:16];
if(i_MByteEn[3]) mem[i_MAddr[`ADDR_WIDTH-1:2]][31:24] <= i_MData[31:24];
/* Note: Need to be modified if DATA_WIDTH/BEN_WIDTH changed. */
end
o_SResp <= `OCP_RESP_DVA;
end
`OCP_CMD_READ: begin
if(i_MAddr[`ADDR_WIDTH-1:2] < MEMWORDS)
begin
o_SData <= mem[i_MAddr[`ADDR_WIDTH-1:2]];
end
else
o_SData <= 32'hDEADDEAD;
o_SResp <= `OCP_RESP_DVA;
end
default: begin
o_SResp <= `OCP_RESP_NULL;
end
endcase
/* verilator lint_on WIDTH */
end
end
endmodule /* memory */
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9652 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
up_adc_gpio_in,
up_adc_gpio_out,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [15:0] adc_data_in_p;
input [15:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid_0;
output adc_enable_0;
output [15:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [15:0] adc_data_1;
input adc_dovf;
input adc_dunf;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
wire delay_rst;
// internal signals
wire [15:0] adc_data_a_s;
wire [15:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire [15:0] adc_dcfilter_data_a_s;
wire [15:0] adc_dcfilter_data_b_s;
wire [15:0] adc_channel_data_a_s;
wire [15:0] adc_channel_data_b_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire adc_ddr_edgesel_s;
wire adc_status_s;
wire [16:0] up_dld_s;
wire [84:0] up_dwdata_s;
wire [84:0] up_drdata_s;
wire delay_locked_s;
wire [31:0] up_rdata_s[0:3];
wire up_rack_s[0:3];
wire up_wack_s[0:3];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// dma interface
assign adc_valid_0 = 1'b1;
assign adc_valid_1 = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1];
up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1];
up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
end
end
// channel
axi_ad9652_channel #(
.IQSEL(0),
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dcfilter_data_out (adc_dcfilter_data_a_s),
.adc_dcfilter_data_in (adc_dcfilter_data_b_s),
.adc_iqcor_data (adc_data_0),
.adc_enable (adc_enable_0),
.up_adc_pn_err (up_status_pn_err_s[0]),
.up_adc_pn_oos (up_status_pn_oos_s[0]),
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel
axi_ad9652_channel #(
.IQSEL(1),
.CHID(1),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dcfilter_data_out (adc_dcfilter_data_b_s),
.adc_dcfilter_data_in (adc_dcfilter_data_a_s),
.adc_iqcor_data (adc_data_1),
.adc_enable (adc_enable_1),
.up_adc_pn_err (up_status_pn_err_s[1]),
.up_adc_pn_oos (up_status_pn_oos_s[1]),
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// main (device interface)
axi_ad9652_if #(
.PCORE_BUFTYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (up_adc_gpio_in),
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(17), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4_FUNCTIONAL_V
`define SKY130_FD_SC_HS__AND4_FUNCTIONAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4 (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4_FUNCTIONAL_V
|
`timescale 1ns/10ps
`include "pipeconnect.h"
/*
Notation:
_ low, 0
~ high, 1
/ posedge
\ negedge
. unknown,undetermined,unimportant
# valid data (held stable)
< changing
> --
*/
/*
Fasttarget presents the request address as the result data after one
cycle. Wait is never asserted.
WISHBONE - no wait states
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata _____________<#### D1 ####><#### D2 ####>____________________
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ####><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
wait _____________________________________________________________
readdata ___________________________<#### D1 ####><#### D2 ####>______
PIPECONNECT - some wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ####>.........................
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
wait _____________/~~~~~~~~~~~~\________________________________________________
readdata _________________________________________<#### D1 ####><#### D2 ####>______
*/
module fasttarget // PIPECONNECT, no wait
(input wire clk,
input wire rst,
input wire `REQ req,
output reg `RES res);
always @(posedge clk) begin
res`WAIT <= 0;
res`RD <= ~rst && req`R ? req`A : 0;
end
endmodule
/*
PIPECONNECT - 1 wait state
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#### A1 ##################><#### A2 ##################>...........
read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\/~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
wait _____________/~~~~~~~~~~~~\______________/~~~~~~~~~~~~\____________________
readdata _________________________________________<#### D1 ####>______________<#### D2 ####>______
_~_~_~_~_~_
.AAAABBBB..
_~~~~~~~~__
_~~__~~____
_____aa__bb
*/
module slowtarget // PIPECONNECT, 1 wait
(input wire clk,
input wire rst,
input wire `REQ req,
output wire `RES res);
reg [31:0] readData;
reg ready;
assign res`RD = readData;
assign res`WAIT = req`R & ~ready;
always @(posedge clk)
if (rst) begin
readData <= 0;
ready <= 0;
//$display("target in reset");
end else begin
readData <= ready ? req`A : 0;
ready <= req`R & ~ready;
//$display("target %d %d", ready, res`WAIT);
end
endmodule
/*
Simple master waits for a result before issuing new request
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock /~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ...<#####req 1###>...........................<#####req 2
read ___/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait ________________________________________________________
readdata ______________________<#############>___________________
*/
/*
Streaming master keeps one outstanding command
PIPECONNECT - no wait states
Request noticed by target
| Response captured by initiator
v v
clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
addr ........<#####req 1###>.............<#####req 2
read ________/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
wait _____________________________________________________________
readdata ___________________________<#############>___________________
*/
module initiator
(input wire clk,
input wire rst,
output reg `REQ req,
input wire `RES res);
reg [31:0] counter;
reg [31:0] dataExpect;
reg dataValid;
always @(posedge clk)
if (rst) begin
counter <= 0;
req <= 0;
dataValid <= 0;
dataExpect <= 0;
end else begin
dataValid <= req`R & ~res`WAIT;
if (dataValid) begin
if (dataExpect != res`RD)
$display("%6d Main got %x !!! BAD!", $time, res`RD);
// else
// $display("%6d Main got %x as expected", $time, res`RD);
end
if (~res`WAIT) begin
req`R <= 1;
req`A <= counter;
dataExpect <= req`A;
counter <= counter + 1;
//$display("%6d Main requests %x", $time, counter);
end
end
endmodule
module main();
reg rst, clk;
wire `REQ req;
wire `RES res;
wire [31:0] addr = req`A;
wire read = req`R;
wire wai = res`WAIT;
wire [31:0] data = res`RD;
initiator initiator (clk, rst, req, res);
slowtarget target(clk, rst, req, res);
always # 5 clk = ~clk;
initial begin
$monitor("%d%d %4d %x %d %d %x", rst, clk, $time, addr, read, wai, data);
clk = 1;
rst = 1;
#15 rst = 0;
#200 $finish;
end
endmodule
|
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