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// File: ./ex-target/Rectifier.v
// Generated by MyHDL 1.0dev
// Date: Mon Oct 5 14:11:09 2015
`timescale 1ns/10ps
module Rectifier (
y,
y_dx,
x
);
// Rectified linear unit (ReLU) and derivative model using fixbv type.
//
// :param y: return max(0, x) as fixbv
// :param y_dx: return d/dx max(0, x) as fixbv
// :param x: input value as fixbv
// :param leaky_val: factor for leaky ReLU, 0.0 without
// :param fix_min: fixbv min value
// :param fix_max: fixbv max value
// :param fix_res: fixbv resolution
output signed [15:0] y;
reg signed [15:0] y;
output signed [15:0] y_dx;
reg signed [15:0] y_dx;
input signed [15:0] x;
always @(x) begin: RECTIFIER_RELU
reg signed [16-1:0] zero;
reg signed [16-1:0] leaky;
if ((x > zero)) begin
y = x;
end
else begin
y = fixbv((leaky * x));
end
end
always @(x) begin: RECTIFIER_RELU_DX
reg signed [16-1:0] zero;
reg signed [16-1:0] leaky;
reg signed [16-1:0] one;
if ((x > zero)) begin
y_dx = one;
end
else begin
y_dx = leaky;
end
end
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module converts video in stream between color spaces on the DE *
* boards. *
* *
******************************************************************************/
module Raster_Laser_Projector_Video_In_video_csc (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IW = 23;
parameter OW = 23;
parameter EIW = 1;
parameter EOW = 1;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EIW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [OW: 0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [EOW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire transfer_data;
wire [OW: 0] converted_data;
wire converted_startofpacket;
wire converted_endofpacket;
wire [EOW:0] converted_empty;
wire converted_valid;
// Internal Registers
reg [IW: 0] data;
reg startofpacket;
reg endofpacket;
reg [EIW:0] empty;
reg valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'h0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 2'h0;
stream_out_valid <= 1'b0;
end
else if (transfer_data)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= converted_startofpacket;
stream_out_endofpacket <= converted_endofpacket;
stream_out_empty <= converted_empty;
stream_out_valid <= converted_valid;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
data <= 'h0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
else if (stream_in_ready)
begin
data <= stream_in_data;
startofpacket <= stream_in_startofpacket;
endofpacket <= stream_in_endofpacket;
empty <= stream_in_empty;
valid <= stream_in_valid;
end
else if (transfer_data)
begin
data <= 'b0;
startofpacket <= 1'b0;
endofpacket <= 1'b0;
empty <= 'h0;
valid <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_in_valid & (~valid | transfer_data);
// Internal Assignments
assign transfer_data = ~stream_out_valid |
(stream_out_ready & stream_out_valid);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_YCrCb_to_RGB_converter YCrCb_to_RGB (
// Inputs
.clk (clk),
.clk_en (transfer_data),
.reset (reset),
.Y (data[ 7: 0]),
.Cr (data[23:16]),
.Cb (data[15: 8]),
.stream_in_startofpacket (startofpacket),
.stream_in_endofpacket (endofpacket),
.stream_in_empty (empty),
.stream_in_valid (valid),
// Bidirectionals
// Outputs
.R (converted_data[23:16]),
.G (converted_data[15: 8]),
.B (converted_data[ 7: 0]),
.stream_out_startofpacket (converted_startofpacket),
.stream_out_endofpacket (converted_endofpacket),
.stream_out_empty (converted_empty),
.stream_out_valid (converted_valid)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:31:20 02/21/2015
// Design Name:
// Module Name: DecodeFSM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//TODO Add reset module that keeps almost everything (except the output clock) in reset until the sector pulses are detected (on speed)
module decodeFSM(clk, rst, currentRealBit, currentRealBitValid, sectorPulse, prog_empty, wordOut, wordOutReady, skipMFMBit, headerOut, headerOutStrobe, decode_state, beginWriteNow);
`include "FSMStates.v"
input clk; //Reception Clock (approximately 30.6us period) 65.536Mhz*2
input rst; //Positive Synchronous Reset
input currentRealBit;
input currentRealBitValid;
input sectorPulse;
input prog_empty;
output reg [16:0] wordOut; //Header+Data output
output reg wordOutReady; //Strobes when header/data word is ready
output reg skipMFMBit;
output reg headerOut;
output reg headerOutStrobe;
output reg [2:0] decode_state;
output reg beginWriteNow;
reg [11:0] bitCounter;
reg [5:0] headerbitCounter;
reg [5:0] preamblebitCounter;
always @(posedge clk) begin
if(rst | sectorPulse) begin
if(sectorPulse) begin
decode_state <= DSFM_PR1;
end else begin
decode_state <= DSFM_INIT;
end
bitCounter <= 12'b0;
preamblebitCounter <= 6'b0;
wordOut <= 17'b0;
headerOut <= 0;
headerOutStrobe <= 0;
headerbitCounter <= 0;
wordOutReady <= 0;
skipMFMBit <= 0;
beginWriteNow <= 0;
end else begin
skipMFMBit <= 0;
case (decode_state)
DSFM_INIT://Wait for the sector pulse
begin
end
DSFM_PR1:
if(currentRealBitValid) begin
if(preamblebitCounter == 31) begin //Check the data right before we're about to start using it, if it looks inverted, fix it
if(currentRealBit == 1) begin
skipMFMBit <= 1;
end
end
if(preamblebitCounter < 32) begin
preamblebitCounter <= preamblebitCounter + 1'b1; //hold off for a little bit
end else if(currentRealBit == 1) begin //now, wait for the sync bit
preamblebitCounter <= 6'b0;
if(!prog_empty) begin //If there's no room in the FPGA->Computer FIFO
decode_state <= DSFM_PO2;//Skip this sector
end else begin
decode_state <= DSFM_HDR;
end
end
end
DSFM_HDR:
begin
wordOutReady <= 0;
headerOutStrobe <= 0;
if(headerbitCounter < 6'd48) begin
if(currentRealBitValid) begin
headerbitCounter <= headerbitCounter + 1'b1;
headerOut <= currentRealBit;
headerOutStrobe <= 1;
wordOut <= {1'b0, currentRealBit, wordOut[15:1]};
if(headerbitCounter == 6'b001111) begin
wordOut <= {1'b1, currentRealBit, wordOut[15:1]};
end
if((headerbitCounter & 4'b1111) == 4'b1111) begin
wordOutReady <= 1;
end
end
end else begin
headerbitCounter <= 6'b0;
decode_state <= DSFM_PO1;
end
end
DSFM_PO1:
begin
if(currentRealBitValid) begin
if(headerbitCounter < 16) begin
headerbitCounter <= headerbitCounter + 1'b1;
end else begin
headerbitCounter <= 6'b0;
beginWriteNow <= 1;
decode_state <= DSFM_IT_IDLE;
end
end
end
DSFM_IT_IDLE: //If we are going to write, now is the time
begin
beginWriteNow <= 0;
decode_state <= DSFM_PR2;
end
DSFM_PR2:
if(currentRealBitValid) begin
if(preamblebitCounter == 31) begin //Check the data right before we're about to start using it, if it looks inverted, fix it
if(currentRealBit == 1) begin
skipMFMBit <= 1;
end
end
if(preamblebitCounter < 32) begin
preamblebitCounter <= preamblebitCounter + 1'b1; //hold off for a little bit
end else if(currentRealBit == 1) begin //now, wait for the sync bit
preamblebitCounter <= 6'b0;
decode_state <= DSFM_DATA;
end
end
DSFM_DATA:
begin
wordOutReady <= 0;
if(bitCounter < 12'd2064) begin
if(currentRealBitValid) begin//This does require the first bit of the postable in order to exit this state
bitCounter <= bitCounter + 1'b1;
wordOut <= {1'b0, currentRealBit, wordOut[15:1]};
if((bitCounter & 4'b1111) == 4'b1111) begin //Tools don't support mod for some reason
wordOutReady <= 1;
end
end
end else begin
bitCounter <= 12'b0;
decode_state <= DSFM_PO2;
end
end
DSFM_PO2: //hold here until sector pulse
begin
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:31:50 03/07/2016
// Design Name: mult4
// Module Name: C:/XilinxP/Practica1/mult4_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mult4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mult4_test;
// Inputs
reg x0;
reg x1;
reg x2;
reg x3;
reg y0;
reg y1;
reg y2;
reg y3;
// Outputs
wire z0;
wire z1;
wire z2;
wire z3;
wire z4;
wire z5;
wire z6;
wire z7;
// Instantiate the Unit Under Test (UUT)
mult4 uut (
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.z0(z0),
.z1(z1),
.z2(z2),
.z3(z3),
.z4(z4),
.z5(z5),
.z6(z6),
.z7(z7)
);
initial begin
// Initialize Inputs
x0 = 0;
x1 = 0;
x2 = 0;
x3 = 0;
y0 = 0;
y1 = 0;
y2 = 0;
y3 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
x0 = 1; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 0; //1011 * 0101
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 1; //1010 * 1101
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 0; y1 = 1; y2 = 1; y3 = 1; //1111 * 1110
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 1; y1 = 1; y2 = 1; y3 = 1; //1111 * 1111
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 0; x2 = 0; x3 = 1; y0 = 0; y1 = 0; y2 = 1; y3 = 0; //1000 * 0100
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 0; //1010 * 0001
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 0; y1 = 0; y2 = 0; y3 = 0; //1111 * 0000
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 1; x3 = 0; y0 = 1; y1 = 0; y2 = 0; y3 = 1; //0110 * 1001
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 11:22:00 10/24/2016
// Module Name: I_DECODE_tb
// Project Name: MIPS
// Description: Tests the MIPS ID (DECODE) pipeline stage.
//
// Dependencies: I_DECODE.v
//
////////////////////////////////////////////////////////////////////////////////
module I_DECODE_tb;
// Inputs
reg clk;
reg RegWrite;
reg [31:0] IF_ID_Instr;
reg [31:0] IF_ID_NPC;
reg [4:0] MEM_WB_Writereg;
reg [31:0] MEM_WB_Writedata;
// Outputs
wire [1:0] WB;
wire [2:0] M;
wire [3:0] EX;
wire [31:0] NPC;
wire [31:0] rdata1out;
wire [31:0] rdata2out;
wire [31:0] IR;
wire [4:0] instrout_2016;
wire [4:0] instrout_1511;
// Instantiate the I_DECODE module
I_DECODE decode(.clk(clk), .RegWrite(RegWrite), .IF_ID_Instr(IF_ID_Instr),
.IF_ID_NPC(IF_ID_NPC), .MEM_WB_Writereg(MEM_WB_Writereg),
.MEM_WB_Writedata(MEM_WB_Writedata), .WB(WB), .M(M), .EX(EX),
.NPC(NPC), .rdata1out(rdata1out), .rdata2out(rdata2out),
.IR(IR), .instrout_2016(instrout_2016), .instrout_1511(instrout_1511));
initial begin
// Initialize Inputs
clk = 1;
RegWrite = 0;
IF_ID_Instr = 0;
IF_ID_NPC = 0;
MEM_WB_Writereg = 0;
MEM_WB_Writedata = 0;
// Wait 100 ns for global reset to finish
$display("Initializing and waiting for reset...");
#100;
// Write test data to the first nine locations
$display("Writing data...");
RegWrite = 1;
MEM_WB_Writedata = 32'h002300AA;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h10654321;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h00100022;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h8C123456;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h8F123456;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'hAD654321;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h13012345;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'hAC654321;
#20;
MEM_WB_Writereg = MEM_WB_Writereg + 1;
MEM_WB_Writedata = 32'h12012345;
// Read test data from the nine test locations.
// rs will read evens and rt will read odds until the last register,
// where both will read the ninth register together.
#20;
$display("Reading data...");
RegWrite = 0;
IF_ID_instr = 32'b00000000000000010000000000000000;
#20
IF_ID_instr = 32'b00000000010000110000000000000000;
#20
IF_ID_instr = 32'b00000000100001010000000000000000;
#20
IF_ID_instr = 32'b00000000110001110000000000000000;
#20
IF_ID_instr = 32'b00000001000010000000000000000000;
#20 $finish;
end
initial begin
$monitor("INPUTS: IF_ID_instr = %b | IF_ID_NPC = %h | RegWrite = %d | ",
IF_ID_instr, IF_ID_NPC, RegWrite,
"MEM_WB_Writereg = %d | MEM_WB_Writedata = %h | ",
MEM_WB_Writereg, MEM_WB_Writedata,
"OUTPUTS: WB = %b | M = %b | EX = %b | NPC = %h | ",
WB, M, EX, NPC,
"rdata1out = %h | rdata2out = %h | IR = %d | ",
rdata1out, rdata2out, IR,
"instrout_2016 = %d | instrout_1511 = %d",
instrout_2016, instrout_1511);
forever begin
#10 clk = ~clk;
end
end
endmodule
|
//----------------------------------------------------------------
//-- Inicializador
//-- (c) BQ. August 2015. Written by Juan Gonzalez (obijuan)
//-- GPL license
//----------------------------------------------------------------
//-- Generacion de una señal escalo (0 -> 1) para inicializar
//-- circuitos digitales
//----------------------------------------------------------------
//-- Version optimizada
//-- Entrada: Señal de reloj
//-- Salida: Señal escalón de inicialización
module init(input wire clk, output ini);
//-- Inicializar la salida a 0 (se pone para que funcione en simulación)
//-- En síntesis siempre estará a cero con independencia del valor que pongamos
reg ini = 0;
//-- En cada flanco de subida se saca un "1" por la salida
always @(posedge(clk))
ini <= 1;
endmodule
/*
//-- Implementacion natural
module init(input wire clk, output wire ini);
wire din;
reg dout = 0;
//-- Registro
always @(posedge(clk))
dout <= din;
//-- Entrada conectadad a 1
assign din = 1;
//-- Conectar la salida
assign ini = dout;
endmodule
*/
|
//bug844
module device(
input clk,
output logic [7:0] Q, out0,
output logic pass, fail
input [7:0] D, in0,in1 );
enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
logic ready, next_ready;
logic next_pass, next_fail;
always_ff @(posedge clk, negedge rstn)
if (!rstn) begin
state <= IDLE;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
fail <= 1'h0;
pass <= 1'h0;
ready <= 1'h0;
// End of automatics
end
else begin
state <= next_state;
ready <= next_ready;
pass <= next_pass;
fail <= next_fail;
end
always @* begin
if (!ready) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
out0 = 8'h0;
// End of automatics
end
else begin
out0 = sel ? in1 : in0;
end
end
always_comb begin
next_state = state;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
next_fail = 1'h0;
next_pass = 1'h0;
next_ready = 1'h0;
// End of automatics
case (state)
IDLE : begin
// stuff ...
end
/* Other states */
PASS: begin
next_state = IDLE;
// stuff ...
next_pass = 1'b1;
next_ready = 1'b1;
end
FAIL: begin
next_state = IDLE;
// stuff ...
next_fail = 1'b1;
end
endcase
end
always_latch begin
if (!rstn) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
Q <= 8'h0;
// End of automatics
end
else if (clk) begin
Q <= D;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:24:22 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474,
n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
DP_OP_15J31_123_3372_n8, DP_OP_15J31_123_3372_n7,
DP_OP_15J31_123_3372_n6, DP_OP_15J31_123_3372_n5,
DP_OP_15J31_123_3372_n4, intadd_28_B_12_, intadd_28_B_11_,
intadd_28_B_10_, intadd_28_B_9_, intadd_28_B_8_, intadd_28_B_7_,
intadd_28_B_6_, intadd_28_B_5_, intadd_28_B_4_, intadd_28_B_3_,
intadd_28_B_2_, intadd_28_B_1_, intadd_28_B_0_, intadd_28_CI,
intadd_28_SUM_12_, intadd_28_SUM_11_, intadd_28_SUM_10_,
intadd_28_SUM_9_, intadd_28_SUM_8_, intadd_28_SUM_7_,
intadd_28_SUM_6_, intadd_28_SUM_5_, intadd_28_SUM_4_,
intadd_28_SUM_3_, intadd_28_SUM_2_, intadd_28_SUM_1_,
intadd_28_SUM_0_, intadd_28_n13, intadd_28_n12, intadd_28_n11,
intadd_28_n10, intadd_28_n9, intadd_28_n8, intadd_28_n7, intadd_28_n6,
intadd_28_n5, intadd_28_n4, intadd_28_n3, intadd_28_n2, intadd_28_n1,
intadd_29_A_2_, intadd_29_A_1_, intadd_29_B_2_, intadd_29_B_1_,
intadd_29_B_0_, intadd_29_CI, intadd_29_SUM_2_, intadd_29_SUM_1_,
intadd_29_SUM_0_, intadd_29_n3, intadd_29_n2, intadd_29_n1,
intadd_30_A_2_, intadd_30_A_1_, intadd_30_B_1_, intadd_30_B_0_,
intadd_30_CI, intadd_30_SUM_2_, intadd_30_SUM_1_, intadd_30_SUM_0_,
intadd_30_n3, intadd_30_n2, intadd_30_n1, n873, n874, n875, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1323, n1324, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1351, n1352, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1576, n1577, n1578, n1579, n1581, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596,
n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1605, n1606, n1607;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:1] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [24:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1578), .QN(
n889) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1579),
.QN(n879) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1581),
.QN(n880) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1577),
.QN(n881) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1576), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1579), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1581),
.Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n875), .QN(n885) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1592),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n875), .Q(
Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1579),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1582),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n874), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1584), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1601), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1588), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1589), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1592), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1585), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n874), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n922), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n875), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n875), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1582), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n922), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n875), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n875), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1579), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1581), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1577), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1576), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1579), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1581), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1583), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1578), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1577), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n874), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1585), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1592), .QN(n890)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1589), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n874), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1601), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1588), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1588), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1584), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n874), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1585), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1584), .Q(
DMP_SFG[2]), .QN(n1559) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1585), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n874), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1597), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1587), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1597), .Q(
DMP_SFG[6]), .QN(n1560) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1587), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1587), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1587), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1587), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1587), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1586), .Q(
DMP_SFG[10]), .QN(n1517) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1585), .Q(
DMP_SFG[11]), .QN(n1516) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1588), .Q(
DMP_SFG[12]), .QN(n1522) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1584), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n874), .Q(
DMP_SFG[13]), .QN(n1521) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1585), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1592), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1589), .Q(
DMP_SFG[14]), .QN(n1525) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n874), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1584), .Q(
DMP_SFG[15]), .QN(n1544) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1588), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1585), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1592), .Q(
DMP_SFG[16]), .QN(n1543) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1589), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n874), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1601), .Q(
DMP_SFG[17]), .QN(n1555) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1584), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n874), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1585), .Q(
DMP_SFG[18]), .QN(n1554) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1592), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1589), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1586), .Q(
DMP_SFG[19]), .QN(n1563) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n874), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1602), .Q(
DMP_SFG[20]), .QN(n1562) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1602), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1597), .Q(
DMP_SFG[21]), .QN(n1573) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1587), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n874), .Q(
DMP_SFG[22]), .QN(n1572) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1587), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1587), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1602), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1586), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1590), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n874), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1590), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n874), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1590), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1586), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1590), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1586), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1594), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1595), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1598), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1591), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n921), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n921), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1594), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1598), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1591), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n921), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1579), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1588), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1601), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1584), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1588), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1585), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1592), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1589), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n874), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1601), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1592), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1585), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1589), .QN(
n892) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1601), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1579), .QN(
n891) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1577), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n874), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1602), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1584), .QN(
n887) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1599), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1596), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1600),
.QN(n888) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1593), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1599), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1596), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1591), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n921), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1594),
.QN(n886) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1589), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1591), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1595), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1601), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1578), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1583), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1596), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1600), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1593), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1599), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1596), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n550), .CK(clk), .RN(n1600), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1593), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1576), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1599), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1596), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1600), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1584), .Q(
final_result_ieee[31]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n874), .Q(
LZD_output_NRM2_EW[3]), .QN(n1526) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1586), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1597), .Q(
LZD_output_NRM2_EW[2]), .QN(n1523) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1586), .Q(
LZD_output_NRM2_EW[1]), .QN(n1518) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1597), .Q(
LZD_output_NRM2_EW[4]), .QN(n1527) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n921), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1598), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1591), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1576), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n921), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1594), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1595), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1598), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1591), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1585), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1593), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1601), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1589), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1599), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1596), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1600), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1593), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1585), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1599), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1596), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1600), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1593), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1600), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[0]), .QN(n911) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[1]), .QN(n912) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[2]), .QN(n913) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[3]), .QN(n917) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[4]), .QN(n918) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[6]), .QN(n915) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[7]), .QN(n914) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1593), .Q(
DmP_mant_SFG_SWR[8]), .QN(n907) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1601), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1584), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n874), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[22]), .QN(n908) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[23]), .QN(n909) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[24]), .QN(n910) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n874), .Q(
DmP_mant_SFG_SWR[25]) );
CMPR32X2TS intadd_28_U14 ( .A(n1517), .B(intadd_28_B_0_), .C(intadd_28_CI),
.CO(intadd_28_n13), .S(intadd_28_SUM_0_) );
CMPR32X2TS intadd_28_U13 ( .A(n1516), .B(intadd_28_B_1_), .C(intadd_28_n13),
.CO(intadd_28_n12), .S(intadd_28_SUM_1_) );
CMPR32X2TS intadd_28_U12 ( .A(n1522), .B(intadd_28_B_2_), .C(intadd_28_n12),
.CO(intadd_28_n11), .S(intadd_28_SUM_2_) );
CMPR32X2TS intadd_28_U11 ( .A(n1521), .B(intadd_28_B_3_), .C(intadd_28_n11),
.CO(intadd_28_n10), .S(intadd_28_SUM_3_) );
CMPR32X2TS intadd_28_U10 ( .A(n1525), .B(intadd_28_B_4_), .C(intadd_28_n10),
.CO(intadd_28_n9), .S(intadd_28_SUM_4_) );
CMPR32X2TS intadd_28_U9 ( .A(n1544), .B(intadd_28_B_5_), .C(intadd_28_n9),
.CO(intadd_28_n8), .S(intadd_28_SUM_5_) );
CMPR32X2TS intadd_28_U8 ( .A(n1543), .B(intadd_28_B_6_), .C(intadd_28_n8),
.CO(intadd_28_n7), .S(intadd_28_SUM_6_) );
CMPR32X2TS intadd_28_U7 ( .A(n1555), .B(intadd_28_B_7_), .C(intadd_28_n7),
.CO(intadd_28_n6), .S(intadd_28_SUM_7_) );
CMPR32X2TS intadd_28_U6 ( .A(n1554), .B(intadd_28_B_8_), .C(intadd_28_n6),
.CO(intadd_28_n5), .S(intadd_28_SUM_8_) );
CMPR32X2TS intadd_28_U5 ( .A(n1563), .B(intadd_28_B_9_), .C(intadd_28_n5),
.CO(intadd_28_n4), .S(intadd_28_SUM_9_) );
CMPR32X2TS intadd_28_U4 ( .A(n1562), .B(intadd_28_B_10_), .C(intadd_28_n4),
.CO(intadd_28_n3), .S(intadd_28_SUM_10_) );
CMPR32X2TS intadd_28_U3 ( .A(n1573), .B(intadd_28_B_11_), .C(intadd_28_n3),
.CO(intadd_28_n2), .S(intadd_28_SUM_11_) );
CMPR32X2TS intadd_28_U2 ( .A(n1572), .B(intadd_28_B_12_), .C(intadd_28_n2),
.CO(intadd_28_n1), .S(intadd_28_SUM_12_) );
CMPR32X2TS intadd_29_U4 ( .A(n1560), .B(intadd_29_B_0_), .C(intadd_29_CI),
.CO(intadd_29_n3), .S(intadd_29_SUM_0_) );
CMPR32X2TS intadd_29_U3 ( .A(intadd_29_A_1_), .B(intadd_29_B_1_), .C(
intadd_29_n3), .CO(intadd_29_n2), .S(intadd_29_SUM_1_) );
CMPR32X2TS intadd_29_U2 ( .A(intadd_29_A_2_), .B(intadd_29_B_2_), .C(
intadd_29_n2), .CO(intadd_29_n1), .S(intadd_29_SUM_2_) );
CMPR32X2TS intadd_30_U4 ( .A(n1559), .B(intadd_30_B_0_), .C(intadd_30_CI),
.CO(intadd_30_n3), .S(intadd_30_SUM_0_) );
CMPR32X2TS intadd_30_U3 ( .A(intadd_30_A_1_), .B(intadd_30_B_1_), .C(
intadd_30_n3), .CO(intadd_30_n2), .S(intadd_30_SUM_1_) );
CMPR32X2TS intadd_30_U2 ( .A(intadd_30_A_2_), .B(n895), .C(intadd_30_n2),
.CO(intadd_30_n1), .S(intadd_30_SUM_2_) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1593), .Q(
OP_FLAG_SFG), .QN(n1493) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1597), .Q(
Data_array_SWR[10]), .QN(n1570) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1591), .Q(
DmP_EXP_EWSW[25]), .QN(n1569) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1585), .Q(
DMP_EXP_EWSW[26]), .QN(n1568) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1577),
.Q(intDX_EWSW[24]), .QN(n1567) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n874), .Q(
Data_array_SWR[13]), .QN(n1566) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1601), .Q(
Data_array_SWR[11]), .QN(n1565) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[26]), .QN(n1564) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n921), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1561) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1576), .Q(
Data_array_SWR[22]), .QN(n1558) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1588), .Q(
DMP_EXP_EWSW[25]), .QN(n1557) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1556) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1553) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1585),
.Q(intDY_EWSW[18]), .QN(n1552) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1581),
.Q(intDY_EWSW[30]), .QN(n1551) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[26]), .QN(n1550) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1587), .Q(
intDY_EWSW[8]), .QN(n1549) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1578), .Q(
intDY_EWSW[1]), .QN(n1548) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n875), .Q(
intDY_EWSW[17]), .QN(n1547) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1577), .Q(
intDY_EWSW[0]), .QN(n1546) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[25]), .QN(n1545) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1597), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1542) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n874), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1541) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1583),
.Q(intDY_EWSW[27]), .QN(n1540) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n922), .Q(
intDY_EWSW[23]), .QN(n1539) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1578),
.Q(intDY_EWSW[28]), .QN(n1538) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n875), .Q(
intDY_EWSW[7]), .QN(n1537) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n875), .Q(
intDY_EWSW[14]), .QN(n1535) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n874), .Q(
intDY_EWSW[12]), .QN(n1534) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n875), .Q(
intDY_EWSW[4]), .QN(n1533) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1583), .Q(
intDY_EWSW[2]), .QN(n1532) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[13]), .QN(n1530) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1582), .Q(
intDY_EWSW[9]), .QN(n1529) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1581), .Q(
intDY_EWSW[6]), .QN(n1528) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1578), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1524) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[28]), .QN(n1520) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[16]), .QN(n1519) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1602), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1515) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1579), .Q(
intDX_EWSW[6]), .QN(n1514) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1513) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1576), .Q(
shift_value_SHT2_EWR[3]), .QN(n1512) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1586), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1511) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n922), .Q(
shift_value_SHT2_EWR[4]), .QN(n1510) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1576), .Q(
intDX_EWSW[5]), .QN(n1509) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1508) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1598), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1507) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1594), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1506) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1576), .Q(
n1488), .QN(n1571) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[26]), .QN(n1505) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[25]), .QN(n1504) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1503) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1584), .Q(
DMP_EXP_EWSW[24]), .QN(n1502) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1598), .Q(
DmP_EXP_EWSW[24]), .QN(n1501) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1579),
.Q(intDY_EWSW[29]), .QN(n1500) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[19]), .QN(n1499) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n875), .Q(
intDY_EWSW[22]), .QN(n1498) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1587),
.Q(intDY_EWSW[16]), .QN(n1497) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n922), .Q(
intDY_EWSW[5]), .QN(n1496) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1579), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1495) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1581), .Q(
intDX_EWSW[7]), .QN(n1494) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1578), .Q(
intDX_EWSW[4]), .QN(n1492) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n921), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1491) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n921), .Q(
Raw_mant_NRM_SWR[15]), .QN(n1490) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1598), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1489) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n875), .Q(
intDY_EWSW[24]), .QN(n1487) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1486) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n874), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1485) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1484) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1587), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1483) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1591), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1482) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1591), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1481) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1480) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1479) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n874), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1478) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1477) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1576),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1583), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1577), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1576), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1579), .Q(
Data_array_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1594), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1578), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1581), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1576), .Q(
intDX_EWSW[9]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1581), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n875), .Q(
Data_array_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1595), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1578), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1577),
.Q(intDX_EWSW[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1583),
.Q(intDX_EWSW[27]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1577), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1597), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n922), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1589), .Q(
Data_array_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1590), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n921), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n875), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n922), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n875), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1586), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1597), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1588), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1577),
.Q(intDX_EWSW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1594), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1595), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1598), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1583), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1599), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1595), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1596), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n875), .Q(
intDY_EWSW[10]), .QN(n878) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1593), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1581), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1591), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1599), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1596), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n921), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1600), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1585), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1592), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1589), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1601), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1585), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1592), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1588), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1601), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n875), .Q(
Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n875), .Q(
intDY_EWSW[15]), .QN(n1607) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1582),
.Q(intDY_EWSW[20]), .QN(n1536) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n1581),
.Q(intDY_EWSW[21]), .QN(n1531) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1592), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1586), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1586), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1587), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1579),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1581),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1576),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n922), .Q(
intDY_EWSW[3]), .QN(n1605) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1578),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n875), .Q(
intDY_EWSW[11]), .QN(n1606) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1579),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n875), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1583), .Q(
Data_array_SWR[20]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n875), .Q(
Data_array_SWR[16]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n922), .Q(
Data_array_SWR[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n921), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[5]), .QN(n916) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[9]), .QN(n877) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1602), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n875), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1582), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n922), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n875), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1594), .Q(
DmP_EXP_EWSW[27]) );
ADDFX1TS DP_OP_15J31_123_3372_U8 ( .A(n1518), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J31_123_3372_n8), .CO(DP_OP_15J31_123_3372_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J31_123_3372_U7 ( .A(n1523), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J31_123_3372_n7), .CO(DP_OP_15J31_123_3372_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J31_123_3372_U6 ( .A(n1526), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J31_123_3372_n6), .CO(DP_OP_15J31_123_3372_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J31_123_3372_U5 ( .A(n1527), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J31_123_3372_n5), .CO(DP_OP_15J31_123_3372_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1577), .Q(
Shift_reg_FLAGS_7[1]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1583), .Q(
busy), .QN(n1574) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1583), .Q(
Shift_reg_FLAGS_7_6), .QN(n919) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1576), .Q(
Shift_reg_FLAGS_7[0]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1583), .Q(
n873), .QN(n1603) );
BUFX4TS U897 ( .A(n921), .Y(n922) );
NAND2X4TS U898 ( .A(n1150), .B(n1280), .Y(n1135) );
CLKINVX6TS U899 ( .A(rst), .Y(n921) );
AOI222X4TS U900 ( .A0(Data_array_SWR[23]), .A1(n1386), .B0(
Data_array_SWR[19]), .B1(n1401), .C0(Data_array_SWR[15]), .C1(n1400),
.Y(n1431) );
AOI211X2TS U901 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1116), .B0(n1254), .C0(
n1115), .Y(n1131) );
OAI222X1TS U902 ( .A0(n1565), .A1(n1297), .B0(n1288), .B1(n1286), .C0(n1147),
.C1(n1285), .Y(n783) );
OAI222X1TS U903 ( .A0(n1297), .A1(n1566), .B0(n1288), .B1(n1285), .C0(n1147),
.C1(n1278), .Y(n785) );
OAI222X1TS U904 ( .A0(n1558), .A1(n1297), .B0(n1288), .B1(n1275), .C0(n1147),
.C1(n1274), .Y(n794) );
CLKINVX6TS U905 ( .A(n1291), .Y(n1147) );
NOR2XLTS U906 ( .A(n1150), .B(n1192), .Y(n1151) );
CLKINVX6TS U907 ( .A(n1282), .Y(n1117) );
NAND3XLTS U908 ( .A(n1123), .B(n1108), .C(n1243), .Y(n1254) );
BUFX4TS U909 ( .A(n996), .Y(n1012) );
NOR2X4TS U910 ( .A(n995), .B(n919), .Y(n996) );
AND2X4TS U911 ( .A(Shift_reg_FLAGS_7_6), .B(n995), .Y(n1087) );
CLKINVX3TS U912 ( .A(n1269), .Y(n1266) );
CLKINVX3TS U913 ( .A(n1267), .Y(n1272) );
BUFX6TS U914 ( .A(n1321), .Y(n1454) );
NOR2X6TS U915 ( .A(n1473), .B(n1411), .Y(n1364) );
BUFX6TS U916 ( .A(n1581), .Y(n874) );
INVX6TS U917 ( .A(Shift_reg_FLAGS_7_6), .Y(n997) );
NOR2X6TS U918 ( .A(shift_value_SHT2_EWR[4]), .B(n1380), .Y(n1363) );
NAND3XLTS U919 ( .A(n1507), .B(n1490), .C(n1482), .Y(n1240) );
BUFX6TS U920 ( .A(n922), .Y(n875) );
NAND2BXLTS U921 ( .AN(n906), .B(intDY_EWSW[2]), .Y(n945) );
NAND2BXLTS U922 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n979) );
NAND2BXLTS U923 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n933) );
NAND2BXLTS U924 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n958) );
OAI2BB2XLTS U925 ( .B0(intDY_EWSW[14]), .B1(n964), .A0N(intDX_EWSW[15]),
.A1N(n1607), .Y(n965) );
NAND2BXLTS U926 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n954) );
NAND2BXLTS U927 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n973) );
INVX2TS U928 ( .A(n882), .Y(n895) );
AO22XLTS U929 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n1354), .B0(n1351), .B1(n915),
.Y(n882) );
AOI222X4TS U930 ( .A0(Data_array_SWR[13]), .A1(n1363), .B0(
Data_array_SWR[21]), .B1(n1427), .C0(Data_array_SWR[17]), .C1(n1426),
.Y(n1376) );
AOI222X4TS U931 ( .A0(Data_array_SWR[22]), .A1(n1427), .B0(
Data_array_SWR[18]), .B1(n1426), .C0(Data_array_SWR[14]), .C1(n1363),
.Y(n1372) );
AOI222X4TS U932 ( .A0(Data_array_SWR[23]), .A1(n1427), .B0(
Data_array_SWR[19]), .B1(n1426), .C0(Data_array_SWR[15]), .C1(n1363),
.Y(n1368) );
AOI222X4TS U933 ( .A0(Data_array_SWR[20]), .A1(n1426), .B0(
Data_array_SWR[16]), .B1(n1363), .C0(Data_array_SWR[24]), .C1(n1427),
.Y(n1369) );
NAND2BXLTS U934 ( .AN(n1256), .B(n928), .Y(n931) );
AOI222X1TS U935 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1279), .C1(n897), .Y(n1161) );
AOI222X1TS U936 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1279), .C1(DmP_mant_SHT1_SW[3]), .Y(n1154)
);
AOI222X1TS U937 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1279), .C1(DmP_mant_SHT1_SW[8]), .Y(n1168)
);
AOI222X1TS U938 ( .A0(n1216), .A1(DMP_SFG[1]), .B0(n1216), .B1(n893), .C0(
DMP_SFG[1]), .C1(n893), .Y(intadd_30_CI) );
AOI222X4TS U939 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1279), .C1(DmP_mant_SHT1_SW[17]), .Y(n1184) );
AOI222X1TS U940 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1117), .B0(n1284), .B1(n900), .C0(n1279), .C1(DmP_mant_SHT1_SW[20]), .Y(n1211) );
AOI222X1TS U941 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1279), .C1(DmP_mant_SHT1_SW[18]), .Y(n1215) );
AOI222X1TS U942 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1279), .C1(DmP_mant_SHT1_SW[7]), .Y(n1179)
);
AOI222X1TS U943 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1117), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1279), .C0(n1284), .C1(
DmP_mant_SHT1_SW[13]), .Y(n1209) );
AOI222X1TS U944 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1279), .C1(DmP_mant_SHT1_SW[16]), .Y(n1206) );
AOI211X1TS U945 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n1336), .B0(n1279), .C0(
n1193), .Y(n1273) );
AOI222X4TS U946 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1187), .C1(DmP_mant_SHT1_SW[21]), .Y(n1194) );
AO22XLTS U947 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n1351), .B0(n1354), .B1(n914),
.Y(n883) );
AO22XLTS U948 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n1351), .B0(n1354), .B1(n917),
.Y(n884) );
INVX4TS U949 ( .A(n1469), .Y(n1476) );
AOI222X1TS U950 ( .A0(n1388), .A1(n1473), .B0(Data_array_SWR[8]), .B1(n1435),
.C0(n1387), .C1(n1408), .Y(n1458) );
AOI222X1TS U951 ( .A0(n1388), .A1(n1434), .B0(Data_array_SWR[8]), .B1(n1364),
.C0(n1387), .C1(n1407), .Y(n1443) );
AOI222X1TS U952 ( .A0(n1383), .A1(n1473), .B0(Data_array_SWR[9]), .B1(n1435),
.C0(n1382), .C1(n1408), .Y(n1456) );
AOI222X1TS U953 ( .A0(n1383), .A1(n1434), .B0(Data_array_SWR[9]), .B1(n1364),
.C0(n1382), .C1(n1407), .Y(n1444) );
AOI222X1TS U954 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1117), .B0(n1284), .B1(
n899), .C0(n1279), .C1(DmP_mant_SHT1_SW[10]), .Y(n1205) );
AOI222X1TS U955 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1117), .B0(n1284), .B1(
n898), .C0(n1279), .C1(DmP_mant_SHT1_SW[12]), .Y(n1202) );
AO22XLTS U956 ( .A0(n1267), .A1(Data_X[19]), .B0(n1266), .B1(intDX_EWSW[19]),
.Y(n843) );
AO22XLTS U957 ( .A0(n1451), .A1(DMP_SHT2_EWSW[0]), .B0(n1321), .B1(
DMP_SFG[0]), .Y(n717) );
AO22XLTS U958 ( .A0(n1329), .A1(DmP_EXP_EWSW[0]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U959 ( .A0(n1329), .A1(DmP_EXP_EWSW[1]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AO22XLTS U960 ( .A0(n1329), .A1(DmP_EXP_EWSW[2]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U961 ( .A0(n1329), .A1(DmP_EXP_EWSW[6]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U962 ( .A0(n1334), .A1(DmP_EXP_EWSW[15]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U963 ( .A0(n1329), .A1(DmP_EXP_EWSW[10]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U964 ( .A0(n1329), .A1(DmP_EXP_EWSW[12]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
AO22XLTS U965 ( .A0(n1329), .A1(DmP_EXP_EWSW[18]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U966 ( .A0(n1334), .A1(DmP_EXP_EWSW[13]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U967 ( .A0(n1329), .A1(DmP_EXP_EWSW[8]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U968 ( .A0(n1334), .A1(DmP_EXP_EWSW[21]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U969 ( .A0(n1329), .A1(DmP_EXP_EWSW[3]), .B0(n1571), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
AO22XLTS U970 ( .A0(n1329), .A1(DmP_EXP_EWSW[7]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AO22XLTS U971 ( .A0(n1329), .A1(DmP_EXP_EWSW[16]), .B0(n1331), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U972 ( .A0(n1334), .A1(DmP_EXP_EWSW[20]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U973 ( .A0(n1263), .A1(n1359), .B0(n1264), .B1(n896), .Y(n865) );
AO22XLTS U974 ( .A0(n1270), .A1(Data_X[31]), .B0(n1268), .B1(intDX_EWSW[31]),
.Y(n831) );
AO22XLTS U975 ( .A0(n1451), .A1(DMP_SHT2_EWSW[1]), .B0(n1469), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U976 ( .A0(n1329), .A1(DmP_EXP_EWSW[11]), .B0(n1571), .B1(n898),
.Y(n587) );
AO22XLTS U977 ( .A0(n1329), .A1(DmP_EXP_EWSW[9]), .B0(n1323), .B1(n899), .Y(
n591) );
AO22XLTS U978 ( .A0(n1329), .A1(DmP_EXP_EWSW[5]), .B0(n1333), .B1(n901), .Y(
n599) );
AO22XLTS U979 ( .A0(n1329), .A1(DmP_EXP_EWSW[4]), .B0(n1331), .B1(n897), .Y(
n601) );
AO22XLTS U980 ( .A0(n1264), .A1(busy), .B0(n1263), .B1(n896), .Y(n866) );
OAI222X1TS U981 ( .A0(n1570), .A1(n1297), .B0(n1288), .B1(n1287), .C0(n1147),
.C1(n1286), .Y(n781) );
AOI221X1TS U982 ( .A0(n1550), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]), .B1(
n1540), .C0(n1033), .Y(n1037) );
OAI21X2TS U983 ( .A0(intDX_EWSW[26]), .A1(n1550), .B0(n933), .Y(n1033) );
NOR2BX2TS U984 ( .AN(n1252), .B(n1251), .Y(n1112) );
NAND4XLTS U985 ( .A(n1489), .B(n1481), .C(n1477), .D(n1506), .Y(n1251) );
BUFX4TS U986 ( .A(n1594), .Y(n1589) );
OAI211XLTS U987 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1107), .B0(n1247), .C0(
n1513), .Y(n1108) );
NOR2X2TS U988 ( .A(Raw_mant_NRM_SWR[6]), .B(n1106), .Y(n1247) );
BUFX4TS U989 ( .A(n1595), .Y(n1592) );
BUFX4TS U990 ( .A(n1598), .Y(n1585) );
BUFX4TS U991 ( .A(n1591), .Y(n1601) );
BUFX4TS U992 ( .A(n1590), .Y(n1588) );
BUFX6TS U993 ( .A(n1321), .Y(n1469) );
CLKINVX6TS U994 ( .A(n1323), .Y(n1332) );
BUFX6TS U995 ( .A(n1571), .Y(n1331) );
BUFX4TS U996 ( .A(n1583), .Y(n1590) );
BUFX4TS U997 ( .A(n1576), .Y(n1586) );
BUFX4TS U998 ( .A(n1579), .Y(n1587) );
BUFX4TS U999 ( .A(n1592), .Y(n1597) );
BUFX4TS U1000 ( .A(n875), .Y(n1583) );
INVX2TS U1001 ( .A(n884), .Y(n893) );
INVX2TS U1002 ( .A(n883), .Y(n894) );
NOR2X2TS U1003 ( .A(Raw_mant_NRM_SWR[13]), .B(n1241), .Y(n1122) );
BUFX6TS U1004 ( .A(n920), .Y(n1270) );
BUFX4TS U1005 ( .A(n920), .Y(n1267) );
BUFX4TS U1006 ( .A(n920), .Y(n1269) );
BUFX4TS U1007 ( .A(n1582), .Y(n1581) );
BUFX4TS U1008 ( .A(n875), .Y(n1579) );
BUFX4TS U1009 ( .A(n922), .Y(n1576) );
BUFX4TS U1010 ( .A(n1588), .Y(n1578) );
NOR2X4TS U1011 ( .A(shift_value_SHT2_EWR[4]), .B(n1473), .Y(n1408) );
BUFX6TS U1012 ( .A(left_right_SHT2), .Y(n1473) );
CLKINVX6TS U1013 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1336) );
INVX2TS U1014 ( .A(n889), .Y(n896) );
INVX2TS U1015 ( .A(n892), .Y(n897) );
INVX2TS U1016 ( .A(n888), .Y(n898) );
INVX2TS U1017 ( .A(n887), .Y(n899) );
INVX2TS U1018 ( .A(n886), .Y(n900) );
INVX2TS U1019 ( .A(n891), .Y(n901) );
INVX2TS U1020 ( .A(n890), .Y(n902) );
NOR4BX2TS U1021 ( .AN(n1128), .B(n1127), .C(n1126), .D(n1125), .Y(n1150) );
BUFX4TS U1022 ( .A(n1087), .Y(n1093) );
BUFX6TS U1023 ( .A(n1129), .Y(n1288) );
BUFX4TS U1024 ( .A(n1365), .Y(n1435) );
BUFX4TS U1025 ( .A(n1362), .Y(n1426) );
INVX6TS U1026 ( .A(n1603), .Y(n1359) );
BUFX6TS U1027 ( .A(n1132), .Y(n1284) );
BUFX6TS U1028 ( .A(n1187), .Y(n1279) );
CLKINVX6TS U1029 ( .A(n1270), .Y(n1268) );
INVX3TS U1030 ( .A(n1355), .Y(n1354) );
CLKINVX3TS U1031 ( .A(n1469), .Y(n1471) );
AOI222X4TS U1032 ( .A0(Data_array_SWR[20]), .A1(n1401), .B0(
Data_array_SWR[16]), .B1(n1400), .C0(Data_array_SWR[24]), .C1(n1386),
.Y(n1423) );
INVX2TS U1033 ( .A(n885), .Y(n903) );
AOI32X1TS U1034 ( .A0(n1552), .A1(n979), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1499), .Y(n980) );
AOI221X1TS U1035 ( .A0(n1552), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1499), .C0(n1040), .Y(n1045) );
AOI221X1TS U1036 ( .A0(n878), .A1(n905), .B0(intDX_EWSW[11]), .B1(n1606),
.C0(n1048), .Y(n1053) );
AOI221X1TS U1037 ( .A0(n1551), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1547), .C0(n1039), .Y(n1046) );
AOI221X4TS U1038 ( .A0(intDX_EWSW[30]), .A1(n1551), .B0(intDX_EWSW[29]),
.B1(n1500), .C0(n938), .Y(n940) );
INVX2TS U1039 ( .A(n879), .Y(n904) );
INVX2TS U1040 ( .A(n881), .Y(n905) );
AOI221X1TS U1041 ( .A0(n1532), .A1(n906), .B0(intDX_EWSW[3]), .B1(n1605),
.C0(n1056), .Y(n1061) );
INVX2TS U1042 ( .A(n880), .Y(n906) );
AOI221X1TS U1043 ( .A0(n1498), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1539), .C0(n1042), .Y(n1043) );
AOI221X1TS U1044 ( .A0(n1535), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1607), .C0(n1050), .Y(n1051) );
OAI211X2TS U1045 ( .A0(intDX_EWSW[20]), .A1(n1536), .B0(n987), .C0(n973),
.Y(n982) );
AOI221X1TS U1046 ( .A0(n1536), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1531), .C0(n1041), .Y(n1044) );
OAI211X2TS U1047 ( .A0(intDX_EWSW[12]), .A1(n1534), .B0(n968), .C0(n954),
.Y(n970) );
AOI221X1TS U1048 ( .A0(n1534), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1530), .C0(n1049), .Y(n1052) );
INVX1TS U1049 ( .A(DMP_SFG[3]), .Y(intadd_30_A_1_) );
INVX1TS U1050 ( .A(DMP_SFG[4]), .Y(intadd_30_A_2_) );
INVX1TS U1051 ( .A(DMP_SFG[7]), .Y(intadd_29_A_1_) );
INVX1TS U1052 ( .A(DMP_SFG[8]), .Y(intadd_29_A_2_) );
OAI31XLTS U1053 ( .A0(n1320), .A1(n1070), .A2(n1326), .B0(n1069), .Y(n720)
);
NOR2X2TS U1054 ( .A(n1300), .B(DMP_EXP_EWSW[23]), .Y(n1305) );
XNOR2X2TS U1055 ( .A(DMP_exp_NRM2_EW[6]), .B(n929), .Y(n1256) );
XNOR2X2TS U1056 ( .A(DMP_exp_NRM2_EW[0]), .B(n1236), .Y(n1218) );
INVX1TS U1057 ( .A(LZD_output_NRM2_EW[0]), .Y(n1236) );
XNOR2X2TS U1058 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J31_123_3372_n4), .Y(
n1220) );
CLKINVX6TS U1059 ( .A(n996), .Y(n1092) );
NOR2X4TS U1060 ( .A(shift_value_SHT2_EWR[4]), .B(n1434), .Y(n1407) );
CLKINVX6TS U1061 ( .A(n1473), .Y(n1434) );
AOI2BB2X2TS U1062 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n1354), .A0N(n1354),
.A1N(DmP_mant_SFG_SWR[10]), .Y(intadd_29_B_2_) );
AOI2BB2X2TS U1063 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1351), .A0N(n1355),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1347) );
BUFX6TS U1064 ( .A(n1603), .Y(n1357) );
NOR2X4TS U1065 ( .A(n1361), .B(n1360), .Y(n1381) );
OAI2BB1X2TS U1066 ( .A0N(n1226), .A1N(n1225), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1360) );
AOI222X4TS U1067 ( .A0(DMP_SFG[5]), .A1(n894), .B0(DMP_SFG[5]), .B1(n1232),
.C0(n894), .C1(n1232), .Y(intadd_29_CI) );
AOI222X4TS U1068 ( .A0(DMP_SFG[9]), .A1(n1347), .B0(DMP_SFG[9]), .B1(n1235),
.C0(n1347), .C1(n1235), .Y(intadd_28_B_0_) );
AOI222X1TS U1069 ( .A0(n1402), .A1(n1434), .B0(n1364), .B1(Data_array_SWR[5]), .C0(n1403), .C1(n1407), .Y(n1440) );
AOI222X1TS U1070 ( .A0(n1402), .A1(n1473), .B0(Data_array_SWR[5]), .B1(n1435), .C0(n1403), .C1(n1408), .Y(n1464) );
AOI222X1TS U1071 ( .A0(n1410), .A1(n1434), .B0(n1364), .B1(Data_array_SWR[4]), .C0(n1409), .C1(n1407), .Y(n1439) );
AOI222X1TS U1072 ( .A0(n1410), .A1(n1473), .B0(Data_array_SWR[4]), .B1(n1435), .C0(n1409), .C1(n1408), .Y(n1466) );
AOI222X1TS U1073 ( .A0(n1392), .A1(n1434), .B0(Data_array_SWR[7]), .B1(n1364), .C0(n1391), .C1(n1407), .Y(n1442) );
AOI222X1TS U1074 ( .A0(n1392), .A1(n1473), .B0(Data_array_SWR[7]), .B1(n1435), .C0(n1391), .C1(n1408), .Y(n1460) );
AOI222X1TS U1075 ( .A0(n1397), .A1(n1434), .B0(Data_array_SWR[6]), .B1(n1364), .C0(n1396), .C1(n1407), .Y(n1441) );
AOI222X1TS U1076 ( .A0(n1397), .A1(n1473), .B0(Data_array_SWR[6]), .B1(n1435), .C0(n1396), .C1(n1408), .Y(n1462) );
AOI22X2TS U1077 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n1352), .B0(n1351), .B1(n877), .Y(intadd_29_B_1_) );
AOI22X2TS U1078 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1352), .B0(n1351), .B1(n916), .Y(intadd_30_B_1_) );
INVX4TS U1079 ( .A(n1355), .Y(n1352) );
INVX3TS U1080 ( .A(n1327), .Y(n1420) );
CLKINVX6TS U1081 ( .A(n1574), .Y(n1335) );
NOR2X2TS U1082 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1524), .Y(n1261) );
OAI21X2TS U1083 ( .A0(intDX_EWSW[18]), .A1(n1552), .B0(n979), .Y(n1040) );
NOR3X1TS U1084 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1252) );
NOR2X2TS U1085 ( .A(Raw_mant_NRM_SWR[12]), .B(n1114), .Y(n1246) );
AOI32X1TS U1086 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1297), .A2(n1336),
.B0(shift_value_SHT2_EWR[2]), .B1(n1294), .Y(n1296) );
NOR3X1TS U1087 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1512), .Y(n1362) );
NOR2X4TS U1088 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1400) );
AND2X2TS U1089 ( .A(beg_OP), .B(n1265), .Y(n920) );
NOR2XLTS U1090 ( .A(n1606), .B(intDX_EWSW[11]), .Y(n956) );
OAI21XLTS U1091 ( .A0(intDX_EWSW[15]), .A1(n1607), .B0(intDX_EWSW[14]), .Y(
n964) );
NOR2XLTS U1092 ( .A(n977), .B(intDY_EWSW[16]), .Y(n978) );
OAI21XLTS U1093 ( .A0(intDX_EWSW[23]), .A1(n1539), .B0(intDX_EWSW[22]), .Y(
n983) );
OAI21XLTS U1094 ( .A0(intDX_EWSW[21]), .A1(n1531), .B0(intDX_EWSW[20]), .Y(
n976) );
NOR2XLTS U1095 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1118) );
OR2X1TS U1096 ( .A(n931), .B(n1217), .Y(n1228) );
OAI21XLTS U1097 ( .A0(n1556), .A1(n1192), .B0(n1169), .Y(n1170) );
OAI21XLTS U1098 ( .A0(n1540), .A1(n1067), .B0(n1021), .Y(n560) );
OAI21XLTS U1099 ( .A0(n1605), .A1(n1324), .B0(n1020), .Y(n604) );
OAI21XLTS U1100 ( .A0(n1547), .A1(n1092), .B0(n1072), .Y(n736) );
OAI21XLTS U1101 ( .A0(n1605), .A1(n1326), .B0(n1029), .Y(n750) );
OAI211XLTS U1102 ( .A0(n1168), .A1(n1288), .B0(n1167), .C0(n1166), .Y(n780)
);
BUFX3TS U1103 ( .A(n921), .Y(n1591) );
BUFX3TS U1104 ( .A(n922), .Y(n1593) );
BUFX3TS U1105 ( .A(n922), .Y(n1594) );
BUFX3TS U1106 ( .A(n921), .Y(n1600) );
BUFX3TS U1107 ( .A(n921), .Y(n1596) );
BUFX3TS U1108 ( .A(n921), .Y(n1582) );
BUFX3TS U1109 ( .A(n922), .Y(n1599) );
BUFX3TS U1110 ( .A(n922), .Y(n1595) );
BUFX3TS U1111 ( .A(n1592), .Y(n1602) );
BUFX3TS U1112 ( .A(n1586), .Y(n1584) );
BUFX3TS U1113 ( .A(n1601), .Y(n1577) );
BUFX3TS U1114 ( .A(n921), .Y(n1598) );
INVX2TS U1115 ( .A(DP_OP_15J31_123_3372_n4), .Y(n923) );
NAND2X1TS U1116 ( .A(n1542), .B(n923), .Y(n929) );
NOR2XLTS U1117 ( .A(n1218), .B(exp_rslt_NRM2_EW1[1]), .Y(n926) );
INVX2TS U1118 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n925) );
INVX2TS U1119 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n924) );
NAND4BXLTS U1120 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n926), .C(n925), .D(n924),
.Y(n927) );
NOR2XLTS U1121 ( .A(n927), .B(n1220), .Y(n928) );
INVX2TS U1122 ( .A(n929), .Y(n930) );
NAND2X1TS U1123 ( .A(n1541), .B(n930), .Y(n1223) );
XNOR2X1TS U1124 ( .A(DMP_exp_NRM2_EW[7]), .B(n1223), .Y(n1217) );
CLKBUFX2TS U1125 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1327) );
NAND2X2TS U1126 ( .A(n1228), .B(n1327), .Y(n1257) );
OA22X1TS U1127 ( .A0(n1257), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n757) );
OA22X1TS U1128 ( .A0(n1257), .A1(n1220), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n756) );
OA22X1TS U1129 ( .A0(n1257), .A1(n1218), .B0(final_result_ieee[23]), .B1(
Shift_reg_FLAGS_7[0]), .Y(n761) );
OA22X1TS U1130 ( .A0(n1257), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n758) );
OA22X1TS U1131 ( .A0(n1257), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n760) );
OA22X1TS U1132 ( .A0(n1257), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n759) );
OAI21XLTS U1133 ( .A0(n1335), .A1(n1434), .B0(n1336), .Y(n829) );
NOR2X1TS U1134 ( .A(n1545), .B(intDX_EWSW[25]), .Y(n990) );
NOR2XLTS U1135 ( .A(n990), .B(intDY_EWSW[24]), .Y(n932) );
AOI22X1TS U1136 ( .A0(intDX_EWSW[25]), .A1(n1545), .B0(intDX_EWSW[24]), .B1(
n932), .Y(n936) );
NAND3XLTS U1137 ( .A(n1550), .B(n933), .C(intDX_EWSW[26]), .Y(n935) );
NAND2BXLTS U1138 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n934) );
OAI211XLTS U1139 ( .A0(n936), .A1(n1033), .B0(n935), .C0(n934), .Y(n941) );
NOR2X1TS U1140 ( .A(n1551), .B(intDX_EWSW[30]), .Y(n939) );
NOR2X1TS U1141 ( .A(n1500), .B(intDX_EWSW[29]), .Y(n937) );
AOI211X1TS U1142 ( .A0(intDY_EWSW[28]), .A1(n1520), .B0(n939), .C0(n937),
.Y(n989) );
NOR3XLTS U1143 ( .A(n1520), .B(n937), .C(intDY_EWSW[28]), .Y(n938) );
AOI2BB2X1TS U1144 ( .B0(n941), .B1(n989), .A0N(n940), .A1N(n939), .Y(n994)
);
NOR2X1TS U1145 ( .A(n1547), .B(intDX_EWSW[17]), .Y(n977) );
OAI22X1TS U1146 ( .A0(n878), .A1(n905), .B0(n1606), .B1(intDX_EWSW[11]), .Y(
n1048) );
INVX2TS U1147 ( .A(n1048), .Y(n961) );
OAI211XLTS U1148 ( .A0(intDX_EWSW[8]), .A1(n1549), .B0(n958), .C0(n961), .Y(
n972) );
OAI2BB1X1TS U1149 ( .A0N(n1509), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n942) );
OAI22X1TS U1150 ( .A0(intDY_EWSW[4]), .A1(n942), .B0(n1509), .B1(
intDY_EWSW[5]), .Y(n953) );
OAI2BB1X1TS U1151 ( .A0N(n1494), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n943) );
OAI22X1TS U1152 ( .A0(intDY_EWSW[6]), .A1(n943), .B0(n1494), .B1(
intDY_EWSW[7]), .Y(n952) );
OAI21XLTS U1153 ( .A0(intDX_EWSW[1]), .A1(n1548), .B0(n904), .Y(n944) );
OAI2BB2XLTS U1154 ( .B0(intDY_EWSW[0]), .B1(n944), .A0N(intDX_EWSW[1]),
.A1N(n1548), .Y(n946) );
OAI211XLTS U1155 ( .A0(n1605), .A1(intDX_EWSW[3]), .B0(n946), .C0(n945), .Y(
n949) );
OAI21XLTS U1156 ( .A0(intDX_EWSW[3]), .A1(n1605), .B0(n906), .Y(n947) );
AOI2BB2XLTS U1157 ( .B0(intDX_EWSW[3]), .B1(n1605), .A0N(intDY_EWSW[2]),
.A1N(n947), .Y(n948) );
AOI222X1TS U1158 ( .A0(intDY_EWSW[4]), .A1(n1492), .B0(n949), .B1(n948),
.C0(intDY_EWSW[5]), .C1(n1509), .Y(n951) );
AOI22X1TS U1159 ( .A0(intDY_EWSW[7]), .A1(n1494), .B0(intDY_EWSW[6]), .B1(
n1514), .Y(n950) );
OAI32X1TS U1160 ( .A0(n953), .A1(n952), .A2(n951), .B0(n950), .B1(n952), .Y(
n971) );
OA22X1TS U1161 ( .A0(n1535), .A1(intDX_EWSW[14]), .B0(n1607), .B1(
intDX_EWSW[15]), .Y(n968) );
OAI21XLTS U1162 ( .A0(intDX_EWSW[13]), .A1(n1530), .B0(intDX_EWSW[12]), .Y(
n955) );
OAI2BB2XLTS U1163 ( .B0(intDY_EWSW[12]), .B1(n955), .A0N(intDX_EWSW[13]),
.A1N(n1530), .Y(n967) );
NOR2XLTS U1164 ( .A(n956), .B(intDY_EWSW[10]), .Y(n957) );
AOI22X1TS U1165 ( .A0(intDX_EWSW[11]), .A1(n1606), .B0(n905), .B1(n957), .Y(
n963) );
NAND2BXLTS U1166 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n960) );
NAND3XLTS U1167 ( .A(n1549), .B(n958), .C(intDX_EWSW[8]), .Y(n959) );
AOI21X1TS U1168 ( .A0(n960), .A1(n959), .B0(n970), .Y(n962) );
OAI2BB2XLTS U1169 ( .B0(n963), .B1(n970), .A0N(n962), .A1N(n961), .Y(n966)
);
AOI211X1TS U1170 ( .A0(n968), .A1(n967), .B0(n966), .C0(n965), .Y(n969) );
OAI31X1TS U1171 ( .A0(n972), .A1(n971), .A2(n970), .B0(n969), .Y(n975) );
OA22X1TS U1172 ( .A0(n1498), .A1(intDX_EWSW[22]), .B0(n1539), .B1(
intDX_EWSW[23]), .Y(n987) );
AOI211XLTS U1173 ( .A0(intDY_EWSW[16]), .A1(n1519), .B0(n982), .C0(n1040),
.Y(n974) );
NAND3BXLTS U1174 ( .AN(n977), .B(n975), .C(n974), .Y(n993) );
OAI2BB2XLTS U1175 ( .B0(intDY_EWSW[20]), .B1(n976), .A0N(intDX_EWSW[21]),
.A1N(n1531), .Y(n986) );
AOI22X1TS U1176 ( .A0(intDX_EWSW[17]), .A1(n1547), .B0(intDX_EWSW[16]), .B1(
n978), .Y(n981) );
OAI32X1TS U1177 ( .A0(n1040), .A1(n982), .A2(n981), .B0(n980), .B1(n982),
.Y(n985) );
OAI2BB2XLTS U1178 ( .B0(intDY_EWSW[22]), .B1(n983), .A0N(intDX_EWSW[23]),
.A1N(n1539), .Y(n984) );
AOI211X1TS U1179 ( .A0(n987), .A1(n986), .B0(n985), .C0(n984), .Y(n992) );
NAND2BXLTS U1180 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n988) );
NAND4BBX1TS U1181 ( .AN(n1033), .BN(n990), .C(n989), .D(n988), .Y(n991) );
AOI32X1TS U1182 ( .A0(n994), .A1(n993), .A2(n992), .B0(n991), .B1(n994), .Y(
n995) );
INVX3TS U1183 ( .A(n1087), .Y(n1067) );
BUFX4TS U1184 ( .A(n997), .Y(n1090) );
AOI22X1TS U1185 ( .A0(intDX_EWSW[14]), .A1(n996), .B0(DmP_EXP_EWSW[14]),
.B1(n1090), .Y(n998) );
OAI21XLTS U1186 ( .A0(n1535), .A1(n1067), .B0(n998), .Y(n582) );
INVX4TS U1187 ( .A(n1087), .Y(n1324) );
BUFX4TS U1188 ( .A(n997), .Y(n1262) );
AOI22X1TS U1189 ( .A0(intDX_EWSW[19]), .A1(n996), .B0(DmP_EXP_EWSW[19]),
.B1(n1262), .Y(n999) );
OAI21XLTS U1190 ( .A0(n1499), .A1(n1324), .B0(n999), .Y(n572) );
AOI22X1TS U1191 ( .A0(n904), .A1(n996), .B0(DmP_EXP_EWSW[0]), .B1(n1090),
.Y(n1000) );
OAI21XLTS U1192 ( .A0(n1546), .A1(n1324), .B0(n1000), .Y(n610) );
AOI22X1TS U1193 ( .A0(intDX_EWSW[22]), .A1(n996), .B0(DmP_EXP_EWSW[22]),
.B1(n1262), .Y(n1001) );
OAI21XLTS U1194 ( .A0(n1498), .A1(n1324), .B0(n1001), .Y(n566) );
AOI22X1TS U1195 ( .A0(intDX_EWSW[16]), .A1(n996), .B0(DmP_EXP_EWSW[16]),
.B1(n1262), .Y(n1002) );
OAI21XLTS U1196 ( .A0(n1497), .A1(n1324), .B0(n1002), .Y(n578) );
AOI22X1TS U1197 ( .A0(intDX_EWSW[5]), .A1(n1012), .B0(DmP_EXP_EWSW[5]), .B1(
n1090), .Y(n1003) );
OAI21XLTS U1198 ( .A0(n1496), .A1(n1067), .B0(n1003), .Y(n600) );
AOI22X1TS U1199 ( .A0(intDX_EWSW[6]), .A1(n1012), .B0(DmP_EXP_EWSW[6]), .B1(
n1262), .Y(n1004) );
OAI21XLTS U1200 ( .A0(n1528), .A1(n1067), .B0(n1004), .Y(n598) );
AOI22X1TS U1201 ( .A0(intDX_EWSW[4]), .A1(n1012), .B0(DmP_EXP_EWSW[4]), .B1(
n997), .Y(n1005) );
OAI21XLTS U1202 ( .A0(n1533), .A1(n1067), .B0(n1005), .Y(n602) );
AOI22X1TS U1203 ( .A0(intDX_EWSW[17]), .A1(n996), .B0(DmP_EXP_EWSW[17]),
.B1(n1262), .Y(n1006) );
OAI21XLTS U1204 ( .A0(n1547), .A1(n1324), .B0(n1006), .Y(n576) );
AOI22X1TS U1205 ( .A0(n905), .A1(n1012), .B0(DmP_EXP_EWSW[10]), .B1(n1090),
.Y(n1007) );
OAI21XLTS U1206 ( .A0(n878), .A1(n1067), .B0(n1007), .Y(n590) );
AOI22X1TS U1207 ( .A0(intDX_EWSW[13]), .A1(n996), .B0(DmP_EXP_EWSW[13]),
.B1(n1262), .Y(n1008) );
OAI21XLTS U1208 ( .A0(n1530), .A1(n1067), .B0(n1008), .Y(n584) );
AOI22X1TS U1209 ( .A0(intDX_EWSW[20]), .A1(n1012), .B0(DmP_EXP_EWSW[20]),
.B1(n1262), .Y(n1009) );
OAI21XLTS U1210 ( .A0(n1536), .A1(n1324), .B0(n1009), .Y(n570) );
AOI22X1TS U1211 ( .A0(intDX_EWSW[9]), .A1(n1012), .B0(DmP_EXP_EWSW[9]), .B1(
n1090), .Y(n1010) );
OAI21XLTS U1212 ( .A0(n1529), .A1(n1067), .B0(n1010), .Y(n592) );
AOI22X1TS U1213 ( .A0(intDX_EWSW[21]), .A1(n1012), .B0(DmP_EXP_EWSW[21]),
.B1(n1262), .Y(n1011) );
OAI21XLTS U1214 ( .A0(n1531), .A1(n1324), .B0(n1011), .Y(n568) );
AOI22X1TS U1215 ( .A0(intDX_EWSW[7]), .A1(n1012), .B0(DmP_EXP_EWSW[7]), .B1(
n1090), .Y(n1013) );
OAI21XLTS U1216 ( .A0(n1537), .A1(n1067), .B0(n1013), .Y(n596) );
AOI22X1TS U1217 ( .A0(intDX_EWSW[18]), .A1(n1012), .B0(DmP_EXP_EWSW[18]),
.B1(n1262), .Y(n1014) );
OAI21XLTS U1218 ( .A0(n1552), .A1(n1324), .B0(n1014), .Y(n574) );
AOI22X1TS U1219 ( .A0(intDX_EWSW[1]), .A1(n1012), .B0(DmP_EXP_EWSW[1]), .B1(
n1262), .Y(n1015) );
OAI21XLTS U1220 ( .A0(n1548), .A1(n1324), .B0(n1015), .Y(n608) );
AOI22X1TS U1221 ( .A0(n906), .A1(n1012), .B0(DmP_EXP_EWSW[2]), .B1(n1262),
.Y(n1016) );
OAI21XLTS U1222 ( .A0(n1532), .A1(n1324), .B0(n1016), .Y(n606) );
AOI22X1TS U1223 ( .A0(intDX_EWSW[12]), .A1(n1012), .B0(DmP_EXP_EWSW[12]),
.B1(n997), .Y(n1017) );
OAI21XLTS U1224 ( .A0(n1534), .A1(n1067), .B0(n1017), .Y(n586) );
AOI22X1TS U1225 ( .A0(intDX_EWSW[8]), .A1(n1012), .B0(DmP_EXP_EWSW[8]), .B1(
n997), .Y(n1018) );
OAI21XLTS U1226 ( .A0(n1549), .A1(n1067), .B0(n1018), .Y(n594) );
AOI22X1TS U1227 ( .A0(intDX_EWSW[11]), .A1(n1012), .B0(DmP_EXP_EWSW[11]),
.B1(n1262), .Y(n1019) );
OAI21XLTS U1228 ( .A0(n1606), .A1(n1067), .B0(n1019), .Y(n588) );
AOI22X1TS U1229 ( .A0(intDX_EWSW[3]), .A1(n1012), .B0(DmP_EXP_EWSW[3]), .B1(
n1090), .Y(n1020) );
AOI22X1TS U1230 ( .A0(DmP_EXP_EWSW[27]), .A1(n1262), .B0(intDX_EWSW[27]),
.B1(n1012), .Y(n1021) );
AOI22X1TS U1231 ( .A0(intDX_EWSW[15]), .A1(n1012), .B0(DmP_EXP_EWSW[15]),
.B1(n1262), .Y(n1022) );
OAI21XLTS U1232 ( .A0(n1607), .A1(n1067), .B0(n1022), .Y(n580) );
INVX4TS U1233 ( .A(n996), .Y(n1326) );
AOI22X1TS U1234 ( .A0(intDX_EWSW[30]), .A1(n1087), .B0(DMP_EXP_EWSW[30]),
.B1(n1090), .Y(n1023) );
OAI21XLTS U1235 ( .A0(n1551), .A1(n1326), .B0(n1023), .Y(n723) );
AOI22X1TS U1236 ( .A0(intDX_EWSW[28]), .A1(n1087), .B0(DMP_EXP_EWSW[28]),
.B1(n1090), .Y(n1024) );
OAI21XLTS U1237 ( .A0(n1538), .A1(n1326), .B0(n1024), .Y(n725) );
AOI22X1TS U1238 ( .A0(n902), .A1(n1262), .B0(intDX_EWSW[27]), .B1(n1087),
.Y(n1025) );
OAI21XLTS U1239 ( .A0(n1540), .A1(n1326), .B0(n1025), .Y(n726) );
AOI22X1TS U1240 ( .A0(DMP_EXP_EWSW[23]), .A1(n1262), .B0(intDX_EWSW[23]),
.B1(n1093), .Y(n1026) );
OAI21XLTS U1241 ( .A0(n1539), .A1(n1326), .B0(n1026), .Y(n730) );
AOI22X1TS U1242 ( .A0(intDX_EWSW[29]), .A1(n1087), .B0(DMP_EXP_EWSW[29]),
.B1(n1090), .Y(n1027) );
OAI21XLTS U1243 ( .A0(n1500), .A1(n1326), .B0(n1027), .Y(n724) );
AOI22X1TS U1244 ( .A0(intDX_EWSW[1]), .A1(n1093), .B0(DMP_EXP_EWSW[1]), .B1(
n997), .Y(n1028) );
OAI21XLTS U1245 ( .A0(n1548), .A1(n1326), .B0(n1028), .Y(n752) );
AOI22X1TS U1246 ( .A0(intDX_EWSW[3]), .A1(n1093), .B0(DMP_EXP_EWSW[3]), .B1(
n997), .Y(n1029) );
AOI22X1TS U1247 ( .A0(intDX_EWSW[4]), .A1(n1093), .B0(DMP_EXP_EWSW[4]), .B1(
n997), .Y(n1030) );
OAI21XLTS U1248 ( .A0(n1533), .A1(n1326), .B0(n1030), .Y(n749) );
AOI22X1TS U1249 ( .A0(intDX_EWSW[9]), .A1(n1093), .B0(DMP_EXP_EWSW[9]), .B1(
n997), .Y(n1031) );
OAI21XLTS U1250 ( .A0(n1529), .A1(n1326), .B0(n1031), .Y(n744) );
OAI22X1TS U1251 ( .A0(n1548), .A1(intDX_EWSW[1]), .B0(n1545), .B1(
intDX_EWSW[25]), .Y(n1032) );
AOI221X1TS U1252 ( .A0(n1548), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1545), .C0(n1032), .Y(n1038) );
OAI22X1TS U1253 ( .A0(n1538), .A1(intDX_EWSW[28]), .B0(n1500), .B1(
intDX_EWSW[29]), .Y(n1034) );
AOI221X1TS U1254 ( .A0(n1538), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1500), .C0(n1034), .Y(n1036) );
AOI2BB2XLTS U1255 ( .B0(intDX_EWSW[7]), .B1(n1537), .A0N(n1537), .A1N(
intDX_EWSW[7]), .Y(n1035) );
NAND4XLTS U1256 ( .A(n1038), .B(n1037), .C(n1036), .D(n1035), .Y(n1066) );
OAI22X1TS U1257 ( .A0(n1551), .A1(intDX_EWSW[30]), .B0(n1547), .B1(
intDX_EWSW[17]), .Y(n1039) );
OAI22X1TS U1258 ( .A0(n1536), .A1(intDX_EWSW[20]), .B0(n1531), .B1(
intDX_EWSW[21]), .Y(n1041) );
OAI22X1TS U1259 ( .A0(n1498), .A1(intDX_EWSW[22]), .B0(n1539), .B1(
intDX_EWSW[23]), .Y(n1042) );
NAND4XLTS U1260 ( .A(n1046), .B(n1045), .C(n1044), .D(n1043), .Y(n1065) );
OAI22X1TS U1261 ( .A0(n1487), .A1(intDX_EWSW[24]), .B0(n1529), .B1(
intDX_EWSW[9]), .Y(n1047) );
AOI221X1TS U1262 ( .A0(n1487), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1529), .C0(n1047), .Y(n1054) );
OAI22X1TS U1263 ( .A0(n1534), .A1(intDX_EWSW[12]), .B0(n1530), .B1(
intDX_EWSW[13]), .Y(n1049) );
OAI22X1TS U1264 ( .A0(n1535), .A1(intDX_EWSW[14]), .B0(n1607), .B1(
intDX_EWSW[15]), .Y(n1050) );
NAND4XLTS U1265 ( .A(n1054), .B(n1053), .C(n1052), .D(n1051), .Y(n1064) );
OAI22X1TS U1266 ( .A0(n1497), .A1(intDX_EWSW[16]), .B0(n1546), .B1(n904),
.Y(n1055) );
AOI221X1TS U1267 ( .A0(n1497), .A1(intDX_EWSW[16]), .B0(n904), .B1(n1546),
.C0(n1055), .Y(n1062) );
OAI22X1TS U1268 ( .A0(n1532), .A1(n906), .B0(n1605), .B1(intDX_EWSW[3]), .Y(
n1056) );
OAI22X1TS U1269 ( .A0(n1533), .A1(intDX_EWSW[4]), .B0(n1496), .B1(
intDX_EWSW[5]), .Y(n1057) );
AOI221X1TS U1270 ( .A0(n1533), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1496), .C0(n1057), .Y(n1060) );
OAI22X1TS U1271 ( .A0(n1549), .A1(intDX_EWSW[8]), .B0(n1528), .B1(
intDX_EWSW[6]), .Y(n1058) );
AOI221X1TS U1272 ( .A0(n1549), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1528), .C0(n1058), .Y(n1059) );
NAND4XLTS U1273 ( .A(n1062), .B(n1061), .C(n1060), .D(n1059), .Y(n1063) );
NOR4X1TS U1274 ( .A(n1066), .B(n1065), .C(n1064), .D(n1063), .Y(n1320) );
CLKXOR2X2TS U1275 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1318) );
INVX2TS U1276 ( .A(n1318), .Y(n1070) );
OAI21XLTS U1277 ( .A0(n1070), .A1(n997), .B0(n1067), .Y(n1068) );
AOI22X1TS U1278 ( .A0(intDX_EWSW[31]), .A1(n1068), .B0(SIGN_FLAG_EXP), .B1(
n1262), .Y(n1069) );
AOI22X1TS U1279 ( .A0(intDX_EWSW[15]), .A1(n1093), .B0(DMP_EXP_EWSW[15]),
.B1(n997), .Y(n1071) );
OAI21XLTS U1280 ( .A0(n1607), .A1(n1092), .B0(n1071), .Y(n738) );
AOI22X1TS U1281 ( .A0(intDX_EWSW[17]), .A1(n1087), .B0(DMP_EXP_EWSW[17]),
.B1(n1090), .Y(n1072) );
AOI22X1TS U1282 ( .A0(intDX_EWSW[14]), .A1(n1093), .B0(DMP_EXP_EWSW[14]),
.B1(n997), .Y(n1073) );
OAI21XLTS U1283 ( .A0(n1535), .A1(n1092), .B0(n1073), .Y(n739) );
AOI22X1TS U1284 ( .A0(intDX_EWSW[8]), .A1(n1087), .B0(DMP_EXP_EWSW[8]), .B1(
n997), .Y(n1074) );
OAI21XLTS U1285 ( .A0(n1549), .A1(n1092), .B0(n1074), .Y(n745) );
AOI22X1TS U1286 ( .A0(intDX_EWSW[12]), .A1(n1087), .B0(DMP_EXP_EWSW[12]),
.B1(n997), .Y(n1075) );
OAI21XLTS U1287 ( .A0(n1534), .A1(n1092), .B0(n1075), .Y(n741) );
AOI22X1TS U1288 ( .A0(intDX_EWSW[22]), .A1(n1087), .B0(DMP_EXP_EWSW[22]),
.B1(n1090), .Y(n1076) );
OAI21XLTS U1289 ( .A0(n1498), .A1(n1092), .B0(n1076), .Y(n731) );
AOI22X1TS U1290 ( .A0(intDX_EWSW[13]), .A1(n1087), .B0(DMP_EXP_EWSW[13]),
.B1(n997), .Y(n1077) );
OAI21XLTS U1291 ( .A0(n1530), .A1(n1092), .B0(n1077), .Y(n740) );
AOI22X1TS U1292 ( .A0(intDX_EWSW[18]), .A1(n1093), .B0(DMP_EXP_EWSW[18]),
.B1(n1090), .Y(n1078) );
OAI21XLTS U1293 ( .A0(n1552), .A1(n1092), .B0(n1078), .Y(n735) );
AOI22X1TS U1294 ( .A0(intDX_EWSW[7]), .A1(n1093), .B0(DMP_EXP_EWSW[7]), .B1(
n997), .Y(n1079) );
OAI21XLTS U1295 ( .A0(n1537), .A1(n1092), .B0(n1079), .Y(n746) );
AOI22X1TS U1296 ( .A0(intDX_EWSW[19]), .A1(n1087), .B0(DMP_EXP_EWSW[19]),
.B1(n1090), .Y(n1080) );
OAI21XLTS U1297 ( .A0(n1499), .A1(n1092), .B0(n1080), .Y(n734) );
AOI22X1TS U1298 ( .A0(intDX_EWSW[6]), .A1(n1093), .B0(DMP_EXP_EWSW[6]), .B1(
n997), .Y(n1081) );
OAI21XLTS U1299 ( .A0(n1528), .A1(n1092), .B0(n1081), .Y(n747) );
AOI22X1TS U1300 ( .A0(intDX_EWSW[5]), .A1(n1087), .B0(DMP_EXP_EWSW[5]), .B1(
n997), .Y(n1082) );
OAI21XLTS U1301 ( .A0(n1496), .A1(n1092), .B0(n1082), .Y(n748) );
AOI22X1TS U1302 ( .A0(intDX_EWSW[16]), .A1(n1087), .B0(DMP_EXP_EWSW[16]),
.B1(n1090), .Y(n1083) );
OAI21XLTS U1303 ( .A0(n1497), .A1(n1092), .B0(n1083), .Y(n737) );
AOI22X1TS U1304 ( .A0(n906), .A1(n1093), .B0(DMP_EXP_EWSW[2]), .B1(n997),
.Y(n1084) );
OAI21XLTS U1305 ( .A0(n1532), .A1(n1092), .B0(n1084), .Y(n751) );
AOI22X1TS U1306 ( .A0(n904), .A1(n1087), .B0(DMP_EXP_EWSW[0]), .B1(n997),
.Y(n1085) );
OAI21XLTS U1307 ( .A0(n1546), .A1(n1092), .B0(n1085), .Y(n753) );
AOI22X1TS U1308 ( .A0(intDX_EWSW[11]), .A1(n1087), .B0(DMP_EXP_EWSW[11]),
.B1(n1090), .Y(n1086) );
OAI21XLTS U1309 ( .A0(n1606), .A1(n1092), .B0(n1086), .Y(n742) );
AOI22X1TS U1310 ( .A0(n905), .A1(n1087), .B0(DMP_EXP_EWSW[10]), .B1(n997),
.Y(n1088) );
OAI21XLTS U1311 ( .A0(n878), .A1(n1092), .B0(n1088), .Y(n743) );
AOI22X1TS U1312 ( .A0(intDX_EWSW[20]), .A1(n1093), .B0(DMP_EXP_EWSW[20]),
.B1(n1090), .Y(n1089) );
OAI21XLTS U1313 ( .A0(n1536), .A1(n1092), .B0(n1089), .Y(n733) );
AOI22X1TS U1314 ( .A0(intDX_EWSW[21]), .A1(n1093), .B0(DMP_EXP_EWSW[21]),
.B1(n1090), .Y(n1091) );
OAI21XLTS U1315 ( .A0(n1531), .A1(n1092), .B0(n1091), .Y(n732) );
AOI222X1TS U1316 ( .A0(n1012), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n997), .C0(intDY_EWSW[23]), .C1(n1093), .Y(n1094) );
INVX2TS U1317 ( .A(n1094), .Y(n564) );
AOI2BB2XLTS U1318 ( .B0(beg_OP), .B1(n1495), .A0N(n1495), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1095) );
NAND3XLTS U1319 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1495), .C(
n1524), .Y(n1258) );
OAI21XLTS U1320 ( .A0(n1261), .A1(n1095), .B0(n1258), .Y(n870) );
NAND2X2TS U1321 ( .A(n1336), .B(n1574), .Y(n1297) );
NOR2XLTS U1322 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1097)
);
NOR2BX1TS U1323 ( .AN(n1112), .B(Raw_mant_NRM_SWR[18]), .Y(n1239) );
NOR2BX1TS U1324 ( .AN(n1239), .B(n1240), .Y(n1109) );
NAND2X1TS U1325 ( .A(n1109), .B(n1491), .Y(n1241) );
NAND2X1TS U1326 ( .A(n1122), .B(n1483), .Y(n1114) );
NAND2X1TS U1327 ( .A(n1246), .B(n1484), .Y(n1096) );
NOR2X1TS U1328 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1098)
);
NOR3X1TS U1329 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1096),
.Y(n1099) );
NAND2X1TS U1330 ( .A(n1099), .B(n1485), .Y(n1106) );
OAI22X1TS U1331 ( .A0(n1097), .A1(n1096), .B0(n1098), .B1(n1106), .Y(n1104)
);
NOR2X1TS U1332 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1101)
);
NAND2X1TS U1333 ( .A(n1247), .B(n1098), .Y(n1102) );
OAI21XLTS U1334 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1099), .Y(n1100) );
OAI21X1TS U1335 ( .A0(n1101), .A1(n1102), .B0(n1100), .Y(n1126) );
INVX2TS U1336 ( .A(n1102), .Y(n1248) );
NAND3XLTS U1337 ( .A(n1101), .B(n1248), .C(Raw_mant_NRM_SWR[1]), .Y(n1242)
);
OAI21XLTS U1338 ( .A0(n1486), .A1(n1102), .B0(n1242), .Y(n1103) );
OAI31X1TS U1339 ( .A0(n1104), .A1(n1126), .A2(n1103), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1238) );
NAND3XLTS U1340 ( .A(n1335), .B(Shift_amount_SHT1_EWR[4]), .C(n1336), .Y(
n1105) );
OAI211XLTS U1341 ( .A0(n1297), .A1(n1510), .B0(n1238), .C0(n1105), .Y(n767)
);
INVX2TS U1342 ( .A(n1106), .Y(n1116) );
AOI22X1TS U1343 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1112), .B0(n1246), .B1(
Raw_mant_NRM_SWR[10]), .Y(n1123) );
OAI32X1TS U1344 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1486), .B0(n1511), .B1(Raw_mant_NRM_SWR[3]), .Y(n1107) );
NAND2X1TS U1345 ( .A(Raw_mant_NRM_SWR[12]), .B(n1122), .Y(n1243) );
NAND2X1TS U1346 ( .A(Raw_mant_NRM_SWR[14]), .B(n1109), .Y(n1128) );
AOI32X1TS U1347 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1477), .A2(n1508), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1477), .Y(n1110) );
AOI32X1TS U1348 ( .A0(n1481), .A1(n1128), .A2(n1110), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1128), .Y(n1111) );
AOI31XLTS U1349 ( .A0(n1112), .A1(Raw_mant_NRM_SWR[16]), .A2(n1507), .B0(
n1111), .Y(n1113) );
OAI31X1TS U1350 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1114), .A2(n1478), .B0(
n1113), .Y(n1115) );
NAND2X2TS U1351 ( .A(Shift_reg_FLAGS_7[1]), .B(n1131), .Y(n1282) );
NOR2BX1TS U1352 ( .AN(Shift_amount_SHT1_EWR[0]), .B(Shift_reg_FLAGS_7[1]),
.Y(n1187) );
AOI22X1TS U1353 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1117), .B0(n1279), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1138) );
NOR2XLTS U1354 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1121) );
NOR2X1TS U1355 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1119) );
AOI32X1TS U1356 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1119), .A2(n1118), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1119), .Y(n1120) );
AOI211X1TS U1357 ( .A0(n1121), .A1(n1120), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1127) );
INVX2TS U1358 ( .A(n1122), .Y(n1124) );
OAI31X1TS U1359 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1483), .A2(n1124), .B0(
n1123), .Y(n1125) );
NOR2X1TS U1360 ( .A(n1150), .B(n1336), .Y(n1255) );
AOI21X1TS U1361 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n1336), .B0(n1255), .Y(
n1130) );
NAND2X1TS U1362 ( .A(n1130), .B(n1297), .Y(n1129) );
INVX2TS U1363 ( .A(n1297), .Y(n1201) );
BUFX4TS U1364 ( .A(n1201), .Y(n1294) );
NOR2X2TS U1365 ( .A(n1294), .B(n1130), .Y(n1291) );
NOR2X4TS U1366 ( .A(n1131), .B(n1336), .Y(n1280) );
AOI22X1TS U1367 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1280), .B0(n1279), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1134) );
NOR2XLTS U1368 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n1132) );
AOI22X1TS U1369 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1133) );
NAND2X1TS U1370 ( .A(n1134), .B(n1133), .Y(n1158) );
AOI22X1TS U1371 ( .A0(n1201), .A1(Data_array_SWR[1]), .B0(n1291), .B1(n1158),
.Y(n1137) );
INVX2TS U1372 ( .A(n1135), .Y(n1289) );
NAND2X1TS U1373 ( .A(Raw_mant_NRM_SWR[23]), .B(n1289), .Y(n1136) );
OAI211XLTS U1374 ( .A0(n1138), .A1(n1288), .B0(n1137), .C0(n1136), .Y(n772)
);
AOI22X1TS U1375 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1280), .B0(n1279), .B1(
n901), .Y(n1140) );
AOI22X1TS U1376 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1117), .B0(n1284), .B1(
n897), .Y(n1139) );
NAND2X1TS U1377 ( .A(n1140), .B(n1139), .Y(n1155) );
AOI22X1TS U1378 ( .A0(n1201), .A1(Data_array_SWR[4]), .B0(n1291), .B1(n1155),
.Y(n1142) );
NAND2X1TS U1379 ( .A(Raw_mant_NRM_SWR[20]), .B(n1289), .Y(n1141) );
OAI211XLTS U1380 ( .A0(n1154), .A1(n1288), .B0(n1142), .C0(n1141), .Y(n775)
);
AOI22X1TS U1381 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1280), .B0(n1279), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1144) );
AOI22X1TS U1382 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1117), .B0(n1284), .B1(
n901), .Y(n1143) );
NAND2X1TS U1383 ( .A(n1144), .B(n1143), .Y(n1162) );
AOI22X1TS U1384 ( .A0(n1294), .A1(Data_array_SWR[5]), .B0(n1291), .B1(n1162),
.Y(n1146) );
NAND2X1TS U1385 ( .A(Raw_mant_NRM_SWR[19]), .B(n1289), .Y(n1145) );
OAI211XLTS U1386 ( .A0(n1161), .A1(n1288), .B0(n1146), .C0(n1145), .Y(n776)
);
INVX2TS U1387 ( .A(n1288), .Y(n1163) );
AOI22X1TS U1388 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1280), .B0(n1279), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1149) );
AOI22X1TS U1389 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1117), .B0(n1284), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1148) );
NAND2X1TS U1390 ( .A(n1149), .B(n1148), .Y(n1290) );
AOI22X1TS U1391 ( .A0(n1294), .A1(Data_array_SWR[2]), .B0(n1163), .B1(n1290),
.Y(n1153) );
INVX2TS U1392 ( .A(n1280), .Y(n1192) );
BUFX3TS U1393 ( .A(n1151), .Y(n1210) );
NAND2X1TS U1394 ( .A(Raw_mant_NRM_SWR[20]), .B(n1210), .Y(n1152) );
OAI211XLTS U1395 ( .A0(n1154), .A1(n1147), .B0(n1153), .C0(n1152), .Y(n773)
);
AOI22X1TS U1396 ( .A0(n1201), .A1(Data_array_SWR[6]), .B0(n1163), .B1(n1155),
.Y(n1157) );
NAND2X1TS U1397 ( .A(Raw_mant_NRM_SWR[16]), .B(n1210), .Y(n1156) );
OAI211XLTS U1398 ( .A0(n1179), .A1(n1147), .B0(n1157), .C0(n1156), .Y(n777)
);
AOI22X1TS U1399 ( .A0(n1201), .A1(Data_array_SWR[3]), .B0(n1163), .B1(n1158),
.Y(n1160) );
NAND2X1TS U1400 ( .A(Raw_mant_NRM_SWR[19]), .B(n1210), .Y(n1159) );
OAI211XLTS U1401 ( .A0(n1161), .A1(n1147), .B0(n1160), .C0(n1159), .Y(n774)
);
AOI22X1TS U1402 ( .A0(n1201), .A1(Data_array_SWR[7]), .B0(n1163), .B1(n1162),
.Y(n1165) );
NAND2X1TS U1403 ( .A(Raw_mant_NRM_SWR[15]), .B(n1210), .Y(n1164) );
OAI211XLTS U1404 ( .A0(n1168), .A1(n1147), .B0(n1165), .C0(n1164), .Y(n778)
);
AOI22X1TS U1405 ( .A0(n1201), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1210), .Y(n1167) );
AOI2BB2XLTS U1406 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1289), .A0N(n1205),
.A1N(n1147), .Y(n1166) );
AOI22X1TS U1407 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[21]), .B0(n1279), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1169) );
AOI21X1TS U1408 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1117), .B0(n1170), .Y(n1275) );
OAI22X1TS U1409 ( .A0(n1211), .A1(n1288), .B0(n1553), .B1(n1135), .Y(n1171)
);
AOI21X1TS U1410 ( .A0(n1294), .A1(Data_array_SWR[20]), .B0(n1171), .Y(n1172)
);
OAI21XLTS U1411 ( .A0(n1275), .A1(n1147), .B0(n1172), .Y(n792) );
AOI22X1TS U1412 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1280), .B0(n1279), .B1(n900), .Y(n1173) );
OAI21XLTS U1413 ( .A0(n1513), .A1(n1282), .B0(n1173), .Y(n1174) );
AOI21X1TS U1414 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[18]), .B0(n1174), .Y(
n1191) );
OAI22X1TS U1415 ( .A0(n1184), .A1(n1288), .B0(n1479), .B1(n1135), .Y(n1175)
);
AOI21X1TS U1416 ( .A0(n1294), .A1(Data_array_SWR[17]), .B0(n1175), .Y(n1176)
);
OAI21XLTS U1417 ( .A0(n1191), .A1(n1147), .B0(n1176), .Y(n789) );
AOI22X1TS U1418 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[8]), .B0(n1279), .B1(n899), .Y(n1177) );
OAI21XLTS U1419 ( .A0(n1491), .A1(n1192), .B0(n1177), .Y(n1178) );
AOI21X1TS U1420 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1117), .B0(n1178), .Y(
n1287) );
OAI22X1TS U1421 ( .A0(n1179), .A1(n1288), .B0(n1482), .B1(n1135), .Y(n1180)
);
AOI21X1TS U1422 ( .A0(n1294), .A1(Data_array_SWR[8]), .B0(n1180), .Y(n1181)
);
OAI21XLTS U1423 ( .A0(n1287), .A1(n1147), .B0(n1181), .Y(n779) );
AOI22X1TS U1424 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1280), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1279), .Y(n1182) );
OAI21XLTS U1425 ( .A0(n1480), .A1(n1282), .B0(n1182), .Y(n1183) );
AOI21X1TS U1426 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n1284), .B0(n1183), .Y(
n1278) );
INVX2TS U1427 ( .A(n1210), .Y(n1188) );
OAI22X1TS U1428 ( .A0(n1184), .A1(n1147), .B0(n1479), .B1(n1188), .Y(n1185)
);
AOI21X1TS U1429 ( .A0(n1294), .A1(Data_array_SWR[15]), .B0(n1185), .Y(n1186)
);
OAI21XLTS U1430 ( .A0(n1278), .A1(n1288), .B0(n1186), .Y(n787) );
OAI22X1TS U1431 ( .A0(n1194), .A1(n1147), .B0(n1511), .B1(n1188), .Y(n1189)
);
AOI21X1TS U1432 ( .A0(n1294), .A1(Data_array_SWR[19]), .B0(n1189), .Y(n1190)
);
OAI21XLTS U1433 ( .A0(n1191), .A1(n1288), .B0(n1190), .Y(n791) );
OAI22X1TS U1434 ( .A0(n1556), .A1(n1282), .B0(n1486), .B1(n1192), .Y(n1193)
);
OAI22X1TS U1435 ( .A0(n1273), .A1(n1147), .B0(n1194), .B1(n1288), .Y(n1195)
);
AOI21X1TS U1436 ( .A0(n1294), .A1(Data_array_SWR[21]), .B0(n1195), .Y(n1196)
);
OAI21XLTS U1437 ( .A0(n1511), .A1(n1135), .B0(n1196), .Y(n793) );
AOI22X1TS U1438 ( .A0(n1294), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1210), .Y(n1198) );
OA22X1TS U1439 ( .A0(n1485), .A1(n1135), .B0(n1215), .B1(n1147), .Y(n1197)
);
OAI211XLTS U1440 ( .A0(n1206), .A1(n1288), .B0(n1198), .C0(n1197), .Y(n788)
);
AOI22X1TS U1441 ( .A0(n1294), .A1(Data_array_SWR[12]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1210), .Y(n1200) );
OA22X1TS U1442 ( .A0(n1483), .A1(n1135), .B0(n1209), .B1(n1147), .Y(n1199)
);
OAI211XLTS U1443 ( .A0(n1202), .A1(n1288), .B0(n1200), .C0(n1199), .Y(n784)
);
AOI22X1TS U1444 ( .A0(n1201), .A1(n903), .B0(Raw_mant_NRM_SWR[11]), .B1(
n1210), .Y(n1204) );
OA22X1TS U1445 ( .A0(n1503), .A1(n1135), .B0(n1202), .B1(n1147), .Y(n1203)
);
OAI211XLTS U1446 ( .A0(n1205), .A1(n1288), .B0(n1204), .C0(n1203), .Y(n782)
);
AOI22X1TS U1447 ( .A0(n1294), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1210), .Y(n1208) );
OA22X1TS U1448 ( .A0(n1480), .A1(n1135), .B0(n1206), .B1(n1147), .Y(n1207)
);
OAI211XLTS U1449 ( .A0(n1209), .A1(n1288), .B0(n1208), .C0(n1207), .Y(n786)
);
AOI22X1TS U1450 ( .A0(n1294), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1210), .Y(n1214) );
OA22X1TS U1451 ( .A0(n1513), .A1(n1135), .B0(n1211), .B1(n1147), .Y(n1213)
);
OAI211XLTS U1452 ( .A0(n1215), .A1(n1288), .B0(n1214), .C0(n1213), .Y(n790)
);
BUFX4TS U1453 ( .A(OP_FLAG_SFG), .Y(n1351) );
CLKBUFX2TS U1454 ( .A(OP_FLAG_SFG), .Y(n1355) );
AOI22X1TS U1455 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n1351), .B0(n1354), .B1(n913), .Y(n1340) );
NAND2X1TS U1456 ( .A(n1340), .B(DMP_SFG[0]), .Y(n1342) );
INVX2TS U1457 ( .A(n1342), .Y(n1216) );
INVX2TS U1458 ( .A(n1217), .Y(n1227) );
AND4X1TS U1459 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1218), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1219) );
NAND3XLTS U1460 ( .A(n1220), .B(exp_rslt_NRM2_EW1[4]), .C(n1219), .Y(n1221)
);
NAND2BXLTS U1461 ( .AN(n1221), .B(n1256), .Y(n1222) );
NOR2XLTS U1462 ( .A(n1227), .B(n1222), .Y(n1226) );
INVX2TS U1463 ( .A(n1223), .Y(n1224) );
CLKAND2X2TS U1464 ( .A(n1561), .B(n1224), .Y(n1225) );
OAI2BB2XLTS U1465 ( .B0(n1360), .B1(n1227), .A0N(final_result_ieee[30]),
.A1N(n1420), .Y(n754) );
INVX2TS U1466 ( .A(n1228), .Y(n1361) );
NOR2XLTS U1467 ( .A(n1361), .B(SIGN_FLAG_SHT1SHT2), .Y(n1229) );
OAI2BB2XLTS U1468 ( .B0(n1229), .B1(n1360), .A0N(n1420), .A1N(
final_result_ieee[31]), .Y(n543) );
AOI22X1TS U1469 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n1354), .B0(n1351), .B1(n918), .Y(intadd_30_B_0_) );
AOI21X1TS U1470 ( .A0(intadd_30_A_1_), .A1(intadd_30_B_1_), .B0(
intadd_30_B_0_), .Y(n1230) );
AOI2BB2X1TS U1471 ( .B0(DMP_SFG[2]), .B1(n1230), .A0N(intadd_30_A_1_), .A1N(
intadd_30_B_1_), .Y(n1231) );
AOI222X1TS U1472 ( .A0(n1231), .A1(intadd_30_A_2_), .B0(n1231), .B1(n895),
.C0(intadd_30_A_2_), .C1(n895), .Y(n1232) );
AOI22X1TS U1473 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n1352), .B0(n1351), .B1(n907), .Y(intadd_29_B_0_) );
AOI21X1TS U1474 ( .A0(intadd_29_A_1_), .A1(intadd_29_B_1_), .B0(
intadd_29_B_0_), .Y(n1233) );
AOI2BB2X1TS U1475 ( .B0(DMP_SFG[6]), .B1(n1233), .A0N(intadd_29_A_1_), .A1N(
intadd_29_B_1_), .Y(n1234) );
AOI222X1TS U1476 ( .A0(n1234), .A1(intadd_29_A_2_), .B0(n1234), .B1(
intadd_29_B_2_), .C0(intadd_29_A_2_), .C1(intadd_29_B_2_), .Y(n1235)
);
INVX2TS U1477 ( .A(n1236), .Y(n1237) );
NAND2X1TS U1478 ( .A(n1515), .B(n1237), .Y(DP_OP_15J31_123_3372_n8) );
MX2X1TS U1479 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n611) );
MX2X1TS U1480 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n616) );
MX2X1TS U1481 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n621) );
MX2X1TS U1482 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n626) );
MX2X1TS U1483 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n631) );
MX2X1TS U1484 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n636) );
MX2X1TS U1485 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n641) );
MX2X1TS U1486 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n646) );
OAI2BB1X1TS U1487 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1336), .B0(n1238),
.Y(n512) );
OAI32X1TS U1488 ( .A0(n1336), .A1(Raw_mant_NRM_SWR[14]), .A2(n1240), .B0(
n1239), .B1(n1336), .Y(n1244) );
AO21XLTS U1489 ( .A0(n1483), .A1(n1503), .B0(n1241), .Y(n1249) );
NAND4XLTS U1490 ( .A(n1244), .B(n1243), .C(n1242), .D(n1249), .Y(n1245) );
AOI21X1TS U1491 ( .A0(n1246), .A1(Raw_mant_NRM_SWR[10]), .B0(n1245), .Y(
n1299) );
AOI2BB1XLTS U1492 ( .A0N(Shift_reg_FLAGS_7[1]), .A1N(LZD_output_NRM2_EW[3]),
.B0(n1299), .Y(n516) );
AOI22X1TS U1493 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1248), .B0(n1247), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1250) );
OAI211XLTS U1494 ( .A0(n1252), .A1(n1251), .B0(n1250), .C0(n1249), .Y(n1253)
);
OAI21X1TS U1495 ( .A0(n1254), .A1(n1253), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1295) );
OAI2BB1X1TS U1496 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1336), .B0(n1295),
.Y(n514) );
AO21XLTS U1497 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1336), .B0(n1255), .Y(n513) );
AO21XLTS U1498 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1336), .B0(n1280), .Y(n515) );
OA22X1TS U1499 ( .A0(n1257), .A1(n1256), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n755) );
OA21XLTS U1500 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1360),
.Y(n558) );
INVX2TS U1501 ( .A(n1261), .Y(n1259) );
AOI22X1TS U1502 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1259), .B1(n1495), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1503 ( .A(n1259), .B(n1258), .Y(n871) );
NOR2XLTS U1504 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1260) );
AOI32X4TS U1505 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1260), .B1(n1524), .Y(n1264)
);
INVX2TS U1506 ( .A(n1264), .Y(n1263) );
AOI22X1TS U1507 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1261), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1495), .Y(n1265) );
AO22XLTS U1508 ( .A0(n1263), .A1(Shift_reg_FLAGS_7_6), .B0(n1264), .B1(n1265), .Y(n869) );
AOI22X1TS U1509 ( .A0(n1264), .A1(n1262), .B0(n1333), .B1(n1263), .Y(n868)
);
AOI22X1TS U1510 ( .A0(n1264), .A1(n1331), .B0(n1574), .B1(n1263), .Y(n867)
);
AOI22X1TS U1511 ( .A0(n1264), .A1(n1603), .B0(n1336), .B1(n1263), .Y(n864)
);
AOI22X1TS U1512 ( .A0(n1264), .A1(n1336), .B0(n1420), .B1(n1263), .Y(n863)
);
AO22XLTS U1513 ( .A0(n1267), .A1(Data_X[0]), .B0(n1266), .B1(n904), .Y(n862)
);
AO22XLTS U1514 ( .A0(n1270), .A1(Data_X[1]), .B0(n1272), .B1(intDX_EWSW[1]),
.Y(n861) );
AO22XLTS U1515 ( .A0(n1270), .A1(Data_X[2]), .B0(n1268), .B1(n906), .Y(n860)
);
AO22XLTS U1516 ( .A0(n1267), .A1(Data_X[3]), .B0(n1272), .B1(intDX_EWSW[3]),
.Y(n859) );
AO22XLTS U1517 ( .A0(n1267), .A1(Data_X[4]), .B0(n1266), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1518 ( .A0(n1267), .A1(Data_X[5]), .B0(n1268), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1519 ( .A0(n1269), .A1(Data_X[6]), .B0(n1268), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1520 ( .A0(n1269), .A1(Data_X[7]), .B0(n1266), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1521 ( .A0(n1270), .A1(Data_X[8]), .B0(n1268), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1522 ( .A0(n1267), .A1(Data_X[9]), .B0(n1268), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1523 ( .A0(n1269), .A1(Data_X[10]), .B0(n1268), .B1(n905), .Y(n852) );
AO22XLTS U1524 ( .A0(n1267), .A1(Data_X[11]), .B0(n1268), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1525 ( .A0(n1269), .A1(Data_X[12]), .B0(n1266), .B1(intDX_EWSW[12]), .Y(n850) );
AO22XLTS U1526 ( .A0(n1270), .A1(Data_X[13]), .B0(n1268), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1527 ( .A0(n1270), .A1(Data_X[14]), .B0(n1266), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1528 ( .A0(n1267), .A1(Data_X[15]), .B0(n1272), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1529 ( .A0(n1270), .A1(Data_X[16]), .B0(n1272), .B1(intDX_EWSW[16]), .Y(n846) );
AO22XLTS U1530 ( .A0(n1269), .A1(Data_X[17]), .B0(n1272), .B1(intDX_EWSW[17]), .Y(n845) );
AO22XLTS U1531 ( .A0(n1269), .A1(Data_X[18]), .B0(n1272), .B1(intDX_EWSW[18]), .Y(n844) );
AO22XLTS U1532 ( .A0(n1269), .A1(Data_X[20]), .B0(n1272), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1533 ( .A0(n1270), .A1(Data_X[21]), .B0(n1272), .B1(intDX_EWSW[21]), .Y(n841) );
AO22XLTS U1534 ( .A0(n1267), .A1(Data_X[22]), .B0(n1272), .B1(intDX_EWSW[22]), .Y(n840) );
AO22XLTS U1535 ( .A0(n1269), .A1(Data_X[23]), .B0(n1272), .B1(intDX_EWSW[23]), .Y(n839) );
AO22XLTS U1536 ( .A0(n1268), .A1(intDX_EWSW[24]), .B0(n1269), .B1(Data_X[24]), .Y(n838) );
AO22XLTS U1537 ( .A0(n1268), .A1(intDX_EWSW[25]), .B0(n920), .B1(Data_X[25]),
.Y(n837) );
AO22XLTS U1538 ( .A0(n1266), .A1(intDX_EWSW[26]), .B0(n1269), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1539 ( .A0(n1270), .A1(Data_X[27]), .B0(n1272), .B1(intDX_EWSW[27]), .Y(n835) );
AO22XLTS U1540 ( .A0(n1270), .A1(Data_X[28]), .B0(n1268), .B1(intDX_EWSW[28]), .Y(n834) );
AO22XLTS U1541 ( .A0(n1270), .A1(Data_X[29]), .B0(n1272), .B1(intDX_EWSW[29]), .Y(n833) );
AO22XLTS U1542 ( .A0(n1270), .A1(Data_X[30]), .B0(n1268), .B1(intDX_EWSW[30]), .Y(n832) );
AO22XLTS U1543 ( .A0(n1269), .A1(add_subt), .B0(n1266), .B1(intAS), .Y(n830)
);
AO22XLTS U1544 ( .A0(n1268), .A1(intDY_EWSW[0]), .B0(n1269), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1545 ( .A0(n1266), .A1(intDY_EWSW[1]), .B0(n1269), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1546 ( .A0(n1268), .A1(intDY_EWSW[2]), .B0(n1267), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1547 ( .A0(n1268), .A1(intDY_EWSW[3]), .B0(n1267), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1548 ( .A0(n1266), .A1(intDY_EWSW[4]), .B0(n1269), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1549 ( .A0(n1268), .A1(intDY_EWSW[5]), .B0(n1270), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1550 ( .A0(n1268), .A1(intDY_EWSW[6]), .B0(n1270), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1551 ( .A0(n1266), .A1(intDY_EWSW[7]), .B0(n1267), .B1(Data_Y[7]),
.Y(n821) );
INVX4TS U1552 ( .A(n920), .Y(n1271) );
AO22XLTS U1553 ( .A0(n1271), .A1(intDY_EWSW[8]), .B0(n1267), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1554 ( .A0(n1268), .A1(intDY_EWSW[9]), .B0(n1270), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1555 ( .A0(n1268), .A1(intDY_EWSW[10]), .B0(n1270), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1556 ( .A0(n1268), .A1(intDY_EWSW[11]), .B0(n1270), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1557 ( .A0(n1271), .A1(intDY_EWSW[12]), .B0(n1270), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1558 ( .A0(n1271), .A1(intDY_EWSW[13]), .B0(n1270), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1559 ( .A0(n1271), .A1(intDY_EWSW[14]), .B0(n1270), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1560 ( .A0(n1268), .A1(intDY_EWSW[15]), .B0(n1270), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1561 ( .A0(n1266), .A1(intDY_EWSW[16]), .B0(n920), .B1(Data_Y[16]),
.Y(n812) );
AO22XLTS U1562 ( .A0(n1271), .A1(intDY_EWSW[17]), .B0(n1267), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1563 ( .A0(n1271), .A1(intDY_EWSW[18]), .B0(n1269), .B1(Data_Y[18]), .Y(n810) );
AO22XLTS U1564 ( .A0(n1271), .A1(intDY_EWSW[19]), .B0(n920), .B1(Data_Y[19]),
.Y(n809) );
AO22XLTS U1565 ( .A0(n1271), .A1(intDY_EWSW[20]), .B0(n920), .B1(Data_Y[20]),
.Y(n808) );
AO22XLTS U1566 ( .A0(n1271), .A1(intDY_EWSW[21]), .B0(n920), .B1(Data_Y[21]),
.Y(n807) );
AO22XLTS U1567 ( .A0(n1271), .A1(intDY_EWSW[22]), .B0(n1267), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1568 ( .A0(n1271), .A1(intDY_EWSW[23]), .B0(n1269), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1569 ( .A0(n1271), .A1(intDY_EWSW[24]), .B0(n1270), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1570 ( .A0(n1271), .A1(intDY_EWSW[25]), .B0(n1267), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1571 ( .A0(n1271), .A1(intDY_EWSW[26]), .B0(n1269), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1572 ( .A0(n1271), .A1(intDY_EWSW[27]), .B0(n1267), .B1(Data_Y[27]), .Y(n801) );
AO22XLTS U1573 ( .A0(n1271), .A1(intDY_EWSW[28]), .B0(n1269), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1574 ( .A0(n1271), .A1(intDY_EWSW[29]), .B0(n1270), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1575 ( .A0(n1271), .A1(intDY_EWSW[30]), .B0(n1267), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1576 ( .A0(n1270), .A1(Data_Y[31]), .B0(n1268), .B1(intDY_EWSW[31]), .Y(n797) );
AOI21X1TS U1577 ( .A0(n1117), .A1(Raw_mant_NRM_SWR[0]), .B0(n1284), .Y(n1274) );
OAI2BB2XLTS U1578 ( .B0(n1274), .B1(n1288), .A0N(n1294), .A1N(
Data_array_SWR[24]), .Y(n796) );
OAI2BB2XLTS U1579 ( .B0(n1273), .B1(n1288), .A0N(n1294), .A1N(
Data_array_SWR[23]), .Y(n795) );
AOI22X1TS U1580 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1280), .B0(n1279), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1276) );
OAI21XLTS U1581 ( .A0(n1483), .A1(n1282), .B0(n1276), .Y(n1277) );
AOI21X1TS U1582 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[12]), .B0(n1277), .Y(
n1285) );
AOI22X1TS U1583 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1280), .B0(n1279), .B1(
n898), .Y(n1281) );
OAI21XLTS U1584 ( .A0(n1503), .A1(n1282), .B0(n1281), .Y(n1283) );
AOI21X1TS U1585 ( .A0(n1284), .A1(DmP_mant_SHT1_SW[10]), .B0(n1283), .Y(
n1286) );
AOI22X1TS U1586 ( .A0(n1294), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1289), .Y(n1293) );
AOI22X1TS U1587 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1117), .B0(n1291), .B1(
n1290), .Y(n1292) );
NAND2X1TS U1588 ( .A(n1293), .B(n1292), .Y(n771) );
NAND2X1TS U1589 ( .A(n1296), .B(n1295), .Y(n770) );
AOI21X1TS U1590 ( .A0(n1335), .A1(Shift_amount_SHT1_EWR[3]), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1298) );
OAI22X1TS U1591 ( .A0(n1299), .A1(n1298), .B0(n1297), .B1(n1512), .Y(n769)
);
INVX4TS U1592 ( .A(n1323), .Y(n1329) );
CLKINVX1TS U1593 ( .A(DmP_EXP_EWSW[23]), .Y(n1300) );
AOI21X1TS U1594 ( .A0(DMP_EXP_EWSW[23]), .A1(n1300), .B0(n1305), .Y(n1301)
);
AOI2BB2XLTS U1595 ( .B0(n1329), .B1(n1301), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1488), .Y(n766) );
NOR2X1TS U1596 ( .A(n1501), .B(DMP_EXP_EWSW[24]), .Y(n1304) );
AOI21X1TS U1597 ( .A0(DMP_EXP_EWSW[24]), .A1(n1501), .B0(n1304), .Y(n1302)
);
XNOR2X1TS U1598 ( .A(n1305), .B(n1302), .Y(n1303) );
AO22XLTS U1599 ( .A0(n1488), .A1(n1303), .B0(n1331), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
OAI22X1TS U1600 ( .A0(n1305), .A1(n1304), .B0(DmP_EXP_EWSW[24]), .B1(n1502),
.Y(n1308) );
NAND2X1TS U1601 ( .A(DmP_EXP_EWSW[25]), .B(n1557), .Y(n1309) );
OAI21XLTS U1602 ( .A0(DmP_EXP_EWSW[25]), .A1(n1557), .B0(n1309), .Y(n1306)
);
XNOR2X1TS U1603 ( .A(n1308), .B(n1306), .Y(n1307) );
AO22XLTS U1604 ( .A0(n1488), .A1(n1307), .B0(n1333), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AOI22X1TS U1605 ( .A0(DMP_EXP_EWSW[25]), .A1(n1569), .B0(n1309), .B1(n1308),
.Y(n1312) );
NOR2X1TS U1606 ( .A(n1564), .B(DMP_EXP_EWSW[26]), .Y(n1313) );
AOI21X1TS U1607 ( .A0(DMP_EXP_EWSW[26]), .A1(n1564), .B0(n1313), .Y(n1310)
);
XNOR2X1TS U1608 ( .A(n1312), .B(n1310), .Y(n1311) );
AO22XLTS U1609 ( .A0(n1488), .A1(n1311), .B0(n1323), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
OAI22X1TS U1610 ( .A0(n1313), .A1(n1312), .B0(DmP_EXP_EWSW[26]), .B1(n1568),
.Y(n1315) );
XNOR2X1TS U1611 ( .A(DmP_EXP_EWSW[27]), .B(n902), .Y(n1314) );
XOR2XLTS U1612 ( .A(n1315), .B(n1314), .Y(n1316) );
AO22XLTS U1613 ( .A0(n1488), .A1(n1316), .B0(n1333), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
OAI222X1TS U1614 ( .A0(n1324), .A1(n1567), .B0(n1502), .B1(
Shift_reg_FLAGS_7_6), .C0(n1487), .C1(n1326), .Y(n729) );
OAI222X1TS U1615 ( .A0(n1324), .A1(n1504), .B0(n1557), .B1(
Shift_reg_FLAGS_7_6), .C0(n1545), .C1(n1326), .Y(n728) );
OAI222X1TS U1616 ( .A0(n1324), .A1(n1505), .B0(n1568), .B1(
Shift_reg_FLAGS_7_6), .C0(n1550), .C1(n1326), .Y(n727) );
OAI21XLTS U1617 ( .A0(n1318), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1317) );
AOI21X1TS U1618 ( .A0(n1318), .A1(intDX_EWSW[31]), .B0(n1317), .Y(n1319) );
AO21XLTS U1619 ( .A0(OP_FLAG_EXP), .A1(n997), .B0(n1319), .Y(n722) );
AO22XLTS U1620 ( .A0(n1320), .A1(n1319), .B0(ZERO_FLAG_EXP), .B1(n997), .Y(
n721) );
AO22XLTS U1621 ( .A0(n1488), .A1(DMP_EXP_EWSW[0]), .B0(n1333), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1622 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1574), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
NAND2X1TS U1623 ( .A(n896), .B(n1420), .Y(n1321) );
INVX4TS U1624 ( .A(n1454), .Y(n1451) );
AO22XLTS U1625 ( .A0(n1488), .A1(DMP_EXP_EWSW[1]), .B0(n1331), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1626 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1574), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1627 ( .A0(n1488), .A1(DMP_EXP_EWSW[2]), .B0(n1323), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1628 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1574), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
INVX4TS U1629 ( .A(n1454), .Y(n1453) );
AO22XLTS U1630 ( .A0(n1454), .A1(DMP_SFG[2]), .B0(n1453), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1631 ( .A0(n1332), .A1(DMP_EXP_EWSW[3]), .B0(n1331), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1632 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1574), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1633 ( .A0(n1454), .A1(DMP_SFG[3]), .B0(n1453), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1634 ( .A0(n1332), .A1(DMP_EXP_EWSW[4]), .B0(n1333), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1635 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1574), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1636 ( .A0(n1454), .A1(DMP_SFG[4]), .B0(n1453), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
AO22XLTS U1637 ( .A0(n1332), .A1(DMP_EXP_EWSW[5]), .B0(n1331), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1638 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1574), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1639 ( .A0(n1471), .A1(DMP_SHT2_EWSW[5]), .B0(n1469), .B1(
DMP_SFG[5]), .Y(n702) );
AO22XLTS U1640 ( .A0(n1332), .A1(DMP_EXP_EWSW[6]), .B0(n1323), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1641 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1574), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
BUFX3TS U1642 ( .A(n1454), .Y(n1447) );
AO22XLTS U1643 ( .A0(n1447), .A1(DMP_SFG[6]), .B0(n1453), .B1(
DMP_SHT2_EWSW[6]), .Y(n699) );
AO22XLTS U1644 ( .A0(n1332), .A1(DMP_EXP_EWSW[7]), .B0(n1333), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1645 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1574), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1646 ( .A0(n1454), .A1(DMP_SFG[7]), .B0(n1453), .B1(
DMP_SHT2_EWSW[7]), .Y(n696) );
AO22XLTS U1647 ( .A0(n1332), .A1(DMP_EXP_EWSW[8]), .B0(n1331), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1648 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1574), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1649 ( .A0(n1454), .A1(DMP_SFG[8]), .B0(n1453), .B1(
DMP_SHT2_EWSW[8]), .Y(n693) );
AO22XLTS U1650 ( .A0(n1332), .A1(DMP_EXP_EWSW[9]), .B0(n1331), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1651 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1574), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1652 ( .A0(n1471), .A1(DMP_SHT2_EWSW[9]), .B0(n1469), .B1(
DMP_SFG[9]), .Y(n690) );
AO22XLTS U1653 ( .A0(n1332), .A1(DMP_EXP_EWSW[10]), .B0(n1333), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
BUFX4TS U1654 ( .A(n1574), .Y(n1330) );
AO22XLTS U1655 ( .A0(n1335), .A1(DMP_SHT1_EWSW[10]), .B0(n1330), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1656 ( .A0(n1454), .A1(DMP_SFG[10]), .B0(n1451), .B1(
DMP_SHT2_EWSW[10]), .Y(n687) );
BUFX4TS U1657 ( .A(n1571), .Y(n1333) );
AO22XLTS U1658 ( .A0(n1332), .A1(DMP_EXP_EWSW[11]), .B0(n1571), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1659 ( .A0(n1335), .A1(DMP_SHT1_EWSW[11]), .B0(n1330), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1660 ( .A0(n1447), .A1(DMP_SFG[11]), .B0(n1453), .B1(
DMP_SHT2_EWSW[11]), .Y(n684) );
AO22XLTS U1661 ( .A0(n1332), .A1(DMP_EXP_EWSW[12]), .B0(n1331), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1662 ( .A0(n1335), .A1(DMP_SHT1_EWSW[12]), .B0(n1330), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1663 ( .A0(n1454), .A1(DMP_SFG[12]), .B0(n1453), .B1(
DMP_SHT2_EWSW[12]), .Y(n681) );
AO22XLTS U1664 ( .A0(n1332), .A1(DMP_EXP_EWSW[13]), .B0(n1333), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1665 ( .A0(n1335), .A1(DMP_SHT1_EWSW[13]), .B0(n1330), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1666 ( .A0(n1447), .A1(DMP_SFG[13]), .B0(n1453), .B1(
DMP_SHT2_EWSW[13]), .Y(n678) );
AO22XLTS U1667 ( .A0(n1332), .A1(DMP_EXP_EWSW[14]), .B0(n1331), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1668 ( .A0(n1335), .A1(DMP_SHT1_EWSW[14]), .B0(n1330), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1669 ( .A0(n1454), .A1(DMP_SFG[14]), .B0(n1453), .B1(
DMP_SHT2_EWSW[14]), .Y(n675) );
AO22XLTS U1670 ( .A0(n1332), .A1(DMP_EXP_EWSW[15]), .B0(n1571), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1671 ( .A0(n1335), .A1(DMP_SHT1_EWSW[15]), .B0(n1330), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1672 ( .A0(n1447), .A1(DMP_SFG[15]), .B0(n1453), .B1(
DMP_SHT2_EWSW[15]), .Y(n672) );
AO22XLTS U1673 ( .A0(n1332), .A1(DMP_EXP_EWSW[16]), .B0(n1331), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1674 ( .A0(n1335), .A1(DMP_SHT1_EWSW[16]), .B0(n1330), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1675 ( .A0(n1454), .A1(DMP_SFG[16]), .B0(n1451), .B1(
DMP_SHT2_EWSW[16]), .Y(n669) );
INVX4TS U1676 ( .A(n1323), .Y(n1334) );
AO22XLTS U1677 ( .A0(n1334), .A1(DMP_EXP_EWSW[17]), .B0(n1333), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1678 ( .A0(n1335), .A1(DMP_SHT1_EWSW[17]), .B0(n1330), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1679 ( .A0(n1447), .A1(DMP_SFG[17]), .B0(n1453), .B1(
DMP_SHT2_EWSW[17]), .Y(n666) );
AO22XLTS U1680 ( .A0(n1334), .A1(DMP_EXP_EWSW[18]), .B0(n1331), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1681 ( .A0(n1335), .A1(DMP_SHT1_EWSW[18]), .B0(n1330), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1682 ( .A0(n1454), .A1(DMP_SFG[18]), .B0(n1451), .B1(
DMP_SHT2_EWSW[18]), .Y(n663) );
BUFX4TS U1683 ( .A(n1571), .Y(n1323) );
AO22XLTS U1684 ( .A0(n1334), .A1(DMP_EXP_EWSW[19]), .B0(n1333), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1685 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1330), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1686 ( .A0(n1447), .A1(DMP_SFG[19]), .B0(n1453), .B1(
DMP_SHT2_EWSW[19]), .Y(n660) );
AO22XLTS U1687 ( .A0(n1334), .A1(DMP_EXP_EWSW[20]), .B0(n1323), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1688 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1330), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1689 ( .A0(n1447), .A1(DMP_SFG[20]), .B0(n1451), .B1(
DMP_SHT2_EWSW[20]), .Y(n657) );
AO22XLTS U1690 ( .A0(n1334), .A1(DMP_EXP_EWSW[21]), .B0(n1333), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1691 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1330), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1692 ( .A0(n1447), .A1(DMP_SFG[21]), .B0(n1451), .B1(
DMP_SHT2_EWSW[21]), .Y(n654) );
AO22XLTS U1693 ( .A0(n1334), .A1(DMP_EXP_EWSW[22]), .B0(n1333), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1694 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n1574), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1695 ( .A0(n1447), .A1(DMP_SFG[22]), .B0(n1451), .B1(
DMP_SHT2_EWSW[22]), .Y(n651) );
AO22XLTS U1696 ( .A0(n1334), .A1(DMP_EXP_EWSW[23]), .B0(n1331), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1697 ( .A0(n1335), .A1(DMP_SHT1_EWSW[23]), .B0(n1574), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1698 ( .A0(n1471), .A1(DMP_SHT2_EWSW[23]), .B0(n1447), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1699 ( .A0(n873), .A1(DMP_SFG[23]), .B0(n1603), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1700 ( .A0(n1334), .A1(DMP_EXP_EWSW[24]), .B0(n1323), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1701 ( .A0(n1335), .A1(DMP_SHT1_EWSW[24]), .B0(n1330), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1702 ( .A0(n1451), .A1(DMP_SHT2_EWSW[24]), .B0(n1469), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1703 ( .A0(n873), .A1(DMP_SFG[24]), .B0(n1603), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1704 ( .A0(n1334), .A1(DMP_EXP_EWSW[25]), .B0(n1331), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1705 ( .A0(n1335), .A1(DMP_SHT1_EWSW[25]), .B0(n1330), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1706 ( .A0(n1471), .A1(DMP_SHT2_EWSW[25]), .B0(n1469), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1707 ( .A0(n873), .A1(DMP_SFG[25]), .B0(n1603), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1708 ( .A0(n1334), .A1(DMP_EXP_EWSW[26]), .B0(n1333), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1709 ( .A0(n1335), .A1(DMP_SHT1_EWSW[26]), .B0(n1330), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1710 ( .A0(n1471), .A1(DMP_SHT2_EWSW[26]), .B0(n1454), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1711 ( .A0(n873), .A1(DMP_SFG[26]), .B0(n1603), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1712 ( .A0(n1334), .A1(n902), .B0(n1331), .B1(DMP_SHT1_EWSW[27]),
.Y(n630) );
AO22XLTS U1713 ( .A0(n1335), .A1(DMP_SHT1_EWSW[27]), .B0(n1330), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1714 ( .A0(n1451), .A1(DMP_SHT2_EWSW[27]), .B0(n1469), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1715 ( .A0(n873), .A1(DMP_SFG[27]), .B0(n1357), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1716 ( .A0(n1334), .A1(DMP_EXP_EWSW[28]), .B0(n1571), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1717 ( .A0(n1335), .A1(DMP_SHT1_EWSW[28]), .B0(n1330), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1718 ( .A0(n1451), .A1(DMP_SHT2_EWSW[28]), .B0(n1454), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1719 ( .A0(n873), .A1(DMP_SFG[28]), .B0(n1357), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1720 ( .A0(n1334), .A1(DMP_EXP_EWSW[29]), .B0(n1333), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1721 ( .A0(n1335), .A1(DMP_SHT1_EWSW[29]), .B0(n1330), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1722 ( .A0(n1471), .A1(DMP_SHT2_EWSW[29]), .B0(n1469), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1723 ( .A0(n1359), .A1(DMP_SFG[29]), .B0(n1357), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1724 ( .A0(n1329), .A1(DMP_EXP_EWSW[30]), .B0(n1331), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1725 ( .A0(n1335), .A1(DMP_SHT1_EWSW[30]), .B0(n1330), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1726 ( .A0(n1451), .A1(DMP_SHT2_EWSW[30]), .B0(n1469), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1727 ( .A0(n1359), .A1(DMP_SFG[30]), .B0(n1357), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1728 ( .A0(n1332), .A1(DmP_EXP_EWSW[14]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U1729 ( .A0(n1332), .A1(DmP_EXP_EWSW[17]), .B0(n1323), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
AO22XLTS U1730 ( .A0(n1332), .A1(DmP_EXP_EWSW[19]), .B0(n1571), .B1(n900),
.Y(n571) );
AO22XLTS U1731 ( .A0(n1332), .A1(DmP_EXP_EWSW[22]), .B0(n1333), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
OAI222X1TS U1732 ( .A0(n1326), .A1(n1567), .B0(n1501), .B1(
Shift_reg_FLAGS_7_6), .C0(n1487), .C1(n1324), .Y(n563) );
OAI222X1TS U1733 ( .A0(n1326), .A1(n1504), .B0(n1569), .B1(
Shift_reg_FLAGS_7_6), .C0(n1545), .C1(n1324), .Y(n562) );
OAI222X1TS U1734 ( .A0(n1326), .A1(n1505), .B0(n1564), .B1(
Shift_reg_FLAGS_7_6), .C0(n1550), .C1(n1324), .Y(n561) );
INVX4TS U1735 ( .A(n1327), .Y(n1424) );
NAND2X1TS U1736 ( .A(n1361), .B(Shift_reg_FLAGS_7[0]), .Y(n1328) );
OAI2BB1X1TS U1737 ( .A0N(underflow_flag), .A1N(n1424), .B0(n1328), .Y(n559)
);
AO22XLTS U1738 ( .A0(n1329), .A1(ZERO_FLAG_EXP), .B0(n1323), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
AO22XLTS U1739 ( .A0(n1335), .A1(ZERO_FLAG_SHT1), .B0(n1330), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1740 ( .A0(n1451), .A1(ZERO_FLAG_SHT2), .B0(n1469), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1741 ( .A0(n873), .A1(ZERO_FLAG_SFG), .B0(n1357), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1742 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n1336),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1743 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1424), .B1(zero_flag), .Y(n552) );
AO22XLTS U1744 ( .A0(n1332), .A1(OP_FLAG_EXP), .B0(n1331), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1745 ( .A0(n1335), .A1(OP_FLAG_SHT1), .B0(n1574), .B1(OP_FLAG_SHT2), .Y(n550) );
AO22XLTS U1746 ( .A0(n1447), .A1(OP_FLAG_SFG), .B0(n1451), .B1(OP_FLAG_SHT2),
.Y(n549) );
AO22XLTS U1747 ( .A0(n1334), .A1(SIGN_FLAG_EXP), .B0(n1331), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1748 ( .A0(n1335), .A1(SIGN_FLAG_SHT1), .B0(n1574), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1749 ( .A0(n1451), .A1(SIGN_FLAG_SHT2), .B0(n1454), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1750 ( .A0(n873), .A1(SIGN_FLAG_SFG), .B0(n1357), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1751 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n1336),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n544) );
AOI22X1TS U1752 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n1352), .B0(n1355), .B1(n911), .Y(n1338) );
AOI22X1TS U1753 ( .A0(n1359), .A1(n1338), .B0(n1486), .B1(n1357), .Y(n542)
);
AOI22X1TS U1754 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n1354), .B0(n1351), .B1(n912), .Y(n1339) );
AOI22X1TS U1755 ( .A0(n1359), .A1(n1339), .B0(n1556), .B1(n1357), .Y(n541)
);
OAI21XLTS U1756 ( .A0(n1340), .A1(DMP_SFG[0]), .B0(n1342), .Y(n1341) );
AOI22X1TS U1757 ( .A0(n1359), .A1(n1341), .B0(n1511), .B1(n1357), .Y(n540)
);
XNOR2X1TS U1758 ( .A(DMP_SFG[1]), .B(n1342), .Y(n1343) );
XNOR2X1TS U1759 ( .A(n1343), .B(n893), .Y(n1344) );
AOI22X1TS U1760 ( .A0(n1359), .A1(n1344), .B0(n1553), .B1(n1603), .Y(n539)
);
AOI2BB2XLTS U1761 ( .B0(n873), .B1(intadd_30_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n873), .Y(n538) );
AOI22X1TS U1762 ( .A0(n1359), .A1(intadd_30_SUM_1_), .B0(n1513), .B1(n1357),
.Y(n537) );
AOI22X1TS U1763 ( .A0(n1359), .A1(intadd_30_SUM_2_), .B0(n1479), .B1(n1357),
.Y(n536) );
XNOR2X1TS U1764 ( .A(DMP_SFG[5]), .B(n894), .Y(n1345) );
XNOR2X1TS U1765 ( .A(intadd_30_n1), .B(n1345), .Y(n1346) );
AOI22X1TS U1766 ( .A0(n1359), .A1(n1346), .B0(n1485), .B1(n1357), .Y(n535)
);
AOI22X1TS U1767 ( .A0(n1359), .A1(intadd_29_SUM_0_), .B0(n1478), .B1(n1357),
.Y(n534) );
AOI22X1TS U1768 ( .A0(n1359), .A1(intadd_29_SUM_1_), .B0(n1480), .B1(n1357),
.Y(n533) );
AOI22X1TS U1769 ( .A0(n1359), .A1(intadd_29_SUM_2_), .B0(n1484), .B1(n1357),
.Y(n532) );
XNOR2X1TS U1770 ( .A(DMP_SFG[9]), .B(n1347), .Y(n1348) );
XNOR2X1TS U1771 ( .A(intadd_29_n1), .B(n1348), .Y(n1349) );
AOI22X1TS U1772 ( .A0(n1359), .A1(n1349), .B0(n1483), .B1(n1357), .Y(n531)
);
AOI2BB2XLTS U1773 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1354), .A0N(n1493),
.A1N(DmP_mant_SFG_SWR[12]), .Y(intadd_28_CI) );
AOI2BB2XLTS U1774 ( .B0(n873), .B1(intadd_28_SUM_0_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n873), .Y(n530) );
AOI2BB2XLTS U1775 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1354), .A0N(n1493),
.A1N(DmP_mant_SFG_SWR[13]), .Y(intadd_28_B_1_) );
AOI22X1TS U1776 ( .A0(n1359), .A1(intadd_28_SUM_1_), .B0(n1503), .B1(n1357),
.Y(n529) );
AOI2BB2XLTS U1777 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n1354), .A0N(n1493),
.A1N(DmP_mant_SFG_SWR[14]), .Y(intadd_28_B_2_) );
AOI22X1TS U1778 ( .A0(n1359), .A1(intadd_28_SUM_2_), .B0(n1491), .B1(n1357),
.Y(n528) );
AOI2BB2XLTS U1779 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n1354), .A0N(n1493),
.A1N(DmP_mant_SFG_SWR[15]), .Y(intadd_28_B_3_) );
AOI22X1TS U1780 ( .A0(n1359), .A1(intadd_28_SUM_3_), .B0(n1490), .B1(n1357),
.Y(n527) );
INVX1TS U1781 ( .A(DmP_mant_SFG_SWR[16]), .Y(n1455) );
AOI22X1TS U1782 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1352), .B0(n1351), .B1(
n1455), .Y(intadd_28_B_4_) );
AOI22X1TS U1783 ( .A0(n1359), .A1(intadd_28_SUM_4_), .B0(n1482), .B1(n1603),
.Y(n526) );
INVX1TS U1784 ( .A(DmP_mant_SFG_SWR[17]), .Y(n1457) );
AOI22X1TS U1785 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1352), .B0(n1351), .B1(
n1457), .Y(intadd_28_B_5_) );
AOI22X1TS U1786 ( .A0(n1359), .A1(intadd_28_SUM_5_), .B0(n1507), .B1(n1603),
.Y(n525) );
INVX1TS U1787 ( .A(DmP_mant_SFG_SWR[18]), .Y(n1459) );
AOI22X1TS U1788 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n1352), .B0(n1351), .B1(
n1459), .Y(intadd_28_B_6_) );
AOI2BB2XLTS U1789 ( .B0(n873), .B1(intadd_28_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n873), .Y(n524) );
INVX1TS U1790 ( .A(DmP_mant_SFG_SWR[19]), .Y(n1461) );
AOI22X1TS U1791 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1352), .B0(n1351), .B1(
n1461), .Y(intadd_28_B_7_) );
AOI2BB2XLTS U1792 ( .B0(n873), .B1(intadd_28_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n873), .Y(n523) );
INVX1TS U1793 ( .A(DmP_mant_SFG_SWR[20]), .Y(n1463) );
AOI22X1TS U1794 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n1352), .B0(n1351), .B1(
n1463), .Y(intadd_28_B_8_) );
AOI2BB2XLTS U1795 ( .B0(n873), .B1(intadd_28_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n873), .Y(n522) );
INVX1TS U1796 ( .A(DmP_mant_SFG_SWR[21]), .Y(n1465) );
AOI22X1TS U1797 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n1352), .B0(n1351), .B1(
n1465), .Y(intadd_28_B_9_) );
AOI22X1TS U1798 ( .A0(n1359), .A1(intadd_28_SUM_9_), .B0(n1508), .B1(n1603),
.Y(n521) );
AOI22X1TS U1799 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1352), .B0(n1351), .B1(
n908), .Y(intadd_28_B_10_) );
AOI22X1TS U1800 ( .A0(n1359), .A1(intadd_28_SUM_10_), .B0(n1506), .B1(n1603),
.Y(n520) );
AOI22X1TS U1801 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n1352), .B0(n1355), .B1(
n909), .Y(intadd_28_B_11_) );
AOI22X1TS U1802 ( .A0(n1359), .A1(intadd_28_SUM_11_), .B0(n1477), .B1(n1603),
.Y(n519) );
AOI22X1TS U1803 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1352), .B0(n1351), .B1(
n910), .Y(intadd_28_B_12_) );
AOI22X1TS U1804 ( .A0(n1359), .A1(intadd_28_SUM_12_), .B0(n1481), .B1(n1603),
.Y(n518) );
INVX1TS U1805 ( .A(DmP_mant_SFG_SWR[25]), .Y(n1474) );
AOI22X1TS U1806 ( .A0(DmP_mant_SFG_SWR[25]), .A1(n1355), .B0(n1354), .B1(
n1474), .Y(n1356) );
XNOR2X1TS U1807 ( .A(intadd_28_n1), .B(n1356), .Y(n1358) );
AOI22X1TS U1808 ( .A0(n1359), .A1(n1358), .B0(n1489), .B1(n1357), .Y(n517)
);
AND3X4TS U1809 ( .A(shift_value_SHT2_EWR[2]), .B(n1510), .C(
shift_value_SHT2_EWR[3]), .Y(n1427) );
NAND2X1TS U1810 ( .A(shift_value_SHT2_EWR[2]), .B(n1512), .Y(n1380) );
NAND2X1TS U1811 ( .A(n1400), .B(n1510), .Y(n1411) );
NOR2XLTS U1812 ( .A(n1434), .B(n1411), .Y(n1365) );
AOI22X1TS U1813 ( .A0(Data_array_SWR[11]), .A1(n1364), .B0(
Data_array_SWR[12]), .B1(n1435), .Y(n1366) );
OAI221X1TS U1814 ( .A0(n1473), .A1(n1368), .B0(n1434), .B1(n1369), .C0(n1366), .Y(n1448) );
AO22XLTS U1815 ( .A0(final_result_ieee[10]), .A1(n1424), .B0(n1381), .B1(
n1448), .Y(n511) );
AOI22X1TS U1816 ( .A0(Data_array_SWR[11]), .A1(n1435), .B0(
Data_array_SWR[12]), .B1(n1364), .Y(n1367) );
OAI221X1TS U1817 ( .A0(n1473), .A1(n1369), .B0(n1434), .B1(n1368), .C0(n1367), .Y(n1449) );
AO22XLTS U1818 ( .A0(n1381), .A1(n1449), .B0(final_result_ieee[11]), .B1(
n1424), .Y(n510) );
AOI22X1TS U1819 ( .A0(Data_array_SWR[21]), .A1(n1426), .B0(
Data_array_SWR[17]), .B1(n1363), .Y(n1373) );
AOI22X1TS U1820 ( .A0(Data_array_SWR[13]), .A1(n1435), .B0(n903), .B1(n1364),
.Y(n1370) );
OAI221X1TS U1821 ( .A0(n1473), .A1(n1372), .B0(n1434), .B1(n1373), .C0(n1370), .Y(n1446) );
AO22XLTS U1822 ( .A0(n1381), .A1(n1446), .B0(final_result_ieee[9]), .B1(
n1424), .Y(n509) );
AOI22X1TS U1823 ( .A0(Data_array_SWR[13]), .A1(n1364), .B0(n903), .B1(n1435),
.Y(n1371) );
OAI221X1TS U1824 ( .A0(n1473), .A1(n1373), .B0(n1434), .B1(n1372), .C0(n1371), .Y(n1450) );
AO22XLTS U1825 ( .A0(n1381), .A1(n1450), .B0(final_result_ieee[12]), .B1(
n1424), .Y(n508) );
AOI22X1TS U1826 ( .A0(Data_array_SWR[22]), .A1(n1426), .B0(
Data_array_SWR[18]), .B1(n1363), .Y(n1377) );
AOI22X1TS U1827 ( .A0(Data_array_SWR[10]), .A1(n1364), .B0(
Data_array_SWR[14]), .B1(n1435), .Y(n1374) );
OAI221X1TS U1828 ( .A0(n1473), .A1(n1376), .B0(n1434), .B1(n1377), .C0(n1374), .Y(n1445) );
AO22XLTS U1829 ( .A0(n1381), .A1(n1445), .B0(final_result_ieee[8]), .B1(
n1424), .Y(n507) );
AOI22X1TS U1830 ( .A0(Data_array_SWR[10]), .A1(n1435), .B0(
Data_array_SWR[14]), .B1(n1364), .Y(n1375) );
OAI221X1TS U1831 ( .A0(n1473), .A1(n1377), .B0(n1434), .B1(n1376), .C0(n1375), .Y(n1452) );
AO22XLTS U1832 ( .A0(n1381), .A1(n1452), .B0(final_result_ieee[13]), .B1(
n1424), .Y(n506) );
AOI22X1TS U1833 ( .A0(Data_array_SWR[16]), .A1(n1426), .B0(
Data_array_SWR[12]), .B1(n1363), .Y(n1379) );
CLKAND2X2TS U1834 ( .A(n1400), .B(shift_value_SHT2_EWR[4]), .Y(n1393) );
AOI22X1TS U1835 ( .A0(Data_array_SWR[20]), .A1(n1427), .B0(
Data_array_SWR[24]), .B1(n1393), .Y(n1378) );
NAND2X1TS U1836 ( .A(n1379), .B(n1378), .Y(n1383) );
NOR2X1TS U1837 ( .A(shift_value_SHT2_EWR[2]), .B(n1512), .Y(n1386) );
INVX2TS U1838 ( .A(n1380), .Y(n1401) );
INVX2TS U1839 ( .A(n1431), .Y(n1382) );
INVX4TS U1840 ( .A(n1381), .Y(n1425) );
OAI2BB2XLTS U1841 ( .B0(n1444), .B1(n1425), .A0N(final_result_ieee[7]),
.A1N(n1424), .Y(n505) );
OAI2BB2XLTS U1842 ( .B0(n1456), .B1(n1425), .A0N(final_result_ieee[14]),
.A1N(n1424), .Y(n504) );
AOI22X1TS U1843 ( .A0(Data_array_SWR[11]), .A1(n1363), .B0(
Data_array_SWR[15]), .B1(n1426), .Y(n1385) );
AOI22X1TS U1844 ( .A0(Data_array_SWR[23]), .A1(n1393), .B0(
Data_array_SWR[19]), .B1(n1427), .Y(n1384) );
NAND2X1TS U1845 ( .A(n1385), .B(n1384), .Y(n1388) );
INVX2TS U1846 ( .A(n1423), .Y(n1387) );
OAI2BB2XLTS U1847 ( .B0(n1443), .B1(n1425), .A0N(final_result_ieee[6]),
.A1N(n1424), .Y(n503) );
OAI2BB2XLTS U1848 ( .B0(n1458), .B1(n1425), .A0N(final_result_ieee[15]),
.A1N(n1424), .Y(n502) );
AOI22X1TS U1849 ( .A0(Data_array_SWR[14]), .A1(n1426), .B0(n903), .B1(n1363),
.Y(n1390) );
AOI22X1TS U1850 ( .A0(Data_array_SWR[22]), .A1(n1393), .B0(
Data_array_SWR[18]), .B1(n1427), .Y(n1389) );
NAND2X1TS U1851 ( .A(n1390), .B(n1389), .Y(n1392) );
AOI22X1TS U1852 ( .A0(Data_array_SWR[21]), .A1(n1401), .B0(
Data_array_SWR[17]), .B1(n1400), .Y(n1417) );
INVX2TS U1853 ( .A(n1417), .Y(n1391) );
OAI2BB2XLTS U1854 ( .B0(n1442), .B1(n1425), .A0N(final_result_ieee[5]),
.A1N(n1424), .Y(n501) );
OAI2BB2XLTS U1855 ( .B0(n1460), .B1(n1425), .A0N(final_result_ieee[16]),
.A1N(n1424), .Y(n500) );
AOI22X1TS U1856 ( .A0(Data_array_SWR[13]), .A1(n1426), .B0(
Data_array_SWR[10]), .B1(n1363), .Y(n1395) );
AOI22X1TS U1857 ( .A0(Data_array_SWR[21]), .A1(n1393), .B0(
Data_array_SWR[17]), .B1(n1427), .Y(n1394) );
NAND2X1TS U1858 ( .A(n1395), .B(n1394), .Y(n1397) );
AOI22X1TS U1859 ( .A0(Data_array_SWR[22]), .A1(n1401), .B0(
Data_array_SWR[18]), .B1(n1400), .Y(n1414) );
INVX2TS U1860 ( .A(n1414), .Y(n1396) );
OAI2BB2XLTS U1861 ( .B0(n1441), .B1(n1425), .A0N(final_result_ieee[4]),
.A1N(n1420), .Y(n499) );
OAI2BB2XLTS U1862 ( .B0(n1462), .B1(n1425), .A0N(final_result_ieee[17]),
.A1N(n1420), .Y(n498) );
AOI22X1TS U1863 ( .A0(Data_array_SWR[20]), .A1(n1400), .B0(
Data_array_SWR[24]), .B1(n1401), .Y(n1406) );
AOI22X1TS U1864 ( .A0(Data_array_SWR[12]), .A1(n1426), .B0(Data_array_SWR[9]), .B1(n1363), .Y(n1399) );
NAND2X1TS U1865 ( .A(Data_array_SWR[16]), .B(n1427), .Y(n1398) );
OAI211X1TS U1866 ( .A0(n1406), .A1(n1510), .B0(n1399), .C0(n1398), .Y(n1402)
);
AO22X1TS U1867 ( .A0(Data_array_SWR[23]), .A1(n1401), .B0(Data_array_SWR[19]), .B1(n1400), .Y(n1403) );
OAI2BB2XLTS U1868 ( .B0(n1440), .B1(n1425), .A0N(final_result_ieee[3]),
.A1N(n1420), .Y(n497) );
OAI2BB2XLTS U1869 ( .B0(n1464), .B1(n1425), .A0N(final_result_ieee[18]),
.A1N(n1420), .Y(n496) );
AOI22X1TS U1870 ( .A0(Data_array_SWR[11]), .A1(n1426), .B0(Data_array_SWR[8]), .B1(n1363), .Y(n1405) );
AOI22X1TS U1871 ( .A0(Data_array_SWR[15]), .A1(n1427), .B0(
shift_value_SHT2_EWR[4]), .B1(n1403), .Y(n1404) );
NAND2X1TS U1872 ( .A(n1405), .B(n1404), .Y(n1410) );
INVX2TS U1873 ( .A(n1406), .Y(n1409) );
OAI2BB2XLTS U1874 ( .B0(n1439), .B1(n1425), .A0N(final_result_ieee[2]),
.A1N(n1420), .Y(n495) );
OAI2BB2XLTS U1875 ( .B0(n1466), .B1(n1425), .A0N(final_result_ieee[19]),
.A1N(n1420), .Y(n494) );
AOI22X1TS U1876 ( .A0(Data_array_SWR[14]), .A1(n1427), .B0(n903), .B1(n1426),
.Y(n1413) );
INVX2TS U1877 ( .A(n1411), .Y(n1428) );
AOI22X1TS U1878 ( .A0(Data_array_SWR[7]), .A1(n1363), .B0(Data_array_SWR[3]),
.B1(n1428), .Y(n1412) );
OAI211X1TS U1879 ( .A0(n1414), .A1(n1510), .B0(n1413), .C0(n1412), .Y(n1418)
);
AOI22X1TS U1880 ( .A0(Data_array_SWR[21]), .A1(n1435), .B0(n1434), .B1(n1418), .Y(n1438) );
OAI2BB2XLTS U1881 ( .B0(n1438), .B1(n1425), .A0N(final_result_ieee[1]),
.A1N(n1420), .Y(n493) );
AOI22X1TS U1882 ( .A0(Data_array_SWR[13]), .A1(n1427), .B0(
Data_array_SWR[10]), .B1(n1426), .Y(n1416) );
AOI22X1TS U1883 ( .A0(Data_array_SWR[6]), .A1(n1363), .B0(Data_array_SWR[2]),
.B1(n1428), .Y(n1415) );
OAI211X1TS U1884 ( .A0(n1417), .A1(n1510), .B0(n1416), .C0(n1415), .Y(n1419)
);
AOI22X1TS U1885 ( .A0(Data_array_SWR[22]), .A1(n1435), .B0(n1434), .B1(n1419), .Y(n1437) );
OAI2BB2XLTS U1886 ( .B0(n1437), .B1(n1425), .A0N(final_result_ieee[0]),
.A1N(n1420), .Y(n492) );
AOI22X1TS U1887 ( .A0(Data_array_SWR[21]), .A1(n1364), .B0(n1473), .B1(n1418), .Y(n1467) );
OAI2BB2XLTS U1888 ( .B0(n1467), .B1(n1425), .A0N(final_result_ieee[20]),
.A1N(n1420), .Y(n491) );
AOI22X1TS U1889 ( .A0(Data_array_SWR[22]), .A1(n1364), .B0(n1473), .B1(n1419), .Y(n1468) );
OAI2BB2XLTS U1890 ( .B0(n1468), .B1(n1425), .A0N(final_result_ieee[21]),
.A1N(n1420), .Y(n490) );
AOI22X1TS U1891 ( .A0(Data_array_SWR[12]), .A1(n1427), .B0(Data_array_SWR[9]), .B1(n1426), .Y(n1422) );
AOI22X1TS U1892 ( .A0(Data_array_SWR[5]), .A1(n1363), .B0(Data_array_SWR[1]),
.B1(n1428), .Y(n1421) );
OAI211X1TS U1893 ( .A0(n1423), .A1(n1510), .B0(n1422), .C0(n1421), .Y(n1433)
);
AOI22X1TS U1894 ( .A0(Data_array_SWR[23]), .A1(n1364), .B0(n1473), .B1(n1433), .Y(n1470) );
OAI2BB2XLTS U1895 ( .B0(n1470), .B1(n1425), .A0N(final_result_ieee[22]),
.A1N(n1424), .Y(n489) );
AOI22X1TS U1896 ( .A0(Data_array_SWR[11]), .A1(n1427), .B0(Data_array_SWR[8]), .B1(n1426), .Y(n1430) );
AOI22X1TS U1897 ( .A0(Data_array_SWR[4]), .A1(n1363), .B0(Data_array_SWR[0]),
.B1(n1428), .Y(n1429) );
OAI211X1TS U1898 ( .A0(n1431), .A1(n1510), .B0(n1430), .C0(n1429), .Y(n1472)
);
AOI22X1TS U1899 ( .A0(Data_array_SWR[24]), .A1(n1435), .B0(n1434), .B1(n1472), .Y(n1432) );
AOI22X1TS U1900 ( .A0(n1476), .A1(n1432), .B0(n1447), .B1(n911), .Y(n488) );
AOI22X1TS U1901 ( .A0(Data_array_SWR[23]), .A1(n1435), .B0(n1434), .B1(n1433), .Y(n1436) );
AOI22X1TS U1902 ( .A0(n1476), .A1(n1436), .B0(n1447), .B1(n912), .Y(n487) );
AOI22X1TS U1903 ( .A0(n1476), .A1(n1437), .B0(n1454), .B1(n913), .Y(n486) );
AOI22X1TS U1904 ( .A0(n1476), .A1(n1438), .B0(n1469), .B1(n917), .Y(n485) );
AOI22X1TS U1905 ( .A0(n1471), .A1(n1439), .B0(n1454), .B1(n918), .Y(n484) );
AOI22X1TS U1906 ( .A0(n1476), .A1(n1440), .B0(n916), .B1(n1469), .Y(n483) );
AOI22X1TS U1907 ( .A0(n1476), .A1(n1441), .B0(n1454), .B1(n915), .Y(n482) );
AOI22X1TS U1908 ( .A0(n1471), .A1(n1442), .B0(n1469), .B1(n914), .Y(n481) );
AOI22X1TS U1909 ( .A0(n1471), .A1(n1443), .B0(n1454), .B1(n907), .Y(n480) );
AOI22X1TS U1910 ( .A0(n1471), .A1(n1444), .B0(n877), .B1(n1469), .Y(n479) );
AO22XLTS U1911 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[10]), .B0(n1453), .B1(
n1445), .Y(n478) );
AO22XLTS U1912 ( .A0(n1447), .A1(DmP_mant_SFG_SWR[11]), .B0(n1453), .B1(
n1446), .Y(n477) );
AO22XLTS U1913 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[12]), .B0(n1453), .B1(
n1448), .Y(n476) );
AO22XLTS U1914 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[13]), .B0(n1451), .B1(
n1449), .Y(n475) );
AO22XLTS U1915 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[14]), .B0(n1451), .B1(
n1450), .Y(n474) );
AO22XLTS U1916 ( .A0(n1454), .A1(DmP_mant_SFG_SWR[15]), .B0(n1453), .B1(
n1452), .Y(n473) );
AOI22X1TS U1917 ( .A0(n1471), .A1(n1456), .B0(n1455), .B1(n1469), .Y(n472)
);
AOI22X1TS U1918 ( .A0(n1476), .A1(n1458), .B0(n1457), .B1(n1469), .Y(n471)
);
AOI22X1TS U1919 ( .A0(n1476), .A1(n1460), .B0(n1459), .B1(n1469), .Y(n470)
);
AOI22X1TS U1920 ( .A0(n1476), .A1(n1462), .B0(n1461), .B1(n1469), .Y(n469)
);
AOI22X1TS U1921 ( .A0(n1476), .A1(n1464), .B0(n1463), .B1(n1469), .Y(n468)
);
AOI22X1TS U1922 ( .A0(n1476), .A1(n1466), .B0(n1465), .B1(n1469), .Y(n467)
);
AOI22X1TS U1923 ( .A0(n1476), .A1(n1467), .B0(n1469), .B1(n908), .Y(n466) );
AOI22X1TS U1924 ( .A0(n1476), .A1(n1468), .B0(n1469), .B1(n909), .Y(n465) );
AOI22X1TS U1925 ( .A0(n1476), .A1(n1470), .B0(n1469), .B1(n910), .Y(n464) );
AOI22X1TS U1926 ( .A0(Data_array_SWR[24]), .A1(n1364), .B0(n1473), .B1(n1472), .Y(n1475) );
AOI22X1TS U1927 ( .A0(n1476), .A1(n1475), .B0(n1474), .B1(n1469), .Y(n463)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk40.tcl_ACAIIN16Q8_syn.sdf");
endmodule
|
/****************************************
Load Store
for MIST1032ISA Processor
Takahiro Ito @cpu_labs
****************************************/
`default_nettype none
`include "core.h"
module execute_adder_calc(
//Prev
input wire [4:0] iCMD,
input wire iLOADSTORE_MODE, //0:SYS_LDST | 1:LDST
input wire [31:0] iSOURCE0,
input wire [31:0] iSOURCE1,
input wire iADV_ACTIVE,
input wire [31:0] iADV_DATA,
input wire [31:0] iSPR,
input wire [31:0] iPSR,
input wire [31:0] iPDTR,
input wire [31:0] iKPDTR,
input wire [31:0] iPC,
//Output - Writeback
output wire oOUT_SPR_VALID,
output wire [31:0] oOUT_SPR,
output wire [31:0] oOUT_DATA,
//Output - LDST Pipe
output wire oLDST_RW,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
output wire [1:0] oLDST_ORDER,
output wire [3:0] oLDST_MASK,
output wire [1:0] oLOAD_SHIFT
);
function [3:0] func_bytemask;
input [1:0] func_order;
input [1:0] func_address;
begin
case(func_order)
2'h0 :
begin
if(func_address[1:0] == 2'h0)begin
func_bytemask = 4'b0001;
end
else if(func_address[1:0] == 2'h1)begin
func_bytemask = 4'b0010;
end
else if(func_address[1:0] == 2'h2)begin
func_bytemask = 4'b0100;
end
else begin
func_bytemask = 4'b1000;
end
end
2'h1 :
begin
if(func_address[1:0] == 2'h0)begin
func_bytemask = 4'b0011;
end
else if(func_address[1:0] == 2'h2)begin
func_bytemask = 4'b1100;
end
else begin
func_bytemask = 4'b0000;
end
end
2'h2 :
begin
func_bytemask = 4'b1111;
end
default:
begin
func_bytemask = 4'b0000;
end
endcase
end
endfunction
function [31:0] func_store_data8;
input [1:0] func_shift;
input [31:0] func_data;
begin
case(func_shift)
2'h0 : func_store_data8 = {24'h0, func_data[7:0]};
2'h1 : func_store_data8 = {16'h0, func_data[7:0], 8'h0};
2'h2 : func_store_data8 = {8'h0, func_data[7:0], 16'h0};
2'h3 : func_store_data8 = {func_data[7:0], 24'h0};
endcase
end
endfunction
function [31:0] func_store_data16;
input [1:0] func_shift;
input [31:0] func_data;
begin
case(func_shift)
2'h0 : func_store_data16 = {16'h0, func_data[15:0]};
2'h2 : func_store_data16 = {func_data[15:0], 16'h0};
default : func_store_data16 = 32'hxxxxxxxx;
endcase
end
endfunction
reg [31:0] ldst_pdt;
always @* begin
if(iLOADSTORE_MODE)begin
if(
iCMD == `EXE_LDSW_LD8U ||
iCMD == `EXE_LDSW_LD16U ||
iCMD == `EXE_LDSW_LD32U ||
iCMD == `EXE_LDSW_ST8U ||
iCMD == `EXE_LDSW_ST16U ||
iCMD == `EXE_LDSW_ST32U
)begin
ldst_pdt = iPDTR;
end
else begin
ldst_pdt = (iPSR[6:5] == 2'h0)? iKPDTR : iPDTR;
end
end
else begin
ldst_pdt = (iPSR[6:5] == 2'h0)? iKPDTR : iPDTR;
end
end
reg spr_valid;
reg [31:0] spr;
reg [31:0] data;
reg [31:0] ldst_addr;
reg [31:0] ldst_data;
reg ldst_rw;
reg [1:0] ldst_order;
reg [3:0] ldst_load_mask;
reg [1:0] ldst_load_shift;
always @* begin
if(iLOADSTORE_MODE)begin
case(iCMD)
`EXE_LDSW_LD8:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h0;
ldst_load_mask = func_bytemask(2'h0, iSOURCE1[1:0]);
ldst_load_shift = iSOURCE1[1:0];
end
`EXE_LDSW_LD16:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h1;
ldst_load_mask = func_bytemask(2'h1, iSOURCE1[1:0]);
ldst_load_shift = (iSOURCE1[1:0] == 2'h0)? 2'h0 : 2'h2;
end
`EXE_LDSW_LD32:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h2;
ldst_load_mask = func_bytemask(2'h2, iSOURCE1[1:0]);
ldst_load_shift = 2'h0;
end
`EXE_LDSW_ST8:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = func_store_data8(iSOURCE1[1:0], iSOURCE0);
ldst_rw = 1'b1;
ldst_order = 2'h0;
ldst_load_mask = func_bytemask(2'h0, iSOURCE1[1:0]);
ldst_load_shift = iSOURCE1[1:0];
end
`EXE_LDSW_ST16:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = func_store_data16((iSOURCE1[1:0] == 2'h0)? 2'h0 : 2'h2, iSOURCE0);
ldst_rw = 1'b1;
ldst_order = 2'h1;
ldst_load_mask = func_bytemask(2'h1, iSOURCE1[1:0]);
ldst_load_shift = (iSOURCE1[1:0] == 2'h0)? 2'h0 : 2'h2;
end
`EXE_LDSW_ST32:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = func_bytemask(2'h2, iSOURCE1[1:0]);
ldst_load_shift = 2'h0;
end
`EXE_LDSW_PUSH:
begin
spr_valid = 1'b1;
spr = iSPR - 32'h4;
data = 32'h0;
ldst_addr = iSPR - 32'h4;
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'hf;
ldst_load_shift = 2'h0;
end
`EXE_LDSW_PPUSH:
begin
spr_valid = 1'b1;
spr = iSPR - 32'h4;
data = 32'h0;
ldst_addr = iSPR - 32'h4;
ldst_data = iPC;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'hf;
ldst_load_shift = 2'h0;
end
`EXE_LDSW_POP:
begin
spr_valid = 1'b1;
spr = iSPR + 32'h4;
data = 32'h0;
ldst_addr = iSPR;
ldst_data = 32'h0;
ldst_rw = 1'b0;
ldst_order = 2'h2;
ldst_load_mask = 4'hf;
ldst_load_shift = 2'h0;
end
`EXE_LDSW_LDD8:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + iADV_DATA;
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h0;
ldst_load_mask = func_bytemask(2'h0, (iSOURCE1[1:0] + iADV_DATA[1:0]));
ldst_load_shift = iSOURCE1[1:0] + iADV_DATA[1:0];
end
`EXE_LDSW_LDD16:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + {iADV_DATA, 1'b0};
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h1;
ldst_load_mask = func_bytemask(2'h1, (iSOURCE1[1:0] + {iADV_DATA[0], 1'b0}));
ldst_load_shift = (iSOURCE1[1:0] + {iADV_DATA[0], 1'b0} == 2'h0)? 2'h0 : 2'h2;//2'h3 - iSOURCE1[1:0];
end
`EXE_LDSW_LDD32:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + {iADV_DATA, 2'b00};
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h2;
ldst_load_mask = func_bytemask(2'h2, iSOURCE1[1:0]);
ldst_load_shift = 2'h0;
end
`EXE_LDSW_STD8:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + iADV_DATA;
ldst_data = func_store_data8(iSOURCE1[1:0] + iADV_DATA[1:0], iSOURCE0);//iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h0;
ldst_load_mask = func_bytemask(2'h0, (iSOURCE1[1:0] + iADV_DATA[1:0]));
ldst_load_shift = iSOURCE1[1:0] + iADV_DATA[1:0];
end
`EXE_LDSW_STD16:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + {iADV_DATA, 1'b0};
ldst_data = func_store_data16((iSOURCE1[1:0] + {iADV_DATA[0], 1'b0} == 2'h0)? 2'h0 : 2'h2, iSOURCE0);//iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h1;
ldst_load_mask = func_bytemask(2'h1, (iSOURCE1[1:0] + {iADV_DATA[0], 1'b0}));
ldst_load_shift = (iSOURCE1[1:0] + {iADV_DATA[0], 1'b0} == 2'h0)? 2'h0 : 2'h2;
end
`EXE_LDSW_STD32:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + {iADV_DATA, 2'b00};
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = func_bytemask(2'h2, iSOURCE1[1:0]);
ldst_load_shift = 2'h0;
end
default:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = 32'h0;
ldst_rw = 1'b0;
ldst_order = 2'h0;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
endcase
end
//Sys Load / Store
else begin
case(iCMD)
`EXE_SYS_LDST_READ_SPR:
begin
spr_valid = 1'b1;
spr = iSPR;
data = iSPR;
ldst_addr = iSOURCE1;
ldst_data = iSPR;
ldst_rw = 1'b0;
ldst_order = 2'h2;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
`EXE_SYS_LDST_WRITE_SPR:
begin
spr_valid = 1'b1;
spr = iSOURCE0;
data = 32'h0;
ldst_addr = iSOURCE0;
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
`EXE_SYS_LDST_ADD_SPR:
begin
spr_valid = 1'b1;
spr = iSOURCE0 + iSOURCE1;
data = 32'h0;
ldst_addr = iSOURCE0;
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
default:
begin
spr_valid = 1'b1;
spr = iSOURCE0 + iSOURCE1;
data = 32'h0;
ldst_addr = iSOURCE0;
ldst_data = iSOURCE0 + iSOURCE1;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
endcase
end
end
assign oOUT_SPR_VALID = spr_valid;
assign oOUT_SPR = spr;
assign oOUT_DATA = data;
//Output - LDST Pipe
assign oLDST_RW = ldst_rw;
assign oLDST_PDT = ldst_pdt;
assign oLDST_ADDR = ldst_addr;
assign oLDST_DATA = ldst_data;
assign oLDST_ORDER = ldst_order;
assign oLDST_MASK = ldst_load_mask;
assign oLOAD_SHIFT = ldst_load_shift;
endmodule
`default_nettype wire
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module m_rep_upload(//input
clk,
rst,
m_flits_rep,
v_m_flits_rep,
flits_max,
en_flits_max,
rep_fifo_rdy,
//output
m_flit_out,
v_m_flit_out,
m_ctrl_out,
m_rep_upload_state
);
//input
input clk;
input rst;
input [175:0] m_flits_rep;
input v_m_flits_rep;
input [3:0] flits_max;
input en_flits_max;
input rep_fifo_rdy;
//output
output [15:0] m_flit_out;
output v_m_flit_out;
output [1:0] m_ctrl_out;
output m_rep_upload_state;
//parameter
parameter m_rep_upload_idle=1'b0;
parameter m_rep_upload_busy=1'b1;
//reg m_req_nstate;
reg m_rep_state;
reg [143:0] m_rep_flits;
reg [3:0] sel_cnt;
reg v_m_flit_out;
reg fsm_rst;
reg next;
reg en_flits_in;
reg inc_cnt;
reg [3:0] flits_max_reg;
reg [1:0] m_ctrl_out;
assign m_rep_upload_state=m_rep_state;
always@(*)
begin
//default value
// dc_req_nstate=dc_req_state;
v_m_flit_out=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
en_flits_in=1'b0;
next=1'b0;
m_ctrl_out=2'b00;
case(m_rep_state)
m_rep_upload_idle:
begin
if(v_m_flits_rep)
begin
en_flits_in=1'b1;
next=1'b1;
end
end
m_rep_upload_busy:
begin
if(rep_fifo_rdy)
begin
if(sel_cnt==flits_max_reg)
begin
fsm_rst=1'b1;
m_ctrl_out=2'b11;
end
else if(sel_cnt==3'b000)
m_ctrl_out=2'b01;
m_ctrl_out=2'b10;
inc_cnt=1'b1;
v_m_flit_out=1'b1;
end
end
endcase
end
// fsm state
always@(posedge clk)
begin
if(rst||fsm_rst)
m_rep_state<=1'b0;
else if(next)
m_rep_state<=1'b1;
end
// flits regs
always@(posedge clk)
begin
if(rst||fsm_rst)
m_rep_flits<=143'h0000;
else if(en_flits_in)
m_rep_flits<=m_flits_rep[175:32];
end
reg [15:0] m_flit_out;
always@(*)
begin
case(sel_cnt)
4'b0000:m_flit_out=m_rep_flits[143:128];
4'b0001:m_flit_out=m_rep_flits[127:112];
4'b0010:m_flit_out=m_rep_flits[111:96];
4'b0011:m_flit_out=m_rep_flits[95:80];
4'b0100:m_flit_out=m_rep_flits[79:64];
4'b0101:m_flit_out=m_rep_flits[63:48];
4'b0110:m_flit_out=m_rep_flits[47:32];
4'b0111:m_flit_out=m_rep_flits[31:16];
4'b1000:m_flit_out=m_rep_flits[15:0];
default:m_flit_out=m_rep_flits[143:128];
endcase
end
// flits_max
always@(posedge clk)
begin
if(rst||fsm_rst)
flits_max_reg<=4'b0000;
else if(en_flits_max)
flits_max_reg<=flits_max;
end
///sel_counter
always@(posedge clk)
begin
if(rst||fsm_rst)
sel_cnt<=4'b0000;
else if(inc_cnt)
sel_cnt<=sel_cnt+4'b0001;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:40:52 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, enab_cont_iter, underflow_flag_mult, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_fmtted_Result_31_,
FPSENCOS_enab_d_ff4_Xn, FPSENCOS_enab_d_ff4_Yn,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPSENCOS_enab_d_ff5_data_out, FPSENCOS_enab_RB3,
FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_exp_operation_A_S,
FPMULT_FSM_barrel_shifter_load, FPMULT_FSM_final_result_load,
FPMULT_FSM_adder_round_norm_load, FPMULT_FSM_load_second_step,
FPMULT_FSM_exp_operation_load_result, FPMULT_FSM_first_phase_load,
FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag, FPADDSUB_N60,
FPADDSUB_N59, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB__19_net_,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_bit_shift_SHT2,
FPADDSUB_left_right_SHT2, FPADDSUB__6_net_, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPADDSUB_enable_Pipeline_input,
FPSENCOS_ITER_CONT_net8324057, FPSENCOS_ITER_CONT_N5,
FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_FS_Module_net8324003, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Exp_module_Overflow_A,
FPMULT_Sgf_operation_EVEN1_result_B_adder_0_,
FPMULT_Sgf_operation_EVEN1_result_A_adder_0_,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPADDSUB_inst_ShiftRegister_net8323895,
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805,
FPSENCOS_d_ff5_data_out_net8324021,
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733,
FPADDSUB_SGF_STAGE_DMP_net8323787,
FPADDSUB_NRM_STAGE_Raw_mant_net8323769, FPSENCOS_reg_Z0_net8324021,
FPSENCOS_reg_val_muxZ_2stage_net8324021,
FPSENCOS_reg_shift_y_net8324021, FPSENCOS_d_ff4_Xn_net8324021,
FPSENCOS_d_ff4_Yn_net8324021, FPSENCOS_d_ff4_Zn_net8324021,
FPADDSUB_INPUT_STAGE_OPERANDY_net8323733,
FPADDSUB_EXP_STAGE_DMP_net8323787, FPADDSUB_SHT1_STAGE_DMP_net8323787,
FPADDSUB_SHT2_STAGE_DMP_net8323787,
FPADDSUB_SHT2_SHIFT_DATA_net8323769,
FPMULT_Exp_module_exp_result_m_net8323967,
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949,
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931,
FPMULT_Adder_M_Add_Subt_Result_net8323913,
FPMULT_Operands_load_reg_XMRegister_net8323985,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1,
n30, n115, n808, n811, n814, n817, n825, n829, n830, n840, n841, n842,
n844, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n857, n858, n859, n860, n861, n862, n863, n872, n873, mult_x_312_n77,
mult_x_312_n72, mult_x_312_n71, mult_x_312_n67, mult_x_312_n59,
mult_x_312_n58, mult_x_312_n53, mult_x_312_n48, mult_x_312_n42,
mult_x_312_n39, mult_x_312_n38, mult_x_312_n37, mult_x_312_n36,
mult_x_312_n35, mult_x_312_n34, mult_x_312_n33, mult_x_312_n32,
mult_x_312_n31, mult_x_312_n30, mult_x_312_n29, mult_x_312_n28,
mult_x_312_n27, mult_x_312_n26, mult_x_312_n25, mult_x_312_n24,
mult_x_312_n23, mult_x_312_n22, mult_x_312_n21, mult_x_312_n20,
mult_x_312_n19, mult_x_312_n18, mult_x_312_n17, mult_x_312_n16,
mult_x_312_n15, mult_x_312_n14, mult_x_312_n13, mult_x_311_n37,
mult_x_311_n36, mult_x_311_n30, mult_x_311_n29, mult_x_311_n23,
mult_x_311_n22, mult_x_311_n18, mult_x_311_n17, mult_x_311_n15,
mult_x_311_n14, mult_x_310_n37, mult_x_310_n36, mult_x_310_n30,
mult_x_310_n29, mult_x_310_n23, mult_x_310_n22, mult_x_310_n18,
mult_x_310_n17, mult_x_310_n15, mult_x_310_n14, mult_x_309_n76,
mult_x_309_n71, mult_x_309_n66, mult_x_309_n65, mult_x_309_n58,
mult_x_309_n52, mult_x_309_n42, mult_x_309_n39, mult_x_309_n38,
mult_x_309_n37, mult_x_309_n36, mult_x_309_n35, mult_x_309_n34,
mult_x_309_n33, mult_x_309_n32, mult_x_309_n31, mult_x_309_n30,
mult_x_309_n29, mult_x_309_n28, mult_x_309_n27, mult_x_309_n26,
mult_x_309_n25, mult_x_309_n24, mult_x_309_n23, mult_x_309_n22,
mult_x_309_n21, mult_x_309_n20, mult_x_309_n19, mult_x_309_n18,
mult_x_309_n17, mult_x_309_n16, mult_x_309_n15, mult_x_309_n14,
mult_x_309_n13, DP_OP_496J324_122_3236_n68,
DP_OP_496J324_122_3236_n17, DP_OP_26J324_129_1325_n18,
DP_OP_26J324_129_1325_n17, DP_OP_26J324_129_1325_n16,
DP_OP_26J324_129_1325_n15, DP_OP_26J324_129_1325_n14,
DP_OP_26J324_129_1325_n8, DP_OP_26J324_129_1325_n7,
DP_OP_26J324_129_1325_n6, DP_OP_26J324_129_1325_n5,
DP_OP_26J324_129_1325_n4, DP_OP_26J324_129_1325_n3,
DP_OP_26J324_129_1325_n2, DP_OP_26J324_129_1325_n1,
DP_OP_234J324_132_4955_n22, DP_OP_234J324_132_4955_n21,
DP_OP_234J324_132_4955_n20, DP_OP_234J324_132_4955_n19,
DP_OP_234J324_132_4955_n18, DP_OP_234J324_132_4955_n17,
DP_OP_234J324_132_4955_n16, DP_OP_234J324_132_4955_n15,
DP_OP_234J324_132_4955_n9, DP_OP_234J324_132_4955_n8,
DP_OP_234J324_132_4955_n7, DP_OP_234J324_132_4955_n6,
DP_OP_234J324_132_4955_n5, DP_OP_234J324_132_4955_n4,
DP_OP_234J324_132_4955_n3, DP_OP_234J324_132_4955_n2,
DP_OP_234J324_132_4955_n1, intadd_1104_A_8_, intadd_1104_A_1_,
intadd_1104_A_0_, intadd_1104_B_8_, intadd_1104_B_7_,
intadd_1104_B_2_, intadd_1104_B_1_, intadd_1104_B_0_, intadd_1104_CI,
intadd_1104_n9, intadd_1104_n8, intadd_1104_n7, intadd_1104_n6,
intadd_1104_n5, intadd_1104_n4, intadd_1104_n3, intadd_1104_n2,
intadd_1104_n1, intadd_1105_A_8_, intadd_1105_A_0_, intadd_1105_B_8_,
intadd_1105_B_7_, intadd_1105_B_2_, intadd_1105_B_1_,
intadd_1105_B_0_, intadd_1105_CI, intadd_1105_n9, intadd_1105_n8,
intadd_1105_n7, intadd_1105_n6, intadd_1105_n5, intadd_1105_n4,
intadd_1105_n3, intadd_1105_n2, intadd_1105_n1, intadd_1106_A_8_,
intadd_1106_A_0_, intadd_1106_B_8_, intadd_1106_B_7_,
intadd_1106_B_2_, intadd_1106_B_1_, intadd_1106_B_0_, intadd_1106_CI,
intadd_1106_n9, intadd_1106_n8, intadd_1106_n7, intadd_1106_n6,
intadd_1106_n5, intadd_1106_n4, intadd_1106_n3, intadd_1106_n2,
intadd_1106_n1, intadd_1107_A_1_, intadd_1107_A_0_, intadd_1107_B_7_,
intadd_1107_B_2_, intadd_1107_B_1_, intadd_1107_B_0_, intadd_1107_CI,
intadd_1107_n8, intadd_1107_n7, intadd_1107_n6, intadd_1107_n5,
intadd_1107_n4, intadd_1107_n3, intadd_1107_n2, intadd_1107_n1,
intadd_1108_CI, intadd_1108_n3, intadd_1108_n2, intadd_1108_n1,
intadd_1109_CI, intadd_1109_n3, intadd_1109_n2, intadd_1109_n1,
intadd_1110_CI, intadd_1110_SUM_2_, intadd_1110_SUM_1_,
intadd_1110_SUM_0_, intadd_1110_n3, intadd_1110_n2, intadd_1110_n1,
DP_OP_502J324_128_4510_n161, DP_OP_502J324_128_4510_n160,
DP_OP_502J324_128_4510_n76, DP_OP_502J324_128_4510_n75,
DP_OP_502J324_128_4510_n70, DP_OP_502J324_128_4510_n69,
DP_OP_502J324_128_4510_n68, DP_OP_502J324_128_4510_n67,
DP_OP_502J324_128_4510_n66, DP_OP_502J324_128_4510_n63,
DP_OP_502J324_128_4510_n62, DP_OP_502J324_128_4510_n61,
DP_OP_502J324_128_4510_n60, DP_OP_502J324_128_4510_n59,
DP_OP_502J324_128_4510_n57, DP_OP_502J324_128_4510_n56,
DP_OP_502J324_128_4510_n55, DP_OP_502J324_128_4510_n54,
DP_OP_502J324_128_4510_n53, DP_OP_502J324_128_4510_n41,
DP_OP_502J324_128_4510_n38, DP_OP_502J324_128_4510_n37,
DP_OP_502J324_128_4510_n36, DP_OP_502J324_128_4510_n35,
DP_OP_502J324_128_4510_n34, DP_OP_502J324_128_4510_n33,
DP_OP_502J324_128_4510_n32, DP_OP_502J324_128_4510_n31,
DP_OP_502J324_128_4510_n30, DP_OP_502J324_128_4510_n29,
DP_OP_502J324_128_4510_n27, DP_OP_502J324_128_4510_n26,
DP_OP_502J324_128_4510_n25, DP_OP_502J324_128_4510_n24,
DP_OP_502J324_128_4510_n23, DP_OP_502J324_128_4510_n22,
DP_OP_502J324_128_4510_n21, DP_OP_501J324_127_5235_n359,
DP_OP_501J324_127_5235_n330, DP_OP_501J324_127_5235_n302,
DP_OP_501J324_127_5235_n294, DP_OP_501J324_127_5235_n236,
DP_OP_501J324_127_5235_n235, DP_OP_501J324_127_5235_n234,
DP_OP_501J324_127_5235_n233, DP_OP_501J324_127_5235_n229,
DP_OP_501J324_127_5235_n227, DP_OP_501J324_127_5235_n226,
DP_OP_501J324_127_5235_n220, DP_OP_501J324_127_5235_n218,
DP_OP_501J324_127_5235_n215, DP_OP_501J324_127_5235_n210,
DP_OP_501J324_127_5235_n209, DP_OP_501J324_127_5235_n207,
DP_OP_501J324_127_5235_n206, DP_OP_501J324_127_5235_n202,
DP_OP_501J324_127_5235_n200, DP_OP_501J324_127_5235_n199,
DP_OP_501J324_127_5235_n195, DP_OP_501J324_127_5235_n194,
DP_OP_501J324_127_5235_n193, DP_OP_501J324_127_5235_n192,
DP_OP_501J324_127_5235_n191, DP_OP_501J324_127_5235_n190,
DP_OP_501J324_127_5235_n189, DP_OP_501J324_127_5235_n188,
DP_OP_501J324_127_5235_n186, DP_OP_501J324_127_5235_n184,
DP_OP_501J324_127_5235_n183, DP_OP_501J324_127_5235_n182,
DP_OP_501J324_127_5235_n181, DP_OP_501J324_127_5235_n179,
DP_OP_501J324_127_5235_n171, DP_OP_501J324_127_5235_n170,
DP_OP_501J324_127_5235_n168, DP_OP_501J324_127_5235_n167,
DP_OP_501J324_127_5235_n166, DP_OP_501J324_127_5235_n163,
DP_OP_501J324_127_5235_n162, DP_OP_501J324_127_5235_n161,
DP_OP_501J324_127_5235_n160, DP_OP_501J324_127_5235_n159,
DP_OP_501J324_127_5235_n158, DP_OP_501J324_127_5235_n156,
DP_OP_501J324_127_5235_n155, DP_OP_501J324_127_5235_n154,
DP_OP_501J324_127_5235_n153, DP_OP_501J324_127_5235_n152,
DP_OP_501J324_127_5235_n151, DP_OP_501J324_127_5235_n150,
DP_OP_501J324_127_5235_n148, DP_OP_501J324_127_5235_n147,
DP_OP_501J324_127_5235_n146, DP_OP_501J324_127_5235_n145,
DP_OP_501J324_127_5235_n144, DP_OP_501J324_127_5235_n143,
DP_OP_501J324_127_5235_n142, DP_OP_501J324_127_5235_n141,
DP_OP_501J324_127_5235_n140, DP_OP_501J324_127_5235_n139,
DP_OP_501J324_127_5235_n138, DP_OP_501J324_127_5235_n137,
DP_OP_501J324_127_5235_n136, DP_OP_501J324_127_5235_n135,
DP_OP_501J324_127_5235_n134, DP_OP_501J324_127_5235_n133,
DP_OP_501J324_127_5235_n132, DP_OP_501J324_127_5235_n131,
DP_OP_501J324_127_5235_n130, DP_OP_501J324_127_5235_n129,
DP_OP_501J324_127_5235_n128, DP_OP_501J324_127_5235_n127,
DP_OP_501J324_127_5235_n126, DP_OP_501J324_127_5235_n125,
DP_OP_501J324_127_5235_n124, DP_OP_501J324_127_5235_n123,
DP_OP_501J324_127_5235_n122, DP_OP_501J324_127_5235_n121,
DP_OP_501J324_127_5235_n120, DP_OP_501J324_127_5235_n119,
DP_OP_501J324_127_5235_n118, DP_OP_501J324_127_5235_n117,
DP_OP_501J324_127_5235_n116, DP_OP_501J324_127_5235_n115,
DP_OP_501J324_127_5235_n114, DP_OP_501J324_127_5235_n113,
DP_OP_501J324_127_5235_n112, DP_OP_501J324_127_5235_n111,
DP_OP_501J324_127_5235_n110, DP_OP_501J324_127_5235_n109,
DP_OP_501J324_127_5235_n77, DP_OP_501J324_127_5235_n72,
DP_OP_501J324_127_5235_n71, DP_OP_501J324_127_5235_n62,
DP_OP_501J324_127_5235_n59, DP_OP_501J324_127_5235_n58,
DP_OP_501J324_127_5235_n56, DP_OP_501J324_127_5235_n55,
DP_OP_501J324_127_5235_n54, DP_OP_501J324_127_5235_n53,
DP_OP_501J324_127_5235_n48, DP_OP_501J324_127_5235_n40,
DP_OP_501J324_127_5235_n39, DP_OP_501J324_127_5235_n37,
DP_OP_501J324_127_5235_n36, DP_OP_501J324_127_5235_n35,
DP_OP_501J324_127_5235_n34, DP_OP_501J324_127_5235_n32,
DP_OP_501J324_127_5235_n31, DP_OP_501J324_127_5235_n30,
DP_OP_501J324_127_5235_n29, DP_OP_501J324_127_5235_n28,
DP_OP_501J324_127_5235_n27, DP_OP_501J324_127_5235_n25,
DP_OP_501J324_127_5235_n24, DP_OP_501J324_127_5235_n23,
DP_OP_501J324_127_5235_n22, DP_OP_501J324_127_5235_n21,
DP_OP_501J324_127_5235_n20, DP_OP_501J324_127_5235_n19,
DP_OP_501J324_127_5235_n18, DP_OP_501J324_127_5235_n17,
DP_OP_501J324_127_5235_n16, DP_OP_501J324_127_5235_n15,
DP_OP_501J324_127_5235_n14, DP_OP_501J324_127_5235_n13,
DP_OP_500J324_126_4510_n161, DP_OP_500J324_126_4510_n160,
DP_OP_500J324_126_4510_n76, DP_OP_500J324_126_4510_n75,
DP_OP_500J324_126_4510_n70, DP_OP_500J324_126_4510_n69,
DP_OP_500J324_126_4510_n68, DP_OP_500J324_126_4510_n67,
DP_OP_500J324_126_4510_n66, DP_OP_500J324_126_4510_n63,
DP_OP_500J324_126_4510_n62, DP_OP_500J324_126_4510_n61,
DP_OP_500J324_126_4510_n60, DP_OP_500J324_126_4510_n59,
DP_OP_500J324_126_4510_n56, DP_OP_500J324_126_4510_n55,
DP_OP_500J324_126_4510_n54, DP_OP_500J324_126_4510_n53,
DP_OP_500J324_126_4510_n52, DP_OP_500J324_126_4510_n41,
DP_OP_500J324_126_4510_n38, DP_OP_500J324_126_4510_n37,
DP_OP_500J324_126_4510_n36, DP_OP_500J324_126_4510_n35,
DP_OP_500J324_126_4510_n34, DP_OP_500J324_126_4510_n33,
DP_OP_500J324_126_4510_n32, DP_OP_500J324_126_4510_n31,
DP_OP_500J324_126_4510_n30, DP_OP_500J324_126_4510_n29,
DP_OP_500J324_126_4510_n27, DP_OP_500J324_126_4510_n26,
DP_OP_500J324_126_4510_n25, DP_OP_500J324_126_4510_n24,
DP_OP_500J324_126_4510_n23, DP_OP_500J324_126_4510_n22,
DP_OP_500J324_126_4510_n21, DP_OP_497J324_123_3916_n59,
DP_OP_497J324_123_3916_n48, mult_x_313_n76, mult_x_313_n75,
mult_x_313_n74, mult_x_313_n69, mult_x_313_n68, mult_x_313_n67,
mult_x_313_n66, mult_x_313_n65, mult_x_313_n62, mult_x_313_n61,
mult_x_313_n60, mult_x_313_n59, mult_x_313_n58, mult_x_313_n56,
mult_x_313_n55, mult_x_313_n54, mult_x_313_n42, mult_x_313_n39,
mult_x_313_n38, mult_x_313_n37, mult_x_313_n36, mult_x_313_n35,
mult_x_313_n34, mult_x_313_n33, mult_x_313_n32, mult_x_313_n31,
mult_x_313_n30, mult_x_313_n29, mult_x_313_n28, mult_x_313_n27,
mult_x_313_n26, mult_x_313_n25, mult_x_313_n24, mult_x_313_n23,
mult_x_313_n22, mult_x_313_n21, DP_OP_499J324_125_1651_n150,
DP_OP_499J324_125_1651_n130, DP_OP_499J324_125_1651_n119,
DP_OP_499J324_125_1651_n118, DP_OP_499J324_125_1651_n117,
DP_OP_499J324_125_1651_n116, DP_OP_499J324_125_1651_n115,
DP_OP_499J324_125_1651_n114, DP_OP_499J324_125_1651_n113,
DP_OP_499J324_125_1651_n112, DP_OP_499J324_125_1651_n111,
DP_OP_499J324_125_1651_n110, DP_OP_499J324_125_1651_n109,
DP_OP_499J324_125_1651_n108, DP_OP_499J324_125_1651_n107,
DP_OP_499J324_125_1651_n106, DP_OP_499J324_125_1651_n105,
DP_OP_499J324_125_1651_n104, DP_OP_499J324_125_1651_n90,
DP_OP_499J324_125_1651_n88, DP_OP_499J324_125_1651_n87,
DP_OP_499J324_125_1651_n86, DP_OP_499J324_125_1651_n85,
DP_OP_499J324_125_1651_n84, DP_OP_499J324_125_1651_n83,
DP_OP_499J324_125_1651_n82, DP_OP_499J324_125_1651_n81,
DP_OP_499J324_125_1651_n80, DP_OP_499J324_125_1651_n79,
DP_OP_499J324_125_1651_n78, DP_OP_499J324_125_1651_n77,
DP_OP_499J324_125_1651_n76, DP_OP_499J324_125_1651_n75,
DP_OP_499J324_125_1651_n74, DP_OP_499J324_125_1651_n73,
DP_OP_499J324_125_1651_n72, DP_OP_499J324_125_1651_n71,
DP_OP_499J324_125_1651_n70, DP_OP_499J324_125_1651_n69,
DP_OP_499J324_125_1651_n68, DP_OP_499J324_125_1651_n67,
DP_OP_499J324_125_1651_n66, DP_OP_499J324_125_1651_n65,
DP_OP_499J324_125_1651_n64, DP_OP_499J324_125_1651_n63,
DP_OP_499J324_125_1651_n62, DP_OP_499J324_125_1651_n61,
DP_OP_499J324_125_1651_n60, DP_OP_499J324_125_1651_n59,
DP_OP_499J324_125_1651_n58, DP_OP_499J324_125_1651_n57,
DP_OP_499J324_125_1651_n56, DP_OP_499J324_125_1651_n55,
DP_OP_499J324_125_1651_n54, DP_OP_499J324_125_1651_n53,
DP_OP_499J324_125_1651_n52, DP_OP_499J324_125_1651_n51,
DP_OP_499J324_125_1651_n50, DP_OP_499J324_125_1651_n49,
DP_OP_499J324_125_1651_n48, DP_OP_499J324_125_1651_n47,
DP_OP_499J324_125_1651_n46, DP_OP_499J324_125_1651_n45,
DP_OP_499J324_125_1651_n44, DP_OP_499J324_125_1651_n43,
DP_OP_499J324_125_1651_n42, DP_OP_499J324_125_1651_n41,
DP_OP_499J324_125_1651_n40, DP_OP_499J324_125_1651_n34,
DP_OP_498J324_124_3916_n137, DP_OP_498J324_124_3916_n136,
DP_OP_498J324_124_3916_n124, n908, n909, n911, n912, n913, n914, n915,
n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926,
n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937,
n938, n940, n941, n942, n943, n944, n945, n946, n947, n948, n949,
n950, n951, n952, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1413, n1414, n1415, n1416,
n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2280, n2281, n2282, n2283, n2284, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369,
n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379,
n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429,
n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109,
n3110, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273,
n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283,
n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293,
n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303,
n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313,
n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323,
n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353,
n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363,
n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373,
n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383,
n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393,
n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403,
n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413,
n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423,
n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433,
n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443,
n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453,
n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463,
n3464, n3465, n3466, n3467, n3468, n3469, n3471, n3472, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:0] FPMULT_Op_MY;
wire [30:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:23] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [25:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [51:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [30:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:0] FPMULT_Sgf_operation_Result;
wire [5:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [24:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [13:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle;
wire [11:6] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [15:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle;
wire [13:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [13:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle;
wire [11:6] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(FPSENCOS_ITER_CONT_net8324057),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n844), .ENCLK(FPMULT_FS_Module_net8324003), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n873), .ENCLK(FPADDSUB_inst_ShiftRegister_net8323895),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[1]), .ENCLK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net8324021), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__19_net_), .ENCLK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
clk), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net8324021),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net8324021), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net8324021), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net8324021), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net8324021), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net8324021), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net8323787), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net8323787), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net8323967), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_EVEN1_finalreg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .TE(
1'b0) );
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n3422), .QN(
n916) );
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n3423), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n3432), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n3423), .Q(
dataA[28]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n3423), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n3422), .Q(
dataB[23]) );
DFFRXLTS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n3422), .QN(
n918) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n3422), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n3422), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n3422), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n3424), .Q(
dataB[31]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n3476), .CK(
FPADDSUB_inst_ShiftRegister_net8323895), .RN(n3405), .Q(
FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
FPADDSUB_inst_ShiftRegister_net8323895), .RN(n3385), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
FPADDSUB_inst_ShiftRegister_net8323895), .RN(n3403), .Q(
FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
FPADDSUB_inst_ShiftRegister_net8323895), .RN(n3402), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3400), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3404), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3397), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n970) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n850), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n860), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n854), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n862), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n851), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n853), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n857), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n3146), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n859), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n852), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n858), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n849), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n861), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n863), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n848), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n847), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n846), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n855), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3420), .Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3419), .Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3424), .Q(FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3432), .Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3432), .Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3432), .Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3432), .Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3432), .Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3431), .Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3431), .Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3430), .Q(
FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3431), .Q(
FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3430), .Q(
FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3430), .Q(
FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3429), .Q(cordic_result[23])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3429), .Q(cordic_result[24])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3429), .Q(cordic_result[25])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3428), .Q(cordic_result[26])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3428), .Q(cordic_result[27])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3428), .Q(cordic_result[28])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3428), .Q(cordic_result[29])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3428), .Q(cordic_result[30])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3427), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3386), .Q(
FPADDSUB_intDX_EWSW[28]), .QN(n969) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3390), .Q(
FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n938), .Q(
FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3377), .Q(
FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3390), .Q(
FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n938), .Q(
FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3379), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n967) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3378), .Q(
FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3404), .Q(
FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3390), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3400), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3391), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3387), .Q(
FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3377), .Q(
FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3388), .Q(
FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3381), .Q(
FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3402), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3376), .Q(
FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3398), .Q(
FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3380), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3389), .Q(
FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3376), .Q(
FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3398), .Q(
FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3402), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n937), .Q(
FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3387), .Q(
FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3400), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3397), .Q(
FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3380), .Q(
FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3390), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n937), .Q(
FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3389), .Q(
FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3376), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3380), .Q(
FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3380), .Q(
FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3401), .Q(
FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3397), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3398), .Q(
FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3379), .Q(
FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3376), .Q(
FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3403), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3376), .Q(
FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3397), .Q(
FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3388), .Q(
FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3404), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3426), .Q(
FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3426), .Q(
FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3426), .Q(cordic_result[22])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3392), .Q(
FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3380), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3426), .Q(
FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3426), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3426), .Q(
FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3425), .Q(cordic_result[19])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3396), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(FPADDSUB_Data_array_SWR[2]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3383), .Q(
FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3425), .Q(
FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3425), .Q(
FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3425), .Q(cordic_result[21])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3382), .Q(
FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n1964), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3425), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3425), .Q(
FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3425), .Q(
FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3424), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3428), .Q(
FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3413), .Q(
FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3412), .Q(cordic_result[2])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3412), .Q(
FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n1963), .Q(
FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3381), .Q(
FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3412), .Q(
FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3412), .Q(
FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3412), .Q(cordic_result[16])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n1962), .Q(
FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n2151), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3412), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3412), .Q(
FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3411), .Q(
FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3411), .Q(cordic_result[18])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3384), .Q(
FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3383), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(FPADDSUB_Data_array_SWR[3]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3382), .Q(
FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3411), .Q(
FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3411), .Q(
FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3411), .Q(cordic_result[20])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3411), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n1964), .Q(
FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n1963), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3410), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3410), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3410), .Q(
FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3410), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3410), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3410), .Q(
FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3410), .Q(cordic_result[17])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3410), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3410), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3381), .Q(
FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3386), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3410), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3410), .Q(
FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3410), .Q(
FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3410), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3410), .Q(
FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3410), .Q(
FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3409), .Q(cordic_result[4])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3409), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3409), .Q(
FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3386), .Q(
FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n2151), .Q(
FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3409), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3409), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3409), .Q(
FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3409), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3409), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3409), .Q(
FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3409), .Q(cordic_result[15])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3409), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3409), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n1962), .Q(
FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3386), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3409), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3409), .Q(
FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3408), .Q(
FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3408), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3408), .Q(
FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3408), .Q(
FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3408), .Q(cordic_result[5])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3408), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3408), .Q(
FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3385), .Q(
FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3384), .Q(
FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3408), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3408), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3408), .Q(
FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3408), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3408), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3408), .Q(
FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3408), .Q(cordic_result[13])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3408), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3383), .Q(
FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3382), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3407), .Q(
FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3407), .Q(
FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3407), .Q(cordic_result[14])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n1964), .Q(
FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n1963), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3407), .Q(
FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3407), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3434), .Q(
FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3434), .Q(cordic_result[11])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3434), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3381), .Q(
FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3386), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3437), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3435), .Q(
FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3435), .Q(
FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3435), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3435), .Q(
FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3423), .Q(
FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3434), .Q(cordic_result[8])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3422), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3424), .Q(
FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n938), .Q(
FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3389), .Q(
FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3435), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3423), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3406), .Q(
FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3406), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3406), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3406), .Q(
FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3406), .Q(cordic_result[10])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3406), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3406), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3391), .Q(
FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3392), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3406), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3406), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3406), .Q(
FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3406), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3406), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3406), .Q(
FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3409), .Q(cordic_result[12])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3418), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3418), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3390), .Q(
FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787),
.RN(n3378), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3418), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3418), .Q(
FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3418), .Q(
FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3418), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3418), .Q(
FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3418), .Q(
FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3418), .Q(cordic_result[9])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3418), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3418), .Q(
FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3418), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3418), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3418), .Q(
FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3417), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(FPSENCOS_d_ff5_data_out_net8324021), .RN(n3417), .Q(
cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3417), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3417), .Q(
FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3417), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3417), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3378), .Q(
FPADDSUB_intDX_EWSW[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3417), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3377), .QN(n913) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3393), .QN(n912) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3388), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3376), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3392), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n3379), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8323805), .RN(n1963), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3417), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3417), .Q(
FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3417), .Q(
FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3417), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3417), .Q(
FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3417), .Q(
FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3417), .Q(cordic_result[0])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3417), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3387), .Q(
FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3388), .Q(
FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n938), .Q(
FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3391), .Q(
FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3416), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3416), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3416), .Q(cordic_result[1])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3416), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3387), .Q(
FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3386), .Q(
FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3389), .Q(
FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3416), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3416), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3416), .Q(
FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3415), .Q(
FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3415), .Q(cordic_result[3])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3415), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3415), .Q(
FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3376), .Q(
FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3389), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3387), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n937), .Q(
FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3415), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3415), .Q(
FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3415), .Q(
FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3415), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3415), .Q(
FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3415), .Q(
FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3415), .Q(cordic_result[6])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3415), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3415), .Q(
FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3404), .Q(
FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3392), .Q(
FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3387), .Q(
FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n937), .Q(
FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3404), .Q(
FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Xn_net8324021), .RN(n3415), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3415), .Q(
FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3432), .Q(
FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Yn_net8324021), .RN(n3433), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3433), .Q(
FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3433), .Q(
FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
FPSENCOS_d_ff5_data_out_net8324021), .RN(n3433), .Q(cordic_result[7])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Zn_net8324021), .RN(n3433), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3432), .Q(
FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3389), .Q(
FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3400), .Q(
FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3379), .Q(
FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3393), .Q(
FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3389), .Q(
FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3400), .Q(
FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3379), .Q(
FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3378), .Q(
FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3378), .Q(
FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3378), .Q(
FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3397), .Q(
FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3402), .Q(
FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3402), .Q(
FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3402), .Q(
FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3396), .Q(
FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3396), .Q(
FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3396), .Q(
FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3396), .Q(
FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3396), .Q(
FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3396), .Q(
FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3379), .Q(
FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3404), .Q(
FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3402), .Q(
FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3397), .Q(
FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3400), .Q(
FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3398), .Q(
FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3398), .Q(
FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3387), .Q(
FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3402), .Q(
FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3381), .Q(
FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3388), .Q(
FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3393), .Q(
FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3380), .Q(
FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3398), .Q(
FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3388), .Q(
FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3403), .Q(
FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3389), .Q(FPADDSUB_N60) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n937), .Q(
FPADDSUB_DmP_mant_SFG_SWR[25]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(
FPMULT_Sgf_operation_Result[47]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3418), .Q(
FPMULT_P_Sgf[47]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n3206), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3447), .Q(
FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3438), .Q(
FPMULT_Op_MY[30]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3443), .Q(
FPMULT_Op_MY[29]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3441), .Q(
FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3449), .Q(
FPMULT_Op_MY[27]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3446), .Q(
FPMULT_Op_MY[26]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3444), .Q(
FPMULT_Op_MY[25]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3445), .Q(
FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3440), .Q(
FPMULT_Op_MY[23]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(Data_2[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3448), .Q(
FPMULT_Op_MY[13]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3449), .Q(
FPMULT_Op_MX[30]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3446), .Q(
FPMULT_Op_MX[29]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n115), .CK(
n3472), .RN(n3441), .Q(FPMULT_zero_flag) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(
FPMULT_Sgf_operation_Result[23]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3441), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3449), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3444), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3445), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3440), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3448), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3450), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3447), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net8323967), .RN(n3439), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3438), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n3500), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3443), .Q(
FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n3498), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3449), .Q(
FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n3496), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3446), .Q(
FPMULT_Sgf_normalized_result[19]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n3494), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3442), .Q(
FPMULT_Sgf_normalized_result[17]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n3492), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3442), .Q(
FPMULT_Sgf_normalized_result[15]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n3490), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3442), .Q(
FPMULT_Sgf_normalized_result[13]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n3488), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3442), .Q(
FPMULT_Sgf_normalized_result[11]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n3486), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3448), .Q(
FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n3484), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3450), .Q(
FPMULT_Sgf_normalized_result[7]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n3482), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3447), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n3480), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3439), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3438), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3449), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3446), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3444), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3445), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3440), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3448), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3450), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3447), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3439), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3438), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3443), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3441), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3443), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3441), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3449), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3446), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3444), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3445), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3440), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3444), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3445), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3440), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3448), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3450), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3441), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3449), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3446), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3444), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3445), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3440), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8323733), .RN(
n3448), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n3467), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3402), .Q(
underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n3468), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3403), .Q(
overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n3466), .CK(
FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3380), .Q(
FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n817), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3399), .Q(
FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3397), .Q(
FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n814), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3401), .Q(
FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(
FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8323787), .RN(n3393), .Q(
FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n811), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3387), .Q(
FPADDSUB_OP_FLAG_SHT2) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_14_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_15_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_Result[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_Result[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_Result[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_Result[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_1106_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_1105_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_1104_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13])
);
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(clk), .EN(n3474), .ENCLK(n3472), .TE(1'b0) );
CMPR42X1TS mult_x_312_U22 ( .A(mult_x_312_n77), .B(mult_x_312_n67), .C(
mult_x_312_n72), .D(mult_x_312_n42), .ICI(mult_x_312_n39), .S(
mult_x_312_n37), .ICO(mult_x_312_n35), .CO(mult_x_312_n36) );
CMPR42X1TS mult_x_312_U19 ( .A(mult_x_312_n71), .B(mult_x_312_n38), .C(
mult_x_312_n35), .D(mult_x_312_n34), .ICI(mult_x_312_n32), .S(
mult_x_312_n30), .ICO(mult_x_312_n28), .CO(mult_x_312_n29) );
CMPR42X1TS mult_x_312_U16 ( .A(mult_x_312_n33), .B(mult_x_312_n31), .C(
mult_x_312_n27), .D(mult_x_312_n25), .ICI(mult_x_312_n28), .S(
mult_x_312_n23), .ICO(mult_x_312_n21), .CO(mult_x_312_n22) );
CMPR42X1TS mult_x_312_U14 ( .A(mult_x_312_n59), .B(mult_x_312_n26), .C(
mult_x_312_n24), .D(mult_x_312_n20), .ICI(mult_x_312_n21), .S(
mult_x_312_n18), .ICO(mult_x_312_n16), .CO(mult_x_312_n17) );
CMPR42X1TS mult_x_312_U13 ( .A(mult_x_312_n58), .B(mult_x_312_n48), .C(
mult_x_312_n53), .D(mult_x_312_n19), .ICI(mult_x_312_n16), .S(
mult_x_312_n15), .ICO(mult_x_312_n13), .CO(mult_x_312_n14) );
CMPR42X1TS mult_x_309_U23 ( .A(mult_x_309_n76), .B(mult_x_309_n66), .C(
mult_x_309_n71), .D(mult_x_309_n42), .ICI(mult_x_309_n39), .S(
mult_x_309_n37), .ICO(mult_x_309_n35), .CO(mult_x_309_n36) );
CMPR42X1TS mult_x_309_U20 ( .A(mult_x_309_n65), .B(mult_x_309_n38), .C(
mult_x_309_n35), .D(mult_x_309_n34), .ICI(mult_x_309_n32), .S(
mult_x_309_n30), .ICO(mult_x_309_n28), .CO(mult_x_309_n29) );
CMPR42X1TS mult_x_309_U17 ( .A(mult_x_309_n33), .B(mult_x_309_n27), .C(
mult_x_309_n31), .D(mult_x_309_n25), .ICI(mult_x_309_n28), .S(
mult_x_309_n23), .ICO(mult_x_309_n21), .CO(mult_x_309_n22) );
CMPR42X1TS mult_x_309_U15 ( .A(mult_x_309_n58), .B(mult_x_309_n26), .C(
mult_x_309_n20), .D(mult_x_309_n24), .ICI(mult_x_309_n21), .S(
mult_x_309_n18), .ICO(mult_x_309_n16), .CO(mult_x_309_n17) );
CMPR42X1TS mult_x_309_U14 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MY[21]), .C(
mult_x_309_n52), .D(mult_x_309_n19), .ICI(mult_x_309_n16), .S(
mult_x_309_n15), .ICO(mult_x_309_n13), .CO(mult_x_309_n14) );
CMPR32X2TS DP_OP_26J324_129_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n909), .C(DP_OP_26J324_129_1325_n18), .CO(DP_OP_26J324_129_1325_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J324_129_1325_U8 ( .A(DP_OP_26J324_129_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J324_129_1325_n8), .CO(
DP_OP_26J324_129_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J324_129_1325_U7 ( .A(DP_OP_26J324_129_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J324_129_1325_n7), .CO(
DP_OP_26J324_129_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J324_129_1325_U6 ( .A(DP_OP_26J324_129_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J324_129_1325_n6), .CO(
DP_OP_26J324_129_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_234J324_132_4955_U2 ( .A(FPMULT_FSM_exp_operation_A_S), .B(
FPMULT_S_Oper_A_exp[8]), .C(DP_OP_234J324_132_4955_n2), .CO(
DP_OP_234J324_132_4955_n1), .S(FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_1104_U9 ( .A(intadd_1104_A_1_), .B(intadd_1104_B_1_), .C(
intadd_1104_n9), .CO(intadd_1104_n8), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1104_U8 ( .A(mult_x_312_n37), .B(intadd_1104_B_2_), .C(
intadd_1104_n8), .CO(intadd_1104_n7), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1104_U7 ( .A(mult_x_312_n36), .B(mult_x_312_n30), .C(
intadd_1104_n7), .CO(intadd_1104_n6), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1104_U6 ( .A(mult_x_312_n29), .B(mult_x_312_n23), .C(
intadd_1104_n6), .CO(intadd_1104_n5), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1104_U5 ( .A(mult_x_312_n22), .B(mult_x_312_n18), .C(
intadd_1104_n5), .CO(intadd_1104_n4), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1104_U4 ( .A(mult_x_312_n17), .B(mult_x_312_n15), .C(
intadd_1104_n4), .CO(intadd_1104_n3), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1104_U3 ( .A(mult_x_312_n14), .B(intadd_1104_B_7_), .C(
intadd_1104_n3), .CO(intadd_1104_n2), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1104_U2 ( .A(intadd_1104_A_8_), .B(intadd_1104_B_8_), .C(
intadd_1104_n2), .CO(intadd_1104_n1), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1105_U10 ( .A(intadd_1105_A_0_), .B(intadd_1105_B_0_), .C(
intadd_1105_CI), .CO(intadd_1105_n9), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
CMPR32X2TS intadd_1105_U8 ( .A(mult_x_311_n37), .B(intadd_1105_B_2_), .C(
intadd_1105_n8), .CO(intadd_1105_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1105_U7 ( .A(mult_x_311_n36), .B(mult_x_311_n30), .C(
intadd_1105_n7), .CO(intadd_1105_n6), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1105_U2 ( .A(intadd_1105_A_8_), .B(intadd_1105_B_8_), .C(
intadd_1105_n2), .CO(intadd_1105_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1106_U10 ( .A(intadd_1106_A_0_), .B(intadd_1106_B_0_), .C(
intadd_1106_CI), .CO(intadd_1106_n9), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
CMPR32X2TS intadd_1106_U9 ( .A(n3251), .B(intadd_1106_B_1_), .C(
intadd_1106_n9), .CO(intadd_1106_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1106_U7 ( .A(mult_x_310_n36), .B(mult_x_310_n30), .C(
intadd_1106_n7), .CO(intadd_1106_n6), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1106_U2 ( .A(intadd_1106_A_8_), .B(intadd_1106_B_8_), .C(
intadd_1106_n2), .CO(intadd_1106_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_1107_U7 ( .A(mult_x_309_n37), .B(intadd_1107_B_2_), .C(
intadd_1107_n7), .CO(intadd_1107_n6), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1107_U6 ( .A(mult_x_309_n36), .B(mult_x_309_n30), .C(
intadd_1107_n6), .CO(intadd_1107_n5), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_1107_U5 ( .A(mult_x_309_n29), .B(mult_x_309_n23), .C(
intadd_1107_n5), .CO(intadd_1107_n4), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1107_U4 ( .A(mult_x_309_n22), .B(mult_x_309_n18), .C(
intadd_1107_n4), .CO(intadd_1107_n3), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1107_U3 ( .A(mult_x_309_n17), .B(mult_x_309_n15), .C(
intadd_1107_n3), .CO(intadd_1107_n2), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1110_U4 ( .A(FPADDSUB_DmP_EXP_EWSW[24]), .B(n3346), .C(
intadd_1110_CI), .CO(intadd_1110_n3), .S(intadd_1110_SUM_0_) );
CMPR32X2TS intadd_1110_U3 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n3345), .C(
intadd_1110_n3), .CO(intadd_1110_n2), .S(intadd_1110_SUM_1_) );
CMPR32X2TS intadd_1110_U2 ( .A(FPADDSUB_DmP_EXP_EWSW[26]), .B(n3361), .C(
intadd_1110_n2), .CO(intadd_1110_n1), .S(intadd_1110_SUM_2_) );
DFFSX2TS R_12 ( .D(n3370), .CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733),
.SN(n3391), .Q(n3465) );
DFFSX2TS R_13 ( .D(n3369), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .SN(n3432), .Q(n3463)
);
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(
FPSENCOS_reg_shift_y_net8324021), .RN(n3435), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3387), .Q(
FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n3362) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3389), .Q(
FPADDSUB_intDY_EWSW[0]), .QN(n3357) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3390), .Q(
FPADDSUB_intDY_EWSW[26]), .QN(n3355) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3392), .Q(
FPADDSUB_intDY_EWSW[1]), .QN(n3354) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1964), .Q(
FPADDSUB_intDY_EWSW[18]), .QN(n3353) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3391), .Q(
FPADDSUB_intDY_EWSW[8]), .QN(n3352) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3377), .Q(
FPADDSUB_intDY_EWSW[25]), .QN(n3351) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3386), .Q(
FPADDSUB_intDY_EWSW[17]), .QN(n3350) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1964), .Q(
FPADDSUB_intDY_EWSW[11]), .QN(n3348) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n3478), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3440), .Q(
FPMULT_Sgf_normalized_result[1]), .QN(n3347) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1962), .Q(
FPADDSUB_intDY_EWSW[20]), .QN(n3342) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3385), .Q(
FPADDSUB_intDY_EWSW[21]), .QN(n3341) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3377), .Q(
FPADDSUB_intDY_EWSW[27]), .QN(n3340) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3379), .Q(
FPADDSUB_intDY_EWSW[9]), .QN(n3339) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n938), .Q(
FPADDSUB_intDY_EWSW[24]), .QN(n3338) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3384), .Q(
FPADDSUB_intDY_EWSW[2]), .QN(n3337) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1964), .Q(
FPADDSUB_intDY_EWSW[13]), .QN(n3336) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1963), .Q(
FPADDSUB_intDY_EWSW[4]), .QN(n3335) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3384), .Q(
FPADDSUB_intDY_EWSW[16]), .QN(n3334) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3387), .Q(
FPADDSUB_intDY_EWSW[6]), .QN(n3333) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3393), .Q(
FPADDSUB_intDY_EWSW[10]), .QN(n3332) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3404), .Q(
FPADDSUB_intDX_EWSW[12]), .QN(n3331) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3387), .Q(
FPADDSUB_DMP_SFG[22]), .QN(n3328) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3397), .Q(
FPADDSUB_intDX_EWSW[22]), .QN(n3324) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[25]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3404), .Q(
FPADDSUB_Data_array_SWR[51]), .QN(n3323) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3382), .Q(
FPADDSUB_intDX_EWSW[14]), .QN(n3322) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3398), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n3321) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3398), .Q(
FPADDSUB_DMP_SFG[20]), .QN(n3320) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n825), .CK(FPMULT_FS_Module_net8324003),
.RN(n3450), .Q(FPMULT_FSM_selector_C), .QN(n3319) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1963), .QN(n3318)
);
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n3476), .CK(
clk), .RN(n3403), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n3317) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(FPADDSUB_Data_array_SWR[23]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n937), .Q(
FPADDSUB_Data_array_SWR[49]), .QN(n3313) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3392), .Q(
FPADDSUB_intDX_EWSW[30]), .QN(n3311) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3376), .Q(
FPADDSUB_intDX_EWSW[29]), .QN(n3310) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3393), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n3309) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3376), .Q(
FPADDSUB_intDX_EWSW[3]), .QN(n3308) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3405), .Q(
FPADDSUB_intDX_EWSW[8]), .QN(n3307) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3381), .Q(
FPADDSUB_intDX_EWSW[25]), .QN(n3305) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3385), .Q(
FPADDSUB_intDX_EWSW[17]), .QN(n3304) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3378), .Q(
FPADDSUB_intDX_EWSW[1]), .QN(n3303) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3383), .Q(
FPADDSUB_intDX_EWSW[15]), .QN(n3302) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3389), .Q(
FPADDSUB_intDX_EWSW[19]), .QN(n3301) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3383), .Q(
FPADDSUB_intDX_EWSW[11]), .QN(n3298) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3400), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n3297) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3379), .Q(
FPADDSUB_DMP_SFG[18]), .QN(n3295) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3388), .Q(
FPADDSUB_DMP_SFG[17]), .QN(n3294) );
DFFRX2TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n3379), .QN(n3293) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3380), .Q(
result_add_subt[23]), .QN(n3292) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3398), .Q(
result_add_subt[24]), .QN(n3291) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3376), .Q(
result_add_subt[25]), .QN(n3290) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3389), .Q(
result_add_subt[26]), .QN(n3289) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3387), .Q(
result_add_subt[27]), .QN(n3288) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3397), .Q(
result_add_subt[28]), .QN(n3287) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3385), .Q(
result_add_subt[29]), .QN(n3286) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3380), .Q(
result_add_subt[30]), .QN(n3285) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3385), .Q(
result_add_subt[0]), .QN(n3284) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3390), .Q(
result_add_subt[1]), .QN(n3283) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3382), .Q(
result_add_subt[2]), .QN(n3282) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3389), .Q(
result_add_subt[3]), .QN(n3281) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3382), .Q(
result_add_subt[4]), .QN(n3280) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3381), .Q(
result_add_subt[5]), .QN(n3279) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n937), .Q(
result_add_subt[6]), .QN(n3278) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3400), .Q(
result_add_subt[7]), .QN(n3277) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3390), .Q(
result_add_subt[8]), .QN(n3276) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3397), .Q(
result_add_subt[9]), .QN(n3275) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3391), .Q(
result_add_subt[10]), .QN(n3274) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3381), .Q(
result_add_subt[11]), .QN(n3273) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3377), .Q(
result_add_subt[12]), .QN(n3272) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3386), .Q(
result_add_subt[13]), .QN(n3271) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3384), .Q(
result_add_subt[14]), .QN(n3270) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n1964), .Q(
result_add_subt[15]), .QN(n3269) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3386), .Q(
result_add_subt[16]), .QN(n3268) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3382), .Q(
result_add_subt[17]), .QN(n3267) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3385), .Q(
result_add_subt[18]), .QN(n3266) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3402), .Q(
result_add_subt[19]), .QN(n3265) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3381), .Q(
result_add_subt[20]), .QN(n3264) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n1962), .Q(
result_add_subt[21]), .QN(n3263) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3401), .Q(
result_add_subt[22]), .QN(n3262) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8323733), .RN(n3378), .Q(
result_add_subt[31]), .QN(n3261) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n938), .Q(
FPADDSUB_intDY_EWSW[30]), .QN(n3260) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3388), .Q(
FPADDSUB_DMP_SFG[16]), .QN(n3258) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3388), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n3256) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n3254) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(FPMULT_FS_Module_net8324003),
.RN(n3434), .Q(FPMULT_FS_Module_state_reg[1]), .QN(n3253) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_SFG[14]), .QN(n3252) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n829), .CK(FPMULT_FS_Module_net8324003),
.RN(n3440), .Q(FPMULT_FSM_selector_B[0]), .QN(n3250) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3388), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n3249) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3400), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n3247) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3377), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n3246) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_SFG[12]), .QN(n3240) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[15]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n937), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n3239) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3395), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n3234) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[13]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3400), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n3229) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3382), .Q(
FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n3224) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_SFG[10]), .QN(n3223) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3394), .Q(
FPADDSUB_DMP_SFG[9]), .QN(n3222) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3389), .Q(
FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n3219) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT2_EWSW[8]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_SFG[8]), .QN(n3218) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3405), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n3216) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT2_EWSW[6]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3393), .Q(
FPADDSUB_DMP_SFG[6]), .QN(n3215) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3401), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n3213) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT2_EWSW[4]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3386), .Q(
FPADDSUB_DMP_SFG[4]), .QN(n3212) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3402), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n3211) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DMP_SFG[2]), .QN(n3210) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3378), .Q(
FPADDSUB_DMP_SFG[0]), .QN(n3209) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3392), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n3208) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3396), .Q(
FPADDSUB_intDY_EWSW[22]), .QN(n3207) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n3477), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3445), .Q(
FPMULT_Sgf_normalized_result[0]), .QN(n3206) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3399), .Q(
FPADDSUB_intDY_EWSW[19]), .QN(n3205) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[24]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3391), .Q(
FPADDSUB_Data_array_SWR[50]), .QN(n3204) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1963), .Q(
FPADDSUB_intDY_EWSW[14]), .QN(n3203) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3403), .Q(
FPADDSUB_intDX_EWSW[23]), .QN(n3202) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_DMP_SFG[21]), .QN(n3201) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3405), .Q(
FPADDSUB_DMP_SFG[19]), .QN(n3199) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3405), .Q(
FPADDSUB_intDX_EWSW[24]), .QN(n3198) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n2151), .Q(
FPADDSUB_intDX_EWSW[20]), .QN(n3197) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1963), .Q(
FPADDSUB_intDX_EWSW[18]), .QN(n3196) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n938), .Q(
FPADDSUB_intDX_EWSW[0]), .QN(n3194) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3383), .Q(
FPADDSUB_intDX_EWSW[21]), .QN(n3193) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3398), .Q(
FPADDSUB_intDX_EWSW[26]), .QN(n3192) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3379), .QN(n3191)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3393), .Q(
FPADDSUB_intDX_EWSW[27]), .QN(n3190) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3399), .Q(
FPADDSUB_intDX_EWSW[9]), .QN(n3189) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3384), .Q(
FPADDSUB_intDX_EWSW[2]), .QN(n3188) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n1963), .Q(
FPADDSUB_intDX_EWSW[13]), .QN(n3186) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3390), .Q(
FPADDSUB_intDY_EWSW[29]), .QN(n3185) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3380), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n3184) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3399), .Q(
FPADDSUB_DMP_SFG[15]), .QN(n3182) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n938), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n3181) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3396), .Q(
FPADDSUB_DMP_SFG[13]), .QN(n3176) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3395), .Q(
FPADDSUB_DMP_SFG[11]), .QN(n3170) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[11]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n3164) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT2_EWSW[7]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3389), .Q(
FPADDSUB_DMP_SFG[7]), .QN(n3161) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT2_EWSW[5]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3396), .Q(
FPADDSUB_DMP_SFG[5]), .QN(n3160) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT2_EWSW[3]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3392), .Q(
FPADDSUB_DMP_SFG[3]), .QN(n3159) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT2_EWSW[1]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3387), .Q(
FPADDSUB_DMP_SFG[1]), .QN(n3158) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n3424), .Q(NaN_flag)
);
CMPR32X2TS intadd_1107_U2 ( .A(mult_x_309_n14), .B(intadd_1107_B_7_), .C(
intadd_1107_n2), .CO(intadd_1107_n1), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS DP_OP_234J324_132_4955_U9 ( .A(DP_OP_234J324_132_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J324_132_4955_n9), .CO(
DP_OP_234J324_132_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J324_132_4955_U8 ( .A(DP_OP_234J324_132_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J324_132_4955_n8), .CO(
DP_OP_234J324_132_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J324_132_4955_U7 ( .A(DP_OP_234J324_132_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J324_132_4955_n7), .CO(
DP_OP_234J324_132_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J324_132_4955_U6 ( .A(DP_OP_234J324_132_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J324_132_4955_n6), .CO(
DP_OP_234J324_132_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J324_132_4955_U5 ( .A(DP_OP_234J324_132_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J324_132_4955_n5), .CO(
DP_OP_234J324_132_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J324_132_4955_U4 ( .A(DP_OP_234J324_132_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J324_132_4955_n4), .CO(
DP_OP_234J324_132_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J324_132_4955_U3 ( .A(DP_OP_234J324_132_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J324_132_4955_n3), .CO(
DP_OP_234J324_132_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_26J324_129_1325_U5 ( .A(DP_OP_26J324_129_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J324_129_1325_n5), .CO(
DP_OP_26J324_129_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J324_129_1325_U4 ( .A(n909), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J324_129_1325_n4), .CO(
DP_OP_26J324_129_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J324_129_1325_U3 ( .A(n909), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J324_129_1325_n3), .CO(
DP_OP_26J324_129_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS intadd_1105_U9 ( .A(n3235), .B(intadd_1105_B_1_), .C(
intadd_1105_n9), .CO(intadd_1105_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_1105_U6 ( .A(mult_x_311_n29), .B(mult_x_311_n23), .C(
intadd_1105_n6), .CO(intadd_1105_n5), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1105_U5 ( .A(mult_x_311_n22), .B(mult_x_311_n18), .C(
intadd_1105_n5), .CO(intadd_1105_n4), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1105_U4 ( .A(mult_x_311_n17), .B(mult_x_311_n15), .C(
intadd_1105_n4), .CO(intadd_1105_n3), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1105_U3 ( .A(mult_x_311_n14), .B(intadd_1105_B_7_), .C(
intadd_1105_n3), .CO(intadd_1105_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1106_U8 ( .A(mult_x_310_n37), .B(intadd_1106_B_2_), .C(
intadd_1106_n8), .CO(intadd_1106_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_1106_U6 ( .A(mult_x_310_n29), .B(mult_x_310_n23), .C(
intadd_1106_n6), .CO(intadd_1106_n5), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_1106_U5 ( .A(mult_x_310_n22), .B(mult_x_310_n18), .C(
intadd_1106_n5), .CO(intadd_1106_n4), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_1106_U4 ( .A(mult_x_310_n17), .B(mult_x_310_n15), .C(
intadd_1106_n4), .CO(intadd_1106_n3), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_1106_U3 ( .A(mult_x_310_n14), .B(intadd_1106_B_7_), .C(
intadd_1106_n3), .CO(intadd_1106_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_1107_U8 ( .A(intadd_1107_A_1_), .B(intadd_1107_B_1_), .C(
intadd_1107_n8), .CO(intadd_1107_n7), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS DP_OP_26J324_129_1325_U2 ( .A(n909), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J324_129_1325_n2), .CO(
DP_OP_26J324_129_1325_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR42X1TS DP_OP_502J324_128_4510_U25 ( .A(DP_OP_502J324_128_4510_n70), .B(
DP_OP_502J324_128_4510_n76), .C(DP_OP_502J324_128_4510_n57), .D(
DP_OP_502J324_128_4510_n63), .ICI(DP_OP_502J324_128_4510_n41), .S(
DP_OP_502J324_128_4510_n38), .ICO(DP_OP_502J324_128_4510_n36), .CO(
DP_OP_502J324_128_4510_n37) );
CMPR42X1TS DP_OP_502J324_128_4510_U24 ( .A(DP_OP_502J324_128_4510_n75), .B(
DP_OP_502J324_128_4510_n69), .C(DP_OP_502J324_128_4510_n62), .D(
DP_OP_502J324_128_4510_n56), .ICI(DP_OP_502J324_128_4510_n36), .S(
DP_OP_502J324_128_4510_n35), .ICO(DP_OP_502J324_128_4510_n33), .CO(
DP_OP_502J324_128_4510_n34) );
CMPR42X1TS DP_OP_502J324_128_4510_U22 ( .A(DP_OP_502J324_128_4510_n32), .B(
DP_OP_502J324_128_4510_n68), .C(DP_OP_502J324_128_4510_n61), .D(
DP_OP_502J324_128_4510_n55), .ICI(DP_OP_502J324_128_4510_n33), .S(
DP_OP_502J324_128_4510_n31), .ICO(DP_OP_502J324_128_4510_n29), .CO(
DP_OP_502J324_128_4510_n30) );
CMPR42X1TS DP_OP_502J324_128_4510_U20 ( .A(DP_OP_502J324_128_4510_n32), .B(
DP_OP_502J324_128_4510_n67), .C(DP_OP_502J324_128_4510_n60), .D(
DP_OP_502J324_128_4510_n54), .ICI(DP_OP_502J324_128_4510_n29), .S(
DP_OP_502J324_128_4510_n26), .ICO(DP_OP_502J324_128_4510_n24), .CO(
DP_OP_502J324_128_4510_n25) );
CMPR42X1TS DP_OP_502J324_128_4510_U19 ( .A(n962), .B(
DP_OP_502J324_128_4510_n66), .C(DP_OP_502J324_128_4510_n59), .D(
DP_OP_502J324_128_4510_n53), .ICI(DP_OP_502J324_128_4510_n24), .S(
DP_OP_502J324_128_4510_n23), .ICO(DP_OP_502J324_128_4510_n21), .CO(
DP_OP_502J324_128_4510_n22) );
CMPR42X1TS DP_OP_501J324_127_5235_U113 ( .A(DP_OP_501J324_127_5235_n229),
.B(DP_OP_501J324_127_5235_n215), .C(DP_OP_501J324_127_5235_n171), .D(
DP_OP_501J324_127_5235_n170), .ICI(DP_OP_501J324_127_5235_n236), .S(
DP_OP_501J324_127_5235_n168), .ICO(DP_OP_501J324_127_5235_n166), .CO(
DP_OP_501J324_127_5235_n167) );
CMPR42X1TS DP_OP_501J324_127_5235_U110 ( .A(DP_OP_501J324_127_5235_n207),
.B(DP_OP_501J324_127_5235_n166), .C(DP_OP_501J324_127_5235_n235), .D(
DP_OP_501J324_127_5235_n200), .ICI(DP_OP_501J324_127_5235_n163), .S(
DP_OP_501J324_127_5235_n161), .ICO(DP_OP_501J324_127_5235_n159), .CO(
DP_OP_501J324_127_5235_n160) );
CMPR42X1TS DP_OP_501J324_127_5235_U108 ( .A(DP_OP_501J324_127_5235_n220),
.B(DP_OP_501J324_127_5235_n206), .C(DP_OP_501J324_127_5235_n158), .D(
DP_OP_501J324_127_5235_n227), .ICI(DP_OP_501J324_127_5235_n162), .S(
DP_OP_501J324_127_5235_n156), .ICO(DP_OP_501J324_127_5235_n154), .CO(
DP_OP_501J324_127_5235_n155) );
CMPR42X1TS DP_OP_501J324_127_5235_U107 ( .A(DP_OP_501J324_127_5235_n199),
.B(DP_OP_501J324_127_5235_n159), .C(DP_OP_501J324_127_5235_n234), .D(
DP_OP_501J324_127_5235_n192), .ICI(DP_OP_501J324_127_5235_n160), .S(
DP_OP_501J324_127_5235_n153), .ICO(DP_OP_501J324_127_5235_n151), .CO(
DP_OP_501J324_127_5235_n152) );
CMPR42X1TS DP_OP_501J324_127_5235_U104 ( .A(DP_OP_501J324_127_5235_n150),
.B(DP_OP_501J324_127_5235_n154), .C(DP_OP_501J324_127_5235_n233), .D(
DP_OP_501J324_127_5235_n184), .ICI(DP_OP_501J324_127_5235_n155), .S(
DP_OP_501J324_127_5235_n146), .ICO(DP_OP_501J324_127_5235_n144), .CO(
DP_OP_501J324_127_5235_n145) );
CMPR42X1TS DP_OP_501J324_127_5235_U97 ( .A(DP_OP_501J324_127_5235_n182), .B(
DP_OP_501J324_127_5235_n139), .C(DP_OP_501J324_127_5235_n189), .D(
DP_OP_501J324_127_5235_n210), .ICI(DP_OP_501J324_127_5235_n134), .S(
DP_OP_501J324_127_5235_n128), .ICO(DP_OP_501J324_127_5235_n126), .CO(
DP_OP_501J324_127_5235_n127) );
CMPR42X1TS DP_OP_501J324_127_5235_U96 ( .A(DP_OP_501J324_127_5235_n137), .B(
DP_OP_501J324_127_5235_n130), .C(DP_OP_501J324_127_5235_n131), .D(
DP_OP_501J324_127_5235_n135), .ICI(DP_OP_501J324_127_5235_n128), .S(
DP_OP_501J324_127_5235_n125), .ICO(DP_OP_501J324_127_5235_n123), .CO(
DP_OP_501J324_127_5235_n124) );
CMPR42X1TS DP_OP_501J324_127_5235_U95 ( .A(DP_OP_501J324_127_5235_n195), .B(
DP_OP_501J324_127_5235_n209), .C(DP_OP_501J324_127_5235_n181), .D(
DP_OP_501J324_127_5235_n188), .ICI(DP_OP_501J324_127_5235_n202), .S(
DP_OP_501J324_127_5235_n122), .ICO(DP_OP_501J324_127_5235_n120), .CO(
DP_OP_501J324_127_5235_n121) );
CMPR42X1TS DP_OP_501J324_127_5235_U94 ( .A(DP_OP_501J324_127_5235_n129), .B(
DP_OP_501J324_127_5235_n126), .C(DP_OP_501J324_127_5235_n127), .D(
DP_OP_501J324_127_5235_n122), .ICI(DP_OP_501J324_127_5235_n123), .S(
DP_OP_501J324_127_5235_n119), .ICO(DP_OP_501J324_127_5235_n117), .CO(
DP_OP_501J324_127_5235_n118) );
CMPR42X1TS DP_OP_501J324_127_5235_U92 ( .A(DP_OP_501J324_127_5235_n194), .B(
DP_OP_501J324_127_5235_n120), .C(DP_OP_501J324_127_5235_n116), .D(
DP_OP_501J324_127_5235_n121), .ICI(DP_OP_501J324_127_5235_n117), .S(
DP_OP_501J324_127_5235_n114), .ICO(DP_OP_501J324_127_5235_n112), .CO(
DP_OP_501J324_127_5235_n113) );
CMPR42X1TS DP_OP_501J324_127_5235_U91 ( .A(DP_OP_501J324_127_5235_n193), .B(
DP_OP_501J324_127_5235_n179), .C(DP_OP_501J324_127_5235_n186), .D(
DP_OP_501J324_127_5235_n115), .ICI(DP_OP_501J324_127_5235_n112), .S(
DP_OP_501J324_127_5235_n111), .ICO(DP_OP_501J324_127_5235_n109), .CO(
DP_OP_501J324_127_5235_n110) );
CMPR42X1TS DP_OP_501J324_127_5235_U22 ( .A(DP_OP_501J324_127_5235_n72), .B(
DP_OP_501J324_127_5235_n62), .C(DP_OP_501J324_127_5235_n40), .D(
DP_OP_501J324_127_5235_n39), .ICI(DP_OP_501J324_127_5235_n77), .S(
DP_OP_501J324_127_5235_n37), .ICO(DP_OP_501J324_127_5235_n35), .CO(
DP_OP_501J324_127_5235_n36) );
CMPR42X1TS DP_OP_501J324_127_5235_U19 ( .A(DP_OP_501J324_127_5235_n34), .B(
DP_OP_501J324_127_5235_n71), .C(DP_OP_501J324_127_5235_n56), .D(
DP_OP_501J324_127_5235_n32), .ICI(DP_OP_501J324_127_5235_n35), .S(
DP_OP_501J324_127_5235_n30), .ICO(DP_OP_501J324_127_5235_n28), .CO(
DP_OP_501J324_127_5235_n29) );
CMPR42X1TS DP_OP_501J324_127_5235_U16 ( .A(DP_OP_501J324_127_5235_n55), .B(
DP_OP_501J324_127_5235_n31), .C(DP_OP_501J324_127_5235_n27), .D(
DP_OP_501J324_127_5235_n28), .ICI(DP_OP_501J324_127_5235_n25), .S(
DP_OP_501J324_127_5235_n23), .ICO(DP_OP_501J324_127_5235_n21), .CO(
DP_OP_501J324_127_5235_n22) );
CMPR42X1TS DP_OP_501J324_127_5235_U14 ( .A(DP_OP_501J324_127_5235_n59), .B(
DP_OP_501J324_127_5235_n54), .C(DP_OP_501J324_127_5235_n20), .D(
DP_OP_501J324_127_5235_n24), .ICI(DP_OP_501J324_127_5235_n21), .S(
DP_OP_501J324_127_5235_n18), .ICO(DP_OP_501J324_127_5235_n16), .CO(
DP_OP_501J324_127_5235_n17) );
CMPR42X1TS DP_OP_501J324_127_5235_U13 ( .A(DP_OP_501J324_127_5235_n58), .B(
DP_OP_501J324_127_5235_n48), .C(DP_OP_501J324_127_5235_n53), .D(
DP_OP_501J324_127_5235_n19), .ICI(DP_OP_501J324_127_5235_n16), .S(
DP_OP_501J324_127_5235_n15), .ICO(DP_OP_501J324_127_5235_n13), .CO(
DP_OP_501J324_127_5235_n14) );
CMPR42X1TS DP_OP_500J324_126_4510_U25 ( .A(DP_OP_500J324_126_4510_n70), .B(
DP_OP_500J324_126_4510_n56), .C(DP_OP_500J324_126_4510_n76), .D(
DP_OP_500J324_126_4510_n41), .ICI(DP_OP_500J324_126_4510_n63), .S(
DP_OP_500J324_126_4510_n38), .ICO(DP_OP_500J324_126_4510_n36), .CO(
DP_OP_500J324_126_4510_n37) );
CMPR42X1TS DP_OP_500J324_126_4510_U24 ( .A(DP_OP_500J324_126_4510_n75), .B(
DP_OP_500J324_126_4510_n69), .C(DP_OP_500J324_126_4510_n55), .D(
DP_OP_500J324_126_4510_n62), .ICI(DP_OP_500J324_126_4510_n36), .S(
DP_OP_500J324_126_4510_n35), .ICO(DP_OP_500J324_126_4510_n33), .CO(
DP_OP_500J324_126_4510_n34) );
CMPR42X1TS DP_OP_500J324_126_4510_U22 ( .A(DP_OP_500J324_126_4510_n32), .B(
DP_OP_500J324_126_4510_n68), .C(DP_OP_500J324_126_4510_n54), .D(
DP_OP_500J324_126_4510_n61), .ICI(DP_OP_500J324_126_4510_n33), .S(
DP_OP_500J324_126_4510_n31), .ICO(DP_OP_500J324_126_4510_n29), .CO(
DP_OP_500J324_126_4510_n30) );
CMPR42X1TS DP_OP_500J324_126_4510_U20 ( .A(DP_OP_500J324_126_4510_n32), .B(
DP_OP_500J324_126_4510_n67), .C(DP_OP_500J324_126_4510_n53), .D(
DP_OP_500J324_126_4510_n60), .ICI(DP_OP_500J324_126_4510_n29), .S(
DP_OP_500J324_126_4510_n26), .ICO(DP_OP_500J324_126_4510_n24), .CO(
DP_OP_500J324_126_4510_n25) );
CMPR42X1TS DP_OP_500J324_126_4510_U19 ( .A(DP_OP_500J324_126_4510_n27), .B(
DP_OP_500J324_126_4510_n66), .C(DP_OP_500J324_126_4510_n52), .D(
DP_OP_500J324_126_4510_n59), .ICI(DP_OP_500J324_126_4510_n24), .S(
DP_OP_500J324_126_4510_n23), .ICO(DP_OP_500J324_126_4510_n21), .CO(
DP_OP_500J324_126_4510_n22) );
CMPR42X1TS mult_x_313_U25 ( .A(mult_x_313_n56), .B(mult_x_313_n76), .C(
mult_x_313_n69), .D(mult_x_313_n62), .ICI(mult_x_313_n42), .S(
mult_x_313_n39), .ICO(mult_x_313_n37), .CO(mult_x_313_n38) );
CMPR42X1TS mult_x_313_U24 ( .A(mult_x_313_n75), .B(mult_x_313_n55), .C(
mult_x_313_n61), .D(mult_x_313_n68), .ICI(mult_x_313_n37), .S(
mult_x_313_n36), .ICO(mult_x_313_n34), .CO(mult_x_313_n35) );
CMPR42X1TS mult_x_313_U22 ( .A(mult_x_313_n67), .B(mult_x_313_n60), .C(
mult_x_313_n74), .D(mult_x_313_n33), .ICI(mult_x_313_n34), .S(
mult_x_313_n31), .ICO(mult_x_313_n29), .CO(mult_x_313_n30) );
CMPR42X1TS mult_x_313_U20 ( .A(mult_x_313_n66), .B(mult_x_313_n32), .C(
mult_x_313_n59), .D(mult_x_313_n28), .ICI(mult_x_313_n29), .S(
mult_x_313_n26), .ICO(mult_x_313_n24), .CO(mult_x_313_n25) );
CMPR42X1TS mult_x_313_U19 ( .A(mult_x_313_n27), .B(mult_x_313_n58), .C(
mult_x_313_n54), .D(mult_x_313_n65), .ICI(mult_x_313_n24), .S(
mult_x_313_n23), .ICO(mult_x_313_n21), .CO(mult_x_313_n22) );
DFFRX1TS R_11 ( .D(n3371), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3448), .Q(n3461)
);
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n3175), .CK(
FPSENCOS_ITER_CONT_net8324057), .RN(n3424), .Q(
FPSENCOS_cont_iter_out[0]), .QN(n3175) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
FPADDSUB_inst_ShiftRegister_net8323895), .RN(n3404), .Q(busy), .QN(
n3364) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
FPSENCOS_ITER_CONT_net8324057), .RN(n3421), .Q(
FPSENCOS_cont_iter_out[2]), .QN(n3146) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
FPSENCOS_ITER_CONT_net8324057), .RN(n3421), .Q(
FPSENCOS_cont_iter_out[3]), .QN(n3151) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n830), .CK(FPMULT_FS_Module_net8324003),
.RN(n3449), .Q(FPMULT_FSM_selector_B[1]), .QN(n3255) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(FPMULT_FS_Module_net8324003),
.RN(n3434), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n3147) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(Data_2[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3438), .Q(
FPMULT_Op_MY[8]), .QN(n3171) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(Data_2[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3443), .Q(
FPMULT_Op_MY[10]), .QN(n3173) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3439), .Q(
FPMULT_Op_MY[9]), .QN(n3178) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(Data_2[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3438), .Q(
FPMULT_Op_MY[21]), .QN(n3228) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3447), .Q(
FPMULT_Op_MY[6]), .QN(n3172) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(Data_2[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3450), .Q(
FPMULT_Op_MY[4]), .QN(n3174) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(Data_2[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3449), .Q(
FPMULT_Op_MY[2]), .QN(n3232) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3441), .Q(
FPMULT_Op_MY[0]), .QN(n3179) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(Data_2[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3439), .Q(
FPMULT_Op_MY[20]), .QN(n3217) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(Data_2[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3450), .Q(
FPMULT_Op_MY[11]), .QN(n3177) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(Data_2[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3447), .Q(
FPMULT_Op_MY[19]), .QN(n3145) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(Data_2[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3449), .Q(
FPMULT_Op_MY[18]), .QN(n3214) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(Data_2[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3441), .Q(
FPMULT_Op_MY[16]), .QN(n3237) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(Data_2[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3446), .Q(
FPMULT_Op_MY[14]), .QN(n3227) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(Data_2[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3444), .Q(
FPMULT_Op_MY[17]), .QN(n3236) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(Data_2[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3445), .Q(
FPMULT_Op_MY[15]), .QN(n3238) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(Data_2[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3446), .Q(
FPMULT_Op_MY[5]), .QN(n3183) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(Data_2[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3444), .Q(
FPMULT_Op_MY[22]), .QN(n3226) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(Data_2[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3448), .Q(
FPMULT_Op_MY[3]), .QN(n3180) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3441), .Q(
FPMULT_Op_MX[5]), .QN(n3257) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(Data_1[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3444), .Q(
FPMULT_Op_MX[22]), .QN(n3162) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(Data_1[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3440), .Q(
FPMULT_Op_MX[20]), .QN(n3166) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(Data_1[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3444), .Q(
FPMULT_Op_MX[18]), .QN(n3148) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3443), .Q(
FPMULT_Op_MX[9]), .QN(n3243) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(Data_1[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3445), .Q(
FPMULT_Op_MX[19]), .QN(n3163) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(Data_1[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3438), .Q(
FPMULT_Op_MX[16]), .QN(n3167) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(Data_1[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3439), .Q(
FPMULT_Op_MX[15]), .QN(n3152) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(Data_1[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3449), .Q(
FPMULT_Op_MX[11]), .QN(n3244) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3441), .Q(
FPMULT_Op_MX[7]), .QN(n3225) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(Data_1[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3447), .Q(
FPMULT_Op_MX[17]), .QN(n3150) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3446), .Q(
FPMULT_Op_MX[6]), .QN(n3230) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(Data_1[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3443), .Q(
FPMULT_Op_MX[21]), .QN(n3149) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3450), .Q(
FPMULT_Op_MX[8]), .QN(n3157) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3446), .Q(
FPMULT_Op_MX[3]), .QN(n3154) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3377), .Q(
FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n3325) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n841), .CK(clk), .RN(n3423), .Q(
FPSENCOS_cont_var_out[0]), .QN(n3155) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3382), .Q(
FPADDSUB_intDX_EWSW[16]), .QN(n3316) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3378), .Q(
FPADDSUB_intDX_EWSW[10]), .QN(n3299) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3392), .Q(
FPADDSUB_intDX_EWSW[6]), .QN(n3306) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3385), .Q(
FPADDSUB_intDY_EWSW[15]), .QN(n3349) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3393), .Q(
FPADDSUB_intDY_EWSW[7]), .QN(n3329) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3383), .Q(
FPADDSUB_intDY_EWSW[5]), .QN(n3330) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3385), .Q(
FPADDSUB_intDY_EWSW[3]), .QN(n3356) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3393), .Q(
FPADDSUB_intDY_EWSW[23]), .QN(n3358) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3379), .Q(
FPADDSUB_intDY_EWSW[12]), .QN(n3300) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3384), .Q(
FPADDSUB_intDX_EWSW[4]), .QN(n3195) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
FPADDSUB_inst_ShiftRegister_net8323895), .RN(n3392), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n3220) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(Data_2[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3440), .Q(
FPMULT_Op_MY[12]), .QN(n3221) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3448), .Q(
FPMULT_Op_MX[0]), .QN(n3156) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3440), .Q(
FPMULT_Op_MX[2]), .QN(n3245) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(Data_1[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3440), .Q(
FPMULT_Op_MX[14]), .QN(n3168) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3445), .Q(
FPMULT_Op_MX[1]), .QN(n3231) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(Data_1[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3448), .Q(
FPMULT_Op_MX[13]), .QN(n3169) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(Data_1[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3445), .Q(
FPMULT_Op_MX[12]), .QN(n3153) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(FPMULT_Op_MY[12]), .RN(FPMULT_Op_MX[12]), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_Q_left[0]), .QN(DP_OP_499J324_125_1651_n150) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(FPMULT_Op_MX[6]), .RN(FPMULT_Op_MY[6]), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .QN(
DP_OP_498J324_124_3916_n137) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(FPMULT_Op_MX[0]), .RN(FPMULT_Op_MY[0]), .CK(clk), .Q(
FPMULT_Sgf_operation_Result[0]), .QN(DP_OP_499J324_125_1651_n34) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(FPMULT_Op_MY[18]), .RN(FPMULT_Op_MX[18]), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .QN(
DP_OP_497J324_123_3916_n59) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n3454), .RN(n3453), .CK(clk), .Q(FPMULT_Sgf_operation_Result[1]),
.QN(DP_OP_498J324_124_3916_n124) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(DP_OP_502J324_128_4510_n160), .RN(DP_OP_502J324_128_4510_n161),
.CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n961), .RN(DP_OP_500J324_126_4510_n161), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(DP_OP_501J324_127_5235_n330), .RN(DP_OP_501J324_127_5235_n359),
.CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .QN(
DP_OP_496J324_122_3236_n68) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .RN(n936), .CK(clk),
.Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .QN(
DP_OP_496J324_122_3236_n17) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(DP_OP_501J324_127_5235_n294), .RN(n941), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(n3142), .RN(n3143), .CK(clk), .Q(DP_OP_497J324_123_3916_n48), .QN(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n3437), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFSX1TS R_1 ( .D(n3375), .CK(clk), .SN(n3423), .Q(n3459) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n3421), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n3187) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
FPADDSUB_Raw_mant_SGF[25]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3391), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n3248) );
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n3472), .RN(n3440), .Q(
FPMULT_FSM_selector_A) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n840), .CK(clk), .RN(n3422), .Q(
FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3397), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n1964), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3404), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3388), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3377), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8323733), .RN(n3377), .Q(
FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3397), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[14]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3401), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[12]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3389), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[10]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3403), .Q(
FPADDSUB_DmP_mant_SFG_SWR[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3387), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3380), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3399), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3400), .Q(
FPADDSUB_DmP_mant_SFG_SWR[22]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3398), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3402), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3391), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3390), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n842), .CK(clk), .RN(n3394), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3397), .Q(
FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(FPADDSUB_Data_array_SWR[17]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3404), .Q(
FPADDSUB_Data_array_SWR[43]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(FPADDSUB_Data_array_SWR[16]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3381), .Q(
FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3378), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(FPADDSUB_Data_array_SWR[18]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3383), .Q(
FPADDSUB_Data_array_SWR[44]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(FPADDSUB_Data_array_SWR[19]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3384), .Q(
FPADDSUB_Data_array_SWR[45]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n937), .Q(
FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(FPMULT_FS_Module_net8324003),
.RN(n3434), .Q(FPMULT_FS_Module_state_reg[2]), .QN(n3344) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(FPADDSUB_Data_array_SWR[9]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n1962), .Q(
FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(FPADDSUB_Data_array_SWR[8]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3396), .Q(
FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(FPADDSUB_Data_array_SWR[11]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3378), .Q(
FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(FPADDSUB_Data_array_SWR[10]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3387), .Q(
FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n3479), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3444), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n930), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n938), .Q(
FPADDSUB_bit_shift_SHT2) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n3481), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3443), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n3422), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(n932), .CK(clk), .RN(n3406), .Q(
operation_reg[0]) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3421), .Q(
FPSENCOS_d_ff1_shift_region_flag_out[1]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n3424),
.Q(operation_reg[1]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n3421), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n3483), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3438), .Q(
FPMULT_Sgf_normalized_result[6]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n3485), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3439), .Q(
FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n3487), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3447), .Q(
FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n3489), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3446), .Q(
FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n3491), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3443), .Q(
FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n3493), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3438), .Q(
FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n3495), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3439), .Q(
FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n3497), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3447), .Q(
FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n3499), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8323931), .RN(n3450), .Q(
FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
FPADDSUB_inst_ShiftRegister_net8323895), .RN(n3402), .Q(
FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX1TS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n3432), .Q(
dataA[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff2_X[25]) );
DFFSX1TS R_19 ( .D(n3367), .CK(clk), .SN(n3422), .Q(n3458) );
DFFSX1TS R_4 ( .D(n3372), .CK(clk), .SN(n3423), .Q(n3456) );
DFFSX1TS R_2 ( .D(n3374), .CK(clk), .SN(n3422), .Q(n3460) );
DFFSX1TS R_3 ( .D(n3373), .CK(clk), .SN(n3423), .Q(n3455) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n3422), .Q(
dataB[30]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3378), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(FPADDSUB_Data_array_SWR[13]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3378), .Q(
FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(FPADDSUB_Data_array_SWR[12]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3377), .Q(
FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(FPADDSUB_Data_array_SWR[14]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n938), .Q(
FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(FPADDSUB_Data_array_SWR[15]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3385), .Q(
FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3390), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3391), .Q(
FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n3423), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3397), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n3259) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
FPSENCOS_ITER_CONT_net8324057), .RN(n3424), .Q(
FPSENCOS_cont_iter_out[1]), .QN(n3242) );
DFFRX4TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(FPMULT_FS_Module_net8324003),
.RN(n3435), .Q(FPMULT_FS_Module_state_reg[0]), .QN(n3165) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n3475), .CK(
FPSENCOS_reg_Z0_net8324021), .RN(n3420), .Q(
FPSENCOS_d_ff1_operation_out) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3399), .Q(FPADDSUB_N59) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n3421), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n3436), .Q(
dataB[28]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n3436), .Q(
dataB[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n3469), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3405), .Q(
FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3444), .Q(
FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3445), .Q(
FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3440), .Q(
FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3445), .Q(
FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3448), .Q(
FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3444), .Q(
FPMULT_Op_MX[25]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n3423), .Q(
dataA[29]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(FPADDSUB_Data_array_SWR[6]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3381), .Q(
FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(
FPMULT_Adder_M_result_A_adder[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3450), .Q(
FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(
FPMULT_Sgf_operation_Result[46]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[46]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n3423), .Q(
dataA[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(FPADDSUB_Data_array_SWR[5]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3385), .Q(
FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(FPADDSUB_Data_array_SWR[7]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3386), .Q(
FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(FPADDSUB_Data_array_SWR[4]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3401), .Q(
FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(
FPMULT_Adder_M_result_A_adder[21]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3447), .Q(
FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3439), .Q(
FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3443), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3438), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3447), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3440), .Q(
FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3450), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3438), .Q(
FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3439), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n1961), .Q(
FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3442), .Q(
FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n2150), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(
FPMULT_Adder_M_result_A_adder[23]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3439), .Q(
FPMULT_Add_result[23]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(
FPMULT_Sgf_operation_Result[44]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(
FPMULT_Sgf_operation_Result[43]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(
FPMULT_Sgf_operation_Result[42]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(
FPMULT_Sgf_operation_Result[41]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(
FPMULT_Sgf_operation_Result[40]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(
FPMULT_Sgf_operation_Result[39]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(
FPMULT_Sgf_operation_Result[38]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(
FPMULT_Sgf_operation_Result[37]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(
FPMULT_Sgf_operation_Result[36]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(
FPMULT_Sgf_operation_Result[35]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(
FPMULT_Sgf_operation_Result[34]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(
FPMULT_Sgf_operation_Result[33]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(
FPMULT_Sgf_operation_Result[32]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(
FPMULT_Sgf_operation_Result[31]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(
FPMULT_Sgf_operation_Result[30]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(
FPMULT_Sgf_operation_Result[29]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(
FPMULT_Sgf_operation_Result[28]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(
FPMULT_Sgf_operation_Result[27]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(
FPMULT_Sgf_operation_Result[26]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(
FPMULT_Sgf_operation_Result[25]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(
FPMULT_Sgf_operation_Result[24]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3414), .Q(
FPMULT_P_Sgf[24]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n3424), .Q(
dataA[23]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8323769), .RN(n3378), .Q(
FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n3233) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(
FPMULT_Sgf_operation_Result[45]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .RN(n3413), .Q(
FPMULT_P_Sgf[45]) );
DFFSXLTS R_14 ( .D(n3368), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .SN(n3433), .Q(n3464)
);
DFFRX1TS R_20 ( .D(n3366), .CK(clk), .RN(n3424), .Q(n3457) );
DFFSXLTS R_21 ( .D(n3365), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8323949), .SN(n3414), .Q(n3462)
);
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n872), .CK(clk), .RN(n3405), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n3326) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n3424), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n3241) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n3421), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n3296) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff2_X[23]), .QN(n3315) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3428), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n3359) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3429), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n3314) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3391), .Q(
FPADDSUB_DMP_EXP_EWSW[26]), .QN(n3361) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3393), .Q(
FPADDSUB_DMP_EXP_EWSW[25]), .QN(n3345) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8323787), .RN(n3392), .Q(
FPADDSUB_DMP_EXP_EWSW[24]), .QN(n3346) );
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n3471), .CK(n3472),
.RN(n3444), .Q(underflow_flag_mult), .QN(n3363) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(FPADDSUB_Data_array_SWR[20]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n1964), .Q(
FPADDSUB_Data_array_SWR[46]), .QN(n3327) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(FPADDSUB_Data_array_SWR[22]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n938), .Q(
FPADDSUB_Data_array_SWR[48]), .QN(n3312) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(FPADDSUB_Data_array_SWR[21]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3397), .Q(
FPADDSUB_Data_array_SWR[47]), .QN(n3200) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(
FPMULT_Adder_M_result_A_adder[24]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8323913), .RN(n3445), .Q(
FPMULT_FSM_add_overflow_flag), .QN(n3343) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n937), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8324021), .RN(n3430), .Q(FPSENCOS_d_ff2_X[28]), .QN(n3360) );
DFFTRX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n3144), .RN(n974), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .QN(
DP_OP_498J324_124_3916_n136) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(Data_2[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3441), .Q(
FPMULT_Op_MY[1]), .QN(n973) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3445), .Q(
FPMULT_Op_MX[4]), .QN(n972) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(Data_2[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3443), .Q(
FPMULT_Op_MY[7]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(Data_1[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8323985), .RN(n3444), .Q(
FPMULT_Op_MX[10]), .QN(n971) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n808), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n3376), .Q(
FPADDSUB_ADD_OVRFLW_NRM2), .QN(n909) );
CMPR32X2TS intadd_1107_U9 ( .A(intadd_1107_A_0_), .B(intadd_1107_B_0_), .C(
intadd_1107_CI), .CO(intadd_1107_n8), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
CMPR32X2TS DP_OP_234J324_132_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_234J324_132_4955_n22), .CO(
DP_OP_234J324_132_4955_n9), .S(FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS intadd_1104_U10 ( .A(intadd_1104_A_0_), .B(intadd_1104_B_0_), .C(
intadd_1104_CI), .CO(intadd_1104_n9), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n3451), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8323769), .RN(n937), .Q(
FPADDSUB_left_right_SHT2), .QN(n911) );
CMPR32X2TS intadd_1109_U4 ( .A(n3242), .B(FPSENCOS_d_ff2_Y[24]), .C(
intadd_1109_CI), .CO(intadd_1109_n3), .S(FPSENCOS_sh_exp_y[1]) );
CMPR32X2TS intadd_1108_U4 ( .A(n3242), .B(FPSENCOS_d_ff2_X[24]), .C(
intadd_1108_CI), .CO(intadd_1108_n3), .S(FPSENCOS_sh_exp_x[1]) );
CMPR32X2TS intadd_1109_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n3146), .C(
intadd_1109_n3), .CO(intadd_1109_n2), .S(FPSENCOS_sh_exp_y[2]) );
CMPR32X2TS intadd_1108_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n3146), .C(
intadd_1108_n3), .CO(intadd_1108_n2), .S(FPSENCOS_sh_exp_x[2]) );
CMPR32X2TS intadd_1108_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n3151), .C(
intadd_1108_n2), .CO(intadd_1108_n1), .S(FPSENCOS_sh_exp_x[3]) );
CMPR32X2TS intadd_1109_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n3151), .C(
intadd_1109_n2), .CO(intadd_1109_n1), .S(FPSENCOS_sh_exp_y[3]) );
DFFRX4TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
FPADDSUB_SGF_STAGE_DMP_net8323787), .RN(n3402), .Q(n908), .QN(n3452)
);
NOR2X4TS U1397 ( .A(n925), .B(n2057), .Y(n2041) );
AOI211X2TS U1398 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n2034), .B0(n2053),
.C0(n2035), .Y(n2181) );
OR2X2TS U1399 ( .A(n3090), .B(operation[2]), .Y(n3105) );
OR2X2TS U1400 ( .A(n3016), .B(n932), .Y(n2324) );
AOI211X2TS U1401 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n2034), .B0(n2053),
.C0(n2052), .Y(n2072) );
INVX2TS U1402 ( .A(n931), .Y(n932) );
NAND2X1TS U1403 ( .A(DP_OP_499J324_125_1651_n41), .B(n1081), .Y(n1088) );
AOI222X4TS U1404 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(FPADDSUB_DMP_SFG[14]), .B1(n2375),
.C0(FPADDSUB_DmP_mant_SFG_SWR[16]), .C1(n2375), .Y(n2894) );
CMPR32X4TS U1405 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[17]), .C(n1385),
.CO(n1552), .S(n1645) );
NAND2X1TS U1406 ( .A(n2507), .B(n3219), .Y(n2493) );
AOI222X4TS U1407 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(FPADDSUB_DMP_SFG[10]), .B1(n2315),
.C0(FPADDSUB_DmP_mant_SFG_SWR[12]), .C1(n2315), .Y(n2320) );
CMPR32X2TS U1408 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[10]), .C(n1741),
.CO(n1781), .S(n1742) );
CMPR32X4TS U1409 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[15]), .C(n1350),
.CO(n1352), .S(n1612) );
NAND2X1TS U1410 ( .A(n2504), .B(n1929), .Y(n1939) );
CMPR32X2TS U1411 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[7]), .C(n1746), .CO(
n1748), .S(n1759) );
CMPR32X2TS U1412 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[20]), .C(n1457),
.CO(n1448), .S(n1460) );
CMPR32X2TS U1413 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[8]), .C(n1744), .CO(
n1739), .S(n1747) );
CMPR32X4TS U1414 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .C(n1349),
.CO(n1354), .S(n1593) );
NAND2X1TS U1415 ( .A(n2501), .B(n1928), .Y(n2503) );
AOI222X4TS U1416 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(FPADDSUB_DMP_SFG[6]), .B1(n2252),
.C0(FPADDSUB_DmP_mant_SFG_SWR[8]), .C1(n2252), .Y(n2292) );
NOR2X1TS U1417 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n1933), .Y(n1928) );
CMPR32X2TS U1418 ( .A(n1003), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .C(
n1002), .CO(n1001), .S(n1046) );
AOI22X1TS U1419 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n3213), .B0(n2245), .B1(
n2244), .Y(n2250) );
CMPR32X2TS U1420 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[19]), .C(n1555),
.CO(n1556), .S(DP_OP_501J324_127_5235_n330) );
CMPR32X2TS U1421 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .C(n1352),
.CO(n1385), .S(n1623) );
CMPR32X2TS U1422 ( .A(n1855), .B(n1854), .C(n1853), .CO(n1861), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
CMPR32X2TS U1423 ( .A(n1285), .B(n1284), .C(n1283), .CO(
DP_OP_499J324_125_1651_n88), .S(n1237) );
CMPR32X2TS U1424 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .B(n1076), .C(n1075), .CO(n1284), .S(n1242) );
CMPR32X2TS U1425 ( .A(n1263), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .C(n1262),
.CO(n1257), .S(n2203) );
CMPR32X2TS U1426 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]), .B(
n1144), .C(n1143), .CO(n1145), .S(n1142) );
CMPR32X2TS U1427 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]), .B(
n1140), .C(n1139), .CO(n1141), .S(n1136) );
CMPR32X2TS U1428 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]), .B(
n1128), .C(n1127), .CO(n1135), .S(n1133) );
CMPR32X2TS U1429 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]), .B(
n1126), .C(n1077), .CO(n1134), .S(n1132) );
NOR2X1TS U1430 ( .A(n1210), .B(n1215), .Y(n1123) );
CMPR32X2TS U1431 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]), .B(
n1125), .C(n1078), .CO(n1131), .S(n1130) );
OAI21X2TS U1432 ( .A0(n1118), .A1(n1117), .B0(n1116), .Y(n1209) );
CMPR32X2TS U1433 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3]), .B(
n1124), .C(n1079), .CO(n1129), .S(n1121) );
INVX2TS U1434 ( .A(n1166), .Y(n1156) );
NAND2X1TS U1435 ( .A(n1155), .B(n1154), .Y(n1166) );
OR2X1TS U1436 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .B(
DP_OP_498J324_124_3916_n137), .Y(n975) );
NOR2XLTS U1437 ( .A(n1717), .B(n1667), .Y(DP_OP_501J324_127_5235_n184) );
OAI21XLTS U1438 ( .A0(mult_x_313_n74), .A1(n1427), .B0(n1612), .Y(
mult_x_313_n65) );
NOR2XLTS U1439 ( .A(n1718), .B(n1713), .Y(n1715) );
NOR2XLTS U1440 ( .A(n960), .B(n1518), .Y(n1475) );
INVX2TS U1441 ( .A(n1275), .Y(n966) );
OAI21XLTS U1442 ( .A0(n2371), .A1(n2374), .B0(n2370), .Y(n2369) );
INVX2TS U1443 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n2926) );
NOR2XLTS U1444 ( .A(n1736), .B(n1579), .Y(n1565) );
NOR2XLTS U1445 ( .A(n1667), .B(n1726), .Y(n1689) );
XOR2X1TS U1446 ( .A(n1042), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n1276)
);
AFHCINX2TS U1447 ( .CIN(n1308), .B(n1309), .A(n1310), .S(
FPMULT_Sgf_operation_Result[36]), .CO(n1280) );
OAI21XLTS U1448 ( .A0(n2471), .A1(n2944), .B0(n2470), .Y(
FPADDSUB_Data_array_SWR[4]) );
OAI21XLTS U1449 ( .A0(n2473), .A1(n944), .B0(n2443), .Y(
FPADDSUB_Data_array_SWR[15]) );
OAI21XLTS U1450 ( .A0(n2455), .A1(n944), .B0(n2445), .Y(
FPADDSUB_Data_array_SWR[11]) );
OAI211XLTS U1451 ( .A0(n2449), .A1(n2386), .B0(n2453), .C0(n2388), .Y(
FPADDSUB_Data_array_SWR[0]) );
OAI21XLTS U1452 ( .A0(n2439), .A1(n2944), .B0(n2438), .Y(
FPADDSUB_Data_array_SWR[3]) );
BUFX4TS U1453 ( .A(n3005), .Y(n3090) );
INVX4TS U1454 ( .A(operation[1]), .Y(n931) );
INVX4TS U1455 ( .A(n932), .Y(n3005) );
XOR2X2TS U1456 ( .A(n1277), .B(n1276), .Y(FPMULT_Sgf_operation_Result[47])
);
ADDHX1TS U1457 ( .A(n1279), .B(n1278), .CO(n1347), .S(
FPMULT_Sgf_operation_Result[45]) );
NAND2X2TS U1458 ( .A(n1275), .B(n1274), .Y(n1342) );
INVX4TS U1459 ( .A(n1341), .Y(n1275) );
XOR2X1TS U1460 ( .A(n2926), .B(n2925), .Y(FPADDSUB_Raw_mant_SGF[25]) );
XOR2X1TS U1461 ( .A(n2898), .B(n2897), .Y(FPADDSUB_Raw_mant_SGF[17]) );
NOR2X1TS U1462 ( .A(n1725), .B(n1677), .Y(n1655) );
AOI21X1TS U1463 ( .A0(n1168), .A1(n979), .B0(n1156), .Y(n1165) );
XNOR2X1TS U1464 ( .A(n1208), .B(n1207), .Y(n1290) );
XNOR2X1TS U1465 ( .A(n1214), .B(n1213), .Y(n1292) );
AOI21X1TS U1466 ( .A0(n1208), .A1(n976), .B0(n977), .Y(n1181) );
OAI22X1TS U1467 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n3212), .B0(n2198),
.B1(n2197), .Y(n2244) );
OAI21X1TS U1468 ( .A0(n1198), .A1(n1204), .B0(n1205), .Y(n1203) );
XOR2X1TS U1469 ( .A(n1219), .B(n1218), .Y(n1294) );
NOR2X1TS U1470 ( .A(n1182), .B(n1193), .Y(n1185) );
NAND2X1TS U1471 ( .A(n1212), .B(n1211), .Y(n1213) );
NAND2X2TS U1472 ( .A(n1217), .B(n1216), .Y(n1219) );
BUFX4TS U1473 ( .A(n3059), .Y(n3030) );
INVX3TS U1474 ( .A(n1215), .Y(n1217) );
OAI21X1TS U1475 ( .A0(n1210), .A1(n1216), .B0(n1211), .Y(n1122) );
OR2X2TS U1476 ( .A(n1155), .B(n1154), .Y(n979) );
NAND2BX1TS U1477 ( .AN(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(n1851)
);
ADDHX2TS U1478 ( .A(n1348), .B(n1347), .CO(n1277), .S(
FPMULT_Sgf_operation_Result[46]) );
XOR2X1TS U1479 ( .A(n966), .B(n1109), .Y(FPMULT_Sgf_operation_Result[38]) );
NOR2X1TS U1480 ( .A(n966), .B(n1301), .Y(n1302) );
NOR2X1TS U1481 ( .A(n966), .B(n1109), .Y(n1307) );
NOR2X1TS U1482 ( .A(n966), .B(n1304), .Y(n1306) );
NOR2X1TS U1483 ( .A(n1341), .B(n1295), .Y(n1296) );
NOR2X1TS U1484 ( .A(n1341), .B(n1298), .Y(n1300) );
XOR2X1TS U1485 ( .A(n2918), .B(n2917), .Y(FPADDSUB_Raw_mant_SGF[24]) );
OAI32X1TS U1486 ( .A0(n2924), .A1(n2923), .A2(n2922), .B0(n2921), .B1(n2920),
.Y(n2925) );
OR2X2TS U1487 ( .A(DP_OP_499J324_125_1651_n41), .B(n1081), .Y(n980) );
AFHCINX2TS U1488 ( .CIN(n1336), .B(n1337), .A(
FPMULT_Sgf_operation_EVEN1_Q_left[0]), .S(
FPMULT_Sgf_operation_Result[24]), .CO(n1334) );
XOR2X1TS U1489 ( .A(n2913), .B(n2912), .Y(FPADDSUB_Raw_mant_SGF[23]) );
OAI21X1TS U1490 ( .A0(n2461), .A1(n928), .B0(n2417), .Y(
FPADDSUB_Data_array_SWR[18]) );
OAI21X1TS U1491 ( .A0(n2473), .A1(n928), .B0(n2414), .Y(
FPADDSUB_Data_array_SWR[14]) );
OAI21X1TS U1492 ( .A0(n2461), .A1(n2372), .B0(n2441), .Y(
FPADDSUB_Data_array_SWR[19]) );
OAI21X1TS U1493 ( .A0(n2459), .A1(n944), .B0(n2458), .Y(
FPADDSUB_Data_array_SWR[8]) );
OAI21X1TS U1494 ( .A0(n2460), .A1(n2944), .B0(n2432), .Y(
FPADDSUB_Data_array_SWR[17]) );
AOI222X4TS U1495 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .B0(FPADDSUB_DMP_SFG[22]), .B1(n2916),
.C0(FPADDSUB_DmP_mant_SFG_SWR[24]), .C1(n2916), .Y(n2921) );
OAI21X1TS U1496 ( .A0(n2455), .A1(n928), .B0(n2420), .Y(
FPADDSUB_Data_array_SWR[10]) );
OAI21X1TS U1497 ( .A0(n2467), .A1(n2944), .B0(n2448), .Y(
FPADDSUB_Data_array_SWR[7]) );
OAI21X1TS U1498 ( .A0(n2466), .A1(n2944), .B0(n2430), .Y(
FPADDSUB_Data_array_SWR[5]) );
OAI21X1TS U1499 ( .A0(n2472), .A1(n944), .B0(n2434), .Y(
FPADDSUB_Data_array_SWR[13]) );
OAI21X1TS U1500 ( .A0(n2465), .A1(n2372), .B0(n2464), .Y(
FPADDSUB_Data_array_SWR[16]) );
OAI21X1TS U1501 ( .A0(n2454), .A1(n944), .B0(n2436), .Y(
FPADDSUB_Data_array_SWR[9]) );
OAI21X1TS U1502 ( .A0(n2467), .A1(n928), .B0(n2423), .Y(
FPADDSUB_Data_array_SWR[6]) );
OAI21X1TS U1503 ( .A0(n2449), .A1(n2944), .B0(n2426), .Y(
FPADDSUB_Data_array_SWR[2]) );
OAI21X1TS U1504 ( .A0(n2477), .A1(n944), .B0(n2476), .Y(
FPADDSUB_Data_array_SWR[12]) );
OAI21X1TS U1505 ( .A0(n2478), .A1(n2944), .B0(n2428), .Y(
FPADDSUB_Data_array_SWR[21]) );
OAI21X1TS U1506 ( .A0(n2945), .A1(n2404), .B0(n2411), .Y(
FPADDSUB_Data_array_SWR[22]) );
OAI21X1TS U1507 ( .A0(n2403), .A1(n2910), .B0(n2402), .Y(n2401) );
AFHCONX2TS U1508 ( .A(n1340), .B(n1339), .CI(n1338), .CON(n1336), .S(
FPMULT_Sgf_operation_Result[23]) );
OAI21X1TS U1509 ( .A0(n2484), .A1(n2944), .B0(n2483), .Y(
FPADDSUB_Data_array_SWR[20]) );
OAI21X1TS U1510 ( .A0(n2453), .A1(n2944), .B0(n2452), .Y(
FPADDSUB_Data_array_SWR[1]) );
XOR2X1TS U1511 ( .A(n2908), .B(n2907), .Y(FPADDSUB_Raw_mant_SGF[21]) );
AFHCINX2TS U1512 ( .CIN(n2108), .B(n2109), .A(n2110), .S(n2123), .CO(n1338)
);
XOR2X2TS U1513 ( .A(n1222), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n1340) );
OAI21X1TS U1514 ( .A0(n2385), .A1(n2399), .B0(n2384), .Y(n2383) );
AOI222X4TS U1515 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(FPADDSUB_DMP_SFG[20]), .B1(n2764),
.C0(FPADDSUB_DmP_mant_SFG_SWR[22]), .C1(n2764), .Y(n2911) );
XOR2X1TS U1516 ( .A(n2903), .B(n2902), .Y(FPADDSUB_Raw_mant_SGF[19]) );
ADDHX2TS U1517 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .B(n1225), .CO(n1222), .S(n2110) );
AOI222X4TS U1518 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(FPADDSUB_DMP_SFG[18]), .B1(n2400),
.C0(FPADDSUB_DmP_mant_SFG_SWR[20]), .C1(n2400), .Y(n2904) );
OAI21X1TS U1519 ( .A0(n2378), .A1(n2380), .B0(n2377), .Y(n2376) );
ADDHX2TS U1520 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .B(n1228),
.CO(n1225), .S(n2135) );
OR2X2TS U1521 ( .A(n1084), .B(n1083), .Y(n968) );
OAI21X1TS U1522 ( .A0(n2945), .A1(n2372), .B0(n2511), .Y(
FPADDSUB_Data_array_SWR[25]) );
NOR2X1TS U1523 ( .A(n1712), .B(n1726), .Y(DP_OP_501J324_127_5235_n202) );
AND2X2TS U1524 ( .A(n2408), .B(n2407), .Y(n2409) );
NOR2X1TS U1525 ( .A(n1717), .B(n1712), .Y(n1716) );
NOR2X1TS U1526 ( .A(n1725), .B(n1713), .Y(DP_OP_501J324_127_5235_n188) );
NOR2X1TS U1527 ( .A(n1667), .B(n1713), .Y(DP_OP_501J324_127_5235_n192) );
NOR2X1TS U1528 ( .A(n1718), .B(n1677), .Y(n1664) );
NOR2X1TS U1529 ( .A(n1678), .B(n1713), .Y(n1641) );
NOR2X1TS U1530 ( .A(n1712), .B(n1724), .Y(DP_OP_501J324_127_5235_n210) );
NOR2X1TS U1531 ( .A(n1718), .B(n1726), .Y(n1642) );
NOR2X1TS U1532 ( .A(n1718), .B(n1676), .Y(n1668) );
NOR2X1TS U1533 ( .A(n1718), .B(n1717), .Y(n1722) );
NOR2X1TS U1534 ( .A(n1717), .B(n1725), .Y(n1643) );
AOI222X4TS U1535 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(FPADDSUB_DMP_SFG[16]), .B1(n2381),
.C0(FPADDSUB_DmP_mant_SFG_SWR[18]), .C1(n2381), .Y(n2899) );
NOR2X1TS U1536 ( .A(n1667), .B(n1679), .Y(DP_OP_501J324_127_5235_n200) );
NOR2X1TS U1537 ( .A(n1727), .B(n1679), .Y(n1666) );
NOR2X1TS U1538 ( .A(n1678), .B(n1676), .Y(n1650) );
NOR2X1TS U1539 ( .A(n1678), .B(n1724), .Y(n1665) );
NOR2X1TS U1540 ( .A(n1675), .B(n1679), .Y(n1648) );
NOR2X1TS U1541 ( .A(n1678), .B(n1677), .Y(DP_OP_501J324_127_5235_n227) );
NOR2X1TS U1542 ( .A(n1725), .B(n1679), .Y(n1670) );
NOR2X1TS U1543 ( .A(n1678), .B(n1726), .Y(n1669) );
NOR2X1TS U1544 ( .A(n1727), .B(n1726), .Y(n1734) );
OAI22X2TS U1545 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(n3252), .B0(n2374),
.B1(n2373), .Y(n2895) );
NOR2X1TS U1546 ( .A(n1725), .B(n1724), .Y(n1735) );
NOR2X1TS U1547 ( .A(n1725), .B(n940), .Y(DP_OP_501J324_127_5235_n236) );
NOR2X1TS U1548 ( .A(n1725), .B(n1726), .Y(n1729) );
OAI21X1TS U1549 ( .A0(n2323), .A1(n2367), .B0(n2322), .Y(n2321) );
NOR2X1TS U1550 ( .A(n1667), .B(n1724), .Y(n1660) );
NOR2X1TS U1551 ( .A(n1727), .B(n1724), .Y(n1731) );
NOR2X1TS U1552 ( .A(n1675), .B(n1724), .Y(n1651) );
NOR2X1TS U1553 ( .A(n1727), .B(n1676), .Y(n1652) );
NOR2X1TS U1554 ( .A(n1727), .B(n940), .Y(n1658) );
NOR2X1TS U1555 ( .A(n1675), .B(n940), .Y(n1605) );
NOR2X1TS U1556 ( .A(n1698), .B(n1697), .Y(n1702) );
NOR2X1TS U1557 ( .A(n1667), .B(n1676), .Y(n1621) );
AOI222X4TS U1558 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(FPADDSUB_DMP_SFG[12]), .B1(n2368),
.C0(FPADDSUB_DmP_mant_SFG_SWR[14]), .C1(n2368), .Y(n2889) );
NOR2X1TS U1559 ( .A(n1675), .B(n1677), .Y(n1653) );
NOR2X1TS U1560 ( .A(n1674), .B(n1676), .Y(n1654) );
NOR2X1TS U1561 ( .A(n1697), .B(n1683), .Y(n1573) );
NOR2X1TS U1562 ( .A(n1579), .B(n1685), .Y(n1590) );
NOR2X1TS U1563 ( .A(n1698), .B(n1682), .Y(n1584) );
NOR2X1TS U1564 ( .A(n1698), .B(n1580), .Y(n1574) );
NOR2X1TS U1565 ( .A(n1684), .B(n1682), .Y(n1588) );
NOR2X1TS U1566 ( .A(n1684), .B(n1580), .Y(n1704) );
NOR2X1TS U1567 ( .A(n1697), .B(n1579), .Y(n1585) );
NOR2X1TS U1568 ( .A(n1697), .B(n1681), .Y(n1710) );
NOR2X1TS U1569 ( .A(n1684), .B(n1685), .Y(n1711) );
NOR2X6TS U1570 ( .A(n3467), .B(n3468), .Y(n2043) );
NOR2X1TS U1571 ( .A(n1683), .B(n1685), .Y(n1705) );
NOR2X1TS U1572 ( .A(n1698), .B(n1680), .Y(n1577) );
NOR2X1TS U1573 ( .A(n1674), .B(n1677), .Y(n1606) );
NOR2X1TS U1574 ( .A(n1674), .B(n940), .Y(n1706) );
NOR2X1TS U1575 ( .A(n1667), .B(n1677), .Y(n1707) );
NOR2X1TS U1576 ( .A(n1579), .B(n1580), .Y(n1569) );
AND3X2TS U1577 ( .A(n1868), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n1867),
.Y(n3468) );
NOR2X1TS U1578 ( .A(n1683), .B(n1682), .Y(n1558) );
NOR2X1TS U1579 ( .A(n1681), .B(n1580), .Y(n1582) );
NOR2X1TS U1580 ( .A(n1683), .B(n1680), .Y(n1581) );
NOR2X1TS U1581 ( .A(n1683), .B(n1580), .Y(n1587) );
NOR2X1TS U1582 ( .A(n1579), .B(n1680), .Y(n1709) );
NOR2X1TS U1583 ( .A(n1681), .B(n1682), .Y(n1708) );
NOR2X1TS U1584 ( .A(n1681), .B(n1680), .Y(n1559) );
NAND2BX1TS U1585 ( .AN(n2493), .B(n958), .Y(n2502) );
OAI21X1TS U1586 ( .A0(n1165), .A1(n1161), .B0(n1162), .Y(n1160) );
INVX3TS U1587 ( .A(n2941), .Y(n2932) );
OAI22X1TS U1588 ( .A0(n1391), .A1(n1441), .B0(n1386), .B1(n1421), .Y(
mult_x_313_n32) );
AOI222X4TS U1589 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(FPADDSUB_DMP_SFG[8]), .B1(n2301),
.C0(FPADDSUB_DmP_mant_SFG_SWR[10]), .C1(n2301), .Y(n2309) );
OAI21X1TS U1590 ( .A0(n1173), .A1(n1169), .B0(n1170), .Y(n1168) );
AOI31X1TS U1591 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n1948), .A2(n3256),
.B0(n1947), .Y(n1949) );
NOR2X1TS U1592 ( .A(n1405), .B(n1442), .Y(n1367) );
INVX3TS U1593 ( .A(n1511), .Y(n1514) );
OAI22X1TS U1594 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(n3215), .B0(n2251),
.B1(n2250), .Y(n2290) );
OAI21XLTS U1595 ( .A0(n1494), .A1(n1522), .B0(n1511), .Y(n1497) );
ADDFX1TS U1596 ( .A(n1290), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .CI(
n1289), .CO(n1287), .S(n2209) );
NAND3BX1TS U1597 ( .AN(n2012), .B(n2010), .C(n2009), .Y(n2029) );
OAI21XLTS U1598 ( .A0(n1814), .A1(n1786), .B0(n1806), .Y(n1789) );
OAI21XLTS U1599 ( .A0(n2234), .A1(n2516), .B0(n2233), .Y(mult_x_311_n36) );
OAI21X1TS U1600 ( .A0(n1181), .A1(n1177), .B0(n1178), .Y(n1176) );
NAND2BX1TS U1601 ( .AN(n2503), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n2498)
);
NOR2X1TS U1602 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n2503), .Y(n1929) );
AOI31X1TS U1603 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n1946), .A2(n3234),
.B0(n2495), .Y(n1938) );
AOI31X1TS U1604 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n1946), .A2(n1945),
.B0(n2495), .Y(n1950) );
INVX3TS U1605 ( .A(n1612), .Y(n1414) );
BUFX3TS U1606 ( .A(n2963), .Y(n952) );
ADDFHX1TS U1607 ( .A(n1294), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .CI(
n1293), .CO(n1291), .S(n2132) );
OAI21XLTS U1608 ( .A0(n2347), .A1(n3284), .B0(n2329), .Y(op_result[0]) );
OAI21XLTS U1609 ( .A0(n2346), .A1(n3286), .B0(n2344), .Y(op_result[29]) );
OAI21XLTS U1610 ( .A0(n2347), .A1(n3261), .B0(n2331), .Y(op_result[31]) );
OAI21XLTS U1611 ( .A0(n2346), .A1(n3285), .B0(n2345), .Y(op_result[30]) );
OAI21XLTS U1612 ( .A0(n2365), .A1(n3262), .B0(n2351), .Y(op_result[22]) );
OAI21XLTS U1613 ( .A0(n2365), .A1(n3278), .B0(n2352), .Y(op_result[6]) );
OAI21XLTS U1614 ( .A0(n2365), .A1(n3263), .B0(n2350), .Y(op_result[21]) );
OAI21XLTS U1615 ( .A0(n2347), .A1(n3277), .B0(n2332), .Y(op_result[7]) );
OAI21XLTS U1616 ( .A0(n2365), .A1(n3264), .B0(n2354), .Y(op_result[20]) );
OAI21XLTS U1617 ( .A0(n2347), .A1(n3276), .B0(n2326), .Y(op_result[8]) );
OAI21XLTS U1618 ( .A0(n2347), .A1(n3275), .B0(n2333), .Y(op_result[9]) );
OAI21XLTS U1619 ( .A0(n2365), .A1(n3265), .B0(n2364), .Y(op_result[19]) );
OAI21XLTS U1620 ( .A0(n2347), .A1(n3274), .B0(n2325), .Y(op_result[10]) );
OAI21XLTS U1621 ( .A0(n2365), .A1(n3266), .B0(n2353), .Y(op_result[18]) );
OAI21XLTS U1622 ( .A0(n2347), .A1(n3273), .B0(n2328), .Y(op_result[11]) );
OAI21XLTS U1623 ( .A0(n2365), .A1(n3267), .B0(n2361), .Y(op_result[17]) );
OAI21XLTS U1624 ( .A0(n2365), .A1(n3272), .B0(n2348), .Y(op_result[12]) );
OAI21XLTS U1625 ( .A0(n2365), .A1(n3271), .B0(n2357), .Y(op_result[13]) );
OAI21XLTS U1626 ( .A0(n2365), .A1(n3270), .B0(n2355), .Y(op_result[14]) );
OAI21XLTS U1627 ( .A0(n2365), .A1(n3268), .B0(n2356), .Y(op_result[16]) );
OAI21XLTS U1628 ( .A0(n2365), .A1(n3269), .B0(n2349), .Y(op_result[15]) );
OAI21XLTS U1629 ( .A0(n2347), .A1(n3283), .B0(n2335), .Y(op_result[1]) );
OAI21XLTS U1630 ( .A0(n2346), .A1(n3289), .B0(n2343), .Y(op_result[26]) );
OAI21XLTS U1631 ( .A0(n2346), .A1(n3290), .B0(n2340), .Y(op_result[25]) );
OAI21XLTS U1632 ( .A0(n2347), .A1(n3282), .B0(n2334), .Y(op_result[2]) );
OAI21XLTS U1633 ( .A0(n2347), .A1(n3281), .B0(n2338), .Y(op_result[3]) );
OAI21XLTS U1634 ( .A0(n2346), .A1(n3291), .B0(n2339), .Y(op_result[24]) );
OAI21XLTS U1635 ( .A0(n2346), .A1(n3288), .B0(n2342), .Y(op_result[27]) );
OAI21XLTS U1636 ( .A0(n2347), .A1(n3279), .B0(n2330), .Y(op_result[5]) );
OAI21XLTS U1637 ( .A0(n2346), .A1(n3287), .B0(n2341), .Y(op_result[28]) );
OAI21XLTS U1638 ( .A0(n2365), .A1(n3292), .B0(n2358), .Y(op_result[23]) );
OAI21XLTS U1639 ( .A0(n2347), .A1(n3280), .B0(n2327), .Y(op_result[4]) );
INVX3TS U1640 ( .A(n1828), .Y(n1814) );
INVX3TS U1641 ( .A(n1535), .Y(n1522) );
AOI222X4TS U1642 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[6]), .B0(FPADDSUB_DMP_SFG[4]), .B1(n2199),
.C0(FPADDSUB_DmP_mant_SFG_SWR[6]), .C1(n2199), .Y(n2246) );
OAI21X1TS U1643 ( .A0(n1183), .A1(n1193), .B0(n1194), .Y(n1184) );
OAI211X1TS U1644 ( .A0(n1970), .A1(n2026), .B0(n1969), .C0(n1968), .Y(n1976)
);
OAI21XLTS U1645 ( .A0(n2574), .A1(n2560), .B0(n2576), .Y(n2561) );
INVX3TS U1646 ( .A(n1593), .Y(mult_x_313_n74) );
AO21XLTS U1647 ( .A0(n1191), .A1(n1138), .B0(n1137), .Y(n977) );
CLKAND2X2TS U1648 ( .A(n1192), .B(n1138), .Y(n976) );
NAND2X4TS U1649 ( .A(n926), .B(n3259), .Y(n2036) );
INVX3TS U1650 ( .A(n2519), .Y(FPMULT_FSM_exp_operation_A_S) );
NOR2X4TS U1651 ( .A(n926), .B(n2057), .Y(n2058) );
AOI21X2TS U1652 ( .A0(n1123), .A1(n1209), .B0(n1122), .Y(n1198) );
BUFX3TS U1653 ( .A(n1885), .Y(n3079) );
NAND2X4TS U1654 ( .A(n3010), .B(n3016), .Y(n2347) );
NAND3XLTS U1655 ( .A(enab_cont_iter), .B(n3098), .C(n3097), .Y(n2982) );
OAI211XLTS U1656 ( .A0(n3356), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n1981), .C0(
n1980), .Y(n1984) );
OAI211XLTS U1657 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n3352), .B0(n1993), .C0(
n1996), .Y(n2007) );
INVX3TS U1658 ( .A(DP_OP_500J324_126_4510_n32), .Y(
DP_OP_500J324_126_4510_n27) );
INVX1TS U1659 ( .A(n1932), .Y(n1946) );
OAI21X1TS U1660 ( .A0(n1194), .A1(n1186), .B0(n1187), .Y(n1137) );
NAND2X4TS U1661 ( .A(n925), .B(n3259), .Y(n2054) );
NOR2X1TS U1662 ( .A(n1193), .B(n1186), .Y(n1138) );
NOR2X4TS U1663 ( .A(n3090), .B(n1882), .Y(n3059) );
NOR2X6TS U1664 ( .A(FPMULT_FSM_selector_C), .B(n2807), .Y(n2808) );
NOR2X1TS U1665 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n2947),
.Y(n2948) );
NAND2X1TS U1666 ( .A(n1134), .B(n1133), .Y(n1194) );
INVX1TS U1667 ( .A(n2485), .Y(n2487) );
NAND3XLTS U1668 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n2968), .C(n3165),
.Y(n2157) );
INVX1TS U1669 ( .A(n2494), .Y(n2496) );
INVX3TS U1670 ( .A(n2924), .Y(n2920) );
OAI21X1TS U1671 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n1935), .B0(n3248),
.Y(n1936) );
OR2X4TS U1672 ( .A(FPSENCOS_cont_iter_out[2]), .B(n2859), .Y(n2955) );
OAI21X1TS U1673 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[1]), .A1(
FPSENCOS_d_ff1_operation_out), .B0(n2929), .Y(n2927) );
NAND3X1TS U1674 ( .A(n3355), .B(n1967), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n1969) );
NAND2BX1TS U1675 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n2023) );
ADDFX1TS U1676 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .B(n997),
.CI(n1079), .CO(n1251), .S(n1255) );
ADDFX1TS U1677 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .B(n999),
.CI(n1080), .CO(n1256), .S(n1260) );
NAND3X1TS U1678 ( .A(n2033), .B(n2241), .C(n3241), .Y(n2105) );
ADDFX1TS U1679 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .B(n995),
.CI(n1078), .CO(n1248), .S(n1250) );
NOR2X2TS U1680 ( .A(n1069), .B(DP_OP_498J324_124_3916_n124), .Y(n1118) );
ADDFX2TS U1681 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]), .B(
n1115), .CI(n1114), .CO(n1120), .S(n1119) );
ADDFX1TS U1682 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]), .B(
n1158), .CI(n1157), .CO(n1159), .S(n1155) );
ADDFX1TS U1683 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]), .B(
n1149), .CI(n1148), .CO(n1150), .S(n1146) );
ADDFX1TS U1684 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]), .B(
n1153), .CI(n1152), .CO(n1154), .S(n1151) );
ADDFX1TS U1685 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .B(n993),
.CI(n1077), .CO(n1076), .S(n1247) );
ADDFX1TS U1686 ( .A(n1849), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]), .CI(
n1848), .CO(n1857), .S(n1852) );
ADDHX2TS U1687 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[12]), .CO(n1446), .S(
DP_OP_500J324_126_4510_n161) );
NAND2BX1TS U1688 ( .AN(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(n3181), .Y(n1942)
);
NAND2BX1TS U1689 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n2014) );
OR2X2TS U1690 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n3220), .Y(n2406) );
ADDHX2TS U1691 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[0]), .CO(n1746), .S(
DP_OP_502J324_128_4510_n160) );
NOR3X1TS U1692 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(
n2494) );
NAND2BX1TS U1693 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n2008) );
NOR3X1TS U1694 ( .A(FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(
n2488) );
NOR3X1TS U1695 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n2501) );
ADDHX2TS U1696 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[0]), .CO(n1738), .S(
DP_OP_502J324_128_4510_n161) );
NAND2BX1TS U1697 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n1968) );
NOR2X6TS U1698 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2034) );
NAND2BX1TS U1699 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n1967) );
NAND3X1TS U1700 ( .A(n2866), .B(n2865), .C(n2864), .Y(n3366) );
NAND2BX1TS U1701 ( .AN(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
n2526) );
NAND2BX1TS U1702 ( .AN(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n2524) );
NAND2BX1TS U1703 ( .AN(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n1032)
);
AFHCONX4TS U1704 ( .A(n1282), .B(n1281), .CI(n1280), .CON(n1341), .S(
FPMULT_Sgf_operation_Result[37]) );
AOI22X2TS U1705 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n3239), .B0(n2891), .B1(
n2890), .Y(n2373) );
CMPR42X1TS U1706 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
DP_OP_499J324_125_1651_n85), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .D(
DP_OP_499J324_125_1651_n86), .ICI(DP_OP_499J324_125_1651_n118), .S(
DP_OP_499J324_125_1651_n84), .ICO(DP_OP_499J324_125_1651_n82), .CO(
DP_OP_499J324_125_1651_n83) );
CMPR42X1TS U1707 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_499J324_125_1651_n43), .D(DP_OP_499J324_125_1651_n104), .ICI(
DP_OP_499J324_125_1651_n44), .S(DP_OP_499J324_125_1651_n42), .ICO(
DP_OP_499J324_125_1651_n40), .CO(DP_OP_499J324_125_1651_n41) );
INVX2TS U1708 ( .A(n1340), .Y(DP_OP_499J324_125_1651_n104) );
NAND2X1TS U1709 ( .A(n1130), .B(n1129), .Y(n1205) );
NOR2X2TS U1710 ( .A(n1130), .B(n1129), .Y(n1204) );
INVX2TS U1711 ( .A(n1348), .Y(n1094) );
AOI21X1TS U1712 ( .A0(n1176), .A1(n978), .B0(n1147), .Y(n1173) );
INVX2TS U1713 ( .A(n1174), .Y(n1147) );
XNOR2X1TS U1714 ( .A(n1160), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]), .Y(
n1235) );
XNOR2X1TS U1715 ( .A(n1176), .B(n1175), .Y(n1258) );
NOR2X2TS U1716 ( .A(n1134), .B(n1133), .Y(n1193) );
NOR2X2TS U1717 ( .A(n1132), .B(n1131), .Y(n1199) );
NAND2X1TS U1718 ( .A(n1132), .B(n1131), .Y(n1200) );
NOR2XLTS U1719 ( .A(n1675), .B(n1676), .Y(n1733) );
INVX2TS U1720 ( .A(n1610), .Y(n1727) );
CMPR42X1TS U1721 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
DP_OP_499J324_125_1651_n79), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .D(
DP_OP_499J324_125_1651_n116), .ICI(DP_OP_499J324_125_1651_n80), .S(
DP_OP_499J324_125_1651_n78), .ICO(DP_OP_499J324_125_1651_n76), .CO(
DP_OP_499J324_125_1651_n77) );
INVX2TS U1722 ( .A(n2166), .Y(DP_OP_499J324_125_1651_n116) );
INVX2TS U1723 ( .A(n1313), .Y(n1227) );
INVX2TS U1724 ( .A(n1276), .Y(n1092) );
NAND2X1TS U1725 ( .A(n1206), .B(n1205), .Y(n1207) );
INVX2TS U1726 ( .A(n1204), .Y(n1206) );
INVX2TS U1727 ( .A(n1633), .Y(n1718) );
ADDHXLTS U1728 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .B(n1286), .CO(DP_OP_499J324_125_1651_n90), .S(n1285) );
NOR2X2TS U1729 ( .A(n1136), .B(n1135), .Y(n1186) );
INVX2TS U1730 ( .A(n1191), .Y(n1183) );
INVX2TS U1731 ( .A(n1192), .Y(n1182) );
INVX2TS U1732 ( .A(n1186), .Y(n1188) );
ADDFX1TS U1733 ( .A(n1000), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]), .CI(n999), .CO(n1029), .S(n1033) );
NOR2X1TS U1734 ( .A(n1151), .B(n1150), .Y(n1169) );
NAND2X1TS U1735 ( .A(n1151), .B(n1150), .Y(n1170) );
INVX2TS U1736 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n1127) );
INVX2TS U1737 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n1128)
);
XNOR2X2TS U1738 ( .A(DP_OP_498J324_124_3916_n136), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n1069) );
INVX2TS U1739 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n1124)
);
INVX2TS U1740 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n1125)
);
CMPR42X1TS U1741 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
DP_OP_499J324_125_1651_n73), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .D(
DP_OP_499J324_125_1651_n114), .ICI(DP_OP_499J324_125_1651_n74), .S(
DP_OP_499J324_125_1651_n72), .ICO(DP_OP_499J324_125_1651_n70), .CO(
DP_OP_499J324_125_1651_n71) );
INVX2TS U1742 ( .A(n2118), .Y(DP_OP_499J324_125_1651_n114) );
CMPR42X1TS U1743 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
DP_OP_499J324_125_1651_n64), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .D(
DP_OP_499J324_125_1651_n111), .ICI(DP_OP_499J324_125_1651_n65), .S(
DP_OP_499J324_125_1651_n63), .ICO(DP_OP_499J324_125_1651_n61), .CO(
DP_OP_499J324_125_1651_n62) );
INVX2TS U1744 ( .A(n2128), .Y(DP_OP_499J324_125_1651_n111) );
CMPR42X1TS U1745 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
DP_OP_499J324_125_1651_n58), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .D(
DP_OP_499J324_125_1651_n109), .ICI(DP_OP_499J324_125_1651_n59), .S(
DP_OP_499J324_125_1651_n57), .ICO(DP_OP_499J324_125_1651_n55), .CO(
DP_OP_499J324_125_1651_n56) );
INVX2TS U1746 ( .A(n2142), .Y(DP_OP_499J324_125_1651_n109) );
CMPR42X1TS U1747 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
DP_OP_499J324_125_1651_n52), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .D(
DP_OP_499J324_125_1651_n107), .ICI(DP_OP_499J324_125_1651_n130), .S(
DP_OP_499J324_125_1651_n51), .ICO(DP_OP_499J324_125_1651_n49), .CO(
DP_OP_499J324_125_1651_n50) );
INVX2TS U1748 ( .A(n2139), .Y(DP_OP_499J324_125_1651_n107) );
INVX2TS U1749 ( .A(n1343), .Y(DP_OP_499J324_125_1651_n130) );
CMPR42X1TS U1750 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
DP_OP_499J324_125_1651_n49), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .D(
DP_OP_499J324_125_1651_n106), .ICI(DP_OP_499J324_125_1651_n50), .S(
DP_OP_499J324_125_1651_n48), .ICO(DP_OP_499J324_125_1651_n46), .CO(
DP_OP_499J324_125_1651_n47) );
INVX2TS U1751 ( .A(n2135), .Y(DP_OP_499J324_125_1651_n106) );
XNOR2X1TS U1752 ( .A(n1168), .B(n1167), .Y(n1245) );
NAND2X1TS U1753 ( .A(n979), .B(n1166), .Y(n1167) );
INVX2TS U1754 ( .A(n1071), .Y(n1072) );
NAND2X2TS U1755 ( .A(n1069), .B(DP_OP_498J324_124_3916_n124), .Y(n1116) );
INVX2TS U1756 ( .A(n1199), .Y(n1201) );
INVX2TS U1757 ( .A(n1629), .Y(n1725) );
INVX2TS U1758 ( .A(n1600), .Y(n1675) );
INVX2TS U1759 ( .A(n1310), .Y(n1113) );
INVX2TS U1760 ( .A(n1088), .Y(n1082) );
NAND2X1TS U1761 ( .A(n1084), .B(n1083), .Y(n1085) );
XOR2X1TS U1762 ( .A(n1197), .B(n1196), .Y(n1269) );
NAND2X1TS U1763 ( .A(n1195), .B(n1194), .Y(n1196) );
AOI21X1TS U1764 ( .A0(n1208), .A1(n1192), .B0(n1191), .Y(n1197) );
NAND2X2TS U1765 ( .A(n975), .B(n1071), .Y(n1067) );
OAI21X1TS U1766 ( .A0(n1218), .A1(n1215), .B0(n1216), .Y(n1214) );
XNOR2X1TS U1767 ( .A(n1090), .B(n1089), .Y(n1309) );
NAND2X1TS U1768 ( .A(n980), .B(n1088), .Y(n1089) );
INVX2TS U1769 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .Y(n1869) );
INVX2TS U1770 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(n1875)
);
INVX2TS U1771 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .Y(n1874) );
INVX2TS U1772 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .Y(n1909) );
INVX2TS U1773 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(n1910)
);
INVX2TS U1774 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .Y(n1952) );
INVX2TS U1775 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .Y(
n2389) );
INVX2TS U1776 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .Y(n2390) );
INVX2TS U1777 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .Y(
n2394) );
INVX2TS U1778 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n987)
);
INVX2TS U1779 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n988) );
INVX2TS U1780 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n985)
);
INVX2TS U1781 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(n986) );
INVX2TS U1782 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n983)
);
INVX2TS U1783 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n984)
);
INVX2TS U1784 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n982)
);
INVX2TS U1785 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n1157) );
INVX2TS U1786 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n1158) );
INVX2TS U1787 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(n1148)
);
INVX2TS U1788 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n1149) );
INVX2TS U1789 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n1153) );
NAND2X1TS U1790 ( .A(n1146), .B(n1145), .Y(n1174) );
INVX2TS U1791 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n1139) );
INVX2TS U1792 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(n1143)
);
INVX2TS U1793 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n1144) );
NAND2BXLTS U1794 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n1995) );
NAND3XLTS U1795 ( .A(n3352), .B(n1993), .C(FPADDSUB_intDX_EWSW[8]), .Y(n1994) );
NOR2XLTS U1796 ( .A(n1991), .B(FPADDSUB_intDY_EWSW[10]), .Y(n1992) );
OAI21XLTS U1797 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n3336), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n1990) );
OAI21XLTS U1798 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n3349), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n1999) );
INVX2TS U1799 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n994) );
INVX2TS U1800 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n991)
);
INVX2TS U1801 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n992) );
INVX2TS U1802 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n989)
);
INVX2TS U1803 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n990) );
CMPR42X1TS U1804 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
DP_OP_499J324_125_1651_n90), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .D(
DP_OP_499J324_125_1651_n88), .ICI(DP_OP_499J324_125_1651_n119), .S(
DP_OP_499J324_125_1651_n87), .ICO(DP_OP_499J324_125_1651_n85), .CO(
DP_OP_499J324_125_1651_n86) );
NOR2X1TS U1805 ( .A(n1159), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n1161) );
NAND2X1TS U1806 ( .A(n1159), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n1162) );
NOR2X1TS U1807 ( .A(n1142), .B(n1141), .Y(n1177) );
NAND2X1TS U1808 ( .A(n1142), .B(n1141), .Y(n1178) );
XOR2X1TS U1809 ( .A(n1190), .B(n1189), .Y(n1267) );
NAND2X1TS U1810 ( .A(n1188), .B(n1187), .Y(n1189) );
AOI21X1TS U1811 ( .A0(n1208), .A1(n1185), .B0(n1184), .Y(n1190) );
OR2X1TS U1812 ( .A(DP_OP_498J324_124_3916_n136), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n1114) );
NOR2X2TS U1813 ( .A(n1121), .B(n1120), .Y(n1210) );
CMPR42X1TS U1814 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
DP_OP_499J324_125_1651_n82), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .D(
DP_OP_499J324_125_1651_n117), .ICI(DP_OP_499J324_125_1651_n83), .S(
DP_OP_499J324_125_1651_n81), .ICO(DP_OP_499J324_125_1651_n79), .CO(
DP_OP_499J324_125_1651_n80) );
INVX2TS U1815 ( .A(n2209), .Y(DP_OP_499J324_125_1651_n117) );
NAND2BXLTS U1816 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n1993) );
NAND2BXLTS U1817 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n1989) );
NOR2XLTS U1818 ( .A(n2025), .B(FPADDSUB_intDY_EWSW[24]), .Y(n1966) );
CMPR42X1TS U1819 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
DP_OP_499J324_125_1651_n76), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .D(
DP_OP_499J324_125_1651_n115), .ICI(DP_OP_499J324_125_1651_n77), .S(
DP_OP_499J324_125_1651_n75), .ICO(DP_OP_499J324_125_1651_n73), .CO(
DP_OP_499J324_125_1651_n74) );
INVX2TS U1820 ( .A(n2206), .Y(DP_OP_499J324_125_1651_n115) );
CMPR42X1TS U1821 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
DP_OP_499J324_125_1651_n70), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .D(
DP_OP_499J324_125_1651_n113), .ICI(DP_OP_499J324_125_1651_n71), .S(
DP_OP_499J324_125_1651_n69), .ICO(DP_OP_499J324_125_1651_n67), .CO(
DP_OP_499J324_125_1651_n68) );
INVX2TS U1822 ( .A(n2203), .Y(DP_OP_499J324_125_1651_n113) );
CMPR42X1TS U1823 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
DP_OP_499J324_125_1651_n67), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .D(
DP_OP_499J324_125_1651_n112), .ICI(DP_OP_499J324_125_1651_n68), .S(
DP_OP_499J324_125_1651_n66), .ICO(DP_OP_499J324_125_1651_n64), .CO(
DP_OP_499J324_125_1651_n65) );
INVX2TS U1824 ( .A(n2115), .Y(DP_OP_499J324_125_1651_n112) );
CMPR42X1TS U1825 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
DP_OP_499J324_125_1651_n61), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .D(
DP_OP_499J324_125_1651_n110), .ICI(DP_OP_499J324_125_1651_n62), .S(
DP_OP_499J324_125_1651_n60), .ICO(DP_OP_499J324_125_1651_n58), .CO(
DP_OP_499J324_125_1651_n59) );
INVX2TS U1826 ( .A(n2126), .Y(DP_OP_499J324_125_1651_n110) );
CMPR42X1TS U1827 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
DP_OP_499J324_125_1651_n55), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .D(
DP_OP_499J324_125_1651_n108), .ICI(DP_OP_499J324_125_1651_n56), .S(
DP_OP_499J324_125_1651_n54), .ICO(DP_OP_499J324_125_1651_n52), .CO(
DP_OP_499J324_125_1651_n53) );
INVX2TS U1828 ( .A(n2113), .Y(DP_OP_499J324_125_1651_n108) );
CMPR42X1TS U1829 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
DP_OP_499J324_125_1651_n46), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .D(
DP_OP_499J324_125_1651_n105), .ICI(DP_OP_499J324_125_1651_n47), .S(
DP_OP_499J324_125_1651_n45), .ICO(DP_OP_499J324_125_1651_n43), .CO(
DP_OP_499J324_125_1651_n44) );
INVX2TS U1830 ( .A(n2110), .Y(DP_OP_499J324_125_1651_n105) );
ADDHX1TS U1831 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
DP_OP_499J324_125_1651_n40), .CO(n1084), .S(n1081) );
XOR2X1TS U1832 ( .A(n1165), .B(n1164), .Y(n1240) );
XOR2X1TS U1833 ( .A(n1173), .B(n1172), .Y(n1253) );
NAND2X1TS U1834 ( .A(n1171), .B(n1170), .Y(n1172) );
INVX2TS U1835 ( .A(n1169), .Y(n1171) );
INVX2TS U1836 ( .A(n1193), .Y(n1195) );
OAI21X2TS U1837 ( .A0(n1199), .A1(n1205), .B0(n1200), .Y(n1191) );
NOR2X2TS U1838 ( .A(n1204), .B(n1199), .Y(n1192) );
INVX2TS U1839 ( .A(n1198), .Y(n1208) );
XOR2X1TS U1840 ( .A(n1181), .B(n1180), .Y(n1263) );
NAND2X1TS U1841 ( .A(n1179), .B(n1178), .Y(n1180) );
INVX2TS U1842 ( .A(n1177), .Y(n1179) );
NAND2X1TS U1843 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .B(
DP_OP_498J324_124_3916_n137), .Y(n1071) );
INVX2TS U1844 ( .A(n1209), .Y(n1218) );
NAND2X2TS U1845 ( .A(n1119), .B(n1080), .Y(n1216) );
INVX2TS U1846 ( .A(n1210), .Y(n1212) );
NAND2X1TS U1847 ( .A(n1121), .B(n1120), .Y(n1211) );
NOR2X4TS U1848 ( .A(n1119), .B(n1080), .Y(n1215) );
NAND2BXLTS U1849 ( .AN(n2634), .B(n2632), .Y(n2636) );
CMPR42X1TS U1850 ( .A(DP_OP_501J324_127_5235_n183), .B(
DP_OP_501J324_127_5235_n218), .C(DP_OP_501J324_127_5235_n190), .D(
DP_OP_501J324_127_5235_n140), .ICI(DP_OP_501J324_127_5235_n141), .S(
DP_OP_501J324_127_5235_n136), .ICO(DP_OP_501J324_127_5235_n134), .CO(
DP_OP_501J324_127_5235_n135) );
NOR2XLTS U1851 ( .A(n3145), .B(n3162), .Y(n2732) );
NAND2X1TS U1852 ( .A(n2488), .B(n2485), .Y(n1932) );
OAI21XLTS U1853 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n3358), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n2019) );
INVX2TS U1854 ( .A(n1282), .Y(n1111) );
INVX2TS U1855 ( .A(n1279), .Y(n1096) );
OAI22X1TS U1856 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(n3240), .B0(n2367),
.B1(n2366), .Y(n2890) );
OAI22X1TS U1857 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n3218), .B0(n2300),
.B1(n2299), .Y(n2307) );
CLKAND2X2TS U1858 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n3215), .Y(n2251)
);
OAI22X1TS U1859 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(n3258), .B0(n2380),
.B1(n2379), .Y(n2900) );
AOI22X1TS U1860 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n3216), .B0(n2291), .B1(
n2290), .Y(n2299) );
CLKAND2X2TS U1861 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n3218), .Y(n2300)
);
OAI22X1TS U1862 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(n3295), .B0(n2399),
.B1(n2398), .Y(n2905) );
CLKAND2X2TS U1863 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n3252), .Y(n2374)
);
OAI22X1TS U1864 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n3223), .B0(n2314),
.B1(n2313), .Y(n2318) );
OAI22X1TS U1865 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n3210), .B0(n2173),
.B1(n2172), .Y(n2191) );
AOI211X1TS U1866 ( .A0(n951), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2086),
.C0(n2048), .Y(n2060) );
OAI21XLTS U1867 ( .A0(n2084), .A1(n3313), .B0(n2047), .Y(n2048) );
AOI22X1TS U1868 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n3309), .B0(n2906), .B1(
n2905), .Y(n2909) );
AOI22X1TS U1869 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n3211), .B0(n2192), .B1(
n2191), .Y(n2197) );
CLKAND2X2TS U1870 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n3212), .Y(n2198)
);
OAI21XLTS U1871 ( .A0(n2084), .A1(n3323), .B0(n2081), .Y(n2082) );
AOI211X1TS U1872 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n951), .B0(n2086),
.C0(n2046), .Y(n2065) );
OAI21XLTS U1873 ( .A0(n3312), .A1(n2084), .B0(n2045), .Y(n2046) );
AOI22X1TS U1874 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n3229), .B0(n2319), .B1(
n2318), .Y(n2366) );
CLKAND2X2TS U1875 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n3240), .Y(n2367)
);
AOI22X1TS U1876 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n3254), .B0(n2896), .B1(
n2895), .Y(n2379) );
CLKAND2X2TS U1877 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n3258), .Y(n2380)
);
AOI22X1TS U1878 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n3184), .B0(n2901), .B1(
n2900), .Y(n2398) );
CLKAND2X2TS U1879 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n3295), .Y(n2399)
);
CLKAND2X2TS U1880 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n3223), .Y(n2314)
);
AOI22X1TS U1881 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n3164), .B0(n2308), .B1(
n2307), .Y(n2313) );
XOR2X1TS U1882 ( .A(n1073), .B(n1117), .Y(n1220) );
NAND2X1TS U1883 ( .A(n1070), .B(n1116), .Y(n1073) );
INVX2TS U1884 ( .A(n1118), .Y(n1070) );
XNOR2X1TS U1885 ( .A(n1203), .B(n1202), .Y(n1288) );
NAND2X1TS U1886 ( .A(n1201), .B(n1200), .Y(n1202) );
OAI32X1TS U1887 ( .A0(DP_OP_502J324_128_4510_n161), .A1(n1815), .A2(n962),
.B0(n1766), .B1(n1750), .Y(n1836) );
OAI21XLTS U1888 ( .A0(n2597), .A1(n2594), .B0(n2595), .Y(n2552) );
NOR2XLTS U1889 ( .A(n3177), .B(n3225), .Y(n2553) );
NOR2XLTS U1890 ( .A(n3173), .B(n3157), .Y(n2555) );
NOR2XLTS U1891 ( .A(n3178), .B(n3243), .Y(n2554) );
OAI21XLTS U1892 ( .A0(n2605), .A1(n2603), .B0(n2602), .Y(n2577) );
NOR2XLTS U1893 ( .A(n3171), .B(n3243), .Y(n2568) );
OAI21XLTS U1894 ( .A0(n2671), .A1(n2668), .B0(n2669), .Y(n2628) );
AO21XLTS U1895 ( .A0(n2650), .A1(n2649), .B0(n2652), .Y(n2637) );
NOR2XLTS U1896 ( .A(n3183), .B(n3231), .Y(n2629) );
NOR2XLTS U1897 ( .A(n3174), .B(n3245), .Y(n2631) );
NOR2XLTS U1898 ( .A(n3180), .B(n3154), .Y(n2630) );
NOR2XLTS U1899 ( .A(n3183), .B(n3156), .Y(n2643) );
NOR2XLTS U1900 ( .A(n3180), .B(n3245), .Y(n2645) );
NOR2XLTS U1901 ( .A(n3232), .B(n3154), .Y(n2644) );
OAI21XLTS U1902 ( .A0(n2657), .A1(n2654), .B0(n2655), .Y(n2217) );
NOR2XLTS U1903 ( .A(n1737), .B(n1682), .Y(DP_OP_501J324_127_5235_n77) );
OR2X1TS U1904 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2522) );
INVX2TS U1905 ( .A(FPMULT_Sgf_normalized_result[13]), .Y(n2701) );
INVX2TS U1906 ( .A(FPMULT_Sgf_normalized_result[11]), .Y(n2704) );
INVX2TS U1907 ( .A(FPMULT_Sgf_normalized_result[9]), .Y(n2707) );
INVX2TS U1908 ( .A(FPMULT_Sgf_normalized_result[7]), .Y(n2710) );
INVX2TS U1909 ( .A(FPMULT_Sgf_normalized_result[5]), .Y(n2713) );
INVX2TS U1910 ( .A(FPMULT_Sgf_normalized_result[3]), .Y(n2714) );
INVX2TS U1911 ( .A(n1346), .Y(n1224) );
CLKAND2X2TS U1912 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n3210), .Y(n2173)
);
NAND2X1TS U1913 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n2885) );
XOR2X1TS U1914 ( .A(n1087), .B(n1086), .Y(n1281) );
NAND2X1TS U1915 ( .A(n968), .B(n1085), .Y(n1086) );
AOI21X1TS U1916 ( .A0(n1090), .A1(n980), .B0(n1082), .Y(n1087) );
AO22XLTS U1917 ( .A0(n3017), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n3220), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
XOR2XLTS U1918 ( .A(n2254), .B(n2253), .Y(FPADDSUB_Raw_mant_SGF[9]) );
XOR2XLTS U1919 ( .A(n2893), .B(n2892), .Y(FPADDSUB_Raw_mant_SGF[15]) );
XOR2XLTS U1920 ( .A(n2303), .B(n2302), .Y(FPADDSUB_Raw_mant_SGF[11]) );
OAI21XLTS U1921 ( .A0(n2249), .A1(n2251), .B0(n2248), .Y(n2247) );
OAI21XLTS U1922 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n3294), .B0(n2901),
.Y(n2902) );
AO22XLTS U1923 ( .A0(n3017), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n3220), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
OAI21XLTS U1924 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n3199), .B0(n2906),
.Y(n2907) );
XOR2XLTS U1925 ( .A(n2317), .B(n2316), .Y(FPADDSUB_Raw_mant_SGF[13]) );
OAI21XLTS U1926 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n3201), .B0(n2915),
.Y(n2912) );
OAI31X1TS U1927 ( .A0(n3108), .A1(FPSENCOS_cont_var_out[1]), .A2(n3155),
.B0(n2514), .Y(n840) );
NOR3XLTS U1928 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n2306), .Y(n3471) );
AOI2BB1XLTS U1929 ( .A0N(n3467), .A1N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
n3468), .Y(FPADDSUB_formatted_number_W[31]) );
AO22XLTS U1930 ( .A0(n3451), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n3220), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
AO22XLTS U1931 ( .A0(operation[1]), .A1(n2765), .B0(n3010), .B1(operation[0]), .Y(n2768) );
OAI21XLTS U1932 ( .A0(n1822), .A1(n1797), .B0(n1793), .Y(n1792) );
NOR2XLTS U1933 ( .A(n1827), .B(n1821), .Y(n1776) );
OAI21XLTS U1934 ( .A0(n1423), .A1(n1421), .B0(n1422), .Y(n1420) );
NOR2XLTS U1935 ( .A(n1442), .B(n1400), .Y(n1383) );
OAI32X1TS U1936 ( .A0(DP_OP_500J324_126_4510_n161), .A1(n1467), .A2(
DP_OP_500J324_126_4510_n27), .B0(n1466), .B1(n1455), .Y(n1486) );
AOI2BB2XLTS U1937 ( .B0(n2938), .B1(n3465), .A0N(FPADDSUB_intDX_EWSW[31]),
.A1N(n2804), .Y(n3466) );
AOI31XLTS U1938 ( .A0(n2803), .A1(n2802), .A2(n2801), .B0(n2932), .Y(n2804)
);
MX2X1TS U1939 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U1940 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U1941 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U1942 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U1943 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U1944 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U1945 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U1946 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
AOI211X1TS U1947 ( .A0(n2497), .A1(n2496), .B0(n2495), .C0(n2506), .Y(n2499)
);
INVX4TS U1948 ( .A(n1960), .Y(n2151) );
NAND2BXLTS U1949 ( .AN(enab_cont_iter), .B(n3406), .Y(n1960) );
INVX2TS U1950 ( .A(n2482), .Y(n2386) );
INVX2TS U1951 ( .A(n926), .Y(n2281) );
BUFX3TS U1952 ( .A(n2404), .Y(n2479) );
BUFX3TS U1953 ( .A(n2372), .Y(n2944) );
OR2X1TS U1954 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n2051), .Y(n914) );
OR2X1TS U1955 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n2268), .Y(n915) );
OR2X1TS U1956 ( .A(FPMULT_FSM_selector_C), .B(n2809), .Y(n917) );
INVX2TS U1957 ( .A(n2928), .Y(n2962) );
OR2X1TS U1958 ( .A(n3319), .B(n2807), .Y(n919) );
BUFX4TS U1959 ( .A(n1961), .Y(n2150) );
BUFX3TS U1960 ( .A(n1963), .Y(n3390) );
INVX2TS U1961 ( .A(n1593), .Y(n920) );
INVX2TS U1962 ( .A(DP_OP_500J324_126_4510_n32), .Y(n921) );
INVX2TS U1963 ( .A(n3059), .Y(n922) );
INVX2TS U1964 ( .A(n922), .Y(n923) );
INVX2TS U1965 ( .A(n922), .Y(n924) );
INVX2TS U1966 ( .A(FPADDSUB_left_right_SHT2), .Y(n925) );
INVX2TS U1967 ( .A(n925), .Y(n926) );
INVX2TS U1968 ( .A(n2409), .Y(n927) );
INVX4TS U1969 ( .A(n2409), .Y(n928) );
CLKINVX3TS U1970 ( .A(n2511), .Y(n929) );
CLKINVX3TS U1971 ( .A(n2511), .Y(n930) );
OAI221X1TS U1972 ( .A0(n3304), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n3316),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n2779), .Y(n2782) );
INVX2TS U1973 ( .A(n916), .Y(n933) );
OAI21X1TS U1974 ( .A0(n2268), .A1(n3313), .B0(n2267), .Y(n2075) );
OAI21X1TS U1975 ( .A0(n2268), .A1(n3312), .B0(n2267), .Y(n2066) );
INVX2TS U1976 ( .A(n918), .Y(n934) );
AOI211X1TS U1977 ( .A0(FPMULT_zero_flag), .A1(FPMULT_FSM_exp_operation_A_S),
.B0(FPMULT_FSM_final_result_load), .C0(FPMULT_FSM_barrel_shifter_load),
.Y(n2970) );
AOI221X1TS U1978 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n3260), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n3185), .C0(n1973), .Y(n1975) );
OAI2BB2X2TS U1979 ( .B0(n2535), .B1(n2548), .A0N(n2551), .A1N(n2549), .Y(
n2593) );
NOR2X1TS U1980 ( .A(n2551), .B(n2549), .Y(n2535) );
NOR2X2TS U1981 ( .A(n3230), .B(n3173), .Y(n2557) );
NOR2X2TS U1982 ( .A(n2267), .B(n3297), .Y(n2053) );
NOR2X2TS U1983 ( .A(n2969), .B(n3165), .Y(FPMULT_FSM_adder_round_norm_load)
);
NAND2X2TS U1984 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n2966), .Y(n2969) );
AOI21X2TS U1985 ( .A0(DP_OP_499J324_125_1651_n34), .A1(n975), .B0(n1072),
.Y(n1117) );
XNOR2X1TS U1986 ( .A(n1067), .B(DP_OP_499J324_125_1651_n34), .Y(n1068) );
OAI21XLTS U1987 ( .A0(n2667), .A1(n2665), .B0(n2664), .Y(n2616) );
OAI2BB2X2TS U1988 ( .B0(n2611), .B1(n2624), .A0N(n2627), .A1N(n2625), .Y(
n2667) );
OAI211X1TS U1989 ( .A0(n3259), .A1(n2188), .B0(n2040), .C0(n2039), .Y(n2079)
);
AOI21X2TS U1990 ( .A0(n2034), .A1(FPADDSUB_Data_array_SWR[51]), .B0(n2074),
.Y(n2188) );
NOR2X2TS U1991 ( .A(n3231), .B(n3180), .Y(n2635) );
NOR2X2TS U1992 ( .A(n3178), .B(n3244), .Y(n2538) );
NOR2X2TS U1993 ( .A(n3177), .B(n3243), .Y(n2537) );
NOR2X2TS U1994 ( .A(n3183), .B(n3154), .Y(n2613) );
NOR4X2TS U1995 ( .A(n3214), .B(n3145), .C(n3166), .D(n3149), .Y(
mult_x_309_n42) );
OAI211X1TS U1996 ( .A0(n3259), .A1(n2185), .B0(n2056), .C0(n2055), .Y(n2062)
);
AOI21X2TS U1997 ( .A0(n2034), .A1(FPADDSUB_Data_array_SWR[50]), .B0(n2074),
.Y(n2185) );
NOR4BX2TS U1998 ( .AN(n3117), .B(n3221), .C(n3168), .D(n3152), .Y(
mult_x_312_n42) );
NOR4BX2TS U1999 ( .AN(n3117), .B(n3221), .C(n3153), .D(n3169), .Y(
intadd_1104_B_0_) );
BUFX4TS U2000 ( .A(n2151), .Y(n3381) );
BUFX4TS U2001 ( .A(n2151), .Y(n3386) );
BUFX3TS U2002 ( .A(n2149), .Y(n3436) );
BUFX4TS U2003 ( .A(n3384), .Y(n3405) );
BUFX4TS U2004 ( .A(n3383), .Y(n3402) );
BUFX4TS U2005 ( .A(n3382), .Y(n3403) );
OAI211X1TS U2006 ( .A0(n3259), .A1(n2257), .B0(n2256), .C0(n2255), .Y(n2263)
);
AOI21X2TS U2007 ( .A0(n2034), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n2074),
.Y(n2257) );
INVX2TS U2008 ( .A(FPMULT_Sgf_operation_EVEN1_result_A_adder_0_), .Y(n935)
);
INVX2TS U2009 ( .A(n935), .Y(n936) );
ADDHXLTS U2010 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[0]), .CO(n1349), .S(
FPMULT_Sgf_operation_EVEN1_result_A_adder_0_) );
AOI21X2TS U2011 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n2034), .B0(n2074),
.Y(n2261) );
NOR4BX2TS U2012 ( .AN(n3117), .B(n3221), .C(n3167), .D(n3150), .Y(
mult_x_312_n33) );
BUFX3TS U2013 ( .A(n3386), .Y(n937) );
BUFX4TS U2014 ( .A(n3384), .Y(n3397) );
BUFX4TS U2015 ( .A(n1962), .Y(n3401) );
BUFX4TS U2016 ( .A(n2151), .Y(n3399) );
BUFX3TS U2017 ( .A(n2151), .Y(n1963) );
AOI21X2TS U2018 ( .A0(n2034), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n2266),
.Y(n2283) );
OAI21X1TS U2019 ( .A0(n2268), .A1(n3323), .B0(n2267), .Y(n2266) );
AOI21X2TS U2020 ( .A0(n2034), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n2269),
.Y(n2287) );
OAI21X1TS U2021 ( .A0(n2268), .A1(n3204), .B0(n2267), .Y(n2269) );
BUFX3TS U2022 ( .A(n1963), .Y(n938) );
BUFX4TS U2023 ( .A(n1964), .Y(n3378) );
BUFX4TS U2024 ( .A(n3381), .Y(n3389) );
BUFX4TS U2025 ( .A(n3386), .Y(n3387) );
BUFX3TS U2026 ( .A(n2151), .Y(n1964) );
NOR4BX2TS U2027 ( .AN(n3117), .B(n3221), .C(n3152), .D(n3167), .Y(
mult_x_312_n38) );
NOR2X4TS U2028 ( .A(n3146), .B(n3151), .Y(n3098) );
CLKINVX3TS U2029 ( .A(n2084), .Y(n2038) );
AOI22X1TS U2030 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n3208), .B0(n2168), .B1(
n2167), .Y(n2172) );
AOI222X4TS U2031 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n3209), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n2886), .C0(n3209), .C1(n2886), .Y(
n2168) );
BUFX3TS U2032 ( .A(n2150), .Y(n3450) );
BUFX4TS U2033 ( .A(n2150), .Y(n3445) );
BUFX4TS U2034 ( .A(n2150), .Y(n3444) );
BUFX4TS U2035 ( .A(n2150), .Y(n3440) );
BUFX4TS U2036 ( .A(n2150), .Y(n3442) );
BUFX4TS U2037 ( .A(n3220), .Y(n2424) );
ADDHX1TS U2038 ( .A(FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .B(
DP_OP_501J324_127_5235_n330), .CO(n1599), .S(
DP_OP_501J324_127_5235_n294) );
INVX2TS U2039 ( .A(DP_OP_501J324_127_5235_n302), .Y(n940) );
INVX2TS U2040 ( .A(n940), .Y(n941) );
BUFX4TS U2041 ( .A(n2950), .Y(n2951) );
BUFX4TS U2042 ( .A(n2950), .Y(n2949) );
OR2X1TS U2043 ( .A(FPADDSUB_N60), .B(FPADDSUB_N59), .Y(n2886) );
INVX2TS U2044 ( .A(FPMULT_Op_MY[7]), .Y(n942) );
INVX2TS U2045 ( .A(n2944), .Y(n943) );
INVX2TS U2046 ( .A(n943), .Y(n944) );
BUFX4TS U2047 ( .A(n2941), .Y(n2936) );
OAI21X2TS U2048 ( .A0(n3246), .A1(n2511), .B0(n2412), .Y(n2475) );
OAI21X2TS U2049 ( .A0(n3219), .A1(n2511), .B0(n2421), .Y(n2469) );
OAI21X2TS U2050 ( .A0(n3247), .A1(n2511), .B0(n2415), .Y(n2463) );
OAI21X2TS U2051 ( .A0(n2406), .A1(n3224), .B0(n2405), .Y(n2481) );
BUFX4TS U2052 ( .A(n3030), .Y(n3066) );
BUFX4TS U2053 ( .A(n1885), .Y(n3093) );
BUFX4TS U2054 ( .A(n3079), .Y(n3067) );
BUFX4TS U2055 ( .A(n3079), .Y(n3084) );
BUFX4TS U2056 ( .A(n3079), .Y(n3070) );
CMPR32X4TS U2057 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[21]), .C(n1448),
.CO(n1449), .S(n1535) );
CMPR32X4TS U2058 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[9]), .C(n1739), .CO(
n1741), .S(n1828) );
AOI222X4TS U2059 ( .A0(n2424), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n3451),
.B1(FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.C1(n929), .Y(n2439) );
CMPR32X4TS U2060 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[11]), .C(n1781),
.CO(n1782), .S(n1806) );
INVX3TS U2061 ( .A(n2955), .Y(n2954) );
CMPR32X4TS U2062 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[19]), .C(n1446),
.CO(n1457), .S(DP_OP_500J324_126_4510_n32) );
INVX2TS U2063 ( .A(n2037), .Y(n945) );
INVX2TS U2064 ( .A(n945), .Y(n946) );
INVX2TS U2065 ( .A(n945), .Y(n947) );
INVX2TS U2066 ( .A(n915), .Y(n948) );
INVX2TS U2067 ( .A(n915), .Y(n949) );
INVX2TS U2068 ( .A(n914), .Y(n950) );
INVX2TS U2069 ( .A(n914), .Y(n951) );
OAI21X2TS U2070 ( .A0(FPMULT_FSM_add_overflow_flag), .A1(n3147), .B0(n3165),
.Y(n2807) );
NAND3X2TS U2071 ( .A(n3151), .B(n3175), .C(n3242), .Y(n2859) );
NOR2X4TS U2072 ( .A(n3175), .B(n3242), .Y(n3097) );
INVX4TS U2073 ( .A(n2938), .Y(n2939) );
INVX4TS U2074 ( .A(n2941), .Y(n2934) );
CLKINVX3TS U2075 ( .A(n919), .Y(n954) );
INVX3TS U2076 ( .A(n919), .Y(n955) );
CLKINVX3TS U2077 ( .A(n917), .Y(n956) );
INVX3TS U2078 ( .A(n917), .Y(n957) );
NOR4BX2TS U2079 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .D(n2947), .Y(n2971) );
NOR2X1TS U2080 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n2241) );
NOR4X4TS U2081 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n2947), .D(n3241), .Y(
enab_cont_iter) );
NOR2X1TS U2082 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n2504) );
NOR4X1TS U2083 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .D(
n2500), .Y(n1934) );
INVX2TS U2084 ( .A(n912), .Y(n958) );
INVX2TS U2085 ( .A(n913), .Y(n959) );
OAI32X1TS U2086 ( .A0(DP_OP_502J324_128_4510_n161), .A1(n1800), .A2(
DP_OP_502J324_128_4510_n27), .B0(n1751), .B1(n1750), .Y(n1752) );
OAI32X1TS U2087 ( .A0(DP_OP_502J324_128_4510_n161), .A1(n1825), .A2(n962),
.B0(n1824), .B1(n1750), .Y(DP_OP_502J324_128_4510_n76) );
INVX2TS U2088 ( .A(DP_OP_500J324_126_4510_n160), .Y(n960) );
INVX2TS U2089 ( .A(n960), .Y(n961) );
ADDHXLTS U2090 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[12]), .CO(n1453), .S(
DP_OP_500J324_126_4510_n160) );
OAI32X1TS U2091 ( .A0(DP_OP_500J324_126_4510_n161), .A1(n1513), .A2(
DP_OP_500J324_126_4510_n27), .B0(n1463), .B1(n1455), .Y(n1471) );
OAI32X1TS U2092 ( .A0(DP_OP_500J324_126_4510_n161), .A1(n1509), .A2(
DP_OP_500J324_126_4510_n27), .B0(n1462), .B1(n1455), .Y(n1473) );
OAI32X1TS U2093 ( .A0(DP_OP_500J324_126_4510_n161), .A1(n1523), .A2(
DP_OP_500J324_126_4510_n27), .B0(n1456), .B1(n1455), .Y(n1477) );
INVX2TS U2094 ( .A(DP_OP_502J324_128_4510_n32), .Y(n962) );
OAI32X1TS U2095 ( .A0(DP_OP_502J324_128_4510_n161), .A1(n1804), .A2(
DP_OP_502J324_128_4510_n27), .B0(n1755), .B1(n1750), .Y(n1763) );
OAI32X1TS U2096 ( .A0(DP_OP_502J324_128_4510_n161), .A1(n1759), .A2(
DP_OP_502J324_128_4510_n27), .B0(n1758), .B1(n1750), .Y(n1777) );
INVX2TS U2097 ( .A(DP_OP_502J324_128_4510_n32), .Y(
DP_OP_502J324_128_4510_n27) );
NOR2X4TS U2098 ( .A(n2408), .B(n2407), .Y(n2482) );
BUFX3TS U2099 ( .A(n2386), .Y(n2946) );
OAI221X1TS U2100 ( .A0(FPADDSUB_intDX_EWSW[14]), .A1(n3203), .B0(n3322),
.B1(FPADDSUB_intDY_EWSW[14]), .C0(n2788), .Y(n2798) );
OAI221X1TS U2101 ( .A0(n3310), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n3196),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n2769), .Y(n2776) );
OAI221X1TS U2102 ( .A0(n3318), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n3195), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n2777), .Y(n2784) );
NOR2X2TS U2103 ( .A(n2683), .B(n2152), .Y(n2681) );
NOR2X2TS U2104 ( .A(n3157), .B(n3171), .Y(n2556) );
NOR4X1TS U2105 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n3373) );
NOR4X1TS U2106 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n3375) );
NOR4X1TS U2107 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n3374) );
NOR4X1TS U2108 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n3372) );
NOR4X1TS U2109 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n1881),
.Y(n3367) );
XOR2XLTS U2110 ( .A(n2599), .B(n2598), .Y(n2600) );
OAI21XLTS U2111 ( .A0(n2599), .A1(n2598), .B0(n2601), .Y(n2566) );
OAI21X2TS U2112 ( .A0(n2573), .A1(n2562), .B0(n2561), .Y(n2598) );
NOR2X2TS U2113 ( .A(n3156), .B(n3174), .Y(n2634) );
NOR2X2TS U2114 ( .A(n3180), .B(n3257), .Y(n2614) );
ADDHX4TS U2115 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .CO(n1356), .S(
FPMULT_Sgf_operation_EVEN1_result_B_adder_0_) );
NOR4X1TS U2116 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[26]), .D(dataA[28]),
.Y(n2876) );
OAI21XLTS U2117 ( .A0(n2641), .A1(n2639), .B0(n2646), .Y(n2623) );
AOI21X2TS U2118 ( .A0(n2621), .A1(n2620), .B0(n2625), .Y(n2641) );
AOI21X2TS U2119 ( .A0(n2545), .A1(n2544), .B0(n2549), .Y(n2565) );
OAI21XLTS U2120 ( .A0(n2679), .A1(n2677), .B0(n2676), .Y(n2653) );
AOI21X2TS U2121 ( .A0(n2648), .A1(n2647), .B0(n2646), .Y(n2679) );
OAI21XLTS U2122 ( .A0(n2673), .A1(n2672), .B0(n2675), .Y(n2642) );
OAI21X2TS U2123 ( .A0(n2649), .A1(n2650), .B0(n2637), .Y(n2672) );
AOI21X2TS U2124 ( .A0(n2572), .A1(n2571), .B0(n2570), .Y(n2605) );
OAI21XLTS U2125 ( .A0(n2565), .A1(n2563), .B0(n2570), .Y(n2547) );
NOR2X2TS U2126 ( .A(n2546), .B(n3244), .Y(n2570) );
NOR2X2TS U2127 ( .A(n3246), .B(n1933), .Y(n2495) );
NOR2X2TS U2128 ( .A(n3177), .B(n971), .Y(n2587) );
NOR2X2TS U2129 ( .A(n3183), .B(n972), .Y(n2661) );
AOI21X2TS U2130 ( .A0(n2230), .A1(n2229), .B0(n2574), .Y(n2581) );
NOR4BX2TS U2131 ( .AN(n3117), .B(n3227), .C(n3167), .D(n3150), .Y(
mult_x_312_n26) );
OAI211X2TS U2132 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n3300), .B0(n2003),
.C0(n1989), .Y(n2005) );
AOI21X2TS U2133 ( .A0(n2214), .A1(n2213), .B0(n2212), .Y(n2657) );
CLKINVX1TS U2134 ( .A(n2650), .Y(n2212) );
BUFX3TS U2135 ( .A(n3432), .Y(n3434) );
ADDHX1TS U2136 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .B(n1041),
.CO(n1042), .S(n1348) );
INVX2TS U2137 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(n1115)
);
ADDFHX2TS U2138 ( .A(n1245), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .CI(n1244), .CO(n1239), .S(n2126) );
INVX2TS U2139 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n1126)
);
ADDFHX2TS U2140 ( .A(n1235), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .CI(n1234), .CO(n1231), .S(n2113) );
INVX2TS U2141 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n1140)
);
OAI211X2TS U2142 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n3342), .B0(n2778),
.C0(n2008), .Y(n2017) );
NOR3X6TS U2143 ( .A(n1868), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n1865),
.Y(n3467) );
XNOR2X2TS U2144 ( .A(DP_OP_26J324_129_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n1868) );
NOR3X2TS U2145 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n3296),
.C(n2513), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
AOI222X4TS U2146 ( .A0(n2424), .A1(FPADDSUB_DmP_mant_SHT1_SW[0]), .B0(n3451),
.B1(FPADDSUB_Raw_mant_NRM_SWR[23]), .C0(n959), .C1(n930), .Y(n2449) );
OAI32X4TS U2147 ( .A0(n970), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.A2(FPSENCOS_d_ff1_operation_out), .B0(
FPSENCOS_d_ff1_shift_region_flag_out[0]), .B1(n2929), .Y(n2930) );
NOR2X2TS U2148 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n2966) );
AOI21X2TS U2149 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3151), .B0(n1965),
.Y(n2178) );
BUFX4TS U2150 ( .A(n2998), .Y(n3087) );
BUFX4TS U2151 ( .A(n3031), .Y(n2998) );
NOR4X2TS U2152 ( .A(n3214), .B(n3145), .C(n3148), .D(n3163), .Y(
intadd_1107_CI) );
NOR2X1TS U2153 ( .A(n1442), .B(n1441), .Y(mult_x_313_n56) );
AOI2BB2X4TS U2154 ( .B0(n1639), .B1(n1406), .A0N(n1406), .A1N(n1639), .Y(
n1441) );
NOR2X4TS U2155 ( .A(n2387), .B(n2408), .Y(n2447) );
AOI2BB2X4TS U2156 ( .B0(n1782), .B1(n1803), .A0N(n1803), .A1N(n1782), .Y(
n1826) );
OAI21XLTS U2157 ( .A0(n1531), .A1(n1504), .B0(n1501), .Y(n1500) );
NOR2X4TS U2158 ( .A(FPMULT_Op_MY[17]), .B(n1490), .Y(n1531) );
BUFX4TS U2159 ( .A(n3059), .Y(n3091) );
BUFX3TS U2160 ( .A(n2043), .Y(n963) );
AOI21X2TS U2161 ( .A0(n2034), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2075),
.Y(n2275) );
AOI21X2TS U2162 ( .A0(n2034), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n2066),
.Y(n2265) );
INVX4TS U2163 ( .A(n2938), .Y(n2935) );
CLKBUFX3TS U2164 ( .A(n2808), .Y(n964) );
BUFX3TS U2165 ( .A(n2806), .Y(n965) );
BUFX3TS U2166 ( .A(n2806), .Y(n2854) );
NOR2X1TS U2167 ( .A(n2809), .B(n3319), .Y(n2806) );
AOI222X1TS U2168 ( .A0(n2107), .A1(n3326), .B0(n2107), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .C0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .C1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n842) );
NAND2X2TS U2169 ( .A(n3326), .B(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.Y(n2857) );
OAI2BB1X1TS U2170 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1N(n930), .B0(
n2418), .Y(n2457) );
NAND2X2TS U2171 ( .A(FPADDSUB_bit_shift_SHT2), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2267) );
NAND3X2TS U2172 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n3259), .Y(n2084) );
AOI222X4TS U2173 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(FPADDSUB_DMP_SFG[2]), .B1(n2174),
.C0(FPADDSUB_DmP_mant_SFG_SWR[4]), .C1(n2174), .Y(n2193) );
OAI221X4TS U2174 ( .A0(n969), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n3306), .B1(
FPADDSUB_intDY_EWSW[6]), .C0(n2770), .Y(n2775) );
OAI32X1TS U2175 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n3249), .B0(n3181), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1935) );
NOR2XLTS U2176 ( .A(FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n1944) );
NOR2XLTS U2177 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1945) );
NOR4X2TS U2178 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .C(FPADDSUB_Raw_mant_NRM_SWR[22]), .D(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2485) );
NOR3BX2TS U2179 ( .AN(FPSENCOS_cont_var_out[1]), .B(n3293), .C(
FPSENCOS_cont_var_out[0]), .Y(FPSENCOS_enab_d_ff4_Zn) );
INVX2TS U2180 ( .A(FPADDSUB_intDX_EWSW[28]), .Y(n1972) );
AO21XLTS U2181 ( .A0(FPMULT_Op_MX[7]), .A1(FPMULT_Op_MY[6]), .B0(n2228), .Y(
n974) );
INVX2TS U2182 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n1080) );
INVX2TS U2183 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n1079) );
INVX2TS U2184 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n1078) );
INVX2TS U2185 ( .A(FPMULT_Sgf_operation_Result[5]), .Y(n1077) );
OR2X1TS U2186 ( .A(n1146), .B(n1145), .Y(n978) );
INVX2TS U2187 ( .A(n1273), .Y(n1109) );
INVX2TS U2188 ( .A(n1272), .Y(n1107) );
INVX2TS U2189 ( .A(n1305), .Y(n1105) );
INVX2TS U2190 ( .A(n1271), .Y(n1103) );
INVX2TS U2191 ( .A(n1270), .Y(n1099) );
INVX2TS U2192 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]), .Y(n1083) );
OAI21XLTS U2193 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n3354), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n1979) );
INVX2TS U2194 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n1152) );
INVX2TS U2195 ( .A(n1161), .Y(n1163) );
NAND2X1TS U2196 ( .A(n1136), .B(n1135), .Y(n1187) );
NOR2XLTS U2197 ( .A(n2012), .B(FPADDSUB_intDY_EWSW[16]), .Y(n2013) );
NAND2X1TS U2198 ( .A(n1163), .B(n1162), .Y(n1164) );
NAND2X1TS U2199 ( .A(n978), .B(n1174), .Y(n1175) );
NOR2XLTS U2200 ( .A(n2556), .B(n2557), .Y(n2559) );
INVX2TS U2201 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(n1953)
);
OAI21XLTS U2202 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n3341), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n2011) );
INVX2TS U2203 ( .A(n1322), .Y(n1238) );
NOR2XLTS U2204 ( .A(n3238), .B(n3152), .Y(n2752) );
INVX2TS U2205 ( .A(n1637), .Y(n1678) );
OAI21XLTS U2206 ( .A0(r_mode[1]), .A1(n3461), .B0(n1957), .Y(n1958) );
NOR2XLTS U2207 ( .A(n1811), .B(n1827), .Y(n1754) );
NOR2XLTS U2208 ( .A(n3237), .B(n3150), .Y(n2744) );
OAI21XLTS U2209 ( .A0(n2589), .A1(n2587), .B0(n2586), .Y(n2238) );
INVX2TS U2210 ( .A(n1299), .Y(n1101) );
OAI21XLTS U2211 ( .A0(n2084), .A1(n3204), .B0(n2083), .Y(n2085) );
INVX2TS U2212 ( .A(n1939), .Y(n1940) );
OAI21XLTS U2213 ( .A0(n2196), .A1(n2198), .B0(n2195), .Y(n2194) );
OAI21XLTS U2214 ( .A0(n2312), .A1(n2314), .B0(n2311), .Y(n2310) );
NOR2XLTS U2215 ( .A(n3221), .B(n3168), .Y(intadd_1104_CI) );
NOR2XLTS U2216 ( .A(n2723), .B(n2725), .Y(intadd_1107_B_2_) );
OAI21XLTS U2217 ( .A0(n2295), .A1(n2300), .B0(n2294), .Y(n2293) );
OAI21XLTS U2218 ( .A0(n2171), .A1(n2173), .B0(n2170), .Y(n2169) );
INVX2TS U2219 ( .A(n2094), .Y(n3142) );
OAI21XLTS U2220 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n2296), .B0(n2857), .Y(n872) );
NOR2XLTS U2221 ( .A(n2227), .B(n855), .Y(FPSENCOS_ITER_CONT_N5) );
OAI21XLTS U2222 ( .A0(n2190), .A1(n2969), .B0(n2189), .Y(
FPMULT_FS_Module_state_next[1]) );
NOR2XLTS U2223 ( .A(n2689), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
NOR2XLTS U2224 ( .A(n2701), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
OR2X1TS U2225 ( .A(FPSENCOS_d_ff_Xn[7]), .B(n2177), .Y(
FPSENCOS_first_mux_X[7]) );
OR2X1TS U2226 ( .A(FPSENCOS_d_ff_Xn[3]), .B(n2177), .Y(
FPSENCOS_first_mux_X[3]) );
OR2X1TS U2227 ( .A(FPSENCOS_d_ff_Xn[17]), .B(n2954), .Y(
FPSENCOS_first_mux_X[17]) );
OR2X1TS U2228 ( .A(FPSENCOS_d_ff_Xn[2]), .B(n2177), .Y(
FPSENCOS_first_mux_X[2]) );
OR2X1TS U2229 ( .A(n861), .B(n3102), .Y(n848) );
OAI21XLTS U2230 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n967), .B0(n2160), .Y(
FPADDSUB_Shift_amount_EXP_EW[0]) );
INVX2TS U2231 ( .A(intadd_1107_n1), .Y(n3143) );
NOR2XLTS U2232 ( .A(n3230), .B(n3172), .Y(n981) );
NOR2X1TS U2233 ( .A(n3225), .B(n942), .Y(n2582) );
CLKAND2X2TS U2234 ( .A(n981), .B(n2582), .Y(intadd_1105_B_0_) );
INVX2TS U2235 ( .A(intadd_1105_B_0_), .Y(n3144) );
NOR2X1TS U2236 ( .A(n3230), .B(n942), .Y(n2228) );
CMPR32X2TS U2237 ( .A(DP_OP_497J324_123_3916_n48), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]), .C(n982), .CO(n1003), .S(n1006) );
CMPR32X2TS U2238 ( .A(n984), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]), .C(n983), .CO(n1005), .S(n1009) );
CMPR32X2TS U2239 ( .A(n986), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]), .C(n985),
.CO(n1008), .S(n1012) );
CMPR32X2TS U2240 ( .A(n988), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]), .C(n987),
.CO(n1011), .S(n1015) );
CMPR32X2TS U2241 ( .A(n990), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]), .C(n989),
.CO(n1014), .S(n1018) );
CMPR32X2TS U2242 ( .A(n992), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]), .C(n991),
.CO(n1017), .S(n1021) );
INVX2TS U2243 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n993) );
CMPR32X2TS U2244 ( .A(n994), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]), .C(n993),
.CO(n1020), .S(n1024) );
INVX2TS U2245 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n996) );
INVX2TS U2246 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(n995) );
CMPR32X2TS U2247 ( .A(n996), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]), .C(n995),
.CO(n1023), .S(n1027) );
INVX2TS U2248 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n998) );
INVX2TS U2249 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(n997) );
CMPR32X2TS U2250 ( .A(n998), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]), .C(n997),
.CO(n1026), .S(n1030) );
INVX2TS U2251 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n1000) );
INVX2TS U2252 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(n999) );
INVX2TS U2253 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n1035) );
XOR2X1TS U2254 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(n1034) );
XNOR2X1TS U2255 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .B(
n1001), .Y(n1044) );
CMPR32X2TS U2256 ( .A(n1006), .B(n1005), .C(n1004), .CO(n1002), .S(n1048) );
CMPR32X2TS U2257 ( .A(n1009), .B(n1008), .C(n1007), .CO(n1004), .S(n1050) );
CMPR32X2TS U2258 ( .A(n1012), .B(n1011), .C(n1010), .CO(n1007), .S(n1052) );
CMPR32X2TS U2259 ( .A(n1015), .B(n1014), .C(n1013), .CO(n1010), .S(n1054) );
CMPR32X2TS U2260 ( .A(n1018), .B(n1017), .C(n1016), .CO(n1013), .S(n1040) );
CMPR32X2TS U2261 ( .A(n1021), .B(n1020), .C(n1019), .CO(n1016), .S(n1056) );
CMPR32X2TS U2262 ( .A(n1024), .B(n1023), .C(n1022), .CO(n1019), .S(n1058) );
CMPR32X2TS U2263 ( .A(n1027), .B(n1026), .C(n1025), .CO(n1022), .S(n1060) );
CMPR32X2TS U2264 ( .A(n1030), .B(n1029), .C(n1028), .CO(n1025), .S(n1062) );
CMPR32X2TS U2265 ( .A(n1033), .B(n1032), .C(n1031), .CO(n1028), .S(n1064) );
CMPR32X2TS U2266 ( .A(n1036), .B(n1035), .C(n1034), .CO(n1031), .S(n1066) );
CMPR32X2TS U2267 ( .A(DP_OP_497J324_123_3916_n59), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .C(
DP_OP_499J324_125_1651_n150), .CO(n1036), .S(n1074) );
ADDHX1TS U2268 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(n1037),
.CO(n1041), .S(n1279) );
ADDHX1TS U2269 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(n1038),
.CO(n1037), .S(n1343) );
CMPR32X2TS U2270 ( .A(n1040), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .C(n1039),
.CO(n1053), .S(n1282) );
CMPR32X2TS U2271 ( .A(n1044), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .C(n1043),
.CO(n1038), .S(n1270) );
CMPR32X2TS U2272 ( .A(n1046), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .C(n1045),
.CO(n1043), .S(n1299) );
CMPR32X2TS U2273 ( .A(n1048), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .C(n1047),
.CO(n1045), .S(n1271) );
CMPR32X2TS U2274 ( .A(n1050), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .C(n1049),
.CO(n1047), .S(n1305) );
CMPR32X2TS U2275 ( .A(n1052), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .C(n1051),
.CO(n1049), .S(n1272) );
CMPR32X2TS U2276 ( .A(n1054), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .C(n1053),
.CO(n1051), .S(n1273) );
CMPR32X2TS U2277 ( .A(n1056), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .C(n1055),
.CO(n1039), .S(n1310) );
CMPR32X2TS U2278 ( .A(n1058), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .C(n1057), .CO(n1055), .S(n1346) );
CMPR32X2TS U2279 ( .A(n1060), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .C(n1059), .CO(n1057), .S(n1313) );
CMPR32X2TS U2280 ( .A(n1062), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .C(n1061),
.CO(n1059), .S(n1316) );
INVX2TS U2281 ( .A(n1316), .Y(n1230) );
CMPR32X2TS U2282 ( .A(n1064), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .C(n1063),
.CO(n1061), .S(n1319) );
INVX2TS U2283 ( .A(n1319), .Y(n1233) );
CMPR32X2TS U2284 ( .A(n1066), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .C(n1065),
.CO(n1063), .S(n1322) );
INVX2TS U2285 ( .A(n2163), .Y(n1075) );
ADDHX1TS U2286 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .B(n1068), .CO(n1221), .S(n2163) );
INVX2TS U2287 ( .A(n2164), .Y(n1283) );
ADDHX1TS U2288 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .B(n1074),
.CO(n1065), .S(n1325) );
INVX2TS U2289 ( .A(n1325), .Y(n1243) );
OR2X1TS U2290 ( .A(n1035), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n1261) );
XNOR2X1TS U2291 ( .A(n1035), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n1265) );
AFHCINX2TS U2292 ( .CIN(n1091), .B(DP_OP_499J324_125_1651_n42), .A(n1092),
.S(n1345), .CO(n1090) );
AFHCONX2TS U2293 ( .A(DP_OP_499J324_125_1651_n45), .B(n1094), .CI(n1093),
.CON(n1091), .S(n1312) );
AFHCINX2TS U2294 ( .CIN(n1095), .B(DP_OP_499J324_125_1651_n48), .A(n1096),
.S(n1315), .CO(n1093) );
AFHCONX2TS U2295 ( .A(DP_OP_499J324_125_1651_n53), .B(
DP_OP_499J324_125_1651_n51), .CI(n1097), .CON(n1095), .S(n1318) );
AFHCINX2TS U2296 ( .CIN(n1098), .B(DP_OP_499J324_125_1651_n54), .A(n1099),
.S(n1321), .CO(n1097) );
AFHCONX2TS U2297 ( .A(n1101), .B(DP_OP_499J324_125_1651_n57), .CI(n1100),
.CON(n1098), .S(n1324) );
AFHCINX2TS U2298 ( .CIN(n1102), .B(DP_OP_499J324_125_1651_n60), .A(n1103),
.S(n1327), .CO(n1100) );
AFHCONX2TS U2299 ( .A(n1105), .B(DP_OP_499J324_125_1651_n63), .CI(n1104),
.CON(n1102), .S(n1329) );
AFHCINX2TS U2300 ( .CIN(n1106), .B(DP_OP_499J324_125_1651_n66), .A(n1107),
.S(n1331), .CO(n1104) );
AFHCONX2TS U2301 ( .A(n1109), .B(DP_OP_499J324_125_1651_n69), .CI(n1108),
.CON(n1106), .S(n1333) );
AFHCINX2TS U2302 ( .CIN(n1110), .B(DP_OP_499J324_125_1651_n72), .A(n1111),
.S(n1335), .CO(n1108) );
AFHCONX2TS U2303 ( .A(n1113), .B(n1112), .CI(DP_OP_499J324_125_1651_n75),
.CON(n1110), .S(n1337) );
CMPR32X2TS U2304 ( .A(n1221), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .C(n1220), .CO(n1293), .S(n2164) );
AFHCINX2TS U2305 ( .CIN(n1223), .B(DP_OP_499J324_125_1651_n78), .A(n1224),
.S(n1339), .CO(n1112) );
AFHCONX2TS U2306 ( .A(n1227), .B(DP_OP_499J324_125_1651_n81), .CI(n1226),
.CON(n1223), .S(n2109) );
AFHCINX2TS U2307 ( .CIN(n1229), .B(DP_OP_499J324_125_1651_n84), .A(n1230),
.S(n2134), .CO(n1226) );
ADDHX1TS U2308 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(n1231),
.CO(n1228), .S(n2139) );
AFHCONX2TS U2309 ( .A(n1233), .B(n1232), .CI(DP_OP_499J324_125_1651_n87),
.CON(n1229), .S(n2138) );
AFHCINX2TS U2310 ( .CIN(n1236), .B(n1237), .A(n1238), .S(n2112), .CO(n1232)
);
CMPR32X2TS U2311 ( .A(n1240), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .C(n1239),
.CO(n1234), .S(n2142) );
AFHCONX2TS U2312 ( .A(n1243), .B(n1242), .CI(n1241), .CON(n1236), .S(n2141)
);
AFHCINX2TS U2313 ( .CIN(n1246), .B(n1247), .A(n1248), .S(n2125), .CO(n1241)
);
AFHCONX2TS U2314 ( .A(n1251), .B(n1250), .CI(n1249), .CON(n1246), .S(n2129)
);
CMPR32X2TS U2315 ( .A(n1253), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .C(n1252),
.CO(n1244), .S(n2128) );
AFHCINX2TS U2316 ( .CIN(n1254), .B(n1255), .A(n1256), .S(n2116), .CO(n1249)
);
CMPR32X2TS U2317 ( .A(n1258), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .C(n1257),
.CO(n1252), .S(n2115) );
AFHCONX2TS U2318 ( .A(n1261), .B(n1260), .CI(n1259), .CON(n1254), .S(n2204)
);
AFHCINX2TS U2319 ( .CIN(n1264), .B(n1265), .A(DP_OP_498J324_124_3916_n124),
.S(n2119), .CO(n1259) );
CMPR32X2TS U2320 ( .A(n1267), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .C(n1266),
.CO(n1262), .S(n2118) );
CMPR32X2TS U2321 ( .A(n1269), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .C(n1268),
.CO(n1266), .S(n2206) );
AFHCONX2TS U2322 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .B(
DP_OP_499J324_125_1651_n150), .CI(DP_OP_499J324_125_1651_n34), .CON(
n1264), .S(n2205) );
NAND2X1TS U2323 ( .A(n2206), .B(n2205), .Y(n2207) );
INVX2TS U2324 ( .A(n2207), .Y(n2117) );
NOR2X1TS U2325 ( .A(n1107), .B(n1109), .Y(n1303) );
NAND2X1TS U2326 ( .A(n1305), .B(n1303), .Y(n1301) );
NOR2X1TS U2327 ( .A(n1103), .B(n1301), .Y(n1297) );
NAND2X1TS U2328 ( .A(n1299), .B(n1297), .Y(n1295) );
NOR2X1TS U2329 ( .A(n1099), .B(n1295), .Y(n1274) );
CMPR32X2TS U2330 ( .A(n1288), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .C(
n1287), .CO(n1268), .S(n2166) );
CMPR32X2TS U2331 ( .A(n1292), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .C(n1291), .CO(n1289), .S(n2165) );
INVX2TS U2332 ( .A(n2165), .Y(DP_OP_499J324_125_1651_n118) );
INVX2TS U2333 ( .A(n2132), .Y(DP_OP_499J324_125_1651_n119) );
XNOR2X1TS U2334 ( .A(n1296), .B(n1099), .Y(FPMULT_Sgf_operation_Result[43])
);
INVX2TS U2335 ( .A(n1297), .Y(n1298) );
XNOR2X1TS U2336 ( .A(n1300), .B(n1101), .Y(FPMULT_Sgf_operation_Result[42])
);
XNOR2X1TS U2337 ( .A(n1302), .B(n1103), .Y(FPMULT_Sgf_operation_Result[41])
);
INVX2TS U2338 ( .A(n1303), .Y(n1304) );
XNOR2X1TS U2339 ( .A(n1306), .B(n1105), .Y(FPMULT_Sgf_operation_Result[40])
);
XNOR2X1TS U2340 ( .A(n1307), .B(n1107), .Y(FPMULT_Sgf_operation_Result[39])
);
AFHCINX2TS U2341 ( .CIN(n1311), .B(n1312), .A(n1313), .S(
FPMULT_Sgf_operation_Result[34]), .CO(n1344) );
AFHCONX2TS U2342 ( .A(n1316), .B(n1315), .CI(n1314), .CON(n1311), .S(
FPMULT_Sgf_operation_Result[33]) );
AFHCINX2TS U2343 ( .CIN(n1317), .B(n1318), .A(n1319), .S(
FPMULT_Sgf_operation_Result[32]), .CO(n1314) );
AFHCONX2TS U2344 ( .A(n1322), .B(n1321), .CI(n1320), .CON(n1317), .S(
FPMULT_Sgf_operation_Result[31]) );
AFHCINX2TS U2345 ( .CIN(n1323), .B(n1324), .A(n1325), .S(
FPMULT_Sgf_operation_Result[30]), .CO(n1320) );
AFHCONX2TS U2346 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .B(n1327), .CI(
n1326), .CON(n1323), .S(FPMULT_Sgf_operation_Result[29]) );
AFHCINX2TS U2347 ( .CIN(n1328), .B(n1329), .A(
FPMULT_Sgf_operation_EVEN1_Q_left[4]), .S(
FPMULT_Sgf_operation_Result[28]), .CO(n1326) );
AFHCONX2TS U2348 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .B(n1331), .CI(
n1330), .CON(n1328), .S(FPMULT_Sgf_operation_Result[27]) );
AFHCINX2TS U2349 ( .CIN(n1332), .B(n1333), .A(
FPMULT_Sgf_operation_EVEN1_Q_left[2]), .S(
FPMULT_Sgf_operation_Result[26]), .CO(n1330) );
AFHCONX2TS U2350 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .B(n1335), .CI(
n1334), .CON(n1332), .S(FPMULT_Sgf_operation_Result[25]) );
AHHCINX2TS U2351 ( .A(n1343), .CIN(n1342), .S(
FPMULT_Sgf_operation_Result[44]), .CO(n1278) );
AFHCONX2TS U2352 ( .A(n1346), .B(n1345), .CI(n1344), .CON(n1308), .S(
FPMULT_Sgf_operation_Result[35]) );
INVX2TS U2353 ( .A(n1623), .Y(n1413) );
AOI22X1TS U2354 ( .A0(n1612), .A1(n1413), .B0(n1623), .B1(n1414), .Y(n1351)
);
BUFX3TS U2355 ( .A(n1351), .Y(n1405) );
BUFX4TS U2356 ( .A(FPMULT_Op_MY[13]), .Y(n3117) );
INVX2TS U2357 ( .A(n1598), .Y(n1386) );
INVX4TS U2358 ( .A(n1645), .Y(n1406) );
AOI22X1TS U2359 ( .A0(n1645), .A1(n1386), .B0(n1598), .B1(n1406), .Y(n1393)
);
OAI221X4TS U2360 ( .A0(n1623), .A1(n1645), .B0(n1413), .B1(n1406), .C0(n1405), .Y(n1404) );
INVX2TS U2361 ( .A(FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .Y(n1442)
);
AOI22X1TS U2362 ( .A0(n1645), .A1(n1442), .B0(
FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .B1(n1406), .Y(n1353)
);
OAI22X1TS U2363 ( .A0(n1405), .A1(n1393), .B0(n1404), .B1(n1353), .Y(n1363)
);
CMPR32X2TS U2364 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .C(n1354),
.CO(n1350), .S(n1602) );
INVX2TS U2365 ( .A(n1602), .Y(n1427) );
AOI22X1TS U2366 ( .A0(n1593), .A1(n1427), .B0(n1602), .B1(n920), .Y(n1355)
);
BUFX3TS U2367 ( .A(n1355), .Y(n1400) );
CMPR32X2TS U2368 ( .A(FPMULT_Op_MY[1]), .B(n3117), .C(n1356), .CO(n1357),
.S(n1598) );
INVX2TS U2369 ( .A(n1627), .Y(n1389) );
AOI22X1TS U2370 ( .A0(n1612), .A1(n1389), .B0(n1627), .B1(n1414), .Y(n1397)
);
OAI221X4TS U2371 ( .A0(n1602), .A1(n1612), .B0(n1427), .B1(n1414), .C0(n1400), .Y(n1398) );
CMPR32X2TS U2372 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[14]), .C(n1357),
.CO(n1358), .S(n1608) );
INVX2TS U2373 ( .A(n1608), .Y(n1391) );
AOI22X1TS U2374 ( .A0(n1612), .A1(n1391), .B0(n1608), .B1(n1414), .Y(n1360)
);
OAI22X1TS U2375 ( .A0(n1400), .A1(n1397), .B0(n1398), .B1(n1360), .Y(n1362)
);
CMPR32X2TS U2376 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[15]), .C(n1358),
.CO(n1364), .S(n1627) );
INVX2TS U2377 ( .A(n1631), .Y(n1407) );
AOI22X1TS U2378 ( .A0(n1593), .A1(n1407), .B0(n1631), .B1(mult_x_313_n74),
.Y(n1359) );
OAI32X1TS U2379 ( .A0(n936), .A1(n1627), .A2(mult_x_313_n74), .B0(n1359),
.B1(n935), .Y(n1368) );
AOI22X1TS U2380 ( .A0(n1612), .A1(n1386), .B0(n1598), .B1(n1414), .Y(n1371)
);
OAI22X1TS U2381 ( .A0(n1400), .A1(n1360), .B0(n1398), .B1(n1371), .Y(n1366)
);
CMPR32X2TS U2382 ( .A(n1363), .B(n1362), .C(n1361), .CO(n1381), .S(n1435) );
CMPR32X2TS U2383 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[16]), .C(n1364),
.CO(n1387), .S(n1631) );
INVX2TS U2384 ( .A(n1635), .Y(n1411) );
AOI22X1TS U2385 ( .A0(n1593), .A1(n1411), .B0(n1635), .B1(mult_x_313_n74),
.Y(n1365) );
OAI32X1TS U2386 ( .A0(n936), .A1(n1631), .A2(mult_x_313_n74), .B0(n1365),
.B1(n935), .Y(n1437) );
OAI32X1TS U2387 ( .A0(n1406), .A1(
FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .A2(n1405), .B0(n1404),
.B1(n1406), .Y(n1436) );
CMPR32X2TS U2388 ( .A(n1368), .B(n1367), .C(n1366), .CO(n1361), .S(n1432) );
AOI22X1TS U2389 ( .A0(n1593), .A1(n1389), .B0(n1627), .B1(n920), .Y(n1369)
);
OAI32X1TS U2390 ( .A0(n936), .A1(n1608), .A2(mult_x_313_n74), .B0(n1369),
.B1(n935), .Y(n1373) );
AOI22X1TS U2391 ( .A0(n1612), .A1(n1442), .B0(
FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .B1(n1414), .Y(n1370)
);
OAI22X1TS U2392 ( .A0(n1400), .A1(n1371), .B0(n1398), .B1(n1370), .Y(n1372)
);
ADDHXLTS U2393 ( .A(n1373), .B(n1372), .CO(n1431), .S(n1440) );
OAI32X1TS U2394 ( .A0(n1414), .A1(
FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .A2(n1400), .B0(n1398),
.B1(n1414), .Y(n1439) );
AOI22X1TS U2395 ( .A0(n1593), .A1(n1391), .B0(n1608), .B1(n920), .Y(n1374)
);
OAI32X1TS U2396 ( .A0(n936), .A1(n1598), .A2(mult_x_313_n74), .B0(n1374),
.B1(n935), .Y(n1384) );
AOI21X1TS U2397 ( .A0(FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .A1(
n936), .B0(mult_x_313_n74), .Y(n1429) );
NAND2X1TS U2398 ( .A(n1593), .B(n935), .Y(n1376) );
AOI22X1TS U2399 ( .A0(n1593), .A1(n1386), .B0(n1598), .B1(n920), .Y(n1375)
);
OAI22X1TS U2400 ( .A0(FPMULT_Sgf_operation_EVEN1_result_B_adder_0_), .A1(
n1376), .B0(n1375), .B1(n935), .Y(n1428) );
CMPR32X2TS U2401 ( .A(mult_x_313_n26), .B(mult_x_313_n30), .C(n1377), .CO(
n1408), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS U2402 ( .A(mult_x_313_n31), .B(mult_x_313_n35), .C(n1378), .CO(
n1377), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS U2403 ( .A(mult_x_313_n36), .B(mult_x_313_n38), .C(n1379), .CO(
n1378), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS U2404 ( .A(mult_x_313_n39), .B(n1381), .C(n1380), .CO(n1379), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS U2405 ( .A(n1384), .B(n1383), .C(n1382), .CO(n1438), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2) );
NAND2X2TS U2406 ( .A(n1645), .B(n1639), .Y(n1421) );
OAI22X1TS U2407 ( .A0(n1389), .A1(n1441), .B0(n1391), .B1(n1421), .Y(
mult_x_313_n27) );
OAI22X1TS U2408 ( .A0(n1407), .A1(n1441), .B0(n1389), .B1(n1421), .Y(
mult_x_313_n54) );
OAI22X1TS U2409 ( .A0(n1442), .A1(n1421), .B0(n1386), .B1(n1441), .Y(
mult_x_313_n55) );
CMPR32X2TS U2410 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[17]), .C(n1387),
.CO(n1551), .S(n1635) );
INVX2TS U2411 ( .A(n1672), .Y(n1423) );
AOI22X1TS U2412 ( .A0(n1645), .A1(n1423), .B0(n1672), .B1(n1406), .Y(n1403)
);
AOI22X1TS U2413 ( .A0(n1645), .A1(n1411), .B0(n1635), .B1(n1406), .Y(n1388)
);
OAI22X1TS U2414 ( .A0(n1405), .A1(n1403), .B0(n1404), .B1(n1388), .Y(
mult_x_313_n58) );
AOI22X1TS U2415 ( .A0(n1645), .A1(n1407), .B0(n1631), .B1(n1406), .Y(n1390)
);
OAI22X1TS U2416 ( .A0(n1405), .A1(n1388), .B0(n1404), .B1(n1390), .Y(
mult_x_313_n59) );
AOI22X1TS U2417 ( .A0(n1645), .A1(n1389), .B0(n1627), .B1(n1406), .Y(n1392)
);
OAI22X1TS U2418 ( .A0(n1405), .A1(n1390), .B0(n1404), .B1(n1392), .Y(
mult_x_313_n60) );
AOI22X1TS U2419 ( .A0(n1645), .A1(n1391), .B0(n1608), .B1(n1406), .Y(n1394)
);
OAI22X1TS U2420 ( .A0(n1405), .A1(n1392), .B0(n1404), .B1(n1394), .Y(
mult_x_313_n61) );
OAI22X1TS U2421 ( .A0(n1405), .A1(n1394), .B0(n1404), .B1(n1393), .Y(
mult_x_313_n62) );
AOI22X1TS U2422 ( .A0(n1612), .A1(n1423), .B0(n1672), .B1(n1414), .Y(n1395)
);
OAI22X1TS U2423 ( .A0(n1414), .A1(n1400), .B0(n1398), .B1(n1395), .Y(
mult_x_313_n66) );
AOI22X1TS U2424 ( .A0(n1612), .A1(n1411), .B0(n1635), .B1(n1414), .Y(n1396)
);
OAI22X1TS U2425 ( .A0(n1400), .A1(n1395), .B0(n1398), .B1(n1396), .Y(
mult_x_313_n67) );
AOI22X1TS U2426 ( .A0(n1612), .A1(n1407), .B0(n1631), .B1(n1414), .Y(n1399)
);
OAI22X1TS U2427 ( .A0(n1400), .A1(n1396), .B0(n1398), .B1(n1399), .Y(
mult_x_313_n68) );
OAI22X1TS U2428 ( .A0(n1400), .A1(n1399), .B0(n1398), .B1(n1397), .Y(
mult_x_313_n69) );
AOI21X1TS U2429 ( .A0(n1672), .A1(n935), .B0(mult_x_313_n74), .Y(
mult_x_313_n75) );
AOI22X1TS U2430 ( .A0(n1672), .A1(mult_x_313_n74), .B0(n1593), .B1(n1423),
.Y(n1402) );
OAI32X1TS U2431 ( .A0(n936), .A1(n1635), .A2(mult_x_313_n74), .B0(n1402),
.B1(n935), .Y(mult_x_313_n76) );
OAI22X1TS U2432 ( .A0(n1406), .A1(n1405), .B0(n1404), .B1(n1403), .Y(n1418)
);
INVX2TS U2433 ( .A(n1418), .Y(n1410) );
OAI22X1TS U2434 ( .A0(n1411), .A1(n1441), .B0(n1407), .B1(n1421), .Y(n1409)
);
CMPR32X2TS U2435 ( .A(mult_x_313_n23), .B(mult_x_313_n25), .C(n1408), .CO(
n1415), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS U2436 ( .A(n1410), .B(n1409), .C(mult_x_313_n21), .CO(n1445), .S(
n1416) );
OAI22X1TS U2437 ( .A0(n1423), .A1(n1441), .B0(n1411), .B1(n1421), .Y(n1419)
);
OAI21X1TS U2438 ( .A0(n1414), .A1(n1413), .B0(n1645), .Y(n1417) );
CMPR32X2TS U2439 ( .A(mult_x_313_n22), .B(n1416), .C(n1415), .CO(n1443), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11) );
CMPR32X2TS U2440 ( .A(n1419), .B(n1418), .C(n1417), .CO(n1422), .S(n1444) );
OAI31X1TS U2441 ( .A0(n1423), .A1(n1422), .A2(n1421), .B0(n1420), .Y(n1424)
);
XNOR2X1TS U2442 ( .A(n1425), .B(n1424), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13) );
INVX2TS U2443 ( .A(mult_x_313_n32), .Y(mult_x_313_n33) );
INVX2TS U2444 ( .A(mult_x_313_n27), .Y(mult_x_313_n28) );
ADDHXLTS U2445 ( .A(n1429), .B(n1428), .CO(n1382), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1) );
CMPR32X2TS U2446 ( .A(n1432), .B(n1431), .C(n1430), .CO(n1433), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4) );
CMPR32X2TS U2447 ( .A(n1435), .B(n1434), .C(n1433), .CO(n1380), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5) );
ADDHXLTS U2448 ( .A(n1437), .B(n1436), .CO(mult_x_313_n42), .S(n1434) );
CMPR32X2TS U2449 ( .A(n1440), .B(n1439), .C(n1438), .CO(n1430), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3) );
CMPR32X2TS U2450 ( .A(n1445), .B(n1444), .C(n1443), .CO(n1425), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12) );
XNOR2X1TS U2451 ( .A(FPMULT_Op_MX[17]), .B(n1489), .Y(n1447) );
BUFX3TS U2452 ( .A(n1447), .Y(n1511) );
INVX2TS U2453 ( .A(n1467), .Y(n1505) );
AOI22X1TS U2454 ( .A0(n1514), .A1(n1467), .B0(n1505), .B1(n1511), .Y(n1517)
);
CMPR32X2TS U2455 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[22]), .C(n1449),
.CO(n1489), .S(n1451) );
INVX2TS U2456 ( .A(n1451), .Y(n1494) );
AOI22X1TS U2457 ( .A0(n1535), .A1(n1494), .B0(n1451), .B1(n1522), .Y(n1450)
);
BUFX3TS U2458 ( .A(n1450), .Y(n1518) );
OAI221X4TS U2459 ( .A0(n1451), .A1(n1511), .B0(n1494), .B1(n1514), .C0(n1518), .Y(n1516) );
AOI22X1TS U2460 ( .A0(n961), .A1(n1514), .B0(n1511), .B1(n960), .Y(n1452) );
OAI22X1TS U2461 ( .A0(n1517), .A1(n1518), .B0(n1516), .B1(n1452), .Y(n1478)
);
CMPR32X2TS U2462 ( .A(n3117), .B(FPMULT_Op_MY[19]), .C(n1453), .CO(n1459),
.S(n1467) );
CMPR32X2TS U2463 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[22]), .C(n1454),
.CO(n1490), .S(n1523) );
CLKXOR2X2TS U2464 ( .A(FPMULT_Op_MY[17]), .B(n1490), .Y(n1520) );
INVX2TS U2465 ( .A(n1520), .Y(n1533) );
AOI22X1TS U2466 ( .A0(n1520), .A1(DP_OP_500J324_126_4510_n32), .B0(
DP_OP_500J324_126_4510_n27), .B1(n1533), .Y(n1456) );
INVX2TS U2467 ( .A(DP_OP_500J324_126_4510_n161), .Y(n1455) );
OAI32X1TS U2468 ( .A0(n1514), .A1(n961), .A2(n1518), .B0(n1516), .B1(n1514),
.Y(n1476) );
INVX2TS U2469 ( .A(n1460), .Y(n1536) );
AOI22X1TS U2470 ( .A0(DP_OP_500J324_126_4510_n32), .A1(n1536), .B0(n1460),
.B1(n921), .Y(n1458) );
BUFX3TS U2471 ( .A(n1458), .Y(n1529) );
CMPR32X2TS U2472 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[20]), .C(n1459),
.CO(n1461), .S(n1513) );
INVX2TS U2473 ( .A(n1513), .Y(n1512) );
AOI22X1TS U2474 ( .A0(n1535), .A1(n1512), .B0(n1513), .B1(n1522), .Y(n1472)
);
OAI221X4TS U2475 ( .A0(n1460), .A1(n1535), .B0(n1536), .B1(n1522), .C0(n1529), .Y(n1527) );
AOI22X1TS U2476 ( .A0(n1535), .A1(n1505), .B0(n1467), .B1(n1522), .Y(n1465)
);
OAI22X1TS U2477 ( .A0(n1529), .A1(n1472), .B0(n1527), .B1(n1465), .Y(n1474)
);
CMPR32X2TS U2478 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[21]), .C(n1461),
.CO(n1454), .S(n1509) );
INVX2TS U2479 ( .A(n1523), .Y(n1524) );
AOI22X1TS U2480 ( .A0(n1523), .A1(DP_OP_500J324_126_4510_n27), .B0(
DP_OP_500J324_126_4510_n32), .B1(n1524), .Y(n1462) );
INVX2TS U2481 ( .A(n1509), .Y(n1508) );
AOI22X1TS U2482 ( .A0(n1509), .A1(n921), .B0(DP_OP_500J324_126_4510_n32),
.B1(n1508), .Y(n1463) );
AOI22X1TS U2483 ( .A0(n961), .A1(n1522), .B0(n1535), .B1(n960), .Y(n1464) );
OAI22X1TS U2484 ( .A0(n1529), .A1(n1465), .B0(n1527), .B1(n1464), .Y(n1470)
);
OAI32X1TS U2485 ( .A0(n1522), .A1(n961), .A2(n1529), .B0(n1527), .B1(n1522),
.Y(n1539) );
AOI22X1TS U2486 ( .A0(n1513), .A1(n921), .B0(DP_OP_500J324_126_4510_n32),
.B1(n1512), .Y(n1466) );
NOR2X1TS U2487 ( .A(n960), .B(n1529), .Y(n1485) );
AOI21X1TS U2488 ( .A0(n961), .A1(DP_OP_500J324_126_4510_n161), .B0(
DP_OP_500J324_126_4510_n27), .Y(n1488) );
NAND2X1TS U2489 ( .A(DP_OP_500J324_126_4510_n32), .B(n1455), .Y(n1469) );
AOI22X1TS U2490 ( .A0(n1467), .A1(n921), .B0(DP_OP_500J324_126_4510_n32),
.B1(n1505), .Y(n1468) );
OAI22X1TS U2491 ( .A0(n961), .A1(n1469), .B0(n1468), .B1(n1455), .Y(n1487)
);
ADDHXLTS U2492 ( .A(n1471), .B(n1470), .CO(n1541), .S(n1537) );
AOI22X1TS U2493 ( .A0(n1535), .A1(n1508), .B0(n1509), .B1(n1522), .Y(n1526)
);
OAI22X1TS U2494 ( .A0(n1529), .A1(n1526), .B0(n1527), .B1(n1472), .Y(n1547)
);
CMPR32X2TS U2495 ( .A(n1475), .B(n1474), .C(n1473), .CO(n1546), .S(n1542) );
CMPR32X2TS U2496 ( .A(n1478), .B(n1477), .C(n1476), .CO(n1483), .S(n1543) );
CMPR32X2TS U2497 ( .A(DP_OP_500J324_126_4510_n26), .B(
DP_OP_500J324_126_4510_n30), .C(n1479), .CO(n1491), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
CMPR32X2TS U2498 ( .A(DP_OP_500J324_126_4510_n31), .B(
DP_OP_500J324_126_4510_n34), .C(n1480), .CO(n1479), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
CMPR32X2TS U2499 ( .A(DP_OP_500J324_126_4510_n35), .B(
DP_OP_500J324_126_4510_n37), .C(n1481), .CO(n1480), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
CMPR32X2TS U2500 ( .A(DP_OP_500J324_126_4510_n38), .B(n1483), .C(n1482),
.CO(n1481), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
CMPR32X2TS U2501 ( .A(n1486), .B(n1485), .C(n1484), .CO(n1538), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
ADDHXLTS U2502 ( .A(n1488), .B(n1487), .CO(n1484), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1) );
NAND2X2TS U2503 ( .A(FPMULT_Op_MX[17]), .B(n1489), .Y(n1504) );
INVX2TS U2504 ( .A(n1504), .Y(n1534) );
OAI22X1TS U2505 ( .A0(n1504), .A1(n1523), .B0(n1533), .B1(n1534), .Y(n1493)
);
INVX2TS U2506 ( .A(n1531), .Y(n1530) );
AOI22X1TS U2507 ( .A0(n1514), .A1(n1530), .B0(n1531), .B1(n1511), .Y(n1506)
);
OAI22X1TS U2508 ( .A0(n1514), .A1(n1518), .B0(n1516), .B1(n1506), .Y(n1492)
);
CMPR32X2TS U2509 ( .A(DP_OP_500J324_126_4510_n23), .B(
DP_OP_500J324_126_4510_n25), .C(n1491), .CO(n1495), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
CMPR32X2TS U2510 ( .A(n1493), .B(n1492), .C(DP_OP_500J324_126_4510_n21),
.CO(n1550), .S(n1496) );
AOI22X1TS U2511 ( .A0(n1534), .A1(n1520), .B0(n1531), .B1(n1504), .Y(n1499)
);
INVX2TS U2512 ( .A(n1493), .Y(n1498) );
CMPR32X2TS U2513 ( .A(n1496), .B(DP_OP_500J324_126_4510_n22), .C(n1495),
.CO(n1548), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
CMPR32X2TS U2514 ( .A(n1499), .B(n1498), .C(n1497), .CO(n1501), .S(n1549) );
OAI31X1TS U2515 ( .A0(n1531), .A1(n1501), .A2(n1504), .B0(n1500), .Y(n1502)
);
XNOR2X1TS U2516 ( .A(n1503), .B(n1502), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
AOI22X1TS U2517 ( .A0(n1534), .A1(n1508), .B0(n1524), .B1(n1504), .Y(
DP_OP_500J324_126_4510_n52) );
AOI22X1TS U2518 ( .A0(n1534), .A1(n1512), .B0(n1508), .B1(n1504), .Y(
DP_OP_500J324_126_4510_n53) );
AOI22X1TS U2519 ( .A0(n1534), .A1(n1505), .B0(n1512), .B1(n1504), .Y(
DP_OP_500J324_126_4510_n54) );
AOI22X1TS U2520 ( .A0(n1534), .A1(n960), .B0(n1505), .B1(n1504), .Y(
DP_OP_500J324_126_4510_n55) );
AOI22X1TS U2521 ( .A0(n1514), .A1(n1533), .B0(n1520), .B1(n1511), .Y(n1507)
);
OAI22X1TS U2522 ( .A0(n1518), .A1(n1506), .B0(n1516), .B1(n1507), .Y(
DP_OP_500J324_126_4510_n59) );
AOI22X1TS U2523 ( .A0(n1514), .A1(n1523), .B0(n1524), .B1(n1511), .Y(n1510)
);
OAI22X1TS U2524 ( .A0(n1510), .A1(n1516), .B0(n1518), .B1(n1507), .Y(
DP_OP_500J324_126_4510_n60) );
AOI22X1TS U2525 ( .A0(n1514), .A1(n1509), .B0(n1508), .B1(n1511), .Y(n1515)
);
OAI22X1TS U2526 ( .A0(n1510), .A1(n1518), .B0(n1515), .B1(n1516), .Y(
DP_OP_500J324_126_4510_n61) );
AOI22X1TS U2527 ( .A0(n1514), .A1(n1513), .B0(n1512), .B1(n1511), .Y(n1519)
);
OAI22X1TS U2528 ( .A0(n1515), .A1(n1518), .B0(n1519), .B1(n1516), .Y(
DP_OP_500J324_126_4510_n62) );
OAI22X1TS U2529 ( .A0(n1519), .A1(n1518), .B0(n1517), .B1(n1516), .Y(
DP_OP_500J324_126_4510_n63) );
AOI22X1TS U2530 ( .A0(n1535), .A1(n1531), .B0(n1530), .B1(n1522), .Y(n1521)
);
OAI22X1TS U2531 ( .A0(n1521), .A1(n1527), .B0(n1522), .B1(n1529), .Y(
DP_OP_500J324_126_4510_n67) );
AOI22X1TS U2532 ( .A0(n1535), .A1(n1520), .B0(n1533), .B1(n1522), .Y(n1525)
);
OAI22X1TS U2533 ( .A0(n1521), .A1(n1529), .B0(n1525), .B1(n1527), .Y(
DP_OP_500J324_126_4510_n68) );
AOI22X1TS U2534 ( .A0(n1535), .A1(n1524), .B0(n1523), .B1(n1522), .Y(n1528)
);
OAI22X1TS U2535 ( .A0(n1525), .A1(n1529), .B0(n1527), .B1(n1528), .Y(
DP_OP_500J324_126_4510_n69) );
OAI22X1TS U2536 ( .A0(n1529), .A1(n1528), .B0(n1527), .B1(n1526), .Y(
DP_OP_500J324_126_4510_n70) );
AOI21X1TS U2537 ( .A0(n1530), .A1(n1455), .B0(DP_OP_500J324_126_4510_n27),
.Y(DP_OP_500J324_126_4510_n75) );
AOI22X1TS U2538 ( .A0(n1531), .A1(DP_OP_500J324_126_4510_n32), .B0(
DP_OP_500J324_126_4510_n27), .B1(n1530), .Y(n1532) );
OAI32X1TS U2539 ( .A0(DP_OP_500J324_126_4510_n161), .A1(n1533), .A2(
DP_OP_500J324_126_4510_n27), .B0(n1532), .B1(n1455), .Y(
DP_OP_500J324_126_4510_n76) );
NOR2X1TS U2540 ( .A(n1534), .B(n960), .Y(DP_OP_500J324_126_4510_n56) );
OAI21X1TS U2541 ( .A0(DP_OP_500J324_126_4510_n27), .A1(n1536), .B0(n1535),
.Y(DP_OP_500J324_126_4510_n66) );
CMPR32X2TS U2542 ( .A(n1539), .B(n1538), .C(n1537), .CO(n1540), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
CMPR32X2TS U2543 ( .A(n1542), .B(n1541), .C(n1540), .CO(n1545), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
CMPR32X2TS U2544 ( .A(n1545), .B(n1544), .C(n1543), .CO(n1482), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
ADDHXLTS U2545 ( .A(n1547), .B(n1546), .CO(DP_OP_500J324_126_4510_n41), .S(
n1544) );
CMPR32X2TS U2546 ( .A(n1550), .B(n1549), .C(n1548), .CO(n1503), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
CMPR32X2TS U2547 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[18]), .C(n1551),
.CO(n1555), .S(n1672) );
CMPR32X2TS U2548 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .C(n1552),
.CO(n1553), .S(n1639) );
INVX2TS U2549 ( .A(DP_OP_501J324_127_5235_n330), .Y(n1579) );
CMPR32X2TS U2550 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .C(n1553),
.CO(n1554), .S(DP_OP_501J324_127_5235_n359) );
INVX2TS U2551 ( .A(n1603), .Y(n1580) );
CMPR32X2TS U2552 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[20]), .C(n1554),
.CO(n1557), .S(n1592) );
INVX2TS U2553 ( .A(n1592), .Y(n1680) );
INVX2TS U2554 ( .A(n1597), .Y(n1681) );
INVX2TS U2555 ( .A(DP_OP_501J324_127_5235_n359), .Y(n1682) );
CMPR32X2TS U2556 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[20]), .C(n1556),
.CO(n1560), .S(n1597) );
INVX2TS U2557 ( .A(n1609), .Y(n1683) );
CMPR32X2TS U2558 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .C(n1557),
.CO(n1561), .S(n1603) );
INVX2TS U2559 ( .A(n1613), .Y(n1685) );
ADDHXLTS U2560 ( .A(n1559), .B(n1558), .CO(n1589), .S(n1567) );
CMPR32X2TS U2561 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .C(n1560),
.CO(n1570), .S(n1609) );
INVX2TS U2562 ( .A(n1628), .Y(n1684) );
CMPR32X2TS U2563 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .C(n1561),
.CO(n1571), .S(n1613) );
CLKXOR2X2TS U2564 ( .A(FPMULT_Op_MX[11]), .B(n1571), .Y(n1736) );
CMPR32X2TS U2565 ( .A(DP_OP_501J324_127_5235_n18), .B(
DP_OP_501J324_127_5235_n22), .C(n1562), .CO(n1694), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS U2566 ( .A(DP_OP_501J324_127_5235_n23), .B(
DP_OP_501J324_127_5235_n29), .C(n1563), .CO(n1562), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS U2567 ( .A(DP_OP_501J324_127_5235_n30), .B(
DP_OP_501J324_127_5235_n36), .C(n1564), .CO(n1563), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS U2568 ( .A(n1566), .B(n1565), .C(DP_OP_501J324_127_5235_n37),
.CO(n1564), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS U2569 ( .A(n1569), .B(n1568), .C(n1567), .CO(n1693), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2) );
CMPR32X2TS U2570 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .C(n1570),
.CO(n1575), .S(n1628) );
NOR2X4TS U2571 ( .A(FPMULT_Op_MY[11]), .B(n1575), .Y(n1698) );
NOR2X4TS U2572 ( .A(FPMULT_Op_MX[11]), .B(n1571), .Y(n1697) );
CMPR32X2TS U2573 ( .A(n1574), .B(n1573), .C(n1572), .CO(
DP_OP_501J324_127_5235_n19), .S(DP_OP_501J324_127_5235_n20) );
CLKXOR2X2TS U2574 ( .A(FPMULT_Op_MY[11]), .B(n1575), .Y(n1737) );
NOR2X1TS U2575 ( .A(n1737), .B(n1580), .Y(n1576) );
CMPR32X2TS U2576 ( .A(n1578), .B(n1577), .C(n1576), .CO(
DP_OP_501J324_127_5235_n24), .S(DP_OP_501J324_127_5235_n25) );
ADDHXLTS U2577 ( .A(n1582), .B(n1581), .CO(n1586), .S(n1692) );
CMPR32X2TS U2578 ( .A(n1585), .B(n1584), .C(n1583), .CO(
DP_OP_501J324_127_5235_n31), .S(DP_OP_501J324_127_5235_n32) );
ADDHXLTS U2579 ( .A(n1587), .B(n1586), .CO(n1583), .S(
DP_OP_501J324_127_5235_n39) );
CMPR32X2TS U2580 ( .A(n1590), .B(n1589), .C(n1588), .CO(
DP_OP_501J324_127_5235_n40), .S(n1691) );
INVX2TS U2581 ( .A(DP_OP_501J324_127_5235_n294), .Y(n1667) );
ADDHXLTS U2582 ( .A(n936), .B(DP_OP_501J324_127_5235_n359), .CO(n1594), .S(
DP_OP_501J324_127_5235_n302) );
INVX2TS U2583 ( .A(n1591), .Y(n1676) );
CMPR32X2TS U2584 ( .A(n1594), .B(n1593), .C(n1592), .CO(n1601), .S(n1595) );
INVX2TS U2585 ( .A(n1595), .Y(n1677) );
INVX2TS U2586 ( .A(n1596), .Y(n1674) );
CMPR32X2TS U2587 ( .A(n1599), .B(n1598), .C(n1597), .CO(n1607), .S(n1596) );
CMPR32X2TS U2588 ( .A(n1603), .B(n1602), .C(n1601), .CO(n1611), .S(n1591) );
INVX2TS U2589 ( .A(n1604), .Y(n1724) );
ADDHXLTS U2590 ( .A(n1606), .B(n1605), .CO(n1659), .S(n1619) );
CMPR32X2TS U2591 ( .A(n1609), .B(n1608), .C(n1607), .CO(n1626), .S(n1600) );
CMPR32X2TS U2592 ( .A(n1613), .B(n1612), .C(n1611), .CO(n1624), .S(n1604) );
INVX2TS U2593 ( .A(n1736), .Y(n1622) );
INVX2TS U2594 ( .A(n1614), .Y(n1726) );
CMPR32X2TS U2595 ( .A(DP_OP_501J324_127_5235_n125), .B(
DP_OP_501J324_127_5235_n132), .C(n1615), .CO(n1662), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9) );
CMPR32X2TS U2596 ( .A(DP_OP_501J324_127_5235_n133), .B(
DP_OP_501J324_127_5235_n142), .C(n1616), .CO(n1615), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8) );
CMPR32X2TS U2597 ( .A(n1617), .B(DP_OP_501J324_127_5235_n156), .C(
DP_OP_501J324_127_5235_n153), .CO(n1661), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6) );
CMPR32X2TS U2598 ( .A(n1618), .B(DP_OP_501J324_127_5235_n167), .C(
DP_OP_501J324_127_5235_n161), .CO(n1617), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5) );
CMPR32X2TS U2599 ( .A(n1621), .B(n1620), .C(n1619), .CO(n1688), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2) );
INVX2TS U2600 ( .A(n1697), .Y(n1646) );
CMPR32X2TS U2601 ( .A(n1624), .B(n1623), .C(n1622), .CO(n1644), .S(n1614) );
INVX2TS U2602 ( .A(n1625), .Y(n1717) );
CMPR32X2TS U2603 ( .A(n1628), .B(n1627), .C(n1626), .CO(n1632), .S(n1610) );
INVX2TS U2604 ( .A(n1737), .Y(n1630) );
INVX2TS U2605 ( .A(n1698), .Y(n1636) );
CMPR32X2TS U2606 ( .A(n1632), .B(n1631), .C(n1630), .CO(n1634), .S(n1629) );
CMPR32X2TS U2607 ( .A(n1636), .B(n1635), .C(n1634), .CO(n1671), .S(n1637) );
ADDHXLTS U2608 ( .A(n1639), .B(n1638), .CO(n1625), .S(n1640) );
INVX2TS U2609 ( .A(n1640), .Y(n1713) );
CMPR32X2TS U2610 ( .A(n1643), .B(n1642), .C(n1641), .CO(
DP_OP_501J324_127_5235_n115), .S(DP_OP_501J324_127_5235_n116) );
CMPR32X2TS U2611 ( .A(n1646), .B(n1645), .C(n1644), .CO(n1638), .S(n1647) );
INVX2TS U2612 ( .A(n1647), .Y(n1679) );
CMPR32X2TS U2613 ( .A(n1650), .B(n1649), .C(n1648), .CO(
DP_OP_501J324_127_5235_n147), .S(DP_OP_501J324_127_5235_n148) );
ADDHXLTS U2614 ( .A(n1652), .B(n1651), .CO(n1730), .S(n1657) );
ADDHXLTS U2615 ( .A(n1654), .B(n1653), .CO(n1732), .S(n1687) );
CMPR32X2TS U2616 ( .A(n1657), .B(n1656), .C(n1655), .CO(
DP_OP_501J324_127_5235_n162), .S(DP_OP_501J324_127_5235_n163) );
CMPR32X2TS U2617 ( .A(n1660), .B(n1659), .C(n1658), .CO(
DP_OP_501J324_127_5235_n171), .S(n1686) );
CMPR32X2TS U2618 ( .A(DP_OP_501J324_127_5235_n143), .B(
DP_OP_501J324_127_5235_n152), .C(n1661), .CO(n1616), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7) );
CMPR32X2TS U2619 ( .A(DP_OP_501J324_127_5235_n119), .B(
DP_OP_501J324_127_5235_n124), .C(n1662), .CO(n1663), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10) );
CMPR32X2TS U2620 ( .A(DP_OP_501J324_127_5235_n114), .B(
DP_OP_501J324_127_5235_n118), .C(n1663), .CO(n1714), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11) );
CMPR32X2TS U2621 ( .A(n1666), .B(n1665), .C(n1664), .CO(
DP_OP_501J324_127_5235_n137), .S(DP_OP_501J324_127_5235_n138) );
NOR2X1TS U2622 ( .A(n1674), .B(n1713), .Y(DP_OP_501J324_127_5235_n191) );
NOR2X1TS U2623 ( .A(n1675), .B(n1713), .Y(DP_OP_501J324_127_5235_n190) );
NOR2X1TS U2624 ( .A(n1674), .B(n1679), .Y(DP_OP_501J324_127_5235_n199) );
NOR2X1TS U2625 ( .A(n1717), .B(n1674), .Y(DP_OP_501J324_127_5235_n183) );
NOR2X1TS U2626 ( .A(n1727), .B(n1713), .Y(DP_OP_501J324_127_5235_n189) );
NOR2X1TS U2627 ( .A(n1718), .B(n940), .Y(DP_OP_501J324_127_5235_n233) );
NOR2X1TS U2628 ( .A(n1717), .B(n1675), .Y(DP_OP_501J324_127_5235_n182) );
NOR2X1TS U2629 ( .A(n1725), .B(n1676), .Y(DP_OP_501J324_127_5235_n220) );
CMPR32X2TS U2630 ( .A(n1670), .B(n1669), .C(n1668), .CO(
DP_OP_501J324_127_5235_n129), .S(DP_OP_501J324_127_5235_n130) );
NOR2X1TS U2631 ( .A(n1717), .B(n1727), .Y(DP_OP_501J324_127_5235_n181) );
NOR2X1TS U2632 ( .A(n1727), .B(n1677), .Y(DP_OP_501J324_127_5235_n229) );
NOR2X1TS U2633 ( .A(n1678), .B(n1679), .Y(DP_OP_501J324_127_5235_n195) );
NOR2X1TS U2634 ( .A(n1674), .B(n1724), .Y(DP_OP_501J324_127_5235_n215) );
NOR2X1TS U2635 ( .A(n1718), .B(n1724), .Y(DP_OP_501J324_127_5235_n209) );
ADDHXLTS U2636 ( .A(n1672), .B(n1671), .CO(n1633), .S(n1673) );
INVX2TS U2637 ( .A(n1673), .Y(n1712) );
NOR2X1TS U2638 ( .A(n1712), .B(n940), .Y(DP_OP_501J324_127_5235_n234) );
NOR2X1TS U2639 ( .A(n1674), .B(n1726), .Y(DP_OP_501J324_127_5235_n207) );
NOR2X1TS U2640 ( .A(n1678), .B(n940), .Y(DP_OP_501J324_127_5235_n235) );
NOR2X1TS U2641 ( .A(n1675), .B(n1726), .Y(DP_OP_501J324_127_5235_n206) );
NOR2X1TS U2642 ( .A(n1712), .B(n1677), .Y(DP_OP_501J324_127_5235_n226) );
NOR2X1TS U2643 ( .A(n1712), .B(n1676), .Y(DP_OP_501J324_127_5235_n218) );
NOR2X1TS U2644 ( .A(n1712), .B(n1713), .Y(DP_OP_501J324_127_5235_n186) );
NOR2X1TS U2645 ( .A(n1712), .B(n1679), .Y(DP_OP_501J324_127_5235_n194) );
NOR2X1TS U2646 ( .A(n1717), .B(n1678), .Y(DP_OP_501J324_127_5235_n179) );
NOR2X1TS U2647 ( .A(n1718), .B(n1679), .Y(DP_OP_501J324_127_5235_n193) );
NOR2X1TS U2648 ( .A(n1684), .B(n1680), .Y(DP_OP_501J324_127_5235_n72) );
NOR2X1TS U2649 ( .A(n1681), .B(n1685), .Y(DP_OP_501J324_127_5235_n62) );
NOR2X1TS U2650 ( .A(n1737), .B(n1680), .Y(DP_OP_501J324_127_5235_n71) );
NOR2X1TS U2651 ( .A(n1736), .B(n1681), .Y(DP_OP_501J324_127_5235_n56) );
NOR2X1TS U2652 ( .A(n1736), .B(n1683), .Y(DP_OP_501J324_127_5235_n55) );
NOR2X1TS U2653 ( .A(n1697), .B(n1684), .Y(DP_OP_501J324_127_5235_n48) );
NOR2X1TS U2654 ( .A(n1736), .B(n1684), .Y(DP_OP_501J324_127_5235_n54) );
NOR2X1TS U2655 ( .A(n1737), .B(n1685), .Y(DP_OP_501J324_127_5235_n59) );
NOR2X1TS U2656 ( .A(n1698), .B(n1685), .Y(DP_OP_501J324_127_5235_n58) );
CMPR32X2TS U2657 ( .A(n1688), .B(n1687), .C(n1686), .CO(n1690), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3) );
CMPR32X2TS U2658 ( .A(n1690), .B(n1689), .C(DP_OP_501J324_127_5235_n168),
.CO(n1618), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4) );
CMPR32X2TS U2659 ( .A(n1693), .B(n1692), .C(n1691), .CO(n1566), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3) );
NOR2X1TS U2660 ( .A(n1697), .B(n1737), .Y(n1696) );
NOR2X1TS U2661 ( .A(n1698), .B(n1736), .Y(n1695) );
CMPR32X2TS U2662 ( .A(DP_OP_501J324_127_5235_n15), .B(
DP_OP_501J324_127_5235_n17), .C(n1694), .CO(n1699), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS U2663 ( .A(n1696), .B(n1695), .C(DP_OP_501J324_127_5235_n13),
.CO(n1703), .S(n1700) );
CMPR32X2TS U2664 ( .A(DP_OP_501J324_127_5235_n14), .B(n1700), .C(n1699),
.CO(n1701), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS U2665 ( .A(n1703), .B(n1702), .C(n1701), .CO(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10) );
ADDHXLTS U2666 ( .A(n1705), .B(n1704), .CO(n1578), .S(
DP_OP_501J324_127_5235_n34) );
ADDHXLTS U2667 ( .A(n1707), .B(n1706), .CO(n1620), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1) );
ADDHXLTS U2668 ( .A(n1709), .B(n1708), .CO(n1568), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1) );
ADDHXLTS U2669 ( .A(n1711), .B(n1710), .CO(n1572), .S(
DP_OP_501J324_127_5235_n27) );
CMPR32X2TS U2670 ( .A(DP_OP_501J324_127_5235_n113), .B(
DP_OP_501J324_127_5235_n111), .C(n1714), .CO(n1719), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12) );
CMPR32X2TS U2671 ( .A(n1716), .B(n1715), .C(DP_OP_501J324_127_5235_n109),
.CO(n1723), .S(n1720) );
CMPR32X2TS U2672 ( .A(DP_OP_501J324_127_5235_n110), .B(n1720), .C(n1719),
.CO(n1721), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13) );
CMPR32X2TS U2673 ( .A(n1723), .B(n1722), .C(n1721), .CO(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14) );
ADDHXLTS U2674 ( .A(n1729), .B(n1728), .CO(DP_OP_501J324_127_5235_n139), .S(
DP_OP_501J324_127_5235_n140) );
ADDHXLTS U2675 ( .A(n1731), .B(n1730), .CO(n1649), .S(
DP_OP_501J324_127_5235_n158) );
ADDHXLTS U2676 ( .A(n1733), .B(n1732), .CO(n1656), .S(
DP_OP_501J324_127_5235_n170) );
ADDHXLTS U2677 ( .A(n1735), .B(n1734), .CO(n1728), .S(
DP_OP_501J324_127_5235_n150) );
NOR2X1TS U2678 ( .A(n1737), .B(n1736), .Y(DP_OP_501J324_127_5235_n53) );
CMPR32X4TS U2679 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[7]), .C(n1738), .CO(
n1744), .S(DP_OP_502J324_128_4510_n32) );
INVX2TS U2680 ( .A(n1742), .Y(n1786) );
AOI22X1TS U2681 ( .A0(n1828), .A1(n1786), .B0(n1742), .B1(n1814), .Y(n1740)
);
BUFX3TS U2682 ( .A(n1740), .Y(n1811) );
INVX2TS U2683 ( .A(n1759), .Y(n1796) );
INVX4TS U2684 ( .A(n1806), .Y(n1803) );
AOI22X1TS U2685 ( .A0(n1806), .A1(n1796), .B0(n1759), .B1(n1803), .Y(n1808)
);
OAI221X4TS U2686 ( .A0(n1742), .A1(n1806), .B0(n1786), .B1(n1803), .C0(n1811), .Y(n1809) );
INVX2TS U2687 ( .A(DP_OP_502J324_128_4510_n160), .Y(n1827) );
AOI22X1TS U2688 ( .A0(n1806), .A1(n1827), .B0(DP_OP_502J324_128_4510_n160),
.B1(n1803), .Y(n1743) );
OAI22X1TS U2689 ( .A0(n1811), .A1(n1808), .B0(n1809), .B1(n1743), .Y(n1769)
);
INVX2TS U2690 ( .A(n1747), .Y(n1829) );
AOI22X1TS U2691 ( .A0(DP_OP_502J324_128_4510_n32), .A1(n1829), .B0(n1747),
.B1(DP_OP_502J324_128_4510_n27), .Y(n1745) );
BUFX3TS U2692 ( .A(n1745), .Y(n1821) );
INVX2TS U2693 ( .A(n1804), .Y(n1805) );
AOI22X1TS U2694 ( .A0(n1828), .A1(n1805), .B0(n1804), .B1(n1814), .Y(n1764)
);
OAI221X4TS U2695 ( .A0(n1747), .A1(n1828), .B0(n1829), .B1(n1814), .C0(n1821), .Y(n1819) );
AOI22X1TS U2696 ( .A0(n1828), .A1(n1796), .B0(n1759), .B1(n1814), .Y(n1757)
);
OAI22X1TS U2697 ( .A0(n1821), .A1(n1764), .B0(n1819), .B1(n1757), .Y(n1753)
);
CMPR32X2TS U2698 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[8]), .C(n1748), .CO(
n1749), .S(n1804) );
CMPR32X2TS U2699 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[9]), .C(n1749), .CO(
n1765), .S(n1800) );
INVX2TS U2700 ( .A(n1815), .Y(n1816) );
AOI22X1TS U2701 ( .A0(DP_OP_502J324_128_4510_n32), .A1(n1816), .B0(n1815),
.B1(DP_OP_502J324_128_4510_n27), .Y(n1751) );
INVX2TS U2702 ( .A(DP_OP_502J324_128_4510_n161), .Y(n1750) );
OAI32X1TS U2703 ( .A0(n1803), .A1(DP_OP_502J324_128_4510_n160), .A2(n1811),
.B0(n1809), .B1(n1803), .Y(n1767) );
CMPR32X2TS U2704 ( .A(n1754), .B(n1753), .C(n1752), .CO(n1768), .S(n1840) );
INVX2TS U2705 ( .A(n1800), .Y(n1801) );
AOI22X1TS U2706 ( .A0(DP_OP_502J324_128_4510_n32), .A1(n1801), .B0(n1800),
.B1(DP_OP_502J324_128_4510_n27), .Y(n1755) );
AOI22X1TS U2707 ( .A0(n1828), .A1(n1827), .B0(DP_OP_502J324_128_4510_n160),
.B1(n1814), .Y(n1756) );
OAI22X1TS U2708 ( .A0(n1821), .A1(n1757), .B0(n1819), .B1(n1756), .Y(n1762)
);
OAI32X1TS U2709 ( .A0(n1814), .A1(DP_OP_502J324_128_4510_n160), .A2(n1821),
.B0(n1819), .B1(n1814), .Y(n1832) );
AOI22X1TS U2710 ( .A0(DP_OP_502J324_128_4510_n32), .A1(n1805), .B0(n1804),
.B1(DP_OP_502J324_128_4510_n27), .Y(n1758) );
AOI21X1TS U2711 ( .A0(DP_OP_502J324_128_4510_n160), .A1(
DP_OP_502J324_128_4510_n161), .B0(DP_OP_502J324_128_4510_n27), .Y(
n1779) );
NAND2X1TS U2712 ( .A(DP_OP_502J324_128_4510_n32), .B(n1750), .Y(n1761) );
AOI22X1TS U2713 ( .A0(DP_OP_502J324_128_4510_n32), .A1(n1796), .B0(n1759),
.B1(DP_OP_502J324_128_4510_n27), .Y(n1760) );
OAI22X1TS U2714 ( .A0(DP_OP_502J324_128_4510_n160), .A1(n1761), .B0(n1760),
.B1(n1750), .Y(n1778) );
ADDHXLTS U2715 ( .A(n1763), .B(n1762), .CO(n1839), .S(n1830) );
AOI22X1TS U2716 ( .A0(n1828), .A1(n1801), .B0(n1800), .B1(n1814), .Y(n1818)
);
OAI22X1TS U2717 ( .A0(n1821), .A1(n1818), .B0(n1819), .B1(n1764), .Y(n1837)
);
CMPR32X2TS U2718 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[10]), .C(n1765),
.CO(n1780), .S(n1815) );
INVX2TS U2719 ( .A(n1825), .Y(n1812) );
AOI22X1TS U2720 ( .A0(DP_OP_502J324_128_4510_n32), .A1(n1812), .B0(n1825),
.B1(n962), .Y(n1766) );
CMPR32X2TS U2721 ( .A(n1769), .B(n1768), .C(n1767), .CO(n1774), .S(n1833) );
CMPR32X2TS U2722 ( .A(DP_OP_502J324_128_4510_n26), .B(
DP_OP_502J324_128_4510_n30), .C(n1770), .CO(n1783), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
CMPR32X2TS U2723 ( .A(DP_OP_502J324_128_4510_n31), .B(
DP_OP_502J324_128_4510_n34), .C(n1771), .CO(n1770), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
CMPR32X2TS U2724 ( .A(DP_OP_502J324_128_4510_n35), .B(
DP_OP_502J324_128_4510_n37), .C(n1772), .CO(n1771), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
CMPR32X2TS U2725 ( .A(DP_OP_502J324_128_4510_n38), .B(n1774), .C(n1773),
.CO(n1772), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
CMPR32X2TS U2726 ( .A(n1777), .B(n1776), .C(n1775), .CO(n1831), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
ADDHXLTS U2727 ( .A(n1779), .B(n1778), .CO(n1775), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1) );
CMPR32X2TS U2728 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[11]), .C(n1780),
.CO(n1823), .S(n1825) );
INVX2TS U2729 ( .A(n1823), .Y(n1822) );
AOI22X1TS U2730 ( .A0(n1806), .A1(n1822), .B0(n1823), .B1(n1803), .Y(n1798)
);
OAI22X1TS U2731 ( .A0(n1811), .A1(n1803), .B0(n1809), .B1(n1798), .Y(n1790)
);
INVX2TS U2732 ( .A(n1790), .Y(n1785) );
NAND2X2TS U2733 ( .A(n1806), .B(n1782), .Y(n1797) );
OAI22X1TS U2734 ( .A0(n1812), .A1(n1826), .B0(n1816), .B1(n1797), .Y(n1784)
);
CMPR32X2TS U2735 ( .A(DP_OP_502J324_128_4510_n23), .B(
DP_OP_502J324_128_4510_n25), .C(n1783), .CO(n1787), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
CMPR32X2TS U2736 ( .A(n1785), .B(n1784), .C(DP_OP_502J324_128_4510_n21),
.CO(n1843), .S(n1788) );
OAI22X1TS U2737 ( .A0(n1822), .A1(n1826), .B0(n1812), .B1(n1797), .Y(n1791)
);
CMPR32X2TS U2738 ( .A(n1788), .B(DP_OP_502J324_128_4510_n22), .C(n1787),
.CO(n1841), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
CMPR32X2TS U2739 ( .A(n1791), .B(n1790), .C(n1789), .CO(n1793), .S(n1842) );
OAI31X1TS U2740 ( .A0(n1822), .A1(n1793), .A2(n1797), .B0(n1792), .Y(n1794)
);
XNOR2X1TS U2741 ( .A(n1795), .B(n1794), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
OAI22X1TS U2742 ( .A0(n1816), .A1(n1826), .B0(n1801), .B1(n1797), .Y(
DP_OP_502J324_128_4510_n53) );
OAI22X1TS U2743 ( .A0(n1801), .A1(n1826), .B0(n1805), .B1(n1797), .Y(
DP_OP_502J324_128_4510_n54) );
OAI22X1TS U2744 ( .A0(n1805), .A1(n1826), .B0(n1796), .B1(n1797), .Y(
DP_OP_502J324_128_4510_n55) );
OAI22X1TS U2745 ( .A0(n1827), .A1(n1797), .B0(n1796), .B1(n1826), .Y(
DP_OP_502J324_128_4510_n56) );
AOI22X1TS U2746 ( .A0(n1806), .A1(n1812), .B0(n1825), .B1(n1803), .Y(n1799)
);
OAI22X1TS U2747 ( .A0(n1811), .A1(n1798), .B0(n1809), .B1(n1799), .Y(
DP_OP_502J324_128_4510_n59) );
AOI22X1TS U2748 ( .A0(n1806), .A1(n1816), .B0(n1815), .B1(n1803), .Y(n1802)
);
OAI22X1TS U2749 ( .A0(n1811), .A1(n1799), .B0(n1809), .B1(n1802), .Y(
DP_OP_502J324_128_4510_n60) );
AOI22X1TS U2750 ( .A0(n1806), .A1(n1801), .B0(n1800), .B1(n1803), .Y(n1807)
);
OAI22X1TS U2751 ( .A0(n1811), .A1(n1802), .B0(n1809), .B1(n1807), .Y(
DP_OP_502J324_128_4510_n61) );
AOI22X1TS U2752 ( .A0(n1806), .A1(n1805), .B0(n1804), .B1(n1803), .Y(n1810)
);
OAI22X1TS U2753 ( .A0(n1811), .A1(n1807), .B0(n1809), .B1(n1810), .Y(
DP_OP_502J324_128_4510_n62) );
OAI22X1TS U2754 ( .A0(n1811), .A1(n1810), .B0(n1809), .B1(n1808), .Y(
DP_OP_502J324_128_4510_n63) );
AOI22X1TS U2755 ( .A0(n1828), .A1(n1822), .B0(n1823), .B1(n1814), .Y(n1813)
);
OAI22X1TS U2756 ( .A0(n1814), .A1(n1821), .B0(n1819), .B1(n1813), .Y(
DP_OP_502J324_128_4510_n67) );
AOI22X1TS U2757 ( .A0(n1828), .A1(n1812), .B0(n1825), .B1(n1814), .Y(n1817)
);
OAI22X1TS U2758 ( .A0(n1821), .A1(n1813), .B0(n1819), .B1(n1817), .Y(
DP_OP_502J324_128_4510_n68) );
AOI22X1TS U2759 ( .A0(n1828), .A1(n1816), .B0(n1815), .B1(n1814), .Y(n1820)
);
OAI22X1TS U2760 ( .A0(n1821), .A1(n1817), .B0(n1819), .B1(n1820), .Y(
DP_OP_502J324_128_4510_n69) );
OAI22X1TS U2761 ( .A0(n1821), .A1(n1820), .B0(n1819), .B1(n1818), .Y(
DP_OP_502J324_128_4510_n70) );
AOI21X1TS U2762 ( .A0(n1823), .A1(n1750), .B0(n962), .Y(
DP_OP_502J324_128_4510_n75) );
AOI22X1TS U2763 ( .A0(n1823), .A1(n962), .B0(DP_OP_502J324_128_4510_n32),
.B1(n1822), .Y(n1824) );
NOR2X1TS U2764 ( .A(n1827), .B(n1826), .Y(DP_OP_502J324_128_4510_n57) );
OAI21X1TS U2765 ( .A0(n962), .A1(n1829), .B0(n1828), .Y(
DP_OP_502J324_128_4510_n66) );
CMPR32X2TS U2766 ( .A(n1832), .B(n1831), .C(n1830), .CO(n1838), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
CMPR32X2TS U2767 ( .A(n1835), .B(n1834), .C(n1833), .CO(n1773), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
ADDHXLTS U2768 ( .A(n1837), .B(n1836), .CO(DP_OP_502J324_128_4510_n41), .S(
n1834) );
CMPR32X2TS U2769 ( .A(n1840), .B(n1839), .C(n1838), .CO(n1835), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
CMPR32X2TS U2770 ( .A(n1843), .B(n1842), .C(n1841), .CO(n1795), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
INVX2TS U2771 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(n1849)
);
INVX2TS U2772 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .Y(n1848) );
CMPR32X2TS U2773 ( .A(DP_OP_496J324_122_3236_n68), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .C(
DP_OP_496J324_122_3236_n17), .CO(n2533), .S(n1286) );
INVX2TS U2774 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2532) );
XOR2X1TS U2775 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(n2531)
);
INVX2TS U2776 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(n1860)
);
INVX2TS U2777 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .Y(n1859) );
INVX2TS U2778 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(n1845)
);
INVX2TS U2779 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .Y(n1844) );
CMPR32X2TS U2780 ( .A(n1845), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]), .C(
n1844), .CO(n1862), .S(n1855) );
INVX2TS U2781 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(n1847)
);
INVX2TS U2782 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .Y(n1846) );
CMPR32X2TS U2783 ( .A(n1847), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]), .C(
n1846), .CO(n1854), .S(n1858) );
CMPR32X2TS U2784 ( .A(n1852), .B(n1851), .C(n1850), .CO(n1856), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
CMPR32X2TS U2785 ( .A(n1858), .B(n1857), .C(n1856), .CO(n1853), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
NAND2X1TS U2786 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n3147), .Y(n2158) );
NOR2X2TS U2787 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n2158), .Y(n2967) );
NAND2X1TS U2788 ( .A(n2967), .B(n3165), .Y(n2519) );
INVX2TS U2789 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(n1870)
);
CMPR32X2TS U2790 ( .A(n1860), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]), .C(
n1859), .CO(n1872), .S(n1863) );
CMPR32X2TS U2791 ( .A(n1863), .B(n1862), .C(n1861), .CO(n1871), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
INVX4TS U2792 ( .A(n2406), .Y(n3451) );
NAND2X2TS U2793 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n2511) );
OR4X2TS U2794 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n1864) );
OR4X2TS U2795 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n1864), .Y(n1865) );
AND4X1TS U2796 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n1866) );
AND4X1TS U2797 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n1866), .Y(n1867) );
CMPR32X2TS U2798 ( .A(n1870), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]), .C(
n1869), .CO(n1877), .S(n1873) );
CMPR32X2TS U2799 ( .A(n1873), .B(n1872), .C(n1871), .CO(n1876), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
CMPR32X2TS U2800 ( .A(n1875), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]), .C(
n1874), .CO(n1912), .S(n1878) );
CMPR32X2TS U2801 ( .A(n1878), .B(n1877), .C(n1876), .CO(n1911), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
NOR2XLTS U2802 ( .A(n3165), .B(FPMULT_P_Sgf[47]), .Y(n1879) );
AOI22X1TS U2803 ( .A0(n1879), .A1(n2967), .B0(n3165), .B1(n3344), .Y(n1880)
);
OAI21XLTS U2804 ( .A0(n2519), .A1(FPMULT_zero_flag), .B0(n1880), .Y(
FPMULT_FS_Module_state_next[0]) );
OR4X2TS U2805 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n1881) );
NOR2XLTS U2806 ( .A(n3236), .B(n3150), .Y(intadd_1104_A_8_) );
INVX2TS U2807 ( .A(Data_2[19]), .Y(n1884) );
NOR3X1TS U2808 ( .A(FPSENCOS_cont_var_out[1]), .B(n3090), .C(n3155), .Y(
n1885) );
NAND2X1TS U2809 ( .A(FPSENCOS_cont_var_out[1]), .B(n3155), .Y(n1882) );
AOI22X1TS U2810 ( .A0(n3093), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n3030),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1883) );
NAND2X1TS U2811 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n2979) );
NOR2X1TS U2812 ( .A(n3090), .B(n2979), .Y(n3031) );
NAND2X1TS U2813 ( .A(n2998), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n1888) );
OAI211XLTS U2814 ( .A0(operation[1]), .A1(n1884), .B0(n1883), .C0(n1888),
.Y(add_subt_data2[19]) );
INVX2TS U2815 ( .A(Data_2[18]), .Y(n1887) );
AOI22X1TS U2816 ( .A0(n3084), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n3066),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1886) );
NAND2X1TS U2817 ( .A(n2998), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n1895) );
OAI211XLTS U2818 ( .A0(operation[1]), .A1(n1887), .B0(n1886), .C0(n1895),
.Y(add_subt_data2[18]) );
INVX2TS U2819 ( .A(Data_2[22]), .Y(n1890) );
AOI22X1TS U2820 ( .A0(n3084), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n3066),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1889) );
OAI211XLTS U2821 ( .A0(operation[1]), .A1(n1890), .B0(n1889), .C0(n1888),
.Y(add_subt_data2[22]) );
INVX2TS U2822 ( .A(Data_2[16]), .Y(n1892) );
AOI22X1TS U2823 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n3030),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1891) );
NAND2X1TS U2824 ( .A(n2998), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n1906) );
OAI211XLTS U2825 ( .A0(operation[1]), .A1(n1892), .B0(n1891), .C0(n1906),
.Y(add_subt_data2[16]) );
INVX2TS U2826 ( .A(Data_2[14]), .Y(n1894) );
AOI22X1TS U2827 ( .A0(n3084), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n923),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1893) );
NAND2X1TS U2828 ( .A(n2998), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n1903) );
OAI211XLTS U2829 ( .A0(n932), .A1(n1894), .B0(n1893), .C0(n1903), .Y(
add_subt_data2[14]) );
INVX2TS U2830 ( .A(Data_2[13]), .Y(n1897) );
AOI22X1TS U2831 ( .A0(n3070), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n3066),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1896) );
OAI211XLTS U2832 ( .A0(operation[1]), .A1(n1897), .B0(n1896), .C0(n1895),
.Y(add_subt_data2[13]) );
INVX2TS U2833 ( .A(Data_2[7]), .Y(n1899) );
AOI22X1TS U2834 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n3030),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1898) );
NAND2X1TS U2835 ( .A(n2998), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n1900) );
OAI211XLTS U2836 ( .A0(operation[1]), .A1(n1899), .B0(n1898), .C0(n1900),
.Y(add_subt_data2[7]) );
INVX2TS U2837 ( .A(Data_2[11]), .Y(n1902) );
AOI22X1TS U2838 ( .A0(n3070), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n923),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1901) );
OAI211XLTS U2839 ( .A0(n932), .A1(n1902), .B0(n1901), .C0(n1900), .Y(
add_subt_data2[11]) );
INVX2TS U2840 ( .A(Data_2[5]), .Y(n1905) );
AOI22X1TS U2841 ( .A0(n3070), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n3066),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1904) );
OAI211XLTS U2842 ( .A0(operation[1]), .A1(n1905), .B0(n1904), .C0(n1903),
.Y(add_subt_data2[5]) );
INVX2TS U2843 ( .A(Data_2[3]), .Y(n1908) );
AOI22X1TS U2844 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n3030),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1907) );
OAI211XLTS U2845 ( .A0(operation[1]), .A1(n1908), .B0(n1907), .C0(n1906),
.Y(add_subt_data2[3]) );
INVX2TS U2846 ( .A(FPMULT_Sgf_normalized_result[23]), .Y(n2686) );
INVX2TS U2847 ( .A(FPMULT_Sgf_normalized_result[21]), .Y(n2689) );
INVX2TS U2848 ( .A(FPMULT_Sgf_normalized_result[19]), .Y(n2692) );
INVX2TS U2849 ( .A(FPMULT_Sgf_normalized_result[17]), .Y(n2695) );
INVX2TS U2850 ( .A(FPMULT_Sgf_normalized_result[15]), .Y(n2698) );
NOR3X2TS U2851 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n2715) );
NOR2X2TS U2852 ( .A(n2714), .B(n2715), .Y(n2718) );
NOR2X2TS U2853 ( .A(FPMULT_Sgf_normalized_result[4]), .B(n2718), .Y(n2717)
);
NOR2X2TS U2854 ( .A(n2713), .B(n2717), .Y(n2712) );
NAND2X1TS U2855 ( .A(FPMULT_Sgf_normalized_result[6]), .B(n2712), .Y(n2711)
);
NOR2X2TS U2856 ( .A(n2710), .B(n2711), .Y(n2709) );
NAND2X1TS U2857 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n2709), .Y(n2708)
);
NOR2X2TS U2858 ( .A(n2707), .B(n2708), .Y(n2706) );
NAND2X1TS U2859 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n2706), .Y(n2705)
);
NOR2X2TS U2860 ( .A(n2704), .B(n2705), .Y(n2703) );
NAND2X1TS U2861 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n2703), .Y(n2702)
);
NOR2X2TS U2862 ( .A(n2701), .B(n2702), .Y(n2700) );
NAND2X1TS U2863 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n2700), .Y(n2699)
);
NOR2X2TS U2864 ( .A(n2698), .B(n2699), .Y(n2697) );
NAND2X1TS U2865 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n2697), .Y(n2696)
);
NOR2X2TS U2866 ( .A(n2695), .B(n2696), .Y(n2694) );
NAND2X1TS U2867 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n2694), .Y(n2693)
);
NOR2X2TS U2868 ( .A(n2692), .B(n2693), .Y(n2691) );
NAND2X1TS U2869 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n2691), .Y(n2690)
);
NOR2X2TS U2870 ( .A(n2689), .B(n2690), .Y(n2688) );
NAND2X1TS U2871 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n2688), .Y(n2687)
);
NOR2X1TS U2872 ( .A(n2686), .B(n2687), .Y(FPMULT_Adder_M_result_A_adder[24])
);
CMPR32X2TS U2873 ( .A(n1910), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]), .C(
n1909), .CO(n1955), .S(n1913) );
CMPR32X2TS U2874 ( .A(n1913), .B(n1912), .C(n1911), .CO(n1954), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
INVX2TS U2875 ( .A(Data_2[27]), .Y(n1915) );
AOI22X1TS U2876 ( .A0(n3093), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n3030),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n1914) );
NAND2X1TS U2877 ( .A(n2998), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n1920) );
OAI211XLTS U2878 ( .A0(operation[1]), .A1(n1915), .B0(n1914), .C0(n1920),
.Y(add_subt_data2[27]) );
INVX2TS U2879 ( .A(Data_2[28]), .Y(n1917) );
AOI22X1TS U2880 ( .A0(n3093), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n3066),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1916) );
OAI211XLTS U2881 ( .A0(operation[1]), .A1(n1917), .B0(n1916), .C0(n1920),
.Y(add_subt_data2[28]) );
INVX2TS U2882 ( .A(Data_2[20]), .Y(n1919) );
AOI22X1TS U2883 ( .A0(n3070), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n3066),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1918) );
NAND2X1TS U2884 ( .A(n2998), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n1925) );
OAI211XLTS U2885 ( .A0(n932), .A1(n1919), .B0(n1918), .C0(n1925), .Y(
add_subt_data2[20]) );
INVX2TS U2886 ( .A(Data_2[29]), .Y(n1922) );
AOI22X1TS U2887 ( .A0(n3093), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n923),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n1921) );
OAI211XLTS U2888 ( .A0(operation[1]), .A1(n1922), .B0(n1921), .C0(n1920),
.Y(add_subt_data2[29]) );
INVX2TS U2889 ( .A(Data_2[17]), .Y(n1924) );
AOI22X1TS U2890 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n923),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1923) );
OAI211XLTS U2891 ( .A0(n932), .A1(n1924), .B0(n1923), .C0(n1925), .Y(
add_subt_data2[17]) );
INVX2TS U2892 ( .A(Data_2[15]), .Y(n1927) );
AOI22X1TS U2893 ( .A0(n3084), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n3030),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1926) );
OAI211XLTS U2894 ( .A0(operation[1]), .A1(n1927), .B0(n1926), .C0(n1925),
.Y(add_subt_data2[15]) );
NOR2X1TS U2895 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .Y(n2033) );
NOR3X1TS U2896 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n2242) );
NAND2X1TS U2897 ( .A(n2033), .B(n2242), .Y(n2947) );
NOR2X1TS U2898 ( .A(FPADDSUB_Raw_mant_NRM_SWR[18]), .B(n1932), .Y(n2497) );
NAND2X1TS U2899 ( .A(n2497), .B(n2494), .Y(n1933) );
INVX2TS U2900 ( .A(n1928), .Y(n2500) );
NOR2X1TS U2901 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n2500), .Y(n1948) );
OAI21X1TS U2902 ( .A0(n1932), .A1(n3247), .B0(n2498), .Y(n1947) );
NOR2X2TS U2903 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n1939), .Y(n2507) );
AOI21X1TS U2904 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n3233), .B0(n959),
.Y(n1930) );
NOR3X2TS U2905 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n958), .C(n2493), .Y(
n2490) );
NAND2X1TS U2906 ( .A(n2490), .B(n3224), .Y(n2510) );
OAI22X1TS U2907 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n2502), .B0(n1930),
.B1(n2510), .Y(n1931) );
AOI211X1TS U2908 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n1948), .B0(n1947), .C0(n1931), .Y(n2492) );
AOI22X1TS U2909 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n1934), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n2507), .Y(n1937) );
NAND4X1TS U2910 ( .A(n2492), .B(n1938), .C(n1937), .D(n1936), .Y(
FPADDSUB_LZD_raw_out_EWR[0]) );
OA21XLTS U2911 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(n959), .B0(n2490),
.Y(n1941) );
OAI31X1TS U2912 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n1941), .A2(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n1940), .Y(n2509) );
NOR2X1TS U2913 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n1943) );
AOI32X1TS U2914 ( .A0(n1944), .A1(n1943), .A2(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B0(n1942), .B1(n1943), .Y(n1951) );
NAND4X1TS U2915 ( .A(n2509), .B(n1951), .C(n1950), .D(n1949), .Y(
FPADDSUB_LZD_raw_out_EWR[1]) );
CMPR32X2TS U2916 ( .A(n1953), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]), .C(
n1952), .CO(n2392), .S(n1956) );
CMPR32X2TS U2917 ( .A(n1956), .B(n1955), .C(n1954), .CO(n2391), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
NOR2X1TS U2918 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .Y(n2858) );
NAND2X1TS U2919 ( .A(n3363), .B(n2858), .Y(n2950) );
OR2X1TS U2920 ( .A(n2951), .B(FPMULT_exp_oper_result[0]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
INVX2TS U2921 ( .A(n3098), .Y(n863) );
NAND2X1TS U2922 ( .A(n3146), .B(FPSENCOS_cont_iter_out[3]), .Y(n2154) );
INVX2TS U2923 ( .A(n2154), .Y(n1965) );
NAND2X1TS U2924 ( .A(n863), .B(FPSENCOS_cont_iter_out[0]), .Y(n3103) );
INVX2TS U2925 ( .A(n3103), .Y(n3102) );
NOR2X1TS U2926 ( .A(n1965), .B(n3102), .Y(n3099) );
OAI211X1TS U2927 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3175), .B0(n3146),
.C0(n3242), .Y(n3101) );
OAI21XLTS U2928 ( .A0(n3099), .A1(n3242), .B0(n3101), .Y(n852) );
INVX2TS U2929 ( .A(rst), .Y(n2149) );
OR2X1TS U2930 ( .A(n2949), .B(FPMULT_exp_oper_result[7]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
NAND2X1TS U2931 ( .A(n3097), .B(n3146), .Y(n2153) );
OAI31X1TS U2932 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[1]), .A2(n3146), .B0(n2153), .Y(n854) );
OAI31X4TS U2933 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n3175), .B0(n863), .Y(n3100) );
OAI21XLTS U2934 ( .A0(n3098), .A1(n3242), .B0(n3100), .Y(n857) );
OAI21XLTS U2935 ( .A0(n3242), .A1(n3100), .B0(n2154), .Y(n858) );
MXI2X1TS U2936 ( .A(n3461), .B(r_mode[1]), .S0(r_mode[0]), .Y(n1957) );
AOI31X1TS U2937 ( .A0(n3464), .A1(n3463), .A2(n3462), .B0(n1958), .Y(n2190)
);
INVX2TS U2938 ( .A(n2190), .Y(n1959) );
OAI31X1TS U2939 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(n2969), .A2(n1959),
.B0(n3319), .Y(n825) );
NOR2X1TS U2940 ( .A(n3245), .B(n3179), .Y(intadd_1106_CI) );
CLKBUFX2TS U2941 ( .A(n3436), .Y(n3433) );
BUFX3TS U2942 ( .A(n2149), .Y(n3435) );
BUFX4TS U2943 ( .A(n3435), .Y(n3406) );
BUFX4TS U2944 ( .A(n3436), .Y(n3427) );
BUFX4TS U2945 ( .A(n2149), .Y(n3429) );
BUFX4TS U2946 ( .A(n3436), .Y(n3430) );
BUFX3TS U2947 ( .A(n2149), .Y(n3437) );
BUFX3TS U2948 ( .A(n3437), .Y(n3432) );
BUFX4TS U2949 ( .A(n3432), .Y(n3431) );
BUFX3TS U2950 ( .A(n3436), .Y(n3422) );
BUFX4TS U2951 ( .A(n3435), .Y(n3407) );
BUFX4TS U2952 ( .A(n3435), .Y(n3408) );
BUFX4TS U2953 ( .A(n3435), .Y(n3409) );
BUFX4TS U2954 ( .A(n3436), .Y(n3428) );
BUFX4TS U2955 ( .A(n3436), .Y(n3425) );
BUFX4TS U2956 ( .A(n3436), .Y(n3426) );
BUFX3TS U2957 ( .A(n3386), .Y(n3404) );
BUFX3TS U2958 ( .A(n3381), .Y(n3379) );
BUFX4TS U2959 ( .A(n3435), .Y(n3410) );
BUFX4TS U2960 ( .A(n3436), .Y(n3421) );
BUFX3TS U2961 ( .A(n3436), .Y(n3423) );
NAND3XLTS U2962 ( .A(n3147), .B(n2966), .C(n3165), .Y(n1961) );
CLKBUFX2TS U2963 ( .A(n2151), .Y(n1962) );
BUFX3TS U2964 ( .A(n3383), .Y(n3396) );
BUFX3TS U2965 ( .A(n1963), .Y(n3377) );
BUFX3TS U2966 ( .A(n3436), .Y(n3424) );
BUFX3TS U2967 ( .A(n1964), .Y(n3394) );
BUFX3TS U2968 ( .A(n3384), .Y(n3395) );
BUFX3TS U2969 ( .A(n3381), .Y(n3400) );
BUFX3TS U2970 ( .A(n1964), .Y(n3391) );
BUFX3TS U2971 ( .A(n3386), .Y(n3392) );
BUFX3TS U2972 ( .A(n3381), .Y(n3393) );
BUFX3TS U2973 ( .A(n3384), .Y(n3388) );
BUFX3TS U2974 ( .A(n3382), .Y(n3398) );
BUFX3TS U2975 ( .A(n3383), .Y(n3380) );
BUFX3TS U2976 ( .A(n3382), .Y(n3376) );
OR2X1TS U2977 ( .A(n2949), .B(FPMULT_exp_oper_result[3]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
OR2X1TS U2978 ( .A(n2951), .B(FPMULT_exp_oper_result[1]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
OR2X1TS U2979 ( .A(n2949), .B(FPMULT_exp_oper_result[2]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
OR2X1TS U2980 ( .A(n2951), .B(FPMULT_exp_oper_result[5]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
OR2X1TS U2981 ( .A(n2949), .B(FPMULT_exp_oper_result[6]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
OR2X1TS U2982 ( .A(n2951), .B(FPMULT_exp_oper_result[4]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
NAND2X1TS U2983 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3317),
.Y(n2296) );
OAI211XLTS U2984 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n3317), .B0(n2296), .C0(n2857), .Y(n873) );
NOR2X2TS U2985 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n3253), .Y(n2968) );
INVX2TS U2986 ( .A(n2968), .Y(n2156) );
NOR3X2TS U2987 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n3165), .C(n2156),
.Y(n3474) );
OAI22X1TS U2988 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(n2158), .B0(n2157),
.B1(n3343), .Y(FPMULT_FSM_load_second_step) );
OR2X1TS U2989 ( .A(n3474), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
INVX2TS U2990 ( .A(n2971), .Y(n2981) );
NOR2BX1TS U2991 ( .AN(FPSENCOS_enab_d_ff4_Zn), .B(n2981), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
NAND2X1TS U2992 ( .A(n2178), .B(n3103), .Y(n849) );
NOR2X1TS U2993 ( .A(n3214), .B(n3148), .Y(mult_x_309_n33) );
NOR2X1TS U2994 ( .A(n3351), .B(FPADDSUB_intDX_EWSW[25]), .Y(n2025) );
AOI22X1TS U2995 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n3351), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n1966), .Y(n1970) );
OAI21X1TS U2996 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n3355), .B0(n1967), .Y(
n2026) );
NOR2X1TS U2997 ( .A(n3260), .B(FPADDSUB_intDX_EWSW[30]), .Y(n1974) );
NOR2X1TS U2998 ( .A(n3185), .B(FPADDSUB_intDX_EWSW[29]), .Y(n1971) );
AOI211X1TS U2999 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n1972), .B0(n1974),
.C0(n1971), .Y(n2024) );
NOR3X1TS U3000 ( .A(n1972), .B(n1971), .C(FPADDSUB_intDY_EWSW[28]), .Y(n1973) );
AOI2BB2X1TS U3001 ( .B0(n1976), .B1(n2024), .A0N(n1975), .A1N(n1974), .Y(
n2030) );
NOR2X1TS U3002 ( .A(n3350), .B(FPADDSUB_intDX_EWSW[17]), .Y(n2012) );
NOR2X1TS U3003 ( .A(n3348), .B(FPADDSUB_intDX_EWSW[11]), .Y(n1991) );
AOI21X1TS U3004 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3299), .B0(n1991), .Y(
n1996) );
OAI2BB1X1TS U3005 ( .A0N(n3318), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n1977) );
OAI22X1TS U3006 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n1977), .B0(n3318), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n1988) );
OAI2BB1X1TS U3007 ( .A0N(n3191), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n1978) );
OAI22X1TS U3008 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n1978), .B0(n3191), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n1987) );
OAI2BB2XLTS U3009 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n1979), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n3354), .Y(n1981) );
NAND2BXLTS U3010 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n1980) );
OAI21XLTS U3011 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n3356), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n1982) );
AOI2BB2XLTS U3012 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n3356), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n1982), .Y(n1983) );
AOI222X1TS U3013 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3195), .B0(n1984), .B1(
n1983), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n3318), .Y(n1986) );
AOI22X1TS U3014 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3191), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n3306), .Y(n1985) );
OAI32X1TS U3015 ( .A0(n1988), .A1(n1987), .A2(n1986), .B0(n1985), .B1(n1987),
.Y(n2006) );
OA22X1TS U3016 ( .A0(n3203), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n3349), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n2003) );
OAI2BB2XLTS U3017 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n1990), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n3336), .Y(n2002) );
AOI22X1TS U3018 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n3348), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n1992), .Y(n1998) );
AOI21X1TS U3019 ( .A0(n1995), .A1(n1994), .B0(n2005), .Y(n1997) );
OAI2BB2XLTS U3020 ( .B0(n1998), .B1(n2005), .A0N(n1997), .A1N(n1996), .Y(
n2001) );
OAI2BB2XLTS U3021 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n1999), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n3349), .Y(n2000) );
AOI211X1TS U3022 ( .A0(n2003), .A1(n2002), .B0(n2001), .C0(n2000), .Y(n2004)
);
OAI31X1TS U3023 ( .A0(n2007), .A1(n2006), .A2(n2005), .B0(n2004), .Y(n2010)
);
OA22X1TS U3024 ( .A0(n3207), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n3358), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n2778) );
OAI21X1TS U3025 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n3353), .B0(n2014), .Y(
n2018) );
AOI211X1TS U3026 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3316), .B0(n2017),
.C0(n2018), .Y(n2009) );
OAI2BB2XLTS U3027 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n2011), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n3341), .Y(n2022) );
AOI22X1TS U3028 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n3350), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n2013), .Y(n2016) );
AOI32X1TS U3029 ( .A0(n3353), .A1(n2014), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n3205), .Y(n2015) );
OAI32X1TS U3030 ( .A0(n2018), .A1(n2017), .A2(n2016), .B0(n2015), .B1(n2017),
.Y(n2021) );
OAI2BB2XLTS U3031 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n2019), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n3358), .Y(n2020) );
AOI211X1TS U3032 ( .A0(n2778), .A1(n2022), .B0(n2021), .C0(n2020), .Y(n2028)
);
NAND4BBX1TS U3033 ( .AN(n2026), .BN(n2025), .C(n2024), .D(n2023), .Y(n2027)
);
AOI32X1TS U3034 ( .A0(n2030), .A1(n2029), .A2(n2028), .B0(n2027), .B1(n2030),
.Y(n2031) );
INVX2TS U3035 ( .A(n2031), .Y(n2933) );
BUFX3TS U3036 ( .A(n2933), .Y(n2938) );
BUFX3TS U3037 ( .A(n2933), .Y(n2941) );
OAI2BB2XLTS U3038 ( .B0(n2938), .B1(n3310), .A0N(n2941), .A1N(
FPADDSUB_intDY_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
NOR2XLTS U3039 ( .A(n3156), .B(n3179), .Y(n2032) );
NOR2X1TS U3040 ( .A(n3231), .B(n973), .Y(n2658) );
NAND2X1TS U3041 ( .A(n2032), .B(n2658), .Y(n3454) );
NOR2X1TS U3042 ( .A(n3156), .B(n3232), .Y(n2659) );
NAND2X1TS U3043 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MY[2]), .Y(n2683) );
NAND2X1TS U3044 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[1]), .Y(n2152) );
AO21XLTS U3045 ( .A0(n2635), .A1(n2659), .B0(n2681), .Y(intadd_1106_B_2_) );
NOR2X1TS U3046 ( .A(n3157), .B(n3172), .Y(intadd_1105_CI) );
OR2X1TS U3047 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n2105), .Y(
n2513) );
NAND2BX2TS U3048 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n2268) );
NAND2X1TS U3049 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n3297), .Y(n2051)
);
OAI22X1TS U3050 ( .A0(n2268), .A1(n3327), .B0(n2051), .B1(n3204), .Y(n2035)
);
NOR2BX2TS U3051 ( .AN(FPADDSUB_bit_shift_SHT2), .B(n2034), .Y(n2074) );
AOI22X1TS U3052 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n951),
.B1(FPADDSUB_Data_array_SWR[43]), .Y(n2040) );
NOR2BX1TS U3053 ( .AN(n2034), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n2037) );
AOI22X1TS U3054 ( .A0(n947), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n2038),
.B1(FPADDSUB_Data_array_SWR[47]), .Y(n2039) );
NAND2X1TS U3055 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n2057) );
AOI21X1TS U3056 ( .A0(n2281), .A1(n2079), .B0(n2041), .Y(n2042) );
OAI21X1TS U3057 ( .A0(n2181), .A1(n2036), .B0(n2042), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
CLKAND2X2TS U3058 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
INVX2TS U3059 ( .A(n2057), .Y(n2086) );
OR2X1TS U3060 ( .A(n2053), .B(n2086), .Y(n2050) );
AO22XLTS U3061 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n946),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n2044) );
AOI211X1TS U3062 ( .A0(n951), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n2050),
.C0(n2044), .Y(n2064) );
AOI22X1TS U3063 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n947),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n2045) );
AOI22X1TS U3064 ( .A0(n926), .A1(n2064), .B0(n2065), .B1(n2281), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U3065 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[10]), .Y(
FPADDSUB_formatted_number_W[8]) );
AOI22X1TS U3066 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n947),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n2047) );
AO22XLTS U3067 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n948), .B0(n946),
.B1(FPADDSUB_Data_array_SWR[40]), .Y(n2049) );
AOI211X1TS U3068 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n951), .B0(n2050),
.C0(n2049), .Y(n2061) );
AOI22X1TS U3069 ( .A0(n926), .A1(n2060), .B0(n2061), .B1(n925), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U3070 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[14]), .Y(
FPADDSUB_formatted_number_W[12]) );
OAI22X1TS U3071 ( .A0(n2268), .A1(n3200), .B0(n2051), .B1(n3323), .Y(n2052)
);
AOI22X1TS U3072 ( .A0(n2038), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n950),
.B1(FPADDSUB_Data_array_SWR[42]), .Y(n2056) );
AOI22X1TS U3073 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n947),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n2055) );
AOI21X1TS U3074 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2062), .B0(n2058), .Y(
n2059) );
OAI21X1TS U3075 ( .A0(n2072), .A1(n2054), .B0(n2059), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
CLKAND2X2TS U3076 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
AOI22X1TS U3077 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2061), .B0(n2060),
.B1(n2281), .Y(FPADDSUB_sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U3078 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[11]), .Y(
FPADDSUB_formatted_number_W[9]) );
AOI21X1TS U3079 ( .A0(n925), .A1(n2062), .B0(n2041), .Y(n2063) );
OAI21X1TS U3080 ( .A0(n2072), .A1(n2036), .B0(n2063), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
CLKAND2X2TS U3081 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
AOI22X1TS U3082 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2065), .B0(n2064),
.B1(n925), .Y(FPADDSUB_sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U3083 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[15]), .Y(
FPADDSUB_formatted_number_W[13]) );
AOI22X1TS U3084 ( .A0(n2038), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n950),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n2068) );
AOI22X1TS U3085 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[32]), .B0(n946),
.B1(FPADDSUB_Data_array_SWR[28]), .Y(n2067) );
OAI211X1TS U3086 ( .A0(n2265), .A1(n3259), .B0(n2068), .C0(n2067), .Y(n2087)
);
AOI21X1TS U3087 ( .A0(n2281), .A1(n2087), .B0(n2041), .Y(n2069) );
OAI21X1TS U3088 ( .A0(n2257), .A1(n2036), .B0(n2069), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
CLKAND2X2TS U3089 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
AOI22X1TS U3090 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[31]), .B0(n947),
.B1(FPADDSUB_Data_array_SWR[27]), .Y(n2071) );
AOI22X1TS U3091 ( .A0(n2038), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n950),
.B1(FPADDSUB_Data_array_SWR[35]), .Y(n2070) );
OAI211X1TS U3092 ( .A0(n2072), .A1(n3259), .B0(n2071), .C0(n2070), .Y(n2183)
);
AOI21X1TS U3093 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2183), .B0(n2058), .Y(
n2073) );
OAI21X1TS U3094 ( .A0(n2185), .A1(n2054), .B0(n2073), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
CLKAND2X2TS U3095 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
AOI22X1TS U3096 ( .A0(n2038), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n950),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n2077) );
AOI22X1TS U3097 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[33]), .B0(n947),
.B1(FPADDSUB_Data_array_SWR[29]), .Y(n2076) );
OAI211X1TS U3098 ( .A0(n2275), .A1(n3259), .B0(n2077), .C0(n2076), .Y(n2089)
);
AOI21X1TS U3099 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2089), .B0(n2058), .Y(
n2078) );
OAI21X1TS U3100 ( .A0(n2261), .A1(n2054), .B0(n2078), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
CLKAND2X2TS U3101 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
AOI21X1TS U3102 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2079), .B0(n2058), .Y(
n2080) );
OAI21X1TS U3103 ( .A0(n2181), .A1(n2054), .B0(n2080), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
CLKAND2X2TS U3104 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
AOI22X1TS U3105 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n946),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n2081) );
AOI211X1TS U3106 ( .A0(n951), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n2086),
.C0(n2082), .Y(n2091) );
AOI22X1TS U3107 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n946),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2083) );
AOI211X1TS U3108 ( .A0(n951), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n2086),
.C0(n2085), .Y(n2092) );
AOI22X1TS U3109 ( .A0(n926), .A1(n2091), .B0(n2092), .B1(n925), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U3110 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[12]), .Y(
FPADDSUB_formatted_number_W[10]) );
AOI21X1TS U3111 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2087), .B0(n2058), .Y(
n2088) );
OAI21X1TS U3112 ( .A0(n2257), .A1(n2054), .B0(n2088), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
CLKAND2X2TS U3113 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
AOI21X1TS U3114 ( .A0(n2281), .A1(n2089), .B0(n2041), .Y(n2090) );
OAI21X1TS U3115 ( .A0(n2036), .A1(n2261), .B0(n2090), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
CLKAND2X2TS U3116 ( .A(n2043), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
AOI22X1TS U3117 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2092), .B0(n2091),
.B1(n2281), .Y(FPADDSUB_sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U3118 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[13]), .Y(
FPADDSUB_formatted_number_W[11]) );
OR2X1TS U3119 ( .A(n2094), .B(intadd_1107_n1), .Y(n2093) );
OAI2BB1X1TS U3120 ( .A0N(intadd_1107_n1), .A1N(n2094), .B0(n2093), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
NOR2XLTS U3121 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n2095) );
OR2X2TS U3122 ( .A(FPMULT_FSM_selector_B[1]), .B(n3250), .Y(n2102) );
OAI21XLTS U3123 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n2095), .B0(n2102), .Y(
n2096) );
XOR2X1TS U3124 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2096), .Y(
DP_OP_234J324_132_4955_n22) );
OAI2BB1X1TS U3125 ( .A0N(FPMULT_Op_MY[24]), .A1N(n3255), .B0(n2102), .Y(
n2097) );
XOR2X1TS U3126 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2097), .Y(
DP_OP_234J324_132_4955_n21) );
OAI2BB1X1TS U3127 ( .A0N(FPMULT_Op_MY[25]), .A1N(n3255), .B0(n2102), .Y(
n2098) );
XOR2X1TS U3128 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2098), .Y(
DP_OP_234J324_132_4955_n20) );
OAI2BB1X1TS U3129 ( .A0N(FPMULT_Op_MY[26]), .A1N(n3255), .B0(n2102), .Y(
n2099) );
XOR2X1TS U3130 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2099), .Y(
DP_OP_234J324_132_4955_n19) );
OAI2BB1X1TS U3131 ( .A0N(FPMULT_Op_MY[27]), .A1N(n3255), .B0(n2102), .Y(
n2100) );
XOR2X1TS U3132 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2100), .Y(
DP_OP_234J324_132_4955_n18) );
OAI2BB1X1TS U3133 ( .A0N(FPMULT_Op_MY[28]), .A1N(n3255), .B0(n2102), .Y(
n2101) );
XOR2X1TS U3134 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2101), .Y(
DP_OP_234J324_132_4955_n17) );
OAI2BB1X1TS U3135 ( .A0N(FPMULT_Op_MY[29]), .A1N(n3255), .B0(n2102), .Y(
n2103) );
XOR2X1TS U3136 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2103), .Y(
DP_OP_234J324_132_4955_n16) );
NOR3BX1TS U3137 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n2104) );
XOR2X1TS U3138 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2104), .Y(
DP_OP_234J324_132_4955_n15) );
INVX2TS U3139 ( .A(begin_operation), .Y(n2974) );
BUFX4TS U3140 ( .A(n3090), .Y(n3010) );
INVX2TS U3141 ( .A(operation[2]), .Y(n3016) );
BUFX3TS U3142 ( .A(n2347), .Y(n2346) );
NAND4BXLTS U3143 ( .AN(n2105), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]),
.C(n3187), .D(n3296), .Y(n2980) );
INVX2TS U3144 ( .A(n2980), .Y(n2978) );
OAI21XLTS U3145 ( .A0(n2978), .A1(n2971), .B0(n932), .Y(n2106) );
OAI21X1TS U3146 ( .A0(n2974), .A1(n2346), .B0(n2106), .Y(n2297) );
OAI21X1TS U3147 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n2297), .B0(n2857), .Y(n2107) );
AFHCONX2TS U3148 ( .A(n2113), .B(n2112), .CI(n2111), .CON(n2137), .S(n2122)
);
AFHCONX2TS U3149 ( .A(n2116), .B(n2115), .CI(n2114), .CON(n2127), .S(n2121)
);
AFHCONX2TS U3150 ( .A(n2119), .B(n2118), .CI(n2117), .CON(n2202), .S(n2120)
);
NOR4X1TS U3151 ( .A(n2123), .B(n2122), .C(n2121), .D(n2120), .Y(n2148) );
AFHCONX2TS U3152 ( .A(n2126), .B(n2125), .CI(n2124), .CON(n2140), .S(n2131)
);
AFHCINX2TS U3153 ( .CIN(n2127), .B(n2128), .A(n2129), .S(n2130), .CO(n2124)
);
NOR3X1TS U3154 ( .A(n2132), .B(n2131), .C(n2130), .Y(n2147) );
AFHCONX2TS U3155 ( .A(n2135), .B(n2134), .CI(n2133), .CON(n2108), .S(n2136)
);
NOR4X1TS U3156 ( .A(n2136), .B(FPMULT_Sgf_operation_Result[5]), .C(
FPMULT_Sgf_operation_Result[3]), .D(FPMULT_Sgf_operation_Result[0]),
.Y(n2146) );
AFHCINX2TS U3157 ( .CIN(n2137), .B(n2138), .A(n2139), .S(n2144), .CO(n2133)
);
AFHCINX2TS U3158 ( .CIN(n2140), .B(n2141), .A(n2142), .S(n2143), .CO(n2111)
);
NOR4X1TS U3159 ( .A(n2144), .B(n2143), .C(FPMULT_Sgf_operation_Result[4]),
.D(FPMULT_Sgf_operation_Result[1]), .Y(n2145) );
AND4X1TS U3160 ( .A(n2148), .B(n2147), .C(n2146), .D(n2145), .Y(n3365) );
BUFX4TS U3161 ( .A(n2149), .Y(n3415) );
BUFX4TS U3162 ( .A(n2149), .Y(n3416) );
BUFX4TS U3163 ( .A(n2149), .Y(n3417) );
BUFX3TS U3164 ( .A(n3434), .Y(n3414) );
BUFX4TS U3165 ( .A(n2149), .Y(n3418) );
BUFX4TS U3166 ( .A(n3434), .Y(n3419) );
BUFX4TS U3167 ( .A(n2149), .Y(n3420) );
BUFX4TS U3168 ( .A(n3434), .Y(n3411) );
BUFX4TS U3169 ( .A(n3434), .Y(n3412) );
BUFX4TS U3170 ( .A(n3434), .Y(n3413) );
BUFX3TS U3171 ( .A(n2150), .Y(n3446) );
BUFX3TS U3172 ( .A(n2150), .Y(n3447) );
BUFX3TS U3173 ( .A(n2150), .Y(n3441) );
BUFX3TS U3174 ( .A(n2150), .Y(n3449) );
BUFX3TS U3175 ( .A(n2150), .Y(n3448) );
BUFX3TS U3176 ( .A(n2150), .Y(n3439) );
BUFX3TS U3177 ( .A(n2150), .Y(n3438) );
BUFX3TS U3178 ( .A(n2151), .Y(n3385) );
BUFX3TS U3179 ( .A(n2150), .Y(n3443) );
BUFX3TS U3180 ( .A(n2151), .Y(n3384) );
BUFX3TS U3181 ( .A(n2151), .Y(n3382) );
BUFX3TS U3182 ( .A(n2151), .Y(n3383) );
NAND2X1TS U3183 ( .A(n3347), .B(n3206), .Y(n2716) );
OAI21XLTS U3184 ( .A0(n3206), .A1(n3347), .B0(n2716), .Y(
FPMULT_Adder_M_result_A_adder[1]) );
NAND2X1TS U3185 ( .A(n3314), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1109_CI) );
OAI21XLTS U3186 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n3314), .B0(
intadd_1109_CI), .Y(FPSENCOS_sh_exp_y[0]) );
NAND2X1TS U3187 ( .A(n3315), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1108_CI) );
OAI21XLTS U3188 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n3315), .B0(
intadd_1108_CI), .Y(FPSENCOS_sh_exp_x[0]) );
NAND2X1TS U3189 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n967), .Y(n2160) );
OAI21XLTS U3190 ( .A0(n3231), .A1(n3179), .B0(n2152), .Y(n3453) );
NOR2XLTS U3191 ( .A(n2692), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
NOR2XLTS U3192 ( .A(n2695), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
NOR2XLTS U3193 ( .A(n2707), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
NOR2XLTS U3194 ( .A(n2704), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
NOR2XLTS U3195 ( .A(n2698), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
NOR2XLTS U3196 ( .A(n2710), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
NOR2XLTS U3197 ( .A(n2713), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
NOR2XLTS U3198 ( .A(n2714), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
NOR2XLTS U3199 ( .A(n3347), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
NOR2XLTS U3200 ( .A(n3206), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
INVX2TS U3201 ( .A(intadd_1110_SUM_0_), .Y(FPADDSUB_Shift_amount_EXP_EW[1])
);
NOR2X1TS U3202 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .Y(n2155) );
NOR2XLTS U3203 ( .A(n3097), .B(n2155), .Y(FPSENCOS_ITER_CONT_N3) );
INVX2TS U3204 ( .A(intadd_1110_SUM_1_), .Y(FPADDSUB_Shift_amount_EXP_EW[2])
);
OAI21XLTS U3205 ( .A0(n3098), .A1(FPSENCOS_cont_iter_out[1]), .B0(n2178),
.Y(n862) );
OAI211XLTS U3206 ( .A0(n2155), .A1(n2154), .B0(n2153), .C0(n2859), .Y(n853)
);
NOR2X1TS U3207 ( .A(n3237), .B(n3167), .Y(mult_x_312_n53) );
NOR3X1TS U3208 ( .A(n3147), .B(n3165), .C(n2156), .Y(
FPMULT_FSM_final_result_load) );
OAI21X1TS U3209 ( .A0(n2158), .A1(n3253), .B0(n2157), .Y(
FPMULT_FSM_barrel_shifter_load) );
NOR2X1TS U3210 ( .A(n3238), .B(n3150), .Y(mult_x_312_n48) );
INVX2TS U3211 ( .A(intadd_1110_SUM_2_), .Y(FPADDSUB_Shift_amount_EXP_EW[3])
);
NOR2X1TS U3212 ( .A(n3236), .B(n3152), .Y(mult_x_312_n58) );
NAND2X1TS U3213 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[18]), .Y(n2159) );
OAI32X1TS U3214 ( .A0(intadd_1107_CI), .A1(n3163), .A2(n3214), .B0(n2159),
.B1(intadd_1107_CI), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1) );
INVX2TS U3215 ( .A(n2160), .Y(intadd_1110_CI) );
NOR2X1TS U3216 ( .A(n3226), .B(n3162), .Y(mult_x_309_n52) );
NAND3XLTS U3217 ( .A(n2967), .B(FPMULT_FS_Module_state_reg[0]), .C(
FPMULT_P_Sgf[47]), .Y(n2685) );
OAI31X1TS U3218 ( .A0(n3474), .A1(FPMULT_FSM_adder_round_norm_load), .A2(
n3255), .B0(n2685), .Y(n830) );
CLKBUFX2TS U3219 ( .A(n3452), .Y(n2924) );
AOI22X1TS U3220 ( .A0(n2920), .A1(n2168), .B0(n2885), .B1(n2924), .Y(n2162)
);
NAND2X1TS U3221 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n3158), .Y(n2167) );
OAI21XLTS U3222 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n3158), .B0(n2167),
.Y(n2161) );
XOR2XLTS U3223 ( .A(n2162), .B(n2161), .Y(FPADDSUB_Raw_mant_SGF[3]) );
NOR2X1TS U3224 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_1108_n1), .Y(n3141) );
OR3X1TS U3225 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_1108_n1), .Y(n3140) );
OAI21XLTS U3226 ( .A0(n3141), .A1(n3360), .B0(n3140), .Y(
FPSENCOS_sh_exp_x[5]) );
NOR2X1TS U3227 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_1109_n1), .Y(n3138) );
OR3X1TS U3228 ( .A(FPSENCOS_d_ff2_Y[27]), .B(FPSENCOS_d_ff2_Y[28]), .C(
intadd_1109_n1), .Y(n3137) );
OAI21XLTS U3229 ( .A0(n3138), .A1(n3359), .B0(n3137), .Y(
FPSENCOS_sh_exp_y[5]) );
NOR2X1TS U3230 ( .A(n3237), .B(n3152), .Y(mult_x_312_n59) );
NAND2X1TS U3231 ( .A(FPSENCOS_cont_iter_out[2]), .B(n3097), .Y(n3096) );
CLKAND2X2TS U3232 ( .A(n3096), .B(n3151), .Y(n855) );
NOR2X1TS U3233 ( .A(n3151), .B(n3096), .Y(n2227) );
OAI21XLTS U3234 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n863), .B0(n3103), .Y(
n847) );
NOR2X1TS U3235 ( .A(n3226), .B(n3149), .Y(mult_x_309_n58) );
NOR4X1TS U3236 ( .A(n2166), .B(n2165), .C(n2164), .D(n2163), .Y(n3369) );
OAI21XLTS U3237 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3100), .B0(n2178),
.Y(n860) );
NOR2X1TS U3238 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n3210), .Y(n2171) );
AOI222X4TS U3239 ( .A0(n3158), .A1(n2885), .B0(n3158), .B1(n3208), .C0(n2885), .C1(n3208), .Y(n2174) );
BUFX3TS U3240 ( .A(n3452), .Y(n2382) );
AOI22X1TS U3241 ( .A0(n2920), .A1(n2172), .B0(n2174), .B1(n2382), .Y(n2170)
);
OAI31X1TS U3242 ( .A0(n2171), .A1(n2170), .A2(n2173), .B0(n2169), .Y(
FPADDSUB_Raw_mant_SGF[4]) );
BUFX3TS U3243 ( .A(n2955), .Y(n2956) );
OR2X1TS U3244 ( .A(FPSENCOS_d_ff_Xn[16]), .B(n2954), .Y(
FPSENCOS_first_mux_X[16]) );
OR2X1TS U3245 ( .A(FPSENCOS_d_ff_Xn[13]), .B(n2954), .Y(
FPSENCOS_first_mux_X[13]) );
OR2X1TS U3246 ( .A(FPSENCOS_d_ff_Xn[27]), .B(n2954), .Y(
FPSENCOS_first_mux_X[27]) );
OR2X1TS U3247 ( .A(FPSENCOS_d_ff_Xn[28]), .B(n2954), .Y(
FPSENCOS_first_mux_X[28]) );
OR2X1TS U3248 ( .A(FPSENCOS_d_ff_Xn[19]), .B(n2954), .Y(
FPSENCOS_first_mux_X[19]) );
OR2X1TS U3249 ( .A(FPSENCOS_d_ff_Xn[20]), .B(n2954), .Y(
FPSENCOS_first_mux_X[20]) );
OR2X1TS U3250 ( .A(FPSENCOS_d_ff_Xn[25]), .B(n2954), .Y(
FPSENCOS_first_mux_X[25]) );
OR2X1TS U3251 ( .A(FPSENCOS_d_ff_Xn[29]), .B(n2954), .Y(
FPSENCOS_first_mux_X[29]) );
OR2X1TS U3252 ( .A(FPSENCOS_d_ff_Xn[14]), .B(n2954), .Y(
FPSENCOS_first_mux_X[14]) );
OR2X1TS U3253 ( .A(FPSENCOS_d_ff_Xn[24]), .B(n2954), .Y(
FPSENCOS_first_mux_X[24]) );
OR2X1TS U3254 ( .A(FPSENCOS_d_ff_Xn[26]), .B(n2954), .Y(
FPSENCOS_first_mux_X[26]) );
NOR2X1TS U3255 ( .A(n3237), .B(n3169), .Y(mult_x_312_n71) );
AOI22X1TS U3256 ( .A0(n2920), .A1(n2191), .B0(n2193), .B1(n2382), .Y(n2176)
);
NAND2X1TS U3257 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n3159), .Y(n2192) );
OAI21XLTS U3258 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n3159), .B0(n2192),
.Y(n2175) );
XOR2XLTS U3259 ( .A(n2176), .B(n2175), .Y(FPADDSUB_Raw_mant_SGF[5]) );
INVX2TS U3260 ( .A(n2955), .Y(n2177) );
OR2X1TS U3261 ( .A(FPSENCOS_d_ff_Xn[5]), .B(n2177), .Y(
FPSENCOS_first_mux_X[5]) );
OR2X1TS U3262 ( .A(FPSENCOS_d_ff_Xn[10]), .B(n2177), .Y(
FPSENCOS_first_mux_X[10]) );
OR2X1TS U3263 ( .A(FPSENCOS_d_ff_Xn[6]), .B(n2177), .Y(
FPSENCOS_first_mux_X[6]) );
OR2X1TS U3264 ( .A(FPSENCOS_d_ff_Xn[12]), .B(n2177), .Y(
FPSENCOS_first_mux_X[12]) );
OR2X1TS U3265 ( .A(FPSENCOS_d_ff_Xn[1]), .B(n2177), .Y(
FPSENCOS_first_mux_X[1]) );
OAI21X1TS U3266 ( .A0(n3098), .A1(n3242), .B0(n2178), .Y(n861) );
NOR2X1TS U3267 ( .A(n3238), .B(n3169), .Y(mult_x_312_n72) );
NOR2X1TS U3268 ( .A(n3228), .B(n3166), .Y(mult_x_309_n65) );
NOR2X1TS U3269 ( .A(n3227), .B(n3168), .Y(mult_x_312_n67) );
NOR2X1TS U3270 ( .A(n3237), .B(n3153), .Y(mult_x_312_n77) );
NOR2X1TS U3271 ( .A(n3228), .B(n3163), .Y(mult_x_309_n71) );
NOR2X1TS U3272 ( .A(n3217), .B(n3166), .Y(mult_x_309_n66) );
AOI22X1TS U3273 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[30]), .B0(n951),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n2180) );
AOI22X1TS U3274 ( .A0(n947), .A1(FPADDSUB_Data_array_SWR[26]), .B0(n2038),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2179) );
OAI211X1TS U3275 ( .A0(n2181), .A1(n3259), .B0(n2180), .C0(n2179), .Y(n2186)
);
AOI21X1TS U3276 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2186), .B0(n2058), .Y(
n2182) );
OAI21XLTS U3277 ( .A0(n2188), .A1(n2054), .B0(n2182), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
AOI21X1TS U3278 ( .A0(n925), .A1(n2183), .B0(n2041), .Y(n2184) );
OAI21XLTS U3279 ( .A0(n2036), .A1(n2185), .B0(n2184), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
AOI21X1TS U3280 ( .A0(n925), .A1(n2186), .B0(n2041), .Y(n2187) );
OAI21XLTS U3281 ( .A0(n2036), .A1(n2188), .B0(n2187), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
NOR2X1TS U3282 ( .A(n3226), .B(n3148), .Y(mult_x_309_n76) );
OAI32X1TS U3283 ( .A0(n3165), .A1(n2966), .A2(n2967), .B0(n2968), .B1(
FPMULT_FS_Module_state_reg[0]), .Y(n2189) );
NOR2X1TS U3284 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n3212), .Y(n2196) );
AOI222X4TS U3285 ( .A0(n2193), .A1(n3159), .B0(n2193), .B1(n3211), .C0(n3159), .C1(n3211), .Y(n2199) );
AOI22X1TS U3286 ( .A0(n2920), .A1(n2197), .B0(n2199), .B1(n2382), .Y(n2195)
);
OAI31X1TS U3287 ( .A0(n2196), .A1(n2195), .A2(n2198), .B0(n2194), .Y(
FPADDSUB_Raw_mant_SGF[6]) );
AOI22X1TS U3288 ( .A0(n2920), .A1(n2244), .B0(n2246), .B1(n2382), .Y(n2201)
);
NAND2X1TS U3289 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n3160), .Y(n2245) );
OAI21XLTS U3290 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n3160), .B0(n2245),
.Y(n2200) );
XOR2XLTS U3291 ( .A(n2201), .B(n2200), .Y(FPADDSUB_Raw_mant_SGF[7]) );
AFHCINX2TS U3292 ( .CIN(n2202), .B(n2203), .A(n2204), .S(n2211), .CO(n2114)
);
OR2X1TS U3293 ( .A(n2206), .B(n2205), .Y(n2208) );
CLKAND2X2TS U3294 ( .A(n2208), .B(n2207), .Y(n2210) );
NOR4X1TS U3295 ( .A(n2211), .B(n2210), .C(n2209), .D(
FPMULT_Sgf_operation_Result[2]), .Y(n3368) );
OR2X1TS U3296 ( .A(n3467), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
FPADDSUB_formatted_number_W[29]) );
OR2X1TS U3297 ( .A(n3467), .B(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X1TS U3298 ( .A(n3467), .B(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
FPADDSUB_formatted_number_W[26]) );
OR2X1TS U3299 ( .A(n3467), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
FPADDSUB_formatted_number_W[28]) );
OR2X1TS U3300 ( .A(n3467), .B(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
FPADDSUB_formatted_number_W[23]) );
OR2X1TS U3301 ( .A(n3467), .B(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
FPADDSUB_formatted_number_W[27]) );
OR2X1TS U3302 ( .A(n3467), .B(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
FPADDSUB_formatted_number_W[25]) );
INVX2TS U3303 ( .A(n3454), .Y(intadd_1106_B_0_) );
NAND2X1TS U3304 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MX[3]), .Y(n2214) );
NAND2X1TS U3305 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MX[4]), .Y(n2213) );
NAND2X1TS U3306 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MX[4]), .Y(n2648) );
NOR2X1TS U3307 ( .A(n2648), .B(n3179), .Y(n2622) );
NAND2X1TS U3308 ( .A(n2622), .B(FPMULT_Op_MX[3]), .Y(n2650) );
INVX2TS U3309 ( .A(n2657), .Y(n2218) );
INVX2TS U3310 ( .A(n2214), .Y(n2215) );
NAND2X1TS U3311 ( .A(intadd_1106_CI), .B(n2215), .Y(n2518) );
INVX2TS U3312 ( .A(n2518), .Y(n2654) );
NAND2X1TS U3313 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MY[2]), .Y(n2632) );
XNOR2X1TS U3314 ( .A(n2635), .B(n2632), .Y(n2216) );
XOR2X1TS U3315 ( .A(n2216), .B(n2634), .Y(n2655) );
OAI21X1TS U3316 ( .A0(n2218), .A1(n2518), .B0(n2217), .Y(mult_x_310_n36) );
NAND2X1TS U3317 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MX[4]), .Y(n2612) );
INVX2TS U3318 ( .A(n2612), .Y(n2219) );
OAI21XLTS U3319 ( .A0(n2613), .A1(n2614), .B0(n2219), .Y(n2221) );
NAND2X1TS U3320 ( .A(n2613), .B(n2614), .Y(n2220) );
NAND2X1TS U3321 ( .A(n2221), .B(n2220), .Y(n2663) );
INVX2TS U3322 ( .A(n2663), .Y(n2224) );
INVX2TS U3323 ( .A(n2661), .Y(n2223) );
NOR2X1TS U3324 ( .A(n3174), .B(n3257), .Y(n2660) );
OAI21XLTS U3325 ( .A0(n2663), .A1(n2661), .B0(n2660), .Y(n2222) );
OAI21XLTS U3326 ( .A0(n2224), .A1(n2223), .B0(n2222), .Y(intadd_1106_B_8_)
);
INVX2TS U3327 ( .A(enab_cont_iter), .Y(n2226) );
OR3X1TS U3328 ( .A(n2513), .B(n3187), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .Y(n2225) );
OAI21XLTS U3329 ( .A0(n2227), .A1(n2226), .B0(n2225), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
NAND2X1TS U3330 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MY[9]), .Y(n2558) );
NAND2X1TS U3331 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MY[8]), .Y(n2585) );
NOR2X1TS U3332 ( .A(n3171), .B(n3225), .Y(n2609) );
NAND2X1TS U3333 ( .A(n2609), .B(n2228), .Y(n2583) );
OAI21XLTS U3334 ( .A0(n2558), .A1(n2585), .B0(n2583), .Y(intadd_1105_B_2_)
);
NAND2X1TS U3335 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MX[9]), .Y(n2230) );
NAND2X1TS U3336 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MX[10]), .Y(n2229) );
NAND3X1TS U3337 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MX[10]), .C(
FPMULT_Op_MY[7]), .Y(n2546) );
NOR2X2TS U3338 ( .A(n2546), .B(n3243), .Y(n2574) );
INVX2TS U3339 ( .A(n2581), .Y(n2234) );
INVX2TS U3340 ( .A(n2230), .Y(n2231) );
NAND2X1TS U3341 ( .A(intadd_1105_CI), .B(n2231), .Y(n2516) );
INVX2TS U3342 ( .A(n2516), .Y(n2578) );
XNOR2X1TS U3343 ( .A(n2556), .B(n2558), .Y(n2232) );
XOR2X1TS U3344 ( .A(n2232), .B(n2557), .Y(n2579) );
OAI21XLTS U3345 ( .A0(n2581), .A1(n2578), .B0(n2579), .Y(n2233) );
NAND2X1TS U3346 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MX[10]), .Y(n2536) );
INVX2TS U3347 ( .A(n2536), .Y(n2235) );
OAI21XLTS U3348 ( .A0(n2537), .A1(n2538), .B0(n2235), .Y(n2237) );
NAND2X1TS U3349 ( .A(n2537), .B(n2538), .Y(n2236) );
NAND2X1TS U3350 ( .A(n2237), .B(n2236), .Y(n2589) );
INVX2TS U3351 ( .A(n2589), .Y(n2240) );
INVX2TS U3352 ( .A(n2587), .Y(n2239) );
NOR2X1TS U3353 ( .A(n3173), .B(n3244), .Y(n2586) );
OAI21XLTS U3354 ( .A0(n2240), .A1(n2239), .B0(n2238), .Y(intadd_1105_B_8_)
);
AND3X1TS U3355 ( .A(n2242), .B(n2241), .C(n3241), .Y(n2512) );
NAND3BXLTS U3356 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n2512), .Y(n2243) );
INVX2TS U3357 ( .A(n2243), .Y(FPSENCOS_enab_RB3) );
NOR2X1TS U3358 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n3215), .Y(n2249) );
AOI222X4TS U3359 ( .A0(n2246), .A1(n3160), .B0(n2246), .B1(n3213), .C0(n3160), .C1(n3213), .Y(n2252) );
AOI22X1TS U3360 ( .A0(n2920), .A1(n2250), .B0(n2252), .B1(n2382), .Y(n2248)
);
OAI31X1TS U3361 ( .A0(n2249), .A1(n2248), .A2(n2251), .B0(n2247), .Y(
FPADDSUB_Raw_mant_SGF[8]) );
AOI22X1TS U3362 ( .A0(n2920), .A1(n2290), .B0(n2292), .B1(n2382), .Y(n2254)
);
NAND2X1TS U3363 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n3161), .Y(n2291) );
OAI21XLTS U3364 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n3161), .B0(n2291),
.Y(n2253) );
AOI22X1TS U3365 ( .A0(n2038), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n951),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n2256) );
AOI22X1TS U3366 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[37]), .B0(n947),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n2255) );
AOI21X1TS U3367 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2263), .B0(n2058), .Y(
n2258) );
OAI21X1TS U3368 ( .A0(n2265), .A1(n2054), .B0(n2258), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI22X1TS U3369 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n2038), .B0(
FPADDSUB_Data_array_SWR[40]), .B1(n950), .Y(n2260) );
AOI22X1TS U3370 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[36]), .B0(
FPADDSUB_Data_array_SWR[32]), .B1(n946), .Y(n2259) );
OAI211X1TS U3371 ( .A0(n3259), .A1(n2261), .B0(n2260), .C0(n2259), .Y(n2273)
);
AOI21X1TS U3372 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2273), .B0(n2058), .Y(
n2262) );
OAI21X1TS U3373 ( .A0(n2275), .A1(n2054), .B0(n2262), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
AOI21X1TS U3374 ( .A0(n2281), .A1(n2263), .B0(n2041), .Y(n2264) );
OAI21X1TS U3375 ( .A0(n2265), .A1(n2036), .B0(n2264), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
AOI22X1TS U3376 ( .A0(n2038), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n950),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2271) );
AOI22X1TS U3377 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n946),
.B1(FPADDSUB_Data_array_SWR[30]), .Y(n2270) );
OAI211X1TS U3378 ( .A0(n2287), .A1(n3259), .B0(n2271), .C0(n2270), .Y(n2280)
);
AOI21X1TS U3379 ( .A0(n926), .A1(n2280), .B0(n2058), .Y(n2272) );
OAI21X1TS U3380 ( .A0(n2283), .A1(n2054), .B0(n2272), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
AOI21X1TS U3381 ( .A0(n2281), .A1(n2273), .B0(n2041), .Y(n2274) );
OAI21X1TS U3382 ( .A0(n2275), .A1(n2036), .B0(n2274), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI22X1TS U3383 ( .A0(n2038), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n950),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n2277) );
AOI22X1TS U3384 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n947),
.B1(FPADDSUB_Data_array_SWR[31]), .Y(n2276) );
OAI211X1TS U3385 ( .A0(n2283), .A1(n3259), .B0(n2277), .C0(n2276), .Y(n2284)
);
AOI21X1TS U3386 ( .A0(n911), .A1(n2284), .B0(n2041), .Y(n2278) );
OAI21X1TS U3387 ( .A0(n2287), .A1(n2036), .B0(n2278), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
AOI21X1TS U3388 ( .A0(n911), .A1(n2280), .B0(n2041), .Y(n2282) );
OAI21X1TS U3389 ( .A0(n2283), .A1(n2036), .B0(n2282), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
AOI21X1TS U3390 ( .A0(n926), .A1(n2284), .B0(n2058), .Y(n2286) );
OAI21X1TS U3391 ( .A0(n2287), .A1(n2054), .B0(n2286), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
NOR2BX1TS U3392 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2288) );
XOR2X1TS U3393 ( .A(n909), .B(n2288), .Y(DP_OP_26J324_129_1325_n15) );
NOR2BX1TS U3394 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2289) );
XOR2X1TS U3395 ( .A(n909), .B(n2289), .Y(DP_OP_26J324_129_1325_n14) );
NOR4X2TS U3396 ( .A(n3214), .B(n3145), .C(n3149), .D(n3162), .Y(
mult_x_309_n38) );
NAND2X1TS U3397 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[19]), .Y(n2720) );
INVX2TS U3398 ( .A(n2720), .Y(mult_x_309_n26) );
AOI32X1TS U3399 ( .A0(FPMULT_Op_MY[20]), .A1(FPMULT_Op_MX[18]), .A2(
mult_x_309_n26), .B0(FPMULT_Op_MY[21]), .B1(FPMULT_Op_MX[18]), .Y(
n2723) );
NAND2X1TS U3400 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MX[19]), .Y(n2725) );
CMPR32X2TS U3401 ( .A(mult_x_309_n13), .B(FPMULT_Op_MX[22]), .C(
FPMULT_Op_MY[22]), .CO(n2094), .S(intadd_1107_B_7_) );
NOR2X1TS U3402 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n3218), .Y(n2295) );
AOI222X4TS U3403 ( .A0(n2292), .A1(n3161), .B0(n2292), .B1(n3216), .C0(n3161), .C1(n3216), .Y(n2301) );
AOI22X1TS U3404 ( .A0(n2920), .A1(n2299), .B0(n2301), .B1(n2382), .Y(n2294)
);
OAI31X1TS U3405 ( .A0(n2295), .A1(n2294), .A2(n2300), .B0(n2293), .Y(
FPADDSUB_Raw_mant_SGF[10]) );
OAI211X1TS U3406 ( .A0(n3317), .A1(n2857), .B0(n2297), .C0(n2296), .Y(n2298)
);
INVX2TS U3407 ( .A(n2298), .Y(FPADDSUB_enable_Pipeline_input) );
AOI22X1TS U3408 ( .A0(n2920), .A1(n2307), .B0(n2309), .B1(n2382), .Y(n2303)
);
NAND2X1TS U3409 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n3222), .Y(n2308) );
OAI21XLTS U3410 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n3222), .B0(n2308),
.Y(n2302) );
AOI222X1TS U3411 ( .A0(n3010), .A1(Data_2[30]), .B0(n924), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n3067), .Y(n2304) );
INVX2TS U3412 ( .A(n2304), .Y(add_subt_data2[30]) );
AND4X1TS U3413 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[0]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n2305) );
AND4X1TS U3414 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n2305), .Y(n2306) );
CLKAND2X2TS U3415 ( .A(FPMULT_FSM_selector_A), .B(FPMULT_exp_oper_result[8]),
.Y(FPMULT_S_Oper_A_exp[8]) );
NOR2X1TS U3416 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n3223), .Y(n2312) );
AOI222X4TS U3417 ( .A0(n2309), .A1(n3222), .B0(n2309), .B1(n3164), .C0(n3222), .C1(n3164), .Y(n2315) );
AOI22X1TS U3418 ( .A0(n908), .A1(n2313), .B0(n2315), .B1(n2382), .Y(n2311)
);
OAI31X1TS U3419 ( .A0(n2312), .A1(n2311), .A2(n2314), .B0(n2310), .Y(
FPADDSUB_Raw_mant_SGF[12]) );
AOI22X1TS U3420 ( .A0(n908), .A1(n2318), .B0(n2320), .B1(n2382), .Y(n2317)
);
NAND2X1TS U3421 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n3170), .Y(n2319) );
OAI21XLTS U3422 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n3170), .B0(n2319),
.Y(n2316) );
NOR2X1TS U3423 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n3240), .Y(n2323) );
AOI222X4TS U3424 ( .A0(n2320), .A1(n3170), .B0(n2320), .B1(n3229), .C0(n3170), .C1(n3229), .Y(n2368) );
AOI22X1TS U3425 ( .A0(n908), .A1(n2366), .B0(n2368), .B1(n2382), .Y(n2322)
);
OAI31X1TS U3426 ( .A0(n2323), .A1(n2322), .A2(n2367), .B0(n2321), .Y(
FPADDSUB_Raw_mant_SGF[14]) );
INVX4TS U3427 ( .A(n3105), .Y(n2360) );
INVX4TS U3428 ( .A(n2324), .Y(n2359) );
AOI22X1TS U3429 ( .A0(n2360), .A1(cordic_result[10]), .B0(n2359), .B1(
mult_result[10]), .Y(n2325) );
AOI22X1TS U3430 ( .A0(n2360), .A1(cordic_result[8]), .B0(n2359), .B1(
mult_result[8]), .Y(n2326) );
INVX2TS U3431 ( .A(n3105), .Y(n2337) );
INVX2TS U3432 ( .A(n2324), .Y(n2336) );
AOI22X1TS U3433 ( .A0(n2337), .A1(cordic_result[4]), .B0(n2336), .B1(
mult_result[4]), .Y(n2327) );
AOI22X1TS U3434 ( .A0(n2360), .A1(cordic_result[11]), .B0(n2359), .B1(
mult_result[11]), .Y(n2328) );
AOI22X1TS U3435 ( .A0(n2337), .A1(cordic_result[0]), .B0(n2336), .B1(
mult_result[0]), .Y(n2329) );
AOI22X1TS U3436 ( .A0(n2337), .A1(cordic_result[5]), .B0(n2336), .B1(
mult_result[5]), .Y(n2330) );
INVX4TS U3437 ( .A(n3105), .Y(n2363) );
INVX4TS U3438 ( .A(n2324), .Y(n2362) );
AOI22X1TS U3439 ( .A0(n2363), .A1(cordic_result[31]), .B0(n2362), .B1(
mult_result[31]), .Y(n2331) );
AOI22X1TS U3440 ( .A0(n2360), .A1(cordic_result[7]), .B0(n2359), .B1(
mult_result[7]), .Y(n2332) );
AOI22X1TS U3441 ( .A0(n2360), .A1(cordic_result[9]), .B0(n2359), .B1(
mult_result[9]), .Y(n2333) );
AOI22X1TS U3442 ( .A0(n2337), .A1(cordic_result[2]), .B0(n2336), .B1(
mult_result[2]), .Y(n2334) );
AOI22X1TS U3443 ( .A0(n2337), .A1(cordic_result[1]), .B0(n2336), .B1(
mult_result[1]), .Y(n2335) );
AOI22X1TS U3444 ( .A0(n2337), .A1(cordic_result[3]), .B0(n2336), .B1(
mult_result[3]), .Y(n2338) );
AOI22X1TS U3445 ( .A0(n2363), .A1(cordic_result[24]), .B0(n2362), .B1(
mult_result[24]), .Y(n2339) );
AOI22X1TS U3446 ( .A0(n2363), .A1(cordic_result[25]), .B0(n2362), .B1(
mult_result[25]), .Y(n2340) );
AOI22X1TS U3447 ( .A0(n2363), .A1(cordic_result[28]), .B0(n2362), .B1(
mult_result[28]), .Y(n2341) );
AOI22X1TS U3448 ( .A0(n2363), .A1(cordic_result[27]), .B0(n2362), .B1(
mult_result[27]), .Y(n2342) );
AOI22X1TS U3449 ( .A0(n2363), .A1(cordic_result[26]), .B0(n2362), .B1(
mult_result[26]), .Y(n2343) );
AOI22X1TS U3450 ( .A0(n2363), .A1(cordic_result[29]), .B0(n2362), .B1(
mult_result[29]), .Y(n2344) );
AOI22X1TS U3451 ( .A0(n2363), .A1(cordic_result[30]), .B0(n2362), .B1(
mult_result[30]), .Y(n2345) );
BUFX3TS U3452 ( .A(n2347), .Y(n2365) );
AOI22X1TS U3453 ( .A0(n2360), .A1(cordic_result[12]), .B0(n2359), .B1(
mult_result[12]), .Y(n2348) );
AOI22X1TS U3454 ( .A0(n2360), .A1(cordic_result[15]), .B0(n2359), .B1(
mult_result[15]), .Y(n2349) );
AOI22X1TS U3455 ( .A0(n2363), .A1(cordic_result[21]), .B0(n2362), .B1(
mult_result[21]), .Y(n2350) );
AOI22X1TS U3456 ( .A0(n2363), .A1(cordic_result[22]), .B0(n2362), .B1(
mult_result[22]), .Y(n2351) );
AOI22X1TS U3457 ( .A0(n2360), .A1(cordic_result[6]), .B0(n2359), .B1(
mult_result[6]), .Y(n2352) );
AOI22X1TS U3458 ( .A0(n2360), .A1(cordic_result[18]), .B0(n2359), .B1(
mult_result[18]), .Y(n2353) );
AOI22X1TS U3459 ( .A0(n2363), .A1(cordic_result[20]), .B0(n2362), .B1(
mult_result[20]), .Y(n2354) );
AOI22X1TS U3460 ( .A0(n2360), .A1(cordic_result[14]), .B0(n2359), .B1(
mult_result[14]), .Y(n2355) );
AOI22X1TS U3461 ( .A0(n2360), .A1(cordic_result[16]), .B0(n2359), .B1(
mult_result[16]), .Y(n2356) );
AOI22X1TS U3462 ( .A0(n2360), .A1(cordic_result[13]), .B0(n2359), .B1(
mult_result[13]), .Y(n2357) );
AOI22X1TS U3463 ( .A0(n2363), .A1(cordic_result[23]), .B0(n2362), .B1(
mult_result[23]), .Y(n2358) );
AOI22X1TS U3464 ( .A0(n2360), .A1(cordic_result[17]), .B0(n2359), .B1(
mult_result[17]), .Y(n2361) );
AOI22X1TS U3465 ( .A0(n2363), .A1(cordic_result[19]), .B0(n2362), .B1(
mult_result[19]), .Y(n2364) );
NOR2X1TS U3466 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n3252), .Y(n2371) );
NAND2X1TS U3467 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n3176), .Y(n2891) );
AOI222X4TS U3468 ( .A0(n2889), .A1(n3176), .B0(n2889), .B1(n3239), .C0(n3176), .C1(n3239), .Y(n2375) );
AOI22X1TS U3469 ( .A0(n908), .A1(n2373), .B0(n2375), .B1(n3452), .Y(n2370)
);
OAI31X1TS U3470 ( .A0(n2371), .A1(n2370), .A2(n2374), .B0(n2369), .Y(
FPADDSUB_Raw_mant_SGF[16]) );
AOI221X4TS U3471 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n3451), .B0(
FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n2406), .C0(n2424), .Y(n2945) );
AOI22X2TS U3472 ( .A0(n3451), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n2424), .Y(n2408) );
OAI22X2TS U3473 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(FPADDSUB_LZD_raw_out_EWR[0]),
.B1(n2406), .Y(n2387) );
NAND2X1TS U3474 ( .A(n2408), .B(n2387), .Y(n2372) );
NOR2X1TS U3475 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n3258), .Y(n2378) );
NAND2X1TS U3476 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n3182), .Y(n2896) );
AOI222X4TS U3477 ( .A0(n2894), .A1(n3182), .B0(n2894), .B1(n3254), .C0(n3182), .C1(n3254), .Y(n2381) );
AOI22X1TS U3478 ( .A0(n908), .A1(n2379), .B0(n2381), .B1(n2382), .Y(n2377)
);
OAI31X1TS U3479 ( .A0(n2378), .A1(n2377), .A2(n2380), .B0(n2376), .Y(
FPADDSUB_Raw_mant_SGF[18]) );
NOR2X1TS U3480 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n3295), .Y(n2385) );
NAND2X1TS U3481 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n3294), .Y(n2901) );
AOI222X4TS U3482 ( .A0(n2899), .A1(n3294), .B0(n2899), .B1(n3184), .C0(n3294), .C1(n3184), .Y(n2400) );
AOI22X1TS U3483 ( .A0(n908), .A1(n2398), .B0(n2400), .B1(n2382), .Y(n2384)
);
OAI31X1TS U3484 ( .A0(n2385), .A1(n2384), .A2(n2399), .B0(n2383), .Y(
FPADDSUB_Raw_mant_SGF[20]) );
INVX2TS U3485 ( .A(n2387), .Y(n2407) );
AOI22X1TS U3486 ( .A0(n3451), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n930), .Y(n2453) );
INVX2TS U3487 ( .A(n2439), .Y(n2451) );
AOI22X1TS U3488 ( .A0(n3451), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n2447),
.B1(n2451), .Y(n2388) );
CMPR32X2TS U3489 ( .A(n2390), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]), .C(
n2389), .CO(n2396), .S(n2393) );
CMPR32X2TS U3490 ( .A(n2393), .B(n2392), .C(n2391), .CO(n2395), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
XOR2X1TS U3491 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n2527) );
XOR2X1TS U3492 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
n2530) );
CMPR32X2TS U3493 ( .A(n1083), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]), .C(
n2394), .CO(n2529), .S(n2397) );
CMPR32X2TS U3494 ( .A(n2397), .B(n2396), .C(n2395), .CO(n2528), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
NOR2X1TS U3495 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .B(
n2534), .Y(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16])
);
NOR2X1TS U3496 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n3320), .Y(n2403) );
NAND2X1TS U3497 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n3199), .Y(n2906) );
AOI222X4TS U3498 ( .A0(n2904), .A1(n3199), .B0(n2904), .B1(n3309), .C0(n3199), .C1(n3309), .Y(n2764) );
AOI22X1TS U3499 ( .A0(n908), .A1(n2909), .B0(n2764), .B1(n2924), .Y(n2402)
);
CLKAND2X2TS U3500 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n3320), .Y(n2910)
);
OAI31X1TS U3501 ( .A0(n2403), .A1(n2402), .A2(n2910), .B0(n2401), .Y(
FPADDSUB_Raw_mant_SGF[22]) );
INVX2TS U3502 ( .A(n2447), .Y(n2404) );
AOI22X1TS U3503 ( .A0(n929), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n2424), .Y(n2405) );
BUFX3TS U3504 ( .A(n2424), .Y(n3110) );
INVX4TS U3505 ( .A(n2406), .Y(n3017) );
AOI222X4TS U3506 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n930), .C0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .C1(n3017), .Y(n2942) );
AOI222X4TS U3507 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n930), .C0(n959), .C1(n3017), .Y(
n2943) );
OAI22X1TS U3508 ( .A0(n2942), .A1(n2946), .B0(n2943), .B1(n928), .Y(n2410)
);
AOI21X1TS U3509 ( .A0(n943), .A1(n2481), .B0(n2410), .Y(n2411) );
AOI222X4TS U3510 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n3451), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(
n929), .Y(n2473) );
AOI22X1TS U3511 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n3451), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n2424), .Y(n2412) );
AOI222X4TS U3512 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n3451), .B1(FPADDSUB_Raw_mant_NRM_SWR[8]), .C0(FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(
n929), .Y(n2460) );
AOI222X4TS U3513 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n3451), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(
n929), .Y(n2465) );
OAI22X1TS U3514 ( .A0(n2460), .A1(n2479), .B0(n2465), .B1(n2946), .Y(n2413)
);
AOI21X1TS U3515 ( .A0(n943), .A1(n2475), .B0(n2413), .Y(n2414) );
AOI222X4TS U3516 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n930), .C0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .C1(n3017), .Y(n2461) );
AOI22X1TS U3517 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n3451), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n2424), .Y(n2415) );
AOI222X4TS U3518 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n930), .C0(n958), .C1(n3017), .Y(
n2478) );
AOI222X4TS U3519 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[18]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n930), .C0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n3017), .Y(n2484) );
OAI22X1TS U3520 ( .A0(n2478), .A1(n2404), .B0(n2484), .B1(n2946), .Y(n2416)
);
AOI21X1TS U3521 ( .A0(n943), .A1(n2463), .B0(n2416), .Y(n2417) );
AOI222X4TS U3522 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n930), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n3017), .Y(n2455) );
AOI22X1TS U3523 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n3451), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n2424), .Y(n2418) );
AOI222X4TS U3524 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n3017), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(
n929), .Y(n2472) );
AOI222X4TS U3525 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n929), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n3017), .Y(n2477) );
OAI22X1TS U3526 ( .A0(n2472), .A1(n2404), .B0(n2477), .B1(n2946), .Y(n2419)
);
AOI21X1TS U3527 ( .A0(n943), .A1(n2457), .B0(n2419), .Y(n2420) );
AOI222X4TS U3528 ( .A0(n2424), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(n3017),
.B1(FPADDSUB_Raw_mant_NRM_SWR[18]), .C0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.C1(n929), .Y(n2467) );
AOI22X1TS U3529 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n3451), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n2424), .Y(n2421) );
AOI222X4TS U3530 ( .A0(n2424), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n930), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n3017), .Y(n2454) );
AOI222X4TS U3531 ( .A0(n3110), .A1(FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n929), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n3017), .Y(n2459) );
OAI22X1TS U3532 ( .A0(n2454), .A1(n2479), .B0(n2459), .B1(n2946), .Y(n2422)
);
AOI21X1TS U3533 ( .A0(n943), .A1(n2469), .B0(n2422), .Y(n2423) );
AOI222X4TS U3534 ( .A0(n2424), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(n3017),
.B1(FPADDSUB_Raw_mant_NRM_SWR[20]), .C0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C1(n929), .Y(n2466) );
AOI222X4TS U3535 ( .A0(n2424), .A1(FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(n3017),
.B1(FPADDSUB_Raw_mant_NRM_SWR[21]), .C0(n958), .C1(n929), .Y(n2471) );
OAI22X1TS U3536 ( .A0(n2466), .A1(n2479), .B0(n2471), .B1(n2946), .Y(n2425)
);
AOI21X1TS U3537 ( .A0(n2409), .A1(n2451), .B0(n2425), .Y(n2426) );
OAI22X1TS U3538 ( .A0(n2942), .A1(n2404), .B0(n2943), .B1(n2946), .Y(n2427)
);
AOI21X1TS U3539 ( .A0(n2409), .A1(n2481), .B0(n2427), .Y(n2428) );
OAI22X1TS U3540 ( .A0(n2459), .A1(n2479), .B0(n2467), .B1(n2946), .Y(n2429)
);
AOI21X1TS U3541 ( .A0(n2409), .A1(n2469), .B0(n2429), .Y(n2430) );
OAI22X1TS U3542 ( .A0(n2484), .A1(n2404), .B0(n2461), .B1(n2946), .Y(n2431)
);
AOI21X1TS U3543 ( .A0(n2409), .A1(n2463), .B0(n2431), .Y(n2432) );
OAI22X1TS U3544 ( .A0(n2465), .A1(n2479), .B0(n2473), .B1(n2946), .Y(n2433)
);
AOI21X1TS U3545 ( .A0(n2409), .A1(n2475), .B0(n2433), .Y(n2434) );
OAI22X1TS U3546 ( .A0(n2477), .A1(n2479), .B0(n2455), .B1(n2946), .Y(n2435)
);
AOI21X1TS U3547 ( .A0(n2409), .A1(n2457), .B0(n2435), .Y(n2436) );
OAI22X1TS U3548 ( .A0(n2466), .A1(n2386), .B0(n2471), .B1(n928), .Y(n2437)
);
AOI21X1TS U3549 ( .A0(n2447), .A1(n2469), .B0(n2437), .Y(n2438) );
OAI22X1TS U3550 ( .A0(n2478), .A1(n2386), .B0(n2484), .B1(n928), .Y(n2440)
);
AOI21X1TS U3551 ( .A0(n2447), .A1(n2481), .B0(n2440), .Y(n2441) );
OAI22X1TS U3552 ( .A0(n2460), .A1(n2946), .B0(n2465), .B1(n927), .Y(n2442)
);
AOI21X1TS U3553 ( .A0(n2447), .A1(n2463), .B0(n2442), .Y(n2443) );
OAI22X1TS U3554 ( .A0(n2472), .A1(n2946), .B0(n2477), .B1(n927), .Y(n2444)
);
AOI21X1TS U3555 ( .A0(n2447), .A1(n2475), .B0(n2444), .Y(n2445) );
OAI22X1TS U3556 ( .A0(n2454), .A1(n2386), .B0(n2459), .B1(n927), .Y(n2446)
);
AOI21X1TS U3557 ( .A0(n2447), .A1(n2457), .B0(n2446), .Y(n2448) );
OAI22X1TS U3558 ( .A0(n2471), .A1(n2404), .B0(n2449), .B1(n928), .Y(n2450)
);
AOI21X1TS U3559 ( .A0(n2482), .A1(n2451), .B0(n2450), .Y(n2452) );
OAI22X1TS U3560 ( .A0(n2455), .A1(n2479), .B0(n2454), .B1(n927), .Y(n2456)
);
AOI21X1TS U3561 ( .A0(n2482), .A1(n2457), .B0(n2456), .Y(n2458) );
OAI22X1TS U3562 ( .A0(n2461), .A1(n2404), .B0(n2460), .B1(n928), .Y(n2462)
);
AOI21X1TS U3563 ( .A0(n2482), .A1(n2463), .B0(n2462), .Y(n2464) );
OAI22X1TS U3564 ( .A0(n2467), .A1(n2479), .B0(n2466), .B1(n927), .Y(n2468)
);
AOI21X1TS U3565 ( .A0(n2482), .A1(n2469), .B0(n2468), .Y(n2470) );
OAI22X1TS U3566 ( .A0(n2473), .A1(n2479), .B0(n2472), .B1(n927), .Y(n2474)
);
AOI21X1TS U3567 ( .A0(n2482), .A1(n2475), .B0(n2474), .Y(n2476) );
OAI22X1TS U3568 ( .A0(n2943), .A1(n2404), .B0(n2478), .B1(n928), .Y(n2480)
);
AOI21X1TS U3569 ( .A0(n2482), .A1(n2481), .B0(n2480), .Y(n2483) );
NOR2XLTS U3570 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n2486) );
OAI22X1TS U3571 ( .A0(n2488), .A1(n2487), .B0(n2486), .B1(n2500), .Y(n2489)
);
AOI21X1TS U3572 ( .A0(n2490), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n2489),
.Y(n2491) );
OAI211X1TS U3573 ( .A0(n2493), .A1(n3325), .B0(n2492), .C0(n2491), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
NOR3X1TS U3574 ( .A(n959), .B(n2510), .C(n3233), .Y(n2506) );
OAI211X1TS U3575 ( .A0(n2501), .A1(n2500), .B0(n2499), .C0(n2498), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
OAI31X1TS U3576 ( .A0(n2504), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n2503),
.B0(n2502), .Y(n2505) );
AOI211X1TS U3577 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n2507), .B0(n2506),
.C0(n2505), .Y(n2508) );
OAI211X1TS U3578 ( .A0(n3362), .A1(n2510), .B0(n2509), .C0(n2508), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
NOR3XLTS U3579 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n3293), .Y(FPSENCOS_enab_d_ff4_Xn) );
NOR3XLTS U3580 ( .A(FPSENCOS_cont_var_out[1]), .B(n3155), .C(n3293), .Y(
FPSENCOS_enab_d_ff4_Yn) );
OAI21XLTS U3581 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n909), .B0(n2511),
.Y(n808) );
NAND3BX1TS U3582 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(n2512), .Y(n2976) );
OAI31X1TS U3583 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n3187),
.A2(n2513), .B0(n2976), .Y(FPSENCOS_enab_d_ff_RB1) );
NOR2X1TS U3584 ( .A(enab_cont_iter), .B(n2978), .Y(n2972) );
NAND2X1TS U3585 ( .A(n2972), .B(n3293), .Y(n3109) );
INVX2TS U3586 ( .A(n3109), .Y(n3108) );
OAI21XLTS U3587 ( .A0(n3108), .A1(n3155), .B0(FPSENCOS_cont_var_out[1]), .Y(
n2514) );
OAI22X1TS U3588 ( .A0(n3172), .A1(n3243), .B0(n3157), .B1(n942), .Y(n2515)
);
CLKAND2X2TS U3589 ( .A(n2516), .B(n2515), .Y(n3235) );
OAI22X1TS U3590 ( .A0(n3179), .A1(n3154), .B0(n3245), .B1(n973), .Y(n2517)
);
CLKAND2X2TS U3591 ( .A(n2518), .B(n2517), .Y(n3251) );
XNOR2X1TS U3592 ( .A(DP_OP_234J324_132_4955_n1), .B(n2519), .Y(
FPMULT_Exp_module_Overflow_A) );
NOR2BX1TS U3593 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2520) );
XOR2X1TS U3594 ( .A(n909), .B(n2520), .Y(DP_OP_26J324_129_1325_n16) );
NOR2BX1TS U3595 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2521) );
XOR2X1TS U3596 ( .A(n909), .B(n2521), .Y(DP_OP_26J324_129_1325_n17) );
XOR2X1TS U3597 ( .A(n909), .B(n2522), .Y(DP_OP_26J324_129_1325_n18) );
CMPR32X2TS U3598 ( .A(n2524), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .C(
n2523), .CO(n2534), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
CMPR32X2TS U3599 ( .A(n2527), .B(n2526), .C(n2525), .CO(n2523), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
CMPR32X2TS U3600 ( .A(n2530), .B(n2529), .C(n2528), .CO(n2525), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
CMPR32X2TS U3601 ( .A(n2533), .B(n2532), .C(n2531), .CO(n1850), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
XNOR2X1TS U3602 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .B(
n2534), .Y(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15])
);
NOR2XLTS U3603 ( .A(n3177), .B(n3244), .Y(intadd_1105_A_8_) );
NOR2XLTS U3604 ( .A(n3178), .B(n971), .Y(n2543) );
NOR2XLTS U3605 ( .A(n3171), .B(n3244), .Y(n2542) );
NOR2XLTS U3606 ( .A(n3177), .B(n3157), .Y(n2541) );
NAND2X1TS U3607 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MY[7]), .Y(n2544) );
NAND2X1TS U3608 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MX[10]), .Y(n2545) );
NOR2X2TS U3609 ( .A(n2544), .B(n2545), .Y(n2549) );
NAND2X1TS U3610 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MX[9]), .Y(n2548) );
XNOR2X1TS U3611 ( .A(n2537), .B(n2536), .Y(n2539) );
XOR2X1TS U3612 ( .A(n2539), .B(n2538), .Y(n2590) );
OAI21XLTS U3613 ( .A0(n2593), .A1(n2591), .B0(n2590), .Y(n2540) );
OAI2BB1X1TS U3614 ( .A0N(n2591), .A1N(n2593), .B0(n2540), .Y(mult_x_311_n14)
);
CMPR32X2TS U3615 ( .A(n2543), .B(n2542), .C(n2541), .CO(n2591), .S(n2594) );
NOR2XLTS U3616 ( .A(n3178), .B(n3157), .Y(n2569) );
NOR2XLTS U3617 ( .A(n3177), .B(n3230), .Y(n2567) );
OAI2BB1X1TS U3618 ( .A0N(n2563), .A1N(n2565), .B0(n2547), .Y(n2597) );
XNOR2X1TS U3619 ( .A(n2549), .B(n2548), .Y(n2550) );
XOR2X1TS U3620 ( .A(n2551), .B(n2550), .Y(n2595) );
OAI2BB1X1TS U3621 ( .A0N(n2594), .A1N(n2597), .B0(n2552), .Y(mult_x_311_n17)
);
CMPR32X2TS U3622 ( .A(n2555), .B(n2554), .C(n2553), .CO(n2551), .S(n2599) );
NAND2X1TS U3623 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MX[7]), .Y(n2573) );
INVX2TS U3624 ( .A(n2574), .Y(n2562) );
INVX2TS U3625 ( .A(n2573), .Y(n2560) );
OAI2BB2X1TS U3626 ( .B0(n2559), .B1(n2558), .A0N(n2557), .A1N(n2556), .Y(
n2576) );
XOR2XLTS U3627 ( .A(n2563), .B(n2570), .Y(n2564) );
XOR2X1TS U3628 ( .A(n2565), .B(n2564), .Y(n2601) );
OAI2BB1X1TS U3629 ( .A0N(n2599), .A1N(n2598), .B0(n2566), .Y(mult_x_311_n22)
);
CMPR32X2TS U3630 ( .A(n2569), .B(n2568), .C(n2567), .CO(n2563), .S(n2603) );
NAND2X1TS U3631 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MX[10]), .Y(n2572) );
NAND2X1TS U3632 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MX[11]), .Y(n2571) );
XOR2XLTS U3633 ( .A(n2574), .B(n2573), .Y(n2575) );
XNOR2X1TS U3634 ( .A(n2576), .B(n2575), .Y(n2602) );
OAI2BB1X1TS U3635 ( .A0N(n2603), .A1N(n2605), .B0(n2577), .Y(mult_x_311_n29)
);
XOR2XLTS U3636 ( .A(n2579), .B(n2578), .Y(n2580) );
XOR2X1TS U3637 ( .A(n2581), .B(n2580), .Y(mult_x_311_n37) );
INVX2TS U3638 ( .A(n2582), .Y(n2584) );
INVX2TS U3639 ( .A(n2583), .Y(n2607) );
AOI21X1TS U3640 ( .A0(n2585), .A1(n2584), .B0(n2607), .Y(intadd_1105_A_0_)
);
XNOR2X1TS U3641 ( .A(n2587), .B(n2586), .Y(n2588) );
XNOR2X1TS U3642 ( .A(n2589), .B(n2588), .Y(intadd_1105_B_7_) );
XNOR2X1TS U3643 ( .A(n2591), .B(n2590), .Y(n2592) );
XNOR2X1TS U3644 ( .A(n2593), .B(n2592), .Y(mult_x_311_n15) );
XNOR2X1TS U3645 ( .A(n2595), .B(n2594), .Y(n2596) );
XNOR2X1TS U3646 ( .A(n2597), .B(n2596), .Y(mult_x_311_n18) );
XOR2X1TS U3647 ( .A(n2601), .B(n2600), .Y(mult_x_311_n23) );
XOR2X1TS U3648 ( .A(n2603), .B(n2602), .Y(n2604) );
XOR2X1TS U3649 ( .A(n2605), .B(n2604), .Y(mult_x_311_n30) );
NAND2X1TS U3650 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MY[9]), .Y(n2606) );
XNOR2X1TS U3651 ( .A(n2607), .B(n2606), .Y(n2608) );
XOR2X1TS U3652 ( .A(n2609), .B(n2608), .Y(intadd_1105_B_1_) );
NOR2XLTS U3653 ( .A(n3183), .B(n3257), .Y(intadd_1106_A_8_) );
NOR2XLTS U3654 ( .A(n3180), .B(n972), .Y(n2619) );
NAND2X1TS U3655 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[5]), .Y(n2610) );
INVX2TS U3656 ( .A(n2610), .Y(n2618) );
NOR2XLTS U3657 ( .A(n3183), .B(n3245), .Y(n2617) );
NOR2X2TS U3658 ( .A(n2648), .B(n2610), .Y(n2625) );
NOR2X1TS U3659 ( .A(n2627), .B(n2625), .Y(n2611) );
NAND2X1TS U3660 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MX[3]), .Y(n2624) );
XNOR2X1TS U3661 ( .A(n2613), .B(n2612), .Y(n2615) );
XOR2X1TS U3662 ( .A(n2615), .B(n2614), .Y(n2664) );
OAI2BB1X1TS U3663 ( .A0N(n2665), .A1N(n2667), .B0(n2616), .Y(mult_x_310_n14)
);
CMPR32X2TS U3664 ( .A(n2619), .B(n2618), .C(n2617), .CO(n2665), .S(n2668) );
NAND2X1TS U3665 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[4]), .Y(n2621) );
NAND2X1TS U3666 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MX[5]), .Y(n2620) );
NAND2X1TS U3667 ( .A(n2622), .B(FPMULT_Op_MX[5]), .Y(n2638) );
INVX2TS U3668 ( .A(n2638), .Y(n2646) );
OAI2BB1X1TS U3669 ( .A0N(n2639), .A1N(n2641), .B0(n2623), .Y(n2671) );
XOR2X1TS U3670 ( .A(n2625), .B(n2624), .Y(n2626) );
XNOR2X1TS U3671 ( .A(n2627), .B(n2626), .Y(n2669) );
OAI2BB1X1TS U3672 ( .A0N(n2668), .A1N(n2671), .B0(n2628), .Y(mult_x_310_n17)
);
CMPR32X2TS U3673 ( .A(n2631), .B(n2630), .C(n2629), .CO(n2627), .S(n2673) );
NAND2X1TS U3674 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MX[1]), .Y(n2649) );
INVX2TS U3675 ( .A(n2632), .Y(n2633) );
AOI22X1TS U3676 ( .A0(n2636), .A1(n2635), .B0(n2634), .B1(n2633), .Y(n2652)
);
XOR2X1TS U3677 ( .A(n2639), .B(n2638), .Y(n2640) );
XNOR2X1TS U3678 ( .A(n2641), .B(n2640), .Y(n2675) );
OAI2BB1X1TS U3679 ( .A0N(n2673), .A1N(n2672), .B0(n2642), .Y(mult_x_310_n22)
);
CMPR32X2TS U3680 ( .A(n2645), .B(n2644), .C(n2643), .CO(n2639), .S(n2677) );
NAND2X1TS U3681 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MX[5]), .Y(n2647) );
XOR2X1TS U3682 ( .A(n2650), .B(n2649), .Y(n2651) );
XNOR2X1TS U3683 ( .A(n2652), .B(n2651), .Y(n2676) );
OAI2BB1X1TS U3684 ( .A0N(n2677), .A1N(n2679), .B0(n2653), .Y(mult_x_310_n29)
);
XOR2XLTS U3685 ( .A(n2655), .B(n2654), .Y(n2656) );
XOR2X1TS U3686 ( .A(n2657), .B(n2656), .Y(mult_x_310_n37) );
AOI2BB1XLTS U3687 ( .A0N(n2659), .A1N(n2658), .B0(n2681), .Y(
intadd_1106_A_0_) );
XNOR2X1TS U3688 ( .A(n2661), .B(n2660), .Y(n2662) );
XNOR2X1TS U3689 ( .A(n2663), .B(n2662), .Y(intadd_1106_B_7_) );
XNOR2X1TS U3690 ( .A(n2665), .B(n2664), .Y(n2666) );
XNOR2X1TS U3691 ( .A(n2667), .B(n2666), .Y(mult_x_310_n15) );
XNOR2X1TS U3692 ( .A(n2669), .B(n2668), .Y(n2670) );
XNOR2X1TS U3693 ( .A(n2671), .B(n2670), .Y(mult_x_310_n18) );
XOR2X1TS U3694 ( .A(n2673), .B(n2672), .Y(n2674) );
XOR2X1TS U3695 ( .A(n2675), .B(n2674), .Y(mult_x_310_n23) );
XOR2X1TS U3696 ( .A(n2677), .B(n2676), .Y(n2678) );
XOR2X1TS U3697 ( .A(n2679), .B(n2678), .Y(mult_x_310_n30) );
NAND2X1TS U3698 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[3]), .Y(n2680) );
XNOR2X1TS U3699 ( .A(n2681), .B(n2680), .Y(n2682) );
XNOR2X1TS U3700 ( .A(n2683), .B(n2682), .Y(intadd_1106_B_1_) );
NOR2XLTS U3701 ( .A(FPMULT_FSM_adder_round_norm_load), .B(n3474), .Y(n2684)
);
OAI2BB1X1TS U3702 ( .A0N(FPMULT_FSM_selector_B[0]), .A1N(n2685), .B0(n2684),
.Y(n829) );
NOR2BX1TS U3703 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n3468), .Y(
FPADDSUB_formatted_number_W[30]) );
AOI21X1TS U3704 ( .A0(n2687), .A1(n2686), .B0(
FPMULT_Adder_M_result_A_adder[24]), .Y(
FPMULT_Adder_M_result_A_adder[23]) );
OA21XLTS U3705 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2688), .B0(
n2687), .Y(FPMULT_Adder_M_result_A_adder[22]) );
AOI21X1TS U3706 ( .A0(n2689), .A1(n2690), .B0(n2688), .Y(
FPMULT_Adder_M_result_A_adder[21]) );
OA21XLTS U3707 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n2691), .B0(
n2690), .Y(FPMULT_Adder_M_result_A_adder[20]) );
AOI21X1TS U3708 ( .A0(n2692), .A1(n2693), .B0(n2691), .Y(
FPMULT_Adder_M_result_A_adder[19]) );
OA21XLTS U3709 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n2694), .B0(
n2693), .Y(FPMULT_Adder_M_result_A_adder[18]) );
AOI21X1TS U3710 ( .A0(n2695), .A1(n2696), .B0(n2694), .Y(
FPMULT_Adder_M_result_A_adder[17]) );
OA21XLTS U3711 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n2697), .B0(
n2696), .Y(FPMULT_Adder_M_result_A_adder[16]) );
AOI21X1TS U3712 ( .A0(n2698), .A1(n2699), .B0(n2697), .Y(
FPMULT_Adder_M_result_A_adder[15]) );
OA21XLTS U3713 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n2700), .B0(
n2699), .Y(FPMULT_Adder_M_result_A_adder[14]) );
AOI21X1TS U3714 ( .A0(n2701), .A1(n2702), .B0(n2700), .Y(
FPMULT_Adder_M_result_A_adder[13]) );
OA21XLTS U3715 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n2703), .B0(
n2702), .Y(FPMULT_Adder_M_result_A_adder[12]) );
AOI21X1TS U3716 ( .A0(n2704), .A1(n2705), .B0(n2703), .Y(
FPMULT_Adder_M_result_A_adder[11]) );
OA21XLTS U3717 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n2706), .B0(
n2705), .Y(FPMULT_Adder_M_result_A_adder[10]) );
AOI21X1TS U3718 ( .A0(n2707), .A1(n2708), .B0(n2706), .Y(
FPMULT_Adder_M_result_A_adder[9]) );
OA21XLTS U3719 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n2709), .B0(n2708), .Y(FPMULT_Adder_M_result_A_adder[8]) );
AOI21X1TS U3720 ( .A0(n2710), .A1(n2711), .B0(n2709), .Y(
FPMULT_Adder_M_result_A_adder[7]) );
OA21XLTS U3721 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n2712), .B0(n2711), .Y(FPMULT_Adder_M_result_A_adder[6]) );
AOI21X1TS U3722 ( .A0(n2717), .A1(n2713), .B0(n2712), .Y(
FPMULT_Adder_M_result_A_adder[5]) );
AOI21X1TS U3723 ( .A0(n2715), .A1(n2714), .B0(n2718), .Y(
FPMULT_Adder_M_result_A_adder[3]) );
AO21XLTS U3724 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n2716), .B0(n2715), .Y(FPMULT_Adder_M_result_A_adder[2]) );
AO21XLTS U3725 ( .A0(n2718), .A1(FPMULT_Sgf_normalized_result[4]), .B0(n2717), .Y(FPMULT_Adder_M_result_A_adder[4]) );
NAND2X1TS U3726 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MX[18]), .Y(n2719) );
NOR3X1TS U3727 ( .A(n3217), .B(n3148), .C(n2720), .Y(n2724) );
AOI21X1TS U3728 ( .A0(n2720), .A1(n2719), .B0(n2724), .Y(intadd_1107_A_0_)
);
NOR2XLTS U3729 ( .A(n3214), .B(n3166), .Y(intadd_1107_B_0_) );
NAND2X1TS U3730 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[20]), .Y(n2722) );
NAND2X1TS U3731 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MX[21]), .Y(n2721) );
AOI21X1TS U3732 ( .A0(n2722), .A1(n2721), .B0(mult_x_309_n42), .Y(
intadd_1107_A_1_) );
AOI21X1TS U3733 ( .A0(n2724), .A1(FPMULT_Op_MY[21]), .B0(n2723), .Y(n2726)
);
XNOR2X1TS U3734 ( .A(n2726), .B(n2725), .Y(intadd_1107_B_1_) );
NOR2XLTS U3735 ( .A(n3228), .B(n3162), .Y(n2727) );
CMPR32X2TS U3736 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MY[20]), .C(n2727),
.CO(mult_x_309_n19), .S(mult_x_309_n20) );
NOR2XLTS U3737 ( .A(n3226), .B(n3166), .Y(n2730) );
NOR2XLTS U3738 ( .A(n3228), .B(n3149), .Y(n2729) );
NOR2XLTS U3739 ( .A(n3217), .B(n3162), .Y(n2728) );
CMPR32X2TS U3740 ( .A(n2730), .B(n2729), .C(n2728), .CO(mult_x_309_n24), .S(
mult_x_309_n25) );
AOI21X1TS U3741 ( .A0(n3145), .A1(n3163), .B0(mult_x_309_n26), .Y(
mult_x_309_n27) );
NOR2XLTS U3742 ( .A(n3217), .B(n3149), .Y(n2733) );
NOR2XLTS U3743 ( .A(n3226), .B(n3163), .Y(n2731) );
CMPR32X2TS U3744 ( .A(n2733), .B(n2732), .C(n2731), .CO(mult_x_309_n31), .S(
mult_x_309_n32) );
AOI21X1TS U3745 ( .A0(n3214), .A1(n3148), .B0(mult_x_309_n33), .Y(
mult_x_309_n34) );
NAND2X1TS U3746 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[21]), .Y(n2734) );
OAI32X1TS U3747 ( .A0(mult_x_309_n38), .A1(n3162), .A2(n3214), .B0(n2734),
.B1(mult_x_309_n38), .Y(mult_x_309_n39) );
NAND2X1TS U3748 ( .A(n3117), .B(FPMULT_Op_MX[14]), .Y(n2736) );
NAND2X1TS U3749 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MX[15]), .Y(n2735) );
AOI21X1TS U3750 ( .A0(n2736), .A1(n2735), .B0(mult_x_312_n42), .Y(
intadd_1104_A_1_) );
NAND2X1TS U3751 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MX[12]), .Y(n2738) );
NAND2X1TS U3752 ( .A(n3117), .B(FPMULT_Op_MX[13]), .Y(n2737) );
NAND4XLTS U3753 ( .A(n3117), .B(FPMULT_Op_MY[14]), .C(FPMULT_Op_MX[12]), .D(
FPMULT_Op_MX[13]), .Y(n2743) );
INVX2TS U3754 ( .A(n2743), .Y(n2739) );
AOI21X1TS U3755 ( .A0(n2738), .A1(n2737), .B0(n2739), .Y(intadd_1104_A_0_)
);
NAND2X1TS U3756 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MX[12]), .Y(n2742) );
XNOR2X1TS U3757 ( .A(n2739), .B(n2742), .Y(n2740) );
NAND2X1TS U3758 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MX[13]), .Y(n2741) );
XNOR2X1TS U3759 ( .A(n2740), .B(n2741), .Y(intadd_1104_B_1_) );
AOI21X1TS U3760 ( .A0(n2743), .A1(n2742), .B0(n2741), .Y(intadd_1104_B_2_)
);
NOR2XLTS U3761 ( .A(n3236), .B(n3167), .Y(n2745) );
CMPR32X2TS U3762 ( .A(mult_x_312_n13), .B(n2745), .C(n2744), .CO(
intadd_1104_B_8_), .S(intadd_1104_B_7_) );
NAND2X1TS U3763 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MX[13]), .Y(n2747) );
NAND2X1TS U3764 ( .A(n3117), .B(FPMULT_Op_MX[12]), .Y(n2746) );
AOI21X1TS U3765 ( .A0(n2747), .A1(n2746), .B0(intadd_1104_B_0_), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1) );
NOR2XLTS U3766 ( .A(n3238), .B(n3167), .Y(n2750) );
NOR2XLTS U3767 ( .A(n3227), .B(n3150), .Y(n2749) );
NOR2XLTS U3768 ( .A(n3236), .B(n3168), .Y(n2748) );
CMPR32X2TS U3769 ( .A(n2750), .B(n2749), .C(n2748), .CO(mult_x_312_n19), .S(
mult_x_312_n20) );
NOR2XLTS U3770 ( .A(n3237), .B(n3168), .Y(n2753) );
NOR2XLTS U3771 ( .A(n3236), .B(n3169), .Y(n2751) );
CMPR32X2TS U3772 ( .A(n2753), .B(n2752), .C(n2751), .CO(mult_x_312_n24), .S(
mult_x_312_n25) );
NAND2X1TS U3773 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MX[16]), .Y(n2755) );
NAND2X1TS U3774 ( .A(n3117), .B(FPMULT_Op_MX[17]), .Y(n2754) );
AOI21X1TS U3775 ( .A0(n2755), .A1(n2754), .B0(mult_x_312_n26), .Y(
mult_x_312_n27) );
NOR2XLTS U3776 ( .A(n3238), .B(n3168), .Y(n2758) );
NOR2XLTS U3777 ( .A(n3227), .B(n3152), .Y(n2757) );
NOR2XLTS U3778 ( .A(n3236), .B(n3153), .Y(n2756) );
CMPR32X2TS U3779 ( .A(n2758), .B(n2757), .C(n2756), .CO(mult_x_312_n31), .S(
mult_x_312_n32) );
NAND2X1TS U3780 ( .A(n3117), .B(FPMULT_Op_MX[16]), .Y(n2760) );
NAND2X1TS U3781 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MX[17]), .Y(n2759) );
AOI21X1TS U3782 ( .A0(n2760), .A1(n2759), .B0(mult_x_312_n33), .Y(
mult_x_312_n34) );
NAND2X1TS U3783 ( .A(n3117), .B(FPMULT_Op_MX[15]), .Y(n2762) );
NAND2X1TS U3784 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MX[16]), .Y(n2761) );
AOI21X1TS U3785 ( .A0(n2762), .A1(n2761), .B0(mult_x_312_n38), .Y(
mult_x_312_n39) );
XOR2XLTS U3786 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(FPADDSUB_DmP_EXP_EWSW[27]), .Y(n2763) );
XOR2XLTS U3787 ( .A(intadd_1110_n1), .B(n2763), .Y(
FPADDSUB_Shift_amount_EXP_EW[4]) );
AOI222X4TS U3788 ( .A0(n2911), .A1(n3201), .B0(n2911), .B1(n3321), .C0(n3201), .C1(n3321), .Y(n2916) );
AOI21X1TS U3789 ( .A0(n2921), .A1(n2926), .B0(n2920), .Y(n3469) );
NOR2BX1TS U3790 ( .AN(operation[0]), .B(n3010), .Y(n3475) );
AOI2BB2XLTS U3791 ( .B0(FPSENCOS_cont_var_out[0]), .B1(
FPSENCOS_d_ff3_sign_out), .A0N(FPSENCOS_d_ff3_sign_out), .A1N(
FPSENCOS_cont_var_out[0]), .Y(n2765) );
AOI222X1TS U3792 ( .A0(n3010), .A1(Data_2[31]), .B0(n3030), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n3070), .Y(n2766) );
INVX2TS U3793 ( .A(n2766), .Y(n2767) );
XNOR2X1TS U3794 ( .A(n2768), .B(n2767), .Y(n3370) );
AOI22X1TS U3795 ( .A0(n3310), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n3196), .B1(
FPADDSUB_intDY_EWSW[18]), .Y(n2769) );
AOI22X1TS U3796 ( .A0(n969), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n3306), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n2770) );
AOI22X1TS U3797 ( .A0(n3303), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n3194), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n2771) );
OAI221XLTS U3798 ( .A0(n3303), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n3194), .B1(
FPADDSUB_intDY_EWSW[0]), .C0(n2771), .Y(n2774) );
AOI22X1TS U3799 ( .A0(n3192), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n3308), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n2772) );
OAI221XLTS U3800 ( .A0(n3192), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n3308),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n2772), .Y(n2773) );
NOR4X1TS U3801 ( .A(n2776), .B(n2774), .C(n2775), .D(n2773), .Y(n2803) );
AOI22X1TS U3802 ( .A0(n3318), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n3195), .B1(
FPADDSUB_intDY_EWSW[4]), .Y(n2777) );
OAI221XLTS U3803 ( .A0(n3202), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n3324),
.B1(FPADDSUB_intDY_EWSW[22]), .C0(n2778), .Y(n2783) );
AOI22X1TS U3804 ( .A0(n3304), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n3316), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n2779) );
AOI22X1TS U3805 ( .A0(n3193), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n3307), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n2780) );
OAI221XLTS U3806 ( .A0(n3193), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n3307),
.B1(FPADDSUB_intDY_EWSW[8]), .C0(n2780), .Y(n2781) );
NOR4X1TS U3807 ( .A(n2784), .B(n2783), .C(n2782), .D(n2781), .Y(n2802) );
AOI22X1TS U3808 ( .A0(n3311), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n3197), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n2785) );
OAI221XLTS U3809 ( .A0(n3311), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n3197),
.B1(FPADDSUB_intDY_EWSW[20]), .C0(n2785), .Y(n2800) );
AOI22X1TS U3810 ( .A0(n3305), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n3198), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n2786) );
OAI221XLTS U3811 ( .A0(n3305), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n3198),
.B1(FPADDSUB_intDY_EWSW[24]), .C0(n2786), .Y(n2799) );
OAI22X1TS U3812 ( .A0(n3301), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n3190), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n2787) );
AOI221X1TS U3813 ( .A0(n3301), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[27]), .B1(n3190), .C0(n2787), .Y(n2788) );
OAI22X1TS U3814 ( .A0(n3300), .A1(FPADDSUB_intDX_EWSW[12]), .B0(n3188), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n2789) );
AOI221X1TS U3815 ( .A0(n3300), .A1(FPADDSUB_intDX_EWSW[12]), .B0(
FPADDSUB_intDY_EWSW[2]), .B1(n3188), .C0(n2789), .Y(n2796) );
OAI22X1TS U3816 ( .A0(n3191), .A1(FPADDSUB_intDY_EWSW[7]), .B0(n3189), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n2790) );
AOI221X1TS U3817 ( .A0(n3191), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDY_EWSW[9]), .B1(n3189), .C0(n2790), .Y(n2795) );
OAI22X1TS U3818 ( .A0(n3299), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n3298), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n2791) );
AOI221X1TS U3819 ( .A0(n3299), .A1(FPADDSUB_intDY_EWSW[10]), .B0(
FPADDSUB_intDY_EWSW[11]), .B1(n3298), .C0(n2791), .Y(n2794) );
OAI22X1TS U3820 ( .A0(n3302), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n3186), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n2792) );
AOI221X1TS U3821 ( .A0(n3302), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n3186), .C0(n2792), .Y(n2793) );
NAND4XLTS U3822 ( .A(n2796), .B(n2795), .C(n2794), .D(n2793), .Y(n2797) );
NOR4X1TS U3823 ( .A(n2797), .B(n2799), .C(n2798), .D(n2800), .Y(n2801) );
AOI22X1TS U3826 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n3319), .Y(n2805) );
AOI32X1TS U3827 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(n2807), .A2(
FPMULT_FS_Module_state_reg[3]), .B0(n2805), .B1(n2807), .Y(n3500) );
AOI32X1TS U3828 ( .A0(FPMULT_FS_Module_state_reg[3]), .A1(n3165), .A2(n3343),
.B0(n3147), .B1(FPMULT_FS_Module_state_reg[0]), .Y(n2809) );
AOI22X1TS U3829 ( .A0(n2854), .A1(FPMULT_Add_result[22]), .B0(n955), .B1(
FPMULT_Add_result[23]), .Y(n2811) );
AOI22X1TS U3830 ( .A0(n2808), .A1(FPMULT_P_Sgf[46]), .B0(n957), .B1(
FPMULT_P_Sgf[45]), .Y(n2810) );
NAND2X1TS U3831 ( .A(n2811), .B(n2810), .Y(n3499) );
AOI22X1TS U3832 ( .A0(n2854), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Add_result[22]), .B1(n954), .Y(n2813) );
AOI22X1TS U3833 ( .A0(n2808), .A1(FPMULT_P_Sgf[45]), .B0(n956), .B1(
FPMULT_P_Sgf[44]), .Y(n2812) );
NAND2X1TS U3834 ( .A(n2813), .B(n2812), .Y(n3498) );
AOI22X1TS U3835 ( .A0(n2854), .A1(FPMULT_Add_result[20]), .B0(n955), .B1(
FPMULT_Add_result[21]), .Y(n2815) );
AOI22X1TS U3836 ( .A0(n2808), .A1(FPMULT_P_Sgf[44]), .B0(n957), .B1(
FPMULT_P_Sgf[43]), .Y(n2814) );
NAND2X1TS U3837 ( .A(n2815), .B(n2814), .Y(n3497) );
AOI22X1TS U3838 ( .A0(n2854), .A1(FPMULT_Add_result[19]), .B0(n954), .B1(
FPMULT_Add_result[20]), .Y(n2817) );
AOI22X1TS U3839 ( .A0(n2808), .A1(FPMULT_P_Sgf[43]), .B0(n956), .B1(
FPMULT_P_Sgf[42]), .Y(n2816) );
NAND2X1TS U3840 ( .A(n2817), .B(n2816), .Y(n3496) );
AOI22X1TS U3841 ( .A0(n2854), .A1(FPMULT_Add_result[18]), .B0(n955), .B1(
FPMULT_Add_result[19]), .Y(n2819) );
AOI22X1TS U3842 ( .A0(n2808), .A1(FPMULT_P_Sgf[42]), .B0(n957), .B1(
FPMULT_P_Sgf[41]), .Y(n2818) );
NAND2X1TS U3843 ( .A(n2819), .B(n2818), .Y(n3495) );
AOI22X1TS U3844 ( .A0(n2854), .A1(FPMULT_Add_result[17]), .B0(n954), .B1(
FPMULT_Add_result[18]), .Y(n2821) );
AOI22X1TS U3845 ( .A0(n2808), .A1(FPMULT_P_Sgf[41]), .B0(n956), .B1(
FPMULT_P_Sgf[40]), .Y(n2820) );
NAND2X1TS U3846 ( .A(n2821), .B(n2820), .Y(n3494) );
AOI22X1TS U3847 ( .A0(n2854), .A1(FPMULT_Add_result[16]), .B0(n955), .B1(
FPMULT_Add_result[17]), .Y(n2823) );
AOI22X1TS U3848 ( .A0(n2808), .A1(FPMULT_P_Sgf[40]), .B0(n957), .B1(
FPMULT_P_Sgf[39]), .Y(n2822) );
NAND2X1TS U3849 ( .A(n2823), .B(n2822), .Y(n3493) );
AOI22X1TS U3850 ( .A0(n2854), .A1(FPMULT_Add_result[15]), .B0(n954), .B1(
FPMULT_Add_result[16]), .Y(n2825) );
AOI22X1TS U3851 ( .A0(n2808), .A1(FPMULT_P_Sgf[39]), .B0(n956), .B1(
FPMULT_P_Sgf[38]), .Y(n2824) );
NAND2X1TS U3852 ( .A(n2825), .B(n2824), .Y(n3492) );
AOI22X1TS U3853 ( .A0(n2854), .A1(FPMULT_Add_result[14]), .B0(n955), .B1(
FPMULT_Add_result[15]), .Y(n2827) );
AOI22X1TS U3854 ( .A0(n2808), .A1(FPMULT_P_Sgf[38]), .B0(n957), .B1(
FPMULT_P_Sgf[37]), .Y(n2826) );
NAND2X1TS U3855 ( .A(n2827), .B(n2826), .Y(n3491) );
AOI22X1TS U3856 ( .A0(n965), .A1(FPMULT_Add_result[13]), .B0(n954), .B1(
FPMULT_Add_result[14]), .Y(n2829) );
AOI22X1TS U3857 ( .A0(n2808), .A1(FPMULT_P_Sgf[37]), .B0(n956), .B1(
FPMULT_P_Sgf[36]), .Y(n2828) );
NAND2X1TS U3858 ( .A(n2829), .B(n2828), .Y(n3490) );
AOI22X1TS U3859 ( .A0(n965), .A1(FPMULT_Add_result[12]), .B0(n955), .B1(
FPMULT_Add_result[13]), .Y(n2831) );
AOI22X1TS U3860 ( .A0(n2808), .A1(FPMULT_P_Sgf[36]), .B0(n957), .B1(
FPMULT_P_Sgf[35]), .Y(n2830) );
NAND2X1TS U3861 ( .A(n2831), .B(n2830), .Y(n3489) );
AOI22X1TS U3862 ( .A0(n965), .A1(FPMULT_Add_result[11]), .B0(n954), .B1(
FPMULT_Add_result[12]), .Y(n2833) );
AOI22X1TS U3863 ( .A0(n2808), .A1(FPMULT_P_Sgf[35]), .B0(n956), .B1(
FPMULT_P_Sgf[34]), .Y(n2832) );
NAND2X1TS U3864 ( .A(n2833), .B(n2832), .Y(n3488) );
AOI22X1TS U3865 ( .A0(n965), .A1(FPMULT_Add_result[10]), .B0(n955), .B1(
FPMULT_Add_result[11]), .Y(n2835) );
AOI22X1TS U3866 ( .A0(n964), .A1(FPMULT_P_Sgf[34]), .B0(n957), .B1(
FPMULT_P_Sgf[33]), .Y(n2834) );
NAND2X1TS U3867 ( .A(n2835), .B(n2834), .Y(n3487) );
AOI22X1TS U3868 ( .A0(n965), .A1(FPMULT_Add_result[9]), .B0(n954), .B1(
FPMULT_Add_result[10]), .Y(n2837) );
AOI22X1TS U3869 ( .A0(n964), .A1(FPMULT_P_Sgf[33]), .B0(n956), .B1(
FPMULT_P_Sgf[32]), .Y(n2836) );
NAND2X1TS U3870 ( .A(n2837), .B(n2836), .Y(n3486) );
AOI22X1TS U3871 ( .A0(n965), .A1(FPMULT_Add_result[8]), .B0(n955), .B1(
FPMULT_Add_result[9]), .Y(n2839) );
AOI22X1TS U3872 ( .A0(n964), .A1(FPMULT_P_Sgf[32]), .B0(n957), .B1(
FPMULT_P_Sgf[31]), .Y(n2838) );
NAND2X1TS U3873 ( .A(n2839), .B(n2838), .Y(n3485) );
AOI22X1TS U3874 ( .A0(n965), .A1(FPMULT_Add_result[7]), .B0(n954), .B1(
FPMULT_Add_result[8]), .Y(n2841) );
AOI22X1TS U3875 ( .A0(n964), .A1(FPMULT_P_Sgf[31]), .B0(n956), .B1(
FPMULT_P_Sgf[30]), .Y(n2840) );
NAND2X1TS U3876 ( .A(n2841), .B(n2840), .Y(n3484) );
AOI22X1TS U3877 ( .A0(n965), .A1(FPMULT_Add_result[6]), .B0(n955), .B1(
FPMULT_Add_result[7]), .Y(n2843) );
AOI22X1TS U3878 ( .A0(n964), .A1(FPMULT_P_Sgf[30]), .B0(n957), .B1(
FPMULT_P_Sgf[29]), .Y(n2842) );
NAND2X1TS U3879 ( .A(n2843), .B(n2842), .Y(n3483) );
AOI22X1TS U3880 ( .A0(n965), .A1(FPMULT_Add_result[5]), .B0(n954), .B1(
FPMULT_Add_result[6]), .Y(n2845) );
AOI22X1TS U3881 ( .A0(n964), .A1(FPMULT_P_Sgf[29]), .B0(n956), .B1(
FPMULT_P_Sgf[28]), .Y(n2844) );
NAND2X1TS U3882 ( .A(n2845), .B(n2844), .Y(n3482) );
AOI22X1TS U3883 ( .A0(n965), .A1(FPMULT_Add_result[4]), .B0(n955), .B1(
FPMULT_Add_result[5]), .Y(n2847) );
AOI22X1TS U3884 ( .A0(n964), .A1(FPMULT_P_Sgf[28]), .B0(n957), .B1(
FPMULT_P_Sgf[27]), .Y(n2846) );
NAND2X1TS U3885 ( .A(n2847), .B(n2846), .Y(n3481) );
AOI22X1TS U3886 ( .A0(n965), .A1(FPMULT_Add_result[3]), .B0(n954), .B1(
FPMULT_Add_result[4]), .Y(n2849) );
AOI22X1TS U3887 ( .A0(n964), .A1(FPMULT_P_Sgf[27]), .B0(n956), .B1(
FPMULT_P_Sgf[26]), .Y(n2848) );
NAND2X1TS U3888 ( .A(n2849), .B(n2848), .Y(n3480) );
AOI22X1TS U3889 ( .A0(n965), .A1(FPMULT_Add_result[2]), .B0(n955), .B1(
FPMULT_Add_result[3]), .Y(n2851) );
AOI22X1TS U3890 ( .A0(n964), .A1(FPMULT_P_Sgf[26]), .B0(n957), .B1(
FPMULT_P_Sgf[25]), .Y(n2850) );
NAND2X1TS U3891 ( .A(n2851), .B(n2850), .Y(n3479) );
AOI22X1TS U3892 ( .A0(n2854), .A1(FPMULT_Add_result[1]), .B0(n954), .B1(
FPMULT_Add_result[2]), .Y(n2853) );
AOI22X1TS U3893 ( .A0(n2808), .A1(FPMULT_P_Sgf[25]), .B0(n956), .B1(
FPMULT_P_Sgf[24]), .Y(n2852) );
NAND2X1TS U3894 ( .A(n2853), .B(n2852), .Y(n3478) );
AOI22X1TS U3895 ( .A0(n2854), .A1(FPMULT_Add_result[0]), .B0(n955), .B1(
FPMULT_Add_result[1]), .Y(n2856) );
AOI22X1TS U3896 ( .A0(n2808), .A1(FPMULT_P_Sgf[24]), .B0(n957), .B1(
FPMULT_P_Sgf[23]), .Y(n2855) );
NAND2X1TS U3897 ( .A(n2856), .B(n2855), .Y(n3477) );
AOI22X1TS U3898 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2857), .B1(n3317),
.Y(n3476) );
XOR2XLTS U3899 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n3371) );
INVX2TS U3900 ( .A(n2858), .Y(n3015) );
AOI2BB1XLTS U3901 ( .A0N(n3461), .A1N(underflow_flag_mult), .B0(n3015), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
AOI32X1TS U3902 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n2859), .A2(n3242),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n2859), .Y(
FPSENCOS_data_out_LUT[4]) );
OAI22X1TS U3903 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3096), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n3097), .Y(FPSENCOS_data_out_LUT[25])
);
NOR4X1TS U3904 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n2866) );
NOR4X1TS U3905 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n2865) );
NOR4X1TS U3906 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n2863) );
NOR3XLTS U3907 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n2862) );
NOR4X1TS U3908 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n2861) );
NOR4X1TS U3909 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n2860) );
AND4X1TS U3910 ( .A(n2863), .B(n2862), .C(n2861), .D(n2860), .Y(n2864) );
NAND4XLTS U3911 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n2868) );
NAND4XLTS U3912 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(n933), .Y(
n2867) );
NOR3X1TS U3913 ( .A(n3457), .B(n2868), .C(n2867), .Y(n2873) );
NOR4X1TS U3914 ( .A(dataB[30]), .B(n934), .C(dataB[28]), .D(dataB[23]), .Y(
n2870) );
NOR3XLTS U3915 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n2869) );
NAND4XLTS U3916 ( .A(n2873), .B(operation_reg[1]), .C(n2870), .D(n2869), .Y(
n2871) );
NOR3XLTS U3917 ( .A(operation_reg[0]), .B(dataB[31]), .C(n2871), .Y(n2872)
);
OAI211XLTS U3918 ( .A0(dataB[27]), .A1(n2872), .B0(n3456), .C0(n3455), .Y(
n2883) );
NOR4BX1TS U3919 ( .AN(operation_reg[1]), .B(dataA[31]), .C(n933), .D(
dataA[25]), .Y(n2875) );
NOR4X1TS U3920 ( .A(n3457), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n2874) );
NOR2BX1TS U3921 ( .AN(n2873), .B(operation_reg[1]), .Y(n2881) );
AOI31XLTS U3922 ( .A0(n2876), .A1(n2875), .A2(n2874), .B0(n2881), .Y(n2879)
);
NAND3XLTS U3923 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n2878) );
NAND4XLTS U3924 ( .A(dataB[30]), .B(n934), .C(dataB[26]), .D(dataB[29]), .Y(
n2877) );
OAI31X1TS U3925 ( .A0(n2879), .A1(n2878), .A2(n2877), .B0(dataB[27]), .Y(
n2880) );
NAND4XLTS U3926 ( .A(n3460), .B(n3459), .C(n3458), .D(n2880), .Y(n2882) );
OAI2BB2XLTS U3927 ( .B0(n2883), .B1(n2882), .A0N(n2881), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NAND2X1TS U3928 ( .A(FPADDSUB_N59), .B(n2920), .Y(n2884) );
XNOR2X1TS U3929 ( .A(n2884), .B(FPADDSUB_N60), .Y(FPADDSUB_Raw_mant_SGF[1])
);
OAI21XLTS U3930 ( .A0(FPADDSUB_DMP_SFG[0]), .A1(FPADDSUB_DmP_mant_SFG_SWR[2]), .B0(n2885), .Y(n2888) );
NAND2X1TS U3931 ( .A(n2886), .B(n2920), .Y(n2887) );
XOR2XLTS U3932 ( .A(n2888), .B(n2887), .Y(FPADDSUB_Raw_mant_SGF[2]) );
AOI22X1TS U3933 ( .A0(n908), .A1(n2890), .B0(n2889), .B1(n3452), .Y(n2893)
);
OAI21XLTS U3934 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n3176), .B0(n2891),
.Y(n2892) );
AOI22X1TS U3935 ( .A0(n908), .A1(n2895), .B0(n2894), .B1(n3452), .Y(n2898)
);
OAI21XLTS U3936 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n3182), .B0(n2896),
.Y(n2897) );
AOI22X1TS U3937 ( .A0(n908), .A1(n2900), .B0(n2899), .B1(n2924), .Y(n2903)
);
AOI22X1TS U3938 ( .A0(n908), .A1(n2905), .B0(n2904), .B1(n3452), .Y(n2908)
);
OAI22X1TS U3939 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(n3320), .B0(n2910),
.B1(n2909), .Y(n2914) );
AOI22X1TS U3940 ( .A0(n908), .A1(n2914), .B0(n2911), .B1(n3452), .Y(n2913)
);
NAND2X1TS U3941 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n3201), .Y(n2915) );
NOR2X1TS U3942 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n3328), .Y(n2923) );
AOI21X1TS U3943 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n3328), .B0(n2923),
.Y(n2918) );
AOI22X1TS U3944 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n3321), .B0(n2915), .B1(
n2914), .Y(n2919) );
AOI22X1TS U3945 ( .A0(n908), .A1(n2919), .B0(n2916), .B1(n2924), .Y(n2917)
);
AOI21X1TS U3946 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n3328), .B0(n2919),
.Y(n2922) );
NAND2X1TS U3947 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[1]), .B(
FPSENCOS_d_ff1_operation_out), .Y(n2929) );
XOR2X1TS U3948 ( .A(n970), .B(n2927), .Y(n2928) );
BUFX3TS U3949 ( .A(n2962), .Y(n2961) );
AOI22X1TS U3950 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[31]), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n2961), .Y(n2931) );
XNOR2X1TS U3951 ( .A(n2931), .B(n2930), .Y(FPSENCOS_fmtted_Result_31_) );
AOI22X1TS U3952 ( .A0(n2932), .A1(n3357), .B0(n3194), .B1(n2938), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U3953 ( .A0(n2934), .A1(n3354), .B0(n3303), .B1(n2941), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U3954 ( .A0(n2934), .A1(n3337), .B0(n3188), .B1(n2941), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
AOI22X1TS U3955 ( .A0(n2932), .A1(n3356), .B0(n3308), .B1(n2941), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
AOI22X1TS U3956 ( .A0(n2939), .A1(n3335), .B0(n3195), .B1(n2933), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
BUFX3TS U3957 ( .A(n2938), .Y(n2937) );
AOI22X1TS U3958 ( .A0(n2934), .A1(n3330), .B0(n3318), .B1(n2937), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U3959 ( .A0(n2935), .A1(n3333), .B0(n3306), .B1(n2933), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U3960 ( .A0(n2939), .A1(n3329), .B0(n3191), .B1(n2933), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U3961 ( .A0(n2934), .A1(n3352), .B0(n3307), .B1(n2933), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U3962 ( .A0(n2935), .A1(n3339), .B0(n3189), .B1(n2933), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U3963 ( .A0(n2934), .A1(n3332), .B0(n3299), .B1(n2933), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U3964 ( .A0(n2934), .A1(n3348), .B0(n3298), .B1(n2933), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U3965 ( .A0(n2934), .A1(n3300), .B0(n3331), .B1(n2941), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
BUFX3TS U3966 ( .A(n2938), .Y(n2940) );
AOI22X1TS U3967 ( .A0(n2932), .A1(n3336), .B0(n3186), .B1(n2940), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U3968 ( .A0(n2934), .A1(n3203), .B0(n3322), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U3969 ( .A0(n2932), .A1(n3349), .B0(n3302), .B1(n2940), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U3970 ( .A0(n2934), .A1(n3334), .B0(n3316), .B1(n2938), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
AOI22X1TS U3971 ( .A0(n2932), .A1(n3350), .B0(n3304), .B1(n2938), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U3972 ( .A0(n2934), .A1(n3353), .B0(n3196), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U3973 ( .A0(n2932), .A1(n3205), .B0(n3301), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U3974 ( .A0(n2934), .A1(n3342), .B0(n3197), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U3975 ( .A0(n2932), .A1(n3341), .B0(n3193), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U3976 ( .A0(n2934), .A1(n3207), .B0(n3324), .B1(n2938), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U3977 ( .A0(n2932), .A1(n3358), .B0(n3202), .B1(n2937), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U3978 ( .A0(n2934), .A1(n3338), .B0(n3198), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U3979 ( .A0(n2932), .A1(n3351), .B0(n3305), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U3980 ( .A0(n2934), .A1(n3355), .B0(n3192), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U3981 ( .A0(n2932), .A1(n3340), .B0(n3190), .B1(n2936), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U3982 ( .A0(n2934), .A1(n3194), .B0(n3357), .B1(n2936), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U3983 ( .A0(n2932), .A1(n3303), .B0(n3354), .B1(n2936), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U3984 ( .A0(n2935), .A1(n3188), .B0(n3337), .B1(n2936), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U3985 ( .A0(n2935), .A1(n3308), .B0(n3356), .B1(n2936), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U3986 ( .A0(n2935), .A1(n3195), .B0(n3335), .B1(n2936), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U3987 ( .A0(n2935), .A1(n3318), .B0(n3330), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U3988 ( .A0(n2935), .A1(n3306), .B0(n3333), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U3989 ( .A0(n2935), .A1(n3191), .B0(n3329), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U3990 ( .A0(n2935), .A1(n3307), .B0(n3352), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U3991 ( .A0(n2935), .A1(n3189), .B0(n3339), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U3992 ( .A0(n2935), .A1(n3299), .B0(n3332), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U3993 ( .A0(n2935), .A1(n3298), .B0(n3348), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U3994 ( .A0(n2935), .A1(n3331), .B0(n3300), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U3995 ( .A0(n2935), .A1(n3186), .B0(n3336), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U3996 ( .A0(n2935), .A1(n3322), .B0(n3203), .B1(n2940), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
AOI22X1TS U3997 ( .A0(n2939), .A1(n3302), .B0(n3349), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U3998 ( .A0(n2939), .A1(n3316), .B0(n3334), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U3999 ( .A0(n2939), .A1(n3304), .B0(n3350), .B1(n2936), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U4000 ( .A0(n2939), .A1(n3196), .B0(n3353), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U4001 ( .A0(n2939), .A1(n3301), .B0(n3205), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U4002 ( .A0(n2939), .A1(n3197), .B0(n3342), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U4003 ( .A0(n2939), .A1(n3193), .B0(n3341), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U4004 ( .A0(n2939), .A1(n3324), .B0(n3207), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U4005 ( .A0(n2939), .A1(n3202), .B0(n3358), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U4006 ( .A0(n2939), .A1(n3198), .B0(n3338), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U4007 ( .A0(n2939), .A1(n3305), .B0(n3351), .B1(n2937), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U4008 ( .A0(n2939), .A1(n3192), .B0(n3355), .B1(n2938), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U4009 ( .A0(n2939), .A1(n3190), .B0(n3340), .B1(n2938), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U4010 ( .B0(n2941), .B1(n1972), .A0N(n2941), .A1N(
FPADDSUB_intDY_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U4011 ( .B0(n2941), .B1(n3311), .A0N(n2940), .A1N(
FPADDSUB_intDY_EWSW[30]), .Y(FPADDSUB_DMP_INIT_EWSW[30]) );
OAI22X1TS U4012 ( .A0(n2942), .A1(n2944), .B0(n2945), .B1(n928), .Y(
FPADDSUB_Data_array_SWR[24]) );
OAI222X1TS U4013 ( .A0(n2386), .A1(n2945), .B0(n2944), .B1(n2943), .C0(n928),
.C1(n2942), .Y(FPADDSUB_Data_array_SWR[23]) );
NAND3BX1TS U4014 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n2948), .Y(n3104) );
NAND2X1TS U4015 ( .A(n3104), .B(n2982), .Y(FPSENCOS_enab_d_ff5_data_out) );
CLKAND2X2TS U4016 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
CLKAND2X2TS U4017 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
CLKAND2X2TS U4018 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U4019 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U4020 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U4021 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U4022 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
CLKAND2X2TS U4023 ( .A(n963), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
NOR2BX1TS U4024 ( .AN(FPMULT_Sgf_normalized_result[2]), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
NOR2BX1TS U4025 ( .AN(FPMULT_Sgf_normalized_result[4]), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
NOR2BX1TS U4026 ( .AN(FPMULT_Sgf_normalized_result[6]), .B(n2950), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
NOR2BX1TS U4027 ( .AN(FPMULT_Sgf_normalized_result[8]), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
NOR2BX1TS U4028 ( .AN(FPMULT_Sgf_normalized_result[10]), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
NOR2BX1TS U4029 ( .AN(FPMULT_Sgf_normalized_result[12]), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
NOR2BX1TS U4030 ( .AN(FPMULT_Sgf_normalized_result[14]), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
NOR2BX1TS U4031 ( .AN(FPMULT_Sgf_normalized_result[16]), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
NOR2BX1TS U4032 ( .AN(FPMULT_Sgf_normalized_result[18]), .B(n2951), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
NOR2BX1TS U4033 ( .AN(FPMULT_Sgf_normalized_result[20]), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
NOR2BX1TS U4034 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n2949), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
INVX4TS U4035 ( .A(n2955), .Y(n2960) );
NOR2BX1TS U4036 ( .AN(FPSENCOS_d_ff_Xn[0]), .B(n2960), .Y(
FPSENCOS_first_mux_X[0]) );
NOR2BX1TS U4037 ( .AN(FPSENCOS_d_ff_Xn[4]), .B(n2960), .Y(
FPSENCOS_first_mux_X[4]) );
INVX4TS U4038 ( .A(n2955), .Y(n2958) );
NOR2BX1TS U4039 ( .AN(FPSENCOS_d_ff_Xn[8]), .B(n2958), .Y(
FPSENCOS_first_mux_X[8]) );
NOR2BX1TS U4040 ( .AN(FPSENCOS_d_ff_Xn[9]), .B(n2958), .Y(
FPSENCOS_first_mux_X[9]) );
INVX4TS U4041 ( .A(n2955), .Y(n2953) );
NOR2BX1TS U4042 ( .AN(FPSENCOS_d_ff_Xn[11]), .B(n2953), .Y(
FPSENCOS_first_mux_X[11]) );
INVX4TS U4043 ( .A(n2955), .Y(n2952) );
NOR2BX1TS U4044 ( .AN(FPSENCOS_d_ff_Xn[15]), .B(n2952), .Y(
FPSENCOS_first_mux_X[15]) );
NOR2BX1TS U4045 ( .AN(FPSENCOS_d_ff_Xn[18]), .B(n2953), .Y(
FPSENCOS_first_mux_X[18]) );
NOR2BX1TS U4046 ( .AN(FPSENCOS_d_ff_Xn[21]), .B(n2952), .Y(
FPSENCOS_first_mux_X[21]) );
INVX4TS U4047 ( .A(n2955), .Y(n2957) );
NOR2BX1TS U4048 ( .AN(FPSENCOS_d_ff_Xn[22]), .B(n2957), .Y(
FPSENCOS_first_mux_X[22]) );
NOR2BX1TS U4049 ( .AN(FPSENCOS_d_ff_Xn[23]), .B(n2957), .Y(
FPSENCOS_first_mux_X[23]) );
NOR2BX1TS U4050 ( .AN(FPSENCOS_d_ff_Xn[30]), .B(n2953), .Y(
FPSENCOS_first_mux_X[30]) );
NOR2BX1TS U4051 ( .AN(FPSENCOS_d_ff_Xn[31]), .B(n2952), .Y(
FPSENCOS_first_mux_X[31]) );
NOR2BX1TS U4052 ( .AN(FPSENCOS_d_ff_Yn[0]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[0]) );
NOR2BX1TS U4053 ( .AN(FPSENCOS_d_ff_Yn[1]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[1]) );
NOR2BX1TS U4054 ( .AN(FPSENCOS_d_ff_Yn[2]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[2]) );
NOR2BX1TS U4055 ( .AN(FPSENCOS_d_ff_Yn[3]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[3]) );
NOR2BX1TS U4056 ( .AN(FPSENCOS_d_ff_Yn[4]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[4]) );
NOR2BX1TS U4057 ( .AN(FPSENCOS_d_ff_Yn[5]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[5]) );
NOR2BX1TS U4058 ( .AN(FPSENCOS_d_ff_Yn[6]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[6]) );
NOR2BX1TS U4059 ( .AN(FPSENCOS_d_ff_Yn[7]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[7]) );
NOR2BX1TS U4060 ( .AN(FPSENCOS_d_ff_Yn[8]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[8]) );
NOR2BX1TS U4061 ( .AN(FPSENCOS_d_ff_Yn[9]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[9]) );
NOR2BX1TS U4062 ( .AN(FPSENCOS_d_ff_Yn[10]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[10]) );
NOR2BX1TS U4063 ( .AN(FPSENCOS_d_ff_Yn[11]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[11]) );
NOR2BX1TS U4064 ( .AN(FPSENCOS_d_ff_Yn[12]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[12]) );
NOR2BX1TS U4065 ( .AN(FPSENCOS_d_ff_Yn[13]), .B(n2958), .Y(
FPSENCOS_first_mux_Y[13]) );
NOR2BX1TS U4066 ( .AN(FPSENCOS_d_ff_Yn[14]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[14]) );
NOR2BX1TS U4067 ( .AN(FPSENCOS_d_ff_Yn[15]), .B(n2958), .Y(
FPSENCOS_first_mux_Y[15]) );
NOR2BX1TS U4068 ( .AN(FPSENCOS_d_ff_Yn[16]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[16]) );
NOR2BX1TS U4069 ( .AN(FPSENCOS_d_ff_Yn[17]), .B(n2958), .Y(
FPSENCOS_first_mux_Y[17]) );
NOR2BX1TS U4070 ( .AN(FPSENCOS_d_ff_Yn[18]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[18]) );
NOR2BX1TS U4071 ( .AN(FPSENCOS_d_ff_Yn[19]), .B(n2958), .Y(
FPSENCOS_first_mux_Y[19]) );
NOR2BX1TS U4072 ( .AN(FPSENCOS_d_ff_Yn[20]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[20]) );
NOR2BX1TS U4073 ( .AN(FPSENCOS_d_ff_Yn[21]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[21]) );
NOR2BX1TS U4074 ( .AN(FPSENCOS_d_ff_Yn[22]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[22]) );
NOR2BX1TS U4075 ( .AN(FPSENCOS_d_ff_Yn[23]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[23]) );
NOR2BX1TS U4076 ( .AN(FPSENCOS_d_ff_Yn[24]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[24]) );
NOR2BX1TS U4077 ( .AN(FPSENCOS_d_ff_Yn[25]), .B(n2958), .Y(
FPSENCOS_first_mux_Y[25]) );
NOR2BX1TS U4078 ( .AN(FPSENCOS_d_ff_Yn[26]), .B(n2952), .Y(
FPSENCOS_first_mux_Y[26]) );
NOR2BX1TS U4079 ( .AN(FPSENCOS_d_ff_Yn[27]), .B(n2958), .Y(
FPSENCOS_first_mux_Y[27]) );
NOR2BX1TS U4080 ( .AN(FPSENCOS_d_ff_Yn[28]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[28]) );
NOR2BX1TS U4081 ( .AN(FPSENCOS_d_ff_Yn[29]), .B(n2958), .Y(
FPSENCOS_first_mux_Y[29]) );
NOR2BX1TS U4082 ( .AN(FPSENCOS_d_ff_Yn[30]), .B(n2953), .Y(
FPSENCOS_first_mux_Y[30]) );
NOR2BX1TS U4083 ( .AN(FPSENCOS_d_ff_Yn[31]), .B(n2958), .Y(
FPSENCOS_first_mux_Y[31]) );
AO22XLTS U4084 ( .A0(n2954), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
AO22XLTS U4085 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n2955), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
AO22XLTS U4086 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n2955), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
AO22XLTS U4087 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n2955), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
BUFX3TS U4088 ( .A(n2956), .Y(n2959) );
AO22XLTS U4089 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
AO22XLTS U4090 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
AO22XLTS U4091 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
AO22XLTS U4092 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
AO22XLTS U4093 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
AO22XLTS U4094 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
AO22XLTS U4095 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
AO22XLTS U4096 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
AO22XLTS U4097 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO22XLTS U4098 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
AO22XLTS U4099 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
AO22XLTS U4100 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
AO22XLTS U4101 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
AO22XLTS U4102 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
AO22XLTS U4103 ( .A0(n2958), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
AO22XLTS U4104 ( .A0(n2958), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
AO22XLTS U4105 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
AO22XLTS U4106 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22XLTS U4107 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
AO22XLTS U4108 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
AO22XLTS U4109 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AO22XLTS U4110 ( .A0(n2958), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
AO22XLTS U4111 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22XLTS U4112 ( .A0(n2958), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n2956), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
AO22XLTS U4113 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n2955), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
AO22XLTS U4114 ( .A0(n2957), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n2955), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
AO22XLTS U4115 ( .A0(n2958), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n2955), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
AO22XLTS U4116 ( .A0(n2960), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n2959), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
BUFX3TS U4117 ( .A(n2961), .Y(n2964) );
AO22XLTS U4118 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[0]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(FPSENCOS_mux_sal[0]) );
AO22XLTS U4119 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[1]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(FPSENCOS_mux_sal[1]) );
AO22XLTS U4120 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[2]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(FPSENCOS_mux_sal[2]) );
AO22XLTS U4121 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[3]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22XLTS U4122 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[4]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(FPSENCOS_mux_sal[4]) );
AO22XLTS U4123 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[5]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(FPSENCOS_mux_sal[5]) );
AO22XLTS U4124 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[6]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(FPSENCOS_mux_sal[6]) );
AO22XLTS U4125 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[7]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(FPSENCOS_mux_sal[7]) );
AO22XLTS U4126 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[8]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(FPSENCOS_mux_sal[8]) );
AO22XLTS U4127 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[9]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(FPSENCOS_mux_sal[9]) );
AO22XLTS U4128 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[10]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(FPSENCOS_mux_sal[10]) );
AO22XLTS U4129 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[11]), .B0(n2962), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(FPSENCOS_mux_sal[11]) );
AO22XLTS U4130 ( .A0(n2963), .A1(FPSENCOS_d_ff_Yn[12]), .B0(n2962), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(FPSENCOS_mux_sal[12]) );
INVX2TS U4131 ( .A(n2962), .Y(n2963) );
AO22XLTS U4132 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[13]), .B0(n2962), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(FPSENCOS_mux_sal[13]) );
AO22XLTS U4133 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[14]), .B0(n2962), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(FPSENCOS_mux_sal[14]) );
AO22XLTS U4134 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[15]), .B0(n2962), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(FPSENCOS_mux_sal[15]) );
AO22XLTS U4135 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[16]), .B0(n2962), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(FPSENCOS_mux_sal[16]) );
AO22XLTS U4136 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[17]), .B0(n2962), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(FPSENCOS_mux_sal[17]) );
AO22XLTS U4137 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[18]), .B0(n2961), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(FPSENCOS_mux_sal[18]) );
AO22XLTS U4138 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[19]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22XLTS U4139 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[20]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(FPSENCOS_mux_sal[20]) );
AO22XLTS U4140 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[21]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(FPSENCOS_mux_sal[21]) );
AO22XLTS U4141 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[22]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(FPSENCOS_mux_sal[22]) );
AO22XLTS U4142 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[23]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(FPSENCOS_mux_sal[23]) );
AO22XLTS U4143 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[24]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(FPSENCOS_mux_sal[24]) );
AO22XLTS U4144 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[25]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22XLTS U4145 ( .A0(n952), .A1(FPSENCOS_d_ff_Yn[26]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(FPSENCOS_mux_sal[26]) );
INVX2TS U4146 ( .A(n2961), .Y(n2965) );
AO22XLTS U4147 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[27]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22XLTS U4148 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[28]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(FPSENCOS_mux_sal[28]) );
AO22XLTS U4149 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[29]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22XLTS U4150 ( .A0(n2965), .A1(FPSENCOS_d_ff_Yn[30]), .B0(n2964), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(FPSENCOS_mux_sal[30]) );
NOR3BXLTS U4151 ( .AN(n2966), .B(n3165), .C(FPMULT_FS_Module_state_reg[3]),
.Y(FPMULT_FSM_first_phase_load) );
AO21XLTS U4152 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(n2968), .B0(n2967),
.Y(FPMULT_FS_Module_state_next[2]) );
NAND2X1TS U4153 ( .A(n2970), .B(n2969), .Y(FPMULT_FS_Module_state_next[3])
);
AOI21X1TS U4154 ( .A0(operation[1]), .A1(ack_operation), .B0(n3104), .Y(
n2983) );
NOR4X1TS U4155 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .B(n2971),
.C(FPSENCOS_enab_RB3), .D(FPSENCOS_enab_d_ff_RB1), .Y(n2973) );
NAND2X1TS U4156 ( .A(n2973), .B(n2972), .Y(n2975) );
NOR2X1TS U4157 ( .A(n3090), .B(n2974), .Y(n2977) );
OAI22X1TS U4158 ( .A0(n2983), .A1(n2975), .B0(n2977), .B1(n2976), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U4159 ( .AN(n2977), .B(n2976), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AO21XLTS U4160 ( .A0(n2978), .A1(n2979), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OAI22X1TS U4161 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n2981), .B0(n2980), .B1(
n2979), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NAND2BXLTS U4162 ( .AN(n2983), .B(n2982), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
AOI22X1TS U4163 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n3030), .B0(Data_2[0]), .B1(n3010), .Y(n2985) );
AOI22X1TS U4164 ( .A0(n3070), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n3087),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n2984) );
NAND2X1TS U4165 ( .A(n2985), .B(n2984), .Y(add_subt_data2[0]) );
AOI22X1TS U4166 ( .A0(FPSENCOS_d_ff3_sh_x_out[1]), .A1(n3091), .B0(Data_2[1]), .B1(n3010), .Y(n2987) );
AOI22X1TS U4167 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n2998),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n2986) );
NAND2X1TS U4168 ( .A(n2987), .B(n2986), .Y(add_subt_data2[1]) );
AOI22X1TS U4169 ( .A0(FPSENCOS_d_ff3_sh_x_out[2]), .A1(n924), .B0(Data_2[2]),
.B1(n3005), .Y(n2989) );
AOI22X1TS U4170 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n2998),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n2988) );
NAND2X1TS U4171 ( .A(n2989), .B(n2988), .Y(add_subt_data2[2]) );
AOI22X1TS U4172 ( .A0(FPSENCOS_d_ff3_sh_x_out[4]), .A1(n3066), .B0(Data_2[4]), .B1(n3010), .Y(n2991) );
AOI22X1TS U4173 ( .A0(n3070), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n2998),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n2990) );
NAND2X1TS U4174 ( .A(n2991), .B(n2990), .Y(add_subt_data2[4]) );
AOI22X1TS U4175 ( .A0(FPSENCOS_d_ff3_sh_x_out[6]), .A1(n924), .B0(Data_2[6]),
.B1(n3010), .Y(n2993) );
AOI22X1TS U4176 ( .A0(n3070), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n2998),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n2992) );
NAND2X1TS U4177 ( .A(n2993), .B(n2992), .Y(add_subt_data2[6]) );
AOI22X1TS U4178 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n3030), .B0(Data_2[8]), .B1(n3010), .Y(n2995) );
AOI22X1TS U4179 ( .A0(n3084), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n2998),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n2994) );
NAND2X1TS U4180 ( .A(n2995), .B(n2994), .Y(add_subt_data2[8]) );
AOI22X1TS U4181 ( .A0(FPSENCOS_d_ff3_sh_x_out[9]), .A1(n3066), .B0(Data_2[9]), .B1(n3010), .Y(n2997) );
AOI22X1TS U4182 ( .A0(n3084), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n2998),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n2996) );
NAND2X1TS U4183 ( .A(n2997), .B(n2996), .Y(add_subt_data2[9]) );
AOI22X1TS U4184 ( .A0(FPSENCOS_d_ff3_sh_x_out[10]), .A1(n3066), .B0(
Data_2[10]), .B1(n3010), .Y(n3000) );
AOI22X1TS U4185 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n2998),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n2999) );
NAND2X1TS U4186 ( .A(n3000), .B(n2999), .Y(add_subt_data2[10]) );
AOI22X1TS U4187 ( .A0(FPSENCOS_d_ff3_sh_x_out[12]), .A1(n923), .B0(
Data_2[12]), .B1(n3010), .Y(n3002) );
BUFX3TS U4188 ( .A(n3087), .Y(n3092) );
AOI22X1TS U4189 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n3092),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n3001) );
NAND2X1TS U4190 ( .A(n3002), .B(n3001), .Y(add_subt_data2[12]) );
AOI22X1TS U4191 ( .A0(FPSENCOS_d_ff3_sh_x_out[21]), .A1(n3091), .B0(
Data_2[21]), .B1(n3005), .Y(n3004) );
AOI22X1TS U4192 ( .A0(n3070), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n3092),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n3003) );
NAND2X1TS U4193 ( .A(n3004), .B(n3003), .Y(add_subt_data2[21]) );
AOI22X1TS U4194 ( .A0(FPSENCOS_d_ff3_sh_x_out[23]), .A1(n3091), .B0(
Data_2[23]), .B1(n3005), .Y(n3007) );
AOI22X1TS U4195 ( .A0(n3067), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n3092),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n3006) );
NAND2X1TS U4196 ( .A(n3007), .B(n3006), .Y(add_subt_data2[23]) );
AOI22X1TS U4197 ( .A0(FPSENCOS_d_ff3_sh_x_out[24]), .A1(n3091), .B0(
Data_2[24]), .B1(n3005), .Y(n3009) );
AOI22X1TS U4198 ( .A0(n3084), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n3092),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n3008) );
NAND2X1TS U4199 ( .A(n3009), .B(n3008), .Y(add_subt_data2[24]) );
AOI22X1TS U4200 ( .A0(FPSENCOS_d_ff3_sh_x_out[25]), .A1(n3091), .B0(
Data_2[25]), .B1(n3010), .Y(n3012) );
AOI22X1TS U4201 ( .A0(n3093), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n3092),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n3011) );
NAND2X1TS U4202 ( .A(n3012), .B(n3011), .Y(add_subt_data2[25]) );
AOI22X1TS U4203 ( .A0(FPSENCOS_d_ff3_sh_x_out[26]), .A1(n3091), .B0(
Data_2[26]), .B1(n3005), .Y(n3014) );
AOI22X1TS U4204 ( .A0(n3093), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n3092),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n3013) );
NAND2X1TS U4205 ( .A(n3014), .B(n3013), .Y(add_subt_data2[26]) );
AO22XLTS U4206 ( .A0(operation[2]), .A1(n3015), .B0(n3016), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U4207 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n3016),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
AOI22X1TS U4208 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n3091), .B0(Data_1[0]), .B1(
n931), .Y(n3019) );
AOI22X1TS U4209 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[0]), .B0(n3092), .B1(
FPSENCOS_d_ff2_Z[0]), .Y(n3018) );
NAND2X1TS U4210 ( .A(n3019), .B(n3018), .Y(add_subt_data1[0]) );
AOI22X1TS U4211 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n3091), .B0(Data_1[1]), .B1(
n931), .Y(n3021) );
AOI22X1TS U4212 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[1]), .B0(n3092), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n3020) );
NAND2X1TS U4213 ( .A(n3021), .B(n3020), .Y(add_subt_data1[1]) );
AOI22X1TS U4214 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n3091), .B0(Data_1[2]), .B1(
n931), .Y(n3023) );
AOI22X1TS U4215 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[2]), .B0(n3092), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n3022) );
NAND2X1TS U4216 ( .A(n3023), .B(n3022), .Y(add_subt_data1[2]) );
AOI22X1TS U4217 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n3091), .B0(Data_1[3]), .B1(
n931), .Y(n3025) );
AOI22X1TS U4218 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[3]), .B0(n3092), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n3024) );
NAND2X1TS U4219 ( .A(n3025), .B(n3024), .Y(add_subt_data1[3]) );
AOI22X1TS U4220 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n3091), .B0(Data_1[4]), .B1(
n3010), .Y(n3027) );
AOI22X1TS U4221 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[4]), .B0(n3092), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n3026) );
NAND2X1TS U4222 ( .A(n3027), .B(n3026), .Y(add_subt_data1[4]) );
AOI22X1TS U4223 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n3091), .B0(Data_1[5]), .B1(
n3005), .Y(n3029) );
AOI22X1TS U4224 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[5]), .B0(n3092), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n3028) );
NAND2X1TS U4225 ( .A(n3029), .B(n3028), .Y(add_subt_data1[5]) );
AOI22X1TS U4226 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n3066), .B0(Data_1[6]), .B1(
n931), .Y(n3033) );
BUFX3TS U4227 ( .A(n3031), .Y(n3056) );
AOI22X1TS U4228 ( .A0(n3084), .A1(FPSENCOS_d_ff2_X[6]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n3032) );
NAND2X1TS U4229 ( .A(n3033), .B(n3032), .Y(add_subt_data1[6]) );
AOI22X1TS U4230 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n923), .B0(Data_1[7]), .B1(
n931), .Y(n3035) );
AOI22X1TS U4231 ( .A0(n3084), .A1(FPSENCOS_d_ff2_X[7]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n3034) );
NAND2X1TS U4232 ( .A(n3035), .B(n3034), .Y(add_subt_data1[7]) );
AOI22X1TS U4233 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n924), .B0(Data_1[8]), .B1(
n931), .Y(n3037) );
AOI22X1TS U4234 ( .A0(n3070), .A1(FPSENCOS_d_ff2_X[8]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n3036) );
NAND2X1TS U4235 ( .A(n3037), .B(n3036), .Y(add_subt_data1[8]) );
AOI22X1TS U4236 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n924), .B0(Data_1[9]), .B1(
n931), .Y(n3039) );
AOI22X1TS U4237 ( .A0(n3067), .A1(FPSENCOS_d_ff2_X[9]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n3038) );
NAND2X1TS U4238 ( .A(n3039), .B(n3038), .Y(add_subt_data1[9]) );
AOI22X1TS U4239 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n3066), .B0(Data_1[10]),
.B1(n3090), .Y(n3041) );
AOI22X1TS U4240 ( .A0(n3070), .A1(FPSENCOS_d_ff2_X[10]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n3040) );
NAND2X1TS U4241 ( .A(n3041), .B(n3040), .Y(add_subt_data1[10]) );
AOI22X1TS U4242 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n923), .B0(Data_1[11]),
.B1(n931), .Y(n3043) );
AOI22X1TS U4243 ( .A0(n3084), .A1(FPSENCOS_d_ff2_X[11]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n3042) );
NAND2X1TS U4244 ( .A(n3043), .B(n3042), .Y(add_subt_data1[11]) );
AOI22X1TS U4245 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n3066), .B0(Data_1[12]),
.B1(n931), .Y(n3045) );
AOI22X1TS U4246 ( .A0(n3084), .A1(FPSENCOS_d_ff2_X[12]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n3044) );
NAND2X1TS U4247 ( .A(n3045), .B(n3044), .Y(add_subt_data1[12]) );
AOI22X1TS U4248 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n924), .B0(Data_1[13]),
.B1(n931), .Y(n3047) );
AOI22X1TS U4249 ( .A0(n3084), .A1(FPSENCOS_d_ff2_X[13]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n3046) );
NAND2X1TS U4250 ( .A(n3047), .B(n3046), .Y(add_subt_data1[13]) );
AOI22X1TS U4251 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n923), .B0(Data_1[14]),
.B1(n931), .Y(n3049) );
AOI22X1TS U4252 ( .A0(n3070), .A1(FPSENCOS_d_ff2_X[14]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n3048) );
NAND2X1TS U4253 ( .A(n3049), .B(n3048), .Y(add_subt_data1[14]) );
AOI22X1TS U4254 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n3030), .B0(Data_1[15]),
.B1(n931), .Y(n3051) );
AOI22X1TS U4255 ( .A0(n3067), .A1(FPSENCOS_d_ff2_X[15]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n3050) );
NAND2X1TS U4256 ( .A(n3051), .B(n3050), .Y(add_subt_data1[15]) );
AOI22X1TS U4257 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n3030), .B0(Data_1[16]),
.B1(n931), .Y(n3053) );
AOI22X1TS U4258 ( .A0(n3070), .A1(FPSENCOS_d_ff2_X[16]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n3052) );
NAND2X1TS U4259 ( .A(n3053), .B(n3052), .Y(add_subt_data1[16]) );
AOI22X1TS U4260 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n924), .B0(Data_1[17]),
.B1(n3005), .Y(n3055) );
AOI22X1TS U4261 ( .A0(n3070), .A1(FPSENCOS_d_ff2_X[17]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n3054) );
NAND2X1TS U4262 ( .A(n3055), .B(n3054), .Y(add_subt_data1[17]) );
AOI22X1TS U4263 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n3030), .B0(Data_1[18]),
.B1(n3005), .Y(n3058) );
AOI22X1TS U4264 ( .A0(n3067), .A1(FPSENCOS_d_ff2_X[18]), .B0(n3056), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n3057) );
NAND2X1TS U4265 ( .A(n3058), .B(n3057), .Y(add_subt_data1[18]) );
AOI22X1TS U4266 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n3059), .B0(Data_1[19]),
.B1(n3005), .Y(n3061) );
AOI22X1TS U4267 ( .A0(n3070), .A1(FPSENCOS_d_ff2_X[19]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n3060) );
NAND2X1TS U4268 ( .A(n3061), .B(n3060), .Y(add_subt_data1[19]) );
AOI22X1TS U4269 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n3059), .B0(Data_1[20]),
.B1(n3005), .Y(n3063) );
AOI22X1TS U4270 ( .A0(n3084), .A1(FPSENCOS_d_ff2_X[20]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n3062) );
NAND2X1TS U4271 ( .A(n3063), .B(n3062), .Y(add_subt_data1[20]) );
AOI22X1TS U4272 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n924), .B0(Data_1[21]),
.B1(n3005), .Y(n3065) );
AOI22X1TS U4273 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[21]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n3064) );
NAND2X1TS U4274 ( .A(n3065), .B(n3064), .Y(add_subt_data1[21]) );
AOI22X1TS U4275 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n3066), .B0(Data_1[22]),
.B1(n3005), .Y(n3069) );
AOI22X1TS U4276 ( .A0(n3067), .A1(FPSENCOS_d_ff2_X[22]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n3068) );
NAND2X1TS U4277 ( .A(n3069), .B(n3068), .Y(add_subt_data1[22]) );
AOI22X1TS U4278 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n3059), .B0(Data_1[23]),
.B1(n3090), .Y(n3072) );
AOI22X1TS U4279 ( .A0(n3084), .A1(FPSENCOS_d_ff2_X[23]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n3071) );
NAND2X1TS U4280 ( .A(n3072), .B(n3071), .Y(add_subt_data1[23]) );
AOI22X1TS U4281 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n3030), .B0(Data_1[24]),
.B1(n3090), .Y(n3074) );
AOI22X1TS U4282 ( .A0(n3079), .A1(FPSENCOS_d_ff2_X[24]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n3073) );
NAND2X1TS U4283 ( .A(n3074), .B(n3073), .Y(add_subt_data1[24]) );
AOI22X1TS U4284 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n3059), .B0(Data_1[25]),
.B1(n3090), .Y(n3076) );
AOI22X1TS U4285 ( .A0(n3079), .A1(FPSENCOS_d_ff2_X[25]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n3075) );
NAND2X1TS U4286 ( .A(n3076), .B(n3075), .Y(add_subt_data1[25]) );
AOI22X1TS U4287 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n3066), .B0(Data_1[26]),
.B1(n3090), .Y(n3078) );
AOI22X1TS U4288 ( .A0(n3079), .A1(FPSENCOS_d_ff2_X[26]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n3077) );
NAND2X1TS U4289 ( .A(n3078), .B(n3077), .Y(add_subt_data1[26]) );
AOI22X1TS U4290 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n924), .B0(Data_1[27]),
.B1(n3090), .Y(n3081) );
AOI22X1TS U4291 ( .A0(n3079), .A1(FPSENCOS_d_ff2_X[27]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n3080) );
NAND2X1TS U4292 ( .A(n3081), .B(n3080), .Y(add_subt_data1[27]) );
AOI22X1TS U4293 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n3091), .B0(Data_1[28]),
.B1(n3090), .Y(n3083) );
AOI22X1TS U4294 ( .A0(n3084), .A1(FPSENCOS_d_ff2_X[28]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n3082) );
NAND2X1TS U4295 ( .A(n3083), .B(n3082), .Y(add_subt_data1[28]) );
AOI22X1TS U4296 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n3091), .B0(Data_1[29]),
.B1(n3005), .Y(n3086) );
AOI22X1TS U4297 ( .A0(n3067), .A1(FPSENCOS_d_ff2_X[29]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n3085) );
NAND2X1TS U4298 ( .A(n3086), .B(n3085), .Y(add_subt_data1[29]) );
AOI22X1TS U4299 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n3066), .B0(Data_1[30]),
.B1(n3090), .Y(n3089) );
AOI22X1TS U4300 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[30]), .B0(n3087), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n3088) );
NAND2X1TS U4301 ( .A(n3089), .B(n3088), .Y(add_subt_data1[30]) );
AOI22X1TS U4302 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n3091), .B0(Data_1[31]),
.B1(n3090), .Y(n3095) );
AOI22X1TS U4303 ( .A0(n3093), .A1(FPSENCOS_d_ff2_X[31]), .B0(n3092), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n3094) );
NAND2X1TS U4304 ( .A(n3095), .B(n3094), .Y(add_subt_data1[31]) );
OA21XLTS U4305 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3097), .B0(n3096), .Y(
FPSENCOS_ITER_CONT_N4) );
AOI22X1TS U4306 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3100), .B0(n3098),
.B1(n3242), .Y(n859) );
AOI22X1TS U4307 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3100), .B0(n3099),
.B1(n3242), .Y(n851) );
OAI2BB1X1TS U4308 ( .A0N(FPSENCOS_cont_iter_out[1]), .A1N(n849), .B0(n3101),
.Y(n850) );
AOI22X1TS U4309 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3103), .B0(n3102),
.B1(n3242), .Y(n846) );
NAND4X1TS U4310 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .C(n3253), .D(n3165), .Y(n3106) );
OAI222X1TS U4311 ( .A0(n2347), .A1(n3293), .B0(n3105), .B1(n3104), .C0(n3106), .C1(n2324), .Y(operation_ready) );
AOI22X1TS U4312 ( .A0(ack_operation), .A1(n2150), .B0(begin_operation), .B1(
n3106), .Y(n3107) );
OAI2BB2XLTS U4313 ( .B0(n3107), .B1(n2324), .A0N(n3106), .A1N(n3442), .Y(
n844) );
AOI22X1TS U4314 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n3109), .B0(n3108),
.B1(n3155), .Y(n841) );
NAND2X1TS U4315 ( .A(n3110), .B(n3364), .Y(FPADDSUB__6_net_) );
NOR4X1TS U4316 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[11]), .C(
FPMULT_Op_MY[0]), .D(FPMULT_Op_MY[1]), .Y(n3116) );
NOR4X1TS U4317 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[7]), .C(
FPMULT_Op_MY[8]), .D(FPMULT_Op_MY[9]), .Y(n3115) );
NOR4X1TS U4318 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[18]), .C(
FPMULT_Op_MY[22]), .D(FPMULT_Op_MY[19]), .Y(n3114) );
NOR4X1TS U4319 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[3]), .C(
FPMULT_Op_MY[4]), .D(FPMULT_Op_MY[5]), .Y(n3113) );
NAND4XLTS U4320 ( .A(n3116), .B(n3115), .C(n3114), .D(n3113), .Y(n3135) );
NOR4X1TS U4321 ( .A(FPMULT_Op_MY[27]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[25]), .D(FPMULT_Op_MY[24]), .Y(n3121) );
NOR3XLTS U4322 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[29]), .C(
FPMULT_Op_MY[28]), .Y(n3120) );
NOR4X1TS U4323 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[15]), .C(
FPMULT_Op_MY[16]), .D(FPMULT_Op_MY[17]), .Y(n3119) );
NOR4X1TS U4324 ( .A(FPMULT_Op_MY[23]), .B(FPMULT_Op_MY[30]), .C(
FPMULT_Op_MY[12]), .D(n3117), .Y(n3118) );
NAND4XLTS U4325 ( .A(n3121), .B(n3120), .C(n3119), .D(n3118), .Y(n3134) );
NOR4X1TS U4326 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[11]), .C(
FPMULT_Op_MX[0]), .D(FPMULT_Op_MX[1]), .Y(n3127) );
NOR4X1TS U4327 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[7]), .C(
FPMULT_Op_MX[8]), .D(FPMULT_Op_MX[9]), .Y(n3126) );
NOR4X1TS U4328 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[18]), .C(
FPMULT_Op_MX[22]), .D(FPMULT_Op_MX[19]), .Y(n3125) );
NOR4X1TS U4329 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[3]), .C(
FPMULT_Op_MX[4]), .D(FPMULT_Op_MX[5]), .Y(n3124) );
NAND4XLTS U4330 ( .A(n3127), .B(n3126), .C(n3125), .D(n3124), .Y(n3133) );
NOR4X1TS U4331 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[27]), .C(
FPMULT_Op_MX[26]), .D(FPMULT_Op_MX[25]), .Y(n3131) );
NOR3XLTS U4332 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .Y(n3130) );
NOR4X1TS U4333 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[15]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[17]), .Y(n3129) );
NOR4X1TS U4334 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_Op_MX[23]), .C(
FPMULT_Op_MX[12]), .D(FPMULT_Op_MX[13]), .Y(n3128) );
NAND4XLTS U4335 ( .A(n3131), .B(n3130), .C(n3129), .D(n3128), .Y(n3132) );
OAI22X1TS U4336 ( .A0(n3135), .A1(n3134), .B0(n3133), .B1(n3132), .Y(n115)
);
AO22XLTS U4337 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n3364), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n817) );
AO22XLTS U4338 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n3220), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n814) );
XNOR2X1TS U4339 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n3465), .Y(n30) );
AO22XLTS U4340 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n3364), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n811) );
NOR2BX1TS U4341 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
NOR2XLTS U4342 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3137), .Y(n3136) );
XOR2XLTS U4343 ( .A(FPSENCOS_d_ff2_Y[30]), .B(n3136), .Y(
FPSENCOS_sh_exp_y[7]) );
XNOR2X1TS U4344 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3137), .Y(
FPSENCOS_sh_exp_y[6]) );
AO21XLTS U4345 ( .A0(intadd_1109_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n3138),
.Y(FPSENCOS_sh_exp_y[4]) );
NOR2XLTS U4346 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3140), .Y(n3139) );
XOR2XLTS U4347 ( .A(FPSENCOS_d_ff2_X[30]), .B(n3139), .Y(
FPSENCOS_sh_exp_x[7]) );
XNOR2X1TS U4348 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3140), .Y(
FPSENCOS_sh_exp_x[6]) );
AO21XLTS U4349 ( .A0(intadd_1108_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n3141),
.Y(FPSENCOS_sh_exp_x[4]) );
CMPR42X1TS U4350 ( .A(DP_OP_501J324_127_5235_n191), .B(
DP_OP_501J324_127_5235_n226), .C(DP_OP_501J324_127_5235_n148), .D(
DP_OP_501J324_127_5235_n151), .ICI(DP_OP_501J324_127_5235_n146), .S(
DP_OP_501J324_127_5235_n143), .ICO(DP_OP_501J324_127_5235_n141), .CO(
DP_OP_501J324_127_5235_n142) );
CMPR42X1TS U4351 ( .A(DP_OP_501J324_127_5235_n147), .B(
DP_OP_501J324_127_5235_n144), .C(DP_OP_501J324_127_5235_n138), .D(
DP_OP_501J324_127_5235_n145), .ICI(DP_OP_501J324_127_5235_n136), .S(
DP_OP_501J324_127_5235_n133), .ICO(DP_OP_501J324_127_5235_n131), .CO(
DP_OP_501J324_127_5235_n132) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_GATED_RKOA_2STAGE_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:04:00 04/01/2012
// Design Name:
// Module Name: sigma_delta_dac
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define MSBI 8 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
module dac (DACout, DACin, Clk, Reset);
output DACout; // This is the average output that feeds low pass filter
input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
input Clk;
input Reset;
reg DACout; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
DACout <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule
module mixer (
input wire clk,
input wire rst_n,
input wire ear,
input wire mic,
input wire spk,
input wire [7:0] saa_left,
input wire [7:0] saa_right,
output wire audio_left,
output wire audio_right
);
reg [6:0] beeper;
always @* begin
beeper = 7'd0;
if (ear == 1'b1)
beeper = beeper + 7'd38; // 30% of total output
if (mic == 1'b1)
beeper = beeper + 7'd38; // 30% of total output
if (spk == 1'b1)
beeper = beeper + 7'd51; // 40% of total output
end
wire [8:0] next_sample_l = beeper + saa_left;
wire [8:0] next_sample_r = beeper + saa_right;
reg [8:0] sample_l, sample_r;
always @(posedge clk) begin
sample_l <= next_sample_l;
sample_r <= next_sample_r;
end
dac audio_dac_left (
.DACout(audio_left),
.DACin(sample_l),
.Clk(clk),
.Reset(~rst_n)
);
dac audio_dac_right (
.DACout(audio_right),
.DACin(sample_r),
.Clk(clk),
.Reset(~rst_n)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVN_TB_V
`define SKY130_FD_SC_HD__EINVN_TB_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__einvn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVN_TB_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 3
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_blk_mem_gen_0_0 (
clka,
rsta,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)
input wire rsta;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [3 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [31 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [31 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(1),
.C_ENABLE_32BIT_ADDRESS(1),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(8),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("NONE"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(1),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(4),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(16384),
.C_READ_DEPTH_A(16384),
.C_ADDRA_WIDTH(32),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(4),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(16384),
.C_READ_DEPTH_B(16384),
.C_ADDRB_WIDTH(32),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("16"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 10.194 mW")
) inst (
.clka(clka),
.rsta(rsta),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(4'B0),
.addrb(32'B0),
.dinb(32'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(4'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:01:47 09/18/2015
// Design Name:
// Module Name: boardSynchroniser
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module boardSynchroniser3 #(parameter CNT_WIDTH = 2)
(
input clk,
input synch_en,
input toggle_en,
input [CNT_WIDTH-1:0] cnt_n,
input [CNT_WIDTH-1:0] cnt_m,
input syncIn,
(* IOB = "true" *) output reg syncOut = 1'b0,
(* equivalent_register_removal = "no" *) output reg synchroStatusInt = 1'b0, synchroStatusExt = 1'b0
);
// Operates in two modes
// FULL DUPLEX - records transmitted and recieved signals, using a buffered AUX_IN and AUX_OUT
// HALF DUPLEX - works in master/slave mode using bi-directional IO (inout)
// - can optionally use two IOs to send/recieve data and clock (synchronisation) signal, eg for FB on/off //
// Synchroniser module for providing n-high-in-m-pulses syncronisation signal to external device, e.g. DC-coupled digitiser.
// For synchronising two FONT5 boards, the module will work in master or slave mode for receiving or transmitting data.
// Eg opMode = 0 (slave), opMode = 1 (master) - eg default to fail-safe (zero) - if need default to master, need to initialise this with the CRs.
reg tog_a = 1'b0, tog_b = 1'b0, toggle = 1'b0;
reg [CNT_WIDTH-1:0] ctr = {CNT_WIDTH{1'b0}};
reg synch = 1'b0;
(* IOB = "true", ASYNC_REG = "TRUE" *) reg syncIn_a = 1'b0;
(* ASYNC_REG = "TRUE" *) reg syncIn_b = 1'b0;
reg synch_en_a = 1'b0, synch_en_b = 1'b0;
always @(posedge clk) begin
synch_en_a <= synch_en;
synch_en_b <= synch_en_a;
syncIn_a <= syncIn;
syncIn_b <= syncIn_a;
tog_a <= toggle_en;
tog_b <= tog_a;
toggle <= tog_a & ~tog_b;
if (toggle) begin
ctr <= (ctr == cnt_m) ? {CNT_WIDTH{1'b0}} : ctr + 1'b1;
if (synch_en_b) begin
if (ctr == cnt_m) synch <= 1'b1;
else if (ctr == cnt_n) synch <= 1'b0;
else synch <= synch;
end else synch <= 1'b0;
end else begin
ctr <= ctr;
synch <= synch;
end
synchroStatusInt <= synch;
synchroStatusExt <= syncIn_b;
syncOut <= ~synch; // NB: auxOuts on FONT5A boards use inverting buffers
end
//NB: for synchronising FB on/off between boards, can set ctr_m (and ctr_n) to zero, and wire synch_en to FB on/off.
// Can then XOR FBon/off signal with the input synchroStatusExt to write the new FB status to the readbacks.
//NB: time offset between trigRdy going high and the FB state toggling!!! Could just use the syncroStatusExt directly to deduce FB state!!
// Alternativelym just use the counter based signal to ensure the boards are synchronous!
//assign syncInOut = (opMode) ? synch : 1'bz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_4_V
`define SKY130_FD_SC_HS__AND2_4_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2_4 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_4_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
//
// Cluster Name: CTU
//
//-----------------------------------------------------------------------------
`include "sys.h"
`include "iop.h"
module ctu (/*AUTOARG*/
// Outputs
tap_iob_vld, tap_iob_stall, tap_iob_data, pscan_select,
jbus_grst_out_l, jbus_gdbginit_out_l, jbus_gclk_out,
jbus_gclk_dup_out, jbus_arst_l, jbus_adbginit_l,
global_scan_bypass_en, dram_grst_out_l, dram_gdbginit_out_l,
dram_gclk_out, dram_arst_l, dram_adbginit_l, ctu_tst_scan_disable,
ctu_spc_sscan_tid, ctu_spc_const_maskid, ctu_spc7_tck,
ctu_spc7_sscan_se, ctu_spc7_mbisten, ctu_spc7_cmp_cken, ctu_spc6_tck,
ctu_spc6_sscan_se, ctu_spc6_mbisten, ctu_spc6_cmp_cken, ctu_spc5_tck,
ctu_spc5_sscan_se, ctu_spc5_mbisten, ctu_spc5_cmp_cken, ctu_spc4_tck,
ctu_spc4_sscan_se, ctu_spc4_mbisten, ctu_spc4_cmp_cken, ctu_spc3_tck,
ctu_spc3_sscan_se, ctu_spc3_mbisten, ctu_spc3_cmp_cken, ctu_spc2_tck,
ctu_spc2_sscan_se, ctu_spc2_mbisten, ctu_spc2_cmp_cken, ctu_spc1_tck,
ctu_spc1_sscan_se, ctu_spc1_mbisten, ctu_spc1_cmp_cken, ctu_spc0_tck,
ctu_spc0_sscan_se, ctu_spc0_mbisten, ctu_spc0_cmp_cken,
ctu_sctag3_mbisten, ctu_sctag3_cmp_cken, ctu_sctag2_mbisten,
ctu_sctag2_cmp_cken, ctu_sctag1_mbisten, ctu_sctag1_cmp_cken,
ctu_sctag0_mbisten, ctu_sctag0_cmp_cken, ctu_scdata3_cmp_cken,
ctu_scdata2_cmp_cken, ctu_scdata1_cmp_cken, ctu_scdata0_cmp_cken,
ctu_pads_sscan_update, ctu_pads_so, ctu_pads_bso, ctu_misc_update_dr,
ctu_misc_shift_dr, ctu_misc_mode_ctl, ctu_misc_jbus_cken,
ctu_misc_hiz_l, ctu_misc_clock_dr, ctu_jbusr_update_dr,
ctu_jbusr_shift_dr, ctu_jbusr_mode_ctl, ctu_jbusr_jbus_cken,
ctu_jbusr_hiz_l, ctu_jbusr_clock_dr, ctu_jbusl_update_dr,
ctu_jbusl_shift_dr, ctu_jbusl_mode_ctl, ctu_jbusl_jbus_cken,
ctu_jbusl_hiz_l, ctu_jbusl_clock_dr, ctu_jbi_jbus_cken,
ctu_jbi_cmp_cken, ctu_iob_wake_thr, ctu_iob_resetstat_wr,
ctu_iob_resetstat, ctu_iob_jbus_cken, ctu_iob_cmp_cken,
ctu_io_tsr_testio, ctu_io_tdo_en, ctu_io_tdo, ctu_io_j_err,
ctu_io_clkobs, ctu_global_snap, ctu_fpu_so, ctu_fpu_cmp_cken,
ctu_efc_updatedr, ctu_efc_tck, ctu_efc_shiftdr, ctu_efc_rowaddr,
ctu_efc_read_mode, ctu_efc_read_en, ctu_efc_jbus_cken,
ctu_efc_fuse_bypass, ctu_efc_dest_sample, ctu_efc_data_in,
ctu_efc_coladdr, ctu_efc_capturedr, ctu_dram_selfrsh,
ctu_dram13_jbus_cken, ctu_dram13_dram_cken, ctu_dram13_cmp_cken,
ctu_dram02_jbus_cken, ctu_dram02_dram_cken, ctu_dram02_cmp_cken,
ctu_dll3_byp_val, ctu_dll3_byp_l, ctu_dll2_byp_val, ctu_dll2_byp_l,
ctu_dll1_byp_val, ctu_dll1_byp_l, ctu_dll0_byp_val, ctu_dll0_byp_l,
ctu_debug_update_dr, ctu_debug_shift_dr, ctu_debug_mode_ctl,
ctu_debug_hiz_l, ctu_debug_clock_dr, ctu_ddr_testmode_l,
ctu_ddr3_update_dr, ctu_ddr3_shift_dr, ctu_ddr3_mode_ctl,
ctu_ddr3_iodll_rst_l, ctu_ddr3_hiz_l, ctu_ddr3_dram_cken,
ctu_ddr3_dll_delayctr, ctu_ddr3_clock_dr, ctu_ddr2_update_dr,
ctu_ddr2_shift_dr, ctu_ddr2_mode_ctl, ctu_ddr2_iodll_rst_l,
ctu_ddr2_hiz_l, ctu_ddr2_dram_cken, ctu_ddr2_dll_delayctr,
ctu_ddr2_clock_dr, ctu_ddr1_update_dr, ctu_ddr1_shift_dr,
ctu_ddr1_mode_ctl, ctu_ddr1_iodll_rst_l, ctu_ddr1_hiz_l,
ctu_ddr1_dram_cken, ctu_ddr1_dll_delayctr, ctu_ddr1_clock_dr,
ctu_ddr0_update_dr, ctu_ddr0_shift_dr, ctu_ddr0_mode_ctl,
ctu_ddr0_iodll_rst_l, ctu_ddr0_hiz_l, ctu_ddr0_dram_cken,
ctu_ddr0_dll_delayctr, ctu_ddr0_clock_dr, ctu_dbg_jbus_cken,
ctu_ccx_cmp_cken, cmp_gdbginit_out_l, cmp_gclk_out, cmp_arst_l,
cmp_adbginit_l, clsp_iob_vld, clsp_iob_stall, clsp_iob_data,
afo_tsr_dout, afo_rt_data_out, afo_rt_ack, afo_rng_data, afo_rng_clk,
ctu_tst_pre_grst_l, global_shift_enable, ctu_tst_scanmode,
ctu_tst_macrotest, ctu_tst_short_chain, ctu_efc_read_start,
ctu_jbi_ssiclk, ctu_dram_rx_sync_out, ctu_dram_tx_sync_out,
ctu_jbus_rx_sync_out, ctu_jbus_tx_sync_out, cmp_grst_out_l,
// Inputs
spc7_ctu_sscan_out, spc7_ctu_mbisterr, spc7_ctu_mbistdone,
spc6_ctu_sscan_out, spc6_ctu_mbisterr, spc6_ctu_mbistdone,
spc5_ctu_sscan_out, spc5_ctu_mbisterr, spc5_ctu_mbistdone,
spc4_ctu_sscan_out, spc4_ctu_mbisterr, spc4_ctu_mbistdone,
spc3_ctu_sscan_out, spc3_ctu_mbisterr, spc3_ctu_mbistdone,
spc2_ctu_sscan_out, spc2_ctu_mbisterr, spc2_ctu_mbistdone,
spc1_ctu_sscan_out, spc1_ctu_mbisterr, spc1_ctu_mbistdone,
spc0_ctu_sscan_out, spc0_ctu_mbisterr, spc0_ctu_mbistdone,
sctag3_ctu_tr, sctag3_ctu_mbisterr, sctag3_ctu_mbistdone,
sctag2_ctu_tr, sctag2_ctu_serial_scan_in, sctag2_ctu_mbisterr,
sctag2_ctu_mbistdone, sctag1_ctu_tr, sctag1_ctu_mbisterr,
sctag1_ctu_mbistdone, sctag0_ctu_tr, sctag0_ctu_mbisterr,
sctag0_ctu_mbistdone, pads_ctu_si, pads_ctu_bsi, jbus_grst_l,
jbus_gclk_dup, jbus_gclk_cts, jbus_gclk, jbi_ctu_tr, iob_tap_vld,
iob_tap_stall, iob_tap_data, iob_ctu_tr, iob_ctu_l2_tr,
iob_ctu_coreavail, iob_clsp_vld, iob_clsp_stall, iob_clsp_data,
io_vreg_selbg_l, io_vdda_tsr, io_vdda_rng, io_vdda_pll, io_trst_l,
io_tms, io_test_mode, io_tdi, io_tck2, io_tck, io_pwron_rst_l,
io_pll_char_in, io_j_rst_l, io_do_bist, io_clk_stretch,
efc_ctu_data_out, dram_gclk_cts, dram13_ctu_tr, dram02_ctu_tr,
dll3_ctu_ctrl, dll2_ctu_ctrl, dll1_ctu_ctrl, dll0_ctu_ctrl,
ddr3_ctu_dll_overflow, ddr3_ctu_dll_lock, ddr2_ctu_dll_overflow,
ddr2_ctu_dll_lock, ddr1_ctu_dll_overflow, ddr1_ctu_dll_lock,
ddr0_ctu_dll_overflow, ddr0_ctu_dll_lock, cmp_gclk_cts, cmp_gclk,
afi_tsr_tsel, afi_tsr_div, afi_rt_valid, afi_rt_read_write,
afi_rt_high_low, afi_rt_data_in, afi_rt_addr_data, afi_rng_ctl,
afi_pll_div2, afi_pll_clamp_fltr, afi_pll_char_mode, afi_bypass_mode,
afi_bist_mode, afi_pll_trst_l, afi_tsr_mode, io_j_clk
);
//***********************
//
// UNCONNECTED PORTS
//
//***********************
//input efc_ctu_si;
//output ctu_efc_so;
//output [5:0] ctu_rpt_cmp_spare ; // To gclk_flop_cluster_a_0 of bw_clk_gclkflop.v
//output ctu_pads_sscan_in ;
// NO longer needed; keep for Int 4.0 only
//input dram_grst_l;
//input ctu_dram_tx_sync;
//input ctu_jbus_rx_sync; // From ctu_clsp of ctu_clsp.v
//input ctu_jbus_tx_sync; // From ctu_clsp of ctu_clsp.v
// ------------------
input afi_pll_trst_l; // check assertion level
input afi_tsr_mode;
input [1:0] io_j_clk; // To ctu_digital of ctu_digital.v, ...
output ctu_tst_pre_grst_l;
output global_shift_enable; // From ctu_dft of ctu_dft.v
output ctu_tst_scanmode; // From ctu_dft of ctu_dft.v
output ctu_tst_macrotest; // From ctu_dft of ctu_dft.v
output ctu_tst_short_chain; // From ctu_dft of ctu_dft.v
output ctu_efc_read_start;
output ctu_jbi_ssiclk;
output ctu_dram_rx_sync_out; // From ctu_clsp of ctu_clsp.v
output ctu_dram_tx_sync_out; // From ctu_clsp of ctu_clsp.v
output ctu_jbus_rx_sync_out; // From ctu_clsp of ctu_clsp.v
output ctu_jbus_tx_sync_out; // From ctu_clsp of ctu_clsp.v
output cmp_grst_out_l; // From ctu_clsp of ctu_clsp.v
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output afo_rng_clk; // From u_rng of bw_rng.v
output afo_rng_data; // From u_rng of bw_rng.v
output afo_rt_ack; // From ctu_dft of ctu_dft.v
output [31:0] afo_rt_data_out; // From ctu_dft of ctu_dft.v
output [7:0] afo_tsr_dout; // From u_tsr of bw_tsr.v
output [`CLK_IOB_WIDTH-1:0]clsp_iob_data; // From ctu_clsp of ctu_clsp.v
output clsp_iob_stall; // From ctu_clsp of ctu_clsp.v
output clsp_iob_vld; // From ctu_clsp of ctu_clsp.v
output cmp_adbginit_l; // From ctu_clsp of ctu_clsp.v
output cmp_arst_l; // From ctu_clsp of ctu_clsp.v
output cmp_gclk_out; // From ctu_clsp of ctu_clsp.v
output cmp_gdbginit_out_l; // From ctu_clsp of ctu_clsp.v
output ctu_ccx_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_dbg_jbus_cken; // From ctu_clsp of ctu_clsp.v
output ctu_ddr0_clock_dr; // From ctu_dft of ctu_dft.v
output [2:0] ctu_ddr0_dll_delayctr; // From ctu_clsp of ctu_clsp.v
output ctu_ddr0_dram_cken; // From ctu_clsp of ctu_clsp.v
output ctu_ddr0_hiz_l; // From ctu_dft of ctu_dft.v
output ctu_ddr0_iodll_rst_l; // From u_ctu_ddr0_iodll_rst_l_or2_ecobug of ctu_or2.v
output ctu_ddr0_mode_ctl; // From ctu_dft of ctu_dft.v
output ctu_ddr0_shift_dr; // From ctu_dft of ctu_dft.v
output ctu_ddr0_update_dr; // From ctu_dft of ctu_dft.v
output ctu_ddr1_clock_dr; // From ctu_dft of ctu_dft.v
output [2:0] ctu_ddr1_dll_delayctr; // From ctu_clsp of ctu_clsp.v
output ctu_ddr1_dram_cken; // From ctu_clsp of ctu_clsp.v
output ctu_ddr1_hiz_l; // From ctu_dft of ctu_dft.v
output ctu_ddr1_iodll_rst_l; // From u_ctu_ddr1_iodll_rst_l_or2_ecobug of ctu_or2.v
output ctu_ddr1_mode_ctl; // From ctu_dft of ctu_dft.v
output ctu_ddr1_shift_dr; // From ctu_dft of ctu_dft.v
output ctu_ddr1_update_dr; // From ctu_dft of ctu_dft.v
output ctu_ddr2_clock_dr; // From ctu_dft of ctu_dft.v
output [2:0] ctu_ddr2_dll_delayctr; // From ctu_clsp of ctu_clsp.v
output ctu_ddr2_dram_cken; // From ctu_clsp of ctu_clsp.v
output ctu_ddr2_hiz_l; // From ctu_dft of ctu_dft.v
output ctu_ddr2_iodll_rst_l; // From u_ctu_ddr2_iodll_rst_l_or2_ecobug of ctu_or2.v
output ctu_ddr2_mode_ctl; // From ctu_dft of ctu_dft.v
output ctu_ddr2_shift_dr; // From ctu_dft of ctu_dft.v
output ctu_ddr2_update_dr; // From ctu_dft of ctu_dft.v
output ctu_ddr3_clock_dr; // From ctu_dft of ctu_dft.v
output [2:0] ctu_ddr3_dll_delayctr; // From ctu_clsp of ctu_clsp.v
output ctu_ddr3_dram_cken; // From ctu_clsp of ctu_clsp.v
output ctu_ddr3_hiz_l; // From ctu_dft of ctu_dft.v
output ctu_ddr3_iodll_rst_l; // From u_ctu_ddr3_iodll_rst_l_or2_ecobug of ctu_or2.v
output ctu_ddr3_mode_ctl; // From ctu_dft of ctu_dft.v
output ctu_ddr3_shift_dr; // From ctu_dft of ctu_dft.v
output ctu_ddr3_update_dr; // From ctu_dft of ctu_dft.v
output ctu_ddr_testmode_l; // From ctu_dft of ctu_dft.v
output ctu_debug_clock_dr; // From ctu_dft of ctu_dft.v
output ctu_debug_hiz_l; // From ctu_dft of ctu_dft.v
output ctu_debug_mode_ctl; // From ctu_dft of ctu_dft.v
output ctu_debug_shift_dr; // From ctu_dft of ctu_dft.v
output ctu_debug_update_dr; // From ctu_dft of ctu_dft.v
output ctu_dll0_byp_l; // From ctu_clsp of ctu_clsp.v
output [4:0] ctu_dll0_byp_val; // From ctu_clsp of ctu_clsp.v
output ctu_dll1_byp_l; // From ctu_clsp of ctu_clsp.v
output [4:0] ctu_dll1_byp_val; // From ctu_clsp of ctu_clsp.v
output ctu_dll2_byp_l; // From ctu_clsp of ctu_clsp.v
output [4:0] ctu_dll2_byp_val; // From ctu_clsp of ctu_clsp.v
output ctu_dll3_byp_l; // From ctu_clsp of ctu_clsp.v
output [4:0] ctu_dll3_byp_val; // From ctu_clsp of ctu_clsp.v
output ctu_dram02_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_dram02_dram_cken; // From ctu_clsp of ctu_clsp.v
output ctu_dram02_jbus_cken; // From ctu_clsp of ctu_clsp.v
output ctu_dram13_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_dram13_dram_cken; // From ctu_clsp of ctu_clsp.v
output ctu_dram13_jbus_cken; // From ctu_clsp of ctu_clsp.v
output ctu_dram_selfrsh; // From ctu_clsp of ctu_clsp.v
output ctu_efc_capturedr; // From ctu_dft of ctu_dft.v
output [4:0] ctu_efc_coladdr; // From ctu_dft of ctu_dft.v
output ctu_efc_data_in; // From ctu_dft of ctu_dft.v
output ctu_efc_dest_sample; // From ctu_dft of ctu_dft.v
output ctu_efc_fuse_bypass; // From ctu_dft of ctu_dft.v
output ctu_efc_jbus_cken; // From ctu_clsp of ctu_clsp.v
output ctu_efc_read_en; // From ctu_dft of ctu_dft.v
output [2:0] ctu_efc_read_mode; // From ctu_dft of ctu_dft.v
output [6:0] ctu_efc_rowaddr; // From ctu_dft of ctu_dft.v
output ctu_efc_shiftdr; // From ctu_dft of ctu_dft.v
output ctu_efc_tck; // From ctu_dft of ctu_dft.v
output ctu_efc_updatedr; // From ctu_dft of ctu_dft.v
output ctu_fpu_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_fpu_so; // From ctu_dft of ctu_dft.v
output ctu_global_snap; // From ctu_dft of ctu_dft.v
output [1:0] ctu_io_clkobs; // From u_pll of bw_pll.v
output ctu_io_j_err; // From ctu_clsp of ctu_clsp.v
output ctu_io_tdo; // From u_test_stub of ctu_test_stub_scan.v
output ctu_io_tdo_en; // From ctu_dft of ctu_dft.v
output [1:0] ctu_io_tsr_testio; // From u_tsr of bw_tsr.v
output ctu_iob_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_iob_jbus_cken; // From ctu_clsp of ctu_clsp.v
output [2:0] ctu_iob_resetstat; // From ctu_clsp of ctu_clsp.v
output ctu_iob_resetstat_wr; // From ctu_clsp of ctu_clsp.v
output ctu_iob_wake_thr; // From ctu_clsp of ctu_clsp.v
output ctu_jbi_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_jbi_jbus_cken; // From ctu_clsp of ctu_clsp.v
output ctu_jbusl_clock_dr; // From ctu_dft of ctu_dft.v
output ctu_jbusl_hiz_l; // From ctu_dft of ctu_dft.v
output ctu_jbusl_jbus_cken; // From ctu_clsp of ctu_clsp.v
output ctu_jbusl_mode_ctl; // From ctu_dft of ctu_dft.v
output ctu_jbusl_shift_dr; // From ctu_dft of ctu_dft.v
output ctu_jbusl_update_dr; // From ctu_dft of ctu_dft.v
output ctu_jbusr_clock_dr; // From ctu_dft of ctu_dft.v
output ctu_jbusr_hiz_l; // From ctu_dft of ctu_dft.v
output ctu_jbusr_jbus_cken; // From ctu_clsp of ctu_clsp.v
output ctu_jbusr_mode_ctl; // From ctu_dft of ctu_dft.v
output ctu_jbusr_shift_dr; // From ctu_dft of ctu_dft.v
output ctu_jbusr_update_dr; // From ctu_dft of ctu_dft.v
output ctu_misc_clock_dr; // From ctu_dft of ctu_dft.v
output ctu_misc_hiz_l; // From ctu_dft of ctu_dft.v
output ctu_misc_jbus_cken; // From ctu_clsp of ctu_clsp.v
output ctu_misc_mode_ctl; // From ctu_dft of ctu_dft.v
output ctu_misc_shift_dr; // From ctu_dft of ctu_dft.v
output ctu_misc_update_dr; // From ctu_dft of ctu_dft.v
output ctu_pads_bso; // From ctu_dft of ctu_dft.v
output ctu_pads_so; // From ctu_dft of ctu_dft.v
output ctu_pads_sscan_update; // From ctu_dft of ctu_dft.v
output ctu_scdata0_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_scdata1_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_scdata2_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_scdata3_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_sctag0_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_sctag0_mbisten; // From ctu_dft of ctu_dft.v
output ctu_sctag1_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_sctag1_mbisten; // From ctu_dft of ctu_dft.v
output ctu_sctag2_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_sctag2_mbisten; // From ctu_dft of ctu_dft.v
output ctu_sctag3_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_sctag3_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc0_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_spc0_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc0_sscan_se; // From ctu_dft of ctu_dft.v
output ctu_spc0_tck; // From ctu_dft of ctu_dft.v
output ctu_spc1_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_spc1_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc1_sscan_se; // From ctu_dft of ctu_dft.v
output ctu_spc1_tck; // From ctu_dft of ctu_dft.v
output ctu_spc2_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_spc2_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc2_sscan_se; // From ctu_dft of ctu_dft.v
output ctu_spc2_tck; // From ctu_dft of ctu_dft.v
output ctu_spc3_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_spc3_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc3_sscan_se; // From ctu_dft of ctu_dft.v
output ctu_spc3_tck; // From ctu_dft of ctu_dft.v
output ctu_spc4_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_spc4_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc4_sscan_se; // From ctu_dft of ctu_dft.v
output ctu_spc4_tck; // From ctu_dft of ctu_dft.v
output ctu_spc5_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_spc5_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc5_sscan_se; // From ctu_dft of ctu_dft.v
output ctu_spc5_tck; // From ctu_dft of ctu_dft.v
output ctu_spc6_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_spc6_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc6_sscan_se; // From ctu_dft of ctu_dft.v
output ctu_spc6_tck; // From ctu_dft of ctu_dft.v
output ctu_spc7_cmp_cken; // From ctu_clsp of ctu_clsp.v
output ctu_spc7_mbisten; // From ctu_dft of ctu_dft.v
output ctu_spc7_sscan_se; // From ctu_dft of ctu_dft.v
output ctu_spc7_tck; // From ctu_dft of ctu_dft.v
output [7:0] ctu_spc_const_maskid; // From ctu_clsp of ctu_clsp.v
output [3:0] ctu_spc_sscan_tid; // From ctu_dft of ctu_dft.v
output ctu_tst_scan_disable; // From ctu_dft of ctu_dft.v
output dram_adbginit_l; // From ctu_clsp of ctu_clsp.v
output dram_arst_l; // From ctu_clsp of ctu_clsp.v
output dram_gclk_out; // From ctu_clsp of ctu_clsp.v
output dram_gdbginit_out_l; // From ctu_clsp of ctu_clsp.v
output dram_grst_out_l; // From ctu_clsp of ctu_clsp.v
output global_scan_bypass_en; // From ctu_dft of ctu_dft.v
output jbus_adbginit_l; // From ctu_clsp of ctu_clsp.v
output jbus_arst_l; // From ctu_clsp of ctu_clsp.v
output jbus_gclk_dup_out; // From ctu_clsp of ctu_clsp.v
output jbus_gclk_out; // From ctu_clsp of ctu_clsp.v
output jbus_gdbginit_out_l; // From ctu_clsp of ctu_clsp.v
output jbus_grst_out_l; // From ctu_clsp of ctu_clsp.v
output pscan_select; // From ctu_dft of ctu_dft.v
output [7:0] tap_iob_data; // From ctu_dft of ctu_dft.v
output tap_iob_stall; // From ctu_dft of ctu_dft.v
output tap_iob_vld; // From ctu_dft of ctu_dft.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input afi_bist_mode; // To ctu_dft of ctu_dft.v
input afi_bypass_mode; // To ctu_dft of ctu_dft.v
input afi_pll_char_mode; // To ctu_dft of ctu_dft.v
input afi_pll_clamp_fltr; // To ctu_dft of ctu_dft.v
input [5:0] afi_pll_div2; // To ctu_dft of ctu_dft.v
input [2:0] afi_rng_ctl; // To ctu_dft of ctu_dft.v
input afi_rt_addr_data; // To ctu_dft of ctu_dft.v
input [31:0] afi_rt_data_in; // To ctu_dft of ctu_dft.v
input afi_rt_high_low; // To ctu_dft of ctu_dft.v
input afi_rt_read_write; // To ctu_dft of ctu_dft.v
input afi_rt_valid; // To ctu_dft of ctu_dft.v
input [9:1] afi_tsr_div; // To ctu_dft of ctu_dft.v
input [7:0] afi_tsr_tsel; // To ctu_dft of ctu_dft.v
input cmp_gclk; // To u_cmp_header of bw_clk_cl_ctu_cmp.v
input cmp_gclk_cts; // To u_cmp_gclk_dr of bw_u1_ckbuf_40x.v
input ddr0_ctu_dll_lock; // To ctu_clsp of ctu_clsp.v
input ddr0_ctu_dll_overflow; // To ctu_clsp of ctu_clsp.v
input ddr1_ctu_dll_lock; // To ctu_clsp of ctu_clsp.v
input ddr1_ctu_dll_overflow; // To ctu_clsp of ctu_clsp.v
input ddr2_ctu_dll_lock; // To ctu_clsp of ctu_clsp.v
input ddr2_ctu_dll_overflow; // To ctu_clsp of ctu_clsp.v
input ddr3_ctu_dll_lock; // To ctu_clsp of ctu_clsp.v
input ddr3_ctu_dll_overflow; // To ctu_clsp of ctu_clsp.v
input [4:0] dll0_ctu_ctrl; // To ctu_clsp of ctu_clsp.v
input [4:0] dll1_ctu_ctrl; // To ctu_clsp of ctu_clsp.v
input [4:0] dll2_ctu_ctrl; // To ctu_clsp of ctu_clsp.v
input [4:0] dll3_ctu_ctrl; // To ctu_clsp of ctu_clsp.v
input dram02_ctu_tr; // To ctu_clsp of ctu_clsp.v
input dram13_ctu_tr; // To ctu_clsp of ctu_clsp.v
input dram_gclk_cts; // To u_dram_gclk_dr of bw_u1_ckbuf_30x.v
input efc_ctu_data_out; // To ctu_dft of ctu_dft.v
input io_clk_stretch; // To ctu_clsp of ctu_clsp.v
input io_do_bist; // To ctu_clsp of ctu_clsp.v
input io_j_rst_l; // To ctu_clsp of ctu_clsp.v
input io_pll_char_in; // To ctu_clsp of ctu_clsp.v, ...
input io_pwron_rst_l; // To ctu_clsp of ctu_clsp.v, ...
input io_tck; // To u_tck_dr of bw_u1_ckbuf_30x.v, ...
input io_tck2; // To ctu_clsp of ctu_clsp.v
input io_tdi; // To ctu_dft of ctu_dft.v
input io_test_mode; // To ctu_dft of ctu_dft.v
input io_tms; // To ctu_dft of ctu_dft.v
input io_trst_l; // To ctu_dft of ctu_dft.v
input io_vdda_pll; // To u_pll of bw_pll.v
input io_vdda_rng; // To u_rng of bw_rng.v
input io_vdda_tsr; // To u_tsr of bw_tsr.v
input io_vreg_selbg_l; // To u_rng of bw_rng.v, ...
input [`IOB_CLK_WIDTH-1:0]iob_clsp_data; // To ctu_clsp of ctu_clsp.v
input iob_clsp_stall; // To ctu_clsp of ctu_clsp.v
input iob_clsp_vld; // To ctu_clsp of ctu_clsp.v
input [`IOB_CPU_WIDTH-1:0]iob_ctu_coreavail; // To ctu_dft of ctu_dft.v
input iob_ctu_l2_tr; // To ctu_clsp of ctu_clsp.v
input iob_ctu_tr; // To ctu_clsp of ctu_clsp.v
input [7:0] iob_tap_data; // To ctu_dft of ctu_dft.v
input iob_tap_stall; // To ctu_dft of ctu_dft.v
input iob_tap_vld; // To ctu_dft of ctu_dft.v
input jbi_ctu_tr; // To ctu_clsp of ctu_clsp.v
input jbus_gclk; // To u_jbus_header of bw_clk_cl_ctu_jbus.v
input jbus_gclk_cts; // To u_jbus_gclk_dr of bw_u1_ckbuf_30x.v
input jbus_gclk_dup; // To u_pll of bw_pll.v
input jbus_grst_l; // To u_jbus_header of bw_clk_cl_ctu_jbus.v
input pads_ctu_bsi; // To ctu_dft of ctu_dft.v
input pads_ctu_si; // To ctu_dft of ctu_dft.v
input sctag0_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input sctag0_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input sctag0_ctu_tr; // To ctu_clsp of ctu_clsp.v
input sctag1_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input sctag1_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input sctag1_ctu_tr; // To ctu_clsp of ctu_clsp.v
input sctag2_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input sctag2_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input sctag2_ctu_serial_scan_in;// To ctu_dft of ctu_dft.v
input sctag2_ctu_tr; // To ctu_clsp of ctu_clsp.v
input sctag3_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input sctag3_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input sctag3_ctu_tr; // To ctu_clsp of ctu_clsp.v
input spc0_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input spc0_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input spc0_ctu_sscan_out; // To ctu_dft of ctu_dft.v
input spc1_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input spc1_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input spc1_ctu_sscan_out; // To ctu_dft of ctu_dft.v
input spc2_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input spc2_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input spc2_ctu_sscan_out; // To ctu_dft of ctu_dft.v
input spc3_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input spc3_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input spc3_ctu_sscan_out; // To ctu_dft of ctu_dft.v
input spc4_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input spc4_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input spc4_ctu_sscan_out; // To ctu_dft of ctu_dft.v
input spc5_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input spc5_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input spc5_ctu_sscan_out; // To ctu_dft of ctu_dft.v
input spc6_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input spc6_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input spc6_ctu_sscan_out; // To ctu_dft of ctu_dft.v
input spc7_ctu_mbistdone; // To ctu_dft of ctu_dft.v
input spc7_ctu_mbisterr; // To ctu_dft of ctu_dft.v
input spc7_ctu_sscan_out; // To ctu_dft of ctu_dft.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [5:0] clsp_bist_ctrl; // From ctu_clsp of ctu_clsp.v
wire clsp_bist_dobist; // From ctu_clsp of ctu_clsp.v
wire clsp_bist_type; // From ctu_clsp of ctu_clsp.v
wire cmp_clk; // From u_cmp_header of bw_clk_cl_ctu_cmp.v
wire cmp_gclk_int; // From u_cmp_gclk_dr of bw_u1_ckbuf_40x.v
wire cmp_grst_l; // From u_cmp_header_cmp_rst_pipe3 of dff_ns.v
wire cmp_grst_pipe1_l; // From u_cmp_header_cmp_rst_pipe1 of dff_ns.v
wire cmp_grst_pipe2_l; // From u_cmp_header_cmp_rst_pipe2 of dff_ns.v
wire cmp_pre_rst_l; // From u_cmp_header of bw_clk_cl_ctu_cmp.v
wire cmp_rst_l; // From u_cmp_header_cmp_rst_l of dffrl_async_ns.v
wire ctu_ddr0_iodll_rst_l_tmp;// From ctu_clsp of ctu_clsp.v
wire ctu_ddr1_iodll_rst_l_tmp;// From ctu_clsp of ctu_clsp.v
wire ctu_ddr2_iodll_rst_l_tmp;// From ctu_clsp of ctu_clsp.v
wire ctu_ddr3_iodll_rst_l_tmp;// From ctu_clsp of ctu_clsp.v
wire ctu_dram_tx_sync_early; // From u_sync_header of ctu_sync_header.v
wire [2:0] ctu_sel_cpu; // From ctu_dft of ctu_dft.v
wire [2:0] ctu_sel_dram; // From ctu_dft of ctu_dft.v
wire [2:0] ctu_sel_jbus; // From ctu_dft of ctu_dft.v
wire dft_clsp_nstep_capture_l;// From ctu_dft of ctu_dft.v
wire dft_ctu_scan_disable; // From ctu_dft of ctu_dft.v
wire dft_pin_pscan_l; // From ctu_dft of ctu_dft.v
wire dft_pll_arst_l; // From ctu_dft of ctu_dft.v
wire dft_pll_clamp_fltr; // From ctu_dft of ctu_dft.v
wire [5:0] dft_pll_div2; // From ctu_dft of ctu_dft.v
wire dft_pll_testmode; // From ctu_dft of ctu_dft.v
wire dft_rng_rst_l; // From ctu_dft of ctu_dft.v
wire [2:0] dft_rng_vctrl; // From ctu_dft of ctu_dft.v
wire dft_tdo; // From ctu_dft of ctu_dft.v
wire [9:1] dft_tsr_div; // From ctu_dft of ctu_dft.v
wire dft_tsr_reset_l; // From ctu_dft of ctu_dft.v
wire [7:0] dft_tsr_tsel; // From ctu_dft of ctu_dft.v
wire dft_wake_thr; // From ctu_dft of ctu_dft.v
wire dram_gclk_int; // From u_dram_gclk_dr of bw_u1_ckbuf_30x.v
wire jbus_clk; // From u_jbus_header of bw_clk_cl_ctu_jbus.v
wire jbus_gclk_int; // From u_jbus_gclk_dr of bw_u1_ckbuf_30x.v
wire jbus_rst_l; // From u_jbus_header of bw_clk_cl_ctu_jbus.v
wire jbus_rx_sync; // From u_sync_header of ctu_sync_header.v
wire jbus_tx_sync; // From u_sync_header of ctu_sync_header.v
wire jtag_clock_dr; // From ctu_dft of ctu_dft.v
wire jtag_clsp_force_cken_cmp;// From ctu_dft of ctu_dft.v
wire jtag_clsp_force_cken_dram;// From ctu_dft of ctu_dft.v
wire jtag_clsp_force_cken_jbus;// From ctu_dft of ctu_dft.v
wire jtag_clsp_ignore_wrm_rst;// From ctu_dft of ctu_dft.v
wire jtag_clsp_sel_tck2; // From ctu_dft of ctu_dft.v
wire [5:0] jtag_clsp_stop_id; // From ctu_dft of ctu_dft.v
wire jtag_clsp_stop_id_vld; // From ctu_dft of ctu_dft.v
wire [3:0] jtag_id; // From u_revision of ctu_revision.v
wire [3:0] jtag_nstep_count; // From ctu_dft of ctu_dft.v
wire [2:0] jtag_nstep_domain; // From ctu_dft of ctu_dft.v
wire jtag_nstep_vld; // From ctu_dft of ctu_dft.v
wire [3:0] mask_major_id; // From u_revision of ctu_revision.v
wire [3:0] mask_minor_id; // From u_revision of ctu_revision.v
wire pll_bypass; // From ctu_dft of ctu_dft.v
wire pll_clk_out; // From u_pll_clkdr0 of bw_clk_cl_ctu_2xcmp.v
wire pll_clk_out_l; // From u_pll_clkdr1 of bw_clk_cl_ctu_2xcmp_b.v
wire pll_clk_out_pre; // From u_pll of bw_pll.v
wire pll_clk_out_pre_l; // From u_pll of bw_pll.v
wire pll_raw_clk_out; // From u_pll of bw_pll.v
wire pll_reset_ref_l; // From ctu_clsp of ctu_clsp.v
wire se; // From u_test_stub of ctu_test_stub_scan.v
wire start_clk_early_jl; // From ctu_clsp of ctu_clsp.v
wire start_clk_jl; // From ctu_clsp of ctu_clsp.v
wire tck_cts; // From u_tck_dr of bw_u1_ckbuf_30x.v
wire tck_l_cts; // From u_tck_l_dr of bw_u1_inv_30x.v
wire testmode_l; // From ctu_dft of ctu_dft.v
// End of automatics
wire ctu_tst_pre_grst_l;
wire MT_long_chain_so_0;
//synopsys translate_off
// check to see all clk select should be 1 hot
always @ ( /*AUTOSENSE*/ctu_sel_cpu or ctu_sel_dram
or ctu_sel_jbus or io_trst_l)
begin
#1 ; // wait for comb logic to settle
if( (io_trst_l === 1'b1) &
(ctu_sel_cpu[2:0] !== 3'b100) &
(ctu_sel_cpu[2:0] !== 3'b010) &
(ctu_sel_cpu[2:0] !== 3'b001)
)
`ifdef MODELSIM
$display ( "CTU_not_one_hot_error",
"Select signals to cmp clkswitch are not one hot: %h",
ctu_sel_cpu[2:0] );
`else
$error ( "CTU_not_one_hot_error",
"Select signals to cmp clkswitch are not one hot: %h",
ctu_sel_cpu[2:0] );
`endif
if( (io_trst_l === 1'b1) &
(ctu_sel_dram[2:0] !== 3'b100) &
(ctu_sel_dram[2:0] !== 3'b010) &
(ctu_sel_dram[2:0] !== 3'b001)
)
`ifdef MODELSIM
$display ( "CTU_not_one_hot_error",
"Select signals to dram clkswitch are not one hot: %h",
ctu_sel_dram[2:0] );
`else
$error ( "CTU_not_one_hot_error",
"Select signals to dram clkswitch are not one hot: %h",
ctu_sel_dram[2:0] );
`endif
if( (io_trst_l === 1'b1) &
(ctu_sel_jbus[2:0] !== 3'b100) &
(ctu_sel_jbus[2:0] !== 3'b010) &
(ctu_sel_jbus[2:0] !== 3'b001)
)
`ifdef MODELSIM
$display ( "CTU_not_one_hot_error",
"Select signals to jbus clkswitch are not one hot: %h",
ctu_sel_jbus[2:0] );
`else
$error ( "CTU_not_one_hot_error",
"Select signals to jbus clkswitch are not one hot: %h",
ctu_sel_jbus[2:0] );
`endif
end
//synopsys translate_on
/* ctu_or2 AUTO_TEMPLATE (
.a (ctu_ddr@_iodll_rst_l_tmp),
.b (ctu_tst_scanmode),
.z (ctu_ddr@_iodll_rst_l),
); */
ctu_or2 u_ctu_ddr0_iodll_rst_l_or2_ecobug (/*AUTOINST*/
// Outputs
.z(ctu_ddr0_iodll_rst_l), // Templated
// Inputs
.a(ctu_ddr0_iodll_rst_l_tmp), // Templated
.b(ctu_tst_scanmode)); // Templated
ctu_or2 u_ctu_ddr1_iodll_rst_l_or2_ecobug (/*AUTOINST*/
// Outputs
.z(ctu_ddr1_iodll_rst_l), // Templated
// Inputs
.a(ctu_ddr1_iodll_rst_l_tmp), // Templated
.b(ctu_tst_scanmode)); // Templated
ctu_or2 u_ctu_ddr2_iodll_rst_l_or2_ecobug (/*AUTOINST*/
// Outputs
.z(ctu_ddr2_iodll_rst_l), // Templated
// Inputs
.a(ctu_ddr2_iodll_rst_l_tmp), // Templated
.b(ctu_tst_scanmode)); // Templated
ctu_or2 u_ctu_ddr3_iodll_rst_l_or2_ecobug (/*AUTOINST*/
// Outputs
.z(ctu_ddr3_iodll_rst_l), // Templated
// Inputs
.a(ctu_ddr3_iodll_rst_l_tmp), // Templated
.b(ctu_tst_scanmode)); // Templated
/* ctu_clsp AUTO_TEMPLATE (
.jbus_dupl_tst_clk (1'b0), // NOT CONNECTED YET
.ctu_sparc\([0-7]\)_cmp_cken (ctu_spc\1_cmp_cken),
.jtag_clsp_sel_cpu (ctu_sel_cpu[2:0]),
.jtag_clsp_sel_dram (ctu_sel_dram[2:0]),
.jtag_clsp_sel_jbus (ctu_sel_jbus[2:0]),
.cmp_gclk (cmp_gclk_int),
.dram_gclk (dram_gclk_int),
.jbus_gclk (jbus_gclk_int),
.ctu_ddr0_iodll_rst_l (ctu_ddr0_iodll_rst_l_tmp),
.ctu_ddr1_iodll_rst_l (ctu_ddr1_iodll_rst_l_tmp),
.ctu_ddr2_iodll_rst_l (ctu_ddr2_iodll_rst_l_tmp),
.ctu_ddr3_iodll_rst_l (ctu_ddr3_iodll_rst_l_tmp),
); */
ctu_clsp ctu_clsp
(/*AUTOINST*/
// Outputs
.clsp_bist_ctrl (clsp_bist_ctrl[5:0]),
.clsp_bist_dobist (clsp_bist_dobist),
.clsp_bist_type (clsp_bist_type),
.clsp_iob_data (clsp_iob_data[`CLK_IOB_WIDTH-1:0]),
.clsp_iob_stall (clsp_iob_stall),
.clsp_iob_vld (clsp_iob_vld),
.cmp_adbginit_l (cmp_adbginit_l),
.cmp_arst_l (cmp_arst_l),
.cmp_gclk_out (cmp_gclk_out),
.cmp_gdbginit_out_l (cmp_gdbginit_out_l),
.cmp_grst_out_l (cmp_grst_out_l),
.ctu_ccx_cmp_cken (ctu_ccx_cmp_cken),
.ctu_dbg_jbus_cken (ctu_dbg_jbus_cken),
.ctu_ddr0_dll_delayctr (ctu_ddr0_dll_delayctr[2:0]),
.ctu_ddr0_dram_cken (ctu_ddr0_dram_cken),
.ctu_ddr1_dll_delayctr (ctu_ddr1_dll_delayctr[2:0]),
.ctu_ddr1_dram_cken (ctu_ddr1_dram_cken),
.ctu_ddr1_iodll_rst_l (ctu_ddr1_iodll_rst_l_tmp), // Templated
.ctu_ddr2_dll_delayctr (ctu_ddr2_dll_delayctr[2:0]),
.ctu_ddr2_dram_cken (ctu_ddr2_dram_cken),
.ctu_ddr2_iodll_rst_l (ctu_ddr2_iodll_rst_l_tmp), // Templated
.ctu_ddr3_dll_delayctr (ctu_ddr3_dll_delayctr[2:0]),
.ctu_ddr3_dram_cken (ctu_ddr3_dram_cken),
.ctu_ddr3_iodll_rst_l (ctu_ddr3_iodll_rst_l_tmp), // Templated
.ctu_dll0_byp_l (ctu_dll0_byp_l),
.ctu_dll0_byp_val (ctu_dll0_byp_val[4:0]),
.ctu_dll1_byp_l (ctu_dll1_byp_l),
.ctu_dll1_byp_val (ctu_dll1_byp_val[4:0]),
.ctu_dll2_byp_l (ctu_dll2_byp_l),
.ctu_dll2_byp_val (ctu_dll2_byp_val[4:0]),
.ctu_dll3_byp_l (ctu_dll3_byp_l),
.ctu_dll3_byp_val (ctu_dll3_byp_val[4:0]),
.ctu_dram02_cmp_cken (ctu_dram02_cmp_cken),
.ctu_dram02_dram_cken (ctu_dram02_dram_cken),
.ctu_dram02_jbus_cken (ctu_dram02_jbus_cken),
.ctu_dram13_cmp_cken (ctu_dram13_cmp_cken),
.ctu_dram13_dram_cken (ctu_dram13_dram_cken),
.ctu_dram13_jbus_cken (ctu_dram13_jbus_cken),
.ctu_dram_rx_sync_out (ctu_dram_rx_sync_out),
.ctu_dram_selfrsh (ctu_dram_selfrsh),
.ctu_dram_tx_sync_out (ctu_dram_tx_sync_out),
.ctu_efc_jbus_cken (ctu_efc_jbus_cken),
.ctu_efc_read_start (ctu_efc_read_start),
.ctu_fpu_cmp_cken (ctu_fpu_cmp_cken),
.ctu_io_j_err (ctu_io_j_err),
.ctu_iob_cmp_cken (ctu_iob_cmp_cken),
.ctu_iob_jbus_cken (ctu_iob_jbus_cken),
.ctu_iob_resetstat (ctu_iob_resetstat[2:0]),
.ctu_iob_resetstat_wr (ctu_iob_resetstat_wr),
.ctu_iob_wake_thr (ctu_iob_wake_thr),
.ctu_jbi_cmp_cken (ctu_jbi_cmp_cken),
.ctu_jbi_jbus_cken (ctu_jbi_jbus_cken),
.ctu_jbi_ssiclk (ctu_jbi_ssiclk),
.ctu_jbus_tx_sync_out (ctu_jbus_tx_sync_out),
.ctu_jbusl_jbus_cken (ctu_jbusl_jbus_cken),
.ctu_jbusr_jbus_cken (ctu_jbusr_jbus_cken),
.ctu_misc_jbus_cken (ctu_misc_jbus_cken),
.ctu_scdata0_cmp_cken (ctu_scdata0_cmp_cken),
.ctu_scdata1_cmp_cken (ctu_scdata1_cmp_cken),
.ctu_scdata2_cmp_cken (ctu_scdata2_cmp_cken),
.ctu_scdata3_cmp_cken (ctu_scdata3_cmp_cken),
.ctu_sctag0_cmp_cken (ctu_sctag0_cmp_cken),
.ctu_sctag1_cmp_cken (ctu_sctag1_cmp_cken),
.ctu_sctag2_cmp_cken (ctu_sctag2_cmp_cken),
.ctu_sctag3_cmp_cken (ctu_sctag3_cmp_cken),
.ctu_sparc0_cmp_cken (ctu_spc0_cmp_cken), // Templated
.ctu_sparc1_cmp_cken (ctu_spc1_cmp_cken), // Templated
.ctu_sparc2_cmp_cken (ctu_spc2_cmp_cken), // Templated
.ctu_sparc3_cmp_cken (ctu_spc3_cmp_cken), // Templated
.ctu_sparc4_cmp_cken (ctu_spc4_cmp_cken), // Templated
.ctu_sparc5_cmp_cken (ctu_spc5_cmp_cken), // Templated
.ctu_sparc6_cmp_cken (ctu_spc6_cmp_cken), // Templated
.ctu_sparc7_cmp_cken (ctu_spc7_cmp_cken), // Templated
.ctu_spc_const_maskid (ctu_spc_const_maskid[7:0]),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.dram_adbginit_l (dram_adbginit_l),
.dram_arst_l (dram_arst_l),
.dram_gclk_out (dram_gclk_out),
.dram_gdbginit_out_l (dram_gdbginit_out_l),
.dram_grst_out_l (dram_grst_out_l),
.jbus_adbginit_l (jbus_adbginit_l),
.jbus_arst_l (jbus_arst_l),
.jbus_gclk_dup_out (jbus_gclk_dup_out),
.jbus_gclk_out (jbus_gclk_out),
.jbus_gdbginit_out_l (jbus_gdbginit_out_l),
.jbus_grst_out_l (jbus_grst_out_l),
.pll_reset_ref_l (pll_reset_ref_l),
.ctu_ddr0_iodll_rst_l (ctu_ddr0_iodll_rst_l_tmp), // Templated
.ctu_jbus_rx_sync_out (ctu_jbus_rx_sync_out),
.start_clk_jl (start_clk_jl),
.start_clk_early_jl (start_clk_early_jl),
// Inputs
.cmp_clk (cmp_clk),
.cmp_gclk (cmp_gclk_int), // Templated
.ctu_dram_tx_sync_early (ctu_dram_tx_sync_early),
.ddr0_ctu_dll_lock (ddr0_ctu_dll_lock),
.ddr0_ctu_dll_overflow (ddr0_ctu_dll_overflow),
.ddr1_ctu_dll_lock (ddr1_ctu_dll_lock),
.ddr1_ctu_dll_overflow (ddr1_ctu_dll_overflow),
.ddr2_ctu_dll_lock (ddr2_ctu_dll_lock),
.ddr2_ctu_dll_overflow (ddr2_ctu_dll_overflow),
.ddr3_ctu_dll_lock (ddr3_ctu_dll_lock),
.ddr3_ctu_dll_overflow (ddr3_ctu_dll_overflow),
.dft_clsp_nstep_capture_l (dft_clsp_nstep_capture_l),
.dft_wake_thr (dft_wake_thr),
.dll0_ctu_ctrl (dll0_ctu_ctrl[4:0]),
.dll1_ctu_ctrl (dll1_ctu_ctrl[4:0]),
.dll2_ctu_ctrl (dll2_ctu_ctrl[4:0]),
.dll3_ctu_ctrl (dll3_ctu_ctrl[4:0]),
.dram02_ctu_tr (dram02_ctu_tr),
.dram13_ctu_tr (dram13_ctu_tr),
.dram_gclk (dram_gclk_int), // Templated
.io_clk_stretch (io_clk_stretch),
.io_do_bist (io_do_bist),
.io_j_rst_l (io_j_rst_l),
.io_pll_char_in (io_pll_char_in),
.io_pwron_rst_l (io_pwron_rst_l),
.io_tck2 (io_tck2),
.iob_clsp_data (iob_clsp_data[`IOB_CLK_WIDTH-1:0]),
.iob_clsp_stall (iob_clsp_stall),
.iob_clsp_vld (iob_clsp_vld),
.iob_ctu_l2_tr (iob_ctu_l2_tr),
.iob_ctu_tr (iob_ctu_tr),
.jbi_ctu_tr (jbi_ctu_tr),
.jbus_clk (jbus_clk),
.jbus_gclk (jbus_gclk_int), // Templated
.jbus_rst_l (jbus_rst_l),
.jbus_rx_sync (jbus_rx_sync),
.jbus_tx_sync (jbus_tx_sync),
.jtag_clock_dr (jtag_clock_dr),
.jtag_clsp_force_cken_cmp (jtag_clsp_force_cken_cmp),
.jtag_clsp_force_cken_dram (jtag_clsp_force_cken_dram),
.jtag_clsp_force_cken_jbus (jtag_clsp_force_cken_jbus),
.jtag_clsp_ignore_wrm_rst (jtag_clsp_ignore_wrm_rst),
.jtag_clsp_sel_cpu (ctu_sel_cpu[2:0]), // Templated
.jtag_clsp_sel_dram (ctu_sel_dram[2:0]), // Templated
.jtag_clsp_sel_jbus (ctu_sel_jbus[2:0]), // Templated
.jtag_clsp_sel_tck2 (jtag_clsp_sel_tck2),
.jtag_clsp_stop_id (jtag_clsp_stop_id[5:0]),
.jtag_clsp_stop_id_vld (jtag_clsp_stop_id_vld),
.jtag_nstep_count (jtag_nstep_count[3:0]),
.jtag_nstep_domain (jtag_nstep_domain[2:0]),
.jtag_nstep_vld (jtag_nstep_vld),
.mask_major_id (mask_major_id[3:0]),
.mask_minor_id (mask_minor_id[3:0]),
.pll_clk_out (pll_clk_out),
.pll_clk_out_l (pll_clk_out_l),
.pll_clk_out_pre (pll_clk_out_pre),
.pll_clk_out_pre_l (pll_clk_out_pre_l),
.pll_raw_clk_out (pll_raw_clk_out),
.sctag0_ctu_tr (sctag0_ctu_tr),
.sctag1_ctu_tr (sctag1_ctu_tr),
.sctag2_ctu_tr (sctag2_ctu_tr),
.sctag3_ctu_tr (sctag3_ctu_tr),
.se (se),
.testmode_l (testmode_l));
/* ctu_dft AUTO_TEMPLATE (
.rt_data_in (afi_rt_data_in[]),
.pscan_mode_pin (afi_pscan_mode),
.pll_bypass_pin (afi_bypass_mode),
.rt_high_low (afi_rt_high_low),
.rt_read_write (afi_rt_read_write),
.rt_addr_data (afi_rt_addr_data),
.rt_valid (afi_rt_valid),
.rt_data_out (afo_rt_data_out[]),
.rt_ack (afo_rt_ack),
.shift_en_pin (afi_shift_en),
.bist_mode_pin (afi_bist_mode),
.test_mode_pin (io_test_mode),
.io_tdo_en (ctu_io_tdo_en),
.cmp_rx_en (jbus_rx_sync),
.cmp_tx_en (jbus_tx_sync),
.io_tck (tck_cts),
.tck_l (tck_l_cts),
); */
ctu_dft ctu_dft
(/*AUTOINST*/
// Outputs
.ctu_ddr0_clock_dr (ctu_ddr0_clock_dr),
.ctu_ddr0_hiz_l (ctu_ddr0_hiz_l),
.ctu_ddr0_mode_ctl (ctu_ddr0_mode_ctl),
.ctu_ddr0_shift_dr (ctu_ddr0_shift_dr),
.ctu_ddr0_update_dr (ctu_ddr0_update_dr),
.ctu_ddr1_clock_dr (ctu_ddr1_clock_dr),
.ctu_ddr1_hiz_l (ctu_ddr1_hiz_l),
.ctu_ddr1_mode_ctl (ctu_ddr1_mode_ctl),
.ctu_ddr1_shift_dr (ctu_ddr1_shift_dr),
.ctu_ddr1_update_dr (ctu_ddr1_update_dr),
.ctu_ddr2_clock_dr (ctu_ddr2_clock_dr),
.ctu_ddr2_hiz_l (ctu_ddr2_hiz_l),
.ctu_ddr2_mode_ctl (ctu_ddr2_mode_ctl),
.ctu_ddr2_shift_dr (ctu_ddr2_shift_dr),
.ctu_ddr2_update_dr (ctu_ddr2_update_dr),
.ctu_ddr3_clock_dr (ctu_ddr3_clock_dr),
.ctu_ddr3_hiz_l (ctu_ddr3_hiz_l),
.ctu_ddr3_mode_ctl (ctu_ddr3_mode_ctl),
.ctu_ddr3_shift_dr (ctu_ddr3_shift_dr),
.ctu_ddr3_update_dr (ctu_ddr3_update_dr),
.ctu_ddr_testmode_l (ctu_ddr_testmode_l),
.ctu_debug_clock_dr (ctu_debug_clock_dr),
.ctu_debug_hiz_l (ctu_debug_hiz_l),
.ctu_debug_mode_ctl (ctu_debug_mode_ctl),
.ctu_debug_shift_dr (ctu_debug_shift_dr),
.ctu_debug_update_dr (ctu_debug_update_dr),
.ctu_efc_capturedr (ctu_efc_capturedr),
.ctu_efc_coladdr (ctu_efc_coladdr[4:0]),
.ctu_efc_data_in (ctu_efc_data_in),
.ctu_efc_dest_sample (ctu_efc_dest_sample),
.ctu_efc_fuse_bypass (ctu_efc_fuse_bypass),
.ctu_efc_read_en (ctu_efc_read_en),
.ctu_efc_read_mode (ctu_efc_read_mode[2:0]),
.ctu_efc_rowaddr (ctu_efc_rowaddr[6:0]),
.ctu_efc_shiftdr (ctu_efc_shiftdr),
.ctu_efc_tck (ctu_efc_tck),
.ctu_efc_updatedr (ctu_efc_updatedr),
.ctu_fpu_so (ctu_fpu_so),
.ctu_global_snap (ctu_global_snap),
.ctu_jbusl_clock_dr (ctu_jbusl_clock_dr),
.ctu_jbusl_hiz_l (ctu_jbusl_hiz_l),
.ctu_jbusl_mode_ctl (ctu_jbusl_mode_ctl),
.ctu_jbusl_shift_dr (ctu_jbusl_shift_dr),
.ctu_jbusl_update_dr (ctu_jbusl_update_dr),
.ctu_jbusr_clock_dr (ctu_jbusr_clock_dr),
.ctu_jbusr_hiz_l (ctu_jbusr_hiz_l),
.ctu_jbusr_mode_ctl (ctu_jbusr_mode_ctl),
.ctu_jbusr_shift_dr (ctu_jbusr_shift_dr),
.ctu_jbusr_update_dr (ctu_jbusr_update_dr),
.ctu_misc_clock_dr (ctu_misc_clock_dr),
.ctu_misc_hiz_l (ctu_misc_hiz_l),
.ctu_misc_mode_ctl (ctu_misc_mode_ctl),
.ctu_misc_shift_dr (ctu_misc_shift_dr),
.ctu_misc_update_dr (ctu_misc_update_dr),
.ctu_pads_bso (ctu_pads_bso),
.ctu_pads_so (ctu_pads_so),
.ctu_pads_sscan_update (ctu_pads_sscan_update),
.ctu_sctag0_mbisten (ctu_sctag0_mbisten),
.ctu_sctag1_mbisten (ctu_sctag1_mbisten),
.ctu_sctag2_mbisten (ctu_sctag2_mbisten),
.ctu_sctag3_mbisten (ctu_sctag3_mbisten),
.ctu_sel_cpu (ctu_sel_cpu[2:0]),
.ctu_sel_dram (ctu_sel_dram[2:0]),
.ctu_sel_jbus (ctu_sel_jbus[2:0]),
.ctu_spc0_mbisten (ctu_spc0_mbisten),
.ctu_spc0_sscan_se (ctu_spc0_sscan_se),
.ctu_spc0_tck (ctu_spc0_tck),
.ctu_spc1_mbisten (ctu_spc1_mbisten),
.ctu_spc1_sscan_se (ctu_spc1_sscan_se),
.ctu_spc1_tck (ctu_spc1_tck),
.ctu_spc2_mbisten (ctu_spc2_mbisten),
.ctu_spc2_sscan_se (ctu_spc2_sscan_se),
.ctu_spc2_tck (ctu_spc2_tck),
.ctu_spc3_mbisten (ctu_spc3_mbisten),
.ctu_spc3_sscan_se (ctu_spc3_sscan_se),
.ctu_spc3_tck (ctu_spc3_tck),
.ctu_spc4_mbisten (ctu_spc4_mbisten),
.ctu_spc4_sscan_se (ctu_spc4_sscan_se),
.ctu_spc4_tck (ctu_spc4_tck),
.ctu_spc5_mbisten (ctu_spc5_mbisten),
.ctu_spc5_sscan_se (ctu_spc5_sscan_se),
.ctu_spc5_tck (ctu_spc5_tck),
.ctu_spc6_mbisten (ctu_spc6_mbisten),
.ctu_spc6_sscan_se (ctu_spc6_sscan_se),
.ctu_spc6_tck (ctu_spc6_tck),
.ctu_spc7_mbisten (ctu_spc7_mbisten),
.ctu_spc7_sscan_se (ctu_spc7_sscan_se),
.ctu_spc7_tck (ctu_spc7_tck),
.ctu_spc_sscan_tid (ctu_spc_sscan_tid[3:0]),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.ctu_tst_short_chain (ctu_tst_short_chain),
.dft_clsp_nstep_capture_l (dft_clsp_nstep_capture_l),
.dft_ctu_scan_disable (dft_ctu_scan_disable),
.dft_pin_pscan_l (dft_pin_pscan_l),
.dft_pll_arst_l (dft_pll_arst_l),
.dft_pll_clamp_fltr (dft_pll_clamp_fltr),
.dft_pll_div2 (dft_pll_div2[5:0]),
.dft_pll_testmode (dft_pll_testmode),
.dft_rng_rst_l (dft_rng_rst_l),
.dft_rng_vctrl (dft_rng_vctrl[2:0]),
.dft_tdo (dft_tdo),
.dft_tsr_div (dft_tsr_div[9:1]),
.dft_tsr_reset_l (dft_tsr_reset_l),
.dft_tsr_tsel (dft_tsr_tsel[7:0]),
.dft_wake_thr (dft_wake_thr),
.global_scan_bypass_en (global_scan_bypass_en),
.global_shift_enable (global_shift_enable),
.io_tdo_en (ctu_io_tdo_en), // Templated
.jtag_clock_dr (jtag_clock_dr),
.jtag_clsp_force_cken_cmp (jtag_clsp_force_cken_cmp),
.jtag_clsp_force_cken_dram (jtag_clsp_force_cken_dram),
.jtag_clsp_force_cken_jbus (jtag_clsp_force_cken_jbus),
.jtag_clsp_ignore_wrm_rst (jtag_clsp_ignore_wrm_rst),
.jtag_clsp_sel_tck2 (jtag_clsp_sel_tck2),
.jtag_clsp_stop_id (jtag_clsp_stop_id[5:0]),
.jtag_clsp_stop_id_vld (jtag_clsp_stop_id_vld),
.jtag_nstep_count (jtag_nstep_count[3:0]),
.jtag_nstep_domain (jtag_nstep_domain[2:0]),
.jtag_nstep_vld (jtag_nstep_vld),
.pll_bypass (pll_bypass),
.pscan_select (pscan_select),
.rt_ack (afo_rt_ack), // Templated
.rt_data_out (afo_rt_data_out[31:0]), // Templated
.tap_iob_data (tap_iob_data[7:0]),
.tap_iob_stall (tap_iob_stall),
.tap_iob_vld (tap_iob_vld),
.testmode_l (testmode_l),
// Inputs
.afi_pll_char_mode (afi_pll_char_mode),
.afi_pll_clamp_fltr (afi_pll_clamp_fltr),
.afi_pll_div2 (afi_pll_div2[5:0]),
.afi_pll_trst_l (afi_pll_trst_l),
.afi_rng_ctl (afi_rng_ctl[2:0]),
.afi_tsr_div (afi_tsr_div[9:1]),
.afi_tsr_mode (afi_tsr_mode),
.afi_tsr_tsel (afi_tsr_tsel[7:0]),
.bist_mode_pin (afi_bist_mode), // Templated
.clsp_bist_ctrl (clsp_bist_ctrl[5:0]),
.clsp_bist_dobist (clsp_bist_dobist),
.clsp_bist_type (clsp_bist_type),
.cmp_clk (cmp_clk),
.cmp_rst_l (cmp_rst_l),
.cmp_rx_en (jbus_rx_sync), // Templated
.cmp_tx_en (jbus_tx_sync), // Templated
.efc_ctu_data_out (efc_ctu_data_out),
.io_pwron_rst_l (io_pwron_rst_l),
.io_tck (tck_cts), // Templated
.io_tdi (io_tdi),
.io_tms (io_tms),
.io_trst_l (io_trst_l),
.iob_ctu_coreavail (iob_ctu_coreavail[`IOB_CPU_WIDTH-1:0]),
.iob_tap_data (iob_tap_data[7:0]),
.iob_tap_stall (iob_tap_stall),
.iob_tap_vld (iob_tap_vld),
.jbus_clk (jbus_clk),
.jbus_rst_l (jbus_rst_l),
.jtag_id (jtag_id[3:0]),
.pads_ctu_bsi (pads_ctu_bsi),
.pads_ctu_si (pads_ctu_si),
.pll_bypass_pin (afi_bypass_mode), // Templated
.pll_reset_ref_l (pll_reset_ref_l),
.rt_addr_data (afi_rt_addr_data), // Templated
.rt_data_in (afi_rt_data_in[31:0]), // Templated
.rt_high_low (afi_rt_high_low), // Templated
.rt_read_write (afi_rt_read_write), // Templated
.rt_valid (afi_rt_valid), // Templated
.sctag0_ctu_mbistdone (sctag0_ctu_mbistdone),
.sctag0_ctu_mbisterr (sctag0_ctu_mbisterr),
.sctag1_ctu_mbistdone (sctag1_ctu_mbistdone),
.sctag1_ctu_mbisterr (sctag1_ctu_mbisterr),
.sctag2_ctu_mbistdone (sctag2_ctu_mbistdone),
.sctag2_ctu_mbisterr (sctag2_ctu_mbisterr),
.sctag2_ctu_serial_scan_in (sctag2_ctu_serial_scan_in),
.sctag3_ctu_mbistdone (sctag3_ctu_mbistdone),
.sctag3_ctu_mbisterr (sctag3_ctu_mbisterr),
.spc0_ctu_mbistdone (spc0_ctu_mbistdone),
.spc0_ctu_mbisterr (spc0_ctu_mbisterr),
.spc0_ctu_sscan_out (spc0_ctu_sscan_out),
.spc1_ctu_mbistdone (spc1_ctu_mbistdone),
.spc1_ctu_mbisterr (spc1_ctu_mbisterr),
.spc1_ctu_sscan_out (spc1_ctu_sscan_out),
.spc2_ctu_mbistdone (spc2_ctu_mbistdone),
.spc2_ctu_mbisterr (spc2_ctu_mbisterr),
.spc2_ctu_sscan_out (spc2_ctu_sscan_out),
.spc3_ctu_mbistdone (spc3_ctu_mbistdone),
.spc3_ctu_mbisterr (spc3_ctu_mbisterr),
.spc3_ctu_sscan_out (spc3_ctu_sscan_out),
.spc4_ctu_mbistdone (spc4_ctu_mbistdone),
.spc4_ctu_mbisterr (spc4_ctu_mbisterr),
.spc4_ctu_sscan_out (spc4_ctu_sscan_out),
.spc5_ctu_mbistdone (spc5_ctu_mbistdone),
.spc5_ctu_mbisterr (spc5_ctu_mbisterr),
.spc5_ctu_sscan_out (spc5_ctu_sscan_out),
.spc6_ctu_mbistdone (spc6_ctu_mbistdone),
.spc6_ctu_mbisterr (spc6_ctu_mbisterr),
.spc6_ctu_sscan_out (spc6_ctu_sscan_out),
.spc7_ctu_mbistdone (spc7_ctu_mbistdone),
.spc7_ctu_mbisterr (spc7_ctu_mbisterr),
.spc7_ctu_sscan_out (spc7_ctu_sscan_out),
.start_clk_jl (start_clk_jl),
.tck_l (tck_l_cts), // Templated
.test_mode_pin (io_test_mode)); // Templated
/* bw_rng AUTO_TEMPLATE (
.rng_data (afo_rng_data),
.rng_clk (afo_rng_clk),
// Inputs
.rst_l (dft_rng_rst_l),
.clk_jbus (jbus_clk),
.vctrl (dft_rng_vctrl[]),
.sel_bg_l (io_vreg_selbg_l),
.vsup_rng_hv18 (io_vdda_rng),
);
*/
bw_rng u_rng (/*AUTOINST*/
// Outputs
.rng_data (afo_rng_data), // Templated
.rng_clk (afo_rng_clk), // Templated
// Inputs
.vsup_rng_hv18 (io_vdda_rng), // Templated
.sel_bg_l (io_vreg_selbg_l), // Templated
.vctrl (dft_rng_vctrl[2:0]), // Templated
.clk_jbus (jbus_clk), // Templated
.rst_l (dft_rng_rst_l)); // Templated
/* bw_pll AUTO_TEMPLATE (
// Inputs:
.pll_sys_clk ({io_j_clk[1],io_j_clk[0]}), // Differential System Clock Inputs
.pll_bypass (pll_bypass), // ctu_pll_bypass or bypass mode pin
.pll_arst_l (dft_pll_arst_l), // PLL Asynchronous Reset, active low
.l2clk (jbus_gclk_dup), // Feedback Clock from l2clk duplicated Grid
.pll_clamp_fltr (dft_pll_clamp_fltr),
.pll_div1 (6'b00_0000), // Frequency Divider 1 : Input Reference, cnt=div1+1
// For Niagara div1=0, => divide by 1
.pll_div2 (dft_pll_div2[]), // Frequency Divider 2 : Feedback Clock , cnt=div2+1
// Program div2 to desired VCO frequency.
// Ex. sys_clk=200MHz, div2=0, vco=1.6GHz, clk_out=1.6GHz
.pll_div3 (6'b00_0000), // Frequency Divider 3 : Clocktree Drive, cnt=div3+1
// For Niagara div3=0, => divide by 1
.vdd_pll (io_vdda_pll), // Vdd for PLL
.pll_char_in (io_pll_char_in), // Characterization In - gated with tesa_mode
.testmode (dft_pll_testmode), // PLL Test Mode. Default=0
.vreg_seldb_l (io_vreg_selbg_l), // Default=0
// Outputs:
.pll_raw_clk_out (pll_raw_clk_out),// Raw Clock Output from Differential Reciever
.pll_vco_out (), // VCO Output
.pll_clk_out (pll_clk_out_pre), // PLL Clock Output to CTU Digital
.pll_clk_out_l (pll_clk_out_pre_l), // PLL Clock Output to CTU Digital, Invert of cktree_drv
.pll_char_out (ctu_io_clkobs[]),
// pll_char_out1 is the invert of pll_char_in (which match the previous release)
// Characterization Output1 to IO
); */
bw_pll u_pll
(
/*AUTOINST*/
// Outputs
.pll_raw_clk_out (pll_raw_clk_out), // Templated
.pll_vco_out (), // Templated
.pll_clk_out (pll_clk_out_pre), // Templated
.pll_clk_out_l (pll_clk_out_pre_l), // Templated
.pll_char_out (ctu_io_clkobs[1:0]), // Templated
// Inputs
.pll_sys_clk ({io_j_clk[1],io_j_clk[0]}), // Templated
.pll_bypass (pll_bypass), // Templated
.pll_arst_l (dft_pll_arst_l), // Templated
.l2clk (jbus_gclk_dup), // Templated
.pll_clamp_fltr (dft_pll_clamp_fltr), // Templated
.pll_div1 (6'b00_0000), // Templated
.pll_div2 (dft_pll_div2[5:0]), // Templated
.pll_div3 (6'b00_0000), // Templated
.vdd_pll (io_vdda_pll), // Templated
.pll_char_in (io_pll_char_in), // Templated
.testmode (dft_pll_testmode), // Templated
.vreg_seldb_l (io_vreg_selbg_l)); // Templated
/* bw_tsr AUTO_TEMPLATE (
// Inputs:
.vdd_tsr (io_vdda_tsr), // VDD for thermo sensor
.div (dft_tsr_div[]) , // controls the macro speed, default 000011001
.clk (jbus_clk) , // jbus clock for thermo sensor
.tsel (dft_tsr_tsel[]), // test mode control, default 00000000
.reset_l (dft_tsr_reset_l),
.vreg_selbg_l (io_vreg_selbg_l),
// Outputs:
.dout (afo_tsr_dout[]), // thermo sensor output (testmode pins)
.testio (ctu_io_tsr_testio[]), // c4 bumps with ESD structures
.i50 () , //
.v0p5 () , //
); */
bw_tsr u_tsr
(
/*AUTOINST*/
// Outputs
.dout (afo_tsr_dout[7:0]), // Templated
.testio (ctu_io_tsr_testio[1:0]), // Templated
.i50 (), // Templated
.v0p5 (), // Templated
// Inputs
.vdd_tsr (io_vdda_tsr), // Templated
.div (dft_tsr_div[9:1]), // Templated
.clk (jbus_clk), // Templated
.reset_l (dft_tsr_reset_l), // Templated
.tsel (dft_tsr_tsel[7:0]), // Templated
.vreg_selbg_l (io_vreg_selbg_l)); // Templated
/* bw_clk_cl_ctu_jbus AUTO_TEMPLATE (
.so (),
.si (1'b0),
.se (se),
.cluster_cken (1'b1),
.adbginit_l (1'b1),
.gdbginit_l (1'b1),
.arst_l (io_pwron_rst_l),
.grst_l (jbus_grst_l),
.gclk (jbus_gclk ),
.rclk (jbus_clk ),
.cluster_grst_l (jbus_rst_l),
.dbginit_l (),
); */
bw_clk_cl_ctu_jbus u_jbus_header
( /*AUTOINST*/
// Outputs
.cluster_grst_l (jbus_rst_l), // Templated
.dbginit_l (), // Templated
.rclk (jbus_clk ), // Templated
.so (), // Templated
// Inputs
.adbginit_l (1'b1), // Templated
.arst_l (io_pwron_rst_l), // Templated
.cluster_cken (1'b1), // Templated
.gclk (jbus_gclk ), // Templated
.gdbginit_l (1'b1), // Templated
.grst_l (jbus_grst_l), // Templated
.se (se), // Templated
.si (1'b0)); // Templated
/* bw_clk_cl_ctu_cmp AUTO_TEMPLATE (
.so (),
.si (1'b0),
.se (1'b0),
.cluster_cken (1'b1),
.adbginit_l (1'b1),
.gdbginit_l (1'b1),
.arst_l (io_pwron_rst_l),
.grst_l (cmp_grst_l),
.gclk (cmp_gclk),
.rclk (cmp_clk ),
.cluster_grst_l (cmp_pre_rst_l),
.dbginit_l (),
); */
bw_clk_cl_ctu_cmp u_cmp_header
( /*AUTOINST*/
// Outputs
.cluster_grst_l (cmp_pre_rst_l), // Templated
.dbginit_l (), // Templated
.rclk (cmp_clk ), // Templated
.so (), // Templated
// Inputs
.adbginit_l (1'b1), // Templated
.arst_l (io_pwron_rst_l), // Templated
.cluster_cken (1'b1), // Templated
.gclk (cmp_gclk), // Templated
.gdbginit_l (1'b1), // Templated
.grst_l (cmp_grst_l), // Templated
.se (1'b0), // Templated
.si (1'b0)); // Templated
// Duplicate the cmp pipe
/* dff_ns AUTO_TEMPLATE (
.din (cmp_grst_out_l),
.q (cmp_grst_pipe1_l),
.rst_l(io_pwron_rst_l),
.clk (cmp_gclk_int),
);
*/
dff_ns u_cmp_header_cmp_rst_pipe1(/*AUTOINST*/
// Outputs
.q(cmp_grst_pipe1_l), // Templated
// Inputs
.din(cmp_grst_out_l), // Templated
.clk(cmp_gclk_int)); // Templated
/* dff_ns AUTO_TEMPLATE (
.din (cmp_grst_pipe1_l),
.q (cmp_grst_pipe2_l),
.rst_l(io_pwron_rst_l),
.clk (cmp_gclk_int),
);
*/
dff_ns u_cmp_header_cmp_rst_pipe2(/*AUTOINST*/
// Outputs
.q(cmp_grst_pipe2_l), // Templated
// Inputs
.din(cmp_grst_pipe1_l), // Templated
.clk(cmp_gclk_int)); // Templated
/* dff_ns AUTO_TEMPLATE (
.din (cmp_grst_pipe2_l),
.q (cmp_grst_l),
.rst_l(io_pwron_rst_l),
.clk (cmp_gclk_int),
);
*/
dff_ns u_cmp_header_cmp_rst_pipe3(/*AUTOINST*/
// Outputs
.q(cmp_grst_l), // Templated
// Inputs
.din(cmp_grst_pipe2_l), // Templated
.clk(cmp_gclk_int)); // Templated
/* dffrl_async_ns AUTO_TEMPLATE (
.din (cmp_pre_rst_l),
.q (cmp_rst_l),
.rst_l(io_pwron_rst_l),
.clk (cmp_clk),
);
*/
dffrl_async_ns u_cmp_header_cmp_rst_l(/*AUTOINST*/
// Outputs
.q(cmp_rst_l), // Templated
// Inputs
.din(cmp_pre_rst_l), // Templated
.clk(cmp_clk), // Templated
.rst_l(io_pwron_rst_l)); // Templated
/* ctu_sync_header AUTO_TEMPLATE (
.jbus_rx_sync(jbus_rx_sync),
.jbus_tx_sync(jbus_tx_sync),
.ctu_jbus_rx_sync(ctu_jbus_rx_sync_out),
.ctu_jbus_tx_sync(ctu_jbus_tx_sync_out),
.ctu_dram_tx_sync(ctu_dram_tx_sync_out),
.cmp_rclk(cmp_clk),
.cmp_gclk(cmp_gclk_int),
.si (1'b0),
.so (),
);
*/
ctu_sync_header u_sync_header (/*AUTOINST*/
// Outputs
.ctu_dram_tx_sync_early(ctu_dram_tx_sync_early),
.jbus_rx_sync(jbus_rx_sync), // Templated
.jbus_tx_sync(jbus_tx_sync), // Templated
.so (), // Templated
// Inputs
.cmp_clk(cmp_clk),
.cmp_gclk(cmp_gclk_int), // Templated
.ctu_dram_tx_sync(ctu_dram_tx_sync_out), // Templated
.ctu_jbus_rx_sync(ctu_jbus_rx_sync_out), // Templated
.ctu_jbus_tx_sync(ctu_jbus_tx_sync_out), // Templated
.se (se),
.si (1'b0), // Templated
.start_clk_early_jl(start_clk_early_jl));
/* bw_u1_ckbuf_30x AUTO_TEMPLATE (
.rclk (io_tck),
.clk (tck_cts),
);
*/
bw_u1_ckbuf_30x u_tck_dr (/*AUTOINST*/
// Outputs
.clk (tck_cts), // Templated
// Inputs
.rclk (io_tck)); // Templated
/* bw_u1_inv_30x AUTO_TEMPLATE (
.a(io_tck),
.z(tck_l_cts),
);
*/
bw_u1_inv_30x u_tck_l_dr (/*AUTOINST*/
// Outputs
.z (tck_l_cts), // Templated
// Inputs
.a (io_tck)); // Templated
/* bw_u1_ckbuf_40x AUTO_TEMPLATE (
.rclk (cmp_gclk_cts),
.clk (cmp_gclk_int),
);
*/
bw_u1_ckbuf_40x u_cmp_gclk_dr (/*AUTOINST*/
// Outputs
.clk (cmp_gclk_int), // Templated
// Inputs
.rclk(cmp_gclk_cts)); // Templated
/* bw_u1_ckbuf_30x AUTO_TEMPLATE (
.rclk (jbus_gclk_cts),
.clk (jbus_gclk_int),
);
*/
bw_u1_ckbuf_30x u_jbus_gclk_dr (/*AUTOINST*/
// Outputs
.clk(jbus_gclk_int), // Templated
// Inputs
.rclk(jbus_gclk_cts)); // Templated
/* bw_u1_ckbuf_30x AUTO_TEMPLATE (
.rclk (dram_gclk_cts),
.clk (dram_gclk_int),
);
*/
bw_u1_ckbuf_30x u_dram_gclk_dr (/*AUTOINST*/
// Outputs
.clk(dram_gclk_int), // Templated
// Inputs
.rclk(dram_gclk_cts)); // Templated
/* bw_clk_cl_ctu_2xcmp AUTO_TEMPLATE (
.bw_pll_2xclk (pll_clk_out_pre),
.bw_pll_2x_clk_local (pll_clk_out),
);
*/
bw_clk_cl_ctu_2xcmp u_pll_clkdr0 (/*AUTOINST*/
// Outputs
.bw_pll_2x_clk_local(pll_clk_out), // Templated
// Inputs
.bw_pll_2xclk(pll_clk_out_pre)); // Templated
/* bw_clk_cl_ctu_2xcmp_b AUTO_TEMPLATE (
.bw_pll_2xclk_b (pll_clk_out_pre_l),
.bw_pll_2x_clk_local_b (pll_clk_out_l),
);
*/
bw_clk_cl_ctu_2xcmp_b u_pll_clkdr1 (/*AUTOINST*/
// Outputs
.bw_pll_2x_clk_local_b(pll_clk_out_l), // Templated
// Inputs
.bw_pll_2xclk_b(pll_clk_out_pre_l)); // Templated
//*******************************************************************************
// Test Stub
//*******************************************************************************
/*ctu_test_stub_scan AUTO_TEMPLATE (
.ctu_tst_scan_disable (dft_ctu_scan_disable),
.ctu_tst_short_chain (dft_pin_pscan_l),
.so_0 (ctu_io_tdo),
.short_chain_so_0 (dft_tdo),
);*/
ctu_test_stub_scan u_test_stub (
.long_chain_so_0 (MT_long_chain_so_0),
/*AUTOINST*/
// Outputs
.se (se),
.so_0 (ctu_io_tdo), // Templated
// Inputs
.global_shift_enable(global_shift_enable),
.ctu_tst_scan_disable(dft_ctu_scan_disable), // Templated
.ctu_tst_short_chain(dft_pin_pscan_l), // Templated
.short_chain_so_0(dft_tdo)); // Templated
//*******************************************************************************
// Version register
//*******************************************************************************
ctu_revision u_revision ( /*AUTOINST*/
// Outputs
.jtag_id (jtag_id[3:0]),
.mask_major_id (mask_major_id[3:0]),
.mask_minor_id (mask_minor_id[3:0]));
endmodule // ctu
//synopsys translate_off
module ctu_sync_pulse_check(/*AUTOARG*/
// Inputs
data, lclk, rclk, enable_chk
);
input data;
input lclk;
input rclk;
input enable_chk;
parameter setup_clocks = 1 ,
hold_clocks = 0;
time last_clk;
time last_data;
time first_edge;
time period;
reg enable_chk_int;
always @( posedge rclk)
begin
if(enable_chk === 1'b1)
first_edge = $time;
end
always @( negedge rclk)
begin
if(enable_chk === 1'b1)
period = ($time - first_edge) * 2;
end
always @ (posedge rclk)
if( ~enable_chk)
enable_chk_int <= 1'b0;
else
enable_chk_int <= enable_chk;
always @ (posedge data)
begin
if((($time - last_clk ) < ( setup_clocks * period)) & enable_chk_int
)
`ifdef MODELSIM
$display ( "CTU_mpath_error",
"Expect setup time : %t. Actual setup time %t",
(setup_clocks * period), ($time - last_clk ));
`else
$error ( "CTU_mpath_error",
"Expect setup time : %t. Actual setup time %t",
(setup_clocks * period), ($time - last_clk ));
`endif
last_data = $time;
end
always @ ( posedge lclk)
begin
if( (($time - last_data) < ( hold_clocks * period)) & enable_chk_int
)
`ifdef MODELSIM
$display ( "CTU_mpath_error",
"Expect hold time : %t. Actual hold time %t",
(hold_clocks * period), ($time - last_data ));
`else
$error ( "CTU_mpath_error",
"Expect hold time : %t. Actual hold time %t",
(hold_clocks * period), ($time - last_data ));
`endif
last_clk = $time;
end
endmodule
//synopsys translate_on
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_BLACKBOX_V
`define SKY130_FD_SC_MS__INV_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_BLACKBOX_V
|
//Legal Notice: (C)2019 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_dut_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
nios_dut_nios2_gen2_0_cpu_debug_slave_tck the_nios_dut_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
nios_dut_nios2_gen2_0_cpu_debug_slave_sysclk the_nios_dut_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic nios_dut_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// nios_dut_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
\file "inverters.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: inverters.v,v 1.3 2010/04/06 00:08:35 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #45 $finish;
/**
// optional: produce vector file for dump
initial begin
$dumpfile ("test.dump");
$dumpvars(0,TOP);
end
**/
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__FA_BEHAVIORAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_BEHAVIORAL_PP_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off MULTIDRIVEN
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [15:0] out2; // From test of Test.v
// End of automatics
// verilator lint_on MULTIDRIVEN
Test test (
.en (crc[21:20]),
.a1 (crc[19:18]),
.a0 (crc[17:16]),
.d1 (crc[15:8]),
.d0 (crc[7:0]),
/*AUTOINST*/
// Outputs
.out (out[31:0]),
.out2 (out2[15:0]),
// Inputs
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {out2, 16'h0, out};
// Test loop
`ifdef TEST_VERBOSE
always @ (negedge clk) begin
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
end
`endif
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
test.clear();
end
else if (cyc<10) begin
sum <= 64'h0;
test.clear();
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hc68a94a34ec970aa
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, out2,
// Inputs
clk, en, a0, a1, d0, d1
);
input clk;
input [1:0] en;
input [1:0] a0;
input [1:0] a1;
input [7:0] d0;
input [7:0] d1;
output reg [31:0] out;
output reg [15:0] out2;
// verilator lint_off MULTIDRIVEN
reg [7:0] mem [4];
// verilator lint_on MULTIDRIVEN
task clear();
for (int i=0; i<4; ++i) mem[i] = 0;
endtask
always @(posedge clk) begin
if (en[0]) begin
mem[a0] <= d0;
out2[7:0] <= d0;
end
end
always @(negedge clk) begin
if (en[1]) begin
mem[a1] <= d1;
out2[15:8] <= d0;
end
end
assign out = {mem[3],mem[2],mem[1],mem[0]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTN_1_V
`define SKY130_FD_SC_HS__SDFRTN_1_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog wrapper for sdfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtn_1 (
RESET_B,
CLK_N ,
D ,
Q ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK_N ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfrtn base (
.RESET_B(RESET_B),
.CLK_N(CLK_N),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtn_1 (
RESET_B,
CLK_N ,
D ,
Q ,
SCD ,
SCE
);
input RESET_B;
input CLK_N ;
input D ;
output Q ;
input SCD ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfrtn base (
.RESET_B(RESET_B),
.CLK_N(CLK_N),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTN_1_V
|
`default_nettype none
`timescale 1ns / 1ps
`include "asserts.vh"
`include "xrs.vh"
module xrs_tb();
reg [11:0] story_to;
reg fault_to;
reg clk_i;
reg [2:0] rwe_i;
reg [4:0] ra_i, rb_i, rd_i;
reg [63:0] rdat_i;
wire [63:0] rdata_o, rdatb_o;
`STANDARD_FAULT
`DEFASSERT(rdata, 63, o)
`DEFASSERT(rdatb, 63, o)
xrs x(
.clk_i(clk_i),
.rd_i(rd_i),
.rdat_i(rdat_i),
.rwe_i(rwe_i),
.rdata_o(rdata_o),
.rdatb_o(rdatb_o),
.ra_i(ra_i),
.rb_i(rb_i)
);
always begin
#5 clk_i <= ~clk_i;
end
initial begin
$dumpfile("xrs.vcd");
$dumpvars;
{
story_to, fault_to, clk_i, rwe_i, ra_i, rb_i, rd_i,
rdat_i
} <= 0;
wait(~clk_i); wait(clk_i); #1;
// Try to store some values in the register file.
rdat_i <= 64'h1122334455667788;
rwe_i <= `XRS_RWE_S64;
rd_i <= 1;
wait(~clk_i); wait(clk_i); #1;
rdat_i <= 64'h7766554433221100;
rd_i <= 2;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_NO;
// Now try to read back the registers we just wrote.
ra_i <= 1;
rb_i <= 2;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h1122334455667788);
assert_rdatb(64'h7766554433221100);
ra_i <= 2;
rb_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h7766554433221100);
assert_rdatb(64'h1122334455667788);
ra_i <= 1;
rb_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h1122334455667788);
assert_rdatb(64'h0);
ra_i <= 0;
rb_i <= 2;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h0);
assert_rdatb(64'h7766554433221100);
// Confirm operation of sign-extension
rdat_i <= 64'h7766554433221100;
rwe_i <= `XRS_RWE_S8;
rd_i <= 1;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S16;
rd_i <= 2;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S32;
rd_i <= 3;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S64;
rd_i <= 4;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_NO;
rdat_i <= 64'h8766554483228180;
rwe_i <= `XRS_RWE_S8;
rd_i <= 5;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S16;
rd_i <= 6;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S32;
rd_i <= 7;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S64;
rd_i <= 8;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_NO;
ra_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h0000000000000000);
ra_i <= 2;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h0000000000001100);
ra_i <= 3;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h0000000033221100);
ra_i <= 4;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h7766554433221100);
ra_i <= 5;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'hFFFFFFFFFFFFFF80);
ra_i <= 6;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'hFFFFFFFFFFFF8180);
ra_i <= 7;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'hFFFFFFFF83228180);
ra_i <= 8;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h8766554483228180);
// Confirm operation of zero-extension
rdat_i <= 64'hFFFFFFFFFFFFFFFF;
rwe_i <= `XRS_RWE_U8;
rd_i <= 1;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_U16;
rd_i <= 2;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_U32;
rd_i <= 3;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_NO;
ra_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h00000000000000FF);
ra_i <= 2;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h000000000000FFFF);
ra_i <= 3;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h00000000FFFFFFFF);
#100;
$stop;
end
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.1 (lin64) Build 1215546 Mon Apr 27 19:07:21 MDT 2015
//Date : Fri Jun 5 14:04:18 2015
//Host : ubuntu running 64-bit Ubuntu 14.04.2 LTS
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: txuart.v
//
// Project: Verilog Tutorial Example file
//
// Purpose: Transmit outputs over a single UART line. This particular UART
// implementation has been extremely simplified: it does not handle
// generating break conditions, nor does it handle anything other than the
// 8N1 (8 data bits, no parity, 1 stop bit) UART sub-protocol.
//
// To interface with this module, connect it to your system clock, and
// pass it the byte of data you wish to transmit. Strobe the i_wr line
// high for one cycle, and your data will be off. Wait until the 'o_busy'
// line is low before strobing the i_wr line again--this implementation
// has NO BUFFER, so strobing i_wr while the core is busy will just
// get ignored. The output will be placed on the o_txuart output line.
//
// There are known deficiencies in the formal proof found within this
// module. These have been left behind for you (the student) to fix.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Written and distributed by Gisselquist Technology, LLC
//
// This program is hereby granted to the public domain.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
//
//
module txuart(i_clk, i_wr, i_data, o_uart_tx, o_busy);
parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
input wire i_clk;
input wire i_wr;
input wire [7:0] i_data;
// And the UART output line itself
output wire o_uart_tx;
// A line to tell others when we are ready to accept data. If
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
// for transmission.
output reg o_busy;
// Define several states
localparam [3:0] START = 4'h0,
BIT_ZERO = 4'h1,
BIT_ONE = 4'h2,
BIT_TWO = 4'h3,
BIT_THREE = 4'h4,
BIT_FOUR = 4'h5,
BIT_FIVE = 4'h6,
BIT_SIX = 4'h7,
BIT_SEVEN = 4'h8,
LAST = 4'h8,
IDLE = 4'hf;
reg [23:0] counter;
reg [3:0] state;
reg [8:0] lcl_data;
reg baud_stb;
// o_busy
//
// This is a register, designed to be true is we are ever busy above.
// originally, this was going to be true if we were ever not in the
// idle state. The logic has since become more complex, hence we have
// a register dedicated to this and just copy out that registers value.
initial o_busy = 1'b0;
initial state = IDLE;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
// Immediately start us off with a start bit
{ o_busy, state } <= { 1'b1, START };
else if (baud_stb)
begin
if (state == IDLE) // Stay in IDLE
{ o_busy, state } <= { 1'b0, IDLE };
else if (state < LAST) begin
o_busy <= 1'b1;
state <= state + 1'b1;
end else // Wait for IDLE
{ o_busy, state } <= { 1'b1, IDLE };
end
// lcl_data
//
// This is our working copy of the i_data register which we use
// when transmitting. It is only of interest during transmit, and is
// allowed to be whatever at any other time. Hence, if o_busy isn't
// true, we can always set it. On the one clock where o_busy isn't
// true and i_wr is, we set it and o_busy is true thereafter.
// Then, on any baud_stb (i.e. change between baud intervals)
// we simple logically shift the register right to grab the next bit.
initial lcl_data = 9'h1ff;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
lcl_data <= { i_data, 1'b0 };
else if (baud_stb)
lcl_data <= { 1'b1, lcl_data[8:1] };
// o_uart_tx
//
// This is the final result/output desired of this core. It's all
// centered about o_uart_tx. This is what finally needs to follow
// the UART protocol.
//
assign o_uart_tx = lcl_data[0];
// All of the above logic is driven by the baud counter. Bits must last
// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
// make certain of that.
//
// The basic logic is this: at the beginning of a bit interval, start
// the baud counter and set it to count CLOCKS_PER_BAUD. When it gets
// to zero, restart it.
//
// However, comparing a 28'bit number to zero can be rather complex--
// especially if we wish to do anything else on that same clock. For
// that reason, we create "baud_stb". baud_stb is
// nothing more than a flag that is true anytime baud_counter is zero.
// It's true when the logic (above) needs to step to the next bit.
// Simple enough?
//
// I wish we could stop there, but there are some other (ugly)
// conditions to deal with that offer exceptions to this basic logic.
//
// 1. When the user has commanded a BREAK across the line, we need to
// wait several baud intervals following the break before we start
// transmitting, to give any receiver a chance to recognize that we are
// out of the break condition, and to know that the next bit will be
// a stop bit.
//
// 2. A reset is similar to a break condition--on both we wait several
// baud intervals before allowing a start bit.
//
// 3. In the idle state, we stop our counter--so that upon a request
// to transmit when idle we can start transmitting immediately, rather
// than waiting for the end of the next (fictitious and arbitrary) baud
// interval.
//
// When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
// the idle state, but we also just accepted a command to start writing
// the next word. At this point, the baud counter needs to be reset
// to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
//
// The logic is a bit twisted here, in that it will only check for the
// above condition when baud_stb is false--so as to make
// certain the STOP bit is complete.
initial baud_stb = 1'b1;
initial counter = 0;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
begin
counter <= CLOCKS_PER_BAUD - 1'b1;
baud_stb <= 1'b0;
end else if (!baud_stb)
begin
baud_stb <= (counter == 24'h01);
counter <= counter - 1'b1;
end else if (state != IDLE)
begin
counter <= CLOCKS_PER_BAUD - 24'h01;
baud_stb <= 1'b0;
end
//
//
// FORMAL METHODS
//
//
//
`ifdef FORMAL
`ifdef TXUART
`define ASSUME assume
`else
`define ASSUME assert
`endif
// Setup
reg f_past_valid;
initial f_past_valid = 1'b0;
always @(posedge i_clk)
f_past_valid <= 1'b1;
// Any outstanding request that was busy on the last cycle,
// should remain busy on this cycle
initial `ASSUME(!i_wr);
always @(posedge i_clk)
if ((f_past_valid)&&($past(i_wr))&&($past(o_busy)))
begin
`ASSUME(i_wr == $past(i_wr));
`ASSUME(i_data == $past(i_data));
end
//////////////////////////////////
//
// The contract
//
//////////////////////////////////
reg [7:0] fv_data;
always @(posedge i_clk)
if ((i_wr)&&(!o_busy))
fv_data <= i_data;
always @(posedge i_clk)
case(state)
IDLE: assert(o_uart_tx == 1'b1);
START: assert(o_uart_tx == 1'b0);
BIT_ZERO: assert(o_uart_tx == fv_data[0]);
BIT_ONE: assert(o_uart_tx == fv_data[1]);
BIT_TWO: assert(o_uart_tx == fv_data[2]);
BIT_THREE: assert(o_uart_tx == fv_data[3]);
BIT_FOUR: assert(o_uart_tx == fv_data[4]);
BIT_FIVE: assert(o_uart_tx == fv_data[5]);
BIT_SIX: assert(o_uart_tx == fv_data[6]);
BIT_SEVEN: assert(o_uart_tx == fv_data[7]);
default: assert(0);
endcase
//////////////////////////////////
//
// Internal state checks
//
//////////////////////////////////
//
// Check the baud counter
//
// The baud_stb needs to be identical to our counter being zero
always @(posedge i_clk)
assert(baud_stb == (counter == 0));
always @(posedge i_clk)
if ((f_past_valid)&&($past(counter != 0)))
assert(counter == $past(counter - 1'b1));
always @(posedge i_clk)
assert(counter < CLOCKS_PER_BAUD);
always @(posedge i_clk)
if (!baud_stb)
assert(o_busy);
`endif // FORMAL
endmodule
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Mon Nov 14 15:54:36 EST 2016
//
// Method conflict info:
// Method: gen_grant_carry
// Conflict-free: gen_grant_carry
//
//
// Ports:
// Name I/O size props
// gen_grant_carry O 2
// gen_grant_carry_c I 1
// gen_grant_carry_r I 1
// gen_grant_carry_p I 1
//
// Combinational paths from inputs to outputs:
// (gen_grant_carry_c, gen_grant_carry_r, gen_grant_carry_p) -> gen_grant_carry
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module module_gen_grant_carry(gen_grant_carry_c,
gen_grant_carry_r,
gen_grant_carry_p,
gen_grant_carry);
// value method gen_grant_carry
input gen_grant_carry_c;
input gen_grant_carry_r;
input gen_grant_carry_p;
output [1 : 0] gen_grant_carry;
// signals for module outputs
wire [1 : 0] gen_grant_carry;
// value method gen_grant_carry
assign gen_grant_carry =
{ gen_grant_carry_r && (gen_grant_carry_c || gen_grant_carry_p),
!gen_grant_carry_r &&
(gen_grant_carry_c || gen_grant_carry_p) } ;
endmodule // module_gen_grant_carry
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Fri Oct 28 10:05:23 2016
/////////////////////////////////////////////////////////////
module mult_SW54 ( clk, Data_A_i, Data_B_i, Data_S_o );
input [53:0] Data_A_i;
input [53:0] Data_B_i;
output [107:0] Data_S_o;
input clk;
wire N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16,
N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30,
N31, N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42, N43, N44,
N45, N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56, N57, N58,
N59, N60, N61, N62, N63, N64, N65, N66, N67, N68, N69, N70, N71, N72,
N73, N74, N75, N76, N77, N78, N79, N80, N81, N82, N83, N84, N85, N86,
N87, N88, N89, N90, N91, N92, N93, N94, N95, N96, N97, N98, N99, N100,
N101, N102, N103, N104, N105, N106, N107, mult_x_1_n1532, n1, n2, n3,
n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18,
n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32,
n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112,
n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134,
n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167,
n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178,
n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266,
n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310,
n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321,
n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332,
n333, n334, n335, n336, n337, n338, n339, n340, n341, n342, n343,
n344, n345, n346, n347, n348, n349, n350, n351, n352, n353, n354,
n355, n356, n357, n358, n359, n360, n361, n362, n363, n364, n365,
n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376,
n377, n378, n379, n380, n381, n382, n383, n384, n385, n386, n387,
n388, n389, n390, n391, n392, n393, n394, n395, n396, n397, n398,
n399, n400, n401, n402, n403, n404, n405, n406, n407, n408, n409,
n410, n411, n412, n413, n414, n415, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431,
n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453,
n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486,
n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508,
n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530,
n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728,
n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750,
n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761,
n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n814, n815, n816,
n817, n818, n819, n820, n821, n822, n823, n824, n825, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882,
n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893,
n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904,
n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915,
n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926,
n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937,
n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948,
n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959,
n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970,
n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981,
n982, n983, n984, n985, n986, n987, n988, n989, n990, n991, n992,
n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003,
n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013,
n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023,
n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033,
n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043,
n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053,
n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063,
n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073,
n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083,
n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093,
n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103,
n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113,
n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123,
n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133,
n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143,
n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153,
n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163,
n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173,
n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183,
n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193,
n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203,
n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213,
n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223,
n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233,
n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243,
n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253,
n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263,
n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273,
n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283,
n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293,
n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303,
n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313,
n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323,
n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353,
n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363,
n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373,
n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383,
n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503,
n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623,
n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633,
n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643,
n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653,
n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663,
n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673,
n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683,
n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693,
n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703,
n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713,
n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723,
n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733,
n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743,
n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753,
n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763,
n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773,
n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783,
n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793,
n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803,
n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813,
n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823,
n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833,
n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843,
n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913,
n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923,
n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953,
n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103,
n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113,
n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133,
n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143,
n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153,
n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163,
n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173,
n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183,
n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193,
n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203,
n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213,
n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223,
n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233,
n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243,
n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253,
n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263,
n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273,
n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283,
n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293,
n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303,
n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313,
n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323,
n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333,
n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343,
n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273,
n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283,
n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293,
n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303,
n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313,
n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323,
n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353,
n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363,
n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373,
n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383,
n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393,
n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403,
n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413,
n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423,
n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433,
n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443,
n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453,
n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463,
n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473,
n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483,
n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493,
n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503,
n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513,
n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523,
n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533,
n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543,
n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553,
n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563,
n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573,
n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583,
n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593,
n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603,
n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613,
n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623,
n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633,
n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643,
n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723,
n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773,
n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783,
n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793,
n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803,
n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813,
n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823,
n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833,
n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843,
n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853,
n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863,
n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873,
n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883,
n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893,
n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903,
n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913,
n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923,
n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933,
n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943,
n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953,
n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963,
n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973,
n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983,
n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993,
n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003,
n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013,
n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023,
n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033,
n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043,
n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053,
n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063,
n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073,
n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083,
n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093,
n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103,
n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113,
n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123,
n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133,
n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143,
n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153,
n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163,
n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173,
n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183,
n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193,
n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203,
n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213,
n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223,
n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233,
n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243,
n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253,
n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263,
n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273,
n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283,
n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293,
n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303,
n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313,
n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323,
n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333,
n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343,
n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353,
n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363,
n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373,
n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383,
n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393,
n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403,
n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413,
n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423,
n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433,
n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443,
n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453,
n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463,
n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473,
n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483,
n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493,
n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503,
n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513,
n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523,
n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533,
n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543,
n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553,
n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563,
n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573,
n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583,
n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593,
n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603,
n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613,
n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623,
n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633,
n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643,
n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653,
n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663,
n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673,
n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683,
n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693,
n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703,
n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713,
n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723,
n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733,
n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743,
n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753,
n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763,
n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773,
n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783,
n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793,
n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803,
n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813,
n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823,
n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833,
n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843,
n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853,
n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863,
n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873,
n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883,
n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893,
n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903,
n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913,
n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923,
n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933,
n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943,
n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953,
n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963,
n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973,
n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983,
n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993,
n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003,
n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013,
n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023,
n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033,
n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043,
n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053,
n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063,
n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073,
n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083,
n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093,
n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103,
n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113,
n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123,
n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133,
n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143,
n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153,
n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163,
n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173,
n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183,
n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193,
n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203,
n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213,
n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223,
n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233,
n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243,
n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253,
n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263,
n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273,
n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283,
n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293,
n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303,
n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313,
n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323,
n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333,
n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343,
n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353,
n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363,
n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373,
n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383,
n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393,
n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403,
n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413,
n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423,
n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433,
n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443,
n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453,
n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463,
n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473,
n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483,
n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493,
n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503,
n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513,
n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523,
n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533,
n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543,
n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553,
n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563,
n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573,
n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583,
n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593,
n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603,
n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613,
n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623,
n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633,
n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643,
n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653,
n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663,
n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673,
n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683,
n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693,
n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703,
n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713,
n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723,
n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733,
n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743,
n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753,
n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763,
n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773,
n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783,
n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793,
n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803,
n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813,
n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823,
n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833,
n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843,
n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853,
n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863,
n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873,
n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883,
n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893,
n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903,
n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913,
n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923,
n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933,
n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943,
n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953,
n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963,
n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973,
n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983,
n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993,
n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003,
n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013,
n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023,
n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033,
n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043,
n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053,
n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063,
n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073,
n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083,
n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093,
n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103,
n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113,
n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123,
n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133,
n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143,
n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153,
n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163,
n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173,
n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183,
n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193,
n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203,
n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213,
n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223,
n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233,
n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243,
n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253,
n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263,
n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273,
n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283,
n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293,
n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303,
n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313,
n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323,
n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333,
n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343,
n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353,
n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363,
n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373,
n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383,
n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393,
n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403,
n6404, n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413,
n6414, n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423,
n6424, n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433,
n6434, n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443,
n6444, n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453,
n6454, n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463,
n6464, n6465, n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473,
n6474, n6475, n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483,
n6484, n6485, n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493,
n6494, n6495, n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503,
n6504, n6505, n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513,
n6514, n6515, n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523,
n6524, n6525, n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533,
n6534, n6535, n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543,
n6544, n6545, n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553,
n6554, n6555, n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563,
n6564, n6565, n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573,
n6574, n6575, n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583,
n6584, n6585, n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593,
n6594, n6595, n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603,
n6604, n6605, n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613,
n6614, n6615, n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623,
n6624, n6625, n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633,
n6634, n6635, n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643,
n6644, n6645, n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653,
n6654, n6655, n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663,
n6664, n6665, n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673,
n6674, n6675, n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683,
n6684, n6685, n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693,
n6694, n6695, n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703,
n6704, n6705, n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713,
n6714, n6715, n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723,
n6724, n6725, n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733,
n6734, n6735, n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743,
n6744, n6745, n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753,
n6754, n6755, n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763,
n6764, n6765, n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773,
n6774, n6775, n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783,
n6784, n6785, n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793,
n6794, n6795, n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803,
n6804, n6805, n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813,
n6814, n6815, n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823,
n6824, n6825, n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833,
n6834, n6835, n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843,
n6844, n6845, n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853,
n6854, n6855, n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863,
n6864, n6865, n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873,
n6874, n6875, n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883,
n6884, n6885, n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893,
n6894, n6895, n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903,
n6904, n6905, n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913,
n6914, n6915, n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923,
n6924, n6925, n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933,
n6934, n6935, n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943,
n6944, n6945, n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953,
n6954, n6955, n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963,
n6964, n6965, n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973,
n6974, n6975, n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983,
n6984, n6985, n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993,
n6994, n6995, n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003,
n7004, n7005, n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013,
n7014, n7015, n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023,
n7024, n7025, n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033,
n7034, n7035, n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043,
n7044, n7045, n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053,
n7054, n7055, n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063,
n7064, n7065, n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073,
n7074, n7075, n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083,
n7084, n7085, n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093,
n7094, n7095, n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103,
n7104, n7105, n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113,
n7114, n7115, n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123,
n7124, n7125, n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133,
n7134, n7135, n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143,
n7144, n7145, n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153,
n7154, n7155, n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163,
n7164, n7165, n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173,
n7174, n7175, n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183,
n7184, n7185, n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193,
n7194, n7195, n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203,
n7204, n7205, n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213,
n7214, n7215, n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223,
n7224, n7225, n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233,
n7234, n7235, n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243,
n7244, n7245, n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253,
n7254, n7255, n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263,
n7264, n7265, n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273,
n7274, n7275, n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283,
n7284, n7285, n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293,
n7294, n7295, n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303,
n7304, n7305, n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313,
n7314, n7315, n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323,
n7324, n7325, n7326, n7327, n7328, n7329, n7330, n7331, n7332, n7333,
n7334, n7335, n7336, n7337, n7338, n7339, n7340, n7341, n7342, n7343,
n7344, n7345, n7346, n7347, n7348, n7349, n7350, n7351, n7352, n7353,
n7354, n7355, n7356, n7357, n7358, n7359, n7360, n7361, n7362, n7363,
n7364, n7365, n7366, n7367, n7368, n7369, n7370, n7371, n7372, n7373,
n7374, n7375, n7376, n7377, n7378, n7379, n7380, n7381, n7382, n7383,
n7384, n7385, n7386, n7387, n7388, n7389, n7390, n7391, n7392, n7393,
n7394, n7395, n7396, n7397, n7398, n7399, n7400, n7401, n7402, n7403,
n7404, n7405, n7406, n7407, n7408, n7409, n7410, n7411, n7412, n7413,
n7414, n7415, n7416, n7417, n7418, n7419, n7420, n7421, n7422, n7423,
n7424, n7425, n7426, n7427, n7428, n7429, n7430, n7431, n7432, n7433,
n7434, n7435, n7436, n7437, n7438, n7439, n7440, n7441, n7442, n7443,
n7444, n7445, n7446, n7447, n7448, n7449, n7450, n7451, n7452, n7453,
n7454, n7455, n7456, n7457, n7458, n7459, n7460, n7461, n7462, n7463,
n7464, n7465, n7466, n7467, n7468, n7469, n7470, n7471, n7472, n7473,
n7474, n7475, n7476, n7477, n7478, n7479, n7480, n7481, n7482, n7483,
n7484, n7485, n7486, n7487, n7488, n7489, n7490, n7491, n7492, n7493,
n7494, n7495, n7496, n7497, n7498, n7499, n7500, n7501, n7502, n7503,
n7504, n7505, n7506, n7507, n7508, n7509, n7510, n7511, n7512, n7513,
n7514, n7515, n7516, n7517, n7518, n7519, n7520, n7521, n7522, n7523,
n7524, n7525, n7526, n7527, n7528, n7529, n7530, n7531, n7532, n7533,
n7534, n7535, n7536, n7537, n7538, n7539, n7540, n7541, n7542, n7543,
n7544, n7545, n7546, n7547, n7548, n7549, n7550, n7551, n7552, n7553,
n7554, n7555, n7556, n7557, n7558, n7559, n7560, n7561, n7562, n7563,
n7564, n7565, n7566, n7567, n7568, n7569, n7570, n7571, n7572, n7573,
n7574, n7575, n7576, n7577, n7578, n7579, n7580, n7581, n7582, n7583,
n7584, n7585, n7586, n7587, n7588, n7589, n7590, n7591, n7592, n7593,
n7594, n7595, n7596, n7597, n7598, n7599, n7600, n7601, n7602, n7603,
n7604, n7605, n7606, n7607, n7608, n7609, n7610, n7611, n7612, n7613,
n7614, n7615, n7616, n7617, n7618, n7619, n7620, n7621, n7622, n7623,
n7624, n7625, n7626, n7627, n7628, n7629, n7630, n7631, n7632, n7633,
n7634, n7635, n7636, n7637, n7638, n7639, n7640, n7641, n7642, n7643,
n7644, n7645, n7646, n7647, n7648, n7649, n7650, n7651, n7652, n7653,
n7654, n7655, n7656, n7657, n7658, n7659, n7660, n7661, n7662, n7663,
n7664, n7665, n7666, n7667, n7668, n7669, n7670, n7671, n7672, n7673,
n7674, n7675, n7676, n7677, n7678, n7679, n7680, n7681, n7682, n7683,
n7684, n7685, n7686, n7687, n7688, n7689, n7690, n7691, n7692, n7693,
n7694, n7695, n7696, n7697, n7698, n7699, n7700, n7701, n7702, n7703,
n7704, n7705, n7706, n7707, n7708, n7709, n7710, n7711, n7712, n7713,
n7714, n7715, n7716, n7717, n7718, n7719, n7720, n7721, n7722, n7723,
n7724, n7725, n7726, n7727, n7728, n7729, n7730, n7731, n7732, n7733,
n7734, n7735, n7736, n7737, n7738, n7739, n7740, n7741, n7742, n7743,
n7744, n7745, n7746, n7747, n7748, n7749, n7750, n7751, n7752, n7753,
n7754, n7755, n7756, n7757, n7758, n7759, n7760, n7761, n7762, n7763,
n7764, n7765, n7766, n7767, n7768, n7769, n7770, n7771, n7772, n7773,
n7774, n7775, n7776, n7777, n7778, n7779, n7780, n7781, n7782, n7783,
n7784, n7785, n7786, n7787, n7788, n7789, n7790, n7791, n7792, n7793,
n7794, n7796;
DFFQX1TS Data_S_o_reg_37_ ( .D(N37), .CK(clk), .Q(Data_S_o[37]) );
DFFQX1TS Data_S_o_reg_36_ ( .D(N36), .CK(clk), .Q(Data_S_o[36]) );
DFFQX1TS Data_S_o_reg_34_ ( .D(N34), .CK(clk), .Q(Data_S_o[34]) );
DFFQX1TS Data_S_o_reg_33_ ( .D(N33), .CK(clk), .Q(Data_S_o[33]) );
DFFQX1TS Data_S_o_reg_32_ ( .D(N32), .CK(clk), .Q(Data_S_o[32]) );
DFFQX1TS Data_S_o_reg_31_ ( .D(N31), .CK(clk), .Q(Data_S_o[31]) );
DFFQX1TS Data_S_o_reg_30_ ( .D(N30), .CK(clk), .Q(Data_S_o[30]) );
DFFQX1TS Data_S_o_reg_29_ ( .D(N29), .CK(clk), .Q(Data_S_o[29]) );
DFFQX1TS Data_S_o_reg_28_ ( .D(N28), .CK(clk), .Q(Data_S_o[28]) );
DFFQX1TS Data_S_o_reg_27_ ( .D(N27), .CK(clk), .Q(Data_S_o[27]) );
DFFQX1TS Data_S_o_reg_26_ ( .D(N26), .CK(clk), .Q(Data_S_o[26]) );
DFFQX1TS Data_S_o_reg_25_ ( .D(N25), .CK(clk), .Q(Data_S_o[25]) );
DFFQX1TS Data_S_o_reg_24_ ( .D(N24), .CK(clk), .Q(Data_S_o[24]) );
DFFQX1TS Data_S_o_reg_23_ ( .D(N23), .CK(clk), .Q(Data_S_o[23]) );
DFFQX1TS Data_S_o_reg_22_ ( .D(N22), .CK(clk), .Q(Data_S_o[22]) );
DFFQX1TS Data_S_o_reg_21_ ( .D(N21), .CK(clk), .Q(Data_S_o[21]) );
DFFQX1TS Data_S_o_reg_20_ ( .D(N20), .CK(clk), .Q(Data_S_o[20]) );
DFFQX1TS Data_S_o_reg_19_ ( .D(N19), .CK(clk), .Q(Data_S_o[19]) );
DFFQX1TS Data_S_o_reg_18_ ( .D(N18), .CK(clk), .Q(Data_S_o[18]) );
DFFQX1TS Data_S_o_reg_17_ ( .D(N17), .CK(clk), .Q(Data_S_o[17]) );
DFFQX1TS Data_S_o_reg_16_ ( .D(N16), .CK(clk), .Q(Data_S_o[16]) );
DFFQX1TS Data_S_o_reg_15_ ( .D(N15), .CK(clk), .Q(Data_S_o[15]) );
DFFQX1TS Data_S_o_reg_14_ ( .D(N14), .CK(clk), .Q(Data_S_o[14]) );
DFFQX1TS Data_S_o_reg_13_ ( .D(N13), .CK(clk), .Q(Data_S_o[13]) );
DFFQX1TS Data_S_o_reg_12_ ( .D(N12), .CK(clk), .Q(Data_S_o[12]) );
DFFQX1TS Data_S_o_reg_11_ ( .D(N11), .CK(clk), .Q(Data_S_o[11]) );
DFFQX1TS Data_S_o_reg_10_ ( .D(N10), .CK(clk), .Q(Data_S_o[10]) );
DFFQX1TS Data_S_o_reg_9_ ( .D(N9), .CK(clk), .Q(Data_S_o[9]) );
DFFQX1TS Data_S_o_reg_8_ ( .D(N8), .CK(clk), .Q(Data_S_o[8]) );
DFFQX1TS Data_S_o_reg_7_ ( .D(N7), .CK(clk), .Q(Data_S_o[7]) );
DFFQX1TS Data_S_o_reg_6_ ( .D(N6), .CK(clk), .Q(Data_S_o[6]) );
DFFQX1TS Data_S_o_reg_5_ ( .D(N5), .CK(clk), .Q(Data_S_o[5]) );
DFFQX1TS Data_S_o_reg_4_ ( .D(N4), .CK(clk), .Q(Data_S_o[4]) );
DFFQX1TS Data_S_o_reg_3_ ( .D(N3), .CK(clk), .Q(Data_S_o[3]) );
DFFQX1TS Data_S_o_reg_2_ ( .D(N2), .CK(clk), .Q(Data_S_o[2]) );
DFFQX1TS Data_S_o_reg_35_ ( .D(N35), .CK(clk), .Q(Data_S_o[35]) );
DFFQX1TS Data_S_o_reg_107_ ( .D(N107), .CK(clk), .Q(Data_S_o[107]) );
DFFQX1TS Data_S_o_reg_106_ ( .D(N106), .CK(clk), .Q(Data_S_o[106]) );
DFFQX1TS Data_S_o_reg_98_ ( .D(N98), .CK(clk), .Q(Data_S_o[98]) );
DFFQX1TS Data_S_o_reg_97_ ( .D(N97), .CK(clk), .Q(Data_S_o[97]) );
DFFQX1TS Data_S_o_reg_96_ ( .D(N96), .CK(clk), .Q(Data_S_o[96]) );
DFFQX1TS Data_S_o_reg_94_ ( .D(N94), .CK(clk), .Q(Data_S_o[94]) );
DFFQX1TS Data_S_o_reg_93_ ( .D(N93), .CK(clk), .Q(Data_S_o[93]) );
DFFQX1TS Data_S_o_reg_92_ ( .D(N92), .CK(clk), .Q(Data_S_o[92]) );
DFFQX1TS Data_S_o_reg_91_ ( .D(N91), .CK(clk), .Q(Data_S_o[91]) );
DFFQX1TS Data_S_o_reg_90_ ( .D(N90), .CK(clk), .Q(Data_S_o[90]) );
DFFQX1TS Data_S_o_reg_89_ ( .D(N89), .CK(clk), .Q(Data_S_o[89]) );
DFFQX1TS Data_S_o_reg_81_ ( .D(N81), .CK(clk), .Q(Data_S_o[81]) );
DFFQX1TS Data_S_o_reg_80_ ( .D(N80), .CK(clk), .Q(Data_S_o[80]) );
DFFQX1TS Data_S_o_reg_79_ ( .D(N79), .CK(clk), .Q(Data_S_o[79]) );
DFFQX1TS Data_S_o_reg_78_ ( .D(N78), .CK(clk), .Q(Data_S_o[78]) );
DFFQX1TS Data_S_o_reg_77_ ( .D(N77), .CK(clk), .Q(Data_S_o[77]) );
DFFQX1TS Data_S_o_reg_76_ ( .D(N76), .CK(clk), .Q(Data_S_o[76]) );
DFFQX1TS Data_S_o_reg_74_ ( .D(N74), .CK(clk), .Q(Data_S_o[74]) );
DFFQX1TS Data_S_o_reg_73_ ( .D(N73), .CK(clk), .Q(Data_S_o[73]) );
DFFQX1TS Data_S_o_reg_71_ ( .D(N71), .CK(clk), .Q(Data_S_o[71]) );
DFFQX1TS Data_S_o_reg_70_ ( .D(N70), .CK(clk), .Q(Data_S_o[70]) );
DFFQX1TS Data_S_o_reg_69_ ( .D(N69), .CK(clk), .Q(Data_S_o[69]) );
DFFQX1TS Data_S_o_reg_68_ ( .D(N68), .CK(clk), .Q(Data_S_o[68]) );
DFFQX1TS Data_S_o_reg_67_ ( .D(N67), .CK(clk), .Q(Data_S_o[67]) );
DFFQX1TS Data_S_o_reg_66_ ( .D(N66), .CK(clk), .Q(Data_S_o[66]) );
DFFQX1TS Data_S_o_reg_65_ ( .D(N65), .CK(clk), .Q(Data_S_o[65]) );
DFFQX1TS Data_S_o_reg_64_ ( .D(N64), .CK(clk), .Q(Data_S_o[64]) );
DFFQX1TS Data_S_o_reg_63_ ( .D(N63), .CK(clk), .Q(Data_S_o[63]) );
DFFQX1TS Data_S_o_reg_62_ ( .D(N62), .CK(clk), .Q(Data_S_o[62]) );
DFFQX1TS Data_S_o_reg_61_ ( .D(N61), .CK(clk), .Q(Data_S_o[61]) );
DFFQX1TS Data_S_o_reg_60_ ( .D(N60), .CK(clk), .Q(Data_S_o[60]) );
DFFQX1TS Data_S_o_reg_59_ ( .D(N59), .CK(clk), .Q(Data_S_o[59]) );
DFFQX1TS Data_S_o_reg_58_ ( .D(N58), .CK(clk), .Q(Data_S_o[58]) );
DFFQX1TS Data_S_o_reg_57_ ( .D(N57), .CK(clk), .Q(Data_S_o[57]) );
DFFQX1TS Data_S_o_reg_56_ ( .D(N56), .CK(clk), .Q(Data_S_o[56]) );
DFFQX1TS Data_S_o_reg_55_ ( .D(N55), .CK(clk), .Q(Data_S_o[55]) );
DFFQX1TS Data_S_o_reg_54_ ( .D(N54), .CK(clk), .Q(Data_S_o[54]) );
DFFQX1TS Data_S_o_reg_53_ ( .D(N53), .CK(clk), .Q(Data_S_o[53]) );
DFFQX1TS Data_S_o_reg_52_ ( .D(N52), .CK(clk), .Q(Data_S_o[52]) );
DFFQX1TS Data_S_o_reg_51_ ( .D(N51), .CK(clk), .Q(Data_S_o[51]) );
DFFQX1TS Data_S_o_reg_50_ ( .D(N50), .CK(clk), .Q(Data_S_o[50]) );
DFFQX1TS Data_S_o_reg_49_ ( .D(N49), .CK(clk), .Q(Data_S_o[49]) );
DFFQX1TS Data_S_o_reg_48_ ( .D(N48), .CK(clk), .Q(Data_S_o[48]) );
DFFQX1TS Data_S_o_reg_47_ ( .D(N47), .CK(clk), .Q(Data_S_o[47]) );
DFFQX1TS Data_S_o_reg_46_ ( .D(N46), .CK(clk), .Q(Data_S_o[46]) );
DFFQX1TS Data_S_o_reg_45_ ( .D(N45), .CK(clk), .Q(Data_S_o[45]) );
DFFQX1TS Data_S_o_reg_44_ ( .D(N44), .CK(clk), .Q(Data_S_o[44]) );
DFFQX1TS Data_S_o_reg_43_ ( .D(N43), .CK(clk), .Q(Data_S_o[43]) );
DFFQX1TS Data_S_o_reg_42_ ( .D(N42), .CK(clk), .Q(Data_S_o[42]) );
DFFQX1TS Data_S_o_reg_41_ ( .D(N41), .CK(clk), .Q(Data_S_o[41]) );
DFFQX1TS Data_S_o_reg_40_ ( .D(N40), .CK(clk), .Q(Data_S_o[40]) );
DFFQX1TS Data_S_o_reg_39_ ( .D(N39), .CK(clk), .Q(Data_S_o[39]) );
DFFQX1TS Data_S_o_reg_82_ ( .D(N82), .CK(clk), .Q(Data_S_o[82]) );
DFFQX1TS Data_S_o_reg_83_ ( .D(N83), .CK(clk), .Q(Data_S_o[83]) );
DFFTRX1TS Data_S_o_reg_0_ ( .D(n3272), .RN(Data_A_i[0]), .CK(clk), .Q(
Data_S_o[0]) );
DFFTRX1TS Data_S_o_reg_1_ ( .D(n7796), .RN(mult_x_1_n1532), .CK(clk), .Q(
Data_S_o[1]) );
DFFHQX4TS Data_S_o_reg_104_ ( .D(N104), .CK(clk), .Q(Data_S_o[104]) );
DFFHQX4TS Data_S_o_reg_103_ ( .D(N103), .CK(clk), .Q(Data_S_o[103]) );
DFFHQX4TS Data_S_o_reg_99_ ( .D(N99), .CK(clk), .Q(Data_S_o[99]) );
DFFHQX4TS Data_S_o_reg_88_ ( .D(N88), .CK(clk), .Q(Data_S_o[88]) );
DFFHQX4TS Data_S_o_reg_84_ ( .D(N84), .CK(clk), .Q(Data_S_o[84]) );
DFFHQX4TS Data_S_o_reg_105_ ( .D(N105), .CK(clk), .Q(Data_S_o[105]) );
DFFHQX4TS Data_S_o_reg_102_ ( .D(N102), .CK(clk), .Q(Data_S_o[102]) );
DFFHQX4TS Data_S_o_reg_101_ ( .D(N101), .CK(clk), .Q(Data_S_o[101]) );
DFFHQX4TS Data_S_o_reg_95_ ( .D(N95), .CK(clk), .Q(Data_S_o[95]) );
DFFHQX4TS Data_S_o_reg_87_ ( .D(N87), .CK(clk), .Q(Data_S_o[87]) );
DFFHQX4TS Data_S_o_reg_86_ ( .D(N86), .CK(clk), .Q(Data_S_o[86]) );
DFFHQX4TS Data_S_o_reg_72_ ( .D(N72), .CK(clk), .Q(Data_S_o[72]) );
DFFHQX4TS Data_S_o_reg_75_ ( .D(N75), .CK(clk), .Q(Data_S_o[75]) );
DFFRHQX1TS Data_S_o_reg_38_ ( .D(N38), .CK(clk), .RN(1'b1), .Q(Data_S_o[38])
);
DFFHQX4TS Data_S_o_reg_85_ ( .D(N85), .CK(clk), .Q(Data_S_o[85]) );
DFFHQX4TS Data_S_o_reg_100_ ( .D(N100), .CK(clk), .Q(Data_S_o[100]) );
NAND2X1TS U3 ( .A(n7084), .B(n7083), .Y(n7160) );
INVX2TS U4 ( .A(n7585), .Y(n7559) );
NAND2X1TS U5 ( .A(n7164), .B(n7166), .Y(n7482) );
NOR2X1TS U6 ( .A(n7292), .B(n7105), .Y(n7405) );
INVX2TS U7 ( .A(n7294), .Y(n7153) );
BUFX3TS U8 ( .A(n7491), .Y(n7585) );
NAND2X1TS U9 ( .A(n7308), .B(n7003), .Y(n7475) );
NAND2X2TS U10 ( .A(n7055), .B(n6859), .Y(n6861) );
NOR2X6TS U11 ( .A(n7029), .B(n6793), .Y(n6795) );
NAND2X2TS U12 ( .A(n3338), .B(n7378), .Y(n3340) );
NOR2X2TS U13 ( .A(n7348), .B(n6782), .Y(n7392) );
NOR2X1TS U14 ( .A(n6775), .B(n6774), .Y(n7348) );
NOR2X2TS U15 ( .A(n7389), .B(n7610), .Y(n7616) );
OAI21X1TS U16 ( .A0(n6911), .A1(n6855), .B0(n6854), .Y(n6856) );
NOR2X2TS U17 ( .A(n2445), .B(n7674), .Y(n7640) );
AOI21X2TS U18 ( .A0(n7001), .A1(n7000), .B0(n6999), .Y(n7071) );
NAND2X1TS U19 ( .A(n2453), .B(n2452), .Y(n7647) );
NAND2X1TS U20 ( .A(n3323), .B(n3322), .Y(n7319) );
NAND2X1TS U21 ( .A(n6809), .B(n6808), .Y(n7111) );
NOR2X1TS U22 ( .A(n3320), .B(n3321), .Y(n7632) );
NAND2X1TS U23 ( .A(n5044), .B(n5043), .Y(n7546) );
NAND2X2TS U24 ( .A(n6799), .B(n6798), .Y(n7299) );
NAND2X2TS U25 ( .A(n3325), .B(n3324), .Y(n7354) );
NAND2XLTS U26 ( .A(n7480), .B(n7067), .Y(n7070) );
NAND2X2TS U27 ( .A(n7657), .B(n7637), .Y(n7643) );
NOR2X2TS U28 ( .A(n7303), .B(n7110), .Y(n7407) );
NAND2X1TS U29 ( .A(n6871), .B(n6870), .Y(n6905) );
INVX2TS U30 ( .A(n5407), .Y(n6786) );
NAND2X1TS U31 ( .A(n7006), .B(n7005), .Y(n7479) );
OAI2BB1X2TS U32 ( .A0N(n3924), .A1N(n3923), .B0(n3922), .Y(n5043) );
OR2X2TS U33 ( .A(n2434), .B(n2432), .Y(n7669) );
NOR2X6TS U34 ( .A(n6799), .B(n6798), .Y(n7298) );
OR2X2TS U35 ( .A(n6896), .B(n6895), .Y(n7000) );
NOR2X2TS U36 ( .A(n7194), .B(n7190), .Y(n1802) );
ADDFHX2TS U37 ( .A(n4938), .B(n4937), .CI(n4936), .CO(n5019), .S(n5017) );
CMPR32X2TS U38 ( .A(n5066), .B(n5065), .C(n5064), .CO(n5157), .S(n5154) );
NAND2X1TS U39 ( .A(n6843), .B(n6842), .Y(n6922) );
NAND2X1TS U40 ( .A(n6825), .B(n6824), .Y(n7443) );
NAND2X1TS U41 ( .A(n6833), .B(n6832), .Y(n6942) );
NAND2X1TS U42 ( .A(n6837), .B(n6836), .Y(n6961) );
OAI2BB1X2TS U43 ( .A0N(n3831), .A1N(n3830), .B0(n3829), .Y(n4551) );
NAND2X1TS U44 ( .A(n1800), .B(n1799), .Y(n7195) );
NOR2X1TS U45 ( .A(n6871), .B(n6870), .Y(n6904) );
NOR2X4TS U46 ( .A(n1337), .B(n1336), .Y(n7693) );
OAI2BB1X2TS U47 ( .A0N(n4976), .A1N(n4975), .B0(n4974), .Y(n4977) );
NAND2X2TS U48 ( .A(n2447), .B(n2446), .Y(n7652) );
XOR2X1TS U49 ( .A(n4172), .B(n4171), .Y(n5009) );
NAND2X1TS U50 ( .A(n2), .B(n7714), .Y(n7698) );
OAI2BB1X1TS U51 ( .A0N(n3921), .A1N(n3920), .B0(n3919), .Y(n3922) );
ADDFHX1TS U52 ( .A(n4440), .B(n4439), .CI(n4438), .CO(n4455), .S(n4554) );
NAND2X1TS U53 ( .A(n6869), .B(n7310), .Y(n6900) );
XOR2X2TS U54 ( .A(n4979), .B(n4978), .Y(n4973) );
ADDFHX2TS U55 ( .A(n5855), .B(n5854), .CI(n5853), .CO(n6800), .S(n6799) );
NAND2X2TS U56 ( .A(n19), .B(n7720), .Y(n7221) );
OAI2BB1X2TS U57 ( .A0N(n4169), .A1N(n4171), .B0(n3824), .Y(n4179) );
NAND2X1TS U58 ( .A(n6865), .B(n6864), .Y(n7471) );
NOR2X1TS U59 ( .A(n6851), .B(n6850), .Y(n7287) );
OAI2BB1X2TS U60 ( .A0N(n6), .A1N(n5), .B0(n4884), .Y(n4844) );
NOR2X2TS U61 ( .A(n6841), .B(n6840), .Y(n6965) );
XNOR2X1TS U62 ( .A(n5000), .B(n4999), .Y(n5002) );
ADDFHX2TS U63 ( .A(n4155), .B(n4154), .CI(n4153), .CO(n4175), .S(n4997) );
ADDFHX2TS U64 ( .A(n6085), .B(n6084), .CI(n6083), .CO(n6096), .S(n6165) );
ADDFHX2TS U65 ( .A(n2223), .B(n2222), .CI(n2221), .CO(n2449), .S(n2446) );
ADDFHX2TS U66 ( .A(n1261), .B(n1260), .CI(n1259), .CO(n1336), .S(n1335) );
OAI21X1TS U67 ( .A0(n7735), .A1(n7732), .B0(n7736), .Y(n7740) );
CMPR32X2TS U68 ( .A(n2603), .B(n2602), .C(n2601), .CO(n2735), .S(n2730) );
CMPR32X2TS U69 ( .A(n2618), .B(n2617), .C(n2616), .CO(n2683), .S(n2733) );
CMPR32X2TS U70 ( .A(n4344), .B(n4343), .C(n4342), .CO(n4545), .S(n4452) );
NAND2X1TS U71 ( .A(n1330), .B(n1329), .Y(n7716) );
NAND2X1TS U72 ( .A(n984), .B(n983), .Y(n7732) );
NOR2X1TS U73 ( .A(n996), .B(n995), .Y(n7226) );
NOR2X1TS U74 ( .A(n6867), .B(n6866), .Y(n6974) );
NOR2X2TS U75 ( .A(n988), .B(n987), .Y(n7743) );
XOR2X2TS U76 ( .A(n5458), .B(n5461), .Y(n5397) );
ADDFHX1TS U77 ( .A(n5921), .B(n5920), .CI(n5919), .CO(n6155), .S(n5924) );
ADDFHX1TS U78 ( .A(n6088), .B(n6087), .CI(n6086), .CO(n6160), .S(n6156) );
ADDFHX2TS U79 ( .A(n5852), .B(n5851), .CI(n5850), .CO(n5895), .S(n5855) );
ADDFHX2TS U80 ( .A(n3289), .B(n3288), .CI(n3287), .CO(n4913), .S(n3282) );
CMPR32X2TS U81 ( .A(n3286), .B(n3285), .C(n3284), .CO(n4914), .S(n3278) );
CMPR32X2TS U82 ( .A(n3166), .B(n3165), .C(n3164), .CO(n3121), .S(n3180) );
CMPR32X2TS U83 ( .A(n5824), .B(n5823), .C(n5822), .CO(n5919), .S(n5850) );
CMPR32X2TS U84 ( .A(n5515), .B(n5514), .C(n5513), .CO(n5634), .S(n5510) );
CMPR32X2TS U85 ( .A(n4414), .B(n4413), .C(n4412), .CO(n4461), .S(n4355) );
CMPR32X2TS U86 ( .A(n5975), .B(n5974), .C(n5973), .CO(n6091), .S(n6087) );
CMPR32X2TS U87 ( .A(n5918), .B(n5917), .C(n5916), .CO(n6086), .S(n5921) );
CMPR32X2TS U88 ( .A(n4329), .B(n4328), .C(n4327), .CO(n4410), .S(n4298) );
NOR2X1TS U89 ( .A(n6847), .B(n6846), .Y(n6629) );
ADDFHX1TS U90 ( .A(n2226), .B(n2225), .CI(n2224), .CO(n2218), .S(n2409) );
ADDFHX1TS U91 ( .A(n2686), .B(n2685), .CI(n2684), .CO(n2762), .S(n2681) );
ADDFHX1TS U92 ( .A(n2680), .B(n2679), .CI(n2678), .CO(n2721), .S(n2738) );
ADDFHX1TS U93 ( .A(n2615), .B(n2614), .CI(n2613), .CO(n2616), .S(n2665) );
ADDFHX1TS U94 ( .A(n5777), .B(n5776), .CI(n5775), .CO(n5828), .S(n5766) );
ADDFHX1TS U95 ( .A(n6082), .B(n6081), .CI(n6080), .CO(n6017), .S(n6152) );
ADDFHX2TS U96 ( .A(n2811), .B(n2810), .CI(n2809), .CO(n3118), .S(n2761) );
CMPR32X2TS U97 ( .A(n4239), .B(n4238), .C(n4237), .CO(n4437), .S(n4295) );
CMPR32X2TS U98 ( .A(n5096), .B(n5095), .C(n5094), .CO(n5169), .S(n5091) );
CMPR32X2TS U99 ( .A(n3820), .B(n3819), .C(n3818), .CO(n3822), .S(n4165) );
CMPR32X2TS U100 ( .A(n3148), .B(n3147), .C(n3146), .CO(n3093), .S(n3158) );
CMPR32X2TS U101 ( .A(n1774), .B(n1773), .C(n1772), .CO(n2402), .S(n1775) );
CMPR32X2TS U102 ( .A(n3097), .B(n3096), .C(n3095), .CO(n3115), .S(n3168) );
CMPR32X2TS U103 ( .A(n6175), .B(n6174), .C(n6173), .CO(n6225), .S(n6220) );
CMPR32X2TS U104 ( .A(n5671), .B(n5670), .C(n5669), .CO(n5776), .S(n5677) );
CMPR32X2TS U105 ( .A(n2711), .B(n2710), .C(n2709), .CO(n2720), .S(n2661) );
CMPR32X2TS U106 ( .A(n5560), .B(n5559), .C(n5558), .CO(n5567), .S(n5507) );
CMPR32X2TS U107 ( .A(n5807), .B(n5806), .C(n5805), .CO(n5870), .S(n5822) );
CMPR32X2TS U108 ( .A(n6335), .B(n6334), .C(n6333), .CO(n6452), .S(n6331) );
CMPR32X2TS U109 ( .A(n1192), .B(n1191), .C(n1190), .CO(n1604), .S(n1219) );
CMPR32X2TS U110 ( .A(n4220), .B(n4219), .C(n4218), .CO(n4266), .S(n4235) );
CMPR32X2TS U111 ( .A(n3103), .B(n3102), .C(n3101), .CO(n3139), .S(n3135) );
CMPR32X2TS U112 ( .A(n5972), .B(n5971), .C(n5970), .CO(n6080), .S(n6077) );
NAND2X1TS U113 ( .A(n903), .B(n902), .Y(n7749) );
NAND2X1TS U114 ( .A(n911), .B(n910), .Y(n7239) );
NAND2X1TS U115 ( .A(n909), .B(n908), .Y(n7244) );
NAND2X1TS U116 ( .A(n905), .B(n904), .Y(n7249) );
NOR2X1TS U117 ( .A(n905), .B(n904), .Y(n631) );
ADDFX1TS U118 ( .A(n6425), .B(n6424), .CI(n6423), .CO(n6453), .S(n6450) );
CMPR32X2TS U119 ( .A(n6449), .B(n6448), .C(n6447), .CO(n6474), .S(n6503) );
ADDFHX1TS U120 ( .A(n2024), .B(n2023), .CI(n2022), .CO(n2361), .S(n2125) );
ADDFHX1TS U121 ( .A(n2214), .B(n2213), .CI(n2212), .CO(n2215), .S(n2365) );
ADDFHX1TS U122 ( .A(n2795), .B(n2794), .CI(n2793), .CO(n3163), .S(n2809) );
ADDFHX1TS U123 ( .A(n1300), .B(n1299), .CI(n1298), .CO(n1286), .S(n1324) );
ADDFHX1TS U124 ( .A(n2644), .B(n2643), .CI(n2642), .CO(n2686), .S(n2605) );
ADDFHX1TS U125 ( .A(n2333), .B(n2332), .CI(n2331), .CO(n2675), .S(n2289) );
ADDFHX1TS U126 ( .A(n6276), .B(n6275), .CI(n6274), .CO(n6293), .S(n6253) );
ADDFHX1TS U127 ( .A(n1237), .B(n1236), .CI(n1235), .CO(n1217), .S(n1287) );
ADDFHX1TS U128 ( .A(n2659), .B(n2658), .CI(n2657), .CO(n2834), .S(n2684) );
CMPR32X2TS U129 ( .A(n3133), .B(n3132), .C(n3131), .CO(n3287), .S(n3016) );
ADDFHX1TS U130 ( .A(n5441), .B(n5440), .CI(n5439), .CO(n5515), .S(n5409) );
ADDFX1TS U131 ( .A(n3127), .B(n3126), .CI(n3125), .CO(n3289), .S(n3122) );
ADDFHX1TS U132 ( .A(n5792), .B(n5791), .CI(n5790), .CO(n5916), .S(n5847) );
ADDFHX2TS U133 ( .A(n2382), .B(n2381), .CI(n2380), .CO(n2418), .S(n2403) );
ADDFHX1TS U134 ( .A(n5874), .B(n5873), .CI(n5872), .CO(n6079), .S(n5871) );
ADDFHX1TS U135 ( .A(n5833), .B(n5832), .CI(n5831), .CO(n5900), .S(n5823) );
ADDFHX1TS U136 ( .A(n6409), .B(n6408), .CI(n6407), .CO(n6455), .S(n6451) );
ADDFHX2TS U137 ( .A(n4847), .B(n4846), .CI(n4845), .CO(n4972), .S(n4881) );
ADDFHX2TS U138 ( .A(n2714), .B(n2713), .CI(n2712), .CO(n2810), .S(n2719) );
ADDFHX1TS U139 ( .A(n6632), .B(n6631), .CI(n6630), .CO(n6851), .S(n6847) );
CMPR32X2TS U140 ( .A(n2169), .B(n2168), .C(n2167), .CO(n2211), .S(n2236) );
CMPR32X2TS U141 ( .A(n1749), .B(n1748), .C(n1747), .CO(n1770), .S(n1766) );
CMPR32X2TS U142 ( .A(n2145), .B(n2144), .C(n2143), .CO(n2147), .S(n2206) );
CMPR32X2TS U143 ( .A(n3611), .B(n3610), .C(n3609), .CO(n3860), .S(n3444) );
CMPR32X2TS U144 ( .A(n3567), .B(n3566), .C(n3565), .CO(n3604), .S(n3648) );
CMPR32X2TS U145 ( .A(n6609), .B(n6608), .C(n6607), .CO(n6631), .S(n6627) );
CMPR32X2TS U146 ( .A(n6270), .B(n6269), .C(n6268), .CO(n6296), .S(n6275) );
CMPR32X2TS U147 ( .A(n1189), .B(n1188), .C(n1187), .CO(n1190), .S(n1195) );
CMPR32X2TS U148 ( .A(n408), .B(n407), .C(n406), .CO(n429), .S(n466) );
CMPR32X2TS U149 ( .A(n2913), .B(n2912), .C(n2911), .CO(n2953), .S(n3104) );
CMPR32X2TS U150 ( .A(n2979), .B(n2978), .C(n2977), .CO(n3127), .S(n2951) );
CMPR32X2TS U151 ( .A(n1545), .B(n1544), .C(n1543), .CO(n1709), .S(n1524) );
CMPR32X2TS U152 ( .A(n2885), .B(n2884), .C(n2883), .CO(n2948), .S(n3083) );
CMPR32X2TS U153 ( .A(n6360), .B(n6359), .C(n6358), .CO(n6424), .S(n6327) );
CMPR32X2TS U154 ( .A(n2695), .B(n2694), .C(n2693), .CO(n2713), .S(n2709) );
CMPR32X2TS U155 ( .A(n6116), .B(n6115), .C(n6114), .CO(n6202), .S(n6131) );
CMPR32X2TS U156 ( .A(n2524), .B(n2523), .C(n2522), .CO(n2747), .S(n2658) );
CMPR32X2TS U157 ( .A(n2591), .B(n2590), .C(n2589), .CO(n2643), .S(n2610) );
CMPR32X2TS U158 ( .A(n2624), .B(n2623), .C(n2622), .CO(n2711), .S(n2607) );
CMPR32X2TS U159 ( .A(n2750), .B(n2749), .C(n2748), .CO(n3097), .S(n2745) );
CMPR32X2TS U160 ( .A(n5906), .B(n5905), .C(n5904), .CO(n5975), .S(n5876) );
CMPR32X2TS U161 ( .A(n4214), .B(n4213), .C(n4212), .CO(n4241), .S(n4191) );
CMPR32X2TS U162 ( .A(n4503), .B(n4502), .C(n4501), .CO(n5077), .S(n4522) );
CMPR32X2TS U163 ( .A(n5413), .B(n5412), .C(n5411), .CO(n5557), .S(n5440) );
CMPR32X2TS U164 ( .A(n5868), .B(n5867), .C(n5866), .CO(n5964), .S(n5873) );
CMPR32X2TS U165 ( .A(n5612), .B(n5611), .C(n5610), .CO(n5669), .S(n5613) );
CMPR32X2TS U166 ( .A(n4405), .B(n4404), .C(n4403), .CO(n4521), .S(n4412) );
CMPR32X2TS U167 ( .A(n5663), .B(n5662), .C(n5661), .CO(n5712), .S(n5671) );
CMPR32X2TS U168 ( .A(n4306), .B(n4305), .C(n4304), .CO(n4414), .S(n4301) );
CMPR32X2TS U169 ( .A(n2594), .B(n2593), .C(n2592), .CO(n2642), .S(n2584) );
ADDFX1TS U170 ( .A(n6206), .B(n6205), .CI(n6204), .CO(n6276), .S(n6201) );
CMPR32X2TS U171 ( .A(n6151), .B(n6150), .C(n6149), .CO(n6173), .S(n6099) );
CMPR32X2TS U172 ( .A(n5503), .B(n5502), .C(n5501), .CO(n5587), .S(n5505) );
ADDFHX1TS U173 ( .A(n3869), .B(n3868), .CI(n3867), .CO(n4270), .S(n3858) );
ADDFHX1TS U174 ( .A(n970), .B(n969), .CI(n968), .CO(n962), .S(n979) );
ADDFHX1TS U175 ( .A(n3443), .B(n3442), .CI(n3441), .CO(n3445), .S(n3516) );
ADDFHX1TS U176 ( .A(n3893), .B(n3892), .CI(n3891), .CO(n4236), .S(n3862) );
ADDFHX1TS U177 ( .A(n952), .B(n951), .CI(n950), .CO(n944), .S(n967) );
ADDFHX1TS U178 ( .A(n2247), .B(n2246), .CI(n2245), .CO(n2388), .S(n2380) );
ADDFHX1TS U179 ( .A(n2262), .B(n2261), .CI(n2260), .CO(n2265), .S(n2377) );
ADDFX1TS U180 ( .A(n2084), .B(n2083), .CI(n2082), .CO(n2151), .S(n2209) );
ADDFHX1TS U181 ( .A(n3582), .B(n3581), .CI(n3580), .CO(n3915), .S(n3446) );
ADDFHX1TS U182 ( .A(n6219), .B(n6218), .CI(n6217), .CO(n6274), .S(n6174) );
ADDFHX1TS U183 ( .A(n2295), .B(n2294), .CI(n2293), .CO(n2614), .S(n2331) );
ADDFX1TS U184 ( .A(n4947), .B(n4946), .CI(n4945), .CO(n4989), .S(n4964) );
CMPR32X2TS U185 ( .A(n2250), .B(n2249), .C(n2248), .CO(n2240), .S(n2387) );
CMPR32X2TS U186 ( .A(n5423), .B(n5422), .C(n5421), .CO(n5508), .S(n5479) );
ADDFX1TS U187 ( .A(n6228), .B(n6227), .CI(n6226), .CO(n6323), .S(n6271) );
ADDFHX1TS U188 ( .A(n721), .B(n720), .CI(n719), .CO(n897), .S(n896) );
ADDFX1TS U189 ( .A(n2256), .B(n2255), .CI(n2254), .CO(n2379), .S(n2384) );
ADDFHX1TS U190 ( .A(n6267), .B(n6266), .CI(n6265), .CO(n6297), .S(n6272) );
ADDFHX2TS U191 ( .A(n1294), .B(n1293), .CI(n1292), .CO(n1311), .S(n1304) );
ADDFHX1TS U192 ( .A(n6461), .B(n6460), .CI(n6459), .CO(n6662), .S(n6493) );
ADDFHX1TS U193 ( .A(n6136), .B(n6135), .CI(n6134), .CO(n6175), .S(n6133) );
ADDFHX1TS U194 ( .A(n4476), .B(n4475), .CI(n4474), .CO(n5134), .S(n4466) );
ADDFHX1TS U195 ( .A(n2879), .B(n2878), .CI(n2877), .CO(n2950), .S(n3085) );
ADDFHX1TS U196 ( .A(n2959), .B(n2958), .CI(n2957), .CO(n3021), .S(n3090) );
ADDFHX2TS U197 ( .A(n2124), .B(n2123), .CI(n2122), .CO(n2150), .S(n2212) );
ADDFHX1TS U198 ( .A(n5743), .B(n5742), .CI(n5741), .CO(n5832), .S(n5736) );
ADDFX1TS U199 ( .A(n2990), .B(n2989), .CI(n2988), .CO(n2886), .S(n3145) );
ADDFX1TS U200 ( .A(n698), .B(n697), .CI(n696), .CO(n895), .S(n894) );
CMPR32X2TS U201 ( .A(n3002), .B(n3001), .C(n3000), .CO(n3129), .S(n3089) );
ADDFX1TS U202 ( .A(n4211), .B(n4210), .CI(n4209), .CO(n4242), .S(n4197) );
ADDFHX1TS U203 ( .A(n4512), .B(n4511), .CI(n4510), .CO(n5132), .S(n4463) );
ADDFX1TS U204 ( .A(n4528), .B(n4527), .CI(n4526), .CO(n5096), .S(n4507) );
CMPR32X2TS U205 ( .A(n2801), .B(n2800), .C(n2799), .CO(n2947), .S(n2746) );
ADDFHX1TS U206 ( .A(n3100), .B(n3099), .CI(n3098), .CO(n3136), .S(n2946) );
ADDFX1TS U207 ( .A(n4371), .B(n4370), .CI(n4369), .CO(n4464), .S(n4413) );
ADDFX1TS U208 ( .A(n2996), .B(n2995), .CI(n2994), .CO(n3143), .S(n3086) );
CMPR32X2TS U209 ( .A(n5696), .B(n5695), .C(n5694), .CO(n5737), .S(n5648) );
CMPR32X2TS U210 ( .A(n4223), .B(n4222), .C(n4221), .CO(n4303), .S(n4192) );
CMPR32X2TS U211 ( .A(n6739), .B(n6738), .C(n6737), .CO(n6772), .S(n6746) );
CMPR32X2TS U212 ( .A(n2698), .B(n2697), .C(n2696), .CO(n2712), .S(n2710) );
CMPR32X2TS U213 ( .A(n1454), .B(n1453), .C(n1452), .CO(n1575), .S(n1425) );
CMPR32X2TS U214 ( .A(n3467), .B(n3466), .C(n3465), .CO(n3492), .S(n3669) );
CMPR32X2TS U215 ( .A(n656), .B(n655), .C(n654), .CO(n633), .S(n716) );
CMPR32X2TS U216 ( .A(n303), .B(n302), .C(n301), .CO(n323), .S(n365) );
CMPR32X2TS U217 ( .A(n1448), .B(n1447), .C(n1446), .CO(n1593), .S(n1608) );
CMPR32X2TS U218 ( .A(n695), .B(n694), .C(n693), .CO(n720), .S(n696) );
CMPR32X2TS U219 ( .A(n934), .B(n933), .C(n932), .CO(n921), .S(n963) );
CMPR32X2TS U220 ( .A(n2178), .B(n2177), .C(n2176), .CO(n2249), .S(n2229) );
CMPR32X2TS U221 ( .A(n3530), .B(n3529), .C(n3528), .CO(n3598), .S(n3536) );
CMPR32X2TS U222 ( .A(n5969), .B(n5968), .C(n5967), .CO(n6071), .S(n6081) );
CMPR32X2TS U223 ( .A(n3596), .B(n3595), .C(n3594), .CO(n3849), .S(n3597) );
CMPR32X2TS U224 ( .A(n411), .B(n410), .C(n409), .CO(n406), .S(n922) );
CMPR32X2TS U225 ( .A(n2692), .B(n2691), .C(n2690), .CO(n2714), .S(n2672) );
CMPR32X2TS U226 ( .A(n3660), .B(n3659), .C(n3658), .CO(n3665), .S(n3776) );
CMPR32X2TS U227 ( .A(n1734), .B(n1733), .C(n1732), .CO(n2228), .S(n1760) );
CMPR32X2TS U228 ( .A(n2477), .B(n2476), .C(n2475), .CO(n2641), .S(n2608) );
CMPR32X2TS U229 ( .A(n2486), .B(n2485), .C(n2484), .CO(n2659), .S(n2639) );
CMPR32X2TS U230 ( .A(n4332), .B(n4331), .C(n4330), .CO(n4431), .S(n4240) );
CMPR32X2TS U231 ( .A(n2566), .B(n2565), .C(n2564), .CO(n2754), .S(n2532) );
CMPR32X2TS U232 ( .A(n3721), .B(n3720), .C(n3719), .CO(n3696), .S(n3811) );
CMPR32X2TS U233 ( .A(n1855), .B(n1854), .C(n1853), .CO(n1908), .S(n1919) );
CMPR32X2TS U234 ( .A(n1871), .B(n1870), .C(n1869), .CO(n1906), .S(n1830) );
CMPR32X2TS U235 ( .A(n4365), .B(n4364), .C(n4363), .CO(n4524), .S(n4430) );
CMPR32X2TS U236 ( .A(n2160), .B(n2159), .C(n2158), .CO(n2253), .S(n2256) );
CMPR32X2TS U237 ( .A(n2822), .B(n2821), .C(n2820), .CO(n3142), .S(n2797) );
CMPR32X2TS U238 ( .A(n4484), .B(n4483), .C(n4482), .CO(n5074), .S(n4508) );
CMPR32X2TS U239 ( .A(n3370), .B(n3369), .C(n3368), .CO(n3563), .S(n3442) );
CMPR32X2TS U240 ( .A(n2163), .B(n2162), .C(n2161), .CO(n2252), .S(n2246) );
CMPR32X2TS U241 ( .A(n5277), .B(n5276), .C(n5275), .CO(n5381), .S(n5270) );
CMPR32X2TS U242 ( .A(n6189), .B(n6188), .C(n6187), .CO(n6265), .S(n6205) );
CMPR32X2TS U243 ( .A(n3546), .B(n3545), .C(n3544), .CO(n3537), .S(n3642) );
CMPR32X2TS U244 ( .A(n1503), .B(n1502), .C(n1501), .CO(n1666), .S(n1559) );
CMPR32X2TS U245 ( .A(n3844), .B(n3843), .C(n3842), .CO(n4198), .S(n3851) );
CMPR32X2TS U246 ( .A(n1067), .B(n1066), .C(n1065), .CO(n1147), .S(n1144) );
CMPR32X2TS U247 ( .A(n2199), .B(n2198), .C(n2197), .CO(n2167), .S(n2234) );
CMPR32X2TS U248 ( .A(n3899), .B(n3898), .C(n3897), .CO(n4219), .S(n3868) );
CMPR32X2TS U249 ( .A(n1704), .B(n1703), .C(n1702), .CO(n2258), .S(n1744) );
CMPR32X2TS U250 ( .A(n5376), .B(n5375), .C(n5374), .CO(n5472), .S(n5328) );
CMPR32X2TS U251 ( .A(n4245), .B(n4244), .C(n4243), .CO(n4417), .S(n4262) );
CMPR32X2TS U252 ( .A(n3950), .B(n3949), .C(n3948), .CO(n3810), .S(n3951) );
CMPR32X2TS U253 ( .A(n2054), .B(n2053), .C(n2052), .CO(n2274), .S(n1905) );
CMPR32X2TS U254 ( .A(n3746), .B(n3745), .C(n3744), .CO(n3692), .S(n3965) );
CMPR32X2TS U255 ( .A(n3768), .B(n3767), .C(n3766), .CO(n3792), .S(n3940) );
CMPR32X2TS U256 ( .A(n3884), .B(n3883), .C(n3882), .CO(n4193), .S(n3892) );
CMPR32X2TS U257 ( .A(n6231), .B(n6230), .C(n6229), .CO(n6279), .S(n6269) );
CMPR32X2TS U258 ( .A(n6243), .B(n6242), .C(n6241), .CO(n6282), .S(n6268) );
CMPR32X2TS U259 ( .A(n3572), .B(n3573), .C(n3571), .CO(n3584), .S(n3565) );
CMPR32X2TS U260 ( .A(n3614), .B(n3613), .C(n3612), .CO(n3837), .S(n3562) );
CMPR32X2TS U261 ( .A(n6395), .B(n6394), .C(n6393), .CO(n6446), .S(n6442) );
ADDHXLTS U262 ( .A(n2792), .B(n2791), .CO(n2883), .S(n2756) );
CMPR32X2TS U263 ( .A(n1045), .B(n1044), .C(n1043), .CO(n1169), .S(n1215) );
CMPR32X2TS U264 ( .A(n1701), .B(n1700), .C(n1699), .CO(n2259), .S(n1751) );
CMPR32X2TS U265 ( .A(n6351), .B(n6350), .C(n6349), .CO(n6439), .S(n6357) );
CMPR32X2TS U266 ( .A(n5225), .B(n5224), .C(n5223), .CO(n5305), .S(n5207) );
CMPR32X2TS U267 ( .A(n3749), .B(n3748), .C(n3747), .CO(n3693), .S(n3964) );
CMPR32X2TS U268 ( .A(n6043), .B(n6042), .C(n6041), .CO(n6115), .S(n6073) );
CMPR32X2TS U269 ( .A(n6690), .B(n6689), .C(n6688), .CO(n6716), .S(n6697) );
CMPR32X2TS U270 ( .A(n3690), .B(n3689), .C(n3688), .CO(n3714), .S(n3791) );
CMPR32X2TS U271 ( .A(n5416), .B(n5415), .C(n5414), .CO(n5556), .S(n5423) );
CMPR32X2TS U272 ( .A(n3521), .B(n3520), .C(n3519), .CO(n3608), .S(n3462) );
ADDFX1TS U273 ( .A(n1673), .B(n1672), .CI(n1671), .CO(n2247), .S(n1764) );
ADDFX1TS U274 ( .A(n6006), .B(n6005), .CI(n6004), .CO(n6051), .S(n5991) );
CMPR32X2TS U275 ( .A(n1084), .B(n1083), .C(n1082), .CO(n1079), .S(n1255) );
CMPR32X2TS U276 ( .A(n1834), .B(n1833), .C(n1832), .CO(n1909), .S(n1829) );
ADDFX1TS U277 ( .A(n3434), .B(n3433), .CI(n3432), .CO(n3443), .S(n3647) );
CMPR32X2TS U278 ( .A(n6579), .B(n6578), .C(n6577), .CO(n6608), .S(n6596) );
OAI22X1TS U279 ( .A0(n4599), .A1(n2802), .B0(n3026), .B1(n2916), .Y(n3100)
);
ADDFHX1TS U280 ( .A(n3663), .B(n3662), .CI(n3661), .CO(n3664), .S(n3775) );
ADDFHX1TS U281 ( .A(n630), .B(n629), .CI(n628), .CO(n601), .S(n632) );
OAI22X1TS U282 ( .A0(n4688), .A1(n2776), .B0(n4230), .B1(n2920), .Y(n2992)
);
ADDFHX1TS U283 ( .A(n3718), .B(n3717), .CI(n3716), .CO(n3668), .S(n3815) );
ADDFHX1TS U284 ( .A(n1222), .B(n1221), .CI(n1220), .CO(n1236), .S(n1276) );
OAI22X1TS U285 ( .A0(n2464), .A1(n2526), .B0(n84), .B1(n2790), .Y(n2801) );
OAI22X1TS U286 ( .A0(n2904), .A1(n2803), .B0(n64), .B1(n2880), .Y(n3099) );
ADDFHX1TS U287 ( .A(n5200), .B(n5199), .CI(n5198), .CO(n5248), .S(n5236) );
OAI22X1TS U288 ( .A0(n40), .A1(n3846), .B0(n85), .B1(n4252), .Y(n4210) );
OAI22X1TS U289 ( .A0(n6657), .A1(n5754), .B0(n5753), .B1(n5816), .Y(n5803)
);
ADDFHX1TS U290 ( .A(n335), .B(n334), .CI(n333), .CO(n348), .S(n389) );
ADDFHX1TS U291 ( .A(n2166), .B(n2165), .CI(n2164), .CO(n2251), .S(n2373) );
ADDFHX2TS U292 ( .A(n4143), .B(n4142), .CI(n4141), .CO(n4021), .S(n4951) );
ADDFX2TS U293 ( .A(n1282), .B(n1281), .CI(n1280), .CO(n1308), .S(n1295) );
ADDFHX2TS U294 ( .A(n4839), .B(n4840), .CI(n4838), .CO(n4834), .S(n4904) );
ADDFHX1TS U295 ( .A(n2324), .B(n2323), .CI(n2322), .CO(n2612), .S(n2335) );
ADDFHX1TS U296 ( .A(n2030), .B(n2029), .CI(n2028), .CO(n2333), .S(n1882) );
ADDFHX1TS U297 ( .A(n5178), .B(n5177), .CI(n5176), .CO(n5257), .S(n5174) );
ADDFHX2TS U298 ( .A(n2011), .B(n2010), .CI(n2009), .CO(n2044), .S(n2086) );
XOR2X1TS U299 ( .A(n4248), .B(n4423), .Y(n4416) );
ADDFHX1TS U300 ( .A(n2303), .B(n2302), .CI(n2301), .CO(n2669), .S(n2320) );
ADDFHX1TS U301 ( .A(n2175), .B(n2174), .CI(n2173), .CO(n2168), .S(n2250) );
ADDFHX2TS U302 ( .A(n3515), .B(n3514), .CI(n3513), .CO(n3491), .S(n3679) );
ADDFHX1TS U303 ( .A(n2065), .B(n2064), .CI(n2063), .CO(n2081), .S(n2169) );
ADDFHX1TS U304 ( .A(n3902), .B(n3901), .CI(n3900), .CO(n4218), .S(n3836) );
ADDFHX1TS U305 ( .A(n3872), .B(n3871), .CI(n3870), .CO(n4190), .S(n3833) );
ADDFHX1TS U306 ( .A(n1731), .B(n1730), .CI(n1729), .CO(n1761), .S(n1663) );
ADDFHX1TS U307 ( .A(n1719), .B(n1718), .CI(n1717), .CO(n1743), .S(n1667) );
ADDFX1TS U308 ( .A(n3955), .B(n3956), .CI(n3954), .CO(n3790), .S(n4059) );
ADDFX1TS U309 ( .A(n1551), .B(n1550), .CI(n1549), .CO(n1486), .S(n1569) );
ADDFHX1TS U310 ( .A(n5343), .B(n5342), .CI(n5341), .CO(n5444), .S(n5329) );
ADDFHX1TS U311 ( .A(n5346), .B(n5345), .CI(n5344), .CO(n5443), .S(n5382) );
ADDFX1TS U312 ( .A(n5312), .B(n5311), .CI(n5310), .CO(n5395), .S(n5256) );
ADDFX1TS U313 ( .A(n1937), .B(n1936), .CI(n1935), .CO(n2051), .S(n2001) );
ADDFX1TS U314 ( .A(n5471), .B(n5470), .CI(n5469), .CO(n5501), .S(n5473) );
ADDFHX1TS U315 ( .A(n3055), .B(n3054), .CI(n3053), .CO(n3205), .S(n3126) );
CMPR32X2TS U316 ( .A(n5389), .B(n5388), .C(n5387), .CO(n5422), .S(n5377) );
ADDFX1TS U317 ( .A(n4294), .B(n4293), .CI(n4292), .CO(n4415), .S(n4327) );
CMPR32X2TS U318 ( .A(n1679), .B(n1678), .C(n1677), .CO(n1746), .S(n1662) );
CMPR32X2TS U319 ( .A(n354), .B(n353), .C(n352), .CO(n364), .S(n407) );
ADDFX1TS U320 ( .A(n3555), .B(n3554), .CI(n3553), .CO(n3611), .S(n3566) );
CMPR32X2TS U321 ( .A(n6285), .B(n6284), .C(n6283), .CO(n6360), .S(n6280) );
CMPR32X2TS U322 ( .A(n6315), .B(n6314), .C(n6313), .CO(n6356), .S(n6278) );
CMPR32X2TS U323 ( .A(n6363), .B(n6362), .C(n6361), .CO(n6443), .S(n6358) );
ADDFHX1TS U324 ( .A(n5138), .B(n5137), .CI(n5136), .CO(n5238), .S(n5131) );
ADDFHX1TS U325 ( .A(n3512), .B(n3511), .CI(n3510), .CO(n3646), .S(n3694) );
CMPR32X2TS U326 ( .A(n3635), .B(n3634), .C(n3633), .CO(n3666), .S(n3715) );
ADDFX2TS U327 ( .A(n3945), .B(n3946), .CI(n3947), .CO(n3788), .S(n3952) );
CMPR32X2TS U328 ( .A(n574), .B(n573), .C(n572), .CO(n566), .S(n602) );
CMPR32X2TS U329 ( .A(n1820), .B(n1821), .C(n1819), .CO(n2010), .S(n2080) );
CMPR32X2TS U330 ( .A(n1931), .B(n1930), .C(n1929), .CO(n2011), .S(n2143) );
CMPR32X2TS U331 ( .A(n1157), .B(n1156), .C(n1155), .CO(n1372), .S(n1146) );
CMPR32X2TS U332 ( .A(n287), .B(n288), .C(n286), .CO(n1267), .S(n285) );
CMPR32X2TS U333 ( .A(n1205), .B(n1206), .C(n1207), .CO(n1222), .S(n1268) );
CMPR32X2TS U334 ( .A(n2133), .B(n2132), .C(n2131), .CO(n2130), .S(n2172) );
CMPR32X2TS U335 ( .A(n5230), .B(n5229), .C(n5228), .CO(n5314), .S(n5200) );
CMPR32X2TS U336 ( .A(n3997), .B(n3996), .C(n3995), .CO(n3941), .S(n4029) );
CMPR32X2TS U337 ( .A(n860), .B(n859), .C(n858), .CO(n862), .S(n814) );
CMPR32X2TS U338 ( .A(n396), .B(n395), .C(n394), .CO(n375), .S(n446) );
CMPR32X2TS U339 ( .A(n261), .B(n260), .C(n259), .CO(n284), .S(n268) );
CMPR32X2TS U340 ( .A(n6593), .B(n6592), .C(n6591), .CO(n6623), .S(n6567) );
CMPR32X2TS U341 ( .A(n1210), .B(n1209), .C(n1208), .CO(n1187), .S(n1221) );
CMPR32X2TS U342 ( .A(n1198), .B(n1197), .C(n1196), .CO(n1240), .S(n1269) );
CMPR32X2TS U343 ( .A(n1231), .B(n1230), .C(n1229), .CO(n1234), .S(n1271) );
CMPR32X2TS U344 ( .A(n1134), .B(n1133), .C(n1132), .CO(n1216), .S(n1233) );
CMPR32X2TS U345 ( .A(n316), .B(n315), .C(n314), .CO(n338), .S(n376) );
CMPR32X2TS U346 ( .A(n1344), .B(n1343), .C(n1342), .CO(n1442), .S(n1444) );
CMPR32X2TS U347 ( .A(n1411), .B(n1410), .C(n1409), .CO(n1544), .S(n1546) );
CMPR32X2TS U348 ( .A(n1554), .B(n1553), .C(n1552), .CO(n1568), .S(n1446) );
CMPR32X2TS U349 ( .A(n1371), .B(n1370), .C(n1369), .CO(n1412), .S(n1437) );
CMPR32X2TS U350 ( .A(n3440), .B(n3439), .C(n3438), .CO(n3418), .S(n3645) );
CMPR32X2TS U351 ( .A(n3486), .B(n3485), .C(n3484), .CO(n3463), .S(n3547) );
CMPR32X2TS U352 ( .A(n5107), .B(n5106), .C(n5105), .CO(n5203), .S(n5135) );
ADDHXLTS U353 ( .A(n1398), .B(n1397), .CO(n1530), .S(n1461) );
CMPR32X2TS U354 ( .A(n3480), .B(n3479), .C(n3478), .CO(n3549), .S(n3717) );
CMPR32X2TS U355 ( .A(n417), .B(n416), .C(n415), .CO(n447), .S(n933) );
CMPR32X2TS U356 ( .A(n1357), .B(n1356), .C(n1355), .CO(n1447), .S(n1443) );
ADDFX1TS U357 ( .A(n3657), .B(n3656), .CI(n3655), .CO(n3663), .S(n3750) );
ADDFX1TS U358 ( .A(n5148), .B(n5147), .CI(n5146), .CO(n5199), .S(n5075) );
ADDFX1TS U359 ( .A(n329), .B(n328), .CI(n327), .CO(n301), .S(n379) );
ADDFX1TS U360 ( .A(n1377), .B(n1376), .CI(n1375), .CO(n1572), .S(n1440) );
ADDFX1TS U361 ( .A(n405), .B(n404), .CI(n403), .CO(n409), .S(n448) );
ADDFX2TS U362 ( .A(n279), .B(n278), .CI(n277), .CO(n1282), .S(n296) );
CMPR32X2TS U363 ( .A(n6573), .B(n6572), .C(n6571), .CO(n6621), .S(n6579) );
CMPR32X2TS U364 ( .A(n5215), .B(n5214), .C(n5213), .CO(n5302), .S(n5202) );
CMPR32X2TS U365 ( .A(n2181), .B(n2180), .C(n2179), .CO(n2157), .S(n2248) );
ADDFHX1TS U366 ( .A(n4626), .B(n4625), .CI(n4624), .CO(n4648), .S(n4645) );
ADDFHX1TS U367 ( .A(n4777), .B(n4776), .CI(n4775), .CO(n4857), .S(n4866) );
OAI22X1TS U368 ( .A0(n4009), .A1(n3499), .B0(n4566), .B1(n3436), .Y(n3511)
);
OAI22X1TS U369 ( .A0(n149), .A1(n1941), .B0(n3503), .B1(n1851), .Y(n1951) );
ADDFHX1TS U370 ( .A(n4674), .B(n4673), .CI(n4672), .CO(n4842), .S(n4728) );
CMPR32X2TS U371 ( .A(n543), .B(n542), .C(n541), .CO(n971), .S(n571) );
ADDFHX1TS U372 ( .A(n4694), .B(n4693), .CI(n4692), .CO(n4868), .S(n4841) );
ADDFHX2TS U373 ( .A(n4856), .B(n4855), .CI(n4854), .CO(n4650), .S(n4863) );
OAI22X1TS U374 ( .A0(n13), .A1(n6367), .B0(n6366), .B1(n6387), .Y(n6394) );
ADDFHX1TS U375 ( .A(n1433), .B(n1432), .CI(n1431), .CO(n1565), .S(n1373) );
ADDFHX2TS U376 ( .A(n3259), .B(n3258), .CI(n3257), .CO(n4727), .S(n3228) );
OAI22X1TS U377 ( .A0(n3525), .A1(n3524), .B0(n111), .B1(n3523), .Y(n3592) );
ADDFHX1TS U378 ( .A(n1228), .B(n1227), .CI(n1226), .CO(n1272), .S(n1266) );
ADDFHX1TS U379 ( .A(n310), .B(n309), .CI(n308), .CO(n302), .S(n352) );
CMPR32X2TS U380 ( .A(n2113), .B(n2112), .C(n2111), .CO(n2128), .S(n2204) );
ADDFHX1TS U381 ( .A(n371), .B(n370), .CI(n369), .CO(n377), .S(n425) );
ADDFX1TS U382 ( .A(n1160), .B(n1158), .CI(n1159), .CO(n1439), .S(n1148) );
ADDFHX1TS U383 ( .A(n5260), .B(n5259), .CI(n5258), .CO(n5379), .S(n5313) );
ADDFHX1TS U384 ( .A(n165), .B(n164), .CI(n163), .CO(n1279), .S(n272) );
ADDFX1TS U385 ( .A(n3709), .B(n3708), .CI(n3707), .CO(n3662), .S(n3813) );
ADDFHX1TS U386 ( .A(n1120), .B(n1119), .CI(n1118), .CO(n1188), .S(n1082) );
ADDFHX1TS U387 ( .A(n258), .B(n257), .CI(n256), .CO(n273), .S(n269) );
CMPR32X2TS U388 ( .A(n2018), .B(n2017), .C(n2016), .CO(n2047), .S(n1920) );
ADDFX1TS U389 ( .A(n225), .B(n224), .CI(n223), .CO(n263), .S(n337) );
ADDFX1TS U390 ( .A(n1759), .B(n1758), .CI(n1757), .CO(n2164), .S(n1762) );
ADDFHX1TS U391 ( .A(n1417), .B(n1416), .CI(n1415), .CO(n1454), .S(n1441) );
ADDFHX1TS U392 ( .A(n1430), .B(n1429), .CI(n1428), .CO(n1571), .S(n1566) );
CMPR32X2TS U393 ( .A(n3509), .B(n3508), .C(n3507), .CO(n3548), .S(n3695) );
CMPR32X2TS U394 ( .A(n6181), .B(n6180), .C(n6179), .CO(n6267), .S(n6198) );
ADDFHX1TS U395 ( .A(n1420), .B(n1419), .CI(n1418), .CO(n1545), .S(n1453) );
ADDFX1TS U396 ( .A(n1225), .B(n1224), .CI(n1223), .CO(n1273), .S(n1278) );
CMPR32X2TS U397 ( .A(n456), .B(n455), .C(n454), .CO(n464), .S(n957) );
ADDFHX1TS U398 ( .A(n1436), .B(n1435), .CI(n1434), .CO(n1547), .S(n1564) );
CMPR32X2TS U399 ( .A(n1541), .B(n1540), .C(n1539), .CO(n1720), .S(n1558) );
CMPR32X2TS U400 ( .A(n3808), .B(n3807), .C(n3806), .CO(n3814), .S(n4011) );
CMPR32X2TS U401 ( .A(n4602), .B(n4601), .C(n4600), .CO(n4622), .S(n4849) );
CMPR32X2TS U402 ( .A(n4589), .B(n4590), .C(n4591), .CO(n4623), .S(n4627) );
CMPR32X2TS U403 ( .A(n4762), .B(n4761), .C(n4760), .CO(n4771), .S(n4811) );
CMPR32X2TS U404 ( .A(n3208), .B(n3207), .C(n3206), .CO(n4798), .S(n3203) );
CMPR32X2TS U405 ( .A(n4759), .B(n4758), .C(n4757), .CO(n4781), .S(n4796) );
CMPR32X2TS U406 ( .A(n1093), .B(n1092), .C(n1091), .CO(n1251), .S(n1265) );
CMPR32X2TS U407 ( .A(n3199), .B(n3198), .C(n3197), .CO(n4673), .S(n3188) );
CMPR32X2TS U408 ( .A(n4680), .B(n4679), .C(n4678), .CO(n4850), .S(n4693) );
CMPR32X2TS U409 ( .A(n202), .B(n201), .C(n200), .CO(n280), .S(n230) );
CMPR32X2TS U410 ( .A(n3196), .B(n3195), .C(n3194), .CO(n4674), .S(n3191) );
CMPR32X2TS U411 ( .A(n3758), .B(n3757), .C(n3756), .CO(n3751), .S(n3971) );
CMPR32X2TS U412 ( .A(n4042), .B(n4041), .C(n4040), .CO(n3984), .S(n4666) );
CMPR32X2TS U413 ( .A(n4765), .B(n4764), .C(n4763), .CO(n4662), .S(n4770) );
CMPR32X2TS U414 ( .A(n1034), .B(n1033), .C(n1032), .CO(n1023), .S(n1080) );
CMPR32X2TS U415 ( .A(n562), .B(n561), .C(n560), .CO(n563), .S(n603) );
CMPR32X2TS U416 ( .A(n4473), .B(n4472), .C(n4471), .CO(n5105), .S(n4475) );
CLKBUFX2TS U417 ( .A(n1825), .Y(n5580) );
CMPR32X2TS U418 ( .A(n592), .B(n591), .C(n590), .CO(n586), .S(n636) );
CMPR32X2TS U419 ( .A(n528), .B(n527), .C(n526), .CO(n958), .S(n942) );
CMPR32X2TS U420 ( .A(n650), .B(n649), .C(n648), .CO(n641), .S(n678) );
CMPR32X2TS U421 ( .A(n534), .B(n533), .C(n532), .CO(n940), .S(n543) );
CMPR32X2TS U422 ( .A(n3015), .B(n3014), .C(n3013), .CO(n3192), .S(n3131) );
CMPR32X2TS U423 ( .A(n595), .B(n594), .C(n593), .CO(n605), .S(n635) );
CMPR32X2TS U424 ( .A(n512), .B(n511), .C(n510), .CO(n521), .S(n573) );
CMPR32X2TS U425 ( .A(n559), .B(n558), .C(n557), .CO(n574), .S(n604) );
CMPR32X2TS U426 ( .A(n6514), .B(n6513), .C(n6512), .CO(n6554), .S(n6516) );
OAI22X1TS U427 ( .A0(n2633), .A1(n3401), .B0(n5893), .B1(n3428), .Y(n3543)
);
OAI22X1TS U428 ( .A0(n2464), .A1(n1153), .B0(n83), .B1(n1378), .Y(n1432) );
BUFX3TS U429 ( .A(n6258), .Y(n6195) );
OAI22X1TS U430 ( .A0(n6184), .A1(n1423), .B0(n4420), .B1(n1494), .Y(n1533)
);
OAI22X1TS U431 ( .A0(n120), .A1(n3957), .B0(n58), .B1(n3742), .Y(n3804) );
ADDFHX1TS U432 ( .A(n2891), .B(n2890), .CI(n2889), .CO(n3190), .S(n2887) );
ADDFHX1TS U433 ( .A(n3994), .B(n3993), .CI(n3992), .CO(n3970), .S(n4030) );
ADDFHX1TS U434 ( .A(n2973), .B(n2972), .CI(n2971), .CO(n3193), .S(n3051) );
CMPR32X2TS U435 ( .A(n4677), .B(n4676), .C(n4675), .CO(n4694), .S(n4778) );
CMPR32X2TS U436 ( .A(n1151), .B(n1150), .C(n1149), .CO(n1374), .S(n1022) );
CMPR32X2TS U437 ( .A(n4822), .B(n4821), .C(n4820), .CO(n4853), .S(n4808) );
CMPR32X2TS U438 ( .A(n2976), .B(n2975), .C(n2974), .CO(n3189), .S(n3050) );
ADDFHX1TS U439 ( .A(n540), .B(n539), .CI(n538), .CO(n960), .S(n541) );
ADDFHX1TS U440 ( .A(n3035), .B(n3034), .CI(n3033), .CO(n3262), .S(n3132) );
CMPR32X2TS U441 ( .A(n4605), .B(n4604), .C(n4603), .CO(n4855), .S(n4848) );
CMPR32X2TS U442 ( .A(n708), .B(n707), .C(n706), .CO(n699), .S(n879) );
ADDFHX1TS U443 ( .A(n3938), .B(n3937), .CI(n3936), .CO(n3983), .S(n4663) );
BUFX3TS U444 ( .A(n6655), .Y(n7059) );
CMPR32X2TS U445 ( .A(n6553), .B(n6552), .C(n6551), .CO(n6591), .S(n6555) );
CMPR32X2TS U446 ( .A(n477), .B(n476), .C(n475), .CO(n935), .S(n939) );
CMPR32X2TS U447 ( .A(n489), .B(n488), .C(n487), .CO(n538), .S(n564) );
CMPR32X2TS U448 ( .A(n738), .B(n737), .C(n736), .CO(n849), .S(n747) );
CLKBUFX2TS U449 ( .A(n155), .Y(n2462) );
CLKBUFX2TS U450 ( .A(n422), .Y(n3503) );
CLKBUFX2TS U451 ( .A(n1516), .Y(n150) );
BUFX6TS U452 ( .A(n5456), .Y(n4381) );
CLKBUFX2TS U453 ( .A(n1825), .Y(n6056) );
BUFX3TS U454 ( .A(n4532), .Y(n6003) );
BUFX3TS U455 ( .A(n3388), .Y(n5373) );
INVX2TS U456 ( .A(n57), .Y(n58) );
CLKBUFX2TS U457 ( .A(n5757), .Y(n6660) );
INVX2TS U458 ( .A(n6390), .Y(n6311) );
CLKBUFX2TS U459 ( .A(n5886), .Y(n6379) );
BUFX3TS U460 ( .A(n5266), .Y(n6381) );
BUFX3TS U461 ( .A(n1516), .Y(n4704) );
CLKBUFX2TS U462 ( .A(n6258), .Y(n6616) );
CLKBUFX2TS U463 ( .A(n6485), .Y(n7046) );
CLKBUFX2TS U464 ( .A(n6485), .Y(n7019) );
BUFX4TS U465 ( .A(n3959), .Y(n1964) );
BUFX4TS U466 ( .A(n6399), .Y(n6732) );
INVX2TS U467 ( .A(n4), .Y(n44) );
BUFX3TS U468 ( .A(n3365), .Y(n113) );
BUFX3TS U469 ( .A(n3425), .Y(n141) );
BUFX3TS U470 ( .A(n5883), .Y(n3735) );
BUFX4TS U471 ( .A(n5884), .Y(n6316) );
OAI22X1TS U472 ( .A0(n4479), .A1(n3210), .B0(n52), .B1(n4738), .Y(n4736) );
OAI22X1TS U473 ( .A0(n4135), .A1(n4568), .B0(n111), .B1(n4134), .Y(n4584) );
OAI22X1TS U474 ( .A0(n8), .A1(n3221), .B0(n5585), .B1(n4124), .Y(n4756) );
BUFX4TS U475 ( .A(n55), .Y(n4390) );
OAI22X1TS U476 ( .A0(n126), .A1(n1021), .B0(n62), .B1(n1154), .Y(n1150) );
INVX2TS U477 ( .A(n65), .Y(n67) );
CLKBUFX2TS U478 ( .A(n4322), .Y(n5798) );
BUFX3TS U479 ( .A(n6655), .Y(n6605) );
CLKBUFX2TS U480 ( .A(n5714), .Y(n5120) );
OAI22X1TS U481 ( .A0(n4009), .A1(n4132), .B0(n4566), .B1(n4008), .Y(n4074)
);
ADDFHX1TS U482 ( .A(n519), .B(n518), .CI(n517), .CO(n539), .S(n535) );
CLKBUFX2TS U483 ( .A(n1825), .Y(n4686) );
INVX6TS U484 ( .A(n6261), .Y(n128) );
CLKBUFX3TS U485 ( .A(n4691), .Y(n60) );
INVX2TS U486 ( .A(n6991), .Y(n6735) );
BUFX3TS U487 ( .A(n3348), .Y(n4006) );
INVX2TS U488 ( .A(n6368), .Y(n5185) );
BUFX3TS U489 ( .A(n4422), .Y(n5621) );
BUFX3TS U490 ( .A(n4479), .Y(n2904) );
BUFX3TS U491 ( .A(n6511), .Y(n6685) );
BUFX6TS U492 ( .A(n5249), .Y(n4746) );
INVX6TS U493 ( .A(n65), .Y(n8) );
CLKBUFX2TS U494 ( .A(n3754), .Y(n2106) );
CLKBUFX2TS U495 ( .A(n3346), .Y(n6541) );
BUFX3TS U496 ( .A(n2935), .Y(n6251) );
INVX2TS U497 ( .A(n6540), .Y(n6376) );
BUFX6TS U498 ( .A(n3959), .Y(n3072) );
INVX2TS U499 ( .A(Data_A_i[53]), .Y(n6062) );
INVX2TS U500 ( .A(n6586), .Y(n5721) );
BUFX6TS U501 ( .A(n5757), .Y(n5702) );
BUFX3TS U502 ( .A(n6586), .Y(n7020) );
INVX4TS U503 ( .A(n6014), .Y(n145) );
BUFX4TS U504 ( .A(n4422), .Y(n6184) );
INVX4TS U505 ( .A(n4), .Y(n51) );
CLKBUFX2TS U506 ( .A(n1393), .Y(n4593) );
BUFX3TS U507 ( .A(n4391), .Y(n6063) );
BUFX3TS U508 ( .A(n6586), .Y(n6531) );
BUFX4TS U509 ( .A(n54), .Y(n2056) );
CLKBUFX3TS U510 ( .A(n1516), .Y(n5294) );
BUFX4TS U511 ( .A(n3425), .Y(n140) );
INVX2TS U512 ( .A(n57), .Y(n59) );
BUFX4TS U513 ( .A(n5249), .Y(n4096) );
BUFX4TS U514 ( .A(n3365), .Y(n4688) );
INVX2TS U515 ( .A(n86), .Y(n7) );
INVX2TS U516 ( .A(Data_A_i[53]), .Y(n7016) );
BUFX4TS U517 ( .A(n6065), .Y(n5451) );
BUFX3TS U518 ( .A(n3365), .Y(n5549) );
CLKBUFX2TS U519 ( .A(n1393), .Y(n4091) );
BUFX4TS U520 ( .A(n4532), .Y(n5945) );
BUFX4TS U521 ( .A(n5494), .Y(n5717) );
BUFX3TS U522 ( .A(n6258), .Y(n4566) );
BUFX3TS U523 ( .A(n4532), .Y(n130) );
BUFX3TS U524 ( .A(n3425), .Y(n5585) );
BUFX4TS U525 ( .A(n6399), .Y(n6769) );
BUFX3TS U526 ( .A(n3346), .Y(n139) );
BUFX3TS U527 ( .A(n3361), .Y(n2984) );
CLKBUFX2TS U528 ( .A(n6365), .Y(n5291) );
BUFX3TS U529 ( .A(n5817), .Y(n6468) );
CLKBUFX2TS U530 ( .A(n6365), .Y(n4750) );
INVX2TS U531 ( .A(n42), .Y(n41) );
INVX2TS U532 ( .A(n4252), .Y(n1896) );
BUFX3TS U533 ( .A(n2525), .Y(n2464) );
BUFX6TS U534 ( .A(n3425), .Y(n5517) );
INVX2TS U535 ( .A(n1816), .Y(n3753) );
INVX2TS U536 ( .A(n5863), .Y(n3073) );
INVX4TS U537 ( .A(n726), .Y(n2965) );
INVX2TS U538 ( .A(n5664), .Y(n4032) );
INVX2TS U539 ( .A(n5370), .Y(n5190) );
CLKBUFX2TS U540 ( .A(n1913), .Y(n3273) );
BUFX3TS U541 ( .A(n1828), .Y(n735) );
INVX2TS U542 ( .A(n5253), .Y(n3781) );
INVX6TS U543 ( .A(n86), .Y(n88) );
INVX2TS U544 ( .A(n42), .Y(n40) );
CLKBUFX2TS U545 ( .A(n1913), .Y(n671) );
BUFX4TS U546 ( .A(n5431), .Y(n5817) );
INVX2TS U547 ( .A(n7090), .Y(n7048) );
INVX2TS U548 ( .A(n6646), .Y(n5465) );
INVX2TS U549 ( .A(n65), .Y(n66) );
BUFX4TS U550 ( .A(n3959), .Y(n704) );
BUFX4TS U551 ( .A(n1516), .Y(n148) );
BUFX3TS U552 ( .A(n6365), .Y(n7093) );
INVX2TS U553 ( .A(n5467), .Y(n3068) );
BUFX4TS U554 ( .A(n7045), .Y(n5622) );
INVX4TS U555 ( .A(n4), .Y(n63) );
BUFX3TS U556 ( .A(n3959), .Y(n1096) );
BUFX3TS U557 ( .A(n2525), .Y(n4684) );
BUFX3TS U558 ( .A(n1020), .Y(n1517) );
BUFX3TS U559 ( .A(n5293), .Y(n2034) );
CLKBUFX2TS U560 ( .A(n196), .Y(n2516) );
BUFX4TS U561 ( .A(n6485), .Y(n4122) );
CLKBUFX2TS U562 ( .A(n155), .Y(n625) );
BUFX16TS U563 ( .A(n6487), .Y(n6399) );
OAI22X1TS U564 ( .A0(n1470), .A1(n188), .B0(n38), .B1(n1131), .Y(n1085) );
BUFX3TS U565 ( .A(Data_A_i[53]), .Y(n6386) );
INVX2TS U566 ( .A(Data_A_i[53]), .Y(n7091) );
INVX2TS U567 ( .A(n6768), .Y(n6388) );
INVX2TS U568 ( .A(n3773), .Y(n4071) );
INVX2TS U569 ( .A(n3652), .Y(n3988) );
CLKBUFX2TS U570 ( .A(Data_A_i[17]), .Y(n81) );
BUFX3TS U571 ( .A(n3047), .Y(n6655) );
INVX2TS U572 ( .A(n4579), .Y(n143) );
INVX2TS U573 ( .A(n75), .Y(n76) );
BUFX3TS U574 ( .A(n1385), .Y(n5714) );
INVX1TS U575 ( .A(n155), .Y(n4682) );
CLKINVX12TS U576 ( .A(n9), .Y(n4) );
INVX3TS U577 ( .A(n2525), .Y(n42) );
INVX2TS U578 ( .A(n3398), .Y(n4108) );
BUFX3TS U579 ( .A(n4322), .Y(n4575) );
INVX2TS U580 ( .A(n6368), .Y(n6238) );
BUFX4TS U581 ( .A(n196), .Y(n3425) );
CLKINVX2TS U582 ( .A(n4479), .Y(n1506) );
INVX2TS U583 ( .A(Data_B_i[30]), .Y(n6061) );
INVX2TS U584 ( .A(Data_A_i[21]), .Y(n5436) );
BUFX4TS U585 ( .A(n2862), .Y(n7045) );
BUFX3TS U586 ( .A(n622), .Y(n762) );
INVX2TS U587 ( .A(Data_B_i[21]), .Y(n5467) );
CLKBUFX2TS U588 ( .A(n2964), .Y(n733) );
INVX2TS U589 ( .A(Data_B_i[53]), .Y(n7090) );
INVX2TS U590 ( .A(Data_B_i[24]), .Y(n5664) );
BUFX3TS U591 ( .A(n622), .Y(n1054) );
INVX2TS U592 ( .A(n4579), .Y(n144) );
INVX2TS U593 ( .A(Data_A_i[41]), .Y(n6588) );
INVX4TS U594 ( .A(Data_A_i[49]), .Y(n6991) );
INVX2TS U595 ( .A(Data_B_i[46]), .Y(n6731) );
INVX2TS U596 ( .A(Data_A_i[31]), .Y(n6123) );
INVX4TS U597 ( .A(n726), .Y(n4078) );
INVX2TS U598 ( .A(n6257), .Y(n4082) );
BUFX6TS U599 ( .A(n2892), .Y(n4258) );
CLKINVX6TS U600 ( .A(n3754), .Y(n4579) );
BUFX8TS U601 ( .A(n199), .Y(n3361) );
BUFX8TS U602 ( .A(n2558), .Y(n6992) );
NAND2X6TS U603 ( .A(n1535), .B(n6391), .Y(n5266) );
BUFX4TS U604 ( .A(n96), .Y(n790) );
BUFX4TS U605 ( .A(n177), .Y(n2964) );
NAND2X4TS U606 ( .A(n154), .B(n155), .Y(n2525) );
INVX4TS U607 ( .A(Data_A_i[47]), .Y(n6768) );
BUFX4TS U608 ( .A(n4052), .Y(n4614) );
INVX2TS U609 ( .A(Data_B_i[51]), .Y(n7047) );
BUFX8TS U610 ( .A(n622), .Y(n4577) );
INVX4TS U611 ( .A(Data_A_i[35]), .Y(n6368) );
INVX4TS U612 ( .A(Data_A_i[51]), .Y(n7044) );
XOR2X2TS U613 ( .A(Data_A_i[53]), .B(Data_A_i[52]), .Y(n3045) );
XOR2X2TS U614 ( .A(Data_A_i[35]), .B(Data_A_i[34]), .Y(n1383) );
INVX2TS U615 ( .A(n4760), .Y(n616) );
INVX6TS U616 ( .A(n2298), .Y(n6487) );
CLKINVX2TS U617 ( .A(Data_A_i[44]), .Y(n2012) );
BUFX8TS U618 ( .A(n1536), .Y(n6391) );
INVX4TS U619 ( .A(Data_A_i[5]), .Y(n1816) );
INVX2TS U620 ( .A(Data_A_i[19]), .Y(n5292) );
XOR2X2TS U621 ( .A(Data_A_i[36]), .B(Data_A_i[37]), .Y(n1535) );
XOR2X2TS U622 ( .A(Data_A_i[20]), .B(Data_A_i[21]), .Y(n156) );
XOR2X1TS U623 ( .A(Data_A_i[47]), .B(Data_A_i[46]), .Y(n2470) );
BUFX3TS U624 ( .A(n179), .Y(n2345) );
INVX6TS U625 ( .A(n1019), .Y(n2503) );
CLKINVX2TS U626 ( .A(Data_A_i[16]), .Y(n174) );
BUFX8TS U627 ( .A(n179), .Y(n5893) );
INVX8TS U628 ( .A(Data_A_i[9]), .Y(n3398) );
INVX4TS U629 ( .A(Data_A_i[0]), .Y(n1913) );
INVX8TS U630 ( .A(Data_A_i[1]), .Y(n4760) );
XOR2X2TS U631 ( .A(Data_A_i[23]), .B(Data_A_i[22]), .Y(n162) );
INVX6TS U632 ( .A(Data_A_i[11]), .Y(n1019) );
INVX6TS U633 ( .A(Data_A_i[7]), .Y(n3455) );
XOR2X1TS U634 ( .A(Data_A_i[24]), .B(Data_A_i[25]), .Y(n161) );
INVX2TS U635 ( .A(n2905), .Y(n2906) );
INVX2TS U636 ( .A(n3653), .Y(n4068) );
INVX2TS U637 ( .A(n4050), .Y(n3241) );
NOR2XLTS U638 ( .A(n5622), .B(n3240), .Y(n3077) );
XNOR2X1TS U639 ( .A(n4051), .B(Data_B_i[53]), .Y(n4611) );
XNOR2X1TS U640 ( .A(n4076), .B(n5911), .Y(n3974) );
BUFX3TS U641 ( .A(n2964), .Y(n4714) );
NOR2XLTS U642 ( .A(n5938), .B(n3653), .Y(n3757) );
INVX2TS U643 ( .A(n5886), .Y(n4596) );
INVX4TS U644 ( .A(n6002), .Y(n3908) );
INVX2TS U645 ( .A(n5231), .Y(n4487) );
INVX2TS U646 ( .A(n5467), .Y(n5289) );
BUFX3TS U647 ( .A(n6586), .Y(n5815) );
INVX2TS U648 ( .A(n6377), .Y(n4335) );
INVX2TS U649 ( .A(Data_A_i[53]), .Y(n5938) );
INVX2TS U650 ( .A(n6123), .Y(n5449) );
OAI22X1TS U651 ( .A0(n4688), .A1(n2013), .B0(n4230), .B1(n2062), .Y(n2041)
);
CLKBUFX2TS U652 ( .A(n3346), .Y(n3357) );
BUFX6TS U653 ( .A(n6319), .Y(n4582) );
OAI22X1TS U654 ( .A0(n3356), .A1(n2508), .B0(n2507), .B1(n2506), .Y(n2539)
);
BUFX4TS U655 ( .A(n5494), .Y(n4599) );
OAI22X1TS U656 ( .A0(n130), .A1(n2961), .B0(n5226), .B1(n2960), .Y(n3002) );
ADDHXLTS U657 ( .A(n3271), .B(n3270), .CO(n4699), .S(n3224) );
OAI22X1TS U658 ( .A0(n4635), .A1(n3211), .B0(n136), .B1(n4597), .Y(n4735) );
ADDFX1TS U659 ( .A(n4710), .B(n4709), .CI(n4708), .CO(n4719), .S(n4722) );
OAI22X1TS U660 ( .A0(n70), .A1(n4117), .B0(n4743), .B1(n4053), .Y(n4115) );
INVX2TS U661 ( .A(n3454), .Y(n3657) );
NOR2XLTS U662 ( .A(n6062), .B(n3400), .Y(n3453) );
INVX2TS U663 ( .A(n4596), .Y(n136) );
BUFX3TS U664 ( .A(n3388), .Y(n3618) );
OAI22X1TS U665 ( .A0(n55), .A1(n3627), .B0(n38), .B1(n3841), .Y(n3899) );
INVX2TS U666 ( .A(n3844), .Y(n3593) );
NOR2XLTS U667 ( .A(n5938), .B(n3845), .Y(n4245) );
NAND2X1TS U668 ( .A(n4424), .B(n4423), .Y(n4427) );
CLKBUFX2TS U669 ( .A(n422), .Y(n5233) );
OAI22X1TS U670 ( .A0(n5373), .A1(n5232), .B0(n5371), .B1(n5280), .Y(n5259)
);
OAI22X1TS U671 ( .A0(n67), .A1(n5369), .B0(n5585), .B1(n5419), .Y(n5471) );
BUFX3TS U672 ( .A(n4391), .Y(n5390) );
INVX2TS U673 ( .A(n6646), .Y(n5864) );
INVX2TS U674 ( .A(n6731), .Y(n5697) );
BUFX3TS U675 ( .A(n54), .Y(n5667) );
BUFX3TS U676 ( .A(n6258), .Y(n5758) );
INVX2TS U677 ( .A(Data_B_i[32]), .Y(n75) );
CLKINVX6TS U678 ( .A(n5438), .Y(n68) );
INVX6TS U679 ( .A(n3398), .Y(n2343) );
BUFX3TS U680 ( .A(n4532), .Y(n5251) );
CLKBUFX2TS U681 ( .A(n2935), .Y(n5144) );
NOR2XLTS U682 ( .A(n5938), .B(n5937), .Y(n6060) );
INVX2TS U683 ( .A(n6014), .Y(n146) );
ADDFX2TS U684 ( .A(n3038), .B(n3037), .CI(n3036), .CO(n3261), .S(n3020) );
OAI22X1TS U685 ( .A0(n4225), .A1(n3619), .B0(n6732), .B1(n3880), .Y(n3901)
);
INVX2TS U686 ( .A(n5230), .Y(n5148) );
OAI22X1TS U687 ( .A0(n113), .A1(n5334), .B0(n5580), .B1(n5417), .Y(n5413) );
INVX2TS U688 ( .A(n5663), .Y(n5609) );
NOR2XLTS U689 ( .A(n5721), .B(n5605), .Y(n5662) );
INVX2TS U690 ( .A(n5795), .Y(n5725) );
OAI22X1TS U691 ( .A0(n6525), .A1(n5751), .B0(n6589), .B1(n5821), .Y(n5804)
);
BUFX3TS U692 ( .A(n6319), .Y(n5980) );
INVX2TS U693 ( .A(n6181), .Y(n6106) );
CLKBUFX2TS U694 ( .A(n2862), .Y(n6234) );
NOR2XLTS U695 ( .A(n7091), .B(n6257), .Y(n6302) );
BUFX3TS U696 ( .A(n5494), .Y(n6310) );
BUFX3TS U697 ( .A(n5266), .Y(n5217) );
INVX4TS U698 ( .A(Data_A_i[37]), .Y(n6390) );
INVX2TS U699 ( .A(Data_A_i[17]), .Y(n5119) );
BUFX6TS U700 ( .A(n422), .Y(n5293) );
BUFX6TS U701 ( .A(n548), .Y(n9) );
BUFX3TS U702 ( .A(n1020), .Y(n2507) );
BUFX3TS U703 ( .A(n1516), .Y(n5235) );
BUFX3TS U704 ( .A(n1393), .Y(n1379) );
INVX4TS U705 ( .A(n4), .Y(n52) );
BUFX3TS U706 ( .A(n2964), .Y(n2781) );
BUFX4TS U707 ( .A(n3348), .Y(n1395) );
CLKBUFX2TS U708 ( .A(n422), .Y(n1514) );
ADDFX1TS U709 ( .A(n1534), .B(n1533), .CI(n1532), .CO(n1722), .S(n1529) );
BUFX3TS U710 ( .A(n5883), .Y(n6707) );
INVX2TS U711 ( .A(n6419), .Y(n6351) );
INVX2TS U712 ( .A(n6464), .Y(n6422) );
NOR2XLTS U713 ( .A(n7091), .B(n6378), .Y(n6463) );
INVX2TS U714 ( .A(n6553), .Y(n6514) );
INVX2TS U715 ( .A(Data_B_i[43]), .Y(n6646) );
NOR2XLTS U716 ( .A(n7016), .B(n6518), .Y(n6614) );
CLKXOR2X2TS U717 ( .A(Data_A_i[50]), .B(Data_A_i[51]), .Y(n2861) );
INVX2TS U718 ( .A(Data_B_i[4]), .Y(n3652) );
CLKBUFX2TS U719 ( .A(n1913), .Y(n1346) );
CLKBUFX2TS U720 ( .A(n155), .Y(n1105) );
BUFX3TS U721 ( .A(n1828), .Y(n2967) );
OAI22X1TS U722 ( .A0(n508), .A1(n507), .B0(n1379), .B1(n498), .Y(n518) );
INVX2TS U723 ( .A(Data_B_i[48]), .Y(n6886) );
NOR2XLTS U724 ( .A(n7016), .B(n6711), .Y(n6743) );
NOR2XLTS U725 ( .A(n7016), .B(n6646), .Y(n6680) );
CLKBUFX2TS U726 ( .A(n2862), .Y(n7017) );
INVX12TS U727 ( .A(n4577), .Y(n86) );
CLKBUFX2TS U728 ( .A(n1828), .Y(n110) );
BUFX3TS U729 ( .A(n2964), .Y(n1176) );
NOR2XLTS U730 ( .A(n7092), .B(n6994), .Y(n7013) );
ADDFHX2TS U731 ( .A(n2151), .B(n2150), .CI(n2149), .CO(n2153), .S(n2224) );
ADDFHX2TS U732 ( .A(n4896), .B(n4895), .CI(n4894), .CO(n4882), .S(n4922) );
INVX2TS U733 ( .A(n7216), .Y(n1005) );
OAI21X1TS U734 ( .A0(n7071), .A1(n7070), .B0(n7069), .Y(n7449) );
INVX2TS U735 ( .A(n7554), .Y(n7501) );
CLKBUFX2TS U736 ( .A(n2871), .Y(n1726) );
INVX2TS U737 ( .A(n7785), .Y(n808) );
INVX2TS U738 ( .A(n7430), .Y(n7433) );
NAND2X1TS U739 ( .A(n7308), .B(n7310), .Y(n7466) );
NOR2X2TS U740 ( .A(n6813), .B(n6812), .Y(n7420) );
NOR2X2TS U741 ( .A(n6807), .B(n6806), .Y(n7303) );
INVX2TS U742 ( .A(n7537), .Y(n7530) );
ADDFHX2TS U743 ( .A(n5403), .B(n5402), .CI(n5401), .CO(n6783), .S(n6778) );
NAND2X1TS U744 ( .A(n7055), .B(n6939), .Y(n6941) );
INVX2TS U745 ( .A(n7164), .Y(n6910) );
INVX2TS U746 ( .A(n7220), .Y(n7213) );
INVX2TS U747 ( .A(n7689), .Y(n7690) );
NAND2X1TS U748 ( .A(n6896), .B(n6895), .Y(n6998) );
INVX2TS U749 ( .A(n7439), .Y(n7442) );
CLKBUFX2TS U750 ( .A(n1913), .Y(n839) );
OAI21XLTS U751 ( .A0(n7107), .A1(n7303), .B0(n7304), .Y(n7108) );
NAND2X2TS U752 ( .A(n2449), .B(n2448), .Y(n7658) );
INVX2TS U753 ( .A(n7382), .Y(n7384) );
NAND2X1TS U754 ( .A(n5042), .B(n5041), .Y(n7534) );
NOR2XLTS U755 ( .A(n7558), .B(n7503), .Y(n7505) );
INVX2TS U756 ( .A(n7295), .Y(n7155) );
OR2X2TS U757 ( .A(n6827), .B(n6826), .Y(n18) );
INVX2TS U758 ( .A(n7271), .Y(n7783) );
OAI21XLTS U759 ( .A0(n7724), .A1(n7743), .B0(n7744), .Y(n7725) );
INVX2TS U760 ( .A(n7713), .Y(n7208) );
NAND2X1TS U761 ( .A(n1337), .B(n1336), .Y(n7694) );
NAND2X1TS U762 ( .A(n6906), .B(n6905), .Y(n6907) );
INVX2TS U763 ( .A(n7177), .Y(n7636) );
OAI21XLTS U764 ( .A0(n7636), .A1(n7326), .B0(n7325), .Y(n7331) );
BUFX6TS U765 ( .A(n5063), .Y(n34) );
AOI21X1TS U766 ( .A0(n34), .A1(n6959), .B0(n6958), .Y(n6964) );
OAI21XLTS U767 ( .A0(n7687), .A1(n7683), .B0(n7685), .Y(n7317) );
OAI21XLTS U768 ( .A0(n7722), .A1(n7226), .B0(n7719), .Y(n7229) );
OAI21XLTS U769 ( .A0(n7687), .A1(n7202), .B0(n7201), .Y(n7206) );
INVX4TS U770 ( .A(n4579), .Y(n142) );
INVX2TS U771 ( .A(Data_B_i[52]), .Y(n78) );
BUFX3TS U772 ( .A(n6365), .Y(n6657) );
INVX2TS U773 ( .A(n4682), .Y(n85) );
INVX2TS U774 ( .A(n4682), .Y(n84) );
INVX2TS U775 ( .A(n68), .Y(n71) );
OR2X2TS U776 ( .A(n6821), .B(n6820), .Y(n1) );
OR2X4TS U777 ( .A(n1330), .B(n1329), .Y(n2) );
INVX4TS U778 ( .A(n53), .Y(n55) );
OR2X1TS U779 ( .A(n807), .B(n806), .Y(n3) );
XOR2X2TS U780 ( .A(Data_A_i[26]), .B(Data_A_i[27]), .Y(n178) );
OAI22X2TS U781 ( .A0(n1395), .A1(n1380), .B0(n1393), .B1(n1394), .Y(n1429)
);
INVX1TS U782 ( .A(n7476), .Y(n7477) );
INVX1TS U783 ( .A(n7125), .Y(n7117) );
NOR2X4TS U784 ( .A(n7574), .B(n5036), .Y(n7586) );
INVX1TS U785 ( .A(n7428), .Y(n7429) );
INVX1TS U786 ( .A(n7405), .Y(n7103) );
NOR2X1TS U787 ( .A(n7142), .B(n7144), .Y(n7147) );
INVX1TS U788 ( .A(n7603), .Y(n7605) );
OAI21X2TS U789 ( .A0(n7230), .A1(n994), .B0(n993), .Y(n7210) );
OAI21X1TS U790 ( .A0(n7751), .A1(n7243), .B0(n7242), .Y(n7247) );
OAI21X1TS U791 ( .A0(n7654), .A1(n7653), .B0(n7652), .Y(n7655) );
CLKINVX2TS U792 ( .A(n7640), .Y(n7651) );
CLKINVX2TS U793 ( .A(n7031), .Y(n7032) );
INVX1TS U794 ( .A(n7449), .Y(n7450) );
INVX1TS U795 ( .A(n7447), .Y(n7451) );
INVX1TS U796 ( .A(n7400), .Y(n7401) );
INVX1TS U797 ( .A(n7616), .Y(n7599) );
INVX1TS U798 ( .A(n7533), .Y(n7540) );
INVX1TS U799 ( .A(n7511), .Y(n7512) );
INVX1TS U800 ( .A(n7534), .Y(n7538) );
CLKINVX2TS U801 ( .A(n7071), .Y(n7002) );
AOI21X1TS U802 ( .A0(n6853), .A1(n7165), .B0(n6852), .Y(n6854) );
CLKINVX2TS U803 ( .A(n6929), .Y(n6930) );
INVX2TS U804 ( .A(n7393), .Y(n7396) );
INVX2TS U805 ( .A(n7256), .Y(n7771) );
CLKINVX2TS U806 ( .A(n7144), .Y(n7036) );
INVX1TS U807 ( .A(n7203), .Y(n7191) );
INVX1TS U808 ( .A(n7001), .Y(n6872) );
NAND2X2TS U809 ( .A(n6979), .B(n7000), .Y(n7040) );
AOI21X2TS U810 ( .A0(n21), .A1(n7235), .B0(n912), .Y(n913) );
CLKINVX2TS U811 ( .A(n7148), .Y(n7150) );
CLKINVX2TS U812 ( .A(n7265), .Y(n7782) );
INVX1TS U813 ( .A(n7128), .Y(n7130) );
INVX1TS U814 ( .A(n7487), .Y(n6849) );
INVX3TS U815 ( .A(n4882), .Y(n5) );
INVX1TS U816 ( .A(n6935), .Y(n6828) );
AND2X2TS U817 ( .A(n7310), .B(n7309), .Y(n7311) );
CLKINVX2TS U818 ( .A(n7758), .Y(n7759) );
INVX1TS U819 ( .A(n7470), .Y(n7472) );
OAI21X1TS U820 ( .A0(n6974), .A1(n7471), .B0(n6975), .Y(n6868) );
INVX1TS U821 ( .A(n4978), .Y(n4976) );
NAND2X2TS U822 ( .A(n988), .B(n987), .Y(n7744) );
ADDFHX2TS U823 ( .A(n5072), .B(n5071), .CI(n5070), .CO(n5163), .S(n5068) );
INVX1TS U824 ( .A(n7775), .Y(n866) );
CLKINVX1TS U825 ( .A(n7479), .Y(n7068) );
NOR2X1TS U826 ( .A(n7266), .B(n7778), .Y(n816) );
NOR2X2TS U827 ( .A(n7006), .B(n7005), .Y(n7039) );
ADDFHX1TS U828 ( .A(n6565), .B(n6564), .CI(n6563), .CO(n6678), .S(n6664) );
ADDFHX1TS U829 ( .A(n6203), .B(n6202), .CI(n6201), .CO(n6254), .S(n6222) );
ADDFHX1TS U830 ( .A(n4359), .B(n4358), .CI(n4357), .CO(n4497), .S(n4432) );
ADDFHX1TS U831 ( .A(n5379), .B(n5378), .CI(n5377), .CO(n5475), .S(n5359) );
ADDFHX1TS U832 ( .A(n5506), .B(n5505), .CI(n5504), .CO(n5630), .S(n5490) );
ADDFHX2TS U833 ( .A(n1024), .B(n1023), .CI(n1022), .CO(n1449), .S(n1075) );
ADDFHX1TS U834 ( .A(n1560), .B(n1559), .CI(n1558), .CO(n1767), .S(n1561) );
ADDFHX1TS U835 ( .A(n692), .B(n691), .CI(n690), .CO(n700), .S(n872) );
XOR2X1TS U836 ( .A(n3063), .B(n3064), .Y(n2944) );
ADDFX1TS U837 ( .A(n1981), .B(n1980), .CI(n1979), .CO(n2008), .S(n1976) );
AO21X1TS U838 ( .A0(n6770), .A1(n6769), .B0(n6768), .Y(n6879) );
AO21X1TS U839 ( .A0(n5235), .A1(n5293), .B0(n5292), .Y(n5374) );
CLKINVX1TS U840 ( .A(n7063), .Y(n7053) );
INVX1TS U841 ( .A(n5367), .Y(n5260) );
INVX1TS U842 ( .A(n4245), .Y(n4211) );
XNOR2X2TS U843 ( .A(n1860), .B(Data_B_i[37]), .Y(n4470) );
NOR2X1TS U844 ( .A(n7016), .B(n6731), .Y(n6885) );
NOR2X1TS U845 ( .A(n7016), .B(n6615), .Y(n6681) );
NOR2X1TS U846 ( .A(n6062), .B(n5939), .Y(n6059) );
NOR2X1TS U847 ( .A(n6062), .B(n5863), .Y(n5934) );
NOR2X1TS U848 ( .A(n7091), .B(n6377), .Y(n6464) );
NOR2X1TS U849 ( .A(n7091), .B(n6307), .Y(n6419) );
NOR2X1TS U850 ( .A(n7091), .B(n7090), .Y(n7095) );
INVX12TS U851 ( .A(Data_A_i[29]), .Y(n6002) );
INVX4TS U852 ( .A(Data_B_i[36]), .Y(n6377) );
XOR2X1TS U853 ( .A(n7636), .B(n7635), .Y(N47) );
XOR2X1TS U854 ( .A(n7639), .B(n7638), .Y(N44) );
XOR2X1TS U855 ( .A(n7650), .B(n7649), .Y(N46) );
XOR2X1TS U856 ( .A(n7673), .B(n7672), .Y(N41) );
XOR2X1TS U857 ( .A(n7660), .B(n7659), .Y(N45) );
XOR2X1TS U858 ( .A(n7682), .B(n7681), .Y(N42) );
XOR2X1TS U859 ( .A(n7667), .B(n7666), .Y(N43) );
XOR2X1TS U860 ( .A(n7712), .B(n7711), .Y(N32) );
INVX1TS U861 ( .A(n7466), .Y(n7469) );
NOR2X1TS U862 ( .A(n7448), .B(n6873), .Y(n6875) );
INVX1TS U863 ( .A(n7622), .Y(n7625) );
XOR2X1TS U864 ( .A(n7687), .B(n7686), .Y(N34) );
NOR2X1TS U865 ( .A(n7448), .B(n7451), .Y(n7454) );
INVX1TS U866 ( .A(n7467), .Y(n7468) );
INVX1TS U867 ( .A(n7064), .Y(n7086) );
XOR2X1TS U868 ( .A(n7706), .B(n7705), .Y(N31) );
INVX1TS U869 ( .A(n7475), .Y(n7478) );
INVX1TS U870 ( .A(n7623), .Y(n7624) );
XOR2X1TS U871 ( .A(n7697), .B(n7696), .Y(N33) );
OAI21X1TS U872 ( .A0(n7687), .A1(n7193), .B0(n7192), .Y(n7198) );
XOR2X1TS U873 ( .A(n7718), .B(n7717), .Y(N30) );
OAI21X1TS U874 ( .A0(n7687), .A1(n7371), .B0(n7370), .Y(n7375) );
NOR2X1TS U875 ( .A(n7558), .B(n7530), .Y(n7532) );
NOR2X1TS U876 ( .A(n7558), .B(n7521), .Y(n7523) );
INVX1TS U877 ( .A(n7482), .Y(n7485) );
INVX1TS U878 ( .A(n7122), .Y(n7118) );
INVX1TS U879 ( .A(n7440), .Y(n7441) );
INVX1TS U880 ( .A(n6954), .Y(n6950) );
NOR2X1TS U881 ( .A(n7429), .B(n7432), .Y(n7435) );
INVX1TS U882 ( .A(n7414), .Y(n7410) );
NOR2X1TS U883 ( .A(n7439), .B(n6932), .Y(n6934) );
NOR2X1TS U884 ( .A(n7103), .B(n7303), .Y(n7109) );
NOR2X1TS U885 ( .A(n7599), .B(n12), .Y(n7602) );
XOR2X1TS U886 ( .A(n7747), .B(n7746), .Y(N23) );
XOR2X1TS U887 ( .A(n7722), .B(n7721), .Y(N25) );
XOR2X1TS U888 ( .A(n7739), .B(n7738), .Y(N22) );
XOR2X1TS U889 ( .A(n7731), .B(n7730), .Y(N24) );
OAI21X1TS U890 ( .A0(n7722), .A1(n7215), .B0(n7214), .Y(n7219) );
NAND2XLTS U891 ( .A(n7376), .B(n7345), .Y(n7326) );
INVX1TS U892 ( .A(n7619), .Y(n12) );
NOR2X1TS U893 ( .A(n7688), .B(n7708), .Y(n7692) );
OAI21X1TS U894 ( .A0(n7145), .A1(n7144), .B0(n7143), .Y(n7146) );
INVX1TS U895 ( .A(n7142), .Y(n7035) );
INVX1TS U896 ( .A(n7145), .Y(n7034) );
OAI21X1TS U897 ( .A0(n7397), .A1(n7396), .B0(n7395), .Y(n7398) );
NOR2X1TS U898 ( .A(n7394), .B(n7396), .Y(n7399) );
OAI21X1TS U899 ( .A0(n7751), .A1(n7238), .B0(n7237), .Y(n7241) );
XOR2X1TS U900 ( .A(n7757), .B(n7756), .Y(N16) );
NOR2X1TS U901 ( .A(n7651), .B(n7643), .Y(n7645) );
XOR2X1TS U902 ( .A(n7766), .B(n7765), .Y(N15) );
OAI21X1TS U903 ( .A0(n7179), .A1(n7382), .B0(n7383), .Y(n7180) );
XOR2X1TS U904 ( .A(n7751), .B(n7750), .Y(N17) );
INVX1TS U905 ( .A(n7365), .Y(n7366) );
INVX1TS U906 ( .A(n7378), .Y(n7175) );
INVX1TS U907 ( .A(n7529), .Y(n31) );
INVX1TS U908 ( .A(n7698), .Y(n7701) );
INVX1TS U909 ( .A(n7327), .Y(n7329) );
INVX1TS U910 ( .A(n7323), .Y(n7345) );
XOR2X1TS U911 ( .A(n7777), .B(n7776), .Y(N11) );
XOR2X1TS U912 ( .A(n7771), .B(n7770), .Y(N12) );
INVX1TS U913 ( .A(n7199), .Y(n7202) );
INVX1TS U914 ( .A(n7674), .Y(n7677) );
NAND2XLTS U915 ( .A(n7199), .B(n7204), .Y(n7193) );
INVX2TS U916 ( .A(n7693), .Y(n7695) );
INVX1TS U917 ( .A(n7459), .Y(n7460) );
CLKINVX2TS U918 ( .A(n7348), .Y(n7461) );
INVX1TS U919 ( .A(n7587), .Y(n7588) );
XOR2X1TS U920 ( .A(n7787), .B(n7786), .Y(N7) );
INVX1TS U921 ( .A(n7262), .Y(n7774) );
OAI21X1TS U922 ( .A0(n7782), .A1(n7778), .B0(n7779), .Y(n7270) );
XOR2X1TS U923 ( .A(n7782), .B(n7781), .Y(N8) );
NOR2X1TS U924 ( .A(n7723), .B(n7743), .Y(n7726) );
AND2X2TS U925 ( .A(n7300), .B(n7299), .Y(n7301) );
NOR2X4TS U926 ( .A(n1799), .B(n1800), .Y(n7194) );
INVX1TS U927 ( .A(n7632), .Y(n7634) );
INVX1TS U928 ( .A(n7683), .Y(n7684) );
AND2X2TS U929 ( .A(n7305), .B(n7304), .Y(n7306) );
INVX2TS U930 ( .A(n7652), .Y(n2451) );
INVX1TS U931 ( .A(n7221), .Y(n7211) );
INVX1TS U932 ( .A(n7646), .Y(n7648) );
NAND2X2TS U933 ( .A(n1333), .B(n1332), .Y(n7703) );
NOR2X6TS U934 ( .A(n5017), .B(n5018), .Y(n7610) );
INVX2TS U935 ( .A(n7431), .Y(n6823) );
INVX1TS U936 ( .A(n7303), .Y(n7305) );
INVX1TS U937 ( .A(n7242), .Y(n7236) );
AOI21X2TS U938 ( .A0(n18), .A1(n6829), .B0(n6828), .Y(n6830) );
NOR2X2TS U939 ( .A(n1794), .B(n1793), .Y(n7683) );
INVX1TS U940 ( .A(n7416), .Y(n7411) );
INVX1TS U941 ( .A(n6921), .Y(n6923) );
INVX1TS U942 ( .A(n6960), .Y(n6962) );
AND2X2TS U943 ( .A(n7289), .B(n7288), .Y(n7290) );
INVX1TS U944 ( .A(n6956), .Y(n6951) );
INVX1TS U945 ( .A(n7272), .Y(n7784) );
CLKINVX2TS U946 ( .A(n7732), .Y(n7733) );
INVX1TS U947 ( .A(n7231), .Y(n7734) );
INVX1TS U948 ( .A(n7735), .Y(n7737) );
AND2X2TS U949 ( .A(n6976), .B(n6975), .Y(n6977) );
INVX1TS U950 ( .A(n3924), .Y(n3920) );
INVX1TS U951 ( .A(n7754), .Y(n899) );
INVX1TS U952 ( .A(n7767), .Y(n7769) );
INVX1TS U953 ( .A(n7762), .Y(n7764) );
INVX1TS U954 ( .A(n7254), .Y(n7760) );
AOI21X2TS U955 ( .A0(n20), .A1(n7772), .B0(n866), .Y(n867) );
INVX1TS U956 ( .A(n7171), .Y(n6848) );
INVX1TS U957 ( .A(n6904), .Y(n6906) );
OAI21X2TS U958 ( .A0(n3830), .A1(n3831), .B0(n3828), .Y(n3829) );
INVX1TS U959 ( .A(n7287), .Y(n7289) );
ADDFHX2TS U960 ( .A(n2154), .B(n2153), .CI(n2152), .CO(n2310), .S(n2223) );
OAI21X1TS U961 ( .A0(n7791), .A1(n7788), .B0(n7789), .Y(n7275) );
OAI21X2TS U962 ( .A0(n5001), .A1(n4999), .B0(n5000), .Y(n4168) );
XOR2X1TS U963 ( .A(n7792), .B(n7791), .Y(N4) );
ADDFHX2TS U964 ( .A(n5358), .B(n5357), .CI(n5356), .CO(n5461), .S(n5400) );
AND2X2TS U965 ( .A(n7480), .B(n7479), .Y(n14) );
INVX3TS U966 ( .A(n4881), .Y(n6) );
INVX1TS U967 ( .A(n7065), .Y(n7066) );
ADDFHX2TS U968 ( .A(n5780), .B(n5779), .CI(n5778), .CO(n5825), .S(n5763) );
ADDFX1TS U969 ( .A(n5486), .B(n5485), .CI(n5484), .CO(n5561), .S(n5406) );
INVX1TS U970 ( .A(n7778), .Y(n7780) );
INVX1TS U971 ( .A(n7266), .Y(n7268) );
INVX1TS U972 ( .A(n7455), .Y(n7074) );
ADDFHX2TS U973 ( .A(n5490), .B(n5489), .CI(n5488), .CO(n5592), .S(n5563) );
ADDFHX2TS U974 ( .A(n4161), .B(n4160), .CI(n4159), .CO(n4156), .S(n4999) );
OAI21X1TS U975 ( .A0(n7266), .A1(n7779), .B0(n7267), .Y(n815) );
INVX1TS U976 ( .A(n7788), .Y(n7790) );
OR2X2TS U977 ( .A(n7073), .B(n7072), .Y(n7456) );
ADDFHX2TS U978 ( .A(n4862), .B(n4861), .CI(n4860), .CO(n4874), .S(n4869) );
ADDFHX2TS U979 ( .A(n5480), .B(n5479), .CI(n5478), .CO(n5488), .S(n5481) );
ADDFX1TS U980 ( .A(n297), .B(n296), .CI(n295), .CO(n1292), .S(n298) );
OR2X2TS U981 ( .A(n7026), .B(n7025), .Y(n7067) );
ADDFHX2TS U982 ( .A(n5566), .B(n5565), .CI(n5564), .CO(n5643), .S(n5633) );
ADDFHX2TS U983 ( .A(n5677), .B(n5676), .CI(n5675), .CO(n5780), .S(n5644) );
INVX1TS U984 ( .A(n7274), .Y(n803) );
ADDFX1TS U985 ( .A(n6298), .B(n6297), .CI(n6296), .CO(n6332), .S(n6295) );
INVX1TS U986 ( .A(n7277), .Y(n784) );
ADDFX1TS U987 ( .A(n6323), .B(n6322), .CI(n6321), .CO(n6330), .S(n6326) );
ADDFX1TS U988 ( .A(n1451), .B(n1450), .CI(n1449), .CO(n1607), .S(n1612) );
NAND3X1TS U989 ( .A(n1090), .B(n1089), .C(n1088), .Y(n1252) );
ADDFX1TS U990 ( .A(n1548), .B(n1547), .CI(n1546), .CO(n1563), .S(n1427) );
ADDFHX2TS U991 ( .A(n1374), .B(n1373), .CI(n1372), .CO(n1589), .S(n1587) );
XOR2X2TS U992 ( .A(n5202), .B(n5203), .Y(n5108) );
OR2X2TS U993 ( .A(n802), .B(n801), .Y(n23) );
OR2X2TS U994 ( .A(n7084), .B(n7083), .Y(n7161) );
ADDFX1TS U995 ( .A(n1765), .B(n1764), .CI(n1763), .CO(n2371), .S(n1772) );
OR2X2TS U996 ( .A(n783), .B(n782), .Y(n7278) );
ADDFX1TS U997 ( .A(n6279), .B(n6278), .CI(n6277), .CO(n6329), .S(n6322) );
OR2X2TS U998 ( .A(n7098), .B(n7097), .Y(n7100) );
NOR2X1TS U999 ( .A(n794), .B(n793), .Y(n7788) );
NAND3X1TS U1000 ( .A(n4428), .B(n4427), .C(n4426), .Y(n4474) );
OR2X2TS U1001 ( .A(n805), .B(n804), .Y(n22) );
ADDFX1TS U1002 ( .A(n3953), .B(n3952), .CI(n3951), .CO(n4016), .S(n4060) );
ADDFX1TS U1003 ( .A(n2999), .B(n2998), .CI(n2997), .CO(n3130), .S(n3146) );
ADDFHX1TS U1004 ( .A(n6306), .B(n6305), .CI(n6304), .CO(n6334), .S(n6298) );
ADDFX1TS U1005 ( .A(n613), .B(n612), .CI(n611), .CO(n630), .S(n655) );
ADDFHX2TS U1006 ( .A(n3190), .B(n3189), .CI(n3188), .CO(n4730), .S(n3186) );
ADDFHX1TS U1007 ( .A(n1934), .B(n1933), .CI(n1932), .CO(n2002), .S(n2144) );
ADDFHX1TS U1008 ( .A(n5609), .B(n5608), .CI(n5607), .CO(n5670), .S(n5615) );
ADDFX1TS U1009 ( .A(n1442), .B(n1441), .CI(n1440), .CO(n1594), .S(n1583) );
ADDFHX2TS U1010 ( .A(n3262), .B(n3261), .CI(n3260), .CO(n4726), .S(n3227) );
ADDFHX1TS U1011 ( .A(n854), .B(n853), .CI(n852), .CO(n885), .S(n855) );
ADDFX1TS U1012 ( .A(n3418), .B(n3417), .CI(n3416), .CO(n3489), .S(n3490) );
ADDFHX1TS U1013 ( .A(n5725), .B(n5724), .CI(n5723), .CO(n5792), .S(n5711) );
AO21X1TS U1014 ( .A0(n152), .A1(n7281), .B0(n781), .Y(n151) );
ADDFX1TS U1015 ( .A(n3626), .B(n3625), .CI(n3624), .CO(n3869), .S(n3564) );
ADDFHX1TS U1016 ( .A(n833), .B(n832), .CI(n831), .CO(n877), .S(n853) );
ADDFHX1TS U1017 ( .A(n357), .B(n356), .CI(n355), .CO(n408), .S(n411) );
ADDFHX1TS U1018 ( .A(n4387), .B(n4386), .CI(n4385), .CO(n4509), .S(n4383) );
INVX1TS U1019 ( .A(n1249), .Y(n1245) );
ADDFX1TS U1020 ( .A(n1173), .B(n1172), .CI(n1171), .CO(n1445), .S(n1170) );
ADDFHX1TS U1021 ( .A(n2825), .B(n2824), .CI(n2823), .CO(n3141), .S(n2794) );
NAND3X1TS U1022 ( .A(n3067), .B(n3066), .C(n3065), .Y(n3232) );
XOR2X1TS U1023 ( .A(n3062), .B(n2944), .Y(n3019) );
ADDFX1TS U1024 ( .A(n5804), .B(n5803), .CI(n5802), .CO(n5872), .S(n5806) );
ADDFHX1TS U1025 ( .A(n1531), .B(n1530), .CI(n1529), .CO(n1715), .S(n1543) );
ADDFHX1TS U1026 ( .A(n2868), .B(n2867), .CI(n2866), .CO(n3101), .S(n3106) );
ADDFX1TS U1027 ( .A(n525), .B(n524), .CI(n523), .CO(n943), .S(n522) );
ADDFX1TS U1028 ( .A(n620), .B(n619), .CI(n618), .CO(n611), .S(n658) );
ADDFX1TS U1029 ( .A(n3226), .B(n3225), .CI(n3224), .CO(n4669), .S(n3260) );
INVX1TS U1030 ( .A(n7280), .Y(n781) );
INVX1TS U1031 ( .A(mult_x_1_n1532), .Y(n7281) );
AO21X1TS U1032 ( .A0(n3356), .A1(n112), .B0(n3523), .Y(n3870) );
ADDFHX1TS U1033 ( .A(n5212), .B(n5211), .CI(n5210), .CO(n5303), .S(n5208) );
AO21X1TS U1034 ( .A0(n71), .A1(n5437), .B0(n5436), .Y(n5531) );
NAND2XLTS U1035 ( .A(n3064), .B(n3062), .Y(n3067) );
NAND2XLTS U1036 ( .A(n3063), .B(n3062), .Y(n3066) );
NAND2XLTS U1037 ( .A(n3064), .B(n3063), .Y(n3065) );
ADDFHX1TS U1038 ( .A(n2042), .B(n2041), .CI(n2040), .CO(n2293), .S(n2048) );
ADDFHX1TS U1039 ( .A(n1895), .B(n1894), .CI(n1893), .CO(n2336), .S(n2050) );
ADDFX1TS U1040 ( .A(n4075), .B(n4074), .CI(n4073), .CO(n4023), .S(n4854) );
OR2X1TS U1041 ( .A(n780), .B(n779), .Y(n152) );
INVX4TS U1042 ( .A(n1506), .Y(n126) );
OR2X1TS U1043 ( .A(n7794), .B(n7793), .Y(n7796) );
ADDFHX1TS U1044 ( .A(n6264), .B(n6263), .CI(n6262), .CO(n6304), .S(n6266) );
NAND2XLTS U1045 ( .A(n4425), .B(n4423), .Y(n4428) );
INVX1TS U1046 ( .A(n6744), .Y(n6715) );
INVX1TS U1047 ( .A(n6885), .Y(n6765) );
INVX1TS U1048 ( .A(n6614), .Y(n6573) );
INVX1TS U1049 ( .A(n5935), .Y(n5867) );
INVX1TS U1050 ( .A(n2898), .Y(n2900) );
INVX1TS U1051 ( .A(n6681), .Y(n6650) );
NAND2X4TS U1052 ( .A(n159), .B(n1020), .Y(n2502) );
INVX1TS U1053 ( .A(n5113), .Y(n5116) );
INVX1TS U1054 ( .A(n7014), .Y(n6985) );
INVX1TS U1055 ( .A(n4226), .Y(n4227) );
BUFX3TS U1056 ( .A(n3275), .Y(n842) );
NOR2X1TS U1057 ( .A(n5721), .B(n5142), .Y(n5229) );
CLKINVX2TS U1058 ( .A(n3758), .Y(n3978) );
INVX1TS U1059 ( .A(n6303), .Y(n6264) );
NOR2X1TS U1060 ( .A(n5721), .B(n5516), .Y(n5663) );
INVX1TS U1061 ( .A(n6060), .Y(n5952) );
NOR2X1TS U1062 ( .A(n5721), .B(n5253), .Y(n5366) );
NOR2X1TS U1063 ( .A(n5721), .B(n5664), .Y(n5795) );
INVX1TS U1064 ( .A(n7096), .Y(n7089) );
NOR2X1TS U1065 ( .A(n7016), .B(n6886), .Y(n7014) );
NOR2X1TS U1066 ( .A(n7016), .B(n6760), .Y(n6884) );
NOR2X1TS U1067 ( .A(n6062), .B(n3589), .Y(n3843) );
NOR2X1TS U1068 ( .A(n7016), .B(n6682), .Y(n6744) );
INVX1TS U1069 ( .A(n4473), .Y(n4425) );
NOR2X1TS U1070 ( .A(n7092), .B(n78), .Y(n7096) );
NOR2X1TS U1071 ( .A(n7092), .B(n7047), .Y(n7062) );
NOR2X1TS U1072 ( .A(n7091), .B(n6465), .Y(n6553) );
NOR2X1TS U1073 ( .A(n7091), .B(n75), .Y(n6303) );
NOR2X1TS U1074 ( .A(n7091), .B(n6346), .Y(n6418) );
NOR2X1TS U1075 ( .A(n5938), .B(n4419), .Y(n4472) );
NOR2X1TS U1076 ( .A(n5938), .B(n4203), .Y(n4244) );
NOR2X1TS U1077 ( .A(n5938), .B(n4050), .Y(n4119) );
BUFX8TS U1078 ( .A(Data_A_i[53]), .Y(n6586) );
INVX12TS U1079 ( .A(Data_A_i[23]), .Y(n5584) );
ADDFHX4TS U1080 ( .A(n2391), .B(n2390), .CI(n2389), .CO(n2408), .S(n2410) );
ADDFHX4TS U1081 ( .A(n4992), .B(n4991), .CI(n4990), .CO(n4998), .S(n5004) );
ADDFHX4TS U1082 ( .A(n4650), .B(n4649), .CI(n4648), .CO(n4953), .S(n4962) );
ADDFHX4TS U1083 ( .A(n4187), .B(n4186), .CI(n4185), .CO(n5039), .S(n5038) );
OAI22X1TS U1084 ( .A0(n73), .A1(n1970), .B0(n137), .B1(n1969), .Y(n2117) );
AO21X1TS U1085 ( .A0(n2633), .A1(n5893), .B0(n5892), .Y(n5976) );
AOI21X4TS U1086 ( .A0(n7406), .A1(n6815), .B0(n6814), .Y(n6816) );
INVX4TS U1087 ( .A(n5892), .Y(n4076) );
ADDFHX2TS U1088 ( .A(n1148), .B(n1147), .CI(n1146), .CO(n1588), .S(n1076) );
BUFX6TS U1089 ( .A(n56), .Y(n1470) );
OAI21X4TS U1090 ( .A0(n7313), .A1(n7685), .B0(n7314), .Y(n7200) );
NAND2X2TS U1091 ( .A(n1796), .B(n1795), .Y(n7314) );
ADDFHX2TS U1092 ( .A(n1716), .B(n1715), .CI(n1714), .CO(n1740), .S(n1710) );
INVX4TS U1093 ( .A(n7047), .Y(n6007) );
ADDFHX2TS U1094 ( .A(n2855), .B(n2854), .CI(n2853), .CO(n3320), .S(n2453) );
INVX2TS U1095 ( .A(n6588), .Y(n5187) );
ADDFHX2TS U1096 ( .A(n2947), .B(n2946), .CI(n2945), .CO(n3157), .S(n3161) );
ADDFHX2TS U1097 ( .A(n4668), .B(n4667), .CI(n4666), .CO(n4146), .S(n4945) );
INVX4TS U1098 ( .A(n6540), .Y(n5082) );
OAI22X2TS U1099 ( .A0(n4571), .A1(n1518), .B0(n1517), .B1(n1648), .Y(n1681)
);
ADDFHX2TS U1100 ( .A(n2683), .B(n2682), .CI(n2681), .CO(n2765), .S(n2740) );
ADDFHX2TS U1101 ( .A(n2148), .B(n2147), .CI(n2146), .CO(n2154), .S(n2225) );
ADDFHX4TS U1102 ( .A(n4494), .B(n4493), .CI(n4492), .CO(n5069), .S(n4490) );
ADDFX2TS U1103 ( .A(n3981), .B(n3980), .CI(n3979), .CO(n4058), .S(n4026) );
ADDFHX2TS U1104 ( .A(n4890), .B(n4889), .CI(n4888), .CO(n4832), .S(n4916) );
ADDFHX2TS U1105 ( .A(n1612), .B(n1611), .CI(n1610), .CO(n1625), .S(n1633) );
OAI22X2TS U1106 ( .A0(n6184), .A1(n3742), .B0(n6251), .B1(n3457), .Y(n3708)
);
OAI22X2TS U1107 ( .A0(n3754), .A1(n4034), .B0(n7), .B1(n1816), .Y(n3977) );
ADDFX2TS U1108 ( .A(n3944), .B(n3943), .CI(n3942), .CO(n3953), .S(n4664) );
XNOR2X1TS U1109 ( .A(n6066), .B(n4335), .Y(n4421) );
ADDFHX2TS U1110 ( .A(n1921), .B(n1920), .CI(n1919), .CO(n2024), .S(n2148) );
INVX4TS U1111 ( .A(n6182), .Y(n57) );
ADDFHX4TS U1112 ( .A(n4795), .B(n4794), .CI(n4793), .CO(n4847), .S(n4833) );
OR2X4TS U1113 ( .A(n4684), .B(n582), .Y(n10) );
OR2X4TS U1114 ( .A(n625), .B(n549), .Y(n11) );
NAND2X4TS U1115 ( .A(n10), .B(n11), .Y(n579) );
XOR2X2TS U1116 ( .A(Data_A_i[12]), .B(Data_A_i[13]), .Y(n154) );
ADDFHX2TS U1117 ( .A(n4911), .B(n4910), .CI(n4909), .CO(n4884), .S(n4938) );
ADDFHX2TS U1118 ( .A(n4264), .B(n4263), .CI(n4262), .CO(n4357), .S(n4237) );
OAI22X1TS U1119 ( .A0(n5451), .A1(n4205), .B0(n4204), .B1(n4334), .Y(n4243)
);
INVX4TS U1120 ( .A(n5755), .Y(n115) );
NOR2X2TS U1121 ( .A(n7040), .B(n7070), .Y(n7447) );
NAND3X1TS U1122 ( .A(n3248), .B(n3247), .C(n3246), .Y(n4807) );
OAI22X2TS U1123 ( .A0(n3618), .A1(n3389), .B0(n125), .B1(n3376), .Y(n3431)
);
CLKINVX1TS U1124 ( .A(n7124), .Y(n7119) );
OAI22X1TS U1125 ( .A0(n5717), .A1(n3410), .B0(n3026), .B1(n3409), .Y(n3551)
);
OAI22X1TS U1126 ( .A0(n149), .A1(n3763), .B0(n5293), .B1(n3736), .Y(n3947)
);
OAI22X1TS U1127 ( .A0(n4277), .A1(n3482), .B0(n48), .B1(n3559), .Y(n3439) );
ADDFHX2TS U1128 ( .A(n4056), .B(n4055), .CI(n4054), .CO(n4047), .S(n4114) );
OAI22X1TS U1129 ( .A0(n55), .A1(n4086), .B0(n4740), .B1(n3774), .Y(n4054) );
BUFX4TS U1130 ( .A(n6065), .Y(n6125) );
NOR2X1TS U1131 ( .A(n6833), .B(n6832), .Y(n6504) );
CLKINVX12TS U1132 ( .A(n4258), .Y(n65) );
OAI22X2TS U1133 ( .A0(n5621), .A1(n1367), .B0(n59), .B1(n1424), .Y(n1403) );
ADDFHX4TS U1134 ( .A(n2229), .B(n2228), .CI(n2227), .CO(n2376), .S(n2381) );
BUFX3TS U1135 ( .A(n2502), .Y(n646) );
XNOR2X1TS U1136 ( .A(n5892), .B(n6061), .Y(n4077) );
INVX4TS U1137 ( .A(Data_A_i[27]), .Y(n5892) );
ADDFHX2TS U1138 ( .A(n2924), .B(n2923), .CI(n2922), .CO(n3148), .S(n2945) );
NOR2X4TS U1139 ( .A(n6803), .B(n6802), .Y(n7128) );
ADDFHX2TS U1140 ( .A(n3130), .B(n3129), .CI(n3128), .CO(n3288), .S(n3017) );
OAI22X2TS U1141 ( .A0(n121), .A1(n1899), .B0(n59), .B1(n2285), .Y(n2323) );
ADDFHX2TS U1142 ( .A(n1743), .B(n1742), .CI(n1741), .CO(n2397), .S(n1739) );
OAI22X1TS U1143 ( .A0(n5494), .A1(n1725), .B0(n3405), .B1(n1724), .Y(n1759)
);
OAI22X1TS U1144 ( .A0(n2525), .A1(n1644), .B0(n2462), .B1(n2071), .Y(n2177)
);
ADDFHX2TS U1145 ( .A(n2385), .B(n2384), .CI(n2383), .CO(n2417), .S(n2401) );
ADDFHX2TS U1146 ( .A(n1746), .B(n1745), .CI(n1744), .CO(n2385), .S(n1771) );
ADDFHX4TS U1147 ( .A(n3094), .B(n3093), .CI(n3092), .CO(n3290), .S(n3120) );
OAI22X2TS U1148 ( .A0(n5103), .A1(n2925), .B0(n4518), .B1(n2940), .Y(n3008)
);
OAI22X2TS U1149 ( .A0(n2904), .A1(n1888), .B0(n51), .B1(n2348), .Y(n2338) );
ADDFHX2TS U1150 ( .A(n1078), .B(n1077), .CI(n1076), .CO(n1610), .S(n1257) );
OAI22X1TS U1151 ( .A0(n2521), .A1(n1040), .B0(n4746), .B1(n1026), .Y(n1044)
);
OAI21X1TS U1152 ( .A0(n7727), .A1(n7744), .B0(n7728), .Y(n991) );
BUFX4TS U1153 ( .A(n6399), .Y(n6709) );
ADDFHX2TS U1154 ( .A(n4025), .B(n4024), .CI(n4023), .CO(n4949), .S(n4659) );
OAI22X2TS U1155 ( .A0(n46), .A1(n3907), .B0(n6124), .B1(n4205), .Y(n4290) );
OAI2BB1X4TS U1156 ( .A0N(n4986), .A1N(n4985), .B0(n4984), .Y(n5007) );
ADDFHX2TS U1157 ( .A(n4789), .B(n4788), .CI(n4787), .CO(n4831), .S(n4818) );
AOI21X4TS U1158 ( .A0(n7153), .A1(n7116), .B0(n7115), .Y(n7125) );
AOI21X2TS U1159 ( .A0(n34), .A1(n7127), .B0(n7126), .Y(n7132) );
OAI22X2TS U1160 ( .A0(n1140), .A1(n290), .B0(n1138), .B1(n1139), .Y(n1227)
);
CLKINVX6TS U1161 ( .A(n3959), .Y(n4564) );
NAND2X8TS U1162 ( .A(n198), .B(n3361), .Y(n3959) );
OAI22X2TS U1163 ( .A0(n104), .A1(n3255), .B0(n4562), .B1(n4563), .Y(n4696)
);
ADDFHX4TS U1164 ( .A(n4834), .B(n4833), .CI(n4832), .CO(n4845), .S(n4910) );
NAND2X2TS U1165 ( .A(n161), .B(n2895), .Y(n5756) );
NOR2X8TS U1166 ( .A(n3331), .B(n3332), .Y(n7327) );
XNOR2X1TS U1167 ( .A(n3986), .B(n2353), .Y(n2626) );
OAI22X2TS U1168 ( .A0(n145), .A1(n2354), .B0(n4204), .B1(n2626), .Y(n2476)
);
CLKINVX6TS U1169 ( .A(n6065), .Y(n6014) );
NOR2X8TS U1170 ( .A(n7105), .B(n6817), .Y(n7055) );
BUFX3TS U1171 ( .A(n6365), .Y(n13) );
NAND2X4TS U1172 ( .A(n3045), .B(n3047), .Y(n6365) );
ADDFHX2TS U1173 ( .A(n3696), .B(n3695), .CI(n3694), .CO(n3680), .S(n3818) );
BUFX8TS U1174 ( .A(n3348), .Y(n4277) );
OAI22X1TS U1175 ( .A0(n2633), .A1(n2346), .B0(n4518), .B1(n2632), .Y(n2491)
);
NAND2BX1TS U1176 ( .AN(n2864), .B(n106), .Y(n1072) );
CLKINVX1TS U1177 ( .A(n7080), .Y(n6927) );
AOI21X2TS U1178 ( .A0(n7080), .A1(n6939), .B0(n6938), .Y(n6940) );
ADDFHX4TS U1179 ( .A(n2127), .B(n2126), .CI(n2125), .CO(n2312), .S(n2219) );
INVX6TS U1180 ( .A(n86), .Y(n87) );
OAI22X2TS U1181 ( .A0(n2638), .A1(n2553), .B0(n7), .B1(n2827), .Y(n2773) );
OAI22X2TS U1182 ( .A0(n145), .A1(n1388), .B0(n90), .B1(n1508), .Y(n1419) );
NAND2X4TS U1183 ( .A(n156), .B(n3615), .Y(n3388) );
BUFX8TS U1184 ( .A(n3388), .Y(n5438) );
OAI22X1TS U1185 ( .A0(n5980), .A1(n3932), .B0(n3933), .B1(n3732), .Y(n3963)
);
ADDFHX2TS U1186 ( .A(n6100), .B(n6099), .CI(n6098), .CO(n6172), .S(n6101) );
XNOR2X1TS U1187 ( .A(n5449), .B(Data_B_i[53]), .Y(n6064) );
ADDFHX4TS U1188 ( .A(n1627), .B(n1626), .CI(n1625), .CO(n1617), .S(n1628) );
ADDFHX2TS U1189 ( .A(n1609), .B(n1608), .CI(n1607), .CO(n1601), .S(n1626) );
NAND2X4TS U1190 ( .A(n1754), .B(n3346), .Y(n5431) );
XOR2X2TS U1191 ( .A(Data_A_i[38]), .B(Data_A_i[39]), .Y(n1754) );
ADDFHX2TS U1192 ( .A(n3715), .B(n3714), .CI(n3713), .CO(n3699), .S(n3816) );
ADDFHX2TS U1193 ( .A(n4039), .B(n4038), .CI(n4037), .CO(n4013), .S(n4667) );
OAI21X1TS U1194 ( .A0(n7559), .A1(n7551), .B0(n7550), .Y(n7552) );
OAI22X1TS U1195 ( .A0(n55), .A1(n3222), .B0(n4740), .B1(n4741), .Y(n4755) );
ADDFHX2TS U1196 ( .A(n1234), .B(n1233), .CI(n1232), .CO(n1194), .S(n1274) );
ADDFHX2TS U1197 ( .A(n6326), .B(n6325), .CI(n6324), .CO(n6824), .S(n6820) );
ADDFHX2TS U1198 ( .A(n6255), .B(n6254), .CI(n6253), .CO(n6325), .S(n6224) );
ADDFHX2TS U1199 ( .A(n3018), .B(n3017), .CI(n3016), .CO(n3280), .S(n3080) );
ADDFHX2TS U1200 ( .A(n3145), .B(n3144), .CI(n3143), .CO(n3018), .S(n3159) );
ADDFHX2TS U1201 ( .A(n2647), .B(n2646), .CI(n2645), .CO(n2689), .S(n2640) );
ADDFHX2TS U1202 ( .A(n6476), .B(n6475), .CI(n6474), .CO(n6671), .S(n6495) );
BUFX8TS U1203 ( .A(n3455), .Y(n726) );
INVX8TS U1204 ( .A(n3455), .Y(n1922) );
AO21X2TS U1205 ( .A0(n735), .A1(n177), .B0(n3455), .Y(n3639) );
ADDFHX4TS U1206 ( .A(n4623), .B(n4622), .CI(n4621), .CO(n4649), .S(n4646) );
NAND2X6TS U1207 ( .A(n1013), .B(n1014), .Y(n4532) );
ADDFHX2TS U1208 ( .A(n4786), .B(n4785), .CI(n4784), .CO(n4819), .S(n4672) );
OAI22X2TS U1209 ( .A0(n142), .A1(n4098), .B0(n7), .B1(n4034), .Y(n4106) );
ADDFHX4TS U1210 ( .A(n2953), .B(n2952), .CI(n2951), .CO(n3094), .S(n3155) );
XOR2X4TS U1211 ( .A(n3243), .B(n3029), .Y(n3258) );
OAI22X2TS U1212 ( .A0(n4135), .A1(n3472), .B0(n111), .B1(n3396), .Y(n3403)
);
ADDFHX2TS U1213 ( .A(n4104), .B(n4103), .CI(n4102), .CO(n4127), .S(n4625) );
ADDFHX2TS U1214 ( .A(n6596), .B(n6595), .CI(n6594), .CO(n6626), .S(n6677) );
AOI21X2TS U1215 ( .A0(n6849), .A1(n7172), .B0(n6848), .Y(n7283) );
OAI21X1TS U1216 ( .A0(n7283), .A1(n7287), .B0(n7288), .Y(n6852) );
NAND2X2TS U1217 ( .A(n6779), .B(n6778), .Y(n7136) );
ADDFHX2TS U1218 ( .A(n4105), .B(n4106), .CI(n4107), .CO(n4668), .S(n4624) );
NOR2X4TS U1219 ( .A(n7594), .B(n7569), .Y(n7577) );
BUFX8TS U1220 ( .A(n122), .Y(n6993) );
ADDFHX2TS U1221 ( .A(n4199), .B(n4198), .CI(n4197), .CO(n4238), .S(n4207) );
OAI22X2TS U1222 ( .A0(n71), .A1(n158), .B0(n125), .B1(n171), .Y(n164) );
ADDFHX2TS U1223 ( .A(n3811), .B(n3810), .CI(n3809), .CO(n4019), .S(n4148) );
OAI22X2TS U1224 ( .A0(n6252), .A1(n4711), .B0(n6251), .B1(n4111), .Y(n4616)
);
ADDFHX4TS U1225 ( .A(n4963), .B(n4962), .CI(n4961), .CO(n4982), .S(n4958) );
ADDFHX4TS U1226 ( .A(n1737), .B(n1736), .CI(n1735), .CO(n1738), .S(n1712) );
ADDFHX2TS U1227 ( .A(n1667), .B(n1666), .CI(n1665), .CO(n1773), .S(n1737) );
OAI21X4TS U1228 ( .A0(n7327), .A1(n7344), .B0(n7328), .Y(n7377) );
XNOR2X1TS U1229 ( .A(n4085), .B(n4082), .Y(n3774) );
XNOR2X1TS U1230 ( .A(n116), .B(n76), .Y(n4086) );
ADDFHX4TS U1231 ( .A(n1615), .B(n1614), .CI(n1613), .CO(n1599), .S(n1616) );
ADDFHX4TS U1232 ( .A(n1621), .B(n1620), .CI(n1619), .CO(n1614), .S(n1630) );
OAI22X1TS U1233 ( .A0(n4575), .A1(n1179), .B0(n3074), .B1(n1407), .Y(n1356)
);
OAI22X1TS U1234 ( .A0(n71), .A1(n1062), .B0(n1689), .B1(n1161), .Y(n1159) );
BUFX6TS U1235 ( .A(n1014), .Y(n5249) );
AOI21X2TS U1236 ( .A0(n992), .A1(n7740), .B0(n991), .Y(n993) );
ADDFHX2TS U1237 ( .A(n3644), .B(n3643), .CI(n3642), .CO(n3650), .S(n3698) );
ADDFHX2TS U1238 ( .A(n3008), .B(n3007), .CI(n3006), .CO(n3133), .S(n3147) );
AOI21X4TS U1239 ( .A0(n7167), .A1(n7166), .B0(n7165), .Y(n7483) );
OAI22X2TS U1240 ( .A0(n5894), .A1(n1128), .B0(n3074), .B1(n1039), .Y(n1119)
);
ADDFHX4TS U1241 ( .A(n3860), .B(n3859), .CI(n3858), .CO(n4346), .S(n3852) );
ADDFHX2TS U1242 ( .A(n3837), .B(n3836), .CI(n3835), .CO(n4343), .S(n3859) );
OAI22X2TS U1243 ( .A0(n8), .A1(n3424), .B0(n5517), .B1(n3621), .Y(n3380) );
BUFX3TS U1244 ( .A(n3388), .Y(n3760) );
ADDFHX2TS U1245 ( .A(n6222), .B(n6221), .CI(n6220), .CO(n6223), .S(n6170) );
OAI21X1TS U1246 ( .A0(n6913), .A1(n6912), .B0(n6911), .Y(n6914) );
NOR2X4TS U1247 ( .A(n7327), .B(n7323), .Y(n7378) );
ADDHX1TS U1248 ( .A(n2297), .B(n2296), .CO(n2671), .S(n2294) );
NOR2X4TS U1249 ( .A(n7693), .B(n7708), .Y(n1339) );
BUFX8TS U1250 ( .A(n5456), .Y(n4610) );
ADDFHX4TS U1251 ( .A(n4932), .B(n4931), .CI(n4930), .CO(n4937), .S(n4939) );
ADDFHX4TS U1252 ( .A(n4917), .B(n4916), .CI(n4915), .CO(n4923), .S(n4931) );
ADDFHX2TS U1253 ( .A(n4644), .B(n4643), .CI(n4642), .CO(n4031), .S(n4660) );
NAND2X2TS U1254 ( .A(n6853), .B(n7166), .Y(n6855) );
NOR2X1TS U1255 ( .A(n7482), .B(n7168), .Y(n7170) );
ADDFHX2TS U1256 ( .A(n1297), .B(n1296), .CI(n1295), .CO(n1310), .S(n1318) );
OAI21X1TS U1257 ( .A0(n7294), .A1(n7082), .B0(n7081), .Y(n7158) );
OAI21X2TS U1258 ( .A0(n6899), .A1(n6904), .B0(n6905), .Y(n7001) );
NOR2X4TS U1259 ( .A(n6778), .B(n6779), .Y(n6780) );
ADDFHX4TS U1260 ( .A(n5297), .B(n5296), .CI(n5295), .CO(n5399), .S(n5320) );
ADDFHX4TS U1261 ( .A(n5169), .B(n5168), .CI(n5167), .CO(n5297), .S(n5164) );
ADDFHX4TS U1262 ( .A(n4175), .B(n4174), .CI(n4173), .CO(n4187), .S(n5010) );
ADDFHX4TS U1263 ( .A(n4158), .B(n4157), .CI(n4156), .CO(n4181), .S(n4174) );
OAI22X2TS U1264 ( .A0(n4006), .A1(n3783), .B0(n3213), .B1(n3733), .Y(n3962)
);
ADDHX1TS U1265 ( .A(n1365), .B(n1364), .CO(n1414), .S(n1363) );
ADDFHX2TS U1266 ( .A(n267), .B(n266), .CI(n265), .CO(n1306), .S(n340) );
ADDFHX2TS U1267 ( .A(n264), .B(n263), .CI(n262), .CO(n267), .S(n346) );
ADDFHX2TS U1268 ( .A(n285), .B(n284), .CI(n283), .CO(n1294), .S(n265) );
OAI22X2TS U1269 ( .A0(n39), .A1(n1407), .B0(n3074), .B1(n1456), .Y(n1435) );
ADDFHX2TS U1270 ( .A(n2970), .B(n2969), .CI(n2968), .CO(n3052), .S(n2952) );
ADDFHX2TS U1271 ( .A(n3404), .B(n3403), .CI(n3402), .CO(n3519), .S(n3466) );
AOI21X2TS U1272 ( .A0(n6948), .A1(n6947), .B0(n6946), .Y(n6957) );
ADDFHX4TS U1273 ( .A(n2211), .B(n2210), .CI(n2209), .CO(n2217), .S(n2366) );
BUFX8TS U1274 ( .A(n5266), .Y(n4635) );
ADDFHX2TS U1275 ( .A(n2205), .B(n2204), .CI(n2203), .CO(n2213), .S(n2263) );
ADDFHX2TS U1276 ( .A(n5631), .B(n5630), .CI(n5629), .CO(n5706), .S(n5591) );
OAI21X1TS U1277 ( .A0(n7417), .A1(n7416), .B0(n7415), .Y(n7418) );
ADDFHX4TS U1278 ( .A(n5093), .B(n5092), .CI(n5091), .CO(n5165), .S(n5070) );
ADDFHX2TS U1279 ( .A(n4525), .B(n4524), .CI(n4523), .CO(n5092), .S(n4496) );
ADDFHX4TS U1280 ( .A(n3599), .B(n3598), .CI(n3597), .CO(n3855), .S(n3607) );
OAI22X2TS U1281 ( .A0(n4375), .A1(n3384), .B0(n52), .B1(n3352), .Y(n3613) );
NOR2BX4TS U1282 ( .AN(n1328), .B(n1327), .Y(n7713) );
ADDFHX4TS U1283 ( .A(n1575), .B(n1574), .CI(n1573), .CO(n1713), .S(n1577) );
ADDFHX2TS U1284 ( .A(n1486), .B(n1485), .CI(n1484), .CO(n1736), .S(n1574) );
ADDFHX2TS U1285 ( .A(n365), .B(n364), .CI(n363), .CO(n383), .S(n428) );
OAI22X2TS U1286 ( .A0(n69), .A1(n312), .B0(n125), .B1(n222), .Y(n309) );
ADDFHX4TS U1287 ( .A(n4551), .B(n4550), .CI(n4549), .CO(n5047), .S(n5044) );
OAI22X1TS U1288 ( .A0(n4684), .A1(n3473), .B0(n85), .B1(n3408), .Y(n3552) );
OAI21X2TS U1289 ( .A0(n6921), .A1(n6966), .B0(n6922), .Y(n7165) );
CLKINVX1TS U1290 ( .A(n7562), .Y(n7564) );
ADDFHX2TS U1291 ( .A(n3963), .B(n3962), .CI(n3961), .CO(n3789), .S(n4057) );
NOR2X2TS U1292 ( .A(n1007), .B(n7221), .Y(n1009) );
OAI21X2TS U1293 ( .A0(n4985), .A1(n4986), .B0(n4983), .Y(n4984) );
ADDFHX4TS U1294 ( .A(n4959), .B(n4958), .CI(n4957), .CO(n4983), .S(n4944) );
ADDFHX4TS U1295 ( .A(n1315), .B(n1314), .CI(n1313), .CO(n1329), .S(n1328) );
XOR2X4TS U1296 ( .A(Data_A_i[6]), .B(n1922), .Y(n176) );
OAI22X2TS U1297 ( .A0(n2110), .A1(n3237), .B0(n4714), .B1(n4715), .Y(n4752)
);
ADDFHX4TS U1298 ( .A(n2367), .B(n2366), .CI(n2365), .CO(n2267), .S(n2412) );
ADDFHX2TS U1299 ( .A(n2208), .B(n2207), .CI(n2206), .CO(n2226), .S(n2367) );
OAI22X1TS U1300 ( .A0(n1096), .A1(n729), .B0(n1390), .B1(n827), .Y(n821) );
NOR2X2TS U1301 ( .A(n814), .B(n813), .Y(n7266) );
OAI21X2TS U1302 ( .A0(n7262), .A1(n868), .B0(n867), .Y(n7256) );
ADDFHX2TS U1303 ( .A(n3543), .B(n3542), .CI(n3541), .CO(n3417), .S(n3643) );
OAI22X2TS U1304 ( .A0(n46), .A1(n3471), .B0(n91), .B1(n3423), .Y(n3542) );
AOI21X4TS U1305 ( .A0(n6823), .A1(n1), .B0(n6822), .Y(n6929) );
CLKINVX1TS U1306 ( .A(n7506), .Y(n7508) );
OAI22X2TS U1307 ( .A0(n96), .A1(n1479), .B0(n1706), .B1(n1646), .Y(n1718) );
ADDFHX2TS U1308 ( .A(n1566), .B(n1565), .CI(n1564), .CO(n1582), .S(n1585) );
ADDFHX2TS U1309 ( .A(n1270), .B(n1269), .CI(n1268), .CO(n1253), .S(n1290) );
ADDFHX2TS U1310 ( .A(n5126), .B(n5125), .CI(n5124), .CO(n5160), .S(n5071) );
ADDFHX2TS U1311 ( .A(n5078), .B(n5077), .CI(n5076), .CO(n5171), .S(n5126) );
ADDFHX2TS U1312 ( .A(n1439), .B(n1438), .CI(n1437), .CO(n1584), .S(n1586) );
NAND2X4TS U1313 ( .A(n1015), .B(n4391), .Y(n6065) );
OAI22X1TS U1314 ( .A0(n646), .A1(n482), .B0(n2507), .B1(n400), .Y(n928) );
OAI22X1TS U1315 ( .A0(n2967), .A1(n1056), .B0(n2781), .B1(n1177), .Y(n1151)
);
OAI22X1TS U1316 ( .A0(n110), .A1(n732), .B0(n1176), .B1(n823), .Y(n829) );
ADDFHX4TS U1317 ( .A(n3796), .B(n3795), .CI(n3794), .CO(n3827), .S(n4180) );
ADDFHX2TS U1318 ( .A(n3699), .B(n3698), .CI(n3697), .CO(n3796), .S(n3821) );
ADDFHX2TS U1319 ( .A(n1740), .B(n1739), .CI(n1738), .CO(n2421), .S(n1778) );
XOR2X2TS U1320 ( .A(Data_A_i[17]), .B(Data_A_i[16]), .Y(n175) );
ADDFHX4TS U1321 ( .A(n3082), .B(n3081), .CI(n3080), .CO(n3294), .S(n3175) );
ADDFHX2TS U1322 ( .A(n3124), .B(n3123), .CI(n3122), .CO(n3283), .S(n3081) );
NAND2X4TS U1323 ( .A(n207), .B(n208), .Y(n3754) );
XOR2X4TS U1324 ( .A(Data_A_i[5]), .B(Data_A_i[4]), .Y(n207) );
ADDFHX2TS U1325 ( .A(n5172), .B(n5171), .CI(n5170), .CO(n5296), .S(n5166) );
NOR2X8TS U1326 ( .A(n7551), .B(n5058), .Y(n5060) );
NOR2X4TS U1327 ( .A(n7533), .B(n7545), .Y(n5046) );
NOR2X4TS U1328 ( .A(n5044), .B(n5043), .Y(n7545) );
ADDFHX4TS U1329 ( .A(n2397), .B(n2396), .CI(n2395), .CO(n2424), .S(n2420) );
ADDFHX4TS U1330 ( .A(n1771), .B(n1770), .CI(n1769), .CO(n2396), .S(n1776) );
ADDFHX2TS U1331 ( .A(n5563), .B(n5562), .CI(n5561), .CO(n5635), .S(n5638) );
ADDFHX2TS U1332 ( .A(n5477), .B(n5476), .CI(n5475), .CO(n5489), .S(n5482) );
ADDFHX2TS U1333 ( .A(n2253), .B(n2252), .CI(n2251), .CO(n2237), .S(n2386) );
ADDFHX2TS U1334 ( .A(n2662), .B(n2660), .CI(n2661), .CO(n2682), .S(n2846) );
ADDFHX4TS U1335 ( .A(n2421), .B(n2420), .CI(n2419), .CO(n2427), .S(n2429) );
ADDFHX2TS U1336 ( .A(n1267), .B(n1266), .CI(n1265), .CO(n1291), .S(n1293) );
AOI21X4TS U1337 ( .A0(n7373), .A1(n7367), .B0(n1807), .Y(n1808) );
CLKINVX1TS U1338 ( .A(n7515), .Y(n7497) );
AOI21X2TS U1339 ( .A0(n7492), .A1(n5056), .B0(n5055), .Y(n5057) );
NOR2X1TS U1340 ( .A(n7512), .B(n7515), .Y(n7518) );
NAND2X4TS U1341 ( .A(n5056), .B(n7511), .Y(n5058) );
ADDFHX2TS U1342 ( .A(n3431), .B(n3430), .CI(n3429), .CO(n3610), .S(n3535) );
OAI22X2TS U1343 ( .A0(n4009), .A1(n3377), .B0(n6195), .B1(n3532), .Y(n3430)
);
OAI21X2TS U1344 ( .A0(n7184), .A1(n7383), .B0(n7185), .Y(n3337) );
ADDFHX2TS U1345 ( .A(n300), .B(n299), .CI(n298), .CO(n1305), .S(n345) );
ADDFHX2TS U1346 ( .A(n580), .B(n579), .CI(n578), .CO(n585), .S(n612) );
ADDFHX2TS U1347 ( .A(n1075), .B(n1074), .CI(n1073), .CO(n1611), .S(n1258) );
AOI21X4TS U1348 ( .A0(n7200), .A1(n1802), .B0(n1801), .Y(n7361) );
OAI22X1TS U1349 ( .A0(n1140), .A1(n1035), .B0(n3251), .B1(n1068), .Y(n1033)
);
XOR2X4TS U1350 ( .A(n5201), .B(n5108), .Y(n5168) );
ADDFHX2TS U1351 ( .A(n3283), .B(n3282), .CI(n3281), .CO(n4929), .S(n3297) );
NAND2X4TS U1352 ( .A(n5024), .B(n7616), .Y(n7574) );
ADDFHX4TS U1353 ( .A(n1588), .B(n1587), .CI(n1586), .CO(n1620), .S(n1624) );
NOR2X4TS U1354 ( .A(n7382), .B(n7184), .Y(n3338) );
NOR2X1TS U1355 ( .A(n7175), .B(n7382), .Y(n7181) );
NOR2X4TS U1356 ( .A(n3334), .B(n3333), .Y(n7382) );
ADDFHX2TS U1357 ( .A(n4969), .B(n4968), .CI(n4967), .CO(n4995), .S(n4980) );
ADDFHX2TS U1358 ( .A(n4146), .B(n4145), .CI(n4144), .CO(n4164), .S(n4968) );
ADDFHX4TS U1359 ( .A(n4659), .B(n4658), .CI(n4657), .CO(n4969), .S(n4965) );
NOR2X8TS U1360 ( .A(n5032), .B(n5031), .Y(n7580) );
ADDFHX2TS U1361 ( .A(n3978), .B(n3977), .CI(n3976), .CO(n3972), .S(n4027) );
ADDFHX4TS U1362 ( .A(n2268), .B(n2267), .CI(n2266), .CO(n2222), .S(n2407) );
NAND2X4TS U1363 ( .A(n1393), .B(n169), .Y(n3348) );
OAI22X2TS U1364 ( .A0(n4006), .A1(n2069), .B0(n1379), .B1(n2068), .Y(n2174)
);
XNOR2X1TS U1365 ( .A(n7481), .B(n14), .Y(N103) );
NOR2X4TS U1366 ( .A(n1796), .B(n1795), .Y(n7313) );
XNOR2X4TS U1367 ( .A(n6908), .B(n6907), .Y(N101) );
NAND2BX2TS U1368 ( .AN(n6903), .B(n6902), .Y(n6908) );
XOR2X1TS U1369 ( .A(n7424), .B(n7423), .Y(N85) );
XOR2X2TS U1370 ( .A(n7028), .B(n7027), .Y(N104) );
NOR2BX2TS U1371 ( .AN(n7008), .B(n7007), .Y(n7028) );
OAI21X1TS U1372 ( .A0(n7476), .A1(n7039), .B0(n7479), .Y(n7007) );
ADDFHX4TS U1373 ( .A(n5011), .B(n5010), .CI(n5009), .CO(n5037), .S(n5032) );
ADDFHX2TS U1374 ( .A(n1585), .B(n1584), .CI(n1583), .CO(n1602), .S(n1621) );
INVX16TS U1375 ( .A(Data_A_i[15]), .Y(n4398) );
CLKINVX1TS U1376 ( .A(n7627), .Y(n7629) );
NOR2XLTS U1377 ( .A(n7622), .B(n7627), .Y(n7579) );
ADDFHX2TS U1378 ( .A(n5474), .B(n5473), .CI(n5472), .CO(n5504), .S(n5476) );
ADDFHX4TS U1379 ( .A(n4929), .B(n4928), .CI(n4927), .CO(n4940), .S(n4934) );
ADDFHX2TS U1380 ( .A(n3295), .B(n3294), .CI(n3293), .CO(n4927), .S(n3301) );
NOR2X2TS U1381 ( .A(n7475), .B(n7039), .Y(n6997) );
NAND2X4TS U1382 ( .A(n7393), .B(n7402), .Y(n7029) );
ADDFHX2TS U1383 ( .A(n2118), .B(n2117), .CI(n2116), .CO(n2156), .S(n2231) );
INVX6TS U1384 ( .A(n72), .Y(n73) );
INVX4TS U1385 ( .A(n6705), .Y(n3926) );
BUFX4TS U1386 ( .A(n4322), .Y(n5894) );
OAI22X1TS U1387 ( .A0(n6252), .A1(n2505), .B0(n58), .B1(n2504), .Y(n2540) );
ADDFHX2TS U1388 ( .A(n2431), .B(n2430), .CI(n2429), .CO(n2432), .S(n1806) );
AOI21X2TS U1389 ( .A0(n7576), .A1(n5034), .B0(n5033), .Y(n5035) );
ADDFHX2TS U1390 ( .A(n949), .B(n948), .CI(n947), .CO(n989), .S(n988) );
INVX2TS U1391 ( .A(n4760), .Y(n3042) );
OR2X2TS U1392 ( .A(n3078), .B(n3077), .Y(n3234) );
OAI22X1TS U1393 ( .A0(n5894), .A1(n3075), .B0(n3074), .B1(n3236), .Y(n3235)
);
XNOR2X1TS U1394 ( .A(n115), .B(n6248), .Y(n3686) );
INVX2TS U1395 ( .A(n5253), .Y(n5114) );
NAND2BXLTS U1396 ( .AN(n2864), .B(n6185), .Y(n1386) );
INVX2TS U1397 ( .A(n6991), .Y(n6610) );
NAND2BXLTS U1398 ( .AN(n2864), .B(n94), .Y(n577) );
CLKBUFX2TS U1399 ( .A(n1825), .Y(n6523) );
CLKBUFX2TS U1400 ( .A(n5527), .Y(n6643) );
INVX2TS U1401 ( .A(n4760), .Y(n1165) );
XOR2X2TS U1402 ( .A(n189), .B(n1085), .Y(n1248) );
NAND2BXLTS U1403 ( .AN(n2472), .B(n1660), .Y(n181) );
BUFX3TS U1404 ( .A(n6319), .Y(n6734) );
NAND2X1TS U1405 ( .A(n2597), .B(n2595), .Y(n25) );
NOR2XLTS U1406 ( .A(n7016), .B(n7015), .Y(n7063) );
AOI21X1TS U1407 ( .A0(n7004), .A1(n7310), .B0(n6970), .Y(n7467) );
ADDFHX2TS U1408 ( .A(n6166), .B(n6165), .CI(n6164), .CO(n6810), .S(n6809) );
NAND3X1TS U1409 ( .A(n1792), .B(n1791), .C(n1790), .Y(n1803) );
NAND2X1TS U1410 ( .A(n1788), .B(n1787), .Y(n1791) );
INVX2TS U1411 ( .A(n7342), .Y(n7379) );
XOR2X1TS U1412 ( .A(n4170), .B(n4169), .Y(n4172) );
INVX2TS U1413 ( .A(n3921), .Y(n3923) );
NOR2X2TS U1414 ( .A(n5048), .B(n5047), .Y(n7500) );
OAI21X2TS U1415 ( .A0(n5460), .A1(n5461), .B0(n5458), .Y(n5459) );
AOI21X2TS U1416 ( .A0(n7430), .A1(n6931), .B0(n6930), .Y(n7440) );
NAND2X4TS U1417 ( .A(n7392), .B(n6795), .Y(n7292) );
ADDFHX2TS U1418 ( .A(n919), .B(n918), .CI(n917), .CO(n995), .S(n990) );
ADDFHX2TS U1419 ( .A(n345), .B(n344), .CI(n343), .CO(n1003), .S(n1002) );
INVX2TS U1420 ( .A(n6777), .Y(n5242) );
NAND2X1TS U1421 ( .A(n33), .B(n6901), .Y(n6902) );
NOR2X1TS U1422 ( .A(n7448), .B(n6900), .Y(n6901) );
NOR2X2TS U1423 ( .A(n6811), .B(n6810), .Y(n7416) );
AOI21X1TS U1424 ( .A0(n7004), .A1(n7003), .B0(n7002), .Y(n7476) );
INVX2TS U1425 ( .A(n2435), .Y(n2425) );
INVX2TS U1426 ( .A(n2432), .Y(n2433) );
INVX2TS U1427 ( .A(n7653), .Y(n7637) );
NOR2X2TS U1428 ( .A(n2446), .B(n2447), .Y(n7653) );
NOR2X2TS U1429 ( .A(n3323), .B(n3322), .Y(n7318) );
NAND2X2TS U1430 ( .A(n5026), .B(n5025), .Y(n7595) );
OAI21XLTS U1431 ( .A0(n7623), .A1(n7627), .B0(n7628), .Y(n7578) );
NAND2X2TS U1432 ( .A(n6789), .B(n6788), .Y(n7143) );
NOR2X2TS U1433 ( .A(n6797), .B(n6796), .Y(n7295) );
OAI21XLTS U1434 ( .A0(n7295), .A1(n7294), .B0(n7293), .Y(n7296) );
NOR2X2TS U1435 ( .A(n6801), .B(n6800), .Y(n7124) );
NOR2X2TS U1436 ( .A(n6835), .B(n6834), .Y(n6956) );
INVX2TS U1437 ( .A(n6957), .Y(n6949) );
NOR2X2TS U1438 ( .A(n6837), .B(n6836), .Y(n6960) );
OAI21X1TS U1439 ( .A0(n6957), .A1(n6956), .B0(n6955), .Y(n6958) );
OR2X2TS U1440 ( .A(n6863), .B(n6862), .Y(n7310) );
INVX2TS U1441 ( .A(n1326), .Y(n1327) );
OAI21XLTS U1442 ( .A0(n7690), .A1(n7708), .B0(n7709), .Y(n7691) );
NAND2BXLTS U1443 ( .AN(n2864), .B(n6376), .Y(n1756) );
XNOR2X1TS U1444 ( .A(n5529), .B(n3988), .Y(n1958) );
NAND2BXLTS U1445 ( .AN(n2864), .B(n4069), .Y(n2865) );
AOI2BB2X1TS U1446 ( .B0(n2901), .B1(n2900), .A0N(n4702), .A1N(n2899), .Y(
n2902) );
NOR2XLTS U1447 ( .A(n4122), .B(n3076), .Y(n3078) );
NAND2BXLTS U1448 ( .AN(n3272), .B(Data_A_i[53]), .Y(n3079) );
AOI2BB2XLTS U1449 ( .B0(n2907), .B1(n4227), .A0N(n6487), .A1N(n4318), .Y(
n4228) );
NAND2BXLTS U1450 ( .AN(n3272), .B(n6735), .Y(n2560) );
ADDFX2TS U1451 ( .A(n3005), .B(n3004), .CI(n3003), .CO(n3128), .S(n2949) );
OAI22X1TS U1452 ( .A0(n4599), .A1(n2981), .B0(n3026), .B1(n3027), .Y(n3054)
);
ADDFX2TS U1453 ( .A(n4707), .B(n4706), .CI(n4705), .CO(n4723), .S(n4698) );
OAI22X1TS U1454 ( .A0(n4122), .A1(n4121), .B0(n5622), .B1(n4120), .Y(n4709)
);
ADDFX2TS U1455 ( .A(n3593), .B(n3592), .CI(n3591), .CO(n3850), .S(n3599) );
XNOR2X1TS U1456 ( .A(n6388), .B(n5190), .Y(n4226) );
OAI22X1TS U1457 ( .A0(n4381), .A1(n4254), .B0(n4253), .B1(n4321), .Y(n4285)
);
AO21XLTS U1458 ( .A0(n4684), .A1(n83), .B0(n4252), .Y(n4292) );
AOI2BB2X1TS U1459 ( .B0(n5117), .B1(n5116), .A0N(n5115), .A1N(n5191), .Y(
n5118) );
OAI22X1TS U1460 ( .A0(n6369), .A1(n5468), .B0(n1385), .B1(n5495), .Y(n5498)
);
NAND2BXLTS U1461 ( .AN(n2037), .B(n5368), .Y(n307) );
NAND2BXLTS U1462 ( .AN(n2472), .B(n5520), .Y(n195) );
INVX2TS U1463 ( .A(n4760), .Y(n1942) );
NAND2BXLTS U1464 ( .AN(n3272), .B(n6129), .Y(n1012) );
NAND2BXLTS U1465 ( .AN(n3272), .B(Data_A_i[37]), .Y(n1538) );
ADDFHX2TS U1466 ( .A(n2157), .B(n2156), .CI(n2155), .CO(n2122), .S(n2238) );
ADDFHX2TS U1467 ( .A(n2232), .B(n2231), .CI(n2230), .CO(n2203), .S(n2375) );
ADDFX2TS U1468 ( .A(n1995), .B(n1993), .CI(n1994), .CO(n1921), .S(n2129) );
OAI22X1TS U1469 ( .A0(n6392), .A1(n1876), .B0(n137), .B1(n1902), .Y(n1911)
);
ADDFHX2TS U1470 ( .A(n2048), .B(n2047), .CI(n2046), .CO(n2306), .S(n2043) );
NAND2BXLTS U1471 ( .AN(n2472), .B(n6686), .Y(n2473) );
BUFX4TS U1472 ( .A(n1828), .Y(n4716) );
OAI22X1TS U1473 ( .A0(n142), .A1(n2827), .B0(n88), .B1(n2963), .Y(n2955) );
OAI22X1TS U1474 ( .A0(n6381), .A1(n2481), .B0(n5267), .B1(n2480), .Y(n2646)
);
ADDFHX2TS U1475 ( .A(n2950), .B(n2949), .CI(n2948), .CO(n3137), .S(n3156) );
ADDFHX2TS U1476 ( .A(n3091), .B(n3090), .CI(n3089), .CO(n3124), .S(n3164) );
OAI22X1TS U1477 ( .A0(n142), .A1(n3201), .B0(n87), .B1(n4578), .Y(n4785) );
OAI22X1TS U1478 ( .A0(n3723), .A1(n3056), .B0(n63), .B1(n3210), .Y(n3219) );
ADDFHX2TS U1479 ( .A(n4798), .B(n4797), .CI(n4796), .CO(n4890), .S(n4836) );
OAI22X1TS U1480 ( .A0(n144), .A1(n4578), .B0(n87), .B1(n4576), .Y(n4821) );
ADDFHX2TS U1481 ( .A(n4819), .B(n4818), .CI(n4817), .CO(n4862), .S(n4838) );
ADDFX2TS U1482 ( .A(n4617), .B(n4616), .CI(n4615), .CO(n4774), .S(n4830) );
OAI22X1TS U1483 ( .A0(n13), .A1(n4072), .B0(n5753), .B1(n3989), .Y(n4643) );
AO21XLTS U1484 ( .A0(n97), .A1(n3990), .B0(n3276), .Y(n4642) );
ADDFHX2TS U1485 ( .A(n4831), .B(n4830), .CI(n4829), .CO(n4647), .S(n4860) );
ADDFHX2TS U1486 ( .A(n4028), .B(n4027), .CI(n4026), .CO(n4142), .S(n4658) );
OAI22X1TS U1487 ( .A0(n4009), .A1(n4008), .B0(n4566), .B1(n3764), .Y(n3996)
);
ADDFX2TS U1488 ( .A(n4049), .B(n4048), .CI(n4047), .CO(n3939), .S(n4126) );
ADDFX2TS U1489 ( .A(n3552), .B(n3551), .CI(n3550), .CO(n3567), .S(n3514) );
OAI22X1TS U1490 ( .A0(n4610), .A1(n3731), .B0(n4253), .B1(n3494), .Y(n3748)
);
ADDFX2TS U1491 ( .A(n3805), .B(n3804), .CI(n3803), .CO(n3966), .S(n4012) );
AO21XLTS U1492 ( .A0(n143), .A1(n88), .B0(n1816), .Y(n3806) );
CLKBUFX2TS U1493 ( .A(n2558), .Y(n4253) );
AO21XLTS U1494 ( .A0(n105), .A1(n3361), .B0(n3398), .Y(n3371) );
OAI22X1TS U1495 ( .A0(n4225), .A1(n3344), .B0(n3933), .B1(n3619), .Y(n3625)
);
AO21XLTS U1496 ( .A0(n102), .A1(n49), .B0(n4398), .Y(n4526) );
OAI22X1TS U1497 ( .A0(n5702), .A1(n5184), .B0(n5758), .B1(n5265), .Y(n5262)
);
INVX2TS U1498 ( .A(n5500), .Y(n5470) );
AO21XLTS U1499 ( .A0(n55), .A1(n38), .B0(n5755), .Y(n5802) );
AO21XLTS U1500 ( .A0(n4258), .A1(n140), .B0(n5584), .Y(n5684) );
CLKBUFX2TS U1501 ( .A(n2558), .Y(n6111) );
NOR2XLTS U1502 ( .A(n7091), .B(n6145), .Y(n6180) );
AO21XLTS U1503 ( .A0(n46), .A1(n6124), .B0(n6123), .Y(n6187) );
CLKBUFX2TS U1504 ( .A(n3346), .Y(n5432) );
CLKBUFX2TS U1505 ( .A(n2558), .Y(n6480) );
BUFX3TS U1506 ( .A(n3365), .Y(n6590) );
NAND2BXLTS U1507 ( .AN(n2864), .B(n3209), .Y(n492) );
NAND2BXLTS U1508 ( .AN(n2037), .B(n3616), .Y(n399) );
XNOR2X1TS U1509 ( .A(n616), .B(n2936), .Y(n480) );
BUFX3TS U1510 ( .A(n2502), .Y(n3525) );
CLKBUFX2TS U1511 ( .A(n2512), .Y(n2281) );
CLKBUFX2TS U1512 ( .A(n3615), .Y(n4743) );
NAND2BXLTS U1513 ( .AN(n2864), .B(n5800), .Y(n1038) );
ADDFX2TS U1514 ( .A(n1018), .B(n1017), .CI(n1016), .CO(n1361), .S(n1024) );
ADDFX2TS U1515 ( .A(n1682), .B(n1681), .CI(n1680), .CO(n1745), .S(n1748) );
ADDFX2TS U1516 ( .A(n1513), .B(n1512), .CI(n1511), .CO(n1749), .S(n1485) );
ADDFX2TS U1517 ( .A(n1354), .B(n1353), .CI(n1352), .CO(n1448), .S(n1438) );
AO21XLTS U1518 ( .A0(n6003), .A1(n1014), .B0(n6002), .Y(n6023) );
ADDFHX2TS U1519 ( .A(n6070), .B(n6069), .CI(n6068), .CO(n6149), .S(n6072) );
OAI2BB1X1TS U1520 ( .A0N(n5952), .A1N(n5953), .B0(n5947), .Y(n6069) );
OAI21XLTS U1521 ( .A0(n5952), .A1(n5953), .B0(n5955), .Y(n5947) );
XOR2X1TS U1522 ( .A(n5955), .B(n5954), .Y(n5969) );
XOR2XLTS U1523 ( .A(n5953), .B(n5952), .Y(n5954) );
ADDFHX2TS U1524 ( .A(n2081), .B(n2080), .CI(n2079), .CO(n2087), .S(n2210) );
OAI21XLTS U1525 ( .A0(n1722), .A1(n1723), .B0(n1720), .Y(n1721) );
ADDFHX2TS U1526 ( .A(n2130), .B(n2129), .CI(n2128), .CO(n2003), .S(n2208) );
ADDFHX2TS U1527 ( .A(n2238), .B(n2237), .CI(n2236), .CO(n2244), .S(n2369) );
ADDFHX2TS U1528 ( .A(n2306), .B(n2305), .CI(n2304), .CO(n2664), .S(n2287) );
OAI22X1TS U1529 ( .A0(n4084), .A1(n2653), .B0(n141), .B1(n2517), .Y(n2566)
);
ADDFHX2TS U1530 ( .A(n3142), .B(n3141), .CI(n3140), .CO(n3160), .S(n3108) );
ADDFHX2TS U1531 ( .A(n3106), .B(n3105), .CI(n3104), .CO(n3134), .S(n3109) );
ADDFHX2TS U1532 ( .A(n2641), .B(n2640), .CI(n2639), .CO(n2582), .S(n2660) );
ADDFHX2TS U1533 ( .A(n2689), .B(n2688), .CI(n2687), .CO(n2811), .S(n2685) );
ADDFHX2TS U1534 ( .A(n3157), .B(n3156), .CI(n3155), .CO(n3082), .S(n3177) );
ADDFHX2TS U1535 ( .A(n4727), .B(n4726), .CI(n4725), .CO(n4899), .S(n4900) );
ADDFHX2TS U1536 ( .A(n4733), .B(n4732), .CI(n4731), .CO(n4897), .S(n4901) );
ADDFHX2TS U1537 ( .A(n4783), .B(n4782), .CI(n4781), .CO(n4794), .S(n4839) );
ADDFHX2TS U1538 ( .A(n4853), .B(n4852), .CI(n4851), .CO(n4864), .S(n4861) );
ADDFHX2TS U1539 ( .A(n4771), .B(n4770), .CI(n4769), .CO(n4859), .S(n4793) );
ADDFHX2TS U1540 ( .A(n4031), .B(n4030), .CI(n4029), .CO(n4950), .S(n4657) );
ADDFHX2TS U1541 ( .A(n4647), .B(n4646), .CI(n4645), .CO(n4963), .S(n4876) );
ADDFHX2TS U1542 ( .A(n4653), .B(n4652), .CI(n4651), .CO(n4952), .S(n4961) );
ADDFX2TS U1543 ( .A(n3790), .B(n3789), .CI(n3788), .CO(n4018), .S(n4151) );
ADDFHX2TS U1544 ( .A(n4127), .B(n4126), .CI(n4125), .CO(n4145), .S(n4652) );
ADDFHX2TS U1545 ( .A(n4016), .B(n4015), .CI(n4014), .CO(n4155), .S(n4991) );
ADDFHX2TS U1546 ( .A(n4019), .B(n4018), .CI(n4017), .CO(n4157), .S(n4154) );
ADDFX2TS U1547 ( .A(n3464), .B(n3463), .CI(n3462), .CO(n3488), .S(n3677) );
ADDFHX2TS U1548 ( .A(n3608), .B(n3607), .CI(n3606), .CO(n3853), .S(n3602) );
ADDFHX2TS U1549 ( .A(n3650), .B(n3649), .CI(n3648), .CO(n3601), .S(n3795) );
ADDFHX2TS U1550 ( .A(n3492), .B(n3491), .CI(n3490), .CO(n3487), .S(n3675) );
ADDFHX2TS U1551 ( .A(n4236), .B(n4235), .CI(n4234), .CO(n4348), .S(n4445) );
ADDFHX2TS U1552 ( .A(n4267), .B(n4266), .CI(n4265), .CO(n4435), .S(n4349) );
ADDFHX2TS U1553 ( .A(n4509), .B(n4508), .CI(n4507), .CO(n5125), .S(n4457) );
ADDFHX2TS U1554 ( .A(n4300), .B(n4299), .CI(n4298), .CO(n4353), .S(n4448) );
AO21XLTS U1555 ( .A0(n4337), .A1(n58), .B0(n6250), .Y(n6283) );
OAI22X1TS U1556 ( .A0(n6618), .A1(n6348), .B0(n6616), .B1(n6416), .Y(n6417)
);
AO21XLTS U1557 ( .A0(n6369), .A1(n1385), .B0(n6368), .Y(n6393) );
AO21XLTS U1558 ( .A0(n74), .A1(n6391), .B0(n6390), .Y(n6471) );
BUFX4TS U1559 ( .A(n128), .Y(n6618) );
INVX2TS U1560 ( .A(Data_B_i[2]), .Y(n4050) );
CLKBUFX2TS U1561 ( .A(n3990), .Y(n1706) );
ADDHXLTS U1562 ( .A(n608), .B(n607), .CO(n613), .S(n642) );
NAND2BXLTS U1563 ( .AN(n2037), .B(n4480), .Y(n461) );
OAI22X1TS U1564 ( .A0(n5586), .A1(n167), .B0(n2516), .B1(n1127), .Y(n1224)
);
ADDFX2TS U1565 ( .A(n1273), .B(n1272), .CI(n1271), .CO(n1275), .S(n1289) );
ADDFX2TS U1566 ( .A(n1145), .B(n1144), .CI(n1143), .CO(n1077), .S(n1193) );
ADDFX2TS U1567 ( .A(n1170), .B(n1169), .CI(n1168), .CO(n1606), .S(n1074) );
XNOR2X1TS U1568 ( .A(n1542), .B(n1720), .Y(n1714) );
ADDFHX2TS U1569 ( .A(n1497), .B(n1496), .CI(n1495), .CO(n1768), .S(n1573) );
AO21XLTS U1570 ( .A0(n6707), .A1(n6706), .B0(n6705), .Y(n6737) );
ADDFHX2TS U1571 ( .A(n2370), .B(n2369), .CI(n2368), .CO(n2391), .S(n2406) );
ADDFHX2TS U1572 ( .A(n2217), .B(n2216), .CI(n2215), .CO(n2220), .S(n2266) );
ADDFHX2TS U1573 ( .A(n3163), .B(n3162), .CI(n3161), .CO(n3181), .S(n3110) );
ADDFHX2TS U1574 ( .A(n3280), .B(n3279), .CI(n3278), .CO(n4918), .S(n3293) );
ADDFHX2TS U1575 ( .A(n4865), .B(n4864), .CI(n4863), .CO(n4956), .S(n4873) );
ADDFHX2TS U1576 ( .A(n4953), .B(n4952), .CI(n4951), .CO(n4994), .S(n4987) );
ADDFHX2TS U1577 ( .A(n4966), .B(n4965), .CI(n4964), .CO(n4981), .S(n4957) );
ADDFHX2TS U1578 ( .A(n4152), .B(n4151), .CI(n4150), .CO(n4159), .S(n4162) );
ADDFHX2TS U1579 ( .A(n3681), .B(n3680), .CI(n3679), .CO(n3674), .S(n3823) );
ADDFHX2TS U1580 ( .A(n3817), .B(n3816), .CI(n3815), .CO(n4158), .S(n4166) );
ADDFHX2TS U1581 ( .A(n4149), .B(n4148), .CI(n4147), .CO(n4167), .S(n4163) );
ADDFHX2TS U1582 ( .A(n3669), .B(n3668), .CI(n3667), .CO(n3676), .S(n3797) );
ADDFHX2TS U1583 ( .A(n3777), .B(n3776), .CI(n3775), .CO(n3799), .S(n4160) );
ADDFHX2TS U1584 ( .A(n4995), .B(n4994), .CI(n4993), .CO(n4996), .S(n5003) );
ADDFHX2TS U1585 ( .A(n3675), .B(n3674), .CI(n3673), .CO(n3702), .S(n4178) );
ADDFHX2TS U1586 ( .A(n4347), .B(n4346), .CI(n4345), .CO(n4544), .S(n4450) );
ADDFHX2TS U1587 ( .A(n4446), .B(n4445), .CI(n4444), .CO(n4548), .S(n4541) );
ADDFHX2TS U1588 ( .A(n4353), .B(n4352), .CI(n4351), .CO(n4491), .S(n4442) );
ADDFHX2TS U1589 ( .A(n5166), .B(n5165), .CI(n5164), .CO(n5321), .S(n5162) );
ADDFHX2TS U1590 ( .A(n5509), .B(n5508), .CI(n5507), .CO(n5629), .S(n5511) );
ADDFHX2TS U1591 ( .A(n5569), .B(n5568), .CI(n5567), .CO(n5642), .S(n5632) );
ADDFHX2TS U1592 ( .A(n5871), .B(n5870), .CI(n5869), .CO(n6093), .S(n5920) );
ADDFHX2TS U1593 ( .A(n5900), .B(n5899), .CI(n5898), .CO(n6157), .S(n5896) );
ADDFHX2TS U1594 ( .A(n5830), .B(n5829), .CI(n5828), .CO(n5897), .S(n5826) );
AO21X1TS U1595 ( .A0(n60), .A1(n6466), .B0(n6540), .Y(n6546) );
AO21XLTS U1596 ( .A0(n5549), .A1(n6589), .B0(n6588), .Y(n6597) );
AO21XLTS U1597 ( .A0(n6660), .A1(n6659), .B0(n6658), .Y(n6688) );
NAND2BXLTS U1598 ( .AN(n2472), .B(n4078), .Y(n725) );
BUFX3TS U1599 ( .A(n1828), .Y(n2110) );
NAND2BXLTS U1600 ( .AN(n2472), .B(n4108), .Y(n730) );
BUFX3TS U1601 ( .A(n1828), .Y(n824) );
NAND2BXLTS U1602 ( .AN(n2472), .B(n3927), .Y(n689) );
NAND2BXLTS U1603 ( .AN(n2864), .B(n92), .Y(n627) );
ADDFHX2TS U1604 ( .A(n940), .B(n939), .CI(n938), .CO(n969), .S(n959) );
ADDFX2TS U1605 ( .A(n273), .B(n272), .CI(n271), .CO(n1297), .S(n299) );
XNOR2X1TS U1606 ( .A(n1244), .B(n192), .Y(n1280) );
XNOR2X1TS U1607 ( .A(n1248), .B(n1249), .Y(n192) );
OAI2BB1X1TS U1608 ( .A0N(n1249), .A1N(n1248), .B0(n1247), .Y(n1284) );
OAI2BB1X2TS U1609 ( .A0N(n1246), .A1N(n1245), .B0(n1244), .Y(n1247) );
ADDFHX2TS U1610 ( .A(n1291), .B(n1290), .CI(n1289), .CO(n1303), .S(n1312) );
ADDFHX2TS U1611 ( .A(n1195), .B(n1194), .CI(n1193), .CO(n1218), .S(n1262) );
ADDFHX2TS U1612 ( .A(n1427), .B(n1426), .CI(n1425), .CO(n1523), .S(n1603) );
ADDFHX2TS U1613 ( .A(n1710), .B(n1709), .CI(n1708), .CO(n1780), .S(n1782) );
NOR2X1TS U1614 ( .A(n7470), .B(n6974), .Y(n6869) );
AO21XLTS U1615 ( .A0(n6993), .A1(n6992), .B0(n6991), .Y(n7023) );
ADDFHX2TS U1616 ( .A(n1777), .B(n1776), .CI(n1775), .CO(n2419), .S(n1786) );
ADDFHX2TS U1617 ( .A(n2403), .B(n2402), .CI(n2401), .CO(n2422), .S(n2431) );
ADDFHX2TS U1618 ( .A(n1780), .B(n1779), .CI(n1778), .CO(n2430), .S(n1785) );
ADDFHX2TS U1619 ( .A(n2361), .B(n2360), .CI(n2359), .CO(n2847), .S(n2363) );
ADDFHX2TS U1620 ( .A(n2846), .B(n2845), .CI(n2844), .CO(n2739), .S(n2858) );
NAND3X1TS U1621 ( .A(n28), .B(n29), .C(n30), .Y(n2743) );
NAND2X1TS U1622 ( .A(n2598), .B(n2599), .Y(n30) );
ADDFHX2TS U1623 ( .A(n4982), .B(n4981), .CI(n4980), .CO(n5008), .S(n4978) );
ADDFHX2TS U1624 ( .A(n4164), .B(n4163), .CI(n4162), .CO(n5001), .S(n4993) );
ADDFHX2TS U1625 ( .A(n3799), .B(n3798), .CI(n3797), .CO(n3794), .S(n4169) );
ADDFHX2TS U1626 ( .A(n4998), .B(n4997), .CI(n4996), .CO(n5011), .S(n5014) );
ADDFHX2TS U1627 ( .A(n3703), .B(n3702), .CI(n3701), .CO(n3828), .S(n4184) );
ADDFHX2TS U1628 ( .A(n4545), .B(n4544), .CI(n4543), .CO(n4441), .S(n4556) );
ADDFX2TS U1629 ( .A(n5483), .B(n5482), .CI(n5481), .CO(n5562), .S(n5460) );
ADDFHX2TS U1630 ( .A(n5592), .B(n5591), .CI(n5590), .CO(n5709), .S(n5637) );
ADDFHX2TS U1631 ( .A(n6157), .B(n6156), .CI(n6155), .CO(n6168), .S(n6161) );
ADDFHX2TS U1632 ( .A(n5827), .B(n5826), .CI(n5825), .CO(n5923), .S(n5853) );
INVX2TS U1633 ( .A(n7395), .Y(n6787) );
NAND2BXLTS U1634 ( .AN(n2472), .B(n4097), .Y(n761) );
BUFX3TS U1635 ( .A(n4614), .Y(n838) );
ADDFHX2TS U1636 ( .A(n877), .B(n876), .CI(n875), .CO(n882), .S(n884) );
ADDFHX2TS U1637 ( .A(n922), .B(n921), .CI(n920), .CO(n465), .S(n949) );
ADDFHX2TS U1638 ( .A(n341), .B(n340), .CI(n339), .CO(n1317), .S(n343) );
ADDFHX2TS U1639 ( .A(n1306), .B(n1305), .CI(n1304), .CO(n1315), .S(n1316) );
ADDFHX2TS U1640 ( .A(n1312), .B(n1311), .CI(n1310), .CO(n1325), .S(n1313) );
ADDFHX2TS U1641 ( .A(n1288), .B(n1287), .CI(n1286), .CO(n1260), .S(n1320) );
ADDFHX2TS U1642 ( .A(n3184), .B(n3183), .CI(n3182), .CO(n3308), .S(n3319) );
ADDFHX2TS U1643 ( .A(n3307), .B(n3306), .CI(n3305), .CO(n3315), .S(n3317) );
ADDFHX2TS U1644 ( .A(n3316), .B(n3315), .CI(n3314), .CO(n3331), .S(n3330) );
ADDFHX2TS U1645 ( .A(n3301), .B(n3300), .CI(n3299), .CO(n3335), .S(n3334) );
OAI2BB1X2TS U1646 ( .A0N(n4882), .A1N(n4881), .B0(n4844), .Y(n4943) );
AO21XLTS U1647 ( .A0(n7046), .A1(n7045), .B0(n7044), .Y(n7058) );
NAND2BXLTS U1648 ( .AN(Data_B_i[0]), .B(n2511), .Y(n776) );
ADDFHX2TS U1649 ( .A(n1318), .B(n1317), .CI(n1316), .CO(n1326), .S(n1004) );
NAND2BXLTS U1650 ( .AN(Data_B_i[0]), .B(n616), .Y(n153) );
INVX2TS U1651 ( .A(n6974), .Y(n6976) );
NOR2XLTS U1652 ( .A(n7466), .B(n7470), .Y(n6971) );
INVX2TS U1653 ( .A(n7354), .Y(n7333) );
INVX2TS U1654 ( .A(n7344), .Y(n7324) );
INVX2TS U1655 ( .A(n7377), .Y(n7179) );
INVX2TS U1656 ( .A(n7389), .Y(n7609) );
INVX2TS U1657 ( .A(n7574), .Y(n7593) );
INVX2TS U1658 ( .A(n7462), .Y(n7133) );
NOR2XLTS U1659 ( .A(n7122), .B(n7124), .Y(n7127) );
XOR3X1TS U1660 ( .A(n7096), .B(n7095), .C(n7094), .Y(n7097) );
AO21XLTS U1661 ( .A0(n4750), .A1(n3047), .B0(n7092), .Y(n7094) );
INVX2TS U1662 ( .A(n7367), .Y(n7362) );
XOR2XLTS U1663 ( .A(n7404), .B(n7403), .Y(N75) );
XOR2XLTS U1664 ( .A(n7465), .B(n7464), .Y(N72) );
INVX2TS U1665 ( .A(n7420), .Y(n7422) );
XOR2XLTS U1666 ( .A(n7427), .B(n7426), .Y(N86) );
XOR2XLTS U1667 ( .A(n7438), .B(n7437), .Y(N87) );
XOR2XLTS U1668 ( .A(n7490), .B(n7489), .Y(N95) );
XOR2X1TS U1669 ( .A(n6898), .B(n6897), .Y(N102) );
XOR2XLTS U1670 ( .A(n7458), .B(n7457), .Y(N105) );
XOR2XLTS U1671 ( .A(n7413), .B(n7412), .Y(N84) );
XOR2XLTS U1672 ( .A(n7446), .B(n7445), .Y(N88) );
XOR2XLTS U1673 ( .A(n7474), .B(n7473), .Y(N99) );
INVX2TS U1674 ( .A(n7110), .Y(n7112) );
INVX2TS U1675 ( .A(n7668), .Y(n7359) );
XOR2XLTS U1676 ( .A(n7621), .B(n7620), .Y(N57) );
XOR2XLTS U1677 ( .A(n7607), .B(n7606), .Y(N58) );
XOR2XLTS U1678 ( .A(n7573), .B(n7572), .Y(N60) );
INVX2TS U1679 ( .A(n7569), .Y(n7571) );
XOR2XLTS U1680 ( .A(n7631), .B(n7630), .Y(N61) );
XOR2XLTS U1681 ( .A(n7584), .B(n7583), .Y(N62) );
INVX2TS U1682 ( .A(n7580), .Y(n7582) );
XOR2XLTS U1683 ( .A(n7591), .B(n7590), .Y(N63) );
XOR2XLTS U1684 ( .A(n7566), .B(n7565), .Y(N64) );
XOR2XLTS U1685 ( .A(n7536), .B(n7535), .Y(N65) );
XOR2XLTS U1686 ( .A(n7549), .B(n7548), .Y(N66) );
XOR2XLTS U1687 ( .A(n7557), .B(n7556), .Y(N67) );
NOR2XLTS U1688 ( .A(n7558), .B(n7551), .Y(n7553) );
XOR2XLTS U1689 ( .A(n7510), .B(n7509), .Y(N68) );
XOR2XLTS U1690 ( .A(n7499), .B(n7498), .Y(N69) );
INVX2TS U1691 ( .A(n7298), .Y(n7300) );
INVX2TS U1692 ( .A(n6965), .Y(n6967) );
OAI21XLTS U1693 ( .A0(n7771), .A1(n7767), .B0(n7768), .Y(n7261) );
INVX2TS U1694 ( .A(n7743), .Y(n7745) );
INVX2TS U1695 ( .A(n7727), .Y(n7729) );
OAI21XLTS U1696 ( .A0(n7722), .A1(n7221), .B0(n7220), .Y(n7225) );
INVX2TS U1697 ( .A(n7702), .Y(n7704) );
INVX2TS U1698 ( .A(n7708), .Y(n7710) );
INVX2TS U1699 ( .A(n7194), .Y(n7196) );
ADDFX2TS U1700 ( .A(n3915), .B(n3914), .CI(n3913), .CO(n4444), .S(n3918) );
ADDFHX2TS U1701 ( .A(n3857), .B(n3856), .CI(n3855), .CO(n4347), .S(n3913) );
ADDFHX2TS U1702 ( .A(n4843), .B(n4842), .CI(n4841), .CO(n4896), .S(n4903) );
OAI22X2TS U1703 ( .A0(n6401), .A1(n5193), .B0(n6732), .B1(n5273), .Y(n5276)
);
INVX2TS U1704 ( .A(n7516), .Y(n15) );
INVX2TS U1705 ( .A(n7492), .Y(n7516) );
BUFX3TS U1706 ( .A(n2892), .Y(n4084) );
NAND2X4TS U1707 ( .A(n4882), .B(n6), .Y(n16) );
NAND2X4TS U1708 ( .A(n5), .B(n4881), .Y(n17) );
NAND2X4TS U1709 ( .A(n16), .B(n17), .Y(n4883) );
BUFX4TS U1710 ( .A(n5063), .Y(n33) );
ADDFHX2TS U1711 ( .A(n467), .B(n466), .CI(n465), .CO(n431), .S(n917) );
BUFX3TS U1712 ( .A(Data_A_i[21]), .Y(n50) );
BUFX3TS U1713 ( .A(n2892), .Y(n5519) );
BUFX3TS U1714 ( .A(n2892), .Y(n5586) );
OR2X4TS U1715 ( .A(n998), .B(n997), .Y(n19) );
OR2X2TS U1716 ( .A(n865), .B(n864), .Y(n20) );
OR2X4TS U1717 ( .A(n911), .B(n910), .Y(n21) );
INVX2TS U1718 ( .A(n78), .Y(n80) );
NAND2X4TS U1719 ( .A(n2557), .B(n6992), .Y(n5456) );
INVX2TS U1720 ( .A(n2298), .Y(n95) );
BUFX4TS U1721 ( .A(n3343), .Y(n6705) );
OAI22X2TS U1722 ( .A0(n4571), .A1(n3252), .B0(n3251), .B1(n4570), .Y(n4559)
);
CLKBUFX2TS U1723 ( .A(n7176), .Y(n7177) );
AOI21X1TS U1724 ( .A0(n7478), .A1(n32), .B0(n7477), .Y(n7481) );
OAI21X4TS U1725 ( .A0(n7699), .A1(n7702), .B0(n7703), .Y(n7689) );
XOR3X2TS U1726 ( .A(n2597), .B(n2596), .C(n2595), .Y(n2604) );
NAND2X1TS U1727 ( .A(n2597), .B(n2596), .Y(n24) );
NAND2X1TS U1728 ( .A(n2596), .B(n2595), .Y(n26) );
NAND3X1TS U1729 ( .A(n24), .B(n25), .C(n26), .Y(n2599) );
XOR2X1TS U1730 ( .A(n2600), .B(n2598), .Y(n27) );
XOR2X1TS U1731 ( .A(n27), .B(n2599), .Y(n2724) );
NAND2X1TS U1732 ( .A(n2600), .B(n2598), .Y(n28) );
NAND2X1TS U1733 ( .A(n2600), .B(n2599), .Y(n29) );
ADDFHX2TS U1734 ( .A(n3969), .B(n3968), .CI(n3967), .CO(n4161), .S(n4022) );
INVX2TS U1735 ( .A(n7539), .Y(n7529) );
NAND2X4TS U1736 ( .A(n5060), .B(n7586), .Y(n5062) );
BUFX4TS U1737 ( .A(n5063), .Y(n32) );
BUFX6TS U1738 ( .A(n5063), .Y(n7486) );
ADDFHX2TS U1739 ( .A(n4780), .B(n4779), .CI(n4778), .CO(n4840), .S(n4732) );
BUFX4TS U1740 ( .A(n3365), .Y(n6148) );
ADDFHX2TS U1741 ( .A(n6295), .B(n6294), .CI(n6293), .CO(n6374), .S(n6324) );
AOI21X2TS U1742 ( .A0(n7080), .A1(n6859), .B0(n6858), .Y(n6860) );
ADDFX2TS U1743 ( .A(n6073), .B(n6072), .CI(n6071), .CO(n6098), .S(n6018) );
ADDFHX2TS U1744 ( .A(n4167), .B(n4166), .CI(n4165), .CO(n4171), .S(n5000) );
BUFX4TS U1745 ( .A(n1536), .Y(n5886) );
ADDFHX2TS U1746 ( .A(n3941), .B(n3940), .CI(n3939), .CO(n3967), .S(n4061) );
NAND2X4TS U1747 ( .A(n7577), .B(n5034), .Y(n5036) );
OAI22X2TS U1748 ( .A0(n4716), .A1(n4079), .B0(n4714), .B1(n3998), .Y(n4130)
);
NAND2X1TS U1749 ( .A(n33), .B(n6971), .Y(n6972) );
INVX2TS U1750 ( .A(n3276), .Y(n35) );
INVX2TS U1751 ( .A(n3276), .Y(n36) );
INVX2TS U1752 ( .A(n5665), .Y(n37) );
INVX2TS U1753 ( .A(n5665), .Y(n38) );
CLKBUFX2TS U1754 ( .A(Data_B_i[0]), .Y(n2871) );
INVX2TS U1755 ( .A(n4252), .Y(n2789) );
BUFX3TS U1756 ( .A(n4322), .Y(n39) );
INVX2TS U1757 ( .A(n42), .Y(n43) );
INVX2TS U1758 ( .A(n4), .Y(n45) );
CLKBUFX2TS U1759 ( .A(n1393), .Y(n3213) );
BUFX3TS U1760 ( .A(n6065), .Y(n46) );
OAI22X1TS U1761 ( .A0(n46), .A1(n3987), .B0(n4204), .B1(n3761), .Y(n3993) );
INVX2TS U1762 ( .A(n1393), .Y(n47) );
INVX2TS U1763 ( .A(n47), .Y(n48) );
INVX2TS U1764 ( .A(n47), .Y(n49) );
CLKINVX6TS U1765 ( .A(n5756), .Y(n53) );
INVX2TS U1766 ( .A(n53), .Y(n54) );
INVX2TS U1767 ( .A(n53), .Y(n56) );
INVX2TS U1768 ( .A(n4), .Y(n61) );
INVX2TS U1769 ( .A(n4), .Y(n62) );
INVX2TS U1770 ( .A(n4), .Y(n64) );
BUFX3TS U1771 ( .A(n4322), .Y(n5103) );
BUFX3TS U1772 ( .A(n4322), .Y(n2633) );
INVX2TS U1773 ( .A(n68), .Y(n69) );
INVX2TS U1774 ( .A(n68), .Y(n70) );
CLKINVX6TS U1775 ( .A(n4635), .Y(n72) );
INVX2TS U1776 ( .A(n72), .Y(n74) );
INVX2TS U1777 ( .A(n6378), .Y(n77) );
INVX2TS U1778 ( .A(n78), .Y(n79) );
INVX2TS U1779 ( .A(n6588), .Y(n82) );
INVX2TS U1780 ( .A(n4682), .Y(n83) );
INVX2TS U1781 ( .A(n4391), .Y(n89) );
INVX2TS U1782 ( .A(n89), .Y(n90) );
INVX2TS U1783 ( .A(n89), .Y(n91) );
BUFX3TS U1784 ( .A(n5431), .Y(n4691) );
BUFX3TS U1785 ( .A(n5431), .Y(n6542) );
CLKBUFX2TS U1786 ( .A(n5431), .Y(n5942) );
INVX2TS U1787 ( .A(n4252), .Y(n92) );
INVX4TS U1788 ( .A(Data_A_i[13]), .Y(n4252) );
INVX2TS U1789 ( .A(n7044), .Y(n93) );
INVX2TS U1790 ( .A(n7044), .Y(n6890) );
INVX2TS U1791 ( .A(n6768), .Y(n6686) );
INVX2TS U1792 ( .A(n6768), .Y(n6708) );
INVX2TS U1793 ( .A(n5292), .Y(n4480) );
INVX2TS U1794 ( .A(n5292), .Y(n4087) );
INVX2TS U1795 ( .A(n4398), .Y(n94) );
INVX2TS U1796 ( .A(n4052), .Y(n3991) );
INVX2TS U1797 ( .A(n3991), .Y(n96) );
INVX2TS U1798 ( .A(n3991), .Y(n97) );
CLKBUFX2TS U1799 ( .A(n96), .Y(n2078) );
INVX2TS U1800 ( .A(n5892), .Y(n98) );
INVX2TS U1801 ( .A(n5892), .Y(n5760) );
INVX2TS U1802 ( .A(n3275), .Y(n3044) );
INVX2TS U1803 ( .A(n3044), .Y(n99) );
INVX2TS U1804 ( .A(n1816), .Y(n100) );
INVX2TS U1805 ( .A(n1816), .Y(n101) );
INVX2TS U1806 ( .A(n3348), .Y(n4595) );
INVX2TS U1807 ( .A(n4595), .Y(n102) );
INVX2TS U1808 ( .A(n4595), .Y(n103) );
INVX2TS U1809 ( .A(n4564), .Y(n104) );
INVX2TS U1810 ( .A(n4564), .Y(n105) );
INVX2TS U1811 ( .A(n6123), .Y(n106) );
INVX2TS U1812 ( .A(n6123), .Y(n6012) );
INVX4TS U1813 ( .A(n7388), .Y(n107) );
INVX4TS U1814 ( .A(n7388), .Y(n7626) );
INVX2TS U1815 ( .A(n2895), .Y(n5665) );
INVX2TS U1816 ( .A(n5665), .Y(n108) );
INVX2TS U1817 ( .A(n5665), .Y(n109) );
NAND2X4TS U1818 ( .A(n176), .B(n177), .Y(n1828) );
INVX2TS U1819 ( .A(n1020), .Y(n4569) );
INVX2TS U1820 ( .A(n4569), .Y(n111) );
INVX2TS U1821 ( .A(n4569), .Y(n112) );
OAI22X1TS U1822 ( .A0(n3525), .A1(n2341), .B0(n111), .B1(n2508), .Y(n2587)
);
OAI22X1TS U1823 ( .A0(n5549), .A1(n2459), .B0(n4230), .B1(n2501), .Y(n2485)
);
INVX2TS U1824 ( .A(n6250), .Y(n114) );
INVX2TS U1825 ( .A(n6250), .Y(n6066) );
INVX4TS U1826 ( .A(Data_A_i[33]), .Y(n6250) );
INVX2TS U1827 ( .A(n5755), .Y(n116) );
INVX2TS U1828 ( .A(n5755), .Y(n5520) );
INVX4TS U1829 ( .A(Data_A_i[25]), .Y(n5755) );
INVX2TS U1830 ( .A(Data_A_i[3]), .Y(n3276) );
INVX2TS U1831 ( .A(n3276), .Y(n117) );
INVX2TS U1832 ( .A(n6540), .Y(n118) );
INVX2TS U1833 ( .A(n6540), .Y(n119) );
INVX4TS U1834 ( .A(Data_A_i[39]), .Y(n6540) );
INVX2TS U1835 ( .A(n6540), .Y(n5529) );
BUFX3TS U1836 ( .A(n4422), .Y(n120) );
BUFX3TS U1837 ( .A(n4422), .Y(n121) );
CLKINVX3TS U1838 ( .A(n5456), .Y(n6537) );
INVX2TS U1839 ( .A(n6537), .Y(n122) );
INVX2TS U1840 ( .A(n6537), .Y(n123) );
OAI22X1TS U1841 ( .A0(n122), .A1(n5691), .B0(n6111), .B1(n5744), .Y(n5727)
);
BUFX3TS U1842 ( .A(n5456), .Y(n6889) );
INVX2TS U1843 ( .A(n3615), .Y(n3390) );
INVX2TS U1844 ( .A(n3390), .Y(n124) );
INVX2TS U1845 ( .A(n3390), .Y(n125) );
INVX2TS U1846 ( .A(n1506), .Y(n127) );
CLKINVX6TS U1847 ( .A(n5757), .Y(n6261) );
INVX2TS U1848 ( .A(n6261), .Y(n129) );
BUFX3TS U1849 ( .A(n4532), .Y(n131) );
BUFX6TS U1850 ( .A(n4532), .Y(n2521) );
INVX2TS U1851 ( .A(n5436), .Y(n132) );
INVX2TS U1852 ( .A(n5436), .Y(n133) );
INVX2TS U1853 ( .A(n5436), .Y(n3616) );
INVX2TS U1854 ( .A(n2345), .Y(n5796) );
INVX2TS U1855 ( .A(n5796), .Y(n134) );
INVX2TS U1856 ( .A(n5796), .Y(n135) );
OAI22X1TS U1857 ( .A0(n39), .A1(n5797), .B0(n135), .B1(n5892), .Y(n5868) );
OAI22X1TS U1858 ( .A0(n5894), .A1(n1966), .B0(n134), .B1(n1965), .Y(n2180)
);
OAI22X1TS U1859 ( .A0(n5894), .A1(n5102), .B0(n135), .B1(n5179), .Y(n5214)
);
INVX2TS U1860 ( .A(n4596), .Y(n137) );
CLKBUFX2TS U1861 ( .A(n3346), .Y(n138) );
OAI22X1TS U1862 ( .A0(n5817), .A1(n4093), .B0(n3357), .B1(n4003), .Y(n4064)
);
INVX2TS U1863 ( .A(n6014), .Y(n147) );
OAI22X1TS U1864 ( .A0(n41), .A1(n610), .B0(n625), .B1(n582), .Y(n619) );
BUFX3TS U1865 ( .A(n1516), .Y(n149) );
ADDFHX2TS U1866 ( .A(n4270), .B(n4269), .CI(n4268), .CO(n4449), .S(n4446) );
OAI22X1TS U1867 ( .A0(n148), .A1(n1110), .B0(n1514), .B1(n1052), .Y(n1133)
);
OAI21XLTS U1868 ( .A0(n7257), .A1(n7768), .B0(n7258), .Y(n891) );
ADDFHX2TS U1869 ( .A(n4542), .B(n4541), .CI(n4540), .CO(n4557), .S(n4549) );
ADDFHX2TS U1870 ( .A(n634), .B(n633), .CI(n632), .CO(n904), .S(n903) );
XOR2X4TS U1871 ( .A(n3908), .B(Data_A_i[28]), .Y(n1013) );
ADDFHX2TS U1872 ( .A(n2582), .B(n2581), .CI(n2580), .CO(n2832), .S(n2726) );
ADDFHX2TS U1873 ( .A(n1831), .B(n1830), .CI(n1829), .CO(n1880), .S(n2085) );
OAI22X1TS U1874 ( .A0(n5251), .A1(n1175), .B0(n4746), .B1(n1348), .Y(n1343)
);
BUFX4TS U1875 ( .A(n2502), .Y(n4571) );
CLKBUFX2TS U1876 ( .A(n7178), .Y(n7342) );
BUFX4TS U1877 ( .A(n5757), .Y(n4009) );
ADDFHX2TS U1878 ( .A(n2674), .B(n2673), .CI(n2672), .CO(n2581), .S(n2715) );
ADDFHX2TS U1879 ( .A(n1603), .B(n1602), .CI(n1601), .CO(n1595), .S(n1618) );
ADDFHX2TS U1880 ( .A(n3605), .B(n3604), .CI(n3603), .CO(n3854), .S(n3600) );
ADDFHX2TS U1881 ( .A(n2418), .B(n2417), .CI(n2416), .CO(n2404), .S(n2428) );
ADDFHX4TS U1882 ( .A(n4920), .B(n4919), .CI(n4918), .CO(n4930), .S(n4935) );
OAI21XLTS U1883 ( .A0(n7600), .A1(n12), .B0(n7618), .Y(n7601) );
NOR2X4TS U1884 ( .A(n7603), .B(n7617), .Y(n5024) );
NOR2X4TS U1885 ( .A(n7295), .B(n7298), .Y(n7116) );
ADDFHX2TS U1886 ( .A(n3205), .B(n3204), .CI(n3203), .CO(n4837), .S(n3285) );
ADDFHX4TS U1887 ( .A(n4902), .B(n4901), .CI(n4900), .CO(n4925), .S(n4919) );
ADDFHX2TS U1888 ( .A(n2098), .B(n2097), .CI(n2096), .CO(n2084), .S(n2183) );
ADDFHX2TS U1889 ( .A(n1414), .B(n1413), .CI(n1412), .CO(n1426), .S(n1590) );
OAI22X1TS U1890 ( .A0(n4688), .A1(n6588), .B0(n4686), .B1(n1957), .Y(n1998)
);
OAI22X1TS U1891 ( .A0(n4688), .A1(n1956), .B0(n4230), .B1(n1961), .Y(n1999)
);
ADDFHX2TS U1892 ( .A(n2244), .B(n2243), .CI(n2242), .CO(n2268), .S(n2390) );
ADDFHX2TS U1893 ( .A(n5355), .B(n5354), .CI(n5353), .CO(n5458), .S(n5398) );
ADDFHX2TS U1894 ( .A(n4431), .B(n4430), .CI(n4429), .CO(n4465), .S(n4409) );
ADDFHX2TS U1895 ( .A(n3021), .B(n3020), .CI(n3019), .CO(n3229), .S(n3092) );
ADDFHX2TS U1896 ( .A(n5410), .B(n5409), .CI(n5408), .CO(n5512), .S(n5485) );
ADDFHX4TS U1897 ( .A(n2087), .B(n2086), .CI(n2085), .CO(n2127), .S(n2216) );
ADDFHX2TS U1898 ( .A(n2534), .B(n2533), .CI(n2532), .CO(n2768), .S(n2600) );
NOR2X4TS U1899 ( .A(n6965), .B(n6921), .Y(n7166) );
ADDFHX2TS U1900 ( .A(n3085), .B(n3084), .CI(n3083), .CO(n3166), .S(n3152) );
XNOR2X1TS U1901 ( .A(n1942), .B(n5383), .Y(n1823) );
ADDFHX2TS U1902 ( .A(n4813), .B(n4812), .CI(n4811), .CO(n4795), .S(n4885) );
ADDFHX2TS U1903 ( .A(n1883), .B(n1882), .CI(n1881), .CO(n2309), .S(n1878) );
ADDFHX2TS U1904 ( .A(n3693), .B(n3692), .CI(n3691), .CO(n3681), .S(n3819) );
ADDFX2TS U1905 ( .A(n5099), .B(n5098), .CI(n5097), .CO(n5201), .S(n5095) );
ADDFHX2TS U1906 ( .A(n4291), .B(n4290), .CI(n4289), .CO(n4328), .S(n4272) );
ADDFHX2TS U1907 ( .A(n1951), .B(n1950), .CI(n1949), .CO(n1831), .S(n2082) );
OAI22X2TS U1908 ( .A0(n4610), .A1(n2874), .B0(n5454), .B1(n3032), .Y(n2890)
);
ADDFHX2TS U1909 ( .A(n1363), .B(n1362), .CI(n1361), .CO(n1591), .S(n1450) );
ADDFHX2TS U1910 ( .A(n6452), .B(n6451), .CI(n6450), .CO(n6502), .S(n6498) );
OAI22X2TS U1911 ( .A0(n60), .A1(n1842), .B0(n6541), .B1(n2057), .Y(n2029) );
NOR2X2TS U1912 ( .A(n7698), .B(n7702), .Y(n7707) );
OAI22X2TS U1913 ( .A0(n2521), .A1(n2500), .B0(n5226), .B1(n2520), .Y(n2515)
);
OAI21XLTS U1914 ( .A0(n7687), .A1(n7365), .B0(n7361), .Y(n7364) );
ADDFHX2TS U1915 ( .A(n4119), .B(n4710), .CI(n4118), .CO(n4116), .S(n4720) );
ADDFHX2TS U1916 ( .A(n2540), .B(n2539), .CI(n2538), .CO(n2533), .S(n2596) );
ADDFHX2TS U1917 ( .A(n2569), .B(n2568), .CI(n2567), .CO(n2758), .S(n2598) );
ADDFX2TS U1918 ( .A(n2572), .B(n2571), .CI(n2570), .CO(n2798), .S(n2568) );
ADDFHX2TS U1919 ( .A(n1768), .B(n1767), .CI(n1766), .CO(n1777), .S(n1711) );
ADDFHX2TS U1920 ( .A(n4804), .B(n4803), .CI(n4802), .CO(n4867), .S(n4888) );
ADDFHX2TS U1921 ( .A(n4700), .B(n4699), .CI(n4698), .CO(n4803), .S(n4799) );
OAI22X1TS U1922 ( .A0(n4277), .A1(n3558), .B0(n49), .B1(n3350), .Y(n3363) );
ADDFHX2TS U1923 ( .A(n1978), .B(n1977), .CI(n1976), .CO(n2005), .S(n2123) );
ADDHXLTS U1924 ( .A(n1999), .B(n1998), .CO(n1977), .S(n2111) );
ADDFHX2TS U1925 ( .A(n928), .B(n927), .CI(n926), .CO(n449), .S(n954) );
ADDFHX2TS U1926 ( .A(n3136), .B(n3135), .CI(n3134), .CO(n3151), .S(n3114) );
ADDFHX2TS U1927 ( .A(n1600), .B(n1599), .CI(n1598), .CO(n1800), .S(n1798) );
ADDFHX2TS U1928 ( .A(n2747), .B(n2746), .CI(n2745), .CO(n3169), .S(n2766) );
ADDFHX2TS U1929 ( .A(n5768), .B(n5767), .CI(n5766), .CO(n5827), .S(n5764) );
ADDFHX2TS U1930 ( .A(n6678), .B(n6677), .CI(n6676), .CO(n6845), .S(n6842) );
XNOR2X1TS U1931 ( .A(n5815), .B(n3048), .Y(n3242) );
ADDFHX4TS U1932 ( .A(n2723), .B(n2722), .CI(n2721), .CO(n2728), .S(n2844) );
ADDFHX4TS U1933 ( .A(n5069), .B(n5068), .CI(n5067), .CO(n5156), .S(n5152) );
ADDFHX2TS U1934 ( .A(n2671), .B(n2670), .CI(n2669), .CO(n2716), .S(n2613) );
ADDFHX2TS U1935 ( .A(n3118), .B(n3117), .CI(n3116), .CO(n3302), .S(n3306) );
ADDFHX2TS U1936 ( .A(n6160), .B(n6159), .CI(n6158), .CO(n6164), .S(n6167) );
ADDFHX2TS U1937 ( .A(n4437), .B(n4436), .CI(n4435), .CO(n4537), .S(n4438) );
ADDFHX2TS U1938 ( .A(n3564), .B(n3563), .CI(n3562), .CO(n3863), .S(n3605) );
ADDFHX2TS U1939 ( .A(n4926), .B(n4925), .CI(n4924), .CO(n4921), .S(n4941) );
XNOR2X1TS U1940 ( .A(n1896), .B(n3073), .Y(n2071) );
OAI22X2TS U1941 ( .A0(n4575), .A1(n3236), .B0(n4573), .B1(n4574), .Y(n4753)
);
BUFX8TS U1942 ( .A(n2345), .Y(n4573) );
ADDFHX2TS U1943 ( .A(n3972), .B(n3971), .CI(n3970), .CO(n3968), .S(n4143) );
OAI22X2TS U1944 ( .A0(n130), .A1(n4095), .B0(n4096), .B1(n3999), .Y(n4129)
);
ADDFHX2TS U1945 ( .A(n377), .B(n376), .CI(n375), .CO(n363), .S(n434) );
ADDFHX4TS U1946 ( .A(n5734), .B(n5733), .CI(n5732), .CO(n5851), .S(n5778) );
ADDFHX2TS U1947 ( .A(n5771), .B(n5770), .CI(n5769), .CO(n5830), .S(n5733) );
ADDFHX2TS U1948 ( .A(n5248), .B(n5247), .CI(n5246), .CO(n5358), .S(n5245) );
ADDFHX2TS U1949 ( .A(n1303), .B(n1302), .CI(n1301), .CO(n1321), .S(n1323) );
ADDFHX2TS U1950 ( .A(n1309), .B(n1308), .CI(n1307), .CO(n1301), .S(n1314) );
ADDFHX2TS U1951 ( .A(n2271), .B(n2270), .CI(n2269), .CO(n2680), .S(n2308) );
ADDFHX2TS U1952 ( .A(n4585), .B(n4584), .CI(n4583), .CO(n4631), .S(n4629) );
OAI22X2TS U1953 ( .A0(n6148), .A1(n2501), .B0(n4230), .B1(n2530), .Y(n2514)
);
ADDFHX2TS U1954 ( .A(n1255), .B(n1254), .CI(n1253), .CO(n1263), .S(n1298) );
CLKINVX1TS U1955 ( .A(n7253), .Y(n7761) );
ADDFHX2TS U1956 ( .A(n2265), .B(n2264), .CI(n2263), .CO(n2242), .S(n2392) );
ADDFHX2TS U1957 ( .A(n2235), .B(n2234), .CI(n2233), .CO(n2264), .S(n2374) );
ADDFHX2TS U1958 ( .A(n2051), .B(n2050), .CI(n2049), .CO(n2305), .S(n2023) );
ADDFHX2TS U1959 ( .A(n568), .B(n567), .CI(n566), .CO(n981), .S(n569) );
AOI21X2TS U1960 ( .A0(n7212), .A1(n7217), .B0(n1005), .Y(n1006) );
INVX2TS U1961 ( .A(n7222), .Y(n7212) );
OAI22X1TS U1962 ( .A0(n6252), .A1(n1990), .B0(n5144), .B1(n1857), .Y(n1820)
);
OAI22X1TS U1963 ( .A0(n5621), .A1(n6183), .B0(n6251), .B1(n6250), .Y(n6263)
);
OAI22X2TS U1964 ( .A0(n7093), .A1(n3049), .B0(n5753), .B1(n3242), .Y(n3270)
);
ADDFHX2TS U1965 ( .A(n2336), .B(n2335), .CI(n2334), .CO(n2603), .S(n2307) );
ADDFHX2TS U1966 ( .A(n2621), .B(n2620), .CI(n2619), .CO(n2662), .S(n2602) );
OAI22X2TS U1967 ( .A0(n4599), .A1(n3027), .B0(n5659), .B1(n3212), .Y(n3244)
);
NAND2BXLTS U1968 ( .AN(n2864), .B(n6520), .Y(n1868) );
ADDFHX2TS U1969 ( .A(n2388), .B(n2387), .CI(n2386), .CO(n2394), .S(n2416) );
ADDFHX2TS U1970 ( .A(n3052), .B(n3051), .CI(n3050), .CO(n3286), .S(n3123) );
ADDFHX2TS U1971 ( .A(n1582), .B(n1581), .CI(n1580), .CO(n1578), .S(n1615) );
ADDFX2TS U1972 ( .A(n1569), .B(n1568), .CI(n1567), .CO(n1562), .S(n1581) );
AO21XLTS U1973 ( .A0(n4375), .A1(n51), .B0(n5119), .Y(n5176) );
ADDFHX2TS U1974 ( .A(n3235), .B(n3234), .CI(n3233), .CO(n4780), .S(n3230) );
XOR2X4TS U1975 ( .A(Data_A_i[8]), .B(n2343), .Y(n198) );
ADDFHX2TS U1976 ( .A(n3666), .B(n3665), .CI(n3664), .CO(n3678), .S(n3798) );
ADDFHX2TS U1977 ( .A(n2612), .B(n2611), .CI(n2610), .CO(n2617), .S(n2676) );
ADDFHX2TS U1978 ( .A(n4950), .B(n4949), .CI(n4948), .CO(n4020), .S(n4988) );
OAI21X1TS U1979 ( .A0(n7128), .A1(n7123), .B0(n7129), .Y(n6804) );
ADDFHX2TS U1980 ( .A(n2609), .B(n2608), .CI(n2607), .CO(n2618), .S(n2601) );
ADDFHX4TS U1981 ( .A(n3112), .B(n3111), .CI(n3110), .CO(n3304), .S(n3307) );
ADDFHX2TS U1982 ( .A(n2768), .B(n2767), .CI(n2766), .CO(n3112), .S(n2744) );
ADDFHX2TS U1983 ( .A(n6273), .B(n6272), .CI(n6271), .CO(n6294), .S(n6255) );
ADDFHX2TS U1984 ( .A(n2606), .B(n2605), .CI(n2604), .CO(n2725), .S(n2734) );
ADDFHX2TS U1985 ( .A(n2585), .B(n2584), .CI(n2583), .CO(n2606), .S(n2678) );
ADDFHX2TS U1986 ( .A(n5300), .B(n5299), .CI(n5298), .CO(n5355), .S(n5295) );
ADDFHX2TS U1987 ( .A(n5175), .B(n5174), .CI(n5173), .CO(n5300), .S(n5167) );
ADDFHX2TS U1988 ( .A(n5271), .B(n5270), .CI(n5269), .CO(n5327), .S(n5298) );
ADDFHX2TS U1989 ( .A(n5361), .B(n5360), .CI(n5359), .CO(n5483), .S(n5357) );
NOR2X4TS U1990 ( .A(n1335), .B(n1334), .Y(n7708) );
AOI21X2TS U1991 ( .A0(n6869), .A1(n6970), .B0(n6868), .Y(n6899) );
ADDFHX2TS U1992 ( .A(n2762), .B(n2761), .CI(n2760), .CO(n3182), .S(n2764) );
OAI22X2TS U1993 ( .A0(n2464), .A1(n3028), .B0(n84), .B1(n3253), .Y(n3245) );
ADDFHX2TS U1994 ( .A(n4560), .B(n4559), .CI(n4558), .CO(n4810), .S(n4806) );
ADDFHX2TS U1995 ( .A(n4261), .B(n4260), .CI(n4259), .CO(n4358), .S(n4302) );
ADDFHX2TS U1996 ( .A(n3139), .B(n3138), .CI(n3137), .CO(n3292), .S(n3150) );
ADDFHX2TS U1997 ( .A(n2492), .B(n2490), .CI(n2491), .CO(n2673), .S(n2619) );
ADDFHX4TS U1998 ( .A(n2406), .B(n2405), .CI(n2404), .CO(n2411), .S(n2413) );
ADDFHX2TS U1999 ( .A(n6037), .B(n6036), .CI(n6035), .CO(n6132), .S(n6021) );
ADDFHX2TS U2000 ( .A(n5257), .B(n5256), .CI(n5255), .CO(n5360), .S(n5299) );
ADDFHX2TS U2001 ( .A(n2327), .B(n2326), .CI(n2325), .CO(n2611), .S(n2273) );
ADDFHX4TS U2002 ( .A(n3304), .B(n3303), .CI(n3302), .CO(n3173), .S(n3316) );
ADDFHX2TS U2003 ( .A(n1606), .B(n1605), .CI(n1604), .CO(n1627), .S(n1623) );
ADDFHX2TS U2004 ( .A(n3219), .B(n3218), .CI(n3217), .CO(n4671), .S(n3204) );
ADDFHX4TS U2005 ( .A(n3313), .B(n3312), .CI(n3311), .CO(n3333), .S(n3332) );
ADDFHX2TS U2006 ( .A(n2318), .B(n2317), .CI(n2316), .CO(n2732), .S(n2313) );
ADDFHX2TS U2007 ( .A(n1909), .B(n1908), .CI(n1907), .CO(n2317), .S(n1879) );
ADDFHX2TS U2008 ( .A(n1906), .B(n1905), .CI(n1904), .CO(n2318), .S(n2022) );
NOR2X2TS U2009 ( .A(n7727), .B(n7743), .Y(n992) );
ADDFHX2TS U2010 ( .A(n5245), .B(n5244), .CI(n5243), .CO(n5403), .S(n5319) );
ADDFHX2TS U2011 ( .A(n5241), .B(n5240), .CI(n5239), .CO(n5243), .S(n5158) );
OAI22X2TS U2012 ( .A0(n6993), .A1(n6112), .B0(n6111), .B1(n6214), .Y(n6191)
);
ADDFHX2TS U2013 ( .A(n4774), .B(n4773), .CI(n4772), .CO(n4653), .S(n4858) );
ADDFHX2TS U2014 ( .A(n1525), .B(n1524), .CI(n1523), .CO(n1783), .S(n1596) );
ADDFHX2TS U2015 ( .A(n5512), .B(n5511), .CI(n5510), .CO(n5590), .S(n5640) );
ADDFHX2TS U2016 ( .A(n3752), .B(n3751), .CI(n3750), .CO(n3777), .S(n3969) );
ADDFHX2TS U2017 ( .A(n323), .B(n322), .CI(n321), .CO(n341), .S(n382) );
ADDFHX2TS U2018 ( .A(n6079), .B(n6078), .CI(n6077), .CO(n6153), .S(n6092) );
ADDFHX2TS U2019 ( .A(n5877), .B(n5876), .CI(n5875), .CO(n6078), .S(n5869) );
NOR2X2TS U2020 ( .A(n7313), .B(n7683), .Y(n7199) );
OAI22X1TS U2021 ( .A0(n5817), .A1(n4003), .B0(n3357), .B1(n3782), .Y(n3938)
);
OAI22X1TS U2022 ( .A0(n4691), .A1(n3737), .B0(n139), .B1(n3505), .Y(n3720)
);
OAI21XLTS U2023 ( .A0(n7077), .A1(n7076), .B0(n7075), .Y(n7078) );
ADDFHX2TS U2024 ( .A(n6675), .B(n6674), .CI(n6673), .CO(n6843), .S(n6841) );
NOR2X4TS U2025 ( .A(n6809), .B(n6808), .Y(n7110) );
NAND2X2TS U2026 ( .A(n894), .B(n893), .Y(n7758) );
ADDFHX2TS U2027 ( .A(n1252), .B(n1251), .CI(n1250), .CO(n1254), .S(n1283) );
ADDFHX2TS U2028 ( .A(n5129), .B(n5128), .CI(n5127), .CO(n5159), .S(n5064) );
ADDFHX4TS U2029 ( .A(n3175), .B(n3174), .CI(n3173), .CO(n3300), .S(n3312) );
XOR2X1TS U2030 ( .A(n4424), .B(n4425), .Y(n4248) );
ADDFHX2TS U2031 ( .A(n2394), .B(n2393), .CI(n2392), .CO(n2389), .S(n2415) );
ADDFHX2TS U2032 ( .A(n6503), .B(n6502), .CI(n6501), .CO(n6834), .S(n6832) );
NAND2X4TS U2033 ( .A(n7680), .B(n7665), .Y(n2445) );
ADDFHX2TS U2034 ( .A(n2008), .B(n2007), .CI(n2006), .CO(n2045), .S(n2004) );
ADDHX1TS U2035 ( .A(n1983), .B(n1982), .CO(n1890), .S(n2007) );
NAND2X4TS U2036 ( .A(n2036), .B(n5527), .Y(n5883) );
ADDFHX2TS U2037 ( .A(n4721), .B(n4720), .CI(n4719), .CO(n4772), .S(n4776) );
ADDFHX2TS U2038 ( .A(n3193), .B(n3192), .CI(n3191), .CO(n4729), .S(n3185) );
ADDFHX2TS U2039 ( .A(n3489), .B(n3488), .CI(n3487), .CO(n3864), .S(n3703) );
ADDFHX2TS U2040 ( .A(n2798), .B(n2797), .CI(n2796), .CO(n3162), .S(n2757) );
ADDFHX2TS U2041 ( .A(n4850), .B(n4849), .CI(n4848), .CO(n4865), .S(n4814) );
BUFX8TS U2042 ( .A(n5714), .Y(n3026) );
ADDFX2TS U2043 ( .A(n4190), .B(n4189), .CI(n4188), .CO(n4297), .S(n4269) );
ADDFHX2TS U2044 ( .A(n5634), .B(n5633), .CI(n5632), .CO(n5705), .S(n5636) );
ADDFHX2TS U2045 ( .A(n5075), .B(n5074), .CI(n5073), .CO(n5172), .S(n5133) );
ADDFHX2TS U2046 ( .A(n6178), .B(n6177), .CI(n6176), .CO(n6273), .S(n6203) );
ADDFHX2TS U2047 ( .A(n3181), .B(n3180), .CI(n3179), .CO(n3170), .S(n3309) );
ADDFHX2TS U2048 ( .A(n4013), .B(n4012), .CI(n4011), .CO(n4149), .S(n4948) );
ADDFHX2TS U2049 ( .A(n4810), .B(n4809), .CI(n4808), .CO(n4816), .S(n4886) );
ADDFHX2TS U2050 ( .A(n4588), .B(n4587), .CI(n4586), .CO(n4628), .S(n4809) );
ADDFHX2TS U2051 ( .A(n2027), .B(n2026), .CI(n2025), .CO(n2360), .S(n2152) );
ADDFHX2TS U2052 ( .A(n973), .B(n972), .CI(n971), .CO(n978), .S(n980) );
ADDFHX2TS U2053 ( .A(n718), .B(n717), .CI(n716), .CO(n902), .S(n898) );
ADDFHX2TS U2054 ( .A(n676), .B(n675), .CI(n674), .CO(n717), .S(n719) );
BUFX4TS U2055 ( .A(n4422), .Y(n6252) );
ADDFHX4TS U2056 ( .A(n4178), .B(n4177), .CI(n4176), .CO(n3825), .S(n4186) );
ADDFHX2TS U2057 ( .A(n3823), .B(n3822), .CI(n3821), .CO(n4176), .S(n4170) );
ADDFHX2TS U2058 ( .A(n5646), .B(n5645), .CI(n5644), .CO(n5765), .S(n5707) );
OAI22X1TS U2059 ( .A0(n2967), .A1(n2107), .B0(n2108), .B1(n1925), .Y(n2141)
);
ADDFHX2TS U2060 ( .A(n4825), .B(n4824), .CI(n4823), .CO(n4852), .S(n4812) );
ADDFHX2TS U2061 ( .A(n4242), .B(n4241), .CI(n4240), .CO(n4434), .S(n4267) );
ADDFHX2TS U2062 ( .A(n1404), .B(n1403), .CI(n1402), .CO(n1548), .S(n1413) );
OAI22X2TS U2063 ( .A0(n5549), .A1(n3057), .B0(n4686), .B1(n3215), .Y(n3218)
);
ADDFHX2TS U2064 ( .A(n2816), .B(n2815), .CI(n2814), .CO(n3105), .S(n2770) );
BUFX8TS U2065 ( .A(n3365), .Y(n6525) );
ADDFHX2TS U2066 ( .A(n602), .B(n601), .CI(n600), .CO(n908), .S(n905) );
ADDFHX2TS U2067 ( .A(n598), .B(n597), .CI(n596), .CO(n570), .S(n600) );
ADDFHX2TS U2068 ( .A(n3088), .B(n3087), .CI(n3086), .CO(n3165), .S(n3153) );
ADDFHX2TS U2069 ( .A(n2993), .B(n2992), .CI(n2991), .CO(n3144), .S(n3087) );
ADDFHX2TS U2070 ( .A(n4724), .B(n4723), .CI(n4722), .CO(n4775), .S(n4802) );
ADDFHX2TS U2071 ( .A(n5327), .B(n5326), .CI(n5325), .CO(n5486), .S(n5356) );
OAI22X2TS U2072 ( .A0(n4375), .A1(n4278), .B0(n51), .B1(n4374), .Y(n4424) );
ADDFHX2TS U2073 ( .A(n3446), .B(n3445), .CI(n3444), .CO(n3865), .S(n3671) );
ADDFHX2TS U2074 ( .A(n4801), .B(n4800), .CI(n4799), .CO(n4889), .S(n4725) );
ADDFHX2TS U2075 ( .A(n1579), .B(n1578), .CI(n1577), .CO(n1781), .S(n1600) );
NAND2X2TS U2076 ( .A(n6801), .B(n6800), .Y(n7123) );
ADDFHX2TS U2077 ( .A(n6500), .B(n6499), .CI(n6498), .CO(n6833), .S(n6827) );
ADDFHX2TS U2078 ( .A(n6332), .B(n6331), .CI(n6330), .CO(n6499), .S(n6373) );
ADDFHX2TS U2079 ( .A(n4326), .B(n4325), .CI(n4324), .CO(n4411), .S(n4299) );
ADDFHX4TS U2080 ( .A(n3854), .B(n3853), .CI(n3852), .CO(n4451), .S(n3916) );
ADDFHX2TS U2081 ( .A(n2241), .B(n2240), .CI(n2239), .CO(n2243), .S(n2368) );
ADDFHX2TS U2082 ( .A(n2172), .B(n2171), .CI(n2170), .CO(n2207), .S(n2241) );
ADDFHX2TS U2083 ( .A(n2515), .B(n2514), .CI(n2513), .CO(n2771), .S(n2534) );
XNOR2X1TS U2084 ( .A(n3042), .B(Data_B_i[53]), .Y(n3274) );
ADDFHX2TS U2085 ( .A(n4130), .B(n4129), .CI(n4128), .CO(n4025), .S(n4632) );
NOR2XLTS U2086 ( .A(n7292), .B(n7295), .Y(n7297) );
BUFX8TS U2087 ( .A(n6655), .Y(n5753) );
ADDFHX2TS U2088 ( .A(n2831), .B(n2830), .CI(n2829), .CO(n3107), .S(n2833) );
ADDFHX2TS U2089 ( .A(n2499), .B(n2498), .CI(n2497), .CO(n2829), .S(n2580) );
ADDFHX2TS U2090 ( .A(n571), .B(n570), .CI(n569), .CO(n910), .S(n909) );
AOI21X2TS U2091 ( .A0(n6839), .A1(n6946), .B0(n6838), .Y(n6911) );
ADDFHX2TS U2092 ( .A(n2849), .B(n2848), .CI(n2847), .CO(n2857), .S(n2853) );
ADDFHX2TS U2093 ( .A(n2732), .B(n2731), .CI(n2730), .CO(n2852), .S(n2848) );
ADDFHX2TS U2094 ( .A(n4288), .B(n4286), .CI(n4287), .CO(n4329), .S(n4189) );
ADDFHX4TS U2095 ( .A(n4815), .B(n4816), .CI(n4814), .CO(n4877), .S(n4870) );
ADDFHX2TS U2096 ( .A(n4629), .B(n4628), .CI(n4627), .CO(n4656), .S(n4815) );
ADDFHX2TS U2097 ( .A(n3232), .B(n3231), .CI(n3230), .CO(n4733), .S(n3284) );
ADDFHX2TS U2098 ( .A(n2843), .B(n2842), .CI(n2841), .CO(n3324), .S(n3323) );
ADDFHX2TS U2099 ( .A(n1786), .B(n1785), .CI(n1784), .CO(n1805), .S(n1804) );
ADDFHX2TS U2100 ( .A(n1783), .B(n1782), .CI(n1781), .CO(n1784), .S(n1787) );
ADDFHX2TS U2101 ( .A(n6375), .B(n6374), .CI(n6373), .CO(n6826), .S(n6825) );
BUFX12TS U2102 ( .A(n1825), .Y(n6589) );
ADDFHX2TS U2103 ( .A(n4756), .B(n4755), .CI(n4754), .CO(n4782), .S(n4670) );
ADDFHX2TS U2104 ( .A(n6672), .B(n6671), .CI(n6670), .CO(n6840), .S(n6837) );
ADDFHX2TS U2105 ( .A(n964), .B(n963), .CI(n962), .CO(n948), .S(n965) );
NOR2X4TS U2106 ( .A(n6789), .B(n6788), .Y(n7144) );
NAND2X4TS U2107 ( .A(n2861), .B(n2862), .Y(n6485) );
AOI21X4TS U2108 ( .A0(n916), .A1(n7233), .B0(n915), .Y(n7230) );
NOR2X2TS U2109 ( .A(n914), .B(n7243), .Y(n916) );
ADDFHX2TS U2110 ( .A(n1563), .B(n1562), .CI(n1561), .CO(n1708), .S(n1579) );
ADDFHX2TS U2111 ( .A(n6169), .B(n6168), .CI(n6167), .CO(n6808), .S(n6807) );
ADDFHX2TS U2112 ( .A(n3292), .B(n3291), .CI(n3290), .CO(n4912), .S(n3295) );
ADDFHX2TS U2113 ( .A(n5406), .B(n5405), .CI(n5404), .CO(n5407), .S(n6784) );
ADDFHX2TS U2114 ( .A(n5924), .B(n5923), .CI(n5922), .CO(n6802), .S(n6801) );
NOR2X4TS U2115 ( .A(n3336), .B(n3335), .Y(n7184) );
ADDFHX2TS U2116 ( .A(n4062), .B(n4061), .CI(n4060), .CO(n4992), .S(n4967) );
ADDFHX2TS U2117 ( .A(n4497), .B(n4496), .CI(n4495), .CO(n5072), .S(n4493) );
ADDFHX2TS U2118 ( .A(n4736), .B(n4735), .CI(n4734), .CO(n4813), .S(n4797) );
ADDFHX2TS U2119 ( .A(n967), .B(n966), .CI(n965), .CO(n987), .S(n986) );
ADDFHX2TS U2120 ( .A(n976), .B(n975), .CI(n974), .CO(n966), .S(n977) );
ADDFHX2TS U2121 ( .A(n4665), .B(n4664), .CI(n4663), .CO(n4062), .S(n4946) );
ADDFHX2TS U2122 ( .A(n4656), .B(n4655), .CI(n4654), .CO(n4966), .S(n4875) );
ADDFHX2TS U2123 ( .A(n282), .B(n281), .CI(n280), .CO(n1281), .S(n295) );
ADDFHX2TS U2124 ( .A(n2315), .B(n2314), .CI(n2313), .CO(n2849), .S(n2311) );
ADDFHX2TS U2125 ( .A(n1880), .B(n1879), .CI(n1878), .CO(n2315), .S(n2126) );
NAND2X2TS U2126 ( .A(n6835), .B(n6834), .Y(n6955) );
ADDFHX2TS U2127 ( .A(n6497), .B(n6496), .CI(n6495), .CO(n6836), .S(n6835) );
ADDFHX2TS U2128 ( .A(n946), .B(n945), .CI(n944), .CO(n918), .S(n947) );
ADDFHX2TS U2129 ( .A(n4065), .B(n4064), .CI(n4063), .CO(n4024), .S(n4856) );
ADDFHX2TS U2130 ( .A(n3229), .B(n3228), .CI(n3227), .CO(n4902), .S(n3279) );
XOR2X1TS U2131 ( .A(n1086), .B(n1087), .Y(n189) );
OAI22X1TS U2132 ( .A0(n5894), .A1(n187), .B0(n134), .B1(n1129), .Y(n1086) );
BUFX8TS U2133 ( .A(n6399), .Y(n3933) );
ADDFHX2TS U2134 ( .A(n3578), .B(n3577), .CI(n3576), .CO(n3630), .S(n3520) );
OAI21X2TS U2135 ( .A0(n7361), .A1(n1809), .B0(n1808), .Y(n1810) );
ADDFHX2TS U2136 ( .A(n3154), .B(n3153), .CI(n3152), .CO(n3178), .S(n3111) );
ADDFHX2TS U2137 ( .A(n3178), .B(n3177), .CI(n3176), .CO(n3171), .S(n3310) );
ADDFHX2TS U2138 ( .A(n3160), .B(n3159), .CI(n3158), .CO(n3149), .S(n3176) );
ADDHX1TS U2139 ( .A(n420), .B(n419), .CO(n450), .S(n936) );
ADDFHX2TS U2140 ( .A(n4461), .B(n4460), .CI(n4459), .CO(n5065), .S(n4538) );
ADDFHX2TS U2141 ( .A(n4434), .B(n4433), .CI(n4432), .CO(n4459), .S(n4436) );
ADDFHX2TS U2142 ( .A(n4467), .B(n4466), .CI(n4465), .CO(n5128), .S(n4460) );
OAI21X2TS U2143 ( .A0(n914), .A1(n7242), .B0(n913), .Y(n915) );
NAND2X2TS U2144 ( .A(n21), .B(n7245), .Y(n914) );
NOR2X4TS U2145 ( .A(n5022), .B(n5021), .Y(n7603) );
ADDFHX2TS U2146 ( .A(n3518), .B(n3517), .CI(n3516), .CO(n3672), .S(n3673) );
ADDFHX2TS U2147 ( .A(n3537), .B(n3536), .CI(n3535), .CO(n3606), .S(n3518) );
ADDFHX2TS U2148 ( .A(n1276), .B(n1275), .CI(n1274), .CO(n1288), .S(n1302) );
ADDFHX2TS U2149 ( .A(n4914), .B(n4913), .CI(n4912), .CO(n4932), .S(n4928) );
XNOR2X1TS U2150 ( .A(n616), .B(Data_B_i[21]), .Y(n401) );
ADDFHX2TS U2151 ( .A(n429), .B(n428), .CI(n427), .CO(n386), .S(n430) );
NAND2X2TS U2152 ( .A(n6845), .B(n6844), .Y(n7487) );
ADDFHX2TS U2153 ( .A(n6628), .B(n6627), .CI(n6626), .CO(n6846), .S(n6844) );
ADDFHX4TS U2154 ( .A(n5324), .B(n5323), .CI(n5322), .CO(n6779), .S(n6777) );
ADDFHX4TS U2155 ( .A(n5163), .B(n5162), .CI(n5161), .CO(n5323), .S(n5155) );
ADDFHX4TS U2156 ( .A(n5783), .B(n5782), .CI(n5781), .CO(n6798), .S(n6797) );
ADDFHX2TS U2157 ( .A(n4059), .B(n4058), .CI(n4057), .CO(n4015), .S(n4144) );
NAND2X2TS U2158 ( .A(n996), .B(n995), .Y(n7719) );
ADDFHX2TS U2159 ( .A(n2489), .B(n2488), .CI(n2487), .CO(n2674), .S(n2670) );
OAI22X2TS U2160 ( .A0(n128), .A1(n2299), .B0(n4400), .B1(n2510), .Y(n2488)
);
NOR2X2TS U2161 ( .A(n896), .B(n895), .Y(n7762) );
ADDFHX4TS U2162 ( .A(n2677), .B(n2676), .CI(n2675), .CO(n2722), .S(n2731) );
ADDFHX2TS U2163 ( .A(n1630), .B(n1629), .CI(n1628), .CO(n1795), .S(n1794) );
ADDFHX2TS U2164 ( .A(n1624), .B(n1623), .CI(n1622), .CO(n1629), .S(n1631) );
ADDFHX2TS U2165 ( .A(n4350), .B(n4349), .CI(n4348), .CO(n4439), .S(n4543) );
OAI21X2TS U2166 ( .A0(n7603), .A1(n7618), .B0(n7604), .Y(n5023) );
NAND2X2TS U2167 ( .A(n3321), .B(n3320), .Y(n7633) );
ADDFHX2TS U2168 ( .A(n2858), .B(n2857), .CI(n2856), .CO(n3322), .S(n3321) );
ADDFHX4TS U2169 ( .A(n4022), .B(n4021), .CI(n4020), .CO(n4153), .S(n4990) );
NAND2X2TS U2170 ( .A(n7217), .B(n7223), .Y(n1007) );
ADDFHX2TS U2171 ( .A(n6225), .B(n6224), .CI(n6223), .CO(n6821), .S(n6819) );
ADDFHX2TS U2172 ( .A(n2665), .B(n2664), .CI(n2663), .CO(n2845), .S(n2736) );
ADDFHX2TS U2173 ( .A(n2309), .B(n2308), .CI(n2307), .CO(n2663), .S(n2314) );
ADDFHX2TS U2174 ( .A(n2220), .B(n2219), .CI(n2218), .CO(n2362), .S(n2221) );
ADDFHX2TS U2175 ( .A(n3851), .B(n3850), .CI(n3849), .CO(n4206), .S(n3856) );
ADDFHX2TS U2176 ( .A(n4208), .B(n4207), .CI(n4206), .CO(n4350), .S(n4342) );
ADDFHX2TS U2177 ( .A(n2888), .B(n2887), .CI(n2886), .CO(n3187), .S(n3138) );
NAND2X4TS U2178 ( .A(n170), .B(n3990), .Y(n4052) );
NAND2X4TS U2179 ( .A(n2470), .B(n6487), .Y(n6319) );
ADDFHX2TS U2180 ( .A(n4539), .B(n4538), .CI(n4537), .CO(n5067), .S(n4489) );
ADDFHX2TS U2181 ( .A(n5352), .B(n5351), .CI(n5350), .CO(n5484), .S(n5354) );
ADDFHX2TS U2182 ( .A(n5318), .B(n5317), .CI(n5316), .CO(n5353), .S(n5244) );
OAI22X2TS U2183 ( .A0(n4006), .A1(n4005), .B0(n3213), .B1(n3783), .Y(n3937)
);
OAI21X1TS U2184 ( .A0(n7524), .A1(n7514), .B0(n7525), .Y(n5055) );
ADDFHX2TS U2185 ( .A(n4184), .B(n4183), .CI(n4182), .CO(n5041), .S(n5040) );
ADDFHX4TS U2186 ( .A(n4181), .B(n4180), .CI(n4179), .CO(n4183), .S(n4185) );
ADDFHX2TS U2187 ( .A(n3151), .B(n3150), .CI(n3149), .CO(n3281), .S(n3172) );
XOR2X4TS U2188 ( .A(n1788), .B(n1789), .Y(n1576) );
ADDFHX2TS U2189 ( .A(n6172), .B(n6171), .CI(n6170), .CO(n6818), .S(n6812) );
ADDFHX2TS U2190 ( .A(n6103), .B(n6102), .CI(n6101), .CO(n6171), .S(n6095) );
ADDFHX2TS U2191 ( .A(n2588), .B(n2587), .CI(n2586), .CO(n2644), .S(n2620) );
NOR2X4TS U2192 ( .A(n7627), .B(n7580), .Y(n5034) );
ADDFHX4TS U2193 ( .A(n2424), .B(n2423), .CI(n2422), .CO(n2414), .S(n2426) );
ADDFHX4TS U2194 ( .A(n2400), .B(n2399), .CI(n2398), .CO(n2405), .S(n2423) );
NAND2X4TS U2195 ( .A(n196), .B(n162), .Y(n2892) );
ADDFHX2TS U2196 ( .A(n5710), .B(n5709), .CI(n5708), .CO(n6796), .S(n6790) );
ADDFHX2TS U2197 ( .A(n5707), .B(n5706), .CI(n5705), .CO(n5781), .S(n5708) );
NOR2X4TS U2198 ( .A(n5020), .B(n5019), .Y(n7617) );
OAI21X1TS U2199 ( .A0(n6960), .A1(n6955), .B0(n6961), .Y(n6838) );
ADDFHX4TS U2200 ( .A(n5637), .B(n5636), .CI(n5635), .CO(n6791), .S(n6789) );
ADDFHX2TS U2201 ( .A(n5640), .B(n5639), .CI(n5638), .CO(n6788), .S(n5487) );
NAND2X4TS U2202 ( .A(n173), .B(n5293), .Y(n1516) );
ADDFHX2TS U2203 ( .A(n4730), .B(n4729), .CI(n4728), .CO(n4898), .S(n4892) );
ADDFHX2TS U2204 ( .A(n5524), .B(n5523), .CI(n5522), .CO(n5614), .S(n5553) );
ADDFHX2TS U2205 ( .A(n5157), .B(n5156), .CI(n5155), .CO(n6776), .S(n6775) );
ADDFHX2TS U2206 ( .A(n3172), .B(n3171), .CI(n3170), .CO(n3296), .S(n3313) );
ADDFHX2TS U2207 ( .A(n3310), .B(n3309), .CI(n3308), .CO(n3311), .S(n3314) );
ADDFHX2TS U2208 ( .A(n3265), .B(n3264), .CI(n3263), .CO(n4801), .S(n3231) );
NAND2X2TS U2209 ( .A(n3334), .B(n3333), .Y(n7383) );
OAI21X4TS U2210 ( .A0(n7610), .A1(n7390), .B0(n7611), .Y(n7615) );
NAND2X4TS U2211 ( .A(n5016), .B(n5015), .Y(n7390) );
NAND2X2TS U2212 ( .A(n5018), .B(n5017), .Y(n7611) );
XNOR2X1TS U2213 ( .A(n1942), .B(n5465), .Y(n1845) );
AOI21X1TS U2214 ( .A0(n7408), .A1(n7407), .B0(n7406), .Y(n7417) );
NAND2X4TS U2215 ( .A(n6815), .B(n7407), .Y(n6817) );
ADDFHX2TS U2216 ( .A(n3024), .B(n3023), .CI(n3022), .CO(n3259), .S(n3125) );
ADDFHX2TS U2217 ( .A(n2289), .B(n2288), .CI(n2287), .CO(n2737), .S(n2359) );
ADDFHX2TS U2218 ( .A(n2045), .B(n2044), .CI(n2043), .CO(n2288), .S(n2025) );
ADDFHX2TS U2219 ( .A(n4641), .B(n4640), .CI(n4639), .CO(n4028), .S(n4661) );
ADDFHX2TS U2220 ( .A(n432), .B(n431), .CI(n430), .CO(n997), .S(n996) );
ADDFHX2TS U2221 ( .A(n387), .B(n386), .CI(n385), .CO(n1001), .S(n998) );
ADDFHX2TS U2222 ( .A(n979), .B(n978), .CI(n977), .CO(n985), .S(n984) );
ADDFHX2TS U2223 ( .A(n6142), .B(n6141), .CI(n6140), .CO(n6218), .S(n6150) );
ADDFHX2TS U2224 ( .A(n5321), .B(n5320), .CI(n5319), .CO(n5401), .S(n5322) );
ADDFHX4TS U2225 ( .A(n5400), .B(n5399), .CI(n5398), .CO(n5404), .S(n5402) );
ADDFHX2TS U2226 ( .A(n5500), .B(n5499), .CI(n5498), .CO(n5576), .S(n5502) );
ADDFHX2TS U2227 ( .A(n2339), .B(n2338), .CI(n2337), .CO(n2621), .S(n2270) );
ADDFHX2TS U2228 ( .A(n4868), .B(n4867), .CI(n4866), .CO(n4872), .S(n4895) );
ADDFHX2TS U2229 ( .A(n2005), .B(n2004), .CI(n2003), .CO(n2026), .S(n2149) );
NOR2X4TS U2230 ( .A(n1333), .B(n1332), .Y(n7702) );
ADDFHX2TS U2231 ( .A(n1322), .B(n1321), .CI(n1320), .CO(n1334), .S(n1333) );
ADDFHX4TS U2232 ( .A(n3602), .B(n3601), .CI(n3600), .CO(n3917), .S(n3701) );
ADDFHX2TS U2233 ( .A(n4356), .B(n4355), .CI(n4354), .CO(n4494), .S(n4352) );
ADDFHX2TS U2234 ( .A(n3672), .B(n3671), .CI(n3670), .CO(n3831), .S(n3826) );
ADDFHX2TS U2235 ( .A(n3678), .B(n3677), .CI(n3676), .CO(n3670), .S(n4177) );
NOR2X2TS U2236 ( .A(n6956), .B(n6960), .Y(n6839) );
ADDFHX2TS U2237 ( .A(n4887), .B(n4886), .CI(n4885), .CO(n4871), .S(n4917) );
ADDFHX2TS U2238 ( .A(n4807), .B(n4806), .CI(n4805), .CO(n4887), .S(n4731) );
ADDFHX2TS U2239 ( .A(n2412), .B(n2411), .CI(n2410), .CO(n2440), .S(n2439) );
ADDFHX2TS U2240 ( .A(n3121), .B(n3120), .CI(n3119), .CO(n3298), .S(n3174) );
ADDFHX2TS U2241 ( .A(n3115), .B(n3114), .CI(n3113), .CO(n3119), .S(n3303) );
INVX2TS U2242 ( .A(n4979), .Y(n4975) );
ADDFHX2TS U2243 ( .A(n5897), .B(n5896), .CI(n5895), .CO(n6162), .S(n5922) );
OAI21X4TS U2244 ( .A0(n7298), .A1(n7293), .B0(n7299), .Y(n7115) );
NAND2X4TS U2245 ( .A(n6797), .B(n6796), .Y(n7293) );
ADDFHX4TS U2246 ( .A(n4449), .B(n4448), .CI(n4447), .CO(n4443), .S(n4547) );
ADDFHX2TS U2247 ( .A(n4297), .B(n4296), .CI(n4295), .CO(n4440), .S(n4447) );
NOR2X2TS U2248 ( .A(n6786), .B(n6785), .Y(n7400) );
INVX4TS U2249 ( .A(n5487), .Y(n6785) );
ADDFHX2TS U2250 ( .A(n2771), .B(n2770), .CI(n2769), .CO(n3154), .S(n2767) );
ADDFHX2TS U2251 ( .A(n2774), .B(n2773), .CI(n2772), .CO(n3088), .S(n2769) );
ADDFHX2TS U2252 ( .A(n3866), .B(n3865), .CI(n3864), .CO(n4542), .S(n3830) );
ADDFHX2TS U2253 ( .A(n3863), .B(n3862), .CI(n3861), .CO(n4345), .S(n3866) );
ADDFHX2TS U2254 ( .A(n2765), .B(n2764), .CI(n2763), .CO(n3318), .S(n2838) );
ADDFHX2TS U2255 ( .A(n2729), .B(n2728), .CI(n2727), .CO(n2763), .S(n2843) );
BUFX8TS U2256 ( .A(n208), .Y(n622) );
ADDFHX2TS U2257 ( .A(n4859), .B(n4858), .CI(n4857), .CO(n4955), .S(n4846) );
ADDFHX2TS U2258 ( .A(n4753), .B(n4752), .CI(n4751), .CO(n4783), .S(n4779) );
ADDFHX2TS U2259 ( .A(n4893), .B(n4892), .CI(n4891), .CO(n4915), .S(n4920) );
NAND2X2TS U2260 ( .A(n2436), .B(n2435), .Y(n7670) );
INVX2TS U2261 ( .A(n13), .Y(n5117) );
OAI22X1TS U2262 ( .A0(n5103), .A1(n3762), .B0(n4573), .B1(n3654), .Y(n3756)
);
XOR2X1TS U2263 ( .A(Data_A_i[18]), .B(Data_A_i[19]), .Y(n173) );
OAI22X1TS U2264 ( .A0(n56), .A1(n4739), .B0(n4740), .B1(n4086), .Y(n4601) );
OAI22X1TS U2265 ( .A0(n4716), .A1(n3743), .B0(n4714), .B1(n3455), .Y(n3656)
);
OAI22X1TS U2266 ( .A0(n4009), .A1(n3764), .B0(n4566), .B1(n3724), .Y(n3949)
);
OAI22X1TS U2267 ( .A0(n5235), .A1(n3387), .B0(n5233), .B1(n3347), .Y(n3370)
);
OAI22X1TS U2268 ( .A0(n8), .A1(n5518), .B0(n5517), .B1(n5584), .Y(n5608) );
NOR2XLTS U2269 ( .A(n5721), .B(n5720), .Y(n5794) );
XNOR2X1TS U2270 ( .A(n1722), .B(n1723), .Y(n1542) );
OAI22X1TS U2271 ( .A0(n6468), .A1(n6027), .B0(n6466), .B1(n6144), .Y(n6139)
);
ADDFHX2TS U2272 ( .A(n5315), .B(n5314), .CI(n5313), .CO(n5394), .S(n5304) );
INVX4TS U2273 ( .A(Data_A_i[43]), .Y(n6658) );
NOR2XLTS U2274 ( .A(n7016), .B(n6569), .Y(n6613) );
BUFX3TS U2275 ( .A(n3275), .Y(n546) );
ADDFHX2TS U2276 ( .A(n2379), .B(n2378), .CI(n2377), .CO(n2393), .S(n2398) );
ADDFHX2TS U2277 ( .A(n4956), .B(n4955), .CI(n4954), .CO(n4986), .S(n4971) );
ADDFHX2TS U2278 ( .A(n2837), .B(n2836), .CI(n2835), .CO(n3305), .S(n2840) );
ADDFHX2TS U2279 ( .A(n1219), .B(n1218), .CI(n1217), .CO(n1622), .S(n1261) );
INVX2TS U2280 ( .A(n7641), .Y(n7654) );
NOR2X1TS U2281 ( .A(n7318), .B(n7632), .Y(n7350) );
NOR2XLTS U2282 ( .A(n7257), .B(n7767), .Y(n892) );
OAI21XLTS U2283 ( .A0(n7133), .A1(n7459), .B0(n7463), .Y(n7134) );
OAI21X1TS U2284 ( .A0(n7125), .A1(n7124), .B0(n7123), .Y(n7126) );
OAI21XLTS U2285 ( .A0(n7751), .A1(n7248), .B0(n7749), .Y(n7252) );
NAND2X2TS U2287 ( .A(Data_A_i[1]), .B(n1913), .Y(n3275) );
BUFX3TS U2288 ( .A(n3275), .Y(n2093) );
CLKBUFX2TS U2289 ( .A(Data_B_i[0]), .Y(n774) );
INVX2TS U2290 ( .A(n4760), .Y(n773) );
INVX2TS U2291 ( .A(Data_B_i[1]), .Y(n3772) );
INVX2TS U2292 ( .A(n3772), .Y(n1036) );
XNOR2X1TS U2293 ( .A(n773), .B(n1036), .Y(n778) );
OAI22X1TS U2294 ( .A0(n2093), .A1(n774), .B0(n778), .B1(n839), .Y(n7794) );
NAND2X1TS U2295 ( .A(n153), .B(n842), .Y(n7793) );
NAND2X1TS U2296 ( .A(n7794), .B(n7793), .Y(mult_x_1_n1532) );
XNOR2X4TS U2297 ( .A(Data_A_i[11]), .B(Data_A_i[12]), .Y(n155) );
INVX2TS U2298 ( .A(n4252), .Y(n3349) );
XNOR2X1TS U2299 ( .A(n3349), .B(Data_B_i[13]), .Y(n197) );
XNOR2X1TS U2300 ( .A(n3349), .B(Data_B_i[14]), .Y(n160) );
OAI22X1TS U2301 ( .A0(n2464), .A1(n197), .B0(n1105), .B1(n160), .Y(n258) );
BUFX3TS U2302 ( .A(n3275), .Y(n2544) );
XNOR2X1TS U2303 ( .A(n1942), .B(Data_B_i[25]), .Y(n246) );
INVX2TS U2304 ( .A(Data_B_i[26]), .Y(n5799) );
INVX2TS U2305 ( .A(n5799), .Y(n3985) );
XNOR2X1TS U2306 ( .A(n1165), .B(n3985), .Y(n157) );
OAI22X1TS U2307 ( .A0(n2544), .A1(n246), .B0(n157), .B1(n1913), .Y(n257) );
XNOR2X4TS U2308 ( .A(Data_A_i[20]), .B(Data_A_i[19]), .Y(n3615) );
XNOR2X1TS U2309 ( .A(n132), .B(Data_B_i[5]), .Y(n221) );
XNOR2X1TS U2310 ( .A(n3040), .B(Data_B_i[6]), .Y(n158) );
OAI22X1TS U2311 ( .A0(n71), .A1(n221), .B0(n124), .B1(n158), .Y(n256) );
XNOR2X1TS U2312 ( .A(n1165), .B(Data_B_i[27]), .Y(n168) );
OAI22X1TS U2313 ( .A0(n2544), .A1(n157), .B0(n168), .B1(n1346), .Y(n165) );
INVX2TS U2314 ( .A(Data_B_i[7]), .Y(n3400) );
INVX2TS U2315 ( .A(n3400), .Y(n1691) );
XNOR2X1TS U2316 ( .A(n3616), .B(n1691), .Y(n171) );
XOR2X4TS U2317 ( .A(n2503), .B(Data_A_i[10]), .Y(n159) );
XNOR2X4TS U2318 ( .A(Data_A_i[10]), .B(Data_A_i[9]), .Y(n1020) );
BUFX8TS U2319 ( .A(n2502), .Y(n4135) );
BUFX8TS U2320 ( .A(n4135), .Y(n1140) );
INVX2TS U2321 ( .A(n1019), .Y(n3374) );
XNOR2X1TS U2322 ( .A(n3374), .B(Data_B_i[16]), .Y(n237) );
CLKBUFX2TS U2323 ( .A(n1020), .Y(n1138) );
INVX2TS U2324 ( .A(Data_B_i[17]), .Y(n5142) );
INVX2TS U2325 ( .A(n5142), .Y(n2573) );
XNOR2X1TS U2326 ( .A(n3374), .B(n2573), .Y(n290) );
OAI22X1TS U2327 ( .A0(n1140), .A1(n237), .B0(n1138), .B1(n290), .Y(n163) );
XNOR2X1TS U2328 ( .A(n3349), .B(Data_B_i[15]), .Y(n166) );
OAI22X1TS U2329 ( .A0(n4684), .A1(n160), .B0(n1105), .B1(n166), .Y(n186) );
XOR2X4TS U2330 ( .A(n5584), .B(Data_A_i[24]), .Y(n2895) );
INVX2TS U2331 ( .A(n5755), .Y(n1468) );
XNOR2X1TS U2332 ( .A(n116), .B(Data_B_i[2]), .Y(n183) );
CLKBUFX2TS U2333 ( .A(n2895), .Y(n2928) );
XNOR2X1TS U2334 ( .A(n115), .B(Data_B_i[3]), .Y(n188) );
OAI22X1TS U2335 ( .A0(n1470), .A1(n183), .B0(n2928), .B1(n188), .Y(n185) );
XNOR2X4TS U2336 ( .A(Data_A_i[21]), .B(Data_A_i[22]), .Y(n196) );
INVX2TS U2337 ( .A(n5584), .Y(n3769) );
XNOR2X1TS U2338 ( .A(n3769), .B(Data_B_i[4]), .Y(n182) );
XNOR2X1TS U2339 ( .A(n3769), .B(Data_B_i[5]), .Y(n167) );
OAI22X1TS U2340 ( .A0(n5586), .A1(n182), .B0(n2516), .B1(n167), .Y(n184) );
INVX2TS U2341 ( .A(Data_B_i[16]), .Y(n4477) );
INVX2TS U2342 ( .A(n4477), .Y(n2353) );
XNOR2X1TS U2343 ( .A(n3349), .B(n2353), .Y(n1106) );
OAI22X1TS U2344 ( .A0(n2464), .A1(n166), .B0(n1105), .B1(n1106), .Y(n1225)
);
XNOR2X1TS U2345 ( .A(n3769), .B(Data_B_i[6]), .Y(n1127) );
XNOR2X1TS U2346 ( .A(n1165), .B(Data_B_i[28]), .Y(n1107) );
OAI22X1TS U2347 ( .A0(n2544), .A1(n168), .B0(n1107), .B1(n1346), .Y(n1223)
);
XNOR2X4TS U2348 ( .A(Data_A_i[14]), .B(Data_A_i[13]), .Y(n1393) );
XOR2X1TS U2349 ( .A(Data_A_i[14]), .B(Data_A_i[15]), .Y(n169) );
INVX2TS U2350 ( .A(n4398), .Y(n4247) );
INVX2TS U2351 ( .A(Data_B_i[13]), .Y(n4203) );
INVX2TS U2352 ( .A(n4203), .Y(n1898) );
XNOR2X1TS U2353 ( .A(n3847), .B(n1898), .Y(n233) );
INVX2TS U2354 ( .A(Data_B_i[14]), .Y(n4246) );
INVX2TS U2355 ( .A(n4246), .Y(n2284) );
XNOR2X1TS U2356 ( .A(n3847), .B(n2284), .Y(n1136) );
OAI22X1TS U2357 ( .A0(n102), .A1(n233), .B0(n3213), .B1(n1136), .Y(n1103) );
XOR2X1TS U2358 ( .A(Data_A_i[2]), .B(Data_A_i[3]), .Y(n170) );
XNOR2X4TS U2359 ( .A(Data_A_i[2]), .B(Data_A_i[1]), .Y(n2512) );
BUFX8TS U2360 ( .A(n2512), .Y(n3990) );
BUFX3TS U2361 ( .A(n4052), .Y(n2547) );
INVX2TS U2362 ( .A(n3276), .Y(n2511) );
XNOR2X1TS U2363 ( .A(n35), .B(Data_B_i[25]), .Y(n172) );
XNOR2X1TS U2364 ( .A(n36), .B(n3985), .Y(n1109) );
OAI22X1TS U2365 ( .A0(n2547), .A1(n172), .B0(n2281), .B1(n1109), .Y(n1102)
);
INVX2TS U2366 ( .A(n5436), .Y(n3040) );
INVX2TS U2367 ( .A(Data_B_i[8]), .Y(n3393) );
INVX2TS U2368 ( .A(n3393), .Y(n1989) );
XNOR2X1TS U2369 ( .A(n133), .B(n1989), .Y(n1098) );
OAI22X1TS U2370 ( .A0(n71), .A1(n171), .B0(n125), .B1(n1098), .Y(n1101) );
XNOR2X1TS U2371 ( .A(n35), .B(Data_B_i[24]), .Y(n227) );
OAI22X1TS U2372 ( .A0(n2547), .A1(n227), .B0(n2281), .B1(n172), .Y(n279) );
XNOR2X4TS U2373 ( .A(Data_A_i[17]), .B(Data_A_i[18]), .Y(n422) );
INVX2TS U2374 ( .A(n5292), .Y(n2859) );
XNOR2X1TS U2375 ( .A(n2859), .B(n1989), .Y(n205) );
INVX2TS U2376 ( .A(n5292), .Y(n1042) );
INVX2TS U2377 ( .A(Data_B_i[9]), .Y(n3394) );
INVX2TS U2378 ( .A(n3394), .Y(n1813) );
XNOR2X1TS U2379 ( .A(n1042), .B(n1813), .Y(n294) );
OAI22X1TS U2380 ( .A0(n149), .A1(n205), .B0(n2034), .B1(n294), .Y(n278) );
XNOR2X4TS U2381 ( .A(n174), .B(n4398), .Y(n548) );
NAND2X4TS U2382 ( .A(n175), .B(n548), .Y(n4479) );
INVX2TS U2383 ( .A(n5119), .Y(n2347) );
INVX2TS U2384 ( .A(Data_B_i[10]), .Y(n3522) );
INVX2TS U2385 ( .A(n3522), .Y(n1991) );
XNOR2X1TS U2386 ( .A(n2347), .B(n1991), .Y(n206) );
INVX2TS U2387 ( .A(Data_B_i[11]), .Y(n3589) );
INVX2TS U2388 ( .A(n3589), .Y(n1856) );
XNOR2X1TS U2389 ( .A(n2347), .B(n1856), .Y(n293) );
OAI22X1TS U2390 ( .A0(n127), .A1(n206), .B0(n44), .B1(n293), .Y(n277) );
XNOR2X4TS U2391 ( .A(Data_A_i[5]), .B(Data_A_i[6]), .Y(n177) );
INVX2TS U2392 ( .A(Data_B_i[20]), .Y(n5370) );
INVX2TS U2393 ( .A(n5370), .Y(n2936) );
XNOR2X1TS U2394 ( .A(Data_A_i[7]), .B(n2936), .Y(n203) );
XNOR2X1TS U2395 ( .A(Data_A_i[7]), .B(Data_B_i[21]), .Y(n289) );
OAI22X1TS U2396 ( .A0(n2967), .A1(n203), .B0(n2781), .B1(n289), .Y(n282) );
XNOR2X4TS U2397 ( .A(Data_A_i[26]), .B(Data_A_i[25]), .Y(n179) );
NAND2X4TS U2398 ( .A(n178), .B(n5893), .Y(n4322) );
INVX2TS U2399 ( .A(n5892), .Y(n1660) );
CLKBUFX2TS U2400 ( .A(Data_B_i[0]), .Y(n2037) );
XNOR2X1TS U2401 ( .A(n98), .B(n2037), .Y(n180) );
BUFX3TS U2402 ( .A(n2345), .Y(n3074) );
XNOR2X1TS U2403 ( .A(n5101), .B(Data_B_i[1]), .Y(n187) );
OAI22X1TS U2404 ( .A0(n4575), .A1(n180), .B0(n3074), .B1(n187), .Y(n191) );
BUFX3TS U2405 ( .A(Data_B_i[0]), .Y(n2472) );
OAI22X1TS U2406 ( .A0(n5103), .A1(n5892), .B0(n134), .B1(n181), .Y(n190) );
NOR2BX1TS U2407 ( .AN(n1726), .B(n5893), .Y(n202) );
XNOR2X1TS U2408 ( .A(n3769), .B(Data_B_i[3]), .Y(n219) );
OAI22X1TS U2409 ( .A0(n2892), .A1(n219), .B0(n2516), .B1(n182), .Y(n201) );
XNOR2X1TS U2410 ( .A(n116), .B(Data_B_i[1]), .Y(n193) );
OAI22X1TS U2411 ( .A0(n2056), .A1(n193), .B0(n37), .B1(n183), .Y(n200) );
CMPR32X2TS U2412 ( .A(n186), .B(n185), .C(n184), .CO(n1244), .S(n271) );
XNOR2X1TS U2413 ( .A(n5760), .B(Data_B_i[2]), .Y(n1129) );
XNOR2X4TS U2414 ( .A(Data_A_i[28]), .B(Data_A_i[27]), .Y(n1014) );
NOR2BX1TS U2415 ( .AN(n1726), .B(n1014), .Y(n1087) );
XNOR2X1TS U2416 ( .A(n115), .B(Data_B_i[4]), .Y(n1131) );
ADDHX1TS U2417 ( .A(n191), .B(n190), .CO(n1249), .S(n281) );
XNOR2X1TS U2418 ( .A(n115), .B(n2037), .Y(n194) );
OAI22X1TS U2419 ( .A0(n2056), .A1(n194), .B0(n2928), .B1(n193), .Y(n239) );
OAI22X1TS U2420 ( .A0(n2056), .A1(n5755), .B0(n37), .B1(n195), .Y(n238) );
NOR2BX1TS U2421 ( .AN(n2871), .B(n108), .Y(n310) );
XNOR2X1TS U2422 ( .A(n50), .B(Data_B_i[3]), .Y(n312) );
XNOR2X1TS U2423 ( .A(n50), .B(Data_B_i[4]), .Y(n222) );
XNOR2X1TS U2424 ( .A(n3769), .B(Data_B_i[1]), .Y(n305) );
XNOR2X1TS U2425 ( .A(n3769), .B(Data_B_i[2]), .Y(n220) );
OAI22X1TS U2426 ( .A0(n5519), .A1(n305), .B0(n5517), .B1(n220), .Y(n308) );
XNOR2X1TS U2427 ( .A(n3374), .B(Data_B_i[13]), .Y(n311) );
XNOR2X1TS U2428 ( .A(n3374), .B(Data_B_i[14]), .Y(n245) );
OAI22X1TS U2429 ( .A0(n3525), .A1(n311), .B0(n1138), .B1(n245), .Y(n329) );
XNOR2X1TS U2430 ( .A(n2347), .B(n1691), .Y(n350) );
XNOR2X1TS U2431 ( .A(n2347), .B(n1989), .Y(n218) );
OAI22X1TS U2432 ( .A0(n126), .A1(n350), .B0(n64), .B1(n218), .Y(n328) );
XNOR2X1TS U2433 ( .A(n1042), .B(Data_B_i[5]), .Y(n313) );
XNOR2X1TS U2434 ( .A(n1042), .B(Data_B_i[6]), .Y(n213) );
OAI22X1TS U2435 ( .A0(n150), .A1(n313), .B0(n2034), .B1(n213), .Y(n327) );
XNOR2X1TS U2436 ( .A(Data_A_i[7]), .B(Data_B_i[18]), .Y(n304) );
INVX2TS U2437 ( .A(Data_B_i[19]), .Y(n5253) );
XNOR2X1TS U2438 ( .A(Data_A_i[7]), .B(n3781), .Y(n204) );
OAI22X1TS U2439 ( .A0(n2110), .A1(n304), .B0(n733), .B1(n204), .Y(n216) );
XNOR2X1TS U2440 ( .A(n92), .B(Data_B_i[12]), .Y(n209) );
OAI22X1TS U2441 ( .A0(n2525), .A1(n209), .B0(n1105), .B1(n197), .Y(n215) );
XNOR2X4TS U2442 ( .A(Data_A_i[8]), .B(Data_A_i[7]), .Y(n199) );
INVX2TS U2443 ( .A(n3398), .Y(n3397) );
XNOR2X1TS U2444 ( .A(n3397), .B(Data_B_i[16]), .Y(n243) );
CLKBUFX2TS U2445 ( .A(n199), .Y(n826) );
XNOR2X1TS U2446 ( .A(n3397), .B(Data_B_i[17]), .Y(n236) );
OAI22X1TS U2447 ( .A0(n1096), .A1(n243), .B0(n826), .B1(n236), .Y(n214) );
OAI22X1TS U2448 ( .A0(n824), .A1(n204), .B0(n2781), .B1(n203), .Y(n242) );
XNOR2X1TS U2449 ( .A(n1042), .B(n1691), .Y(n212) );
OAI22X1TS U2450 ( .A0(n148), .A1(n212), .B0(n2034), .B1(n205), .Y(n241) );
XNOR2X1TS U2451 ( .A(n2347), .B(n1813), .Y(n217) );
OAI22X1TS U2452 ( .A0(n127), .A1(n217), .B0(n63), .B1(n206), .Y(n240) );
XNOR2X4TS U2453 ( .A(Data_A_i[4]), .B(Data_A_i[3]), .Y(n208) );
XNOR2X1TS U2454 ( .A(n3753), .B(n3781), .Y(n349) );
INVX2TS U2455 ( .A(n1816), .Y(n2552) );
XNOR2X1TS U2456 ( .A(n2552), .B(n2936), .Y(n210) );
OAI22X1TS U2457 ( .A0(n144), .A1(n349), .B0(n87), .B1(n210), .Y(n316) );
BUFX3TS U2458 ( .A(n3348), .Y(n508) );
INVX2TS U2459 ( .A(n4398), .Y(n2897) );
XNOR2X1TS U2460 ( .A(n4089), .B(n1813), .Y(n351) );
INVX2TS U2461 ( .A(n4398), .Y(n2705) );
XNOR2X1TS U2462 ( .A(n4247), .B(n1991), .Y(n211) );
OAI22X1TS U2463 ( .A0(n508), .A1(n351), .B0(n4091), .B1(n211), .Y(n315) );
XNOR2X1TS U2464 ( .A(n1896), .B(Data_B_i[11]), .Y(n324) );
OAI22X1TS U2465 ( .A0(n41), .A1(n324), .B0(n1105), .B1(n209), .Y(n314) );
XNOR2X1TS U2466 ( .A(n3753), .B(Data_B_i[21]), .Y(n228) );
OAI22X1TS U2467 ( .A0(n144), .A1(n210), .B0(n87), .B1(n228), .Y(n225) );
XNOR2X1TS U2468 ( .A(n4247), .B(n1856), .Y(n226) );
OAI22X1TS U2469 ( .A0(n508), .A1(n211), .B0(n1379), .B1(n226), .Y(n224) );
OAI22X1TS U2470 ( .A0(n150), .A1(n213), .B0(n2034), .B1(n212), .Y(n223) );
CMPR32X2TS U2471 ( .A(n216), .B(n215), .C(n214), .CO(n231), .S(n336) );
OAI22X1TS U2472 ( .A0(n126), .A1(n218), .B0(n52), .B1(n217), .Y(n252) );
OAI22X1TS U2473 ( .A0(n5519), .A1(n220), .B0(n2516), .B1(n219), .Y(n251) );
OAI22X1TS U2474 ( .A0(n70), .A1(n222), .B0(n124), .B1(n221), .Y(n250) );
INVX2TS U2475 ( .A(Data_B_i[12]), .Y(n3845) );
INVX2TS U2476 ( .A(n3845), .Y(n1859) );
XNOR2X1TS U2477 ( .A(n2705), .B(n1859), .Y(n234) );
OAI22X1TS U2478 ( .A0(n508), .A1(n226), .B0(n3213), .B1(n234), .Y(n276) );
XNOR2X1TS U2479 ( .A(n36), .B(Data_B_i[23]), .Y(n248) );
OAI22X1TS U2480 ( .A0(n2547), .A1(n248), .B0(n2281), .B1(n227), .Y(n275) );
BUFX3TS U2481 ( .A(n3754), .Y(n2638) );
XNOR2X1TS U2482 ( .A(n2552), .B(Data_B_i[22]), .Y(n232) );
OAI22X1TS U2483 ( .A0(n2638), .A1(n228), .B0(n87), .B1(n232), .Y(n274) );
ADDFHX2TS U2484 ( .A(n231), .B(n230), .CI(n229), .CO(n266), .S(n322) );
XNOR2X1TS U2485 ( .A(n2552), .B(Data_B_i[23]), .Y(n292) );
OAI22X1TS U2486 ( .A0(n2638), .A1(n232), .B0(n88), .B1(n292), .Y(n288) );
OAI22X1TS U2487 ( .A0(n102), .A1(n234), .B0(n1379), .B1(n233), .Y(n287) );
XNOR2X1TS U2488 ( .A(n3397), .B(Data_B_i[18]), .Y(n235) );
XNOR2X1TS U2489 ( .A(n3397), .B(n3781), .Y(n291) );
OAI22X1TS U2490 ( .A0(n1096), .A1(n235), .B0(n826), .B1(n291), .Y(n286) );
OAI22X1TS U2491 ( .A0(n1096), .A1(n236), .B0(n826), .B1(n235), .Y(n261) );
XNOR2X1TS U2492 ( .A(n3374), .B(Data_B_i[15]), .Y(n244) );
OAI22X1TS U2493 ( .A0(n1140), .A1(n244), .B0(n1138), .B1(n237), .Y(n260) );
ADDHXLTS U2494 ( .A(n239), .B(n238), .CO(n259), .S(n303) );
CMPR32X2TS U2495 ( .A(n242), .B(n241), .C(n240), .CO(n283), .S(n229) );
XNOR2X1TS U2496 ( .A(n3397), .B(Data_B_i[15]), .Y(n318) );
OAI22X1TS U2497 ( .A0(n1096), .A1(n318), .B0(n826), .B1(n243), .Y(n332) );
XNOR2X1TS U2498 ( .A(n1942), .B(Data_B_i[23]), .Y(n325) );
XNOR2X1TS U2499 ( .A(n1942), .B(Data_B_i[24]), .Y(n247) );
OAI22X1TS U2500 ( .A0(n546), .A1(n325), .B0(n247), .B1(n1346), .Y(n331) );
INVX2TS U2501 ( .A(n3276), .Y(n4051) );
XNOR2X1TS U2502 ( .A(n4051), .B(Data_B_i[21]), .Y(n326) );
XNOR2X1TS U2503 ( .A(n35), .B(Data_B_i[22]), .Y(n249) );
OAI22X1TS U2504 ( .A0(n2547), .A1(n326), .B0(n2281), .B1(n249), .Y(n330) );
OAI22X1TS U2505 ( .A0(n1140), .A1(n245), .B0(n1138), .B1(n244), .Y(n255) );
OAI22X1TS U2506 ( .A0(n546), .A1(n247), .B0(n246), .B1(n1913), .Y(n254) );
OAI22X1TS U2507 ( .A0(n2547), .A1(n249), .B0(n2281), .B1(n248), .Y(n253) );
CMPR32X2TS U2508 ( .A(n252), .B(n251), .C(n250), .CO(n264), .S(n333) );
CMPR32X2TS U2509 ( .A(n255), .B(n254), .C(n253), .CO(n270), .S(n334) );
CMPR32X2TS U2510 ( .A(n270), .B(n269), .C(n268), .CO(n300), .S(n347) );
CMPR32X2TS U2511 ( .A(n276), .B(n275), .C(n274), .CO(n297), .S(n262) );
XNOR2X1TS U2512 ( .A(n2965), .B(Data_B_i[22]), .Y(n1115) );
OAI22X1TS U2513 ( .A0(n824), .A1(n289), .B0(n2781), .B1(n1115), .Y(n1228) );
INVX2TS U2514 ( .A(Data_B_i[18]), .Y(n5231) );
INVX2TS U2515 ( .A(n5231), .Y(n2804) );
XNOR2X1TS U2516 ( .A(n3374), .B(n2804), .Y(n1139) );
XNOR2X1TS U2517 ( .A(n3397), .B(n2936), .Y(n1095) );
OAI22X1TS U2518 ( .A0(n1096), .A1(n291), .B0(n2984), .B1(n1095), .Y(n1226)
);
XNOR2X1TS U2519 ( .A(n2552), .B(Data_B_i[24]), .Y(n1113) );
OAI22X1TS U2520 ( .A0(n2638), .A1(n292), .B0(n7), .B1(n1113), .Y(n1093) );
INVX2TS U2521 ( .A(n5119), .Y(n4373) );
XNOR2X1TS U2522 ( .A(n4373), .B(n1859), .Y(n1100) );
OAI22X1TS U2523 ( .A0(n126), .A1(n293), .B0(n64), .B1(n1100), .Y(n1092) );
XNOR2X1TS U2524 ( .A(n2859), .B(n1991), .Y(n1111) );
OAI22X1TS U2525 ( .A0(n5294), .A1(n294), .B0(n2034), .B1(n1111), .Y(n1091)
);
XNOR2X1TS U2526 ( .A(n1922), .B(Data_B_i[17]), .Y(n317) );
OAI22X1TS U2527 ( .A0(n824), .A1(n317), .B0(n733), .B1(n304), .Y(n354) );
XNOR2X1TS U2528 ( .A(n3769), .B(n774), .Y(n306) );
OAI22X1TS U2529 ( .A0(n4258), .A1(n306), .B0(n2516), .B1(n305), .Y(n320) );
INVX2TS U2530 ( .A(n5584), .Y(n5368) );
OAI22X1TS U2531 ( .A0(n4084), .A1(n5584), .B0(n140), .B1(n307), .Y(n319) );
XNOR2X1TS U2532 ( .A(n3374), .B(Data_B_i[12]), .Y(n358) );
OAI22X1TS U2533 ( .A0(n3525), .A1(n358), .B0(n1138), .B1(n311), .Y(n371) );
XNOR2X1TS U2534 ( .A(n3040), .B(Data_B_i[2]), .Y(n362) );
OAI22X1TS U2535 ( .A0(n70), .A1(n362), .B0(n124), .B1(n312), .Y(n370) );
XNOR2X1TS U2536 ( .A(n1042), .B(Data_B_i[4]), .Y(n361) );
OAI22X1TS U2537 ( .A0(n5235), .A1(n361), .B0(n2034), .B1(n313), .Y(n369) );
XNOR2X1TS U2538 ( .A(Data_A_i[7]), .B(Data_B_i[16]), .Y(n393) );
OAI22X1TS U2539 ( .A0(n2967), .A1(n393), .B0(n733), .B1(n317), .Y(n396) );
XNOR2X1TS U2540 ( .A(n3397), .B(Data_B_i[14]), .Y(n392) );
OAI22X1TS U2541 ( .A0(n1096), .A1(n392), .B0(n826), .B1(n318), .Y(n395) );
ADDHXLTS U2542 ( .A(n320), .B(n319), .CO(n353), .S(n394) );
XNOR2X1TS U2543 ( .A(n1896), .B(Data_B_i[10]), .Y(n366) );
OAI22X1TS U2544 ( .A0(n4684), .A1(n366), .B0(n2462), .B1(n324), .Y(n374) );
XNOR2X1TS U2545 ( .A(n1942), .B(Data_B_i[22]), .Y(n359) );
OAI22X1TS U2546 ( .A0(n546), .A1(n359), .B0(n325), .B1(n1913), .Y(n373) );
XNOR2X1TS U2547 ( .A(n4051), .B(n2936), .Y(n360) );
OAI22X1TS U2548 ( .A0(n790), .A1(n360), .B0(n2281), .B1(n326), .Y(n372) );
CMPR32X2TS U2549 ( .A(n332), .B(n331), .C(n330), .CO(n335), .S(n378) );
CMPR32X2TS U2550 ( .A(n338), .B(n337), .C(n336), .CO(n321), .S(n388) );
NOR2X2TS U2551 ( .A(n1004), .B(n1003), .Y(n342) );
INVX2TS U2552 ( .A(n342), .Y(n7217) );
CMPR32X2TS U2553 ( .A(n348), .B(n347), .C(n346), .CO(n339), .S(n387) );
XNOR2X1TS U2554 ( .A(n3753), .B(Data_B_i[18]), .Y(n391) );
OAI22X1TS U2555 ( .A0(n144), .A1(n391), .B0(n762), .B1(n349), .Y(n357) );
XNOR2X1TS U2556 ( .A(Data_A_i[17]), .B(Data_B_i[6]), .Y(n367) );
OAI22X1TS U2557 ( .A0(n126), .A1(n367), .B0(n44), .B1(n350), .Y(n356) );
XNOR2X1TS U2558 ( .A(n4247), .B(n1989), .Y(n368) );
OAI22X1TS U2559 ( .A0(n508), .A1(n368), .B0(n4593), .B1(n351), .Y(n355) );
INVX2TS U2560 ( .A(n1019), .Y(n1987) );
XNOR2X1TS U2561 ( .A(n1987), .B(Data_B_i[11]), .Y(n400) );
OAI22X1TS U2562 ( .A0(n646), .A1(n400), .B0(n1138), .B1(n358), .Y(n441) );
OAI22X1TS U2563 ( .A0(n546), .A1(n401), .B0(n359), .B1(n1913), .Y(n440) );
XNOR2X1TS U2564 ( .A(n4051), .B(n3781), .Y(n402) );
OAI22X1TS U2565 ( .A0(n790), .A1(n402), .B0(n2281), .B1(n360), .Y(n439) );
NOR2BX1TS U2566 ( .AN(n1726), .B(n141), .Y(n405) );
XNOR2X1TS U2567 ( .A(n1042), .B(Data_B_i[3]), .Y(n413) );
OAI22X1TS U2568 ( .A0(n4704), .A1(n413), .B0(n2034), .B1(n361), .Y(n404) );
XNOR2X1TS U2569 ( .A(n133), .B(Data_B_i[1]), .Y(n397) );
CLKBUFX2TS U2570 ( .A(n3615), .Y(n1689) );
OAI22X1TS U2571 ( .A0(n3760), .A1(n397), .B0(n1689), .B1(n362), .Y(n403) );
XNOR2X1TS U2572 ( .A(n92), .B(Data_B_i[9]), .Y(n418) );
OAI22X1TS U2573 ( .A0(n4684), .A1(n418), .B0(n625), .B1(n366), .Y(n444) );
XNOR2X1TS U2574 ( .A(n81), .B(Data_B_i[5]), .Y(n414) );
OAI22X1TS U2575 ( .A0(n126), .A1(n414), .B0(n62), .B1(n367), .Y(n443) );
XNOR2X1TS U2576 ( .A(n2897), .B(n1691), .Y(n436) );
OAI22X1TS U2577 ( .A0(n508), .A1(n436), .B0(n4091), .B1(n368), .Y(n442) );
CMPR32X2TS U2578 ( .A(n374), .B(n373), .C(n372), .CO(n380), .S(n424) );
CMPR32X2TS U2579 ( .A(n380), .B(n379), .C(n378), .CO(n390), .S(n433) );
ADDFHX2TS U2580 ( .A(n383), .B(n382), .CI(n381), .CO(n344), .S(n385) );
NOR2X1TS U2581 ( .A(n1002), .B(n1001), .Y(n384) );
INVX2TS U2582 ( .A(n384), .Y(n7223) );
CMPR32X2TS U2583 ( .A(n390), .B(n389), .C(n388), .CO(n381), .S(n432) );
XNOR2X1TS U2584 ( .A(n3753), .B(Data_B_i[17]), .Y(n437) );
OAI22X1TS U2585 ( .A0(n143), .A1(n437), .B0(n762), .B1(n391), .Y(n417) );
XNOR2X1TS U2586 ( .A(n3397), .B(Data_B_i[13]), .Y(n412) );
OAI22X1TS U2587 ( .A0(n1964), .A1(n412), .B0(n826), .B1(n392), .Y(n416) );
XNOR2X1TS U2588 ( .A(Data_A_i[7]), .B(Data_B_i[15]), .Y(n438) );
OAI22X1TS U2589 ( .A0(n110), .A1(n438), .B0(n733), .B1(n393), .Y(n415) );
XNOR2X1TS U2590 ( .A(n3616), .B(n774), .Y(n398) );
OAI22X1TS U2591 ( .A0(n69), .A1(n398), .B0(n124), .B1(n397), .Y(n420) );
OAI22X1TS U2592 ( .A0(n3760), .A1(n5436), .B0(n1689), .B1(n399), .Y(n419) );
XNOR2X1TS U2593 ( .A(n1987), .B(Data_B_i[10]), .Y(n482) );
OAI22X1TS U2594 ( .A0(n546), .A1(n480), .B0(n401), .B1(n671), .Y(n927) );
XNOR2X1TS U2595 ( .A(n4051), .B(Data_B_i[18]), .Y(n457) );
CLKBUFX2TS U2596 ( .A(n2512), .Y(n788) );
OAI22X1TS U2597 ( .A0(n790), .A1(n457), .B0(n788), .B1(n402), .Y(n926) );
INVX2TS U2598 ( .A(n3398), .Y(n728) );
XNOR2X1TS U2599 ( .A(n728), .B(Data_B_i[12]), .Y(n451) );
OAI22X1TS U2600 ( .A0(n1964), .A1(n451), .B0(n826), .B1(n412), .Y(n931) );
XNOR2X1TS U2601 ( .A(n1042), .B(Data_B_i[2]), .Y(n423) );
OAI22X1TS U2602 ( .A0(n148), .A1(n423), .B0(n2034), .B1(n413), .Y(n930) );
XNOR2X1TS U2603 ( .A(Data_A_i[17]), .B(Data_B_i[4]), .Y(n421) );
OAI22X1TS U2604 ( .A0(n127), .A1(n421), .B0(n52), .B1(n414), .Y(n929) );
XNOR2X1TS U2605 ( .A(n1896), .B(Data_B_i[8]), .Y(n453) );
OAI22X1TS U2606 ( .A0(n40), .A1(n453), .B0(n625), .B1(n418), .Y(n937) );
XNOR2X1TS U2607 ( .A(Data_A_i[17]), .B(Data_B_i[3]), .Y(n495) );
OAI22X1TS U2608 ( .A0(n126), .A1(n495), .B0(n9), .B1(n421), .Y(n477) );
CLKBUFX2TS U2609 ( .A(n2472), .Y(n3272) );
CLKBUFX2TS U2610 ( .A(n3615), .Y(n5437) );
NOR2BX1TS U2611 ( .AN(n3272), .B(n5437), .Y(n476) );
XNOR2X1TS U2612 ( .A(n1042), .B(Data_B_i[1]), .Y(n459) );
OAI22X1TS U2613 ( .A0(n148), .A1(n459), .B0(n1514), .B1(n423), .Y(n475) );
CMPR32X2TS U2614 ( .A(n426), .B(n425), .C(n424), .CO(n435), .S(n920) );
CMPR32X2TS U2615 ( .A(n435), .B(n434), .C(n433), .CO(n427), .S(n919) );
XNOR2X1TS U2616 ( .A(n3847), .B(Data_B_i[6]), .Y(n452) );
OAI22X1TS U2617 ( .A0(n508), .A1(n452), .B0(n1379), .B1(n436), .Y(n456) );
XNOR2X1TS U2618 ( .A(n3753), .B(Data_B_i[16]), .Y(n458) );
OAI22X1TS U2619 ( .A0(n144), .A1(n458), .B0(n762), .B1(n437), .Y(n455) );
XNOR2X1TS U2620 ( .A(Data_A_i[7]), .B(Data_B_i[14]), .Y(n478) );
OAI22X1TS U2621 ( .A0(n2967), .A1(n478), .B0(n733), .B1(n438), .Y(n454) );
CMPR32X2TS U2622 ( .A(n441), .B(n440), .C(n439), .CO(n410), .S(n463) );
CMPR32X2TS U2623 ( .A(n444), .B(n443), .C(n442), .CO(n426), .S(n462) );
CMPR32X2TS U2624 ( .A(n447), .B(n446), .C(n445), .CO(n467), .S(n945) );
CMPR32X2TS U2625 ( .A(n450), .B(n449), .C(n448), .CO(n445), .S(n952) );
INVX2TS U2626 ( .A(n3398), .Y(n1849) );
XNOR2X1TS U2627 ( .A(n1849), .B(Data_B_i[11]), .Y(n493) );
OAI22X1TS U2628 ( .A0(n704), .A1(n493), .B0(n826), .B1(n451), .Y(n528) );
XNOR2X1TS U2629 ( .A(n94), .B(Data_B_i[5]), .Y(n497) );
OAI22X1TS U2630 ( .A0(n508), .A1(n497), .B0(n4091), .B1(n452), .Y(n527) );
XNOR2X1TS U2631 ( .A(n92), .B(Data_B_i[7]), .Y(n468) );
OAI22X1TS U2632 ( .A0(n43), .A1(n468), .B0(n625), .B1(n453), .Y(n526) );
XNOR2X1TS U2633 ( .A(n4051), .B(Data_B_i[17]), .Y(n472) );
OAI22X1TS U2634 ( .A0(n790), .A1(n472), .B0(n788), .B1(n457), .Y(n531) );
XNOR2X1TS U2635 ( .A(n3753), .B(Data_B_i[15]), .Y(n474) );
OAI22X1TS U2636 ( .A0(n144), .A1(n474), .B0(n762), .B1(n458), .Y(n530) );
XNOR2X1TS U2637 ( .A(n1042), .B(n774), .Y(n460) );
OAI22X1TS U2638 ( .A0(n148), .A1(n460), .B0(n2034), .B1(n459), .Y(n470) );
OAI22X1TS U2639 ( .A0(n149), .A1(n5292), .B0(n1514), .B1(n461), .Y(n469) );
CMPR32X2TS U2640 ( .A(n464), .B(n463), .C(n462), .CO(n946), .S(n950) );
INVX2TS U2641 ( .A(n7226), .Y(n7720) );
INVX2TS U2642 ( .A(n3455), .Y(n723) );
XNOR2X1TS U2643 ( .A(n723), .B(Data_B_i[12]), .Y(n513) );
XNOR2X1TS U2644 ( .A(Data_A_i[7]), .B(Data_B_i[13]), .Y(n479) );
OAI22X1TS U2645 ( .A0(n735), .A1(n513), .B0(n733), .B1(n479), .Y(n505) );
XNOR2X1TS U2646 ( .A(n616), .B(Data_B_i[18]), .Y(n471) );
XNOR2X1TS U2647 ( .A(n616), .B(n3781), .Y(n481) );
OAI22X1TS U2648 ( .A0(n546), .A1(n471), .B0(n481), .B1(n671), .Y(n504) );
INVX2TS U2649 ( .A(Data_B_i[6]), .Y(n3399) );
INVX2TS U2650 ( .A(n3399), .Y(n1641) );
XNOR2X1TS U2651 ( .A(n92), .B(n1641), .Y(n501) );
OAI22X1TS U2652 ( .A0(n41), .A1(n501), .B0(n625), .B1(n468), .Y(n503) );
ADDHXLTS U2653 ( .A(n470), .B(n469), .CO(n529), .S(n540) );
NOR2BX1TS U2654 ( .AN(n1726), .B(n5293), .Y(n519) );
XNOR2X1TS U2655 ( .A(n3847), .B(Data_B_i[3]), .Y(n507) );
XNOR2X1TS U2656 ( .A(n4089), .B(Data_B_i[4]), .Y(n498) );
XNOR2X1TS U2657 ( .A(n81), .B(Data_B_i[1]), .Y(n490) );
XNOR2X1TS U2658 ( .A(n81), .B(Data_B_i[2]), .Y(n496) );
OAI22X1TS U2659 ( .A0(n127), .A1(n490), .B0(n62), .B1(n496), .Y(n517) );
XNOR2X1TS U2660 ( .A(n728), .B(Data_B_i[9]), .Y(n484) );
CLKBUFX2TS U2661 ( .A(n199), .Y(n1390) );
XNOR2X1TS U2662 ( .A(n1849), .B(Data_B_i[10]), .Y(n494) );
OAI22X1TS U2663 ( .A0(n704), .A1(n484), .B0(n1390), .B1(n494), .Y(n489) );
XNOR2X1TS U2664 ( .A(n616), .B(Data_B_i[17]), .Y(n485) );
OAI22X1TS U2665 ( .A0(n546), .A1(n485), .B0(n471), .B1(n671), .Y(n488) );
XNOR2X1TS U2666 ( .A(n4051), .B(Data_B_i[15]), .Y(n486) );
XNOR2X1TS U2667 ( .A(n4051), .B(Data_B_i[16]), .Y(n473) );
OAI22X1TS U2668 ( .A0(n790), .A1(n486), .B0(n788), .B1(n473), .Y(n487) );
OAI22X1TS U2669 ( .A0(n790), .A1(n473), .B0(n788), .B1(n472), .Y(n534) );
XNOR2X1TS U2670 ( .A(Data_A_i[11]), .B(Data_B_i[8]), .Y(n502) );
XNOR2X1TS U2671 ( .A(n1987), .B(Data_B_i[9]), .Y(n483) );
OAI22X1TS U2672 ( .A0(n646), .A1(n502), .B0(n1517), .B1(n483), .Y(n533) );
XNOR2X1TS U2673 ( .A(n3753), .B(Data_B_i[14]), .Y(n499) );
OAI22X1TS U2674 ( .A0(n143), .A1(n499), .B0(n762), .B1(n474), .Y(n532) );
OAI22X1TS U2675 ( .A0(n2110), .A1(n479), .B0(n733), .B1(n478), .Y(n925) );
OAI22X1TS U2676 ( .A0(n546), .A1(n481), .B0(n480), .B1(n671), .Y(n924) );
OAI22X1TS U2677 ( .A0(n646), .A1(n483), .B0(n1517), .B1(n482), .Y(n923) );
XNOR2X1TS U2678 ( .A(n1849), .B(Data_B_i[8]), .Y(n555) );
OAI22X1TS U2679 ( .A0(n704), .A1(n555), .B0(n1390), .B1(n484), .Y(n553) );
XNOR2X1TS U2680 ( .A(n616), .B(Data_B_i[16]), .Y(n545) );
OAI22X1TS U2681 ( .A0(n546), .A1(n545), .B0(n485), .B1(n671), .Y(n552) );
XNOR2X1TS U2682 ( .A(n4051), .B(Data_B_i[14]), .Y(n554) );
OAI22X1TS U2683 ( .A0(n790), .A1(n554), .B0(n788), .B1(n486), .Y(n551) );
XNOR2X1TS U2684 ( .A(n3753), .B(Data_B_i[12]), .Y(n556) );
XNOR2X1TS U2685 ( .A(n3753), .B(Data_B_i[13]), .Y(n500) );
OAI22X1TS U2686 ( .A0(n2106), .A1(n556), .B0(n762), .B1(n500), .Y(n562) );
INVX2TS U2687 ( .A(n3455), .Y(n1645) );
XNOR2X1TS U2688 ( .A(n1645), .B(Data_B_i[10]), .Y(n544) );
BUFX3TS U2689 ( .A(n2964), .Y(n2108) );
XNOR2X1TS U2690 ( .A(n1645), .B(Data_B_i[11]), .Y(n514) );
OAI22X1TS U2691 ( .A0(n110), .A1(n544), .B0(n2108), .B1(n514), .Y(n561) );
CLKBUFX2TS U2692 ( .A(Data_B_i[0]), .Y(n3046) );
XNOR2X1TS U2693 ( .A(n81), .B(n3046), .Y(n491) );
OAI22X1TS U2694 ( .A0(n127), .A1(n491), .B0(n63), .B1(n490), .Y(n516) );
CLKBUFX2TS U2695 ( .A(n2472), .Y(n2864) );
INVX2TS U2696 ( .A(n5119), .Y(n3209) );
OAI22X1TS U2697 ( .A0(n127), .A1(n5119), .B0(n62), .B1(n492), .Y(n515) );
CLKBUFX2TS U2698 ( .A(n199), .Y(n2058) );
OAI22X1TS U2699 ( .A0(n704), .A1(n494), .B0(n2058), .B1(n493), .Y(n525) );
OAI22X1TS U2700 ( .A0(n127), .A1(n496), .B0(n63), .B1(n495), .Y(n524) );
OAI22X1TS U2701 ( .A0(n508), .A1(n498), .B0(n4593), .B1(n497), .Y(n523) );
OAI22X1TS U2702 ( .A0(n2106), .A1(n500), .B0(n762), .B1(n499), .Y(n512) );
INVX2TS U2703 ( .A(Data_B_i[5]), .Y(n3653) );
INVX2TS U2704 ( .A(n3653), .Y(n1493) );
XNOR2X1TS U2705 ( .A(n92), .B(n1493), .Y(n506) );
OAI22X1TS U2706 ( .A0(n4684), .A1(n506), .B0(n625), .B1(n501), .Y(n511) );
XNOR2X1TS U2707 ( .A(Data_A_i[11]), .B(Data_B_i[7]), .Y(n509) );
OAI22X1TS U2708 ( .A0(n646), .A1(n509), .B0(n1517), .B1(n502), .Y(n510) );
CMPR32X2TS U2709 ( .A(n505), .B(n504), .C(n503), .CO(n961), .S(n520) );
INVX2TS U2710 ( .A(n3652), .Y(n1400) );
XNOR2X1TS U2711 ( .A(Data_A_i[13]), .B(n1400), .Y(n549) );
OAI22X1TS U2712 ( .A0(n43), .A1(n549), .B0(n625), .B1(n506), .Y(n559) );
XNOR2X1TS U2713 ( .A(n2897), .B(Data_B_i[2]), .Y(n550) );
OAI22X1TS U2714 ( .A0(n508), .A1(n550), .B0(n4593), .B1(n507), .Y(n558) );
XNOR2X1TS U2715 ( .A(Data_A_i[11]), .B(n1641), .Y(n547) );
OAI22X1TS U2716 ( .A0(n646), .A1(n547), .B0(n1517), .B1(n509), .Y(n557) );
OAI22X1TS U2717 ( .A0(n110), .A1(n514), .B0(n733), .B1(n513), .Y(n537) );
ADDHXLTS U2718 ( .A(n516), .B(n515), .CO(n536), .S(n560) );
CMPR32X2TS U2719 ( .A(n522), .B(n521), .C(n520), .CO(n973), .S(n567) );
CMPR32X2TS U2720 ( .A(n531), .B(n530), .C(n529), .CO(n956), .S(n941) );
CMPR32X2TS U2721 ( .A(n537), .B(n536), .C(n535), .CO(n542), .S(n572) );
XNOR2X1TS U2722 ( .A(n723), .B(Data_B_i[9]), .Y(n581) );
OAI22X1TS U2723 ( .A0(n2967), .A1(n581), .B0(n1176), .B1(n544), .Y(n592) );
XNOR2X1TS U2724 ( .A(n616), .B(Data_B_i[15]), .Y(n587) );
OAI22X1TS U2725 ( .A0(n546), .A1(n587), .B0(n545), .B1(n671), .Y(n591) );
XNOR2X1TS U2726 ( .A(Data_A_i[11]), .B(n1493), .Y(n583) );
OAI22X1TS U2727 ( .A0(n646), .A1(n583), .B0(n1517), .B1(n547), .Y(n590) );
NOR2BX1TS U2728 ( .AN(n1726), .B(n548), .Y(n580) );
INVX2TS U2729 ( .A(Data_B_i[3]), .Y(n3773) );
INVX2TS U2730 ( .A(n3773), .Y(n1399) );
XNOR2X1TS U2731 ( .A(n2789), .B(n1399), .Y(n582) );
XNOR2X1TS U2732 ( .A(n3847), .B(Data_B_i[1]), .Y(n575) );
OAI22X1TS U2733 ( .A0(n1395), .A1(n575), .B0(n4091), .B1(n550), .Y(n578) );
CMPR32X2TS U2734 ( .A(n553), .B(n552), .C(n551), .CO(n565), .S(n584) );
XNOR2X1TS U2735 ( .A(n4051), .B(Data_B_i[13]), .Y(n606) );
OAI22X1TS U2736 ( .A0(n97), .A1(n606), .B0(n788), .B1(n554), .Y(n595) );
XNOR2X1TS U2737 ( .A(n728), .B(Data_B_i[7]), .Y(n588) );
OAI22X1TS U2738 ( .A0(n704), .A1(n588), .B0(n1390), .B1(n555), .Y(n594) );
XNOR2X1TS U2739 ( .A(Data_A_i[5]), .B(Data_B_i[11]), .Y(n589) );
OAI22X1TS U2740 ( .A0(n3754), .A1(n589), .B0(n762), .B1(n556), .Y(n593) );
CMPR32X2TS U2741 ( .A(n565), .B(n564), .C(n563), .CO(n568), .S(n596) );
XNOR2X1TS U2742 ( .A(n2705), .B(n3046), .Y(n576) );
OAI22X1TS U2743 ( .A0(n1395), .A1(n576), .B0(n4593), .B1(n575), .Y(n608) );
INVX2TS U2744 ( .A(n4398), .Y(n3847) );
OAI22X1TS U2745 ( .A0(n1395), .A1(n4398), .B0(n3213), .B1(n577), .Y(n607) );
XNOR2X1TS U2746 ( .A(n1645), .B(Data_B_i[8]), .Y(n614) );
OAI22X1TS U2747 ( .A0(n735), .A1(n614), .B0(n1176), .B1(n581), .Y(n620) );
INVX2TS U2748 ( .A(n4050), .Y(n1366) );
XNOR2X1TS U2749 ( .A(n92), .B(n1366), .Y(n610) );
XNOR2X1TS U2750 ( .A(Data_A_i[11]), .B(n1400), .Y(n609) );
OAI22X1TS U2751 ( .A0(n646), .A1(n609), .B0(n1517), .B1(n583), .Y(n618) );
CMPR32X2TS U2752 ( .A(n586), .B(n585), .C(n584), .CO(n598), .S(n629) );
XNOR2X1TS U2753 ( .A(n616), .B(Data_B_i[14]), .Y(n617) );
OAI22X1TS U2754 ( .A0(n99), .A1(n617), .B0(n587), .B1(n671), .Y(n640) );
XNOR2X1TS U2755 ( .A(n728), .B(n1641), .Y(n615) );
OAI22X1TS U2756 ( .A0(n704), .A1(n615), .B0(n1390), .B1(n588), .Y(n639) );
XNOR2X1TS U2757 ( .A(Data_A_i[5]), .B(Data_B_i[10]), .Y(n623) );
BUFX3TS U2758 ( .A(n622), .Y(n1812) );
OAI22X1TS U2759 ( .A0(n3754), .A1(n623), .B0(n1812), .B1(n589), .Y(n638) );
NOR2X1TS U2760 ( .A(n909), .B(n908), .Y(n599) );
INVX2TS U2761 ( .A(n599), .Y(n7245) );
CMPR32X2TS U2762 ( .A(n605), .B(n604), .C(n603), .CO(n597), .S(n634) );
XNOR2X1TS U2763 ( .A(n2511), .B(Data_B_i[12]), .Y(n621) );
OAI22X1TS U2764 ( .A0(n97), .A1(n621), .B0(n788), .B1(n606), .Y(n643) );
NOR2BX1TS U2765 ( .AN(Data_B_i[0]), .B(n48), .Y(n650) );
XNOR2X1TS U2766 ( .A(Data_A_i[11]), .B(n1399), .Y(n645) );
OAI22X1TS U2767 ( .A0(n646), .A1(n645), .B0(n1517), .B1(n609), .Y(n649) );
XNOR2X1TS U2768 ( .A(n2789), .B(n1036), .Y(n624) );
OAI22X1TS U2769 ( .A0(n2525), .A1(n624), .B0(n625), .B1(n610), .Y(n648) );
XNOR2X1TS U2770 ( .A(n723), .B(Data_B_i[7]), .Y(n660) );
OAI22X1TS U2771 ( .A0(n110), .A1(n660), .B0(n1176), .B1(n614), .Y(n653) );
XNOR2X1TS U2772 ( .A(n728), .B(n1493), .Y(n647) );
OAI22X1TS U2773 ( .A0(n704), .A1(n647), .B0(n1390), .B1(n615), .Y(n652) );
XNOR2X1TS U2774 ( .A(n616), .B(Data_B_i[13]), .Y(n661) );
OAI22X1TS U2775 ( .A0(n3275), .A1(n661), .B0(n617), .B1(n671), .Y(n651) );
XNOR2X1TS U2776 ( .A(n2511), .B(Data_B_i[11]), .Y(n662) );
OAI22X1TS U2777 ( .A0(n838), .A1(n662), .B0(n788), .B1(n621), .Y(n665) );
XNOR2X1TS U2778 ( .A(Data_A_i[5]), .B(Data_B_i[9]), .Y(n644) );
OAI22X1TS U2779 ( .A0(n3754), .A1(n644), .B0(n1054), .B1(n623), .Y(n664) );
XNOR2X1TS U2780 ( .A(n2789), .B(n774), .Y(n626) );
OAI22X1TS U2781 ( .A0(n43), .A1(n626), .B0(n625), .B1(n624), .Y(n667) );
OAI22X1TS U2782 ( .A0(n40), .A1(n4252), .B0(n1105), .B1(n627), .Y(n666) );
INVX2TS U2783 ( .A(n631), .Y(n7250) );
CMPR32X2TS U2784 ( .A(n637), .B(n636), .C(n635), .CO(n628), .S(n718) );
CMPR32X2TS U2785 ( .A(n640), .B(n639), .C(n638), .CO(n637), .S(n676) );
CMPR32X2TS U2786 ( .A(n643), .B(n642), .C(n641), .CO(n656), .S(n675) );
XNOR2X1TS U2787 ( .A(n100), .B(Data_B_i[8]), .Y(n670) );
OAI22X1TS U2788 ( .A0(n142), .A1(n670), .B0(n1054), .B1(n644), .Y(n682) );
XNOR2X1TS U2789 ( .A(Data_A_i[11]), .B(n1366), .Y(n669) );
OAI22X1TS U2790 ( .A0(n646), .A1(n669), .B0(n1517), .B1(n645), .Y(n681) );
XNOR2X1TS U2791 ( .A(n728), .B(n1400), .Y(n668) );
OAI22X1TS U2792 ( .A0(n704), .A1(n668), .B0(n1390), .B1(n647), .Y(n680) );
CMPR32X2TS U2793 ( .A(n653), .B(n652), .C(n651), .CO(n659), .S(n677) );
NOR2X1TS U2794 ( .A(n903), .B(n902), .Y(n7248) );
INVX2TS U2795 ( .A(n7248), .Y(n7748) );
NAND2X1TS U2796 ( .A(n7250), .B(n7748), .Y(n7243) );
CMPR32X2TS U2797 ( .A(n659), .B(n658), .C(n657), .CO(n654), .S(n721) );
XNOR2X1TS U2798 ( .A(n723), .B(n1641), .Y(n673) );
OAI22X1TS U2799 ( .A0(n735), .A1(n673), .B0(n1176), .B1(n660), .Y(n685) );
XNOR2X1TS U2800 ( .A(n773), .B(Data_B_i[12]), .Y(n672) );
OAI22X1TS U2801 ( .A0(n842), .A1(n672), .B0(n661), .B1(n671), .Y(n684) );
XNOR2X1TS U2802 ( .A(n2511), .B(Data_B_i[10]), .Y(n686) );
OAI22X1TS U2803 ( .A0(n838), .A1(n686), .B0(n1706), .B1(n662), .Y(n683) );
CMPR32X2TS U2804 ( .A(n665), .B(n664), .C(n663), .CO(n657), .S(n694) );
ADDHXLTS U2805 ( .A(n667), .B(n666), .CO(n663), .S(n701) );
NOR2BX1TS U2806 ( .AN(n1726), .B(n85), .Y(n692) );
XNOR2X1TS U2807 ( .A(n728), .B(n1399), .Y(n703) );
OAI22X1TS U2808 ( .A0(n704), .A1(n703), .B0(n1390), .B1(n668), .Y(n691) );
XNOR2X1TS U2809 ( .A(Data_A_i[11]), .B(n1036), .Y(n687) );
OAI22X1TS U2810 ( .A0(n1140), .A1(n687), .B0(n1138), .B1(n669), .Y(n690) );
XNOR2X1TS U2811 ( .A(n100), .B(Data_B_i[7]), .Y(n702) );
OAI22X1TS U2812 ( .A0(n142), .A1(n702), .B0(n1054), .B1(n670), .Y(n708) );
XNOR2X1TS U2813 ( .A(n1165), .B(Data_B_i[11]), .Y(n705) );
OAI22X1TS U2814 ( .A0(n842), .A1(n705), .B0(n672), .B1(n671), .Y(n707) );
XNOR2X1TS U2815 ( .A(n723), .B(n1493), .Y(n710) );
OAI22X1TS U2816 ( .A0(n735), .A1(n710), .B0(n1176), .B1(n673), .Y(n706) );
CMPR32X2TS U2817 ( .A(n679), .B(n678), .C(n677), .CO(n674), .S(n698) );
CMPR32X2TS U2818 ( .A(n682), .B(n681), .C(n680), .CO(n679), .S(n715) );
CMPR32X2TS U2819 ( .A(n685), .B(n684), .C(n683), .CO(n695), .S(n714) );
XNOR2X1TS U2820 ( .A(n117), .B(Data_B_i[9]), .Y(n709) );
CLKBUFX2TS U2821 ( .A(n2512), .Y(n1108) );
OAI22X1TS U2822 ( .A0(n838), .A1(n709), .B0(n1108), .B1(n686), .Y(n874) );
XNOR2X1TS U2823 ( .A(n2503), .B(n774), .Y(n688) );
OAI22X1TS U2824 ( .A0(n1140), .A1(n688), .B0(n1517), .B1(n687), .Y(n712) );
CLKBUFX2TS U2825 ( .A(n1019), .Y(n3523) );
INVX2TS U2826 ( .A(n1019), .Y(n3927) );
OAI22X1TS U2827 ( .A0(n1140), .A1(n3523), .B0(n1138), .B1(n689), .Y(n711) );
CMPR32X2TS U2828 ( .A(n701), .B(n700), .C(n699), .CO(n693), .S(n871) );
XNOR2X1TS U2829 ( .A(n100), .B(n1641), .Y(n834) );
OAI22X1TS U2830 ( .A0(n142), .A1(n834), .B0(n1054), .B1(n702), .Y(n845) );
XNOR2X1TS U2831 ( .A(n728), .B(n1366), .Y(n825) );
OAI22X1TS U2832 ( .A0(n704), .A1(n825), .B0(n1390), .B1(n703), .Y(n844) );
XNOR2X1TS U2833 ( .A(n1165), .B(Data_B_i[10]), .Y(n840) );
OAI22X1TS U2834 ( .A0(n842), .A1(n840), .B0(n705), .B1(n1346), .Y(n843) );
XNOR2X1TS U2835 ( .A(n35), .B(Data_B_i[8]), .Y(n836) );
OAI22X1TS U2836 ( .A0(n838), .A1(n836), .B0(n1108), .B1(n709), .Y(n819) );
XNOR2X1TS U2837 ( .A(n723), .B(n1400), .Y(n822) );
OAI22X1TS U2838 ( .A0(n824), .A1(n822), .B0(n1176), .B1(n710), .Y(n818) );
ADDHXLTS U2839 ( .A(n712), .B(n711), .CO(n873), .S(n817) );
CMPR32X2TS U2840 ( .A(n715), .B(n714), .C(n713), .CO(n697), .S(n869) );
NOR2X1TS U2841 ( .A(n894), .B(n893), .Y(n7254) );
NOR2X1TS U2842 ( .A(n7762), .B(n7254), .Y(n7753) );
OR2X2TS U2843 ( .A(n898), .B(n897), .Y(n7755) );
NAND2X1TS U2844 ( .A(n7753), .B(n7755), .Y(n901) );
XNOR2X1TS U2845 ( .A(n101), .B(n1400), .Y(n731) );
XNOR2X1TS U2846 ( .A(n100), .B(n1493), .Y(n835) );
OAI22X1TS U2847 ( .A0(n3754), .A1(n731), .B0(n1054), .B1(n835), .Y(n830) );
XNOR2X1TS U2848 ( .A(n723), .B(n1366), .Y(n732) );
XNOR2X1TS U2849 ( .A(n723), .B(n1399), .Y(n823) );
XNOR2X1TS U2850 ( .A(n36), .B(n1641), .Y(n722) );
XNOR2X1TS U2851 ( .A(n117), .B(Data_B_i[7]), .Y(n837) );
OAI22X1TS U2852 ( .A0(n838), .A1(n722), .B0(n1108), .B1(n837), .Y(n828) );
XNOR2X1TS U2853 ( .A(n773), .B(Data_B_i[7]), .Y(n739) );
XNOR2X1TS U2854 ( .A(n1165), .B(Data_B_i[8]), .Y(n727) );
OAI22X1TS U2855 ( .A0(n842), .A1(n739), .B0(n727), .B1(n839), .Y(n744) );
XNOR2X1TS U2856 ( .A(n117), .B(n1493), .Y(n741) );
OAI22X1TS U2857 ( .A0(n838), .A1(n741), .B0(n1108), .B1(n722), .Y(n743) );
XNOR2X1TS U2858 ( .A(n723), .B(n774), .Y(n724) );
XNOR2X1TS U2859 ( .A(n723), .B(n1036), .Y(n734) );
OAI22X1TS U2860 ( .A0(n2110), .A1(n724), .B0(n1176), .B1(n734), .Y(n749) );
OAI22X1TS U2861 ( .A0(n824), .A1(n726), .B0(n733), .B1(n725), .Y(n748) );
XNOR2X1TS U2862 ( .A(n773), .B(Data_B_i[9]), .Y(n841) );
OAI22X1TS U2863 ( .A0(n842), .A1(n727), .B0(n841), .B1(n839), .Y(n851) );
XNOR2X1TS U2864 ( .A(n728), .B(n774), .Y(n729) );
XNOR2X1TS U2865 ( .A(n728), .B(n1036), .Y(n827) );
OAI22X1TS U2866 ( .A0(n1096), .A1(n3398), .B0(n826), .B1(n730), .Y(n820) );
NOR2BX1TS U2867 ( .AN(n3272), .B(n3361), .Y(n738) );
XNOR2X1TS U2868 ( .A(n100), .B(n1399), .Y(n740) );
OAI22X1TS U2869 ( .A0(n142), .A1(n740), .B0(n1054), .B1(n731), .Y(n737) );
OAI22X1TS U2870 ( .A0(n110), .A1(n734), .B0(n733), .B1(n732), .Y(n736) );
XNOR2X1TS U2871 ( .A(n773), .B(n1641), .Y(n750) );
OAI22X1TS U2872 ( .A0(n842), .A1(n750), .B0(n739), .B1(n839), .Y(n754) );
XNOR2X1TS U2873 ( .A(n101), .B(n1366), .Y(n751) );
OAI22X1TS U2874 ( .A0(n142), .A1(n751), .B0(n1054), .B1(n740), .Y(n753) );
XNOR2X1TS U2875 ( .A(n117), .B(n1400), .Y(n758) );
OAI22X1TS U2876 ( .A0(n838), .A1(n758), .B0(n1108), .B1(n741), .Y(n752) );
CMPR32X2TS U2877 ( .A(n744), .B(n743), .C(n742), .CO(n859), .S(n745) );
CMPR32X2TS U2878 ( .A(n747), .B(n746), .C(n745), .CO(n813), .S(n812) );
ADDHXLTS U2879 ( .A(n749), .B(n748), .CO(n742), .S(n757) );
NOR2BX1TS U2880 ( .AN(n1726), .B(n177), .Y(n765) );
XNOR2X1TS U2881 ( .A(n773), .B(n1493), .Y(n769) );
OAI22X1TS U2882 ( .A0(n842), .A1(n769), .B0(n750), .B1(n839), .Y(n764) );
XNOR2X1TS U2883 ( .A(n101), .B(n1036), .Y(n759) );
OAI22X1TS U2884 ( .A0(n143), .A1(n759), .B0(n762), .B1(n751), .Y(n763) );
CMPR32X2TS U2885 ( .A(n754), .B(n753), .C(n752), .CO(n746), .S(n755) );
NOR2X1TS U2886 ( .A(n812), .B(n811), .Y(n7778) );
CMPR32X2TS U2887 ( .A(n757), .B(n756), .C(n755), .CO(n811), .S(n807) );
XNOR2X1TS U2888 ( .A(n2511), .B(n1399), .Y(n770) );
OAI22X1TS U2889 ( .A0(n838), .A1(n770), .B0(n1108), .B1(n758), .Y(n768) );
XNOR2X1TS U2890 ( .A(n100), .B(n774), .Y(n760) );
OAI22X1TS U2891 ( .A0(n144), .A1(n760), .B0(n1054), .B1(n759), .Y(n772) );
INVX2TS U2892 ( .A(n1816), .Y(n4097) );
OAI22X1TS U2893 ( .A0(n143), .A1(n1816), .B0(n762), .B1(n761), .Y(n771) );
CMPR32X2TS U2894 ( .A(n765), .B(n764), .C(n763), .CO(n756), .S(n766) );
CMPR32X2TS U2895 ( .A(n768), .B(n767), .C(n766), .CO(n806), .S(n805) );
XNOR2X1TS U2896 ( .A(n773), .B(n1400), .Y(n785) );
OAI22X1TS U2897 ( .A0(n842), .A1(n785), .B0(n769), .B1(n839), .Y(n797) );
XNOR2X1TS U2898 ( .A(Data_A_i[3]), .B(n1366), .Y(n787) );
OAI22X1TS U2899 ( .A0(n838), .A1(n787), .B0(n1108), .B1(n770), .Y(n796) );
ADDHXLTS U2900 ( .A(n772), .B(n771), .CO(n767), .S(n795) );
NAND2X1TS U2901 ( .A(n3), .B(n22), .Y(n810) );
XNOR2X1TS U2902 ( .A(n773), .B(n1366), .Y(n777) );
XNOR2X1TS U2903 ( .A(n773), .B(n1399), .Y(n786) );
OAI22X1TS U2904 ( .A0(n2093), .A1(n777), .B0(n786), .B1(n839), .Y(n792) );
XNOR2X1TS U2905 ( .A(n117), .B(n774), .Y(n775) );
XNOR2X1TS U2906 ( .A(n117), .B(n1036), .Y(n789) );
OAI22X1TS U2907 ( .A0(n790), .A1(n775), .B0(n1108), .B1(n789), .Y(n791) );
OAI22X1TS U2908 ( .A0(n790), .A1(n3276), .B0(n788), .B1(n776), .Y(n782) );
OAI22X1TS U2909 ( .A0(n2093), .A1(n778), .B0(n777), .B1(n839), .Y(n780) );
NOR2BX1TS U2910 ( .AN(n1726), .B(n3990), .Y(n779) );
NAND2X1TS U2911 ( .A(n780), .B(n779), .Y(n7280) );
NAND2X1TS U2912 ( .A(n783), .B(n782), .Y(n7277) );
AOI21X1TS U2913 ( .A0(n7278), .A1(n151), .B0(n784), .Y(n7791) );
NOR2BX1TS U2914 ( .AN(n3272), .B(n88), .Y(n800) );
OAI22X1TS U2915 ( .A0(n2093), .A1(n786), .B0(n785), .B1(n839), .Y(n799) );
OAI22X1TS U2916 ( .A0(n790), .A1(n789), .B0(n788), .B1(n787), .Y(n798) );
ADDHXLTS U2917 ( .A(n792), .B(n791), .CO(n793), .S(n783) );
NAND2X1TS U2918 ( .A(n794), .B(n793), .Y(n7789) );
CMPR32X2TS U2919 ( .A(n797), .B(n796), .C(n795), .CO(n804), .S(n802) );
CMPR32X2TS U2920 ( .A(n800), .B(n799), .C(n798), .CO(n801), .S(n794) );
NAND2X1TS U2921 ( .A(n802), .B(n801), .Y(n7274) );
AOI21X1TS U2922 ( .A0(n7275), .A1(n23), .B0(n803), .Y(n7272) );
NAND2X1TS U2923 ( .A(n805), .B(n804), .Y(n7271) );
NAND2X1TS U2924 ( .A(n807), .B(n806), .Y(n7785) );
AOI21X1TS U2925 ( .A0(n3), .A1(n7783), .B0(n808), .Y(n809) );
OAI21X1TS U2926 ( .A0(n810), .A1(n7272), .B0(n809), .Y(n7265) );
NAND2X1TS U2927 ( .A(n812), .B(n811), .Y(n7779) );
NAND2X1TS U2928 ( .A(n814), .B(n813), .Y(n7267) );
AOI21X1TS U2929 ( .A0(n816), .A1(n7265), .B0(n815), .Y(n7262) );
CMPR32X2TS U2930 ( .A(n819), .B(n818), .C(n817), .CO(n878), .S(n886) );
ADDHXLTS U2931 ( .A(n821), .B(n820), .CO(n854), .S(n850) );
NOR2BX1TS U2932 ( .AN(Data_B_i[0]), .B(n111), .Y(n833) );
OAI22X1TS U2933 ( .A0(n735), .A1(n823), .B0(n1176), .B1(n822), .Y(n832) );
OAI22X1TS U2934 ( .A0(n1096), .A1(n827), .B0(n826), .B1(n825), .Y(n831) );
CMPR32X2TS U2935 ( .A(n830), .B(n829), .C(n828), .CO(n852), .S(n860) );
OAI22X1TS U2936 ( .A0(n3754), .A1(n835), .B0(n1054), .B1(n834), .Y(n848) );
OAI22X1TS U2937 ( .A0(n838), .A1(n837), .B0(n1108), .B1(n836), .Y(n847) );
OAI22X1TS U2938 ( .A0(n842), .A1(n841), .B0(n840), .B1(n839), .Y(n846) );
CMPR32X2TS U2939 ( .A(n845), .B(n844), .C(n843), .CO(n880), .S(n875) );
CMPR32X2TS U2940 ( .A(n848), .B(n847), .C(n846), .CO(n876), .S(n857) );
CMPR32X2TS U2941 ( .A(n851), .B(n850), .C(n849), .CO(n856), .S(n858) );
CMPR32X2TS U2942 ( .A(n857), .B(n856), .C(n855), .CO(n864), .S(n863) );
NOR2X1TS U2943 ( .A(n863), .B(n862), .Y(n861) );
INVX2TS U2944 ( .A(n861), .Y(n7773) );
NAND2X1TS U2945 ( .A(n20), .B(n7773), .Y(n868) );
NAND2X1TS U2946 ( .A(n863), .B(n862), .Y(n7263) );
INVX2TS U2947 ( .A(n7263), .Y(n7772) );
NAND2X1TS U2948 ( .A(n865), .B(n864), .Y(n7775) );
CMPR32X2TS U2949 ( .A(n871), .B(n870), .C(n869), .CO(n893), .S(n890) );
CMPR32X2TS U2950 ( .A(n874), .B(n873), .C(n872), .CO(n713), .S(n883) );
CMPR32X2TS U2951 ( .A(n880), .B(n879), .C(n878), .CO(n870), .S(n881) );
NOR2X1TS U2952 ( .A(n890), .B(n889), .Y(n7257) );
CMPR32X2TS U2953 ( .A(n883), .B(n882), .C(n881), .CO(n889), .S(n888) );
CMPR32X2TS U2954 ( .A(n886), .B(n885), .C(n884), .CO(n887), .S(n865) );
NOR2X1TS U2955 ( .A(n888), .B(n887), .Y(n7767) );
NAND2X1TS U2956 ( .A(n888), .B(n887), .Y(n7768) );
NAND2X1TS U2957 ( .A(n890), .B(n889), .Y(n7258) );
AOI21X2TS U2958 ( .A0(n7256), .A1(n892), .B0(n891), .Y(n7253) );
NAND2X1TS U2959 ( .A(n896), .B(n895), .Y(n7763) );
OAI21X1TS U2960 ( .A0(n7762), .A1(n7758), .B0(n7763), .Y(n7752) );
NAND2X1TS U2961 ( .A(n898), .B(n897), .Y(n7754) );
AOI21X2TS U2962 ( .A0(n7752), .A1(n7755), .B0(n899), .Y(n900) );
OAI21X2TS U2963 ( .A0(n901), .A1(n7253), .B0(n900), .Y(n7233) );
INVX2TS U2964 ( .A(n7749), .Y(n907) );
INVX2TS U2965 ( .A(n7249), .Y(n906) );
AOI21X4TS U2966 ( .A0(n7250), .A1(n907), .B0(n906), .Y(n7242) );
INVX2TS U2967 ( .A(n7244), .Y(n7235) );
INVX2TS U2968 ( .A(n7239), .Y(n912) );
CMPR32X2TS U2969 ( .A(n925), .B(n924), .C(n923), .CO(n955), .S(n938) );
CMPR32X2TS U2970 ( .A(n931), .B(n930), .C(n929), .CO(n934), .S(n953) );
CMPR32X2TS U2971 ( .A(n937), .B(n936), .C(n935), .CO(n932), .S(n970) );
CMPR32X2TS U2972 ( .A(n943), .B(n942), .C(n941), .CO(n968), .S(n972) );
NOR2X4TS U2973 ( .A(n990), .B(n989), .Y(n7727) );
CMPR32X2TS U2974 ( .A(n955), .B(n954), .C(n953), .CO(n964), .S(n976) );
CMPR32X2TS U2975 ( .A(n958), .B(n957), .C(n956), .CO(n951), .S(n975) );
CMPR32X2TS U2976 ( .A(n961), .B(n960), .C(n959), .CO(n974), .S(n982) );
NOR2X2TS U2977 ( .A(n986), .B(n985), .Y(n7735) );
ADDFHX2TS U2978 ( .A(n982), .B(n981), .CI(n980), .CO(n983), .S(n911) );
NOR2X1TS U2979 ( .A(n984), .B(n983), .Y(n7231) );
NOR2X1TS U2980 ( .A(n7735), .B(n7231), .Y(n7741) );
NAND2X1TS U2981 ( .A(n992), .B(n7741), .Y(n994) );
NAND2X1TS U2982 ( .A(n986), .B(n985), .Y(n7736) );
NAND2X1TS U2983 ( .A(n990), .B(n989), .Y(n7728) );
INVX2TS U2984 ( .A(n7719), .Y(n1000) );
NAND2X1TS U2985 ( .A(n998), .B(n997), .Y(n7227) );
INVX2TS U2986 ( .A(n7227), .Y(n999) );
AOI21X4TS U2987 ( .A0(n19), .A1(n1000), .B0(n999), .Y(n7220) );
NAND2X1TS U2988 ( .A(n1002), .B(n1001), .Y(n7222) );
NAND2X1TS U2989 ( .A(n1004), .B(n1003), .Y(n7216) );
OAI21X2TS U2990 ( .A0(n1007), .A1(n7220), .B0(n1006), .Y(n1008) );
AOI21X4TS U2991 ( .A0(n7210), .A1(n1009), .B0(n1008), .Y(n7207) );
XNOR2X1TS U2992 ( .A(n4076), .B(Data_B_i[5]), .Y(n1027) );
XNOR2X1TS U2993 ( .A(n5760), .B(Data_B_i[6]), .Y(n1179) );
OAI22X1TS U2994 ( .A0(n39), .A1(n1027), .B0(n3074), .B1(n1179), .Y(n1030) );
INVX2TS U2995 ( .A(Data_B_i[27]), .Y(n5863) );
XNOR2X1TS U2996 ( .A(n101), .B(n3073), .Y(n1053) );
INVX2TS U2997 ( .A(Data_B_i[28]), .Y(n5937) );
INVX2TS U2998 ( .A(n5937), .Y(n3704) );
XNOR2X1TS U2999 ( .A(n100), .B(n3704), .Y(n1163) );
OAI22X1TS U3000 ( .A0(n2638), .A1(n1053), .B0(n1812), .B1(n1163), .Y(n1029)
);
INVX2TS U3001 ( .A(n5292), .Y(n5086) );
XNOR2X1TS U3002 ( .A(n5086), .B(n1898), .Y(n1051) );
XNOR2X1TS U3003 ( .A(n5086), .B(n2284), .Y(n1174) );
OAI22X1TS U3004 ( .A0(n150), .A1(n1051), .B0(n1514), .B1(n1174), .Y(n1028)
);
XOR2X1TS U3005 ( .A(Data_A_i[32]), .B(Data_A_i[33]), .Y(n1010) );
XNOR2X4TS U3006 ( .A(Data_A_i[32]), .B(Data_A_i[31]), .Y(n2935) );
NAND2X2TS U3007 ( .A(n1010), .B(n2935), .Y(n4422) );
INVX2TS U3008 ( .A(n6250), .Y(n1860) );
XNOR2X1TS U3009 ( .A(n1860), .B(n3046), .Y(n1011) );
XNOR2X1TS U3010 ( .A(n114), .B(n1036), .Y(n1367) );
OAI22X1TS U3011 ( .A0(n6252), .A1(n1011), .B0(n5144), .B1(n1367), .Y(n1365)
);
OAI22X1TS U3012 ( .A0(n120), .A1(n6250), .B0(n59), .B1(n1012), .Y(n1364) );
INVX2TS U3013 ( .A(n5584), .Y(n3220) );
XNOR2X1TS U3014 ( .A(n3220), .B(n1991), .Y(n1063) );
XNOR2X1TS U3015 ( .A(n3220), .B(n1856), .Y(n1381) );
OAI22X1TS U3016 ( .A0(n5586), .A1(n1063), .B0(n196), .B1(n1381), .Y(n1362)
);
BUFX3TS U3017 ( .A(n2935), .Y(n6182) );
NOR2BX1TS U3018 ( .AN(n1726), .B(n5144), .Y(n1018) );
INVX2TS U3019 ( .A(n6002), .Y(n1482) );
XNOR2X1TS U3020 ( .A(n1482), .B(n1399), .Y(n1026) );
XNOR2X1TS U3021 ( .A(n1482), .B(n1400), .Y(n1175) );
OAI22X1TS U3022 ( .A0(n5251), .A1(n1026), .B0(n4746), .B1(n1175), .Y(n1017)
);
XOR2X1TS U3023 ( .A(Data_A_i[30]), .B(Data_A_i[31]), .Y(n1015) );
XOR2X4TS U3024 ( .A(n6002), .B(Data_A_i[30]), .Y(n4391) );
INVX2TS U3025 ( .A(n6123), .Y(n1814) );
XNOR2X1TS U3026 ( .A(n3986), .B(n1036), .Y(n1070) );
XNOR2X1TS U3027 ( .A(n106), .B(n1366), .Y(n1162) );
OAI22X1TS U3028 ( .A0(n147), .A1(n1070), .B0(n91), .B1(n1162), .Y(n1016) );
XNOR2X1TS U3029 ( .A(n3040), .B(n1991), .Y(n1031) );
XNOR2X1TS U3030 ( .A(n3616), .B(n1856), .Y(n1062) );
OAI22X1TS U3031 ( .A0(n71), .A1(n1031), .B0(n4743), .B1(n1062), .Y(n1034) );
INVX2TS U3032 ( .A(n1019), .Y(n4133) );
XNOR2X1TS U3033 ( .A(n4133), .B(n2936), .Y(n1035) );
BUFX3TS U3034 ( .A(n1020), .Y(n3251) );
XNOR2X1TS U3035 ( .A(n3374), .B(Data_B_i[21]), .Y(n1068) );
XNOR2X1TS U3036 ( .A(n4373), .B(n2284), .Y(n1050) );
INVX2TS U3037 ( .A(Data_B_i[15]), .Y(n4419) );
INVX2TS U3038 ( .A(n4419), .Y(n2461) );
XNOR2X1TS U3039 ( .A(n4373), .B(n2461), .Y(n1021) );
OAI22X1TS U3040 ( .A0(n127), .A1(n1050), .B0(n62), .B1(n1021), .Y(n1032) );
XNOR2X1TS U3041 ( .A(n2965), .B(Data_B_i[25]), .Y(n1056) );
XNOR2X1TS U3042 ( .A(n1645), .B(n3985), .Y(n1177) );
XNOR2X1TS U3043 ( .A(n4373), .B(n2353), .Y(n1154) );
XNOR2X1TS U3044 ( .A(n3349), .B(n3781), .Y(n1046) );
XNOR2X1TS U3045 ( .A(n3349), .B(n2936), .Y(n1153) );
OAI22X1TS U3046 ( .A0(n4684), .A1(n1046), .B0(n1105), .B1(n1153), .Y(n1149)
);
XNOR2X1TS U3047 ( .A(n4089), .B(n2573), .Y(n1025) );
XNOR2X1TS U3048 ( .A(n2897), .B(n2804), .Y(n1164) );
OAI22X1TS U3049 ( .A0(n1395), .A1(n1025), .B0(n4593), .B1(n1164), .Y(n1173)
);
INVX2TS U3050 ( .A(Data_B_i[31]), .Y(n6145) );
INVX2TS U3051 ( .A(n6145), .Y(n3497) );
XNOR2X1TS U3052 ( .A(n1165), .B(n3497), .Y(n1048) );
XNOR2X1TS U3053 ( .A(n3042), .B(Data_B_i[32]), .Y(n1166) );
OAI22X1TS U3054 ( .A0(n99), .A1(n1048), .B0(n1166), .B1(n1346), .Y(n1172) );
INVX2TS U3055 ( .A(Data_B_i[29]), .Y(n5939) );
INVX2TS U3056 ( .A(n5939), .Y(n3930) );
XNOR2X1TS U3057 ( .A(n2511), .B(n3930), .Y(n1049) );
INVX2TS U3058 ( .A(n6061), .Y(n3738) );
XNOR2X1TS U3059 ( .A(n2511), .B(n3738), .Y(n1167) );
OAI22X1TS U3060 ( .A0(n97), .A1(n1049), .B0(n1706), .B1(n1167), .Y(n1171) );
XNOR2X1TS U3061 ( .A(n94), .B(n2353), .Y(n1121) );
OAI22X1TS U3062 ( .A0(n1395), .A1(n1121), .B0(n1393), .B1(n1025), .Y(n1045)
);
XNOR2X1TS U3063 ( .A(n1482), .B(n1366), .Y(n1040) );
XNOR2X1TS U3064 ( .A(n1660), .B(Data_B_i[4]), .Y(n1039) );
OAI22X1TS U3065 ( .A0(n2633), .A1(n1039), .B0(n3074), .B1(n1027), .Y(n1043)
);
CMPR32X2TS U3066 ( .A(n1030), .B(n1029), .C(n1028), .CO(n1451), .S(n1168) );
XNOR2X1TS U3067 ( .A(n5520), .B(Data_B_i[5]), .Y(n1130) );
XNOR2X1TS U3068 ( .A(n1468), .B(Data_B_i[6]), .Y(n1059) );
OAI22X1TS U3069 ( .A0(n1470), .A1(n1130), .B0(n2928), .B1(n1059), .Y(n1204)
);
XNOR2X1TS U3070 ( .A(n3769), .B(n1691), .Y(n1126) );
XNOR2X1TS U3071 ( .A(n3769), .B(n1989), .Y(n1060) );
OAI22X1TS U3072 ( .A0(n5519), .A1(n1126), .B0(n2516), .B1(n1060), .Y(n1203)
);
XNOR2X1TS U3073 ( .A(n133), .B(n1813), .Y(n1097) );
OAI22X1TS U3074 ( .A0(n70), .A1(n1097), .B0(n124), .B1(n1031), .Y(n1202) );
XNOR2X1TS U3075 ( .A(n3374), .B(n5114), .Y(n1137) );
OAI22X1TS U3076 ( .A0(n1140), .A1(n1137), .B0(n3251), .B1(n1035), .Y(n1084)
);
XNOR2X1TS U3077 ( .A(n1482), .B(n3046), .Y(n1037) );
XNOR2X1TS U3078 ( .A(n1482), .B(n1036), .Y(n1041) );
OAI22X1TS U3079 ( .A0(n5251), .A1(n1037), .B0(n4746), .B1(n1041), .Y(n1142)
);
BUFX3TS U3080 ( .A(n5249), .Y(n2494) );
INVX2TS U3081 ( .A(n6002), .Y(n5800) );
OAI22X1TS U3082 ( .A0(n5945), .A1(n6002), .B0(n2494), .B1(n1038), .Y(n1141)
);
NOR2BX1TS U3083 ( .AN(n2871), .B(n4391), .Y(n1120) );
XNOR2X1TS U3084 ( .A(n98), .B(Data_B_i[3]), .Y(n1128) );
OAI22X1TS U3085 ( .A0(n131), .A1(n1041), .B0(n2494), .B1(n1040), .Y(n1118)
);
XNOR2X1TS U3086 ( .A(n3397), .B(Data_B_i[21]), .Y(n1094) );
INVX2TS U3087 ( .A(Data_B_i[22]), .Y(n5516) );
INVX2TS U3088 ( .A(n5516), .Y(n2896) );
XNOR2X1TS U3089 ( .A(n2343), .B(n2896), .Y(n1058) );
OAI22X1TS U3090 ( .A0(n3072), .A1(n1094), .B0(n2984), .B1(n1058), .Y(n1134)
);
XNOR2X1TS U3091 ( .A(n2859), .B(n1856), .Y(n1110) );
XNOR2X1TS U3092 ( .A(n1042), .B(n1859), .Y(n1052) );
XNOR2X1TS U3093 ( .A(n3349), .B(n2573), .Y(n1104) );
XNOR2X1TS U3094 ( .A(n3349), .B(n2804), .Y(n1047) );
OAI22X1TS U3095 ( .A0(n40), .A1(n1104), .B0(n1105), .B1(n1047), .Y(n1132) );
OAI22X1TS U3096 ( .A0(n41), .A1(n1047), .B0(n1105), .B1(n1046), .Y(n1183) );
XNOR2X1TS U3097 ( .A(n1165), .B(n3738), .Y(n1122) );
OAI22X1TS U3098 ( .A0(n3275), .A1(n1122), .B0(n1048), .B1(n1346), .Y(n1182)
);
XNOR2X1TS U3099 ( .A(n117), .B(Data_B_i[28]), .Y(n1124) );
OAI22X1TS U3100 ( .A0(n97), .A1(n1124), .B0(n1706), .B1(n1049), .Y(n1181) );
XNOR2X1TS U3101 ( .A(n4373), .B(n1898), .Y(n1099) );
OAI22X1TS U3102 ( .A0(n2904), .A1(n1099), .B0(n64), .B1(n1050), .Y(n1213) );
XNOR2X1TS U3103 ( .A(n2552), .B(Data_B_i[25]), .Y(n1112) );
XNOR2X1TS U3104 ( .A(n100), .B(n3985), .Y(n1055) );
OAI22X1TS U3105 ( .A0(n2638), .A1(n1112), .B0(n7), .B1(n1055), .Y(n1212) );
XNOR2X1TS U3106 ( .A(n2965), .B(Data_B_i[23]), .Y(n1114) );
XNOR2X1TS U3107 ( .A(n2965), .B(Data_B_i[24]), .Y(n1057) );
OAI22X1TS U3108 ( .A0(n110), .A1(n1114), .B0(n2781), .B1(n1057), .Y(n1211)
);
OAI22X1TS U3109 ( .A0(n148), .A1(n1052), .B0(n1514), .B1(n1051), .Y(n1067)
);
OAI22X1TS U3110 ( .A0(n2638), .A1(n1055), .B0(n1054), .B1(n1053), .Y(n1066)
);
OAI22X1TS U3111 ( .A0(n2110), .A1(n1057), .B0(n2781), .B1(n1056), .Y(n1065)
);
XNOR2X1TS U3112 ( .A(Data_A_i[9]), .B(Data_B_i[23]), .Y(n1069) );
OAI22X1TS U3113 ( .A0(n3072), .A1(n1058), .B0(n2984), .B1(n1069), .Y(n1186)
);
XNOR2X1TS U3114 ( .A(n115), .B(n1691), .Y(n1061) );
OAI22X1TS U3115 ( .A0(n1470), .A1(n1059), .B0(n108), .B1(n1061), .Y(n1185)
);
XNOR2X1TS U3116 ( .A(n3220), .B(n1813), .Y(n1064) );
OAI22X1TS U3117 ( .A0(n66), .A1(n1060), .B0(n2516), .B1(n1064), .Y(n1184) );
INVX2TS U3118 ( .A(n5755), .Y(n4085) );
XNOR2X1TS U3119 ( .A(n1468), .B(n1989), .Y(n1180) );
OAI22X1TS U3120 ( .A0(n1470), .A1(n1061), .B0(n108), .B1(n1180), .Y(n1160)
);
XNOR2X1TS U3121 ( .A(n132), .B(n1859), .Y(n1161) );
OAI22X1TS U3122 ( .A0(n5519), .A1(n1064), .B0(n2516), .B1(n1063), .Y(n1158)
);
XNOR2X1TS U3123 ( .A(n4133), .B(n2896), .Y(n1152) );
OAI22X1TS U3124 ( .A0(n4571), .A1(n1068), .B0(n3251), .B1(n1152), .Y(n1157)
);
XNOR2X1TS U3125 ( .A(Data_A_i[9]), .B(Data_B_i[24]), .Y(n1178) );
OAI22X1TS U3126 ( .A0(n3072), .A1(n1069), .B0(n2984), .B1(n1178), .Y(n1156)
);
XNOR2X1TS U3127 ( .A(n1814), .B(n3046), .Y(n1071) );
BUFX3TS U3128 ( .A(n4391), .Y(n4204) );
OAI22X1TS U3129 ( .A0(n146), .A1(n1071), .B0(n4204), .B1(n1070), .Y(n1117)
);
OAI22X1TS U3130 ( .A0(n145), .A1(n6123), .B0(n4204), .B1(n1072), .Y(n1116)
);
CMPR32X2TS U3131 ( .A(n1081), .B(n1080), .C(n1079), .CO(n1073), .S(n1264) );
NAND2X1TS U3132 ( .A(n1087), .B(n1085), .Y(n1090) );
NAND2X1TS U3133 ( .A(n1086), .B(n1085), .Y(n1089) );
NAND2X1TS U3134 ( .A(n1087), .B(n1086), .Y(n1088) );
OAI22X1TS U3135 ( .A0(n1096), .A1(n1095), .B0(n2984), .B1(n1094), .Y(n1201)
);
OAI22X1TS U3136 ( .A0(n70), .A1(n1098), .B0(n124), .B1(n1097), .Y(n1200) );
OAI22X1TS U3137 ( .A0(n2904), .A1(n1100), .B0(n63), .B1(n1099), .Y(n1199) );
CMPR32X2TS U3138 ( .A(n1103), .B(n1102), .C(n1101), .CO(n1270), .S(n1277) );
OAI22X1TS U3139 ( .A0(n41), .A1(n1106), .B0(n1105), .B1(n1104), .Y(n1198) );
XNOR2X1TS U3140 ( .A(n1165), .B(n3930), .Y(n1123) );
OAI22X1TS U3141 ( .A0(n3275), .A1(n1107), .B0(n1123), .B1(n1346), .Y(n1197)
);
XNOR2X1TS U3142 ( .A(n2511), .B(Data_B_i[27]), .Y(n1125) );
OAI22X1TS U3143 ( .A0(n2547), .A1(n1109), .B0(n1108), .B1(n1125), .Y(n1196)
);
BUFX3TS U3144 ( .A(n5293), .Y(n4702) );
OAI22X1TS U3145 ( .A0(n150), .A1(n1111), .B0(n4702), .B1(n1110), .Y(n1207)
);
OAI22X1TS U3146 ( .A0(n2638), .A1(n1113), .B0(n87), .B1(n1112), .Y(n1206) );
OAI22X1TS U3147 ( .A0(n110), .A1(n1115), .B0(n2781), .B1(n1114), .Y(n1205)
);
ADDHXLTS U3148 ( .A(n1117), .B(n1116), .CO(n1155), .S(n1189) );
XNOR2X1TS U3149 ( .A(n2897), .B(n2461), .Y(n1135) );
OAI22X1TS U3150 ( .A0(n1395), .A1(n1135), .B0(n3213), .B1(n1121), .Y(n1210)
);
OAI22X1TS U3151 ( .A0(n3275), .A1(n1123), .B0(n1122), .B1(n1346), .Y(n1209)
);
OAI22X1TS U3152 ( .A0(n2547), .A1(n1125), .B0(n1706), .B1(n1124), .Y(n1208)
);
OAI22X1TS U3153 ( .A0(n5519), .A1(n1127), .B0(n2516), .B1(n1126), .Y(n1231)
);
OAI22X1TS U3154 ( .A0(n39), .A1(n1129), .B0(n3074), .B1(n1128), .Y(n1230) );
OAI22X1TS U3155 ( .A0(n1470), .A1(n1131), .B0(n2928), .B1(n1130), .Y(n1229)
);
OAI22X1TS U3156 ( .A0(n1395), .A1(n1136), .B0(n4593), .B1(n1135), .Y(n1243)
);
OAI22X1TS U3157 ( .A0(n1140), .A1(n1139), .B0(n1138), .B1(n1137), .Y(n1242)
);
ADDHXLTS U3158 ( .A(n1142), .B(n1141), .CO(n1083), .S(n1241) );
XNOR2X1TS U3159 ( .A(n4133), .B(Data_B_i[23]), .Y(n1406) );
OAI22X1TS U3160 ( .A0(n4571), .A1(n1152), .B0(n3251), .B1(n1406), .Y(n1433)
);
XNOR2X1TS U3161 ( .A(n3349), .B(n3068), .Y(n1378) );
XNOR2X1TS U3162 ( .A(n4373), .B(n2573), .Y(n1345) );
OAI22X1TS U3163 ( .A0(n126), .A1(n1154), .B0(n64), .B1(n1345), .Y(n1431) );
XNOR2X1TS U3164 ( .A(n132), .B(n1898), .Y(n1359) );
OAI22X1TS U3165 ( .A0(n69), .A1(n1161), .B0(n1689), .B1(n1359), .Y(n1354) );
XNOR2X1TS U3166 ( .A(n6012), .B(n1399), .Y(n1368) );
OAI22X1TS U3167 ( .A0(n145), .A1(n1162), .B0(n90), .B1(n1368), .Y(n1353) );
XNOR2X1TS U3168 ( .A(Data_A_i[5]), .B(n3930), .Y(n1351) );
OAI22X1TS U3169 ( .A0(n1163), .A1(n2106), .B0(n1812), .B1(n1351), .Y(n1352)
);
XNOR2X1TS U3170 ( .A(n94), .B(Data_B_i[19]), .Y(n1380) );
OAI22X1TS U3171 ( .A0(n1395), .A1(n1164), .B0(n1393), .B1(n1380), .Y(n1371)
);
XNOR2X1TS U3172 ( .A(n1165), .B(Data_B_i[33]), .Y(n1347) );
OAI22X1TS U3173 ( .A0(n99), .A1(n1166), .B0(n1347), .B1(n1346), .Y(n1370) );
XNOR2X1TS U3174 ( .A(n35), .B(n3497), .Y(n1350) );
OAI22X1TS U3175 ( .A0(n97), .A1(n1167), .B0(n1706), .B1(n1350), .Y(n1369) );
XNOR2X1TS U3176 ( .A(n5086), .B(n2461), .Y(n1349) );
OAI22X1TS U3177 ( .A0(n5235), .A1(n1174), .B0(n1514), .B1(n1349), .Y(n1344)
);
XNOR2X1TS U3178 ( .A(n1482), .B(n1493), .Y(n1348) );
XNOR2X1TS U3179 ( .A(n1645), .B(Data_B_i[27]), .Y(n1358) );
OAI22X1TS U3180 ( .A0(n110), .A1(n1177), .B0(n1176), .B1(n1358), .Y(n1342)
);
XNOR2X1TS U3181 ( .A(Data_A_i[9]), .B(Data_B_i[25]), .Y(n1360) );
OAI22X1TS U3182 ( .A0(n3072), .A1(n1178), .B0(n2984), .B1(n1360), .Y(n1357)
);
XNOR2X1TS U3183 ( .A(n4076), .B(n1691), .Y(n1407) );
XNOR2X1TS U3184 ( .A(n115), .B(n1813), .Y(n1408) );
OAI22X1TS U3185 ( .A0(n1470), .A1(n1180), .B0(n2928), .B1(n1408), .Y(n1355)
);
CMPR32X2TS U3186 ( .A(n1183), .B(n1182), .C(n1181), .CO(n1192), .S(n1214) );
CMPR32X2TS U3187 ( .A(n1186), .B(n1185), .C(n1184), .CO(n1191), .S(n1143) );
CMPR32X2TS U3188 ( .A(n1201), .B(n1200), .C(n1199), .CO(n1239), .S(n1250) );
CMPR32X2TS U3189 ( .A(n1204), .B(n1203), .C(n1202), .CO(n1081), .S(n1238) );
CMPR32X2TS U3190 ( .A(n1213), .B(n1212), .C(n1211), .CO(n1145), .S(n1220) );
CMPR32X2TS U3191 ( .A(n1216), .B(n1215), .C(n1214), .CO(n1078), .S(n1235) );
CMPR32X2TS U3192 ( .A(n1240), .B(n1239), .C(n1238), .CO(n1237), .S(n1300) );
CMPR32X2TS U3193 ( .A(n1243), .B(n1242), .C(n1241), .CO(n1232), .S(n1285) );
INVX1TS U3194 ( .A(n1248), .Y(n1246) );
ADDFHX4TS U3195 ( .A(n1258), .B(n1257), .CI(n1256), .CO(n1632), .S(n1259) );
CMPR32X2TS U3196 ( .A(n1264), .B(n1263), .C(n1262), .CO(n1256), .S(n1322) );
CMPR32X2TS U3197 ( .A(n1279), .B(n1278), .C(n1277), .CO(n1309), .S(n1296) );
CMPR32X2TS U3198 ( .A(n1285), .B(n1284), .C(n1283), .CO(n1299), .S(n1307) );
NOR2X1TS U3199 ( .A(n1328), .B(n1326), .Y(n1319) );
INVX2TS U3200 ( .A(n1319), .Y(n7714) );
ADDFHX2TS U3201 ( .A(n1325), .B(n1324), .CI(n1323), .CO(n1332), .S(n1330) );
NAND2X2TS U3202 ( .A(n1339), .B(n7707), .Y(n1341) );
INVX2TS U3203 ( .A(n7716), .Y(n1331) );
AOI21X4TS U3204 ( .A0(n2), .A1(n7713), .B0(n1331), .Y(n7699) );
NAND2X2TS U3205 ( .A(n1335), .B(n1334), .Y(n7709) );
OAI21X2TS U3206 ( .A0(n7693), .A1(n7709), .B0(n7694), .Y(n1338) );
AOI21X4TS U3207 ( .A0(n1339), .A1(n7689), .B0(n1338), .Y(n1340) );
OAI21X4TS U3208 ( .A0(n7207), .A1(n1341), .B0(n1340), .Y(n7189) );
XNOR2X1TS U3209 ( .A(n4373), .B(n2804), .Y(n1421) );
OAI22X1TS U3210 ( .A0(n126), .A1(n1345), .B0(n63), .B1(n1421), .Y(n1417) );
INVX2TS U3211 ( .A(Data_B_i[34]), .Y(n6307) );
INVX2TS U3212 ( .A(n6307), .Y(n3878) );
XNOR2X1TS U3213 ( .A(n3042), .B(n3878), .Y(n1422) );
OAI22X1TS U3214 ( .A0(n99), .A1(n1347), .B0(n1422), .B1(n1346), .Y(n1416) );
XNOR2X1TS U3215 ( .A(n1482), .B(n1641), .Y(n1466) );
OAI22X1TS U3216 ( .A0(n131), .A1(n1348), .B0(n4746), .B1(n1466), .Y(n1415)
);
XNOR2X1TS U3217 ( .A(n5086), .B(n2353), .Y(n1464) );
OAI22X1TS U3218 ( .A0(n149), .A1(n1349), .B0(n1514), .B1(n1464), .Y(n1377)
);
XNOR2X1TS U3219 ( .A(Data_A_i[3]), .B(Data_B_i[32]), .Y(n1389) );
OAI22X1TS U3220 ( .A0(n97), .A1(n1350), .B0(n1706), .B1(n1389), .Y(n1376) );
XNOR2X1TS U3221 ( .A(n101), .B(n3738), .Y(n1465) );
OAI22X1TS U3222 ( .A0(n2106), .A1(n1351), .B0(n1812), .B1(n1465), .Y(n1375)
);
XNOR2X1TS U3223 ( .A(n1645), .B(Data_B_i[28]), .Y(n1455) );
OAI22X1TS U3224 ( .A0(n824), .A1(n1358), .B0(n2108), .B1(n1455), .Y(n1554)
);
XNOR2X1TS U3225 ( .A(n132), .B(n2284), .Y(n1387) );
OAI22X1TS U3226 ( .A0(n71), .A1(n1359), .B0(n1689), .B1(n1387), .Y(n1553) );
XNOR2X1TS U3227 ( .A(n1849), .B(n3985), .Y(n1391) );
OAI22X1TS U3228 ( .A0(n3072), .A1(n1360), .B0(n2984), .B1(n1391), .Y(n1552)
);
XNOR2X4TS U3229 ( .A(Data_A_i[34]), .B(Data_A_i[33]), .Y(n1385) );
NOR2BX1TS U3230 ( .AN(n2871), .B(n1385), .Y(n1404) );
XNOR2X1TS U3231 ( .A(n6129), .B(n1366), .Y(n1424) );
XNOR2X1TS U3232 ( .A(n5449), .B(n1400), .Y(n1388) );
OAI22X1TS U3233 ( .A0(n145), .A1(n1368), .B0(n90), .B1(n1388), .Y(n1402) );
INVX2TS U3234 ( .A(n4252), .Y(n4136) );
XNOR2X1TS U3235 ( .A(n4136), .B(Data_B_i[22]), .Y(n1382) );
OAI22X1TS U3236 ( .A0(n40), .A1(n1378), .B0(n85), .B1(n1382), .Y(n1430) );
XNOR2X1TS U3237 ( .A(n2897), .B(Data_B_i[20]), .Y(n1394) );
INVX2TS U3238 ( .A(n5584), .Y(n5418) );
XNOR2X1TS U3239 ( .A(n5418), .B(n1859), .Y(n1392) );
OAI22X1TS U3240 ( .A0(n67), .A1(n1381), .B0(n140), .B1(n1392), .Y(n1428) );
XNOR2X1TS U3241 ( .A(n4133), .B(Data_B_i[24]), .Y(n1405) );
XNOR2X1TS U3242 ( .A(n4133), .B(Data_B_i[25]), .Y(n1396) );
OAI22X1TS U3243 ( .A0(n4571), .A1(n1405), .B0(n3251), .B1(n1396), .Y(n1463)
);
XNOR2X1TS U3244 ( .A(n4136), .B(Data_B_i[23]), .Y(n1458) );
OAI22X1TS U3245 ( .A0(n43), .A1(n1382), .B0(n84), .B1(n1458), .Y(n1462) );
NAND2X4TS U3246 ( .A(n1383), .B(n1385), .Y(n5494) );
XNOR2X1TS U3247 ( .A(Data_A_i[35]), .B(n3046), .Y(n1384) );
CLKBUFX2TS U3248 ( .A(n1385), .Y(n3405) );
INVX2TS U3249 ( .A(n3772), .Y(n3048) );
XNOR2X1TS U3250 ( .A(Data_A_i[35]), .B(n3048), .Y(n1401) );
OAI22X1TS U3251 ( .A0(n4599), .A1(n1384), .B0(n3405), .B1(n1401), .Y(n1398)
);
INVX2TS U3252 ( .A(n6368), .Y(n6185) );
OAI22X1TS U3253 ( .A0(n4599), .A1(n6368), .B0(n5659), .B1(n1386), .Y(n1397)
);
XNOR2X1TS U3254 ( .A(n133), .B(n2461), .Y(n1459) );
OAI22X1TS U3255 ( .A0(n3760), .A1(n1387), .B0(n1689), .B1(n1459), .Y(n1420)
);
XNOR2X1TS U3256 ( .A(n1814), .B(n1493), .Y(n1508) );
XNOR2X1TS U3257 ( .A(n36), .B(Data_B_i[33]), .Y(n1480) );
OAI22X1TS U3258 ( .A0(n97), .A1(n1389), .B0(n1706), .B1(n1480), .Y(n1418) );
XNOR2X1TS U3259 ( .A(n1849), .B(Data_B_i[27]), .Y(n1460) );
OAI22X1TS U3260 ( .A0(n3072), .A1(n1391), .B0(n1390), .B1(n1460), .Y(n1411)
);
XNOR2X1TS U3261 ( .A(n5418), .B(n1898), .Y(n1471) );
OAI22X1TS U3262 ( .A0(n66), .A1(n1392), .B0(n5517), .B1(n1471), .Y(n1410) );
XNOR2X1TS U3263 ( .A(n4089), .B(n3068), .Y(n1477) );
OAI22X1TS U3264 ( .A0(n1395), .A1(n1394), .B0(n4593), .B1(n1477), .Y(n1409)
);
XNOR2X1TS U3265 ( .A(n1987), .B(n3985), .Y(n1518) );
OAI22X1TS U3266 ( .A0(n4571), .A1(n1396), .B0(n3251), .B1(n1518), .Y(n1531)
);
XNOR2X4TS U3267 ( .A(Data_A_i[35]), .B(Data_A_i[36]), .Y(n1536) );
NOR2BX1TS U3268 ( .AN(n3272), .B(n6391), .Y(n1534) );
XNOR2X1TS U3269 ( .A(n1860), .B(n1399), .Y(n1423) );
XNOR2X1TS U3270 ( .A(n114), .B(n1400), .Y(n1494) );
XNOR2X1TS U3271 ( .A(Data_A_i[35]), .B(n3241), .Y(n1491) );
OAI22X1TS U3272 ( .A0(n4599), .A1(n1401), .B0(n5120), .B1(n1491), .Y(n1532)
);
OAI22X1TS U3273 ( .A0(n4571), .A1(n1406), .B0(n3251), .B1(n1405), .Y(n1436)
);
XNOR2X1TS U3274 ( .A(n5101), .B(n1989), .Y(n1456) );
XNOR2X1TS U3275 ( .A(n1468), .B(n1991), .Y(n1457) );
OAI22X1TS U3276 ( .A0(n1470), .A1(n1408), .B0(n2928), .B1(n1457), .Y(n1434)
);
XNOR2X1TS U3277 ( .A(n81), .B(Data_B_i[19]), .Y(n1505) );
OAI22X1TS U3278 ( .A0(n127), .A1(n1421), .B0(n64), .B1(n1505), .Y(n1500) );
INVX2TS U3279 ( .A(Data_B_i[35]), .Y(n6346) );
INVX2TS U3280 ( .A(n6346), .Y(n4201) );
XNOR2X1TS U3281 ( .A(n3042), .B(n4201), .Y(n1478) );
CLKBUFX2TS U3282 ( .A(n1913), .Y(n2090) );
OAI22X1TS U3283 ( .A0(n99), .A1(n1422), .B0(n1478), .B1(n2090), .Y(n1499) );
OAI22X1TS U3284 ( .A0(n121), .A1(n1424), .B0(n5144), .B1(n1423), .Y(n1498)
);
CMPR32X2TS U3285 ( .A(n1445), .B(n1444), .C(n1443), .CO(n1609), .S(n1605) );
XNOR2X1TS U3286 ( .A(n1645), .B(n3930), .Y(n1467) );
OAI22X1TS U3287 ( .A0(n2967), .A1(n1455), .B0(n2108), .B1(n1467), .Y(n1551)
);
XNOR2X1TS U3288 ( .A(n5760), .B(n1813), .Y(n1473) );
OAI22X1TS U3289 ( .A0(n5103), .A1(n1456), .B0(n3074), .B1(n1473), .Y(n1550)
);
XNOR2X1TS U3290 ( .A(n5520), .B(n1856), .Y(n1469) );
OAI22X1TS U3291 ( .A0(n1470), .A1(n1457), .B0(n2928), .B1(n1469), .Y(n1549)
);
XNOR2X1TS U3292 ( .A(n4136), .B(Data_B_i[24]), .Y(n1519) );
OAI22X1TS U3293 ( .A0(n43), .A1(n1458), .B0(n85), .B1(n1519), .Y(n1513) );
XNOR2X1TS U3294 ( .A(n133), .B(n2353), .Y(n1492) );
OAI22X1TS U3295 ( .A0(n71), .A1(n1459), .B0(n1689), .B1(n1492), .Y(n1512) );
XNOR2X1TS U3296 ( .A(n1849), .B(Data_B_i[28]), .Y(n1520) );
OAI22X1TS U3297 ( .A0(n3072), .A1(n1460), .B0(n2058), .B1(n1520), .Y(n1511)
);
CMPR32X2TS U3298 ( .A(n1463), .B(n1462), .C(n1461), .CO(n1484), .S(n1570) );
XNOR2X1TS U3299 ( .A(n5086), .B(n2573), .Y(n1472) );
OAI22X1TS U3300 ( .A0(n5235), .A1(n1464), .B0(n1514), .B1(n1472), .Y(n1557)
);
XNOR2X1TS U3301 ( .A(n101), .B(n3497), .Y(n1474) );
OAI22X1TS U3302 ( .A0(n2106), .A1(n1465), .B0(n1812), .B1(n1474), .Y(n1556)
);
XNOR2X1TS U3303 ( .A(n1482), .B(n1691), .Y(n1510) );
OAI22X1TS U3304 ( .A0(n130), .A1(n1466), .B0(n4746), .B1(n1510), .Y(n1555)
);
XNOR2X1TS U3305 ( .A(n1645), .B(n3738), .Y(n1481) );
OAI22X1TS U3306 ( .A0(n824), .A1(n1467), .B0(n2108), .B1(n1481), .Y(n1489)
);
XNOR2X1TS U3307 ( .A(n116), .B(n1859), .Y(n1521) );
OAI22X1TS U3308 ( .A0(n1470), .A1(n1469), .B0(n38), .B1(n1521), .Y(n1488) );
XNOR2X1TS U3309 ( .A(n5418), .B(n2284), .Y(n1522) );
OAI22X1TS U3310 ( .A0(n5586), .A1(n1471), .B0(n5585), .B1(n1522), .Y(n1487)
);
XNOR2X1TS U3311 ( .A(n5086), .B(n2804), .Y(n1515) );
OAI22X1TS U3312 ( .A0(n150), .A1(n1472), .B0(n1514), .B1(n1515), .Y(n1528)
);
XNOR2X1TS U3313 ( .A(n98), .B(n1991), .Y(n1483) );
OAI22X1TS U3314 ( .A0(n5103), .A1(n1473), .B0(n3074), .B1(n1483), .Y(n1527)
);
XNOR2X1TS U3315 ( .A(Data_A_i[5]), .B(n76), .Y(n1475) );
OAI22X1TS U3316 ( .A0(n2106), .A1(n1474), .B0(n1812), .B1(n1475), .Y(n1526)
);
INVX2TS U3317 ( .A(n4398), .Y(n4089) );
XNOR2X1TS U3318 ( .A(n4089), .B(n2896), .Y(n1476) );
INVX2TS U3319 ( .A(Data_B_i[23]), .Y(n5605) );
INVX2TS U3320 ( .A(n5605), .Y(n4110) );
XNOR2X1TS U3321 ( .A(n2705), .B(n4110), .Y(n1657) );
OAI22X1TS U3322 ( .A0(n4006), .A1(n1476), .B0(n3213), .B1(n1657), .Y(n1719)
);
XNOR2X1TS U3323 ( .A(Data_A_i[3]), .B(n3878), .Y(n1479) );
XNOR2X1TS U3324 ( .A(Data_A_i[3]), .B(n4201), .Y(n1646) );
XNOR2X1TS U3325 ( .A(n101), .B(Data_B_i[33]), .Y(n1650) );
OAI22X1TS U3326 ( .A0(n2106), .A1(n1475), .B0(n1812), .B1(n1650), .Y(n1717)
);
OAI22X1TS U3327 ( .A0(n4006), .A1(n1477), .B0(n4593), .B1(n1476), .Y(n1503)
);
XNOR2X1TS U3328 ( .A(n3042), .B(n4335), .Y(n1490) );
OAI22X1TS U3329 ( .A0(n99), .A1(n1478), .B0(n1490), .B1(n2090), .Y(n1502) );
OAI22X1TS U3330 ( .A0(n97), .A1(n1480), .B0(n1706), .B1(n1479), .Y(n1501) );
XNOR2X1TS U3331 ( .A(n1645), .B(n3497), .Y(n1652) );
OAI22X1TS U3332 ( .A0(n824), .A1(n1481), .B0(n2108), .B1(n1652), .Y(n1636)
);
XNOR2X1TS U3333 ( .A(n1482), .B(n1989), .Y(n1509) );
INVX2TS U3334 ( .A(n6002), .Y(n4094) );
XNOR2X1TS U3335 ( .A(n4094), .B(n1813), .Y(n1686) );
OAI22X1TS U3336 ( .A0(n131), .A1(n1509), .B0(n4746), .B1(n1686), .Y(n1635)
);
XNOR2X1TS U3337 ( .A(Data_A_i[27]), .B(n1856), .Y(n1688) );
OAI22X1TS U3338 ( .A0(n39), .A1(n1483), .B0(n4573), .B1(n1688), .Y(n1634) );
CMPR32X2TS U3339 ( .A(n1489), .B(n1488), .C(n1487), .CO(n1664), .S(n1496) );
XNOR2X1TS U3340 ( .A(n81), .B(Data_B_i[20]), .Y(n1504) );
XNOR2X1TS U3341 ( .A(Data_A_i[17]), .B(n3068), .Y(n1684) );
OAI22X1TS U3342 ( .A0(n126), .A1(n1504), .B0(n44), .B1(n1684), .Y(n1731) );
XNOR2X1TS U3343 ( .A(n3042), .B(Data_B_i[37]), .Y(n1655) );
OAI22X1TS U3344 ( .A0(n2093), .A1(n1490), .B0(n1655), .B1(n2090), .Y(n1730)
);
BUFX3TS U3345 ( .A(n5494), .Y(n2280) );
XNOR2X1TS U3346 ( .A(Data_A_i[35]), .B(n4071), .Y(n1725) );
OAI22X1TS U3347 ( .A0(n2280), .A1(n1491), .B0(n3405), .B1(n1725), .Y(n1729)
);
XNOR2X1TS U3348 ( .A(n50), .B(n2573), .Y(n1656) );
OAI22X1TS U3349 ( .A0(n70), .A1(n1492), .B0(n1689), .B1(n1656), .Y(n1679) );
XNOR2X1TS U3350 ( .A(n6129), .B(n1493), .Y(n1642) );
OAI22X1TS U3351 ( .A0(n120), .A1(n1494), .B0(n5144), .B1(n1642), .Y(n1678)
);
XNOR2X1TS U3352 ( .A(n106), .B(n1641), .Y(n1507) );
XNOR2X1TS U3353 ( .A(n6012), .B(n1691), .Y(n1643) );
OAI22X1TS U3354 ( .A0(n146), .A1(n1507), .B0(n91), .B1(n1643), .Y(n1677) );
CMPR32X2TS U3355 ( .A(n1500), .B(n1499), .C(n1498), .CO(n1560), .S(n1452) );
OAI22X1TS U3356 ( .A0(n127), .A1(n1505), .B0(n44), .B1(n1504), .Y(n1541) );
OAI22X1TS U3357 ( .A0(n146), .A1(n1508), .B0(n90), .B1(n1507), .Y(n1540) );
OAI22X1TS U3358 ( .A0(n130), .A1(n1510), .B0(n4746), .B1(n1509), .Y(n1539)
);
XNOR2X1TS U3359 ( .A(n5086), .B(Data_B_i[19]), .Y(n1640) );
OAI22X1TS U3360 ( .A0(n1516), .A1(n1515), .B0(n1514), .B1(n1640), .Y(n1682)
);
XNOR2X1TS U3361 ( .A(n1987), .B(n3073), .Y(n1648) );
XNOR2X1TS U3362 ( .A(n4136), .B(Data_B_i[25]), .Y(n1637) );
OAI22X1TS U3363 ( .A0(n40), .A1(n1519), .B0(n85), .B1(n1637), .Y(n1680) );
XNOR2X1TS U3364 ( .A(n1849), .B(n3930), .Y(n1649) );
OAI22X1TS U3365 ( .A0(n1964), .A1(n1520), .B0(n2058), .B1(n1649), .Y(n1670)
);
XNOR2X1TS U3366 ( .A(n116), .B(n1898), .Y(n1638) );
OAI22X1TS U3367 ( .A0(n55), .A1(n1521), .B0(n37), .B1(n1638), .Y(n1669) );
XNOR2X1TS U3368 ( .A(n5418), .B(n2461), .Y(n1639) );
OAI22X1TS U3369 ( .A0(n4258), .A1(n1522), .B0(n141), .B1(n1639), .Y(n1668)
);
CMPR32X2TS U3370 ( .A(n1528), .B(n1527), .C(n1526), .CO(n1716), .S(n1495) );
INVX2TS U3371 ( .A(n6390), .Y(n2466) );
XNOR2X1TS U3372 ( .A(n2466), .B(n2037), .Y(n1537) );
XNOR2X1TS U3373 ( .A(n2466), .B(n3048), .Y(n1728) );
OAI22X1TS U3374 ( .A0(n6381), .A1(n1537), .B0(n136), .B1(n1728), .Y(n1654)
);
OAI22X1TS U3375 ( .A0(n5217), .A1(n6390), .B0(n137), .B1(n1538), .Y(n1653)
);
CMPR32X2TS U3376 ( .A(n1557), .B(n1556), .C(n1555), .CO(n1497), .S(n1567) );
CMPR32X2TS U3377 ( .A(n1572), .B(n1571), .C(n1570), .CO(n1525), .S(n1580) );
XOR2X4TS U3378 ( .A(n1576), .B(n1787), .Y(n1799) );
CMPR32X2TS U3379 ( .A(n1591), .B(n1590), .C(n1589), .CO(n1592), .S(n1619) );
CMPR32X2TS U3380 ( .A(n1594), .B(n1593), .C(n1592), .CO(n1597), .S(n1613) );
ADDFHX2TS U3381 ( .A(n1597), .B(n1596), .CI(n1595), .CO(n1788), .S(n1598) );
NOR2X2TS U3382 ( .A(n1798), .B(n1797), .Y(n7190) );
ADDFHX2TS U3383 ( .A(n1618), .B(n1617), .CI(n1616), .CO(n1797), .S(n1796) );
ADDFHX4TS U3384 ( .A(n1633), .B(n1632), .CI(n1631), .CO(n1793), .S(n1337) );
NAND2X2TS U3385 ( .A(n1802), .B(n7199), .Y(n7365) );
CMPR32X2TS U3386 ( .A(n1636), .B(n1635), .C(n1634), .CO(n1752), .S(n1665) );
XNOR2X1TS U3387 ( .A(n1896), .B(n3985), .Y(n1644) );
OAI22X1TS U3388 ( .A0(n2464), .A1(n1637), .B0(n85), .B1(n1644), .Y(n1701) );
XNOR2X1TS U3389 ( .A(n4085), .B(n2284), .Y(n1661) );
OAI22X1TS U3390 ( .A0(n56), .A1(n1638), .B0(n37), .B1(n1661), .Y(n1700) );
XNOR2X1TS U3391 ( .A(n5418), .B(n2353), .Y(n1705) );
OAI22X1TS U3392 ( .A0(n5519), .A1(n1639), .B0(n3425), .B1(n1705), .Y(n1699)
);
XNOR2X1TS U3393 ( .A(n5086), .B(Data_B_i[20]), .Y(n1695) );
OAI22X1TS U3394 ( .A0(n5235), .A1(n1640), .B0(n3503), .B1(n1695), .Y(n1698)
);
XNOR2X1TS U3395 ( .A(n6129), .B(n1641), .Y(n1692) );
OAI22X1TS U3396 ( .A0(n121), .A1(n1642), .B0(n6182), .B1(n1692), .Y(n1697)
);
INVX2TS U3397 ( .A(n6123), .Y(n3986) );
XNOR2X1TS U3398 ( .A(Data_A_i[31]), .B(n1989), .Y(n1693) );
OAI22X1TS U3399 ( .A0(n146), .A1(n1643), .B0(n90), .B1(n1693), .Y(n1696) );
XNOR2X1TS U3400 ( .A(n1987), .B(n3704), .Y(n1647) );
XNOR2X1TS U3401 ( .A(n1987), .B(n3930), .Y(n2067) );
OAI22X1TS U3402 ( .A0(n3525), .A1(n1647), .B0(n2507), .B1(n2067), .Y(n2178)
);
XNOR2X1TS U3403 ( .A(n1922), .B(n76), .Y(n1651) );
XNOR2X1TS U3404 ( .A(n1645), .B(Data_B_i[33]), .Y(n2109) );
OAI22X1TS U3405 ( .A0(n2967), .A1(n1651), .B0(n2108), .B1(n2109), .Y(n2176)
);
XNOR2X1TS U3406 ( .A(Data_A_i[3]), .B(n4335), .Y(n1707) );
OAI22X1TS U3407 ( .A0(n96), .A1(n1646), .B0(n3990), .B1(n1707), .Y(n1734) );
OAI22X1TS U3408 ( .A0(n4571), .A1(n1648), .B0(n2507), .B1(n1647), .Y(n1733)
);
XNOR2X1TS U3409 ( .A(n1849), .B(n3738), .Y(n1753) );
OAI22X1TS U3410 ( .A0(n1964), .A1(n1649), .B0(n2058), .B1(n1753), .Y(n1732)
);
XNOR2X1TS U3411 ( .A(n101), .B(n3878), .Y(n1658) );
OAI22X1TS U3412 ( .A0(n2106), .A1(n1650), .B0(n1812), .B1(n1658), .Y(n1676)
);
OAI22X1TS U3413 ( .A0(n735), .A1(n1652), .B0(n2108), .B1(n1651), .Y(n1675)
);
ADDHXLTS U3414 ( .A(n1654), .B(n1653), .CO(n1674), .S(n1723) );
INVX2TS U3415 ( .A(Data_B_i[38]), .Y(n6465) );
INVX2TS U3416 ( .A(n6465), .Y(n4469) );
XNOR2X1TS U3417 ( .A(n3042), .B(n4469), .Y(n1694) );
OAI22X1TS U3418 ( .A0(n2093), .A1(n1655), .B0(n1694), .B1(n2090), .Y(n1673)
);
XNOR2X1TS U3419 ( .A(Data_A_i[21]), .B(n2804), .Y(n1690) );
OAI22X1TS U3420 ( .A0(n3760), .A1(n1656), .B0(n1689), .B1(n1690), .Y(n1672)
);
XNOR2X1TS U3421 ( .A(n94), .B(n4032), .Y(n1659) );
OAI22X1TS U3422 ( .A0(n4006), .A1(n1657), .B0(n4091), .B1(n1659), .Y(n1671)
);
XNOR2X1TS U3423 ( .A(n101), .B(n4201), .Y(n2105) );
OAI22X1TS U3424 ( .A0(n2106), .A1(n1658), .B0(n1812), .B1(n2105), .Y(n2163)
);
BUFX3TS U3425 ( .A(n4479), .Y(n3723) );
XNOR2X1TS U3426 ( .A(n81), .B(n2896), .Y(n1683) );
XNOR2X1TS U3427 ( .A(n81), .B(n4110), .Y(n2135) );
OAI22X1TS U3428 ( .A0(n3723), .A1(n1683), .B0(n45), .B1(n2135), .Y(n2162) );
INVX2TS U3429 ( .A(Data_B_i[25]), .Y(n5720) );
INVX2TS U3430 ( .A(n5720), .Y(n4066) );
XNOR2X1TS U3431 ( .A(n2705), .B(n4066), .Y(n2069) );
OAI22X1TS U3432 ( .A0(n4006), .A1(n1659), .B0(n3213), .B1(n2069), .Y(n2161)
);
XNOR2X1TS U3433 ( .A(n4094), .B(n1991), .Y(n1685) );
XNOR2X1TS U3434 ( .A(n4094), .B(n1856), .Y(n2139) );
OAI22X1TS U3435 ( .A0(n6003), .A1(n1685), .B0(n4096), .B1(n2139), .Y(n2187)
);
XNOR2X1TS U3436 ( .A(n4076), .B(n1859), .Y(n1687) );
XNOR2X1TS U3437 ( .A(n5101), .B(n1898), .Y(n1966) );
OAI22X1TS U3438 ( .A0(n4575), .A1(n1687), .B0(n135), .B1(n1966), .Y(n2186)
);
XNOR2X1TS U3439 ( .A(n4085), .B(n2461), .Y(n1968) );
OAI22X1TS U3440 ( .A0(n2056), .A1(n1661), .B0(n37), .B1(n1968), .Y(n2185) );
CMPR32X2TS U3441 ( .A(n1664), .B(n1663), .C(n1662), .CO(n1774), .S(n1735) );
CMPR32X2TS U3442 ( .A(n1670), .B(n1669), .C(n1668), .CO(n1765), .S(n1747) );
CMPR32X2TS U3443 ( .A(n1676), .B(n1675), .C(n1674), .CO(n2227), .S(n1763) );
OAI22X1TS U3444 ( .A0(n3723), .A1(n1684), .B0(n44), .B1(n1683), .Y(n1704) );
OAI22X1TS U3445 ( .A0(n2521), .A1(n1686), .B0(n4746), .B1(n1685), .Y(n1703)
);
OAI22X1TS U3446 ( .A0(n5798), .A1(n1688), .B0(n134), .B1(n1687), .Y(n1702)
);
XNOR2X1TS U3447 ( .A(n132), .B(Data_B_i[19]), .Y(n2089) );
OAI22X1TS U3448 ( .A0(n3760), .A1(n1690), .B0(n1689), .B1(n2089), .Y(n2160)
);
XNOR2X1TS U3449 ( .A(n114), .B(n1691), .Y(n2075) );
OAI22X1TS U3450 ( .A0(n4337), .A1(n1692), .B0(n6182), .B1(n2075), .Y(n2159)
);
XNOR2X1TS U3451 ( .A(n1814), .B(n1813), .Y(n2137) );
OAI22X1TS U3452 ( .A0(n147), .A1(n1693), .B0(n90), .B1(n2137), .Y(n2158) );
XNOR2X1TS U3453 ( .A(n2466), .B(n3241), .Y(n1727) );
XNOR2X1TS U3454 ( .A(n2466), .B(n4071), .Y(n1970) );
OAI22X1TS U3455 ( .A0(n4635), .A1(n1727), .B0(n136), .B1(n1970), .Y(n2121)
);
INVX2TS U3456 ( .A(Data_B_i[39]), .Y(n6509) );
INVX2TS U3457 ( .A(n6509), .Y(n5143) );
XNOR2X1TS U3458 ( .A(Data_A_i[1]), .B(n5143), .Y(n2092) );
OAI22X1TS U3459 ( .A0(n2093), .A1(n1694), .B0(n2092), .B1(n2090), .Y(n2120)
);
XNOR2X1TS U3460 ( .A(n5086), .B(n3068), .Y(n2073) );
OAI22X1TS U3461 ( .A0(n5235), .A1(n1695), .B0(n3503), .B1(n2073), .Y(n2119)
);
CMPR32X2TS U3462 ( .A(n1698), .B(n1697), .C(n1696), .CO(n2254), .S(n1750) );
XNOR2X1TS U3463 ( .A(n5418), .B(n2573), .Y(n2103) );
OAI22X1TS U3464 ( .A0(n5586), .A1(n1705), .B0(n5585), .B1(n2103), .Y(n2196)
);
XNOR2X1TS U3465 ( .A(n36), .B(n77), .Y(n2077) );
OAI22X1TS U3466 ( .A0(n97), .A1(n1707), .B0(n1706), .B1(n2077), .Y(n2195) );
XNOR2X1TS U3467 ( .A(Data_A_i[35]), .B(n3988), .Y(n1724) );
XNOR2X1TS U3468 ( .A(n5185), .B(n4068), .Y(n2095) );
OAI22X1TS U3469 ( .A0(n2280), .A1(n1724), .B0(n3405), .B1(n2095), .Y(n2194)
);
ADDFHX4TS U3470 ( .A(n1713), .B(n1712), .CI(n1711), .CO(n1779), .S(n1789) );
OAI2BB1X1TS U3471 ( .A0N(n1723), .A1N(n1722), .B0(n1721), .Y(n1742) );
XNOR2X4TS U3472 ( .A(Data_A_i[38]), .B(Data_A_i[37]), .Y(n3346) );
NOR2BX1TS U3473 ( .AN(n1726), .B(n3346), .Y(n1758) );
OAI22X1TS U3474 ( .A0(n74), .A1(n1728), .B0(n136), .B1(n1727), .Y(n1757) );
CMPR32X2TS U3475 ( .A(n1752), .B(n1751), .C(n1750), .CO(n2382), .S(n1769) );
XNOR2X1TS U3476 ( .A(n1849), .B(n3497), .Y(n1963) );
OAI22X1TS U3477 ( .A0(n1964), .A1(n1753), .B0(n2058), .B1(n1963), .Y(n2166)
);
XNOR2X1TS U3478 ( .A(n5082), .B(n2037), .Y(n1755) );
XNOR2X1TS U3479 ( .A(n119), .B(n3048), .Y(n1972) );
OAI22X1TS U3480 ( .A0(n6542), .A1(n1755), .B0(n139), .B1(n1972), .Y(n2115)
);
BUFX3TS U3481 ( .A(n3346), .Y(n6466) );
OAI22X1TS U3482 ( .A0(n5942), .A1(n6540), .B0(n5432), .B1(n1756), .Y(n2114)
);
CMPR32X2TS U3483 ( .A(n1762), .B(n1761), .C(n1760), .CO(n2372), .S(n1741) );
OR2X4TS U3484 ( .A(n1806), .B(n1805), .Y(n7373) );
NAND2X1TS U3485 ( .A(n1789), .B(n1787), .Y(n1792) );
NAND2X1TS U3486 ( .A(n1789), .B(n1788), .Y(n1790) );
OR2X4TS U3487 ( .A(n1804), .B(n1803), .Y(n7368) );
NAND2X2TS U3488 ( .A(n7373), .B(n7368), .Y(n1809) );
NOR2X2TS U3489 ( .A(n7365), .B(n1809), .Y(n1811) );
NAND2X2TS U3490 ( .A(n1794), .B(n1793), .Y(n7685) );
NAND2X2TS U3491 ( .A(n1798), .B(n1797), .Y(n7203) );
OAI21X2TS U3492 ( .A0(n7203), .A1(n7194), .B0(n7195), .Y(n1801) );
AND2X4TS U3493 ( .A(n1804), .B(n1803), .Y(n7367) );
NAND2X1TS U3494 ( .A(n1806), .B(n1805), .Y(n7372) );
INVX2TS U3495 ( .A(n7372), .Y(n1807) );
AOI21X4TS U3496 ( .A0(n7189), .A1(n1811), .B0(n1810), .Y(n7358) );
XNOR2X1TS U3497 ( .A(n4388), .B(n2353), .Y(n1967) );
XNOR2X1TS U3498 ( .A(n4388), .B(n2573), .Y(n1927) );
OAI22X1TS U3499 ( .A0(n2056), .A1(n1967), .B0(n37), .B1(n1927), .Y(n2065) );
XNOR2X1TS U3500 ( .A(n101), .B(n4335), .Y(n2104) );
XNOR2X1TS U3501 ( .A(n100), .B(Data_B_i[37]), .Y(n1817) );
OAI22X1TS U3502 ( .A0(n142), .A1(n2104), .B0(n1812), .B1(n1817), .Y(n2064)
);
INVX2TS U3503 ( .A(n3399), .Y(n4035) );
XNOR2X1TS U3504 ( .A(n5185), .B(n4035), .Y(n2094) );
INVX2TS U3505 ( .A(n3400), .Y(n4099) );
XNOR2X1TS U3506 ( .A(Data_A_i[35]), .B(n4099), .Y(n1948) );
OAI22X1TS U3507 ( .A0(n2280), .A1(n2094), .B0(n3405), .B1(n1948), .Y(n2063)
);
XNOR2X1TS U3508 ( .A(n5418), .B(Data_B_i[19]), .Y(n1952) );
INVX2TS U3509 ( .A(n5584), .Y(n4256) );
XNOR2X1TS U3510 ( .A(n4256), .B(Data_B_i[20]), .Y(n1826) );
OAI22X1TS U3511 ( .A0(n4084), .A1(n1952), .B0(n141), .B1(n1826), .Y(n1821)
);
XNOR2X1TS U3512 ( .A(n1860), .B(n1813), .Y(n1990) );
INVX2TS U3513 ( .A(n6250), .Y(n3741) );
XNOR2X1TS U3514 ( .A(n6129), .B(n1991), .Y(n1857) );
XNOR2X1TS U3515 ( .A(n1814), .B(n1856), .Y(n1992) );
XNOR2X1TS U3516 ( .A(n6012), .B(n1859), .Y(n1835) );
OAI22X1TS U3517 ( .A0(n147), .A1(n1992), .B0(n4204), .B1(n1835), .Y(n1819)
);
XNOR2X1TS U3518 ( .A(n1896), .B(Data_B_i[28]), .Y(n2070) );
XNOR2X1TS U3519 ( .A(n1896), .B(n3930), .Y(n1848) );
OAI22X1TS U3520 ( .A0(n2525), .A1(n2070), .B0(n2462), .B1(n1848), .Y(n1975)
);
INVX2TS U3521 ( .A(n6002), .Y(n5908) );
XNOR2X1TS U3522 ( .A(n5908), .B(n1859), .Y(n2138) );
XNOR2X1TS U3523 ( .A(n5908), .B(n1898), .Y(n1815) );
OAI22X1TS U3524 ( .A0(n2521), .A1(n2138), .B0(n2494), .B1(n1815), .Y(n1974)
);
XNOR2X1TS U3525 ( .A(n98), .B(n2284), .Y(n1965) );
XNOR2X1TS U3526 ( .A(n98), .B(n2461), .Y(n1818) );
OAI22X1TS U3527 ( .A0(n5103), .A1(n1965), .B0(n135), .B1(n1818), .Y(n1973)
);
XNOR2X1TS U3528 ( .A(n5908), .B(n2284), .Y(n1837) );
OAI22X1TS U3529 ( .A0(n131), .A1(n1815), .B0(n2494), .B1(n1837), .Y(n1931)
);
XNOR2X1TS U3530 ( .A(n100), .B(n4469), .Y(n1827) );
OAI22X1TS U3531 ( .A0(n142), .A1(n1817), .B0(n88), .B1(n1827), .Y(n1930) );
XNOR2X1TS U3532 ( .A(Data_A_i[27]), .B(n2353), .Y(n1836) );
OAI22X1TS U3533 ( .A0(n5798), .A1(n1818), .B0(n134), .B1(n1836), .Y(n1929)
);
XNOR2X1TS U3534 ( .A(n115), .B(n2804), .Y(n1926) );
XNOR2X1TS U3535 ( .A(n1468), .B(Data_B_i[19]), .Y(n1875) );
OAI22X1TS U3536 ( .A0(n2056), .A1(n1926), .B0(n38), .B1(n1875), .Y(n1840) );
XNOR2X1TS U3537 ( .A(n6336), .B(n4068), .Y(n1842) );
OAI22X1TS U3538 ( .A0(n5817), .A1(n1958), .B0(n6541), .B1(n1842), .Y(n1839)
);
INVX2TS U3539 ( .A(Data_B_i[40]), .Y(n6518) );
INVX2TS U3540 ( .A(n6518), .Y(n5180) );
XNOR2X1TS U3541 ( .A(n36), .B(n5180), .Y(n1822) );
INVX2TS U3542 ( .A(Data_B_i[41]), .Y(n6569) );
INVX2TS U3543 ( .A(n6569), .Y(n5278) );
XNOR2X1TS U3544 ( .A(n36), .B(n5278), .Y(n1846) );
OAI22X1TS U3545 ( .A0(n2078), .A1(n1822), .B0(n3990), .B1(n1846), .Y(n1838)
);
XNOR2X1TS U3546 ( .A(Data_A_i[19]), .B(n4110), .Y(n1941) );
XNOR2X1TS U3547 ( .A(n4087), .B(n4032), .Y(n1851) );
XNOR2X1TS U3548 ( .A(n1942), .B(n5278), .Y(n1943) );
INVX2TS U3549 ( .A(Data_B_i[42]), .Y(n6615) );
INVX2TS U3550 ( .A(n6615), .Y(n5383) );
OAI22X1TS U3551 ( .A0(n2093), .A1(n1943), .B0(n1823), .B1(n2090), .Y(n1950)
);
XNOR2X1TS U3552 ( .A(n36), .B(n5143), .Y(n1954) );
OAI22X1TS U3553 ( .A0(n2078), .A1(n1954), .B0(n3990), .B1(n1822), .Y(n1949)
);
XNOR2X1TS U3554 ( .A(n3040), .B(n2896), .Y(n1944) );
XNOR2X1TS U3555 ( .A(n50), .B(n4110), .Y(n1844) );
OAI22X1TS U3556 ( .A0(n3618), .A1(n1944), .B0(n125), .B1(n1844), .Y(n1871)
);
OAI22X1TS U3557 ( .A0(n2544), .A1(n1823), .B0(n1845), .B1(n2090), .Y(n1870)
);
XOR2X1TS U3558 ( .A(Data_A_i[41]), .B(Data_A_i[40]), .Y(n1824) );
XNOR2X4TS U3559 ( .A(Data_A_i[40]), .B(Data_A_i[39]), .Y(n1825) );
NAND2X4TS U3560 ( .A(n1824), .B(n6589), .Y(n3365) );
XNOR2X1TS U3561 ( .A(Data_A_i[41]), .B(n3241), .Y(n1960) );
BUFX3TS U3562 ( .A(n6589), .Y(n4230) );
XNOR2X1TS U3563 ( .A(n82), .B(n4071), .Y(n2013) );
OAI22X1TS U3564 ( .A0(n6525), .A1(n1960), .B0(n4230), .B1(n2013), .Y(n1869)
);
XNOR2X1TS U3565 ( .A(n5418), .B(n3068), .Y(n1886) );
OAI22X1TS U3566 ( .A0(n5586), .A1(n1826), .B0(n3425), .B1(n1886), .Y(n1834)
);
XNOR2X1TS U3567 ( .A(n4097), .B(n5143), .Y(n1843) );
OAI22X1TS U3568 ( .A0(n143), .A1(n1827), .B0(n87), .B1(n1843), .Y(n1833) );
XNOR2X1TS U3569 ( .A(n1922), .B(n4335), .Y(n1924) );
XNOR2X1TS U3570 ( .A(Data_B_i[37]), .B(n1922), .Y(n1873) );
OAI22X1TS U3571 ( .A0(n2110), .A1(n1924), .B0(n2108), .B1(n1873), .Y(n1832)
);
XNOR2X1TS U3572 ( .A(n1896), .B(n3738), .Y(n1847) );
XNOR2X1TS U3573 ( .A(n1896), .B(n3497), .Y(n1884) );
OAI22X1TS U3574 ( .A0(n40), .A1(n1847), .B0(n2462), .B1(n1884), .Y(n1855) );
XNOR2X1TS U3575 ( .A(n5449), .B(n1898), .Y(n1862) );
OAI22X1TS U3576 ( .A0(n6125), .A1(n1835), .B0(n90), .B1(n1862), .Y(n1854) );
XNOR2X1TS U3577 ( .A(n1660), .B(n2573), .Y(n1841) );
OAI22X1TS U3578 ( .A0(n5798), .A1(n1836), .B0(n135), .B1(n1841), .Y(n1853)
);
XNOR2X1TS U3579 ( .A(n5908), .B(n2461), .Y(n1885) );
OAI22X1TS U3580 ( .A0(n5945), .A1(n1837), .B0(n2494), .B1(n1885), .Y(n1940)
);
XNOR2X1TS U3581 ( .A(n2466), .B(n4035), .Y(n1946) );
XNOR2X1TS U3582 ( .A(n2466), .B(n4099), .Y(n1876) );
OAI22X1TS U3583 ( .A0(n6381), .A1(n1946), .B0(n137), .B1(n1876), .Y(n1939)
);
XNOR2X1TS U3584 ( .A(n2343), .B(n3878), .Y(n1850) );
XNOR2X1TS U3585 ( .A(n2343), .B(n4201), .Y(n1874) );
OAI22X1TS U3586 ( .A0(n1964), .A1(n1850), .B0(n2058), .B1(n1874), .Y(n1938)
);
CMPR32X2TS U3587 ( .A(n1840), .B(n1839), .C(n1838), .CO(n1883), .S(n2009) );
XNOR2X1TS U3588 ( .A(n98), .B(n2804), .Y(n1917) );
OAI22X1TS U3589 ( .A0(n39), .A1(n1841), .B0(n134), .B1(n1917), .Y(n2030) );
XNOR2X1TS U3590 ( .A(n6336), .B(n4035), .Y(n2057) );
XNOR2X1TS U3591 ( .A(n2552), .B(n5180), .Y(n1918) );
OAI22X1TS U3592 ( .A0(n144), .A1(n1843), .B0(n87), .B1(n1918), .Y(n2028) );
XNOR2X1TS U3593 ( .A(n50), .B(n4032), .Y(n1915) );
OAI22X1TS U3594 ( .A0(n3618), .A1(n1844), .B0(n125), .B1(n1915), .Y(n2033)
);
INVX2TS U3595 ( .A(Data_B_i[44]), .Y(n6682) );
INVX2TS U3596 ( .A(n6682), .Y(n5525) );
XNOR2X1TS U3597 ( .A(n1942), .B(n5525), .Y(n1914) );
OAI22X1TS U3598 ( .A0(n2544), .A1(n1845), .B0(n1914), .B1(n2090), .Y(n2032)
);
XNOR2X1TS U3599 ( .A(n35), .B(n5383), .Y(n1916) );
OAI22X1TS U3600 ( .A0(n4614), .A1(n1846), .B0(n2281), .B1(n1916), .Y(n2031)
);
OAI22X1TS U3601 ( .A0(n2525), .A1(n1848), .B0(n2462), .B1(n1847), .Y(n1995)
);
XNOR2X1TS U3602 ( .A(n2897), .B(n3073), .Y(n1996) );
XNOR2X1TS U3603 ( .A(n4089), .B(n3704), .Y(n1852) );
OAI22X1TS U3604 ( .A0(n4006), .A1(n1996), .B0(n1393), .B1(n1852), .Y(n1994)
);
XNOR2X1TS U3605 ( .A(n1849), .B(Data_B_i[33]), .Y(n1923) );
OAI22X1TS U3606 ( .A0(n1964), .A1(n1923), .B0(n2058), .B1(n1850), .Y(n1993)
);
XNOR2X1TS U3607 ( .A(Data_A_i[19]), .B(n4066), .Y(n1872) );
OAI22X1TS U3608 ( .A0(n4704), .A1(n1851), .B0(n3503), .B1(n1872), .Y(n2018)
);
INVX2TS U3609 ( .A(n5799), .Y(n4338) );
XNOR2X1TS U3610 ( .A(n2347), .B(n4338), .Y(n1928) );
XNOR2X1TS U3611 ( .A(n2347), .B(n3073), .Y(n1863) );
OAI22X1TS U3612 ( .A0(n4479), .A1(n1928), .B0(n61), .B1(n1863), .Y(n2017) );
INVX2TS U3613 ( .A(n5939), .Y(n5890) );
XNOR2X1TS U3614 ( .A(n4247), .B(n5890), .Y(n1864) );
OAI22X1TS U3615 ( .A0(n103), .A1(n1852), .B0(n4593), .B1(n1864), .Y(n2016)
);
XNOR2X1TS U3616 ( .A(n1987), .B(n76), .Y(n1955) );
XNOR2X1TS U3617 ( .A(n2503), .B(Data_B_i[33]), .Y(n1858) );
OAI22X1TS U3618 ( .A0(n3525), .A1(n1955), .B0(n2507), .B1(n1858), .Y(n1937)
);
INVX2TS U3619 ( .A(n3393), .Y(n4000) );
XNOR2X1TS U3620 ( .A(Data_A_i[35]), .B(n4000), .Y(n1947) );
INVX2TS U3621 ( .A(n6368), .Y(n3873) );
INVX2TS U3622 ( .A(n3394), .Y(n4080) );
XNOR2X1TS U3623 ( .A(n3873), .B(n4080), .Y(n1877) );
OAI22X1TS U3624 ( .A0(n2280), .A1(n1947), .B0(n3405), .B1(n1877), .Y(n1936)
);
BUFX3TS U3625 ( .A(n2935), .Y(n4420) );
XNOR2X1TS U3626 ( .A(n6066), .B(n1856), .Y(n1861) );
OAI22X1TS U3627 ( .A0(n120), .A1(n1857), .B0(n2935), .B1(n1861), .Y(n1935)
);
XNOR2X1TS U3628 ( .A(n2503), .B(n3878), .Y(n1901) );
OAI22X1TS U3629 ( .A0(n2502), .A1(n1858), .B0(n2507), .B1(n1901), .Y(n1895)
);
XNOR2X1TS U3630 ( .A(n6066), .B(n1859), .Y(n1899) );
OAI22X1TS U3631 ( .A0(n5621), .A1(n1861), .B0(n58), .B1(n1899), .Y(n1894) );
XNOR2X1TS U3632 ( .A(n5449), .B(n2284), .Y(n1900) );
OAI22X1TS U3633 ( .A0(n6125), .A1(n1862), .B0(n91), .B1(n1900), .Y(n1893) );
XNOR2X1TS U3634 ( .A(n2347), .B(n3704), .Y(n1888) );
OAI22X1TS U3635 ( .A0(n3723), .A1(n1863), .B0(n45), .B1(n1888), .Y(n1892) );
INVX2TS U3636 ( .A(n6061), .Y(n5844) );
XNOR2X1TS U3637 ( .A(n94), .B(n5844), .Y(n1887) );
OAI22X1TS U3638 ( .A0(n103), .A1(n1864), .B0(n4091), .B1(n1887), .Y(n1891)
);
XOR2X1TS U3639 ( .A(Data_A_i[42]), .B(Data_A_i[43]), .Y(n1865) );
XNOR2X4TS U3640 ( .A(Data_A_i[41]), .B(Data_A_i[42]), .Y(n1866) );
BUFX6TS U3641 ( .A(n1866), .Y(n6659) );
NAND2X4TS U3642 ( .A(n1865), .B(n6659), .Y(n5757) );
INVX2TS U3643 ( .A(n6658), .Y(n3249) );
XNOR2X1TS U3644 ( .A(n3249), .B(n2037), .Y(n1867) );
BUFX3TS U3645 ( .A(n1866), .Y(n6258) );
BUFX3TS U3646 ( .A(n6258), .Y(n4400) );
XNOR2X1TS U3647 ( .A(n3249), .B(n3048), .Y(n2015) );
OAI22X1TS U3648 ( .A0(n4009), .A1(n1867), .B0(n4400), .B1(n2015), .Y(n1983)
);
INVX2TS U3649 ( .A(n6658), .Y(n6520) );
OAI22X1TS U3650 ( .A0(n4009), .A1(n6658), .B0(n4566), .B1(n1868), .Y(n1982)
);
XNOR2X1TS U3651 ( .A(n2859), .B(n4338), .Y(n2035) );
OAI22X1TS U3652 ( .A0(n148), .A1(n1872), .B0(n3503), .B1(n2035), .Y(n2054)
);
XNOR2X1TS U3653 ( .A(n1922), .B(n4469), .Y(n2061) );
OAI22X1TS U3654 ( .A0(n4716), .A1(n1873), .B0(n177), .B1(n2061), .Y(n2053)
);
XNOR2X1TS U3655 ( .A(n2343), .B(n4335), .Y(n2059) );
OAI22X1TS U3656 ( .A0(n1964), .A1(n1874), .B0(n3361), .B1(n2059), .Y(n2052)
);
XNOR2X1TS U3657 ( .A(n1468), .B(Data_B_i[20]), .Y(n2055) );
OAI22X1TS U3658 ( .A0(n2056), .A1(n1875), .B0(n108), .B1(n2055), .Y(n1912)
);
INVX2TS U3659 ( .A(n6390), .Y(n4394) );
XNOR2X1TS U3660 ( .A(n4394), .B(n4000), .Y(n1902) );
INVX2TS U3661 ( .A(n3522), .Y(n4043) );
XNOR2X1TS U3662 ( .A(n3873), .B(n4043), .Y(n1903) );
OAI22X1TS U3663 ( .A0(n2280), .A1(n1877), .B0(n3405), .B1(n1903), .Y(n1910)
);
XNOR2X1TS U3664 ( .A(n2789), .B(Data_B_i[32]), .Y(n1897) );
OAI22X1TS U3665 ( .A0(n4684), .A1(n1884), .B0(n2462), .B1(n1897), .Y(n2021)
);
XNOR2X1TS U3666 ( .A(n5908), .B(n2353), .Y(n2060) );
OAI22X1TS U3667 ( .A0(n5945), .A1(n1885), .B0(n2494), .B1(n2060), .Y(n2020)
);
XNOR2X1TS U3668 ( .A(n4256), .B(n2896), .Y(n1889) );
OAI22X1TS U3669 ( .A0(n66), .A1(n1886), .B0(n141), .B1(n1889), .Y(n2019) );
INVX2TS U3670 ( .A(n6145), .Y(n5911) );
XNOR2X1TS U3671 ( .A(n2897), .B(n5911), .Y(n2342) );
OAI22X1TS U3672 ( .A0(n103), .A1(n1887), .B0(n1379), .B1(n2342), .Y(n2339)
);
XNOR2X1TS U3673 ( .A(n2347), .B(n5890), .Y(n2348) );
XNOR2X1TS U3674 ( .A(n4256), .B(n4110), .Y(n2356) );
OAI22X1TS U3675 ( .A0(n67), .A1(n1889), .B0(n140), .B1(n2356), .Y(n2337) );
CMPR32X2TS U3676 ( .A(n1892), .B(n1891), .C(n1890), .CO(n2269), .S(n2049) );
XNOR2X1TS U3677 ( .A(n1896), .B(Data_B_i[33]), .Y(n2340) );
OAI22X1TS U3678 ( .A0(n43), .A1(n1897), .B0(n2462), .B1(n2340), .Y(n2324) );
BUFX3TS U3679 ( .A(n4422), .Y(n4337) );
INVX2TS U3680 ( .A(n6250), .Y(n6129) );
XNOR2X1TS U3681 ( .A(n6129), .B(n1898), .Y(n2285) );
XNOR2X1TS U3682 ( .A(Data_A_i[31]), .B(n2461), .Y(n2354) );
OAI22X1TS U3683 ( .A0(n147), .A1(n1900), .B0(n90), .B1(n2354), .Y(n2322) );
XNOR2X1TS U3684 ( .A(n2503), .B(n4201), .Y(n2341) );
OAI22X1TS U3685 ( .A0(n3525), .A1(n1901), .B0(n2507), .B1(n2341), .Y(n2351)
);
XNOR2X1TS U3686 ( .A(n2466), .B(n4080), .Y(n2329) );
OAI22X1TS U3687 ( .A0(n73), .A1(n1902), .B0(n137), .B1(n2329), .Y(n2350) );
INVX2TS U3688 ( .A(n3589), .Y(n4112) );
XNOR2X1TS U3689 ( .A(n3873), .B(n4112), .Y(n2279) );
OAI22X1TS U3690 ( .A0(n2280), .A1(n1903), .B0(n6308), .B1(n2279), .Y(n2349)
);
CMPR32X2TS U3691 ( .A(n1912), .B(n1911), .C(n1910), .CO(n2321), .S(n1904) );
INVX2TS U3692 ( .A(Data_B_i[45]), .Y(n6711) );
INVX2TS U3693 ( .A(n6711), .Y(n5619) );
XNOR2X1TS U3694 ( .A(n1942), .B(n5619), .Y(n2330) );
OAI22X1TS U3695 ( .A0(n2544), .A1(n1914), .B0(n2330), .B1(n3273), .Y(n2303)
);
XNOR2X1TS U3696 ( .A(n50), .B(n4066), .Y(n2328) );
OAI22X1TS U3697 ( .A0(n3618), .A1(n1915), .B0(n124), .B1(n2328), .Y(n2302)
);
XNOR2X1TS U3698 ( .A(n36), .B(n5465), .Y(n2282) );
OAI22X1TS U3699 ( .A0(n2547), .A1(n1916), .B0(n2281), .B1(n2282), .Y(n2301)
);
XNOR2X1TS U3700 ( .A(Data_A_i[27]), .B(Data_B_i[19]), .Y(n2346) );
OAI22X1TS U3701 ( .A0(n4575), .A1(n1917), .B0(n135), .B1(n2346), .Y(n2277)
);
XNOR2X1TS U3702 ( .A(n3249), .B(n3241), .Y(n2014) );
XNOR2X1TS U3703 ( .A(n3249), .B(n4071), .Y(n2299) );
OAI22X1TS U3704 ( .A0(n128), .A1(n2014), .B0(n4400), .B1(n2299), .Y(n2276)
);
XNOR2X1TS U3705 ( .A(n2552), .B(n5278), .Y(n2286) );
OAI22X1TS U3706 ( .A0(n143), .A1(n1918), .B0(n88), .B1(n2286), .Y(n2275) );
XNOR2X1TS U3707 ( .A(n132), .B(Data_B_i[20]), .Y(n2088) );
XNOR2X1TS U3708 ( .A(n3040), .B(n3068), .Y(n1945) );
OAI22X1TS U3709 ( .A0(n70), .A1(n2088), .B0(n124), .B1(n1945), .Y(n2142) );
XNOR2X1TS U3710 ( .A(n1922), .B(n3878), .Y(n2107) );
XNOR2X1TS U3711 ( .A(n1922), .B(n4201), .Y(n1925) );
XNOR2X1TS U3712 ( .A(n2343), .B(Data_B_i[32]), .Y(n1962) );
OAI22X1TS U3713 ( .A0(n1964), .A1(n1962), .B0(n2058), .B1(n1923), .Y(n2140)
);
OAI22X1TS U3714 ( .A0(n824), .A1(n1925), .B0(n177), .B1(n1924), .Y(n1934) );
OAI22X1TS U3715 ( .A0(n2056), .A1(n1927), .B0(n38), .B1(n1926), .Y(n1933) );
XNOR2X1TS U3716 ( .A(n3209), .B(n4066), .Y(n1997) );
OAI22X1TS U3717 ( .A0(n3723), .A1(n1997), .B0(n44), .B1(n1928), .Y(n1932) );
CMPR32X2TS U3718 ( .A(n1940), .B(n1939), .C(n1938), .CO(n1907), .S(n2000) );
XNOR2X1TS U3719 ( .A(Data_A_i[19]), .B(n2896), .Y(n2072) );
OAI22X1TS U3720 ( .A0(n149), .A1(n2072), .B0(n3503), .B1(n1941), .Y(n2098)
);
XNOR2X1TS U3721 ( .A(n1942), .B(n5180), .Y(n2091) );
OAI22X1TS U3722 ( .A0(n2093), .A1(n2091), .B0(n1943), .B1(n2090), .Y(n2097)
);
XNOR2X1TS U3723 ( .A(n6376), .B(n3241), .Y(n1971) );
XNOR2X1TS U3724 ( .A(n5529), .B(n4071), .Y(n1959) );
OAI22X1TS U3725 ( .A0(n60), .A1(n1971), .B0(n138), .B1(n1959), .Y(n2096) );
OAI22X1TS U3726 ( .A0(n3618), .A1(n1945), .B0(n125), .B1(n1944), .Y(n1986)
);
XNOR2X1TS U3727 ( .A(n2466), .B(n4068), .Y(n1953) );
OAI22X1TS U3728 ( .A0(n4635), .A1(n1953), .B0(n137), .B1(n1946), .Y(n1985)
);
OAI22X1TS U3729 ( .A0(n2280), .A1(n1948), .B0(n3405), .B1(n1947), .Y(n1984)
);
XNOR2X1TS U3730 ( .A(n5418), .B(n2804), .Y(n2102) );
OAI22X1TS U3731 ( .A0(n4084), .A1(n2102), .B0(n141), .B1(n1952), .Y(n2101)
);
XNOR2X1TS U3732 ( .A(n2466), .B(n3988), .Y(n1969) );
OAI22X1TS U3733 ( .A0(n5217), .A1(n1969), .B0(n136), .B1(n1953), .Y(n2100)
);
XNOR2X1TS U3734 ( .A(Data_A_i[3]), .B(n4469), .Y(n2076) );
OAI22X1TS U3735 ( .A0(n2078), .A1(n2076), .B0(n3990), .B1(n1954), .Y(n2099)
);
XNOR2X1TS U3736 ( .A(n1987), .B(n3497), .Y(n1988) );
OAI22X1TS U3737 ( .A0(n3525), .A1(n1988), .B0(n2507), .B1(n1955), .Y(n1978)
);
XNOR2X1TS U3738 ( .A(Data_A_i[41]), .B(n2037), .Y(n1956) );
XNOR2X1TS U3739 ( .A(Data_A_i[41]), .B(n3048), .Y(n1961) );
INVX2TS U3740 ( .A(n6588), .Y(n6469) );
NAND2BX1TS U3741 ( .AN(n2472), .B(n6469), .Y(n1957) );
NOR2BX1TS U3742 ( .AN(n2871), .B(n6659), .Y(n1981) );
OAI22X1TS U3743 ( .A0(n5431), .A1(n1959), .B0(n3357), .B1(n1958), .Y(n1980)
);
OAI22X1TS U3744 ( .A0(n5549), .A1(n1961), .B0(n4686), .B1(n1960), .Y(n1979)
);
OAI22X1TS U3745 ( .A0(n1964), .A1(n1963), .B0(n2058), .B1(n1962), .Y(n2181)
);
OAI22X1TS U3746 ( .A0(n2056), .A1(n1968), .B0(n38), .B1(n1967), .Y(n2179) );
NOR2BX1TS U3747 ( .AN(n2871), .B(n6589), .Y(n2118) );
OAI22X1TS U3748 ( .A0(n5942), .A1(n1972), .B0(n6466), .B1(n1971), .Y(n2116)
);
CMPR32X2TS U3749 ( .A(n1975), .B(n1974), .C(n1973), .CO(n2079), .S(n2155) );
CMPR32X2TS U3750 ( .A(n1986), .B(n1985), .C(n1984), .CO(n2006), .S(n2083) );
XNOR2X1TS U3751 ( .A(n1987), .B(n3738), .Y(n2066) );
OAI22X1TS U3752 ( .A0(n3525), .A1(n2066), .B0(n2507), .B1(n1988), .Y(n2133)
);
XNOR2X1TS U3753 ( .A(n3741), .B(n1989), .Y(n2074) );
OAI22X1TS U3754 ( .A0(n4422), .A1(n2074), .B0(n4420), .B1(n1990), .Y(n2132)
);
XNOR2X1TS U3755 ( .A(n3986), .B(n1991), .Y(n2136) );
OAI22X1TS U3756 ( .A0(n147), .A1(n2136), .B0(n91), .B1(n1992), .Y(n2131) );
XNOR2X1TS U3757 ( .A(n3847), .B(n4338), .Y(n2068) );
OAI22X1TS U3758 ( .A0(n4006), .A1(n2068), .B0(n4091), .B1(n1996), .Y(n2113)
);
XNOR2X1TS U3759 ( .A(n81), .B(n4032), .Y(n2134) );
OAI22X1TS U3760 ( .A0(n3723), .A1(n2134), .B0(n45), .B1(n1997), .Y(n2112) );
CMPR32X2TS U3761 ( .A(n2002), .B(n2001), .C(n2000), .CO(n2027), .S(n2146) );
XNOR2X4TS U3762 ( .A(n6658), .B(n2012), .Y(n5527) );
NOR2BX1TS U3763 ( .AN(n2871), .B(n5527), .Y(n2042) );
XNOR2X1TS U3764 ( .A(Data_A_i[41]), .B(n3988), .Y(n2062) );
OAI22X1TS U3765 ( .A0(n4009), .A1(n2015), .B0(n4566), .B1(n2014), .Y(n2040)
);
CMPR32X2TS U3766 ( .A(n2021), .B(n2020), .C(n2019), .CO(n2271), .S(n2046) );
CMPR32X2TS U3767 ( .A(n2033), .B(n2032), .C(n2031), .CO(n2332), .S(n1881) );
XNOR2X1TS U3768 ( .A(n2859), .B(n3073), .Y(n2278) );
OAI22X1TS U3769 ( .A0(n150), .A1(n2035), .B0(n2034), .B1(n2278), .Y(n2295)
);
INVX12TS U3770 ( .A(Data_A_i[45]), .Y(n3343) );
INVX4TS U3771 ( .A(n3343), .Y(n5959) );
XOR2X4TS U3772 ( .A(Data_A_i[44]), .B(n5959), .Y(n2036) );
XNOR2X1TS U3773 ( .A(n3926), .B(n2037), .Y(n2038) );
BUFX3TS U3774 ( .A(n5527), .Y(n6683) );
XNOR2X1TS U3775 ( .A(n3926), .B(n3048), .Y(n2300) );
OAI22X1TS U3776 ( .A0(n3735), .A1(n2038), .B0(n6683), .B1(n2300), .Y(n2297)
);
BUFX4TS U3777 ( .A(n5527), .Y(n5884) );
NAND2BX1TS U3778 ( .AN(n2864), .B(n5959), .Y(n2039) );
OAI22X1TS U3779 ( .A0(n3735), .A1(n6705), .B0(n5884), .B1(n2039), .Y(n2296)
);
XNOR2X1TS U3780 ( .A(n1468), .B(n3068), .Y(n2283) );
OAI22X1TS U3781 ( .A0(n2056), .A1(n2055), .B0(n109), .B1(n2283), .Y(n2327)
);
XNOR2X1TS U3782 ( .A(n6336), .B(n4099), .Y(n2358) );
OAI22X1TS U3783 ( .A0(n5817), .A1(n2057), .B0(n3357), .B1(n2358), .Y(n2326)
);
XNOR2X1TS U3784 ( .A(n2343), .B(n77), .Y(n2344) );
OAI22X1TS U3785 ( .A0(n105), .A1(n2059), .B0(n2058), .B1(n2344), .Y(n2325)
);
XNOR2X1TS U3786 ( .A(n5908), .B(Data_B_i[17]), .Y(n2355) );
OAI22X1TS U3787 ( .A0(n6003), .A1(n2060), .B0(n2494), .B1(n2355), .Y(n2292)
);
XNOR2X1TS U3788 ( .A(n4078), .B(n5143), .Y(n2352) );
OAI22X1TS U3789 ( .A0(n2110), .A1(n2061), .B0(n177), .B1(n2352), .Y(n2291)
);
XNOR2X1TS U3790 ( .A(n82), .B(n4068), .Y(n2357) );
OAI22X1TS U3791 ( .A0(n6525), .A1(n2062), .B0(n4230), .B1(n2357), .Y(n2290)
);
OAI22X1TS U3792 ( .A0(n3525), .A1(n2067), .B0(n2507), .B1(n2066), .Y(n2175)
);
OAI22X1TS U3793 ( .A0(n43), .A1(n2071), .B0(n2462), .B1(n2070), .Y(n2173) );
OAI22X1TS U3794 ( .A0(n5294), .A1(n2073), .B0(n3503), .B1(n2072), .Y(n2199)
);
OAI22X1TS U3795 ( .A0(n6184), .A1(n2075), .B0(n5144), .B1(n2074), .Y(n2198)
);
OAI22X1TS U3796 ( .A0(n2078), .A1(n2077), .B0(n3990), .B1(n2076), .Y(n2197)
);
OAI22X1TS U3797 ( .A0(n3760), .A1(n2089), .B0(n125), .B1(n2088), .Y(n2202)
);
OAI22X1TS U3798 ( .A0(n2093), .A1(n2092), .B0(n2091), .B1(n2090), .Y(n2201)
);
OAI22X1TS U3799 ( .A0(n2280), .A1(n2095), .B0(n3405), .B1(n2094), .Y(n2200)
);
CMPR32X2TS U3800 ( .A(n2101), .B(n2100), .C(n2099), .CO(n2124), .S(n2182) );
OAI22X1TS U3801 ( .A0(n4258), .A1(n2103), .B0(n5585), .B1(n2102), .Y(n2193)
);
OAI22X1TS U3802 ( .A0(n2106), .A1(n2105), .B0(n87), .B1(n2104), .Y(n2192) );
OAI22X1TS U3803 ( .A0(n735), .A1(n2109), .B0(n2108), .B1(n2107), .Y(n2191)
);
ADDHX1TS U3804 ( .A(n2115), .B(n2114), .CO(n2232), .S(n2165) );
CMPR32X2TS U3805 ( .A(n2121), .B(n2120), .C(n2119), .CO(n2230), .S(n2255) );
OAI22X1TS U3806 ( .A0(n3723), .A1(n2135), .B0(n44), .B1(n2134), .Y(n2190) );
OAI22X1TS U3807 ( .A0(n145), .A1(n2137), .B0(n91), .B1(n2136), .Y(n2189) );
OAI22X1TS U3808 ( .A0(n6003), .A1(n2139), .B0(n2494), .B1(n2138), .Y(n2188)
);
CMPR32X2TS U3809 ( .A(n2142), .B(n2141), .C(n2140), .CO(n2145), .S(n2170) );
CMPR32X2TS U3810 ( .A(n2184), .B(n2183), .C(n2182), .CO(n2214), .S(n2239) );
CMPR32X2TS U3811 ( .A(n2187), .B(n2186), .C(n2185), .CO(n2262), .S(n2245) );
CMPR32X2TS U3812 ( .A(n2190), .B(n2189), .C(n2188), .CO(n2171), .S(n2261) );
CMPR32X2TS U3813 ( .A(n2193), .B(n2192), .C(n2191), .CO(n2205), .S(n2260) );
CMPR32X2TS U3814 ( .A(n2196), .B(n2195), .C(n2194), .CO(n2235), .S(n2257) );
CMPR32X2TS U3815 ( .A(n2202), .B(n2201), .C(n2200), .CO(n2184), .S(n2233) );
OR2X8TS U3816 ( .A(n2448), .B(n2449), .Y(n7657) );
CMPR32X2TS U3817 ( .A(n2259), .B(n2258), .C(n2257), .CO(n2378), .S(n2383) );
CMPR32X2TS U3818 ( .A(n2274), .B(n2273), .C(n2272), .CO(n2679), .S(n2304) );
CMPR32X2TS U3819 ( .A(n2277), .B(n2276), .C(n2275), .CO(n2585), .S(n2319) );
XNOR2X1TS U3820 ( .A(n2859), .B(n3704), .Y(n2652) );
OAI22X1TS U3821 ( .A0(n5235), .A1(n2278), .B0(n4702), .B1(n2652), .Y(n2594)
);
INVX2TS U3822 ( .A(n3845), .Y(n3925) );
XNOR2X1TS U3823 ( .A(n6238), .B(n3925), .Y(n2483) );
OAI22X1TS U3824 ( .A0(n2280), .A1(n2279), .B0(n3026), .B1(n2483), .Y(n2593)
);
XNOR2X1TS U3825 ( .A(n35), .B(n5525), .Y(n2546) );
OAI22X1TS U3826 ( .A0(n2547), .A1(n2282), .B0(n2281), .B1(n2546), .Y(n2592)
);
INVX2TS U3827 ( .A(n5755), .Y(n4388) );
XNOR2X1TS U3828 ( .A(n116), .B(n2896), .Y(n2496) );
OAI22X1TS U3829 ( .A0(n4390), .A1(n2283), .B0(n2928), .B1(n2496), .Y(n2537)
);
XNOR2X1TS U3830 ( .A(n6066), .B(n2284), .Y(n2505) );
OAI22X1TS U3831 ( .A0(n6252), .A1(n2285), .B0(n59), .B1(n2505), .Y(n2536) );
XNOR2X1TS U3832 ( .A(n2552), .B(n5383), .Y(n2637) );
OAI22X1TS U3833 ( .A0(n144), .A1(n2286), .B0(n88), .B1(n2637), .Y(n2535) );
CMPR32X2TS U3834 ( .A(n2292), .B(n2291), .C(n2290), .CO(n2615), .S(n2272) );
XNOR2X4TS U3835 ( .A(n3343), .B(Data_A_i[46]), .Y(n2298) );
NOR2BX1TS U3836 ( .AN(n2871), .B(n6487), .Y(n2489) );
XNOR2X1TS U3837 ( .A(n3249), .B(n3988), .Y(n2510) );
XNOR2X1TS U3838 ( .A(n3926), .B(n3241), .Y(n2635) );
OAI22X1TS U3839 ( .A0(n3735), .A1(n2300), .B0(n6316), .B1(n2635), .Y(n2487)
);
ADDFHX2TS U3840 ( .A(n2312), .B(n2311), .CI(n2310), .CO(n2854), .S(n2364) );
CMPR32X2TS U3841 ( .A(n2321), .B(n2320), .C(n2319), .CO(n2677), .S(n2316) );
XNOR2X1TS U3842 ( .A(n132), .B(n4338), .Y(n2541) );
OAI22X1TS U3843 ( .A0(n3618), .A1(n2328), .B0(n124), .B1(n2541), .Y(n2591)
);
XNOR2X1TS U3844 ( .A(n4394), .B(n4043), .Y(n2481) );
OAI22X1TS U3845 ( .A0(n6381), .A1(n2329), .B0(n137), .B1(n2481), .Y(n2590)
);
XNOR2X1TS U3846 ( .A(Data_A_i[1]), .B(n5697), .Y(n2543) );
OAI22X1TS U3847 ( .A0(n2544), .A1(n2330), .B0(n2543), .B1(n3273), .Y(n2589)
);
XNOR2X1TS U3848 ( .A(n2789), .B(n3878), .Y(n2458) );
OAI22X1TS U3849 ( .A0(n40), .A1(n2340), .B0(n2462), .B1(n2458), .Y(n2588) );
XNOR2X1TS U3850 ( .A(n2503), .B(n4335), .Y(n2508) );
XNOR2X1TS U3851 ( .A(Data_A_i[15]), .B(n76), .Y(n2479) );
OAI22X1TS U3852 ( .A0(n102), .A1(n2342), .B0(n4593), .B1(n2479), .Y(n2586)
);
XNOR2X1TS U3853 ( .A(n2343), .B(n4469), .Y(n2630) );
OAI22X1TS U3854 ( .A0(n105), .A1(n2344), .B0(n3361), .B1(n2630), .Y(n2492)
);
BUFX3TS U3855 ( .A(n2345), .Y(n4518) );
XNOR2X1TS U3856 ( .A(Data_A_i[27]), .B(Data_B_i[20]), .Y(n2632) );
XNOR2X1TS U3857 ( .A(n2347), .B(n5844), .Y(n2493) );
OAI22X1TS U3858 ( .A0(n2904), .A1(n2348), .B0(n45), .B1(n2493), .Y(n2490) );
CMPR32X2TS U3859 ( .A(n2351), .B(n2350), .C(n2349), .CO(n2609), .S(n2334) );
XNOR2X1TS U3860 ( .A(n2965), .B(n5180), .Y(n2628) );
OAI22X1TS U3861 ( .A0(n735), .A1(n2352), .B0(n177), .B1(n2628), .Y(n2477) );
XNOR2X1TS U3862 ( .A(n5908), .B(Data_B_i[18]), .Y(n2495) );
OAI22X1TS U3863 ( .A0(n6003), .A1(n2355), .B0(n2494), .B1(n2495), .Y(n2475)
);
XNOR2X1TS U3864 ( .A(n4256), .B(n4032), .Y(n2654) );
OAI22X1TS U3865 ( .A0(n4084), .A1(n2356), .B0(n140), .B1(n2654), .Y(n2624)
);
XNOR2X1TS U3866 ( .A(n82), .B(n4035), .Y(n2459) );
OAI22X1TS U3867 ( .A0(n6590), .A1(n2357), .B0(n4230), .B1(n2459), .Y(n2623)
);
XNOR2X1TS U3868 ( .A(n118), .B(n4000), .Y(n2460) );
OAI22X1TS U3869 ( .A0(n60), .A1(n2358), .B0(n5432), .B1(n2460), .Y(n2622) );
ADDFHX4TS U3870 ( .A(n2364), .B(n2363), .CI(n2362), .CO(n2452), .S(n2448) );
NOR2X2TS U3871 ( .A(n2453), .B(n2452), .Y(n7646) );
NOR2X4TS U3872 ( .A(n7643), .B(n7646), .Y(n2455) );
ADDFHX2TS U3873 ( .A(n2373), .B(n2372), .CI(n2371), .CO(n2400), .S(n2395) );
ADDFHX4TS U3874 ( .A(n2376), .B(n2375), .CI(n2374), .CO(n2370), .S(n2399) );
NOR2X2TS U3875 ( .A(n2439), .B(n2438), .Y(n7661) );
INVX2TS U3876 ( .A(n7661), .Y(n7680) );
ADDFHX2TS U3877 ( .A(n2409), .B(n2408), .CI(n2407), .CO(n2447), .S(n2441) );
OR2X4TS U3878 ( .A(n2441), .B(n2440), .Y(n7665) );
ADDFHX2TS U3879 ( .A(n2415), .B(n2414), .CI(n2413), .CO(n2438), .S(n2436) );
NAND2BX4TS U3880 ( .AN(n2436), .B(n2425), .Y(n7671) );
ADDFHX2TS U3881 ( .A(n2428), .B(n2427), .CI(n2426), .CO(n2435), .S(n2434) );
NAND2X2TS U3882 ( .A(n7671), .B(n7669), .Y(n7674) );
NAND2X2TS U3883 ( .A(n2455), .B(n7640), .Y(n2457) );
NOR2BX4TS U3884 ( .AN(n2434), .B(n2433), .Y(n7668) );
INVX2TS U3885 ( .A(n7670), .Y(n2437) );
AOI21X4TS U3886 ( .A0(n7671), .A1(n7668), .B0(n2437), .Y(n7675) );
NAND2X2TS U3887 ( .A(n2439), .B(n2438), .Y(n7679) );
INVX2TS U3888 ( .A(n7679), .Y(n2443) );
NAND2X1TS U3889 ( .A(n2441), .B(n2440), .Y(n7664) );
INVX2TS U3890 ( .A(n7664), .Y(n2442) );
AOI21X4TS U3891 ( .A0(n7665), .A1(n2443), .B0(n2442), .Y(n2444) );
OAI21X4TS U3892 ( .A0(n7675), .A1(n2445), .B0(n2444), .Y(n7641) );
INVX2TS U3893 ( .A(n7658), .Y(n2450) );
AOI21X4TS U3894 ( .A0(n7657), .A1(n2451), .B0(n2450), .Y(n7642) );
OAI21X2TS U3895 ( .A0(n7642), .A1(n7646), .B0(n7647), .Y(n2454) );
AOI21X4TS U3896 ( .A0(n7641), .A1(n2455), .B0(n2454), .Y(n2456) );
OAI21X4TS U3897 ( .A0(n7358), .A1(n2457), .B0(n2456), .Y(n7176) );
XNOR2X1TS U3898 ( .A(n2789), .B(n4201), .Y(n2463) );
OAI22X1TS U3899 ( .A0(n43), .A1(n2458), .B0(n83), .B1(n2463), .Y(n2486) );
XNOR2X1TS U3900 ( .A(Data_A_i[41]), .B(n4099), .Y(n2501) );
XNOR2X1TS U3901 ( .A(n118), .B(n4080), .Y(n2465) );
OAI22X1TS U3902 ( .A0(n5942), .A1(n2460), .B0(n6466), .B1(n2465), .Y(n2484)
);
INVX2TS U3903 ( .A(Data_B_i[33]), .Y(n6257) );
XNOR2X1TS U3904 ( .A(n2705), .B(n4082), .Y(n2478) );
INVX2TS U3905 ( .A(n6307), .Y(n6033) );
XNOR2X1TS U3906 ( .A(n4247), .B(n6033), .Y(n2706) );
OAI22X1TS U3907 ( .A0(n102), .A1(n2478), .B0(n4091), .B1(n2706), .Y(n2524)
);
BUFX3TS U3908 ( .A(n5494), .Y(n4536) );
INVX2TS U3909 ( .A(n4203), .Y(n4131) );
XNOR2X1TS U3910 ( .A(n6238), .B(n4131), .Y(n2482) );
INVX2TS U3911 ( .A(n4246), .Y(n4007) );
XNOR2X1TS U3912 ( .A(n6238), .B(n4007), .Y(n2577) );
OAI22X1TS U3913 ( .A0(n4536), .A1(n2482), .B0(n6308), .B1(n2577), .Y(n2523)
);
XNOR2X1TS U3914 ( .A(n114), .B(n2461), .Y(n2504) );
XNOR2X1TS U3915 ( .A(n3741), .B(Data_B_i[16]), .Y(n2574) );
OAI22X1TS U3916 ( .A0(n121), .A1(n2504), .B0(n59), .B1(n2574), .Y(n2522) );
XNOR2X1TS U3917 ( .A(n2789), .B(n4335), .Y(n2526) );
OAI22X1TS U3918 ( .A0(n41), .A1(n2463), .B0(n2462), .B1(n2526), .Y(n2469) );
XNOR2X1TS U3919 ( .A(n119), .B(n4043), .Y(n2531) );
OAI22X1TS U3920 ( .A0(n5942), .A1(n2465), .B0(n139), .B1(n2531), .Y(n2468)
);
XNOR2X1TS U3921 ( .A(n4394), .B(n4112), .Y(n2480) );
XNOR2X1TS U3922 ( .A(n2466), .B(n3925), .Y(n2527) );
OAI22X1TS U3923 ( .A0(n6381), .A1(n2480), .B0(n137), .B1(n2527), .Y(n2467)
);
CMPR32X2TS U3924 ( .A(n2469), .B(n2468), .C(n2467), .CO(n2831), .S(n2657) );
XNOR2X1TS U3925 ( .A(n3986), .B(Data_B_i[17]), .Y(n2625) );
XNOR2X1TS U3926 ( .A(Data_A_i[31]), .B(Data_B_i[18]), .Y(n2528) );
OAI22X1TS U3927 ( .A0(n146), .A1(n2625), .B0(n4204), .B1(n2528), .Y(n2556)
);
XNOR2X1TS U3928 ( .A(n4108), .B(n5143), .Y(n2629) );
XNOR2X1TS U3929 ( .A(Data_A_i[9]), .B(n5180), .Y(n2575) );
OAI22X1TS U3930 ( .A0(n105), .A1(n2629), .B0(n3361), .B1(n2575), .Y(n2555)
);
XNOR2X1TS U3931 ( .A(n3249), .B(n4068), .Y(n2509) );
XNOR2X1TS U3932 ( .A(n3249), .B(n4035), .Y(n2529) );
OAI22X1TS U3933 ( .A0(n129), .A1(n2509), .B0(n4400), .B1(n2529), .Y(n2554)
);
XNOR2X1TS U3934 ( .A(n2859), .B(n5890), .Y(n2651) );
XNOR2X1TS U3935 ( .A(n2859), .B(n5844), .Y(n2703) );
OAI22X1TS U3936 ( .A0(n150), .A1(n2651), .B0(n4702), .B1(n2703), .Y(n2499)
);
BUFX4TS U3937 ( .A(n6319), .Y(n4225) );
XNOR2X1TS U3938 ( .A(Data_A_i[47]), .B(n3046), .Y(n2471) );
XNOR2X1TS U3939 ( .A(Data_A_i[47]), .B(n3048), .Y(n2474) );
OAI22X1TS U3940 ( .A0(n4225), .A1(n2471), .B0(n6487), .B1(n2474), .Y(n2656)
);
OAI22X1TS U3941 ( .A0(n4225), .A1(n6768), .B0(n3933), .B1(n2473), .Y(n2655)
);
XNOR2X4TS U3942 ( .A(Data_A_i[47]), .B(Data_A_i[48]), .Y(n2558) );
NOR2BX1TS U3943 ( .AN(n2871), .B(n6992), .Y(n2563) );
XNOR2X1TS U3944 ( .A(n3926), .B(n4071), .Y(n2634) );
XNOR2X1TS U3945 ( .A(n3926), .B(n3988), .Y(n2579) );
OAI22X1TS U3946 ( .A0(n5883), .A1(n2634), .B0(n6683), .B1(n2579), .Y(n2562)
);
XNOR2X1TS U3947 ( .A(Data_A_i[47]), .B(n3241), .Y(n2578) );
OAI22X1TS U3948 ( .A0(n4225), .A1(n2474), .B0(n3933), .B1(n2578), .Y(n2561)
);
OAI22X1TS U3949 ( .A0(n3348), .A1(n2479), .B0(n3213), .B1(n2478), .Y(n2647)
);
BUFX3TS U3950 ( .A(n5886), .Y(n5267) );
OAI22X1TS U3951 ( .A0(n4536), .A1(n2483), .B0(n5120), .B1(n2482), .Y(n2645)
);
XNOR2X1TS U3952 ( .A(n3209), .B(n5911), .Y(n2648) );
OAI22X1TS U3953 ( .A0(n2904), .A1(n2493), .B0(n63), .B1(n2648), .Y(n2692) );
XNOR2X1TS U3954 ( .A(n5908), .B(n3781), .Y(n2500) );
OAI22X1TS U3955 ( .A0(n130), .A1(n2495), .B0(n2494), .B1(n2500), .Y(n2691)
);
XNOR2X1TS U3956 ( .A(n5520), .B(n4110), .Y(n2649) );
OAI22X1TS U3957 ( .A0(n4390), .A1(n2496), .B0(n2895), .B1(n2649), .Y(n2690)
);
BUFX3TS U3958 ( .A(n5249), .Y(n5226) );
XNOR2X1TS U3959 ( .A(n1482), .B(n2936), .Y(n2520) );
XNOR2X1TS U3960 ( .A(Data_A_i[41]), .B(n4000), .Y(n2530) );
BUFX3TS U3961 ( .A(n2502), .Y(n3356) );
XNOR2X1TS U3962 ( .A(n2503), .B(Data_B_i[37]), .Y(n2506) );
XNOR2X1TS U3963 ( .A(n2503), .B(n4469), .Y(n2576) );
OAI22X1TS U3964 ( .A0(n3356), .A1(n2506), .B0(n111), .B1(n2576), .Y(n2513)
);
OAI22X1TS U3965 ( .A0(n129), .A1(n2510), .B0(n4400), .B1(n2509), .Y(n2538)
);
XNOR2X1TS U3966 ( .A(n4256), .B(n4066), .Y(n2653) );
XNOR2X1TS U3967 ( .A(n3220), .B(n4338), .Y(n2517) );
INVX2TS U3968 ( .A(Data_B_i[47]), .Y(n6760) );
INVX2TS U3969 ( .A(n6760), .Y(n5718) );
XNOR2X1TS U3970 ( .A(Data_A_i[1]), .B(n5718), .Y(n2542) );
INVX2TS U3971 ( .A(n6886), .Y(n5839) );
XNOR2X1TS U3972 ( .A(Data_A_i[1]), .B(n5839), .Y(n2518) );
OAI22X1TS U3973 ( .A0(n2544), .A1(n2542), .B0(n2518), .B1(n3273), .Y(n2565)
);
XNOR2X1TS U3974 ( .A(n35), .B(n5619), .Y(n2545) );
BUFX3TS U3975 ( .A(n2512), .Y(n4612) );
XNOR2X1TS U3976 ( .A(n35), .B(n5697), .Y(n2519) );
OAI22X1TS U3977 ( .A0(n4614), .A1(n2545), .B0(n4612), .B1(n2519), .Y(n2564)
);
XNOR2X1TS U3978 ( .A(n3220), .B(n3073), .Y(n2784) );
OAI22X1TS U3979 ( .A0(n5586), .A1(n2517), .B0(n2516), .B1(n2784), .Y(n2816)
);
INVX2TS U3980 ( .A(Data_B_i[49]), .Y(n6994) );
INVX2TS U3981 ( .A(n6994), .Y(n5881) );
XNOR2X1TS U3982 ( .A(Data_A_i[1]), .B(n5881), .Y(n2807) );
OAI22X1TS U3983 ( .A0(n2544), .A1(n2518), .B0(n2807), .B1(n3273), .Y(n2815)
);
XNOR2X1TS U3984 ( .A(n117), .B(n5718), .Y(n2808) );
OAI22X1TS U3985 ( .A0(n4614), .A1(n2519), .B0(n4612), .B1(n2808), .Y(n2814)
);
XNOR2X1TS U3986 ( .A(n5908), .B(Data_B_i[21]), .Y(n2778) );
OAI22X1TS U3987 ( .A0(n2521), .A1(n2520), .B0(n5226), .B1(n2778), .Y(n2774)
);
XNOR2X1TS U3988 ( .A(n4097), .B(n5525), .Y(n2553) );
XNOR2X1TS U3989 ( .A(n2552), .B(n5619), .Y(n2827) );
XNOR2X1TS U3990 ( .A(n2965), .B(n5383), .Y(n2551) );
XNOR2X1TS U3991 ( .A(n2965), .B(n5465), .Y(n2782) );
OAI22X1TS U3992 ( .A0(n2110), .A1(n2551), .B0(n2781), .B1(n2782), .Y(n2772)
);
XNOR2X1TS U3993 ( .A(n2789), .B(Data_B_i[37]), .Y(n2790) );
INVX2TS U3994 ( .A(n6390), .Y(n6343) );
XNOR2X1TS U3995 ( .A(n6343), .B(n4131), .Y(n2828) );
OAI22X1TS U3996 ( .A0(n5266), .A1(n2527), .B0(n136), .B1(n2828), .Y(n2800)
);
XNOR2X1TS U3997 ( .A(n3986), .B(n3781), .Y(n2783) );
OAI22X1TS U3998 ( .A0(n146), .A1(n2528), .B0(n4204), .B1(n2783), .Y(n2799)
);
XNOR2X1TS U3999 ( .A(n3249), .B(n4099), .Y(n2780) );
OAI22X1TS U4000 ( .A0(n129), .A1(n2529), .B0(n4400), .B1(n2780), .Y(n2750)
);
XNOR2X1TS U4001 ( .A(n5187), .B(n4080), .Y(n2776) );
OAI22X1TS U4002 ( .A0(n6525), .A1(n2530), .B0(n4230), .B1(n2776), .Y(n2749)
);
XNOR2X1TS U4003 ( .A(n6376), .B(n4112), .Y(n2777) );
OAI22X1TS U4004 ( .A0(n60), .A1(n2531), .B0(n6466), .B1(n2777), .Y(n2748) );
CMPR32X2TS U4005 ( .A(n2537), .B(n2536), .C(n2535), .CO(n2597), .S(n2583) );
XNOR2X1TS U4006 ( .A(n132), .B(n3073), .Y(n2650) );
OAI22X1TS U4007 ( .A0(n3618), .A1(n2541), .B0(n124), .B1(n2650), .Y(n2550)
);
OAI22X1TS U4008 ( .A0(n2544), .A1(n2543), .B0(n2542), .B1(n3273), .Y(n2549)
);
OAI22X1TS U4009 ( .A0(n2547), .A1(n2546), .B0(n4612), .B1(n2545), .Y(n2548)
);
CMPR32X2TS U4010 ( .A(n2550), .B(n2549), .C(n2548), .CO(n2569), .S(n2595) );
XNOR2X1TS U4011 ( .A(Data_A_i[27]), .B(n3068), .Y(n2631) );
INVX2TS U4012 ( .A(n5892), .Y(n5101) );
XNOR2X1TS U4013 ( .A(n5101), .B(n2896), .Y(n2707) );
OAI22X1TS U4014 ( .A0(n5103), .A1(n2631), .B0(n4518), .B1(n2707), .Y(n2572)
);
XNOR2X1TS U4015 ( .A(n2965), .B(n5278), .Y(n2627) );
OAI22X1TS U4016 ( .A0(n4716), .A1(n2627), .B0(n2781), .B1(n2551), .Y(n2571)
);
XNOR2X1TS U4017 ( .A(n2552), .B(n5465), .Y(n2636) );
OAI22X1TS U4018 ( .A0(n2638), .A1(n2636), .B0(n7), .B1(n2553), .Y(n2570) );
CMPR32X2TS U4019 ( .A(n2556), .B(n2555), .C(n2554), .CO(n2830), .S(n2567) );
XOR2X2TS U4020 ( .A(Data_A_i[48]), .B(Data_A_i[49]), .Y(n2557) );
INVX2TS U4021 ( .A(n6991), .Y(n4100) );
XNOR2X1TS U4022 ( .A(n4100), .B(n3046), .Y(n2559) );
BUFX3TS U4023 ( .A(n6992), .Y(n5454) );
XNOR2X1TS U4024 ( .A(n4100), .B(n3048), .Y(n2813) );
OAI22X1TS U4025 ( .A0(n4381), .A1(n2559), .B0(n5454), .B1(n2813), .Y(n2792)
);
OAI22X1TS U4026 ( .A0(n4381), .A1(n6991), .B0(n4253), .B1(n2560), .Y(n2791)
);
CMPR32X2TS U4027 ( .A(n2563), .B(n2562), .C(n2561), .CO(n2755), .S(n2497) );
XNOR2X1TS U4028 ( .A(Data_A_i[33]), .B(n2573), .Y(n2805) );
OAI22X1TS U4029 ( .A0(n120), .A1(n2574), .B0(n59), .B1(n2805), .Y(n2822) );
XNOR2X1TS U4030 ( .A(n4108), .B(n5278), .Y(n2817) );
OAI22X1TS U4031 ( .A0(n104), .A1(n2575), .B0(n3361), .B1(n2817), .Y(n2821)
);
XNOR2X1TS U4032 ( .A(n3927), .B(n5143), .Y(n2788) );
OAI22X1TS U4033 ( .A0(n3356), .A1(n2576), .B0(n111), .B1(n2788), .Y(n2820)
);
INVX2TS U4034 ( .A(n4419), .Y(n4250) );
XNOR2X1TS U4035 ( .A(n6238), .B(n4250), .Y(n2802) );
OAI22X1TS U4036 ( .A0(n4599), .A1(n2577), .B0(n6308), .B1(n2802), .Y(n2753)
);
XNOR2X1TS U4037 ( .A(Data_A_i[47]), .B(n4071), .Y(n2812) );
OAI22X1TS U4038 ( .A0(n4582), .A1(n2578), .B0(n6399), .B1(n2812), .Y(n2752)
);
BUFX3TS U4039 ( .A(n5883), .Y(n6511) );
BUFX3TS U4040 ( .A(n5884), .Y(n6044) );
XNOR2X1TS U4041 ( .A(n3926), .B(n4068), .Y(n2779) );
OAI22X1TS U4042 ( .A0(n6685), .A1(n2579), .B0(n6044), .B1(n2779), .Y(n2751)
);
OAI22X1TS U4043 ( .A0(n146), .A1(n2626), .B0(n4204), .B1(n2625), .Y(n2698)
);
OAI22X1TS U4044 ( .A0(n2110), .A1(n2628), .B0(n177), .B1(n2627), .Y(n2697)
);
OAI22X1TS U4045 ( .A0(n105), .A1(n2630), .B0(n3361), .B1(n2629), .Y(n2696)
);
OAI22X1TS U4046 ( .A0(n2633), .A1(n2632), .B0(n4518), .B1(n2631), .Y(n2695)
);
OAI22X1TS U4047 ( .A0(n6511), .A1(n2635), .B0(n6683), .B1(n2634), .Y(n2694)
);
OAI22X1TS U4048 ( .A0(n2638), .A1(n2637), .B0(n87), .B1(n2636), .Y(n2693) );
XNOR2X1TS U4049 ( .A(n3209), .B(n76), .Y(n2702) );
OAI22X1TS U4050 ( .A0(n2904), .A1(n2648), .B0(n51), .B1(n2702), .Y(n2701) );
XNOR2X1TS U4051 ( .A(n5520), .B(n4032), .Y(n2708) );
OAI22X1TS U4052 ( .A0(n55), .A1(n2649), .B0(n108), .B1(n2708), .Y(n2700) );
XNOR2X1TS U4053 ( .A(n133), .B(n3704), .Y(n2704) );
OAI22X1TS U4054 ( .A0(n3618), .A1(n2650), .B0(n4743), .B1(n2704), .Y(n2699)
);
OAI22X1TS U4055 ( .A0(n149), .A1(n2652), .B0(n4702), .B1(n2651), .Y(n2668)
);
OAI22X1TS U4056 ( .A0(n4084), .A1(n2654), .B0(n3425), .B1(n2653), .Y(n2667)
);
ADDHXLTS U4057 ( .A(n2656), .B(n2655), .CO(n2498), .S(n2666) );
CMPR32X2TS U4058 ( .A(n2668), .B(n2667), .C(n2666), .CO(n2687), .S(n2717) );
CMPR32X2TS U4059 ( .A(n2701), .B(n2700), .C(n2699), .CO(n2795), .S(n2688) );
XNOR2X1TS U4060 ( .A(n3209), .B(n4082), .Y(n2803) );
OAI22X1TS U4061 ( .A0(n2904), .A1(n2702), .B0(n44), .B1(n2803), .Y(n2825) );
XNOR2X1TS U4062 ( .A(n2859), .B(n5911), .Y(n2819) );
OAI22X1TS U4063 ( .A0(n149), .A1(n2703), .B0(n4702), .B1(n2819), .Y(n2824)
);
XNOR2X1TS U4064 ( .A(n3040), .B(n5890), .Y(n2826) );
OAI22X1TS U4065 ( .A0(n69), .A1(n2704), .B0(n4743), .B1(n2826), .Y(n2823) );
INVX2TS U4066 ( .A(n6346), .Y(n6248) );
XNOR2X1TS U4067 ( .A(n4089), .B(n6248), .Y(n2818) );
OAI22X1TS U4068 ( .A0(n103), .A1(n2706), .B0(n1379), .B1(n2818), .Y(n2787)
);
XNOR2X1TS U4069 ( .A(n5101), .B(n4110), .Y(n2775) );
OAI22X1TS U4070 ( .A0(n5103), .A1(n2707), .B0(n4518), .B1(n2775), .Y(n2786)
);
XNOR2X1TS U4071 ( .A(n1468), .B(n4066), .Y(n2806) );
OAI22X1TS U4072 ( .A0(n4390), .A1(n2708), .B0(n109), .B1(n2806), .Y(n2785)
);
CMPR32X2TS U4073 ( .A(n2717), .B(n2716), .C(n2715), .CO(n2718), .S(n2723) );
ADDFHX2TS U4074 ( .A(n2720), .B(n2719), .CI(n2718), .CO(n2760), .S(n2729) );
ADDFHX1TS U4075 ( .A(n2726), .B(n2725), .CI(n2724), .CO(n2835), .S(n2727) );
ADDFHX2TS U4076 ( .A(n2735), .B(n2734), .CI(n2733), .CO(n2741), .S(n2851) );
ADDFHX2TS U4077 ( .A(n2738), .B(n2737), .CI(n2736), .CO(n2850), .S(n2855) );
ADDFHX2TS U4078 ( .A(n2741), .B(n2740), .CI(n2739), .CO(n2839), .S(n2841) );
NOR2X2TS U4079 ( .A(n3325), .B(n3324), .Y(n7332) );
ADDFHX2TS U4080 ( .A(n2744), .B(n2743), .CI(n2742), .CO(n3184), .S(n2836) );
CMPR32X2TS U4081 ( .A(n2753), .B(n2752), .C(n2751), .CO(n3096), .S(n2796) );
ADDFHX2TS U4082 ( .A(n2756), .B(n2755), .CI(n2754), .CO(n3095), .S(n2759) );
ADDFHX1TS U4083 ( .A(n2759), .B(n2758), .CI(n2757), .CO(n3167), .S(n2742) );
XNOR2X1TS U4084 ( .A(n5760), .B(n4032), .Y(n2925) );
OAI22X1TS U4085 ( .A0(n2633), .A1(n2775), .B0(n4518), .B1(n2925), .Y(n2993)
);
XNOR2X1TS U4086 ( .A(n5187), .B(n4043), .Y(n2920) );
XNOR2X1TS U4087 ( .A(n119), .B(n3925), .Y(n2932) );
OAI22X1TS U4088 ( .A0(n5942), .A1(n2777), .B0(n138), .B1(n2932), .Y(n2991)
);
XNOR2X1TS U4089 ( .A(Data_A_i[29]), .B(Data_B_i[22]), .Y(n2961) );
OAI22X1TS U4090 ( .A0(n130), .A1(n2778), .B0(n5226), .B1(n2961), .Y(n2996)
);
XNOR2X1TS U4091 ( .A(n3926), .B(n4035), .Y(n2927) );
OAI22X1TS U4092 ( .A0(n6511), .A1(n2779), .B0(n6683), .B1(n2927), .Y(n2995)
);
INVX2TS U4093 ( .A(n6658), .Y(n5427) );
XNOR2X1TS U4094 ( .A(n5427), .B(n4000), .Y(n2930) );
OAI22X1TS U4095 ( .A0(n129), .A1(n2780), .B0(n4400), .B1(n2930), .Y(n2994)
);
XNOR2X1TS U4096 ( .A(n2965), .B(n5525), .Y(n2966) );
OAI22X1TS U4097 ( .A0(n2967), .A1(n2782), .B0(n2781), .B1(n2966), .Y(n2879)
);
XNOR2X1TS U4098 ( .A(n6012), .B(n2936), .Y(n2881) );
OAI22X1TS U4099 ( .A0(n145), .A1(n2783), .B0(n5390), .B1(n2881), .Y(n2878)
);
XNOR2X1TS U4100 ( .A(n3220), .B(n3704), .Y(n2873) );
OAI22X1TS U4101 ( .A0(n5519), .A1(n2784), .B0(n5585), .B1(n2873), .Y(n2877)
);
CMPR32X2TS U4102 ( .A(n2787), .B(n2786), .C(n2785), .CO(n3084), .S(n2793) );
XNOR2X1TS U4103 ( .A(n4133), .B(n5180), .Y(n2934) );
OAI22X1TS U4104 ( .A0(n3356), .A1(n2788), .B0(n112), .B1(n2934), .Y(n2885)
);
XNOR2X1TS U4105 ( .A(n2789), .B(n4469), .Y(n2919) );
OAI22X1TS U4106 ( .A0(n2525), .A1(n2790), .B0(n83), .B1(n2919), .Y(n2884) );
INVX2TS U4107 ( .A(n4477), .Y(n4312) );
XNOR2X1TS U4108 ( .A(n6238), .B(n4312), .Y(n2916) );
XNOR2X1TS U4109 ( .A(n3209), .B(n6033), .Y(n2880) );
XNOR2X1TS U4110 ( .A(n6066), .B(n2804), .Y(n2917) );
OAI22X1TS U4111 ( .A0(n121), .A1(n2805), .B0(n58), .B1(n2917), .Y(n3098) );
XNOR2X1TS U4112 ( .A(n115), .B(n4338), .Y(n2929) );
OAI22X1TS U4113 ( .A0(n4390), .A1(n2806), .B0(n2928), .B1(n2929), .Y(n2924)
);
INVX2TS U4114 ( .A(Data_B_i[50]), .Y(n7015) );
INVX2TS U4115 ( .A(n7015), .Y(n5961) );
XNOR2X1TS U4116 ( .A(n3042), .B(n5961), .Y(n2926) );
OAI22X1TS U4117 ( .A0(n99), .A1(n2807), .B0(n2926), .B1(n3273), .Y(n2923) );
XNOR2X1TS U4118 ( .A(n35), .B(n5839), .Y(n2931) );
OAI22X1TS U4119 ( .A0(n4614), .A1(n2808), .B0(n4612), .B1(n2931), .Y(n2922)
);
XNOR2X4TS U4120 ( .A(Data_A_i[50]), .B(Data_A_i[49]), .Y(n2862) );
NOR2BX1TS U4121 ( .AN(Data_B_i[0]), .B(n7045), .Y(n2868) );
XNOR2X1TS U4122 ( .A(Data_A_i[47]), .B(n3988), .Y(n2876) );
OAI22X1TS U4123 ( .A0(n4582), .A1(n2812), .B0(n6487), .B1(n2876), .Y(n2867)
);
XNOR2X1TS U4124 ( .A(n4100), .B(n3241), .Y(n2875) );
OAI22X1TS U4125 ( .A0(n4381), .A1(n2813), .B0(n4253), .B1(n2875), .Y(n2866)
);
XNOR2X1TS U4126 ( .A(Data_A_i[9]), .B(n5383), .Y(n2933) );
OAI22X1TS U4127 ( .A0(n105), .A1(n2817), .B0(n2984), .B1(n2933), .Y(n2913)
);
INVX2TS U4128 ( .A(n6377), .Y(n5547) );
XNOR2X1TS U4129 ( .A(n2705), .B(n5547), .Y(n2915) );
OAI22X1TS U4130 ( .A0(n102), .A1(n2818), .B0(n49), .B1(n2915), .Y(n2912) );
XNOR2X1TS U4131 ( .A(n4087), .B(Data_B_i[32]), .Y(n2860) );
OAI22X1TS U4132 ( .A0(n5294), .A1(n2819), .B0(n4702), .B1(n2860), .Y(n2911)
);
XNOR2X1TS U4133 ( .A(n133), .B(n5844), .Y(n2882) );
OAI22X1TS U4134 ( .A0(n3760), .A1(n2826), .B0(n4743), .B1(n2882), .Y(n2956)
);
XNOR2X1TS U4135 ( .A(n4097), .B(n5697), .Y(n2963) );
XNOR2X1TS U4136 ( .A(n6343), .B(n4007), .Y(n2921) );
OAI22X1TS U4137 ( .A0(n5217), .A1(n2828), .B0(n136), .B1(n2921), .Y(n2954)
);
ADDFHX2TS U4138 ( .A(n2834), .B(n2833), .CI(n2832), .CO(n3116), .S(n2837) );
ADDFHX2TS U4139 ( .A(n2840), .B(n2839), .CI(n2838), .CO(n7336), .S(n3325) );
NOR2X2TS U4140 ( .A(n7337), .B(n7336), .Y(n3326) );
NOR2X2TS U4141 ( .A(n7332), .B(n3326), .Y(n3328) );
ADDFHX2TS U4142 ( .A(n2852), .B(n2851), .CI(n2850), .CO(n2842), .S(n2856) );
NAND2X2TS U4143 ( .A(n3328), .B(n7350), .Y(n7343) );
XNOR2X1TS U4144 ( .A(n2859), .B(n4082), .Y(n2898) );
OAI22X1TS U4145 ( .A0(n5294), .A1(n2860), .B0(n4702), .B1(n2898), .Y(n3103)
);
BUFX3TS U4146 ( .A(n6485), .Y(n5085) );
INVX2TS U4147 ( .A(n7044), .Y(n4069) );
XNOR2X1TS U4148 ( .A(n6995), .B(n3046), .Y(n2863) );
XNOR2X1TS U4149 ( .A(n6890), .B(n3048), .Y(n2872) );
OAI22X1TS U4150 ( .A0(n5085), .A1(n2863), .B0(n5622), .B1(n2872), .Y(n2870)
);
BUFX3TS U4151 ( .A(n7045), .Y(n4378) );
OAI22X1TS U4152 ( .A0(n5085), .A1(n7044), .B0(n4378), .B1(n2865), .Y(n2869)
);
ADDHX1TS U4153 ( .A(n2870), .B(n2869), .CO(n2888), .S(n3102) );
XNOR2X4TS U4154 ( .A(Data_A_i[52]), .B(Data_A_i[51]), .Y(n3047) );
NOR2BX1TS U4155 ( .AN(n2871), .B(n3047), .Y(n2891) );
XNOR2X1TS U4156 ( .A(n4100), .B(n4071), .Y(n2874) );
XNOR2X1TS U4157 ( .A(n4100), .B(n3988), .Y(n3032) );
XNOR2X1TS U4158 ( .A(n6890), .B(n3241), .Y(n3076) );
OAI22X1TS U4159 ( .A0(n5085), .A1(n2872), .B0(n4378), .B1(n3076), .Y(n2889)
);
XNOR2X1TS U4160 ( .A(n3220), .B(n5890), .Y(n2893) );
OAI22X1TS U4161 ( .A0(n67), .A1(n2873), .B0(n141), .B1(n2893), .Y(n2990) );
OAI22X1TS U4162 ( .A0(n4610), .A1(n2875), .B0(n5454), .B1(n2874), .Y(n2989)
);
XNOR2X1TS U4163 ( .A(Data_A_i[47]), .B(n4068), .Y(n2905) );
OAI22X1TS U4164 ( .A0(n4582), .A1(n2876), .B0(n6399), .B1(n2905), .Y(n2988)
);
XNOR2X1TS U4165 ( .A(n3209), .B(n6248), .Y(n2903) );
OAI22X1TS U4166 ( .A0(n2904), .A1(n2880), .B0(n45), .B1(n2903), .Y(n3005) );
XNOR2X1TS U4167 ( .A(n106), .B(n3068), .Y(n3010) );
OAI22X1TS U4168 ( .A0(n6065), .A1(n2881), .B0(n5390), .B1(n3010), .Y(n3004)
);
XNOR2X1TS U4169 ( .A(n3616), .B(n5911), .Y(n2894) );
OAI22X1TS U4170 ( .A0(n69), .A1(n2882), .B0(n4743), .B1(n2894), .Y(n3003) );
XNOR2X1TS U4171 ( .A(Data_A_i[13]), .B(n5143), .Y(n2918) );
XNOR2X1TS U4172 ( .A(n4136), .B(n5180), .Y(n3028) );
OAI22X1TS U4173 ( .A0(n2464), .A1(n2918), .B0(n85), .B1(n3028), .Y(n2976) );
XNOR2X1TS U4174 ( .A(n3220), .B(n5844), .Y(n3039) );
OAI22X1TS U4175 ( .A0(n5586), .A1(n2893), .B0(n5585), .B1(n3039), .Y(n2975)
);
XNOR2X1TS U4176 ( .A(n132), .B(Data_B_i[32]), .Y(n3041) );
OAI22X1TS U4177 ( .A0(n69), .A1(n2894), .B0(n4743), .B1(n3041), .Y(n2974) );
XNOR2X1TS U4178 ( .A(n115), .B(n3704), .Y(n2982) );
BUFX3TS U4179 ( .A(n2895), .Y(n4740) );
XNOR2X1TS U4180 ( .A(n5520), .B(n5890), .Y(n3222) );
OAI22X1TS U4181 ( .A0(n56), .A1(n2982), .B0(n4740), .B1(n3222), .Y(n3199) );
XNOR2X1TS U4182 ( .A(n6012), .B(n2896), .Y(n3009) );
XNOR2X1TS U4183 ( .A(n5449), .B(n4110), .Y(n3239) );
OAI22X1TS U4184 ( .A0(n5451), .A1(n3009), .B0(n5390), .B1(n3239), .Y(n3198)
);
XNOR2X1TS U4185 ( .A(n4087), .B(n6033), .Y(n2899) );
XNOR2X1TS U4186 ( .A(n4087), .B(n6248), .Y(n3223) );
OAI22X1TS U4187 ( .A0(n5294), .A1(n2899), .B0(n4702), .B1(n3223), .Y(n3197)
);
INVX2TS U4188 ( .A(Data_B_i[37]), .Y(n6378) );
INVX2TS U4189 ( .A(n6378), .Y(n5579) );
XNOR2X1TS U4190 ( .A(n2897), .B(n5579), .Y(n2914) );
INVX2TS U4191 ( .A(n6465), .Y(n5811) );
XNOR2X1TS U4192 ( .A(n94), .B(n5811), .Y(n3059) );
OAI22X1TS U4193 ( .A0(n103), .A1(n2914), .B0(n1379), .B1(n3059), .Y(n2973)
);
INVX2TS U4194 ( .A(n149), .Y(n2901) );
INVX2TS U4195 ( .A(n2902), .Y(n2972) );
XNOR2X1TS U4196 ( .A(n3209), .B(n5547), .Y(n3056) );
OAI22X1TS U4197 ( .A0(n2904), .A1(n2903), .B0(n51), .B1(n3056), .Y(n2971) );
INVX2TS U4198 ( .A(n4582), .Y(n2907) );
XNOR2X1TS U4199 ( .A(Data_A_i[47]), .B(n4035), .Y(n3025) );
AOI2BB2X1TS U4200 ( .B0(n2907), .B1(n2906), .A0N(n6487), .A1N(n3025), .Y(
n2908) );
INVX2TS U4201 ( .A(n2908), .Y(n3015) );
XNOR2X1TS U4202 ( .A(n3908), .B(n4110), .Y(n2960) );
XNOR2X1TS U4203 ( .A(n3908), .B(n4032), .Y(n2909) );
OAI22X1TS U4204 ( .A0(n5251), .A1(n2960), .B0(n5226), .B1(n2909), .Y(n3014)
);
XNOR2X1TS U4205 ( .A(n4097), .B(n5718), .Y(n2962) );
XNOR2X1TS U4206 ( .A(n4097), .B(n5839), .Y(n2910) );
OAI22X1TS U4207 ( .A0(n144), .A1(n2962), .B0(n7), .B1(n2910), .Y(n3013) );
XNOR2X1TS U4208 ( .A(n3908), .B(n4066), .Y(n3200) );
OAI22X1TS U4209 ( .A0(n5251), .A1(n2909), .B0(n5226), .B1(n3200), .Y(n3196)
);
XNOR2X1TS U4210 ( .A(n2511), .B(n5961), .Y(n2941) );
XNOR2X1TS U4211 ( .A(n117), .B(n6007), .Y(n3277) );
OAI22X1TS U4212 ( .A0(n4614), .A1(n2941), .B0(n4612), .B1(n3277), .Y(n3195)
);
XNOR2X1TS U4213 ( .A(n4097), .B(n5881), .Y(n3201) );
OAI22X1TS U4214 ( .A0(n143), .A1(n2910), .B0(n88), .B1(n3201), .Y(n3194) );
OAI22X1TS U4215 ( .A0(n103), .A1(n2915), .B0(n4091), .B1(n2914), .Y(n2970)
);
INVX2TS U4216 ( .A(n5142), .Y(n4396) );
XNOR2X1TS U4217 ( .A(n6238), .B(n4396), .Y(n2981) );
OAI22X1TS U4218 ( .A0(n4599), .A1(n2916), .B0(n6308), .B1(n2981), .Y(n2969)
);
XNOR2X1TS U4219 ( .A(n114), .B(n3781), .Y(n2937) );
OAI22X1TS U4220 ( .A0(n120), .A1(n2917), .B0(n59), .B1(n2937), .Y(n2968) );
OAI22X1TS U4221 ( .A0(n40), .A1(n2919), .B0(n83), .B1(n2918), .Y(n2979) );
XNOR2X1TS U4222 ( .A(n5187), .B(n4112), .Y(n2939) );
OAI22X1TS U4223 ( .A0(n6148), .A1(n2920), .B0(n5580), .B1(n2939), .Y(n2978)
);
XNOR2X1TS U4224 ( .A(n6343), .B(n4250), .Y(n2987) );
OAI22X1TS U4225 ( .A0(n6381), .A1(n2921), .B0(n137), .B1(n2987), .Y(n2977)
);
XNOR2X1TS U4226 ( .A(n1660), .B(n4066), .Y(n2940) );
XNOR2X1TS U4227 ( .A(n3042), .B(n6007), .Y(n2943) );
OAI22X1TS U4228 ( .A0(n99), .A1(n2926), .B0(n2943), .B1(n3273), .Y(n3007) );
XNOR2X1TS U4229 ( .A(n3926), .B(n4099), .Y(n3012) );
OAI22X1TS U4230 ( .A0(n6511), .A1(n2927), .B0(n6044), .B1(n3012), .Y(n3006)
);
XNOR2X1TS U4231 ( .A(n5520), .B(n3073), .Y(n2983) );
OAI22X1TS U4232 ( .A0(n4390), .A1(n2929), .B0(n2928), .B1(n2983), .Y(n2999)
);
XNOR2X1TS U4233 ( .A(n3249), .B(n4080), .Y(n2938) );
OAI22X1TS U4234 ( .A0(n128), .A1(n2930), .B0(n4400), .B1(n2938), .Y(n2998)
);
XNOR2X1TS U4235 ( .A(n36), .B(n5881), .Y(n2942) );
OAI22X1TS U4236 ( .A0(n4614), .A1(n2931), .B0(n4612), .B1(n2942), .Y(n2997)
);
XNOR2X1TS U4237 ( .A(n6336), .B(n4131), .Y(n2986) );
OAI22X1TS U4238 ( .A0(n4691), .A1(n2932), .B0(n5432), .B1(n2986), .Y(n2959)
);
XNOR2X1TS U4239 ( .A(n2343), .B(n5465), .Y(n2985) );
OAI22X1TS U4240 ( .A0(n3072), .A1(n2933), .B0(n2984), .B1(n2985), .Y(n2958)
);
XNOR2X1TS U4241 ( .A(n4133), .B(n5278), .Y(n2980) );
OAI22X1TS U4242 ( .A0(n3356), .A1(n2934), .B0(n112), .B1(n2980), .Y(n2957)
);
XNOR2X1TS U4243 ( .A(n6066), .B(n2936), .Y(n3069) );
OAI22X1TS U4244 ( .A0(n120), .A1(n2937), .B0(n5144), .B1(n3069), .Y(n3038)
);
XNOR2X1TS U4245 ( .A(n5427), .B(n4043), .Y(n3060) );
OAI22X1TS U4246 ( .A0(n128), .A1(n2938), .B0(n4400), .B1(n3060), .Y(n3037)
);
INVX2TS U4247 ( .A(n6588), .Y(n6519) );
XNOR2X1TS U4248 ( .A(n6519), .B(n3925), .Y(n3057) );
OAI22X1TS U4249 ( .A0(n5549), .A1(n2939), .B0(n4686), .B1(n3057), .Y(n3036)
);
XNOR2X1TS U4250 ( .A(n98), .B(n4338), .Y(n3075) );
OAI22X1TS U4251 ( .A0(n4575), .A1(n2940), .B0(n4518), .B1(n3075), .Y(n3062)
);
OAI22X1TS U4252 ( .A0(n4614), .A1(n2942), .B0(n4612), .B1(n2941), .Y(n3063)
);
XNOR2X1TS U4253 ( .A(Data_A_i[1]), .B(Data_B_i[52]), .Y(n3043) );
OAI22X1TS U4254 ( .A0(n99), .A1(n2943), .B0(n3043), .B1(n3273), .Y(n3064) );
CMPR32X2TS U4255 ( .A(n2956), .B(n2955), .C(n2954), .CO(n3091), .S(n3140) );
OAI22X1TS U4256 ( .A0(n143), .A1(n2963), .B0(n88), .B1(n2962), .Y(n3001) );
XNOR2X1TS U4257 ( .A(n2965), .B(n5619), .Y(n3011) );
OAI22X1TS U4258 ( .A0(n110), .A1(n2966), .B0(n4714), .B1(n3011), .Y(n3000)
);
XNOR2X1TS U4259 ( .A(n4133), .B(n5383), .Y(n3031) );
OAI22X1TS U4260 ( .A0(n4135), .A1(n2980), .B0(n3251), .B1(n3031), .Y(n3055)
);
XNOR2X1TS U4261 ( .A(n6238), .B(n4487), .Y(n3027) );
OAI22X1TS U4262 ( .A0(n4390), .A1(n2983), .B0(n4740), .B1(n2982), .Y(n3053)
);
XNOR2X1TS U4263 ( .A(n2343), .B(n5525), .Y(n3071) );
OAI22X1TS U4264 ( .A0(n3072), .A1(n2985), .B0(n2984), .B1(n3071), .Y(n3024)
);
XNOR2X1TS U4265 ( .A(n5529), .B(n4007), .Y(n3058) );
OAI22X1TS U4266 ( .A0(n5817), .A1(n2986), .B0(n3357), .B1(n3058), .Y(n3023)
);
XNOR2X1TS U4267 ( .A(n6343), .B(n4312), .Y(n3030) );
OAI22X1TS U4268 ( .A0(n5217), .A1(n2987), .B0(n136), .B1(n3030), .Y(n3022)
);
OAI22X1TS U4269 ( .A0(n5451), .A1(n3010), .B0(n5390), .B1(n3009), .Y(n3035)
);
XNOR2X1TS U4270 ( .A(n4078), .B(n5697), .Y(n3070) );
OAI22X1TS U4271 ( .A0(n4716), .A1(n3011), .B0(n4714), .B1(n3070), .Y(n3034)
);
INVX2TS U4272 ( .A(n6705), .Y(n5627) );
XNOR2X1TS U4273 ( .A(n5627), .B(n4000), .Y(n3061) );
OAI22X1TS U4274 ( .A0(n6511), .A1(n3012), .B0(n6044), .B1(n3061), .Y(n3033)
);
INVX2TS U4275 ( .A(n6768), .Y(n6030) );
XNOR2X1TS U4276 ( .A(n6030), .B(n4099), .Y(n3238) );
OAI22X1TS U4277 ( .A0(n4582), .A1(n3025), .B0(n6487), .B1(n3238), .Y(n3243)
);
XNOR2X1TS U4278 ( .A(n6238), .B(n5114), .Y(n3212) );
XNOR2X1TS U4279 ( .A(n4136), .B(n5278), .Y(n3253) );
XOR2X1TS U4280 ( .A(n3244), .B(n3245), .Y(n3029) );
XNOR2X1TS U4281 ( .A(n6343), .B(n4396), .Y(n3211) );
OAI22X1TS U4282 ( .A0(n6392), .A1(n3030), .B0(n136), .B1(n3211), .Y(n3268)
);
XNOR2X1TS U4283 ( .A(n4133), .B(n5465), .Y(n3252) );
OAI22X1TS U4284 ( .A0(n4571), .A1(n3031), .B0(n3251), .B1(n3252), .Y(n3267)
);
XNOR2X1TS U4285 ( .A(n4100), .B(n4068), .Y(n3202) );
OAI22X1TS U4286 ( .A0(n4610), .A1(n3032), .B0(n5454), .B1(n3202), .Y(n3266)
);
XNOR2X1TS U4287 ( .A(n3220), .B(n5911), .Y(n3221) );
OAI22X1TS U4288 ( .A0(n8), .A1(n3039), .B0(n140), .B1(n3221), .Y(n3226) );
XNOR2X1TS U4289 ( .A(n3616), .B(n4082), .Y(n3269) );
OAI22X1TS U4290 ( .A0(n71), .A1(n3041), .B0(n4743), .B1(n3269), .Y(n3225) );
OAI22X1TS U4291 ( .A0(n99), .A1(n3043), .B0(n3274), .B1(n3273), .Y(n3271) );
BUFX3TS U4292 ( .A(n6586), .Y(n7049) );
XNOR2X1TS U4293 ( .A(n7049), .B(n3046), .Y(n3049) );
XNOR2X1TS U4294 ( .A(n3209), .B(n5579), .Y(n3210) );
XNOR2X1TS U4295 ( .A(n6519), .B(n4131), .Y(n3215) );
XNOR2X1TS U4296 ( .A(n119), .B(n4250), .Y(n3216) );
OAI22X1TS U4297 ( .A0(n5942), .A1(n3058), .B0(n139), .B1(n3216), .Y(n3217)
);
INVX2TS U4298 ( .A(n6509), .Y(n5750) );
XNOR2X1TS U4299 ( .A(n94), .B(n5750), .Y(n3214) );
OAI22X1TS U4300 ( .A0(n103), .A1(n3059), .B0(n1379), .B1(n3214), .Y(n3208)
);
XNOR2X1TS U4301 ( .A(n5427), .B(n4112), .Y(n3250) );
OAI22X1TS U4302 ( .A0(n128), .A1(n3060), .B0(n5758), .B1(n3250), .Y(n3207)
);
XNOR2X1TS U4303 ( .A(n3926), .B(n4080), .Y(n3256) );
OAI22X1TS U4304 ( .A0(n6511), .A1(n3061), .B0(n6683), .B1(n3256), .Y(n3206)
);
XNOR2X1TS U4305 ( .A(n1860), .B(n3068), .Y(n3254) );
OAI22X1TS U4306 ( .A0(n121), .A1(n3069), .B0(n4420), .B1(n3254), .Y(n3265)
);
XNOR2X1TS U4307 ( .A(n4078), .B(n5718), .Y(n3237) );
OAI22X1TS U4308 ( .A0(n735), .A1(n3070), .B0(n4714), .B1(n3237), .Y(n3264)
);
BUFX3TS U4309 ( .A(n199), .Y(n4562) );
XNOR2X1TS U4310 ( .A(Data_A_i[9]), .B(n5619), .Y(n3255) );
OAI22X1TS U4311 ( .A0(n3072), .A1(n3071), .B0(n4562), .B1(n3255), .Y(n3263)
);
XNOR2X1TS U4312 ( .A(n4076), .B(n3073), .Y(n3236) );
XNOR2X1TS U4313 ( .A(n6015), .B(n4071), .Y(n3240) );
INVX2TS U4314 ( .A(Data_A_i[53]), .Y(n7092) );
BUFX3TS U4315 ( .A(n6655), .Y(n5115) );
OAI22X1TS U4316 ( .A0(n7093), .A1(n7092), .B0(n5115), .B1(n3079), .Y(n3233)
);
ADDFHX2TS U4317 ( .A(n3109), .B(n3108), .CI(n3107), .CO(n3113), .S(n3117) );
ADDFHX2TS U4318 ( .A(n3169), .B(n3168), .CI(n3167), .CO(n3179), .S(n3183) );
ADDFHX2TS U4319 ( .A(n3187), .B(n3186), .CI(n3185), .CO(n4893), .S(n3291) );
XNOR2X1TS U4320 ( .A(n4094), .B(n3985), .Y(n4747) );
OAI22X1TS U4321 ( .A0(n5251), .A1(n3200), .B0(n5226), .B1(n4747), .Y(n4786)
);
XNOR2X1TS U4322 ( .A(n4097), .B(n5961), .Y(n4578) );
XNOR2X1TS U4323 ( .A(n4100), .B(n4035), .Y(n4609) );
OAI22X1TS U4324 ( .A0(n4610), .A1(n3202), .B0(n5454), .B1(n4609), .Y(n4784)
);
XNOR2X1TS U4325 ( .A(n3209), .B(n5811), .Y(n4738) );
XNOR2X1TS U4326 ( .A(n6343), .B(n4487), .Y(n4597) );
BUFX3TS U4327 ( .A(n5714), .Y(n5659) );
INVX2TS U4328 ( .A(n6368), .Y(n5715) );
XNOR2X1TS U4329 ( .A(n5715), .B(n5190), .Y(n4598) );
OAI22X1TS U4330 ( .A0(n4599), .A1(n3212), .B0(n5659), .B1(n4598), .Y(n4734)
);
INVX2TS U4331 ( .A(n6518), .Y(n5496) );
XNOR2X1TS U4332 ( .A(n4247), .B(n5496), .Y(n4594) );
OAI22X1TS U4333 ( .A0(n102), .A1(n3214), .B0(n3213), .B1(n4594), .Y(n4759)
);
XNOR2X1TS U4334 ( .A(n6519), .B(n4007), .Y(n4687) );
OAI22X1TS U4335 ( .A0(n6148), .A1(n3215), .B0(n4686), .B1(n4687), .Y(n4758)
);
XNOR2X1TS U4336 ( .A(n119), .B(n4312), .Y(n4690) );
OAI22X1TS U4337 ( .A0(n5942), .A1(n3216), .B0(n139), .B1(n4690), .Y(n4757)
);
XNOR2X1TS U4338 ( .A(n3220), .B(n76), .Y(n4124) );
XNOR2X1TS U4339 ( .A(n115), .B(n5844), .Y(n4741) );
XNOR2X1TS U4340 ( .A(n4087), .B(n5547), .Y(n4703) );
OAI22X1TS U4341 ( .A0(n148), .A1(n3223), .B0(n5293), .B1(n4703), .Y(n4754)
);
XNOR2X1TS U4342 ( .A(n4076), .B(n3704), .Y(n4574) );
XNOR2X1TS U4343 ( .A(n4078), .B(n5839), .Y(n4715) );
XNOR2X1TS U4344 ( .A(n6030), .B(n4000), .Y(n4581) );
OAI22X1TS U4345 ( .A0(n4582), .A1(n3238), .B0(n6769), .B1(n4581), .Y(n4751)
);
XNOR2X1TS U4346 ( .A(n5449), .B(n4032), .Y(n4607) );
OAI22X1TS U4347 ( .A0(n5451), .A1(n3239), .B0(n5390), .B1(n4607), .Y(n4677)
);
XNOR2X1TS U4348 ( .A(n4069), .B(n3988), .Y(n4121) );
OAI22X1TS U4349 ( .A0(n4122), .A1(n3240), .B0(n5622), .B1(n4121), .Y(n4676)
);
XNOR2X1TS U4350 ( .A(n5815), .B(n3241), .Y(n4749) );
OAI22X1TS U4351 ( .A0(n5291), .A1(n3242), .B0(n5115), .B1(n4749), .Y(n4675)
);
NAND2X1TS U4352 ( .A(n3245), .B(n3243), .Y(n3248) );
NAND2X1TS U4353 ( .A(n3244), .B(n3243), .Y(n3247) );
NAND2X1TS U4354 ( .A(n3245), .B(n3244), .Y(n3246) );
XNOR2X1TS U4355 ( .A(n3249), .B(n3925), .Y(n4567) );
OAI22X1TS U4356 ( .A0(n128), .A1(n3250), .B0(n4566), .B1(n4567), .Y(n4560)
);
XNOR2X1TS U4357 ( .A(n3927), .B(n5525), .Y(n4570) );
XNOR2X1TS U4358 ( .A(n4136), .B(n5383), .Y(n4683) );
OAI22X1TS U4359 ( .A0(n41), .A1(n3253), .B0(n84), .B1(n4683), .Y(n4558) );
XNOR2X1TS U4360 ( .A(n1860), .B(Data_B_i[22]), .Y(n4712) );
OAI22X1TS U4361 ( .A0(n4337), .A1(n3254), .B0(n4420), .B1(n4712), .Y(n4697)
);
XNOR2X1TS U4362 ( .A(n4108), .B(n5697), .Y(n4563) );
XNOR2X1TS U4363 ( .A(n5627), .B(n4043), .Y(n4718) );
OAI22X1TS U4364 ( .A0(n6511), .A1(n3256), .B0(n6044), .B1(n4718), .Y(n4695)
);
CMPR32X2TS U4365 ( .A(n3268), .B(n3267), .C(n3266), .CO(n4800), .S(n3257) );
XNOR2X1TS U4366 ( .A(n133), .B(n6033), .Y(n4744) );
OAI22X1TS U4367 ( .A0(n69), .A1(n3269), .B0(n4743), .B1(n4744), .Y(n4700) );
NOR2BX1TS U4368 ( .AN(n3272), .B(n7092), .Y(n4707) );
OAI22X1TS U4369 ( .A0(n3275), .A1(n3274), .B0(n4760), .B1(n3273), .Y(n4706)
);
XNOR2X1TS U4370 ( .A(n117), .B(Data_B_i[52]), .Y(n4613) );
OAI22X1TS U4371 ( .A0(n4614), .A1(n3277), .B0(n4612), .B1(n4613), .Y(n4705)
);
ADDFHX2TS U4372 ( .A(n3298), .B(n3297), .CI(n3296), .CO(n4933), .S(n3299) );
ADDFHX2TS U4373 ( .A(n3319), .B(n3318), .CI(n3317), .CO(n3329), .S(n7337) );
NOR2X2TS U4374 ( .A(n3330), .B(n3329), .Y(n7323) );
NOR2X4TS U4375 ( .A(n7343), .B(n3340), .Y(n3342) );
OAI21X2TS U4376 ( .A0(n7633), .A1(n7318), .B0(n7319), .Y(n7351) );
NAND2X1TS U4377 ( .A(n7337), .B(n7336), .Y(n7339) );
OAI21X2TS U4378 ( .A0(n3326), .A1(n7354), .B0(n7339), .Y(n3327) );
AOI21X4TS U4379 ( .A0(n3328), .A1(n7351), .B0(n3327), .Y(n7178) );
NAND2X2TS U4380 ( .A(n3330), .B(n3329), .Y(n7344) );
NAND2X2TS U4381 ( .A(n3332), .B(n3331), .Y(n7328) );
NAND2X1TS U4382 ( .A(n3336), .B(n3335), .Y(n7185) );
AOI21X2TS U4383 ( .A0(n3338), .A1(n7377), .B0(n3337), .Y(n3339) );
OAI21X2TS U4384 ( .A0(n7178), .A1(n3340), .B0(n3339), .Y(n3341) );
AOI21X4TS U4385 ( .A0(n7176), .A1(n3342), .B0(n3341), .Y(n7387) );
XNOR2X1TS U4386 ( .A(n1660), .B(n5579), .Y(n3427) );
XNOR2X1TS U4387 ( .A(n1660), .B(n5811), .Y(n3629) );
OAI22X1TS U4388 ( .A0(n4322), .A1(n3427), .B0(n5893), .B1(n3629), .Y(n3626)
);
XNOR2X1TS U4389 ( .A(n6708), .B(n4396), .Y(n3344) );
XNOR2X1TS U4390 ( .A(n6708), .B(n4487), .Y(n3619) );
INVX2TS U4391 ( .A(n3343), .Y(n6642) );
XNOR2X1TS U4392 ( .A(n6642), .B(n5114), .Y(n3345) );
XNOR2X1TS U4393 ( .A(n6642), .B(n5190), .Y(n3351) );
OAI22X1TS U4394 ( .A0(n3735), .A1(n3345), .B0(n6044), .B1(n3351), .Y(n3624)
);
INVX2TS U4395 ( .A(n6682), .Y(n6055) );
XNOR2X1TS U4396 ( .A(Data_A_i[19]), .B(n6055), .Y(n3387) );
INVX2TS U4397 ( .A(n6711), .Y(n5940) );
XNOR2X1TS U4398 ( .A(Data_A_i[19]), .B(n5940), .Y(n3347) );
XNOR2X1TS U4399 ( .A(n6708), .B(n4312), .Y(n3367) );
OAI22X1TS U4400 ( .A0(n4225), .A1(n3367), .B0(n3933), .B1(n3344), .Y(n3369)
);
XNOR2X1TS U4401 ( .A(n6642), .B(n4487), .Y(n3386) );
OAI22X1TS U4402 ( .A0(n3735), .A1(n3386), .B0(n5884), .B1(n3345), .Y(n3368)
);
INVX2TS U4403 ( .A(n6540), .Y(n6336) );
INVX2TS U4404 ( .A(n5720), .Y(n5582) );
XNOR2X1TS U4405 ( .A(n5082), .B(n5582), .Y(n3556) );
XNOR2X1TS U4406 ( .A(n6336), .B(Data_B_i[26]), .Y(n3358) );
OAI22X1TS U4407 ( .A0(n6542), .A1(n3556), .B0(n6541), .B1(n3358), .Y(n3614)
);
BUFX3TS U4408 ( .A(n4479), .Y(n4375) );
INVX2TS U4409 ( .A(n5119), .Y(n3875) );
INVX2TS U4410 ( .A(n6760), .Y(n6347) );
XNOR2X1TS U4411 ( .A(n3875), .B(n6347), .Y(n3384) );
INVX2TS U4412 ( .A(n6886), .Y(n6193) );
XNOR2X1TS U4413 ( .A(n3875), .B(n6193), .Y(n3352) );
INVX2TS U4414 ( .A(n6731), .Y(n6026) );
XNOR2X1TS U4415 ( .A(n4480), .B(n6026), .Y(n3353) );
OAI22X1TS U4416 ( .A0(n5294), .A1(n3347), .B0(n5233), .B1(n3353), .Y(n3612)
);
XNOR2X1TS U4417 ( .A(n3873), .B(Data_B_i[29]), .Y(n3375) );
XNOR2X1TS U4418 ( .A(n3873), .B(Data_B_i[30]), .Y(n3354) );
OAI22X1TS U4419 ( .A0(n4536), .A1(n3375), .B0(n6308), .B1(n3354), .Y(n3364)
);
INVX2TS U4420 ( .A(n6994), .Y(n6232) );
XNOR2X1TS U4421 ( .A(n3847), .B(n6232), .Y(n3558) );
INVX2TS U4422 ( .A(n7015), .Y(n6290) );
XNOR2X1TS U4423 ( .A(n2705), .B(n6290), .Y(n3350) );
XNOR2X1TS U4424 ( .A(n6386), .B(n4112), .Y(n3360) );
XNOR2X1TS U4425 ( .A(n7049), .B(n3925), .Y(n3355) );
OAI22X1TS U4426 ( .A0(n5291), .A1(n3360), .B0(n5115), .B1(n3355), .Y(n3362)
);
INVX2TS U4427 ( .A(n5937), .Y(n5814) );
XNOR2X1TS U4428 ( .A(n4394), .B(n5814), .Y(n3533) );
XNOR2X1TS U4429 ( .A(n4394), .B(Data_B_i[29]), .Y(n3910) );
OAI22X1TS U4430 ( .A0(n6381), .A1(n3533), .B0(n5267), .B1(n3910), .Y(n3884)
);
XNOR2X1TS U4431 ( .A(n92), .B(Data_B_i[52]), .Y(n3526) );
XNOR2X1TS U4432 ( .A(n3349), .B(Data_B_i[53]), .Y(n3846) );
OAI22X1TS U4433 ( .A0(n4684), .A1(n3526), .B0(n84), .B1(n3846), .Y(n3883) );
INVX2TS U4434 ( .A(n7047), .Y(n6989) );
XNOR2X1TS U4435 ( .A(n4089), .B(n6989), .Y(n3848) );
OAI22X1TS U4436 ( .A0(n4277), .A1(n3350), .B0(n48), .B1(n3848), .Y(n3882) );
XNOR2X1TS U4437 ( .A(n6642), .B(n5289), .Y(n3881) );
OAI22X1TS U4438 ( .A0(n3735), .A1(n3351), .B0(n6044), .B1(n3881), .Y(n3840)
);
XNOR2X1TS U4439 ( .A(n3875), .B(n6232), .Y(n3876) );
OAI22X1TS U4440 ( .A0(n4375), .A1(n3352), .B0(n52), .B1(n3876), .Y(n3839) );
XNOR2X1TS U4441 ( .A(n4480), .B(n6347), .Y(n3886) );
OAI22X1TS U4442 ( .A0(n150), .A1(n3353), .B0(n5233), .B1(n3886), .Y(n3838)
);
INVX2TS U4443 ( .A(n6991), .Y(n6761) );
XNOR2X1TS U4444 ( .A(n6761), .B(n4250), .Y(n3383) );
XNOR2X1TS U4445 ( .A(n6761), .B(n4312), .Y(n3359) );
OAI22X1TS U4446 ( .A0(n4381), .A1(n3383), .B0(n4253), .B1(n3359), .Y(n3381)
);
INVX2TS U4447 ( .A(n6569), .Y(n5999) );
XNOR2X1TS U4448 ( .A(n4256), .B(n5999), .Y(n3424) );
INVX2TS U4449 ( .A(n6615), .Y(n5818) );
XNOR2X1TS U4450 ( .A(n4256), .B(n5818), .Y(n3621) );
XNOR2X1TS U4451 ( .A(n4388), .B(n5750), .Y(n3392) );
XNOR2X1TS U4452 ( .A(n116), .B(n5496), .Y(n3627) );
OAI22X1TS U4453 ( .A0(n56), .A1(n3392), .B0(n38), .B1(n3627), .Y(n3379) );
XNOR2X1TS U4454 ( .A(n3873), .B(Data_B_i[31]), .Y(n3874) );
OAI22X1TS U4455 ( .A0(n4536), .A1(n3354), .B0(n5659), .B1(n3874), .Y(n3872)
);
XNOR2X1TS U4456 ( .A(n7049), .B(n4131), .Y(n3912) );
OAI22X1TS U4457 ( .A0(n6530), .A1(n3355), .B0(n5115), .B1(n3912), .Y(n3871)
);
INVX2TS U4458 ( .A(n5863), .Y(n5752) );
XNOR2X1TS U4459 ( .A(n5082), .B(n5752), .Y(n3890) );
OAI22X1TS U4460 ( .A0(n6542), .A1(n3358), .B0(n6541), .B1(n3890), .Y(n3896)
);
INVX2TS U4461 ( .A(n7044), .Y(n6995) );
XNOR2X1TS U4462 ( .A(n6995), .B(n4007), .Y(n3366) );
XNOR2X1TS U4463 ( .A(n6995), .B(n4250), .Y(n3911) );
OAI22X1TS U4464 ( .A0(n5085), .A1(n3366), .B0(n4378), .B1(n3911), .Y(n3895)
);
XNOR2X1TS U4465 ( .A(n6761), .B(n4396), .Y(n3877) );
OAI22X1TS U4466 ( .A0(n4381), .A1(n3359), .B0(n4253), .B1(n3877), .Y(n3894)
);
XNOR2X1TS U4467 ( .A(n3741), .B(n3738), .Y(n3421) );
XNOR2X1TS U4468 ( .A(n114), .B(n3497), .Y(n3575) );
OAI22X1TS U4469 ( .A0(n6184), .A1(n3421), .B0(n6182), .B1(n3575), .Y(n3373)
);
XNOR2X1TS U4470 ( .A(n5815), .B(n4043), .Y(n3411) );
BUFX3TS U4471 ( .A(n6655), .Y(n6366) );
OAI22X1TS U4472 ( .A0(n7093), .A1(n3411), .B0(n6366), .B1(n3360), .Y(n3372)
);
CMPR32X2TS U4473 ( .A(n3364), .B(n3363), .C(n3362), .CO(n3893), .S(n3581) );
INVX2TS U4474 ( .A(n6588), .Y(n6146) );
INVX2TS U4475 ( .A(n5605), .Y(n5434) );
XNOR2X1TS U4476 ( .A(n6146), .B(n5434), .Y(n3378) );
INVX2TS U4477 ( .A(n5664), .Y(n5539) );
XNOR2X1TS U4478 ( .A(n6146), .B(n5539), .Y(n3622) );
OAI22X1TS U4479 ( .A0(n6590), .A1(n3378), .B0(n6056), .B1(n3622), .Y(n3588)
);
XNOR2X1TS U4480 ( .A(n3040), .B(n5864), .Y(n3376) );
XNOR2X1TS U4481 ( .A(n3040), .B(n6055), .Y(n3617) );
OAI22X1TS U4482 ( .A0(n3618), .A1(n3376), .B0(n125), .B1(n3617), .Y(n3587)
);
BUFX3TS U4483 ( .A(n6485), .Y(n6212) );
XNOR2X1TS U4484 ( .A(n6995), .B(n4131), .Y(n3560) );
OAI22X1TS U4485 ( .A0(n6212), .A1(n3560), .B0(n4378), .B1(n3366), .Y(n3586)
);
XNOR2X1TS U4486 ( .A(n5368), .B(n5750), .Y(n3461) );
XNOR2X1TS U4487 ( .A(n4256), .B(n5496), .Y(n3426) );
OAI22X1TS U4488 ( .A0(n5519), .A1(n3461), .B0(n140), .B1(n3426), .Y(n3434)
);
XNOR2X1TS U4489 ( .A(n6708), .B(n4250), .Y(n3449) );
OAI22X1TS U4490 ( .A0(n4225), .A1(n3449), .B0(n3933), .B1(n3367), .Y(n3433)
);
INVX2TS U4491 ( .A(n6658), .Y(n6580) );
XNOR2X1TS U4492 ( .A(n6580), .B(n5114), .Y(n3436) );
XNOR2X1TS U4493 ( .A(n6580), .B(n5190), .Y(n3377) );
OAI22X1TS U4494 ( .A0(n4009), .A1(n3436), .B0(n6195), .B1(n3377), .Y(n3432)
);
CMPR32X2TS U4495 ( .A(n3373), .B(n3372), .C(n3371), .CO(n3582), .S(n3441) );
XNOR2X1TS U4496 ( .A(Data_A_i[13]), .B(n5961), .Y(n3408) );
XNOR2X1TS U4497 ( .A(Data_A_i[13]), .B(n6007), .Y(n3527) );
OAI22X1TS U4498 ( .A0(n2464), .A1(n3408), .B0(n83), .B1(n3527), .Y(n3555) );
XNOR2X1TS U4499 ( .A(n3927), .B(Data_B_i[52]), .Y(n3396) );
XNOR2X1TS U4500 ( .A(n3374), .B(Data_B_i[53]), .Y(n3524) );
OAI22X1TS U4501 ( .A0(n4135), .A1(n3396), .B0(n112), .B1(n3524), .Y(n3554)
);
XNOR2X1TS U4502 ( .A(n3873), .B(n5814), .Y(n3409) );
OAI22X1TS U4503 ( .A0(n4536), .A1(n3409), .B0(n6308), .B1(n3375), .Y(n3553)
);
XNOR2X1TS U4504 ( .A(n3616), .B(n5818), .Y(n3389) );
XNOR2X1TS U4505 ( .A(n6580), .B(n5289), .Y(n3532) );
INVX2TS U4506 ( .A(n5516), .Y(n5335) );
XNOR2X1TS U4507 ( .A(n6146), .B(n5335), .Y(n3420) );
OAI22X1TS U4508 ( .A0(n5549), .A1(n3420), .B0(n6056), .B1(n3378), .Y(n3429)
);
CMPR32X2TS U4509 ( .A(n3381), .B(n3380), .C(n3379), .CO(n3834), .S(n3609) );
INVX2TS U4510 ( .A(n6390), .Y(n5887) );
XNOR2X1TS U4511 ( .A(n5887), .B(n5582), .Y(n3483) );
BUFX3TS U4512 ( .A(n5886), .Y(n5842) );
XNOR2X1TS U4513 ( .A(n4394), .B(Data_B_i[26]), .Y(n3382) );
OAI22X1TS U4514 ( .A0(n6392), .A1(n3483), .B0(n5842), .B1(n3382), .Y(n3440)
);
XNOR2X1TS U4515 ( .A(n4247), .B(n6347), .Y(n3482) );
XNOR2X1TS U4516 ( .A(n2705), .B(n6193), .Y(n3559) );
XNOR2X1TS U4517 ( .A(n3875), .B(n5940), .Y(n3459) );
XNOR2X1TS U4518 ( .A(n3875), .B(n6026), .Y(n3385) );
OAI22X1TS U4519 ( .A0(n4375), .A1(n3459), .B0(n52), .B1(n3385), .Y(n3438) );
XNOR2X1TS U4520 ( .A(n98), .B(n6248), .Y(n3401) );
XNOR2X1TS U4521 ( .A(n5101), .B(n5547), .Y(n3428) );
XNOR2X1TS U4522 ( .A(n6012), .B(n3497), .Y(n3471) );
XNOR2X1TS U4523 ( .A(n1814), .B(n76), .Y(n3423) );
XNOR2X1TS U4524 ( .A(n3908), .B(Data_B_i[33]), .Y(n3460) );
XNOR2X1TS U4525 ( .A(n3908), .B(n3878), .Y(n3395) );
OAI22X1TS U4526 ( .A0(n130), .A1(n3460), .B0(n4096), .B1(n3395), .Y(n3541)
);
XNOR2X1TS U4527 ( .A(n4394), .B(n5752), .Y(n3534) );
OAI22X1TS U4528 ( .A0(n6392), .A1(n3382), .B0(n136), .B1(n3534), .Y(n3570)
);
XNOR2X1TS U4529 ( .A(n6761), .B(n4007), .Y(n3391) );
OAI22X1TS U4530 ( .A0(n4381), .A1(n3391), .B0(n4253), .B1(n3383), .Y(n3569)
);
OAI22X1TS U4531 ( .A0(n4375), .A1(n3385), .B0(n52), .B1(n3384), .Y(n3568) );
XNOR2X1TS U4532 ( .A(n6642), .B(n4396), .Y(n3437) );
OAI22X1TS U4533 ( .A0(n3735), .A1(n3437), .B0(n6683), .B1(n3386), .Y(n3415)
);
XNOR2X1TS U4534 ( .A(n4087), .B(n5864), .Y(n3450) );
OAI22X1TS U4535 ( .A0(n149), .A1(n3450), .B0(n3503), .B1(n3387), .Y(n3414)
);
XNOR2X1TS U4536 ( .A(n3040), .B(n5999), .Y(n3451) );
OAI22X1TS U4537 ( .A0(n5373), .A1(n3451), .B0(n125), .B1(n3389), .Y(n3413)
);
XNOR2X1TS U4538 ( .A(n6376), .B(n5434), .Y(n3447) );
XNOR2X1TS U4539 ( .A(n6336), .B(n5539), .Y(n3557) );
OAI22X1TS U4540 ( .A0(n4691), .A1(n3447), .B0(n138), .B1(n3557), .Y(n3486)
);
INVX2TS U4541 ( .A(n7044), .Y(n6015) );
XNOR2X1TS U4542 ( .A(n6890), .B(n4112), .Y(n3407) );
XNOR2X1TS U4543 ( .A(n4069), .B(n3925), .Y(n3561) );
OAI22X1TS U4544 ( .A0(n4122), .A1(n3407), .B0(n4378), .B1(n3561), .Y(n3485)
);
XNOR2X1TS U4545 ( .A(n6761), .B(n4131), .Y(n3448) );
OAI22X1TS U4546 ( .A0(n123), .A1(n3448), .B0(n4253), .B1(n3391), .Y(n3484)
);
XNOR2X1TS U4547 ( .A(n4085), .B(n5811), .Y(n3419) );
OAI22X1TS U4548 ( .A0(n56), .A1(n3419), .B0(n4740), .B1(n3392), .Y(n3521) );
NOR2X1TS U4549 ( .A(n6062), .B(n3393), .Y(n3578) );
NOR2X1TS U4550 ( .A(n6062), .B(n3394), .Y(n3577) );
XNOR2X1TS U4551 ( .A(n3908), .B(n4201), .Y(n3531) );
OAI22X1TS U4552 ( .A0(n131), .A1(n3395), .B0(n4096), .B1(n3531), .Y(n3576)
);
INVX2TS U4553 ( .A(n3578), .Y(n3404) );
XNOR2X1TS U4554 ( .A(n3927), .B(n6007), .Y(n3472) );
XNOR2X1TS U4555 ( .A(n3397), .B(Data_B_i[53]), .Y(n3406) );
OAI22X1TS U4556 ( .A0(n105), .A1(n3406), .B0(n4562), .B1(n3398), .Y(n3402)
);
NOR2X1TS U4557 ( .A(n6062), .B(n3399), .Y(n3454) );
XNOR2X1TS U4558 ( .A(n5101), .B(n6033), .Y(n3636) );
OAI22X1TS U4559 ( .A0(n39), .A1(n3636), .B0(n4573), .B1(n3401), .Y(n3452) );
XNOR2X1TS U4560 ( .A(n3741), .B(Data_B_i[28]), .Y(n3457) );
XNOR2X1TS U4561 ( .A(n6066), .B(n3930), .Y(n3422) );
OAI22X1TS U4562 ( .A0(n121), .A1(n3457), .B0(n6251), .B1(n3422), .Y(n3641)
);
XNOR2X1TS U4563 ( .A(n5815), .B(n4000), .Y(n3470) );
XNOR2X1TS U4564 ( .A(n5815), .B(n4080), .Y(n3412) );
OAI22X1TS U4565 ( .A0(n13), .A1(n3470), .B0(n5753), .B1(n3412), .Y(n3640) );
XNOR2X1TS U4566 ( .A(n3873), .B(n4338), .Y(n3468) );
XNOR2X1TS U4567 ( .A(n3873), .B(n5752), .Y(n3410) );
OAI22X1TS U4568 ( .A0(n5717), .A1(n3468), .B0(n3405), .B1(n3410), .Y(n3477)
);
XNOR2X1TS U4569 ( .A(n4108), .B(Data_B_i[52]), .Y(n3456) );
OAI22X1TS U4570 ( .A0(n104), .A1(n3456), .B0(n4562), .B1(n3406), .Y(n3476)
);
XNOR2X1TS U4571 ( .A(n6015), .B(n4043), .Y(n3469) );
OAI22X1TS U4572 ( .A0(n4122), .A1(n3469), .B0(n6234), .B1(n3407), .Y(n3475)
);
XNOR2X1TS U4573 ( .A(n92), .B(n5881), .Y(n3473) );
OAI22X1TS U4574 ( .A0(n4750), .A1(n3412), .B0(n5753), .B1(n3411), .Y(n3550)
);
CMPR32X2TS U4575 ( .A(n3415), .B(n3414), .C(n3413), .CO(n3464), .S(n3513) );
XNOR2X1TS U4576 ( .A(n4388), .B(n5579), .Y(n3435) );
OAI22X1TS U4577 ( .A0(n55), .A1(n3435), .B0(n108), .B1(n3419), .Y(n3546) );
XNOR2X1TS U4578 ( .A(n6519), .B(n5289), .Y(n3481) );
OAI22X1TS U4579 ( .A0(n6590), .A1(n3481), .B0(n6056), .B1(n3420), .Y(n3545)
);
OAI22X1TS U4580 ( .A0(n121), .A1(n3422), .B0(n6251), .B1(n3421), .Y(n3544)
);
XNOR2X1TS U4581 ( .A(n6012), .B(Data_B_i[33]), .Y(n3574) );
OAI22X1TS U4582 ( .A0(n145), .A1(n3423), .B0(n91), .B1(n3574), .Y(n3530) );
OAI22X1TS U4583 ( .A0(n5586), .A1(n3426), .B0(n3425), .B1(n3424), .Y(n3529)
);
OAI22X1TS U4584 ( .A0(n5798), .A1(n3428), .B0(n4573), .B1(n3427), .Y(n3528)
);
XNOR2X1TS U4585 ( .A(n1468), .B(n5547), .Y(n3458) );
OAI22X1TS U4586 ( .A0(n55), .A1(n3458), .B0(n4740), .B1(n3435), .Y(n3512) );
XNOR2X1TS U4587 ( .A(n6580), .B(n4487), .Y(n3499) );
XNOR2X1TS U4588 ( .A(n6642), .B(n4312), .Y(n3496) );
OAI22X1TS U4589 ( .A0(n3735), .A1(n3496), .B0(n5884), .B1(n3437), .Y(n3510)
);
XNOR2X1TS U4590 ( .A(n5082), .B(n5335), .Y(n3505) );
OAI22X1TS U4591 ( .A0(n5942), .A1(n3505), .B0(n6541), .B1(n3447), .Y(n3635)
);
XNOR2X1TS U4592 ( .A(n4100), .B(n3925), .Y(n3494) );
OAI22X1TS U4593 ( .A0(n4610), .A1(n3494), .B0(n4253), .B1(n3448), .Y(n3634)
);
XNOR2X1TS U4594 ( .A(n6708), .B(n4007), .Y(n3495) );
OAI22X1TS U4595 ( .A0(n4225), .A1(n3495), .B0(n3933), .B1(n3449), .Y(n3633)
);
XNOR2X1TS U4596 ( .A(n4480), .B(n5818), .Y(n3502) );
OAI22X1TS U4597 ( .A0(n150), .A1(n3502), .B0(n3503), .B1(n3450), .Y(n3660)
);
XNOR2X1TS U4598 ( .A(n3040), .B(n5496), .Y(n3501) );
OAI22X1TS U4599 ( .A0(n3760), .A1(n3501), .B0(n5437), .B1(n3451), .Y(n3659)
);
CMPR32X2TS U4600 ( .A(n3454), .B(n3453), .C(n3452), .CO(n3467), .S(n3658) );
XNOR2X1TS U4601 ( .A(n4078), .B(Data_B_i[53]), .Y(n3743) );
XNOR2X1TS U4602 ( .A(n4108), .B(n6007), .Y(n3740) );
OAI22X1TS U4603 ( .A0(n105), .A1(n3740), .B0(n4562), .B1(n3456), .Y(n3655)
);
XNOR2X1TS U4604 ( .A(Data_A_i[13]), .B(n5718), .Y(n3730) );
XNOR2X1TS U4605 ( .A(Data_A_i[13]), .B(n5839), .Y(n3474) );
OAI22X1TS U4606 ( .A0(n2464), .A1(n3730), .B0(n84), .B1(n3474), .Y(n3709) );
XNOR2X1TS U4607 ( .A(n1860), .B(Data_B_i[27]), .Y(n3742) );
OAI22X1TS U4608 ( .A0(n4390), .A1(n3686), .B0(n38), .B1(n3458), .Y(n3707) );
XNOR2X1TS U4609 ( .A(n3875), .B(n6055), .Y(n3651) );
OAI22X1TS U4610 ( .A0(n3723), .A1(n3651), .B0(n52), .B1(n3459), .Y(n3540) );
XNOR2X1TS U4611 ( .A(n4094), .B(n76), .Y(n3498) );
OAI22X1TS U4612 ( .A0(n5945), .A1(n3498), .B0(n4096), .B1(n3460), .Y(n3539)
);
XNOR2X1TS U4613 ( .A(Data_A_i[23]), .B(n5811), .Y(n3504) );
OAI22X1TS U4614 ( .A0(n4084), .A1(n3504), .B0(n5585), .B1(n3461), .Y(n3538)
);
XNOR2X1TS U4615 ( .A(n5715), .B(n5582), .Y(n3729) );
OAI22X1TS U4616 ( .A0(n5717), .A1(n3729), .B0(n6308), .B1(n3468), .Y(n3728)
);
XNOR2X1TS U4617 ( .A(n6015), .B(n4080), .Y(n3684) );
OAI22X1TS U4618 ( .A0(n4122), .A1(n3684), .B0(n5622), .B1(n3469), .Y(n3727)
);
XNOR2X1TS U4619 ( .A(n5815), .B(n4099), .Y(n3706) );
OAI22X1TS U4620 ( .A0(n4750), .A1(n3706), .B0(n5753), .B1(n3470), .Y(n3726)
);
XNOR2X1TS U4621 ( .A(n5449), .B(n3738), .Y(n3493) );
OAI22X1TS U4622 ( .A0(n5451), .A1(n3493), .B0(n6063), .B1(n3471), .Y(n3480)
);
XNOR2X1TS U4623 ( .A(n3927), .B(n5961), .Y(n3638) );
OAI22X1TS U4624 ( .A0(n4135), .A1(n3638), .B0(n111), .B1(n3472), .Y(n3479)
);
OAI22X1TS U4625 ( .A0(n41), .A1(n3474), .B0(n84), .B1(n3473), .Y(n3478) );
CMPR32X2TS U4626 ( .A(n3477), .B(n3476), .C(n3475), .CO(n3515), .S(n3716) );
XNOR2X1TS U4627 ( .A(n6146), .B(n5190), .Y(n3637) );
OAI22X1TS U4628 ( .A0(n6148), .A1(n3637), .B0(n6056), .B1(n3481), .Y(n3509)
);
XNOR2X1TS U4629 ( .A(n94), .B(n6026), .Y(n3500) );
OAI22X1TS U4630 ( .A0(n4277), .A1(n3500), .B0(n49), .B1(n3482), .Y(n3508) );
XNOR2X1TS U4631 ( .A(n5887), .B(n5539), .Y(n3506) );
OAI22X1TS U4632 ( .A0(n74), .A1(n3506), .B0(n5842), .B1(n3483), .Y(n3507) );
XNOR2X4TS U4633 ( .A(n3830), .B(n3831), .Y(n3579) );
XNOR2X1TS U4634 ( .A(n3986), .B(n3930), .Y(n3705) );
OAI22X1TS U4635 ( .A0(n6125), .A1(n3705), .B0(n91), .B1(n3493), .Y(n3749) );
INVX2TS U4636 ( .A(n6991), .Y(n5913) );
XNOR2X1TS U4637 ( .A(n5913), .B(n4112), .Y(n3731) );
XNOR2X1TS U4638 ( .A(n6708), .B(n4131), .Y(n3732) );
OAI22X1TS U4639 ( .A0(n5980), .A1(n3732), .B0(n3933), .B1(n3495), .Y(n3747)
);
XNOR2X1TS U4640 ( .A(n6642), .B(n4250), .Y(n3734) );
OAI22X1TS U4641 ( .A0(n3735), .A1(n3734), .B0(n5884), .B1(n3496), .Y(n3746)
);
XNOR2X1TS U4642 ( .A(n4094), .B(n3497), .Y(n3739) );
OAI22X1TS U4643 ( .A0(n2521), .A1(n3739), .B0(n4096), .B1(n3498), .Y(n3745)
);
XNOR2X1TS U4644 ( .A(n6580), .B(n4396), .Y(n3724) );
OAI22X1TS U4645 ( .A0(n4009), .A1(n3724), .B0(n4566), .B1(n3499), .Y(n3744)
);
XNOR2X1TS U4646 ( .A(n4247), .B(n5940), .Y(n3733) );
OAI22X1TS U4647 ( .A0(n4277), .A1(n3733), .B0(n48), .B1(n3500), .Y(n3712) );
XNOR2X1TS U4648 ( .A(n50), .B(n5750), .Y(n3687) );
OAI22X1TS U4649 ( .A0(n71), .A1(n3687), .B0(n5437), .B1(n3501), .Y(n3711) );
XNOR2X1TS U4650 ( .A(n4480), .B(n5999), .Y(n3736) );
OAI22X1TS U4651 ( .A0(n5235), .A1(n3736), .B0(n3503), .B1(n3502), .Y(n3710)
);
XNOR2X1TS U4652 ( .A(Data_A_i[23]), .B(n5579), .Y(n3685) );
OAI22X1TS U4653 ( .A0(n4084), .A1(n3685), .B0(n140), .B1(n3504), .Y(n3721)
);
XNOR2X1TS U4654 ( .A(n5529), .B(n5289), .Y(n3737) );
XNOR2X1TS U4655 ( .A(n5887), .B(n5434), .Y(n3682) );
OAI22X1TS U4656 ( .A0(n6381), .A1(n3682), .B0(n5842), .B1(n3506), .Y(n3719)
);
NOR2X1TS U4657 ( .A(n6062), .B(n3522), .Y(n3844) );
OAI22X1TS U4658 ( .A0(n41), .A1(n3527), .B0(n85), .B1(n3526), .Y(n3591) );
XNOR2X1TS U4659 ( .A(n3908), .B(n4335), .Y(n3628) );
OAI22X1TS U4660 ( .A0(n130), .A1(n3531), .B0(n1014), .B1(n3628), .Y(n3596)
);
INVX2TS U4661 ( .A(n6658), .Y(n6259) );
XNOR2X1TS U4662 ( .A(n6259), .B(n5335), .Y(n3620) );
OAI22X1TS U4663 ( .A0(n128), .A1(n3532), .B0(n6195), .B1(n3620), .Y(n3595)
);
OAI22X1TS U4664 ( .A0(n5217), .A1(n3534), .B0(n5267), .B1(n3533), .Y(n3594)
);
CMPR32X2TS U4665 ( .A(n3540), .B(n3539), .C(n3538), .CO(n3644), .S(n3661) );
CMPR32X2TS U4666 ( .A(n3549), .B(n3548), .C(n3547), .CO(n3649), .S(n3667) );
OAI22X1TS U4667 ( .A0(n4691), .A1(n3557), .B0(n6466), .B1(n3556), .Y(n3573)
);
OAI22X1TS U4668 ( .A0(n4277), .A1(n3559), .B0(n48), .B1(n3558), .Y(n3572) );
OAI22X1TS U4669 ( .A0(n6212), .A1(n3561), .B0(n4378), .B1(n3560), .Y(n3571)
);
CMPR32X2TS U4670 ( .A(n3570), .B(n3569), .C(n3568), .CO(n3585), .S(n3416) );
XNOR2X1TS U4671 ( .A(n106), .B(n3878), .Y(n3590) );
OAI22X1TS U4672 ( .A0(n46), .A1(n3574), .B0(n91), .B1(n3590), .Y(n3632) );
XNOR2X1TS U4673 ( .A(n114), .B(Data_B_i[32]), .Y(n3623) );
OAI22X1TS U4674 ( .A0(n5621), .A1(n3575), .B0(n5144), .B1(n3623), .Y(n3631)
);
XOR2X4TS U4675 ( .A(n3579), .B(n3828), .Y(n3921) );
CMPR32X2TS U4676 ( .A(n3585), .B(n3584), .C(n3583), .CO(n3914), .S(n3603) );
CMPR32X2TS U4677 ( .A(n3588), .B(n3587), .C(n3586), .CO(n3857), .S(n3580) );
XNOR2X1TS U4678 ( .A(n3986), .B(n4201), .Y(n3907) );
OAI22X1TS U4679 ( .A0(n145), .A1(n3590), .B0(n6063), .B1(n3907), .Y(n3842)
);
BUFX3TS U4680 ( .A(n3615), .Y(n5371) );
XNOR2X1TS U4681 ( .A(n133), .B(n5940), .Y(n3888) );
OAI22X1TS U4682 ( .A0(n3618), .A1(n3617), .B0(n5371), .B1(n3888), .Y(n3902)
);
XNOR2X1TS U4683 ( .A(n6708), .B(n5114), .Y(n3880) );
XNOR2X1TS U4684 ( .A(n6259), .B(n5434), .Y(n3887) );
OAI22X1TS U4685 ( .A0(n129), .A1(n3620), .B0(n6195), .B1(n3887), .Y(n3900)
);
XNOR2X1TS U4686 ( .A(n4256), .B(n5864), .Y(n3906) );
OAI22X1TS U4687 ( .A0(n4084), .A1(n3621), .B0(n5585), .B1(n3906), .Y(n3905)
);
XNOR2X1TS U4688 ( .A(n6146), .B(n5582), .Y(n3889) );
OAI22X1TS U4689 ( .A0(n6148), .A1(n3622), .B0(n6056), .B1(n3889), .Y(n3904)
);
XNOR2X1TS U4690 ( .A(n114), .B(n4082), .Y(n3879) );
OAI22X1TS U4691 ( .A0(n6184), .A1(n3623), .B0(n6251), .B1(n3879), .Y(n3903)
);
XNOR2X1TS U4692 ( .A(n4388), .B(n5999), .Y(n3841) );
XNOR2X1TS U4693 ( .A(n3908), .B(Data_B_i[37]), .Y(n3909) );
OAI22X1TS U4694 ( .A0(n5945), .A1(n3628), .B0(n4096), .B1(n3909), .Y(n3898)
);
XNOR2X1TS U4695 ( .A(n4076), .B(n5750), .Y(n3885) );
OAI22X1TS U4696 ( .A0(n5798), .A1(n3629), .B0(n5893), .B1(n3885), .Y(n3897)
);
CMPR32X2TS U4697 ( .A(n3632), .B(n3631), .C(n3630), .CO(n3867), .S(n3583) );
XNOR2X4TS U4698 ( .A(n3921), .B(n3924), .Y(n3700) );
XNOR2X1TS U4699 ( .A(n5760), .B(n4082), .Y(n3654) );
OAI22X1TS U4700 ( .A0(n4575), .A1(n3654), .B0(n4573), .B1(n3636), .Y(n3690)
);
XNOR2X1TS U4701 ( .A(n6519), .B(n5114), .Y(n3725) );
OAI22X1TS U4702 ( .A0(n4688), .A1(n3725), .B0(n6056), .B1(n3637), .Y(n3689)
);
XNOR2X1TS U4703 ( .A(n3927), .B(n5881), .Y(n3683) );
OAI22X1TS U4704 ( .A0(n4135), .A1(n3683), .B0(n112), .B1(n3638), .Y(n3688)
);
CMPR32X2TS U4705 ( .A(n3641), .B(n3640), .C(n3639), .CO(n3465), .S(n3713) );
CMPR32X2TS U4706 ( .A(n3647), .B(n3646), .C(n3645), .CO(n3517), .S(n3697) );
XNOR2X1TS U4707 ( .A(n3875), .B(n5864), .Y(n3722) );
OAI22X1TS U4708 ( .A0(n3723), .A1(n3722), .B0(n45), .B1(n3651), .Y(n3752) );
NOR2X1TS U4709 ( .A(n5938), .B(n3652), .Y(n3758) );
XNOR2X1TS U4710 ( .A(n4076), .B(n76), .Y(n3762) );
XNOR2X1TS U4711 ( .A(n5887), .B(n5335), .Y(n3800) );
OAI22X1TS U4712 ( .A0(n4635), .A1(n3800), .B0(n5842), .B1(n3682), .Y(n3787)
);
XNOR2X1TS U4713 ( .A(n3927), .B(n5839), .Y(n3779) );
OAI22X1TS U4714 ( .A0(n4135), .A1(n3779), .B0(n112), .B1(n3683), .Y(n3786)
);
XNOR2X1TS U4715 ( .A(n93), .B(n4000), .Y(n3784) );
OAI22X1TS U4716 ( .A0(n4122), .A1(n3784), .B0(n5622), .B1(n3684), .Y(n3785)
);
XNOR2X1TS U4717 ( .A(Data_A_i[23]), .B(n5547), .Y(n3770) );
OAI22X1TS U4718 ( .A0(n5519), .A1(n3770), .B0(n140), .B1(n3685), .Y(n3768)
);
XNOR2X1TS U4719 ( .A(n4085), .B(n6033), .Y(n3771) );
OAI22X1TS U4720 ( .A0(n54), .A1(n3771), .B0(n4740), .B1(n3686), .Y(n3767) );
XNOR2X1TS U4721 ( .A(n133), .B(n5811), .Y(n3759) );
OAI22X1TS U4722 ( .A0(n3760), .A1(n3759), .B0(n5437), .B1(n3687), .Y(n3766)
);
XOR2X4TS U4723 ( .A(n3700), .B(n3919), .Y(n5042) );
XNOR2X1TS U4724 ( .A(n3986), .B(n3704), .Y(n3761) );
OAI22X1TS U4725 ( .A0(n46), .A1(n3761), .B0(n4204), .B1(n3705), .Y(n3808) );
XNOR2X1TS U4726 ( .A(n5815), .B(n4035), .Y(n3960) );
OAI22X1TS U4727 ( .A0(n6530), .A1(n3960), .B0(n5753), .B1(n3706), .Y(n3807)
);
CMPR32X2TS U4728 ( .A(n3712), .B(n3711), .C(n3710), .CO(n3691), .S(n3812) );
XNOR2X1TS U4729 ( .A(n3875), .B(n5818), .Y(n3802) );
OAI22X1TS U4730 ( .A0(n3723), .A1(n3802), .B0(n45), .B1(n3722), .Y(n3950) );
XNOR2X1TS U4731 ( .A(n6580), .B(n4312), .Y(n3764) );
XNOR2X1TS U4732 ( .A(n6519), .B(n4487), .Y(n3765) );
OAI22X1TS U4733 ( .A0(n6590), .A1(n3765), .B0(n4686), .B1(n3725), .Y(n3948)
);
CMPR32X2TS U4734 ( .A(n3728), .B(n3727), .C(n3726), .CO(n3718), .S(n3809) );
XNOR2X1TS U4735 ( .A(n5715), .B(n5539), .Y(n3778) );
OAI22X1TS U4736 ( .A0(n5717), .A1(n3778), .B0(n3026), .B1(n3729), .Y(n3956)
);
XNOR2X1TS U4737 ( .A(Data_A_i[13]), .B(n5697), .Y(n3780) );
OAI22X1TS U4738 ( .A0(n2464), .A1(n3780), .B0(n83), .B1(n3730), .Y(n3955) );
XNOR2X1TS U4739 ( .A(n5913), .B(n4043), .Y(n3801) );
OAI22X1TS U4740 ( .A0(n4610), .A1(n3801), .B0(n6111), .B1(n3731), .Y(n3954)
);
XNOR2X1TS U4741 ( .A(n6708), .B(n3925), .Y(n3932) );
XNOR2X1TS U4742 ( .A(n3847), .B(n6055), .Y(n3783) );
XNOR2X1TS U4743 ( .A(n6642), .B(n4007), .Y(n3934) );
CLKBUFX2TS U4744 ( .A(n5527), .Y(n6706) );
OAI22X1TS U4745 ( .A0(n3735), .A1(n3934), .B0(n6706), .B1(n3734), .Y(n3961)
);
XNOR2X1TS U4746 ( .A(Data_A_i[19]), .B(n5496), .Y(n3763) );
XNOR2X1TS U4747 ( .A(n5529), .B(n5190), .Y(n3782) );
OAI22X1TS U4748 ( .A0(n5817), .A1(n3782), .B0(n3357), .B1(n3737), .Y(n3946)
);
XNOR2X1TS U4749 ( .A(n4094), .B(n3738), .Y(n3931) );
OAI22X1TS U4750 ( .A0(n5945), .A1(n3931), .B0(n4096), .B1(n3739), .Y(n3945)
);
XNOR2X1TS U4751 ( .A(n4108), .B(n5961), .Y(n3958) );
OAI22X1TS U4752 ( .A0(n105), .A1(n3958), .B0(n4562), .B1(n3740), .Y(n3805)
);
XNOR2X1TS U4753 ( .A(n3741), .B(n3985), .Y(n3957) );
XNOR2X1TS U4754 ( .A(n4078), .B(Data_B_i[52]), .Y(n3755) );
OAI22X1TS U4755 ( .A0(n2967), .A1(n3755), .B0(n4714), .B1(n3743), .Y(n3803)
);
XNOR2X1TS U4756 ( .A(n3753), .B(Data_B_i[53]), .Y(n4034) );
XNOR2X1TS U4757 ( .A(n4078), .B(n6007), .Y(n3998) );
OAI22X1TS U4758 ( .A0(n2110), .A1(n3998), .B0(n4714), .B1(n3755), .Y(n3976)
);
XNOR2X1TS U4759 ( .A(n50), .B(n5579), .Y(n4053) );
OAI22X1TS U4760 ( .A0(n3760), .A1(n4053), .B0(n5437), .B1(n3759), .Y(n3994)
);
XNOR2X1TS U4761 ( .A(n5449), .B(Data_B_i[27]), .Y(n3987) );
OAI22X1TS U4762 ( .A0(n5103), .A1(n3974), .B0(n4573), .B1(n3762), .Y(n3992)
);
XNOR2X1TS U4763 ( .A(n4480), .B(n5750), .Y(n3975) );
OAI22X1TS U4764 ( .A0(n4704), .A1(n3975), .B0(n5293), .B1(n3763), .Y(n3997)
);
XNOR2X1TS U4765 ( .A(n6580), .B(n4250), .Y(n4008) );
XNOR2X1TS U4766 ( .A(n6519), .B(n4396), .Y(n4010) );
OAI22X1TS U4767 ( .A0(n113), .A1(n4010), .B0(n4686), .B1(n3765), .Y(n3995)
);
XNOR2X1TS U4768 ( .A(n3769), .B(n6248), .Y(n3973) );
OAI22X1TS U4769 ( .A0(n8), .A1(n3973), .B0(n5517), .B1(n3770), .Y(n4049) );
OAI22X1TS U4770 ( .A0(n56), .A1(n3774), .B0(n4740), .B1(n3771), .Y(n4048) );
NOR2X1TS U4771 ( .A(n5938), .B(n3772), .Y(n4056) );
NOR2X1TS U4772 ( .A(n5938), .B(n3773), .Y(n4055) );
XNOR2X1TS U4773 ( .A(n5715), .B(n5434), .Y(n4045) );
OAI22X1TS U4774 ( .A0(n5717), .A1(n4045), .B0(n3026), .B1(n3778), .Y(n4042)
);
XNOR2X1TS U4775 ( .A(n3927), .B(n5718), .Y(n3928) );
OAI22X1TS U4776 ( .A0(n4135), .A1(n3928), .B0(n112), .B1(n3779), .Y(n4041)
);
XNOR2X1TS U4777 ( .A(n4136), .B(n5619), .Y(n3929) );
OAI22X1TS U4778 ( .A0(n43), .A1(n3929), .B0(n84), .B1(n3780), .Y(n4040) );
XNOR2X1TS U4779 ( .A(n5082), .B(n3781), .Y(n4003) );
XNOR2X1TS U4780 ( .A(n4247), .B(n5864), .Y(n4005) );
XNOR2X1TS U4781 ( .A(n6015), .B(n4099), .Y(n4036) );
OAI22X1TS U4782 ( .A0(n4122), .A1(n4036), .B0(n5622), .B1(n3784), .Y(n3936)
);
CMPR32X2TS U4783 ( .A(n3787), .B(n3786), .C(n3785), .CO(n3793), .S(n3982) );
CMPR32X2TS U4784 ( .A(n3793), .B(n3792), .C(n3791), .CO(n3820), .S(n4150) );
XNOR2X1TS U4785 ( .A(n6343), .B(n5289), .Y(n4004) );
OAI22X1TS U4786 ( .A0(n6392), .A1(n4004), .B0(n5842), .B1(n3800), .Y(n4039)
);
XNOR2X1TS U4787 ( .A(n4100), .B(n4080), .Y(n4001) );
OAI22X1TS U4788 ( .A0(n5456), .A1(n4001), .B0(n5454), .B1(n3801), .Y(n4038)
);
XNOR2X1TS U4789 ( .A(n3875), .B(n5999), .Y(n4002) );
OAI22X1TS U4790 ( .A0(n4375), .A1(n4002), .B0(n45), .B1(n3802), .Y(n4037) );
CMPR32X2TS U4791 ( .A(n3814), .B(n3813), .C(n3812), .CO(n3817), .S(n4147) );
OAI21X4TS U4792 ( .A0(n4171), .A1(n4169), .B0(n4170), .Y(n3824) );
ADDFHX2TS U4793 ( .A(n3827), .B(n3826), .CI(n3825), .CO(n3919), .S(n4182) );
NOR2X2TS U4794 ( .A(n5042), .B(n5041), .Y(n7533) );
CMPR32X2TS U4795 ( .A(n3834), .B(n3833), .C(n3832), .CO(n4344), .S(n3861) );
CMPR32X2TS U4796 ( .A(n3840), .B(n3839), .C(n3838), .CO(n4208), .S(n3891) );
XNOR2X1TS U4797 ( .A(n5520), .B(n5818), .Y(n4224) );
OAI22X1TS U4798 ( .A0(n5667), .A1(n3841), .B0(n109), .B1(n4224), .Y(n4199)
);
XNOR2X1TS U4799 ( .A(n2705), .B(n80), .Y(n4276) );
OAI22X1TS U4800 ( .A0(n4277), .A1(n3848), .B0(n49), .B1(n4276), .Y(n4209) );
INVX2TS U4801 ( .A(n75), .Y(n6047) );
XNOR2X1TS U4802 ( .A(n3873), .B(n6047), .Y(n4249) );
OAI22X1TS U4803 ( .A0(n4536), .A1(n3874), .B0(n5659), .B1(n4249), .Y(n4288)
);
XNOR2X1TS U4804 ( .A(n3875), .B(n6290), .Y(n4279) );
OAI22X1TS U4805 ( .A0(n4375), .A1(n3876), .B0(n51), .B1(n4279), .Y(n4287) );
XNOR2X1TS U4806 ( .A(n6761), .B(n4487), .Y(n4254) );
OAI22X1TS U4807 ( .A0(n4381), .A1(n3877), .B0(n4253), .B1(n4254), .Y(n4286)
);
XNOR2X1TS U4808 ( .A(n6129), .B(n3878), .Y(n4202) );
OAI22X1TS U4809 ( .A0(n120), .A1(n3879), .B0(n4420), .B1(n4202), .Y(n4196)
);
OAI22X1TS U4810 ( .A0(n4225), .A1(n3880), .B0(n3933), .B1(n4226), .Y(n4195)
);
BUFX3TS U4811 ( .A(n5883), .Y(n6340) );
INVX2TS U4812 ( .A(n6705), .Y(n6338) );
XNOR2X1TS U4813 ( .A(n6338), .B(n5335), .Y(n4229) );
OAI22X1TS U4814 ( .A0(n6340), .A1(n3881), .B0(n6316), .B1(n4229), .Y(n4194)
);
XNOR2X1TS U4815 ( .A(n5760), .B(n5496), .Y(n4215) );
OAI22X1TS U4816 ( .A0(n5103), .A1(n3885), .B0(n5893), .B1(n4215), .Y(n4223)
);
XNOR2X1TS U4817 ( .A(n4480), .B(n6193), .Y(n4232) );
OAI22X1TS U4818 ( .A0(n148), .A1(n3886), .B0(n5233), .B1(n4232), .Y(n4222)
);
XNOR2X1TS U4819 ( .A(n6259), .B(n5539), .Y(n4216) );
OAI22X1TS U4820 ( .A0(n129), .A1(n3887), .B0(n6195), .B1(n4216), .Y(n4221)
);
XNOR2X1TS U4821 ( .A(n3616), .B(n6026), .Y(n4255) );
OAI22X1TS U4822 ( .A0(n5373), .A1(n3888), .B0(n5371), .B1(n4255), .Y(n4214)
);
XNOR2X1TS U4823 ( .A(n5187), .B(n4338), .Y(n4231) );
OAI22X1TS U4824 ( .A0(n6525), .A1(n3889), .B0(n6056), .B1(n4231), .Y(n4213)
);
XNOR2X1TS U4825 ( .A(n6376), .B(n5814), .Y(n4217) );
OAI22X1TS U4826 ( .A0(n60), .A1(n3890), .B0(n5432), .B1(n4217), .Y(n4212) );
CMPR32X2TS U4827 ( .A(n3896), .B(n3895), .C(n3894), .CO(n4220), .S(n3832) );
CMPR32X2TS U4828 ( .A(n3905), .B(n3904), .C(n3903), .CO(n4273), .S(n3835) );
XNOR2X1TS U4829 ( .A(n5368), .B(n6055), .Y(n4257) );
OAI22X1TS U4830 ( .A0(n4084), .A1(n3906), .B0(n5585), .B1(n4257), .Y(n4291)
);
CLKBUFX2TS U4831 ( .A(n4391), .Y(n6124) );
XNOR2X1TS U4832 ( .A(n106), .B(n4335), .Y(n4205) );
XNOR2X1TS U4833 ( .A(n3908), .B(n4469), .Y(n4200) );
OAI22X1TS U4834 ( .A0(n5945), .A1(n3909), .B0(n1014), .B1(n4200), .Y(n4289)
);
XNOR2X1TS U4835 ( .A(n4394), .B(Data_B_i[30]), .Y(n4274) );
OAI22X1TS U4836 ( .A0(n5217), .A1(n3910), .B0(n5267), .B1(n4274), .Y(n4282)
);
XNOR2X1TS U4837 ( .A(n6890), .B(n4312), .Y(n4233) );
OAI22X1TS U4838 ( .A0(n5085), .A1(n3911), .B0(n4378), .B1(n4233), .Y(n4281)
);
BUFX3TS U4839 ( .A(n6365), .Y(n6530) );
XNOR2X1TS U4840 ( .A(n7049), .B(n4007), .Y(n4251) );
OAI22X1TS U4841 ( .A0(n4750), .A1(n3912), .B0(n5115), .B1(n4251), .Y(n4280)
);
ADDFHX4TS U4842 ( .A(n3918), .B(n3917), .CI(n3916), .CO(n4540), .S(n3924) );
BUFX3TS U4843 ( .A(n5883), .Y(n5838) );
XNOR2X1TS U4844 ( .A(n3926), .B(n3925), .Y(n4113) );
XNOR2X1TS U4845 ( .A(n6642), .B(n4131), .Y(n3935) );
OAI22X1TS U4846 ( .A0(n5838), .A1(n4113), .B0(n6683), .B1(n3935), .Y(n4140)
);
XNOR2X1TS U4847 ( .A(n3927), .B(n5697), .Y(n4134) );
OAI22X1TS U4848 ( .A0(n4135), .A1(n4134), .B0(n112), .B1(n3928), .Y(n4139)
);
XNOR2X1TS U4849 ( .A(n4136), .B(n5525), .Y(n4137) );
OAI22X1TS U4850 ( .A0(n40), .A1(n4137), .B0(n84), .B1(n3929), .Y(n4138) );
XNOR2X1TS U4851 ( .A(n4094), .B(n3930), .Y(n3999) );
OAI22X1TS U4852 ( .A0(n5251), .A1(n3999), .B0(n4096), .B1(n3931), .Y(n3944)
);
INVX2TS U4853 ( .A(n6768), .Y(n5692) );
XNOR2X1TS U4854 ( .A(n5692), .B(n4112), .Y(n4044) );
OAI22X1TS U4855 ( .A0(n4582), .A1(n4044), .B0(n3933), .B1(n3932), .Y(n3943)
);
OAI22X1TS U4856 ( .A0(n5838), .A1(n3935), .B0(n6706), .B1(n3934), .Y(n3942)
);
XNOR2X1TS U4857 ( .A(n1860), .B(n4066), .Y(n4033) );
OAI22X1TS U4858 ( .A0(n6184), .A1(n4033), .B0(n4420), .B1(n3957), .Y(n3981)
);
XNOR2X1TS U4859 ( .A(n4108), .B(n5881), .Y(n4046) );
OAI22X1TS U4860 ( .A0(n3959), .A1(n4046), .B0(n4562), .B1(n3958), .Y(n3980)
);
XNOR2X1TS U4861 ( .A(n5815), .B(n4068), .Y(n3989) );
OAI22X1TS U4862 ( .A0(n7093), .A1(n3989), .B0(n5753), .B1(n3960), .Y(n3979)
);
CMPR32X2TS U4863 ( .A(n3966), .B(n3965), .C(n3964), .CO(n4017), .S(n4014) );
XNOR2X1TS U4864 ( .A(Data_A_i[23]), .B(n6033), .Y(n4083) );
OAI22X1TS U4865 ( .A0(n5519), .A1(n4083), .B0(n140), .B1(n3973), .Y(n4641)
);
OAI22X1TS U4866 ( .A0(n4322), .A1(n4077), .B0(n4573), .B1(n3974), .Y(n4640)
);
XNOR2X1TS U4867 ( .A(n4087), .B(n5811), .Y(n4088) );
OAI22X1TS U4868 ( .A0(n5294), .A1(n4088), .B0(n5293), .B1(n3975), .Y(n4639)
);
CMPR32X2TS U4869 ( .A(n3984), .B(n3983), .C(n3982), .CO(n4152), .S(n4141) );
XNOR2X1TS U4870 ( .A(n1814), .B(n3985), .Y(n4067) );
OAI22X1TS U4871 ( .A0(n6125), .A1(n4067), .B0(n90), .B1(n3987), .Y(n4644) );
XNOR2X1TS U4872 ( .A(n7049), .B(n3988), .Y(n4072) );
XNOR2X1TS U4873 ( .A(n4078), .B(n5961), .Y(n4079) );
XNOR2X1TS U4874 ( .A(n4094), .B(Data_B_i[28]), .Y(n4095) );
XNOR2X1TS U4875 ( .A(n5913), .B(n4000), .Y(n4101) );
OAI22X1TS U4876 ( .A0(n4610), .A1(n4101), .B0(n5454), .B1(n4001), .Y(n4128)
);
XNOR2X1TS U4877 ( .A(Data_A_i[17]), .B(n5496), .Y(n4636) );
OAI22X1TS U4878 ( .A0(n4479), .A1(n4636), .B0(n63), .B1(n4002), .Y(n4065) );
XNOR2X1TS U4879 ( .A(n118), .B(n4487), .Y(n4093) );
XNOR2X1TS U4880 ( .A(n6343), .B(n5190), .Y(n4633) );
OAI22X1TS U4881 ( .A0(n74), .A1(n4633), .B0(n5842), .B1(n4004), .Y(n4063) );
XNOR2X1TS U4882 ( .A(n2897), .B(n5818), .Y(n4090) );
OAI22X1TS U4883 ( .A0(n4006), .A1(n4090), .B0(n1379), .B1(n4005), .Y(n4075)
);
XNOR2X1TS U4884 ( .A(n6580), .B(n4007), .Y(n4132) );
XNOR2X1TS U4885 ( .A(n6519), .B(n4312), .Y(n4092) );
OAI22X1TS U4886 ( .A0(n5549), .A1(n4092), .B0(n4686), .B1(n4010), .Y(n4073)
);
XNOR2X1TS U4887 ( .A(n1860), .B(n4032), .Y(n4111) );
OAI22X1TS U4888 ( .A0(n6252), .A1(n4111), .B0(n6182), .B1(n4033), .Y(n4107)
);
XNOR2X1TS U4889 ( .A(n4097), .B(n79), .Y(n4098) );
XNOR2X1TS U4890 ( .A(n4069), .B(n4035), .Y(n4070) );
OAI22X1TS U4891 ( .A0(n4122), .A1(n4070), .B0(n5622), .B1(n4036), .Y(n4105)
);
XNOR2X1TS U4892 ( .A(n5692), .B(n4043), .Y(n4081) );
OAI22X1TS U4893 ( .A0(n4582), .A1(n4081), .B0(n6709), .B1(n4044), .Y(n4104)
);
XNOR2X1TS U4894 ( .A(n5715), .B(n5335), .Y(n4637) );
OAI22X1TS U4895 ( .A0(n5717), .A1(n4637), .B0(n3026), .B1(n4045), .Y(n4103)
);
XNOR2X1TS U4896 ( .A(n4108), .B(n5839), .Y(n4109) );
OAI22X1TS U4897 ( .A0(n105), .A1(n4109), .B0(n4562), .B1(n4046), .Y(n4102)
);
INVX2TS U4898 ( .A(n4056), .Y(n4710) );
OAI22X1TS U4899 ( .A0(n4052), .A1(n4611), .B0(n4612), .B1(n3276), .Y(n4118)
);
XNOR2X1TS U4900 ( .A(n3616), .B(n5547), .Y(n4117) );
XNOR2X1TS U4901 ( .A(n1814), .B(n4066), .Y(n4606) );
OAI22X1TS U4902 ( .A0(n6125), .A1(n4606), .B0(n5390), .B1(n4067), .Y(n4605)
);
XNOR2X1TS U4903 ( .A(n4069), .B(n4068), .Y(n4120) );
OAI22X1TS U4904 ( .A0(n4122), .A1(n4120), .B0(n5622), .B1(n4070), .Y(n4604)
);
XNOR2X1TS U4905 ( .A(n5815), .B(n4071), .Y(n4748) );
OAI22X1TS U4906 ( .A0(n4750), .A1(n4748), .B0(n5753), .B1(n4072), .Y(n4603)
);
XNOR2X1TS U4907 ( .A(n5760), .B(n5890), .Y(n4572) );
OAI22X1TS U4908 ( .A0(n39), .A1(n4572), .B0(n4573), .B1(n4077), .Y(n4591) );
XNOR2X1TS U4909 ( .A(n4078), .B(n5881), .Y(n4713) );
OAI22X1TS U4910 ( .A0(n4716), .A1(n4713), .B0(n4714), .B1(n4079), .Y(n4590)
);
XNOR2X1TS U4911 ( .A(n5692), .B(n4080), .Y(n4580) );
OAI22X1TS U4912 ( .A0(n4582), .A1(n4580), .B0(n6487), .B1(n4081), .Y(n4589)
);
XNOR2X1TS U4913 ( .A(Data_A_i[23]), .B(n4082), .Y(n4123) );
OAI22X1TS U4914 ( .A0(n4258), .A1(n4123), .B0(n5517), .B1(n4083), .Y(n4602)
);
XNOR2X1TS U4915 ( .A(n5520), .B(n5911), .Y(n4739) );
XNOR2X1TS U4916 ( .A(n4087), .B(n5579), .Y(n4701) );
OAI22X1TS U4917 ( .A0(n5294), .A1(n4701), .B0(n5293), .B1(n4088), .Y(n4600)
);
XNOR2X1TS U4918 ( .A(n4089), .B(n5999), .Y(n4592) );
OAI22X1TS U4919 ( .A0(n4277), .A1(n4592), .B0(n4091), .B1(n4090), .Y(n4768)
);
XNOR2X1TS U4920 ( .A(n6519), .B(n4250), .Y(n4685) );
OAI22X1TS U4921 ( .A0(n6148), .A1(n4685), .B0(n4686), .B1(n4092), .Y(n4767)
);
XNOR2X1TS U4922 ( .A(n6336), .B(n4396), .Y(n4689) );
OAI22X1TS U4923 ( .A0(n60), .A1(n4689), .B0(n6466), .B1(n4093), .Y(n4766) );
XNOR2X1TS U4924 ( .A(n4094), .B(Data_B_i[27]), .Y(n4745) );
OAI22X1TS U4925 ( .A0(n131), .A1(n4745), .B0(n4096), .B1(n4095), .Y(n4620)
);
XNOR2X1TS U4926 ( .A(n4097), .B(n6007), .Y(n4576) );
OAI22X1TS U4927 ( .A0(n143), .A1(n4576), .B0(n88), .B1(n4098), .Y(n4619) );
XNOR2X1TS U4928 ( .A(n4100), .B(n4099), .Y(n4608) );
OAI22X1TS U4929 ( .A0(n4610), .A1(n4608), .B0(n5454), .B1(n4101), .Y(n4618)
);
XNOR2X1TS U4930 ( .A(n4108), .B(n5718), .Y(n4561) );
OAI22X1TS U4931 ( .A0(n104), .A1(n4561), .B0(n4562), .B1(n4109), .Y(n4617)
);
XNOR2X1TS U4932 ( .A(n3741), .B(n4110), .Y(n4711) );
XNOR2X1TS U4933 ( .A(n5627), .B(n4112), .Y(n4717) );
OAI22X1TS U4934 ( .A0(n6511), .A1(n4717), .B0(n5884), .B1(n4113), .Y(n4615)
);
ADDFHX2TS U4935 ( .A(n4116), .B(n4115), .CI(n4114), .CO(n4125), .S(n4773) );
XNOR2X1TS U4936 ( .A(n3616), .B(n6248), .Y(n4742) );
OAI22X1TS U4937 ( .A0(n69), .A1(n4742), .B0(n5437), .B1(n4117), .Y(n4721) );
OAI22X1TS U4938 ( .A0(n66), .A1(n4124), .B0(n5517), .B1(n4123), .Y(n4708) );
XNOR2X1TS U4939 ( .A(n6580), .B(n4131), .Y(n4565) );
OAI22X1TS U4940 ( .A0(n5702), .A1(n4565), .B0(n4566), .B1(n4132), .Y(n4585)
);
XNOR2X1TS U4941 ( .A(n4133), .B(n5619), .Y(n4568) );
XNOR2X1TS U4942 ( .A(n4136), .B(n5465), .Y(n4681) );
OAI22X1TS U4943 ( .A0(n41), .A1(n4681), .B0(n85), .B1(n4137), .Y(n4583) );
CMPR32X2TS U4944 ( .A(n4140), .B(n4139), .C(n4138), .CO(n4665), .S(n4630) );
OAI2BB1X2TS U4945 ( .A0N(n4999), .A1N(n5001), .B0(n4168), .Y(n4173) );
NOR2X2TS U4946 ( .A(n5037), .B(n5038), .Y(n7587) );
NOR2X4TS U4947 ( .A(n5040), .B(n5039), .Y(n7562) );
NOR2X2TS U4948 ( .A(n7587), .B(n7562), .Y(n7537) );
NAND2X4TS U4949 ( .A(n5046), .B(n7537), .Y(n7551) );
CMPR32X2TS U4950 ( .A(n4193), .B(n4192), .C(n4191), .CO(n4296), .S(n4268) );
CMPR32X2TS U4951 ( .A(n4196), .B(n4195), .C(n4194), .CO(n4239), .S(n4188) );
XNOR2X1TS U4952 ( .A(n5800), .B(n5143), .Y(n4317) );
OAI22X1TS U4953 ( .A0(n131), .A1(n4200), .B0(n1014), .B1(n4317), .Y(n4264)
);
XNOR2X1TS U4954 ( .A(Data_A_i[33]), .B(n4201), .Y(n4336) );
OAI22X1TS U4955 ( .A0(n6184), .A1(n4202), .B0(n4420), .B1(n4336), .Y(n4263)
);
XNOR2X1TS U4956 ( .A(n5449), .B(n77), .Y(n4334) );
XNOR2X1TS U4957 ( .A(n98), .B(n5999), .Y(n4323) );
OAI22X1TS U4958 ( .A0(n4575), .A1(n4215), .B0(n5893), .B1(n4323), .Y(n4332)
);
XNOR2X1TS U4959 ( .A(n6259), .B(n5582), .Y(n4339) );
OAI22X1TS U4960 ( .A0(n128), .A1(n4216), .B0(n6195), .B1(n4339), .Y(n4331)
);
XNOR2X1TS U4961 ( .A(n118), .B(Data_B_i[29]), .Y(n4310) );
OAI22X1TS U4962 ( .A0(n60), .A1(n4217), .B0(n138), .B1(n4310), .Y(n4330) );
XNOR2X1TS U4963 ( .A(n4388), .B(n5864), .Y(n4341) );
OAI22X1TS U4964 ( .A0(n4390), .A1(n4224), .B0(n109), .B1(n4341), .Y(n4261)
);
XNOR2X1TS U4965 ( .A(n6708), .B(n5289), .Y(n4318) );
INVX2TS U4966 ( .A(n4228), .Y(n4260) );
XNOR2X1TS U4967 ( .A(n6338), .B(n5434), .Y(n4319) );
OAI22X1TS U4968 ( .A0(n6340), .A1(n4229), .B0(n6316), .B1(n4319), .Y(n4259)
);
XNOR2X1TS U4969 ( .A(n5187), .B(n5752), .Y(n4333) );
OAI22X1TS U4970 ( .A0(n4688), .A1(n4231), .B0(n4230), .B1(n4333), .Y(n4306)
);
XNOR2X1TS U4971 ( .A(n4087), .B(n6232), .Y(n4311) );
OAI22X1TS U4972 ( .A0(n4704), .A1(n4232), .B0(n5233), .B1(n4311), .Y(n4305)
);
XNOR2X1TS U4973 ( .A(n6995), .B(n4396), .Y(n4340) );
OAI22X1TS U4974 ( .A0(n5085), .A1(n4233), .B0(n4378), .B1(n4340), .Y(n4304)
);
XNOR2X1TS U4975 ( .A(n4373), .B(n6989), .Y(n4278) );
XNOR2X1TS U4976 ( .A(n4373), .B(n80), .Y(n4374) );
NOR2X1TS U4977 ( .A(n5938), .B(n4246), .Y(n4473) );
INVX2TS U4978 ( .A(n7090), .Y(n6128) );
XNOR2X1TS U4979 ( .A(n3847), .B(n6128), .Y(n4275) );
OAI22X1TS U4980 ( .A0(n4277), .A1(n4275), .B0(n49), .B1(n4398), .Y(n4423) );
INVX2TS U4981 ( .A(n6257), .Y(n6121) );
XNOR2X1TS U4982 ( .A(n5185), .B(n6121), .Y(n4320) );
OAI22X1TS U4983 ( .A0(n4536), .A1(n4249), .B0(n5659), .B1(n4320), .Y(n4294)
);
XNOR2X1TS U4984 ( .A(n7049), .B(n4250), .Y(n4313) );
OAI22X1TS U4985 ( .A0(n6530), .A1(n4251), .B0(n5115), .B1(n4313), .Y(n4293)
);
XNOR2X1TS U4986 ( .A(n6761), .B(n5114), .Y(n4321) );
XNOR2X1TS U4987 ( .A(Data_A_i[21]), .B(n6347), .Y(n4308) );
OAI22X1TS U4988 ( .A0(n5373), .A1(n4255), .B0(n5371), .B1(n4308), .Y(n4284)
);
XNOR2X1TS U4989 ( .A(n4256), .B(n5940), .Y(n4309) );
OAI22X1TS U4990 ( .A0(n5586), .A1(n4257), .B0(n5517), .B1(n4309), .Y(n4283)
);
CMPR32X2TS U4991 ( .A(n4273), .B(n4272), .C(n4271), .CO(n4300), .S(n4234) );
XNOR2X1TS U4992 ( .A(n4394), .B(Data_B_i[31]), .Y(n4307) );
OAI22X1TS U4993 ( .A0(n6392), .A1(n4274), .B0(n5267), .B1(n4307), .Y(n4316)
);
OAI22X1TS U4994 ( .A0(n4277), .A1(n4276), .B0(n48), .B1(n4275), .Y(n4315) );
OAI22X1TS U4995 ( .A0(n4375), .A1(n4279), .B0(n52), .B1(n4278), .Y(n4314) );
CMPR32X2TS U4996 ( .A(n4282), .B(n4281), .C(n4280), .CO(n4325), .S(n4271) );
CMPR32X2TS U4997 ( .A(n4285), .B(n4284), .C(n4283), .CO(n4359), .S(n4324) );
CMPR32X2TS U4998 ( .A(n4303), .B(n4302), .C(n4301), .CO(n4356), .S(n4265) );
XNOR2X1TS U4999 ( .A(n6311), .B(n6047), .Y(n4395) );
OAI22X1TS U5000 ( .A0(n4635), .A1(n4307), .B0(n5267), .B1(n4395), .Y(n4371)
);
XNOR2X1TS U5001 ( .A(Data_A_i[21]), .B(n6193), .Y(n4407) );
OAI22X1TS U5002 ( .A0(n5373), .A1(n4308), .B0(n5371), .B1(n4407), .Y(n4370)
);
XNOR2X1TS U5003 ( .A(n5368), .B(n6026), .Y(n4399) );
OAI22X1TS U5004 ( .A0(n66), .A1(n4309), .B0(n3425), .B1(n4399), .Y(n4369) );
XNOR2X1TS U5005 ( .A(n6376), .B(Data_B_i[30]), .Y(n4372) );
OAI22X1TS U5006 ( .A0(n6542), .A1(n4310), .B0(n139), .B1(n4372), .Y(n4405)
);
XNOR2X1TS U5007 ( .A(n4480), .B(n6290), .Y(n4376) );
OAI22X1TS U5008 ( .A0(n4704), .A1(n4311), .B0(n5233), .B1(n4376), .Y(n4404)
);
XNOR2X1TS U5009 ( .A(n7049), .B(n4312), .Y(n4397) );
OAI22X1TS U5010 ( .A0(n5291), .A1(n4313), .B0(n5115), .B1(n4397), .Y(n4403)
);
CMPR32X2TS U5011 ( .A(n4316), .B(n4315), .C(n4314), .CO(n4384), .S(n4326) );
XNOR2X1TS U5012 ( .A(Data_A_i[29]), .B(n5180), .Y(n4393) );
OAI22X1TS U5013 ( .A0(n5945), .A1(n4317), .B0(n1014), .B1(n4393), .Y(n4387)
);
BUFX3TS U5014 ( .A(n6319), .Y(n6401) );
XNOR2X1TS U5015 ( .A(n6388), .B(n5335), .Y(n4406) );
OAI22X1TS U5016 ( .A0(n6401), .A1(n4318), .B0(n6732), .B1(n4406), .Y(n4386)
);
XNOR2X1TS U5017 ( .A(n6338), .B(n5539), .Y(n4408) );
OAI22X1TS U5018 ( .A0(n6340), .A1(n4319), .B0(n6316), .B1(n4408), .Y(n4385)
);
XNOR2X1TS U5019 ( .A(n5185), .B(Data_B_i[34]), .Y(n4402) );
OAI22X1TS U5020 ( .A0(n4536), .A1(n4320), .B0(n6308), .B1(n4402), .Y(n4368)
);
XNOR2X1TS U5021 ( .A(n6761), .B(n5190), .Y(n4380) );
OAI22X1TS U5022 ( .A0(n4381), .A1(n4321), .B0(n6480), .B1(n4380), .Y(n4367)
);
XNOR2X1TS U5023 ( .A(n5760), .B(n5818), .Y(n4418) );
OAI22X1TS U5024 ( .A0(n2633), .A1(n4323), .B0(n4518), .B1(n4418), .Y(n4366)
);
XNOR2X1TS U5025 ( .A(n5187), .B(n5814), .Y(n4377) );
OAI22X1TS U5026 ( .A0(n6148), .A1(n4333), .B0(n5580), .B1(n4377), .Y(n4365)
);
XNOR2X1TS U5027 ( .A(n106), .B(n4469), .Y(n4392) );
OAI22X1TS U5028 ( .A0(n6125), .A1(n4334), .B0(n6063), .B1(n4392), .Y(n4364)
);
OAI22X1TS U5029 ( .A0(n6184), .A1(n4336), .B0(n58), .B1(n4421), .Y(n4363) );
XNOR2X1TS U5030 ( .A(n5427), .B(n4338), .Y(n4401) );
OAI22X1TS U5031 ( .A0(n129), .A1(n4339), .B0(n6195), .B1(n4401), .Y(n4362)
);
XNOR2X1TS U5032 ( .A(n6995), .B(n4487), .Y(n4379) );
OAI22X1TS U5033 ( .A0(n5085), .A1(n4340), .B0(n4378), .B1(n4379), .Y(n4361)
);
XNOR2X1TS U5034 ( .A(n116), .B(n6055), .Y(n4389) );
OAI22X1TS U5035 ( .A0(n4390), .A1(n4341), .B0(n38), .B1(n4389), .Y(n4360) );
CMPR32X2TS U5036 ( .A(n4362), .B(n4361), .C(n4360), .CO(n4525), .S(n4429) );
CMPR32X2TS U5037 ( .A(n4368), .B(n4367), .C(n4366), .CO(n4523), .S(n4382) );
XNOR2X1TS U5038 ( .A(n6376), .B(Data_B_i[31]), .Y(n4485) );
OAI22X1TS U5039 ( .A0(n6542), .A1(n4372), .B0(n138), .B1(n4485), .Y(n4512)
);
XNOR2X1TS U5040 ( .A(n4373), .B(n6128), .Y(n4478) );
OAI22X1TS U5041 ( .A0(n4375), .A1(n4374), .B0(n52), .B1(n4478), .Y(n4511) );
XNOR2X1TS U5042 ( .A(n4480), .B(n6989), .Y(n4481) );
OAI22X1TS U5043 ( .A0(n150), .A1(n4376), .B0(n5233), .B1(n4481), .Y(n4510)
);
XNOR2X1TS U5044 ( .A(n5187), .B(Data_B_i[29]), .Y(n4513) );
OAI22X1TS U5045 ( .A0(n6590), .A1(n4377), .B0(n5580), .B1(n4513), .Y(n4500)
);
XNOR2X1TS U5046 ( .A(n6995), .B(n5114), .Y(n4515) );
OAI22X1TS U5047 ( .A0(n5085), .A1(n4379), .B0(n4378), .B1(n4515), .Y(n4499)
);
XNOR2X1TS U5048 ( .A(n6761), .B(n5289), .Y(n4529) );
OAI22X1TS U5049 ( .A0(n4381), .A1(n4380), .B0(n6480), .B1(n4529), .Y(n4498)
);
CMPR32X2TS U5050 ( .A(n4384), .B(n4383), .C(n4382), .CO(n4458), .S(n4354) );
XNOR2X1TS U5051 ( .A(n4388), .B(n5940), .Y(n4517) );
OAI22X1TS U5052 ( .A0(n4390), .A1(n4389), .B0(n108), .B1(n4517), .Y(n4484)
);
XNOR2X1TS U5053 ( .A(n6012), .B(n5143), .Y(n4468) );
OAI22X1TS U5054 ( .A0(n5451), .A1(n4392), .B0(n4391), .B1(n4468), .Y(n4483)
);
XNOR2X1TS U5055 ( .A(Data_A_i[29]), .B(n5278), .Y(n4533) );
OAI22X1TS U5056 ( .A0(n6003), .A1(n4393), .B0(n1014), .B1(n4533), .Y(n4482)
);
XNOR2X1TS U5057 ( .A(n4394), .B(n6121), .Y(n4516) );
OAI22X1TS U5058 ( .A0(n5217), .A1(n4395), .B0(n5267), .B1(n4516), .Y(n4528)
);
XNOR2X1TS U5059 ( .A(n7049), .B(n4396), .Y(n4488) );
OAI22X1TS U5060 ( .A0(n13), .A1(n4397), .B0(n5115), .B1(n4488), .Y(n4527) );
XNOR2X1TS U5061 ( .A(n5368), .B(n6347), .Y(n4514) );
OAI22X1TS U5062 ( .A0(n67), .A1(n4399), .B0(n5517), .B1(n4514), .Y(n4503) );
XNOR2X1TS U5063 ( .A(n5427), .B(n5752), .Y(n4530) );
OAI22X1TS U5064 ( .A0(n5757), .A1(n4401), .B0(n4400), .B1(n4530), .Y(n4502)
);
XNOR2X1TS U5065 ( .A(n5185), .B(Data_B_i[35]), .Y(n4535) );
OAI22X1TS U5066 ( .A0(n4536), .A1(n4402), .B0(n5120), .B1(n4535), .Y(n4501)
);
XNOR2X1TS U5067 ( .A(n6388), .B(n5434), .Y(n4531) );
OAI22X1TS U5068 ( .A0(n6401), .A1(n4406), .B0(n6732), .B1(n4531), .Y(n4506)
);
XNOR2X1TS U5069 ( .A(n132), .B(n6232), .Y(n4486) );
OAI22X1TS U5070 ( .A0(n5373), .A1(n4407), .B0(n5371), .B1(n4486), .Y(n4505)
);
XNOR2X1TS U5071 ( .A(n6338), .B(n5582), .Y(n4534) );
OAI22X1TS U5072 ( .A0(n6340), .A1(n4408), .B0(n6316), .B1(n4534), .Y(n4504)
);
CMPR32X2TS U5073 ( .A(n4411), .B(n4410), .C(n4409), .CO(n4539), .S(n4351) );
ADDFHX1TS U5074 ( .A(n4417), .B(n4416), .CI(n4415), .CO(n4467), .S(n4433) );
XNOR2X1TS U5075 ( .A(n1660), .B(n5864), .Y(n4519) );
OAI22X1TS U5076 ( .A0(n5798), .A1(n4418), .B0(n4518), .B1(n4519), .Y(n4476)
);
OAI22X1TS U5077 ( .A0(n4422), .A1(n4421), .B0(n6251), .B1(n4470), .Y(n4471)
);
NAND2X1TS U5078 ( .A(n4425), .B(n4424), .Y(n4426) );
ADDFHX4TS U5079 ( .A(n4443), .B(n4442), .CI(n4441), .CO(n4454), .S(n4553) );
ADDFHX2TS U5080 ( .A(n4452), .B(n4451), .CI(n4450), .CO(n4546), .S(n4550) );
NOR2X2TS U5081 ( .A(n5052), .B(n5051), .Y(n7515) );
ADDFHX2TS U5082 ( .A(n4455), .B(n4454), .CI(n4453), .CO(n5054), .S(n5052) );
CMPR32X2TS U5083 ( .A(n4458), .B(n4457), .C(n4456), .CO(n5066), .S(n4492) );
CMPR32X2TS U5084 ( .A(n4464), .B(n4463), .C(n4462), .CO(n5129), .S(n4495) );
XNOR2X1TS U5085 ( .A(n3986), .B(n5180), .Y(n5090) );
OAI22X1TS U5086 ( .A0(n6125), .A1(n4468), .B0(n6063), .B1(n5090), .Y(n5107)
);
XNOR2X1TS U5087 ( .A(n3741), .B(n4469), .Y(n5145) );
OAI22X1TS U5088 ( .A0(n6184), .A1(n4470), .B0(n58), .B1(n5145), .Y(n5106) );
NOR2X1TS U5089 ( .A(n5721), .B(n4477), .Y(n5230) );
OAI22X1TS U5090 ( .A0(n4479), .A1(n4478), .B0(n51), .B1(n5119), .Y(n5147) );
XNOR2X1TS U5091 ( .A(n4480), .B(n80), .Y(n5087) );
OAI22X1TS U5092 ( .A0(n5294), .A1(n4481), .B0(n5233), .B1(n5087), .Y(n5146)
);
XNOR2X1TS U5093 ( .A(n118), .B(n6047), .Y(n5083) );
OAI22X1TS U5094 ( .A0(n6542), .A1(n4485), .B0(n138), .B1(n5083), .Y(n5081)
);
XNOR2X1TS U5095 ( .A(n50), .B(n6290), .Y(n5088) );
OAI22X1TS U5096 ( .A0(n5373), .A1(n4486), .B0(n5371), .B1(n5088), .Y(n5080)
);
XNOR2X1TS U5097 ( .A(n7049), .B(n4487), .Y(n5113) );
OAI22X1TS U5098 ( .A0(n7093), .A1(n4488), .B0(n5115), .B1(n5113), .Y(n5079)
);
ADDFHX2TS U5099 ( .A(n4491), .B(n4490), .CI(n4489), .CO(n5153), .S(n4453) );
CMPR32X2TS U5100 ( .A(n4500), .B(n4499), .C(n4498), .CO(n5078), .S(n4462) );
CMPR32X2TS U5101 ( .A(n4506), .B(n4505), .C(n4504), .CO(n5076), .S(n4520) );
XNOR2X1TS U5102 ( .A(n5187), .B(Data_B_i[30]), .Y(n5089) );
OAI22X1TS U5103 ( .A0(n6590), .A1(n4513), .B0(n5580), .B1(n5089), .Y(n5138)
);
XNOR2X1TS U5104 ( .A(n5368), .B(n6193), .Y(n5100) );
OAI22X1TS U5105 ( .A0(n66), .A1(n4514), .B0(n5517), .B1(n5100), .Y(n5137) );
BUFX3TS U5106 ( .A(n7045), .Y(n6528) );
XNOR2X1TS U5107 ( .A(n93), .B(n5190), .Y(n5084) );
OAI22X1TS U5108 ( .A0(n5085), .A1(n4515), .B0(n6528), .B1(n5084), .Y(n5136)
);
XNOR2X1TS U5109 ( .A(n6311), .B(Data_B_i[34]), .Y(n5112) );
OAI22X1TS U5110 ( .A0(n6392), .A1(n4516), .B0(n5267), .B1(n5112), .Y(n5111)
);
XNOR2X1TS U5111 ( .A(n4388), .B(n6026), .Y(n5104) );
OAI22X1TS U5112 ( .A0(n5667), .A1(n4517), .B0(n109), .B1(n5104), .Y(n5110)
);
XNOR2X1TS U5113 ( .A(n1660), .B(n6055), .Y(n5102) );
OAI22X1TS U5114 ( .A0(n4575), .A1(n4519), .B0(n4518), .B1(n5102), .Y(n5109)
);
CMPR32X2TS U5115 ( .A(n4522), .B(n4521), .C(n4520), .CO(n5093), .S(n4456) );
XNOR2X1TS U5116 ( .A(Data_A_i[49]), .B(n5335), .Y(n5122) );
OAI22X1TS U5117 ( .A0(n123), .A1(n4529), .B0(n6480), .B1(n5122), .Y(n5099)
);
XNOR2X1TS U5118 ( .A(n5427), .B(n5814), .Y(n5141) );
OAI22X1TS U5119 ( .A0(n128), .A1(n4530), .B0(n5758), .B1(n5141), .Y(n5098)
);
XNOR2X1TS U5120 ( .A(n6388), .B(n5539), .Y(n5123) );
OAI22X1TS U5121 ( .A0(n6401), .A1(n4531), .B0(n6709), .B1(n5123), .Y(n5097)
);
XNOR2X1TS U5122 ( .A(Data_A_i[29]), .B(n5383), .Y(n5139) );
OAI22X1TS U5123 ( .A0(n6003), .A1(n4533), .B0(n5226), .B1(n5139), .Y(n5151)
);
XNOR2X1TS U5124 ( .A(n5627), .B(Data_B_i[26]), .Y(n5140) );
OAI22X1TS U5125 ( .A0(n6340), .A1(n4534), .B0(n6316), .B1(n5140), .Y(n5150)
);
XNOR2X1TS U5126 ( .A(n5185), .B(n5547), .Y(n5121) );
OAI22X1TS U5127 ( .A0(n4536), .A1(n4535), .B0(n1385), .B1(n5121), .Y(n5149)
);
NOR2X2TS U5128 ( .A(n5054), .B(n5053), .Y(n7524) );
NOR2X2TS U5129 ( .A(n7515), .B(n7524), .Y(n5056) );
ADDFHX2TS U5130 ( .A(n4548), .B(n4547), .CI(n4546), .CO(n4552), .S(n4555) );
ADDFHX2TS U5131 ( .A(n4554), .B(n4553), .CI(n4552), .CO(n5051), .S(n5050) );
ADDFHX4TS U5132 ( .A(n4557), .B(n4556), .CI(n4555), .CO(n5049), .S(n5048) );
NOR2X4TS U5133 ( .A(n5050), .B(n5049), .Y(n7506) );
NOR2X4TS U5134 ( .A(n7500), .B(n7506), .Y(n7511) );
OAI22X1TS U5135 ( .A0(n104), .A1(n4563), .B0(n4562), .B1(n4561), .Y(n4588)
);
OAI22X1TS U5136 ( .A0(n5702), .A1(n4567), .B0(n4566), .B1(n4565), .Y(n4587)
);
OAI22X1TS U5137 ( .A0(n4571), .A1(n4570), .B0(n111), .B1(n4568), .Y(n4586)
);
OAI22X1TS U5138 ( .A0(n2633), .A1(n4574), .B0(n4573), .B1(n4572), .Y(n4822)
);
OAI22X1TS U5139 ( .A0(n4582), .A1(n4581), .B0(n95), .B1(n4580), .Y(n4820) );
OAI22X1TS U5140 ( .A0(n102), .A1(n4594), .B0(n48), .B1(n4592), .Y(n4680) );
XNOR2X1TS U5141 ( .A(n6343), .B(n5114), .Y(n4634) );
OAI22X1TS U5142 ( .A0(n4635), .A1(n4597), .B0(n137), .B1(n4634), .Y(n4679)
);
XNOR2X1TS U5143 ( .A(n6238), .B(n5289), .Y(n4638) );
OAI22X1TS U5144 ( .A0(n4599), .A1(n4598), .B0(n5659), .B1(n4638), .Y(n4678)
);
OAI22X1TS U5145 ( .A0(n6125), .A1(n4607), .B0(n5390), .B1(n4606), .Y(n4789)
);
OAI22X1TS U5146 ( .A0(n4610), .A1(n4609), .B0(n5454), .B1(n4608), .Y(n4788)
);
OAI22X1TS U5147 ( .A0(n4614), .A1(n4613), .B0(n4612), .B1(n4611), .Y(n4787)
);
CMPR32X2TS U5148 ( .A(n4620), .B(n4619), .C(n4618), .CO(n4626), .S(n4829) );
CMPR32X2TS U5149 ( .A(n4632), .B(n4631), .C(n4630), .CO(n4651), .S(n4655) );
OAI22X1TS U5150 ( .A0(n73), .A1(n4634), .B0(n5842), .B1(n4633), .Y(n4765) );
XNOR2X1TS U5151 ( .A(Data_A_i[17]), .B(n5750), .Y(n4737) );
OAI22X1TS U5152 ( .A0(n4479), .A1(n4737), .B0(n51), .B1(n4636), .Y(n4764) );
OAI22X1TS U5153 ( .A0(n5717), .A1(n4638), .B0(n6308), .B1(n4637), .Y(n4763)
);
CMPR32X2TS U5154 ( .A(n4662), .B(n4661), .C(n4660), .CO(n4947), .S(n4654) );
CMPR32X2TS U5155 ( .A(n4671), .B(n4670), .C(n4669), .CO(n4843), .S(n4835) );
OAI22X1TS U5156 ( .A0(n43), .A1(n4683), .B0(n84), .B1(n4681), .Y(n4828) );
OAI22X1TS U5157 ( .A0(n6590), .A1(n4687), .B0(n4686), .B1(n4685), .Y(n4827)
);
OAI22X1TS U5158 ( .A0(n5942), .A1(n4690), .B0(n5432), .B1(n4689), .Y(n4826)
);
CMPR32X2TS U5159 ( .A(n4697), .B(n4696), .C(n4695), .CO(n4804), .S(n4805) );
OAI22X1TS U5160 ( .A0(n5235), .A1(n4703), .B0(n4702), .B1(n4701), .Y(n4724)
);
OAI22X1TS U5161 ( .A0(n5621), .A1(n4712), .B0(n6251), .B1(n4711), .Y(n4792)
);
OAI22X1TS U5162 ( .A0(n4716), .A1(n4715), .B0(n4714), .B1(n4713), .Y(n4791)
);
OAI22X1TS U5163 ( .A0(n6511), .A1(n4718), .B0(n6706), .B1(n4717), .Y(n4790)
);
OAI22X1TS U5164 ( .A0(n4479), .A1(n4738), .B0(n45), .B1(n4737), .Y(n4825) );
OAI22X1TS U5165 ( .A0(n55), .A1(n4741), .B0(n4740), .B1(n4739), .Y(n4824) );
OAI22X1TS U5166 ( .A0(n69), .A1(n4744), .B0(n4743), .B1(n4742), .Y(n4823) );
OAI22X1TS U5167 ( .A0(n130), .A1(n4747), .B0(n4746), .B1(n4745), .Y(n4762)
);
OAI22X1TS U5168 ( .A0(n6530), .A1(n4749), .B0(n5753), .B1(n4748), .Y(n4761)
);
CMPR32X2TS U5169 ( .A(n4768), .B(n4767), .C(n4766), .CO(n4621), .S(n4769) );
CMPR32X2TS U5170 ( .A(n4792), .B(n4791), .C(n4790), .CO(n4777), .S(n4817) );
CMPR32X2TS U5171 ( .A(n4828), .B(n4827), .C(n4826), .CO(n4851), .S(n4692) );
ADDFHX1TS U5172 ( .A(n4837), .B(n4836), .CI(n4835), .CO(n4905), .S(n4891) );
ADDFHX4TS U5173 ( .A(n4871), .B(n4870), .CI(n4869), .CO(n4880), .S(n4911) );
ADDFHX2TS U5174 ( .A(n4874), .B(n4873), .CI(n4872), .CO(n4954), .S(n4879) );
ADDFHX2TS U5175 ( .A(n4877), .B(n4876), .CI(n4875), .CO(n4959), .S(n4878) );
ADDFHX1TS U5176 ( .A(n4880), .B(n4879), .CI(n4878), .CO(n4970), .S(n4908) );
XOR2X4TS U5177 ( .A(n4884), .B(n4883), .Y(n4907) );
ADDFHX2TS U5178 ( .A(n4899), .B(n4898), .CI(n4897), .CO(n4894), .S(n4926) );
ADDFHX1TS U5179 ( .A(n4905), .B(n4904), .CI(n4903), .CO(n4909), .S(n4924) );
ADDFHX2TS U5180 ( .A(n4908), .B(n4907), .CI(n4906), .CO(n5021), .S(n5020) );
ADDFHX2TS U5181 ( .A(n4923), .B(n4922), .CI(n4921), .CO(n4906), .S(n4936) );
ADDFHX2TS U5182 ( .A(n4935), .B(n4934), .CI(n4933), .CO(n5015), .S(n3336) );
NOR2X2TS U5183 ( .A(n5016), .B(n5015), .Y(n7389) );
ADDFHX2TS U5184 ( .A(n4941), .B(n4940), .CI(n4939), .CO(n5018), .S(n5016) );
ADDFHX2TS U5185 ( .A(n4944), .B(n4943), .CI(n4942), .CO(n5025), .S(n5022) );
XNOR2X4TS U5186 ( .A(n4985), .B(n4986), .Y(n4960) );
XNOR2X4TS U5187 ( .A(n4960), .B(n4983), .Y(n4979) );
ADDFHX2TS U5188 ( .A(n4972), .B(n4971), .CI(n4970), .CO(n4974), .S(n4942) );
XOR2X4TS U5189 ( .A(n4973), .B(n4974), .Y(n5026) );
NOR2X2TS U5190 ( .A(n5025), .B(n5026), .Y(n7594) );
OAI2BB1X4TS U5191 ( .A0N(n4979), .A1N(n4978), .B0(n4977), .Y(n5027) );
ADDFHX2TS U5192 ( .A(n4989), .B(n4988), .CI(n4987), .CO(n5005), .S(n4985) );
NOR2X4TS U5193 ( .A(n5027), .B(n5028), .Y(n7569) );
XNOR2X4TS U5194 ( .A(n5002), .B(n5001), .Y(n5013) );
ADDFHX2TS U5195 ( .A(n5005), .B(n5004), .CI(n5003), .CO(n5012), .S(n5006) );
ADDFHX2TS U5196 ( .A(n5008), .B(n5007), .CI(n5006), .CO(n5029), .S(n5028) );
NOR2X4TS U5197 ( .A(n5030), .B(n5029), .Y(n7627) );
ADDFHX4TS U5198 ( .A(n5014), .B(n5013), .CI(n5012), .CO(n5031), .S(n5030) );
NAND2X2TS U5199 ( .A(n5020), .B(n5019), .Y(n7618) );
NAND2X1TS U5200 ( .A(n5022), .B(n5021), .Y(n7604) );
AOI21X4TS U5201 ( .A0(n7615), .A1(n5024), .B0(n5023), .Y(n7575) );
NAND2X1TS U5202 ( .A(n5028), .B(n5027), .Y(n7570) );
OAI21X2TS U5203 ( .A0(n7595), .A1(n7569), .B0(n7570), .Y(n7576) );
NAND2X2TS U5204 ( .A(n5030), .B(n5029), .Y(n7628) );
NAND2X2TS U5205 ( .A(n5032), .B(n5031), .Y(n7581) );
OAI21X2TS U5206 ( .A0(n7628), .A1(n7580), .B0(n7581), .Y(n5033) );
OAI21X4TS U5207 ( .A0(n7575), .A1(n5036), .B0(n5035), .Y(n7491) );
NAND2X2TS U5208 ( .A(n5038), .B(n5037), .Y(n7589) );
NAND2X2TS U5209 ( .A(n5040), .B(n5039), .Y(n7563) );
OAI21X4TS U5210 ( .A0(n7589), .A1(n7562), .B0(n7563), .Y(n7539) );
OAI21X2TS U5211 ( .A0(n7545), .A1(n7534), .B0(n7546), .Y(n5045) );
AOI21X4TS U5212 ( .A0(n7539), .A1(n5046), .B0(n5045), .Y(n7550) );
NAND2X2TS U5213 ( .A(n5048), .B(n5047), .Y(n7554) );
NAND2X1TS U5214 ( .A(n5050), .B(n5049), .Y(n7507) );
OAI21X2TS U5215 ( .A0(n7554), .A1(n7506), .B0(n7507), .Y(n7492) );
NAND2X1TS U5216 ( .A(n5052), .B(n5051), .Y(n7514) );
NAND2X1TS U5217 ( .A(n5054), .B(n5053), .Y(n7525) );
OAI21X2TS U5218 ( .A0(n7550), .A1(n5058), .B0(n5057), .Y(n5059) );
AOI21X4TS U5219 ( .A0(n7491), .A1(n5060), .B0(n5059), .Y(n5061) );
OAI21X4TS U5220 ( .A0(n7387), .A1(n5062), .B0(n5061), .Y(n5063) );
CMPR32X2TS U5221 ( .A(n5081), .B(n5080), .C(n5079), .CO(n5209), .S(n5073) );
XNOR2X1TS U5222 ( .A(n5082), .B(n6121), .Y(n5192) );
OAI22X1TS U5223 ( .A0(n6542), .A1(n5083), .B0(n6466), .B1(n5192), .Y(n5212)
);
XNOR2X1TS U5224 ( .A(n93), .B(n5289), .Y(n5189) );
OAI22X1TS U5225 ( .A0(n5085), .A1(n5084), .B0(n6528), .B1(n5189), .Y(n5211)
);
XNOR2X1TS U5226 ( .A(n5086), .B(n6128), .Y(n5234) );
OAI22X1TS U5227 ( .A0(n5294), .A1(n5087), .B0(n5233), .B1(n5234), .Y(n5210)
);
XNOR2X1TS U5228 ( .A(Data_A_i[21]), .B(n6989), .Y(n5232) );
OAI22X1TS U5229 ( .A0(n5373), .A1(n5088), .B0(n5371), .B1(n5232), .Y(n5225)
);
XNOR2X1TS U5230 ( .A(n5187), .B(Data_B_i[31]), .Y(n5188) );
OAI22X1TS U5231 ( .A0(n4688), .A1(n5089), .B0(n5580), .B1(n5188), .Y(n5224)
);
XNOR2X1TS U5232 ( .A(n1814), .B(n5278), .Y(n5182) );
OAI22X1TS U5233 ( .A0(n46), .A1(n5090), .B0(n91), .B1(n5182), .Y(n5223) );
XNOR2X1TS U5234 ( .A(n5368), .B(n6232), .Y(n5219) );
OAI22X1TS U5235 ( .A0(n67), .A1(n5100), .B0(n141), .B1(n5219), .Y(n5215) );
XNOR2X1TS U5236 ( .A(n4076), .B(n5940), .Y(n5179) );
XNOR2X1TS U5237 ( .A(n1468), .B(n6347), .Y(n5183) );
OAI22X1TS U5238 ( .A0(n5667), .A1(n5104), .B0(n108), .B1(n5183), .Y(n5213)
);
CMPR32X2TS U5239 ( .A(n5111), .B(n5110), .C(n5109), .CO(n5175), .S(n5130) );
XNOR2X1TS U5240 ( .A(n6311), .B(Data_B_i[35]), .Y(n5216) );
OAI22X1TS U5241 ( .A0(n73), .A1(n5112), .B0(n5267), .B1(n5216), .Y(n5178) );
XNOR2X1TS U5242 ( .A(n6531), .B(n5114), .Y(n5191) );
INVX2TS U5243 ( .A(n5118), .Y(n5177) );
BUFX3TS U5244 ( .A(n5494), .Y(n6369) );
XNOR2X1TS U5245 ( .A(n5185), .B(n5579), .Y(n5186) );
OAI22X1TS U5246 ( .A0(n6369), .A1(n5121), .B0(n5659), .B1(n5186), .Y(n5222)
);
XNOR2X1TS U5247 ( .A(Data_A_i[49]), .B(n5434), .Y(n5218) );
OAI22X1TS U5248 ( .A0(n122), .A1(n5122), .B0(n6480), .B1(n5218), .Y(n5221)
);
XNOR2X1TS U5249 ( .A(n6388), .B(n5582), .Y(n5193) );
OAI22X1TS U5250 ( .A0(n6401), .A1(n5123), .B0(n6769), .B1(n5193), .Y(n5220)
);
CMPR32X2TS U5251 ( .A(n5132), .B(n5131), .C(n5130), .CO(n5241), .S(n5124) );
CMPR32X2TS U5252 ( .A(n5135), .B(n5134), .C(n5133), .CO(n5240), .S(n5127) );
XNOR2X1TS U5253 ( .A(Data_A_i[29]), .B(n5465), .Y(n5227) );
OAI22X1TS U5254 ( .A0(n6003), .A1(n5139), .B0(n5226), .B1(n5227), .Y(n5197)
);
XNOR2X1TS U5255 ( .A(n5627), .B(n5752), .Y(n5194) );
OAI22X1TS U5256 ( .A0(n6340), .A1(n5140), .B0(n6044), .B1(n5194), .Y(n5196)
);
XNOR2X1TS U5257 ( .A(n5427), .B(Data_B_i[29]), .Y(n5184) );
OAI22X1TS U5258 ( .A0(n5702), .A1(n5141), .B0(n5758), .B1(n5184), .Y(n5195)
);
XNOR2X1TS U5259 ( .A(n1860), .B(n5143), .Y(n5181) );
OAI22X1TS U5260 ( .A0(n6252), .A1(n5145), .B0(n5144), .B1(n5181), .Y(n5228)
);
CMPR32X2TS U5261 ( .A(n5151), .B(n5150), .C(n5149), .CO(n5198), .S(n5094) );
ADDFHX2TS U5262 ( .A(n5154), .B(n5153), .CI(n5152), .CO(n6774), .S(n5053) );
ADDFHX2TS U5263 ( .A(n5160), .B(n5159), .CI(n5158), .CO(n5324), .S(n5161) );
XNOR2X1TS U5264 ( .A(n1660), .B(n6026), .Y(n5264) );
OAI22X1TS U5265 ( .A0(n39), .A1(n5179), .B0(n134), .B1(n5264), .Y(n5312) );
XNOR2X1TS U5266 ( .A(n6129), .B(n5180), .Y(n5279) );
OAI22X1TS U5267 ( .A0(n4337), .A1(n5181), .B0(n58), .B1(n5279), .Y(n5311) );
XNOR2X1TS U5268 ( .A(n3986), .B(n5383), .Y(n5252) );
OAI22X1TS U5269 ( .A0(n146), .A1(n5182), .B0(n5390), .B1(n5252), .Y(n5310)
);
XNOR2X1TS U5270 ( .A(n4388), .B(n6193), .Y(n5272) );
OAI22X1TS U5271 ( .A0(n5667), .A1(n5183), .B0(n108), .B1(n5272), .Y(n5263)
);
XNOR2X1TS U5272 ( .A(n5427), .B(Data_B_i[30]), .Y(n5265) );
XNOR2X1TS U5273 ( .A(n5185), .B(n5811), .Y(n5254) );
OAI22X1TS U5274 ( .A0(n6369), .A1(n5186), .B0(n1385), .B1(n5254), .Y(n5261)
);
XNOR2X1TS U5275 ( .A(n5187), .B(n6047), .Y(n5285) );
OAI22X1TS U5276 ( .A0(n113), .A1(n5188), .B0(n5580), .B1(n5285), .Y(n5284)
);
BUFX3TS U5277 ( .A(n6485), .Y(n6583) );
XNOR2X1TS U5278 ( .A(Data_A_i[51]), .B(n5335), .Y(n5286) );
OAI22X1TS U5279 ( .A0(n6583), .A1(n5189), .B0(n6528), .B1(n5286), .Y(n5283)
);
XNOR2X1TS U5280 ( .A(n6531), .B(n5190), .Y(n5290) );
OAI22X1TS U5281 ( .A0(n5291), .A1(n5191), .B0(n6605), .B1(n5290), .Y(n5282)
);
XNOR2X1TS U5282 ( .A(n118), .B(Data_B_i[34]), .Y(n5288) );
OAI22X1TS U5283 ( .A0(n4691), .A1(n5192), .B0(n5432), .B1(n5288), .Y(n5277)
);
XNOR2X1TS U5284 ( .A(n5692), .B(Data_B_i[26]), .Y(n5273) );
XNOR2X1TS U5285 ( .A(n5627), .B(n5814), .Y(n5274) );
OAI22X1TS U5286 ( .A0(n6340), .A1(n5194), .B0(n5884), .B1(n5274), .Y(n5275)
);
CMPR32X2TS U5287 ( .A(n5197), .B(n5196), .C(n5195), .CO(n5269), .S(n5237) );
NAND2X1TS U5288 ( .A(n5203), .B(n5201), .Y(n5206) );
NAND2X1TS U5289 ( .A(n5202), .B(n5201), .Y(n5205) );
NAND2X1TS U5290 ( .A(n5203), .B(n5202), .Y(n5204) );
NAND3X1TS U5291 ( .A(n5206), .B(n5205), .C(n5204), .Y(n5247) );
CMPR32X2TS U5292 ( .A(n5209), .B(n5208), .C(n5207), .CO(n5246), .S(n5170) );
XNOR2X1TS U5293 ( .A(n6311), .B(Data_B_i[36]), .Y(n5268) );
OAI22X1TS U5294 ( .A0(n73), .A1(n5216), .B0(n6391), .B1(n5268), .Y(n5309) );
XNOR2X1TS U5295 ( .A(Data_A_i[49]), .B(n5539), .Y(n5287) );
OAI22X1TS U5296 ( .A0(n123), .A1(n5218), .B0(n6480), .B1(n5287), .Y(n5308)
);
XNOR2X1TS U5297 ( .A(n5368), .B(n6290), .Y(n5281) );
OAI22X1TS U5298 ( .A0(n67), .A1(n5219), .B0(n3425), .B1(n5281), .Y(n5307) );
CMPR32X2TS U5299 ( .A(n5222), .B(n5221), .C(n5220), .CO(n5306), .S(n5173) );
XNOR2X1TS U5300 ( .A(n5800), .B(n5525), .Y(n5250) );
OAI22X1TS U5301 ( .A0(n131), .A1(n5227), .B0(n5226), .B1(n5250), .Y(n5315)
);
NOR2X1TS U5302 ( .A(n5721), .B(n5231), .Y(n5367) );
XNOR2X1TS U5303 ( .A(Data_A_i[21]), .B(n79), .Y(n5280) );
OAI22X1TS U5304 ( .A0(n148), .A1(n5234), .B0(n5233), .B1(n5292), .Y(n5258)
);
CMPR32X2TS U5305 ( .A(n5238), .B(n5237), .C(n5236), .CO(n5316), .S(n5239) );
NAND2BX4TS U5306 ( .AN(n6776), .B(n5242), .Y(n7462) );
BUFX3TS U5307 ( .A(n5249), .Y(n5943) );
XNOR2X1TS U5308 ( .A(Data_A_i[29]), .B(n5619), .Y(n5348) );
OAI22X1TS U5309 ( .A0(n5945), .A1(n5250), .B0(n5943), .B1(n5348), .Y(n5364)
);
XNOR2X1TS U5310 ( .A(n6012), .B(n5465), .Y(n5391) );
OAI22X1TS U5311 ( .A0(n5451), .A1(n5252), .B0(n5390), .B1(n5391), .Y(n5363)
);
XNOR2X1TS U5312 ( .A(n6185), .B(Data_B_i[39]), .Y(n5386) );
OAI22X1TS U5313 ( .A0(n6369), .A1(n5254), .B0(n1385), .B1(n5386), .Y(n5365)
);
CMPR32X2TS U5314 ( .A(n5263), .B(n5262), .C(n5261), .CO(n5378), .S(n5255) );
XNOR2X1TS U5315 ( .A(n98), .B(n6347), .Y(n5340) );
OAI22X1TS U5316 ( .A0(n2633), .A1(n5264), .B0(n134), .B1(n5340), .Y(n5389)
);
XNOR2X1TS U5317 ( .A(n5427), .B(Data_B_i[31]), .Y(n5392) );
OAI22X1TS U5318 ( .A0(n5702), .A1(n5265), .B0(n5758), .B1(n5392), .Y(n5388)
);
BUFX3TS U5319 ( .A(n5266), .Y(n6392) );
XNOR2X1TS U5320 ( .A(n6311), .B(n77), .Y(n5338) );
OAI22X1TS U5321 ( .A0(n5217), .A1(n5268), .B0(n5267), .B1(n5338), .Y(n5387)
);
XNOR2X1TS U5322 ( .A(n4085), .B(n6232), .Y(n5339) );
OAI22X1TS U5323 ( .A0(n5667), .A1(n5272), .B0(n109), .B1(n5339), .Y(n5346)
);
XNOR2X1TS U5324 ( .A(n5692), .B(n5752), .Y(n5349) );
OAI22X1TS U5325 ( .A0(n6401), .A1(n5273), .B0(n6769), .B1(n5349), .Y(n5345)
);
XNOR2X1TS U5326 ( .A(n5627), .B(Data_B_i[29]), .Y(n5393) );
OAI22X1TS U5327 ( .A0(n5838), .A1(n5274), .B0(n5884), .B1(n5393), .Y(n5344)
);
XNOR2X1TS U5328 ( .A(n3741), .B(n5278), .Y(n5384) );
OAI22X1TS U5329 ( .A0(n6184), .A1(n5279), .B0(n58), .B1(n5384), .Y(n5333) );
XNOR2X1TS U5330 ( .A(Data_A_i[21]), .B(n6128), .Y(n5372) );
OAI22X1TS U5331 ( .A0(n5373), .A1(n5280), .B0(n5371), .B1(n5372), .Y(n5332)
);
XNOR2X1TS U5332 ( .A(n5368), .B(n6989), .Y(n5369) );
OAI22X1TS U5333 ( .A0(n8), .A1(n5281), .B0(n141), .B1(n5369), .Y(n5331) );
CMPR32X2TS U5334 ( .A(n5284), .B(n5283), .C(n5282), .CO(n5330), .S(n5271) );
XNOR2X1TS U5335 ( .A(Data_A_i[41]), .B(n6121), .Y(n5334) );
OAI22X1TS U5336 ( .A0(n6525), .A1(n5285), .B0(n5580), .B1(n5334), .Y(n5343)
);
XNOR2X1TS U5337 ( .A(n4069), .B(n5434), .Y(n5337) );
OAI22X1TS U5338 ( .A0(n6583), .A1(n5286), .B0(n6528), .B1(n5337), .Y(n5342)
);
XNOR2X1TS U5339 ( .A(Data_A_i[49]), .B(n5582), .Y(n5347) );
OAI22X1TS U5340 ( .A0(n123), .A1(n5287), .B0(n6480), .B1(n5347), .Y(n5341)
);
XNOR2X1TS U5341 ( .A(n119), .B(Data_B_i[35]), .Y(n5385) );
OAI22X1TS U5342 ( .A0(n6542), .A1(n5288), .B0(n138), .B1(n5385), .Y(n5376)
);
XNOR2X1TS U5343 ( .A(n6531), .B(n5289), .Y(n5336) );
OAI22X1TS U5344 ( .A0(n6530), .A1(n5290), .B0(n6605), .B1(n5336), .Y(n5375)
);
CMPR32X2TS U5345 ( .A(n5303), .B(n5302), .C(n5301), .CO(n5352), .S(n5318) );
CMPR32X2TS U5346 ( .A(n5306), .B(n5305), .C(n5304), .CO(n5351), .S(n5317) );
CMPR32X2TS U5347 ( .A(n5309), .B(n5308), .C(n5307), .CO(n5396), .S(n5301) );
INVX2TS U5348 ( .A(n6780), .Y(n7137) );
NAND2X4TS U5349 ( .A(n7462), .B(n7137), .Y(n6782) );
CMPR32X2TS U5350 ( .A(n5330), .B(n5329), .C(n5328), .CO(n5410), .S(n5325) );
CMPR32X2TS U5351 ( .A(n5333), .B(n5332), .C(n5331), .CO(n5441), .S(n5380) );
XNOR2X1TS U5352 ( .A(n82), .B(Data_B_i[34]), .Y(n5417) );
XNOR2X1TS U5353 ( .A(n6531), .B(n5335), .Y(n5435) );
OAI22X1TS U5354 ( .A0(n6365), .A1(n5336), .B0(n6605), .B1(n5435), .Y(n5412)
);
XNOR2X1TS U5355 ( .A(Data_A_i[51]), .B(n5539), .Y(n5429) );
OAI22X1TS U5356 ( .A0(n6583), .A1(n5337), .B0(n6528), .B1(n5429), .Y(n5411)
);
XNOR2X1TS U5357 ( .A(n6311), .B(Data_B_i[38]), .Y(n5452) );
OAI22X1TS U5358 ( .A0(n73), .A1(n5338), .B0(n6391), .B1(n5452), .Y(n5464) );
XNOR2X1TS U5359 ( .A(n4388), .B(n6290), .Y(n5420) );
OAI22X1TS U5360 ( .A0(n5667), .A1(n5339), .B0(n109), .B1(n5420), .Y(n5463)
);
XNOR2X1TS U5361 ( .A(n5760), .B(n6193), .Y(n5430) );
OAI22X1TS U5362 ( .A0(n5798), .A1(n5340), .B0(n134), .B1(n5430), .Y(n5462)
);
XNOR2X1TS U5363 ( .A(n5913), .B(Data_B_i[26]), .Y(n5455) );
OAI22X1TS U5364 ( .A0(n122), .A1(n5347), .B0(n6480), .B1(n5455), .Y(n5426)
);
XNOR2X1TS U5365 ( .A(n5800), .B(n5697), .Y(n5453) );
OAI22X1TS U5366 ( .A0(n130), .A1(n5348), .B0(n5943), .B1(n5453), .Y(n5425)
);
XNOR2X1TS U5367 ( .A(n5692), .B(n5814), .Y(n5457) );
OAI22X1TS U5368 ( .A0(n6401), .A1(n5349), .B0(n6769), .B1(n5457), .Y(n5424)
);
CMPR32X2TS U5369 ( .A(n5364), .B(n5363), .C(n5362), .CO(n5477), .S(n5361) );
CMPR32X2TS U5370 ( .A(n5367), .B(n5366), .C(n5365), .CO(n5474), .S(n5362) );
XNOR2X1TS U5371 ( .A(n5368), .B(n79), .Y(n5419) );
NOR2X1TS U5372 ( .A(n5721), .B(n5370), .Y(n5500) );
OAI22X1TS U5373 ( .A0(n5373), .A1(n5372), .B0(n5371), .B1(n5436), .Y(n5469)
);
CMPR32X2TS U5374 ( .A(n5382), .B(n5381), .C(n5380), .CO(n5480), .S(n5326) );
XNOR2X1TS U5375 ( .A(n6066), .B(n5383), .Y(n5466) );
OAI22X1TS U5376 ( .A0(n4337), .A1(n5384), .B0(n4420), .B1(n5466), .Y(n5416)
);
XNOR2X1TS U5377 ( .A(n119), .B(n5547), .Y(n5433) );
OAI22X1TS U5378 ( .A0(n5817), .A1(n5385), .B0(n139), .B1(n5433), .Y(n5415)
);
XNOR2X1TS U5379 ( .A(n5715), .B(n5496), .Y(n5468) );
OAI22X1TS U5380 ( .A0(n6369), .A1(n5386), .B0(n1385), .B1(n5468), .Y(n5414)
);
XNOR2X1TS U5381 ( .A(n106), .B(n5525), .Y(n5450) );
OAI22X1TS U5382 ( .A0(n46), .A1(n5391), .B0(n5390), .B1(n5450), .Y(n5447) );
XNOR2X1TS U5383 ( .A(Data_A_i[43]), .B(n6047), .Y(n5428) );
OAI22X1TS U5384 ( .A0(n5702), .A1(n5392), .B0(n5758), .B1(n5428), .Y(n5446)
);
XNOR2X1TS U5385 ( .A(n5627), .B(Data_B_i[30]), .Y(n5448) );
OAI22X1TS U5386 ( .A0(n5838), .A1(n5393), .B0(n6706), .B1(n5448), .Y(n5445)
);
CMPR32X2TS U5387 ( .A(n5396), .B(n5395), .C(n5394), .CO(n5478), .S(n5350) );
XOR2X4TS U5388 ( .A(n5397), .B(n5460), .Y(n5405) );
OR2X4TS U5389 ( .A(n6784), .B(n6783), .Y(n7393) );
XNOR2X1TS U5390 ( .A(n82), .B(Data_B_i[35]), .Y(n5548) );
OAI22X1TS U5391 ( .A0(n6148), .A1(n5417), .B0(n5580), .B1(n5548), .Y(n5493)
);
XNOR2X1TS U5392 ( .A(n5418), .B(n6128), .Y(n5518) );
OAI22X1TS U5393 ( .A0(n66), .A1(n5419), .B0(n141), .B1(n5518), .Y(n5492) );
XNOR2X1TS U5394 ( .A(n4085), .B(n6989), .Y(n5521) );
OAI22X1TS U5395 ( .A0(n5667), .A1(n5420), .B0(n108), .B1(n5521), .Y(n5491)
);
CMPR32X2TS U5396 ( .A(n5426), .B(n5425), .C(n5424), .CO(n5560), .S(n5442) );
XNOR2X1TS U5397 ( .A(n5427), .B(n6121), .Y(n5537) );
OAI22X1TS U5398 ( .A0(n5702), .A1(n5428), .B0(n5758), .B1(n5537), .Y(n5543)
);
XNOR2X1TS U5399 ( .A(Data_A_i[51]), .B(n5582), .Y(n5551) );
OAI22X1TS U5400 ( .A0(n6583), .A1(n5429), .B0(n6528), .B1(n5551), .Y(n5542)
);
XNOR2X1TS U5401 ( .A(n1660), .B(n6232), .Y(n5538) );
OAI22X1TS U5402 ( .A0(n5798), .A1(n5430), .B0(n135), .B1(n5538), .Y(n5541)
);
XNOR2X1TS U5403 ( .A(n119), .B(n5579), .Y(n5530) );
OAI22X1TS U5404 ( .A0(n4691), .A1(n5433), .B0(n5432), .B1(n5530), .Y(n5533)
);
XNOR2X1TS U5405 ( .A(n6531), .B(n5434), .Y(n5540) );
OAI22X1TS U5406 ( .A0(n6530), .A1(n5435), .B0(n6605), .B1(n5540), .Y(n5532)
);
CMPR32X2TS U5407 ( .A(n5444), .B(n5443), .C(n5442), .CO(n5514), .S(n5408) );
CMPR32X2TS U5408 ( .A(n5447), .B(n5446), .C(n5445), .CO(n5554), .S(n5421) );
XNOR2X1TS U5409 ( .A(n5627), .B(Data_B_i[31]), .Y(n5528) );
OAI22X1TS U5410 ( .A0(n5838), .A1(n5448), .B0(n6706), .B1(n5528), .Y(n5524)
);
XNOR2X1TS U5411 ( .A(n1814), .B(n5619), .Y(n5545) );
OAI22X1TS U5412 ( .A0(n5451), .A1(n5450), .B0(n90), .B1(n5545), .Y(n5523) );
XNOR2X1TS U5413 ( .A(n6311), .B(Data_B_i[39]), .Y(n5497) );
OAI22X1TS U5414 ( .A0(n74), .A1(n5452), .B0(n6391), .B1(n5497), .Y(n5522) );
XNOR2X1TS U5415 ( .A(n5800), .B(n5718), .Y(n5550) );
OAI22X1TS U5416 ( .A0(n5251), .A1(n5453), .B0(n5943), .B1(n5550), .Y(n5536)
);
XNOR2X1TS U5417 ( .A(n5913), .B(n5752), .Y(n5544) );
OAI22X1TS U5418 ( .A0(n5456), .A1(n5455), .B0(n5454), .B1(n5544), .Y(n5535)
);
XNOR2X1TS U5419 ( .A(n5692), .B(Data_B_i[29]), .Y(n5546) );
OAI22X1TS U5420 ( .A0(n5980), .A1(n5457), .B0(n6709), .B1(n5546), .Y(n5534)
);
OAI2BB1X4TS U5421 ( .A0N(n5461), .A1N(n5460), .B0(n5459), .Y(n5639) );
CMPR32X2TS U5422 ( .A(n5464), .B(n5463), .C(n5462), .CO(n5506), .S(n5439) );
XNOR2X1TS U5423 ( .A(Data_A_i[33]), .B(n5465), .Y(n5526) );
OAI22X1TS U5424 ( .A0(n120), .A1(n5466), .B0(n4420), .B1(n5526), .Y(n5503)
);
NOR2X1TS U5425 ( .A(n5721), .B(n5467), .Y(n5499) );
XNOR2X1TS U5426 ( .A(n5715), .B(n5999), .Y(n5495) );
NAND2X4TS U5427 ( .A(n6786), .B(n6785), .Y(n7402) );
CMPR32X2TS U5428 ( .A(n5493), .B(n5492), .C(n5491), .CO(n5589), .S(n5555) );
XNOR2X1TS U5429 ( .A(n5715), .B(n5818), .Y(n5625) );
OAI22X1TS U5430 ( .A0(n6310), .A1(n5495), .B0(n3026), .B1(n5625), .Y(n5578)
);
XNOR2X1TS U5431 ( .A(n5887), .B(n5496), .Y(n5606) );
OAI22X1TS U5432 ( .A0(n4635), .A1(n5497), .B0(n6391), .B1(n5606), .Y(n5577)
);
XNOR2X1TS U5433 ( .A(n5520), .B(n80), .Y(n5603) );
OAI22X1TS U5434 ( .A0(n5667), .A1(n5521), .B0(n109), .B1(n5603), .Y(n5607)
);
XNOR2X1TS U5435 ( .A(Data_A_i[33]), .B(n5525), .Y(n5620) );
OAI22X1TS U5436 ( .A0(n5621), .A1(n5526), .B0(n6182), .B1(n5620), .Y(n5612)
);
XNOR2X1TS U5437 ( .A(n5959), .B(n6047), .Y(n5628) );
OAI22X1TS U5438 ( .A0(n5838), .A1(n5528), .B0(n6643), .B1(n5628), .Y(n5611)
);
XNOR2X1TS U5439 ( .A(n119), .B(Data_B_i[38]), .Y(n5602) );
OAI22X1TS U5440 ( .A0(n60), .A1(n5530), .B0(n139), .B1(n5602), .Y(n5610) );
CMPR32X2TS U5441 ( .A(n5533), .B(n5532), .C(n5531), .CO(n5595), .S(n5558) );
CMPR32X2TS U5442 ( .A(n5536), .B(n5535), .C(n5534), .CO(n5594), .S(n5552) );
XNOR2X1TS U5443 ( .A(Data_A_i[43]), .B(Data_B_i[34]), .Y(n5626) );
OAI22X1TS U5444 ( .A0(n5702), .A1(n5537), .B0(n5758), .B1(n5626), .Y(n5618)
);
XNOR2X1TS U5445 ( .A(n5760), .B(n6290), .Y(n5604) );
OAI22X1TS U5446 ( .A0(n4575), .A1(n5538), .B0(n135), .B1(n5604), .Y(n5617)
);
XNOR2X1TS U5447 ( .A(n6531), .B(n5539), .Y(n5583) );
OAI22X1TS U5448 ( .A0(n4750), .A1(n5540), .B0(n6605), .B1(n5583), .Y(n5616)
);
CMPR32X2TS U5449 ( .A(n5543), .B(n5542), .C(n5541), .CO(n5572), .S(n5559) );
XNOR2X1TS U5450 ( .A(n5913), .B(n5814), .Y(n5599) );
OAI22X1TS U5451 ( .A0(n122), .A1(n5544), .B0(n6111), .B1(n5599), .Y(n5575)
);
XNOR2X1TS U5452 ( .A(n106), .B(n5697), .Y(n5601) );
OAI22X1TS U5453 ( .A0(n145), .A1(n5545), .B0(n6063), .B1(n5601), .Y(n5574)
);
XNOR2X1TS U5454 ( .A(n5692), .B(Data_B_i[30]), .Y(n5624) );
OAI22X1TS U5455 ( .A0(n5980), .A1(n5546), .B0(n6709), .B1(n5624), .Y(n5573)
);
XNOR2X1TS U5456 ( .A(n82), .B(n5547), .Y(n5581) );
OAI22X1TS U5457 ( .A0(n113), .A1(n5548), .B0(n6589), .B1(n5581), .Y(n5598)
);
XNOR2X1TS U5458 ( .A(n5800), .B(n5839), .Y(n5600) );
OAI22X1TS U5459 ( .A0(n131), .A1(n5550), .B0(n5943), .B1(n5600), .Y(n5597)
);
XNOR2X1TS U5460 ( .A(n6995), .B(Data_B_i[26]), .Y(n5623) );
OAI22X1TS U5461 ( .A0(n6583), .A1(n5551), .B0(n6528), .B1(n5623), .Y(n5596)
);
CMPR32X2TS U5462 ( .A(n5554), .B(n5553), .C(n5552), .CO(n5569), .S(n5513) );
CMPR32X2TS U5463 ( .A(n5557), .B(n5556), .C(n5555), .CO(n5568), .S(n5509) );
CMPR32X2TS U5464 ( .A(n5572), .B(n5571), .C(n5570), .CO(n5680), .S(n5564) );
CMPR32X2TS U5465 ( .A(n5575), .B(n5574), .C(n5573), .CO(n5674), .S(n5571) );
CMPR32X2TS U5466 ( .A(n5578), .B(n5577), .C(n5576), .CO(n5673), .S(n5588) );
XNOR2X1TS U5467 ( .A(n82), .B(n5579), .Y(n5688) );
OAI22X1TS U5468 ( .A0(n113), .A1(n5581), .B0(n5580), .B1(n5688), .Y(n5686)
);
XNOR2X1TS U5469 ( .A(n6531), .B(n5582), .Y(n5704) );
OAI22X1TS U5470 ( .A0(n7093), .A1(n5583), .B0(n6605), .B1(n5704), .Y(n5685)
);
CMPR32X2TS U5471 ( .A(n5589), .B(n5588), .C(n5587), .CO(n5678), .S(n5631) );
CMPR32X2TS U5472 ( .A(n5595), .B(n5594), .C(n5593), .CO(n5646), .S(n5565) );
CMPR32X2TS U5473 ( .A(n5598), .B(n5597), .C(n5596), .CO(n5683), .S(n5570) );
XNOR2X1TS U5474 ( .A(n5913), .B(Data_B_i[29]), .Y(n5691) );
OAI22X1TS U5475 ( .A0(n123), .A1(n5599), .B0(n6111), .B1(n5691), .Y(n5658)
);
XNOR2X1TS U5476 ( .A(n5800), .B(n5881), .Y(n5703) );
OAI22X1TS U5477 ( .A0(n2521), .A1(n5600), .B0(n5943), .B1(n5703), .Y(n5657)
);
XNOR2X1TS U5478 ( .A(n106), .B(n5718), .Y(n5687) );
OAI22X1TS U5479 ( .A0(n147), .A1(n5601), .B0(n6124), .B1(n5687), .Y(n5656)
);
XNOR2X1TS U5480 ( .A(n6336), .B(Data_B_i[39]), .Y(n5690) );
OAI22X1TS U5481 ( .A0(n5942), .A1(n5602), .B0(n5432), .B1(n5690), .Y(n5652)
);
XNOR2X1TS U5482 ( .A(n1468), .B(n6128), .Y(n5666) );
OAI22X1TS U5483 ( .A0(n5667), .A1(n5603), .B0(n109), .B1(n5666), .Y(n5651)
);
XNOR2X1TS U5484 ( .A(n5101), .B(n6989), .Y(n5668) );
OAI22X1TS U5485 ( .A0(n5798), .A1(n5604), .B0(n135), .B1(n5668), .Y(n5650)
);
XNOR2X1TS U5486 ( .A(n5887), .B(n5999), .Y(n5700) );
OAI22X1TS U5487 ( .A0(n6392), .A1(n5606), .B0(n6391), .B1(n5700), .Y(n5661)
);
CMPR32X2TS U5488 ( .A(n5615), .B(n5614), .C(n5613), .CO(n5676), .S(n5566) );
CMPR32X2TS U5489 ( .A(n5618), .B(n5617), .C(n5616), .CO(n5649), .S(n5593) );
XNOR2X1TS U5490 ( .A(n114), .B(n5619), .Y(n5698) );
OAI22X1TS U5491 ( .A0(n5621), .A1(n5620), .B0(n6251), .B1(n5698), .Y(n5696)
);
XNOR2X1TS U5492 ( .A(n6015), .B(n5752), .Y(n5689) );
OAI22X1TS U5493 ( .A0(n6583), .A1(n5623), .B0(n5622), .B1(n5689), .Y(n5695)
);
XNOR2X1TS U5494 ( .A(n5692), .B(Data_B_i[31]), .Y(n5693) );
OAI22X1TS U5495 ( .A0(n5980), .A1(n5624), .B0(n6399), .B1(n5693), .Y(n5694)
);
XNOR2X1TS U5496 ( .A(n5715), .B(n5864), .Y(n5660) );
OAI22X1TS U5497 ( .A0(n5717), .A1(n5625), .B0(n5120), .B1(n5660), .Y(n5655)
);
XNOR2X1TS U5498 ( .A(Data_A_i[43]), .B(Data_B_i[35]), .Y(n5701) );
OAI22X1TS U5499 ( .A0(n5702), .A1(n5626), .B0(n5758), .B1(n5701), .Y(n5654)
);
XNOR2X1TS U5500 ( .A(n5627), .B(n6121), .Y(n5699) );
OAI22X1TS U5501 ( .A0(n5838), .A1(n5628), .B0(n6706), .B1(n5699), .Y(n5653)
);
NOR2X4TS U5502 ( .A(n6791), .B(n6790), .Y(n7148) );
OR2X8TS U5503 ( .A(n7148), .B(n7144), .Y(n6793) );
CMPR32X2TS U5504 ( .A(n5643), .B(n5642), .C(n5641), .CO(n5783), .S(n5710) );
CMPR32X2TS U5505 ( .A(n5649), .B(n5648), .C(n5647), .CO(n5768), .S(n5675) );
CMPR32X2TS U5506 ( .A(n5652), .B(n5651), .C(n5650), .CO(n5774), .S(n5681) );
CMPR32X2TS U5507 ( .A(n5655), .B(n5654), .C(n5653), .CO(n5773), .S(n5647) );
CMPR32X2TS U5508 ( .A(n5658), .B(n5657), .C(n5656), .CO(n5772), .S(n5682) );
XNOR2X1TS U5509 ( .A(n6185), .B(Data_B_i[44]), .Y(n5716) );
OAI22X1TS U5510 ( .A0(n5717), .A1(n5660), .B0(n5120), .B1(n5716), .Y(n5713)
);
OAI22X1TS U5511 ( .A0(n5667), .A1(n5666), .B0(n109), .B1(n5755), .Y(n5724)
);
XNOR2X1TS U5512 ( .A(n5101), .B(n79), .Y(n5761) );
OAI22X1TS U5513 ( .A0(n5798), .A1(n5668), .B0(n135), .B1(n5761), .Y(n5723)
);
CMPR32X2TS U5514 ( .A(n5674), .B(n5673), .C(n5672), .CO(n5775), .S(n5679) );
ADDFHX4TS U5515 ( .A(n5680), .B(n5679), .CI(n5678), .CO(n5779), .S(n5641) );
CMPR32X2TS U5516 ( .A(n5683), .B(n5682), .C(n5681), .CO(n5734), .S(n5645) );
CMPR32X2TS U5517 ( .A(n5686), .B(n5685), .C(n5684), .CO(n5771), .S(n5672) );
XNOR2X1TS U5518 ( .A(Data_A_i[31]), .B(n5839), .Y(n5729) );
OAI22X1TS U5519 ( .A0(n147), .A1(n5687), .B0(n6063), .B1(n5729), .Y(n5749)
);
XNOR2X1TS U5520 ( .A(n82), .B(n5811), .Y(n5751) );
OAI22X1TS U5521 ( .A0(n5549), .A1(n5688), .B0(n6589), .B1(n5751), .Y(n5748)
);
XNOR2X1TS U5522 ( .A(n6890), .B(n5814), .Y(n5762) );
OAI22X1TS U5523 ( .A0(n6583), .A1(n5689), .B0(n6234), .B1(n5762), .Y(n5747)
);
XNOR2X1TS U5524 ( .A(n6376), .B(Data_B_i[40]), .Y(n5731) );
OAI22X1TS U5525 ( .A0(n6542), .A1(n5690), .B0(n6466), .B1(n5731), .Y(n5728)
);
XNOR2X1TS U5526 ( .A(n5913), .B(Data_B_i[30]), .Y(n5744) );
XNOR2X1TS U5527 ( .A(n5692), .B(n6047), .Y(n5746) );
OAI22X1TS U5528 ( .A0(n5980), .A1(n5693), .B0(n6399), .B1(n5746), .Y(n5726)
);
XNOR2X1TS U5529 ( .A(n6066), .B(n5697), .Y(n5719) );
OAI22X1TS U5530 ( .A0(n121), .A1(n5698), .B0(n4420), .B1(n5719), .Y(n5743)
);
XNOR2X1TS U5531 ( .A(n5959), .B(Data_B_i[34]), .Y(n5730) );
OAI22X1TS U5532 ( .A0(n5838), .A1(n5699), .B0(n6706), .B1(n5730), .Y(n5742)
);
XNOR2X1TS U5533 ( .A(n5887), .B(n5818), .Y(n5722) );
OAI22X1TS U5534 ( .A0(n74), .A1(n5700), .B0(n5842), .B1(n5722), .Y(n5741) );
XNOR2X1TS U5535 ( .A(Data_A_i[43]), .B(Data_B_i[36]), .Y(n5759) );
OAI22X1TS U5536 ( .A0(n5702), .A1(n5701), .B0(n6659), .B1(n5759), .Y(n5740)
);
XNOR2X1TS U5537 ( .A(n5800), .B(n5961), .Y(n5745) );
OAI22X1TS U5538 ( .A0(n131), .A1(n5703), .B0(n5943), .B1(n5745), .Y(n5739)
);
XNOR2X1TS U5539 ( .A(n6386), .B(Data_B_i[26]), .Y(n5754) );
OAI22X1TS U5540 ( .A0(n7093), .A1(n5704), .B0(n6605), .B1(n5754), .Y(n5738)
);
CMPR32X2TS U5541 ( .A(n5713), .B(n5712), .C(n5711), .CO(n5849), .S(n5777) );
BUFX3TS U5542 ( .A(n5714), .Y(n6308) );
XNOR2X1TS U5543 ( .A(n5715), .B(Data_B_i[45]), .Y(n5841) );
OAI22X1TS U5544 ( .A0(n5717), .A1(n5716), .B0(n5120), .B1(n5841), .Y(n5789)
);
XNOR2X1TS U5545 ( .A(Data_A_i[33]), .B(n5718), .Y(n5840) );
OAI22X1TS U5546 ( .A0(n120), .A1(n5719), .B0(n59), .B1(n5840), .Y(n5788) );
XNOR2X1TS U5547 ( .A(n5887), .B(n5864), .Y(n5843) );
OAI22X1TS U5548 ( .A0(n6392), .A1(n5722), .B0(n5842), .B1(n5843), .Y(n5793)
);
CMPR32X2TS U5549 ( .A(n5728), .B(n5727), .C(n5726), .CO(n5791), .S(n5769) );
XNOR2X1TS U5550 ( .A(n6012), .B(n5881), .Y(n5813) );
OAI22X1TS U5551 ( .A0(n147), .A1(n5729), .B0(n6124), .B1(n5813), .Y(n5810)
);
XNOR2X1TS U5552 ( .A(n5959), .B(Data_B_i[35]), .Y(n5837) );
OAI22X1TS U5553 ( .A0(n5838), .A1(n5730), .B0(n6316), .B1(n5837), .Y(n5809)
);
XNOR2X1TS U5554 ( .A(n6376), .B(Data_B_i[41]), .Y(n5819) );
OAI22X1TS U5555 ( .A0(n60), .A1(n5731), .B0(n138), .B1(n5819), .Y(n5808) );
CMPR32X2TS U5556 ( .A(n5737), .B(n5736), .C(n5735), .CO(n5824), .S(n5732) );
CMPR32X2TS U5557 ( .A(n5740), .B(n5739), .C(n5738), .CO(n5833), .S(n5735) );
XNOR2X1TS U5558 ( .A(n5913), .B(Data_B_i[31]), .Y(n5846) );
OAI22X1TS U5559 ( .A0(n122), .A1(n5744), .B0(n6111), .B1(n5846), .Y(n5786)
);
XNOR2X1TS U5560 ( .A(n5800), .B(n6007), .Y(n5801) );
OAI22X1TS U5561 ( .A0(n5945), .A1(n5745), .B0(n5943), .B1(n5801), .Y(n5785)
);
XNOR2X1TS U5562 ( .A(n6030), .B(n6121), .Y(n5820) );
OAI22X1TS U5563 ( .A0(n5980), .A1(n5746), .B0(n6399), .B1(n5820), .Y(n5784)
);
CMPR32X2TS U5564 ( .A(n5749), .B(n5748), .C(n5747), .CO(n5807), .S(n5770) );
XNOR2X1TS U5565 ( .A(n6469), .B(n5750), .Y(n5821) );
XNOR2X1TS U5566 ( .A(n6386), .B(n5752), .Y(n5816) );
XNOR2X1TS U5567 ( .A(Data_A_i[43]), .B(n77), .Y(n5812) );
OAI22X1TS U5568 ( .A0(n6660), .A1(n5759), .B0(n5758), .B1(n5812), .Y(n5836)
);
XNOR2X1TS U5569 ( .A(n5101), .B(n6128), .Y(n5797) );
OAI22X1TS U5570 ( .A0(n39), .A1(n5761), .B0(n134), .B1(n5797), .Y(n5835) );
XNOR2X1TS U5571 ( .A(n93), .B(Data_B_i[29]), .Y(n5845) );
OAI22X1TS U5572 ( .A0(n6212), .A1(n5762), .B0(n6234), .B1(n5845), .Y(n5834)
);
ADDFHX4TS U5573 ( .A(n5765), .B(n5764), .CI(n5763), .CO(n5854), .S(n5782) );
CMPR32X2TS U5574 ( .A(n5774), .B(n5773), .C(n5772), .CO(n5829), .S(n5767) );
CMPR32X2TS U5575 ( .A(n5786), .B(n5785), .C(n5784), .CO(n5918), .S(n5831) );
CMPR32X2TS U5576 ( .A(n5789), .B(n5788), .C(n5787), .CO(n5917), .S(n5848) );
CMPR32X2TS U5577 ( .A(n5795), .B(n5794), .C(n5793), .CO(n5874), .S(n5787) );
NOR2X1TS U5578 ( .A(n6062), .B(n5799), .Y(n5935) );
XNOR2X1TS U5579 ( .A(n5800), .B(Data_B_i[52]), .Y(n5909) );
OAI22X1TS U5580 ( .A0(n6003), .A1(n5801), .B0(n5943), .B1(n5909), .Y(n5866)
);
CMPR32X2TS U5581 ( .A(n5810), .B(n5809), .C(n5808), .CO(n5877), .S(n5790) );
XNOR2X1TS U5582 ( .A(n6520), .B(n5811), .Y(n5889) );
OAI22X1TS U5583 ( .A0(n6660), .A1(n5812), .B0(n6659), .B1(n5889), .Y(n5906)
);
XNOR2X1TS U5584 ( .A(n1814), .B(n5961), .Y(n5910) );
OAI22X1TS U5585 ( .A0(n146), .A1(n5813), .B0(n6063), .B1(n5910), .Y(n5905)
);
XNOR2X1TS U5586 ( .A(n5815), .B(n5814), .Y(n5891) );
OAI22X1TS U5587 ( .A0(n4750), .A1(n5816), .B0(n6366), .B1(n5891), .Y(n5904)
);
XNOR2X1TS U5588 ( .A(n118), .B(n5818), .Y(n5865) );
OAI22X1TS U5589 ( .A0(n6468), .A1(n5819), .B0(n6541), .B1(n5865), .Y(n5861)
);
XNOR2X1TS U5590 ( .A(n6030), .B(Data_B_i[34]), .Y(n5915) );
OAI22X1TS U5591 ( .A0(n5980), .A1(n5820), .B0(n6709), .B1(n5915), .Y(n5860)
);
XNOR2X1TS U5592 ( .A(n6146), .B(Data_B_i[40]), .Y(n5907) );
OAI22X1TS U5593 ( .A0(n5549), .A1(n5821), .B0(n6589), .B1(n5907), .Y(n5859)
);
CMPR32X2TS U5594 ( .A(n5836), .B(n5835), .C(n5834), .CO(n5903), .S(n5805) );
XNOR2X1TS U5595 ( .A(n5959), .B(Data_B_i[36]), .Y(n5885) );
OAI22X1TS U5596 ( .A0(n5838), .A1(n5837), .B0(n6044), .B1(n5885), .Y(n5858)
);
XNOR2X1TS U5597 ( .A(n6129), .B(n5839), .Y(n5882) );
OAI22X1TS U5598 ( .A0(n4337), .A1(n5840), .B0(n6251), .B1(n5882), .Y(n5857)
);
XNOR2X1TS U5599 ( .A(n6185), .B(n6026), .Y(n5862) );
OAI22X1TS U5600 ( .A0(n6310), .A1(n5841), .B0(n5120), .B1(n5862), .Y(n5856)
);
XNOR2X1TS U5601 ( .A(n5887), .B(n6055), .Y(n5888) );
OAI22X1TS U5602 ( .A0(n74), .A1(n5843), .B0(n5842), .B1(n5888), .Y(n5880) );
XNOR2X1TS U5603 ( .A(n6890), .B(n5844), .Y(n5912) );
OAI22X1TS U5604 ( .A0(n6212), .A1(n5845), .B0(n6234), .B1(n5912), .Y(n5879)
);
XNOR2X1TS U5605 ( .A(n6610), .B(n6047), .Y(n5914) );
OAI22X1TS U5606 ( .A0(n6889), .A1(n5846), .B0(n6111), .B1(n5914), .Y(n5878)
);
CMPR32X2TS U5607 ( .A(n5849), .B(n5848), .C(n5847), .CO(n5898), .S(n5852) );
CMPR32X2TS U5608 ( .A(n5858), .B(n5857), .C(n5856), .CO(n6076), .S(n5902) );
CMPR32X2TS U5609 ( .A(n5861), .B(n5860), .C(n5859), .CO(n6075), .S(n5875) );
XNOR2X1TS U5610 ( .A(n6185), .B(n6347), .Y(n5983) );
OAI22X1TS U5611 ( .A0(n6310), .A1(n5862), .B0(n5120), .B1(n5983), .Y(n5966)
);
XNOR2X1TS U5612 ( .A(n6336), .B(n5864), .Y(n5931) );
OAI22X1TS U5613 ( .A0(n5817), .A1(n5865), .B0(n138), .B1(n5931), .Y(n5933)
);
CMPR32X2TS U5614 ( .A(n5880), .B(n5879), .C(n5878), .CO(n5972), .S(n5901) );
XNOR2X1TS U5615 ( .A(n6066), .B(n5881), .Y(n5962) );
OAI22X1TS U5616 ( .A0(n4337), .A1(n5882), .B0(n5144), .B1(n5962), .Y(n5958)
);
XNOR2X1TS U5617 ( .A(n5959), .B(Data_B_i[37]), .Y(n5960) );
OAI22X1TS U5618 ( .A0(n6707), .A1(n5885), .B0(n5884), .B1(n5960), .Y(n5957)
);
XNOR2X1TS U5619 ( .A(n5887), .B(n5940), .Y(n5949) );
OAI22X1TS U5620 ( .A0(n6381), .A1(n5888), .B0(n6379), .B1(n5949), .Y(n5956)
);
XNOR2X1TS U5621 ( .A(n6520), .B(Data_B_i[39]), .Y(n5951) );
OAI22X1TS U5622 ( .A0(n6660), .A1(n5889), .B0(n6659), .B1(n5951), .Y(n5978)
);
XNOR2X1TS U5623 ( .A(n6386), .B(n5890), .Y(n5963) );
OAI22X1TS U5624 ( .A0(n7093), .A1(n5891), .B0(n6366), .B1(n5963), .Y(n5977)
);
CMPR32X2TS U5625 ( .A(n5903), .B(n5902), .C(n5901), .CO(n6088), .S(n5899) );
XNOR2X1TS U5626 ( .A(n6146), .B(Data_B_i[41]), .Y(n5932) );
OAI22X1TS U5627 ( .A0(n113), .A1(n5907), .B0(n6589), .B1(n5932), .Y(n5927)
);
XNOR2X1TS U5628 ( .A(n5908), .B(Data_B_i[53]), .Y(n5944) );
OAI22X1TS U5629 ( .A0(n6003), .A1(n5909), .B0(n5943), .B1(n5944), .Y(n5926)
);
XNOR2X1TS U5630 ( .A(n5449), .B(n6007), .Y(n5946) );
OAI22X1TS U5631 ( .A0(n146), .A1(n5910), .B0(n6124), .B1(n5946), .Y(n5925)
);
XNOR2X1TS U5632 ( .A(n6015), .B(n5911), .Y(n5981) );
OAI22X1TS U5633 ( .A0(n6212), .A1(n5912), .B0(n6234), .B1(n5981), .Y(n5930)
);
XNOR2X1TS U5634 ( .A(n5913), .B(n6121), .Y(n5950) );
OAI22X1TS U5635 ( .A0(n6993), .A1(n5914), .B0(n6111), .B1(n5950), .Y(n5929)
);
XNOR2X1TS U5636 ( .A(n6030), .B(Data_B_i[35]), .Y(n5979) );
OAI22X1TS U5637 ( .A0(n5980), .A1(n5915), .B0(n95), .B1(n5979), .Y(n5928) );
NOR2X2TS U5638 ( .A(n7124), .B(n7128), .Y(n6805) );
NAND2X4TS U5639 ( .A(n7116), .B(n6805), .Y(n7105) );
CMPR32X2TS U5640 ( .A(n5927), .B(n5926), .C(n5925), .CO(n5989), .S(n5974) );
CMPR32X2TS U5641 ( .A(n5930), .B(n5929), .C(n5928), .CO(n5988), .S(n5973) );
XNOR2X1TS U5642 ( .A(n5082), .B(n6055), .Y(n5941) );
OAI22X1TS U5643 ( .A0(n6542), .A1(n5931), .B0(n5432), .B1(n5941), .Y(n5998)
);
XNOR2X1TS U5644 ( .A(n6146), .B(Data_B_i[42]), .Y(n5936) );
OAI22X1TS U5645 ( .A0(n113), .A1(n5932), .B0(n6056), .B1(n5936), .Y(n5997)
);
CMPR32X2TS U5646 ( .A(n5935), .B(n5934), .C(n5933), .CO(n5996), .S(n5965) );
XNOR2X1TS U5647 ( .A(n6185), .B(n6193), .Y(n5982) );
XNOR2X1TS U5648 ( .A(n6185), .B(n6232), .Y(n6046) );
OAI22X1TS U5649 ( .A0(n6310), .A1(n5982), .B0(n5659), .B1(n6046), .Y(n6043)
);
XNOR2X1TS U5650 ( .A(n6146), .B(Data_B_i[43]), .Y(n6057) );
OAI22X1TS U5651 ( .A0(n6525), .A1(n5936), .B0(n6056), .B1(n6057), .Y(n6042)
);
XNOR2X1TS U5652 ( .A(Data_A_i[37]), .B(n6026), .Y(n5948) );
XNOR2X1TS U5653 ( .A(Data_A_i[37]), .B(n6347), .Y(n6032) );
OAI22X1TS U5654 ( .A0(n74), .A1(n5948), .B0(n6379), .B1(n6032), .Y(n6041) );
XNOR2X1TS U5655 ( .A(n5082), .B(n5940), .Y(n6027) );
OAI22X1TS U5656 ( .A0(n5817), .A1(n5941), .B0(n6541), .B1(n6027), .Y(n6058)
);
OAI22X1TS U5657 ( .A0(n2521), .A1(n5944), .B0(n5943), .B1(n6002), .Y(n5953)
);
XNOR2X1TS U5658 ( .A(Data_A_i[31]), .B(n80), .Y(n6013) );
OAI22X1TS U5659 ( .A0(n147), .A1(n5946), .B0(n6063), .B1(n6013), .Y(n5955)
);
OAI22X1TS U5660 ( .A0(n73), .A1(n5949), .B0(n6379), .B1(n5948), .Y(n5986) );
XNOR2X1TS U5661 ( .A(n6610), .B(Data_B_i[34]), .Y(n6009) );
OAI22X1TS U5662 ( .A0(n122), .A1(n5950), .B0(n6111), .B1(n6009), .Y(n5985)
);
XNOR2X1TS U5663 ( .A(n6259), .B(Data_B_i[40]), .Y(n6000) );
OAI22X1TS U5664 ( .A0(n6660), .A1(n5951), .B0(n6659), .B1(n6000), .Y(n5984)
);
CMPR32X2TS U5665 ( .A(n5958), .B(n5957), .C(n5956), .CO(n5968), .S(n5971) );
XNOR2X1TS U5666 ( .A(n5959), .B(Data_B_i[38]), .Y(n6011) );
OAI22X1TS U5667 ( .A0(n6707), .A1(n5960), .B0(n6044), .B1(n6011), .Y(n5995)
);
XNOR2X1TS U5668 ( .A(n3741), .B(n5961), .Y(n6008) );
OAI22X1TS U5669 ( .A0(n121), .A1(n5962), .B0(n6182), .B1(n6008), .Y(n5994)
);
XNOR2X1TS U5670 ( .A(n6386), .B(Data_B_i[30]), .Y(n6001) );
OAI22X1TS U5671 ( .A0(n4750), .A1(n5963), .B0(n6366), .B1(n6001), .Y(n5993)
);
CMPR32X2TS U5672 ( .A(n5966), .B(n5965), .C(n5964), .CO(n6082), .S(n6074) );
CMPR32X2TS U5673 ( .A(n5978), .B(n5977), .C(n5976), .CO(n5992), .S(n5970) );
XNOR2X1TS U5674 ( .A(n6030), .B(Data_B_i[36]), .Y(n6010) );
OAI22X1TS U5675 ( .A0(n5980), .A1(n5979), .B0(n6769), .B1(n6010), .Y(n6006)
);
XNOR2X1TS U5676 ( .A(n6890), .B(n6047), .Y(n6016) );
OAI22X1TS U5677 ( .A0(n6212), .A1(n5981), .B0(n6234), .B1(n6016), .Y(n6005)
);
OAI22X1TS U5678 ( .A0(n6310), .A1(n5983), .B0(n5120), .B1(n5982), .Y(n6004)
);
CMPR32X2TS U5679 ( .A(n5986), .B(n5985), .C(n5984), .CO(n6068), .S(n5990) );
CMPR32X2TS U5680 ( .A(n5989), .B(n5988), .C(n5987), .CO(n6019), .S(n6089) );
CMPR32X2TS U5681 ( .A(n5992), .B(n5991), .C(n5990), .CO(n6022), .S(n6090) );
CMPR32X2TS U5682 ( .A(n5995), .B(n5994), .C(n5993), .CO(n6037), .S(n5967) );
CMPR32X2TS U5683 ( .A(n5998), .B(n5997), .C(n5996), .CO(n6036), .S(n5987) );
XNOR2X1TS U5684 ( .A(n6259), .B(n5999), .Y(n6029) );
OAI22X1TS U5685 ( .A0(n6660), .A1(n6000), .B0(n6659), .B1(n6029), .Y(n6025)
);
XNOR2X1TS U5686 ( .A(n6386), .B(Data_B_i[31]), .Y(n6048) );
OAI22X1TS U5687 ( .A0(n5291), .A1(n6001), .B0(n6366), .B1(n6048), .Y(n6024)
);
XNOR2X1TS U5688 ( .A(n3741), .B(n6007), .Y(n6067) );
OAI22X1TS U5689 ( .A0(n5621), .A1(n6008), .B0(n6182), .B1(n6067), .Y(n6054)
);
XNOR2X1TS U5690 ( .A(n6610), .B(Data_B_i[35]), .Y(n6028) );
OAI22X1TS U5691 ( .A0(n123), .A1(n6009), .B0(n6111), .B1(n6028), .Y(n6053)
);
CLKBUFX2TS U5692 ( .A(n6319), .Y(n6770) );
XNOR2X1TS U5693 ( .A(n6030), .B(n77), .Y(n6031) );
OAI22X1TS U5694 ( .A0(n6770), .A1(n6010), .B0(n6709), .B1(n6031), .Y(n6052)
);
XNOR2X1TS U5695 ( .A(Data_A_i[45]), .B(Data_B_i[39]), .Y(n6045) );
OAI22X1TS U5696 ( .A0(n6707), .A1(n6011), .B0(n6683), .B1(n6045), .Y(n6040)
);
OAI22X1TS U5697 ( .A0(n147), .A1(n6013), .B0(n6063), .B1(n6064), .Y(n6039)
);
XNOR2X1TS U5698 ( .A(n6015), .B(n6121), .Y(n6034) );
OAI22X1TS U5699 ( .A0(n6212), .A1(n6016), .B0(n6234), .B1(n6034), .Y(n6038)
);
ADDFHX2TS U5700 ( .A(n6019), .B(n6018), .CI(n6017), .CO(n6097), .S(n6083) );
CMPR32X2TS U5701 ( .A(n6022), .B(n6021), .C(n6020), .CO(n6103), .S(n6084) );
CMPR32X2TS U5702 ( .A(n6025), .B(n6024), .C(n6023), .CO(n6136), .S(n6035) );
XNOR2X1TS U5703 ( .A(n6336), .B(n6026), .Y(n6144) );
XNOR2X1TS U5704 ( .A(n6610), .B(Data_B_i[36]), .Y(n6112) );
OAI22X1TS U5705 ( .A0(n5456), .A1(n6028), .B0(n6992), .B1(n6112), .Y(n6138)
);
XNOR2X1TS U5706 ( .A(n6259), .B(Data_B_i[42]), .Y(n6126) );
OAI22X1TS U5707 ( .A0(n6618), .A1(n6029), .B0(n6195), .B1(n6126), .Y(n6137)
);
XNOR2X1TS U5708 ( .A(n6030), .B(Data_B_i[38]), .Y(n6113) );
OAI22X1TS U5709 ( .A0(n6770), .A1(n6031), .B0(n6769), .B1(n6113), .Y(n6119)
);
XNOR2X1TS U5710 ( .A(n6311), .B(n6193), .Y(n6143) );
OAI22X1TS U5711 ( .A0(n6392), .A1(n6032), .B0(n6379), .B1(n6143), .Y(n6118)
);
XNOR2X1TS U5712 ( .A(n6995), .B(n6033), .Y(n6127) );
OAI22X1TS U5713 ( .A0(n6212), .A1(n6034), .B0(n6234), .B1(n6127), .Y(n6117)
);
CMPR32X2TS U5714 ( .A(n6040), .B(n6039), .C(n6038), .CO(n6116), .S(n6049) );
XNOR2X1TS U5715 ( .A(n6338), .B(Data_B_i[40]), .Y(n6120) );
OAI22X1TS U5716 ( .A0(n6707), .A1(n6045), .B0(n6044), .B1(n6120), .Y(n6109)
);
XNOR2X1TS U5717 ( .A(n6185), .B(n6290), .Y(n6110) );
OAI22X1TS U5718 ( .A0(n6310), .A1(n6046), .B0(n5659), .B1(n6110), .Y(n6108)
);
XNOR2X1TS U5719 ( .A(n6386), .B(n6047), .Y(n6122) );
OAI22X1TS U5720 ( .A0(n5291), .A1(n6048), .B0(n6366), .B1(n6122), .Y(n6107)
);
CMPR32X2TS U5721 ( .A(n6051), .B(n6050), .C(n6049), .CO(n6100), .S(n6020) );
CMPR32X2TS U5722 ( .A(n6054), .B(n6053), .C(n6052), .CO(n6151), .S(n6050) );
XNOR2X1TS U5723 ( .A(n6469), .B(n6055), .Y(n6147) );
OAI22X1TS U5724 ( .A0(n113), .A1(n6057), .B0(n6056), .B1(n6147), .Y(n6142)
);
CMPR32X2TS U5725 ( .A(n6060), .B(n6059), .C(n6058), .CO(n6141), .S(n6070) );
NOR2X1TS U5726 ( .A(n6062), .B(n6061), .Y(n6181) );
OAI22X1TS U5727 ( .A0(n6065), .A1(n6064), .B0(n6063), .B1(n6123), .Y(n6105)
);
XNOR2X1TS U5728 ( .A(n6129), .B(Data_B_i[52]), .Y(n6130) );
OAI22X1TS U5729 ( .A0(n5621), .A1(n6067), .B0(n6182), .B1(n6130), .Y(n6104)
);
CMPR32X2TS U5730 ( .A(n6076), .B(n6075), .C(n6074), .CO(n6154), .S(n6094) );
CMPR32X2TS U5731 ( .A(n6091), .B(n6090), .C(n6089), .CO(n6085), .S(n6159) );
CMPR32X2TS U5732 ( .A(n6094), .B(n6093), .C(n6092), .CO(n6158), .S(n6163) );
ADDFHX2TS U5733 ( .A(n6097), .B(n6096), .CI(n6095), .CO(n6813), .S(n6811) );
CMPR32X2TS U5734 ( .A(n6106), .B(n6105), .C(n6104), .CO(n6178), .S(n6140) );
CMPR32X2TS U5735 ( .A(n6109), .B(n6108), .C(n6107), .CO(n6177), .S(n6114) );
XNOR2X1TS U5736 ( .A(n6185), .B(Data_B_i[51]), .Y(n6186) );
OAI22X1TS U5737 ( .A0(n6310), .A1(n6110), .B0(n5120), .B1(n6186), .Y(n6192)
);
XNOR2X1TS U5738 ( .A(n6610), .B(n77), .Y(n6214) );
XNOR2X1TS U5739 ( .A(n6686), .B(Data_B_i[39]), .Y(n6210) );
OAI22X1TS U5740 ( .A0(n6770), .A1(n6113), .B0(n6769), .B1(n6210), .Y(n6190)
);
CMPR32X2TS U5741 ( .A(n6119), .B(n6118), .C(n6117), .CO(n6206), .S(n6134) );
XNOR2X1TS U5742 ( .A(n6338), .B(Data_B_i[41]), .Y(n6216) );
OAI22X1TS U5743 ( .A0(n6707), .A1(n6120), .B0(n6683), .B1(n6216), .Y(n6189)
);
XNOR2X1TS U5744 ( .A(n6386), .B(n6121), .Y(n6213) );
OAI22X1TS U5745 ( .A0(n6530), .A1(n6122), .B0(n6366), .B1(n6213), .Y(n6188)
);
XNOR2X1TS U5746 ( .A(n6259), .B(Data_B_i[43]), .Y(n6196) );
OAI22X1TS U5747 ( .A0(n129), .A1(n6126), .B0(n6195), .B1(n6196), .Y(n6209)
);
XNOR2X1TS U5748 ( .A(n93), .B(Data_B_i[35]), .Y(n6211) );
OAI22X1TS U5749 ( .A0(n6212), .A1(n6127), .B0(n6234), .B1(n6211), .Y(n6208)
);
XNOR2X1TS U5750 ( .A(n114), .B(n6128), .Y(n6183) );
OAI22X1TS U5751 ( .A0(n5621), .A1(n6130), .B0(n6182), .B1(n6183), .Y(n6207)
);
CMPR32X2TS U5752 ( .A(n6133), .B(n6132), .C(n6131), .CO(n6221), .S(n6102) );
CMPR32X2TS U5753 ( .A(n6139), .B(n6138), .C(n6137), .CO(n6219), .S(n6135) );
XNOR2X1TS U5754 ( .A(Data_A_i[37]), .B(n6232), .Y(n6215) );
OAI22X1TS U5755 ( .A0(n74), .A1(n6143), .B0(n6379), .B1(n6215), .Y(n6200) );
XNOR2X1TS U5756 ( .A(n118), .B(Data_B_i[47]), .Y(n6194) );
OAI22X1TS U5757 ( .A0(n6468), .A1(n6144), .B0(n6466), .B1(n6194), .Y(n6199)
);
XNOR2X1TS U5758 ( .A(n6146), .B(Data_B_i[45]), .Y(n6197) );
OAI22X1TS U5759 ( .A0(n113), .A1(n6147), .B0(n6523), .B1(n6197), .Y(n6179)
);
NOR2X2TS U5760 ( .A(n7416), .B(n7420), .Y(n6815) );
CMPR32X2TS U5761 ( .A(n6154), .B(n6153), .C(n6152), .CO(n6166), .S(n6169) );
ADDFHX2TS U5762 ( .A(n6163), .B(n6162), .CI(n6161), .CO(n6806), .S(n6803) );
XNOR2X1TS U5763 ( .A(n6185), .B(n79), .Y(n6239) );
OAI22X1TS U5764 ( .A0(n6310), .A1(n6186), .B0(n6308), .B1(n6239), .Y(n6262)
);
CMPR32X2TS U5765 ( .A(n6192), .B(n6191), .C(n6190), .CO(n6228), .S(n6176) );
XNOR2X1TS U5766 ( .A(n5082), .B(n6193), .Y(n6233) );
OAI22X1TS U5767 ( .A0(n6468), .A1(n6194), .B0(n5432), .B1(n6233), .Y(n6246)
);
XNOR2X1TS U5768 ( .A(n6259), .B(Data_B_i[44]), .Y(n6260) );
OAI22X1TS U5769 ( .A0(n129), .A1(n6196), .B0(n6195), .B1(n6260), .Y(n6245)
);
XNOR2X1TS U5770 ( .A(n6469), .B(Data_B_i[46]), .Y(n6256) );
OAI22X1TS U5771 ( .A0(n6525), .A1(n6197), .B0(n6523), .B1(n6256), .Y(n6244)
);
CMPR32X2TS U5772 ( .A(n6200), .B(n6199), .C(n6198), .CO(n6226), .S(n6217) );
CMPR32X2TS U5773 ( .A(n6209), .B(n6208), .C(n6207), .CO(n6270), .S(n6204) );
XNOR2X1TS U5774 ( .A(n6388), .B(Data_B_i[40]), .Y(n6237) );
OAI22X1TS U5775 ( .A0(n6770), .A1(n6210), .B0(n6769), .B1(n6237), .Y(n6231)
);
XNOR2X1TS U5776 ( .A(n93), .B(Data_B_i[36]), .Y(n6235) );
OAI22X1TS U5777 ( .A0(n6212), .A1(n6211), .B0(n7045), .B1(n6235), .Y(n6230)
);
XNOR2X1TS U5778 ( .A(n6386), .B(Data_B_i[34]), .Y(n6249) );
OAI22X1TS U5779 ( .A0(n5291), .A1(n6213), .B0(n6366), .B1(n6249), .Y(n6229)
);
XNOR2X1TS U5780 ( .A(n6610), .B(Data_B_i[38]), .Y(n6236) );
OAI22X1TS U5781 ( .A0(n6993), .A1(n6214), .B0(n6992), .B1(n6236), .Y(n6243)
);
XNOR2X1TS U5782 ( .A(Data_A_i[37]), .B(n6290), .Y(n6240) );
OAI22X1TS U5783 ( .A0(n6381), .A1(n6215), .B0(n6379), .B1(n6240), .Y(n6242)
);
XNOR2X1TS U5784 ( .A(n6338), .B(Data_B_i[42]), .Y(n6247) );
OAI22X1TS U5785 ( .A0(n6685), .A1(n6216), .B0(n6316), .B1(n6247), .Y(n6241)
);
NOR2X2TS U5786 ( .A(n6818), .B(n6819), .Y(n7432) );
INVX2TS U5787 ( .A(n7432), .Y(n7425) );
XNOR2X1TS U5788 ( .A(n6376), .B(n6232), .Y(n6291) );
OAI22X1TS U5789 ( .A0(n6468), .A1(n6233), .B0(n139), .B1(n6291), .Y(n6315)
);
XNOR2X1TS U5790 ( .A(n93), .B(Data_B_i[37]), .Y(n6318) );
OAI22X1TS U5791 ( .A0(n7046), .A1(n6235), .B0(n6234), .B1(n6318), .Y(n6314)
);
XNOR2X1TS U5792 ( .A(n6735), .B(Data_B_i[39]), .Y(n6289) );
OAI22X1TS U5793 ( .A0(n6993), .A1(n6236), .B0(n6992), .B1(n6289), .Y(n6313)
);
XNOR2X1TS U5794 ( .A(n6388), .B(Data_B_i[41]), .Y(n6320) );
OAI22X1TS U5795 ( .A0(n6770), .A1(n6237), .B0(n6769), .B1(n6320), .Y(n6288)
);
XNOR2X1TS U5796 ( .A(n6238), .B(n7048), .Y(n6309) );
OAI22X1TS U5797 ( .A0(n6310), .A1(n6239), .B0(n3026), .B1(n6309), .Y(n6287)
);
XNOR2X1TS U5798 ( .A(n6311), .B(Data_B_i[51]), .Y(n6312) );
OAI22X1TS U5799 ( .A0(n5217), .A1(n6240), .B0(n6379), .B1(n6312), .Y(n6286)
);
CMPR32X2TS U5800 ( .A(n6246), .B(n6245), .C(n6244), .CO(n6281), .S(n6227) );
XNOR2X1TS U5801 ( .A(n6338), .B(Data_B_i[43]), .Y(n6317) );
OAI22X1TS U5802 ( .A0(n6340), .A1(n6247), .B0(n6316), .B1(n6317), .Y(n6285)
);
XNOR2X1TS U5803 ( .A(n6586), .B(n6248), .Y(n6292) );
OAI22X1TS U5804 ( .A0(n6530), .A1(n6249), .B0(n6366), .B1(n6292), .Y(n6284)
);
XNOR2X1TS U5805 ( .A(n6469), .B(Data_B_i[47]), .Y(n6299) );
OAI22X1TS U5806 ( .A0(n5549), .A1(n6256), .B0(n6523), .B1(n6299), .Y(n6306)
);
XNOR2X1TS U5807 ( .A(n6259), .B(Data_B_i[45]), .Y(n6300) );
OAI22X1TS U5808 ( .A0(n129), .A1(n6260), .B0(n6616), .B1(n6300), .Y(n6301)
);
NAND2X2TS U5809 ( .A(n7425), .B(n1), .Y(n6926) );
CMPR32X2TS U5810 ( .A(n6282), .B(n6281), .C(n6280), .CO(n6328), .S(n6321) );
CMPR32X2TS U5811 ( .A(n6288), .B(n6287), .C(n6286), .CO(n6359), .S(n6277) );
XNOR2X1TS U5812 ( .A(Data_A_i[49]), .B(Data_B_i[40]), .Y(n6345) );
OAI22X1TS U5813 ( .A0(n6993), .A1(n6289), .B0(n6992), .B1(n6345), .Y(n6363)
);
XNOR2X1TS U5814 ( .A(n5082), .B(n6290), .Y(n6337) );
OAI22X1TS U5815 ( .A0(n6468), .A1(n6291), .B0(n139), .B1(n6337), .Y(n6362)
);
XNOR2X1TS U5816 ( .A(n6586), .B(Data_B_i[36]), .Y(n6367) );
OAI22X1TS U5817 ( .A0(n5291), .A1(n6292), .B0(n3047), .B1(n6367), .Y(n6361)
);
XNOR2X1TS U5818 ( .A(n6469), .B(Data_B_i[48]), .Y(n6341) );
OAI22X1TS U5819 ( .A0(n6590), .A1(n6299), .B0(n6523), .B1(n6341), .Y(n6372)
);
XNOR2X1TS U5820 ( .A(n6520), .B(Data_B_i[46]), .Y(n6348) );
OAI22X1TS U5821 ( .A0(n6618), .A1(n6300), .B0(n6616), .B1(n6348), .Y(n6371)
);
CMPR32X2TS U5822 ( .A(n6303), .B(n6302), .C(n6301), .CO(n6370), .S(n6305) );
OAI22X1TS U5823 ( .A0(n6310), .A1(n6309), .B0(n3026), .B1(n6368), .Y(n6350)
);
XNOR2X1TS U5824 ( .A(n6311), .B(n79), .Y(n6344) );
OAI22X1TS U5825 ( .A0(n74), .A1(n6312), .B0(n6379), .B1(n6344), .Y(n6349) );
XNOR2X1TS U5826 ( .A(n6338), .B(Data_B_i[44]), .Y(n6339) );
OAI22X1TS U5827 ( .A0(n6340), .A1(n6317), .B0(n6316), .B1(n6339), .Y(n6354)
);
XNOR2X1TS U5828 ( .A(n6015), .B(Data_B_i[38]), .Y(n6342) );
OAI22X1TS U5829 ( .A0(n7046), .A1(n6318), .B0(n7045), .B1(n6342), .Y(n6353)
);
XNOR2X1TS U5830 ( .A(n6388), .B(Data_B_i[42]), .Y(n6364) );
OAI22X1TS U5831 ( .A0(n6734), .A1(n6320), .B0(n95), .B1(n6364), .Y(n6352) );
NOR2X2TS U5832 ( .A(n6825), .B(n6824), .Y(n6932) );
INVX2TS U5833 ( .A(n6932), .Y(n7444) );
CMPR32X2TS U5834 ( .A(n6329), .B(n6328), .C(n6327), .CO(n6500), .S(n6375) );
XNOR2X1TS U5835 ( .A(n118), .B(Data_B_i[51]), .Y(n6383) );
OAI22X1TS U5836 ( .A0(n6468), .A1(n6337), .B0(n6541), .B1(n6383), .Y(n6415)
);
XNOR2X1TS U5837 ( .A(n6338), .B(Data_B_i[45]), .Y(n6403) );
OAI22X1TS U5838 ( .A0(n6340), .A1(n6339), .B0(n6643), .B1(n6403), .Y(n6414)
);
XNOR2X1TS U5839 ( .A(n6469), .B(Data_B_i[49]), .Y(n6397) );
OAI22X1TS U5840 ( .A0(n6590), .A1(n6341), .B0(n6523), .B1(n6397), .Y(n6413)
);
XNOR2X1TS U5841 ( .A(n93), .B(Data_B_i[39]), .Y(n6385) );
OAI22X1TS U5842 ( .A0(n7046), .A1(n6342), .B0(n7045), .B1(n6385), .Y(n6412)
);
XNOR2X1TS U5843 ( .A(n6343), .B(n7048), .Y(n6380) );
OAI22X1TS U5844 ( .A0(n5217), .A1(n6344), .B0(n6379), .B1(n6380), .Y(n6411)
);
XNOR2X1TS U5845 ( .A(n6735), .B(Data_B_i[41]), .Y(n6384) );
OAI22X1TS U5846 ( .A0(n6993), .A1(n6345), .B0(n6992), .B1(n6384), .Y(n6410)
);
XNOR2X1TS U5847 ( .A(n6520), .B(n6347), .Y(n6416) );
CMPR32X2TS U5848 ( .A(n6354), .B(n6353), .C(n6352), .CO(n6438), .S(n6355) );
CMPR32X2TS U5849 ( .A(n6357), .B(n6356), .C(n6355), .CO(n6425), .S(n6333) );
XNOR2X1TS U5850 ( .A(n6388), .B(Data_B_i[43]), .Y(n6400) );
OAI22X1TS U5851 ( .A0(n6401), .A1(n6364), .B0(n6709), .B1(n6400), .Y(n6395)
);
XNOR2X1TS U5852 ( .A(n6586), .B(n77), .Y(n6387) );
CMPR32X2TS U5853 ( .A(n6372), .B(n6371), .C(n6370), .CO(n6441), .S(n6335) );
NAND2X2TS U5854 ( .A(n7444), .B(n18), .Y(n6831) );
NOR2X4TS U5855 ( .A(n6926), .B(n6831), .Y(n6939) );
XNOR2X1TS U5856 ( .A(n119), .B(n80), .Y(n6382) );
XNOR2X1TS U5857 ( .A(n118), .B(n7048), .Y(n6467) );
OAI22X1TS U5858 ( .A0(n6468), .A1(n6382), .B0(n6541), .B1(n6467), .Y(n6458)
);
XNOR2X1TS U5859 ( .A(n6469), .B(Data_B_i[50]), .Y(n6396) );
XNOR2X1TS U5860 ( .A(n6469), .B(Data_B_i[51]), .Y(n6470) );
OAI22X1TS U5861 ( .A0(n113), .A1(n6396), .B0(n6523), .B1(n6470), .Y(n6457)
);
XNOR2X1TS U5862 ( .A(Data_A_i[45]), .B(Data_B_i[46]), .Y(n6402) );
XNOR2X1TS U5863 ( .A(Data_A_i[45]), .B(Data_B_i[47]), .Y(n6484) );
OAI22X1TS U5864 ( .A0(n6685), .A1(n6402), .B0(n6643), .B1(n6484), .Y(n6462)
);
OAI22X1TS U5865 ( .A0(n73), .A1(n6380), .B0(n6379), .B1(n6390), .Y(n6421) );
OAI22X1TS U5866 ( .A0(n6468), .A1(n6383), .B0(n138), .B1(n6382), .Y(n6420)
);
XNOR2X1TS U5867 ( .A(Data_A_i[49]), .B(Data_B_i[42]), .Y(n6433) );
OAI22X1TS U5868 ( .A0(n6993), .A1(n6384), .B0(n6480), .B1(n6433), .Y(n6406)
);
XNOR2X1TS U5869 ( .A(Data_A_i[51]), .B(Data_B_i[40]), .Y(n6432) );
OAI22X1TS U5870 ( .A0(n7046), .A1(n6385), .B0(n7045), .B1(n6432), .Y(n6405)
);
XNOR2X1TS U5871 ( .A(n6386), .B(Data_B_i[38]), .Y(n6389) );
OAI22X1TS U5872 ( .A0(n4750), .A1(n6387), .B0(n3047), .B1(n6389), .Y(n6404)
);
XNOR2X1TS U5873 ( .A(n6686), .B(Data_B_i[44]), .Y(n6398) );
XNOR2X1TS U5874 ( .A(n6388), .B(Data_B_i[45]), .Y(n6488) );
OAI22X1TS U5875 ( .A0(n6401), .A1(n6398), .B0(n6709), .B1(n6488), .Y(n6473)
);
XNOR2X1TS U5876 ( .A(Data_A_i[53]), .B(Data_B_i[39]), .Y(n6483) );
OAI22X1TS U5877 ( .A0(n5291), .A1(n6389), .B0(n3047), .B1(n6483), .Y(n6472)
);
OAI22X1TS U5878 ( .A0(n6525), .A1(n6397), .B0(n6523), .B1(n6396), .Y(n6431)
);
OAI22X1TS U5879 ( .A0(n6401), .A1(n6400), .B0(n6399), .B1(n6398), .Y(n6430)
);
OAI22X1TS U5880 ( .A0(n6685), .A1(n6403), .B0(n6643), .B1(n6402), .Y(n6429)
);
CMPR32X2TS U5881 ( .A(n6406), .B(n6405), .C(n6404), .CO(n6460), .S(n6444) );
CMPR32X2TS U5882 ( .A(n6412), .B(n6411), .C(n6410), .CO(n6428), .S(n6408) );
CMPR32X2TS U5883 ( .A(n6415), .B(n6414), .C(n6413), .CO(n6427), .S(n6409) );
XNOR2X1TS U5884 ( .A(n6520), .B(Data_B_i[48]), .Y(n6434) );
OAI22X1TS U5885 ( .A0(n6618), .A1(n6416), .B0(n6616), .B1(n6434), .Y(n6437)
);
CMPR32X2TS U5886 ( .A(n6419), .B(n6418), .C(n6417), .CO(n6436), .S(n6440) );
CMPR32X2TS U5887 ( .A(n6422), .B(n6421), .C(n6420), .CO(n6461), .S(n6435) );
CMPR32X2TS U5888 ( .A(n6428), .B(n6427), .C(n6426), .CO(n6476), .S(n6454) );
CMPR32X2TS U5889 ( .A(n6431), .B(n6430), .C(n6429), .CO(n6491), .S(n6445) );
XNOR2X1TS U5890 ( .A(n4069), .B(Data_B_i[41]), .Y(n6486) );
OAI22X1TS U5891 ( .A0(n7046), .A1(n6432), .B0(n7045), .B1(n6486), .Y(n6479)
);
XNOR2X1TS U5892 ( .A(Data_A_i[49]), .B(Data_B_i[43]), .Y(n6481) );
OAI22X1TS U5893 ( .A0(n6993), .A1(n6433), .B0(n6480), .B1(n6481), .Y(n6478)
);
XNOR2X1TS U5894 ( .A(n6520), .B(Data_B_i[49]), .Y(n6482) );
OAI22X1TS U5895 ( .A0(n6618), .A1(n6434), .B0(n6616), .B1(n6482), .Y(n6477)
);
CMPR32X2TS U5896 ( .A(n6437), .B(n6436), .C(n6435), .CO(n6489), .S(n6426) );
CMPR32X2TS U5897 ( .A(n6440), .B(n6439), .C(n6438), .CO(n6449), .S(n6407) );
CMPR32X2TS U5898 ( .A(n6443), .B(n6442), .C(n6441), .CO(n6448), .S(n6423) );
CMPR32X2TS U5899 ( .A(n6446), .B(n6445), .C(n6444), .CO(n6492), .S(n6447) );
ADDFHX1TS U5900 ( .A(n6455), .B(n6454), .CI(n6453), .CO(n6496), .S(n6501) );
CMPR32X2TS U5901 ( .A(n6458), .B(n6457), .C(n6456), .CO(n6663), .S(n6494) );
CMPR32X2TS U5902 ( .A(n6464), .B(n6463), .C(n6462), .CO(n6517), .S(n6456) );
OAI22X1TS U5903 ( .A0(n6468), .A1(n6467), .B0(n6541), .B1(n6540), .Y(n6513)
);
XNOR2X1TS U5904 ( .A(n6469), .B(n80), .Y(n6524) );
OAI22X1TS U5905 ( .A0(n6525), .A1(n6470), .B0(n6523), .B1(n6524), .Y(n6512)
);
CMPR32X2TS U5906 ( .A(n6473), .B(n6472), .C(n6471), .CO(n6515), .S(n6459) );
CMPR32X2TS U5907 ( .A(n6479), .B(n6478), .C(n6477), .CO(n6559), .S(n6490) );
XNOR2X1TS U5908 ( .A(n6610), .B(Data_B_i[44]), .Y(n6536) );
OAI22X1TS U5909 ( .A0(n123), .A1(n6481), .B0(n6480), .B1(n6536), .Y(n6534)
);
XNOR2X1TS U5910 ( .A(n6520), .B(Data_B_i[50]), .Y(n6508) );
OAI22X1TS U5911 ( .A0(n6618), .A1(n6482), .B0(n6616), .B1(n6508), .Y(n6533)
);
XNOR2X1TS U5912 ( .A(n6531), .B(Data_B_i[40]), .Y(n6539) );
OAI22X1TS U5913 ( .A0(n5291), .A1(n6483), .B0(n3047), .B1(n6539), .Y(n6532)
);
XNOR2X1TS U5914 ( .A(Data_A_i[45]), .B(Data_B_i[48]), .Y(n6510) );
OAI22X1TS U5915 ( .A0(n6685), .A1(n6484), .B0(n6643), .B1(n6510), .Y(n6507)
);
XNOR2X1TS U5916 ( .A(Data_A_i[51]), .B(Data_B_i[42]), .Y(n6526) );
OAI22X1TS U5917 ( .A0(n7019), .A1(n6486), .B0(n6528), .B1(n6526), .Y(n6506)
);
XNOR2X1TS U5918 ( .A(n6686), .B(Data_B_i[46]), .Y(n6527) );
OAI22X1TS U5919 ( .A0(n6734), .A1(n6488), .B0(n95), .B1(n6527), .Y(n6505) );
CMPR32X2TS U5920 ( .A(n6491), .B(n6490), .C(n6489), .CO(n6668), .S(n6475) );
CMPR32X2TS U5921 ( .A(n6494), .B(n6493), .C(n6492), .CO(n6667), .S(n6497) );
INVX2TS U5922 ( .A(n6504), .Y(n6947) );
NAND2X2TS U5923 ( .A(n6839), .B(n6947), .Y(n6912) );
CMPR32X2TS U5924 ( .A(n6507), .B(n6506), .C(n6505), .CO(n6565), .S(n6557) );
XNOR2X1TS U5925 ( .A(n6520), .B(Data_B_i[51]), .Y(n6521) );
OAI22X1TS U5926 ( .A0(n6618), .A1(n6508), .B0(n6616), .B1(n6521), .Y(n6556)
);
NOR2X1TS U5927 ( .A(n7091), .B(n6509), .Y(n6552) );
XNOR2X1TS U5928 ( .A(Data_A_i[45]), .B(Data_B_i[49]), .Y(n6549) );
OAI22X1TS U5929 ( .A0(n6511), .A1(n6510), .B0(n6643), .B1(n6549), .Y(n6551)
);
CMPR32X2TS U5930 ( .A(n6517), .B(n6516), .C(n6515), .CO(n6563), .S(n6661) );
XNOR2X1TS U5931 ( .A(n6519), .B(n7048), .Y(n6522) );
OAI22X1TS U5932 ( .A0(n4688), .A1(n6522), .B0(n6523), .B1(n6588), .Y(n6572)
);
XNOR2X1TS U5933 ( .A(n6520), .B(n80), .Y(n6581) );
OAI22X1TS U5934 ( .A0(n6618), .A1(n6521), .B0(n6616), .B1(n6581), .Y(n6571)
);
OAI22X1TS U5935 ( .A0(n6590), .A1(n6524), .B0(n6523), .B1(n6522), .Y(n6545)
);
XNOR2X1TS U5936 ( .A(Data_A_i[51]), .B(Data_B_i[43]), .Y(n6529) );
OAI22X1TS U5937 ( .A0(n6583), .A1(n6526), .B0(n6528), .B1(n6529), .Y(n6544)
);
XNOR2X1TS U5938 ( .A(n6686), .B(Data_B_i[47]), .Y(n6550) );
OAI22X1TS U5939 ( .A0(n6734), .A1(n6527), .B0(n6709), .B1(n6550), .Y(n6543)
);
XNOR2X1TS U5940 ( .A(n4069), .B(Data_B_i[44]), .Y(n6582) );
OAI22X1TS U5941 ( .A0(n6583), .A1(n6529), .B0(n6528), .B1(n6582), .Y(n6576)
);
XNOR2X1TS U5942 ( .A(n6735), .B(Data_B_i[45]), .Y(n6535) );
CLKBUFX2TS U5943 ( .A(n2558), .Y(n6887) );
XNOR2X1TS U5944 ( .A(n6735), .B(Data_B_i[46]), .Y(n6585) );
OAI22X1TS U5945 ( .A0(n6889), .A1(n6535), .B0(n6887), .B1(n6585), .Y(n6575)
);
XNOR2X1TS U5946 ( .A(n6531), .B(Data_B_i[41]), .Y(n6538) );
XNOR2X1TS U5947 ( .A(n6531), .B(Data_B_i[42]), .Y(n6587) );
OAI22X1TS U5948 ( .A0(n6657), .A1(n6538), .B0(n6605), .B1(n6587), .Y(n6574)
);
CMPR32X2TS U5949 ( .A(n6534), .B(n6533), .C(n6532), .CO(n6562), .S(n6558) );
OAI22X1TS U5950 ( .A0(n122), .A1(n6536), .B0(n6887), .B1(n6535), .Y(n6548)
);
OAI22X1TS U5951 ( .A0(n4750), .A1(n6539), .B0(n3047), .B1(n6538), .Y(n6547)
);
CMPR32X2TS U5952 ( .A(n6545), .B(n6544), .C(n6543), .CO(n6578), .S(n6560) );
CMPR32X2TS U5953 ( .A(n6548), .B(n6547), .C(n6546), .CO(n6568), .S(n6561) );
XNOR2X1TS U5954 ( .A(Data_A_i[45]), .B(Data_B_i[50]), .Y(n6584) );
OAI22X1TS U5955 ( .A0(n6685), .A1(n6549), .B0(n6643), .B1(n6584), .Y(n6593)
);
XNOR2X1TS U5956 ( .A(n6686), .B(Data_B_i[48]), .Y(n6570) );
OAI22X1TS U5957 ( .A0(n6734), .A1(n6550), .B0(n6732), .B1(n6570), .Y(n6592)
);
CMPR32X2TS U5958 ( .A(n6556), .B(n6555), .C(n6554), .CO(n6566), .S(n6564) );
CMPR32X2TS U5959 ( .A(n6559), .B(n6558), .C(n6557), .CO(n6666), .S(n6669) );
CMPR32X2TS U5960 ( .A(n6562), .B(n6561), .C(n6560), .CO(n6595), .S(n6665) );
CMPR32X2TS U5961 ( .A(n6568), .B(n6567), .C(n6566), .CO(n6628), .S(n6594) );
XNOR2X1TS U5962 ( .A(n6686), .B(Data_B_i[49]), .Y(n6604) );
OAI22X1TS U5963 ( .A0(n6734), .A1(n6570), .B0(n6732), .B1(n6604), .Y(n6612)
);
CMPR32X2TS U5964 ( .A(n6576), .B(n6575), .C(n6574), .CO(n6620), .S(n6577) );
XNOR2X1TS U5965 ( .A(n6580), .B(n7048), .Y(n6617) );
OAI22X1TS U5966 ( .A0(n6618), .A1(n6581), .B0(n6616), .B1(n6617), .Y(n6602)
);
XNOR2X1TS U5967 ( .A(n93), .B(Data_B_i[45]), .Y(n6603) );
OAI22X1TS U5968 ( .A0(n6583), .A1(n6582), .B0(n7017), .B1(n6603), .Y(n6601)
);
XNOR2X1TS U5969 ( .A(Data_A_i[45]), .B(Data_B_i[51]), .Y(n6619) );
OAI22X1TS U5970 ( .A0(n6685), .A1(n6584), .B0(n6643), .B1(n6619), .Y(n6600)
);
XNOR2X1TS U5971 ( .A(n6735), .B(Data_B_i[47]), .Y(n6611) );
OAI22X1TS U5972 ( .A0(n6889), .A1(n6585), .B0(n6887), .B1(n6611), .Y(n6599)
);
XNOR2X1TS U5973 ( .A(n7020), .B(Data_B_i[43]), .Y(n6606) );
OAI22X1TS U5974 ( .A0(n13), .A1(n6587), .B0(n6605), .B1(n6606), .Y(n6598) );
NOR2X2TS U5975 ( .A(n6845), .B(n6844), .Y(n7168) );
INVX2TS U5976 ( .A(n7168), .Y(n7488) );
CMPR32X2TS U5977 ( .A(n6599), .B(n6598), .C(n6597), .CO(n6635), .S(n6624) );
CMPR32X2TS U5978 ( .A(n6602), .B(n6601), .C(n6600), .CO(n6634), .S(n6625) );
XNOR2X1TS U5979 ( .A(n6890), .B(Data_B_i[46]), .Y(n6654) );
OAI22X1TS U5980 ( .A0(n7019), .A1(n6603), .B0(n7017), .B1(n6654), .Y(n6653)
);
XNOR2X1TS U5981 ( .A(n6686), .B(Data_B_i[50]), .Y(n6647) );
OAI22X1TS U5982 ( .A0(n6734), .A1(n6604), .B0(n6732), .B1(n6647), .Y(n6652)
);
XNOR2X1TS U5983 ( .A(n7020), .B(Data_B_i[44]), .Y(n6656) );
OAI22X1TS U5984 ( .A0(n7093), .A1(n6606), .B0(n6605), .B1(n6656), .Y(n6651)
);
XNOR2X1TS U5985 ( .A(n6610), .B(Data_B_i[48]), .Y(n6645) );
OAI22X1TS U5986 ( .A0(n6889), .A1(n6611), .B0(n6887), .B1(n6645), .Y(n6641)
);
CMPR32X2TS U5987 ( .A(n6614), .B(n6613), .C(n6612), .CO(n6640), .S(n6622) );
OAI22X1TS U5988 ( .A0(n6618), .A1(n6617), .B0(n6616), .B1(n6658), .Y(n6649)
);
XNOR2X1TS U5989 ( .A(Data_A_i[45]), .B(n80), .Y(n6644) );
OAI22X1TS U5990 ( .A0(n6685), .A1(n6619), .B0(n6643), .B1(n6644), .Y(n6648)
);
CMPR32X2TS U5991 ( .A(n6622), .B(n6621), .C(n6620), .CO(n6637), .S(n6609) );
CMPR32X2TS U5992 ( .A(n6625), .B(n6624), .C(n6623), .CO(n6636), .S(n6607) );
INVX2TS U5993 ( .A(n6629), .Y(n7172) );
NAND2X2TS U5994 ( .A(n7488), .B(n7172), .Y(n7284) );
CMPR32X2TS U5995 ( .A(n6635), .B(n6634), .C(n6633), .CO(n6750), .S(n6632) );
CMPR32X2TS U5996 ( .A(n6638), .B(n6637), .C(n6636), .CO(n6749), .S(n6630) );
CMPR32X2TS U5997 ( .A(n6641), .B(n6640), .C(n6639), .CO(n6721), .S(n6638) );
XNOR2X1TS U5998 ( .A(n6642), .B(n7048), .Y(n6684) );
OAI22X1TS U5999 ( .A0(n6685), .A1(n6644), .B0(n6643), .B1(n6684), .Y(n6696)
);
XNOR2X1TS U6000 ( .A(n6735), .B(Data_B_i[49]), .Y(n6692) );
OAI22X1TS U6001 ( .A0(n6889), .A1(n6645), .B0(n6887), .B1(n6692), .Y(n6695)
);
XNOR2X1TS U6002 ( .A(n6686), .B(Data_B_i[51]), .Y(n6687) );
OAI22X1TS U6003 ( .A0(n6734), .A1(n6647), .B0(n6732), .B1(n6687), .Y(n6679)
);
CMPR32X2TS U6004 ( .A(n6650), .B(n6649), .C(n6648), .CO(n6699), .S(n6639) );
CMPR32X2TS U6005 ( .A(n6653), .B(n6652), .C(n6651), .CO(n6698), .S(n6633) );
XNOR2X1TS U6006 ( .A(n6890), .B(Data_B_i[47]), .Y(n6691) );
OAI22X1TS U6007 ( .A0(n7019), .A1(n6654), .B0(n7017), .B1(n6691), .Y(n6690)
);
XNOR2X1TS U6008 ( .A(n7020), .B(Data_B_i[45]), .Y(n6693) );
OAI22X1TS U6009 ( .A0(n7093), .A1(n6656), .B0(n7059), .B1(n6693), .Y(n6689)
);
NOR2X1TS U6010 ( .A(n7284), .B(n7287), .Y(n6853) );
CMPR32X2TS U6011 ( .A(n6663), .B(n6662), .C(n6661), .CO(n6675), .S(n6672) );
ADDFHX2TS U6012 ( .A(n6666), .B(n6665), .CI(n6664), .CO(n6676), .S(n6674) );
CMPR32X2TS U6013 ( .A(n6669), .B(n6668), .C(n6667), .CO(n6673), .S(n6670) );
NOR2X2TS U6014 ( .A(n6843), .B(n6842), .Y(n6921) );
NOR2X2TS U6015 ( .A(n6912), .B(n6855), .Y(n6857) );
NAND2X2TS U6016 ( .A(n6939), .B(n6857), .Y(n7054) );
INVX2TS U6017 ( .A(n7054), .Y(n6859) );
NOR2X4TS U6018 ( .A(n7292), .B(n6861), .Y(n7308) );
INVX2TS U6019 ( .A(n7308), .Y(n7448) );
CMPR32X2TS U6020 ( .A(n6681), .B(n6680), .C(n6679), .CO(n6718), .S(n6694) );
OAI22X1TS U6021 ( .A0(n6685), .A1(n6684), .B0(n6683), .B1(n6705), .Y(n6714)
);
XNOR2X1TS U6022 ( .A(n6686), .B(n79), .Y(n6710) );
OAI22X1TS U6023 ( .A0(n6734), .A1(n6687), .B0(n6732), .B1(n6710), .Y(n6713)
);
XNOR2X1TS U6024 ( .A(n6995), .B(Data_B_i[48]), .Y(n6703) );
OAI22X1TS U6025 ( .A0(n7019), .A1(n6691), .B0(n7017), .B1(n6703), .Y(n6702)
);
XNOR2X1TS U6026 ( .A(n6735), .B(Data_B_i[50]), .Y(n6712) );
OAI22X1TS U6027 ( .A0(n6889), .A1(n6692), .B0(n6887), .B1(n6712), .Y(n6701)
);
XNOR2X1TS U6028 ( .A(n7020), .B(Data_B_i[46]), .Y(n6704) );
OAI22X1TS U6029 ( .A0(n6657), .A1(n6693), .B0(n7059), .B1(n6704), .Y(n6700)
);
CMPR32X2TS U6030 ( .A(n6696), .B(n6695), .C(n6694), .CO(n6723), .S(n6720) );
CMPR32X2TS U6031 ( .A(n6699), .B(n6698), .C(n6697), .CO(n6722), .S(n6719) );
CMPR32X2TS U6032 ( .A(n6702), .B(n6701), .C(n6700), .CO(n6747), .S(n6724) );
XNOR2X1TS U6033 ( .A(n93), .B(Data_B_i[49]), .Y(n6740) );
OAI22X1TS U6034 ( .A0(n7019), .A1(n6703), .B0(n7017), .B1(n6740), .Y(n6739)
);
XNOR2X1TS U6035 ( .A(n7020), .B(Data_B_i[47]), .Y(n6741) );
OAI22X1TS U6036 ( .A0(n6657), .A1(n6704), .B0(n7059), .B1(n6741), .Y(n6738)
);
XNOR2X1TS U6037 ( .A(n6708), .B(n7048), .Y(n6733) );
OAI22X1TS U6038 ( .A0(n6734), .A1(n6710), .B0(n6709), .B1(n6733), .Y(n6730)
);
XNOR2X1TS U6039 ( .A(n6735), .B(Data_B_i[51]), .Y(n6736) );
OAI22X1TS U6040 ( .A0(n6889), .A1(n6712), .B0(n6887), .B1(n6736), .Y(n6742)
);
CMPR32X2TS U6041 ( .A(n6715), .B(n6714), .C(n6713), .CO(n6728), .S(n6717) );
CMPR32X2TS U6042 ( .A(n6718), .B(n6717), .C(n6716), .CO(n6727), .S(n6753) );
CMPR32X2TS U6043 ( .A(n6721), .B(n6720), .C(n6719), .CO(n6752), .S(n6748) );
CMPR32X2TS U6044 ( .A(n6724), .B(n6723), .C(n6722), .CO(n6726), .S(n6751) );
NOR2X2TS U6045 ( .A(n6865), .B(n6864), .Y(n7470) );
CMPR32X2TS U6046 ( .A(n6727), .B(n6726), .C(n6725), .CO(n6867), .S(n6865) );
CMPR32X2TS U6047 ( .A(n6730), .B(n6729), .C(n6728), .CO(n6756), .S(n6745) );
OAI22X1TS U6048 ( .A0(n6734), .A1(n6733), .B0(n6732), .B1(n6768), .Y(n6764)
);
XNOR2X1TS U6049 ( .A(n6735), .B(n80), .Y(n6762) );
OAI22X1TS U6050 ( .A0(n6889), .A1(n6736), .B0(n6887), .B1(n6762), .Y(n6763)
);
XNOR2X1TS U6051 ( .A(n6015), .B(Data_B_i[50]), .Y(n6766) );
OAI22X1TS U6052 ( .A0(n7019), .A1(n6740), .B0(n7017), .B1(n6766), .Y(n6759)
);
XNOR2X1TS U6053 ( .A(n7020), .B(Data_B_i[48]), .Y(n6767) );
OAI22X1TS U6054 ( .A0(n6657), .A1(n6741), .B0(n7059), .B1(n6767), .Y(n6758)
);
CMPR32X2TS U6055 ( .A(n6744), .B(n6743), .C(n6742), .CO(n6757), .S(n6729) );
CMPR32X2TS U6056 ( .A(n6747), .B(n6746), .C(n6745), .CO(n6754), .S(n6725) );
CMPR32X2TS U6057 ( .A(n6750), .B(n6749), .C(n6748), .CO(n6863), .S(n6850) );
ADDFHX1TS U6058 ( .A(n6753), .B(n6752), .CI(n6751), .CO(n6864), .S(n6862) );
CMPR32X2TS U6059 ( .A(n6756), .B(n6755), .C(n6754), .CO(n6871), .S(n6866) );
CMPR32X2TS U6060 ( .A(n6759), .B(n6758), .C(n6757), .CO(n6878), .S(n6771) );
XNOR2X1TS U6061 ( .A(n6761), .B(n7048), .Y(n6888) );
OAI22X1TS U6062 ( .A0(n6889), .A1(n6762), .B0(n6887), .B1(n6888), .Y(n6883)
);
CMPR32X2TS U6063 ( .A(n6765), .B(n6764), .C(n6763), .CO(n6893), .S(n6773) );
XNOR2X1TS U6064 ( .A(n6890), .B(Data_B_i[51]), .Y(n6891) );
OAI22X1TS U6065 ( .A0(n7019), .A1(n6766), .B0(n7017), .B1(n6891), .Y(n6881)
);
XNOR2X1TS U6066 ( .A(n7020), .B(Data_B_i[49]), .Y(n6882) );
OAI22X1TS U6067 ( .A0(n6657), .A1(n6767), .B0(n7059), .B1(n6882), .Y(n6880)
);
CMPR32X2TS U6068 ( .A(n6773), .B(n6772), .C(n6771), .CO(n6876), .S(n6755) );
NOR2X1TS U6069 ( .A(n6900), .B(n6904), .Y(n6979) );
CLKINVX1TS U6070 ( .A(n6979), .Y(n6873) );
NAND2X2TS U6071 ( .A(n6775), .B(n6774), .Y(n7459) );
NAND2X2TS U6072 ( .A(n6777), .B(n6776), .Y(n7463) );
OA21X4TS U6073 ( .A0(n7463), .A1(n6780), .B0(n7136), .Y(n6781) );
OAI21X4TS U6074 ( .A0(n6782), .A1(n7459), .B0(n6781), .Y(n7030) );
NAND2X2TS U6075 ( .A(n6784), .B(n6783), .Y(n7395) );
AOI21X4TS U6076 ( .A0(n7402), .A1(n6787), .B0(n7400), .Y(n7031) );
NAND2X1TS U6077 ( .A(n6791), .B(n6790), .Y(n7149) );
OA21X4TS U6078 ( .A0(n7148), .A1(n7143), .B0(n7149), .Y(n6792) );
OAI21X4TS U6079 ( .A0(n7031), .A1(n6793), .B0(n6792), .Y(n6794) );
AOI21X4TS U6080 ( .A0(n7030), .A1(n6795), .B0(n6794), .Y(n7106) );
NAND2X1TS U6081 ( .A(n6803), .B(n6802), .Y(n7129) );
AOI21X4TS U6082 ( .A0(n7115), .A1(n6805), .B0(n6804), .Y(n7104) );
NAND2X2TS U6083 ( .A(n6807), .B(n6806), .Y(n7304) );
OAI21X2TS U6084 ( .A0(n7110), .A1(n7304), .B0(n7111), .Y(n7406) );
NAND2X1TS U6085 ( .A(n6811), .B(n6810), .Y(n7415) );
NAND2X1TS U6086 ( .A(n6813), .B(n6812), .Y(n7421) );
OAI21X1TS U6087 ( .A0(n7420), .A1(n7415), .B0(n7421), .Y(n6814) );
OAI21X4TS U6088 ( .A0(n7104), .A1(n6817), .B0(n6816), .Y(n7080) );
NAND2X2TS U6089 ( .A(n6819), .B(n6818), .Y(n7431) );
NAND2X1TS U6090 ( .A(n6821), .B(n6820), .Y(n7436) );
INVX2TS U6091 ( .A(n7436), .Y(n6822) );
INVX2TS U6092 ( .A(n7443), .Y(n6829) );
NAND2X1TS U6093 ( .A(n6827), .B(n6826), .Y(n6935) );
OAI21X2TS U6094 ( .A0(n6929), .A1(n6831), .B0(n6830), .Y(n6938) );
INVX2TS U6095 ( .A(n6942), .Y(n6946) );
NAND2X2TS U6096 ( .A(n6841), .B(n6840), .Y(n6966) );
NAND2X1TS U6097 ( .A(n6847), .B(n6846), .Y(n7171) );
NAND2X1TS U6098 ( .A(n6851), .B(n6850), .Y(n7288) );
AOI21X2TS U6099 ( .A0(n6938), .A1(n6857), .B0(n6856), .Y(n7077) );
INVX2TS U6100 ( .A(n7077), .Y(n6858) );
OAI21X2TS U6101 ( .A0(n7106), .A1(n6861), .B0(n6860), .Y(n7004) );
INVX2TS U6102 ( .A(n7004), .Y(n7452) );
NAND2X1TS U6103 ( .A(n6863), .B(n6862), .Y(n7309) );
INVX2TS U6104 ( .A(n7309), .Y(n6970) );
NAND2X1TS U6105 ( .A(n6867), .B(n6866), .Y(n6975) );
OAI21X1TS U6106 ( .A0(n7452), .A1(n6873), .B0(n6872), .Y(n6874) );
AOI21X1TS U6107 ( .A0(n6875), .A1(n32), .B0(n6874), .Y(n6898) );
CMPR32X2TS U6108 ( .A(n6878), .B(n6877), .C(n6876), .CO(n6896), .S(n6870) );
CMPR32X2TS U6109 ( .A(n6881), .B(n6880), .C(n6879), .CO(n6982), .S(n6892) );
XNOR2X1TS U6110 ( .A(n7020), .B(Data_B_i[50]), .Y(n6990) );
OAI22X1TS U6111 ( .A0(n6657), .A1(n6882), .B0(n7059), .B1(n6990), .Y(n6988)
);
CMPR32X2TS U6112 ( .A(n6885), .B(n6884), .C(n6883), .CO(n6987), .S(n6894) );
OAI22X1TS U6113 ( .A0(n6889), .A1(n6888), .B0(n6887), .B1(n6991), .Y(n6984)
);
XNOR2X1TS U6114 ( .A(n4069), .B(n79), .Y(n6996) );
OAI22X1TS U6115 ( .A0(n7019), .A1(n6891), .B0(n7017), .B1(n6996), .Y(n6983)
);
CMPR32X2TS U6116 ( .A(n6894), .B(n6893), .C(n6892), .CO(n6980), .S(n6877) );
NAND2X1TS U6117 ( .A(n7000), .B(n6998), .Y(n6897) );
OAI21X1TS U6118 ( .A0(n7452), .A1(n6900), .B0(n6899), .Y(n6903) );
INVX2TS U6119 ( .A(n6939), .Y(n6909) );
NOR2X2TS U6120 ( .A(n6909), .B(n6912), .Y(n6915) );
NAND2X2TS U6121 ( .A(n7055), .B(n6915), .Y(n6917) );
NOR2X2TS U6122 ( .A(n7292), .B(n6917), .Y(n7164) );
NOR2X1TS U6123 ( .A(n6910), .B(n6965), .Y(n6920) );
CLKINVX1TS U6124 ( .A(n6938), .Y(n6913) );
AOI21X2TS U6125 ( .A0(n6915), .A1(n7080), .B0(n6914), .Y(n6916) );
OAI21X2TS U6126 ( .A0(n7106), .A1(n6917), .B0(n6916), .Y(n7167) );
CLKINVX1TS U6127 ( .A(n7167), .Y(n6918) );
OAI21X1TS U6128 ( .A0(n6918), .A1(n6965), .B0(n6966), .Y(n6919) );
AOI21X1TS U6129 ( .A0(n33), .A1(n6920), .B0(n6919), .Y(n6925) );
NAND2X1TS U6130 ( .A(n6923), .B(n6922), .Y(n6924) );
XOR2XLTS U6131 ( .A(n6925), .B(n6924), .Y(N94) );
INVX2TS U6132 ( .A(n7055), .Y(n6928) );
NOR2X2TS U6133 ( .A(n7292), .B(n6928), .Y(n7428) );
INVX2TS U6134 ( .A(n6926), .Y(n6931) );
NAND2X1TS U6135 ( .A(n7428), .B(n6931), .Y(n7439) );
OAI21X2TS U6136 ( .A0(n7106), .A1(n6928), .B0(n6927), .Y(n7430) );
OAI21X1TS U6137 ( .A0(n7440), .A1(n6932), .B0(n7443), .Y(n6933) );
AOI21X1TS U6138 ( .A0(n34), .A1(n6934), .B0(n6933), .Y(n6937) );
NAND2X1TS U6139 ( .A(n18), .B(n6935), .Y(n6936) );
XOR2XLTS U6140 ( .A(n6937), .B(n6936), .Y(N89) );
NOR2X1TS U6141 ( .A(n7292), .B(n6941), .Y(n6945) );
OAI21X2TS U6142 ( .A0(n7106), .A1(n6941), .B0(n6940), .Y(n6948) );
AOI21X1TS U6143 ( .A0(n7486), .A1(n6945), .B0(n6948), .Y(n6944) );
NAND2X1TS U6144 ( .A(n6947), .B(n6942), .Y(n6943) );
XOR2XLTS U6145 ( .A(n6944), .B(n6943), .Y(N90) );
NAND2X1TS U6146 ( .A(n6945), .B(n6947), .Y(n6954) );
AOI21X1TS U6147 ( .A0(n7486), .A1(n6950), .B0(n6949), .Y(n6953) );
NAND2X1TS U6148 ( .A(n6951), .B(n6955), .Y(n6952) );
XOR2XLTS U6149 ( .A(n6953), .B(n6952), .Y(N91) );
NOR2X1TS U6150 ( .A(n6954), .B(n6956), .Y(n6959) );
NAND2X1TS U6151 ( .A(n6962), .B(n6961), .Y(n6963) );
XOR2XLTS U6152 ( .A(n6964), .B(n6963), .Y(N92) );
AOI21X1TS U6153 ( .A0(n7486), .A1(n7164), .B0(n7167), .Y(n6969) );
NAND2X1TS U6154 ( .A(n6967), .B(n6966), .Y(n6968) );
XOR2XLTS U6155 ( .A(n6969), .B(n6968), .Y(N93) );
OAI21X1TS U6156 ( .A0(n7467), .A1(n7470), .B0(n7471), .Y(n6973) );
NAND2BX2TS U6157 ( .AN(n6973), .B(n6972), .Y(n6978) );
XOR2X4TS U6158 ( .A(n6978), .B(n6977), .Y(N100) );
INVX2TS U6159 ( .A(n7040), .Y(n7003) );
CMPR32X2TS U6160 ( .A(n6982), .B(n6981), .C(n6980), .CO(n7006), .S(n6895) );
CMPR32X2TS U6161 ( .A(n6985), .B(n6984), .C(n6983), .CO(n7011), .S(n6986) );
CMPR32X2TS U6162 ( .A(n6988), .B(n6987), .C(n6986), .CO(n7010), .S(n6981) );
XNOR2X1TS U6163 ( .A(n7020), .B(n6989), .Y(n7021) );
OAI22X1TS U6164 ( .A0(n6657), .A1(n6990), .B0(n7059), .B1(n7021), .Y(n7024)
);
XNOR2X1TS U6165 ( .A(n6015), .B(n7048), .Y(n7018) );
OAI22X1TS U6166 ( .A0(n7019), .A1(n6996), .B0(n7017), .B1(n7018), .Y(n7012)
);
NAND2X2TS U6167 ( .A(n34), .B(n6997), .Y(n7008) );
INVX2TS U6168 ( .A(n6998), .Y(n6999) );
CMPR32X2TS U6169 ( .A(n7011), .B(n7010), .C(n7009), .CO(n7026), .S(n7005) );
CMPR32X2TS U6170 ( .A(n7014), .B(n7013), .C(n7012), .CO(n7043), .S(n7022) );
OAI22X1TS U6171 ( .A0(n7019), .A1(n7018), .B0(n7017), .B1(n7044), .Y(n7052)
);
XNOR2X1TS U6172 ( .A(n7020), .B(n79), .Y(n7050) );
OAI22X1TS U6173 ( .A0(n6657), .A1(n7021), .B0(n7059), .B1(n7050), .Y(n7051)
);
CMPR32X2TS U6174 ( .A(n7024), .B(n7023), .C(n7022), .CO(n7041), .S(n7009) );
NAND2X1TS U6175 ( .A(n7026), .B(n7025), .Y(n7065) );
NAND2X1TS U6176 ( .A(n7067), .B(n7065), .Y(n7027) );
INVX2TS U6177 ( .A(n7029), .Y(n7033) );
NAND2X1TS U6178 ( .A(n7392), .B(n7033), .Y(n7142) );
AOI21X1TS U6179 ( .A0(n7033), .A1(n7030), .B0(n7032), .Y(n7145) );
AOI21X1TS U6180 ( .A0(n34), .A1(n7035), .B0(n7034), .Y(n7038) );
NAND2X1TS U6181 ( .A(n7036), .B(n7143), .Y(n7037) );
XOR2XLTS U6182 ( .A(n7038), .B(n7037), .Y(N76) );
INVX2TS U6183 ( .A(n7039), .Y(n7480) );
CMPR32X2TS U6184 ( .A(n7043), .B(n7042), .C(n7041), .CO(n7073), .S(n7025) );
XNOR2X1TS U6185 ( .A(n7049), .B(n7048), .Y(n7060) );
OAI22X1TS U6186 ( .A0(n6657), .A1(n7050), .B0(n7059), .B1(n7060), .Y(n7061)
);
CMPR32X2TS U6187 ( .A(n7053), .B(n7052), .C(n7051), .CO(n7056), .S(n7042) );
NAND2X1TS U6188 ( .A(n7447), .B(n7456), .Y(n7076) );
NOR2X1TS U6189 ( .A(n7054), .B(n7076), .Y(n7079) );
NAND2X1TS U6190 ( .A(n7079), .B(n7055), .Y(n7082) );
NOR2X1TS U6191 ( .A(n7292), .B(n7082), .Y(n7159) );
CMPR32X2TS U6192 ( .A(n7058), .B(n7057), .C(n7056), .CO(n7084), .S(n7072) );
OAI22X1TS U6193 ( .A0(n13), .A1(n7060), .B0(n7059), .B1(n7092), .Y(n7088) );
CMPR32X2TS U6194 ( .A(n7063), .B(n7062), .C(n7061), .CO(n7087), .S(n7057) );
NAND2X1TS U6195 ( .A(n7159), .B(n7161), .Y(n7064) );
BUFX6TS U6196 ( .A(n7106), .Y(n7294) );
AOI21X1TS U6197 ( .A0(n7068), .A1(n7067), .B0(n7066), .Y(n7069) );
NAND2X1TS U6198 ( .A(n7073), .B(n7072), .Y(n7455) );
AOI21X1TS U6199 ( .A0(n7449), .A1(n7456), .B0(n7074), .Y(n7075) );
AOI21X1TS U6200 ( .A0(n7080), .A1(n7079), .B0(n7078), .Y(n7081) );
OAI2BB1X4TS U6201 ( .A0N(n7158), .A1N(n7161), .B0(n7160), .Y(n7085) );
AOI21X1TS U6202 ( .A0(n33), .A1(n7086), .B0(n7085), .Y(n7102) );
CMPR32X2TS U6203 ( .A(n7089), .B(n7088), .C(n7087), .CO(n7098), .S(n7083) );
NAND2X1TS U6204 ( .A(n7098), .B(n7097), .Y(n7099) );
NAND2X1TS U6205 ( .A(n7100), .B(n7099), .Y(n7101) );
XOR2XLTS U6206 ( .A(n7102), .B(n7101), .Y(N107) );
OAI21X2TS U6207 ( .A0(n7106), .A1(n7105), .B0(n7104), .Y(n7408) );
CLKINVX1TS U6208 ( .A(n7408), .Y(n7107) );
AOI21X1TS U6209 ( .A0(n33), .A1(n7109), .B0(n7108), .Y(n7114) );
NAND2X1TS U6210 ( .A(n7112), .B(n7111), .Y(n7113) );
XOR2XLTS U6211 ( .A(n7114), .B(n7113), .Y(N83) );
INVX2TS U6212 ( .A(n7292), .Y(n7154) );
NAND2X1TS U6213 ( .A(n7154), .B(n7116), .Y(n7122) );
AOI21X1TS U6214 ( .A0(n33), .A1(n7118), .B0(n7117), .Y(n7121) );
NAND2X1TS U6215 ( .A(n7119), .B(n7123), .Y(n7120) );
XOR2XLTS U6216 ( .A(n7121), .B(n7120), .Y(N80) );
NAND2X1TS U6217 ( .A(n7130), .B(n7129), .Y(n7131) );
XOR2XLTS U6218 ( .A(n7132), .B(n7131), .Y(N81) );
NOR2XLTS U6219 ( .A(n7348), .B(n7133), .Y(n7135) );
AOI21X1TS U6220 ( .A0(n33), .A1(n7135), .B0(n7134), .Y(n7139) );
NAND2X1TS U6221 ( .A(n7137), .B(n7136), .Y(n7138) );
XOR2XLTS U6222 ( .A(n7139), .B(n7138), .Y(N73) );
AOI21X1TS U6223 ( .A0(n34), .A1(n7392), .B0(n7030), .Y(n7141) );
NAND2X1TS U6224 ( .A(n7393), .B(n7395), .Y(n7140) );
XOR2XLTS U6225 ( .A(n7141), .B(n7140), .Y(N74) );
AOI21X1TS U6226 ( .A0(n34), .A1(n7147), .B0(n7146), .Y(n7152) );
NAND2X1TS U6227 ( .A(n7150), .B(n7149), .Y(n7151) );
XOR2XLTS U6228 ( .A(n7152), .B(n7151), .Y(N77) );
AOI21X1TS U6229 ( .A0(n7486), .A1(n7154), .B0(n7153), .Y(n7157) );
NAND2X1TS U6230 ( .A(n7155), .B(n7293), .Y(n7156) );
XOR2XLTS U6231 ( .A(n7157), .B(n7156), .Y(N78) );
AOI21X1TS U6232 ( .A0(n7486), .A1(n7159), .B0(n7158), .Y(n7163) );
NAND2X1TS U6233 ( .A(n7161), .B(n7160), .Y(n7162) );
XOR2XLTS U6234 ( .A(n7163), .B(n7162), .Y(N106) );
OAI21X1TS U6235 ( .A0(n7483), .A1(n7168), .B0(n7487), .Y(n7169) );
AOI21X1TS U6236 ( .A0(n33), .A1(n7170), .B0(n7169), .Y(n7174) );
NAND2X1TS U6237 ( .A(n7172), .B(n7171), .Y(n7173) );
XOR2XLTS U6238 ( .A(n7174), .B(n7173), .Y(N96) );
CLKINVX1TS U6239 ( .A(n7343), .Y(n7376) );
NAND2X1TS U6240 ( .A(n7181), .B(n7376), .Y(n7183) );
AOI21X1TS U6241 ( .A0(n7181), .A1(n7379), .B0(n7180), .Y(n7182) );
OAI21X1TS U6242 ( .A0(n7183), .A1(n7636), .B0(n7182), .Y(n7188) );
CLKINVX1TS U6243 ( .A(n7184), .Y(n7186) );
NAND2X1TS U6244 ( .A(n7186), .B(n7185), .Y(n7187) );
XNOR2X1TS U6245 ( .A(n7188), .B(n7187), .Y(N54) );
INVX2TS U6246 ( .A(n7189), .Y(n7687) );
CLKINVX1TS U6247 ( .A(n7190), .Y(n7204) );
AOI21X1TS U6248 ( .A0(n7200), .A1(n7204), .B0(n7191), .Y(n7192) );
NAND2X1TS U6249 ( .A(n7196), .B(n7195), .Y(n7197) );
XNOR2X1TS U6250 ( .A(n7198), .B(n7197), .Y(N37) );
CLKINVX1TS U6251 ( .A(n7200), .Y(n7201) );
NAND2X1TS U6252 ( .A(n7204), .B(n7203), .Y(n7205) );
XNOR2X1TS U6253 ( .A(n7206), .B(n7205), .Y(N36) );
INVX2TS U6254 ( .A(n7207), .Y(n7715) );
NAND2X1TS U6255 ( .A(n7714), .B(n7208), .Y(n7209) );
XNOR2X1TS U6256 ( .A(n7715), .B(n7209), .Y(N29) );
INVX2TS U6257 ( .A(n7210), .Y(n7722) );
NAND2X1TS U6258 ( .A(n7211), .B(n7223), .Y(n7215) );
AOI21X1TS U6259 ( .A0(n7213), .A1(n7223), .B0(n7212), .Y(n7214) );
NAND2X1TS U6260 ( .A(n7217), .B(n7216), .Y(n7218) );
XNOR2X1TS U6261 ( .A(n7219), .B(n7218), .Y(N28) );
NAND2X1TS U6262 ( .A(n7223), .B(n7222), .Y(n7224) );
XNOR2X1TS U6263 ( .A(n7225), .B(n7224), .Y(N27) );
NAND2X1TS U6264 ( .A(n19), .B(n7227), .Y(n7228) );
XNOR2X1TS U6265 ( .A(n7229), .B(n7228), .Y(N26) );
INVX2TS U6266 ( .A(n7230), .Y(n7742) );
NAND2X1TS U6267 ( .A(n7734), .B(n7732), .Y(n7232) );
XNOR2X1TS U6268 ( .A(n7742), .B(n7232), .Y(N21) );
INVX2TS U6269 ( .A(n7233), .Y(n7751) );
CLKINVX1TS U6270 ( .A(n7243), .Y(n7234) );
NAND2X1TS U6271 ( .A(n7234), .B(n7245), .Y(n7238) );
AOI21X1TS U6272 ( .A0(n7236), .A1(n7245), .B0(n7235), .Y(n7237) );
NAND2X1TS U6273 ( .A(n21), .B(n7239), .Y(n7240) );
XNOR2X1TS U6274 ( .A(n7241), .B(n7240), .Y(N20) );
NAND2X1TS U6275 ( .A(n7245), .B(n7244), .Y(n7246) );
XNOR2X1TS U6276 ( .A(n7247), .B(n7246), .Y(N19) );
NAND2X1TS U6277 ( .A(n7250), .B(n7249), .Y(n7251) );
XNOR2X1TS U6278 ( .A(n7252), .B(n7251), .Y(N18) );
NAND2X1TS U6279 ( .A(n7760), .B(n7758), .Y(n7255) );
XNOR2X1TS U6280 ( .A(n7761), .B(n7255), .Y(N14) );
CLKINVX1TS U6281 ( .A(n7257), .Y(n7259) );
NAND2X1TS U6282 ( .A(n7259), .B(n7258), .Y(n7260) );
XNOR2X1TS U6283 ( .A(n7261), .B(n7260), .Y(N13) );
NAND2X1TS U6284 ( .A(n7773), .B(n7263), .Y(n7264) );
XNOR2X1TS U6285 ( .A(n7774), .B(n7264), .Y(N10) );
NAND2X1TS U6286 ( .A(n7268), .B(n7267), .Y(n7269) );
XNOR2X1TS U6287 ( .A(n7270), .B(n7269), .Y(N9) );
NAND2X1TS U6288 ( .A(n22), .B(n7271), .Y(n7273) );
XNOR2X1TS U6289 ( .A(n7273), .B(n7784), .Y(N6) );
NAND2X1TS U6290 ( .A(n23), .B(n7274), .Y(n7276) );
XNOR2X1TS U6291 ( .A(n7276), .B(n7275), .Y(N5) );
NAND2X1TS U6292 ( .A(n7278), .B(n7277), .Y(n7279) );
XNOR2X1TS U6293 ( .A(n7279), .B(n151), .Y(N3) );
NAND2X1TS U6294 ( .A(n152), .B(n7280), .Y(n7282) );
XNOR2X1TS U6295 ( .A(n7282), .B(n7281), .Y(N2) );
NOR2X1TS U6296 ( .A(n7482), .B(n7284), .Y(n7286) );
OAI21X2TS U6297 ( .A0(n7483), .A1(n7284), .B0(n7283), .Y(n7285) );
AOI21X1TS U6298 ( .A0(n7486), .A1(n7286), .B0(n7285), .Y(n7291) );
XNOR2X1TS U6299 ( .A(n7291), .B(n7290), .Y(N97) );
AOI21X1TS U6300 ( .A0(n7486), .A1(n7297), .B0(n7296), .Y(n7302) );
XNOR2X1TS U6301 ( .A(n7302), .B(n7301), .Y(N79) );
AOI21X1TS U6302 ( .A0(n7486), .A1(n7405), .B0(n7408), .Y(n7307) );
XNOR2X1TS U6303 ( .A(n7307), .B(n7306), .Y(N82) );
AOI21X1TS U6304 ( .A0(n7486), .A1(n7308), .B0(n7004), .Y(n7312) );
XNOR2X1TS U6305 ( .A(n7312), .B(n7311), .Y(N98) );
INVX2TS U6306 ( .A(n7313), .Y(n7315) );
NAND2X1TS U6307 ( .A(n7315), .B(n7314), .Y(n7316) );
XNOR2X1TS U6308 ( .A(n7317), .B(n7316), .Y(N35) );
OAI21X1TS U6309 ( .A0(n7636), .A1(n7632), .B0(n7633), .Y(n7322) );
CLKINVX1TS U6310 ( .A(n7318), .Y(n7320) );
NAND2X1TS U6311 ( .A(n7320), .B(n7319), .Y(n7321) );
XNOR2X1TS U6312 ( .A(n7322), .B(n7321), .Y(N48) );
AOI21X1TS U6313 ( .A0(n7379), .A1(n7345), .B0(n7324), .Y(n7325) );
NAND2X1TS U6314 ( .A(n7329), .B(n7328), .Y(n7330) );
XNOR2X1TS U6315 ( .A(n7331), .B(n7330), .Y(N52) );
CLKINVX1TS U6316 ( .A(n7332), .Y(n7355) );
NAND2X1TS U6317 ( .A(n7350), .B(n7355), .Y(n7335) );
AOI21X1TS U6318 ( .A0(n7355), .A1(n7351), .B0(n7333), .Y(n7334) );
OAI21X1TS U6319 ( .A0(n7636), .A1(n7335), .B0(n7334), .Y(n7341) );
OR2X1TS U6320 ( .A(n7337), .B(n7336), .Y(n7338) );
NAND2X1TS U6321 ( .A(n7339), .B(n7338), .Y(n7340) );
XNOR2X1TS U6322 ( .A(n7341), .B(n7340), .Y(N50) );
OAI21X1TS U6323 ( .A0(n7636), .A1(n7343), .B0(n7342), .Y(n7347) );
NAND2X1TS U6324 ( .A(n7345), .B(n7344), .Y(n7346) );
XNOR2X1TS U6325 ( .A(n7347), .B(n7346), .Y(N51) );
NAND2X1TS U6326 ( .A(n7461), .B(n7459), .Y(n7349) );
XNOR2X1TS U6327 ( .A(n7349), .B(n34), .Y(N71) );
CLKINVX1TS U6328 ( .A(n7350), .Y(n7353) );
CLKINVX1TS U6329 ( .A(n7351), .Y(n7352) );
OAI21X1TS U6330 ( .A0(n7636), .A1(n7353), .B0(n7352), .Y(n7357) );
NAND2X1TS U6331 ( .A(n7355), .B(n7354), .Y(n7356) );
XNOR2X1TS U6332 ( .A(n7357), .B(n7356), .Y(N49) );
INVX2TS U6333 ( .A(n7358), .Y(n7678) );
NAND2X1TS U6334 ( .A(n7669), .B(n7359), .Y(n7360) );
XNOR2X1TS U6335 ( .A(n7678), .B(n7360), .Y(N40) );
NAND2X1TS U6336 ( .A(n7368), .B(n7362), .Y(n7363) );
XNOR2X1TS U6337 ( .A(n7364), .B(n7363), .Y(N38) );
NAND2X1TS U6338 ( .A(n7366), .B(n7368), .Y(n7371) );
CLKINVX1TS U6339 ( .A(n7361), .Y(n7369) );
AOI21X1TS U6340 ( .A0(n7369), .A1(n7368), .B0(n7367), .Y(n7370) );
NAND2X1TS U6341 ( .A(n7373), .B(n7372), .Y(n7374) );
XNOR2X1TS U6342 ( .A(n7375), .B(n7374), .Y(N39) );
NAND2X1TS U6343 ( .A(n7376), .B(n7378), .Y(n7381) );
AOI21X1TS U6344 ( .A0(n7379), .A1(n7378), .B0(n7377), .Y(n7380) );
OAI21X1TS U6345 ( .A0(n7636), .A1(n7381), .B0(n7380), .Y(n7386) );
NAND2X1TS U6346 ( .A(n7384), .B(n7383), .Y(n7385) );
XNOR2X1TS U6347 ( .A(n7386), .B(n7385), .Y(N53) );
BUFX3TS U6348 ( .A(n7387), .Y(n7388) );
INVX2TS U6349 ( .A(n7390), .Y(n7608) );
NAND2X1TS U6350 ( .A(n7609), .B(n7390), .Y(n7391) );
XNOR2X1TS U6351 ( .A(n107), .B(n7391), .Y(N55) );
CLKINVX1TS U6352 ( .A(n7392), .Y(n7394) );
CLKINVX1TS U6353 ( .A(n7030), .Y(n7397) );
AOI21X1TS U6354 ( .A0(n7399), .A1(n32), .B0(n7398), .Y(n7404) );
NAND2X1TS U6355 ( .A(n7402), .B(n7401), .Y(n7403) );
NAND2X1TS U6356 ( .A(n7405), .B(n7407), .Y(n7414) );
CLKINVX1TS U6357 ( .A(n7417), .Y(n7409) );
AOI21X1TS U6358 ( .A0(n7410), .A1(n32), .B0(n7409), .Y(n7413) );
NAND2X1TS U6359 ( .A(n7411), .B(n7415), .Y(n7412) );
NOR2X1TS U6360 ( .A(n7414), .B(n7416), .Y(n7419) );
AOI21X1TS U6361 ( .A0(n7419), .A1(n32), .B0(n7418), .Y(n7424) );
NAND2X1TS U6362 ( .A(n7422), .B(n7421), .Y(n7423) );
AOI21X1TS U6363 ( .A0(n7428), .A1(n32), .B0(n7430), .Y(n7427) );
NAND2X1TS U6364 ( .A(n7425), .B(n7431), .Y(n7426) );
OAI21X1TS U6365 ( .A0(n7433), .A1(n7432), .B0(n7431), .Y(n7434) );
AOI21X1TS U6366 ( .A0(n7435), .A1(n32), .B0(n7434), .Y(n7438) );
NAND2X1TS U6367 ( .A(n1), .B(n7436), .Y(n7437) );
AOI21X1TS U6368 ( .A0(n7442), .A1(n33), .B0(n7441), .Y(n7446) );
NAND2X1TS U6369 ( .A(n7444), .B(n7443), .Y(n7445) );
OAI21X1TS U6370 ( .A0(n7452), .A1(n7451), .B0(n7450), .Y(n7453) );
AOI21X1TS U6371 ( .A0(n7454), .A1(n32), .B0(n7453), .Y(n7458) );
NAND2X1TS U6372 ( .A(n7456), .B(n7455), .Y(n7457) );
AOI21X1TS U6373 ( .A0(n7461), .A1(n32), .B0(n7460), .Y(n7465) );
NAND2X1TS U6374 ( .A(n7463), .B(n7462), .Y(n7464) );
AOI21X1TS U6375 ( .A0(n7469), .A1(n32), .B0(n7468), .Y(n7474) );
NAND2X1TS U6376 ( .A(n7472), .B(n7471), .Y(n7473) );
CLKINVX1TS U6377 ( .A(n7483), .Y(n7484) );
AOI21X1TS U6378 ( .A0(n7485), .A1(n33), .B0(n7484), .Y(n7490) );
NAND2X1TS U6379 ( .A(n7488), .B(n7487), .Y(n7489) );
INVX2TS U6380 ( .A(n7586), .Y(n7558) );
CLKINVX1TS U6381 ( .A(n7551), .Y(n7513) );
NAND2X1TS U6382 ( .A(n7513), .B(n7511), .Y(n7494) );
NOR2X1TS U6383 ( .A(n7558), .B(n7494), .Y(n7496) );
CLKINVX1TS U6384 ( .A(n7550), .Y(n7519) );
AOI21X1TS U6385 ( .A0(n7519), .A1(n7511), .B0(n15), .Y(n7493) );
OAI21X1TS U6386 ( .A0(n7559), .A1(n7494), .B0(n7493), .Y(n7495) );
AOI21X1TS U6387 ( .A0(n7496), .A1(n7626), .B0(n7495), .Y(n7499) );
NAND2X1TS U6388 ( .A(n7514), .B(n7497), .Y(n7498) );
CLKINVX1TS U6389 ( .A(n7500), .Y(n7555) );
NAND2X1TS U6390 ( .A(n7513), .B(n7555), .Y(n7503) );
AOI21X1TS U6391 ( .A0(n7519), .A1(n7555), .B0(n7501), .Y(n7502) );
OAI21X1TS U6392 ( .A0(n7559), .A1(n7503), .B0(n7502), .Y(n7504) );
AOI21X1TS U6393 ( .A0(n7505), .A1(n107), .B0(n7504), .Y(n7510) );
NAND2X1TS U6394 ( .A(n7508), .B(n7507), .Y(n7509) );
NAND2X1TS U6395 ( .A(n7513), .B(n7518), .Y(n7521) );
OAI21XLTS U6396 ( .A0(n7516), .A1(n7515), .B0(n7514), .Y(n7517) );
AOI21X1TS U6397 ( .A0(n7519), .A1(n7518), .B0(n7517), .Y(n7520) );
OAI21X1TS U6398 ( .A0(n7559), .A1(n7521), .B0(n7520), .Y(n7522) );
AOI21X1TS U6399 ( .A0(n7523), .A1(n7626), .B0(n7522), .Y(n7528) );
CLKINVX1TS U6400 ( .A(n7524), .Y(n7526) );
NAND2X1TS U6401 ( .A(n7526), .B(n7525), .Y(n7527) );
XOR2X1TS U6402 ( .A(n7528), .B(n7527), .Y(N70) );
OAI21X1TS U6403 ( .A0(n7559), .A1(n7530), .B0(n7529), .Y(n7531) );
AOI21X1TS U6404 ( .A0(n7532), .A1(n107), .B0(n7531), .Y(n7536) );
NAND2X1TS U6405 ( .A(n7540), .B(n7534), .Y(n7535) );
NAND2X1TS U6406 ( .A(n7537), .B(n7540), .Y(n7542) );
NOR2X1TS U6407 ( .A(n7558), .B(n7542), .Y(n7544) );
AOI21X1TS U6408 ( .A0(n7540), .A1(n31), .B0(n7538), .Y(n7541) );
OAI21X1TS U6409 ( .A0(n7559), .A1(n7542), .B0(n7541), .Y(n7543) );
AOI21X1TS U6410 ( .A0(n7544), .A1(n7626), .B0(n7543), .Y(n7549) );
CLKINVX1TS U6411 ( .A(n7545), .Y(n7547) );
NAND2X1TS U6412 ( .A(n7547), .B(n7546), .Y(n7548) );
AOI21X1TS U6413 ( .A0(n7553), .A1(n107), .B0(n7552), .Y(n7557) );
NAND2X1TS U6414 ( .A(n7555), .B(n7554), .Y(n7556) );
NOR2X1TS U6415 ( .A(n7558), .B(n7587), .Y(n7561) );
OAI21X1TS U6416 ( .A0(n7559), .A1(n7587), .B0(n7589), .Y(n7560) );
AOI21X1TS U6417 ( .A0(n7561), .A1(n7626), .B0(n7560), .Y(n7566) );
NAND2X1TS U6418 ( .A(n7564), .B(n7563), .Y(n7565) );
NOR2XLTS U6419 ( .A(n7574), .B(n7594), .Y(n7568) );
OAI21XLTS U6420 ( .A0(n7594), .A1(n7575), .B0(n7595), .Y(n7567) );
AOI21X1TS U6421 ( .A0(n107), .A1(n7568), .B0(n7567), .Y(n7573) );
NAND2X1TS U6422 ( .A(n7571), .B(n7570), .Y(n7572) );
NAND2X1TS U6423 ( .A(n7593), .B(n7577), .Y(n7622) );
CLKINVX1TS U6424 ( .A(n7575), .Y(n7592) );
AOI21X1TS U6425 ( .A0(n7592), .A1(n7577), .B0(n7576), .Y(n7623) );
AOI21X1TS U6426 ( .A0(n7626), .A1(n7579), .B0(n7578), .Y(n7584) );
NAND2X1TS U6427 ( .A(n7582), .B(n7581), .Y(n7583) );
AOI21X1TS U6428 ( .A0(n7626), .A1(n7586), .B0(n7585), .Y(n7591) );
NAND2X1TS U6429 ( .A(n7589), .B(n7588), .Y(n7590) );
AOI21X1TS U6430 ( .A0(n7626), .A1(n7593), .B0(n7592), .Y(n7598) );
CLKINVX1TS U6431 ( .A(n7594), .Y(n7596) );
NAND2X1TS U6432 ( .A(n7596), .B(n7595), .Y(n7597) );
XOR2X1TS U6433 ( .A(n7598), .B(n7597), .Y(N59) );
CLKINVX1TS U6434 ( .A(n7615), .Y(n7600) );
AOI21X1TS U6435 ( .A0(n7626), .A1(n7602), .B0(n7601), .Y(n7607) );
NAND2X1TS U6436 ( .A(n7605), .B(n7604), .Y(n7606) );
AOI21X1TS U6437 ( .A0(n107), .A1(n7609), .B0(n7608), .Y(n7614) );
CLKINVX1TS U6438 ( .A(n7610), .Y(n7612) );
NAND2X1TS U6439 ( .A(n7612), .B(n7611), .Y(n7613) );
XOR2X1TS U6440 ( .A(n7614), .B(n7613), .Y(N56) );
AOI21X1TS U6441 ( .A0(n107), .A1(n7616), .B0(n7615), .Y(n7621) );
CLKINVX1TS U6442 ( .A(n7617), .Y(n7619) );
NAND2X1TS U6443 ( .A(n7619), .B(n7618), .Y(n7620) );
AOI21X1TS U6444 ( .A0(n107), .A1(n7625), .B0(n7624), .Y(n7631) );
NAND2X1TS U6445 ( .A(n7629), .B(n7628), .Y(n7630) );
NAND2X1TS U6446 ( .A(n7634), .B(n7633), .Y(n7635) );
AOI21X1TS U6447 ( .A0(n7678), .A1(n7640), .B0(n7641), .Y(n7639) );
NAND2X1TS U6448 ( .A(n7637), .B(n7652), .Y(n7638) );
OAI21XLTS U6449 ( .A0(n7654), .A1(n7643), .B0(n7642), .Y(n7644) );
AOI21X1TS U6450 ( .A0(n7678), .A1(n7645), .B0(n7644), .Y(n7650) );
NAND2X1TS U6451 ( .A(n7648), .B(n7647), .Y(n7649) );
NOR2XLTS U6452 ( .A(n7651), .B(n7653), .Y(n7656) );
AOI21X1TS U6453 ( .A0(n7678), .A1(n7656), .B0(n7655), .Y(n7660) );
NAND2X1TS U6454 ( .A(n7658), .B(n7657), .Y(n7659) );
NOR2XLTS U6455 ( .A(n7674), .B(n7661), .Y(n7663) );
OAI21XLTS U6456 ( .A0(n7661), .A1(n7675), .B0(n7679), .Y(n7662) );
AOI21X1TS U6457 ( .A0(n7678), .A1(n7663), .B0(n7662), .Y(n7667) );
NAND2X1TS U6458 ( .A(n7665), .B(n7664), .Y(n7666) );
AOI21X1TS U6459 ( .A0(n7678), .A1(n7669), .B0(n7668), .Y(n7673) );
NAND2X1TS U6460 ( .A(n7671), .B(n7670), .Y(n7672) );
CLKINVX1TS U6461 ( .A(n7675), .Y(n7676) );
AOI21X1TS U6462 ( .A0(n7678), .A1(n7677), .B0(n7676), .Y(n7682) );
NAND2X1TS U6463 ( .A(n7680), .B(n7679), .Y(n7681) );
NAND2X1TS U6464 ( .A(n7685), .B(n7684), .Y(n7686) );
CLKINVX1TS U6465 ( .A(n7707), .Y(n7688) );
AOI21X1TS U6466 ( .A0(n7692), .A1(n7715), .B0(n7691), .Y(n7697) );
NAND2X1TS U6467 ( .A(n7695), .B(n7694), .Y(n7696) );
CLKINVX1TS U6468 ( .A(n7699), .Y(n7700) );
AOI21X1TS U6469 ( .A0(n7715), .A1(n7701), .B0(n7700), .Y(n7706) );
NAND2X1TS U6470 ( .A(n7704), .B(n7703), .Y(n7705) );
AOI21X1TS U6471 ( .A0(n7715), .A1(n7707), .B0(n7689), .Y(n7712) );
NAND2X1TS U6472 ( .A(n7710), .B(n7709), .Y(n7711) );
AOI21X1TS U6473 ( .A0(n7715), .A1(n7714), .B0(n7713), .Y(n7718) );
NAND2X1TS U6474 ( .A(n2), .B(n7716), .Y(n7717) );
NAND2X1TS U6475 ( .A(n7720), .B(n7719), .Y(n7721) );
CLKINVX1TS U6476 ( .A(n7741), .Y(n7723) );
CLKINVX1TS U6477 ( .A(n7740), .Y(n7724) );
AOI21X1TS U6478 ( .A0(n7726), .A1(n7742), .B0(n7725), .Y(n7731) );
NAND2X1TS U6479 ( .A(n7729), .B(n7728), .Y(n7730) );
AOI21X1TS U6480 ( .A0(n7742), .A1(n7734), .B0(n7733), .Y(n7739) );
NAND2X1TS U6481 ( .A(n7737), .B(n7736), .Y(n7738) );
AOI21X1TS U6482 ( .A0(n7742), .A1(n7741), .B0(n7740), .Y(n7747) );
NAND2X1TS U6483 ( .A(n7745), .B(n7744), .Y(n7746) );
NAND2X1TS U6484 ( .A(n7749), .B(n7748), .Y(n7750) );
AOI21X1TS U6485 ( .A0(n7761), .A1(n7753), .B0(n7752), .Y(n7757) );
NAND2X1TS U6486 ( .A(n7755), .B(n7754), .Y(n7756) );
AOI21X1TS U6487 ( .A0(n7761), .A1(n7760), .B0(n7759), .Y(n7766) );
NAND2X1TS U6488 ( .A(n7764), .B(n7763), .Y(n7765) );
NAND2X1TS U6489 ( .A(n7769), .B(n7768), .Y(n7770) );
AOI21X1TS U6490 ( .A0(n7774), .A1(n7773), .B0(n7772), .Y(n7777) );
NAND2X1TS U6491 ( .A(n20), .B(n7775), .Y(n7776) );
NAND2X1TS U6492 ( .A(n7780), .B(n7779), .Y(n7781) );
AOI21X1TS U6493 ( .A0(n7784), .A1(n22), .B0(n7783), .Y(n7787) );
NAND2X1TS U6494 ( .A(n3), .B(n7785), .Y(n7786) );
NAND2X1TS U6495 ( .A(n7790), .B(n7789), .Y(n7792) );
initial $sdf_annotate("mult_syn.sdf");
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_dadd_64ns_64ns_64_5_full_dsp
#(parameter
ID = 5,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
HLS_accel_ap_dadd_3_full_dsp_64 HLS_accel_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:34:23 02/26/2016
// Design Name: Alu
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab3/test_for_Alu.v
// Project Name: lab3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_Alu;
// Inputs
reg [31:0] input1;
reg [31:0] input2;
reg [3:0] aluCtr;
// Outputs
wire zero;
wire [31:0] aluRes;
// Instantiate the Unit Under Test (UUT)
Alu uut (
.input1(input1),
.input2(input2),
.aluCtr(aluCtr),
.zero(zero),
.aluRes(aluRes)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
aluCtr = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
#100
begin
input1 = 255;
input2 = 170;
aluCtr = 'b0000;
end
#100
begin
input1 = 255;
input2 = 170;
aluCtr = 'b0001;
end
#100
begin
input1 = 1;
input2 = 1;
aluCtr = 'b0010;
end
#100
begin
input1 = 255;
input2 = 170;
aluCtr = 'b0110;
end
#100
begin
input1 = 1;
input2 = 1;
aluCtr = 'b0110;
end
#100
begin
input1 = 255;
input2 = 170;
aluCtr = 'b0111;
end
#100
begin
input1 = 170;
input2 = 255;
aluCtr = 'b0111;
end
#100
begin
input1 = 0;
input2 = 1;
aluCtr = 'b1100;
end
end
endmodule
|
module HastiBus(input clk, input reset,
input [31:0] io_master_haddr,
input io_master_hwrite,
input [2:0] io_master_hsize,
input [2:0] io_master_hburst,
input [3:0] io_master_hprot,
input [1:0] io_master_htrans,
input io_master_hmastlock,
input [31:0] io_master_hwdata,
output[31:0] io_master_hrdata,
output io_master_hready,
output io_master_hresp,
output[31:0] io_slaves_1_haddr,
output io_slaves_1_hwrite,
output[2:0] io_slaves_1_hsize,
output[2:0] io_slaves_1_hburst,
output[3:0] io_slaves_1_hprot,
output[1:0] io_slaves_1_htrans,
output io_slaves_1_hmastlock,
output[31:0] io_slaves_1_hwdata,
input [31:0] io_slaves_1_hrdata,
output io_slaves_1_hsel,
output io_slaves_1_hreadyin,
input io_slaves_1_hreadyout,
input io_slaves_1_hresp,
output[31:0] io_slaves_0_haddr,
output io_slaves_0_hwrite,
output[2:0] io_slaves_0_hsize,
output[2:0] io_slaves_0_hburst,
output[3:0] io_slaves_0_hprot,
output[1:0] io_slaves_0_htrans,
output io_slaves_0_hmastlock,
output[31:0] io_slaves_0_hwdata,
input [31:0] io_slaves_0_hrdata,
output io_slaves_0_hsel,
output io_slaves_0_hreadyin,
input io_slaves_0_hreadyout,
input io_slaves_0_hresp
);
wire T0;
reg skb_valid;
wire T47;
wire T1;
wire T2;
wire T3;
wire T4;
wire T5;
wire T6;
wire[1:0] T7;
wire[1:0] T8;
wire T9;
wire T10;
wire[1:0] master_htrans;
reg [1:0] skb_htrans;
wire[1:0] T11;
wire T12;
wire T13;
wire[3:0] T14;
wire[31:0] master_haddr;
reg [31:0] skb_haddr;
wire[31:0] T15;
wire T16;
wire T17;
wire T18;
wire[3:0] T19;
wire T20;
wire T21;
wire T22;
wire T23;
reg R24;
wire T48;
wire T25;
reg R26;
wire T49;
wire T27;
wire master_hready;
wire T28;
wire T29;
wire T30;
wire T31;
wire T32;
wire[31:0] master_hwdata;
reg [31:0] skb_hwdata;
wire master_hmastlock;
reg skb_hmastlock;
wire T33;
wire[3:0] master_hprot;
reg [3:0] skb_hprot;
wire[3:0] T34;
wire[2:0] master_hburst;
reg [2:0] skb_hburst;
wire[2:0] T35;
wire[2:0] master_hsize;
reg [2:0] skb_hsize;
wire[2:0] T36;
wire master_hwrite;
reg skb_hwrite;
wire T37;
wire T38;
wire T39;
wire T40;
wire T41;
wire T42;
wire T43;
wire[31:0] T44;
wire[31:0] T45;
wire[31:0] T46;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
skb_valid = {1{$random}};
skb_htrans = {1{$random}};
skb_haddr = {1{$random}};
R24 = {1{$random}};
R26 = {1{$random}};
skb_hwdata = {1{$random}};
skb_hmastlock = {1{$random}};
skb_hprot = {1{$random}};
skb_hburst = {1{$random}};
skb_hsize = {1{$random}};
skb_hwrite = {1{$random}};
end
// synthesis translate_on
`endif
assign io_slaves_0_hreadyin = T0;
assign T0 = skb_valid | io_master_hready;
assign T47 = reset ? 1'h0 : T1;
assign T1 = master_hready ? T2 : skb_valid;
assign T2 = T23 & T3;
assign T3 = T20 | T4;
assign T4 = T6 & T5;
assign T5 = io_slaves_1_hreadyout ^ 1'h1;
assign T6 = T7[1];
assign T7 = T16 ? 2'h1 : T8;
assign T8 = T9 ? 2'h2 : 2'h0;
assign T9 = T13 & T10;
assign T10 = master_htrans != 2'h0;
assign master_htrans = skb_valid ? skb_htrans : io_master_htrans;
assign T11 = T12 ? io_master_htrans : skb_htrans;
assign T12 = master_hready & T2;
assign T13 = T14 == 4'h0;
assign T14 = master_haddr[31:28];
assign master_haddr = skb_valid ? skb_haddr : io_master_haddr;
assign T15 = T12 ? io_master_haddr : skb_haddr;
assign T16 = T18 & T17;
assign T17 = master_htrans != 2'h0;
assign T18 = T19 == 4'h2;
assign T19 = master_haddr[31:28];
assign T20 = T22 & T21;
assign T21 = io_slaves_0_hreadyout ^ 1'h1;
assign T22 = T7[0];
assign T23 = R26 | R24;
assign T48 = reset ? 1'h0 : T25;
assign T25 = master_hready ? T6 : R24;
assign T49 = reset ? 1'h0 : T27;
assign T27 = master_hready ? T22 : R26;
assign master_hready = T31 | T28;
assign T28 = T30 | T29;
assign T29 = R24 ? io_slaves_1_hreadyout : 1'h0;
assign T30 = R26 ? io_slaves_0_hreadyout : 1'h0;
assign T31 = T32 == 1'h0;
assign T32 = R26 | R24;
assign io_slaves_0_hsel = T22;
assign io_slaves_0_hwdata = master_hwdata;
assign master_hwdata = skb_valid ? skb_hwdata : io_master_hwdata;
assign io_slaves_0_hmastlock = master_hmastlock;
assign master_hmastlock = skb_valid ? skb_hmastlock : io_master_hmastlock;
assign T33 = T12 ? io_master_hmastlock : skb_hmastlock;
assign io_slaves_0_htrans = master_htrans;
assign io_slaves_0_hprot = master_hprot;
assign master_hprot = skb_valid ? skb_hprot : io_master_hprot;
assign T34 = T12 ? io_master_hprot : skb_hprot;
assign io_slaves_0_hburst = master_hburst;
assign master_hburst = skb_valid ? skb_hburst : io_master_hburst;
assign T35 = T12 ? io_master_hburst : skb_hburst;
assign io_slaves_0_hsize = master_hsize;
assign master_hsize = skb_valid ? skb_hsize : io_master_hsize;
assign T36 = T12 ? io_master_hsize : skb_hsize;
assign io_slaves_0_hwrite = master_hwrite;
assign master_hwrite = skb_valid ? skb_hwrite : io_master_hwrite;
assign T37 = T12 ? io_master_hwrite : skb_hwrite;
assign io_slaves_0_haddr = master_haddr;
assign io_slaves_1_hreadyin = T38;
assign T38 = skb_valid | io_master_hready;
assign io_slaves_1_hsel = T6;
assign io_slaves_1_hwdata = master_hwdata;
assign io_slaves_1_hmastlock = master_hmastlock;
assign io_slaves_1_htrans = master_htrans;
assign io_slaves_1_hprot = master_hprot;
assign io_slaves_1_hburst = master_hburst;
assign io_slaves_1_hsize = master_hsize;
assign io_slaves_1_hwrite = master_hwrite;
assign io_slaves_1_haddr = master_haddr;
assign io_master_hresp = T39;
assign T39 = T41 | T40;
assign T40 = R24 ? io_slaves_1_hresp : 1'h0;
assign T41 = R26 ? io_slaves_0_hresp : 1'h0;
assign io_master_hready = T42;
assign T42 = T43 & master_hready;
assign T43 = skb_valid ^ 1'h1;
assign io_master_hrdata = T44;
assign T44 = T46 | T45;
assign T45 = R24 ? io_slaves_1_hrdata : 32'h0;
assign T46 = R26 ? io_slaves_0_hrdata : 32'h0;
always @(posedge clk) begin
if(reset) begin
skb_valid <= 1'h0;
end else if(master_hready) begin
skb_valid <= T2;
end
if(T12) begin
skb_htrans <= io_master_htrans;
end
if(T12) begin
skb_haddr <= io_master_haddr;
end
if(reset) begin
R24 <= 1'h0;
end else if(master_hready) begin
R24 <= T6;
end
if(reset) begin
R26 <= 1'h0;
end else if(master_hready) begin
R26 <= T22;
end
skb_hwdata <= skb_hwdata;
if(T12) begin
skb_hmastlock <= io_master_hmastlock;
end
if(T12) begin
skb_hprot <= io_master_hprot;
end
if(T12) begin
skb_hburst <= io_master_hburst;
end
if(T12) begin
skb_hsize <= io_master_hsize;
end
if(T12) begin
skb_hwrite <= io_master_hwrite;
end
end
endmodule
module HastiSlaveMux(input clk, input reset,
input [31:0] io_ins_2_haddr,
input io_ins_2_hwrite,
input [2:0] io_ins_2_hsize,
input [2:0] io_ins_2_hburst,
input [3:0] io_ins_2_hprot,
input [1:0] io_ins_2_htrans,
input io_ins_2_hmastlock,
input [31:0] io_ins_2_hwdata,
output[31:0] io_ins_2_hrdata,
input io_ins_2_hsel,
input io_ins_2_hreadyin,
output io_ins_2_hreadyout,
output io_ins_2_hresp,
input [31:0] io_ins_1_haddr,
input io_ins_1_hwrite,
input [2:0] io_ins_1_hsize,
input [2:0] io_ins_1_hburst,
input [3:0] io_ins_1_hprot,
input [1:0] io_ins_1_htrans,
input io_ins_1_hmastlock,
input [31:0] io_ins_1_hwdata,
output[31:0] io_ins_1_hrdata,
input io_ins_1_hsel,
input io_ins_1_hreadyin,
output io_ins_1_hreadyout,
output io_ins_1_hresp,
input [31:0] io_ins_0_haddr,
input io_ins_0_hwrite,
input [2:0] io_ins_0_hsize,
input [2:0] io_ins_0_hburst,
input [3:0] io_ins_0_hprot,
input [1:0] io_ins_0_htrans,
input io_ins_0_hmastlock,
input [31:0] io_ins_0_hwdata,
output[31:0] io_ins_0_hrdata,
input io_ins_0_hsel,
input io_ins_0_hreadyin,
output io_ins_0_hreadyout,
output io_ins_0_hresp,
output[31:0] io_out_haddr,
output io_out_hwrite,
output[2:0] io_out_hsize,
output[2:0] io_out_hburst,
output[3:0] io_out_hprot,
output[1:0] io_out_htrans,
output io_out_hmastlock,
output[31:0] io_out_hwdata,
input [31:0] io_out_hrdata,
output io_out_hsel,
output io_out_hreadyin,
input io_out_hreadyout,
input io_out_hresp
);
wire T0;
wire T1;
wire[2:0] T2;
wire[2:0] T3;
wire[2:0] T4;
wire requests_2;
reg R5;
wire T168;
wire T6;
wire T7;
wire T8;
wire T9;
wire T10;
wire T11;
wire T12;
wire T13;
wire T14;
wire requests_1;
reg R15;
wire T169;
wire T16;
wire T17;
wire T18;
wire T19;
wire T20;
wire T21;
wire T22;
wire T23;
wire T24;
wire T25;
wire requests_0;
reg R26;
wire T170;
wire T27;
wire T28;
wire T29;
wire T30;
wire T31;
wire T32;
wire T33;
wire T34;
wire T35;
wire T36;
wire T37;
wire[31:0] T38;
wire[31:0] T39;
reg R40;
wire T171;
wire T41;
wire[31:0] T42;
wire[31:0] T43;
reg R44;
wire T172;
wire T45;
wire[31:0] T46;
reg R47;
wire T173;
wire T48;
wire T49;
wire T50;
wire T51;
reg R52;
wire T53;
wire T54;
wire T55;
wire T56;
wire T57;
reg R58;
wire T59;
wire T60;
wire T61;
wire T62;
reg R63;
wire T64;
wire T65;
wire[1:0] T66;
wire[1:0] T67;
wire[1:0] T68;
reg [1:0] R69;
wire[1:0] T70;
wire[1:0] T71;
wire[1:0] T72;
wire[1:0] T73;
reg [1:0] R74;
wire[1:0] T75;
wire[1:0] T76;
wire[1:0] T77;
reg [1:0] R78;
wire[1:0] T79;
wire[3:0] T80;
wire[3:0] T81;
wire[3:0] T82;
reg [3:0] R83;
wire[3:0] T84;
wire[3:0] T85;
wire[3:0] T86;
wire[3:0] T87;
reg [3:0] R88;
wire[3:0] T89;
wire[3:0] T90;
wire[3:0] T91;
reg [3:0] R92;
wire[3:0] T93;
wire[2:0] T94;
wire[2:0] T95;
wire[2:0] T96;
reg [2:0] R97;
wire[2:0] T98;
wire[2:0] T99;
wire[2:0] T100;
wire[2:0] T101;
reg [2:0] R102;
wire[2:0] T103;
wire[2:0] T104;
wire[2:0] T105;
reg [2:0] R106;
wire[2:0] T107;
wire[2:0] T108;
wire[2:0] T109;
wire[2:0] T110;
reg [2:0] R111;
wire[2:0] T112;
wire[2:0] T113;
wire[2:0] T114;
wire[2:0] T115;
reg [2:0] R116;
wire[2:0] T117;
wire[2:0] T118;
wire[2:0] T119;
reg [2:0] R120;
wire[2:0] T121;
wire T122;
wire T123;
wire T124;
reg R125;
wire T126;
wire T127;
wire T128;
wire T129;
reg R130;
wire T131;
wire T132;
wire T133;
reg R134;
wire T135;
wire[31:0] T136;
wire[31:0] T137;
wire[31:0] T138;
reg [31:0] R139;
wire[31:0] T140;
wire[31:0] T141;
wire[31:0] T142;
wire[31:0] T143;
reg [31:0] R144;
wire[31:0] T145;
wire[31:0] T146;
wire[31:0] T147;
reg [31:0] R148;
wire[31:0] T149;
wire T150;
wire T151;
wire T152;
wire T153;
wire[31:0] T154;
wire[31:0] T155;
wire[31:0] T174;
wire T156;
wire T157;
wire T158;
wire T159;
wire[31:0] T160;
wire[31:0] T161;
wire[31:0] T175;
wire T162;
wire T163;
wire T164;
wire T165;
wire[31:0] T166;
wire[31:0] T167;
wire[31:0] T176;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R5 = {1{$random}};
R15 = {1{$random}};
R26 = {1{$random}};
R40 = {1{$random}};
R44 = {1{$random}};
R47 = {1{$random}};
R52 = {1{$random}};
R58 = {1{$random}};
R63 = {1{$random}};
R69 = {1{$random}};
R74 = {1{$random}};
R78 = {1{$random}};
R83 = {1{$random}};
R88 = {1{$random}};
R92 = {1{$random}};
R97 = {1{$random}};
R102 = {1{$random}};
R106 = {1{$random}};
R111 = {1{$random}};
R116 = {1{$random}};
R120 = {1{$random}};
R125 = {1{$random}};
R130 = {1{$random}};
R134 = {1{$random}};
R139 = {1{$random}};
R144 = {1{$random}};
R148 = {1{$random}};
end
// synthesis translate_on
`endif
assign io_out_hreadyin = io_out_hreadyout;
assign io_out_hsel = T0;
assign T0 = T37 | T1;
assign T1 = T2[2];
assign T2 = requests_0 ? 3'h1 : T3;
assign T3 = requests_1 ? 3'h2 : T4;
assign T4 = requests_2 ? 3'h4 : 3'h0;
assign requests_2 = T14 | R5;
assign T168 = reset ? 1'h0 : T6;
assign T6 = T10 ? T9 : T7;
assign T7 = T8 ? 1'h0 : R5;
assign T8 = io_out_hreadyout & T1;
assign T9 = io_ins_2_hsel & io_ins_2_hreadyin;
assign T10 = io_out_hreadyout & T11;
assign T11 = T13 & T12;
assign T12 = R5 ^ 1'h1;
assign T13 = T1 ^ 1'h1;
assign T14 = io_ins_2_hsel & io_ins_2_hreadyin;
assign requests_1 = T25 | R15;
assign T169 = reset ? 1'h0 : T16;
assign T16 = T21 ? T20 : T17;
assign T17 = T18 ? 1'h0 : R15;
assign T18 = io_out_hreadyout & T19;
assign T19 = T2[1];
assign T20 = io_ins_1_hsel & io_ins_1_hreadyin;
assign T21 = io_out_hreadyout & T22;
assign T22 = T24 & T23;
assign T23 = R15 ^ 1'h1;
assign T24 = T19 ^ 1'h1;
assign T25 = io_ins_1_hsel & io_ins_1_hreadyin;
assign requests_0 = T36 | R26;
assign T170 = reset ? 1'h0 : T27;
assign T27 = T32 ? T31 : T28;
assign T28 = T29 ? 1'h0 : R26;
assign T29 = io_out_hreadyout & T30;
assign T30 = T2[0];
assign T31 = io_ins_0_hsel & io_ins_0_hreadyin;
assign T32 = io_out_hreadyout & T33;
assign T33 = T35 & T34;
assign T34 = R26 ^ 1'h1;
assign T35 = T30 ^ 1'h1;
assign T36 = io_ins_0_hsel & io_ins_0_hreadyin;
assign T37 = T30 | T19;
assign io_out_hwdata = T38;
assign T38 = T42 | T39;
assign T39 = R40 ? io_ins_2_hwdata : 32'h0;
assign T171 = reset ? 1'h1 : T41;
assign T41 = io_out_hreadyout ? T1 : R40;
assign T42 = T46 | T43;
assign T43 = R44 ? io_ins_1_hwdata : 32'h0;
assign T172 = reset ? 1'h1 : T45;
assign T45 = io_out_hreadyout ? T19 : R44;
assign T46 = R47 ? io_ins_0_hwdata : 32'h0;
assign T173 = reset ? 1'h1 : T48;
assign T48 = io_out_hreadyout ? T30 : R47;
assign io_out_hmastlock = T49;
assign T49 = T55 | T50;
assign T50 = T1 ? T51 : 1'h0;
assign T51 = R5 ? R52 : io_ins_2_hmastlock;
assign T53 = T54 ? io_ins_2_hmastlock : R52;
assign T54 = T10 & T9;
assign T55 = T61 | T56;
assign T56 = T19 ? T57 : 1'h0;
assign T57 = R15 ? R58 : io_ins_1_hmastlock;
assign T59 = T60 ? io_ins_1_hmastlock : R58;
assign T60 = T21 & T20;
assign T61 = T30 ? T62 : 1'h0;
assign T62 = R26 ? R63 : io_ins_0_hmastlock;
assign T64 = T65 ? io_ins_0_hmastlock : R63;
assign T65 = T32 & T31;
assign io_out_htrans = T66;
assign T66 = T71 | T67;
assign T67 = T1 ? T68 : 2'h0;
assign T68 = R5 ? R69 : io_ins_2_htrans;
assign T70 = T54 ? io_ins_2_htrans : R69;
assign T71 = T76 | T72;
assign T72 = T19 ? T73 : 2'h0;
assign T73 = R15 ? R74 : io_ins_1_htrans;
assign T75 = T60 ? io_ins_1_htrans : R74;
assign T76 = T30 ? T77 : 2'h0;
assign T77 = R26 ? R78 : io_ins_0_htrans;
assign T79 = T65 ? io_ins_0_htrans : R78;
assign io_out_hprot = T80;
assign T80 = T85 | T81;
assign T81 = T1 ? T82 : 4'h0;
assign T82 = R5 ? R83 : io_ins_2_hprot;
assign T84 = T54 ? io_ins_2_hprot : R83;
assign T85 = T90 | T86;
assign T86 = T19 ? T87 : 4'h0;
assign T87 = R15 ? R88 : io_ins_1_hprot;
assign T89 = T60 ? io_ins_1_hprot : R88;
assign T90 = T30 ? T91 : 4'h0;
assign T91 = R26 ? R92 : io_ins_0_hprot;
assign T93 = T65 ? io_ins_0_hprot : R92;
assign io_out_hburst = T94;
assign T94 = T99 | T95;
assign T95 = T1 ? T96 : 3'h0;
assign T96 = R5 ? R97 : io_ins_2_hburst;
assign T98 = T54 ? io_ins_2_hburst : R97;
assign T99 = T104 | T100;
assign T100 = T19 ? T101 : 3'h0;
assign T101 = R15 ? R102 : io_ins_1_hburst;
assign T103 = T60 ? io_ins_1_hburst : R102;
assign T104 = T30 ? T105 : 3'h0;
assign T105 = R26 ? R106 : io_ins_0_hburst;
assign T107 = T65 ? io_ins_0_hburst : R106;
assign io_out_hsize = T108;
assign T108 = T113 | T109;
assign T109 = T1 ? T110 : 3'h0;
assign T110 = R5 ? R111 : io_ins_2_hsize;
assign T112 = T54 ? io_ins_2_hsize : R111;
assign T113 = T118 | T114;
assign T114 = T19 ? T115 : 3'h0;
assign T115 = R15 ? R116 : io_ins_1_hsize;
assign T117 = T60 ? io_ins_1_hsize : R116;
assign T118 = T30 ? T119 : 3'h0;
assign T119 = R26 ? R120 : io_ins_0_hsize;
assign T121 = T65 ? io_ins_0_hsize : R120;
assign io_out_hwrite = T122;
assign T122 = T127 | T123;
assign T123 = T1 ? T124 : 1'h0;
assign T124 = R5 ? R125 : io_ins_2_hwrite;
assign T126 = T54 ? io_ins_2_hwrite : R125;
assign T127 = T132 | T128;
assign T128 = T19 ? T129 : 1'h0;
assign T129 = R15 ? R130 : io_ins_1_hwrite;
assign T131 = T60 ? io_ins_1_hwrite : R130;
assign T132 = T30 ? T133 : 1'h0;
assign T133 = R26 ? R134 : io_ins_0_hwrite;
assign T135 = T65 ? io_ins_0_hwrite : R134;
assign io_out_haddr = T136;
assign T136 = T141 | T137;
assign T137 = T1 ? T138 : 32'h0;
assign T138 = R5 ? R139 : io_ins_2_haddr;
assign T140 = T54 ? io_ins_2_haddr : R139;
assign T141 = T146 | T142;
assign T142 = T19 ? T143 : 32'h0;
assign T143 = R15 ? R144 : io_ins_1_haddr;
assign T145 = T60 ? io_ins_1_haddr : R144;
assign T146 = T30 ? T147 : 32'h0;
assign T147 = R26 ? R148 : io_ins_0_haddr;
assign T149 = T65 ? io_ins_0_haddr : R148;
assign io_ins_0_hresp = T150;
assign T150 = R47 & io_out_hresp;
assign io_ins_0_hreadyout = T151;
assign T151 = io_out_hreadyout & T152;
assign T152 = T153 | R47;
assign T153 = R26 ^ 1'h1;
assign io_ins_0_hrdata = T154;
assign T154 = T155 & io_out_hrdata;
assign T155 = 32'h0 - T174;
assign T174 = {31'h0, R47};
assign io_ins_1_hresp = T156;
assign T156 = R44 & io_out_hresp;
assign io_ins_1_hreadyout = T157;
assign T157 = io_out_hreadyout & T158;
assign T158 = T159 | R44;
assign T159 = R15 ^ 1'h1;
assign io_ins_1_hrdata = T160;
assign T160 = T161 & io_out_hrdata;
assign T161 = 32'h0 - T175;
assign T175 = {31'h0, R44};
assign io_ins_2_hresp = T162;
assign T162 = R40 & io_out_hresp;
assign io_ins_2_hreadyout = T163;
assign T163 = io_out_hreadyout & T164;
assign T164 = T165 | R40;
assign T165 = R5 ^ 1'h1;
assign io_ins_2_hrdata = T166;
assign T166 = T167 & io_out_hrdata;
assign T167 = 32'h0 - T176;
assign T176 = {31'h0, R40};
always @(posedge clk) begin
if(reset) begin
R5 <= 1'h0;
end else if(T10) begin
R5 <= T9;
end else if(T8) begin
R5 <= 1'h0;
end
if(reset) begin
R15 <= 1'h0;
end else if(T21) begin
R15 <= T20;
end else if(T18) begin
R15 <= 1'h0;
end
if(reset) begin
R26 <= 1'h0;
end else if(T32) begin
R26 <= T31;
end else if(T29) begin
R26 <= 1'h0;
end
if(reset) begin
R40 <= 1'h1;
end else if(io_out_hreadyout) begin
R40 <= T1;
end
if(reset) begin
R44 <= 1'h1;
end else if(io_out_hreadyout) begin
R44 <= T19;
end
if(reset) begin
R47 <= 1'h1;
end else if(io_out_hreadyout) begin
R47 <= T30;
end
if(T54) begin
R52 <= io_ins_2_hmastlock;
end
if(T60) begin
R58 <= io_ins_1_hmastlock;
end
if(T65) begin
R63 <= io_ins_0_hmastlock;
end
if(T54) begin
R69 <= io_ins_2_htrans;
end
if(T60) begin
R74 <= io_ins_1_htrans;
end
if(T65) begin
R78 <= io_ins_0_htrans;
end
if(T54) begin
R83 <= io_ins_2_hprot;
end
if(T60) begin
R88 <= io_ins_1_hprot;
end
if(T65) begin
R92 <= io_ins_0_hprot;
end
if(T54) begin
R97 <= io_ins_2_hburst;
end
if(T60) begin
R102 <= io_ins_1_hburst;
end
if(T65) begin
R106 <= io_ins_0_hburst;
end
if(T54) begin
R111 <= io_ins_2_hsize;
end
if(T60) begin
R116 <= io_ins_1_hsize;
end
if(T65) begin
R120 <= io_ins_0_hsize;
end
if(T54) begin
R125 <= io_ins_2_hwrite;
end
if(T60) begin
R130 <= io_ins_1_hwrite;
end
if(T65) begin
R134 <= io_ins_0_hwrite;
end
if(T54) begin
R139 <= io_ins_2_haddr;
end
if(T60) begin
R144 <= io_ins_1_haddr;
end
if(T65) begin
R148 <= io_ins_0_haddr;
end
end
endmodule
module HastiXbar(input clk, input reset,
input [31:0] io_masters_2_haddr,
input io_masters_2_hwrite,
input [2:0] io_masters_2_hsize,
input [2:0] io_masters_2_hburst,
input [3:0] io_masters_2_hprot,
input [1:0] io_masters_2_htrans,
input io_masters_2_hmastlock,
input [31:0] io_masters_2_hwdata,
output[31:0] io_masters_2_hrdata,
output io_masters_2_hready,
output io_masters_2_hresp,
input [31:0] io_masters_1_haddr,
input io_masters_1_hwrite,
input [2:0] io_masters_1_hsize,
input [2:0] io_masters_1_hburst,
input [3:0] io_masters_1_hprot,
input [1:0] io_masters_1_htrans,
input io_masters_1_hmastlock,
input [31:0] io_masters_1_hwdata,
output[31:0] io_masters_1_hrdata,
output io_masters_1_hready,
output io_masters_1_hresp,
input [31:0] io_masters_0_haddr,
input io_masters_0_hwrite,
input [2:0] io_masters_0_hsize,
input [2:0] io_masters_0_hburst,
input [3:0] io_masters_0_hprot,
input [1:0] io_masters_0_htrans,
input io_masters_0_hmastlock,
input [31:0] io_masters_0_hwdata,
output[31:0] io_masters_0_hrdata,
output io_masters_0_hready,
output io_masters_0_hresp,
output[31:0] io_slaves_1_haddr,
output io_slaves_1_hwrite,
output[2:0] io_slaves_1_hsize,
output[2:0] io_slaves_1_hburst,
output[3:0] io_slaves_1_hprot,
output[1:0] io_slaves_1_htrans,
output io_slaves_1_hmastlock,
output[31:0] io_slaves_1_hwdata,
input [31:0] io_slaves_1_hrdata,
output io_slaves_1_hsel,
output io_slaves_1_hreadyin,
input io_slaves_1_hreadyout,
input io_slaves_1_hresp,
output[31:0] io_slaves_0_haddr,
output io_slaves_0_hwrite,
output[2:0] io_slaves_0_hsize,
output[2:0] io_slaves_0_hburst,
output[3:0] io_slaves_0_hprot,
output[1:0] io_slaves_0_htrans,
output io_slaves_0_hmastlock,
output[31:0] io_slaves_0_hwdata,
input [31:0] io_slaves_0_hrdata,
output io_slaves_0_hsel,
output io_slaves_0_hreadyin,
input io_slaves_0_hreadyout,
input io_slaves_0_hresp
);
wire[31:0] HastiBus_io_master_hrdata;
wire HastiBus_io_master_hready;
wire HastiBus_io_master_hresp;
wire[31:0] HastiBus_io_slaves_1_haddr;
wire HastiBus_io_slaves_1_hwrite;
wire[2:0] HastiBus_io_slaves_1_hsize;
wire[2:0] HastiBus_io_slaves_1_hburst;
wire[3:0] HastiBus_io_slaves_1_hprot;
wire[1:0] HastiBus_io_slaves_1_htrans;
wire HastiBus_io_slaves_1_hmastlock;
wire[31:0] HastiBus_io_slaves_1_hwdata;
wire HastiBus_io_slaves_1_hsel;
wire HastiBus_io_slaves_1_hreadyin;
wire[31:0] HastiBus_io_slaves_0_haddr;
wire HastiBus_io_slaves_0_hwrite;
wire[2:0] HastiBus_io_slaves_0_hsize;
wire[2:0] HastiBus_io_slaves_0_hburst;
wire[3:0] HastiBus_io_slaves_0_hprot;
wire[1:0] HastiBus_io_slaves_0_htrans;
wire HastiBus_io_slaves_0_hmastlock;
wire[31:0] HastiBus_io_slaves_0_hwdata;
wire HastiBus_io_slaves_0_hsel;
wire HastiBus_io_slaves_0_hreadyin;
wire[31:0] HastiBus_1_io_master_hrdata;
wire HastiBus_1_io_master_hready;
wire HastiBus_1_io_master_hresp;
wire[31:0] HastiBus_1_io_slaves_1_haddr;
wire HastiBus_1_io_slaves_1_hwrite;
wire[2:0] HastiBus_1_io_slaves_1_hsize;
wire[2:0] HastiBus_1_io_slaves_1_hburst;
wire[3:0] HastiBus_1_io_slaves_1_hprot;
wire[1:0] HastiBus_1_io_slaves_1_htrans;
wire HastiBus_1_io_slaves_1_hmastlock;
wire[31:0] HastiBus_1_io_slaves_1_hwdata;
wire HastiBus_1_io_slaves_1_hsel;
wire HastiBus_1_io_slaves_1_hreadyin;
wire[31:0] HastiBus_1_io_slaves_0_haddr;
wire HastiBus_1_io_slaves_0_hwrite;
wire[2:0] HastiBus_1_io_slaves_0_hsize;
wire[2:0] HastiBus_1_io_slaves_0_hburst;
wire[3:0] HastiBus_1_io_slaves_0_hprot;
wire[1:0] HastiBus_1_io_slaves_0_htrans;
wire HastiBus_1_io_slaves_0_hmastlock;
wire[31:0] HastiBus_1_io_slaves_0_hwdata;
wire HastiBus_1_io_slaves_0_hsel;
wire HastiBus_1_io_slaves_0_hreadyin;
wire[31:0] HastiBus_2_io_master_hrdata;
wire HastiBus_2_io_master_hready;
wire HastiBus_2_io_master_hresp;
wire[31:0] HastiBus_2_io_slaves_1_haddr;
wire HastiBus_2_io_slaves_1_hwrite;
wire[2:0] HastiBus_2_io_slaves_1_hsize;
wire[2:0] HastiBus_2_io_slaves_1_hburst;
wire[3:0] HastiBus_2_io_slaves_1_hprot;
wire[1:0] HastiBus_2_io_slaves_1_htrans;
wire HastiBus_2_io_slaves_1_hmastlock;
wire[31:0] HastiBus_2_io_slaves_1_hwdata;
wire HastiBus_2_io_slaves_1_hsel;
wire HastiBus_2_io_slaves_1_hreadyin;
wire[31:0] HastiBus_2_io_slaves_0_haddr;
wire HastiBus_2_io_slaves_0_hwrite;
wire[2:0] HastiBus_2_io_slaves_0_hsize;
wire[2:0] HastiBus_2_io_slaves_0_hburst;
wire[3:0] HastiBus_2_io_slaves_0_hprot;
wire[1:0] HastiBus_2_io_slaves_0_htrans;
wire HastiBus_2_io_slaves_0_hmastlock;
wire[31:0] HastiBus_2_io_slaves_0_hwdata;
wire HastiBus_2_io_slaves_0_hsel;
wire HastiBus_2_io_slaves_0_hreadyin;
wire[31:0] HastiSlaveMux_io_ins_2_hrdata;
wire HastiSlaveMux_io_ins_2_hreadyout;
wire HastiSlaveMux_io_ins_2_hresp;
wire[31:0] HastiSlaveMux_io_ins_1_hrdata;
wire HastiSlaveMux_io_ins_1_hreadyout;
wire HastiSlaveMux_io_ins_1_hresp;
wire[31:0] HastiSlaveMux_io_ins_0_hrdata;
wire HastiSlaveMux_io_ins_0_hreadyout;
wire HastiSlaveMux_io_ins_0_hresp;
wire[31:0] HastiSlaveMux_io_out_haddr;
wire HastiSlaveMux_io_out_hwrite;
wire[2:0] HastiSlaveMux_io_out_hsize;
wire[2:0] HastiSlaveMux_io_out_hburst;
wire[3:0] HastiSlaveMux_io_out_hprot;
wire[1:0] HastiSlaveMux_io_out_htrans;
wire HastiSlaveMux_io_out_hmastlock;
wire[31:0] HastiSlaveMux_io_out_hwdata;
wire HastiSlaveMux_io_out_hsel;
wire HastiSlaveMux_io_out_hreadyin;
wire[31:0] HastiSlaveMux_1_io_ins_2_hrdata;
wire HastiSlaveMux_1_io_ins_2_hreadyout;
wire HastiSlaveMux_1_io_ins_2_hresp;
wire[31:0] HastiSlaveMux_1_io_ins_1_hrdata;
wire HastiSlaveMux_1_io_ins_1_hreadyout;
wire HastiSlaveMux_1_io_ins_1_hresp;
wire[31:0] HastiSlaveMux_1_io_ins_0_hrdata;
wire HastiSlaveMux_1_io_ins_0_hreadyout;
wire HastiSlaveMux_1_io_ins_0_hresp;
wire[31:0] HastiSlaveMux_1_io_out_haddr;
wire HastiSlaveMux_1_io_out_hwrite;
wire[2:0] HastiSlaveMux_1_io_out_hsize;
wire[2:0] HastiSlaveMux_1_io_out_hburst;
wire[3:0] HastiSlaveMux_1_io_out_hprot;
wire[1:0] HastiSlaveMux_1_io_out_htrans;
wire HastiSlaveMux_1_io_out_hmastlock;
wire[31:0] HastiSlaveMux_1_io_out_hwdata;
wire HastiSlaveMux_1_io_out_hsel;
wire HastiSlaveMux_1_io_out_hreadyin;
assign io_slaves_0_hreadyin = HastiSlaveMux_io_out_hreadyin;
assign io_slaves_0_hsel = HastiSlaveMux_io_out_hsel;
assign io_slaves_0_hwdata = HastiSlaveMux_io_out_hwdata;
assign io_slaves_0_hmastlock = HastiSlaveMux_io_out_hmastlock;
assign io_slaves_0_htrans = HastiSlaveMux_io_out_htrans;
assign io_slaves_0_hprot = HastiSlaveMux_io_out_hprot;
assign io_slaves_0_hburst = HastiSlaveMux_io_out_hburst;
assign io_slaves_0_hsize = HastiSlaveMux_io_out_hsize;
assign io_slaves_0_hwrite = HastiSlaveMux_io_out_hwrite;
assign io_slaves_0_haddr = HastiSlaveMux_io_out_haddr;
assign io_slaves_1_hreadyin = HastiSlaveMux_1_io_out_hreadyin;
assign io_slaves_1_hsel = HastiSlaveMux_1_io_out_hsel;
assign io_slaves_1_hwdata = HastiSlaveMux_1_io_out_hwdata;
assign io_slaves_1_hmastlock = HastiSlaveMux_1_io_out_hmastlock;
assign io_slaves_1_htrans = HastiSlaveMux_1_io_out_htrans;
assign io_slaves_1_hprot = HastiSlaveMux_1_io_out_hprot;
assign io_slaves_1_hburst = HastiSlaveMux_1_io_out_hburst;
assign io_slaves_1_hsize = HastiSlaveMux_1_io_out_hsize;
assign io_slaves_1_hwrite = HastiSlaveMux_1_io_out_hwrite;
assign io_slaves_1_haddr = HastiSlaveMux_1_io_out_haddr;
assign io_masters_0_hresp = HastiBus_io_master_hresp;
assign io_masters_0_hready = HastiBus_io_master_hready;
assign io_masters_0_hrdata = HastiBus_io_master_hrdata;
assign io_masters_1_hresp = HastiBus_1_io_master_hresp;
assign io_masters_1_hready = HastiBus_1_io_master_hready;
assign io_masters_1_hrdata = HastiBus_1_io_master_hrdata;
assign io_masters_2_hresp = HastiBus_2_io_master_hresp;
assign io_masters_2_hready = HastiBus_2_io_master_hready;
assign io_masters_2_hrdata = HastiBus_2_io_master_hrdata;
HastiBus HastiBus(.clk(clk), .reset(reset),
.io_master_haddr( io_masters_0_haddr ),
.io_master_hwrite( io_masters_0_hwrite ),
.io_master_hsize( io_masters_0_hsize ),
.io_master_hburst( io_masters_0_hburst ),
.io_master_hprot( io_masters_0_hprot ),
.io_master_htrans( io_masters_0_htrans ),
.io_master_hmastlock( io_masters_0_hmastlock ),
.io_master_hwdata( io_masters_0_hwdata ),
.io_master_hrdata( HastiBus_io_master_hrdata ),
.io_master_hready( HastiBus_io_master_hready ),
.io_master_hresp( HastiBus_io_master_hresp ),
.io_slaves_1_haddr( HastiBus_io_slaves_1_haddr ),
.io_slaves_1_hwrite( HastiBus_io_slaves_1_hwrite ),
.io_slaves_1_hsize( HastiBus_io_slaves_1_hsize ),
.io_slaves_1_hburst( HastiBus_io_slaves_1_hburst ),
.io_slaves_1_hprot( HastiBus_io_slaves_1_hprot ),
.io_slaves_1_htrans( HastiBus_io_slaves_1_htrans ),
.io_slaves_1_hmastlock( HastiBus_io_slaves_1_hmastlock ),
.io_slaves_1_hwdata( HastiBus_io_slaves_1_hwdata ),
.io_slaves_1_hrdata( HastiSlaveMux_1_io_ins_0_hrdata ),
.io_slaves_1_hsel( HastiBus_io_slaves_1_hsel ),
.io_slaves_1_hreadyin( HastiBus_io_slaves_1_hreadyin ),
.io_slaves_1_hreadyout( HastiSlaveMux_1_io_ins_0_hreadyout ),
.io_slaves_1_hresp( HastiSlaveMux_1_io_ins_0_hresp ),
.io_slaves_0_haddr( HastiBus_io_slaves_0_haddr ),
.io_slaves_0_hwrite( HastiBus_io_slaves_0_hwrite ),
.io_slaves_0_hsize( HastiBus_io_slaves_0_hsize ),
.io_slaves_0_hburst( HastiBus_io_slaves_0_hburst ),
.io_slaves_0_hprot( HastiBus_io_slaves_0_hprot ),
.io_slaves_0_htrans( HastiBus_io_slaves_0_htrans ),
.io_slaves_0_hmastlock( HastiBus_io_slaves_0_hmastlock ),
.io_slaves_0_hwdata( HastiBus_io_slaves_0_hwdata ),
.io_slaves_0_hrdata( HastiSlaveMux_io_ins_0_hrdata ),
.io_slaves_0_hsel( HastiBus_io_slaves_0_hsel ),
.io_slaves_0_hreadyin( HastiBus_io_slaves_0_hreadyin ),
.io_slaves_0_hreadyout( HastiSlaveMux_io_ins_0_hreadyout ),
.io_slaves_0_hresp( HastiSlaveMux_io_ins_0_hresp )
);
HastiBus HastiBus_1(.clk(clk), .reset(reset),
.io_master_haddr( io_masters_1_haddr ),
.io_master_hwrite( io_masters_1_hwrite ),
.io_master_hsize( io_masters_1_hsize ),
.io_master_hburst( io_masters_1_hburst ),
.io_master_hprot( io_masters_1_hprot ),
.io_master_htrans( io_masters_1_htrans ),
.io_master_hmastlock( io_masters_1_hmastlock ),
.io_master_hwdata( io_masters_1_hwdata ),
.io_master_hrdata( HastiBus_1_io_master_hrdata ),
.io_master_hready( HastiBus_1_io_master_hready ),
.io_master_hresp( HastiBus_1_io_master_hresp ),
.io_slaves_1_haddr( HastiBus_1_io_slaves_1_haddr ),
.io_slaves_1_hwrite( HastiBus_1_io_slaves_1_hwrite ),
.io_slaves_1_hsize( HastiBus_1_io_slaves_1_hsize ),
.io_slaves_1_hburst( HastiBus_1_io_slaves_1_hburst ),
.io_slaves_1_hprot( HastiBus_1_io_slaves_1_hprot ),
.io_slaves_1_htrans( HastiBus_1_io_slaves_1_htrans ),
.io_slaves_1_hmastlock( HastiBus_1_io_slaves_1_hmastlock ),
.io_slaves_1_hwdata( HastiBus_1_io_slaves_1_hwdata ),
.io_slaves_1_hrdata( HastiSlaveMux_1_io_ins_1_hrdata ),
.io_slaves_1_hsel( HastiBus_1_io_slaves_1_hsel ),
.io_slaves_1_hreadyin( HastiBus_1_io_slaves_1_hreadyin ),
.io_slaves_1_hreadyout( HastiSlaveMux_1_io_ins_1_hreadyout ),
.io_slaves_1_hresp( HastiSlaveMux_1_io_ins_1_hresp ),
.io_slaves_0_haddr( HastiBus_1_io_slaves_0_haddr ),
.io_slaves_0_hwrite( HastiBus_1_io_slaves_0_hwrite ),
.io_slaves_0_hsize( HastiBus_1_io_slaves_0_hsize ),
.io_slaves_0_hburst( HastiBus_1_io_slaves_0_hburst ),
.io_slaves_0_hprot( HastiBus_1_io_slaves_0_hprot ),
.io_slaves_0_htrans( HastiBus_1_io_slaves_0_htrans ),
.io_slaves_0_hmastlock( HastiBus_1_io_slaves_0_hmastlock ),
.io_slaves_0_hwdata( HastiBus_1_io_slaves_0_hwdata ),
.io_slaves_0_hrdata( HastiSlaveMux_io_ins_1_hrdata ),
.io_slaves_0_hsel( HastiBus_1_io_slaves_0_hsel ),
.io_slaves_0_hreadyin( HastiBus_1_io_slaves_0_hreadyin ),
.io_slaves_0_hreadyout( HastiSlaveMux_io_ins_1_hreadyout ),
.io_slaves_0_hresp( HastiSlaveMux_io_ins_1_hresp )
);
HastiBus HastiBus_2(.clk(clk), .reset(reset),
.io_master_haddr( io_masters_2_haddr ),
.io_master_hwrite( io_masters_2_hwrite ),
.io_master_hsize( io_masters_2_hsize ),
.io_master_hburst( io_masters_2_hburst ),
.io_master_hprot( io_masters_2_hprot ),
.io_master_htrans( io_masters_2_htrans ),
.io_master_hmastlock( io_masters_2_hmastlock ),
.io_master_hwdata( io_masters_2_hwdata ),
.io_master_hrdata( HastiBus_2_io_master_hrdata ),
.io_master_hready( HastiBus_2_io_master_hready ),
.io_master_hresp( HastiBus_2_io_master_hresp ),
.io_slaves_1_haddr( HastiBus_2_io_slaves_1_haddr ),
.io_slaves_1_hwrite( HastiBus_2_io_slaves_1_hwrite ),
.io_slaves_1_hsize( HastiBus_2_io_slaves_1_hsize ),
.io_slaves_1_hburst( HastiBus_2_io_slaves_1_hburst ),
.io_slaves_1_hprot( HastiBus_2_io_slaves_1_hprot ),
.io_slaves_1_htrans( HastiBus_2_io_slaves_1_htrans ),
.io_slaves_1_hmastlock( HastiBus_2_io_slaves_1_hmastlock ),
.io_slaves_1_hwdata( HastiBus_2_io_slaves_1_hwdata ),
.io_slaves_1_hrdata( HastiSlaveMux_1_io_ins_2_hrdata ),
.io_slaves_1_hsel( HastiBus_2_io_slaves_1_hsel ),
.io_slaves_1_hreadyin( HastiBus_2_io_slaves_1_hreadyin ),
.io_slaves_1_hreadyout( HastiSlaveMux_1_io_ins_2_hreadyout ),
.io_slaves_1_hresp( HastiSlaveMux_1_io_ins_2_hresp ),
.io_slaves_0_haddr( HastiBus_2_io_slaves_0_haddr ),
.io_slaves_0_hwrite( HastiBus_2_io_slaves_0_hwrite ),
.io_slaves_0_hsize( HastiBus_2_io_slaves_0_hsize ),
.io_slaves_0_hburst( HastiBus_2_io_slaves_0_hburst ),
.io_slaves_0_hprot( HastiBus_2_io_slaves_0_hprot ),
.io_slaves_0_htrans( HastiBus_2_io_slaves_0_htrans ),
.io_slaves_0_hmastlock( HastiBus_2_io_slaves_0_hmastlock ),
.io_slaves_0_hwdata( HastiBus_2_io_slaves_0_hwdata ),
.io_slaves_0_hrdata( HastiSlaveMux_io_ins_2_hrdata ),
.io_slaves_0_hsel( HastiBus_2_io_slaves_0_hsel ),
.io_slaves_0_hreadyin( HastiBus_2_io_slaves_0_hreadyin ),
.io_slaves_0_hreadyout( HastiSlaveMux_io_ins_2_hreadyout ),
.io_slaves_0_hresp( HastiSlaveMux_io_ins_2_hresp )
);
HastiSlaveMux HastiSlaveMux(.clk(clk), .reset(reset),
.io_ins_2_haddr( HastiBus_2_io_slaves_0_haddr ),
.io_ins_2_hwrite( HastiBus_2_io_slaves_0_hwrite ),
.io_ins_2_hsize( HastiBus_2_io_slaves_0_hsize ),
.io_ins_2_hburst( HastiBus_2_io_slaves_0_hburst ),
.io_ins_2_hprot( HastiBus_2_io_slaves_0_hprot ),
.io_ins_2_htrans( HastiBus_2_io_slaves_0_htrans ),
.io_ins_2_hmastlock( HastiBus_2_io_slaves_0_hmastlock ),
.io_ins_2_hwdata( HastiBus_2_io_slaves_0_hwdata ),
.io_ins_2_hrdata( HastiSlaveMux_io_ins_2_hrdata ),
.io_ins_2_hsel( HastiBus_2_io_slaves_0_hsel ),
.io_ins_2_hreadyin( HastiBus_2_io_slaves_0_hreadyin ),
.io_ins_2_hreadyout( HastiSlaveMux_io_ins_2_hreadyout ),
.io_ins_2_hresp( HastiSlaveMux_io_ins_2_hresp ),
.io_ins_1_haddr( HastiBus_1_io_slaves_0_haddr ),
.io_ins_1_hwrite( HastiBus_1_io_slaves_0_hwrite ),
.io_ins_1_hsize( HastiBus_1_io_slaves_0_hsize ),
.io_ins_1_hburst( HastiBus_1_io_slaves_0_hburst ),
.io_ins_1_hprot( HastiBus_1_io_slaves_0_hprot ),
.io_ins_1_htrans( HastiBus_1_io_slaves_0_htrans ),
.io_ins_1_hmastlock( HastiBus_1_io_slaves_0_hmastlock ),
.io_ins_1_hwdata( HastiBus_1_io_slaves_0_hwdata ),
.io_ins_1_hrdata( HastiSlaveMux_io_ins_1_hrdata ),
.io_ins_1_hsel( HastiBus_1_io_slaves_0_hsel ),
.io_ins_1_hreadyin( HastiBus_1_io_slaves_0_hreadyin ),
.io_ins_1_hreadyout( HastiSlaveMux_io_ins_1_hreadyout ),
.io_ins_1_hresp( HastiSlaveMux_io_ins_1_hresp ),
.io_ins_0_haddr( HastiBus_io_slaves_0_haddr ),
.io_ins_0_hwrite( HastiBus_io_slaves_0_hwrite ),
.io_ins_0_hsize( HastiBus_io_slaves_0_hsize ),
.io_ins_0_hburst( HastiBus_io_slaves_0_hburst ),
.io_ins_0_hprot( HastiBus_io_slaves_0_hprot ),
.io_ins_0_htrans( HastiBus_io_slaves_0_htrans ),
.io_ins_0_hmastlock( HastiBus_io_slaves_0_hmastlock ),
.io_ins_0_hwdata( HastiBus_io_slaves_0_hwdata ),
.io_ins_0_hrdata( HastiSlaveMux_io_ins_0_hrdata ),
.io_ins_0_hsel( HastiBus_io_slaves_0_hsel ),
.io_ins_0_hreadyin( HastiBus_io_slaves_0_hreadyin ),
.io_ins_0_hreadyout( HastiSlaveMux_io_ins_0_hreadyout ),
.io_ins_0_hresp( HastiSlaveMux_io_ins_0_hresp ),
.io_out_haddr( HastiSlaveMux_io_out_haddr ),
.io_out_hwrite( HastiSlaveMux_io_out_hwrite ),
.io_out_hsize( HastiSlaveMux_io_out_hsize ),
.io_out_hburst( HastiSlaveMux_io_out_hburst ),
.io_out_hprot( HastiSlaveMux_io_out_hprot ),
.io_out_htrans( HastiSlaveMux_io_out_htrans ),
.io_out_hmastlock( HastiSlaveMux_io_out_hmastlock ),
.io_out_hwdata( HastiSlaveMux_io_out_hwdata ),
.io_out_hrdata( io_slaves_0_hrdata ),
.io_out_hsel( HastiSlaveMux_io_out_hsel ),
.io_out_hreadyin( HastiSlaveMux_io_out_hreadyin ),
.io_out_hreadyout( io_slaves_0_hreadyout ),
.io_out_hresp( io_slaves_0_hresp )
);
HastiSlaveMux HastiSlaveMux_1(.clk(clk), .reset(reset),
.io_ins_2_haddr( HastiBus_2_io_slaves_1_haddr ),
.io_ins_2_hwrite( HastiBus_2_io_slaves_1_hwrite ),
.io_ins_2_hsize( HastiBus_2_io_slaves_1_hsize ),
.io_ins_2_hburst( HastiBus_2_io_slaves_1_hburst ),
.io_ins_2_hprot( HastiBus_2_io_slaves_1_hprot ),
.io_ins_2_htrans( HastiBus_2_io_slaves_1_htrans ),
.io_ins_2_hmastlock( HastiBus_2_io_slaves_1_hmastlock ),
.io_ins_2_hwdata( HastiBus_2_io_slaves_1_hwdata ),
.io_ins_2_hrdata( HastiSlaveMux_1_io_ins_2_hrdata ),
.io_ins_2_hsel( HastiBus_2_io_slaves_1_hsel ),
.io_ins_2_hreadyin( HastiBus_2_io_slaves_1_hreadyin ),
.io_ins_2_hreadyout( HastiSlaveMux_1_io_ins_2_hreadyout ),
.io_ins_2_hresp( HastiSlaveMux_1_io_ins_2_hresp ),
.io_ins_1_haddr( HastiBus_1_io_slaves_1_haddr ),
.io_ins_1_hwrite( HastiBus_1_io_slaves_1_hwrite ),
.io_ins_1_hsize( HastiBus_1_io_slaves_1_hsize ),
.io_ins_1_hburst( HastiBus_1_io_slaves_1_hburst ),
.io_ins_1_hprot( HastiBus_1_io_slaves_1_hprot ),
.io_ins_1_htrans( HastiBus_1_io_slaves_1_htrans ),
.io_ins_1_hmastlock( HastiBus_1_io_slaves_1_hmastlock ),
.io_ins_1_hwdata( HastiBus_1_io_slaves_1_hwdata ),
.io_ins_1_hrdata( HastiSlaveMux_1_io_ins_1_hrdata ),
.io_ins_1_hsel( HastiBus_1_io_slaves_1_hsel ),
.io_ins_1_hreadyin( HastiBus_1_io_slaves_1_hreadyin ),
.io_ins_1_hreadyout( HastiSlaveMux_1_io_ins_1_hreadyout ),
.io_ins_1_hresp( HastiSlaveMux_1_io_ins_1_hresp ),
.io_ins_0_haddr( HastiBus_io_slaves_1_haddr ),
.io_ins_0_hwrite( HastiBus_io_slaves_1_hwrite ),
.io_ins_0_hsize( HastiBus_io_slaves_1_hsize ),
.io_ins_0_hburst( HastiBus_io_slaves_1_hburst ),
.io_ins_0_hprot( HastiBus_io_slaves_1_hprot ),
.io_ins_0_htrans( HastiBus_io_slaves_1_htrans ),
.io_ins_0_hmastlock( HastiBus_io_slaves_1_hmastlock ),
.io_ins_0_hwdata( HastiBus_io_slaves_1_hwdata ),
.io_ins_0_hrdata( HastiSlaveMux_1_io_ins_0_hrdata ),
.io_ins_0_hsel( HastiBus_io_slaves_1_hsel ),
.io_ins_0_hreadyin( HastiBus_io_slaves_1_hreadyin ),
.io_ins_0_hreadyout( HastiSlaveMux_1_io_ins_0_hreadyout ),
.io_ins_0_hresp( HastiSlaveMux_1_io_ins_0_hresp ),
.io_out_haddr( HastiSlaveMux_1_io_out_haddr ),
.io_out_hwrite( HastiSlaveMux_1_io_out_hwrite ),
.io_out_hsize( HastiSlaveMux_1_io_out_hsize ),
.io_out_hburst( HastiSlaveMux_1_io_out_hburst ),
.io_out_hprot( HastiSlaveMux_1_io_out_hprot ),
.io_out_htrans( HastiSlaveMux_1_io_out_htrans ),
.io_out_hmastlock( HastiSlaveMux_1_io_out_hmastlock ),
.io_out_hwdata( HastiSlaveMux_1_io_out_hwdata ),
.io_out_hrdata( io_slaves_1_hrdata ),
.io_out_hsel( HastiSlaveMux_1_io_out_hsel ),
.io_out_hreadyin( HastiSlaveMux_1_io_out_hreadyin ),
.io_out_hreadyout( io_slaves_1_hreadyout ),
.io_out_hresp( io_slaves_1_hresp )
);
endmodule
module Ahbmli(input clk, input reset,
input [31:0] io_jtag_haddr,
input io_jtag_hwrite,
input [2:0] io_jtag_hsize,
input [2:0] io_jtag_hburst,
input [3:0] io_jtag_hprot,
input [1:0] io_jtag_htrans,
input io_jtag_hmastlock,
input [31:0] io_jtag_hwdata,
output[31:0] io_jtag_hrdata,
output io_jtag_hready,
output io_jtag_hresp,
input [31:0] io_dmem_haddr,
input io_dmem_hwrite,
input [2:0] io_dmem_hsize,
input [2:0] io_dmem_hburst,
input [3:0] io_dmem_hprot,
input [1:0] io_dmem_htrans,
input io_dmem_hmastlock,
input [31:0] io_dmem_hwdata,
output[31:0] io_dmem_hrdata,
output io_dmem_hready,
output io_dmem_hresp,
input [31:0] io_imem_haddr,
input io_imem_hwrite,
input [2:0] io_imem_hsize,
input [2:0] io_imem_hburst,
input [3:0] io_imem_hprot,
input [1:0] io_imem_htrans,
input io_imem_hmastlock,
input [31:0] io_imem_hwdata,
output[31:0] io_imem_hrdata,
output io_imem_hready,
output io_imem_hresp,
output[31:0] io_datamem_haddr,
output io_datamem_hwrite,
output[2:0] io_datamem_hsize,
output[2:0] io_datamem_hburst,
output[3:0] io_datamem_hprot,
output[1:0] io_datamem_htrans,
output io_datamem_hmastlock,
output[31:0] io_datamem_hwdata,
input [31:0] io_datamem_hrdata,
output io_datamem_hsel,
output io_datamem_hreadyin,
input io_datamem_hreadyout,
input io_datamem_hresp,
output[31:0] io_codemem_haddr,
output io_codemem_hwrite,
output[2:0] io_codemem_hsize,
output[2:0] io_codemem_hburst,
output[3:0] io_codemem_hprot,
output[1:0] io_codemem_htrans,
output io_codemem_hmastlock,
output[31:0] io_codemem_hwdata,
input [31:0] io_codemem_hrdata,
output io_codemem_hsel,
output io_codemem_hreadyin,
input io_codemem_hreadyout,
input io_codemem_hresp
);
wire[31:0] xbar_io_masters_2_hrdata;
wire xbar_io_masters_2_hready;
wire xbar_io_masters_2_hresp;
wire[31:0] xbar_io_masters_1_hrdata;
wire xbar_io_masters_1_hready;
wire xbar_io_masters_1_hresp;
wire[31:0] xbar_io_masters_0_hrdata;
wire xbar_io_masters_0_hready;
wire xbar_io_masters_0_hresp;
wire[31:0] xbar_io_slaves_1_haddr;
wire xbar_io_slaves_1_hwrite;
wire[2:0] xbar_io_slaves_1_hsize;
wire[2:0] xbar_io_slaves_1_hburst;
wire[3:0] xbar_io_slaves_1_hprot;
wire[1:0] xbar_io_slaves_1_htrans;
wire xbar_io_slaves_1_hmastlock;
wire[31:0] xbar_io_slaves_1_hwdata;
wire xbar_io_slaves_1_hsel;
wire xbar_io_slaves_1_hreadyin;
wire[31:0] xbar_io_slaves_0_haddr;
wire xbar_io_slaves_0_hwrite;
wire[2:0] xbar_io_slaves_0_hsize;
wire[2:0] xbar_io_slaves_0_hburst;
wire[3:0] xbar_io_slaves_0_hprot;
wire[1:0] xbar_io_slaves_0_htrans;
wire xbar_io_slaves_0_hmastlock;
wire[31:0] xbar_io_slaves_0_hwdata;
wire xbar_io_slaves_0_hsel;
wire xbar_io_slaves_0_hreadyin;
assign io_codemem_hreadyin = xbar_io_slaves_1_hreadyin;
assign io_codemem_hsel = xbar_io_slaves_1_hsel;
assign io_codemem_hwdata = xbar_io_slaves_1_hwdata;
assign io_codemem_hmastlock = xbar_io_slaves_1_hmastlock;
assign io_codemem_htrans = xbar_io_slaves_1_htrans;
assign io_codemem_hprot = xbar_io_slaves_1_hprot;
assign io_codemem_hburst = xbar_io_slaves_1_hburst;
assign io_codemem_hsize = xbar_io_slaves_1_hsize;
assign io_codemem_hwrite = xbar_io_slaves_1_hwrite;
assign io_codemem_haddr = xbar_io_slaves_1_haddr;
assign io_datamem_hreadyin = xbar_io_slaves_0_hreadyin;
assign io_datamem_hsel = xbar_io_slaves_0_hsel;
assign io_datamem_hwdata = xbar_io_slaves_0_hwdata;
assign io_datamem_hmastlock = xbar_io_slaves_0_hmastlock;
assign io_datamem_htrans = xbar_io_slaves_0_htrans;
assign io_datamem_hprot = xbar_io_slaves_0_hprot;
assign io_datamem_hburst = xbar_io_slaves_0_hburst;
assign io_datamem_hsize = xbar_io_slaves_0_hsize;
assign io_datamem_hwrite = xbar_io_slaves_0_hwrite;
assign io_datamem_haddr = xbar_io_slaves_0_haddr;
assign io_imem_hresp = xbar_io_masters_2_hresp;
assign io_imem_hready = xbar_io_masters_2_hready;
assign io_imem_hrdata = xbar_io_masters_2_hrdata;
assign io_dmem_hresp = xbar_io_masters_1_hresp;
assign io_dmem_hready = xbar_io_masters_1_hready;
assign io_dmem_hrdata = xbar_io_masters_1_hrdata;
assign io_jtag_hresp = xbar_io_masters_0_hresp;
assign io_jtag_hready = xbar_io_masters_0_hready;
assign io_jtag_hrdata = xbar_io_masters_0_hrdata;
HastiXbar xbar(.clk(clk), .reset(reset),
.io_masters_2_haddr( io_imem_haddr ),
.io_masters_2_hwrite( io_imem_hwrite ),
.io_masters_2_hsize( io_imem_hsize ),
.io_masters_2_hburst( io_imem_hburst ),
.io_masters_2_hprot( io_imem_hprot ),
.io_masters_2_htrans( io_imem_htrans ),
.io_masters_2_hmastlock( io_imem_hmastlock ),
.io_masters_2_hwdata( io_imem_hwdata ),
.io_masters_2_hrdata( xbar_io_masters_2_hrdata ),
.io_masters_2_hready( xbar_io_masters_2_hready ),
.io_masters_2_hresp( xbar_io_masters_2_hresp ),
.io_masters_1_haddr( io_dmem_haddr ),
.io_masters_1_hwrite( io_dmem_hwrite ),
.io_masters_1_hsize( io_dmem_hsize ),
.io_masters_1_hburst( io_dmem_hburst ),
.io_masters_1_hprot( io_dmem_hprot ),
.io_masters_1_htrans( io_dmem_htrans ),
.io_masters_1_hmastlock( io_dmem_hmastlock ),
.io_masters_1_hwdata( io_dmem_hwdata ),
.io_masters_1_hrdata( xbar_io_masters_1_hrdata ),
.io_masters_1_hready( xbar_io_masters_1_hready ),
.io_masters_1_hresp( xbar_io_masters_1_hresp ),
.io_masters_0_haddr( io_jtag_haddr ),
.io_masters_0_hwrite( io_jtag_hwrite ),
.io_masters_0_hsize( io_jtag_hsize ),
.io_masters_0_hburst( io_jtag_hburst ),
.io_masters_0_hprot( io_jtag_hprot ),
.io_masters_0_htrans( io_jtag_htrans ),
.io_masters_0_hmastlock( io_jtag_hmastlock ),
.io_masters_0_hwdata( io_jtag_hwdata ),
.io_masters_0_hrdata( xbar_io_masters_0_hrdata ),
.io_masters_0_hready( xbar_io_masters_0_hready ),
.io_masters_0_hresp( xbar_io_masters_0_hresp ),
.io_slaves_1_haddr( xbar_io_slaves_1_haddr ),
.io_slaves_1_hwrite( xbar_io_slaves_1_hwrite ),
.io_slaves_1_hsize( xbar_io_slaves_1_hsize ),
.io_slaves_1_hburst( xbar_io_slaves_1_hburst ),
.io_slaves_1_hprot( xbar_io_slaves_1_hprot ),
.io_slaves_1_htrans( xbar_io_slaves_1_htrans ),
.io_slaves_1_hmastlock( xbar_io_slaves_1_hmastlock ),
.io_slaves_1_hwdata( xbar_io_slaves_1_hwdata ),
.io_slaves_1_hrdata( io_codemem_hrdata ),
.io_slaves_1_hsel( xbar_io_slaves_1_hsel ),
.io_slaves_1_hreadyin( xbar_io_slaves_1_hreadyin ),
.io_slaves_1_hreadyout( io_codemem_hreadyout ),
.io_slaves_1_hresp( io_codemem_hresp ),
.io_slaves_0_haddr( xbar_io_slaves_0_haddr ),
.io_slaves_0_hwrite( xbar_io_slaves_0_hwrite ),
.io_slaves_0_hsize( xbar_io_slaves_0_hsize ),
.io_slaves_0_hburst( xbar_io_slaves_0_hburst ),
.io_slaves_0_hprot( xbar_io_slaves_0_hprot ),
.io_slaves_0_htrans( xbar_io_slaves_0_htrans ),
.io_slaves_0_hmastlock( xbar_io_slaves_0_hmastlock ),
.io_slaves_0_hwdata( xbar_io_slaves_0_hwdata ),
.io_slaves_0_hrdata( io_datamem_hrdata ),
.io_slaves_0_hsel( xbar_io_slaves_0_hsel ),
.io_slaves_0_hreadyin( xbar_io_slaves_0_hreadyin ),
.io_slaves_0_hreadyout( io_datamem_hreadyout ),
.io_slaves_0_hresp( io_datamem_hresp )
);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The module to handle the different exceptions
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_excp(
output commit_trap,
output core_wfi,
output wfi_halt_ifu_req,
output wfi_halt_exu_req,
input wfi_halt_ifu_ack,
input wfi_halt_exu_ack,
input amo_wait,
output alu_excp_i_ready,
input alu_excp_i_valid ,
input alu_excp_i_ld ,
input alu_excp_i_stamo ,
input alu_excp_i_misalgn ,
input alu_excp_i_buserr ,
input alu_excp_i_ecall ,
input alu_excp_i_ebreak ,
input alu_excp_i_wfi ,
input alu_excp_i_ifu_misalgn ,
input alu_excp_i_ifu_buserr ,
input alu_excp_i_ifu_ilegl ,
input [`E203_ADDR_SIZE-1:0] alu_excp_i_badaddr,
input [`E203_PC_SIZE-1:0] alu_excp_i_pc,
input [`E203_INSTR_SIZE-1:0] alu_excp_i_instr,
input alu_excp_i_pc_vld,
output longp_excp_i_ready,
input longp_excp_i_valid,
input longp_excp_i_ld,
input longp_excp_i_st,// 1: load, 0: store
input longp_excp_i_buserr , // The load/store bus-error exception generated
input longp_excp_i_insterr,
input [`E203_ADDR_SIZE-1:0] longp_excp_i_badaddr,
input [`E203_PC_SIZE-1:0] longp_excp_i_pc,
input excpirq_flush_ack,
output excpirq_flush_req,
output nonalu_excpirq_flush_req_raw,
output [`E203_PC_SIZE-1:0] excpirq_flush_add_op1,
output [`E203_PC_SIZE-1:0] excpirq_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] excpirq_flush_pc,
`endif//}
input [`E203_XLEN-1:0] csr_mtvec_r,
input cmt_dret_ena,
input cmt_ena,
output [`E203_ADDR_SIZE-1:0] cmt_badaddr,
output [`E203_PC_SIZE-1:0] cmt_epc,
output [`E203_XLEN-1:0] cmt_cause,
output cmt_badaddr_ena,
output cmt_epc_ena,
output cmt_cause_ena,
output cmt_status_ena,
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
input status_mie_r,
input mtie_r,
input msie_r,
input meie_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input oitf_empty,
input u_mode,
input s_mode,
input h_mode,
input m_mode,
output excp_active,
input clk,
input rst_n
);
////////////////////////////////////////////////////////////////////////////
// Because the core's clock may be gated when it is idle, we need to check
// if the interrupts is coming, and generate an active indication, and use
// this active signal to turn on core's clock
wire irq_req_active;
wire nonalu_dbg_entry_req_raw;
assign excp_active = irq_req_active | nonalu_dbg_entry_req_raw;
////////////////////////////////////////////////////////////////////////////
// WFI flag generation
//
wire wfi_req_hsked = (wfi_halt_ifu_req & wfi_halt_ifu_ack & wfi_halt_exu_req & wfi_halt_exu_ack)
;
// The wfi_flag will be set if there is a new WFI instruction halt req handshaked
wire wfi_flag_set = wfi_req_hsked;
// The wfi_flag will be cleared if there is interrupt pending, or debug entry request
wire wfi_irq_req;
wire dbg_entry_req;
wire wfi_flag_r;
wire wfi_flag_clr = (wfi_irq_req | dbg_entry_req);// & wfi_flag_r;// Here we cannot use this flag_r
wire wfi_flag_ena = wfi_flag_set | wfi_flag_clr;
// If meanwhile set and clear, then clear preempt
wire wfi_flag_nxt = wfi_flag_set & (~wfi_flag_clr);
sirv_gnrl_dfflr #(1) wfi_flag_dfflr (wfi_flag_ena, wfi_flag_nxt, wfi_flag_r, clk, rst_n);
assign core_wfi = wfi_flag_r & (~wfi_flag_clr);
// The wfi_halt_req will be set if there is a new WFI instruction committed
// And note in debug mode WFI is treated as nop
wire wfi_cmt_ena = alu_excp_i_wfi & cmt_ena;
wire wfi_halt_req_set = wfi_cmt_ena & (~dbg_mode);
// The wfi_halt_req will be cleared same as wfi_flag_r
wire wfi_halt_req_clr = wfi_flag_clr;
wire wfi_halt_req_ena = wfi_halt_req_set | wfi_halt_req_clr;
// If meanwhile set and clear, then clear preempt
wire wfi_halt_req_nxt = wfi_halt_req_set & (~wfi_halt_req_clr);
wire wfi_halt_req_r;
sirv_gnrl_dfflr #(1) wfi_halt_req_dfflr (wfi_halt_req_ena, wfi_halt_req_nxt, wfi_halt_req_r, clk, rst_n);
// In order to make sure the flush to IFU and halt to IFU is not asserte at same cycle
// we use the clr signal here to qualify it
assign wfi_halt_ifu_req = (wfi_halt_req_r & (~wfi_halt_req_clr))
;
// To cut the comb loops, we dont use the clr signal here to qualify,
// the outcome is the halt-to-exu will be deasserted 1 cycle later than to-IFU
// but it doesnt matter much.
assign wfi_halt_exu_req = wfi_halt_req_r
;
wire irq_req;
wire longp_need_flush;
wire alu_need_flush;
wire dbg_ebrk_req;
wire dbg_trig_req;
////////////////////////////////////////////////////////////////////////////
// The Exception generate included several cases, priority from top to down
// *** Long-pipe triggered exception
// ---- Must wait the PC vld
// *** DebugMode-entry triggered exception (included ALU ebreakm)
// ---- Must wait the OITF empty and PC vld
// *** IRQ triggered exception
// ---- Must wait the OITF empty and PC vld
// *** ALU triggered exception (excluded the ebreakm into debug-mode)
// ---- Must wait the OITF empty
// Exclude the pc_vld for longp, to just always make sure the longp can always accepted
wire longp_excp_flush_req = longp_need_flush ;
assign longp_excp_i_ready = excpirq_flush_ack;
// ^^^ Below we qualified the pc_vld signal to IRQ and Debug-entry req, why?
// -- The Asyn-precise-excp (include IRQ and Debug-entry exception)
// need to use the next upcoming (not yet commited) instruction's PC
// for the mepc value, so we must wait next valid instruction coming
// and use its PC.
// -- The pc_vld indicate is just used to indicate next instruction's valid
// PC value.
// ^^^ Then the questions are coming, is there a possible that there is no pc_vld
// comes forever? and then this async-precise-exception never
// get served, and then become a deadlock?
// -- It should not be. Becuase:
// The IFU is always actively fetching next instructions, never stop,
// so ideally it will always provide next valid instructions as
// long as the Ifetch-path (bus to external memory or ITCM) is not hang
// (no bus response returned).
// ^^^ Then if there possible the Ifetch-path is hang? For examples:
// -- The Ifetched external memory does not provide response because of the External IRQ is not
// accepted by core.
// ** How could it be? This should not happen, otherwise it is a SoC bug.
//
wire dbg_entry_flush_req = dbg_entry_req & oitf_empty & alu_excp_i_pc_vld & (~longp_need_flush);
wire alu_excp_i_ready4dbg = (excpirq_flush_ack & oitf_empty & alu_excp_i_pc_vld & (~longp_need_flush));
wire irq_flush_req = irq_req & oitf_empty & alu_excp_i_pc_vld
& (~dbg_entry_req)
& (~longp_need_flush);
wire alu_excp_flush_req = alu_excp_i_valid & alu_need_flush & oitf_empty
& (~irq_req)
& (~dbg_entry_req)
& (~longp_need_flush);
wire nonalu_dbg_entry_req;
wire alu_excp_i_ready4nondbg = alu_need_flush ?
(excpirq_flush_ack & oitf_empty & (~irq_req) & (~nonalu_dbg_entry_req) & (~longp_need_flush))
: ( // The other higher priorty flush will override ALU commit
(~irq_req)
& (~nonalu_dbg_entry_req)
& (~longp_need_flush)
);
wire alu_ebreakm_flush_req_novld;
wire alu_dbgtrig_flush_req_novld;
assign alu_excp_i_ready = (alu_ebreakm_flush_req_novld | alu_dbgtrig_flush_req_novld) ? alu_excp_i_ready4dbg : alu_excp_i_ready4nondbg;
assign excpirq_flush_req = longp_excp_flush_req | dbg_entry_flush_req | irq_flush_req | alu_excp_flush_req;
wire all_excp_flush_req = longp_excp_flush_req | alu_excp_flush_req;
assign nonalu_excpirq_flush_req_raw =
longp_need_flush |
nonalu_dbg_entry_req_raw |
irq_req ;
wire excpirq_taken_ena = excpirq_flush_req & excpirq_flush_ack;
assign commit_trap = excpirq_taken_ena;
wire excp_taken_ena = all_excp_flush_req & excpirq_taken_ena;
wire irq_taken_ena = irq_flush_req & excpirq_taken_ena;
wire dbg_entry_taken_ena = dbg_entry_flush_req & excpirq_taken_ena;
assign excpirq_flush_add_op1 = dbg_entry_flush_req ? `E203_PC_SIZE'h800 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h808 : csr_mtvec_r;
assign excpirq_flush_add_op2 = dbg_entry_flush_req ? `E203_PC_SIZE'h0 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h0 : `E203_PC_SIZE'b0;
`ifdef E203_TIMING_BOOST//}
assign excpirq_flush_pc = dbg_entry_flush_req ? `E203_PC_SIZE'h800 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h808 : csr_mtvec_r;
`endif//}
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The Long-pipe triggered Exception
//
assign longp_need_flush = longp_excp_i_valid;// The longp come to excp
// module always ask for excepiton
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The DebugMode-entry triggered Exception
//
wire step_req_r;
wire alu_ebreakm_flush_req;
wire alu_dbgtrig_flush_req;
// The priority from top to down
// dbg_trig_req ? 3'd2 :
// dbg_ebrk_req ? 3'd1 :
// dbg_irq_req ? 3'd3 :
// dbg_step_req ? 3'd4 :
// dbg_halt_req ? 3'd5 :
// Since the step_req_r is last cycle generated indicated, means last instruction is single-step
// and it have been commited in non debug-mode, and then this cyclc step_req_r is the of the highest priority
wire dbg_step_req = step_req_r;
assign dbg_trig_req = alu_dbgtrig_flush_req & (~step_req_r);
assign dbg_ebrk_req = alu_ebreakm_flush_req & (~alu_dbgtrig_flush_req) & (~step_req_r);
wire dbg_irq_req = dbg_irq_r & (~alu_ebreakm_flush_req) & (~alu_dbgtrig_flush_req) & (~step_req_r);
wire nonalu_dbg_irq_req = dbg_irq_r & (~step_req_r);
// The step have higher priority, and will preempt the halt
wire dbg_halt_req = dbg_halt_r & (~dbg_irq_r) & (~alu_ebreakm_flush_req) & (~alu_dbgtrig_flush_req) & (~step_req_r) & (~dbg_step_r);
wire nonalu_dbg_halt_req = dbg_halt_r & (~dbg_irq_r) & (~step_req_r) & (~dbg_step_r);
// The debug-step request will be set when currently the step_r is high, and one
// instruction (in non debug_mode) have been executed
// The step request will be clear when
// core enter into the debug-mode
wire step_req_set = (~dbg_mode) & dbg_step_r & cmt_ena & (~dbg_entry_taken_ena);
wire step_req_clr = dbg_entry_taken_ena;
wire step_req_ena = step_req_set | step_req_clr;
wire step_req_nxt = step_req_set | (~step_req_clr);
sirv_gnrl_dfflr #(1) step_req_dfflr (step_req_ena, step_req_nxt, step_req_r, clk, rst_n);
// The debug-mode will mask off the debug-mode-entry
wire dbg_entry_mask = dbg_mode;
assign dbg_entry_req = (~dbg_entry_mask) & (
// Why do we put a AMO_wait here, because the AMO instructions
// is atomic, we must wait it to complete its all atomic operations
// and during wait cycles irq must be masked, otherwise the irq_req
// will block ALU commit (including AMO) and cause a deadlock
//
// Note: Only the async irq and halt and trig need to have this amo_wait to check
// others are sync event, no need to check with this
(dbg_irq_req & (~amo_wait))
| (dbg_halt_req & (~amo_wait))
| dbg_step_req
| (dbg_trig_req & (~amo_wait))
| dbg_ebrk_req
);
assign nonalu_dbg_entry_req = (~dbg_entry_mask) & (
(nonalu_dbg_irq_req & (~amo_wait))
| (nonalu_dbg_halt_req & (~amo_wait))
| dbg_step_req
//| (dbg_trig_req & (~amo_wait))
//| dbg_ebrk_req
);
assign nonalu_dbg_entry_req_raw = (~dbg_entry_mask) & (
dbg_irq_r
| dbg_halt_r
| step_req_r
//| dbg_trig_req
//| dbg_ebrk_req
);
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The IRQ triggered Exception
//
// The debug mode will mask off the interrupts
// The single-step mode will mask off the interrupts
wire irq_mask = dbg_mode | dbg_step_r | (~status_mie_r)
// Why do we put a AMO_wait here, because the AMO instructions
// is atomic, we must wait it to complete its all atomic operations
// and during wait cycles irq must be masked, otherwise the irq_req
// will block ALU commit (including AMO) and cause a deadlock
// Dont need to worry about the clock gating issue, if amo_wait,
// then defefinitely the ALU is active, and clock on
| amo_wait;
wire wfi_irq_mask = dbg_mode | dbg_step_r;
// Why dont we put amo_wait here, because this is for IRQ to wake
// up the core from sleep mode, the core was in sleep mode, then
// means there is no chance for it to still executing the AMO instructions
// with oustanding uops, so we dont need to worry about it.
wire irq_req_raw = (
//(|lcl_irq_r) // not support this now
(ext_irq_r & meie_r)
| (sft_irq_r & msie_r)
| (tmr_irq_r & mtie_r)
);
assign irq_req = (~irq_mask) & irq_req_raw;
assign wfi_irq_req = (~wfi_irq_mask) & irq_req_raw;
assign irq_req_active = wfi_flag_r ? wfi_irq_req : irq_req;
wire [`E203_XLEN-1:0] irq_cause;
assign irq_cause[31] = 1'b1;
assign irq_cause[30:4] = 27'b0;
assign irq_cause[3:0] = (sft_irq_r & msie_r) ? 4'd3 : // 3 Machine software interrupt
(tmr_irq_r & mtie_r) ? 4'd7 : // 7 Machine timer interrupt
(ext_irq_r & meie_r) ? 4'd11 : // 11 Machine external interrupt
4'b0;
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The ALU triggered Exception
// The ebreak instruction will generated regular exception when the ebreakm
// bit of DCSR reg is not set
wire alu_excp_i_ebreak4excp = (alu_excp_i_ebreak & ((~dbg_ebreakm_r) | dbg_mode))
;
// The ebreak instruction will enter into the debug-mode when the ebreakm
// bit of DCSR reg is set
wire alu_excp_i_ebreak4dbg = alu_excp_i_ebreak
& (~alu_need_flush)// override by other alu exceptions
& dbg_ebreakm_r
& (~dbg_mode);//Not in debug mode
assign alu_ebreakm_flush_req = alu_excp_i_valid & alu_excp_i_ebreak4dbg;
assign alu_ebreakm_flush_req_novld = alu_excp_i_ebreak4dbg;
`ifndef E203_SUPPORT_TRIGM//{
// We dont support the HW Trigger Module yet
assign alu_dbgtrig_flush_req_novld = 1'b0;
assign alu_dbgtrig_flush_req = 1'b0;
`endif
assign alu_need_flush =
( alu_excp_i_misalgn
| alu_excp_i_buserr
| alu_excp_i_ebreak4excp
| alu_excp_i_ecall
| alu_excp_i_ifu_misalgn
| alu_excp_i_ifu_buserr
| alu_excp_i_ifu_ilegl
);
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// Update the CSRs (Mcause, .etc)
wire longp_excp_flush_req_ld = longp_excp_flush_req & longp_excp_i_ld;
wire longp_excp_flush_req_st = longp_excp_flush_req & longp_excp_i_st;
wire longp_excp_flush_req_insterr = longp_excp_flush_req & longp_excp_i_insterr;
wire alu_excp_flush_req_ld = alu_excp_flush_req & alu_excp_i_ld;
wire alu_excp_flush_req_stamo = alu_excp_flush_req & alu_excp_i_stamo;
wire alu_excp_flush_req_ebreak = (alu_excp_flush_req & alu_excp_i_ebreak4excp);
wire alu_excp_flush_req_ecall = (alu_excp_flush_req & alu_excp_i_ecall);
wire alu_excp_flush_req_ifu_misalgn = (alu_excp_flush_req & alu_excp_i_ifu_misalgn);
wire alu_excp_flush_req_ifu_buserr = (alu_excp_flush_req & alu_excp_i_ifu_buserr);
wire alu_excp_flush_req_ifu_ilegl = (alu_excp_flush_req & alu_excp_i_ifu_ilegl);
wire alu_excp_flush_req_ld_misalgn = (alu_excp_flush_req_ld & alu_excp_i_misalgn);// ALU load misalign
wire alu_excp_flush_req_ld_buserr = (alu_excp_flush_req_ld & alu_excp_i_buserr);// ALU load bus error
wire alu_excp_flush_req_stamo_misalgn = (alu_excp_flush_req_stamo & alu_excp_i_misalgn);// ALU store/AMO misalign
wire alu_excp_flush_req_stamo_buserr = (alu_excp_flush_req_stamo & alu_excp_i_buserr);// ALU store/AMO bus error
wire longp_excp_flush_req_ld_buserr = (longp_excp_flush_req_ld & longp_excp_i_buserr);// Longpipe load bus error
wire longp_excp_flush_req_st_buserr = (longp_excp_flush_req_st & longp_excp_i_buserr);// Longpipe store bus error
wire excp_flush_by_alu_agu =
alu_excp_flush_req_ld_misalgn
| alu_excp_flush_req_ld_buserr
| alu_excp_flush_req_stamo_misalgn
| alu_excp_flush_req_stamo_buserr;
wire excp_flush_by_longp_ldst =
longp_excp_flush_req_ld_buserr
| longp_excp_flush_req_st_buserr;
wire [`E203_XLEN-1:0] excp_cause;
assign excp_cause[31:5] = 27'b0;
assign excp_cause[4:0] =
alu_excp_flush_req_ifu_misalgn? 5'd0 //Instruction address misaligned
: alu_excp_flush_req_ifu_buserr ? 5'd1 //Instruction access fault
: alu_excp_flush_req_ifu_ilegl ? 5'd2 //Illegal instruction
: alu_excp_flush_req_ebreak ? 5'd3 //Breakpoint
: alu_excp_flush_req_ld_misalgn ? 5'd4 //load address misalign
: (longp_excp_flush_req_ld_buserr | alu_excp_flush_req_ld_buserr) ? 5'd5 //load access fault
: alu_excp_flush_req_stamo_misalgn ? 5'd6 //Store/AMO address misalign
: (longp_excp_flush_req_st_buserr | alu_excp_flush_req_stamo_buserr) ? 5'd7 //Store/AMO access fault
: (alu_excp_flush_req_ecall & u_mode) ? 5'd8 //Environment call from U-mode
: (alu_excp_flush_req_ecall & s_mode) ? 5'd9 //Environment call from S-mode
: (alu_excp_flush_req_ecall & h_mode) ? 5'd10 //Environment call from H-mode
: (alu_excp_flush_req_ecall & m_mode) ? 5'd11 //Environment call from M-mode
: longp_excp_flush_req_insterr ? 5'd16// This only happened for the EAI long instructions actually
: 5'h1F;//Otherwise a reserved value
// mbadaddr is an XLEN-bit read-write register formatted as shown in Figure 3.21. When
// * a hardware breakpoint is triggered,
// * an instruction-fetch address-misaligned or access exception
// * load address-misaligned or access exception
// * store address-misaligned or access exception
// occurs, mbadaddr is written with the faulting address.
// In Priv SPEC v1.10, the mbadaddr have been replaced to mtval, and added following points:
// * On an illegal instruction trap, mtval is written with the first XLEN bits of the faulting
// instruction .
// * For other exceptions, mtval is set to zero, but a future standard may redefine mtval's
// setting for other exceptions.
//
wire excp_flush_req_ld_misalgn = alu_excp_flush_req_ld_misalgn;
wire excp_flush_req_ld_buserr = alu_excp_flush_req_ld_buserr | longp_excp_flush_req_ld_buserr;
//wire cmt_badaddr_update = all_excp_flush_req &
// (
// alu_excp_flush_req_ebreak
// | alu_excp_flush_req_ifu_misalgn
// | alu_excp_flush_req_ifu_buserr
// | excp_flush_by_alu_agu
// | excp_flush_by_longp_ldst);
// Per Priv Spec v1.10, all trap need to update this register
// * When a trap is taken into M-mode, mtval is written with exception-specific
// information to assist software in handling the trap.
wire cmt_badaddr_update = excpirq_flush_req;
assign cmt_badaddr = excp_flush_by_longp_ldst ? longp_excp_i_badaddr :
excp_flush_by_alu_agu ? alu_excp_i_badaddr :
(alu_excp_flush_req_ebreak
| alu_excp_flush_req_ifu_misalgn
| alu_excp_flush_req_ifu_buserr) ? alu_excp_i_pc :
alu_excp_flush_req_ifu_ilegl ? alu_excp_i_instr :
`E203_ADDR_SIZE'b0;
// We use the exact PC of long-instruction when exception happened, but
// to note since the later instruction may already commited, so long-pipe
// excpetion is async-imprecise exceptions
assign cmt_epc = longp_excp_i_valid ? longp_excp_i_pc : alu_excp_i_pc;
assign cmt_cause = excp_taken_ena ? excp_cause : irq_cause;
// Any trap include exception and irq (exclude dbg_irq) will update mstatus register
// In the debug mode, epc/cause/status/badaddr will not update badaddr
assign cmt_epc_ena = (~dbg_mode) & (excp_taken_ena | irq_taken_ena);
assign cmt_cause_ena = cmt_epc_ena;
assign cmt_status_ena = cmt_epc_ena;
assign cmt_badaddr_ena = cmt_epc_ena & cmt_badaddr_update;
assign cmt_dpc = alu_excp_i_pc;// The ALU PC is the current next commiting PC (not yet commited)
assign cmt_dpc_ena = dbg_entry_taken_ena;
wire cmt_dcause_set = dbg_entry_taken_ena;
wire cmt_dcause_clr = cmt_dret_ena;
wire [2:0] set_dcause_nxt =
dbg_trig_req ? 3'd2 :
dbg_ebrk_req ? 3'd1 :
dbg_irq_req ? 3'd3 :
dbg_step_req ? 3'd4 :
dbg_halt_req ? 3'd5 :
3'd0;
assign cmt_dcause_ena = cmt_dcause_set | cmt_dcause_clr;
assign cmt_dcause = cmt_dcause_set ? set_dcause_nxt : 3'd0;
endmodule
|
/*
* Test Bench of the baseband processor
*
* This module is an example of the communication between a Reader and a single Tag
*
* Procedure : Select -> Inventory -> Access
* refer to annex E
*
* Define your SDF file
* if you want to simulate the ideal module, comment out the line 15 and 57 - 59
*/
`timescale 1us / 1ns
`define SDF_FILE = "./bb_proc.sdf"
module bb_proc_tb;
// --- input ---
reg clk_200K;
reg pie_code;
reg clk_dpie;
reg rst;
// --- output ---
wire bs_data;
wire package_complete;
wire crc_check_pass;
// --- variable ---
reg [59:0]data_i;
reg [59:0]data_j;
integer i;
integer j;
parameter half_of_tari = 3.125; // Tari = 6.25 us in this Tag design
parameter gclk_T = 5; // frequency of global clock signal generated by multivibrator = 200 KHz
bb_proc uut
(
.bs_data(bs_data),
.package_complete(package_complete),
.crc_check_pass(crc_check_pass),
.clk_200K(clk_200K),
.pie_code(pie_code),
.clk_dpie(clk_dpie),
.rst(rst)
);
initial begin
$sdf_annotate(`SDF_FILE);
end
// --- clock signal in 200 KHz generated by multivibrator ---
initial begin
clk_200K = 1'b0;
#(100 + 12.5 + 6.25 + half_of_tari);
clk_200K = 1'b1;
while(1) #(gclk_T / 2.0) clk_200K = ~clk_200K;
end
// --- PIE code ---
initial begin
pie_code = 1'b1;
#100;
frame_sync_pie;
// Select command
// 1010_100_100_01_00011011_00001011_01110001110_1_1011101100000001
data_i = 56'b1010_100_100_01_00011011_00001011_01110001110_1_1011101100000001;
for(i=56; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#100;
frame_sync_pie;
// Query command
// 1000_0_01_1_10_01_0_0011_01000
data_i = 22'b1000_0_01_1_10_01_0_0011_01000;
for(i=22; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#100;
frame_sync_pie;
// QueryAdjust command
// 1001_01_011
data_i = 9'b1001_01_011;
for(i=9; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#100;
frame_sync_pie;
// QueryRep command
// 00_01
data_i = 4'b00_01;
for(i=4; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#100;
frame_sync_pie;
// QueryRep command
// 00_01
data_i = 4'b00_01;
for(i=4; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
/*
#2100;
frame_sync_pie;
// NAK command
// 11000000
data_i = 8'b11000000;
for(i=8; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
*/
#2100;
frame_sync_pie;
// ACK command
// 01_0000010111111100
data_i = 18'b01_0000010111111100;
for(i=18; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#3300;
frame_sync_pie;
// Req_RN command
// 11000001_0000010111111100_1111001111000010
data_i = 40'b11000001_0000010111111100_1111001111000010;
for(i=40; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#3000;
frame_sync_pie;
// Read command
// 11000010_00_00000000_00000010_0000101111111000_1010101110001111
data_i = 58'b11000010_00_00000000_00000010_0000101111111000_1010101110001111;
for(i=58; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#5000;
frame_sync_pie;
// Lock command
// 11000101_11000000001100000000_0000101111111000_0100001111010101
data_i = 60'b11000101_11000000001100000000_0000101111111000_0100001111010101;
for(i=60; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#3000;
frame_sync_pie;
// Read command
// 11000010_00_00000000_00000010_0000101111111000_1010101110001111
data_i = 58'b11000010_00_00000000_00000010_0000101111111000_1010101110001111;
for(i=58; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
// Kill procedure
// begin in the Open or Secured state
// Req_RN -> Kill -> Req_RN -> Kill
#2500;
frame_sync_pie;
// Req_RN command
// 11000001_0000101111111000_1001000001001001
data_i = 40'b11000001_0000101111111000_1001000001001001;
for(i=40; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#3000;
frame_sync_pie;
// Kill command
// 11000100_1100010010100111_000_0000101111111000_0110101010101101
data_i = 59'b11000100_1100010010100111_000_0000101111111000_0110101010101101;
for(i=59; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#3000;
frame_sync_pie;
// Req_RN command
// 11000001_0000101111111000_1001000001001001
data_i = 40'b11000001_0000101111111000_1001000001001001;
for(i=40; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
#3000;
frame_sync_pie;
// Kill command
// 11000100_0010100100101100_000_0000101111111000_1110110011110110
data_i = 59'b11000100_0010100100101100_000_0000101111111000_1110110011110110;
for(i=59; i!=0; i=i-1) begin
if(data_i[i-1]) pie_1;
else pie_0;
end
end
// --- Delayed PIE code ---
initial begin
clk_dpie = 1;
#(100 + half_of_tari + 1);
frame_sync_dpie;
data_j = 56'b1010_100_100_01_00011011_00001011_01110001110_1_1011101100000001;
for(j=56; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#100;
frame_sync_dpie;
data_j = 22'b1000_0_01_1_10_01_0_0011_01000;
for(j=22; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#100;
frame_sync_dpie;
data_j = 9'b1001_01_011;
for(j=9; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#100;
frame_sync_dpie;
data_j = 4'b00_01;
for(j=4; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#100;
frame_sync_dpie;
data_j = 4'b00_01;
for(j=4; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
/*
#2100;
frame_sync_dpie;
data_j = 8'b11000000;
for(j=8; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
*/
#2100;
frame_sync_dpie;
data_j = 18'b01_0000010111111100;
for(j=18; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#3300;
frame_sync_dpie;
data_j = 40'b11000001_0000010111111100_1111001111000010;
for(j=40; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#3000;
frame_sync_dpie;
data_j = 58'b11000010_00_00000000_00000010_0000101111111000_1010101110001111;
for(j=58; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#5000;
frame_sync_dpie;
data_j = 60'b11000101_11000000001100000000_0000101111111000_0100001111010101;
for(j=60; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#3000;
frame_sync_dpie;
data_j = 58'b11000010_00_00000000_00000010_0000101111111000_1010101110001111;
for(j=58; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#2500;
frame_sync_dpie;
data_j = 40'b11000001_0000101111111000_1001000001001001;
for(j=40; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#3000;
frame_sync_dpie;
data_j = 59'b11000100_1100010010100111_000_0000101111111000_0110101010101101;
for(j=59; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#3000;
frame_sync_dpie;
data_j = 40'b11000001_0000101111111000_1001000001001001;
for(j=40; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#3000;
frame_sync_dpie;
data_j = 59'b11000100_0010100100101100_000_0000101111111000_1110110011110110;
for(j=59; j!=0; j=j-1) begin
if(data_j[j-1]) dpie_1;
else dpie_0;
end
#3000 $finish;
end
// --- reset signal generated by POR ---
initial begin
rst = 1'b0;
#10 rst = 1'b1;
#3 rst = 1'b0;
end
initial begin
$fsdbDumpfile("bb_proc.fsdb");
$fsdbDumpvars;
// $dumpfile("bb_proc.fsdb");
// $dumpvars;
end
// ----------------------------------------------
// task
// ----------------------------------------------
// --- Frame-Sync ---
task frame_sync_pie;
begin
pie_code = 1'b0;
#12.5 pie_code = 1'b1;
#half_of_tari pie_code = 1'b0;
#half_of_tari pie_code = 1'b1;
#(5 * half_of_tari) pie_code = 1'b0;
#half_of_tari pie_code = 1'b1;
end
endtask
task frame_sync_dpie;
begin
clk_dpie = 1'b0;
#12.5 clk_dpie = 1'b1;
#half_of_tari clk_dpie = 1'b0;
#half_of_tari clk_dpie = 1'b1;
#(5 * half_of_tari) clk_dpie = 1'b0;
#half_of_tari clk_dpie = 1'b1;
end
endtask
// --- PIE symbol 0 ---
task pie_0;
begin
#half_of_tari pie_code = 1'b0;
#half_of_tari pie_code = 1'b1;
end
endtask
task dpie_0;
begin
#half_of_tari clk_dpie = 1'b0;
#half_of_tari clk_dpie = 1'b1;
end
endtask
// --- PIE symbol 1 ---
task pie_1;
begin
#(3 * half_of_tari) pie_code = 1'b0;
#half_of_tari pie_code = 1'b1;
end
endtask
task dpie_1;
begin
#(3 * half_of_tari) clk_dpie = 1'b0;
#half_of_tari clk_dpie = 1'b1;
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DLXBN_PP_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_PP_SYMBOL_V
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Receive-only UART
// IDLE state -- rxd high
// READING state -- clocking in bits
// STOP_BIT state -- waiting for stop bit, then sending the data out rx_data
module uart_rx(
input wire clock, // main clock
input wire rxd, // rxd pin
output reg [7:0] rx_data, // received data output register
output reg rx_full = 1'b0, // '1' when rx_data is valid
input wire ack // pulse '1' to ack rx_data and allow a new byte
);
// clock divider to get baud rate x 4. 82M / 115.2k / 4 = 178, giving 115.169 kb/s
parameter divide_count = 178;
reg [9:0] divider = 0; // 0-1023
// state machine
parameter IDLE = 0, READING = 1, STOP_BIT = 2;
reg [1:0] state = 0;
// input shift register
reg [7:0] shifter;
// how many bits to shift (0-7)
reg [2:0] shift_count;
// sync external rxd signal
reg [2:0] rxd_sync;
// timer to sample the bit right in the center (0-7)
reg [2:0] bit_timer;
always @(posedge clock) begin
if (ack == 1'b1) begin
rx_full <= 1'b0;
end
rxd_sync <= {rxd_sync[1:0], rxd};
// divider divides clock down to the serial bit rate (x 4 for reception)
if (state == IDLE) begin
// hold divider
divider = 3;
// look for a falling edge on rxd
if (rxd_sync[2] == 0) begin
bit_timer <= 3'd5;
state <= READING;
shift_count <= 7;
end
end else begin // READING or STOP_BIT state
if (divider != divide_count) begin
divider <= divider + 10'd1;
end else begin
// divider just hit its target -- reset it
divider <= 1;
if (bit_timer != 0) begin
bit_timer <= bit_timer - 3'd1;
end else begin
// it's time to sample a bit on divider + bit_timer expiry
// uart is little-endian, so we shift in from the left.
if (state == STOP_BIT) begin
if (rxd_sync[2] == 1'b1) begin
rx_full <= 1'b1;
rx_data <= shifter;
end;
state <= IDLE;
end else begin
shifter <= {rxd_sync[2], shifter[7:1]};
if (shift_count == 0) begin
state <= STOP_BIT;
end else begin
shift_count <= shift_count - 3'd1;
end
end
bit_timer <= 3;
end
end
if (divider == 0) begin
end
end
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
// Date : Fri Sep 22 17:41:20 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clka,
rsta,
ena,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
web,
addrb,
dinb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) input rsta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [3:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [31:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [31:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) input rstb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) input enb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) input [3:0]web;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [31:0]addrb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) input [31:0]dinb;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [31:0]doutb;
wire [31:0]addra;
wire [31:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [31:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "32" *)
(* C_ADDRB_WIDTH = "32" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "2" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "1" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 10.7492 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "1" *)
(* C_HAS_RSTB = "1" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "NONE" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2048" *)
(* C_READ_DEPTH_B = "2048" *)
(* C_READ_WIDTH_A = "32" *)
(* C_READ_WIDTH_B = "32" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "1" *)
(* C_USE_BYTE_WEA = "1" *)
(* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "4" *)
(* C_WEB_WIDTH = "4" *)
(* C_WRITE_DEPTH_A = "2048" *)
(* C_WRITE_DEPTH_B = "2048" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "32" *)
(* C_WRITE_WIDTH_B = "32" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.eccpipece(1'b0),
.ena(ena),
.enb(enb),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[31:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(rsta),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(rstb),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[31:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(web));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[15:0]),
.dinb(dinb[15:0]),
.douta(douta[15:0]),
.doutb(doutb[15:0]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[1:0]),
.web(web[1:0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina[31:16]),
.dinb(dinb[31:16]),
.douta(douta[31:16]),
.doutb(doutb[31:16]),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea[3:2]),
.web(web[3:2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
input [15:0]dinb;
input [1:0]wea;
input [1:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [1:0]wea;
wire [1:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
input [15:0]dinb;
input [1:0]wea;
input [1:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [1:0]wea;
wire [1:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
input [15:0]dinb;
input [1:0]wea;
input [1:0]web;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92 ;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [1:0]wea;
wire [1:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[15:0][0:2047]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
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.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:16],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:16],doutb}),
.DOPADOP({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87 ,\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88 }),
.DOPBDOP({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:2],\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91 ,\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [15:0]douta;
output [15:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
input [15:0]dinb;
input [1:0]wea;
input [1:0]web;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91 ;
wire \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92 ;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]douta;
wire [15:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [1:0]wea;
wire [1:0]web;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED ;
(* bmm_info_memory_device = "[31:16][0:2047]" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dinb}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED [31:16],douta}),
.DOBDO({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED [31:16],doutb}),
.DOPADOP({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_87 ,\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_88 }),
.DOPBDOP({\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED [3:2],\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_91 ,\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(enb),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(rsta),
.RSTRAMB(rstb),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,web,web}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
(* C_ADDRA_WIDTH = "32" *) (* C_ADDRB_WIDTH = "32" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "8" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "2" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "1" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 10.7492 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "1" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "1" *)
(* C_HAS_RSTB = "1" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "NONE" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "2" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2048" *) (* C_READ_DEPTH_B = "2048" *) (* C_READ_WIDTH_A = "32" *)
(* C_READ_WIDTH_B = "32" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "1" *) (* C_USE_BYTE_WEA = "1" *) (* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "4" *) (* C_WEB_WIDTH = "4" *)
(* C_WRITE_DEPTH_A = "2048" *) (* C_WRITE_DEPTH_B = "2048" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *)
(* C_XDEVICEFAMILY = "zynq" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [31:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [31:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [31:0]addra;
wire [31:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
assign dbiterr = \<const0> ;
assign rdaddrecc[31] = \<const0> ;
assign rdaddrecc[30] = \<const0> ;
assign rdaddrecc[29] = \<const0> ;
assign rdaddrecc[28] = \<const0> ;
assign rdaddrecc[27] = \<const0> ;
assign rdaddrecc[26] = \<const0> ;
assign rdaddrecc[25] = \<const0> ;
assign rdaddrecc[24] = \<const0> ;
assign rdaddrecc[23] = \<const0> ;
assign rdaddrecc[22] = \<const0> ;
assign rdaddrecc[21] = \<const0> ;
assign rdaddrecc[20] = \<const0> ;
assign rdaddrecc[19] = \<const0> ;
assign rdaddrecc[18] = \<const0> ;
assign rdaddrecc[17] = \<const0> ;
assign rdaddrecc[16] = \<const0> ;
assign rdaddrecc[15] = \<const0> ;
assign rdaddrecc[14] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[31] = \<const0> ;
assign s_axi_rdaddrecc[30] = \<const0> ;
assign s_axi_rdaddrecc[29] = \<const0> ;
assign s_axi_rdaddrecc[28] = \<const0> ;
assign s_axi_rdaddrecc[27] = \<const0> ;
assign s_axi_rdaddrecc[26] = \<const0> ;
assign s_axi_rdaddrecc[25] = \<const0> ;
assign s_axi_rdaddrecc[24] = \<const0> ;
assign s_axi_rdaddrecc[23] = \<const0> ;
assign s_axi_rdaddrecc[22] = \<const0> ;
assign s_axi_rdaddrecc[21] = \<const0> ;
assign s_axi_rdaddrecc[20] = \<const0> ;
assign s_axi_rdaddrecc[19] = \<const0> ;
assign s_axi_rdaddrecc[18] = \<const0> ;
assign s_axi_rdaddrecc[17] = \<const0> ;
assign s_axi_rdaddrecc[16] = \<const0> ;
assign s_axi_rdaddrecc[15] = \<const0> ;
assign s_axi_rdaddrecc[14] = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth inst_blk_mem_gen
(.addra(addra[12:2]),
.addrb(addrb[12:2]),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_6_synth
(douta,
doutb,
clka,
clkb,
ena,
enb,
rsta,
rstb,
addra,
addrb,
dina,
dinb,
wea,
web);
output [31:0]douta;
output [31:0]doutb;
input clka;
input clkb;
input ena;
input enb;
input rsta;
input rstb;
input [10:0]addra;
input [10:0]addrb;
input [31:0]dina;
input [31:0]dinb;
input [3:0]wea;
input [3:0]web;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [31:0]dina;
wire [31:0]dinb;
wire [31:0]douta;
wire [31:0]doutb;
wire ena;
wire enb;
wire rsta;
wire rstb;
wire [3:0]wea;
wire [3:0]web;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.dinb(dinb),
.douta(douta),
.doutb(doutb),
.ena(ena),
.enb(enb),
.rsta(rsta),
.rstb(rstb),
.wea(wea),
.web(web));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_system_onchip_memory2_0.hex";
output [ 63: 0] readdata;
input [ 12: 0] address;
input [ 7: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 63: 0] writedata;
wire clocken0;
wire [ 63: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 64,
the_altsyncram.width_byteena_a = 8,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, CrYCb to RGB conversion
// The multiplication coefficients are in 1.4.12 format
// The addition coefficients are in 1.12.12 format
// R = (+408.583/256)*Cr + (+298.082/256)*Y + ( 000.000/256)*Cb + (-222.921);
// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
module ad_csc_CrYCb2RGB (
// Cr-Y-Cb inputs
clk,
CrYCb_sync,
CrYCb_data,
// R-G-B outputs
RGB_sync,
RGB_data);
// parameters
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// Cr-Y-Cb inputs
input clk;
input [DW:0] CrYCb_sync;
input [23:0] CrYCb_data;
// R-G-B outputs
output [DW:0] RGB_sync;
output [23:0] RGB_data;
// red
ad_csc_1 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_csc_1_R (
.clk (clk),
.sync (CrYCb_sync),
.data (CrYCb_data),
.C1 (17'h01989),
.C2 (17'h012a1),
.C3 (17'h00000),
.C4 (25'h10deebc),
.csc_sync_1 (RGB_sync),
.csc_data_1 (RGB_data[23:16]));
// green
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_G (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (17'h10d01),
.C2 (17'h012a1),
.C3 (17'h10644),
.C4 (25'h0087937),
.csc_sync_1 (),
.csc_data_1 (RGB_data[15:8]));
// blue
ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_B (
.clk (clk),
.sync (1'd0),
.data (CrYCb_data),
.C1 (17'h00000),
.C2 (17'h012a1),
.C3 (17'h02046),
.C4 (25'h1114d60),
.csc_sync_1 (),
.csc_data_1 (RGB_data[7:0]));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd3 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD3_FUNCTIONAL_PP_V
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
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// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={16} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1600.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.034, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.03, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.082, PCW_UIPARAM_DDR_BOARD_DELAY0=0.176, PCW_UIPARAM_DDR_BOARD_DELAY1=0.159, PCW_UIPARAM_DDR_BOARD_DELAY2=0.162, PCW_UIPARAM_DDR_BOARD_DELAY3=0.187, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50.000000, PCW_APU_PERIPHERAL_FREQMHZ=650, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=32, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1600.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 46, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "design_SWandHW_standalone_v2_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
wire S_AXI_GP0_ARESETN_shim;
wire S_AXI_GP0_ARREADY_shim;
wire S_AXI_GP0_AWREADY_shim;
wire S_AXI_GP0_BVALID_shim;
wire S_AXI_GP0_RLAST_shim;
wire S_AXI_GP0_RVALID_shim;
wire S_AXI_GP0_WREADY_shim;
wire [1:0] S_AXI_GP0_BRESP_shim;
wire [1:0] S_AXI_GP0_RRESP_shim;
wire [31:0] S_AXI_GP0_RDATA_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID_out_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID_out_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID_shim;
wire S_AXI_GP0_ACLK_shim;
wire S_AXI_GP0_ARVALID_shim;
wire S_AXI_GP0_AWVALID_shim;
wire S_AXI_GP0_BREADY_shim;
wire S_AXI_GP0_RREADY_shim;
wire S_AXI_GP0_WLAST_shim;
wire S_AXI_GP0_WVALID_shim;
wire [1:0] S_AXI_GP0_ARBURST_shim;
wire [1:0] S_AXI_GP0_ARLOCK_shim;
wire [2:0] S_AXI_GP0_ARSIZE_shim;
wire [1:0] S_AXI_GP0_AWBURST_shim;
wire [1:0] S_AXI_GP0_AWLOCK_shim;
wire [2:0] S_AXI_GP0_AWSIZE_shim;
wire [2:0] S_AXI_GP0_ARPROT_shim;
wire [2:0] S_AXI_GP0_AWPROT_shim;
wire [31:0] S_AXI_GP0_ARADDR_shim;
wire [31:0] S_AXI_GP0_AWADDR_shim;
wire [31:0] S_AXI_GP0_WDATA_shim;
wire [3:0] S_AXI_GP0_ARCACHE_shim;
wire [3:0] S_AXI_GP0_ARLEN_shim;
wire [3:0] S_AXI_GP0_ARQOS_shim;
wire [3:0] S_AXI_GP0_AWCACHE_shim;
wire [3:0] S_AXI_GP0_AWLEN_shim;
wire [3:0] S_AXI_GP0_AWQOS_shim;
wire [3:0] S_AXI_GP0_WSTRB_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID_in_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID_in_shim;
wire [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID_in_shim;
xlnx_axi_wrshim_unwrap #
(
.ID_WIDTH(C_S_AXI_GP0_ID_WIDTH),
.D_WIDTH(32)
)xlnx_axi_wrshim_unwrap_inst_gp0
(
.clk(S_AXI_GP0_ACLK_temp),
.rst_n(S_AXI_GP0_ARESETN),
.awqos_in(S_AXI_GP0_AWQOS),
.awid_in(S_AXI_GP0_AWID_in),
.awaddr_in(S_AXI_GP0_AWADDR),
.awlen_in(S_AXI_GP0_AWLEN),
.awsize_in(S_AXI_GP0_AWSIZE),
.awburst_in(S_AXI_GP0_AWBURST),
.awlock_in(S_AXI_GP0_AWLOCK),
.awcache_in(S_AXI_GP0_AWCACHE),
.awprot_in(S_AXI_GP0_AWPROT),
.awvalid_in(S_AXI_GP0_AWVALID),
.wdata_in(S_AXI_GP0_WDATA),
.wid_in(S_AXI_GP0_WID_in),
.wstrb_in(S_AXI_GP0_WSTRB),
.wlast_in(S_AXI_GP0_WLAST),
.wvalid_in(S_AXI_GP0_WVALID),
.bready_in(S_AXI_GP0_BREADY),
.arqos_in(S_AXI_GP0_ARQOS),
.arid_in(S_AXI_GP0_ARID_in),
.araddr_in(S_AXI_GP0_ARADDR),
.arlen_in(S_AXI_GP0_ARLEN),
.arsize_in(S_AXI_GP0_ARSIZE),
.arburst_in(S_AXI_GP0_ARBURST),
.arlock_in(S_AXI_GP0_ARLOCK),
.arcache_in(S_AXI_GP0_ARCACHE),
.arprot_in(S_AXI_GP0_ARPROT),
.arvalid_in(S_AXI_GP0_ARVALID),
.rready_in(S_AXI_GP0_RREADY),
.awready_in(S_AXI_GP0_AWREADY),
.arready_in(S_AXI_GP0_ARREADY),
.rid_in(S_AXI_GP0_RID),
.rdata_in(S_AXI_GP0_RDATA),
.rresp_in(S_AXI_GP0_RRESP),
.rlast_in(S_AXI_GP0_RLAST),
.rvalid_in(S_AXI_GP0_RVALID),
.wready_in(S_AXI_GP0_WREADY),
.bid_in(S_AXI_GP0_BID),
.bresp_in(S_AXI_GP0_BRESP),
.bvalid_in(S_AXI_GP0_BVALID),
.awqos_out(S_AXI_GP0_AWQOS_shim),
.awid_out(S_AXI_GP0_AWID_in_shim),
.awaddr_out(S_AXI_GP0_AWADDR_shim),
.awlen_out(S_AXI_GP0_AWLEN_shim),
.awsize_out(S_AXI_GP0_AWSIZE_shim),
.awburst_out(S_AXI_GP0_AWBURST_shim),
.awlock_out(S_AXI_GP0_AWLOCK_shim),
.awcache_out(S_AXI_GP0_AWCACHE_shim),
.awprot_out(S_AXI_GP0_AWPROT_shim),
.awvalid_out(S_AXI_GP0_AWVALID_shim),
.wdata_out(S_AXI_GP0_WDATA_shim),
.wid_out(S_AXI_GP0_WID_in_shim),
.wstrb_out(S_AXI_GP0_WSTRB_shim),
.wlast_out(S_AXI_GP0_WLAST_shim),
.wvalid_out(S_AXI_GP0_WVALID_shim),
.bready_out(S_AXI_GP0_BREADY_shim),
.arqos_out(S_AXI_GP0_ARQOS_shim),
.arid_out(S_AXI_GP0_ARID_in_shim),
.araddr_out(S_AXI_GP0_ARADDR_shim),
.arlen_out(S_AXI_GP0_ARLEN_shim),
.arsize_out(S_AXI_GP0_ARSIZE_shim),
.arburst_out(S_AXI_GP0_ARBURST_shim),
.arlock_out(S_AXI_GP0_ARLOCK_shim),
.arcache_out(S_AXI_GP0_ARCACHE_shim),
.arprot_out(S_AXI_GP0_ARPROT_shim),
.arvalid_out(S_AXI_GP0_ARVALID_shim),
.rready_out(S_AXI_GP0_RREADY_shim),
.awready_out(S_AXI_GP0_AWREADY_shim),
.arready_out(S_AXI_GP0_ARREADY_shim),
.rid_out(S_AXI_GP0_RID_shim),
.rdata_out(S_AXI_GP0_RDATA_shim),
.rresp_out(S_AXI_GP0_RRESP_shim),
.rlast_out(S_AXI_GP0_RLAST_shim),
.rvalid_out(S_AXI_GP0_RVALID_shim),
.wready_out(S_AXI_GP0_WREADY_shim),
.bid_out(S_AXI_GP0_BID_shim),
.bresp_out(S_AXI_GP0_BRESP_shim),
.bvalid_out(S_AXI_GP0_BVALID_shim));
wire S_AXI_GP1_ARESETN_shim;
wire S_AXI_GP1_ARREADY_shim;
wire S_AXI_GP1_AWREADY_shim;
wire S_AXI_GP1_BVALID_shim;
wire S_AXI_GP1_RLAST_shim;
wire S_AXI_GP1_RVALID_shim;
wire S_AXI_GP1_WREADY_shim;
wire [1:0] S_AXI_GP1_BRESP_shim;
wire [1:0] S_AXI_GP1_RRESP_shim;
wire [31:0] S_AXI_GP1_RDATA_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID_out_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID_out_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID_shim;
// -- Input
wire S_AXI_GP1_ACLK_shim;
wire S_AXI_GP1_ARVALID_shim;
wire S_AXI_GP1_AWVALID_shim;
wire S_AXI_GP1_BREADY_shim;
wire S_AXI_GP1_RREADY_shim;
wire S_AXI_GP1_WLAST_shim;
wire S_AXI_GP1_WVALID_shim;
wire [1:0] S_AXI_GP1_ARBURST_shim;
wire [1:0] S_AXI_GP1_ARLOCK_shim;
wire [2:0] S_AXI_GP1_ARSIZE_shim;
wire [1:0] S_AXI_GP1_AWBURST_shim;
wire [1:0] S_AXI_GP1_AWLOCK_shim;
wire [2:0] S_AXI_GP1_AWSIZE_shim;
wire [2:0] S_AXI_GP1_ARPROT_shim;
wire [2:0] S_AXI_GP1_AWPROT_shim;
wire [31:0] S_AXI_GP1_ARADDR_shim;
wire [31:0] S_AXI_GP1_AWADDR_shim;
wire [31:0] S_AXI_GP1_WDATA_shim;
wire [3:0] S_AXI_GP1_ARCACHE_shim;
wire [3:0] S_AXI_GP1_ARLEN_shim;
wire [3:0] S_AXI_GP1_ARQOS_shim;
wire [3:0] S_AXI_GP1_AWCACHE_shim;
wire [3:0] S_AXI_GP1_AWLEN_shim;
wire [3:0] S_AXI_GP1_AWQOS_shim;
wire [3:0] S_AXI_GP1_WSTRB_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID_in_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID_in_shim;
wire [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID_in_shim;
xlnx_axi_wrshim_unwrap #
(
.ID_WIDTH(C_S_AXI_GP1_ID_WIDTH),
.D_WIDTH(32)
)xlnx_axi_wrshim_unwrap_inst_gp1
(
.clk(S_AXI_GP1_ACLK_temp),
.rst_n(S_AXI_GP1_ARESETN),
.awqos_in(S_AXI_GP1_AWQOS),
.awid_in(S_AXI_GP1_AWID_in),
.awaddr_in(S_AXI_GP1_AWADDR),
.awlen_in(S_AXI_GP1_AWLEN),
.awsize_in(S_AXI_GP1_AWSIZE),
.awburst_in(S_AXI_GP1_AWBURST),
.awlock_in(S_AXI_GP1_AWLOCK),
.awcache_in(S_AXI_GP1_AWCACHE),
.awprot_in(S_AXI_GP1_AWPROT),
.awvalid_in(S_AXI_GP1_AWVALID),
.wdata_in(S_AXI_GP1_WDATA),
.wid_in(S_AXI_GP1_WID_in),
.wstrb_in(S_AXI_GP1_WSTRB),
.wlast_in(S_AXI_GP1_WLAST),
.wvalid_in(S_AXI_GP1_WVALID),
.bready_in(S_AXI_GP1_BREADY),
.arqos_in(S_AXI_GP1_ARQOS),
.arid_in(S_AXI_GP1_ARID_in),
.araddr_in(S_AXI_GP1_ARADDR),
.arlen_in(S_AXI_GP1_ARLEN),
.arsize_in(S_AXI_GP1_ARSIZE),
.arburst_in(S_AXI_GP1_ARBURST),
.arlock_in(S_AXI_GP1_ARLOCK),
.arcache_in(S_AXI_GP1_ARCACHE),
.arprot_in(S_AXI_GP1_ARPROT),
.arvalid_in(S_AXI_GP1_ARVALID),
.rready_in(S_AXI_GP1_RREADY),
.awready_in(S_AXI_GP1_AWREADY),
.arready_in(S_AXI_GP1_ARREADY),
.rid_in(S_AXI_GP1_RID),
.rdata_in(S_AXI_GP1_RDATA),
.rresp_in(S_AXI_GP1_RRESP),
.rlast_in(S_AXI_GP1_RLAST),
.rvalid_in(S_AXI_GP1_RVALID),
.wready_in(S_AXI_GP1_WREADY),
.bid_in(S_AXI_GP1_BID),
.bresp_in(S_AXI_GP1_BRESP),
.bvalid_in(S_AXI_GP1_BVALID),
.awqos_out(S_AXI_GP1_AWQOS_shim),
.awid_out(S_AXI_GP1_AWID_in_shim),
.awaddr_out(S_AXI_GP1_AWADDR_shim),
.awlen_out(S_AXI_GP1_AWLEN_shim),
.awsize_out(S_AXI_GP1_AWSIZE_shim),
.awburst_out(S_AXI_GP1_AWBURST_shim),
.awlock_out(S_AXI_GP1_AWLOCK_shim),
.awcache_out(S_AXI_GP1_AWCACHE_shim),
.awprot_out(S_AXI_GP1_AWPROT_shim),
.awvalid_out(S_AXI_GP1_AWVALID_shim),
.wdata_out(S_AXI_GP1_WDATA_shim),
.wid_out(S_AXI_GP1_WID_in_shim),
.wstrb_out(S_AXI_GP1_WSTRB_shim),
.wlast_out(S_AXI_GP1_WLAST_shim),
.wvalid_out(S_AXI_GP1_WVALID_shim),
.bready_out(S_AXI_GP1_BREADY_shim),
.arqos_out(S_AXI_GP1_ARQOS_shim),
.arid_out(S_AXI_GP1_ARID_in_shim),
.araddr_out(S_AXI_GP1_ARADDR_shim),
.arlen_out(S_AXI_GP1_ARLEN_shim),
.arsize_out(S_AXI_GP1_ARSIZE_shim),
.arburst_out(S_AXI_GP1_ARBURST_shim),
.arlock_out(S_AXI_GP1_ARLOCK_shim),
.arcache_out(S_AXI_GP1_ARCACHE_shim),
.arprot_out(S_AXI_GP1_ARPROT_shim),
.arvalid_out(S_AXI_GP1_ARVALID_shim),
.rready_out(S_AXI_GP1_RREADY_shim),
.awready_out(S_AXI_GP1_AWREADY_shim),
.arready_out(S_AXI_GP1_ARREADY_shim),
.rid_out(S_AXI_GP1_RID_shim),
.rdata_out(S_AXI_GP1_RDATA_shim),
.rresp_out(S_AXI_GP1_RRESP_shim),
.rlast_out(S_AXI_GP1_RLAST_shim),
.rvalid_out(S_AXI_GP1_RVALID_shim),
.wready_out(S_AXI_GP1_WREADY_shim),
.bid_out(S_AXI_GP1_BID_shim),
.bresp_out(S_AXI_GP1_BRESP_shim),
.bvalid_out(S_AXI_GP1_BVALID_shim));
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID_shim = id_out_gp0(S_AXI_GP0_BID_out_shim);
assign S_AXI_GP0_RID_shim = id_out_gp0(S_AXI_GP0_RID_out_shim);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID_shim = id_out_gp1(S_AXI_GP1_BID_out_shim);
assign S_AXI_GP1_RID_shim = id_out_gp1(S_AXI_GP1_RID_out_shim);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY_shim),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY_shim),
.SAXIGP0BID (S_AXI_GP0_BID_out_shim),
.SAXIGP0BRESP (S_AXI_GP0_BRESP_shim ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID_shim ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA_shim ),
.SAXIGP0RID (S_AXI_GP0_RID_out_shim ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST_shim ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP_shim ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID_shim ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY_shim ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY_shim),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY_shim),
.SAXIGP1BID (S_AXI_GP1_BID_out_shim ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP_shim ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID_shim ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA_shim ),
.SAXIGP1RID (S_AXI_GP1_RID_out_shim ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST_shim ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP_shim ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID_shim ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY_shim ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR_shim ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST_shim),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE_shim),
.SAXIGP0ARID (S_AXI_GP0_ARID_in_shim ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN_shim ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK_shim ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT_shim ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS_shim ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE_shim[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID_shim),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR_shim ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST_shim),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE_shim),
.SAXIGP0AWID (S_AXI_GP0_AWID_in_shim ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN_shim ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK_shim ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT_shim ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS_shim ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE_shim[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID_shim),
.SAXIGP0BREADY (S_AXI_GP0_BREADY_shim ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY_shim ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA_shim ),
.SAXIGP0WID (S_AXI_GP0_WID_in_shim ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST_shim ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB_shim ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID_shim ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR_shim ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST_shim),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE_shim),
.SAXIGP1ARID (S_AXI_GP1_ARID_in_shim ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN_shim ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK_shim ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT_shim ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS_shim ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE_shim[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID_shim),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR_shim ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST_shim),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE_shim),
.SAXIGP1AWID (S_AXI_GP1_AWID_in_shim ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN_shim ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK_shim ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT_shim ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS_shim ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE_shim[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID_shim),
.SAXIGP1BREADY (S_AXI_GP1_BREADY_shim ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY_shim ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA_shim ),
.SAXIGP1WID (S_AXI_GP1_WID_in_shim ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST_shim ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB_shim ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID_shim ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY_shim),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY_shim),
.SAXIGP0BID (S_AXI_GP0_BID_out_shim),
.SAXIGP0BRESP (S_AXI_GP0_BRESP_shim ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID_shim ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA_shim ),
.SAXIGP0RID (S_AXI_GP0_RID_out_shim ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST_shim ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP_shim ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID_shim ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY_shim ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY_shim),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY_shim),
.SAXIGP1BID (S_AXI_GP1_BID_out_shim ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP_shim ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID_shim ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA_shim ),
.SAXIGP1RID (S_AXI_GP1_RID_out_shim ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST_shim ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP_shim ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID_shim ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY_shim ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR_shim ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST_shim),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE_shim),
.SAXIGP0ARID (S_AXI_GP0_ARID_in_shim ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN_shim ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK_shim ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT_shim ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS_shim ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE_shim[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID_shim),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR_shim ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST_shim),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE_shim),
.SAXIGP0AWID (S_AXI_GP0_AWID_in_shim ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN_shim ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK_shim ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT_shim ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS_shim ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE_shim[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID_shim),
.SAXIGP0BREADY (S_AXI_GP0_BREADY_shim ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY_shim ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA_shim ),
.SAXIGP0WID (S_AXI_GP0_WID_in_shim ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST_shim ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB_shim ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID_shim ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR_shim ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST_shim),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE_shim),
.SAXIGP1ARID (S_AXI_GP1_ARID_in_shim ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN_shim ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK_shim ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT_shim ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS_shim ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE_shim[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID_shim),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR_shim ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST_shim),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE_shim),
.SAXIGP1AWID (S_AXI_GP1_AWID_in_shim ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN_shim ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK_shim ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT_shim ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS_shim ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE_shim[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID_shim),
.SAXIGP1BREADY (S_AXI_GP1_BREADY_shim ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY_shim ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA_shim ),
.SAXIGP1WID (S_AXI_GP1_WID_in_shim ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST_shim ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB_shim ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID_shim ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
/****************************************************************************
* Xilinx Confidential
* Copyright 2013 Xilinx, Inc. All rights reserved
*
* File: xlnx_axi_wrshim_unwrap.sv
* Owner: jmurray
* Initial Date: 22-May-2013
*
*
* Description:
* - Wr Shim to prevent PCIe lockup scenario
* - Should be inserted inline with any masters WrData and WrCmd AXI
* channels
* - Will not allow the wrCmd to be issued unless the first beat of
* the associated wrBurst is available
* - Likewise, will not allow the first beat of wrData to be issued
* unless the associated wrCmd is available
*
****************************************************************************/
module xlnx_axi_wrshim_unwrap #(
parameter ID_WIDTH = 6, // ID width
parameter AD_WIDTH = 32, // Address Width
parameter D_WIDTH = 64 // Data Width
)
(
//
//*********** MISC Signals *****************
//
input clk,
input rst_n,
//input apb_en_wrshim,
//
//*********** FUll AXI Interface Input (from Master) *****************
//
input[3:0] awqos_in,
input[ID_WIDTH-1:0] awid_in,
input[AD_WIDTH-1:0] awaddr_in,
input[3:0] awlen_in,
input[2:0] awsize_in,
input[1:0] awburst_in,
input[1:0] awlock_in,
input[3:0] awcache_in,
input[2:0] awprot_in,
input awvalid_in,
output awready_in,
input[D_WIDTH-1:0] wdata_in,
input[ID_WIDTH-1:0] wid_in,
input[D_WIDTH/8-1:0] wstrb_in,
input wlast_in,
input wvalid_in,
output wready_in,
output[ID_WIDTH-1:0] bid_in,
output[1:0] bresp_in,
output bvalid_in,
input bready_in,
input[3:0] arqos_in,
input[ID_WIDTH-1:0] arid_in,
input[AD_WIDTH-1:0] araddr_in,
input[3:0] arlen_in,
input[2:0] arsize_in,
input[1:0] arburst_in,
input[1:0] arlock_in,
input[3:0] arcache_in,
input[2:0] arprot_in,
input arvalid_in,
output arready_in,
output[ID_WIDTH-1:0] rid_in,
output[D_WIDTH-1:0] rdata_in,
output[1:0] rresp_in,
output rlast_in,
output rvalid_in,
input rready_in,
//
//*********** FUll AXI Interface Input (to Slave ) *****************
//
output[3:0] awqos_out,
output[ID_WIDTH-1:0] awid_out,
output[AD_WIDTH-1:0] awaddr_out,
output[3:0] awlen_out,
output[2:0] awsize_out,
output[1:0] awburst_out,
output[1:0] awlock_out,
output[3:0] awcache_out,
output[2:0] awprot_out,
output awvalid_out,
input awready_out,
output[D_WIDTH-1:0] wdata_out,
output[ID_WIDTH-1:0] wid_out,
output[D_WIDTH/8-1:0] wstrb_out,
output wlast_out,
output wvalid_out,
input wready_out,
input[ID_WIDTH-1:0] bid_out,
input[1:0] bresp_out,
input bvalid_out,
output bready_out,
output[3:0] arqos_out,
output[ID_WIDTH-1:0] arid_out,
output[AD_WIDTH-1:0] araddr_out,
output[3:0] arlen_out,
output[2:0] arsize_out,
output[1:0] arburst_out,
output[1:0] arlock_out,
output[3:0] arcache_out,
output[2:0] arprot_out,
output arvalid_out,
input arready_out,
input[ID_WIDTH-1:0] rid_out,
input[D_WIDTH-1:0] rdata_out,
input[1:0] rresp_out,
input rlast_out,
input rvalid_out,
output rready_out
);
/* ========================================================================== */
// Register and Wire Declarations
/* ========================================================================== */
wire wlast_consumed;
wire en_wrshim;
reg wlast_detect;
reg stall_awvalid;
reg store_first_beat;
reg previous_cmd_done;
reg burst_still_active;
reg [2:0] awsize_i;
reg [D_WIDTH-1:0] wdata_i;
reg [1:0] address_offset;
localparam AXI_WRSHIM_APB_SYNC_LEVELS = 2;
/* ========================================================================== */
// Code the Shim
/* ========================================================================== */
// Sync the APB enable signal for the shim
/*
xlnx_sync_bit #(AXI_WRSHIM_APB_SYNC_LEVELS, 0) axi_wrshim_en_sync (
.clk (clk),
.rst_n (rst_n),
.raw_input (apb_en_wrshim),
.sync_out (en_wrshim)
);
*/
wire axi_burst_length_is_zero= (awvalid_in && (awlen_in==0))?1'b1:1'b0;
wire zero_length_transfer=axi_burst_length_is_zero ;
//assign en_wrshim=zero_length_transfer;
assign en_wrshim=1'b1;
//
//*********** AXI signals Flow Throughs *****************
//
assign bid_in = bid_out;
assign bresp_in = bresp_out;
assign bvalid_in = bvalid_out;
assign arready_in = arready_out;
assign rid_in = rid_out;
assign rdata_in = rdata_out;
assign rresp_in = rresp_out;
assign rlast_in = rlast_out;
assign rvalid_in = rvalid_out;
assign awqos_out = awqos_in;
assign awid_out = awid_in;
assign awaddr_out[31:2] = awaddr_in[31:2];
assign awaddr_out[1:0] = (zero_length_transfer==1)?address_offset:awaddr_in[1:0];
assign awlen_out = awlen_in;
assign awsize_out = (zero_length_transfer==1)?awsize_i:awsize_in;
assign awburst_out = awburst_in;
assign awlock_out = awlock_in;
assign awcache_out = awcache_in;
assign awprot_out = awprot_in;
//assign wdata_out = (zero_length_transfer==1)?wdata_i:wdata_in;
assign wdata_out = wdata_in;
assign wid_out = wid_in;
assign wstrb_out = wstrb_in;
assign wlast_out = wlast_in;
assign bready_out = bready_in;
assign arqos_out = arqos_in;
assign arid_out = arid_in;
assign araddr_out = araddr_in;
assign arlen_out = arlen_in;
assign arsize_out = arsize_in;
assign arburst_out = arburst_in;
assign arlock_out = arlock_in;
assign arcache_out = arcache_in;
assign arprot_out = arprot_in;
assign arvalid_out = arvalid_in;
assign rready_out = rready_in;
// *****************************************************************
// ************************* WRITE COMMAND ****************************
// *****************************************************************
// Detect a Wlast. This is required since we cannot release the next AwCmd
// before we have seen a wlast from the previous WrBurst
always @(posedge clk )
if (!rst_n)
wlast_detect <= 1'b1;
else begin
if (wlast_consumed)
wlast_detect <= 1'b1;
else if (en_wrshim && wvalid_out && wready_out)
wlast_detect <= 1'b0;
end
// Detect the First WrData Beat of a wrBurst - only need to determine if
// it is available, NOT that it is consumed
wire first_beat_detect = wlast_detect && wvalid_in;
// Enable the Write Command to be issued
wire awcmd_en = en_wrshim ? ((first_beat_detect && !stall_awvalid) ||
store_first_beat) : 1'b1;
//assign awvalid_out = (zero_length_transfer==1)?awvalid_in && awcmd_en:awvalid_in;
assign awvalid_out = awvalid_in && awcmd_en;
// Also need to flow control the AwReady
//assign awready_in = (zero_length_transfer==1)?awready_out && awcmd_en:awready_out;
assign awready_in = awready_out && awcmd_en;
// Detect the case where AwCmd is released, but the wrData is not consumed
always @(posedge clk )
if (!rst_n)
stall_awvalid <= 1'b0;
else begin
if (en_wrshim && awvalid_out && awready_out && !wready_out)
stall_awvalid <= 1'b1;
else if (wready_out)
stall_awvalid <= 1'b0;
end
// Detect the case where AwValid=1, WValid=1, but AWReady=0 (WReady=1)
always @(posedge clk )
if (!rst_n)
store_first_beat <= 1'b0;
else begin
if (en_wrshim && first_beat_detect && !awready_out)
store_first_beat <= 1'b1;
else if (awready_out)
store_first_beat <= 1'b0;
end
// *****************************************************************
// ************************* WRITE DATA ****************************
// *****************************************************************
assign wlast_consumed = (wvalid_out && wready_out && wlast_in);
// For the Write Data, We need to enable the entire wrBurst
wire start_wr = wlast_detect && awvalid_in && previous_cmd_done;
// Detect if the previous AwCmd was consumed - May be backpressure
always @(posedge clk )
if (!rst_n)
previous_cmd_done <= 1'b1;
else begin
if (awvalid_out && awready_out)
previous_cmd_done <= 1'b1;
else if (awvalid_out && en_wrshim)
previous_cmd_done <= 1'b0;
end
// Store the enable unless it is a single beat wrCmd
always @(posedge clk )
if (!rst_n)
burst_still_active <= 1'b0;
else begin
if (start_wr && !wlast_consumed && en_wrshim)
burst_still_active <= 1'b1;
else if (wlast_consumed)
burst_still_active <= 1'b0;
end
wire write_data_en = en_wrshim ? (burst_still_active || start_wr) : 1'b1;
//assign wvalid_out = (zero_length_transfer==1)? wvalid_in && write_data_en:wvalid_in;
//assign wready_in = (zero_length_transfer==1)? wready_out && write_data_en:wready_out;
assign wvalid_out = wvalid_in && write_data_en;
assign wready_in = wready_out && write_data_en;
always @ *
case (wstrb_in)
4'b0001:begin
awsize_i=0;
wdata_i=wdata_in[7:0];
address_offset<=0;
end
4'b0010:begin
awsize_i=0;
wdata_i=wdata_in[15:8];
address_offset<=1;
end
4'b0100:begin
awsize_i=0;
wdata_i=wdata_in[23:16];
address_offset<=2;
end
4'b1000:begin
awsize_i=0;
wdata_i=wdata_in[31:24];
address_offset<=3;
end
4'b1100:begin
awsize_i=1;
wdata_i=wdata_in[31:16];
address_offset<=2;
end
4'b0011:begin
awsize_i=1;
wdata_i=wdata_in[15:0];
address_offset<=0;
end
default: begin
awsize_i=awsize_in;
wdata_i=wdata_in;
address_offset<=0;
end
endcase
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/02/2013 08:41:31 PM
// Design Name:
// Module Name: maxi_controller
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module maxi_controller # (
parameter M_AXI_TDATA_WIDTH = 32,
parameter M_AXI_ADDR_WIDTH = 32,
parameter OUTSTANDING_READS = 5,
parameter RELAXED_ORDERING = 1'b0,
parameter BAR0AXI = 64'h00000000,
parameter BAR1AXI = 64'h00000000,
parameter BAR2AXI = 64'h00000000,
parameter BAR3AXI = 64'h00000000,
parameter BAR4AXI = 64'h00000000,
parameter BAR5AXI = 64'h00000000,
parameter BAR0SIZE = 12,
parameter BAR1SIZE = 12,
parameter BAR2SIZE = 12,
parameter BAR3SIZE = 12,
parameter BAR4SIZE = 12,
parameter BAR5SIZE = 12
) (
input m_axi_aclk,
input m_axi_aresetn,
output [M_AXI_ADDR_WIDTH-1 : 0] m_axi_awaddr,
output [2 : 0] m_axi_awprot,
output m_axi_awvalid,
input m_axi_awready,
output [M_AXI_TDATA_WIDTH-1 : 0] m_axi_wdata,
output [M_AXI_TDATA_WIDTH/8-1 : 0] m_axi_wstrb,
output m_axi_wvalid,
input m_axi_wready,
input [1 : 0] m_axi_bresp,
input m_axi_bvalid,
output m_axi_bready,
output [M_AXI_ADDR_WIDTH-1 : 0] m_axi_araddr,
output [2 : 0] m_axi_arprot,
output m_axi_arvalid,
input m_axi_arready,
input [M_AXI_TDATA_WIDTH-1 : 0] m_axi_rdata,
input [1 : 0] m_axi_rresp,
input m_axi_rvalid,
output m_axi_rready,
//Memory Request TLP Info
input mem_req_valid,
output mem_req_ready,
input [2:0] mem_req_bar_hit,
input [31:0] mem_req_pcie_address,
input [3:0] mem_req_byte_enable,
input mem_req_write_readn,
input mem_req_phys_func,
input [31:0] mem_req_write_data,
//Completion Data Coming back
output axi_cpld_valid,
input axi_cpld_ready,
output [31:0] axi_cpld_data
);
wire mem_req_ready_r;
wire mem_req_ready_w;
wire mem_req_valid_wr;
generate
if ( RELAXED_ORDERING == 1'b1 ) begin: RELAXED_ORDERING_ENABLED
assign mem_req_ready = mem_req_write_readn ? mem_req_ready_w : mem_req_ready_r;
assign mem_req_valid_wr = mem_req_valid ;
end else begin: RELAXED_ORDERING_DISABLED
assign mem_req_ready = mem_req_ready_w & mem_req_ready_r;
assign mem_req_valid_wr = (mem_req_ready_w & mem_req_ready_r) ? mem_req_valid: 1'b0 ;
end
endgenerate
axi_read_controller # (
.M_AXI_TDATA_WIDTH ( M_AXI_TDATA_WIDTH ),
.OUTSTANDING_READS ( OUTSTANDING_READS ),
.BAR0AXI ( BAR0AXI ),
.BAR1AXI ( BAR1AXI ),
.BAR2AXI ( BAR2AXI ),
.BAR3AXI ( BAR3AXI ),
.BAR4AXI ( BAR4AXI ),
.BAR5AXI ( BAR5AXI ),
.BAR0SIZE ( BAR0SIZE ),
.BAR1SIZE ( BAR1SIZE ),
.BAR2SIZE ( BAR2SIZE ),
.BAR3SIZE ( BAR3SIZE ),
.BAR4SIZE ( BAR4SIZE ),
.BAR5SIZE ( BAR5SIZE )
) axi_read_controller (
.m_axi_aclk (m_axi_aclk),
.m_axi_aresetn (m_axi_aresetn),
.m_axi_araddr (m_axi_araddr),
.m_axi_arprot (m_axi_arprot),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready),
//Memory Request TLP Info
.mem_req_valid ( mem_req_valid_wr ),
.mem_req_ready ( mem_req_ready_r ),
.mem_req_bar_hit ( mem_req_bar_hit ),
.mem_req_pcie_address ( mem_req_pcie_address ),
.mem_req_byte_enable ( mem_req_byte_enable ),
.mem_req_write_readn ( mem_req_write_readn ),
.mem_req_phys_func ( mem_req_phys_func ),
.mem_req_write_data ( mem_req_write_data ),
//Completion TLP Info
.axi_cpld_valid ( axi_cpld_valid ),
.axi_cpld_ready ( axi_cpld_ready ),
.axi_cpld_data ( axi_cpld_data )
);
axi_write_controller #(
.M_AXI_TDATA_WIDTH ( M_AXI_TDATA_WIDTH ),
.BAR0AXI ( BAR0AXI ),
.BAR1AXI ( BAR1AXI ),
.BAR2AXI ( BAR2AXI ),
.BAR3AXI ( BAR3AXI ),
.BAR4AXI ( BAR4AXI ),
.BAR5AXI ( BAR5AXI ),
.BAR0SIZE ( BAR0SIZE ),
.BAR1SIZE ( BAR1SIZE ),
.BAR2SIZE ( BAR2SIZE ),
.BAR3SIZE ( BAR3SIZE ),
.BAR4SIZE ( BAR4SIZE ),
.BAR5SIZE ( BAR5SIZE )
) axi_write_controller (
.m_axi_aclk ( m_axi_aclk ),
.m_axi_aresetn ( m_axi_aresetn ),
.m_axi_awaddr ( m_axi_awaddr ),
.m_axi_awprot ( m_axi_awprot ),
.m_axi_awvalid ( m_axi_awvalid ),
.m_axi_awready ( m_axi_awready ),
.m_axi_wdata ( m_axi_wdata ),
.m_axi_wstrb ( m_axi_wstrb ),
.m_axi_wvalid ( m_axi_wvalid ),
.m_axi_wready ( m_axi_wready ),
.m_axi_bresp ( m_axi_bresp ),
.m_axi_bvalid ( m_axi_bvalid ),
.m_axi_bready ( m_axi_bready ),
//Memory Request TLP Info
.mem_req_valid ( mem_req_valid_wr ),
.mem_req_ready ( mem_req_ready_w ),
.mem_req_bar_hit ( mem_req_bar_hit ),
.mem_req_pcie_address ( mem_req_pcie_address ),
.mem_req_byte_enable ( mem_req_byte_enable ),
.mem_req_write_readn ( mem_req_write_readn ),
.mem_req_phys_func ( mem_req_phys_func ),
.mem_req_write_data ( mem_req_write_data )
);
endmodule
|
`define STATE_BYTE_START 3'h0
`define STATE_BYTE_WAIT_FOR_BUSY 3'h1
`define STATE_BYTE_WAIT_FOR_NOT_BUSY 3'h2
`define STATE_STOPPED 3'h3
`define MESSAGE "Hello, world!\r\n"
`define MESSAGE_LEN 15
`define MESSAGE_LEN_BITS `MESSAGE_LEN * 8
module hello(
input clk_50,
input reset_n,
output tx);
reg [7:0] data;
reg dataReady;
wire busy;
reg [0:`MESSAGE_LEN_BITS - 1] message;
reg [1:0] state;
always @(posedge clk_50 or negedge reset_n)
if (reset_n == 1'b0) begin
data <= 0;
dataReady <= 0;
message <= `MESSAGE;
state <= `STATE_BYTE_START;
end else begin
case (state)
`STATE_BYTE_START:
if (message[0:7] != 0) begin
data <= message[0:7];
message <= {message[8:`MESSAGE_LEN_BITS - 1], 8'd0};
dataReady <= 1;
state <= `STATE_BYTE_WAIT_FOR_BUSY;
end else
state <= `STATE_STOPPED;
`STATE_BYTE_WAIT_FOR_BUSY:
if (busy) begin
dataReady <= 0;
state <= `STATE_BYTE_WAIT_FOR_NOT_BUSY;
end
`STATE_BYTE_WAIT_FOR_NOT_BUSY:
if (!busy)
state <= `STATE_BYTE_START;
default: state <= `STATE_STOPPED;
endcase
end
uart yuart(
.clk(clk_50),
.reset(!reset_n),
.data(data),
.dataReady(dataReady),
.busy(busy),
.tx(tx)
);
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit... *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption. Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* FILL IN HERE *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* FILL IN HERE *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
(** [] *)
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Definition multistep := multi step.
Notation " t '==>*' t' " := (multistep t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* $Date: 2014-04-02 10:55:30 -0400 (Wed, 02 Apr 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFRBP_PP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrbp (
RESET_B,
CLK ,
D ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N (
Q ,
D ,
GATE ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:04:30 EST 2014
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkWciTarget(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag);
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// signals for module outputs
wire [31 : 0] wciS0_SData;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy;
// inlined wires
wire [71 : 0] target_wciReq_wget;
wire [33 : 0] target_respF_x_wire_wget;
wire [31 : 0] wci_Es_mAddr_w_wget, wci_Es_mData_w_wget;
wire [3 : 0] wci_Es_mByteEn_w_wget;
wire [2 : 0] target_wEdge_wget, wci_Es_mCmd_w_wget;
wire target_ctlAckReg_1_wget,
target_ctlAckReg_1_whas,
target_reqF_r_clr_whas,
target_reqF_r_deq_whas,
target_reqF_r_enq_whas,
target_respF_dequeueing_whas,
target_respF_enqueueing_whas,
target_respF_x_wire_whas,
target_sFlagReg_1_wget,
target_sFlagReg_1_whas,
target_sThreadBusy_pw_whas,
target_wEdge_whas,
target_wciReq_whas,
target_wci_cfrd_pw_whas,
target_wci_cfwr_pw_whas,
target_wci_ctrl_pw_whas,
wci_Es_mAddrSpace_w_wget,
wci_Es_mAddrSpace_w_whas,
wci_Es_mAddr_w_whas,
wci_Es_mByteEn_w_whas,
wci_Es_mCmd_w_whas,
wci_Es_mData_w_whas;
// register biasValue
reg [31 : 0] biasValue;
wire [31 : 0] biasValue_D_IN;
wire biasValue_EN;
// register controlReg
reg [31 : 0] controlReg;
wire [31 : 0] controlReg_D_IN;
wire controlReg_EN;
// register operating
reg operating;
wire operating_D_IN, operating_EN;
// register target_cEdge
reg [2 : 0] target_cEdge;
wire [2 : 0] target_cEdge_D_IN;
wire target_cEdge_EN;
// register target_cState
reg [2 : 0] target_cState;
wire [2 : 0] target_cState_D_IN;
wire target_cState_EN;
// register target_ctlAckReg
reg target_ctlAckReg;
wire target_ctlAckReg_D_IN, target_ctlAckReg_EN;
// register target_ctlOpActive
reg target_ctlOpActive;
wire target_ctlOpActive_D_IN, target_ctlOpActive_EN;
// register target_illegalEdge
reg target_illegalEdge;
wire target_illegalEdge_D_IN, target_illegalEdge_EN;
// register target_isReset_isInReset
reg target_isReset_isInReset;
wire target_isReset_isInReset_D_IN, target_isReset_isInReset_EN;
// register target_nState
reg [2 : 0] target_nState;
reg [2 : 0] target_nState_D_IN;
wire target_nState_EN;
// register target_reqF_countReg
reg [1 : 0] target_reqF_countReg;
wire [1 : 0] target_reqF_countReg_D_IN;
wire target_reqF_countReg_EN;
// register target_respF_cntr_r
reg [1 : 0] target_respF_cntr_r;
wire [1 : 0] target_respF_cntr_r_D_IN;
wire target_respF_cntr_r_EN;
// register target_respF_q_0
reg [33 : 0] target_respF_q_0;
reg [33 : 0] target_respF_q_0_D_IN;
wire target_respF_q_0_EN;
// register target_respF_q_1
reg [33 : 0] target_respF_q_1;
reg [33 : 0] target_respF_q_1_D_IN;
wire target_respF_q_1_EN;
// register target_sFlagReg
reg target_sFlagReg;
wire target_sFlagReg_D_IN, target_sFlagReg_EN;
// register target_sThreadBusy_d
reg target_sThreadBusy_d;
wire target_sThreadBusy_d_D_IN, target_sThreadBusy_d_EN;
// ports of submodule target_reqF
wire [71 : 0] target_reqF_D_IN, target_reqF_D_OUT;
wire target_reqF_CLR, target_reqF_DEQ, target_reqF_EMPTY_N, target_reqF_ENQ;
// rule scheduling signals
wire WILL_FIRE_RL_report_operating,
WILL_FIRE_RL_target_cfrd,
WILL_FIRE_RL_target_cfwr,
WILL_FIRE_RL_target_ctl_op_complete,
WILL_FIRE_RL_target_ctl_op_start,
WILL_FIRE_RL_target_ctrl_EiI,
WILL_FIRE_RL_target_respF_both,
WILL_FIRE_RL_target_respF_decCtr,
WILL_FIRE_RL_target_respF_incCtr;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_target_respF_q_0_write_1__VAL_2;
wire [33 : 0] MUX_target_respF_q_0_write_1__VAL_1,
MUX_target_respF_q_1_write_1__VAL_1,
MUX_target_respF_x_wire_wset_1__VAL_1,
MUX_target_respF_x_wire_wset_1__VAL_2;
wire [1 : 0] MUX_target_respF_cntr_r_write_1__VAL_2;
wire MUX_target_illegalEdge_write_1__SEL_1,
MUX_target_illegalEdge_write_1__SEL_2,
MUX_target_illegalEdge_write_1__VAL_2,
MUX_target_respF_q_0_write_1__SEL_1,
MUX_target_respF_q_0_write_1__SEL_2,
MUX_target_respF_q_1_write_1__SEL_1,
MUX_target_respF_q_1_write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h3558, v__h3733, v__h3877, v__h4170, v__h4428, v__h4583;
reg [31 : 0] _theResult____h4567;
wire [1 : 0] target_respF_cntr_r_8_MINUS_1___d27;
wire _dfoo1, _dfoo3;
// value method wciS0_sResp
assign wciS0_SResp = target_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = target_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
target_reqF_countReg > 2'd1 || target_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, target_sFlagReg } ;
// submodule target_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) target_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(target_reqF_D_IN),
.ENQ(target_reqF_ENQ),
.DEQ(target_reqF_DEQ),
.CLR(target_reqF_CLR),
.D_OUT(target_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(target_reqF_EMPTY_N));
// rule RL_report_operating
assign WILL_FIRE_RL_report_operating = target_cState == 3'd2 && !operating ;
// rule RL_target_cfwr
assign WILL_FIRE_RL_target_cfwr =
target_respF_cntr_r != 2'd2 && target_reqF_EMPTY_N &&
target_wci_cfwr_pw_whas ;
// rule RL_target_cfrd
assign WILL_FIRE_RL_target_cfrd =
target_respF_cntr_r != 2'd2 && target_reqF_EMPTY_N &&
target_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_target_cfwr ;
// rule RL_target_ctl_op_start
assign WILL_FIRE_RL_target_ctl_op_start =
target_reqF_EMPTY_N && target_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_target_ctl_op_complete &&
!WILL_FIRE_RL_target_cfrd &&
!WILL_FIRE_RL_target_cfwr ;
// rule RL_target_ctrl_EiI
assign WILL_FIRE_RL_target_ctrl_EiI =
target_wci_ctrl_pw_whas && WILL_FIRE_RL_target_ctl_op_start &&
target_cState == 3'd0 &&
target_reqF_D_OUT[36:34] == 3'd0 ;
// rule RL_target_ctl_op_complete
assign WILL_FIRE_RL_target_ctl_op_complete =
target_respF_cntr_r != 2'd2 && target_ctlOpActive &&
target_ctlAckReg &&
!WILL_FIRE_RL_target_cfrd &&
!WILL_FIRE_RL_target_cfwr ;
// rule RL_target_respF_incCtr
assign WILL_FIRE_RL_target_respF_incCtr =
target_respF_x_wire_whas && target_respF_enqueueing_whas &&
!(target_respF_cntr_r != 2'd0) ;
// rule RL_target_respF_decCtr
assign WILL_FIRE_RL_target_respF_decCtr =
target_respF_cntr_r != 2'd0 && !target_respF_enqueueing_whas ;
// rule RL_target_respF_both
assign WILL_FIRE_RL_target_respF_both =
target_respF_x_wire_whas && target_respF_cntr_r != 2'd0 &&
target_respF_enqueueing_whas ;
// inputs to muxes for submodule ports
assign MUX_target_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_target_ctl_op_complete && target_illegalEdge ;
assign MUX_target_illegalEdge_write_1__SEL_2 =
WILL_FIRE_RL_target_ctl_op_start &&
(target_reqF_D_OUT[36:34] == 3'd0 && target_cState != 3'd0 ||
target_reqF_D_OUT[36:34] == 3'd1 && target_cState != 3'd1 &&
target_cState != 3'd3 ||
target_reqF_D_OUT[36:34] == 3'd2 && target_cState != 3'd2 ||
target_reqF_D_OUT[36:34] == 3'd3 && target_cState != 3'd3 &&
target_cState != 3'd2 &&
target_cState != 3'd1 ||
target_reqF_D_OUT[36:34] == 3'd4 ||
target_reqF_D_OUT[36:34] == 3'd5 ||
target_reqF_D_OUT[36:34] == 3'd6 ||
target_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_target_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_target_respF_both && _dfoo3 ;
assign MUX_target_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_target_respF_incCtr && target_respF_cntr_r == 2'd0 ;
assign MUX_target_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_target_respF_both && _dfoo1 ;
assign MUX_target_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_target_respF_incCtr && target_respF_cntr_r == 2'd1 ;
assign MUX_target_illegalEdge_write_1__VAL_2 =
target_reqF_D_OUT[36:34] != 3'd4 &&
target_reqF_D_OUT[36:34] != 3'd5 &&
target_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_target_respF_cntr_r_write_1__VAL_2 = target_respF_cntr_r + 2'd1 ;
assign MUX_target_respF_q_0_write_1__VAL_1 =
(target_respF_cntr_r == 2'd1) ?
MUX_target_respF_q_0_write_1__VAL_2 :
target_respF_q_1 ;
always@(WILL_FIRE_RL_target_ctl_op_complete or
MUX_target_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_target_cfrd or
MUX_target_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_target_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_target_ctl_op_complete:
MUX_target_respF_q_0_write_1__VAL_2 =
MUX_target_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_target_cfrd:
MUX_target_respF_q_0_write_1__VAL_2 =
MUX_target_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_target_cfwr:
MUX_target_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_target_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_target_respF_q_1_write_1__VAL_1 =
(target_respF_cntr_r == 2'd2) ?
MUX_target_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_target_respF_x_wire_wset_1__VAL_1 =
target_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_target_respF_x_wire_wset_1__VAL_2 =
{ 2'd1, _theResult____h4567 } ;
// inlined wires
assign target_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign target_wciReq_whas = 1'd1 ;
assign target_respF_x_wire_wget = MUX_target_respF_q_0_write_1__VAL_2 ;
assign target_respF_x_wire_whas =
WILL_FIRE_RL_target_ctl_op_complete ||
WILL_FIRE_RL_target_cfrd ||
WILL_FIRE_RL_target_cfwr ;
assign target_wEdge_wget = target_reqF_D_OUT[36:34] ;
assign target_wEdge_whas = WILL_FIRE_RL_target_ctl_op_start ;
assign target_sFlagReg_1_wget = 1'b0 ;
assign target_sFlagReg_1_whas = 1'b0 ;
assign target_ctlAckReg_1_wget = 1'd1 ;
assign target_ctlAckReg_1_whas =
target_wci_ctrl_pw_whas && WILL_FIRE_RL_target_ctl_op_start &&
target_cState == 3'd2 &&
target_reqF_D_OUT[36:34] == 3'd3 ||
target_wci_ctrl_pw_whas && WILL_FIRE_RL_target_ctl_op_start &&
target_cState == 3'd1 &&
target_reqF_D_OUT[36:34] == 3'd1 ||
WILL_FIRE_RL_target_ctrl_EiI ;
assign wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_Es_mData_w_wget = wciS0_MData ;
assign wci_Es_mData_w_whas = 1'd1 ;
assign target_reqF_r_enq_whas = target_wciReq_wget[71:69] != 3'd0 ;
assign target_reqF_r_deq_whas =
WILL_FIRE_RL_target_cfrd || WILL_FIRE_RL_target_cfwr ||
WILL_FIRE_RL_target_ctl_op_start ;
assign target_reqF_r_clr_whas = 1'b0 ;
assign target_respF_enqueueing_whas =
WILL_FIRE_RL_target_cfrd || WILL_FIRE_RL_target_cfwr ||
WILL_FIRE_RL_target_ctl_op_complete ;
assign target_respF_dequeueing_whas = target_respF_cntr_r != 2'd0 ;
assign target_sThreadBusy_pw_whas = 1'b0 ;
assign target_wci_cfwr_pw_whas =
target_reqF_EMPTY_N && target_reqF_D_OUT[68] &&
target_reqF_D_OUT[71:69] == 3'd1 ;
assign target_wci_cfrd_pw_whas =
target_reqF_EMPTY_N && target_reqF_D_OUT[68] &&
target_reqF_D_OUT[71:69] == 3'd2 ;
assign target_wci_ctrl_pw_whas =
target_reqF_EMPTY_N && !target_reqF_D_OUT[68] &&
target_reqF_D_OUT[71:69] == 3'd2 ;
// register biasValue
assign biasValue_D_IN =
WILL_FIRE_RL_target_ctrl_EiI ? 32'd0 : target_reqF_D_OUT[31:0] ;
assign biasValue_EN =
WILL_FIRE_RL_target_cfwr && target_reqF_D_OUT[39:32] == 8'h0 ||
WILL_FIRE_RL_target_ctrl_EiI ;
// register controlReg
assign controlReg_D_IN =
WILL_FIRE_RL_target_ctrl_EiI ? 32'd0 : target_reqF_D_OUT[31:0] ;
assign controlReg_EN =
WILL_FIRE_RL_target_cfwr && target_reqF_D_OUT[39:32] == 8'h04 ||
WILL_FIRE_RL_target_ctrl_EiI ;
// register operating
assign operating_D_IN = 1'd1 ;
assign operating_EN = WILL_FIRE_RL_report_operating ;
// register target_cEdge
assign target_cEdge_D_IN = target_reqF_D_OUT[36:34] ;
assign target_cEdge_EN = WILL_FIRE_RL_target_ctl_op_start ;
// register target_cState
assign target_cState_D_IN = target_nState ;
assign target_cState_EN =
WILL_FIRE_RL_target_ctl_op_complete && !target_illegalEdge ;
// register target_ctlAckReg
assign target_ctlAckReg_D_IN = target_ctlAckReg_1_whas ;
assign target_ctlAckReg_EN = 1'd1 ;
// register target_ctlOpActive
assign target_ctlOpActive_D_IN = !WILL_FIRE_RL_target_ctl_op_complete ;
assign target_ctlOpActive_EN =
WILL_FIRE_RL_target_ctl_op_complete ||
WILL_FIRE_RL_target_ctl_op_start ;
// register target_illegalEdge
assign target_illegalEdge_D_IN =
!MUX_target_illegalEdge_write_1__SEL_1 &&
MUX_target_illegalEdge_write_1__VAL_2 ;
assign target_illegalEdge_EN =
WILL_FIRE_RL_target_ctl_op_complete && target_illegalEdge ||
MUX_target_illegalEdge_write_1__SEL_2 ;
// register target_isReset_isInReset
assign target_isReset_isInReset_D_IN = 1'd0 ;
assign target_isReset_isInReset_EN = target_isReset_isInReset ;
// register target_nState
always@(target_reqF_D_OUT)
begin
case (target_reqF_D_OUT[36:34])
3'd0: target_nState_D_IN = 3'd1;
3'd1: target_nState_D_IN = 3'd2;
3'd2: target_nState_D_IN = 3'd3;
default: target_nState_D_IN = 3'd0;
endcase
end
assign target_nState_EN =
WILL_FIRE_RL_target_ctl_op_start &&
(target_reqF_D_OUT[36:34] == 3'd0 && target_cState == 3'd0 ||
target_reqF_D_OUT[36:34] == 3'd1 &&
(target_cState == 3'd1 || target_cState == 3'd3) ||
target_reqF_D_OUT[36:34] == 3'd2 && target_cState == 3'd2 ||
target_reqF_D_OUT[36:34] == 3'd3 &&
(target_cState == 3'd3 || target_cState == 3'd2 ||
target_cState == 3'd1)) ;
// register target_reqF_countReg
assign target_reqF_countReg_D_IN =
(target_wciReq_wget[71:69] != 3'd0) ?
target_reqF_countReg + 2'd1 :
target_reqF_countReg - 2'd1 ;
assign target_reqF_countReg_EN =
(target_wciReq_wget[71:69] != 3'd0) != target_reqF_r_deq_whas ;
// register target_respF_cntr_r
assign target_respF_cntr_r_D_IN =
WILL_FIRE_RL_target_respF_decCtr ?
target_respF_cntr_r_8_MINUS_1___d27 :
MUX_target_respF_cntr_r_write_1__VAL_2 ;
assign target_respF_cntr_r_EN =
WILL_FIRE_RL_target_respF_decCtr ||
WILL_FIRE_RL_target_respF_incCtr ;
// register target_respF_q_0
always@(MUX_target_respF_q_0_write_1__SEL_1 or
MUX_target_respF_q_0_write_1__VAL_1 or
MUX_target_respF_q_0_write_1__SEL_2 or
MUX_target_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_target_respF_decCtr or target_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_target_respF_q_0_write_1__SEL_1:
target_respF_q_0_D_IN = MUX_target_respF_q_0_write_1__VAL_1;
MUX_target_respF_q_0_write_1__SEL_2:
target_respF_q_0_D_IN = MUX_target_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_target_respF_decCtr:
target_respF_q_0_D_IN = target_respF_q_1;
default: target_respF_q_0_D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign target_respF_q_0_EN =
WILL_FIRE_RL_target_respF_both && _dfoo3 ||
WILL_FIRE_RL_target_respF_incCtr &&
target_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_target_respF_decCtr ;
// register target_respF_q_1
always@(MUX_target_respF_q_1_write_1__SEL_1 or
MUX_target_respF_q_1_write_1__VAL_1 or
MUX_target_respF_q_1_write_1__SEL_2 or
MUX_target_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_target_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_target_respF_q_1_write_1__SEL_1:
target_respF_q_1_D_IN = MUX_target_respF_q_1_write_1__VAL_1;
MUX_target_respF_q_1_write_1__SEL_2:
target_respF_q_1_D_IN = MUX_target_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_target_respF_decCtr: target_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: target_respF_q_1_D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign target_respF_q_1_EN =
WILL_FIRE_RL_target_respF_both && _dfoo1 ||
WILL_FIRE_RL_target_respF_incCtr &&
target_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_target_respF_decCtr ;
// register target_sFlagReg
assign target_sFlagReg_D_IN = 1'b0 ;
assign target_sFlagReg_EN = 1'd1 ;
// register target_sThreadBusy_d
assign target_sThreadBusy_d_D_IN = 1'b0 ;
assign target_sThreadBusy_d_EN = 1'd1 ;
// submodule target_reqF
assign target_reqF_D_IN = target_wciReq_wget ;
assign target_reqF_ENQ = target_wciReq_wget[71:69] != 3'd0 ;
assign target_reqF_DEQ = target_reqF_r_deq_whas ;
assign target_reqF_CLR = 1'b0 ;
// remaining internal signals
assign _dfoo1 =
target_respF_cntr_r != 2'd2 ||
target_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
target_respF_cntr_r != 2'd1 ||
target_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign target_respF_cntr_r_8_MINUS_1___d27 = target_respF_cntr_r - 2'd1 ;
always@(target_reqF_D_OUT or biasValue or controlReg)
begin
case (target_reqF_D_OUT[39:32])
8'h0: _theResult____h4567 = biasValue;
8'h04: _theResult____h4567 = controlReg;
default: _theResult____h4567 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
operating <= `BSV_ASSIGNMENT_DELAY 1'd0;
target_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
target_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
target_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
target_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
target_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
target_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
target_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
target_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
target_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
target_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
target_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
target_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (operating_EN) operating <= `BSV_ASSIGNMENT_DELAY operating_D_IN;
if (target_cEdge_EN)
target_cEdge <= `BSV_ASSIGNMENT_DELAY target_cEdge_D_IN;
if (target_cState_EN)
target_cState <= `BSV_ASSIGNMENT_DELAY target_cState_D_IN;
if (target_ctlAckReg_EN)
target_ctlAckReg <= `BSV_ASSIGNMENT_DELAY target_ctlAckReg_D_IN;
if (target_ctlOpActive_EN)
target_ctlOpActive <= `BSV_ASSIGNMENT_DELAY target_ctlOpActive_D_IN;
if (target_illegalEdge_EN)
target_illegalEdge <= `BSV_ASSIGNMENT_DELAY target_illegalEdge_D_IN;
if (target_nState_EN)
target_nState <= `BSV_ASSIGNMENT_DELAY target_nState_D_IN;
if (target_reqF_countReg_EN)
target_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
target_reqF_countReg_D_IN;
if (target_respF_cntr_r_EN)
target_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
target_respF_cntr_r_D_IN;
if (target_respF_q_0_EN)
target_respF_q_0 <= `BSV_ASSIGNMENT_DELAY target_respF_q_0_D_IN;
if (target_respF_q_1_EN)
target_respF_q_1 <= `BSV_ASSIGNMENT_DELAY target_respF_q_1_D_IN;
if (target_sFlagReg_EN)
target_sFlagReg <= `BSV_ASSIGNMENT_DELAY target_sFlagReg_D_IN;
if (target_sThreadBusy_d_EN)
target_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
target_sThreadBusy_d_D_IN;
end
if (biasValue_EN) biasValue <= `BSV_ASSIGNMENT_DELAY biasValue_D_IN;
if (controlReg_EN) controlReg <= `BSV_ASSIGNMENT_DELAY controlReg_D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
target_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (target_isReset_isInReset_EN)
target_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
target_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
biasValue = 32'hAAAAAAAA;
controlReg = 32'hAAAAAAAA;
operating = 1'h0;
target_cEdge = 3'h2;
target_cState = 3'h2;
target_ctlAckReg = 1'h0;
target_ctlOpActive = 1'h0;
target_illegalEdge = 1'h0;
target_isReset_isInReset = 1'h0;
target_nState = 3'h2;
target_reqF_countReg = 2'h2;
target_respF_cntr_r = 2'h2;
target_respF_q_0 = 34'h2AAAAAAAA;
target_respF_q_1 = 34'h2AAAAAAAA;
target_sFlagReg = 1'h0;
target_sThreadBusy_d = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_report_operating)
begin
v__h4170 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_report_operating)
$display("[%0d]: %m: WCI Target is Operating", v__h4170);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_cfwr)
begin
v__h4428 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_cfwr)
$display("[%0d]: %m: WCI TARGET CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h4428,
target_reqF_D_OUT[63:32],
target_reqF_D_OUT[67:64],
target_reqF_D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_cfrd)
begin
v__h4583 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_cfrd)
$display("[%0d]: %m: WCI TARGET CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h4583,
target_reqF_D_OUT[63:32],
target_reqF_D_OUT[67:64],
_theResult____h4567);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_ctl_op_start)
begin
v__h3558 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3558,
target_reqF_D_OUT[36:34],
target_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_ctl_op_complete && target_illegalEdge)
begin
v__h3877 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_ctl_op_complete && target_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3877,
target_cEdge,
target_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_ctl_op_complete && !target_illegalEdge)
begin
v__h3733 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_target_ctl_op_complete && !target_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3733,
target_cEdge,
target_cState,
target_nState);
end
// synopsys translate_on
endmodule // mkWciTarget
|
/*cia b*/
module ciab
(
input clk, // clock
input clk7_en,
input aen, // adress enable
input rd, // read enable
input wr, // write enable
input reset, // reset
input [3:0] rs, // register select (address)
input [7:0] data_in, // bus data in
output [7:0] data_out, // bus data out
input tick, // tick (counter input for TOD timer)
input eclk, // eclk (counter input for timer A/B)
input flag, // flag (set FLG bit in ICR register)
output irq, // interrupt request out
input [5:3] porta_in, // input port
output [7:6] porta_out, // output port
output [7:0] portb_out // output port
);
// local signals
wire [7:0] icr_out;
wire [7:0] tmra_out;
wire [7:0] tmrb_out;
wire [7:0] tmrd_out;
reg [7:0] pa_out;
reg [7:0] pb_out;
wire alrm; // TOD interrupt
wire ta; // TIMER A interrupt
wire tb; // TIMER B interrupt
wire tmra_ovf; // TIMER A underflow (for Timer B)
reg [7:0] sdr_latch;
wire [7:0] sdr_out;
reg tick_del; // required for edge detection
//----------------------------------------------------------------------------------
// address decoder
//----------------------------------------------------------------------------------
wire pra,prb,ddra,ddrb,cra,talo,tahi,crb,tblo,tbhi,tdlo,tdme,tdhi,sdr,icrs;
wire enable;
assign enable = aen & (rd | wr);
// decoder
assign pra = (enable && rs==4'h0) ? 1'b1 : 1'b0;
assign prb = (enable && rs==4'h1) ? 1'b1 : 1'b0;
assign ddra = (enable && rs==4'h2) ? 1'b1 : 1'b0;
assign ddrb = (enable && rs==4'h3) ? 1'b1 : 1'b0;
assign talo = (enable && rs==4'h4) ? 1'b1 : 1'b0;
assign tahi = (enable && rs==4'h5) ? 1'b1 : 1'b0;
assign tblo = (enable && rs==4'h6) ? 1'b1 : 1'b0;
assign tbhi = (enable && rs==4'h7) ? 1'b1 : 1'b0;
assign tdlo = (enable && rs==4'h8) ? 1'b1 : 1'b0;
assign tdme = (enable && rs==4'h9) ? 1'b1 : 1'b0;
assign tdhi = (enable && rs==4'hA) ? 1'b1 : 1'b0;
assign sdr = (enable && rs==4'hC) ? 1'b1 : 1'b0;
assign icrs = (enable && rs==4'hD) ? 1'b1 : 1'b0;
assign cra = (enable && rs==4'hE) ? 1'b1 : 1'b0;
assign crb = (enable && rs==4'hF) ? 1'b1 : 1'b0;
//----------------------------------------------------------------------------------
// data_out multiplexer
//----------------------------------------------------------------------------------
assign data_out = icr_out | tmra_out | tmrb_out | tmrd_out | sdr_out | pb_out | pa_out;
// fake serial port data register
always @(posedge clk)
if (clk7_en) begin
if (reset)
sdr_latch[7:0] <= 8'h00;
else if (wr & sdr)
sdr_latch[7:0] <= data_in[7:0];
end
// sdr register read
assign sdr_out = (!wr && sdr) ? sdr_latch[7:0] : 8'h00;
//----------------------------------------------------------------------------------
// porta
//----------------------------------------------------------------------------------
reg [5:3] porta_in2;
reg [7:0] regporta;
reg [7:0] ddrporta;
// synchronizing of input data
always @(posedge clk)
if (clk7_en) begin
porta_in2[5:3] <= porta_in[5:3];
end
// writing of output port
always @(posedge clk)
if (clk7_en) begin
if (reset)
regporta[7:0] <= 8'd0;
else if (wr && pra)
regporta[7:0] <= data_in[7:0];
end
// writing of ddr register
always @(posedge clk)
if (clk7_en) begin
if (reset)
ddrporta[7:0] <= 8'd0;
else if (wr && ddra)
ddrporta[7:0] <= data_in[7:0];
end
// reading of port/ddr register
always @(*)
begin
if (!wr && pra)
pa_out[7:0] = {porta_out[7:6],porta_in2[5:3],3'b111};
else if (!wr && ddra)
pa_out[7:0] = ddrporta[7:0];
else
pa_out[7:0] = 8'h00;
end
// assignment of output port while keeping in mind that the original 8520 uses pull-ups
assign porta_out[7:6] = (~ddrporta[7:6]) | regporta[7:6];
//----------------------------------------------------------------------------------
// portb
//----------------------------------------------------------------------------------
reg [7:0] regportb;
reg [7:0] ddrportb;
// writing of output port
always @(posedge clk)
if (clk7_en) begin
if (reset)
regportb[7:0] <= 8'd0;
else if (wr && prb)
regportb[7:0] <= data_in[7:0];
end
// writing of ddr register
always @(posedge clk)
if (clk7_en) begin
if (reset)
ddrportb[7:0] <= 8'd0;
else if (wr && ddrb)
ddrportb[7:0] <= data_in[7:0];
end
// reading of port/ddr register
always @(*)
begin
if (!wr && prb)
pb_out[7:0] = portb_out[7:0];
else if (!wr && ddrb)
pb_out[7:0] = ddrportb[7:0];
else
pb_out[7:0] = 8'h00;
end
// assignment of output port while keeping in mind that the original 8520 uses pull-ups
assign portb_out[7:0] = (~ddrportb[7:0]) | regportb[7:0];
// deleyed tick signal for edge detection
always @(posedge clk)
if (clk7_en) begin
tick_del <= tick;
end
//----------------------------------------------------------------------------------
// instantiate cia interrupt controller
//----------------------------------------------------------------------------------
cia_int cnt
(
.clk(clk),
.clk7_en(clk7_en),
.wr(wr),
.reset(reset),
.icrs(icrs),
.ta(ta),
.tb(tb),
.alrm(alrm),
.flag(flag),
.ser(1'b0),
.data_in(data_in),
.data_out(icr_out),
.irq(irq)
);
//----------------------------------------------------------------------------------
// instantiate timer A
//----------------------------------------------------------------------------------
cia_timera tmra
(
.clk(clk),
.clk7_en(clk7_en),
.wr(wr),
.reset(reset),
.tlo(talo),
.thi(tahi),
.tcr(cra),
.data_in(data_in),
.data_out(tmra_out),
.eclk(eclk),
.tmra_ovf(tmra_ovf),
.irq(ta)
);
//----------------------------------------------------------------------------------
// instantiate timer B
//----------------------------------------------------------------------------------
cia_timerb tmrb
(
.clk(clk),
.clk7_en(clk7_en),
.wr(wr),
.reset(reset),
.tlo(tblo),
.thi(tbhi),
.tcr(crb),
.data_in(data_in),
.data_out(tmrb_out),
.eclk(eclk),
.tmra_ovf(tmra_ovf),
.irq(tb)
);
//----------------------------------------------------------------------------------
// instantiate timer D
//----------------------------------------------------------------------------------
cia_timerd tmrd
(
.clk(clk),
.clk7_en(clk7_en),
.wr(wr),
.reset(reset),
.tlo(tdlo),
.tme(tdme),
.thi(tdhi),
.tcr(crb),
.data_in(data_in),
.data_out(tmrd_out),
.count(tick & ~tick_del),
.irq(alrm)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 15
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "ip_design_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "ip_design_xbar_0,axi_crossbar_v2_1_15_axi_crossbar,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=15,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=6,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x000000004121000000000000412000000000000043c300000000000043c000000000000043c100000000000043c20000,C_M_AXI_ADDR_WIDTH=0x\
00000010000000100000000e000000100000000f0000000c,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x000000010000000100000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x000000010000000100000001000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEP\
TANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x000000010000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x000000010000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x000000000000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ip_design_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLKIF, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160]" *)
output wire [191 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15]" *)
output wire [17 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5]" *)
output wire [5 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5]" *)
input wire [5 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160]" *)
output wire [191 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20]" *)
output wire [23 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5]" *)
output wire [5 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5]" *)
input wire [5 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10]" *)
input wire [11 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5]" *)
input wire [5 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5]" *)
output wire [5 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160]" *)
output wire [191 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15]" *)
output wire [17 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5]" *)
output wire [5 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5]" *)
input wire [5 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160]" *)
input wire [191 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10]" *)
input wire [11 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5]" *)
input wire [5 : 0] m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M00_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M01_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M02_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M03_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M04_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, XIL_INTERFACENAME M05_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5]" *)
output wire [5 : 0] m_axi_rready;
axi_crossbar_v2_1_15_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(6),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(384'H000000004121000000000000412000000000000043c300000000000043c000000000000043c100000000000043c20000),
.C_M_AXI_ADDR_WIDTH(192'H00000010000000100000000e000000100000000f0000000c),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(192'H000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(192'H000000010000000100000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(192'H000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(192'H000000010000000100000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(192'H000000000000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(6'H00),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(6'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(6'H00),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(6'H3F),
.m_axi_ruser(6'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`include "constants.vh"
`include "rv32_opcodes.vh"
`include "alu_ops.vh"
`default_nettype none
module mux_4x1(
input wire [1:0] sel,
input wire [2*`DATA_LEN-1:0] dat0,
input wire [2*`DATA_LEN-1:0] dat1,
input wire [2*`DATA_LEN-1:0] dat2,
input wire [2*`DATA_LEN-1:0] dat3,
output reg [2*`DATA_LEN-1:0] out
);
always @(*) begin
case(sel)
0: begin
out = dat0;
end
1: begin
out = dat1;
end
2: begin
out = dat2;
end
3: begin
out = dat3;
end
endcase
end
endmodule // mux_4x1
// sel_lohi = md_req_out_sel[0]
module multiplier(
input wire signed [`DATA_LEN-1:0] src1,
input wire signed [`DATA_LEN-1:0] src2,
input wire src1_signed,
input wire src2_signed,
input wire sel_lohi,
output wire [`DATA_LEN-1:0] result
);
wire signed [`DATA_LEN:0] src1_unsign = {1'b0, src1};
wire signed [`DATA_LEN:0] src2_unsign = {1'b0, src2};
wire signed [2*`DATA_LEN-1:0] res_ss = src1 * src2;
wire signed [2*`DATA_LEN-1:0] res_su = src1 * src2_unsign;
wire signed [2*`DATA_LEN-1:0] res_us = src1_unsign * src2;
wire signed [2*`DATA_LEN-1:0] res_uu = src1_unsign * src2_unsign;
wire [2*`DATA_LEN-1:0] res;
mux_4x1 mxres(
.sel({src1_signed, src2_signed}),
.dat0(res_uu),
.dat1(res_us),
.dat2(res_su),
.dat3(res_ss),
.out(res)
);
assign result = sel_lohi ? res[`DATA_LEN+:`DATA_LEN] : res[`DATA_LEN-1:0];
endmodule // multiplier
`default_nettype wire
|
`timescale 1ns / 1ps
/*
Group Members: Nikita Eisenhauer and Warren Seto
Lab Name: Adder Design
Design Description: Verilog test fixture to test the 64-bit look ahead adder
*/
module look_ahead_adder_test;
// Inputs
reg [63:0] A;
reg [63:0] B;
// Outputs
wire [63:0] SUM;
wire CARRY;
// Instantiate two counter variables for the test loop
integer count;
integer count2;
// Instantiate the Unit Under Test (UUT)
look_ahead_adder_64 uut
(
.A(A),
.B(B),
.SUM(SUM),
.CARRY(CARRY)
);
initial begin
$monitor("%d + %d = %d and carry %d", A, B, SUM, CARRY);
// Iterate through all possible combination of 0-32
count = 0;
count2 = 0;
A = 0;
B = 0;
// Loops over the possible combinations for the inputs A and B
for (count = 0; count <= 32; count = count + 1) begin
{A} = count;
for (count2 = 0; count2 <= 32; count2 = count2 + 1) begin
{B} = count2;
#1;
end
end
end
initial #4000 $finish; // The test will run for a total interval of 4000 nanoseconds
endmodule
|
(** * MoreInd: More on Induction *)
Require Export "ProofObjects".
(* ##################################################### *)
(** * Induction Principles *)
(** This is a good point to pause and take a deeper look at induction
principles.
Every time we declare a new [Inductive] datatype, Coq
automatically generates and proves an _induction principle_
for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** *** *)
(** The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
Case "O". reflexivity.
Case "S". simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, optional (plus_one_r') *)
(** Complete this proof as we did [mult_0_r'] above, without using
the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
apply nat_ind.
reflexivity.
intros. simpl. apply f_equal. apply H.
Qed.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. (Although
we don't need induction to prove properties of non-recursive
datatypes, the idea of an induction principle still makes sense
for them: it gives a way to prove that a property holds for all
values of the type.)
These generated principles follow a similar pattern. If we define a
type [t] with constructors [c1] ... [cn], Coq generates a theorem
with this shape:
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(** **** Exercise: 1 star, optional (rgb) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
Check rgb_ind.
(** [] *)
Check rgb_ind.
(* rgb_ind
: forall P : rgb -> Prop,
P red -> P green -> P blue -> forall r : rgb, P r *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little variable renaming for clarity)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(** **** Exercise: 1 star, optional (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
Check natlist_ind.
(* natlist_ind
: forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (n0 : natlist), P n0 -> P (ncons n n0)) ->
forall n : natlist, P n *)
(** Now what will the induction principle look like? *)
(** [] *)
(** From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of
type [t]), then [P] holds for [c x1 ... xn]".
*)
(** **** Exercise: 1 star, optional (byntree_ind) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive byntree : Type :=
| bempty : byntree
| bleaf : yesno -> byntree
| nbranch : yesno -> byntree -> byntree -> byntree.
(** [] *)
Check byntree_ind.
(* byntree_ind
: forall P : byntree -> Prop,
P bempty ->
(forall y : yesno, P (bleaf y)) ->
(forall (y : yesno) (b : byntree),
P b -> forall b0 : byntree, P b0 -> P (nbranch y b b0)) ->
forall b : byntree, P b *)
(** **** Exercise: 1 star, optional (ex_set) *)
(** Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
Inductive ExSet : Type :=
| con1 : forall b : bool, ExSet
| con2: forall (n : nat) (e : ExSet), ExSet
.
Check ExSet_ind.
(** [] *)
(** What about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** **** Exercise: 1 star, optional (tree) *)
(** Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
Check tree_ind.
(* tree_ind
: forall (X : Type) (P : tree X -> Prop),
(forall x : X, P (leaf X x)) ->
(forall t : tree X, P t -> forall t0 : tree X, P t0 -> P (node X t t0)) ->
forall t : tree X, P t *)
(** [] *)
(** **** Exercise: 1 star, optional (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
Inductive mytype (X:Type) : Type :=
| constr1 : X -> mytype X
| constr2 : nat -> mytype X
| constr3 : mytype X -> nat -> mytype X
.
Check mytype_ind.
(* mytype_ind
: forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m -> forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m *)
(** [] *)
(** **** Exercise: 1 star, optional (foo) *)
(** Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
Inductive foo (X Y : Type) : Type :=
| bar : X -> foo X Y
| baz : Y -> foo X Y
| quux : (nat -> foo X Y) -> foo X Y
.
Check foo_ind.
(* foo_ind
: forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2 *)
(** [] *)
(** **** Exercise: 1 star, optional (foo') *)
(** Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(** What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
Check foo'_ind.
(* foo'_ind
: forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X), P f -> P (C1 X l f)) ->
P (C2 X) ->
forall f1 : foo' X, P f1 *)
(** [] *)
(* ##################################################### *)
(** ** Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently... *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** Now when we do the proof it is easier to see where [P_m0r]
appears. *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
Case "n = O". reflexivity.
Case "n = S n'".
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(** This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ##################################################### *)
(** ** More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative...
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
Case "n = O". intros m. rewrite -> plus_0_r. reflexivity.
Case "n = S n'". intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m'].
Case "m = O". simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
Theorem plus_assoc'' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
intros.
generalize dependent n.
apply nat_ind.
reflexivity.
intros.
simpl. rewrite H. reflexivity.
Qed.
Theorem plus_comm''' : forall n m : nat,
n + m = m + n.
Proof.
intro n.
apply nat_ind.
rewrite plus_0_r. reflexivity.
intros. rewrite <-plus_n_Sm. rewrite H. reflexivity.
Qed.
(** [] *)
(** ** Generalizing Inductions. *)
(** One potentially confusing feature of the [induction] tactic is
that it happily lets you try to set up an induction over a term
that isn't sufficiently general. The net effect of this will be
to lose information (much as [destruct] can do), and leave
you unable to complete the proof. Here's an example: *)
Lemma one_not_beautiful_FAILED: ~ beautiful 1.
Proof.
intro H.
(* Just doing an [inversion] on [H] won't get us very far in the [b_sum]
case. (Try it!). So we'll need induction. A naive first attempt: *)
induction H.
(* But now, although we get four cases, as we would expect from
the definition of [beautiful], we lose all information about [H] ! *)
Abort.
(** The problem is that [induction] over a Prop only works properly over
completely general instances of the Prop, i.e. one in which all
the arguments are free (unconstrained) variables.
In this respect it behaves more
like [destruct] than like [inversion].
When you're tempted to do use [induction] like this, it is generally
an indication that you need to be proving something more general.
But in some cases, it suffices to pull out any concrete arguments
into separate equations, like this: *)
Lemma one_not_beautiful: forall n, n = 1 -> ~ beautiful n.
Proof.
intros n E H.
induction H as [| | | p q Hp IHp Hq IHq].
Case "b_0".
inversion E.
Case "b_3".
inversion E.
Case "b_5".
inversion E.
Case "b_sum".
(* the rest is a tedious case analysis *)
destruct p as [|p'].
SCase "p = 0".
destruct q as [|q'].
SSCase "q = 0".
inversion E.
SSCase "q = S q'".
apply IHq. apply E.
SCase "p = S p'".
destruct q as [|q'].
SSCase "q = 0".
apply IHp. rewrite plus_0_r in E. apply E.
SSCase "q = S q'".
simpl in E. inversion E. destruct p'. inversion H0. inversion H0.
Qed.
(** There's a handy [remember] tactic that can generate the second
proof state out of the original one. *)
Lemma one_not_beautiful': ~ beautiful 1.
Proof.
intros H.
remember 1 as n eqn:E.
(* now carry on as above *)
induction H.
Admitted.
(* ####################################################### *)
(** * Informal Proofs (Advanced) *)
(** Q: What is the relation between a formal proof of a proposition
[P] and an informal proof of the same proposition [P]?
A: The latter should _teach_ the reader how to produce the
former.
Q: How much detail is needed??
Unfortunately, There is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the informal proof amounts to just
transcribing the formal one into words). This gives the reader
the _ability_ to reproduce the formal one for themselves, but it
doesn't _teach_ them anything.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because
usually writing the proof requires some deep insights into the
thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard part of work
that we went through to find the proof in the first place) and
clear high-level suggestions for the more routine parts to save the
reader from spending too much time reconstructing these
parts (e.g., what the IH says and what must be shown in each case
of an inductive proof), but not so much detail that the main ideas
are obscured.
Another key point: if we're comparing a formal proof of a
proposition [P] and an informal proof of [P], the proposition [P]
doesn't change. That is, formal and informal proofs are _talking
about the same world_ and they _must play by the same rules_. *)
(** ** Informal Proofs by Induction *)
(** Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief
and telegraphic. The ideal is somewhere in between, of course,
but while you are getting used to the style it is better to start
out at the pedantic end. Also, during the learning phase, it is
probably helpful to have a clear standard to compare against.
With this in mind, we offer two templates below -- one for proofs
by induction over _data_ (i.e., where the thing we're doing
induction on lives in [Type]) and one for proofs by induction over
_evidence_ (i.e., where the inductively defined thing lives in
[Prop]). In the rest of this course, please follow one of the two
for _all_ of your inductive proofs. *)
(** *** Induction Over an Inductively Defined Set *)
(** _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if length [[] = n], then [index (S n) [] =
None].
This follows immediately from the definition of index.
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be length [l']. [] *)
(** *** Induction Over an Inductively Defined Proposition *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(* ##################################################### *)
(** * Optional Material *)
(** The remainder of this chapter offers some additional details on
how induction works in Coq, the process of building proof
trees, and the "trusted computing base" that underlies
Coq proofs. It can safely be skimmed on a first reading. (We
recommend skimming rather than skipping over it outright: it
answers some questions that occur to many Coq users at some point,
so it is useful to have a rough idea of what's here.) *)
(* ##################################################### *)
(** ** Induction Principles in [Prop] *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [gorgeous]
are a tiny bit more complicated. As with all induction
principles, we want to use the induction principle on [gorgeous]
to prove things by inductively considering the possible shapes
that something in [gorgeous] can have -- either it is evidence
that [0] is gorgeous, or it is evidence that, for some [n], [3+n]
is gorgeous, or it is evidence that, for some [n], [5+n] is
gorgeous and it includes evidence that [n] itself is. Intuitively
speaking, however, what we want to prove are not statements about
_evidence_ but statements about _numbers_. So we want an
induction principle that lets us prove properties of numbers by
induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [gorgeous]...
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+m)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+m).
...to give rise to an induction principle that looks like this...
gorgeous_ind_max :
forall P : (forall n : nat, gorgeous n -> Prop),
P O g_0 ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (3+m) (g_plus3 m e) ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (5+m) (g_plus5 m e) ->
forall (n : nat) (e : gorgeous n), P n e
... because:
- Since [gorgeous] is indexed by a number [n] (every [gorgeous]
object [e] is a piece of evidence that some particular number
[n] is gorgeous), the proposition [P] is parameterized by both
[n] and [e] -- that is, the induction principle can be used to
prove assertions involving both a gorgeous number and the
evidence that it is gorgeous.
- Since there are three ways of giving evidence of gorgeousness
([gorgeous] has three constructors), applying the induction
principle generates three subgoals:
- We must prove that [P] holds for [O] and [b_0].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [3+m] and [g_plus3 n e].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [5+m] and [g_plus5 n e].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ gorgeous numbers [n] and
evidence [e] of their gorgeousness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
gorgeousness, while all we really care about is proving
properties of _numbers_ that are gorgeous -- we are interested in
assertions about numbers, not about evidence. It would therefore
be more convenient to have an induction principle for proving
propositions [P] that are parameterized just by [n] and whose
conclusion establishes [P] for all gorgeous numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat, gorgeous n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [gorgeous]: *)
Check gorgeous_ind.
(* ===> gorgeous_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, gorgeous n -> P n -> P (3 + n)) ->
(forall n : nat, gorgeous n -> P n -> P (5 + n)) ->
forall n : nat, gorgeous n -> P n *)
(** In particular, Coq has dropped the evidence term [e] as a
parameter of the the proposition [P], and consequently has
rewritten the assumption [forall (n : nat) (e: gorgeous n), ...]
to be [forall (n : nat), gorgeous n -> ...]; i.e., we no longer
require explicit evidence of the provability of [gorgeous n]. *)
(** In English, [gorgeous_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is gorgeous, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [3+n],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [5+n]. *)
(** As expected, we can apply [gorgeous_ind] directly instead of using [induction]. *)
Theorem gorgeous__beautiful' : forall n, gorgeous n -> beautiful n.
Proof.
intros.
apply gorgeous_ind.
Case "g_0".
apply b_0.
Case "g_plus3".
intros.
apply b_sum. apply b_3.
apply H1.
Case "g_plus5".
intros.
apply b_sum. apply b_5.
apply H1.
apply H.
Qed.
(** The precise form of an Inductive definition can affect the
induction principle Coq generates.
For example, in [Logic], we have defined [<=] as: *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(** By contrast, the induction principle that Coq calculates for the
first definition has a lot of extra quantifiers, which makes it
messier to work with when proving things by induction. Here is
the induction principle for the first [le]: *)
(* le_ind :
forall P : nat -> nat -> Prop,
(forall n : nat, P n n) ->
(forall n m : nat, le n m -> P n m -> P n (S m)) ->
forall n n0 : nat, le n n0 -> P n n0 *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** Suppose we make the following inductive definition:
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
Fill in the blanks to complete the induction principle that will be
generated by Coq.
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
*)
Inductive foo'' (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo'' X Y
| foo2 : Y -> foo'' X Y
| foo3 : foo'' X Y -> foo'' X Y.
Check foo''_ind.
(* foo''_ind
: forall (X Y : Set) (P : foo'' X Y -> Prop),
(forall x : X, P (foo1 X Y x)) ->
(forall y : Y, P (foo2 X Y y)) ->
(forall f1 : foo'' X Y, P f1 -> P (foo3 X Y f1)) ->
forall f2 : foo'' X Y, P f2 *)
(** [] *)
(** **** Exercise: 2 stars, optional (bar_ind_principle) *)
(** Consider the following induction principle:
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
Write out the corresponding inductive set definition.
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
*)
Inductive bar' : Set :=
| bar'1 : nat -> bar'
| bar'2 : bar' -> bar'
| bar'3 : bool -> bar' -> bar'.
Check bar'_ind.
(* bar'_ind
: forall P : bar' -> Prop,
(forall n : nat, P (bar'1 n)) ->
(forall b : bar', P b -> P (bar'2 b)) ->
(forall (b : bool) (b0 : bar'), P b0 -> P (bar'3 b b0)) ->
forall b : bar', P b *)
(** [] *)
(** **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** Given the following inductively defined proposition:
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
write the induction principle generated by Coq.
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
*)
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
Check no_longer_than_ind.
(* no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, P [] n) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> P l n -> P (x :: l) (S n)) ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> P l n -> P l (S n)) ->
forall (l : list X) (n : nat), no_longer_than X l n -> P l n *)
(** [] *)
(* ##################################################### *)
(** ** Induction Principles for other Logical Propositions *)
(** Similarly, in [Logic] we have defined [eq] as: *)
(* Inductive eq (X:Type) : X -> X -> Prop :=
refl_equal : forall x, eq X x x. *)
(** In the Coq standard library, the definition of equality is
slightly different: *)
Inductive eq' (X:Type) (x:X) : X -> Prop :=
refl_equal' : eq' X x x.
(** The advantage of this definition is that the induction
principle that Coq derives for it is precisely the familiar
principle of _Leibniz equality_: what we mean when we say "[x] and
[y] are equal" is that every property on [P] that is true of [x]
is also true of [y]. *)
Check eq'_ind.
(* ===>
forall (X : Type) (x : X) (P : X -> Prop),
P x -> forall y : X, x =' y -> P y
===> (i.e., after a little reorganization)
forall (X : Type) (x : X) forall y : X,
x =' y ->
forall P : X -> Prop, P x -> P y *)
(** The induction principles for conjunction and disjunction are a
good illustration of Coq's way of generating simplified induction
principles for [Inductive]ly defined propositions, which we
discussed above. You try first: *)
(** **** Exercise: 1 star, optional (and_ind_principle) *)
(** See if you can predict the induction principle for conjunction. *)
Check and_ind.
(** [] *)
(** **** Exercise: 1 star, optional (or_ind_principle) *)
(** See if you can predict the induction principle for disjunction. *)
Check or_ind.
(** [] *)
Check and_ind.
(** From the inductive definition of the proposition [and P Q]
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
we might expect Coq to generate this induction principle
and_ind_max :
forall (P Q : Prop) (P0 : P /\ Q -> Prop),
(forall (a : P) (b : Q), P0 (conj P Q a b)) ->
forall a : P /\ Q, P0 a
but actually it generates this simpler and more useful one:
and_ind :
forall P Q P0 : Prop,
(P -> Q -> P0) ->
P /\ Q -> P0
In the same way, when given the inductive definition of [or P Q]
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
instead of the "maximal induction principle"
or_ind_max :
forall (P Q : Prop) (P0 : P \/ Q -> Prop),
(forall a : P, P0 (or_introl P Q a)) ->
(forall b : Q, P0 (or_intror P Q b)) ->
forall o : P \/ Q, P0 o
what Coq actually generates is this:
or_ind :
forall P Q P0 : Prop,
(P -> P0) ->
(Q -> P0) ->
P \/ Q -> P0
]]
*)
(** **** Exercise: 1 star, optional (False_ind_principle) *)
(** Can you predict the induction principle for falsehood? *)
Check False_ind.
(* False_ind
: forall P : Prop, False -> P *)
(** [] *)
(** Here's the induction principle that Coq generates for existentials: *)
Check ex_ind.
(* ex_ind
: forall (X : Type) (P : X -> Prop) (P0 : Prop),
(forall witness : X, P witness -> P0) -> (exists x, P x) -> P0 *)
(* ===> forall (X:Type) (P: X->Prop) (Q: Prop),
(forall witness:X, P witness -> Q) ->
ex X P ->
Q *)
(** This induction principle can be understood as follows: If we have
a function [f] that can construct evidence for [Q] given _any_
witness of type [X] together with evidence that this witness has
property [P], then from a proof of [ex X P] we can extract the
witness and evidence that must have been supplied to the
constructor, give these to [f], and thus obtain a proof of [Q]. *)
(* ######################################################### *)
(** ** Explicit Proof Objects for Induction *)
(** Although tactic-based proofs are normally much easier to
work with, the ability to write a proof term directly is sometimes
very handy, particularly when we want Coq to do something slightly
non-standard. *)
(** Recall the induction principle on naturals that Coq generates for
us automatically from the Inductive declation for [nat]. *)
Check nat_ind.
(* ===>
nat_ind : forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** There's nothing magic about this induction lemma: it's just
another Coq lemma that requires a proof. Coq generates the proof
automatically too... *)
Print nat_ind.
Print nat_rect.
(* ===> (after some manual inlining and tidying)
nat_ind =
fun (P : nat -> Prop)
(f : P 0)
(f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n with
| 0 => f
| S n0 => f0 n0 (F n0)
end.
*)
(** We can read this as follows:
Suppose we have evidence [f] that [P] holds on 0, and
evidence [f0] that [forall n:nat, P n -> P (S n)].
Then we can prove that [P] holds of an arbitrary nat [n] via
a recursive function [F] (here defined using the expression
form [Fix] rather than by a top-level [Fixpoint]
declaration). [F] pattern matches on [n]:
- If it finds 0, [F] uses [f] to show that [P n] holds.
- If it finds [S n0], [F] applies itself recursively on [n0]
to obtain evidence that [P n0] holds; then it applies [f0]
on that evidence to show that [P (S n)] holds.
[F] is just an ordinary recursive function that happens to
operate on evidence in [Prop] rather than on terms in [Set].
*)
(** We can adapt this approach to proving [nat_ind] to help prove
_non-standard_ induction principles too. Recall our desire to
prove that
[forall n : nat, even n -> ev n].
Attempts to do this by standard induction on [n] fail, because the
induction principle only lets us proceed when we can prove that
[even n -> even (S n)] -- which is of course never provable. What
we did in [Logic] was a bit of a hack:
[Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n))].
We can make a much better proof by defining and proving a
non-standard induction principle that goes "by twos":
*)
Definition nat_ind2 :
forall (P : nat -> Prop),
P 0 ->
P 1 ->
(forall n : nat, P n -> P (S(S n))) ->
forall n : nat , P n :=
fun P => fun P0 => fun P1 => fun PSS =>
fix f (n:nat) := match n with
0 => P0
| 1 => P1
| S (S n') => PSS n' (f n')
end.
(** Once you get the hang of it, it is entirely straightforward to
give an explicit proof term for induction principles like this.
Proving this as a lemma using tactics is much less intuitive (try
it!).
The [induction ... using] tactic variant gives a convenient way to
specify a non-standard induction principle like this. *)
Lemma even__ev' : forall n, even n -> ev n.
Proof.
intros.
induction n as [ | |n'] using nat_ind2.
Case "even 0".
apply ev_0.
Case "even 1".
inversion H.
Case "even (S(S n'))".
apply ev_SS.
apply IHn'. unfold even. unfold even in H. simpl in H. apply H.
Qed.
(* ######################################################### *)
(** ** The Coq Trusted Computing Base *)
(** One issue that arises with any automated proof assistant is "why
trust it?": what if there is a bug in the implementation that
renders all its reasoning suspect?
While it is impossible to allay such concerns completely, the fact
that Coq is based on the Curry-Howard correspondence gives it a
strong foundation. Because propositions are just types and proofs
are just terms, checking that an alleged proof of a proposition is
valid just amounts to _type-checking_ the term. Type checkers are
relatively small and straightforward programs, so the "trusted
computing base" for Coq -- the part of the code that we have to
believe is operating correctly -- is small too.
What must a typechecker do? Its primary job is to make sure that
in each function application the expected and actual argument
types match, that the arms of a [match] expression are constructor
patterns belonging to the inductive type being matched over and
all arms of the [match] return the same type, and so on.
There are a few additional wrinkles:
- Since Coq types can themselves be expressions, the checker must
normalize these (by using the computation rules) before
comparing them.
- The checker must make sure that [match] expressions are
_exhaustive_. That is, there must be an arm for every possible
constructor. To see why, consider the following alleged proof
object:
Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
All the types here match correctly, but the [match] only
considers one of the possible constructors for [or]. Coq's
exhaustiveness check will reject this definition.
- The checker must make sure that each [fix] expression
terminates. It does this using a syntactic check to make sure
that each recursive call is on a subexpression of the original
argument. To see why this is essential, consider this alleged
proof:
Definition nat_false : forall (n:nat), False :=
fix f (n:nat) : False := f n.
Again, this is perfectly well-typed, but (fortunately) Coq will
reject it. *)
(** Note that the soundness of Coq depends only on the correctness of
this typechecking engine, not on the tactic machinery. If there
is a bug in a tactic implementation (and this certainly does
happen!), that tactic might construct an invalid proof term. But
when you type [Qed], Coq checks the term for validity from
scratch. Only lemmas whose proofs pass the type-checker can be
used in further proof developments. *)
(* $Date: 2014-06-05 05:22:21 -0600 (Thu, 05 Jun 2014) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_PP_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRBP_BEHAVIORAL_PP_V
|
// ======================================================================
// DES encryption/decryption testbench
// tests according to NIST 800-17 special publication
// Copyright (C) 2012 Torsten Meissner
//-----------------------------------------------------------------------
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
// ======================================================================
`timescale 1ns/1ps
module tb_cbcdes;
// set dumpfile
initial begin
$dumpfile ("tb_cbcdes.vcd");
$dumpvars (0, tb_cbcdes);
end
reg reset;
reg clk = 0;
reg mode;
reg [0:63] key;
reg [0:63] datain;
reg validin;
reg start;
reg [0:63] iv;
wire [0:63] dataout;
wire validout;
wire readyout;
integer index;
integer outdex;
integer enc_errors;
integer dec_errors;
reg [0:63] data_input [0:469];
reg [0:63] key_input [0:469];
reg [0:63] data_output [0:469];
// read in test data files
initial begin
$readmemh("data_input.txt", data_input);
$readmemh("key_input.txt", key_input);
$readmemh("data_output.txt", data_output);
end
// setup simulation
initial begin
reset = 1;
#1 reset = 0;
#20 reset = 1;
end
// generate clock with 100 mhz
always #5 clk = !clk;
// stimuli generator process
initial
forever @(negedge reset) begin
@(posedge clk)
for (index = 0; index < 235; index = index + 1)
begin
@(posedge clk)
mode <= 0;
validin <= 1;
datain <= data_input[index];
key <= key_input[index];
end
for (index = 0; index < 10; index = index + 1)
begin
@(posedge clk)
validin <= 0;
end
for (index = 235; index < 470; index = index + 1)
begin
@(posedge clk)
mode <= 1;
validin <= 1;
datain <= data_input[index];
key <= key_input[index];
end
@(posedge clk)
validin <= 0;
mode <= 0;
end
// checker process
always begin : checker
wait (reset)
// encryption tests
@(posedge validout)
for(outdex = 0; outdex < 235; outdex = outdex + 1)
begin
@(posedge clk)
// detected an error -> print error message
// increment error counter
if (dataout != data_output[outdex]) begin
$display ("error, output was %h - should have been %h", dataout, data_output[outdex]);
enc_errors = enc_errors + 1;
end
end
// simulation finished -> print messages and if an error was detected
$display ("#############");
if (enc_errors) begin
$display ("encryption tests finished, %0d errors detected :(", enc_errors);
end else begin
$display ("encryption tests finished, no errors detected :)");
end
// decryption tests
@(posedge validout)
for(outdex = 235; outdex < 470; outdex = outdex + 1)
begin
@(posedge clk)
// detected an error -> print error message
// increment error counter
if (dataout != data_output[outdex]) begin
$display ("error, output was %h - should have been %h", dataout, data_output[outdex]);
dec_errors = dec_errors + 1;
end
end
// simulation finished -> print messages and if an error was detected
$display ("#############");
if (dec_errors) begin
$display ("decryption tests finished, %0d errors detected :(", dec_errors);
end else begin
$display ("decryption tests finished, no errors detected :)");
end
$display ("#############");
if (dec_errors | enc_errors) begin
$display ("simulation finished, %0d errors detected :(", enc_errors + dec_errors);
end else begin
$display ("simulation tests finished, no errors detected :)");
end
$display ("#############");
@(posedge clk)
$finish;
end
// dut
cbcdes i_cbcdes (
.reset_i(reset),
.clk_i(clk),
.start_i(start),
.mode_i(mode),
.key_i(key),
.iv_i(iv),
.data_i(datain),
.valid_i(validin),
.ready_o(readyout),
.data_o(dataout),
.valid_o(validout)
);
endmodule
|
//Copyright 2014 Zeno Futurista ([email protected])
//
//Licensed under the Apache License, Version 2.0 (the "License");
//you may not use this file except in compliance with the License.
//You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//Unless required by applicable law or agreed to in writing, software
//distributed under the License is distributed on an "AS IS" BASIS,
//WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
//See the License for the specific language governing permissions and
//limitations under the License.
//behold :)
module hmac_prescrypt(input clk, input doWork, input [7:0] available, input [7:0] in[0:79], input [31:0] job, output reg[7:0] scryptResultOut[0:127], output reg[31:0] scryptResultJobOut, output reg[31:0] scryptResultNonceOut, output reg[31:0] scryptPadOut[0:7], output reg scryptResultAvailable);
//unroll parameter
parameter unroll = 64;
//sha initial digest constant
wire [31:0] H [0:7];
//initial digest (sha state)
assign H = '{32'h6a09e667, 32'hbb67ae85, 32'h3c6ef372, 32'ha54ff53a, 32'h510e527f, 32'h9b05688c, 32'h1f83d9ab, 32'h5be0cd19};
//actual work registers
reg[7:0] workBuffer[0:79];
reg[31:0] currentJob;
reg midstateReady;
reg[31:0] midstate[0:7];
//signals that there is task to be scheduled
reg scheduleTask;
//interconnection wires and regs for first pipeline follow
//task state wire and reg
reg[31:0] stateOut;
wire[31:0] stateIn;
//digest wires and registers
reg[31:0] digestOut[0:7];
reg[31:0] padOut[0:7];
reg[31:0] digestOutOriginal[0:7];
wire [31:0] digestIn [0:7];
wire [31:0] padIn [0:7];
wire [31:0] digestInOriginal [0:7];
//wires for first phase midstate computation
//second part with 12 header bytes + nonce and padding
wire[7:0] firstStageSecondPart[0:63];
wire[7:0] midstateSecondPart[0:63];
//used for words
reg[31:0] wordsOut[0:15];
wire[31:0] wordsIn[0:15];
//nonce vars
reg[31:0] nonceOut;
wire[31:0] nonceIn;
//job vars
reg[31:0] jobOut;
wire[31:0] jobIn;
//pipeline for first part of computation
hmac_pipeline #(unroll) hmacp(clk, stateOut, digestOut, digestOutOriginal, wordsOut, jobOut, nonceOut, padOut, digestIn, digestInOriginal, wordsIn, stateIn, jobIn, nonceIn, padIn);
//digest stored for one stage cycle in the middle of computation
wire[31:0] midDigestOut[0:7];
hmacqueue #(.elementWidth(32), .elementCount(8), .depth(unroll + 1)) dq(clk, secondBlockPartReady, opadHashed, newDigest, midDigestOut);
//new nonce register
reg[31:0] newNonce;
//work counter
reg[2:0] workCounter;
reg [7:0] preparing;
//combinationals needed to assemble new data to hash (paddings, nonces...)
wire[7:0] blockPadding[0:63];
wire[7:0] midDigestPadding[0:63];
wire [31:0] newDigest[0:7];
always @(*) begin
for(int i =0; i < 8; i++) begin
newDigest[i] = (digestIn[i] + digestInOriginal[i]);
end
//this is maybe not the best way to set things up, but i find this way readable and easy to understand
firstStageSecondPart[0:11] = workBuffer[64:75];
//assembly nonce for new sha hashing
firstStageSecondPart[8'd15] = newNonce;
firstStageSecondPart[8'd14] = (newNonce >>> 8);
firstStageSecondPart[8'd13] = (newNonce >>> 16);
firstStageSecondPart[8'd12] = (newNonce >>> 24);
//padding to 128 bytes of 80B input (first stage second sha part)
firstStageSecondPart[8'd16] = 128;
for(int i =1; i < 46; i++) begin
firstStageSecondPart[16+i] = 0;
end
firstStageSecondPart[8'd62] = 2;
firstStageSecondPart[8'd63] = 128;
midstateSecondPart[0:11] = firstStageSecondPart[0:11];
midstateSecondPart[8'd15] = nonceIn;
midstateSecondPart[8'd14] = (nonceIn >>> 8);
midstateSecondPart[8'd13] = (nonceIn >>> 16);
midstateSecondPart[8'd12] = (nonceIn >>> 24);
midstateSecondPart[16:63] = firstStageSecondPart[16:63];
//extended block padding
blockPadding[0:11] = workBuffer[64:75];
blockPadding[8'd15] = nonceIn;
blockPadding[8'd14] = (nonceIn >>> 8);
blockPadding[8'd13] = (nonceIn >>> 16);
blockPadding[8'd12] = (nonceIn >>> 24);
blockPadding[8'd16] = 0;
blockPadding[8'd17] = 0;
blockPadding[8'd18] = 0;
blockPadding[8'd19] = stateIn[18:16];
blockPadding[8'd20] = 8'd128;
for(int i =21; i < 60; i++) begin
blockPadding[i] = 8'd0;
end
blockPadding[8'd60] = 0;
blockPadding[8'd61] = 0;
blockPadding[8'd62] = 4;
blockPadding[8'd63] = 160;
//opad and first part digest padding
for(int i =0; i < 8; i++) begin
midDigestPadding[i*4 + 3] = midDigestOut[i];
midDigestPadding[i*4 + 2] = (midDigestOut[i] >>> 8);
midDigestPadding[i*4 + 1] = (midDigestOut[i] >>> 16);
midDigestPadding[i*4] = (midDigestOut[i] >>> 24);
end
midDigestPadding[32] = 128;
for(int i =33; i < 60; i++) begin
midDigestPadding[i] = 0;
end
midDigestPadding[60] = 0;
midDigestPadding[61] = 0;
midDigestPadding[62] = 3;
midDigestPadding[63] = 0;
end
//some states to be easilly readable
wire pipelineWorkIn = stateIn[31] & (jobIn == currentJob);
wire pipelineReady = (~pipelineWorkIn | resultReady);
wire midstateStageReady = (stateIn[15:0] == 64) & (jobIn == currentJob);
wire paddingReady = (stateIn[15:0] == 128) & (jobIn == currentJob);
wire ipadHashed = (stateIn[15:0] == 192) & (jobIn == currentJob);
wire firstBlockPartReady = (stateIn[15:0] == 256) & (jobIn == currentJob);
wire secondBlockPartReady = (stateIn[15:0] == 320) & (jobIn == currentJob);
wire opadHashed = ((stateIn[15:0] == 384) & (jobIn == currentJob)) | ((jobIn != currentJob) & (stateIn[15:0] > 320) & (stateIn[15:0] <= 384));
wire resultReady = (stateIn[15:0] == 448) & (jobIn == currentJob);
//without actual job control, better for performance
// wire pipelineWorkIn = stateIn[31];
// wire pipelineReady = (~pipelineWorkIn | resultReady);
//
// wire midstateStageReady = (stateIn[15:0] == 64);
// wire paddingReady = (stateIn[15:0] == 128);
// wire ipadHashed = (stateIn[15:0] == 192);
// wire firstBlockPartReady = (stateIn[15:0] == 256);
// wire secondBlockPartReady = (stateIn[15:0] == 320);
// wire opadHashed = ((stateIn[15:0] == 384));
// wire resultReady = (stateIn[15:0] == 448);
// & (jobIn == currentJob)
reg decreasePrepare;
always@(posedge clk) begin
if(doWork) begin
//set new data
workBuffer <= in;
//set new job
currentJob <= job;
//reset nonce
//concatenation of input bytes in header
newNonce <= {in[76],in[77],in[78],in[79]};
//new midstate must be computed
midstateReady <= 0;
//if there is job control, we can null preparing counter
preparing <= 0;
//set schedule flag
scheduleTask <= 1;
//null work counter
workCounter <= 0;
end
if(pipelineReady) begin
if(scheduleTask & (preparing < available)) begin
//now we can schedule task, there is something to do! :) as always in life!
if(~midstateReady) begin
//begining of new work - there is no midstate known
//midstate is the same result of first 64 bytes part sha transform; (because of nonce, which changes, lies at bytes 76-79 [zero index])
//--> concatenation
for(int i =0; i<16; i++) begin
wordsOut[i] <= (workBuffer[4*i] <<< 24) | (workBuffer[4*i + 1] <<< 16) | (workBuffer[4*i + 2] <<< 8) | (workBuffer[4*i + 3]);
end
//empty pad out
for(int i =0; i<8; i++) begin
padOut[i] <= 0;
end
//set state variables
stateOut[31] <= 1;
stateOut[15:0] <= 0;
//set up other job infos
jobOut <= currentJob;
nonceOut <= newNonce;
//there are four jobs queued for one nonce - this prescrypt hmac part outputs 128 bytes
//work counter signals when it is needed to nonce
stateOut[18:16] <= workCounter + 1'h1;
if(workCounter == 3) begin
workCounter <= 0;
newNonce <= newNonce + 1;
if(newNonce == (32'hffffffff)) begin
scheduleTask <= 0;
end
end else begin
workCounter <= workCounter + 1'd1;
end
//set initial digest
digestOut <= H;
digestOutOriginal <= H;
end else begin
//new work scheduling is in stage, where midstate is known (first sha done)
stateOut[31] <= 1;
for(int i =0; i<8; i++) begin
padOut[i] <= 0;
end
//set digest from midstate
digestOut <= midstate;
digestOutOriginal <= midstate;
//set job info
jobOut <= currentJob;
nonceOut <= newNonce;
//use data out assembly, that generates new second part of first sha (few bytes from header with changing nonce + padding)
//this is in fact some kind of concatenation
for(int i =0; i<16; i++) begin
wordsOut[i] <= (firstStageSecondPart[4*i] <<< 24) | (firstStageSecondPart[4*i + 1] <<< 16) | (firstStageSecondPart[4*i + 2] <<< 8) | (firstStageSecondPart[4*i + 3]);
end
//there are four jobs queued for one nonce - this prescrypt hmac part outputs 128 bytes
//work counter signals when it is needed to nonce
stateOut[18:16] <= workCounter + 1'd1;
if(workCounter == 3) begin
workCounter <= 0;
newNonce <= newNonce + 1;
if(newNonce == (32'hffffffff)) begin
scheduleTask <= 0;
end
end else begin
workCounter <= workCounter + 1'd1;
end
//we continue from state 64 (midstate is known)
stateOut[15:0] <= 64;
end
end else begin
//otherwise fill pipeline with zeros
stateOut <= 0;
jobOut <= 0;
nonceOut <= 0;
for(int i = 0; i < 16; i++) begin
wordsOut[i] <= 0;
end
for(int i = 0; i < 8; i++) begin
digestOut[i] <= 0;
digestOutOriginal[i] <= 0;
end
for(int i =0; i<8; i++) begin
padOut[i] <= 0;
end
end
end
if(pipelineWorkIn) begin
if(midstateStageReady) begin
//this state is possible only at the several beginning cycles, when there is no midstate...
//continue to second data part and set midstate, so that we do not need to go trough this stage for this job anymore
digestOut <= newDigest;
digestOutOriginal <= newDigest;
midstate <= newDigest;
//second part of data mix stored in queue
//concatenate/assemble words variable
for(int i =0; i<16; i++) begin
wordsOut[i] <= (midstateSecondPart[4*i] <<< 24) | (midstateSecondPart[4*i + 1] <<< 16) | (midstateSecondPart[4*i + 2] <<< 8) | (midstateSecondPart[4*i + 3]);
end
//set job info states etc.
stateOut <= stateIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
padOut <= padIn;
//mark midstate ready for this job
midstateReady <= 1;
end else if(paddingReady) begin
//opad and ipad source is now ready, do hash on ipad
//reset digest
digestOut <= H;
digestOutOriginal <= H;
jobOut <= jobIn;
nonceOut <= nonceIn;
stateOut <= stateIn;
//set up words.
//new digest is padding source, xor it with ipad constant (0x36)
for(int i =0; i < 8; i++) begin
padOut[i] <= newDigest[i];
wordsOut[i] <= newDigest[i] ^ 32'h36363636;
wordsOut[8+i] <= 32'h36363636;
end
end else if(ipadHashed) begin
//ipad is hashed, continue with block data
digestOut <= newDigest;
digestOutOriginal <= newDigest;
//set state variables
stateOut <= stateIn;
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
//set up words.
//concatenate block data from work buffer, first part
for(int i =0; i<16; i++) begin
wordsOut[i] <= (workBuffer[4*i] <<< 24) | (workBuffer[4*i + 1] <<< 16) | (workBuffer[4*i + 2] <<< 8) | (workBuffer[4*i + 3]);
end
end else if(firstBlockPartReady) begin
//firs block part is hashed, continue with secon padded part and new digest
digestOut <= newDigest;
digestOutOriginal <= newDigest;
//set state variables
stateOut <= stateIn;
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
//set up words.
//concatenate second padded part of block data
for(int i =0; i<16; i++) begin
wordsOut[i] <= (blockPadding[4*i] <<< 24) | (blockPadding[4*i + 1] <<< 16) | (blockPadding[4*i + 2] <<< 8) | (blockPadding[4*i + 3]);
end
end else if(secondBlockPartReady) begin
//second padded part of block is hashed now, its digest is also stored to queue
//reset digest
digestOut <= H;
digestOutOriginal <= H;
//set state variables
stateOut <= stateIn;
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
//set up words.
//xor pad source so that we obtain opad
for(int i =0; i < 8; i++) begin
wordsOut[i] <= padIn[i] ^ 32'h5C5C5C5C;
wordsOut[8+i] <= 32'h5C5C5C5C;
end
end else if(opadHashed) begin
//opad part hash is ready, continue mixing with current digest
digestOut <= newDigest;
digestOutOriginal <= newDigest;
//set state variables
stateOut <= stateIn;
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
//set up words.
//words are filled from padded stored digest from middle hmac stage
for(int i =0; i<16; i++) begin
wordsOut[i] <= (midDigestPadding[4*i] <<< 24) | (midDigestPadding[4*i + 1] <<< 16) | (midDigestPadding[4*i + 2] <<< 8) | (midDigestPadding[4*i + 3]);
end
end else if(resultReady) begin
//one of final parts is ready
for(int i =0; i < 8; i++) begin
scryptResultOut[(stateIn[18:16] - 1)*32 + i*4 + 3] <= newDigest[i];
scryptResultOut[(stateIn[18:16] - 1)*32 + i*4 + 2] <= (newDigest[i] >>> 8);
scryptResultOut[(stateIn[18:16] - 1)*32 + i*4 + 1] <= (newDigest[i] >>> 16);
scryptResultOut[(stateIn[18:16] - 1)*32 + i*4] <= (newDigest[i] >>> 24);
end
scryptResultJobOut <= jobIn;
scryptResultNonceOut <= nonceIn;
scryptPadOut <= padIn;
end else begin
//some middle phase, continue mixing
wordsOut <= wordsIn;
digestOut <= digestIn;
digestOutOriginal <= digestInOriginal;
stateOut <= stateIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
padOut <= padIn;
end
end
//if result ready, signal it to module connected to output
if((resultReady & (stateIn[18:16] == 4))) begin
scryptResultAvailable <= 1;
//decrease prepare after one cycle - so connected module can react
//and change its available state - so that we do not begin with preparation too early
decreasePrepare <= 1;
end else begin
scryptResultAvailable <= 0;
decreasePrepare <= 0;
end
//increment preparing counter
if(pipelineReady & scheduleTask & (workCounter == 3) & ~decreasePrepare & ~doWork) begin
preparing <= preparing +1;
end
//it is safe now to decrease count of items being prepared
if(~(pipelineReady & scheduleTask & (workCounter == 3)) & decreasePrepare & ~doWork) begin
preparing <= preparing - 1;
end
end
endmodule
module hmac_postscrypt(input clk, input doWork, input [7:0] in[0:127], input [31:0] job, input [31:0] nonce, input[31:0] pad[0:7] , output reg[7:0] resultOut[0:31], output reg[31:0] resultJobOut, output reg[31:0] resultNonceOut, output reg resultAvailable);
//unroll parameter
parameter unroll = 4;
//sha initial digest constant
wire [31:0] H [0:7];
//initial digest (sha state)
assign H = '{32'h6a09e667, 32'hbb67ae85, 32'h3c6ef372, 32'ha54ff53a, 32'h510e527f, 32'h9b05688c, 32'h1f83d9ab, 32'h5be0cd19};
//actual work registers
reg[7:0] workBuffer[0:127];
reg[7:0] workFirstPart[0:63];
reg[7:0] workSecondPart[0:63];
reg[31:0] midstate[0:7];
//signals that there is task to be scheduled
reg scheduleTask;
//interconnection wires and regs for first pipeline follow
//task state wire and reg
reg[31:0] stateOut;
wire[31:0] stateIn;
//digest wires and registers
reg[31:0] digestOut[0:7];
reg[31:0] padOut[0:7];
reg[31:0] digestOutOriginal[0:7];
wire [31:0] digestIn [0:7];
wire [31:0] padIn [0:7];
wire [31:0] digestInOriginal [0:7];
//used for words
reg[31:0] wordsOut[0:15];
wire[31:0] wordsIn[0:15];
//nonce vars
reg[31:0] nonceOut;
wire[31:0] nonceIn;
//job vars
reg[31:0] jobOut;
wire[31:0] jobIn;
//pipeline for first part of computation
hmac_pipeline #(unroll) hmacp(clk, stateOut, digestOut, digestOutOriginal, wordsOut, jobOut, nonceOut, padOut, digestIn, digestInOriginal, wordsIn, stateIn, jobIn, nonceIn, padIn);
//work was scheduled to pipeline, so drop it
wire dropWork = pipelineReady & workAvailable;
wire[7:0] queuedWork[0:127];
wire [31:0] queuedPad [0:7];
wire [31:0] queuedJob;
wire [31:0] queuedNonce;
wire workAvailable;
//in the middle of process, we need to store digest for some time -> queue it
wire[31:0] midDigestOut[0:7];
hmacqueue #(.elementWidth(32), .elementCount(8), .depth(8)) dq(clk, blockPaddingReady, opadPartReady, newDigest, midDigestOut);
//we need to know block data later in computation process, so store it to queue
hmacqueue #(.elementWidth(8), .elementCount(64), .depth(8)) ws1(clk, doWork, ipadPartReady, in[0:63], workFirstPart);
hmacqueue #(.elementWidth(8), .elementCount(64), .depth(8)) ws2(clk, doWork, firstBlockPartReady, in[64:127], workSecondPart);
//queues/buffers work from scrypt mix (just in case there will be more inputs)
hmacqueue_packed #(.elementWidth(32), .depth(8)) jq(clk, doWork, dropWork, job, queuedJob);
hmacqueue_packed #(.elementWidth(32), .depth(8)) nq(clk, doWork, dropWork, nonce, queuedNonce);
hmacqueue #(.elementWidth(32), .elementCount(8), .depth(8)) pq(clk, doWork, dropWork, pad, queuedPad, workAvailable);
//combinationals needed to assemble new data to hash (paddings, nonces...)
wire[7:0] blockPadding[0:63];
wire[7:0] midDigestPadding[0:63];
wire [31:0] newDigest[0:7];
always @(*) begin
//new digest, needed usually in each stage of computation
for(int i =0; i < 8; i++) begin
newDigest[i] = (digestIn[i] + digestInOriginal[i]);
end
//ipad and block padding
blockPadding[0] = 0;
blockPadding[1] = 0;
blockPadding[2] = 0;
blockPadding[3] = 1;
blockPadding[4] = 128;
for(int i =5; i < 60; i++) begin
blockPadding[i] = 0;
end
blockPadding[60] = 0;
blockPadding[61] = 0;
blockPadding[62] = 6;
blockPadding[63] = 32;
//opad and first part digest padding
for(int i =0; i < 8; i++) begin
midDigestPadding[i*4 + 3] = midDigestOut[i];
midDigestPadding[i*4 + 2] = (midDigestOut[i] >>> 8);
midDigestPadding[i*4 + 1] = (midDigestOut[i] >>> 16);
midDigestPadding[i*4] = (midDigestOut[i] >>> 24);
end
midDigestPadding[32] = 128;
for(int i =33; i < 60; i++) begin
midDigestPadding[i] = 0;
end
midDigestPadding[60] = 0;
midDigestPadding[61] = 0;
midDigestPadding[62] = 3;
midDigestPadding[63] = 0;
end
//some state vars, just to be easily readable
wire pipelineWorkIn = stateIn[31];
wire pipelineReady = ~pipelineWorkIn | resultReady;
//translate states to something more readable
wire ipadPartReady = (stateIn[15:0] == 64);
wire firstBlockPartReady = (stateIn[15:0] == 128);
wire secondBlockPartReady = (stateIn[15:0] == 192);
wire blockPaddingReady = (stateIn[15:0] == 256);
wire opadPartReady = (stateIn[15:0] == 320);
wire resultReady = (stateIn[15:0] == 384);
always@(posedge clk) begin
if(pipelineReady) begin
if(workAvailable) begin
//now we can schedule new task, there is something to do! :) as always in life!
//--> concatenation
for(int i =0; i<8; i++) begin
wordsOut[i] <= queuedPad[i] ^ 32'h36363636;
wordsOut[8+i] <= 32'h36363636;
end
//set state variables
stateOut[31] <= 1;
stateOut[15:0] <= 0;
//set up other job infos
jobOut <= queuedJob;
nonceOut <= queuedNonce;
padOut <= queuedPad;
//set initial digest
digestOut <= H;
digestOutOriginal <= H;
end else begin
//otherwise fill pipeline with zeros
stateOut <= 0;
jobOut <= 0;
nonceOut <= 0;
for(int i = 0; i < 16; i++) begin
wordsOut[i] <= 0;
end
for(int i = 0; i < 8; i++) begin
digestOut[i] <= 0;
digestOutOriginal[i] <= 0;
end
for(int i =0; i<8; i++) begin
padOut[i] <= 0;
end
end
end
if(pipelineWorkIn) begin
if(ipadPartReady) begin
//first sha is complete (sha from ipad from first prescrypt hmac part),
//use its digest and scrypt output block data as next input
digestOut <= newDigest;
digestOutOriginal <= newDigest;
//continue shifting other states
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
stateOut <= stateIn;
//set up words.
//concatenate some bytes, could be written also like {x,x,x,x}, but copiler result is the same anyway
//work is from first shift
for(int i =0; i<16; i++) begin
wordsOut[i] <= (workFirstPart[4*i] <<< 24) | (workFirstPart[4*i + 1] <<< 16) | (workFirstPart[4*i + 2] <<< 8) | (workFirstPart[4*i + 3]);
end
end else if(firstBlockPartReady) begin
//first sha is complete, use its final digest and info as input for second sha pipeline
digestOut <= newDigest;
digestOutOriginal <= newDigest;
//set states
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
stateOut <= stateIn;
//set up words
//concatenate next work part, work from second longer shift
for(int i =0; i<16; i++) begin
wordsOut[i] <= (workSecondPart[4*i] <<< 24) | (workSecondPart[4*i + 1] <<< 16) | (workSecondPart[4*i + 2] <<< 8) | (workSecondPart[4*i + 3]);
end
end else if(secondBlockPartReady) begin
//second block digest ready, finish padding
digestOut <= newDigest;
digestOutOriginal <= newDigest;
//continue shifting other states
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
stateOut <= stateIn;
//set up words.
//concatenate some stages
for(int i =0; i<16; i++) begin
wordsOut[i] <= (blockPadding[4*i] <<< 24) | (blockPadding[4*i + 1] <<< 16) | (blockPadding[4*i + 2] <<< 8) | (blockPadding[4*i + 3]);
end
end else if(blockPaddingReady) begin
//second part of hmac, reset digest, process opad
digestOut <= H;
digestOutOriginal <= H;
//continue shifting other states
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
stateOut <= stateIn;
//set up opad words.
//create opad and set up words from it
for(int i =0; i < 8; i++) begin
wordsOut[i] <= padIn[i] ^ 32'h5C5C5C5C;
wordsOut[8+i] <= 32'h5C5C5C5C;
end
end else if(opadPartReady) begin
//opad hashed, and now finally process padded digest from middle stage
digestOut <= newDigest;
digestOutOriginal <= newDigest;
//set state variables
padOut <= padIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
stateOut <= stateIn;
//set up final words.
//concatenate mid digest to form new words
for(int i =0; i<16; i++) begin
wordsOut[i] <= (midDigestPadding[4*i] <<< 24) | (midDigestPadding[4*i + 1] <<< 16) | (midDigestPadding[4*i + 2] <<< 8) | (midDigestPadding[4*i + 3]);
end
end else if(resultReady) begin
//result is ready, whole cycle finished
for(int i =0; i < 8; i++) begin
resultOut[i*4 + 3] <= newDigest[i];
resultOut[i*4 + 2] <= (newDigest[i] >>> 8);
resultOut[i*4 + 1] <= (newDigest[i] >>> 16);
resultOut[i*4] <= (newDigest[i] >>> 24);
end
resultJobOut <= jobIn;
resultNonceOut <= nonceIn;
end else begin
//some middle phase, continue mixing
wordsOut <= wordsIn;
digestOut <= digestIn;
digestOutOriginal <= digestInOriginal;
stateOut <= stateIn;
jobOut <= jobIn;
nonceOut <= nonceIn;
padOut <= padIn;
end
end
//signal result available
resultAvailable <= resultReady;
end
endmodule
extern module parameterized_shift_unpacked #(parameter elementWidth = 8, parameter depth = 8, parameter elementCount = 64) (input clk, input [(elementWidth-1):0] in[0:(elementCount-1)], output [(elementWidth-1):0] out[0:(elementCount-1)]);
extern module sha_mix #(parameter N = 4)(input clk,input[15:0] indexIn, input [31:0] wordsIn[0:15], input [31:0] digestIn[0:7], output [31:0] digestOut[0:7],output [31:0] wordsOut[0:15], output[15:0] indexOut);
//I believe it is readable and easy to understand
module hmac_pipeline(input clk, input [31:0] stateIn, input[31:0] digestIn[0:7], input[31:0] digestInOriginal[0:7], input [31:0] wordsIn[0:15], input [31:0] jobIn, input [31:0] nonceIn, input[31:0] padIn[0:7], output [31:0] digestOutNew[0:7], output [31:0] digestOutOriginal[0:7], output [31:0] wordsOut[0:15], output [31:0] stateOut, output [31:0] jobOut, output [31:0] nonceOut, output [31:0] padOut[0:7]);
//valid values are 64,32,16,8,4,2,1
parameter N = 64;
//unroll assertion (taken from serial interface example)
generate
if(~(N==64 | N==32 | N==16 | N ==8 | N ==4 | N ==2 | N==1)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("SHA unroll parameter is not valid!");
endgenerate
//some interconnects
wire [31:0] stateMid;
wire [15:0] stateMidm;
//we need to shift some values in parallel with actual computation (usually needed in next steps)
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db(clk, stateIn, stateMid);
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db1(clk, jobIn, jobOut);
parameterized_shift_packed #(.elementWidth(32), .depth(N)) db2(clk, nonceIn, nonceOut);
parameterized_shift_unpacked #(.elementWidth(32), .elementCount(8),.depth(N)) db3(clk, digestInOriginal, digestOutOriginal);
parameterized_shift_unpacked #(.elementWidth(32), .elementCount(8),.depth(N)) db4(clk, padIn, padOut);
//sha unrolled according to the N parameter
sha_mix #(N) mix(clk, stateIn[15:0], wordsIn, digestIn, digestOutNew, wordsOut, stateMidm);
//apply new index to state if needed (ie. there was valid task in pipeline)
assign stateOut = {stateMid[31:16], stateMid[31] ? stateMidm : 16'h00};
endmodule
extern module ram #(parameter elementWidth = 8, parameter elementCount = 64, parameter depth = 4, parameter addrWidth = log2(depth)) (input clk, input [(elementWidth-1):0] data[0:(elementCount-1)], input [(addrWidth-1):0] write_addr, input [(addrWidth-1):0] read_addr, input we, output [(elementWidth-1):0] q[0:(elementCount-1)]);
//queue - same as in sha, but different data size
//inspiration taken from altera examples
//this queue now replaces last element if it is full, could be changed, but newer results are ussually better
//anyway it should be never filled, if so we need to change target
module hmacqueue(clk, write, read, in, out, available, full);
parameter elementWidth = 8;
parameter elementCount = 128;
parameter depth = 256;
input clk;
input write;
input read;
input [(elementWidth-1):0] in[0:(elementCount-1)];
output [(elementWidth-1):0] out[0:(elementCount-1)];
output available;
output full;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end endfunction
localparam addrWidth = log2(depth-1);
reg[(addrWidth-1):0] write_addr, read_addr;
reg[addrWidth:0] count;
ram #(.elementWidth(elementWidth), .elementCount(elementCount), .depth(depth)) ram(clk, in, write_addr, (read & available) ? (read_addr+1) : read_addr, write, out);
initial begin
read_addr = 0;
write_addr = 0;
count = 0;
end
//queue is full
assign full = (count == depth);
//some elements available
assign available = (count > 0);
always@(posedge clk) begin
//put, drop and available case
if(write & read & available) begin
write_addr <= write_addr + 1'h1;
read_addr <= read_addr +1'h1;
//write only case
end else if(write) begin
write_addr <= write_addr + 1'h1;
//this causes rewrite of oldest value
if(~full) begin
count <= count +1'h1;
end
//drop only case
end else if(read & available) begin
read_addr <= read_addr + 1'h1;
count <= count - 1'h1;
end
end
endmodule
// parameterized queue tailored for hmac
module hmacqueue_packed(clk, write, read, in, out, available, full, size);
parameter elementWidth = 8;
parameter elementCount = 128;
parameter depth = 256;
input clk;
input write;
input read;
input [(elementWidth-1):0] in;
output [(elementWidth-1):0] out;
output available;
output full;
output [addrWidth:0] size;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end endfunction
localparam addrWidth = log2(depth-1);
reg[(addrWidth-1):0] write_addr, read_addr;
reg[addrWidth:0] count;
ram_packed #(.elementWidth(elementWidth), .depth(depth)) ram(clk, in, write_addr, (read & available) ? (read_addr+3'h1) : read_addr, write, out);
initial begin
read_addr = 0;
write_addr = 0;
count = 0;
end
//queue is full
assign full = (count == depth);
//some elements available
assign available = (count > 0);
assign size = depth - count;
always@(posedge clk) begin
//put, drop and available case
if(write & read & available) begin
write_addr <= write_addr + 1'h1;
read_addr <= read_addr +1'h1;
//write only case
end else if(write) begin
write_addr <= write_addr + 1'h1;
//this causes rewrite of oldest value
if(~full) begin
count <= count +1'h1;
end
//this is drop only case
end else if(read & available) begin
read_addr <= read_addr + 1'h1;
count <= count - 1'h1;
end
end
endmodule
|
module I2C_WRITE_WDATA (
input RESET_N ,
input PT_CK,
input GO,
input [15:0] REG_DATA,
input [7:0] SLAVE_ADDRESS,
input SDAI,
output reg SDAO,
output reg SCLO,
output reg END_OK,
//--for test
output reg [7:0] ST ,
output reg [7:0] CNT,
output reg [7:0] BYTE,
output reg ACK_OK,
input [7:0] BYTE_NUM // 4 : 4 byte
);
//===reg/wire
reg [8:0]A ;
reg [7:0]DELY ;
always @( negedge RESET_N or posedge PT_CK )begin
if (!RESET_N ) ST <=0;
else
case (ST)
0: begin //start
SDAO <=1;
SCLO <=1;
ACK_OK <=0;
CNT <=0;
END_OK <=1;
BYTE <=0;
if (GO) ST <=30 ; // inital
end
1: begin //start
ST <=2 ;
{ SDAO, SCLO } <= 2'b01;
A <= {SLAVE_ADDRESS ,1'b1 };//WRITE COMMAND
end
2: begin //start
ST <=3 ;
{ SDAO, SCLO } <= 2'b00;
end
3: begin
ST <=4 ;
{ SDAO, A } <= { A ,1'b0 };
end
4: begin
ST <=5 ;
SCLO <= 1'b1 ;
CNT <= CNT +1 ;
end
5: begin
SCLO <= 1'b0 ;
if (CNT==9) begin
if ( BYTE == BYTE_NUM ) ST <= 6 ;
else begin
CNT <=0 ;
ST <= 2 ;
if ( BYTE ==0 ) begin BYTE <=1 ; A <= {REG_DATA[15:8] ,1'b1 }; end
else if ( BYTE ==1 ) begin BYTE <=2 ; A <= {REG_DATA[7:0] ,1'b1 }; end
end
if (SDAI ) ACK_OK <=1 ;
end
else ST <= 2;
end
6: begin //stop
ST <=7 ;
{ SDAO, SCLO } <= 2'b00;
end
7: begin //stop
ST <=8 ;
{ SDAO, SCLO } <= 2'b01;
end
8: begin //stop
ST <=9 ;
{ SDAO, SCLO } <= 2'b11;
end
9: begin
ST <= 30;
SDAO <=1;
SCLO <=1;
CNT <=0;
END_OK <=1;
BYTE <=0;
end
//--- END ---
30: begin
if (!GO) ST <=31;
end
31: begin //
END_OK<=0;
ACK_OK<=0;
ST <=1;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_4_V
`define SKY130_FD_SC_HS__DFXTP_4_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxtp_4 (
CLK ,
D ,
Q ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dfxtp base (
.CLK(CLK),
.D(D),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfxtp_4 (
CLK,
D ,
Q
);
input CLK;
input D ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfxtp base (
.CLK(CLK),
.D(D),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_4_V
|
module SeletorClock(
input wire clock,
input wire reset,
input wire sel_1hz,
input wire clock_1hz,
input wire sel_10hz,
input wire clock_10hz,
input wire sel_100hz,
input wire clock_100hz,
input wire sel_1khz,
input wire clock_1khz,
input wire sel_10khz,
input wire clock_10khz,
input wire sel_100khz,
input wire clock_100khz,
input wire sel_1mhz,
input wire clock_1mhz,
input wire sel_12mhz,
input wire clock_12mhz,
input wire sel_25mhz,
output reg clock_saida
);
always @ (posedge clock or posedge reset)
begin
if(reset) begin
clock_saida <= 1'b0;
end
else if( (sel_1hz == 1'b1) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0) ) begin
clock_saida <= clock_1hz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b1) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0) ) begin
clock_saida <= clock_10hz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b1) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_100hz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b1) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_1khz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b1) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_10khz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b1) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_100khz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b1) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_1mhz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b1) && (sel_25mhz == 1'b0)) begin
clock_saida <= clock_12mhz;
end
else if( (sel_1hz == 1'b0) && (sel_10hz == 1'b0) && (sel_100hz == 1'b0) && (sel_1khz == 1'b0) && (sel_10khz == 1'b0) && (sel_100khz == 1'b0) && (sel_1mhz == 1'b0) && (sel_12mhz == 1'b0) && (sel_25mhz == 1'b1)) begin
clock_saida <= clock;
end
else begin
clock_saida <= 1'b0;
end
end
endmodule
|
/*
* Copyright (c) 2013, The DDK Project
* Dmitry Nedospasov <dmitry at nedos dot net>
* Thorsten Schroeder <ths at modzero dot ch>
*
* All rights reserved.
*
* This file is part of Die Datenkrake (DDK).
*
* "THE BEER-WARE LICENSE" (Revision 42):
* <dmitry at nedos dot net> and <ths at modzero dot ch> wrote this file. As
* long as you retain this notice you can do whatever you want with this stuff.
* If we meet some day, and you think this stuff is worth it, you can buy us a
* beer in return. Die Datenkrake Project.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE DDK PROJECT BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Module: krake_port
* Description: Basic Krake I/O Port
*/
`include "reg_defs.v"
`include "uart_tx.v"
module krake_tx_port(
input wire clk_i,
input wire rst_i,
output reg ack_o,
input wire [7:0] dat_i,
input wire [3:0] adr_i,
output reg [7:0] dat_o,
input wire stb_i,
input wire we_i,
output wire dout);
reg [7:0] data;
reg tx_en;
wire tx_rdy;
reg tx_rst;
uart_tx txi(
.clk(clk_i),
.rst(rst_i),
.en(tx_en),
.data_out(data),
.rdy(tx_rdy),
.dout(dout));
always @ (posedge clk_i)
begin
if(rst_i)
begin
tx_rst <= 1'd1;
data <= 8'd0;
tx_en <= 1'd0;
end
else
begin
// Default Assignments
ack_o <= 1'b0;
dat_o <= 8'd0;
tx_en <= 1'b0;
data <= data;
if(stb_i)
begin
case(adr_i)
`UART_STATUS:
begin
if(we_i) // Write
begin
tx_en <= dat_i[0];
ack_o <= 1'b1;
end
else // Read
begin
dat_o[0] <= tx_rdy;
ack_o <= 1'b1;
end
end
`UART_DATAREG:
begin
if(we_i) // Write
begin
data <= dat_i;
ack_o <= 1'b1;
end
else // Read
begin
dat_o <= data;
ack_o <= 1'b1;
end
end
endcase
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_1_V
`define SKY130_FD_SC_MS__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFRTN_BEHAVIORAL_PP_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTN_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_sct_out_queues.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// jbi_sct_out_queues -- Outbound JBus Return Data queues from an SCTAG.
// _____________________________________________________________________________
//
// Design Notes:
// o 'sctrdq_trans_count' synchronizer can support clock ratios up to 32:2.
// _____________________________________________________________________________
`include "sys.h"
`include "iop.h"
`include "jbi.h"
module jbi_sct_out_queues (/*AUTOARG*/
// Outputs
sctrdq_trans_count, sctrdq_data1_4, sctrdq_install_state,
sctrdq_unmapped_error, sctrdq_jid, sctrdq_data, sctrdq_ue_err,
mout_scb_jbus_wr_ack,
// Inputs
scbuf_jbi_data, scbuf_jbi_ctag_vld, scbuf_jbi_ue_err,
sctrdq_dec_count, sctrdq_dequeue, testmux_sel, hold, rst_tri_en, cclk, crst_l,
clk, rst_l, tx_en_local_m1, arst_l
);
`include "jbi_mout.h"
`include "jbi_sct_out_queues.h"
// SCTAG/BUF Outbound Requests and Return Data (Cmp clock).
input [31:0] scbuf_jbi_data;
input scbuf_jbi_ctag_vld; // Header cycle of a new response packet.
input scbuf_jbi_ue_err; // Current data cycle has a uncorrectable error.
// JBI Outbound Interface (JBus clock).
output [3:0] sctrdq_trans_count;
output sctrdq_data1_4;
output sctrdq_install_state;
output sctrdq_unmapped_error;
output [5:0] sctrdq_jid;
output [127:0] sctrdq_data;
output sctrdq_ue_err;
input sctrdq_dec_count;
input sctrdq_dequeue;
// Memory In (jbi_min) (Cmp clock).
output mout_scb_jbus_wr_ack;
// Misc.
input testmux_sel; // Memory and ATPG test mode signal.
input hold;
input rst_tri_en;
// Clock and reset.
input cclk; // CMP clock.
input crst_l; // CMP clock domain reset.
input clk; // JBus clock.
input rst_l; // JBus clock domain reset.
input tx_en_local_m1; // CMP to JBI clock domain crossing synchronization pulse.
input arst_l; // Asynch reset.
// Wires and Regs.
wire [5:0] state;
wire [5:0] saved_jid;
wire [3:0] inc_count_cntr, inc_count_cntr_presync, inc_count_cntr_sync;
wire [31:0] scbuf_jbi_data_p1;
reg save_sctrdq_header, sctrdq_enqueue, sctrdq_inc_count, mout_scb_jbus_wr_ack, start_running_ue;
reg [5:0] next_state;
// Add last stage of distribution pipeline to 'tx_en'.
dff_ns u_dff_ctu_jbi_tx_en_mout_ff (.din(tx_en_local_m1), .q(tx_en), .clk(cclk));
// Stage SC interface for timing reasons.
dff_ns #(32) scbuf_jbi_data_p1_reg (.din(scbuf_jbi_data), .q(scbuf_jbi_data_p1), .clk(cclk));
dff_ns scbuf_jbi_ctag_vld_p1_reg (.din(scbuf_jbi_ctag_vld), .q(scbuf_jbi_ctag_vld_p1), .clk(cclk));
dff_ns scbuf_jbi_ue_err_p1_reg (.din(scbuf_jbi_ue_err), .q(scbuf_jbi_ue_err_p1), .clk(cclk));
// Decode SCBUF header.
wire [1:0] critical_byte = scbuf_jbi_data_p1[`L2_BSC_CBA_HI:`L2_BSC_CBA_LO];
wire read_write = scbuf_jbi_data_p1[`L2_BSC_READ];
wire [11:0] tag = scbuf_jbi_data_p1[`L2_BSC_CTAG_HI:`L2_BSC_CTAG_LO];
// Break the 'tag' field down furthur.
wire [1:0] tag_destination = tag[`JBI_SCTAG_TAG_DEST_HI:`JBI_SCTAG_TAG_DEST_LO];
wire tag_read_write = tag[`JBI_SCTAG_TAG_RW];
wire tag_subline = tag[`JBI_SCTAG_TAG_SUBLINE];
wire tag_install_state = tag[`JBI_SCTAG_TAG_INSTALL];
wire tag_unmapped_error = tag[`JBI_SCTAG_TAG_ERR];
wire [5:0] tag_jid = tag[`JBI_SCTAG_TAG_JID_HI:`JBI_SCTAG_TAG_JID_LO];
// Determine the transaction type being sent by the SCBUF.
wire [1:0] trans_type = (scbuf_jbi_ctag_vld_p1 && (tag_destination == `JBI_CTAG_PRE) && !read_write)? TT_JBUS_WR:
(scbuf_jbi_ctag_vld_p1 && (tag_destination == `JBI_CTAG_PRE) && read_write && tag_subline)? TT_JBUS_RD16:
(scbuf_jbi_ctag_vld_p1 && (tag_destination == `JBI_CTAG_PRE) && read_write && !tag_subline)? TT_JBUS_RD64:
TT_NONE;
// SCBUF Transaction Routing state machine (initialize to IDLE).
dffrl_ns #(6) state_reg (.din(next_state[5:0]), .q(state[5:0]), .rst_l(crst_l), .clk(cclk));
//
always @(/*AS*/mout_scb_jbus_wr_ack
or next_state or save_sctrdq_header or sctrdq_enqueue
or sctrdq_inc_count or start_running_ue or state or trans_type) begin
casex ({ state, trans_type })
`define out { next_state, save_sctrdq_header, sctrdq_enqueue, sctrdq_inc_count, mout_scb_jbus_wr_ack, start_running_ue }
//
// ][ save sctrdq scb start
// trans ][ next sctrdq sctrdq inc jbus running
// state type ][ state header enqueue count wr_ack ue
// -----------------------------++---------------------------------------------------------------------
// IDLE - Waiting for transaction.
{ IDLE, TT_NONE }: `out = { IDLE, x, N, N, N, x };
{ IDLE, TT_JBUS_WR }: `out = { IDLE, x, N, N, Y, x };
{ IDLE, TT_JBUS_RD16 }: `out = { JBUS_RD16_D01, Y, N, N, N, x };
{ IDLE, TT_JBUS_RD64 }: `out = { JBUS_RD64_D01, Y, N, N, N, x };
// JBus Read Return Data 16 bytes.
// Save Header; Bump transcount. Write 4 w/ header and w/ ue. Ignore last 12 cycles.
{ JBUS_RD16_D01, TT_X }: `out = { JBUS_RD16_D02, N, Y, N, N, Y };
{ JBUS_RD16_D02, TT_X }: `out = { JBUS_RD16_D03, N, Y, N, N, N };
{ JBUS_RD16_D03, TT_X }: `out = { JBUS_RD16_D04, N, Y, N, N, N };
{ JBUS_RD16_D04, TT_X }: `out = { JBUS_RD16_D05, N, Y, N, N, N };
{ JBUS_RD16_D05, TT_X }: `out = { JBUS_RD16_D06, N, N, N, N, x };
{ JBUS_RD16_D06, TT_X }: `out = { JBUS_RD16_D07, N, N, N, N, x };
{ JBUS_RD16_D07, TT_X }: `out = { JBUS_RD16_D08, N, N, N, N, x };
{ JBUS_RD16_D08, TT_X }: `out = { JBUS_RD16_D09, N, N, N, N, x };
{ JBUS_RD16_D09, TT_X }: `out = { JBUS_RD16_D10, N, N, N, N, x };
{ JBUS_RD16_D10, TT_X }: `out = { JBUS_RD16_D11, N, N, N, N, x };
{ JBUS_RD16_D11, TT_X }: `out = { JBUS_RD16_D12, N, N, N, N, x };
{ JBUS_RD16_D12, TT_X }: `out = { JBUS_RD16_D13, N, N, N, N, x };
{ JBUS_RD16_D13, TT_X }: `out = { JBUS_RD16_D14, N, N, N, N, x };
{ JBUS_RD16_D14, TT_X }: `out = { JBUS_RD16_D15, N, N, N, N, x };
{ JBUS_RD16_D15, TT_X }: `out = { JBUS_RD16_D16, N, N, N, N, x };
{ JBUS_RD16_D16, TT_X }: `out = { IDLE, N, N, Y, N, x };
// ][ save sctrdq scb start
// trans ][ next sctrdq sctrdq inc jbus running
// state type ][ state header enqueue count wr_ack ue
// -----------------------------++---------------------------------------------------------------------
// JBus Read Return Data 64 bytes.
// Save Header; Bump transcount. Write 16 w/ header and w/ ue.
{ JBUS_RD64_D01, TT_X }: `out = { JBUS_RD64_D02, N, Y, N, N, Y };
{ JBUS_RD64_D02, TT_X }: `out = { JBUS_RD64_D03, N, Y, N, N, N };
{ JBUS_RD64_D03, TT_X }: `out = { JBUS_RD64_D04, N, Y, N, N, N };
{ JBUS_RD64_D04, TT_X }: `out = { JBUS_RD64_D05, N, Y, N, N, N };
{ JBUS_RD64_D05, TT_X }: `out = { JBUS_RD64_D06, N, Y, N, N, Y };
{ JBUS_RD64_D06, TT_X }: `out = { JBUS_RD64_D07, N, Y, N, N, N };
{ JBUS_RD64_D07, TT_X }: `out = { JBUS_RD64_D08, N, Y, N, N, N };
{ JBUS_RD64_D08, TT_X }: `out = { JBUS_RD64_D09, N, Y, N, N, N };
{ JBUS_RD64_D09, TT_X }: `out = { JBUS_RD64_D10, N, Y, N, N, Y };
{ JBUS_RD64_D10, TT_X }: `out = { JBUS_RD64_D11, N, Y, N, N, N };
{ JBUS_RD64_D11, TT_X }: `out = { JBUS_RD64_D12, N, Y, N, N, N };
{ JBUS_RD64_D12, TT_X }: `out = { JBUS_RD64_D13, N, Y, N, N, N };
{ JBUS_RD64_D13, TT_X }: `out = { JBUS_RD64_D14, N, Y, N, N, Y };
{ JBUS_RD64_D14, TT_X }: `out = { JBUS_RD64_D15, N, Y, N, N, N };
{ JBUS_RD64_D15, TT_X }: `out = { JBUS_RD64_D16, N, Y, N, N, N };
{ JBUS_RD64_D16, TT_X }: `out = { IDLE, N, Y, Y, N, N };
// CoverMeter line_off
default: `out = { XXX, x, x, x, x, x };
// CoverMeter line_on
`undef out
endcase
end
// Saving the SCTRDQ header.
// When 'save_sctrdq_header' is asserted, save the subline, install_state, and jid from the SCBUF.
dffe_ns saved_subline_reg (.din(tag_subline), .en(save_sctrdq_header), .q(saved_subline), .clk(cclk));
dffe_ns saved_install_state_reg (.din(tag_install_state), .en(save_sctrdq_header), .q(saved_install_state), .clk(cclk));
dffe_ns saved_unmapped_error_reg (.din(tag_unmapped_error), .en(save_sctrdq_header), .q(saved_unmapped_error), .clk(cclk));
dffe_ns #(6) saved_jid_reg (.din(tag_jid), .en(save_sctrdq_header), .q(saved_jid), .clk(cclk));
// Running UE accumulator.
// Create 'ue' signal by or'ing sequential 'scbuf_jbi_ue_err_p1' values from SCBUF. Asserting 'start_running_ue'
// will make "ue = scbuf_jbi_ue_err_p1". Otherwise, it accumulates "ue = scbuf_jbi_ue_err_p1 || ue_p1".
dffrl_ns ue_p1_reg (.din(ue), .q(ue_p1), .rst_l(crst_l), .clk(cclk));
assign ue = (start_running_ue)? scbuf_jbi_ue_err_p1: scbuf_jbi_ue_err_p1 || ue_p1;
// SCTAG Return Data Queue (SCTxRQQ).
// 4 to 1 packing with header, 32 + 10 -> 128 + 10. Write header last cycle, read first cycle.
jbi_sctrdq sctrdq (
// Head of queue.
.enqueue (sctrdq_enqueue),
.attr_in ({ saved_subline, saved_install_state, saved_unmapped_error, saved_jid[5:0], ue }),
.data_in (scbuf_jbi_data_p1),
.flush (1'b0),
.full (sctrdq_full),
.cclk (cclk),
.tx_en (tx_en),
.crst_l (crst_l),
// Tail of queue.
.dequeue (sctrdq_dequeue),
.data_out (sctrdq_data),
.attr_out ({ sctrdq_data1_4, sctrdq_install_state, sctrdq_unmapped_error, sctrdq_jid[5:0], sctrdq_ue_err }),
.empty (sctrdq_empty),
.clk (clk),
.rst_l (rst_l),
// Misc.
.hold (hold),
.testmux_sel (testmux_sel),
.rst_tri_en (rst_tri_en),
.arst_l (arst_l)
);
// SCTRDQ Transaction counter.
//
// Implemented as a up/down counter in the Jbus clock domain. The 'sctrdq_inc_count'
// is in the Cmp clock domain and may pulse multiple times before a Jbus clock. So
// it increments its own counter and this is passed between the clock domains to
// update the SCTRDQ Transaction counter. Can support clock ratios up to 32:2.
//
// 'inc_count_cntr' accumulates the 'sctrdq_inc_count' pulses.
wire [3:0] next_inc_count_cntr = (sctrdq_inc_count)? (inc_count_cntr + 1'b1): inc_count_cntr;
wire inc_count_cntr_rst_l = ~(tx_en);
dffrl_ns #(4) inc_count_cntr_reg (.din(next_inc_count_cntr), .q(inc_count_cntr), .rst_l(inc_count_cntr_rst_l), .clk(cclk));
//
// Synchonize 'inc_count_cntr' to the JBus clock domain (Cmp -> JBus).
wire [3:0] next_inc_count_cntr_presync = next_inc_count_cntr;
wire inc_count_cntr_presync_en = tx_en;
dffe_ns #(4) inc_count_cntr_presync_reg (.din(next_inc_count_cntr_presync), .en(inc_count_cntr_presync_en), .q(inc_count_cntr_presync), .clk(cclk));
//
wire [3:0] next_inc_count_cntr_sync = inc_count_cntr_presync;
dff_ns #(4) inc_count_cntr_sync_reg (.din(next_inc_count_cntr_sync), .q(inc_count_cntr_sync), .clk(clk));
//
// Create the SCTRDQ Transaction counter 'sctrdq_trans_count'.
wire [3:0] next_sctrdq_trans_count = (sctrdq_dec_count)? (sctrdq_trans_count + inc_count_cntr_sync - 1'b1): (sctrdq_trans_count + inc_count_cntr_sync);
dffrl_ns #(4) sctrdq_trans_count_reg (.din(next_sctrdq_trans_count), .q(sctrdq_trans_count), .rst_l(rst_l), .clk(clk));
// Monitors.
// simtech modcovoff -bpen
// synopsys translate_off
// Check: State machine has valid state.
always @(posedge clk) begin
if (!(~rst_l) && next_state === XXX) begin
$dispmon ("jbi_mout_jbi_sct_out_queues", 49, "%d %m: ERROR - No state asserted! (state=%b)", $time, state);
end
end
// synopsys translate_on
// simtech modcovon -bpen
endmodule
// Local Variables:
// verilog-library-directories:("." "../../include" "../../../include")
// verilog-library-files:("../../../common/rtl/swrvr_clib.v")
// verilog-auto-read-includes:t
// verilog-module-parents:("jbi_mout")
// End:
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:31:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_1_stub.v
// Design : zynq_design_1_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_PP_SYMBOL_V
`define SKY130_FD_SC_HD__MAJ3_PP_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__maj3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_PP_SYMBOL_V
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Test register module for RCN Bus
// 0x00 : Bus ID
// 0x04 : Test Progress Mark
// 0x08 : Test Fail
// 0x0C : Test Pass
//
module rcn_testregs
(
input clk,
input rst,
input [68:0] rcn_in,
output [68:0] rcn_out,
output [31:0] test_progress,
output [31:0] test_fail,
output [31:0] test_pass
);
parameter ADDR_BASE = 0;
wire cs;
wire wr;
wire [23:0] addr;
wire [31:0] wdata;
reg [31:0] rdata;
rcn_slave_fast #(.ADDR_MASK(24'hFFFFF0), .ADDR_BASE(ADDR_BASE)) rcn_slave
(
.rst(rst),
.clk(clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(cs),
.wr(wr),
.mask(),
.addr(addr),
.wdata(wdata),
.rdata(rdata)
);
reg [7:0] id_seq;
always @ (posedge clk)
id_seq <= {rcn_in[65:60], rcn_in[33:32]};
reg [31:0] test_progress_reg;
reg [31:0] test_fail_reg;
reg [31:0] test_pass_reg;
assign test_progress = test_progress_reg;
assign test_fail = test_fail_reg;
assign test_pass = test_pass_reg;
always @ *
case (addr[3:0])
4'h0: rdata = {24'd0, id_seq};
4'h4: rdata = test_progress_reg;
4'h8: rdata = test_fail_reg;
default: rdata = test_pass_reg;
endcase
always @ (posedge clk or posedge rst)
if (rst)
begin
test_progress_reg <= 32'd0;
test_fail_reg <= 32'd0;
test_pass_reg <= 32'd0;
end
else if (cs && wr)
case (addr[3:0])
4'h0: ;
4'h4: test_progress_reg <= wdata;
4'h8: test_fail_reg <= wdata;
default: test_pass_reg <= wdata;
endcase
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.7
// \ \ Application: MIG
// / / Filename: infrastructure.v
// /___/ /\ Date Last Modified: $Date: 2010/10/29 15:22:39 $
// \ \ / \ Date Created:Tue Jun 30 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: infrastructure.v,v 1.2 2010/10/29 15:22:39 pboya Exp $
**$Date: 2010/10/29 15:22:39 $
**$Author: pboya $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_7/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ip_top/infrastructure.v,v $
******************************************************************************/
`timescale 1ps/1ps
module infrastructure #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter CLK_PERIOD = 3000, // Internal (fabric) clk period
parameter nCK_PER_CLK = 2, // External (memory) clock period =
// CLK_PERIOD/nCK_PER_CLK
parameter INPUT_CLK_TYPE = "DIFFERENTIAL", // input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter MMCM_ADV_BANDWIDTH = "OPTIMIZED", // MMCM programming algorithm
parameter CLKFBOUT_MULT_F = 2, // write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor
parameter CLKOUT_DIVIDE = 2, // VCO output divisor for fast
// (memory) clocks
parameter RST_ACT_LOW = 1
)
(
// Clock inputs
input mmcm_clk, // System clock diff input
// System reset input
input sys_rst, // core reset from user application
// MMCM/IDELAYCTRL Lock status
input iodelay_ctrl_rdy, // IDELAYCTRL lock status
// Clock outputs
output clk_mem, // 2x logic clock
output clk, // 1x logic clock
output clk_rd_base, // 2x base read clock
// Reset outputs
output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O),
// Phase Shift Interface
input PSEN, // For enabling fine-phase shift
input PSINCDEC, // = 1 increment phase shift, = 0
output PSDONE
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
//localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
localparam RST_SYNC_NUM = 65;
// Round up for clk reset delay to ensure that CLKDIV reset deassertion
// occurs at same time or after CLK reset deassertion (still need to
// consider route delay - add one or two extra cycles to be sure!)
localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2;
localparam real CLKIN1_PERIOD
= (CLKFBOUT_MULT_F * CLK_PERIOD)/
(DIVCLK_DIVIDE * CLKOUT_DIVIDE * nCK_PER_CLK * 1000.0); // in ns
localparam integer VCO_PERIOD
= (DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK);
localparam CLKOUT0_DIVIDE_F = CLKOUT_DIVIDE;
localparam CLKOUT1_DIVIDE = CLKOUT_DIVIDE * nCK_PER_CLK;
localparam CLKOUT2_DIVIDE = CLKOUT_DIVIDE;
localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE_F;
localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE;
localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE;
//synthesis translate_off
initial begin
$display("############# Write Clocks MMCM_ADV Parameters #############\n");
$display("nCK_PER_CLK = %7d", nCK_PER_CLK );
$display("CLK_PERIOD = %7d", CLK_PERIOD );
$display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD );
$display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE );
$display("CLKFBOUT_MULT_F = %7d", CLKFBOUT_MULT_F );
$display("VCO_PERIOD = %7d", VCO_PERIOD );
$display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE_F);
$display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE );
$display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE );
$display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD );
$display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD );
$display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD );
$display("############################################################\n");
end
//synthesis translate_on
wire clk_bufg;
wire clk_mem_bufg;
wire clk_mem_pll;
wire clk_pll;
wire clkfbout_pll;
wire pll_lock
/* synthesis syn_maxfan = 10 */;
reg [RST_DIV_SYNC_NUM-1:0] rstdiv0_sync_r
/* synthesis syn_maxfan = 10 */;
wire rst_tmp;
wire sys_rst_act_hi;
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Assign global clocks:
// 1. clk_mem : Full rate (used only for IOB)
// 2. clk : Half rate (used for majority of internal logic)
//***************************************************************************
assign clk_mem = clk_mem_bufg;
assign clk = clk_bufg;
//***************************************************************************
// Global base clock generation and distribution
//***************************************************************************
//*****************************************************************
// NOTES ON CALCULTING PROPER VCO FREQUENCY
// 1. VCO frequency =
// 1/((DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK))
// 2. VCO frequency must be in the range [800MHz, 1.2MHz] for -1 part.
// The lower limit of 800MHz is greater than the lower supported
// frequency of 400MHz according to the datasheet because the MMCM
// jitter performance improves significantly when the VCO is operatin
// above 800MHz. For speed grades faster than -1, the max VCO frequency
// will be highe, and the multiply and divide factors can be adjusted
// according (in general to run the VCO as fast as possible).
//*****************************************************************
MMCM_ADV #
(
.BANDWIDTH (MMCM_ADV_BANDWIDTH),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("INTERNAL"),
.REF_JITTER1 (0.005),
.REF_JITTER2 (0.005),
.STARTUP_WAIT ("FALSE"),
.CLKIN1_PERIOD (CLKIN1_PERIOD),
.CLKIN2_PERIOD (10.000),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_USE_FINE_PS ("TRUE"),
.CLKOUT3_DIVIDE (1),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_CASCADE ("FALSE"),
.CLKOUT4_DIVIDE (1),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKOUT5_DIVIDE (1),
.CLKOUT5_DUTY_CYCLE (0.500),
.CLKOUT5_PHASE (0.000),
.CLKOUT5_USE_FINE_PS ("FALSE"),
.CLKOUT6_DIVIDE (1),
.CLKOUT6_DUTY_CYCLE (0.500),
.CLKOUT6_PHASE (0.000),
.CLKOUT6_USE_FINE_PS ("FALSE")
)
u_mmcm_adv
(
.CLKFBOUT (clkfbout_pll),
.CLKFBOUTB (),
.CLKFBSTOPPED (),
.CLKINSTOPPED (),
.CLKOUT0 (clk_mem_pll),
.CLKOUT0B (),
.CLKOUT1 (clk_pll),
.CLKOUT1B (),
.CLKOUT2 (clk_rd_base),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.DO (),
.DRDY (),
.LOCKED (pll_lock),
.PSDONE (PSDONE),
.CLKFBIN (clkfbout_pll),
.CLKIN1 (mmcm_clk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DADDR (7'b0000000),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0000),
.DWE (1'b0),
.PSCLK (clk_bufg),
.PSEN (PSEN),
.PSINCDEC (PSINCDEC),
.PWRDWN (1'b0),
.RST (sys_rst_act_hi)
);
BUFG u_bufg_clk0
(
.O (clk_mem_bufg),
.I (clk_mem_pll)
);
BUFG u_bufg_clkdiv0
(
.O (clk_bufg),
.I (clk_pll)
);
//***************************************************************************
// RESET SYNCHRONIZATION DESCRIPTION:
// Various resets are generated to ensure that:
// 1. All resets are synchronously deasserted with respect to the clock
// domain they are interfacing to. There are several different clock
// domains - each one will receive a synchronized reset.
// 2. The reset deassertion order starts with deassertion of SYS_RST,
// followed by deassertion of resets for various parts of the design
// (see "RESET ORDER" below) based on the lock status of MMCMs.
// RESET ORDER:
// 1. User deasserts SYS_RST
// 2. Reset MMCM and IDELAYCTRL
// 3. Wait for MMCM and IDELAYCTRL to lock
// 4. Release reset for all I/O primitives and internal logic
// OTHER NOTES:
// 1. Asynchronously assert reset. This way we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers
// to prevent initial bus contention). Reset deassertion is synchronous.
//***************************************************************************
//*****************************************************************
// CLKDIV logic reset
//*****************************************************************
// Wait for MMCM and IDELAYCTRL to lock before releasing reset
assign rst_tmp = sys_rst_act_hi | ~pll_lock | ~iodelay_ctrl_rdy;
always @(posedge clk_bufg or posedge rst_tmp)
if (rst_tmp) rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}};
else rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1; // Shift in a Zero
assign rstdiv0 = rstdiv0_sync_r[RST_DIV_SYNC_NUM-1];
endmodule
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_onchip_trace_mem (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "wasca_onchip_trace_mem.hex";
output [ 63: 0] readdata;
input [ 8: 0] address;
input [ 7: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 63: 0] writedata;
wire clocken0;
wire [ 63: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 512,
the_altsyncram.numwords_a = 512,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 64,
the_altsyncram.width_byteena_a = 8,
the_altsyncram.widthad_a = 9;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// nios_dut_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [31:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [29:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_dut_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
//date:2016/8/02
//engineer:ZhaiShaoMin
//module name :regflie
//version: test bench
module tb_core_rf();
//input
reg clk;
reg rst;
reg [4:0] raddr1;
reg [4:0] raddr2;
reg rf_write;
reg [4:0] waddr;
reg [31:0] data;
//output
wire [31:0] rd_data1;
wire [31:0] rd_data2;
core_id_regfile duv(//input
.clk(clk),
.rst(rst),
.raddr1(raddr1),
.raddr2(raddr2),
.rf_write(rf_write),
.waddr(waddr),
.data(data),
//output
.rd_data1(rd_data1),
.rd_data2(rd_data2)
);
always #5 clk=~clk;
integer log_file;
integer i;
`define clk_step #10;
initial begin
clk=1'b0;
rst=1'b1;
raddr1=5'h00;
raddr2=5'h00;
rf_write=1'b0;
waddr=5'h01;
data=32'h11112222;
log_file=$fopen("core_rf_log.txt");
end
////////////////////////////////////////////////////////////////////////////
/////////////BEGIN TEST/////////////////////////////////////////////////////
initial begin
////////case 1: write the regfile then we should see what I want to see////////
///////here just write th rf/////////////
`clk_step
rst=1'b0;
for(i=0;i<32;i=i+1)
begin
rf_write=1'b1;
waddr=i;
data=i+1;
$display( "(%t) writing %d. to %d ", $time, data, waddr);
$fdisplay(log_file, "(%t) writing %d. to %d ", $time, data, waddr);
`clk_step
end
////////case 2: read out the content in regfile /////////////////
`clk_step
rf_write=1'b0;
for(i=0;i<32;i=i+1)
begin
raddr1=i;
raddr2=i;
$display( "(%t) get %d. from %d and get %d from %d", $time, rd_data1, raddr1 ,rd_data2, raddr2);
$fdisplay(log_file, "(%t) get %d. from %d and get %d from %d", $time, rd_data1, raddr1 ,rd_data2, raddr2);
`clk_step
end
////////case 3: when read a reg same as being written one, it should get it direct from write data////////////
////read port 1
for(i=0;i<32;i=i+1)
begin
raddr1=i;
rf_write=1'b1;
waddr=i;
data=i+32;
$display( "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
$fdisplay(log_file, "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
`clk_step
end
////read port 2
for(i=0;i<32;i=i+1)
begin
raddr2=i;
rf_write=1'b1;
waddr=i;
data=i+64;
$display( "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
$fdisplay(log_file, "(%t) get %d. from %d and write %d to %d", $time, rd_data1, raddr1 ,data, waddr);
`clk_step
end
$stop;
end
endmodule
|
`include "./Definition.v"
//float Lmin = 0, L1x = 5, L2x = 10, L3x = 50;
//float Lmax = 100, L1y = 10, L2y = 17.5, L3y = 55;
//float a1 = ( L1y - Lmin ) / ( L1x - Lmin ), a2 = ( L2y - L1y ) / ( L2x - L1x ), a3 = ( L3y - L2y ) / ( L3x - L2x ), a4 = ( Lmax - L3y ) / ( Lmax - L3x);
//float b1 = ( L1y - ( L1x * a1)), b2 = ( L1y - ( L1x * a2 )), b3 = ( L3y - ( L3x * a3 )), b4 = ( L3y - ( L3x * a4 ));
`define Lmin 0
`define L1x 8127
`define L2x 16255
`define L3x 81275
`define Lmax 162550
`define L1y 16255
`define L2y 28446
`define L3y 89402
`define a1 512
`define a2 384
`define a3 240
`define a4 230
`define b1 0
`define b2 640
`define b3 2080
`define b4 2560
module ToneReproduction
(
input[ `size_int - 1 : 0 ]L,
input[ `size_int - 1 : 0 ]IN_R,
input[ `size_int - 1 : 0 ]IN_G,
input[ `size_int - 1 : 0 ]IN_B,
output reg[ `size_int - 1 : 0 ]OUT_R,
output reg[ `size_int - 1 : 0 ]OUT_G,
output reg[ `size_int - 1 : 0 ]OUT_B
);
always@( L )
begin
if( L <= `L1x )
begin
OUT_R = ( ( IN_R * `a1 ) + `b1 );
OUT_G = ( ( IN_G * `a1 ) + `b1 );
OUT_B = ( ( IN_B * `a1 ) + `b1 );
end
else if( `L1x < L && L <= `L2x)
begin
OUT_R = ( ( IN_R * `a2 ) + `b2 );
OUT_G = ( ( IN_G * `a2 ) + `b2 );
OUT_B = ( ( IN_B * `a2 ) + `b2 );
end
else if( `L2x < L && L <= `L3x)
begin
OUT_R = ( ( IN_R * `a3 ) + `b3 );
OUT_G = ( ( IN_G * `a3 ) + `b3 );
OUT_B = ( ( IN_B * `a3 ) + `b3 );
end
else
begin
OUT_R = ( ( IN_R * `a4 ) + `b4 );
OUT_G = ( ( IN_G * `a4 ) + `b4 );
OUT_B = ( ( IN_B * `a4 ) + `b4 );
end
end
endmodule
module ToneReproduction_testbench;
reg[ `size_int - 1 : 0 ]L;
reg[ `size_int - 1 : 0 ]IN_R;
reg[ `size_int - 1 : 0 ]IN_G;
reg[ `size_int - 1 : 0 ]IN_B;
wire[ `size_int - 1 : 0 ]OUT_R;
wire[ `size_int - 1 : 0 ]OUT_G;
wire[ `size_int - 1 : 0 ]OUT_B;
ToneReproduction ToneReproduction_test( L, IN_R, IN_G, IN_B, OUT_R, OUT_G, OUT_B );
initial
begin
//L = 58 * 256 * 6.3496042078727978990068225570775 = 94279
//IN_R = 128 * 256 = 32768
//IN_G = 90 * 256 = 23040
//IN_B = 78 * 256 = 19968
#10
begin
L = 65019;
IN_R = 32768;
IN_G = 23040;
IN_B = 19968;
end
#10 $display( "L = %d\tIN_R = %d\tIN_G = %d\tIN_B = %d", L, IN_R, IN_G, IN_B );
#10 $display( "OUT_R = %d\tOUT_G = %d\tOUT_B = %d",OUT_R, OUT_G, OUT_B );
#10 $stop;
#10 $finish;
end
endmodule
|
Require Import MapProofs.Common.
Set Bullet Behavior "Strict Subproofs".
Require Import MapProofs.Bounds.
Require Import MapProofs.Tactics.
Require Import MapProofs.MaxMinProofs.
Require Import MapProofs.InsertProofs.
Section WF.
Context {e : Type} {a : Type} {HEq : Eq_ e} {HOrd : Ord e} {HEqLaws : EqLaws e} {HOrdLaws : OrdLaws e}.
(** ** Verification of [glue] *)
Lemma glue_Desc:
forall (s1: Map e a) s2 lb ub x,
Bounded s1 lb (Some x) ->
Bounded s2 (Some x) ub ->
isLB lb x = true ->
isUB ub x = true ->
balance_prop (size s1) (size s2) ->
Desc (glue s1 s2) lb ub ((size s1 + size s2)%Z) (fun i => sem s1 i ||| sem s2 i).
Proof.
intros ????? HB1 HB2 ???.
inversion HB1; inversion HB2; subst; cbn -[Z.add]; clear HB1 HB2.
1-3: solve [solve_Desc e|solve_size].
destruct (Z.ltb_spec (1 + size s4 + size s5) (1 + size s0 + size s3)).
- eapply maxViewSure_Desc; only 1: solve_Bounded e.
intros y vy r [Hthere HD].
applyDesc e HD.
destruct Hthere as [[??]|Hthere].
(*TODO: See why this is not rewriting automatically*)
* subst. applyDesc e (@balanceR_Desc e a). rewrite size_Bin in *. rewrite size_Bin in H1.
solve_size. solve_Desc e. repeat(rewrite size_Bin in H1). rewrite size_Bin in Hsz0. solve_size.
(*subst; applyDesc e (@balanceR_Desc e a); solve_Desc e.*)
* subst; applyDesc e (@balanceR_Desc e a). rewrite size_Bin in *. rewrite size_Bin in H1. solve_size.
solve_Desc e. rewrite size_Bin in Hsz0. solve_size.
- eapply minViewSure_Desc; only 1: solve_Bounded e.
intros y vy r [Hthere HD].
applyDesc e HD.
destruct Hthere as [[??]|Hthere]; subst; applyDesc e (@balanceL_Desc e a).
rewrite size_Bin in H1. solve_size. solve_Desc e. rewrite size_Bin in Hsz0. solve_size.
rewrite size_Bin in H1. solve_size. solve_Desc e. rewrite size_Bin in Hsz0. solve_size.
Qed.
(** ** Verification of [delete] *)
Lemma delete_Desc :
forall x (s: Map e a) lb ub,
Bounded s lb ub ->
Desc (delete x s) lb ub (if isSome (sem s x) then (size s - 1) else size s) (fun i => if i == x then None else sem s i).
Proof.
intros ???? HB.
induction HB; intros; subst.
- simpl. solve_Desc e.
- cbn -[Z.add].
destruct (compare x x0) eqn:Heq.
+ replace (x == x0) with true by solve_Bounds e.
simpl_options.
applyDesc e glue_Desc.
solve_Desc e.
+ applyDesc e IHHB1; clear IHHB1 IHHB2.
replace (x == x0) with false by solve_Bounds e.
rewrite -> (sem_outside_below HB2) by solve_Bounds e.
simpl_options.
destruct_ptrEq.
* replace (isSome (sem s1 x)) with false in *
by (destruct (sem s1 x); simpl in *; try congruence; lia).
solve_Desc e.
* destruct (sem s1 x); cbn -[Z.add] in *; applyDesc e (@balanceR_Desc e a); solve_Desc e.
+ applyDesc e IHHB2; clear IHHB1 IHHB2.
replace (x == x0) with false by solve_Bounds e.
rewrite -> (sem_outside_above HB1) by solve_Bounds e.
simpl_options.
destruct_ptrEq.
* replace (isSome (sem s2 x)) with false by (destruct (sem s2 x); simpl in *; try congruence; lia).
solve_Desc e.
* destruct (sem s2 x); cbn -[Z.add] in *; applyDesc e (@balanceL_Desc e a); solve_Desc e.
Qed.
(** ** Verification of [deleteMin] *)
(** It is hard to phrase this without refering to [lookupMin] *)
Lemma deleteMin_Desc :
forall (m: Map e a) lb ub,
Bounded m lb ub ->
deleteMin m = match lookupMin m with | None => m
| Some (x, y) => delete x m end.
Proof.
intros ??? HD.
induction HD.
* reflexivity.
* clear IHHD2.
cbn [deleteMin].
rewrite IHHD1; clear IHHD1.
destruct s1 eqn:?.
+ replace (lookupMin (Bin sz x v (Bin s e0 a0 m1 m2) s2)) with (lookupMin (Bin s e0 a0 m1 m2)) by reflexivity.
rewrite <- Heqm in *. clear s e0 a0 m1 m1 Heqm.
pose proof (lookupMin_Desc s1 lb (Some x) HD1) as Hlookup.
destruct (lookupMin s1) as [ex|].
- destruct ex. destruct Hlookup as [Hthere Hextrem].
simpl.
apply (sem_inside HD1) in Hthere. destruct Hthere.
replace (compare e0 x) with Lt by (symmetry; solve_Bounds e).
** destruct_ptrEq.
++ rewrite Hpe. clear Hpe.
eapply balanceR_noop; try eassumption.
++ reflexivity.
- rewrite H1.
eapply balanceR_noop; try eassumption.
+ simpl.
replace (compare x x) with Eq by (symmetry; order e).
reflexivity.
Qed.
(** ** Verification of [deleteMax] *)
(** It is hard to phrase this without refering to [lookupMax] *)
Lemma deleteMax_Desc :
forall (m: Map e a) lb ub,
Bounded m lb ub ->
deleteMax m = match lookupMax m with | None => m
| Some (x, y) => delete x m end.
Proof.
intros ??? HD.
induction HD.
* reflexivity.
* clear IHHD1.
cbn [deleteMax].
rewrite IHHD2; clear IHHD2.
destruct s2 eqn:?.
+ replace (lookupMax (Bin sz x v s1 (Bin s e0 a0 m1 m2))) with (lookupMax (Bin s e0 a0 m1 m2)) by reflexivity.
rewrite <- Heqm in *. clear s e0 a0 m1 m2 Heqm.
pose proof (lookupMax_Desc s2 (Some x) ub HD2) as Hlookup.
destruct (lookupMax s2) as [ex|].
- destruct ex. destruct Hlookup as [Hthere Hextrem].
simpl.
apply (sem_inside HD2) in Hthere. destruct Hthere.
replace (compare e0 x) with Gt by (symmetry; solve_Bounds e).
** destruct_ptrEq.
++ rewrite Hpe. clear Hpe.
eapply balanceL_noop; try eassumption.
++ reflexivity.
- rewrite H1.
eapply balanceL_noop; try eassumption.
+ simpl.
replace (compare x x) with Eq by (symmetry; order e).
destruct s1; reflexivity.
Qed.
(** ** Verification of [adjustWithKey *)
Require Import Coq.Classes.Morphisms. (* For [Proper] *)
(*TODO: Had to add assumption that f is proper*)
Lemma adjustWithKey_Desc :
forall x f (m: Map e a) lb ub,
Bounded m lb ub ->
Proper ((fun i j : e => _GHC.Base.==_ i j = true) ==> eq) f ->
Desc (adjustWithKey f x m) lb ub (size m) (fun i => if i == x then match (sem m x) with
| Some v => Some (f x v)
| None => None end else sem m i).
Proof.
intros ????? HA HP. induction HA.
- simpl. solve_Desc e.
- cbn -[Z.add]. destruct (compare x x0) eqn : ?.
+ replace (x == x0) with true by solve_Bounds e. simpl_options.
solve_Desc e. f_solver e.
assert (f x0 v = f x v). apply equal_f. apply HP. order e. rewrite H3. reflexivity.
+ applyDesc e IHHA1; clear IHHA1 IHHA2. replace (x == x0) with false by solve_Bounds e.
rewrite -> (sem_outside_below HA2) by solve_Bounds e.
simpl_options. solve_Desc e.
+ applyDesc e IHHA2; clear IHHA1 IHHA2. replace (x == x0) with false by solve_Bounds e.
rewrite -> (sem_outside_above HA1) by solve_Bounds e. simpl_options.
solve_Desc e.
Qed.
(** ** Verification of [adjust] *)
Lemma adjust_spec: forall (m: Map e a) (f: a -> a) k,
adjust f k m = adjustWithKey (fun _ x => f x) k m.
Proof.
intros. unfold adjust. reflexivity.
Qed.
(** ** Verification of [updateWithKey] *)
Lemma updateWithKey_Desc:
forall x f (m: Map e a) lb ub,
Bounded m lb ub ->
Proper ((fun i j : e => _GHC.Base.==_ i j = true) ==> eq) f ->
Desc (updateWithKey f x m) lb ub (match sem m x with
| None => size m
| Some y => if isSome (f x y) then
size m else size m - 1
end) (fun i => if i == x then match (sem m x) with
| Some v => f x v
| None => None end else sem m i).
Proof.
intros ????? HB HP.
induction HB; intros; subst.
- simpl. solve_Desc e.
- cbn -[Z.add].
destruct (compare x x0) eqn:Heq.
+ assert (f x0 v = f x v). apply equal_f. apply HP. order e.
replace (x == x0) with true by solve_Bounds e.
simpl_options. destruct (f x0 v) eqn : ?.
* solve_Desc e. rewrite size_Bin in *.
rewrite -> (sem_outside_above HB1) by solve_Bounds e.
rewrite -> (sem_outside_below HB2) by solve_Bounds e.
simpl_options. rewrite <- H1. reflexivity.
* applyDesc e glue_Desc. solve_Desc e.
rewrite -> (sem_outside_above HB1) by solve_Bounds e.
rewrite -> (sem_outside_below HB2) by solve_Bounds e.
simpl_options. rewrite <-H1. cbn -[Z.add]. rewrite Hsz. omega.
+ applyDesc e IHHB1. replace (x == x0) with false by solve_Bounds e.
rewrite -> (sem_outside_below HB2) by solve_Bounds e.
simpl_options. destruct (sem s1 x); cbn -[Z.add] in *; applyDesc e (@balanceR_Desc e a).
destruct (f x a0) eqn : ?. simpl in Hsz. rewrite Hsz. left. assumption.
simpl in Hsz. rewrite Hsz. solve_size.
solve_Desc e. rewrite Hsz0. destruct (f x a0); simpl in Hsz; rewrite Hsz;
cbn -[Z.add]. reflexivity. omega. solve_Desc e.
+ applyDesc e IHHB2. replace (x == x0) with false by (order e).
rewrite -> (sem_outside_above HB1) by solve_Bounds e.
simpl_options. destruct (sem s2 x); cbn -[Z.add] in *; applyDesc e (@balanceL_Desc e a).
destruct (f x a0) eqn : ?. simpl in Hsz. rewrite Hsz. left. assumption.
simpl in Hsz. rewrite Hsz. solve_size.
solve_Desc e. rewrite Hsz0. destruct (f x a0); simpl in Hsz; rewrite Hsz; cbn -[Z.add]; omega.
solve_Desc e.
Qed.
(** ** Verification of [update] *)
Lemma update_spec: forall (m: Map e a) (f: a -> option a) k,
update f k m = updateWithKey (fun _ x => f x) k m.
Proof.
intros. unfold update. reflexivity.
Qed.
(** ** Verification of [updateLookupWithKey] *)
Lemma updateLookupWithKey_lookup_f_true:
forall (m: Map e a) lb ub f k v v1,
Bounded m lb ub ->
Proper ((fun i j : e => _GHC.Base.==_ i j = true) ==> eq) f ->
sem m k = Some v ->
f k v = Some v1 ->
fst ((updateLookupWithKey f k m)) = Some v1.
Proof.
intros. generalize dependent k. revert v v1. induction H; intros.
- inversion H1.
- simpl. simpl in H6. destruct (sem s1 k) eqn : ?.
+ assert (compare k x = Lt) by (solve_Bounds e). rewrite H8.
rewrite (pair_fst_snd (updateLookupWithKey f k s1 )). simpl.
eapply IHBounded1. apply Heqo. inversion H6. apply H7.
+ simpl in H6. destruct (k == x) eqn : ?.
* simpl in H6. assert (compare k x = Eq) by (order e).
rewrite H8. destruct (f x v) eqn : ?.
-- simpl. inversion H6; subst. rewrite <- Heqo0. rewrite <- H7.
apply equal_f. apply H0. order e.
-- simpl. inversion H6; subst. assert (f k v0 = f x v0). apply equal_f.
apply H0. order e. rewrite <- H4 in Heqo0. rewrite Heqo0 in H7.
inversion H7.
* simpl. destruct (sem s2 k) eqn : ?.
-- assert (compare k x = Gt) by (solve_Bounds e). rewrite H8.
rewrite (pair_fst_snd (updateLookupWithKey f k s2 )). simpl.
eapply IHBounded2. apply Heqo0. inversion H6; subst. apply H7.
-- inversion H6.
Qed.
Lemma updateLookupWithKey_lookup_f_false:
forall (m: Map e a) lb ub f k v,
Bounded m lb ub ->
Proper ((fun i j : e => _GHC.Base.==_ i j = true) ==> eq) f ->
sem m k = Some v ->
f k v = None ->
fst ((updateLookupWithKey f k m)) = Some v.
Proof.
intros. generalize dependent v. revert k. induction H; intros.
- inversion H1.
- simpl in H6. simpl. destruct (sem s1 k) eqn : ?.
+ assert (compare k x = Lt) by (solve_Bounds e). rewrite H8.
rewrite (pair_fst_snd (updateLookupWithKey f k s1 )). simpl.
eapply IHBounded1. inversion H6; subst. apply Heqo. apply H7.
+ simpl in H6. destruct (k == x) eqn : ?.
* simpl in H6. assert (compare k x = Eq) by (order e).
rewrite H8. destruct (f x v) eqn : ?.
-- simpl. inversion H6; subst. assert (f k v0 = f x v0). apply equal_f.
apply H0. order e. rewrite H4 in H7. rewrite H7 in Heqo0. inversion Heqo0.
-- simpl. assumption.
* simpl in H6. assert (compare k x = Gt) by (solve_Bounds e). rewrite H8.
rewrite (pair_fst_snd (updateLookupWithKey f k s2 )). simpl.
eapply IHBounded2. apply H6. apply H7.
Qed.
Lemma updateLookupWithKey_lookup_None:
forall (m: Map e a) lb ub f k,
Bounded m lb ub ->
Proper ((fun i j : e => _GHC.Base.==_ i j = true) ==> eq) f ->
sem m k = None ->
fst ((updateLookupWithKey f k m)) = None.
Proof.
intros. generalize dependent k. induction H; intros.
- simpl. reflexivity.
- simpl in H6. simpl. destruct (sem s1 k) eqn : ?. inversion H6.
destruct (k == x) eqn : ?. inversion H6. destruct (sem s2 k) eqn : ?.
inversion H6.
destruct (compare k x) eqn : ?.
+ order e.
+ rewrite (pair_fst_snd (updateLookupWithKey f k s1 )). simpl. apply IHBounded1.
assumption.
+ rewrite (pair_fst_snd (updateLookupWithKey f k s2 )). simpl. apply IHBounded2.
assumption.
Qed.
(*This makes the Desc incredibly easy*)
Lemma updateWithKey_updateLookupWithKey: forall (m: Map e a) f k,
updateWithKey f k m = snd(updateLookupWithKey f k m).
Proof.
intros m. induction m; intros.
- simpl. destruct (compare k0 k).
+ destruct (f k a0); simpl; reflexivity.
+ rewrite (pair_fst_snd (updateLookupWithKey f k0 m1)). simpl.
rewrite IHm1. reflexivity.
+ rewrite (pair_fst_snd (updateLookupWithKey f k0 m2)). simpl.
rewrite IHm2. reflexivity.
- simpl. reflexivity.
Qed.
Lemma updateLookupWithKey_Desc:
forall x f (m: Map e a) lb ub,
Bounded m lb ub ->
Proper ((fun i j : e => _GHC.Base.==_ i j = true) ==> eq) f ->
Desc (snd(updateLookupWithKey f x m)) lb ub (match sem m x with
| None => size m
| Some y => if isSome (f x y) then
size m else size m - 1
end) (fun i => if i == x then match (sem m x) with
| Some v => f x v
| None => None end else sem m i).
Proof.
intros. rewrite <- updateWithKey_updateLookupWithKey. apply updateWithKey_Desc; assumption.
Qed.
(** ** Verification of [alter] *)
(*Note: the bounds assumptions are only needed in the insert case, but we can always expand the bounds
if needed*)
Lemma alter_Desc:
forall m (f: option a -> option a) k lb ub,
Bounded m lb ub ->
isLB lb k = true ->
isUB ub k = true ->
Desc(alter f k m) lb ub (if (negb (isSome (sem m k)) && isSome (f None)) then (1 + size m)%Z
else if (isSome(sem m k) && negb (isSome (f (sem m k)))) then (size m - 1)%Z else size m)
(fun i => (if i == k then f (sem m k) else sem m i)).
Proof.
intros ????? HB HL HU. induction HB.
- simpl. destruct (f None).
+ applyDesc e (@singleton_Desc e a). solve_Desc e.
+ solve_Desc e.
- cbn -[Z.add]. destruct (compare k x) eqn : Heq.
+ replace (k == x) with true by solve_Bounds e. simpl_options.
destruct (f (Some v)) eqn : ?.
* solve_Desc e. simpl.
rewrite -> (sem_outside_above HB1) by (solve_Bounds e). simpl_options.
rewrite Heqo. simpl. reflexivity. f_solver e.
assert (sem s1 k = None). eapply sem_outside_above. eassumption.
solve_Bounds e. rewrite H3 in Heqo1. simpl in Heqo1. rewrite Heqo1 in Heqo.
inversion Heqo. reflexivity.
assert (sem s1 k = None). eapply sem_outside_above. eassumption. solve_Bounds e.
rewrite H3 in Heqo1. simpl in Heqo1. rewrite Heqo1 in Heqo. inversion Heqo.
* rewrite -> (sem_outside_above HB1) by (solve_Bounds e).
rewrite -> (sem_outside_below HB2) by (solve_Bounds e).
simpl_options. applyDesc e glue_Desc. solve_Desc e.
simpl. rewrite Heqo. simpl. solve_size.
+ replace (k == x) with false by solve_Bounds e.
rewrite -> (sem_outside_below HB2) by (solve_Bounds e).
simpl_options.
applyDesc e IHHB1. applyDesc e (@balance_Desc e a). destruct (sem s1 k). simpl in Hsz.
destruct (f (Some a0)); simpl in Hsz; solve_size. cbn -[Z.add] in *.
destruct (f None). cbn -[Z.add] in *. solve_size.
simpl in Hsz. solve_size. solve_Desc e.
rewrite Hsz0. rewrite Hsz. destruct (sem s1 k); cbn -[Z.add].
destruct (f(Some a0)); cbn -[Z.add]; solve_size.
destruct (f(None)); cbn -[Z.add]; solve_size.
+ replace (k == x) with false by (order e).
rewrite -> (sem_outside_above HB1) by (solve_Bounds e).
simpl_options.
applyDesc e IHHB2. applyDesc e (@balance_Desc e a). destruct (sem s2 k); cbn -[Z.add] in *.
destruct (f(Some a0)); cbn -[Z.add] in *; solve_size.
destruct (f(None)); cbn -[Z.add] in *; solve_size.
solve_Desc e. rewrite Hsz0. rewrite Hsz. destruct (sem s2 k); cbn -[Z.add].
destruct (f(Some a0)); cbn -[Z.add]; solve_size.
destruct (f(None)); cbn -[Z.add]; solve_size.
Qed.
Lemma delete_WF:
forall x (s: Map e a), WF s -> WF (delete x s).
Proof.
intros. eapply Desc_WF.
eapply delete_Desc. assumption.
Qed.
Lemma alter_WF :
forall f x (s : Map e a), WF s -> WF (alter f x s).
Proof.
intros. eapply Desc_WF.
eapply alter_Desc; [assumption | reflexivity | reflexivity ].
Qed.
Lemma adjust_WF :
forall f x (s : Map e a),
WF s -> WF (adjust f x s).
Proof.
intros. eapply Desc_WF. rewrite adjust_spec.
eapply adjustWithKey_Desc.
- assumption.
- intros i j Heq. reflexivity.
Qed.
End WF.
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0\
,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AX\
I_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=2,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=1,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg484,C_GP0_EN_MODIFIABLE_TXN=0,C_GP1_EN_MODIFIABLE\
_TXN=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_processing_system7_0_0 (
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *)
output wire S_AXI_HP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *)
output wire S_AXI_HP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *)
output wire S_AXI_HP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *)
output wire S_AXI_HP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *)
output wire S_AXI_HP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *)
output wire S_AXI_HP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *)
output wire [1 : 0] S_AXI_HP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *)
output wire [1 : 0] S_AXI_HP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *)
output wire [5 : 0] S_AXI_HP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *)
output wire [5 : 0] S_AXI_HP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *)
output wire [63 : 0] S_AXI_HP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *)
output wire [7 : 0] S_AXI_HP0_RCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *)
output wire [7 : 0] S_AXI_HP0_WCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *)
output wire [2 : 0] S_AXI_HP0_RACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *)
output wire [5 : 0] S_AXI_HP0_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *)
input wire S_AXI_HP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *)
input wire S_AXI_HP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *)
input wire S_AXI_HP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *)
input wire S_AXI_HP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *)
input wire S_AXI_HP0_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *)
input wire S_AXI_HP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *)
input wire S_AXI_HP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *)
input wire S_AXI_HP0_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *)
input wire S_AXI_HP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *)
input wire [1 : 0] S_AXI_HP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *)
input wire [1 : 0] S_AXI_HP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *)
input wire [2 : 0] S_AXI_HP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *)
input wire [1 : 0] S_AXI_HP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *)
input wire [1 : 0] S_AXI_HP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *)
input wire [2 : 0] S_AXI_HP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *)
input wire [2 : 0] S_AXI_HP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *)
input wire [2 : 0] S_AXI_HP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *)
input wire [31 : 0] S_AXI_HP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *)
input wire [31 : 0] S_AXI_HP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *)
input wire [3 : 0] S_AXI_HP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *)
input wire [3 : 0] S_AXI_HP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *)
input wire [3 : 0] S_AXI_HP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *)
input wire [3 : 0] S_AXI_HP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *)
input wire [3 : 0] S_AXI_HP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *)
input wire [3 : 0] S_AXI_HP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *)
input wire [5 : 0] S_AXI_HP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *)
input wire [5 : 0] S_AXI_HP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *)
input wire [5 : 0] S_AXI_HP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *)
input wire [63 : 0] S_AXI_HP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *)
input wire [7 : 0] S_AXI_HP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [1 : 0] IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(2),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"),
.C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"),
.C_PACKAGE_NAME("clg484"),
.C_GP0_EN_MODIFIABLE_TXN(0),
.C_GP1_EN_MODIFIABLE_TXN(0)
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT),
.S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT),
.S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT),
.S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// File : ../RTL/serialInterfaceEngine/SIETransmitter.v
// Generated : 10/15/06 20:31:22
// From : ../RTL/serialInterfaceEngine/SIETransmitter.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// SIETransmitter
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
module SIETransmitter (CRC16En, CRC16Result, CRC16UpdateRdy, CRC5En, CRC5Result, CRC5UpdateRdy, CRC5_8Bit, CRCData, JBit, KBit, SIEPortCtrlIn, SIEPortDataIn, SIEPortTxRdy, SIEPortWEn, TxByteOutCtrl, TxByteOutFullSpeedRate, TxByteOut, USBWireCtrl, USBWireData, USBWireFullSpeedRate, USBWireGnt, USBWireRdy, USBWireReq, USBWireWEn, clk, fullSpeedRateIn, processTxByteRdy, processTxByteWEn, rst, rstCRC);
input [15:0] CRC16Result;
input CRC16UpdateRdy;
input [4:0] CRC5Result;
input CRC5UpdateRdy;
input [1:0] JBit;
input [1:0] KBit;
input [7:0] SIEPortCtrlIn;
input [7:0] SIEPortDataIn;
input SIEPortWEn;
input USBWireGnt;
input USBWireRdy;
input clk;
input fullSpeedRateIn;
input processTxByteRdy;
input rst;
output CRC16En;
output CRC5En;
output CRC5_8Bit;
output [7:0] CRCData;
output SIEPortTxRdy;
output [7:0] TxByteOutCtrl;
output TxByteOutFullSpeedRate;
output [7:0] TxByteOut;
output USBWireCtrl;
output [1:0] USBWireData;
output USBWireFullSpeedRate;
output USBWireReq;
output USBWireWEn;
output processTxByteWEn;
output rstCRC;
reg CRC16En, next_CRC16En;
wire [15:0] CRC16Result;
wire CRC16UpdateRdy;
reg CRC5En, next_CRC5En;
wire [4:0] CRC5Result;
wire CRC5UpdateRdy;
reg CRC5_8Bit, next_CRC5_8Bit;
reg [7:0] CRCData, next_CRCData;
wire [1:0] JBit;
wire [1:0] KBit;
wire [7:0] SIEPortCtrlIn;
wire [7:0] SIEPortDataIn;
reg SIEPortTxRdy, next_SIEPortTxRdy;
wire SIEPortWEn;
reg [7:0] TxByteOutCtrl, next_TxByteOutCtrl;
reg TxByteOutFullSpeedRate, next_TxByteOutFullSpeedRate;
reg [7:0] TxByteOut, next_TxByteOut;
reg USBWireCtrl, next_USBWireCtrl;
reg [1:0] USBWireData, next_USBWireData;
reg USBWireFullSpeedRate, next_USBWireFullSpeedRate;
wire USBWireGnt;
wire USBWireRdy;
reg USBWireReq, next_USBWireReq;
reg USBWireWEn, next_USBWireWEn;
wire clk;
wire fullSpeedRateIn;
wire processTxByteRdy;
reg processTxByteWEn, next_processTxByteWEn;
wire rst;
reg rstCRC, next_rstCRC;
// diagram signals declarations
reg [7:0]SIEPortCtrl, next_SIEPortCtrl;
reg [7:0]SIEPortData, next_SIEPortData;
reg [2:0]i, next_i;
reg [15:0]resumeCnt, next_resumeCnt;
// BINARY ENCODED state machine: SIETx
// State codes definitions:
`define DIR_CTL_CHK_FIN 6'b000000
`define RES_ST_CHK_FIN 6'b000001
`define PKT_ST_CHK_PID 6'b000010
`define PKT_ST_DATA_DATA_CHK_STOP 6'b000011
`define IDLE 6'b000100
`define PKT_ST_DATA_DATA_PKT_SENT 6'b000101
`define PKT_ST_DATA_PID_PKT_SENT 6'b000110
`define PKT_ST_HS_PKT_SENT 6'b000111
`define PKT_ST_TKN_CRC_PKT_SENT 6'b001000
`define PKT_ST_TKN_PID_PKT_SENT 6'b001001
`define PKT_ST_SPCL_PKT_SENT 6'b001010
`define PKT_ST_DATA_CRC_PKT_SENT1 6'b001011
`define PKT_ST_TKN_BYTE1_PKT_SENT1 6'b001100
`define PKT_ST_DATA_CRC_PKT_SENT2 6'b001101
`define RES_ST_SND_J_1 6'b001110
`define RES_ST_SND_J_2 6'b001111
`define RES_ST_SND_SE0_1 6'b010000
`define RES_ST_SND_SE0_2 6'b010001
`define START_SIETX 6'b010010
`define STX_CHK_ST 6'b010011
`define STX_WAIT_BYTE 6'b010100
`define PKT_ST_TKN_CRC_UPD_CRC 6'b010101
`define PKT_ST_TKN_BYTE1_UPD_CRC 6'b010110
`define PKT_ST_DATA_DATA_UPD_CRC 6'b010111
`define PKT_ST_TKN_CRC_WAIT_BYTE 6'b011000
`define PKT_ST_TKN_BYTE1_WAIT_BYTE 6'b011001
`define PKT_ST_DATA_DATA_WAIT_BYTE 6'b011010
`define DIR_CTL_WAIT_GNT 6'b011011
`define RES_ST_WAIT_GNT 6'b011100
`define PKT_ST_HS_WAIT_RDY 6'b011101
`define DIR_CTL_WAIT_RDY 6'b011110
`define PKT_ST_SPCL_WAIT_RDY 6'b011111
`define PKT_ST_TKN_CRC_WAIT_RDY 6'b100000
`define PKT_ST_TKN_PID_WAIT_RDY 6'b100001
`define PKT_ST_DATA_DATA_WAIT_RDY 6'b100010
`define RES_ST_WAIT_RDY 6'b100011
`define PKT_ST_TKN_BYTE1_WAIT_RDY 6'b100100
`define PKT_ST_DATA_PID_WAIT_RDY 6'b100101
`define PKT_ST_DATA_CRC_WAIT_RDY1 6'b100110
`define PKT_ST_DATA_CRC_WAIT_RDY2 6'b100111
`define PKT_ST_WAIT_RDY_PKT 6'b101000
`define RES_ST_W_RDY1 6'b101001
`define PKT_ST_TKN_CRC_WAIT_CRC_RDY 6'b101010
`define PKT_ST_DATA_DATA_WAIT_CRC_RDY 6'b101011
`define PKT_ST_TKN_BYTE1_WAIT_CRC_RDY 6'b101100
`define TX_LS_EOP_WAIT_GNT1 6'b101101
`define TX_LS_EOP_SND_SE0_2 6'b101110
`define TX_LS_EOP_SND_SE0_1 6'b101111
`define TX_LS_EOP_W_RDY1 6'b110000
`define TX_LS_EOP_SND_J 6'b110001
`define TX_LS_EOP_W_RDY2 6'b110010
`define TX_LS_EOP_W_RDY3 6'b110011
`define RES_ST_DELAY 6'b110100
`define RES_ST_W_RDY2 6'b110101
`define RES_ST_W_RDY3 6'b110110
`define RES_ST_W_RDY4 6'b110111
`define DIR_CTL_DELAY 6'b111000
reg [5:0] CurrState_SIETx;
reg [5:0] NextState_SIETx;
//--------------------------------------------------------------------
// Machine: SIETx
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (SIEPortDataIn or SIEPortCtrlIn or fullSpeedRateIn or i or SIEPortData or CRC16Result or CRC5Result or KBit or resumeCnt or JBit or SIEPortCtrl or SIEPortWEn or USBWireGnt or USBWireRdy or processTxByteRdy or CRC16UpdateRdy or CRC5UpdateRdy or processTxByteWEn or TxByteOut or TxByteOutCtrl or USBWireData or USBWireCtrl or USBWireReq or USBWireWEn or rstCRC or CRCData or CRC5En or CRC5_8Bit or CRC16En or SIEPortTxRdy or TxByteOutFullSpeedRate or USBWireFullSpeedRate or CurrState_SIETx)
begin : SIETx_NextState
NextState_SIETx <= CurrState_SIETx;
// Set default values for outputs and signals
next_processTxByteWEn <= processTxByteWEn;
next_TxByteOut <= TxByteOut;
next_TxByteOutCtrl <= TxByteOutCtrl;
next_USBWireData <= USBWireData;
next_USBWireCtrl <= USBWireCtrl;
next_USBWireReq <= USBWireReq;
next_USBWireWEn <= USBWireWEn;
next_rstCRC <= rstCRC;
next_CRCData <= CRCData;
next_CRC5En <= CRC5En;
next_CRC5_8Bit <= CRC5_8Bit;
next_CRC16En <= CRC16En;
next_SIEPortTxRdy <= SIEPortTxRdy;
next_SIEPortData <= SIEPortData;
next_SIEPortCtrl <= SIEPortCtrl;
next_i <= i;
next_resumeCnt <= resumeCnt;
next_TxByteOutFullSpeedRate <= TxByteOutFullSpeedRate;
next_USBWireFullSpeedRate <= USBWireFullSpeedRate;
case (CurrState_SIETx)
`IDLE:
NextState_SIETx <= `STX_WAIT_BYTE;
`START_SIETX:
begin
next_processTxByteWEn <= 1'b0;
next_TxByteOut <= 8'h00;
next_TxByteOutCtrl <= 8'h00;
next_USBWireData <= 2'b00;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireReq <= 1'b0;
next_USBWireWEn <= 1'b0;
next_rstCRC <= 1'b0;
next_CRCData <= 8'h00;
next_CRC5En <= 1'b0;
next_CRC5_8Bit <= 1'b0;
next_CRC16En <= 1'b0;
next_SIEPortTxRdy <= 1'b0;
next_SIEPortData <= 8'h00;
next_SIEPortCtrl <= 8'h00;
next_i <= 3'h0;
next_resumeCnt <= 16'h0000;
next_TxByteOutFullSpeedRate <= 1'b0;
next_USBWireFullSpeedRate <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`STX_CHK_ST:
if ((SIEPortCtrl == `TX_PACKET_START) && (SIEPortData[3:0] == `SOF || SIEPortData[3:0] == `PREAMBLE))
begin
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
next_TxByteOutFullSpeedRate <= 1'b1;
//SOF and PRE always at full speed
end
else if (SIEPortCtrl == `TX_PACKET_START)
NextState_SIETx <= `PKT_ST_WAIT_RDY_PKT;
else if (SIEPortCtrl == `TX_LS_KEEP_ALIVE)
begin
NextState_SIETx <= `TX_LS_EOP_WAIT_GNT1;
next_USBWireReq <= 1'b1;
end
else if (SIEPortCtrl == `TX_DIRECT_CONTROL)
begin
NextState_SIETx <= `DIR_CTL_WAIT_GNT;
next_USBWireReq <= 1'b1;
end
else if (SIEPortCtrl == `TX_IDLE)
NextState_SIETx <= `IDLE;
else if (SIEPortCtrl == `TX_RESUME_START)
begin
NextState_SIETx <= `RES_ST_WAIT_GNT;
next_USBWireReq <= 1'b1;
next_resumeCnt <= 16'h0000;
next_USBWireFullSpeedRate <= 1'b0;
//resume always uses low speed timing
end
`STX_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `STX_CHK_ST;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
next_TxByteOutFullSpeedRate <= fullSpeedRateIn;
next_USBWireFullSpeedRate <= fullSpeedRateIn;
end
end
`DIR_CTL_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
next_i <= i + 1'b1;
if (i == 3'h7)
begin
NextState_SIETx <= `STX_WAIT_BYTE;
next_USBWireReq <= 1'b0;
end
else
NextState_SIETx <= `DIR_CTL_DELAY;
end
`DIR_CTL_WAIT_GNT:
begin
next_i <= 3'h0;
if (USBWireGnt == 1'b1)
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
end
`DIR_CTL_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `DIR_CTL_CHK_FIN;
next_USBWireData <= SIEPortData[1:0];
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`DIR_CTL_DELAY:
NextState_SIETx <= `DIR_CTL_WAIT_RDY;
`PKT_ST_CHK_PID:
begin
next_processTxByteWEn <= 1'b0;
if (SIEPortData[1:0] == `TOKEN)
NextState_SIETx <= `PKT_ST_TKN_PID_WAIT_RDY;
else if (SIEPortData[1:0] == `HANDSHAKE)
NextState_SIETx <= `PKT_ST_HS_WAIT_RDY;
else if (SIEPortData[1:0] == `DATA)
NextState_SIETx <= `PKT_ST_DATA_PID_WAIT_RDY;
else if (SIEPortData[1:0] == `SPECIAL)
NextState_SIETx <= `PKT_ST_SPCL_WAIT_RDY;
end
`PKT_ST_WAIT_RDY_PKT:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_CHK_PID;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= `SYNC_BYTE;
next_TxByteOutCtrl <= `DATA_START;
end
`PKT_ST_DATA_CRC_PKT_SENT1:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY2;
end
`PKT_ST_DATA_CRC_PKT_SENT2:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_DATA_CRC_WAIT_RDY1:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT1;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= ~CRC16Result[7:0];
next_TxByteOutCtrl <= `DATA_STREAM;
end
`PKT_ST_DATA_CRC_WAIT_RDY2:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_CRC_PKT_SENT2;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= ~CRC16Result[15:8];
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_DATA_DATA_CHK_STOP:
if (SIEPortCtrl == `TX_PACKET_STOP)
NextState_SIETx <= `PKT_ST_DATA_CRC_WAIT_RDY1;
else
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_CRC_RDY;
`PKT_ST_DATA_DATA_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
end
`PKT_ST_DATA_DATA_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC16En <= 1'b1;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_RDY;
end
`PKT_ST_DATA_DATA_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_DATA_CHK_STOP;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_DATA_DATA_WAIT_RDY:
begin
next_CRC16En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_DATA_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
end
end
`PKT_ST_DATA_DATA_WAIT_CRC_RDY:
if (CRC16UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_DATA_DATA_UPD_CRC;
`PKT_ST_DATA_PID_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
next_rstCRC <= 1'b0;
NextState_SIETx <= `PKT_ST_DATA_DATA_WAIT_BYTE;
end
`PKT_ST_DATA_PID_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_DATA_PID_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
next_rstCRC <= 1'b1;
end
`PKT_ST_HS_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_HS_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_HS_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_SPCL_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_SPCL_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_SPCL_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
if (SIEPortData[3:0] == `PREAMBLE)
next_TxByteOutCtrl <= `DATA_STOP_PRE;
else
next_TxByteOutCtrl <= `DATA_STOP;
end
`PKT_ST_TKN_BYTE1_PKT_SENT1:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_BYTE;
end
`PKT_ST_TKN_BYTE1_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC5_8Bit <= 1'b1;
next_CRC5En <= 1'b1;
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_RDY;
end
`PKT_ST_TKN_BYTE1_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_CRC_RDY;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_TKN_BYTE1_WAIT_RDY:
begin
next_CRC5En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_BYTE1_PKT_SENT1;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
end
end
`PKT_ST_TKN_BYTE1_WAIT_CRC_RDY:
if (CRC5UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_TKN_BYTE1_UPD_CRC;
`PKT_ST_TKN_CRC_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`PKT_ST_TKN_CRC_UPD_CRC:
begin
next_CRCData <= SIEPortData;
next_CRC5_8Bit <= 1'b0;
next_CRC5En <= 1'b1;
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_RDY;
end
`PKT_ST_TKN_CRC_WAIT_BYTE:
begin
next_SIEPortTxRdy <= 1'b1;
if (SIEPortWEn == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_CRC_WAIT_CRC_RDY;
next_SIEPortData <= SIEPortDataIn;
next_SIEPortCtrl <= SIEPortCtrlIn;
next_SIEPortTxRdy <= 1'b0;
end
end
`PKT_ST_TKN_CRC_WAIT_RDY:
begin
next_CRC5En <= 1'b0;
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_CRC_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= {~CRC5Result, SIEPortData[2:0] };
next_TxByteOutCtrl <= `DATA_STOP;
end
end
`PKT_ST_TKN_CRC_WAIT_CRC_RDY:
if (CRC5UpdateRdy == 1'b1)
NextState_SIETx <= `PKT_ST_TKN_CRC_UPD_CRC;
`PKT_ST_TKN_PID_PKT_SENT:
begin
next_processTxByteWEn <= 1'b0;
next_rstCRC <= 1'b0;
NextState_SIETx <= `PKT_ST_TKN_BYTE1_WAIT_BYTE;
end
`PKT_ST_TKN_PID_WAIT_RDY:
if (processTxByteRdy == 1'b1)
begin
NextState_SIETx <= `PKT_ST_TKN_PID_PKT_SENT;
next_processTxByteWEn <= 1'b1;
next_TxByteOut <= SIEPortData;
next_TxByteOutCtrl <= `DATA_STREAM;
next_rstCRC <= 1'b1;
end
`RES_ST_CHK_FIN:
begin
next_USBWireWEn <= 1'b0;
if (resumeCnt == `HOST_TX_RESUME_TIME)
NextState_SIETx <= `RES_ST_W_RDY1;
else
NextState_SIETx <= `RES_ST_DELAY;
end
`RES_ST_SND_J_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY4;
end
`RES_ST_SND_J_2:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
next_USBWireFullSpeedRate <= fullSpeedRateIn;
end
`RES_ST_SND_SE0_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY2;
end
`RES_ST_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `RES_ST_W_RDY3;
end
`RES_ST_WAIT_GNT:
if (USBWireGnt == 1'b1)
NextState_SIETx <= `RES_ST_WAIT_RDY;
`RES_ST_WAIT_RDY:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_CHK_FIN;
next_USBWireData <= KBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
next_resumeCnt <= resumeCnt + 1'b1;
end
`RES_ST_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_SE0_1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_DELAY:
NextState_SIETx <= `RES_ST_WAIT_RDY;
`RES_ST_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_SE0_2;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_J_1;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`RES_ST_W_RDY4:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `RES_ST_SND_J_2;
next_USBWireData <= JBit;
next_USBWireCtrl <= `TRI_STATE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_WAIT_GNT1:
if (USBWireGnt == 1'b1)
NextState_SIETx <= `TX_LS_EOP_W_RDY1;
`TX_LS_EOP_SND_SE0_2:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `TX_LS_EOP_W_RDY3;
end
`TX_LS_EOP_SND_SE0_1:
begin
next_USBWireWEn <= 1'b0;
NextState_SIETx <= `TX_LS_EOP_W_RDY2;
end
`TX_LS_EOP_W_RDY1:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_SE0_1;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_SND_J:
begin
next_USBWireWEn <= 1'b0;
next_USBWireReq <= 1'b0;
NextState_SIETx <= `STX_WAIT_BYTE;
end
`TX_LS_EOP_W_RDY2:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_SE0_2;
next_USBWireData <= `SE0;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
`TX_LS_EOP_W_RDY3:
if (USBWireRdy == 1'b1)
begin
NextState_SIETx <= `TX_LS_EOP_SND_J;
next_USBWireData <= JBit;
next_USBWireCtrl <= `DRIVE;
next_USBWireWEn <= 1'b1;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SIETx_CurrentState
if (rst)
CurrState_SIETx <= `START_SIETX;
else
CurrState_SIETx <= NextState_SIETx;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SIETx_RegOutput
if (rst)
begin
SIEPortData <= 8'h00;
SIEPortCtrl <= 8'h00;
i <= 3'h0;
resumeCnt <= 16'h0000;
processTxByteWEn <= 1'b0;
TxByteOut <= 8'h00;
TxByteOutCtrl <= 8'h00;
USBWireData <= 2'b00;
USBWireCtrl <= `TRI_STATE;
USBWireReq <= 1'b0;
USBWireWEn <= 1'b0;
rstCRC <= 1'b0;
CRCData <= 8'h00;
CRC5En <= 1'b0;
CRC5_8Bit <= 1'b0;
CRC16En <= 1'b0;
SIEPortTxRdy <= 1'b0;
TxByteOutFullSpeedRate <= 1'b0;
USBWireFullSpeedRate <= 1'b0;
end
else
begin
SIEPortData <= next_SIEPortData;
SIEPortCtrl <= next_SIEPortCtrl;
i <= next_i;
resumeCnt <= next_resumeCnt;
processTxByteWEn <= next_processTxByteWEn;
TxByteOut <= next_TxByteOut;
TxByteOutCtrl <= next_TxByteOutCtrl;
USBWireData <= next_USBWireData;
USBWireCtrl <= next_USBWireCtrl;
USBWireReq <= next_USBWireReq;
USBWireWEn <= next_USBWireWEn;
rstCRC <= next_rstCRC;
CRCData <= next_CRCData;
CRC5En <= next_CRC5En;
CRC5_8Bit <= next_CRC5_8Bit;
CRC16En <= next_CRC16En;
SIEPortTxRdy <= next_SIEPortTxRdy;
TxByteOutFullSpeedRate <= next_TxByteOutFullSpeedRate;
USBWireFullSpeedRate <= next_USBWireFullSpeedRate;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__FA_PP_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_SYMBOL_V
`define SKY130_FD_SC_HD__A41OI_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_1_V
`define SKY130_FD_SC_HVL__DLCLKP_1_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_1_V
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=8 LPM_WIDTHN=6 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgofk
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [7:0] denom;
input [5:0] numer;
output [5:0] quotient;
output [7:0] remain;
wire [5:0] wire_mgl_prim1_quotient;
wire [7:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 8,
mgl_prim1.lpm_widthn = 6,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgofk
//VALID FILE
|
// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// Quartus II 6.0 Build 202 04/27/2006
// ********** PRIMITIVE DEFINITIONS **********
`timescale 1 ps/1 ps
// ***** DFFE
primitive CYCLONEII_PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
input D;
input CLRN;
input PRN;
input CLK;
input ENA;
input notifier;
output Q; reg Q;
initial Q = 1'b0;
table
// ENA D CLK CLRN PRN notifier : Qt : Qt+1
(??) ? ? 1 1 ? : ? : -; // pessimism
x ? ? 1 1 ? : ? : -; // pessimism
1 1 (01) 1 1 ? : ? : 1; // clocked data
1 1 (01) 1 x ? : ? : 1; // pessimism
1 1 ? 1 x ? : 1 : 1; // pessimism
1 0 0 1 x ? : 1 : 1; // pessimism
1 0 x 1 (?x) ? : 1 : 1; // pessimism
1 0 1 1 (?x) ? : 1 : 1; // pessimism
1 x 0 1 x ? : 1 : 1; // pessimism
1 x x 1 (?x) ? : 1 : 1; // pessimism
1 x 1 1 (?x) ? : 1 : 1; // pessimism
1 0 (01) 1 1 ? : ? : 0; // clocked data
1 0 (01) x 1 ? : ? : 0; // pessimism
1 0 ? x 1 ? : 0 : 0; // pessimism
0 ? ? x 1 ? : ? : -;
1 1 0 x 1 ? : 0 : 0; // pessimism
1 1 x (?x) 1 ? : 0 : 0; // pessimism
1 1 1 (?x) 1 ? : 0 : 0; // pessimism
1 x 0 x 1 ? : 0 : 0; // pessimism
1 x x (?x) 1 ? : 0 : 0; // pessimism
1 x 1 (?x) 1 ? : 0 : 0; // pessimism
// 1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
// 1 0 (x1) 1 1 ? : 0 : 0;
1 ? (x1) 1 1 ? : ? : -; // spr 80166-ignore
// x->1 edge
1 1 (0x) 1 1 ? : 1 : 1;
1 0 (0x) 1 1 ? : 0 : 0;
? ? ? 0 0 ? : ? : 0; // clear wins preset
? ? ? 0 1 ? : ? : 0; // asynch clear
? ? ? 1 0 ? : ? : 1; // asynch set
1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
1 * ? ? ? ? : ? : -; // ignore data edges
1 ? ? (?1) ? ? : ? : -; // ignore edges on
1 ? ? ? (?1) ? : ? : -; // set and clear
0 ? ? 1 1 ? : ? : -; // set and clear
? ? ? 1 1 * : ? : x; // spr 36954 - at any
// notifier event,
// output 'x'
endtable
endprimitive
module cycloneii_dffe ( Q, CLK, ENA, D, CLRN, PRN );
input D;
input CLK;
input CLRN;
input PRN;
input ENA;
output Q;
wire D_ipd;
wire ENA_ipd;
wire CLK_ipd;
wire PRN_ipd;
wire CLRN_ipd;
buf (D_ipd, D);
buf (ENA_ipd, ENA);
buf (CLK_ipd, CLK);
buf (PRN_ipd, PRN);
buf (CLRN_ipd, CLRN);
wire legal;
reg viol_notifier;
CYCLONEII_PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier );
and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
specify
specparam TREG = 0;
specparam TREN = 0;
specparam TRSU = 0;
specparam TRH = 0;
specparam TRPR = 0;
specparam TRCL = 0;
$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
endspecify
endmodule
// ***** cycloneii_latch
module cycloneii_latch(D, ENA, PRE, CLR, Q);
input D;
input ENA, PRE, CLR;
output Q;
reg q_out;
specify
$setup (D, posedge ENA, 0) ;
$hold (negedge ENA, D, 0) ;
(D => Q) = (0, 0);
(posedge ENA => (Q +: q_out)) = (0, 0);
(negedge PRE => (Q +: q_out)) = (0, 0);
(negedge CLR => (Q +: q_out)) = (0, 0);
endspecify
wire D_in;
wire ENA_in;
wire PRE_in;
wire CLR_in;
buf (D_in, D);
buf (ENA_in, ENA);
buf (PRE_in, PRE);
buf (CLR_in, CLR);
initial
begin
q_out = 1'b0;
end
always @(D_in or ENA_in or PRE_in or CLR_in)
begin
if (PRE_in == 1'b0)
begin
// latch being preset, preset is active low
q_out = 1'b1;
end
else if (CLR_in == 1'b0)
begin
// latch being cleared, clear is active low
q_out = 1'b0;
end
else if (ENA_in == 1'b1)
begin
// latch is transparent
q_out = D_in;
end
end
and (Q, q_out, 1'b1);
endmodule
// ***** cycloneii_mux21
module cycloneii_mux21 (MO, A, B, S);
input A, B, S;
output MO;
wire A_in;
wire B_in;
wire S_in;
buf(A_in, A);
buf(B_in, B);
buf(S_in, S);
wire tmp_MO;
specify
(A => MO) = (0, 0);
(B => MO) = (0, 0);
(S => MO) = (0, 0);
endspecify
assign tmp_MO = (S_in == 1) ? B_in : A_in;
buf (MO, tmp_MO);
endmodule
// ***** cycloneii_mux41
module cycloneii_mux41 (MO, IN0, IN1, IN2, IN3, S);
input IN0;
input IN1;
input IN2;
input IN3;
input [1:0] S;
output MO;
wire IN0_in;
wire IN1_in;
wire IN2_in;
wire IN3_in;
wire S1_in;
wire S0_in;
buf(IN0_in, IN0);
buf(IN1_in, IN1);
buf(IN2_in, IN2);
buf(IN3_in, IN3);
buf(S1_in, S[1]);
buf(S0_in, S[0]);
wire tmp_MO;
specify
(IN0 => MO) = (0, 0);
(IN1 => MO) = (0, 0);
(IN2 => MO) = (0, 0);
(IN3 => MO) = (0, 0);
(S[1] => MO) = (0, 0);
(S[0] => MO) = (0, 0);
endspecify
assign tmp_MO = S1_in ? (S0_in ? IN3_in : IN2_in) : (S0_in ? IN1_in : IN0_in);
buf (MO, tmp_MO);
endmodule
// ***** cycloneii_and1
module cycloneii_and1 (Y, IN1);
input IN1;
output Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y, IN1);
endmodule
// ***** cycloneii_and16
module cycloneii_and16 (Y, IN1);
input [15:0] IN1;
output [15:0] Y;
specify
(IN1 => Y) = (0, 0);
endspecify
buf (Y[0], IN1[0]);
buf (Y[1], IN1[1]);
buf (Y[2], IN1[2]);
buf (Y[3], IN1[3]);
buf (Y[4], IN1[4]);
buf (Y[5], IN1[5]);
buf (Y[6], IN1[6]);
buf (Y[7], IN1[7]);
buf (Y[8], IN1[8]);
buf (Y[9], IN1[9]);
buf (Y[10], IN1[10]);
buf (Y[11], IN1[11]);
buf (Y[12], IN1[12]);
buf (Y[13], IN1[13]);
buf (Y[14], IN1[14]);
buf (Y[15], IN1[15]);
endmodule
// ***** cycloneii_bmux21
module cycloneii_bmux21 (MO, A, B, S);
input [15:0] A, B;
input S;
output [15:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneii_b17mux21
module cycloneii_b17mux21 (MO, A, B, S);
input [16:0] A, B;
input S;
output [16:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ***** cycloneii_nmux21
module cycloneii_nmux21 (MO, A, B, S);
input A, B, S;
output MO;
assign MO = (S == 1) ? ~B : ~A;
endmodule
// ***** cycloneii_b5mux21
module cycloneii_b5mux21 (MO, A, B, S);
input [4:0] A, B;
input S;
output [4:0] MO;
assign MO = (S == 1) ? B : A;
endmodule
// ********** END PRIMITIVE DEFINITIONS **********
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_pulse_generator
// Description : Generate pulse to initiate memory read/write operations
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_ram_pulse_generator (
clk,
ena,
pulse,
cycle
);
input clk; // clock
input ena; // pulse enable
output pulse; // pulse
output cycle; // delayed clock
reg state;
wire clk_ipd;
specify
specparam t_decode = 0,t_access = 0;
(posedge clk => (pulse +: state)) = (t_decode,t_access);
endspecify
buf #(1) (clk_ipd,clk);
wire pulse_opd;
buf buf_pulse (pulse,pulse_opd);
always @(posedge clk_ipd or posedge pulse)
begin
if (pulse) state <= 1'b0;
else if (ena) state <= 1'b1;
end
assign cycle = clk_ipd;
assign pulse_opd = state;
endmodule
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_register
// Description : Register module for RAM inputs/outputs
//--------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_ram_register (
d,
clk,
aclr,
devclrn,
devpor,
stall,
ena,
q,
aclrout
);
parameter width = 1; // data width
parameter preset = 1'b0; // clear acts as preset
input [width - 1:0] d; // data
input clk; // clock
input aclr; // asynch clear
input devclrn,devpor; // device wide clear/reset
input stall; // address stall
input ena; // clock enable
output [width - 1:0] q; // register output
output aclrout; // delayed asynch clear
wire ena_ipd;
wire clk_ipd;
wire aclr_ipd;
wire [width - 1:0] d_ipd;
buf buf_ena (ena_ipd,ena);
buf buf_clk (clk_ipd,clk);
buf buf_aclr (aclr_ipd,aclr);
buf buf_d [width - 1:0] (d_ipd,d);
wire stall_ipd;
buf buf_stall (stall_ipd,stall);
wire [width - 1:0] q_opd;
buf buf_q [width - 1:0] (q,q_opd);
reg [width - 1:0] q_reg;
reg viol_notifier;
wire reset;
assign reset = devpor && devclrn && (!aclr_ipd) && (ena_ipd);
specify
$setup (d, posedge clk &&& reset, 0, viol_notifier);
$setup (aclr, posedge clk, 0, viol_notifier);
$setup (ena, posedge clk &&& reset, 0, viol_notifier );
$setup (stall, posedge clk &&& reset, 0, viol_notifier );
$hold (posedge clk &&& reset, d , 0, viol_notifier);
$hold (posedge clk, aclr, 0, viol_notifier);
$hold (posedge clk &&& reset, ena , 0, viol_notifier );
$hold (posedge clk &&& reset, stall, 0, viol_notifier );
(posedge clk => (q +: q_reg)) = (0,0);
(posedge aclr => (q +: q_reg)) = (0,0);
endspecify
initial q_reg <= (preset) ? {width{1'b1}} : 'b0;
always @(posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (aclr_ipd || ~devclrn || ~devpor)
q_reg <= (preset) ? {width{1'b1}} : 'b0;
else if (ena_ipd & !stall_ipd)
q_reg <= d_ipd;
end
assign aclrout = aclr_ipd;
assign q_opd = q_reg;
endmodule
`timescale 1 ps/1 ps
`define PRIME 1
`define SEC 0
//--------------------------------------------------------------------------
// Module Name : cycloneii_ram_block
// Description : Main RAM module
//--------------------------------------------------------------------------
module cycloneii_ram_block
(
portadatain,
portaaddr,
portawe,
portbdatain,
portbaddr,
portbrewe,
clk0, clk1,
ena0, ena1,
clr0, clr1,
portabyteenamasks,
portbbyteenamasks,
portaaddrstall,
portbaddrstall,
devclrn,
devpor,
portadataout,
portbdataout
);
// -------- GLOBAL PARAMETERS ---------
parameter operation_mode = "single_port";
parameter mixed_port_feed_through_mode = "dont_care";
parameter ram_block_type = "auto";
parameter logical_ram_name = "ram_name";
parameter init_file = "init_file.hex";
parameter init_file_layout = "none";
parameter data_interleave_width_in_bits = 1;
parameter data_interleave_offset_in_bits = 1;
parameter port_a_logical_ram_depth = 0;
parameter port_a_logical_ram_width = 0;
parameter port_a_first_address = 0;
parameter port_a_last_address = 0;
parameter port_a_first_bit_number = 0;
parameter port_a_data_in_clear = "none";
parameter port_a_address_clear = "none";
parameter port_a_write_enable_clear = "none";
parameter port_a_data_out_clear = "none";
parameter port_a_byte_enable_clear = "none";
parameter port_a_data_in_clock = "clock0";
parameter port_a_address_clock = "clock0";
parameter port_a_write_enable_clock = "clock0";
parameter port_a_byte_enable_clock = "clock0";
parameter port_a_data_out_clock = "none";
parameter port_a_data_width = 1;
parameter port_a_address_width = 1;
parameter port_a_byte_enable_mask_width = 1;
parameter port_b_logical_ram_depth = 0;
parameter port_b_logical_ram_width = 0;
parameter port_b_first_address = 0;
parameter port_b_last_address = 0;
parameter port_b_first_bit_number = 0;
parameter port_b_data_in_clear = "none";
parameter port_b_address_clear = "none";
parameter port_b_read_enable_write_enable_clear = "none";
parameter port_b_byte_enable_clear = "none";
parameter port_b_data_out_clear = "none";
parameter port_b_data_in_clock = "clock0";
parameter port_b_address_clock = "clock0";
parameter port_b_read_enable_write_enable_clock = "clock0";
parameter port_b_byte_enable_clock = "none";
parameter port_b_data_out_clock = "none";
parameter port_b_data_width = 1;
parameter port_b_address_width = 1;
parameter port_b_byte_enable_mask_width = 1;
parameter power_up_uninitialized = "false";
parameter lpm_type = "cycloneii_ram_block";
parameter lpm_hint = "true";
parameter connectivity_checking = "off";
parameter mem_init0 = 2048'b0;
parameter mem_init1 = 2560'b0;
parameter port_a_byte_size = 0;
parameter port_a_disable_ce_on_input_registers = "off";
parameter port_a_disable_ce_on_output_registers = "off";
parameter port_b_byte_size = 0;
parameter port_b_disable_ce_on_input_registers = "off";
parameter port_b_disable_ce_on_output_registers = "off";
parameter safe_write = "err_on_2clk";
// -------- LOCAL PARAMETERS ---------
parameter primary_port_is_a = (port_b_data_width <= port_a_data_width) ? 1'b1 : 1'b0;
parameter primary_port_is_b = ~primary_port_is_a;
parameter mode_is_rom_or_sp = ((operation_mode == "rom") || (operation_mode == "single_port")) ? 1'b1 : 1'b0;
parameter data_width = (primary_port_is_a) ? port_a_data_width : port_b_data_width;
parameter data_unit_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_data_width : port_b_data_width;
parameter address_width = (mode_is_rom_or_sp | primary_port_is_b) ? port_a_address_width : port_b_address_width;
parameter address_unit_width = (mode_is_rom_or_sp | primary_port_is_a) ? port_a_address_width : port_b_address_width;
parameter wired_mode = ((port_a_address_width == 1) && (port_a_address_width == port_b_address_width)
&& (port_a_data_width != port_b_data_width));
parameter num_rows = 1 << address_unit_width;
parameter num_cols = (mode_is_rom_or_sp) ? 1 : ( wired_mode ? 2 :
( (primary_port_is_a) ?
1 << (port_b_address_width - port_a_address_width) :
1 << (port_a_address_width - port_b_address_width) ) ) ;
parameter mask_width_prime = (primary_port_is_a) ?
port_a_byte_enable_mask_width : port_b_byte_enable_mask_width;
parameter mask_width_sec = (primary_port_is_a) ?
port_b_byte_enable_mask_width : port_a_byte_enable_mask_width;
parameter byte_size_a = port_a_data_width/port_a_byte_enable_mask_width;
parameter byte_size_b = port_b_data_width/port_b_byte_enable_mask_width;
parameter mode_is_dp = (operation_mode == "dual_port") ? 1'b1 : 1'b0;
// -------- PORT DECLARATIONS ---------
input portawe;
input [port_a_data_width - 1:0] portadatain;
input [port_a_address_width - 1:0] portaaddr;
input [port_a_byte_enable_mask_width - 1:0] portabyteenamasks;
input portbrewe;
input [port_b_data_width - 1:0] portbdatain;
input [port_b_address_width - 1:0] portbaddr;
input [port_b_byte_enable_mask_width - 1:0] portbbyteenamasks;
input clr0,clr1;
input clk0,clk1;
input ena0,ena1;
input devclrn,devpor;
input portaaddrstall;
input portbaddrstall;
output [port_a_data_width - 1:0] portadataout;
output [port_b_data_width - 1:0] portbdataout;
// -------- INTERNAL signals ---------
// clock / clock enable
wire clk_a_in,clk_a_byteena,clk_a_out,clkena_a_out;
wire clk_b_in,clk_b_byteena,clk_b_out,clkena_b_out;
wire write_cycle_a,write_cycle_b;
// asynch clear
wire datain_a_clr,dataout_a_clr,datain_b_clr,dataout_b_clr;
wire addr_a_clr,addr_b_clr;
wire byteena_a_clr,byteena_b_clr;
wire we_a_clr,rewe_b_clr;
wire datain_a_clr_in,datain_b_clr_in;
wire addr_a_clr_in,addr_b_clr_in;
wire byteena_a_clr_in,byteena_b_clr_in;
wire we_a_clr_in,rewe_b_clr_in;
reg mem_invalidate;
wire [`PRIME:`SEC] clear_asserted_during_write;
reg clear_asserted_during_write_a,clear_asserted_during_write_b;
// port A registers
wire we_a_reg;
wire [port_a_address_width - 1:0] addr_a_reg;
wire [port_a_data_width - 1:0] datain_a_reg, dataout_a_reg;
reg [port_a_data_width - 1:0] dataout_a;
wire [port_a_byte_enable_mask_width - 1:0] byteena_a_reg;
reg out_a_is_reg;
// port B registers
wire rewe_b_reg;
wire [port_b_address_width - 1:0] addr_b_reg;
wire [port_b_data_width - 1:0] datain_b_reg, dataout_b_reg;
reg [port_b_data_width - 1:0] dataout_b;
wire [port_b_byte_enable_mask_width - 1:0] byteena_b_reg;
reg out_b_is_reg;
// placeholders for read/written data
reg [data_width - 1:0] read_data_latch;
reg [data_width - 1:0] mem_data;
reg [data_unit_width - 1:0] read_unit_data_latch;
reg [data_width - 1:0] mem_unit_data;
// pulses for A/B ports
wire write_pulse_a,write_pulse_b;
wire read_pulse_a,read_pulse_b;
wire read_pulse_a_feedthru,read_pulse_b_feedthru;
wire [address_unit_width - 1:0] addr_prime_reg; // registered address
wire [address_width - 1:0] addr_sec_reg;
wire [data_width - 1:0] datain_prime_reg; // registered data
wire [data_unit_width - 1:0] datain_sec_reg;
// pulses for primary/secondary ports
wire write_pulse_prime,write_pulse_sec;
wire read_pulse_prime,read_pulse_sec;
wire read_pulse_prime_feedthru,read_pulse_sec_feedthru;
reg [`PRIME:`SEC] dual_write; // simultaneous write to same location
// (row,column) coordinates
reg [address_unit_width - 1:0] row_sec;
reg [address_width + data_unit_width - address_unit_width - 1:0] col_sec;
// memory core
reg [data_width - 1:0] mem [num_rows - 1:0];
// byte enable
wire [data_width - 1:0] mask_vector_prime, mask_vector_prime_int;
wire [data_unit_width - 1:0] mask_vector_sec, mask_vector_sec_int;
reg [data_unit_width - 1:0] mask_vector_common_int;
reg [port_a_data_width - 1:0] mask_vector_a, mask_vector_a_int;
reg [port_b_data_width - 1:0] mask_vector_b, mask_vector_b_int;
// memory initialization
integer i,j,k;
integer addr_range_init;
reg [data_width - 1:0] init_mem_word;
reg [(port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1:0] mem_init;
// port active for read/write
wire active_a,active_a_in,active_b,active_b_in;
wire active_write_a,active_write_b,active_write_clear_a,active_write_clear_b;
reg mode_is_rom,mode_is_sp,mode_is_bdp; // ram mode
reg ram_type; // ram type eg. MRAM
initial
begin
ram_type = (ram_block_type == "M-RAM" || ram_block_type == "m-ram" || ram_block_type == "MegaRAM" ||
(ram_block_type == "auto" && mixed_port_feed_through_mode == "dont_care" && port_b_read_enable_write_enable_clock == "clock0"));
mode_is_rom = (operation_mode == "rom");
mode_is_sp = (operation_mode == "single_port");
mode_is_bdp = (operation_mode == "bidir_dual_port");
out_a_is_reg = (port_a_data_out_clock == "none") ? 1'b0 : 1'b1;
out_b_is_reg = (port_b_data_out_clock == "none") ? 1'b0 : 1'b1;
// powerup output latches to 0
dataout_a = 'b0;
if (mode_is_dp || mode_is_bdp) dataout_b = 'b0;
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'b0;
if ((init_file_layout == "port_a") || (init_file_layout == "port_b"))
begin
mem_init = {mem_init1,mem_init0};
addr_range_init = (primary_port_is_a) ?
port_a_last_address - port_a_first_address + 1 :
port_b_last_address - port_b_first_address + 1 ;
for (j = 0; j < addr_range_init; j = j + 1)
begin
for (k = 0; k < data_width; k = k + 1)
init_mem_word[k] = mem_init[j*data_width + k];
mem[j] = init_mem_word;
end
end
dual_write = 'b0;
end
assign clk_a_in = clk0;
assign clk_a_byteena = (port_a_byte_enable_clock == "none") ? 1'b0 : clk_a_in;
assign clk_a_out = (port_a_data_out_clock == "none") ? 1'b0 : (
(port_a_data_out_clock == "clock0") ? clk0 : clk1);
assign clk_b_in = (port_b_read_enable_write_enable_clock == "clock0") ? clk0 : clk1;
assign clk_b_byteena = (port_b_byte_enable_clock == "none") ? 1'b0 : (
(port_b_byte_enable_clock == "clock0") ? clk0 : clk1);
assign clk_b_out = (port_b_data_out_clock == "none") ? 1'b0 : (
(port_b_data_out_clock == "clock0") ? clk0 : clk1);
assign addr_a_clr_in = (port_a_address_clear == "none") ? 1'b0 : clr0;
assign addr_b_clr_in = (port_b_address_clear == "none") ? 1'b0 : (
(port_b_address_clear == "clear0") ? clr0 : clr1);
assign datain_a_clr_in = (port_a_data_in_clear == "none") ? 1'b0 : clr0;
assign dataout_a_clr = (port_a_data_out_clear == "none") ? 1'b0 : (
(port_a_data_out_clear == "clear0") ? clr0 : clr1);
assign datain_b_clr_in = (port_b_data_in_clear == "none") ? 1'b0 : (
(port_b_data_in_clear == "clear0") ? clr0 : clr1);
assign dataout_b_clr = (port_b_data_out_clear == "none") ? 1'b0 : (
(port_b_data_out_clear == "clear0") ? clr0 : clr1);
assign byteena_a_clr_in = (port_a_byte_enable_clear == "none") ? 1'b0 : clr0;
assign byteena_b_clr_in = (port_b_byte_enable_clear == "none") ? 1'b0 : (
(port_b_byte_enable_clear == "clear0") ? clr0 : clr1);
assign we_a_clr_in = (port_a_write_enable_clear == "none") ? 1'b0 : clr0;
assign rewe_b_clr_in = (port_b_read_enable_write_enable_clear == "none") ? 1'b0 : (
(port_b_read_enable_write_enable_clear == "clear0") ? clr0 : clr1);
assign active_a_in = ena0 || (port_a_disable_ce_on_input_registers == "on");
assign active_b_in = ((port_b_read_enable_write_enable_clock == "clock0") ? ena0 : ena1) ||
(port_b_disable_ce_on_input_registers == "on");
// Store clock enable value for SEAB/MEAB
// port A active
cycloneii_ram_register active_port_a (
.d(active_a_in),
.clk(clk_a_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_a),.aclrout()
);
defparam active_port_a.width = 1;
assign active_write_a = active_a && (byteena_a_reg !== 'b0);
// port B active
cycloneii_ram_register active_port_b (
.d(active_b_in),
.clk(clk_b_in),
.aclr(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.stall(1'b0),
.ena(1'b1),
.q(active_b),.aclrout()
);
defparam active_port_b.width = 1;
assign active_write_b = active_b && (byteena_b_reg !== 'b0);
// ------- A input registers -------
// write enable
cycloneii_ram_register we_a_register (
.d(mode_is_rom ? 1'b0 : portawe),
.clk(clk_a_in),
.aclr(we_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(we_a_reg),
.aclrout(we_a_clr)
);
defparam we_a_register.width = 1;
// address
cycloneii_ram_register addr_a_register (
.d(portaaddr),
.clk(clk_a_in),
.aclr(addr_a_clr_in),
.devclrn(devclrn),.devpor(devpor),
.stall(portaaddrstall),
.ena(active_a_in),
.q(addr_a_reg),
.aclrout(addr_a_clr)
);
defparam addr_a_register.width = port_a_address_width;
// data
cycloneii_ram_register datain_a_register (
.d(portadatain),
.clk(clk_a_in),
.aclr(datain_a_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_a_in),
.q(datain_a_reg),
.aclrout(datain_a_clr)
);
defparam datain_a_register.width = port_a_data_width;
// byte enable
cycloneii_ram_register byteena_a_register (
.d(portabyteenamasks),
.clk(clk_a_byteena),
.aclr(byteena_a_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_a_in),
.q(byteena_a_reg),
.aclrout(byteena_a_clr)
);
defparam byteena_a_register.width = port_a_byte_enable_mask_width;
defparam byteena_a_register.preset = 1'b1;
// ------- B input registers -------
// read/write enable
cycloneii_ram_register rewe_b_register (
.d(portbrewe),
.clk(clk_b_in),
.aclr(rewe_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(rewe_b_reg),
.aclrout(rewe_b_clr)
);
defparam rewe_b_register.width = 1;
defparam rewe_b_register.preset = mode_is_dp;
// address
cycloneii_ram_register addr_b_register (
.d(portbaddr),
.clk(clk_b_in),
.aclr(addr_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(portbaddrstall),
.ena(active_b_in),
.q(addr_b_reg),
.aclrout(addr_b_clr)
);
defparam addr_b_register.width = port_b_address_width;
// data
cycloneii_ram_register datain_b_register (
.d(portbdatain),
.clk(clk_b_in),
.aclr(datain_b_clr_in),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(active_b_in),
.q(datain_b_reg),
.aclrout(datain_b_clr)
);
defparam datain_b_register.width = port_b_data_width;
// byte enable
cycloneii_ram_register byteena_b_register (
.d(portbbyteenamasks),
.clk(clk_b_byteena),
.aclr(byteena_b_clr_in),
.stall(1'b0),
.devclrn(devclrn),
.devpor(devpor),
.ena(active_b_in),
.q(byteena_b_reg),
.aclrout(byteena_b_clr)
);
defparam byteena_b_register.width = port_b_byte_enable_mask_width;
defparam byteena_b_register.preset = 1'b1;
assign datain_prime_reg = (primary_port_is_a) ? datain_a_reg : datain_b_reg;
assign addr_prime_reg = (primary_port_is_a) ? addr_a_reg : addr_b_reg;
assign datain_sec_reg = (primary_port_is_a) ? datain_b_reg : datain_a_reg;
assign addr_sec_reg = (primary_port_is_a) ? addr_b_reg : addr_a_reg;
assign mask_vector_prime = (primary_port_is_a) ? mask_vector_a : mask_vector_b;
assign mask_vector_prime_int = (primary_port_is_a) ? mask_vector_a_int : mask_vector_b_int;
assign mask_vector_sec = (primary_port_is_a) ? mask_vector_b : mask_vector_a;
assign mask_vector_sec_int = (primary_port_is_a) ? mask_vector_b_int : mask_vector_a_int;
// Write pulse generation
cycloneii_ram_pulse_generator wpgen_a (
.clk(ram_type ? clk_a_in : ~clk_a_in),
.ena(active_write_a & we_a_reg),
.pulse(write_pulse_a),
.cycle(write_cycle_a)
);
cycloneii_ram_pulse_generator wpgen_b (
.clk(ram_type ? clk_b_in : ~clk_b_in),
.ena(active_write_b & mode_is_bdp & rewe_b_reg),
.pulse(write_pulse_b),
.cycle(write_cycle_b)
);
// Read pulse generation
cycloneii_ram_pulse_generator rpgen_a (
.clk(clk_a_in),
.ena(active_a & ~we_a_reg),
.pulse(read_pulse_a),.cycle()
);
cycloneii_ram_pulse_generator rpgen_b (
.clk(clk_b_in),
.ena(active_b & (mode_is_dp ? rewe_b_reg : ~rewe_b_reg)),
.pulse(read_pulse_b),.cycle()
);
assign write_pulse_prime = (primary_port_is_a) ? write_pulse_a : write_pulse_b;
assign read_pulse_prime = (primary_port_is_a) ? read_pulse_a : read_pulse_b;
assign read_pulse_prime_feedthru = (primary_port_is_a) ? read_pulse_a_feedthru : read_pulse_b_feedthru;
assign write_pulse_sec = (primary_port_is_a) ? write_pulse_b : write_pulse_a;
assign read_pulse_sec = (primary_port_is_a) ? read_pulse_b : read_pulse_a;
assign read_pulse_sec_feedthru = (primary_port_is_a) ? read_pulse_b_feedthru : read_pulse_a_feedthru;
// Create internal masks for byte enable processing
always @(byteena_a_reg)
begin
for (i = 0; i < port_a_data_width; i = i + 1)
begin
mask_vector_a[i] = (byteena_a_reg[i/byte_size_a] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_a_int[i] = (byteena_a_reg[i/byte_size_a] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(byteena_b_reg)
begin
for (i = 0; i < port_b_data_width; i = i + 1)
begin
mask_vector_b[i] = (byteena_b_reg[i/byte_size_b] === 1'b1) ? 1'b0 : 1'bx;
mask_vector_b_int[i] = (byteena_b_reg[i/byte_size_b] === 1'b0) ? 1'b0 : 1'bx;
end
end
always @(posedge write_pulse_prime or posedge write_pulse_sec or
posedge read_pulse_prime or posedge read_pulse_sec)
begin
// Write stage 1 : write X to memory
if (write_pulse_prime)
begin
mem_data = mem[addr_prime_reg] ^ mask_vector_prime_int;
mem[addr_prime_reg] = mem_data;
end
if (write_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = mem_unit_data[j] ^ mask_vector_sec_int[j - col_sec];
mem[row_sec] = mem_unit_data;
end
if ((addr_prime_reg == row_sec) && write_pulse_prime && write_pulse_sec) dual_write = 2'b11;
// Read stage 1 : read data from memory
if (read_pulse_prime) read_data_latch = mem[addr_prime_reg];
if (read_pulse_sec)
begin
row_sec = addr_sec_reg / num_cols; col_sec = (addr_sec_reg % num_cols) * data_unit_width;
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
read_unit_data_latch[j - col_sec] = mem_unit_data[j];
end
end
// Simultaneous write to same/overlapping location by both ports
always @(dual_write)
begin
if (dual_write == 2'b11)
begin
for (i = 0; i < data_unit_width; i = i + 1)
mask_vector_common_int[i] = mask_vector_prime_int[col_sec + i] &
mask_vector_sec_int[i];
end
else if (dual_write == 2'b01) mem_unit_data = mem[row_sec];
else if (dual_write == 'b0)
begin
mem_data = mem[addr_prime_reg];
for (i = 0; i < data_unit_width; i = i + 1)
mem_data[col_sec + i] = mem_data[col_sec + i] ^ mask_vector_common_int[i];
mem[addr_prime_reg] = mem_data;
end
end
// Write stage 2 : Write actual data to memory
always @(negedge write_pulse_prime)
begin
if (clear_asserted_during_write[`PRIME] !== 1'b1)
begin
for (i = 0; i < data_width; i = i + 1)
if (mask_vector_prime[i] == 1'b0)
mem_data[i] = datain_prime_reg[i];
mem[addr_prime_reg] = mem_data;
end
dual_write[`PRIME] = 1'b0;
end
always @(negedge write_pulse_sec)
begin
if (clear_asserted_during_write[`SEC] !== 1'b1)
begin
for (i = 0; i < data_unit_width; i = i + 1)
if (mask_vector_sec[i] == 1'b0)
mem_unit_data[col_sec + i] = datain_sec_reg[i];
mem[row_sec] = mem_unit_data;
end
dual_write[`SEC] = 1'b0;
end
// Read stage 2 : Send data to output
always @(negedge read_pulse_prime)
begin
if (primary_port_is_a)
dataout_a = read_data_latch;
else
dataout_b = read_data_latch;
end
always @(negedge read_pulse_sec)
begin
if (primary_port_is_b)
dataout_a = read_unit_data_latch;
else
dataout_b = read_unit_data_latch;
end
// Same port feed through
cycloneii_ram_pulse_generator ftpgen_a (
.clk(clk_a_in),
.ena(active_a & ~mode_is_dp & we_a_reg),
.pulse(read_pulse_a_feedthru),.cycle()
);
cycloneii_ram_pulse_generator ftpgen_b (
.clk(clk_b_in),
.ena(active_b & mode_is_bdp & rewe_b_reg),
.pulse(read_pulse_b_feedthru),.cycle()
);
always @(negedge read_pulse_prime_feedthru)
begin
if (primary_port_is_a)
dataout_a = datain_prime_reg ^ mask_vector_prime;
else
dataout_b = datain_prime_reg ^ mask_vector_prime;
end
always @(negedge read_pulse_sec_feedthru)
begin
if (primary_port_is_b)
dataout_a = datain_sec_reg ^ mask_vector_sec;
else
dataout_b = datain_sec_reg ^ mask_vector_sec;
end
// -------- Async clear logic ---------
always @(posedge addr_a_clr or posedge datain_a_clr or posedge we_a_clr)
clear_asserted_during_write_a = write_pulse_a;
assign active_write_clear_a = active_write_a & write_cycle_a;
always @(posedge addr_a_clr)
begin
if (active_write_clear_a & we_a_reg)
mem_invalidate = 1'b1;
else if (active_a & ~we_a_reg)
begin
if (primary_port_is_a)
read_data_latch = 'bx;
else
read_unit_data_latch = 'bx;
end
end
always @(posedge datain_a_clr or posedge we_a_clr)
begin
if (active_write_clear_a & we_a_reg)
begin
if (primary_port_is_a)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 1'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_a)
read_data_latch = 'bx;
else
read_unit_data_latch = 'bx;
end
end
assign active_write_clear_b = active_write_b & write_cycle_b;
always @(posedge addr_b_clr or posedge datain_b_clr or posedge rewe_b_clr)
clear_asserted_during_write_b = write_pulse_b;
always @(posedge addr_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
mem_invalidate = 1'b1;
else if (active_b & (mode_is_dp & rewe_b_reg || mode_is_bdp & ~rewe_b_reg))
begin
if (primary_port_is_b)
read_data_latch = 'bx;
else
read_unit_data_latch = 'bx;
end
end
always @(posedge datain_b_clr or posedge rewe_b_clr)
begin
if (mode_is_bdp & active_write_clear_b & rewe_b_reg)
begin
if (primary_port_is_b)
mem[addr_prime_reg] = 'bx;
else
begin
mem_unit_data = mem[row_sec];
for (j = col_sec; j <= col_sec + data_unit_width - 1; j = j + 1)
mem_unit_data[j] = 'bx;
mem[row_sec] = mem_unit_data;
end
if (primary_port_is_b)
read_data_latch = 'bx;
else
read_unit_data_latch = 'bx;
end
end
assign clear_asserted_during_write[primary_port_is_a] = clear_asserted_during_write_a;
assign clear_asserted_during_write[primary_port_is_b] = clear_asserted_during_write_b;
always @(posedge mem_invalidate)
begin
for (i = 0; i < num_rows; i = i + 1) mem[i] = 'bx;
mem_invalidate = 1'b0;
end
// ------- Output registers --------
assign clkena_a_out = (port_a_data_out_clock == "clock0") ?
ena0 || (port_a_disable_ce_on_output_registers == "on") :
ena1 || (port_a_disable_ce_on_output_registers == "on") ;
cycloneii_ram_register dataout_a_register (
.d(dataout_a),
.clk(clk_a_out),
.aclr(dataout_a_clr),
.devclrn(devclrn),
.devpor(devpor),
.stall(1'b0),
.ena(clkena_a_out),
.q(dataout_a_reg),.aclrout()
);
defparam dataout_a_register.width = port_a_data_width;
assign portadataout = (out_a_is_reg) ? dataout_a_reg : dataout_a;
assign clkena_b_out = (port_b_data_out_clock == "clock0") ?
ena0 || (port_b_disable_ce_on_output_registers == "on") :
ena1 || (port_b_disable_ce_on_output_registers == "on") ;
cycloneii_ram_register dataout_b_register (
.d( dataout_b ),
.clk(clk_b_out),
.aclr(dataout_b_clr),
.devclrn(devclrn),.devpor(devpor),
.stall(1'b0),
.ena(clkena_b_out),
.q(dataout_b_reg),.aclrout()
);
defparam dataout_b_register.width = port_b_data_width;
assign portbdataout = (out_b_is_reg) ? dataout_b_reg : dataout_b;
endmodule // cycloneii_ram_block
//--------------------------------------------------------------------
//
// Module Name : cycloneii_jtag
//
// Description : CycloneII JTAG Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_jtag (tms, tck, tdi, ntrst, tdoutap, tdouser, tdo, tmsutap, tckutap, tdiutap, shiftuser, clkdruser, updateuser, runidleuser, usr1user);
input tms, tck, tdi, ntrst, tdoutap, tdouser;
output tdo, tmsutap, tckutap, tdiutap, shiftuser, clkdruser;
output updateuser, runidleuser, usr1user;
parameter lpm_type = "cycloneii_jtag";
initial
begin
end
always @(tms or tck or tdi or ntrst or tdoutap or tdouser)
begin
end
endmodule
//--------------------------------------------------------------------
//
// Module Name : cycloneii_crcblock
//
// Description : CycloneII CRCBLOCK Verilog Simulation model
//
//--------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_crcblock
(
clk,
shiftnld,
ldsrc,
crcerror,
regout
);
input clk;
input shiftnld;
input ldsrc;
output crcerror;
output regout;
parameter oscillator_divider = 1;
parameter lpm_type = "cycloneii_crcblock";
endmodule
//---------------------------------------------------------------------
//
// Module Name : cycloneii_asmiblock
//
// Description : CycloneII ASMIBLOCK Verilog Simulation model
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_asmiblock
(
dclkin,
scein,
sdoin,
data0out,
oe
);
input dclkin;
input scein;
input sdoin;
input oe;
output data0out;
parameter lpm_type = "cycloneii_asmiblock";
endmodule // cycloneii_asmiblock
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_m_cntr
//
// Description : Timing simulation model for the M counter. This is the
// loop feedback counter for the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_m_cntr ( clk,
reset,
cout,
initial_value,
modulus,
time_delay);
// INPUT PORTS
input clk;
input reset;
input [31:0] initial_value;
input [31:0] modulus;
input [31:0] time_delay;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
cout_tmp <= tmp_cout;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
cout_tmp <= #(time_delay) tmp_cout;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
cout_tmp <= #(time_delay) tmp_cout;
end
end
end
clk_last_value = clk;
// cout_tmp <= #(time_delay) tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneii_m_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_n_cntr
//
// Description : Timing simulation model for the N counter. This is the
// input clock divide counter for the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_n_cntr ( clk,
reset,
cout,
modulus);
// INPUT PORTS
input clk;
input reset;
input [31:0] modulus;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
integer count;
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 1;
clk_last_value = 0;
end
always @(reset or clk)
begin
if (reset)
begin
count = 1;
tmp_cout = 0;
first_rising_edge = 1;
end
else begin
if (clk == 1 && clk_last_value !== clk && first_rising_edge)
begin
first_rising_edge = 0;
tmp_cout = clk;
end
else if (first_rising_edge == 0)
begin
if (count < modulus)
count = count + 1;
else
begin
count = 1;
tmp_cout = ~tmp_cout;
end
end
end
clk_last_value = clk;
end
assign cout = tmp_cout;
endmodule // cycloneii_n_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_scale_cntr
//
// Description : Timing simulation model for the output scale-down counters.
// This is a common model for the C0, C1, C2, C3, C4 and
// C5 output counters of the CycloneII PLL.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module cycloneii_scale_cntr ( clk,
reset,
cout,
high,
low,
initial_value,
mode,
ph_tap);
// INPUT PORTS
input clk;
input reset;
input [31:0] high;
input [31:0] low;
input [31:0] initial_value;
input [8*6:1] mode;
input [31:0] ph_tap;
// OUTPUT PORTS
output cout;
// INTERNAL VARIABLES AND NETS
reg tmp_cout;
reg first_rising_edge;
reg clk_last_value;
reg init;
integer count;
integer output_shift_count;
reg cout_tmp;
initial
begin
count = 1;
first_rising_edge = 0;
tmp_cout = 0;
output_shift_count = 1;
end
always @(clk or reset)
begin
if (init !== 1'b1)
begin
clk_last_value = 0;
init = 1'b1;
end
if (reset)
begin
count = 1;
output_shift_count = 1;
tmp_cout = 0;
first_rising_edge = 0;
end
else if (clk_last_value !== clk)
begin
if (mode == " off")
tmp_cout = 0;
else if (mode == "bypass")
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else if (first_rising_edge == 0)
begin
if (clk == 1)
begin
if (output_shift_count == initial_value)
begin
tmp_cout = clk;
first_rising_edge = 1;
end
else
output_shift_count = output_shift_count + 1;
end
end
else if (output_shift_count < initial_value)
begin
if (clk == 1)
output_shift_count = output_shift_count + 1;
end
else
begin
count = count + 1;
if (mode == " even" && (count == (high*2) + 1))
tmp_cout = 0;
else if (mode == " odd" && (count == (high*2)))
tmp_cout = 0;
else if (count == (high + low)*2 + 1)
begin
tmp_cout = 1;
count = 1; // reset count
end
end
end
clk_last_value = clk;
cout_tmp <= tmp_cout;
end
and (cout, cout_tmp, 1'b1);
endmodule // cycloneii_scale_cntr
///////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_pll_reg
//
// Description : Simulation model for a simple DFF.
// This is required for the generation of the bit slip-signals.
// No timing, powers upto 0.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
module cycloneii_pll_reg ( q,
clk,
ena,
d,
clrn,
prn);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q;
reg clk_last_value;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
initial q = 0;
always @ (clk or negedge clrn or negedge prn )
begin
if (prn == 1'b0)
q <= 1;
else if (clrn == 1'b0)
q <= 0;
else if ((clk === 1'b1) && (clk_last_value === 1'b0) && (ena === 1'b1))
q <= d;
clk_last_value = clk;
end
endmodule // cycloneii_pll_reg
//////////////////////////////////////////////////////////////////////////////
//
// Module Name : cycloneii_pll
//
// Description : Timing simulation model for the CycloneII PLL.
// In the functional mode, it is also the model for the altpll
// megafunction.
//
// Limitations : Does not support Spread Spectrum and Bandwidth.
//
// Outputs : Up to 6 output clocks, each defined by its own set of
// parameters. Locked output (active high) indicates when the
// PLL locks. clkbad, clkloss and activeclock are used for
// clock switchover to indicate which input clock has gone
// bad, when the clock switchover initiates and which input
// clock is being used as the reference, respectively.
// scandataout is the data output of the serial scan chain.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
`define WORD_LENGTH 18
module cycloneii_pll (inclk,
ena,
clkswitch,
areset,
pfdena,
testclearlock,
clk,
locked,
testupout,
testdownout,
sbdin,
sbdout
);
parameter operation_mode = "normal";
parameter pll_type = "auto";
parameter compensate_clock = "clk0";
parameter feedback_source = "clk0";
parameter qualify_conf_done = "off";
parameter test_input_comp_delay_chain_bits = 0;
parameter test_feedback_comp_delay_chain_bits = 0;
parameter inclk0_input_frequency = 10000;
parameter inclk1_input_frequency = 10000;
parameter gate_lock_signal = "no";
parameter gate_lock_counter = 1;
parameter self_reset_on_gated_loss_lock = "off";
parameter valid_lock_multiplier = 1;
parameter invalid_lock_multiplier = 5;
parameter switch_over_type = "manual";
parameter switch_over_on_lossclk = "off";
parameter switch_over_on_gated_lock = "off";
parameter switch_over_counter = 1;
parameter enable_switch_over_counter = "on";
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter down_spread = "0.0";
parameter spread_frequency = 0;
parameter common_rx_tx = "off";
parameter rx_outclock_resource = "auto";
parameter use_dc_coupling = "false";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 1;
parameter clk0_divide_by = 1;
parameter clk0_phase_shift = "0";
parameter clk0_duty_cycle = 50;
parameter clk1_output_frequency = 0;
parameter clk1_multiply_by = 1;
parameter clk1_divide_by = 1;
parameter clk1_phase_shift = "0";
parameter clk1_duty_cycle = 50;
parameter clk2_output_frequency = 0;
parameter clk2_multiply_by = 1;
parameter clk2_divide_by = 1;
parameter clk2_phase_shift = "0";
parameter clk2_duty_cycle = 50;
parameter clk3_output_frequency = 0;
parameter clk3_multiply_by = 1;
parameter clk3_divide_by = 1;
parameter clk3_phase_shift = "0";
parameter clk3_duty_cycle = 50;
parameter clk4_output_frequency = 0;
parameter clk4_multiply_by = 1;
parameter clk4_divide_by = 1;
parameter clk4_phase_shift = "0";
parameter clk4_duty_cycle = 50;
parameter clk5_output_frequency = 0;
parameter clk5_multiply_by = 1;
parameter clk5_divide_by = 1;
parameter clk5_phase_shift = "0";
parameter clk5_duty_cycle = 50;
parameter pfd_min = 0;
parameter pfd_max = 0;
parameter vco_min = 0;
parameter vco_max = 0;
parameter vco_center = 0;
// ADVANCED USE PARAMETERS
parameter m_initial = 1;
parameter m = 1;
parameter n = 1;
parameter m2 = 1;
parameter n2 = 1;
parameter ss = 0;
parameter c0_high = 1;
parameter c0_low = 1;
parameter c0_initial = 1;
parameter c0_mode = "bypass";
parameter c0_ph = 0;
parameter c1_high = 1;
parameter c1_low = 1;
parameter c1_initial = 1;
parameter c1_mode = "bypass";
parameter c1_ph = 0;
parameter c2_high = 1;
parameter c2_low = 1;
parameter c2_initial = 1;
parameter c2_mode = "bypass";
parameter c2_ph = 0;
parameter c3_high = 1;
parameter c3_low = 1;
parameter c3_initial = 1;
parameter c3_mode = "bypass";
parameter c3_ph = 0;
parameter c4_high = 1;
parameter c4_low = 1;
parameter c4_initial = 1;
parameter c4_mode = "bypass";
parameter c4_ph = 0;
parameter c5_high = 1;
parameter c5_low = 1;
parameter c5_initial = 1;
parameter c5_mode = "bypass";
parameter c5_ph = 0;
parameter m_ph = 0;
parameter clk0_counter = "c0";
parameter clk1_counter = "c1";
parameter clk2_counter = "c2";
parameter clk3_counter = "c3";
parameter clk4_counter = "c4";
parameter clk5_counter = "c5";
parameter c1_use_casc_in = "off";
parameter c2_use_casc_in = "off";
parameter c3_use_casc_in = "off";
parameter c4_use_casc_in = "off";
parameter c5_use_casc_in = "off";
parameter m_test_source = 5;
parameter c0_test_source = 5;
parameter c1_test_source = 5;
parameter c2_test_source = 5;
parameter c3_test_source = 5;
parameter c4_test_source = 5;
parameter c5_test_source = 5;
// LVDS mode parameters
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
parameter vco_post_scale = 1;
parameter charge_pump_current = 0;
parameter loop_filter_r = "1.0";
parameter loop_filter_c = 1;
parameter pll_compensation_delay = 0;
parameter simulation_type = "functional";
parameter lpm_type = "cycloneii_pll";
//parameter for cycloneii lvds
parameter clk0_phase_shift_num = 0;
parameter clk1_phase_shift_num = 0;
parameter clk2_phase_shift_num = 0;
parameter clk0_use_even_counter_mode = "off";
parameter clk1_use_even_counter_mode = "off";
parameter clk2_use_even_counter_mode = "off";
parameter clk3_use_even_counter_mode = "off";
parameter clk4_use_even_counter_mode = "off";
parameter clk5_use_even_counter_mode = "off";
parameter clk0_use_even_counter_value = "off";
parameter clk1_use_even_counter_value = "off";
parameter clk2_use_even_counter_value = "off";
parameter clk3_use_even_counter_value = "off";
parameter clk4_use_even_counter_value = "off";
parameter clk5_use_even_counter_value = "off";
// INPUT PORTS
input [1:0] inclk;
input ena;
input clkswitch;
input areset;
input pfdena;
input testclearlock;
input sbdin;
// OUTPUT PORTS
output [2:0] clk;
output locked;
output sbdout;
// lvds specific output ports
// test ports
output testupout;
output testdownout;
// BUFFER INPUTS
wire inclk0_ipd;
wire inclk1_ipd;
wire ena_ipd;
wire fbin_ipd;
wire clkswitch_ipd;
wire areset_ipd;
wire pfdena_ipd;
wire scanclk_ipd;
wire scanread_ipd;
wire scanwrite_ipd;
wire scandata_ipd;
wire sbdin_ipd;
buf (inclk0_ipd, inclk[0]);
buf (inclk1_ipd, inclk[1]);
buf (ena_ipd, ena);
buf (fbin_ipd, 1'b0);
buf (clkswitch_ipd, clkswitch);
buf (areset_ipd, areset);
buf (pfdena_ipd, pfdena);
buf (scanclk_ipd, 1'b0);
buf (scanread_ipd, 1'b0);
buf (scanwrite_ipd, 1'b0);
buf (scandata_ipd, 1'b0);
buf (sbdin_ipd, sbdin);
// TIMING CHECKS
specify
(sbdin => sbdout) = (0, 0);
endspecify
// INTERNAL VARIABLES AND NETS
integer scan_chain_length;
integer i;
integer j;
integer k;
integer x;
integer y;
integer l_index;
integer gate_count;
integer egpp_offset;
integer sched_time;
integer delay_chain;
integer low;
integer high;
integer initial_delay;
integer fbk_phase;
integer fbk_delay;
integer phase_shift[0:7];
integer last_phase_shift[0:7];
integer m_times_vco_period;
integer new_m_times_vco_period;
integer refclk_period;
integer fbclk_period;
integer high_time;
integer low_time;
integer my_rem;
integer tmp_rem;
integer rem;
integer tmp_vco_per;
integer vco_per;
integer offset;
integer temp_offset;
integer cycles_to_lock;
integer cycles_to_unlock;
integer c0_count;
integer c0_initial_count;
integer c1_count;
integer c1_initial_count;
integer loop_xplier;
integer loop_initial;
integer loop_ph;
integer cycle_to_adjust;
integer total_pull_back;
integer pull_back_M;
time fbclk_time;
time first_fbclk_time;
time refclk_time;
time next_vco_sched_time;
reg got_first_refclk;
reg got_second_refclk;
reg got_first_fbclk;
reg refclk_last_value;
reg fbclk_last_value;
reg inclk_last_value;
reg pll_is_locked;
reg pll_about_to_lock;
reg locked_tmp;
reg c0_got_first_rising_edge;
reg c1_got_first_rising_edge;
reg vco_c0_last_value;
reg vco_c1_last_value;
reg areset_ipd_last_value;
reg ena_ipd_last_value;
reg pfdena_ipd_last_value;
reg inclk_out_of_range;
reg schedule_vco_last_value;
reg gate_out;
reg vco_val;
reg [31:0] m_initial_val;
reg [31:0] m_val[0:1];
reg [31:0] n_val[0:1];
reg [31:0] m_delay;
reg [8*6:1] m_mode_val[0:1];
reg [8*6:1] n_mode_val[0:1];
reg [31:0] c_high_val[0:5];
reg [31:0] c_low_val[0:5];
reg [8*6:1] c_mode_val[0:5];
reg [31:0] c_initial_val[0:5];
integer c_ph_val[0:5];
// temporary registers for reprogramming
integer c_ph_val_tmp[0:5];
reg [31:0] c_high_val_tmp[0:5];
reg [31:0] c_low_val_tmp[0:5];
reg [8*6:1] c_mode_val_tmp[0:5];
// hold registers for reprogramming
integer c_ph_val_hold[0:5];
reg [31:0] c_high_val_hold[0:5];
reg [31:0] c_low_val_hold[0:5];
reg [8*6:1] c_mode_val_hold[0:5];
// old values
reg [31:0] m_val_old[0:1];
reg [31:0] m_val_tmp[0:1];
reg [31:0] n_val_old[0:1];
reg [8*6:1] m_mode_val_old[0:1];
reg [8*6:1] n_mode_val_old[0:1];
reg [31:0] c_high_val_old[0:5];
reg [31:0] c_low_val_old[0:5];
reg [8*6:1] c_mode_val_old[0:5];
integer c_ph_val_old[0:5];
integer m_ph_val_old;
integer m_ph_val_tmp;
integer cp_curr_old;
integer cp_curr_val;
integer lfc_old;
integer lfc_val;
reg [9*8:1] lfr_val;
reg [9*8:1] lfr_old;
reg [31:0] m_hi;
reg [31:0] m_lo;
// ph tap orig values (POF)
integer c_ph_val_orig[0:5];
integer m_ph_val_orig;
reg schedule_vco;
reg stop_vco;
reg inclk_n;
reg [7:0] vco_out;
reg [7:0] vco_tap;
reg [7:0] vco_out_last_value;
reg [7:0] vco_tap_last_value;
wire inclk_c0;
wire inclk_c1;
wire inclk_c2;
wire inclk_c3;
wire inclk_c4;
wire inclk_c5;
reg inclk_c0_from_vco;
reg inclk_c1_from_vco;
reg inclk_c2_from_vco;
reg inclk_c3_from_vco;
reg inclk_c4_from_vco;
reg inclk_c5_from_vco;
reg inclk_m_from_vco;
wire inclk_m;
wire [5:0] clk_tmp;
wire ena_pll;
wire n_cntr_inclk;
reg vco_c0;
reg vco_c1;
wire [5:0] clk_out;
wire sclkout0;
wire sclkout1;
wire c0_clk;
wire c1_clk;
wire c2_clk;
wire c3_clk;
wire c4_clk;
wire c5_clk;
reg first_schedule;
wire enable0_tmp;
wire enable1_tmp;
wire enable_0;
wire enable_1;
reg vco_period_was_phase_adjusted;
reg phase_adjust_was_scheduled;
wire refclk;
wire fbclk;
wire pllena_reg;
wire test_mode_inclk;
wire sbdout_tmp;
// for external feedback mode
reg [31:0] ext_fbk_cntr_high;
reg [31:0] ext_fbk_cntr_low;
reg [31:0] ext_fbk_cntr_modulus;
reg [8*2:1] ext_fbk_cntr;
reg [8*6:1] ext_fbk_cntr_mode;
integer ext_fbk_cntr_ph;
integer ext_fbk_cntr_initial;
integer ext_fbk_cntr_index;
// variables for clk_switch
reg clk0_is_bad;
reg clk1_is_bad;
reg inclk0_last_value;
reg inclk1_last_value;
reg other_clock_value;
reg other_clock_last_value;
reg primary_clk_is_bad;
reg current_clk_is_bad;
reg external_switch;
reg active_clock;
reg clkloss_tmp;
reg got_curr_clk_falling_edge_after_clkswitch;
integer clk0_count;
integer clk1_count;
integer switch_over_count;
wire scandataout_tmp;
reg scandone_tmp;
reg scandone_tmp_last_value;
integer quiet_time;
integer slowest_clk_old;
integer slowest_clk_new;
reg reconfig_err;
reg error;
time scanclk_last_rising_edge;
time scanread_active_edge;
reg got_first_scanclk;
reg got_first_gated_scanclk;
reg gated_scanclk;
integer scanclk_period;
reg scanclk_last_value;
reg scanread_reg;
reg scanwrite_reg;
reg scanwrite_enabled;
reg scanwrite_last_value;
reg [173:0] scan_data;
reg [173:0] tmp_scan_data;
reg c0_rising_edge_transfer_done;
reg c1_rising_edge_transfer_done;
reg c2_rising_edge_transfer_done;
reg c3_rising_edge_transfer_done;
reg c4_rising_edge_transfer_done;
reg c5_rising_edge_transfer_done;
reg scanread_setup_violation;
integer index;
integer scanclk_cycles;
reg d_msg;
integer num_output_cntrs;
reg no_warn;
// INTERNAL PARAMETERS
parameter GPP_SCAN_CHAIN = 174;
parameter FAST_SCAN_CHAIN = 75;
// primary clk is always inclk0
parameter primary_clock = "inclk0";
// internal variables for scaling of multiply_by and divide_by values
integer i_clk0_mult_by;
integer i_clk0_div_by;
integer i_clk1_mult_by;
integer i_clk1_div_by;
integer i_clk2_mult_by;
integer i_clk2_div_by;
integer i_clk3_mult_by;
integer i_clk3_div_by;
integer i_clk4_mult_by;
integer i_clk4_div_by;
integer i_clk5_mult_by;
integer i_clk5_div_by;
integer max_d_value;
integer new_multiplier;
// internal variables for storing the phase shift number.(used in lvds mode only)
integer i_clk0_phase_shift;
integer i_clk1_phase_shift;
integer i_clk2_phase_shift;
// user to advanced internal signals
integer i_m_initial;
integer i_m;
integer i_n;
integer i_m2;
integer i_n2;
integer i_ss;
integer i_c_high[0:5];
integer i_c_low[0:5];
integer i_c_initial[0:5];
integer i_c_ph[0:5];
reg [8*6:1] i_c_mode[0:5];
integer i_vco_min;
integer i_vco_max;
integer i_vco_center;
integer i_pfd_min;
integer i_pfd_max;
integer i_m_ph;
integer m_ph_val;
reg [8*2:1] i_clk5_counter;
reg [8*2:1] i_clk4_counter;
reg [8*2:1] i_clk3_counter;
reg [8*2:1] i_clk2_counter;
reg [8*2:1] i_clk1_counter;
reg [8*2:1] i_clk0_counter;
integer i_charge_pump_current;
integer i_loop_filter_r;
integer max_neg_abs;
integer output_count;
integer new_divisor;
integer loop_filter_c_arr[0:3];
integer fpll_loop_filter_c_arr[0:3];
integer charge_pump_curr_arr[0:15];
reg [9*8:1] loop_filter_r_arr[0:39];
reg pll_in_test_mode;
reg pll_is_in_reset;
reg pll_is_disabled;
// uppercase to lowercase parameter values
reg [8*`WORD_LENGTH:1] l_operation_mode;
reg [8*`WORD_LENGTH:1] l_pll_type;
reg [8*`WORD_LENGTH:1] l_qualify_conf_done;
reg [8*`WORD_LENGTH:1] l_compensate_clock;
reg [8*`WORD_LENGTH:1] l_scan_chain;
reg [8*`WORD_LENGTH:1] l_primary_clock;
reg [8*`WORD_LENGTH:1] l_gate_lock_signal;
reg [8*`WORD_LENGTH:1] l_switch_over_on_lossclk;
reg [8*`WORD_LENGTH:1] l_switch_over_type;
reg [8*`WORD_LENGTH:1] l_switch_over_on_gated_lock;
reg [8*`WORD_LENGTH:1] l_enable_switch_over_counter;
reg [8*`WORD_LENGTH:1] l_feedback_source;
reg [8*`WORD_LENGTH:1] l_bandwidth_type;
reg [8*`WORD_LENGTH:1] l_simulation_type;
integer current_clock;
reg is_fast_pll;
reg ic1_use_casc_in;
reg ic2_use_casc_in;
reg ic3_use_casc_in;
reg ic4_use_casc_in;
reg ic5_use_casc_in;
reg op_mode;
reg init;
reg tap0_is_active;
specify
endspecify
// finds the closest integer fraction of a given pair of numerator and denominator.
task find_simple_integer_fraction;
input numerator;
input denominator;
input max_denom;
output fraction_num;
output fraction_div;
parameter max_iter = 20;
integer numerator;
integer denominator;
integer max_denom;
integer fraction_num;
integer fraction_div;
integer quotient_array[max_iter-1:0];
integer int_loop_iter;
integer int_quot;
integer m_value;
integer d_value;
integer old_m_value;
integer swap;
integer loop_iter;
integer num;
integer den;
integer i_max_iter;
begin
loop_iter = 0;
num = numerator;
den = denominator;
i_max_iter = max_iter;
while (loop_iter < i_max_iter)
begin
int_quot = num / den;
quotient_array[loop_iter] = int_quot;
num = num - (den*int_quot);
loop_iter=loop_iter+1;
if ((num == 0) || (max_denom != -1) || (loop_iter == i_max_iter))
begin
// calculate the numerator and denominator if there is a restriction on the
// max denom value or if the loop is ending
m_value = 0;
d_value = 1;
// get the rounded value at this stage for the remaining fraction
if (den != 0)
begin
m_value = (2*num/den);
end
// calculate the fraction numerator and denominator at this stage
for (int_loop_iter = loop_iter-1; int_loop_iter >= 0; int_loop_iter=int_loop_iter-1)
begin
if (m_value == 0)
begin
m_value = quotient_array[int_loop_iter];
d_value = 1;
end
else
begin
old_m_value = m_value;
m_value = quotient_array[int_loop_iter]*m_value + d_value;
d_value = old_m_value;
end
end
// if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) || (max_denom == -1))
begin
if ((m_value == 0) || (d_value == 0))
begin
fraction_num = numerator;
fraction_div = denominator;
end
else
begin
fraction_num = m_value;
fraction_div = d_value;
end
end
// end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) && (max_denom != -1)) || (num == 0))
begin
i_max_iter = loop_iter;
end
end
// swap the numerator and denominator for the next round
swap = den;
den = num;
num = swap;
end
end
endtask // find_simple_integer_fraction
// get the absolute value
function integer abs;
input value;
integer value;
begin
if (value < 0)
abs = value * -1;
else abs = value;
end
endfunction
// find twice the period of the slowest clock
function integer slowest_clk;
input C0, C0_mode, C1, C1_mode, C2, C2_mode, C3, C3_mode, C4, C4_mode, C5, C5_mode, refclk, m_mod;
integer C0, C1, C2, C3, C4, C5;
reg [8*6:1] C0_mode, C1_mode, C2_mode, C3_mode, C4_mode, C5_mode;
integer refclk;
reg [31:0] m_mod;
integer max_modulus;
begin
max_modulus = 1;
if (C0_mode != "bypass" && C0_mode != " off")
max_modulus = C0;
if (C1 > max_modulus && C1_mode != "bypass" && C1_mode != " off")
max_modulus = C1;
if (C2 > max_modulus && C2_mode != "bypass" && C2_mode != " off")
max_modulus = C2;
if (C3 > max_modulus && C3_mode != "bypass" && C3_mode != " off")
max_modulus = C3;
if (C4 > max_modulus && C4_mode != "bypass" && C4_mode != " off")
max_modulus = C4;
if (C5 > max_modulus && C5_mode != "bypass" && C5_mode != " off")
max_modulus = C5;
slowest_clk = (refclk * max_modulus *2 / m_mod);
end
endfunction
// count the number of digits in the given integer
function integer count_digit;
input X;
integer X;
integer count, result;
begin
count = 0;
result = X;
while (result != 0)
begin
result = (result / 10);
count = count + 1;
end
count_digit = count;
end
endfunction
// reduce the given huge number(X) to Y significant digits
function integer scale_num;
input X, Y;
integer X, Y;
integer count;
integer fac_ten, lc;
begin
fac_ten = 1;
count = count_digit(X);
for (lc = 0; lc < (count-Y); lc = lc + 1)
fac_ten = fac_ten * 10;
scale_num = (X / fac_ten);
end
endfunction
// find the greatest common denominator of X and Y
function integer gcd;
input X,Y;
integer X,Y;
integer L, S, R, G;
begin
if (X < Y) // find which is smaller.
begin
S = X;
L = Y;
end
else
begin
S = Y;
L = X;
end
R = S;
while ( R > 1)
begin
S = L;
L = R;
R = S % L; // divide bigger number by smaller.
// remainder becomes smaller number.
end
if (R == 0) // if evenly divisible then L is gcd else it is 1.
G = L;
else
G = R;
gcd = G;
end
endfunction
// find the least common multiple of A1 to A10
function integer lcm;
input A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, P;
integer M1, M2, M3, M4, M5 , M6, M7, M8, M9, R;
begin
M1 = (A1 * A2)/gcd(A1, A2);
M2 = (M1 * A3)/gcd(M1, A3);
M3 = (M2 * A4)/gcd(M2, A4);
M4 = (M3 * A5)/gcd(M3, A5);
M5 = (M4 * A6)/gcd(M4, A6);
M6 = (M5 * A7)/gcd(M5, A7);
M7 = (M6 * A8)/gcd(M6, A8);
M8 = (M7 * A9)/gcd(M7, A9);
M9 = (M8 * A10)/gcd(M8, A10);
if (M9 < 3)
R = 10;
else if ((M9 <= 10) && (M9 >= 3))
R = 4 * M9;
else if (M9 > 1000)
R = scale_num(M9, 3);
else
R = M9;
lcm = R;
end
endfunction
// find the factor of division of the output clock frequency
// compared to the VCO
function integer output_counter_value;
input clk_divide, clk_mult, M, N;
integer clk_divide, clk_mult, M, N;
integer R;
begin
R = (clk_divide * M)/(clk_mult * N);
output_counter_value = R;
end
endfunction
// find the mode of each of the PLL counters - bypass, even or odd
function [8*6:1] counter_mode;
input duty_cycle;
input output_counter_value;
integer duty_cycle;
integer output_counter_value;
integer half_cycle_high;
reg [8*6:1] R;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
if (output_counter_value == 1)
R = "bypass";
else if ((half_cycle_high % 2) == 0)
R = " even";
else
R = " odd";
counter_mode = R;
end
endfunction
// find the number of VCO clock cycles to hold the output clock high
function integer counter_high;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle;
integer half_cycle_high;
integer tmp_counter_high;
integer mode;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_high = tmp_counter_high + !mode;
end
endfunction
// find the number of VCO clock cycles to hold the output clock low
function integer counter_low;
input output_counter_value, duty_cycle;
integer output_counter_value, duty_cycle, counter_h;
integer half_cycle_high;
integer mode;
integer tmp_counter_high;
begin
half_cycle_high = (2*duty_cycle*output_counter_value)/100;
mode = ((half_cycle_high % 2) == 0);
tmp_counter_high = half_cycle_high/2;
counter_h = tmp_counter_high + !mode;
counter_low = output_counter_value - counter_h;
end
endfunction
// find the smallest time delay amongst t1 to t10
function integer mintimedelay;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2)
m1 = t1;
else
m1 = t2;
if (m1 < t3)
m2 = m1;
else
m2 = t3;
if (m2 < t4)
m3 = m2;
else
m3 = t4;
if (m3 < t5)
m4 = m3;
else
m4 = t5;
if (m4 < t6)
m5 = m4;
else
m5 = t6;
if (m5 < t7)
m6 = m5;
else
m6 = t7;
if (m6 < t8)
m7 = m6;
else
m7 = t8;
if (m7 < t9)
m8 = m7;
else
m8 = t9;
if (m8 < t10)
m9 = m8;
else
m9 = t10;
if (m9 > 0)
mintimedelay = m9;
else
mintimedelay = 0;
end
endfunction
// find the numerically largest negative number, and return its absolute value
function integer maxnegabs;
input t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer t1, t2, t3, t4, t5, t6, t7, t8, t9, t10;
integer m1,m2,m3,m4,m5,m6,m7,m8,m9;
begin
if (t1 < t2) m1 = t1; else m1 = t2;
if (m1 < t3) m2 = m1; else m2 = t3;
if (m2 < t4) m3 = m2; else m3 = t4;
if (m3 < t5) m4 = m3; else m4 = t5;
if (m4 < t6) m5 = m4; else m5 = t6;
if (m5 < t7) m6 = m5; else m6 = t7;
if (m6 < t8) m7 = m6; else m7 = t8;
if (m7 < t9) m8 = m7; else m8 = t9;
if (m8 < t10) m9 = m8; else m9 = t10;
maxnegabs = (m9 < 0) ? 0 - m9 : 0;
end
endfunction
// adjust the given tap_phase by adding the largest negative number (ph_base)
function integer ph_adjust;
input tap_phase, ph_base;
integer tap_phase, ph_base;
begin
ph_adjust = tap_phase + ph_base;
end
endfunction
// find the number of VCO clock cycles to wait initially before the first
// rising edge of the output clock
function integer counter_initial;
input tap_phase, m, n;
integer tap_phase, m, n, phase;
begin
if (tap_phase < 0) tap_phase = 0 - tap_phase;
// adding 0.5 for rounding correction (required in order to round
// to the nearest integer instead of truncating)
phase = ((tap_phase * m) / (360 * n)) + 0.5;
counter_initial = phase;
end
endfunction
// find which VCO phase tap to align the rising edge of the output clock to
function integer counter_ph;
input tap_phase;
input m,n;
integer m,n, phase;
integer tap_phase;
begin
// adding 0.5 for rounding correction
phase = (tap_phase * m / n) + 0.5;
counter_ph = (phase % 360)/45;
end
endfunction
// convert the given string to length 6 by padding with spaces
function [8*6:1] translate_string;
input [8*6:1] mode;
reg [8*6:1] new_mode;
begin
if (mode == "bypass")
new_mode = "bypass";
else if (mode == "even")
new_mode = " even";
else if (mode == "odd")
new_mode = " odd";
translate_string = new_mode;
end
endfunction
// convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp>=48) && (tmp<=57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign*magnitude;
end
endfunction
// this is for cycloneii lvds only
// convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
// calculate the given phase shift (in ps) in terms of degrees
function integer get_phase_degree;
input phase_shift;
integer phase_shift, result;
begin
result = (phase_shift * 360) / inclk0_input_frequency;
// this is to round up the calculation result
if ( result > 0 )
result = result + 1;
else if ( result < 0 )
result = result - 1;
else
result = 0;
// assign the rounded up result
get_phase_degree = result;
end
endfunction
// convert uppercase parameter values to lowercase
// assumes that the maximum character length of a parameter is 18
function [8*`WORD_LENGTH:1] alpha_tolower;
input [8*`WORD_LENGTH:1] given_string;
reg [8*`WORD_LENGTH:1] return_string;
reg [8*`WORD_LENGTH:1] reg_string;
reg [8:1] tmp;
reg [8:1] conv_char;
integer byte_count;
begin
return_string = " "; // initialise strings to spaces
conv_char = " ";
reg_string = given_string;
for (byte_count = `WORD_LENGTH; byte_count >= 1; byte_count = byte_count - 1)
begin
tmp = reg_string[8*`WORD_LENGTH:(8*(`WORD_LENGTH-1)+1)];
reg_string = reg_string << 8;
if ((tmp >= 65) && (tmp <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = tmp + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
return_string = {return_string, conv_char};
end
else
return_string = {return_string, tmp};
end
alpha_tolower = return_string;
end
endfunction
function integer display_msg;
input [8*2:1] cntr_name;
input msg_code;
integer msg_code;
begin
if (msg_code == 1)
$display ("Warning : %s counter switched from BYPASS mode to enabled. PLL may lose lock.", cntr_name);
else if (msg_code == 2)
$display ("Warning : Illegal 1 value for %s counter. Instead, the %s counter should be BYPASSED. Reconfiguration may not work.", cntr_name, cntr_name);
else if (msg_code == 3)
$display ("Warning : Illegal value for counter %s in BYPASS mode. The LSB of the counter should be set to 0 in order to operate the counter in BYPASS mode. Reconfiguration may not work.", cntr_name);
else if (msg_code == 4)
$display ("Warning : %s counter switched from enabled to BYPASS mode. PLL may lose lock.", cntr_name);
display_msg = 1;
end
endfunction
initial
begin
// convert string parameter values from uppercase to lowercase,
// as expected in this model
l_operation_mode = alpha_tolower(operation_mode);
l_pll_type = alpha_tolower(pll_type);
l_qualify_conf_done = alpha_tolower(qualify_conf_done);
l_compensate_clock = alpha_tolower(compensate_clock);
l_primary_clock = alpha_tolower(primary_clock);
l_gate_lock_signal = alpha_tolower(gate_lock_signal);
l_switch_over_on_lossclk = alpha_tolower(switch_over_on_lossclk);
l_switch_over_on_gated_lock = alpha_tolower(switch_over_on_gated_lock);
l_enable_switch_over_counter = alpha_tolower(enable_switch_over_counter);
l_switch_over_type = alpha_tolower(switch_over_type);
l_feedback_source = alpha_tolower(feedback_source);
l_bandwidth_type = alpha_tolower(bandwidth_type);
l_simulation_type = alpha_tolower(simulation_type);
// initialize charge_pump_current, and loop_filter tables
loop_filter_c_arr[0] = 57;
loop_filter_c_arr[1] = 16;
loop_filter_c_arr[2] = 36;
loop_filter_c_arr[3] = 5;
fpll_loop_filter_c_arr[0] = 18;
fpll_loop_filter_c_arr[1] = 13;
fpll_loop_filter_c_arr[2] = 8;
fpll_loop_filter_c_arr[3] = 2;
charge_pump_curr_arr[0] = 6;
charge_pump_curr_arr[1] = 12;
charge_pump_curr_arr[2] = 30;
charge_pump_curr_arr[3] = 36;
charge_pump_curr_arr[4] = 52;
charge_pump_curr_arr[5] = 57;
charge_pump_curr_arr[6] = 72;
charge_pump_curr_arr[7] = 77;
charge_pump_curr_arr[8] = 92;
charge_pump_curr_arr[9] = 96;
charge_pump_curr_arr[10] = 110;
charge_pump_curr_arr[11] = 114;
charge_pump_curr_arr[12] = 127;
charge_pump_curr_arr[13] = 131;
charge_pump_curr_arr[14] = 144;
charge_pump_curr_arr[15] = 148;
loop_filter_r_arr[0] = " 1.000000";
loop_filter_r_arr[1] = " 1.500000";
loop_filter_r_arr[2] = " 2.000000";
loop_filter_r_arr[3] = " 2.500000";
loop_filter_r_arr[4] = " 3.000000";
loop_filter_r_arr[5] = " 3.500000";
loop_filter_r_arr[6] = " 4.000000";
loop_filter_r_arr[7] = " 4.500000";
loop_filter_r_arr[8] = " 5.000000";
loop_filter_r_arr[9] = " 5.500000";
loop_filter_r_arr[10] = " 6.000000";
loop_filter_r_arr[11] = " 6.500000";
loop_filter_r_arr[12] = " 7.000000";
loop_filter_r_arr[13] = " 7.500000";
loop_filter_r_arr[14] = " 8.000000";
loop_filter_r_arr[15] = " 8.500000";
loop_filter_r_arr[16] = " 9.000000";
loop_filter_r_arr[17] = " 9.500000";
loop_filter_r_arr[18] = "10.000000";
loop_filter_r_arr[19] = "10.500000";
loop_filter_r_arr[20] = "11.000000";
loop_filter_r_arr[21] = "11.500000";
loop_filter_r_arr[22] = "12.000000";
loop_filter_r_arr[23] = "12.500000";
loop_filter_r_arr[24] = "13.000000";
loop_filter_r_arr[25] = "13.500000";
loop_filter_r_arr[26] = "14.000000";
loop_filter_r_arr[27] = "14.500000";
loop_filter_r_arr[28] = "15.000000";
loop_filter_r_arr[29] = "15.500000";
loop_filter_r_arr[30] = "16.000000";
loop_filter_r_arr[31] = "16.500000";
loop_filter_r_arr[32] = "17.000000";
loop_filter_r_arr[33] = "17.500000";
loop_filter_r_arr[34] = "18.000000";
loop_filter_r_arr[35] = "18.500000";
loop_filter_r_arr[36] = "19.000000";
loop_filter_r_arr[37] = "19.500000";
loop_filter_r_arr[38] = "20.000000";
loop_filter_r_arr[39] = "20.500000";
if (m == 0)
begin
i_clk5_counter = "c5" ;
i_clk4_counter = "c4" ;
i_clk3_counter = "c3" ;
i_clk2_counter = "c2" ;
i_clk1_counter = "c1" ;
i_clk0_counter = "c0" ;
end
else begin
i_clk5_counter = alpha_tolower(clk5_counter);
i_clk4_counter = alpha_tolower(clk4_counter);
i_clk3_counter = alpha_tolower(clk3_counter);
i_clk2_counter = alpha_tolower(clk2_counter);
i_clk1_counter = alpha_tolower(clk1_counter);
i_clk0_counter = alpha_tolower(clk0_counter);
end
// VCO feedback loop settings for external feedback mode
// first find which counter is used for feedback
if (l_operation_mode == "external_feedback")
begin
op_mode = 1;
if (l_feedback_source == "clk0")
ext_fbk_cntr = i_clk0_counter;
else if (l_feedback_source == "clk1")
ext_fbk_cntr = i_clk1_counter;
else if (l_feedback_source == "clk2")
ext_fbk_cntr = i_clk2_counter;
else if (l_feedback_source == "clk3")
ext_fbk_cntr = i_clk3_counter;
else if (l_feedback_source == "clk4")
ext_fbk_cntr = i_clk4_counter;
else if (l_feedback_source == "clk5")
ext_fbk_cntr = i_clk5_counter;
else ext_fbk_cntr = "c0";
if (ext_fbk_cntr == "c0")
ext_fbk_cntr_index = 0;
else if (ext_fbk_cntr == "c1")
ext_fbk_cntr_index = 1;
else if (ext_fbk_cntr == "c2")
ext_fbk_cntr_index = 2;
else if (ext_fbk_cntr == "c3")
ext_fbk_cntr_index = 3;
else if (ext_fbk_cntr == "c4")
ext_fbk_cntr_index = 4;
else if (ext_fbk_cntr == "c5")
ext_fbk_cntr_index = 5;
end
else op_mode = 0;
if (m == 0)
begin
// set the limit of the divide_by value that can be returned by
// the following function.
max_d_value = 500;
// scale down the multiply_by and divide_by values provided by the design
// before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
// convert user parameters to advanced
if (((l_pll_type == "fast") || (l_pll_type == "lvds")) && (vco_multiply_by != 0) && (vco_divide_by != 0))
begin
i_n = vco_divide_by;
i_m = vco_multiply_by;
end
else begin
i_n = 1;
i_m = lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by, i_clk5_mult_by,
1, 1, 1, 1, inclk0_input_frequency);
end
i_c_high[0] = counter_high (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high[1] = counter_high (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high[2] = counter_high (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high[3] = counter_high (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high[4] = counter_high (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high[5] = counter_high (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low[0] = counter_low (output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low[1] = counter_low (output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low[2] = counter_low (output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low[3] = counter_low (output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low[4] = counter_low (output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low[5] = counter_low (output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
if (l_pll_type == "flvds")
begin
// Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier = clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift = (clk0_phase_shift_num * new_multiplier);
i_clk1_phase_shift = (clk1_phase_shift_num * new_multiplier);
i_clk2_phase_shift = (clk2_phase_shift_num * new_multiplier);
end
else
begin
i_clk0_phase_shift = get_int_phase_shift(clk0_phase_shift, clk0_phase_shift_num);
i_clk1_phase_shift = get_int_phase_shift(clk1_phase_shift, clk1_phase_shift_num);
i_clk2_phase_shift = get_int_phase_shift(clk2_phase_shift, clk2_phase_shift_num);
end
max_neg_abs = maxnegabs ( i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
0, 0, 0, 0);
i_c_initial[0] = counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[1] = counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[2] = counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_initial[3] = counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[4] = counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs)), i_m, i_n);
i_c_initial[5] = counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs)), i_m, i_n);
i_c_mode[0] = counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode[1] = counter_mode(clk1_duty_cycle,output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode[2] = counter_mode(clk2_duty_cycle,output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode[3] = counter_mode(clk3_duty_cycle,output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode[4] = counter_mode(clk4_duty_cycle,output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode[5] = counter_mode(clk5_duty_cycle,output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_m_ph = counter_ph(get_phase_degree(max_neg_abs), i_m, i_n);
i_m_initial = counter_initial(get_phase_degree(max_neg_abs), i_m, i_n);
i_c_ph[0] = counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[1] = counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[2] = counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs)), i_m, i_n);
i_c_ph[3] = counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[4] = counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs)), i_m, i_n);
i_c_ph[5] = counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs)), i_m, i_n);
// in external feedback mode, need to adjust M value to take
// into consideration the external feedback counter value
if (l_operation_mode == "external_feedback")
begin
// if there is a negative phase shift, m_initial can only be 1
if (max_neg_abs > 0)
i_m_initial = 1;
if (i_c_mode[ext_fbk_cntr_index] == "bypass")
output_count = 1;
else
output_count = i_c_high[ext_fbk_cntr_index] + i_c_low[ext_fbk_cntr_index];
new_divisor = gcd(i_m, output_count);
i_m = i_m / new_divisor;
i_n = output_count / new_divisor;
end
end
else
begin // m != 0
i_n = n;
i_m = m;
i_c_high[0] = c0_high;
i_c_high[1] = c1_high;
i_c_high[2] = c2_high;
i_c_high[3] = c3_high;
i_c_high[4] = c4_high;
i_c_high[5] = c5_high;
i_c_low[0] = c0_low;
i_c_low[1] = c1_low;
i_c_low[2] = c2_low;
i_c_low[3] = c3_low;
i_c_low[4] = c4_low;
i_c_low[5] = c5_low;
i_c_initial[0] = c0_initial;
i_c_initial[1] = c1_initial;
i_c_initial[2] = c2_initial;
i_c_initial[3] = c3_initial;
i_c_initial[4] = c4_initial;
i_c_initial[5] = c5_initial;
i_c_mode[0] = translate_string(alpha_tolower(c0_mode));
i_c_mode[1] = translate_string(alpha_tolower(c1_mode));
i_c_mode[2] = translate_string(alpha_tolower(c2_mode));
i_c_mode[3] = translate_string(alpha_tolower(c3_mode));
i_c_mode[4] = translate_string(alpha_tolower(c4_mode));
i_c_mode[5] = translate_string(alpha_tolower(c5_mode));
i_c_ph[0] = c0_ph;
i_c_ph[1] = c1_ph;
i_c_ph[2] = c2_ph;
i_c_ph[3] = c3_ph;
i_c_ph[4] = c4_ph;
i_c_ph[5] = c5_ph;
i_m_ph = m_ph; // default
i_m_initial = m_initial;
end // user to advanced conversion
refclk_period = inclk0_input_frequency * i_n;
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
fbclk_period = 0;
high_time = 0;
low_time = 0;
schedule_vco = 0;
vco_out[7:0] = 8'b0;
vco_tap[7:0] = 8'b0;
fbclk_last_value = 0;
offset = 0;
temp_offset = 0;
got_first_refclk = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
refclk_time = 0;
first_schedule = 1;
sched_time = 0;
vco_val = 0;
c0_got_first_rising_edge = 0;
c1_got_first_rising_edge = 0;
vco_c0_last_value = 0;
c0_count = 2;
c0_initial_count = 1;
c1_count = 2;
c1_initial_count = 1;
gate_count = 0;
gate_out = 0;
initial_delay = 0;
fbk_phase = 0;
for (i = 0; i <= 7; i = i + 1)
begin
phase_shift[i] = 0;
last_phase_shift[i] = 0;
end
fbk_delay = 0;
inclk_n = 0;
cycle_to_adjust = 0;
m_delay = 0;
vco_c0 = 0;
vco_c1 = 0;
total_pull_back = 0;
pull_back_M = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
ena_ipd_last_value = 0;
inclk_out_of_range = 0;
scandone_tmp = 0;
schedule_vco_last_value = 0;
// set initial values for counter parameters
m_initial_val = i_m_initial;
m_val[0] = i_m;
n_val[0] = i_n;
m_ph_val = i_m_ph;
m_ph_val_orig = i_m_ph;
m_ph_val_tmp = i_m_ph;
m_val_tmp[0] = i_m;
m_val[1] = m2;
n_val[1] = n2;
if (m_val[0] == 1)
m_mode_val[0] = "bypass";
else m_mode_val[0] = "";
if (m_val[1] == 1)
m_mode_val[1] = "bypass";
if (n_val[0] == 1)
n_mode_val[0] = "bypass";
if (n_val[1] == 1)
n_mode_val[1] = "bypass";
for (i = 0; i < 6; i=i+1)
begin
c_high_val[i] = i_c_high[i];
c_low_val[i] = i_c_low[i];
c_initial_val[i] = i_c_initial[i];
c_mode_val[i] = i_c_mode[i];
c_ph_val[i] = i_c_ph[i];
c_high_val_tmp[i] = i_c_high[i];
c_low_val_tmp[i] = i_c_low[i];
if (c_mode_val[i] == "bypass")
begin
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
c_high_val[i] = 5'b10000;
c_low_val[i] = 5'b10000;
c_high_val_tmp[i] = 5'b10000;
c_low_val_tmp[i] = 5'b10000;
end
else begin
c_high_val[i] = 9'b100000000;
c_low_val[i] = 9'b100000000;
c_high_val_tmp[i] = 9'b100000000;
c_low_val_tmp[i] = 9'b100000000;
end
end
c_mode_val_tmp[i] = i_c_mode[i];
c_ph_val_tmp[i] = i_c_ph[i];
c_ph_val_orig[i] = i_c_ph[i];
c_high_val_hold[i] = i_c_high[i];
c_low_val_hold[i] = i_c_low[i];
c_mode_val_hold[i] = i_c_mode[i];
end
lfc_val = loop_filter_c;
lfr_val = loop_filter_r;
cp_curr_val = charge_pump_current;
i = 0;
j = 0;
inclk_last_value = 0;
ext_fbk_cntr_ph = 0;
ext_fbk_cntr_initial = 1;
// initialize clkswitch variables
clk0_is_bad = 0;
clk1_is_bad = 0;
inclk0_last_value = 0;
inclk1_last_value = 0;
other_clock_value = 0;
other_clock_last_value = 0;
primary_clk_is_bad = 0;
current_clk_is_bad = 0;
external_switch = 0;
if (l_primary_clock == "inclk0")
current_clock = 0;
else current_clock = 1;
active_clock = 0; // primary_clk is always inclk0
if (l_pll_type == "fast")
l_switch_over_type = "manual";
if (l_switch_over_type == "manual" && clkswitch_ipd === 1'b1)
begin
current_clock = 1;
active_clock = 1;
end
clkloss_tmp = 0;
got_curr_clk_falling_edge_after_clkswitch = 0;
clk0_count = 0;
clk1_count = 0;
switch_over_count = 0;
// initialize reconfiguration variables
// quiet_time
quiet_time = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
refclk_period, m_val[0]);
reconfig_err = 0;
error = 0;
scanread_active_edge = 0;
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
begin
scan_chain_length = FAST_SCAN_CHAIN;
num_output_cntrs = 4;
end
else
begin
scan_chain_length = GPP_SCAN_CHAIN;
num_output_cntrs = 6;
end
scanread_reg = 0;
scanwrite_reg = 0;
scanwrite_enabled = 0;
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
gated_scanclk = 1;
scanread_setup_violation = 0;
index = 0;
// initialize the scan_chain contents
// CP/LF bits
scan_data[11:0] = 12'b0;
for (i = 0; i <= 3; i = i + 1)
begin
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
begin
if (fpll_loop_filter_c_arr[i] == loop_filter_c)
scan_data[11:10] = i;
end
else begin
if (loop_filter_c_arr[i] == loop_filter_c)
scan_data[11:10] = i;
end
end
for (i = 0; i <= 15; i = i + 1)
begin
if (charge_pump_curr_arr[i] == charge_pump_current)
scan_data[3:0] = i;
end
for (i = 0; i <= 39; i = i + 1)
begin
if (loop_filter_r_arr[i] == loop_filter_r)
begin
if ((i >= 16) && (i <= 23))
scan_data[9:4] = i+8;
else if ((i >= 24) && (i <= 31))
scan_data[9:4] = i+16;
else if (i >= 32)
scan_data[9:4] = i+24;
else
scan_data[9:4] = i;
end
end
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
scan_data[21:12] = 10'b0; // M, C3-C0 ph
// C0-C3 high
scan_data[25:22] = c_high_val[0];
scan_data[35:32] = c_high_val[1];
scan_data[45:42] = c_high_val[2];
scan_data[55:52] = c_high_val[3];
// C0-C3 low
scan_data[30:27] = c_low_val[0];
scan_data[40:37] = c_low_val[1];
scan_data[50:47] = c_low_val[2];
scan_data[60:57] = c_low_val[3];
// C0-C3 mode
for (i = 0; i < 4; i = i + 1)
begin
if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
begin
scan_data[26 + (10*i)] = 1;
if (c_mode_val[i] == " off")
scan_data[31 + (10*i)] = 1;
else
scan_data[31 + (10*i)] = 0;
end
else begin
scan_data[26 + (10*i)] = 0;
if (c_mode_val[i] == " odd")
scan_data[31 + (10*i)] = 1;
else
scan_data[31 + (10*i)] = 0;
end
end
// M
if (m_mode_val[0] == "bypass")
begin
scan_data[66] = 1;
scan_data[71] = 0;
scan_data[65:62] = 4'b0;
scan_data[70:67] = 4'b0;
end
else begin
scan_data[66] = 0; // set BYPASS bit to 0
scan_data[70:67] = m_val[0]/2; // set M low
if (m_val[0] % 2 == 0)
begin
// M is an even no. : set M high = low,
// set odd/even bit to 0
scan_data[65:62] = scan_data[70:67];
scan_data[71] = 0;
end
else begin // M is odd : M high = low + 1
scan_data[65:62] = (m_val[0]/2) + 1;
scan_data[71] = 1;
end
end
// N
scan_data[73:72] = n_val[0];
if (n_mode_val[0] == "bypass")
begin
scan_data[74] = 1;
scan_data[73:72] = 2'b0;
end
end
else begin // PLL type is enhanced/auto
scan_data[25:12] = 14'b0;
// C5-C0 high
scan_data[33:26] = c_high_val[5];
scan_data[51:44] = c_high_val[4];
scan_data[69:62] = c_high_val[3];
scan_data[87:80] = c_high_val[2];
scan_data[105:98] = c_high_val[1];
scan_data[123:116] = c_high_val[0];
// C5-C0 low
scan_data[42:35] = c_low_val[5];
scan_data[60:53] = c_low_val[4];
scan_data[78:71] = c_low_val[3];
scan_data[96:89] = c_low_val[2];
scan_data[114:107] = c_low_val[1];
scan_data[132:125] = c_low_val[0];
for (i = 5; i >= 0; i = i - 1)
begin
if (c_mode_val[i] == " off" || c_mode_val[i] == "bypass")
begin
scan_data[124 - (18*i)] = 1;
if (c_mode_val[i] == " off")
scan_data[133 - (18*i)] = 1;
else
scan_data[133 - (18*i)] = 0;
end
else begin
scan_data[124 - (18*i)] = 0;
if (c_mode_val[i] == " odd")
scan_data[133 - (18*i)] = 1;
else
scan_data[133 - (18*i)] = 0;
end
end
scan_data[142:134] = m_val[0];
scan_data[143] = 0;
scan_data[152:144] = m_val[1];
scan_data[153] = 0;
if (m_mode_val[0] == "bypass")
begin
scan_data[143] = 1;
scan_data[142:134] = 9'b0;
end
if (m_mode_val[1] == "bypass")
begin
scan_data[153] = 1;
scan_data[152:144] = 9'b0;
end
scan_data[162:154] = n_val[0];
scan_data[172:164] = n_val[1];
if (n_mode_val[0] == "bypass")
begin
scan_data[163] = 1;
scan_data[162:154] = 9'b0;
end
if (n_mode_val[1] == "bypass")
begin
scan_data[173] = 1;
scan_data[172:164] = 9'b0;
end
end
// now save this counter's parameters
ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
ext_fbk_cntr_initial = c_initial_val[ext_fbk_cntr_index];
ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
l_index = 1;
stop_vco = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
no_warn = 1'b0;
// check if pll is in test mode
if (m_test_source == 1 || c0_test_source == 1 || c0_test_source == 2 || c1_test_source == 1 || c1_test_source == 2 || c2_test_source == 1 || c2_test_source == 2)
pll_in_test_mode = 1'b1;
else
pll_in_test_mode = 1'b0;
pll_is_in_reset = 0;
pll_is_disabled = 0;
if (l_pll_type == "fast" || l_pll_type == "lvds")
is_fast_pll = 1;
else is_fast_pll = 0;
if (c1_use_casc_in == "on")
ic1_use_casc_in = 1;
else
ic1_use_casc_in = 0;
if (c2_use_casc_in == "on")
ic2_use_casc_in = 1;
else
ic2_use_casc_in = 0;
if (c3_use_casc_in == "on")
ic3_use_casc_in = 1;
else
ic3_use_casc_in = 0;
if (c4_use_casc_in == "on")
ic4_use_casc_in = 1;
else
ic4_use_casc_in = 0;
if (c5_use_casc_in == "on")
ic5_use_casc_in = 1;
else
ic5_use_casc_in = 0;
tap0_is_active = 1;
next_vco_sched_time = 0;
end
always @(clkswitch_ipd)
begin
if (clkswitch_ipd === 1'b1 && l_switch_over_type == "auto")
external_switch = 1;
else if (l_switch_over_type == "manual")
begin
if (clkswitch_ipd === 1'b1)
begin
current_clock = 1;
active_clock = 1;
inclk_n = inclk1_ipd;
end
else if (clkswitch_ipd === 1'b0)
begin
current_clock = 0;
active_clock = 0;
inclk_n = inclk0_ipd;
end
end
end
always @(inclk0_ipd or inclk1_ipd)
begin
// save the inclk event value
if (inclk0_ipd !== inclk0_last_value)
begin
if (current_clock != 0)
other_clock_value = inclk0_ipd;
end
if (inclk1_ipd !== inclk1_last_value)
begin
if (current_clock != 1)
other_clock_value = inclk1_ipd;
end
// check if either input clk is bad
if (inclk0_ipd === 1'b1 && inclk0_ipd !== inclk0_last_value)
begin
clk0_count = clk0_count + 1;
clk0_is_bad = 0;
clk1_count = 0;
if (clk0_count > 2)
begin
// no event on other clk for 2 cycles
clk1_is_bad = 1;
if (current_clock == 1)
current_clk_is_bad = 1;
end
end
if (inclk1_ipd === 1'b1 && inclk1_ipd !== inclk1_last_value)
begin
clk1_count = clk1_count + 1;
clk1_is_bad = 0;
clk0_count = 0;
if (clk1_count > 2)
begin
// no event on other clk for 2 cycles
clk0_is_bad = 1;
if (current_clock == 0)
current_clk_is_bad = 1;
end
end
// check if the bad clk is the primary clock, which is always clk0
if (clk0_is_bad == 1'b1)
primary_clk_is_bad = 1;
else
primary_clk_is_bad = 0;
// actual switching -- manual switch
if ((inclk0_ipd !== inclk0_last_value) && current_clock == 0)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk0_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk0_ipd;
end
end
else inclk_n = inclk0_ipd;
end
if ((inclk1_ipd !== inclk1_last_value) && current_clock == 1)
begin
if (external_switch == 1'b1)
begin
if (!got_curr_clk_falling_edge_after_clkswitch)
begin
if (inclk1_ipd === 1'b0)
got_curr_clk_falling_edge_after_clkswitch = 1;
inclk_n = inclk1_ipd;
end
end
else inclk_n = inclk1_ipd;
end
// actual switching -- automatic switch
if ((other_clock_value == 1'b1) && (other_clock_value != other_clock_last_value) && (l_switch_over_on_lossclk == "on") && l_enable_switch_over_counter == "on" && primary_clk_is_bad)
switch_over_count = switch_over_count + 1;
if ((other_clock_value == 1'b0) && (other_clock_value != other_clock_last_value))
begin
if ((external_switch && (got_curr_clk_falling_edge_after_clkswitch || current_clk_is_bad)) || (l_switch_over_on_lossclk == "on" && primary_clk_is_bad && l_pll_type !== "fast" && l_pll_type !== "lvds" && ((l_enable_switch_over_counter == "off" || switch_over_count == switch_over_counter))))
begin
got_curr_clk_falling_edge_after_clkswitch = 0;
if (current_clock == 0)
current_clock = 1;
else
current_clock = 0;
active_clock = ~active_clock;
switch_over_count = 0;
external_switch = 0;
current_clk_is_bad = 0;
end
end
if (l_switch_over_on_lossclk == "on" && (clkswitch_ipd != 1'b1))
begin
if (primary_clk_is_bad)
clkloss_tmp = 1;
else
clkloss_tmp = 0;
end
else clkloss_tmp = clkswitch_ipd;
inclk0_last_value = inclk0_ipd;
inclk1_last_value = inclk1_ipd;
other_clock_last_value = other_clock_value;
end
cycloneii_pll_reg ena_reg ( .clk(!inclk_n),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(1'b1),
.q(pllena_reg));
and (test_mode_inclk, inclk_n, pllena_reg);
assign n_cntr_inclk = inclk_n;
assign ena_pll = ena_ipd;
assign inclk_m = (m_test_source == 1) ? refclk : (m_test_source == 2) ? 1'b0 : (m_test_source == 3) ? 1'b0 : op_mode == 1 ? (l_feedback_source == "clk0" ? clk_tmp[0] :
l_feedback_source == "clk1" ? clk_tmp[1] :
l_feedback_source == "clk2" ? clk_tmp[2] :
l_feedback_source == "clk3" ? clk_tmp[3] :
l_feedback_source == "clk4" ? clk_tmp[4] :
l_feedback_source == "clk5" ? clk_tmp[5] : 'b0) :
inclk_m_from_vco;
cycloneii_m_cntr m1 (.clk(inclk_m),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(fbclk),
.initial_value(m_initial_val),
.modulus(m_val[0]),
.time_delay(m_delay));
cycloneii_n_cntr n1 (.clk(n_cntr_inclk),
.reset(areset_ipd),
.cout(refclk),
.modulus(n_val[0]));
always @(vco_out)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_out[x] !== vco_out_last_value[x])
begin
// TAP 'X' has event
if ((x == 0) && (!pll_is_in_reset) && (!pll_is_disabled) && (stop_vco !== 1'b1))
begin
if (vco_out[0] == 1'b1)
tap0_is_active = 1;
if (tap0_is_active == 1'b1)
vco_tap[0] <= vco_out[0];
end
else if (tap0_is_active == 1'b1)
vco_tap[x] <= vco_out[x];
if (stop_vco === 1'b1)
vco_out[x] <= 1'b0;
end
end
vco_out_last_value = vco_out;
end
always @(vco_tap)
begin
// check which VCO TAP has event
for (x = 0; x <= 7; x = x + 1)
begin
if (vco_tap[x] !== vco_tap_last_value[x])
begin
if (c_ph_val[0] == x)
begin
inclk_c0_from_vco <= vco_tap[x];
end
if (c_ph_val[1] == x)
begin
inclk_c1_from_vco <= vco_tap[x];
end
if (c_ph_val[2] == x)
inclk_c2_from_vco <= vco_tap[x];
if (c_ph_val[3] == x)
inclk_c3_from_vco <= vco_tap[x];
if (c_ph_val[4] == x)
inclk_c4_from_vco <= vco_tap[x];
if (c_ph_val[5] == x)
inclk_c5_from_vco <= vco_tap[x];
if (m_ph_val == x)
inclk_m_from_vco <= vco_tap[x];
end
end
if (scanwrite_enabled === 1'b1)
begin
for (x = 0; x <= 7; x = x + 1)
begin
if ((vco_tap[x] === 1'b0) && (vco_tap[x] !== vco_tap_last_value[x]))
begin
for (y = 0; y <= 5; y = y + 1)
begin
if (c_ph_val[y] == x)
c_ph_val[y] <= c_ph_val_tmp[y];
end
if (m_ph_val == x)
m_ph_val <= m_ph_val_tmp;
end
end
end
// reset all counter phase tap values to POF programmed values
if (areset_ipd === 1'b1)
begin
m_ph_val <= m_ph_val_orig;
m_ph_val_tmp <= m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
begin
c_ph_val[i] <= c_ph_val_orig[i];
c_ph_val_tmp[i] <= c_ph_val_orig[i];
end
end
vco_tap_last_value = vco_tap;
end
assign inclk_c0 = (c0_test_source == 1) ? refclk : (c0_test_source == 2) ? fbclk : (c0_test_source == 3) ? 1'b0 : inclk_c0_from_vco;
cycloneii_scale_cntr c0 (.clk(inclk_c0),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c0_clk),
.high(c_high_val[0]),
.low(c_low_val[0]),
.initial_value(c_initial_val[0]),
.mode(c_mode_val[0]),
.ph_tap(c_ph_val[0]));
always @(posedge c0_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[0] <= c_high_val_tmp[0];
c_mode_val_hold[0] <= c_mode_val_tmp[0];
c_high_val[0] <= c_high_val_hold[0];
c_mode_val[0] <= c_mode_val_hold[0];
c0_rising_edge_transfer_done = 1;
end
end
always @(negedge c0_clk)
begin
if (c0_rising_edge_transfer_done)
begin
c_low_val_hold[0] <= c_low_val_tmp[0];
c_low_val[0] <= c_low_val_hold[0];
end
end
assign inclk_c1 = (c1_test_source == 1) ? refclk : (c1_test_source == 2) ? fbclk : (c1_test_source == 3) ? 1'b0 : (ic1_use_casc_in == 1) ? c0_clk : inclk_c1_from_vco;
cycloneii_scale_cntr c1 (.clk(inclk_c1),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c1_clk),
.high(c_high_val[1]),
.low(c_low_val[1]),
.initial_value(c_initial_val[1]),
.mode(c_mode_val[1]),
.ph_tap(c_ph_val[1]));
always @(posedge c1_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[1] <= c_high_val_tmp[1];
c_mode_val_hold[1] <= c_mode_val_tmp[1];
c_high_val[1] <= c_high_val_hold[1];
c_mode_val[1] <= c_mode_val_hold[1];
c1_rising_edge_transfer_done = 1;
end
end
always @(negedge c1_clk)
begin
if (c1_rising_edge_transfer_done)
begin
c_low_val_hold[1] <= c_low_val_tmp[1];
c_low_val[1] <= c_low_val_hold[1];
end
end
assign inclk_c2 = (c2_test_source == 1) ? refclk : (c2_test_source == 2) ? fbclk : (c2_test_source == 3) ? 1'b0 : (ic2_use_casc_in == 1) ? c1_clk : inclk_c2_from_vco;
cycloneii_scale_cntr c2 (.clk(inclk_c2),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c2_clk),
.high(c_high_val[2]),
.low(c_low_val[2]),
.initial_value(c_initial_val[2]),
.mode(c_mode_val[2]),
.ph_tap(c_ph_val[2]));
always @(posedge c2_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[2] <= c_high_val_tmp[2];
c_mode_val_hold[2] <= c_mode_val_tmp[2];
c_high_val[2] <= c_high_val_hold[2];
c_mode_val[2] <= c_mode_val_hold[2];
c2_rising_edge_transfer_done = 1;
end
end
always @(negedge c2_clk)
begin
if (c2_rising_edge_transfer_done)
begin
c_low_val_hold[2] <= c_low_val_tmp[2];
c_low_val[2] <= c_low_val_hold[2];
end
end
assign inclk_c3 = (c3_test_source == 0) ? n_cntr_inclk : (ic3_use_casc_in == 1) ? c2_clk : inclk_c3_from_vco;
cycloneii_scale_cntr c3 (.clk(inclk_c3),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c3_clk),
.high(c_high_val[3]),
.low(c_low_val[3]),
.initial_value(c_initial_val[3]),
.mode(c_mode_val[3]),
.ph_tap(c_ph_val[3]));
always @(posedge c3_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[3] <= c_high_val_tmp[3];
c_mode_val_hold[3] <= c_mode_val_tmp[3];
c_high_val[3] <= c_high_val_hold[3];
c_mode_val[3] <= c_mode_val_hold[3];
c3_rising_edge_transfer_done = 1;
end
end
always @(negedge c3_clk)
begin
if (c3_rising_edge_transfer_done)
begin
c_low_val_hold[3] <= c_low_val_tmp[3];
c_low_val[3] <= c_low_val_hold[3];
end
end
assign inclk_c4 = ((c4_test_source == 0) ? n_cntr_inclk : (ic4_use_casc_in == 1) ? c3_clk : inclk_c4_from_vco);
cycloneii_scale_cntr c4 (.clk(inclk_c4),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c4_clk),
.high(c_high_val[4]),
.low(c_low_val[4]),
.initial_value(c_initial_val[4]),
.mode(c_mode_val[4]),
.ph_tap(c_ph_val[4]));
always @(posedge c4_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[4] <= c_high_val_tmp[4];
c_mode_val_hold[4] <= c_mode_val_tmp[4];
c_high_val[4] <= c_high_val_hold[4];
c_mode_val[4] <= c_mode_val_hold[4];
c4_rising_edge_transfer_done = 1;
end
end
always @(negedge c4_clk)
begin
if (c4_rising_edge_transfer_done)
begin
c_low_val_hold[4] <= c_low_val_tmp[4];
c_low_val[4] <= c_low_val_hold[4];
end
end
assign inclk_c5 = ((c5_test_source == 0) ? n_cntr_inclk : (ic5_use_casc_in == 1) ? c4_clk : inclk_c5_from_vco);
cycloneii_scale_cntr c5 (.clk(inclk_c5),
.reset(areset_ipd || (!ena_pll) || stop_vco),
.cout(c5_clk),
.high(c_high_val[5]),
.low(c_low_val[5]),
.initial_value(c_initial_val[5]),
.mode(c_mode_val[5]),
.ph_tap(c_ph_val[5]));
always @(posedge c5_clk)
begin
if (scanwrite_enabled == 1'b1)
begin
c_high_val_hold[5] <= c_high_val_tmp[5];
c_mode_val_hold[5] <= c_mode_val_tmp[5];
c_high_val[5] <= c_high_val_hold[5];
c_mode_val[5] <= c_mode_val_hold[5];
c5_rising_edge_transfer_done = 1;
end
end
always @(negedge c5_clk)
begin
if (c5_rising_edge_transfer_done)
begin
c_low_val_hold[5] <= c_low_val_tmp[5];
c_low_val[5] <= c_low_val_hold[5];
end
end
always @ (inclk_n or ena_pll or areset_ipd)
begin
if (areset_ipd == 1'b1 || ena_pll == 1'b0)
begin
gate_count = 0;
gate_out = 0;
end
else if (inclk_n == 'b1 && inclk_last_value != inclk_n)
begin
gate_count = gate_count + 1;
if (gate_count == gate_lock_counter)
gate_out = 1;
end
inclk_last_value = inclk_n;
end
assign locked = (l_gate_lock_signal == "yes") ? gate_out && locked_tmp : locked_tmp;
always @(posedge scanread_ipd)
begin
scanread_active_edge = $time;
end
always @ (scanclk_ipd)
begin
if (scanclk_ipd === 1'b0 && scanclk_last_value === 1'b1)
begin
// enable scanwrite on falling edge
scanwrite_enabled <= scanwrite_reg;
end
if (scanread_reg === 1'b1)
gated_scanclk <= scanclk_ipd && scanread_reg;
else
gated_scanclk <= 1'b1;
if (scanclk_ipd === 1'b1 && scanclk_last_value === 1'b0)
begin
// register scanread and scanwrite
scanread_reg <= scanread_ipd;
scanwrite_reg <= scanwrite_ipd;
if (got_first_scanclk)
scanclk_period = $time - scanclk_last_rising_edge;
else begin
got_first_scanclk = 1;
end
// reset got_first_scanclk on falling edge of scanread_reg
if (scanread_ipd == 1'b0 && scanread_reg == 1'b1)
begin
got_first_scanclk = 0;
got_first_gated_scanclk = 0;
end
scanclk_last_rising_edge = $time;
end
scanclk_last_value = scanclk_ipd;
end
always @(posedge gated_scanclk)
begin
if ($time > 0)
begin
if (!got_first_gated_scanclk)
begin
got_first_gated_scanclk = 1;
// if ($time - scanread_active_edge < scanclk_period)
// begin
// scanread_setup_violation = 1;
// $display("Warning : SCANREAD must go high at least one cycle before SCANDATA is read in.");
// $display ("Time: %0t Instance: %m", $time);
// end
end
for (j = scan_chain_length-1; j >= 1; j = j - 1)
begin
scan_data[j] = scan_data[j - 1];
end
scan_data[0] <= scandata_ipd;
end
end
assign scandataout_tmp = (l_pll_type == "fast" || l_pll_type == "lvds") ? scan_data[FAST_SCAN_CHAIN-1] : scan_data[GPP_SCAN_CHAIN-1];
always @(posedge scandone_tmp)
begin
if (reconfig_err == 1'b0)
begin
$display("NOTE : CycloneII PLL Reprogramming completed with the following values (Values in parantheses are original values) : ");
$display ("Time: %0t Instance: %m", $time);
$display(" N modulus = %0d (%0d) ", n_val[0], n_val_old[0]);
$display(" M modulus = %0d (%0d) ", m_val[0], m_val_old[0]);
$display(" M ph_tap = %0d (%0d) ", m_ph_val, m_ph_val_old);
if (ss > 0)
begin
$display(" M2 modulus = %0d (%0d) ", m_val[1], m_val_old[1]);
$display(" N2 modulus = %0d (%0d) ", n_val[1], n_val_old[1]);
end
for (i = 0; i < num_output_cntrs; i=i+1)
begin
$display(" C%0d high = %0d (%0d), C%0d low = %0d (%0d), C%0d mode = %s (%s), C%0d phase tap = %0d (%0d)", i, c_high_val[i], c_high_val_old[i], i, c_low_val_tmp[i], c_low_val_old[i], i, c_mode_val[i], c_mode_val_old[i], i, c_ph_val[i], c_ph_val_old[i]);
end
// display Charge pump and loop filter values
$display (" Charge Pump Current (uA) = %0d (%0d) ", cp_curr_val, cp_curr_old);
$display (" Loop Filter Capacitor (pF) = %0d (%0d) ", lfc_val, lfc_old);
$display (" Loop Filter Resistor (Kohm) = %s (%s) ", lfr_val, lfr_old);
end
else begin
$display("Warning : Errors were encountered during PLL reprogramming. Please refer to error/warning messages above.");
$display ("Time: %0t Instance: %m", $time);
end
end
always @(scanwrite_enabled)
begin
if (scanwrite_enabled === 1'b0 && scanwrite_last_value === 1'b1)
begin
// falling edge : deassert scandone
scandone_tmp <= #(1.5*scanclk_period) 1'b0;
// reset counter transfer flags
c0_rising_edge_transfer_done = 0;
c1_rising_edge_transfer_done = 0;
c2_rising_edge_transfer_done = 0;
c3_rising_edge_transfer_done = 0;
c4_rising_edge_transfer_done = 0;
c5_rising_edge_transfer_done = 0;
end
if (scanwrite_enabled === 1'b1 && scanwrite_last_value !== scanwrite_enabled)
begin
$display ("NOTE : CycloneII PLL Reprogramming initiated ....");
$display ("Time: %0t Instance: %m", $time);
error = 0;
reconfig_err = 0;
scanread_setup_violation = 0;
// make temp. copy of scan_data for processing
tmp_scan_data = scan_data;
// save old values
cp_curr_old = cp_curr_val;
lfc_old = lfc_val;
lfr_old = lfr_val;
// CP
// Bits 0-3 : all values are legal
cp_curr_val = charge_pump_curr_arr[scan_data[3:0]];
// LF Resistance : bits 4-9
// values from 010000 - 010111, 100000 - 100111,
// 110000- 110111 are illegal
if (((tmp_scan_data[9:4] >= 6'b010000) && (tmp_scan_data[9:4] <= 6'b010111)) ||
((tmp_scan_data[9:4] >= 6'b100000) && (tmp_scan_data[9:4] <= 6'b100111)) ||
((tmp_scan_data[9:4] >= 6'b110000) && (tmp_scan_data[9:4] <= 6'b110111)))
begin
$display ("Illegal bit settings for Loop Filter Resistance. Legal bit values range from 000000 to 001111, 011000 to 011111, 101000 to 101111 and 111000 to 111111. Reconfiguration may not work.");
reconfig_err = 1;
end
else begin
i = scan_data[9:4];
if (i >= 56 )
i = i - 24;
else if ((i >= 40) && (i <= 47))
i = i - 16;
else if ((i >= 24) && (i <= 31))
i = i - 8;
lfr_val = loop_filter_r_arr[i];
end
// LF Capacitance : bits 10,11 : all values are legal
if ((l_pll_type == "fast") || (l_pll_type == "lvds"))
lfc_val = fpll_loop_filter_c_arr[scan_data[11:10]];
else
lfc_val = loop_filter_c_arr[scan_data[11:10]];
// save old values for display info.
for (i=0; i<=1; i=i+1)
begin
m_val_old[i] = m_val[i];
n_val_old[i] = n_val[i];
m_mode_val_old[i] = m_mode_val[i];
n_mode_val_old[i] = n_mode_val[i];
end
m_ph_val_old = m_ph_val;
for (i=0; i<=5; i=i+1)
begin
c_high_val_old[i] = c_high_val[i];
c_low_val_old[i] = c_low_val[i];
c_ph_val_old[i] = c_ph_val[i];
c_mode_val_old[i] = c_mode_val[i];
end
// first the M counter phase : bit order same for fast and GPP
if (scan_data[12] == 1'b0)
begin
// do nothing
end
else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b1)
begin
m_ph_val_tmp = m_ph_val_tmp + 1;
if (m_ph_val_tmp > 7)
m_ph_val_tmp = 0;
end
else if (scan_data[12] === 1'b1 && scan_data[13] === 1'b0)
begin
m_ph_val_tmp = m_ph_val_tmp - 1;
if (m_ph_val_tmp < 0)
m_ph_val_tmp = 7;
end
else begin
$display ("Warning : Illegal bit settings for M counter phase tap. Reconfiguration may not work.");
reconfig_err = 1;
end
// read the fast PLL bits.
if (l_pll_type == "fast" || l_pll_type == "lvds")
begin
// C3-C0 phase bits
for (i = 3; i >= 0; i=i-1)
begin
if (tmp_scan_data[14] == 1'b0)
begin
// do nothing
end
else if (tmp_scan_data[14] === 1'b1)
begin
if (tmp_scan_data[15] === 1'b1)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
if (c_ph_val_tmp[i] > 7)
c_ph_val_tmp[i] = 0;
end
else if (tmp_scan_data[15] === 1'b0)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
if (c_ph_val_tmp[i] < 0)
c_ph_val_tmp[i] = 7;
end
end
tmp_scan_data = tmp_scan_data >> 2;
end
// C0-C3 counter moduli
tmp_scan_data = scan_data;
for (i = 0; i < 4; i=i+1)
begin
if (tmp_scan_data[26] == 1'b1)
begin
c_mode_val_tmp[i] = "bypass";
if (tmp_scan_data[31] === 1'b1)
begin
c_mode_val_tmp[i] = " off";
$display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
end
end
else if (tmp_scan_data[31] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
if (tmp_scan_data[25:22] === 4'b0000)
c_high_val_tmp[i] = 5'b10000;
else
c_high_val_tmp[i] = tmp_scan_data[25:22];
if (tmp_scan_data[30:27] === 4'b0000)
c_low_val_tmp[i] = 5'b10000;
else
c_low_val_tmp[i] = tmp_scan_data[30:27];
tmp_scan_data = tmp_scan_data >> 10;
end
// M
error = 0;
// some temporary storage
if (scan_data[65:62] == 4'b0000)
m_hi = 5'b10000;
else
m_hi = scan_data[65:62];
if (scan_data[70:67] == 4'b0000)
m_lo = 5'b10000;
else
m_lo = scan_data[70:67];
m_val_tmp[0] = m_hi + m_lo;
if (scan_data[66] === 1'b1)
begin
if (scan_data[71] === 1'b1)
begin
// this will turn off the M counter : error
reconfig_err = 1;
error = 1;
$display ("The specified bit settings will turn OFF the M counter. This is illegal. Reconfiguration may not work.");
end
else begin
// M counter is being bypassed
if (m_mode_val[0] !== "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" M", 4);
end
m_val_tmp[0] = 32'b1;
m_mode_val[0] = "bypass";
end
end
else begin
if (m_mode_val[0] === "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" M", 1);
end
m_mode_val[0] = "";
if (scan_data[71] === 1'b1)
begin
// odd : check for duty cycle, if not 50% -- error
if (m_hi - m_lo !== 1)
begin
reconfig_err = 1;
$display ("Warning : The M counter of the CycloneII Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work");
end
end
else begin // even mode
if (m_hi !== m_lo)
begin
reconfig_err = 1;
$display ("Warning : The M counter of the CycloneII Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work");
end
end
end
// N
error = 0;
n_val[0] = scan_data[73:72];
if (scan_data[74] !== 1'b1)
begin
if (scan_data[73:72] == 2'b01)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
d_msg = display_msg(" N", 2);
end
else if (scan_data[73:72] == 2'b00)
n_val[0] = 3'b100;
if (error == 1'b0)
begin
if (n_mode_val[0] === "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" N", 1);
end
n_mode_val[0] = "";
end
end
else if (scan_data[74] == 1'b1) // bypass
begin
if (scan_data[72] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
d_msg = display_msg(" N", 3);
end
else begin
if (n_mode_val[0] != "bypass")
begin
// Mode is switched : give warning
d_msg = display_msg(" N", 4);
end
n_val[0] = 2'b01;
n_mode_val[0] = "bypass";
end
end
end
else begin // pll type is auto or enhanced
for (i = 0; i < 6; i=i+1)
begin
if (tmp_scan_data[124] == 1'b1)
begin
c_mode_val_tmp[i] = "bypass";
if (tmp_scan_data[133] === 1'b1)
begin
c_mode_val_tmp[i] = " off";
$display("Warning : The specified bit settings will turn OFF the C%0d counter. It cannot be turned on unless the part is re-initialized.", i);
end
end
else if (tmp_scan_data[133] == 1'b1)
c_mode_val_tmp[i] = " odd";
else
c_mode_val_tmp[i] = " even";
if (tmp_scan_data[123:116] === 8'b00000000)
c_high_val_tmp[i] = 9'b100000000;
else
c_high_val_tmp[i] = tmp_scan_data[123:116];
if (tmp_scan_data[132:125] === 8'b00000000)
c_low_val_tmp[i] = 9'b100000000;
else
c_low_val_tmp[i] = tmp_scan_data[132:125];
tmp_scan_data = tmp_scan_data << 18;
end
// the phase_taps
tmp_scan_data = scan_data;
for (i = 0; i < 6; i=i+1)
begin
if (tmp_scan_data[14] == 1'b0)
begin
// do nothing
end
else if (tmp_scan_data[14] === 1'b1)
begin
if (tmp_scan_data[15] === 1'b1)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] + 1;
if (c_ph_val_tmp[i] > 7)
c_ph_val_tmp[i] = 0;
end
else if (tmp_scan_data[15] === 1'b0)
begin
c_ph_val_tmp[i] = c_ph_val_tmp[i] - 1;
if (c_ph_val_tmp[i] < 0)
c_ph_val_tmp[i] = 7;
end
end
tmp_scan_data = tmp_scan_data >> 2;
end
ext_fbk_cntr_high = c_high_val[ext_fbk_cntr_index];
ext_fbk_cntr_low = c_low_val[ext_fbk_cntr_index];
ext_fbk_cntr_ph = c_ph_val[ext_fbk_cntr_index];
ext_fbk_cntr_mode = c_mode_val[ext_fbk_cntr_index];
// cntrs M/M2
tmp_scan_data = scan_data;
for (i=0; i<2; i=i+1)
begin
if (i == 0 || (i == 1 && ss > 0))
begin
error = 0;
m_val_tmp[i] = tmp_scan_data[142:134];
if (tmp_scan_data[143] !== 1'b1)
begin
if (tmp_scan_data[142:134] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" M", 2);
else
d_msg = display_msg("M2", 2);
end
else if (tmp_scan_data[142:134] == 9'b000000000)
m_val_tmp[i] = 10'b1000000000;
if (error == 1'b0)
begin
if (m_mode_val[i] === "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" M", 1);
else
d_msg = display_msg("M2", 1);
end
m_mode_val[i] = "";
end
end
else if (tmp_scan_data[143] == 1'b1)
begin
if (tmp_scan_data[134] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" M", 3);
else
d_msg = display_msg("M2", 3);
end
else begin
if (m_mode_val[i] !== "bypass")
begin
// Mode is switched: give warning
if (i == 0)
d_msg = display_msg(" M", 4);
else
d_msg = display_msg("M2", 4);
end
m_val_tmp[i] = 10'b0000000001;
m_mode_val[i] = "bypass";
end
end
end
tmp_scan_data = tmp_scan_data >> 10;
end
if (ss > 0)
begin
if (m_mode_val[0] != m_mode_val[1])
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for M/M2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
end
end
// cntrs N/N2
tmp_scan_data = scan_data;
for (i=0; i<2; i=i+1)
begin
if (i == 0 || (i == 1 && ss > 0))
begin
error = 0;
n_val[i] = tmp_scan_data[162:154];
if (tmp_scan_data[163] !== 1'b1)
begin
if (tmp_scan_data[162:154] == 9'b000000001)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" N", 2);
else
d_msg = display_msg("N2", 2);
end
else if (tmp_scan_data[162:154] == 9'b000000000)
n_val[i] = 10'b1000000000;
if (error == 1'b0)
begin
if (n_mode_val[i] === "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" N", 1);
else
d_msg = display_msg("N2", 1);
end
n_mode_val[i] = "";
end
end
else if (tmp_scan_data[163] == 1'b1) // bypass
begin
if (tmp_scan_data[154] !== 1'b0)
begin
reconfig_err = 1;
error = 1;
// Cntr value is illegal : give warning
if (i == 0)
d_msg = display_msg(" N", 3);
else
d_msg = display_msg("N2", 3);
end
else begin
if (n_mode_val[i] != "bypass")
begin
// Mode is switched : give warning
if (i == 0)
d_msg = display_msg(" N", 4);
else
d_msg = display_msg("N2", 4);
end
n_val[i] = 10'b0000000001;
n_mode_val[i] = "bypass";
end
end
end
tmp_scan_data = tmp_scan_data >> 10;
end
if (ss > 0)
begin
if (n_mode_val[0] != n_mode_val[1])
begin
reconfig_err = 1;
error = 1;
$display ("Warning : Incompatible modes for N/N2 counters. Either both should be BYASSED or both NON-BYPASSED. Reconfiguration may not work.");
end
end
end
slowest_clk_old = slowest_clk ( c_high_val[0]+c_low_val[0], c_mode_val[0],
c_high_val[1]+c_low_val[1], c_mode_val[1],
c_high_val[2]+c_low_val[2], c_mode_val[2],
c_high_val[3]+c_low_val[3], c_mode_val[3],
c_high_val[4]+c_low_val[4], c_mode_val[4],
c_high_val[5]+c_low_val[5], c_mode_val[5],
refclk_period, m_val[0]);
slowest_clk_new = slowest_clk ( c_high_val_tmp[0]+c_low_val[0], c_mode_val_tmp[0],
c_high_val_tmp[1]+c_low_val[1], c_mode_val_tmp[1],
c_high_val_tmp[2]+c_low_val[2], c_mode_val_tmp[2],
c_high_val_tmp[3]+c_low_val[3], c_mode_val_tmp[3],
c_high_val_tmp[4]+c_low_val[4], c_mode_val_tmp[4],
c_high_val_tmp[5]+c_low_val[5], c_mode_val_tmp[5],
refclk_period, m_val[0]);
quiet_time = (slowest_clk_new > slowest_clk_old) ? slowest_clk_new : slowest_clk_old;
// get quiet time in terms of scanclk cycles
my_rem = quiet_time % scanclk_period;
scanclk_cycles = quiet_time/scanclk_period;
if (my_rem != 0)
scanclk_cycles = scanclk_cycles + 1;
scandone_tmp <= #((scanclk_cycles+0.5) * scanclk_period) 1'b1;
end
scanwrite_last_value = scanwrite_enabled;
end
always @(schedule_vco or areset_ipd or ena_pll)
begin
sched_time = 0;
for (i = 0; i <= 7; i=i+1)
last_phase_shift[i] = phase_shift[i];
cycle_to_adjust = 0;
l_index = 1;
m_times_vco_period = new_m_times_vco_period;
// give appropriate messages
// if areset was asserted
if (areset_ipd === 1'b1 && areset_ipd_last_value !== areset_ipd)
begin
$display (" Note : CycloneII PLL was reset");
$display ("Time: %0t Instance: %m", $time);
// reset lock parameters
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
pll_is_in_reset = 1;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
// areset deasserted : note time
// note it as refclk_time to prevent false triggering
// of stop_vco after areset
if (areset_ipd === 1'b0 && areset_ipd_last_value === 1'b1 && pll_is_in_reset === 1'b1)
begin
refclk_time = $time;
pll_is_in_reset = 0;
if ((ena_pll === 1'b1) && (stop_vco !== 1'b1) && (next_vco_sched_time < $time))
schedule_vco = ~ schedule_vco;
end
// if ena was deasserted
if (ena_pll == 1'b0 && ena_ipd_last_value !== ena_pll)
begin
$display (" Note : CycloneII PLL is disabled");
$display ("Time: %0t Instance: %m", $time);
pll_is_disabled = 1;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
if (ena_pll == 1'b1 && ena_ipd_last_value !== ena_pll)
begin
$display (" Note : CycloneII PLL is enabled");
$display ("Time: %0t Instance: %m", $time);
pll_is_disabled = 0;
if ((areset_ipd !== 1'b1) && (stop_vco !== 1'b1) && (next_vco_sched_time < $time))
schedule_vco = ~ schedule_vco;
end
// illegal value on areset_ipd
if (areset_ipd === 1'bx && (areset_ipd_last_value === 1'b0 || areset_ipd_last_value === 1'b1))
begin
$display("Warning : Illegal value 'X' detected on ARESET input");
$display ("Time: %0t Instance: %m", $time);
end
if (areset_ipd == 1'b1 || ena_pll == 1'b0 || stop_vco == 1'b1)
begin
// reset lock parameters
locked_tmp = 0;
pll_is_locked = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = 0;
got_first_fbclk = 0;
fbclk_time = 0;
first_fbclk_time = 0;
fbclk_period = 0;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
// reset all counter phase tap values to POF programmed values
m_ph_val = m_ph_val_orig;
for (i=0; i<= 5; i=i+1)
c_ph_val[i] = c_ph_val_orig[i];
end
if ( ($time == 0 && first_schedule == 1'b1) || (schedule_vco !== schedule_vco_last_value && (stop_vco !== 1'b1) && (ena_pll === 1'b1) && (areset_ipd !== 1'b1)) )
begin
// calculate loop_xplier : this will be different from m_val in ext. fbk mode
loop_xplier = m_val[0];
loop_initial = i_m_initial - 1;
loop_ph = m_ph_val;
if (op_mode == 1)
begin
if (ext_fbk_cntr_mode == "bypass")
ext_fbk_cntr_modulus = 1;
else
ext_fbk_cntr_modulus = ext_fbk_cntr_high + ext_fbk_cntr_low;
loop_xplier = m_val[0] * (ext_fbk_cntr_modulus);
loop_ph = ext_fbk_cntr_ph;
loop_initial = ext_fbk_cntr_initial - 1 + ((i_m_initial - 1) * ext_fbk_cntr_modulus);
end
// convert initial value to delay
initial_delay = (loop_initial * m_times_vco_period)/loop_xplier;
// convert loop ph_tap to delay
rem = m_times_vco_period % loop_xplier;
vco_per = m_times_vco_period/loop_xplier;
if (rem != 0)
vco_per = vco_per + 1;
fbk_phase = (loop_ph * vco_per)/8;
if (op_mode == 1)
begin
pull_back_M = (i_m_initial - 1) * (ext_fbk_cntr_modulus) * (m_times_vco_period/loop_xplier);
while (pull_back_M > refclk_period)
pull_back_M = pull_back_M - refclk_period;
end
else begin
pull_back_M = initial_delay + fbk_phase;
end
total_pull_back = pull_back_M;
if (l_simulation_type == "timing")
total_pull_back = total_pull_back + pll_compensation_delay;
while (total_pull_back > refclk_period)
total_pull_back = total_pull_back - refclk_period;
if (total_pull_back > 0)
offset = refclk_period - total_pull_back;
else
offset = 0;
if (op_mode == 1)
begin
fbk_delay = pull_back_M;
if (l_simulation_type == "timing")
fbk_delay = fbk_delay + pll_compensation_delay;
end
else begin
fbk_delay = total_pull_back - fbk_phase;
if (fbk_delay < 0)
begin
offset = offset - fbk_phase;
fbk_delay = total_pull_back;
end
end
// assign m_delay
m_delay = fbk_delay;
for (i = 1; i <= loop_xplier; i=i+1)
begin
// adjust cycles
tmp_vco_per = m_times_vco_period/loop_xplier;
if (rem != 0 && l_index <= rem)
begin
tmp_rem = (loop_xplier * l_index) % rem;
cycle_to_adjust = (loop_xplier * l_index) / rem;
if (tmp_rem != 0)
cycle_to_adjust = cycle_to_adjust + 1;
end
if (cycle_to_adjust == i)
begin
tmp_vco_per = tmp_vco_per + 1;
l_index = l_index + 1;
end
// calculate high and low periods
high_time = tmp_vco_per/2;
if (tmp_vco_per % 2 != 0)
high_time = high_time + 1;
low_time = tmp_vco_per - high_time;
// schedule the rising and falling egdes
for (j=0; j<=1; j=j+1)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
// schedule taps with appropriate phase shifts
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
if (first_schedule)
vco_out[k] <= #(sched_time + phase_shift[k]) vco_val;
else
vco_out[k] <= #(sched_time + last_phase_shift[k]) vco_val;
end
end
end
if (first_schedule)
begin
vco_val = ~vco_val;
if (vco_val == 1'b0)
sched_time = sched_time + high_time;
else
sched_time = sched_time + low_time;
for (k = 0; k <= 7; k=k+1)
begin
phase_shift[k] = (k*tmp_vco_per)/8;
vco_out[k] <= #(sched_time+phase_shift[k]) vco_val;
end
first_schedule = 0;
end
schedule_vco <= #(sched_time) ~schedule_vco;
next_vco_sched_time = $time + sched_time;
if (vco_period_was_phase_adjusted)
begin
m_times_vco_period = refclk_period;
new_m_times_vco_period = refclk_period;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 1;
tmp_vco_per = m_times_vco_period/loop_xplier;
for (k = 0; k <= 7; k=k+1)
phase_shift[k] = (k*tmp_vco_per)/8;
end
end
areset_ipd_last_value = areset_ipd;
ena_ipd_last_value = ena_pll;
schedule_vco_last_value = schedule_vco;
end
always @(pfdena_ipd)
begin
if (pfdena_ipd === 1'b0)
begin
if (pll_is_locked)
locked_tmp = 1'bx;
pll_is_locked = 0;
cycles_to_lock = 0;
$display (" Note : CycloneII PFDENA was deasserted");
$display ("Time: %0t Instance: %m", $time);
end
else if (pfdena_ipd === 1'b1 && pfdena_ipd_last_value === 1'b0)
begin
// PFD was disabled, now enabled again
got_first_refclk = 0;
got_second_refclk = 0;
refclk_time = $time;
end
pfdena_ipd_last_value = pfdena_ipd;
end
always @(negedge refclk or negedge fbclk)
begin
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
always @(posedge refclk or posedge fbclk)
begin
if (refclk == 1'b1 && refclk_last_value !== refclk && areset_ipd === 1'b0)
begin
if (! got_first_refclk)
begin
got_first_refclk = 1;
end else
begin
got_second_refclk = 1;
refclk_period = $time - refclk_time;
// check if incoming freq. will cause VCO range to be
// exceeded
if ((vco_max != 0 && vco_min != 0) && (pfdena_ipd === 1'b1) &&
((refclk_period/loop_xplier > vco_max) ||
(refclk_period/loop_xplier < vco_min)) )
begin
if (pll_is_locked == 1'b1)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may lose lock");
$display ("Time: %0t Instance: %m", $time);
if (inclk_out_of_range === 1'b1)
begin
// unlock
pll_is_locked = 0;
locked_tmp = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : CycloneII PLL lost lock");
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
else begin
if (no_warn == 1'b0)
begin
$display ("Warning : Input clock freq. is not within VCO range. PLL may not lock");
$display ("Time: %0t Instance: %m", $time);
no_warn = 1'b1;
end
end
inclk_out_of_range = 1;
end
else begin
inclk_out_of_range = 0;
end
end
if (stop_vco == 1'b1)
begin
stop_vco = 0;
schedule_vco = ~schedule_vco;
end
refclk_time = $time;
end
if (fbclk == 1'b1 && fbclk_last_value !== fbclk)
begin
if (scanwrite_enabled === 1'b1)
begin
m_val[0] <= m_val_tmp[0];
m_val[1] <= m_val_tmp[1];
end
if (!got_first_fbclk)
begin
got_first_fbclk = 1;
first_fbclk_time = $time;
end
else
fbclk_period = $time - fbclk_time;
// need refclk_period here, so initialized to proper value above
if ( ( ($time - refclk_time > 1.5 * refclk_period) && pfdena_ipd === 1'b1 && pll_is_locked === 1'b1) || ( ($time - refclk_time > 5 * refclk_period) && pfdena_ipd === 1'b1) )
begin
stop_vco = 1;
// reset
got_first_refclk = 0;
got_first_fbclk = 0;
got_second_refclk = 0;
if (pll_is_locked == 1'b1)
begin
pll_is_locked = 0;
locked_tmp = 0;
$display ("Note : CycloneII PLL lost lock due to loss of input clock");
$display ("Time: %0t Instance: %m", $time);
end
pll_about_to_lock = 0;
cycles_to_lock = 0;
cycles_to_unlock = 0;
first_schedule = 1;
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
tap0_is_active = 0;
for (x = 0; x <= 7; x=x+1)
vco_tap[x] <= 1'b0;
end
fbclk_time = $time;
end
if (got_second_refclk && pfdena_ipd === 1'b1 && (!inclk_out_of_range))
begin
// now we know actual incoming period
if (abs(fbclk_time - refclk_time) <= 5 || (got_first_fbclk && abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
// considered in phase
if (cycles_to_lock == valid_lock_multiplier - 1)
pll_about_to_lock <= 1;
if (cycles_to_lock == valid_lock_multiplier)
begin
if (pll_is_locked === 1'b0)
begin
$display (" Note : CycloneII PLL locked to incoming clock");
$display ("Time: %0t Instance: %m", $time);
end
pll_is_locked = 1;
locked_tmp = 1;
cycles_to_unlock = 0;
end
// increment lock counter only if the second part of the above
// time check is not true
if (!(abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5))
begin
cycles_to_lock = cycles_to_lock + 1;
end
// adjust m_times_vco_period
new_m_times_vco_period = refclk_period;
end else
begin
// if locked, begin unlock
if (pll_is_locked)
begin
cycles_to_unlock = cycles_to_unlock + 1;
if (cycles_to_unlock == invalid_lock_multiplier)
begin
pll_is_locked = 0;
locked_tmp = 0;
pll_about_to_lock = 0;
cycles_to_lock = 0;
$display ("Note : CycloneII PLL lost lock");
$display ("Time: %0t Instance: %m", $time);
vco_period_was_phase_adjusted = 0;
phase_adjust_was_scheduled = 0;
end
end
if (abs(refclk_period - fbclk_period) <= 2)
begin
// frequency is still good
if ($time == fbclk_time && (!phase_adjust_was_scheduled))
begin
if (abs(fbclk_time - refclk_time) > refclk_period/2)
begin
new_m_times_vco_period = m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted = 1;
end else
begin
new_m_times_vco_period = m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted = 1;
end
end
end else
begin
new_m_times_vco_period = refclk_period;
phase_adjust_was_scheduled = 0;
end
end
end
if (reconfig_err == 1'b1)
begin
locked_tmp = 0;
end
refclk_last_value = refclk;
fbclk_last_value = fbclk;
end
assign clk_tmp[0] = i_clk0_counter == "c0" ? c0_clk : i_clk0_counter == "c1" ? c1_clk : i_clk0_counter == "c2" ? c2_clk : i_clk0_counter == "c3" ? c3_clk : i_clk0_counter == "c4" ? c4_clk : i_clk0_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[1] = i_clk1_counter == "c0" ? c0_clk : i_clk1_counter == "c1" ? c1_clk : i_clk1_counter == "c2" ? c2_clk : i_clk1_counter == "c3" ? c3_clk : i_clk1_counter == "c4" ? c4_clk : i_clk1_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[2] = i_clk2_counter == "c0" ? c0_clk : i_clk2_counter == "c1" ? c1_clk : i_clk2_counter == "c2" ? c2_clk : i_clk2_counter == "c3" ? c3_clk : i_clk2_counter == "c4" ? c4_clk : i_clk2_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[3] = i_clk3_counter == "c0" ? c0_clk : i_clk3_counter == "c1" ? c1_clk : i_clk3_counter == "c2" ? c2_clk : i_clk3_counter == "c3" ? c3_clk : i_clk3_counter == "c4" ? c4_clk : i_clk3_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[4] = i_clk4_counter == "c0" ? c0_clk : i_clk4_counter == "c1" ? c1_clk : i_clk4_counter == "c2" ? c2_clk : i_clk4_counter == "c3" ? c3_clk : i_clk4_counter == "c4" ? c4_clk : i_clk4_counter == "c5" ? c5_clk : 'b0;
assign clk_tmp[5] = i_clk5_counter == "c0" ? c0_clk : i_clk5_counter == "c1" ? c1_clk : i_clk5_counter == "c2" ? c2_clk : i_clk5_counter == "c3" ? c3_clk : i_clk5_counter == "c4" ? c4_clk : i_clk5_counter == "c5" ? c5_clk : 'b0;
assign clk_out[0] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[0] : 'bx;
assign clk_out[1] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[1] : 'bx;
assign clk_out[2] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[2] : 'bx;
assign clk_out[3] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[3] : 'bx;
assign clk_out[4] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[4] : 'bx;
assign clk_out[5] = (areset_ipd === 1'b1 || ena_pll === 1'b0 || pll_in_test_mode === 1'b1) || (pll_about_to_lock == 1'b1 && !reconfig_err) ? clk_tmp[5] : 'bx;
assign sbdout_tmp = sbdin_ipd;
// ACCELERATE OUTPUTS
and (clk[0], 1'b1, clk_out[0]);
and (clk[1], 1'b1, clk_out[1]);
and (clk[2], 1'b1, clk_out[2]);
and (sbdout, 1'b1, sbdout_tmp);
endmodule // cycloneii_pll
//------------------------------------------------------------------
//
// Module Name : cycloneii_routing_wire
//
// Description : Simulation model for a simple routing wire
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_routing_wire (
datain,
dataout
);
// INPUT PORTS
input datain;
// OUTPUT PORTS
output dataout;
// INTERNAL VARIABLES
wire dataout_tmp;
specify
(datain => dataout) = (0, 0) ;
endspecify
assign dataout_tmp = datain;
and (dataout, dataout_tmp, 1'b1);
endmodule // cycloneii_routing_wire
//------------------------------------------------------------------
//
// Module Name : cycloneii_lcell_ff
//
// Description : Cyclone II LCELL_FF Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_lcell_ff (
datain,
clk,
aclr,
sclr,
sload,
sdata,
ena,
devclrn,
devpor,
regout
);
parameter x_on_violation = "on";
parameter lpm_type = "cycloneii_lcell_ff";
input datain;
input clk;
input aclr;
input sclr;
input sload;
input sdata;
input ena;
input devclrn;
input devpor;
output regout;
reg regout_tmp;
wire reset;
reg datain_viol;
reg sclr_viol;
reg sload_viol;
reg sdata_viol;
reg ena_viol;
reg violation;
reg clk_last_value;
reg ix_on_violation;
wire datain_in;
wire clk_in;
wire aclr_in;
wire sclr_in;
wire sload_in;
wire sdata_in;
wire ena_in;
wire nosloadsclr;
wire sloaddata;
buf (datain_in, datain);
buf (clk_in, clk);
buf (aclr_in, aclr);
buf (sclr_in, sclr);
buf (sload_in, sload);
buf (sdata_in, sdata);
buf (ena_in, ena);
assign reset = devpor && devclrn && (!aclr_in) && (ena_in);
assign nosloadsclr = reset && (!sload_in && !sclr_in);
assign sloaddata = reset && sload_in;
specify
$setuphold (posedge clk &&& nosloadsclr, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& sloaddata, sdata, 0, 0, sdata_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: regout_tmp)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
endspecify
initial
begin
violation = 'b0;
clk_last_value = 'b0;
regout_tmp = 'b0;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (datain_viol or sclr_viol or sload_viol or ena_viol or sdata_viol)
begin
if (ix_on_violation == 1)
violation = 'b1;
end
always @ (sdata_in or aclr_in or devclrn or devpor)
begin
if (devpor == 'b0)
regout_tmp <= 'b0;
else if (devclrn == 'b0)
regout_tmp <= 'b0;
else if (aclr_in == 'b1)
regout_tmp <= 'b0;
end
always @ (clk_in or posedge aclr_in or
devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 'b0;
regout_tmp <= 'bX;
end
else
begin
if (devpor == 'b0 || devclrn == 'b0 || aclr_in === 'b1)
regout_tmp <= 'b0;
else if (ena_in === 'b1 && clk_in === 'b1 && clk_last_value === 'b0)
begin
if (sclr_in === 'b1)
regout_tmp <= 'b0 ;
else if (sload_in === 'b1)
regout_tmp <= sdata_in;
else
regout_tmp <= datain_in;
end
end
clk_last_value = clk_in;
end
and (regout, regout_tmp, 'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_lcell_comb
//
// Description : Cyclone II LCELL_COMB Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_lcell_comb (
dataa,
datab,
datac,
datad,
cin,
combout,
cout
);
input dataa;
input datab;
input datac;
input datad;
input cin;
output combout;
output cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter lpm_type = "cycloneii_lcell_comb";
reg cout_tmp;
reg combout_tmp;
reg [1:0] isum_lutc_input;
wire dataa_in;
wire datab_in;
wire datac_in;
wire datad_in;
wire cin_in;
buf (dataa_in, dataa);
buf (datab_in, datab);
buf (datac_in, datac);
buf (datad_in, datad);
buf (cin_in, cin);
specify
(dataa => combout) = (0, 0) ;
(datab => combout) = (0, 0) ;
(datac => combout) = (0, 0) ;
(datad => combout) = (0, 0) ;
(cin => combout) = (0, 0) ;
(dataa => cout) = (0, 0);
(datab => cout) = (0, 0);
(cin => cout) = (0, 0) ;
endspecify
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa;
input datab;
input datac;
input datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
begin
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else
begin
$display ("Error: Invalid sum_lutc_input specified\n");
isum_lutc_input = 2;
end
end
always @(datad_in or datac_in or datab_in or dataa_in or cin_in)
begin
if (isum_lutc_input == 0) // datac
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
datac_in, datad_in);
cout_tmp = lut4(lut_mask, dataa_in, datab_in, datac_in, 'b0);
end
else if (isum_lutc_input == 1) // cin
begin
combout_tmp = lut4(lut_mask, dataa_in, datab_in,
cin_in, datad_in);
cout_tmp = lut4(lut_mask, dataa_in, datab_in, cin_in, 'b0);
end
end
and (combout, combout_tmp, 1'b1) ;
and (cout, cout_tmp, 1'b1) ;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// CYCLONEII ASYNCH IO Atom
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneii_asynch_io (datain, oe, regin,
differentialin, differentialout,
padio, combout, regout);
input datain, oe;
input regin;
input differentialin;
output differentialout;
output combout;
output regout;
inout padio;
parameter operation_mode = "input";
parameter bus_hold = "false";
parameter open_drain_output = "false";
parameter use_differential_input = "false";
reg prev_value;
reg tmp_padio, tmp_combout;
reg buf_control;
wire differentialout_tmp;
wire tmp_combout_differentialin_or_pad;
wire datain_in;
wire differentialin_in;
wire oe_in;
buf(differentialin_in, differentialin);
buf(oe_in, oe);
buf(datain_in, datain);
tri padio_tmp;
specify
(padio => differentialout) = (0,0);
(differentialin => combout) = (0,0);
(padio => combout) = (0,0);
(datain => padio) = (0, 0);
(posedge oe => (padio +: padio_tmp)) = (0, 0);
(negedge oe => (padio +: 1'bz)) = (0, 0);
(regin => regout) = (0, 0);
endspecify
initial
begin
prev_value = 'b0;
tmp_padio = 'bz;
end
always @(datain_in or oe_in or padio)
begin
if (bus_hold == "true" )
begin
buf_control = 'b1;
if ( operation_mode == "input")
begin
if (padio === 1'bz)
tmp_combout = prev_value;
else
begin
prev_value = padio;
tmp_combout = padio;
end
tmp_padio = 1'bz;
end
else
begin
if ( operation_mode == "output" || operation_mode == "bidir")
begin
if ( oe_in == 1)
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 1'b0)
begin
tmp_padio = 1'b0;
prev_value = 1'b0;
end
else if (datain_in === 1'bx)
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
else // output of tri is 'Z'
begin
if ( operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
end
else // open drain_output = false;
begin
tmp_padio = datain_in;
prev_value = datain_in;
end
end
else if ( oe_in == 0 )
begin
if (operation_mode == "bidir")
prev_value = padio;
tmp_padio = 1'bz;
end
else // oe == 'X'
begin
tmp_padio = 1'bx;
prev_value = 1'bx;
end
end // bidir or output
if ( operation_mode == "output")
tmp_combout = 1'bz;
else
tmp_combout = padio;
end
end
else // bus hold is false
begin
buf_control = 'b0;
if ( operation_mode == "input")
begin
tmp_combout = padio;
end
else if (operation_mode == "output" || operation_mode == "bidir")
begin
if ( operation_mode == "bidir")
tmp_combout = padio;
if ( oe_in == 1 )
begin
if ( open_drain_output == "true" )
begin
if (datain_in == 0)
tmp_padio = 1'b0;
else if ( datain_in === 1'bx)
tmp_padio = 1'bx;
else
tmp_padio = 1'bz;
end
else
tmp_padio = datain_in;
end
else if ( oe_in == 0 )
tmp_padio = 1'bz;
else
tmp_padio = 1'bx;
end
else
$display ("Error: Invalid operation_mode specified in cycloneii io atom!\n");
end
end
assign differentialout_tmp = (operation_mode == "input" || operation_mode == "bidir") ? padio : 1'bx;
assign tmp_combout_differentialin_or_pad = (use_differential_input == "true") ? differentialin_in : tmp_combout;
bufif1 (weak1, weak0) b(padio_tmp, prev_value, buf_control); //weak value
pmos (padio_tmp, tmp_padio, 'b0);
pmos (combout, tmp_combout_differentialin_or_pad, 'b0);
pmos (padio, padio_tmp, 'b0);
and (regout, regin, 1'b1);
pmos (differentialout, differentialout_tmp, 'b0);
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// CYCLONEII IO Atom
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module cycloneii_io (datain, oe, outclk, outclkena, inclk, inclkena, areset, sreset,
devclrn, devpor, devoe, linkin,
differentialin, differentialout,
padio, combout, regout, linkout);
parameter operation_mode = "input";
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter output_register_mode = "none";
parameter output_async_reset = "none";
parameter output_sync_reset = "none";
parameter output_power_up = "low";
parameter tie_off_output_clock_enable = "false";
parameter oe_register_mode = "none";
parameter oe_async_reset = "none";
parameter oe_sync_reset = "none";
parameter oe_power_up = "low";
parameter tie_off_oe_clock_enable = "false";
parameter input_register_mode = "none";
parameter input_async_reset = "none";
parameter input_sync_reset = "none";
parameter input_power_up = "low";
parameter lpm_type = "cycloneii_io";
parameter use_differential_input = "false";
inout padio;
input datain, oe;
input outclk, outclkena, inclk, inclkena, areset, sreset;
input devclrn, devpor, devoe;
input linkin;
input differentialin;
output differentialout;
output combout, regout;
output linkout;
wire out_reg_clk_ena, oe_reg_clk_ena;
wire tmp_oe_reg_out, tmp_input_reg_out, tmp_output_reg_out;
wire inreg_sreset_is_used, outreg_sreset_is_used, oereg_sreset_is_used;
wire inreg_sreset, outreg_sreset, oereg_sreset;
wire in_reg_aclr, in_reg_apreset;
wire oe_reg_aclr, oe_reg_apreset, oe_reg_sel;
wire out_reg_aclr, out_reg_apreset, out_reg_sel;
wire input_reg_pu_low, output_reg_pu_low, oe_reg_pu_low;
wire inreg_D, outreg_D, oereg_D;
wire tmp_datain, tmp_oe;
wire iareset, isreset;
wire pad_or_differentialin;
assign pad_or_differentialin = (use_differential_input == "true") ? differentialin : padio;
assign input_reg_pu_low = ( input_power_up == "low") ? 'b0 : 'b1;
assign output_reg_pu_low = ( output_power_up == "low") ? 'b0 : 'b1;
assign oe_reg_pu_low = ( oe_power_up == "low") ? 'b0 : 'b1;
assign out_reg_sel = (output_register_mode == "register" ) ? 'b1 : 'b0;
assign oe_reg_sel = ( oe_register_mode == "register" ) ? 'b1 : 'b0;
assign iareset = ( areset === 'b0 || areset === 'b1 ) ? !areset : 'b1;
assign isreset = ( sreset === 'b0 || sreset === 'b1 ) ? sreset : 'b0;
// output register signals
assign out_reg_aclr = (output_async_reset == "clear") ? iareset : 'b1;
assign out_reg_apreset = ( output_async_reset == "preset") ? iareset : 'b1;
assign outreg_sreset_is_used = ( output_sync_reset == "none") ? 'b0 : 'b1;
assign outreg_sreset = (output_sync_reset == "clear") ? 'b0 : 'b1;
// oe register signals
assign oe_reg_aclr = ( oe_async_reset == "clear") ? iareset : 'b1;
assign oe_reg_apreset = ( oe_async_reset == "preset") ? iareset : 'b1;
assign oereg_sreset_is_used = ( oe_sync_reset == "none") ? 'b0 : 'b1;
assign oereg_sreset = (oe_sync_reset == "clear") ? 'b0 : 'b1;
// input register signals
assign in_reg_aclr = ( input_async_reset == "clear") ? iareset : 'b1;
assign in_reg_apreset = ( input_async_reset == "preset") ? iareset : 'b1;
assign inreg_sreset_is_used = ( input_sync_reset == "none") ? 'b0 : 'b1;
assign inreg_sreset = (input_sync_reset == "clear") ? 'b0 : 'b1;
// oe and output register clock enable signals
assign out_reg_clk_ena = ( tie_off_output_clock_enable == "true") ? 'b1 : outclkena;
assign oe_reg_clk_ena = ( tie_off_oe_clock_enable == "true") ? 'b1 : outclkena;
// input reg
cycloneii_mux21 inreg_D_mux (.MO (inreg_D),
.A (pad_or_differentialin),
.B (inreg_sreset),
.S (isreset && inreg_sreset_is_used));
cycloneii_dffe input_reg (.Q (tmp_input_reg_out),
.CLK (inclk),
.ENA (inclkena),
.D (inreg_D),
.CLRN (in_reg_aclr && devclrn && (input_reg_pu_low || devpor)),
.PRN (in_reg_apreset && (!input_reg_pu_low || devpor)));
//output reg
cycloneii_mux21 outreg_D_mux (.MO (outreg_D),
.A (datain),
.B (outreg_sreset),
.S (isreset && outreg_sreset_is_used));
cycloneii_dffe output_reg (.Q (tmp_output_reg_out),
.CLK (outclk),
.ENA (out_reg_clk_ena),
.D (outreg_D),
.CLRN (out_reg_aclr && devclrn && (output_reg_pu_low || devpor)),
.PRN (out_reg_apreset && (!output_reg_pu_low || devpor)));
//oe reg
cycloneii_mux21 oereg_D_mux (.MO (oereg_D),
.A (oe),
.B (oereg_sreset),
.S (isreset && oereg_sreset_is_used));
cycloneii_dffe oe_reg (.Q (tmp_oe_reg_out),
.CLK (outclk),
.ENA (oe_reg_clk_ena),
.D (oereg_D),
.CLRN (oe_reg_aclr && devclrn && (oe_reg_pu_low || devpor)),
.PRN (oe_reg_apreset && (!oe_reg_pu_low || devpor)));
// asynchronous block
assign tmp_oe = (oe_reg_sel == 'b1) ? tmp_oe_reg_out : oe;
assign tmp_datain = ((operation_mode == "output" || operation_mode == "bidir") && out_reg_sel == 'b1 ) ? tmp_output_reg_out : datain;
cycloneii_asynch_io asynch_inst(.datain(tmp_datain),
.oe(tmp_oe),
.regin(tmp_input_reg_out),
.differentialin(differentialin),
.differentialout(differentialout),
.padio(padio),
.combout(combout),
.regout(regout));
defparam asynch_inst.operation_mode = operation_mode;
defparam asynch_inst.bus_hold = bus_hold;
defparam asynch_inst.open_drain_output = open_drain_output;
defparam asynch_inst.use_differential_input = use_differential_input;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_clk_delay_ctrl
//
// Description : Cycloneii CLK DELAY CTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clk_delay_ctrl (
clk,
delayctrlin,
disablecalibration,
pllcalibrateclkdelayedin,
devpor,
devclrn,
clkout
);
input clk;
input [5:0] delayctrlin;
input disablecalibration;
input pllcalibrateclkdelayedin;
input devpor;
input devclrn;
output clkout;
parameter behavioral_sim_delay = 0;
parameter delay_chain = "54"; // or "1362ps"
parameter delay_chain_mode = "static";
parameter uses_calibration = "false";
parameter use_new_style_dq_detection = "false";
parameter tan_delay_under_delay_ctrl_signal = "unused";
parameter delay_ctrl_sim_delay_15_0 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_31_16 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_47_32 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_63_48 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter lpm_type = "cycloneii_clk_delay_ctrl";
// BUFFERED BUS INPUTS
wire [5:0] delayctrl_in;
// TMP OUTPUTS
wire clk_out_w;
wire clk_after_calib_mux_w;
reg clk_after_dly_chain_r;
integer dqs_dynamic_dly_index_i;
integer dqs_dynamic_dly_i;
// Dynamic Delay Table
reg [31:0] dly_table_r [0:63];
reg [2047:0] delay_ctrl_sim_delay_all_r;
reg [31:0] a_val_r;
integer i;
integer j;
// FUNCTIONS
// INTERNAL NETS AND VARIABLES
// TIMING HOOKS
wire clk_in;
wire delayctrl_in5;
wire delayctrl_in4;
wire delayctrl_in3;
wire delayctrl_in2;
wire delayctrl_in1;
wire delayctrl_in0;
wire disablecalibration_in;
wire pllcalibrateclkdelayed_in;
buf (clk_in, clk);
buf (delayctrl_in5, delayctrlin[5]);
buf (delayctrl_in4, delayctrlin[4]);
buf (delayctrl_in3, delayctrlin[3]);
buf (delayctrl_in2, delayctrlin[2]);
buf (delayctrl_in1, delayctrlin[1]);
buf (delayctrl_in0, delayctrlin[0]);
buf (disablecalibration_in, disablecalibration);
buf (pllcalibrateclkdelayed_in, pllcalibrateclkdelayedin);
assign delayctrl_in = {delayctrl_in5, delayctrl_in4, delayctrl_in3,
delayctrl_in2,delayctrl_in1,delayctrl_in0};
specify
(clk => clkout) = (0,0);
(disablecalibration => clkout) = (0,0);
(pllcalibrateclkdelayedin => clkout) = (0,0);
endspecify
// MODEL
initial
begin
delay_ctrl_sim_delay_all_r = {delay_ctrl_sim_delay_63_48, delay_ctrl_sim_delay_47_32, delay_ctrl_sim_delay_31_16, delay_ctrl_sim_delay_15_0};
// dly_table_r = delay_ctrl_sim_delay_all_r;
for (i=0; i<64; i=i+1)
begin
// dly_table_r[i] = delay_ctrl_sim_delay_all_r[32*i+31 : 32*i];
for (j=0; j<32; j=j+1)
a_val_r[j] = delay_ctrl_sim_delay_all_r[32*i+j];
dly_table_r[i] = a_val_r;
end
`ifdef CYCLONEII_CLK_DELAY_CTRL_DEBUG
$display("DEBUG: CLK_DELAY_CTRL instance %m has dynamic delay table ...");
for (i=0; i<64; i=i+1)
$display("%0d", dly_table_r[i]);
`endif
end
// generate dynamic delay value
initial
begin
dqs_dynamic_dly_index_i = 0;
dqs_dynamic_dly_i = 0;
end
always @(delayctrl_in)
begin
dqs_dynamic_dly_index_i = delayctrl_in;
if (dqs_dynamic_dly_index_i >= 0 && dqs_dynamic_dly_index_i < 64)
dqs_dynamic_dly_i = dly_table_r[dqs_dynamic_dly_index_i];
end
// generating post delay chain clock
always @(clk_in)
begin
if (delay_chain_mode == "dynamic")
clk_after_dly_chain_r <= #(dqs_dynamic_dly_i) clk_in;
else if (delay_chain_mode == "static")
clk_after_dly_chain_r <= #(behavioral_sim_delay) clk_in;
end
// generating post calib mux clock
assign clk_after_calib_mux_w = (uses_calibration == "true" && disablecalibration_in === 1'b0) ?
pllcalibrateclkdelayed_in : clk_after_dly_chain_r;
// final clock
assign clk_out_w = (delay_chain_mode == "none") ? clk_in : clk_after_calib_mux_w;
and (clkout, clk_out_w, 1'b1);
endmodule
//-----------------------------------------------------------------------------
//
// Module Name : cycloneii_clk_delay_cal_ctrl
//
// Description : Cycloneii CLK DELAY CALIBRATION CTRL Verilog simulation model
//
//-----------------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clk_delay_cal_ctrl(
pllcalibrateclk, plldataclk, delayctrlin, disablecalibration,
devclrn, devpor,
calibratedata, pllcalibrateclkdelayedout);
input pllcalibrateclk;
input plldataclk;
input [5:0] delayctrlin;
input disablecalibration;
input devclrn;
input devpor;
output calibratedata;
output pllcalibrateclkdelayedout;
parameter delay_ctrl_sim_delay_15_0 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_31_16 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_47_32 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter delay_ctrl_sim_delay_63_48 = 512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter lpm_type = "cycloneii_clk_delay_cal_ctrl";
// BUFFERED BUS INPUTS
wire [5:0] delayctrl_in;
// TIMING HOOKS
wire plldataclk_in;
wire pllcalibrateclk_in;
wire delayctrl_in5;
wire delayctrl_in4;
wire delayctrl_in3;
wire delayctrl_in2;
wire delayctrl_in1;
wire delayctrl_in0;
wire disablecalibration_in;
buf (plldataclk_in, plldataclk);
buf (pllcalibrateclk_in, pllcalibrateclk);
buf (delayctrl_in5, delayctrlin[5]);
buf (delayctrl_in4, delayctrlin[4]);
buf (delayctrl_in3, delayctrlin[3]);
buf (delayctrl_in2, delayctrlin[2]);
buf (delayctrl_in1, delayctrlin[1]);
buf (delayctrl_in0, delayctrlin[0]);
buf (disablecalibration_in, disablecalibration);
// TMP OUTPUTS
wire cal_clk_out_w;
wire cal_data_out_w;
reg clk_after_dly_chain_r;
reg cal_clk_by2_r;
reg cal_data_by2_r;
reg cal_clk_prev;
reg cal_data_prev;
integer dqs_dynamic_dly_index_i;
integer dqs_dynamic_dly_i;
// Dynamic Delay Table
reg [31:0] dly_table_r [0:63];
reg [2047:0] delay_ctrl_sim_delay_all_r;
reg [31:0] a_val_r;
integer i;
integer j;
// FUNCTIONS
// INTERNAL NETS AND VARIABLES
assign delayctrl_in = {delayctrl_in5, delayctrl_in4, delayctrl_in3,
delayctrl_in2,delayctrl_in1,delayctrl_in0};
specify
(plldataclk => calibratedata) = (0,0);
(disablecalibration => calibratedata) = (0,0);
(pllcalibrateclk => pllcalibrateclkdelayedout) = (0,0);
(disablecalibration => pllcalibrateclkdelayedout) = (0,0);
endspecify
// MODEL
initial
begin
delay_ctrl_sim_delay_all_r = {delay_ctrl_sim_delay_63_48, delay_ctrl_sim_delay_47_32, delay_ctrl_sim_delay_31_16, delay_ctrl_sim_delay_15_0};
for (i=0; i<64; i=i+1)
begin
for (j=0; j<32; j=j+1)
a_val_r[j] = delay_ctrl_sim_delay_all_r[32*i+j];
dly_table_r[i] = a_val_r;
end
`ifdef CYCLONEII_CLK_DELAY_CTRL_DEBUG
$display("DEBUG: CLK_DELAY_CAL_CTRL instance %m has dynamic delay table ...");
for (i=0; i<64; i=i+1)
$display("%0d", dly_table_r[i]);
`endif
end
// generate dynamic delay value
initial
begin
dqs_dynamic_dly_index_i = 0;
dqs_dynamic_dly_i = 0;
end
always @(delayctrl_in)
begin
dqs_dynamic_dly_index_i = delayctrl_in;
if (dqs_dynamic_dly_index_i >= 0 && dqs_dynamic_dly_index_i < 64)
dqs_dynamic_dly_i = dly_table_r[dqs_dynamic_dly_index_i];
end
// generate divided by 2 clocks
initial
begin
cal_clk_by2_r = 1'b0;
end
always @(pllcalibrateclk_in or posedge disablecalibration_in or negedge devclrn or negedge devpor)
begin
if (disablecalibration_in === 1'b1 || devclrn === 1'b0 || devpor === 1'b0)
begin
cal_clk_prev <= 1'bx;
cal_clk_by2_r <= 1'b0;
end
else
begin
cal_clk_prev <= pllcalibrateclk_in;
if (pllcalibrateclk_in === 1'b1 && cal_clk_prev === 1'b0)
cal_clk_by2_r <= ~cal_clk_by2_r;
end
end
initial
begin
cal_data_by2_r = 1'b0;
end
always @(plldataclk_in or posedge disablecalibration_in or negedge devclrn or negedge devpor)
begin
if (disablecalibration_in === 1'b1 || devclrn === 1'b0 || devpor === 1'b0)
begin
cal_data_prev <= 1'bx;
cal_data_by2_r <= 1'b0;
end
else
begin
cal_data_prev <= plldataclk_in;
if (plldataclk_in === 1'b1 && cal_data_prev === 1'b0)
cal_data_by2_r <= ~cal_data_by2_r;
end
end
// generating post delay chain clock
always @(cal_clk_by2_r)
begin
clk_after_dly_chain_r <= #(dqs_dynamic_dly_i) cal_clk_by2_r;
end
// final clocks
assign cal_clk_out_w = clk_after_dly_chain_r;
assign cal_data_out_w = cal_data_by2_r;
and (calibratedata, cal_data_out_w, 1'b1);
and (pllcalibrateclkdelayedout, cal_clk_out_w, 1'b1);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_ena_reg
//
// Description : Simulation model for a simple DFF.
// This is used for the gated clock generation.
// Powers upto 1.
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_ena_reg (
clk,
ena,
d,
clrn,
prn,
q
);
// INPUT PORTS
input d;
input clk;
input clrn;
input prn;
input ena;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg q_tmp;
reg violation;
reg d_viol;
wire reset;
// DEFAULT VALUES THRO' PULLUPs
tri1 prn, clrn, ena;
wire d_in;
wire clk_in;
buf (d_in, d);
buf (clk_in, clk);
assign reset = (!clrn) && (ena);
specify
$setuphold (posedge clk &&& reset, d, 0, 0, d_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
endspecify
initial
begin
q_tmp = 'b1;
violation = 'b0;
end
always @ (posedge clk_in or negedge clrn or negedge prn )
begin
if (d_viol == 1'b1)
begin
violation = 1'b0;
q_tmp <= 'bX;
end
else
if (prn == 1'b0)
q_tmp <= 1;
else if (clrn == 1'b0)
q_tmp <= 0;
else if ((clk_in == 1'b1) & (ena == 1'b1))
q_tmp <= d_in;
end
and (q, q_tmp, 'b1);
endmodule // cycloneii_ena_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_clkctrl
//
// Description : Cycloneii CLKCTRL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_clkctrl (
inclk,
clkselect,
ena,
devpor,
devclrn,
outclk
);
input [3:0] inclk;
input [1:0] clkselect;
input ena;
input devpor;
input devclrn;
output outclk;
parameter clock_type = "auto";
parameter ena_register_mode = "falling edge";
parameter lpm_type = "cycloneii_clkctrl";
wire clkmux_out; // output of CLK mux
wire cereg_out; // output of ENA register
wire ena_out; // choice of registered ENA or none.
wire inclk3_ipd;
wire inclk2_ipd;
wire inclk1_ipd;
wire inclk0_ipd;
wire clkselect1_ipd;
wire clkselect0_ipd;
wire ena_ipd;
buf (inclk3_ipd, inclk[3]);
buf (inclk2_ipd, inclk[2]);
buf (inclk1_ipd, inclk[1]);
buf (inclk0_ipd, inclk[0]);
buf (clkselect1_ipd, clkselect[1]);
buf (clkselect0_ipd, clkselect[0]);
buf (ena_ipd, ena);
cycloneii_mux41 clk_mux (.MO(clkmux_out),
.IN0(inclk0_ipd),
.IN1(inclk1_ipd),
.IN2(inclk2_ipd),
.IN3(inclk3_ipd),
.S({clkselect1_ipd, clkselect0_ipd}));
cycloneii_ena_reg extena0_reg(
.clk(!clkmux_out),
.ena(1'b1),
.d(ena_ipd),
.clrn(1'b1),
.prn(devpor),
.q(cereg_out)
);
assign ena_out = (ena_register_mode == "falling edge") ? cereg_out : ena_ipd;
and (outclk, ena_out, clkmux_out);
endmodule
//---------------------------------------------------------------------
//
// Module Name : cycloneii_mac_data_reg
//
// Description : Simulation model for the data input register of
// Cyclone II MAC_MULT
//
//---------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_data_reg (clk,
data,
ena,
aclr,
dataout
);
parameter data_width = 18;
// INPUT PORTS
input clk;
input [17 : 0] data;
input ena;
input aclr;
// OUTPUT PORTS
output [17:0] dataout;
// INTERNAL VARIABLES AND NETS
reg clk_last_value;
reg [17:0] dataout_tmp;
wire [17:0] dataout_wire;
// INTERNAL VARIABLES
wire [17:0] data_ipd;
wire enable;
wire no_clr;
reg d_viol;
reg ena_viol;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
// BUFFER INPUTS
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
buf (data_ipd[0], data[0]);
buf (data_ipd[1], data[1]);
buf (data_ipd[2], data[2]);
buf (data_ipd[3], data[3]);
buf (data_ipd[4], data[4]);
buf (data_ipd[5], data[5]);
buf (data_ipd[6], data[6]);
buf (data_ipd[7], data[7]);
buf (data_ipd[8], data[8]);
buf (data_ipd[9], data[9]);
buf (data_ipd[10], data[10]);
buf (data_ipd[11], data[11]);
buf (data_ipd[12], data[12]);
buf (data_ipd[13], data[13]);
buf (data_ipd[14], data[14]);
buf (data_ipd[15], data[15]);
buf (data_ipd[16], data[16]);
buf (data_ipd[17], data[17]);
assign enable = (!aclr_ipd) && (ena_ipd);
assign no_clr = (!aclr_ipd);
// TIMING PATHS
specify
$setuphold (posedge clk &&& enable, data, 0, 0, d_viol);
$setuphold (posedge clk &&& no_clr, ena, 0, 0, ena_viol);
(posedge clk => (dataout +: dataout_tmp)) = (0, 0);
(posedge aclr => (dataout +: 1'b0)) = (0, 0);
endspecify
initial
begin
clk_last_value <= 'b0;
dataout_tmp <= 18'b0;
end
always @(clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
dataout_tmp <= 'bX;
end
else if (aclr_ipd == 1'b1)
begin
dataout_tmp <= 'b0;
end
else
begin
if ((clk_ipd === 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd === 1'b1)
dataout_tmp <= data_ipd;
end
clk_last_value <= clk_ipd;
end // always
assign dataout_wire = dataout_tmp;
and (dataout[0], dataout_wire[0], 1'b1);
and (dataout[1], dataout_wire[1], 1'b1);
and (dataout[2], dataout_wire[2], 1'b1);
and (dataout[3], dataout_wire[3], 1'b1);
and (dataout[4], dataout_wire[4], 1'b1);
and (dataout[5], dataout_wire[5], 1'b1);
and (dataout[6], dataout_wire[6], 1'b1);
and (dataout[7], dataout_wire[7], 1'b1);
and (dataout[8], dataout_wire[8], 1'b1);
and (dataout[9], dataout_wire[9], 1'b1);
and (dataout[10], dataout_wire[10], 1'b1);
and (dataout[11], dataout_wire[11], 1'b1);
and (dataout[12], dataout_wire[12], 1'b1);
and (dataout[13], dataout_wire[13], 1'b1);
and (dataout[14], dataout_wire[14], 1'b1);
and (dataout[15], dataout_wire[15], 1'b1);
and (dataout[16], dataout_wire[16], 1'b1);
and (dataout[17], dataout_wire[17], 1'b1);
endmodule //cycloneii_mac_data_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_sign_reg
//
// Description : Simulation model for the sign input register of
// Cyclone II MAC_MULT
//
//------------------------------------------------------------------
`timescale 1ps / 1ps
module cycloneii_mac_sign_reg (
clk,
d,
ena,
aclr,
q
);
// INPUT PORTS
input clk;
input d;
input ena;
input aclr;
// OUTPUT PORTS
output q;
// INTERNAL VARIABLES
reg clk_last_value;
reg q_tmp;
reg ena_viol;
reg d_viol;
wire enable;
// DEFAULT VALUES THRO' PULLUPs
tri1 aclr, ena;
wire d_ipd;
wire clk_ipd;
wire ena_ipd;
wire aclr_ipd;
buf (d_ipd, d);
buf (clk_ipd, clk);
buf (ena_ipd, ena);
buf (aclr_ipd, aclr);
assign enable = (!aclr_ipd) && (ena_ipd);
specify
$setuphold (posedge clk &&& enable, d, 0, 0, d_viol) ;
$setuphold (posedge clk &&& enable, ena, 0, 0, ena_viol) ;
(posedge clk => (q +: q_tmp)) = 0 ;
(posedge aclr => (q +: 1'b0)) = 0 ;
endspecify
initial
begin
clk_last_value <= 'b0;
q_tmp <= 'b0;
end
always @ (clk_ipd or aclr_ipd)
begin
if (d_viol == 1'b1 || ena_viol == 1'b1)
begin
q_tmp <= 'bX;
end
else
begin
if (aclr_ipd == 1'b1)
q_tmp <= 0;
else if ((clk_ipd == 1'b1) && (clk_last_value == 1'b0))
if (ena_ipd == 1'b1)
q_tmp <= d_ipd;
end
clk_last_value <= clk_ipd;
end
and (q, q_tmp, 'b1);
endmodule // cycloneii_mac_sign_reg
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_mult_internal
//
// Description : Cyclone II MAC_MULT_INTERNAL Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_mult_internal
(
dataa,
datab,
signa,
signb,
dataout
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
// INPUT
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
// OUTPUT
output [dataout_width-1:0] dataout;
// Internal variables
wire [17:0] dataa_ipd;
wire [17:0] datab_ipd;
wire signa_ipd;
wire signb_ipd;
wire [dataout_width-1:0] dataout_tmp;
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
reg [17:0] i_ones; // padding with 1's for input negation
// Input buffers
buf (signa_ipd, signa);
buf (signb_ipd, signb);
buf dataa_buf [dataa_width-1:0] (dataa_ipd[dataa_width-1:0], dataa);
buf datab_buf [datab_width-1:0] (datab_ipd[datab_width-1:0], datab);
specify
(dataa *> dataout) = (0, 0);
(datab *> dataout) = (0, 0);
(signa *> dataout) = (0, 0);
(signb *> dataout) = (0, 0);
endspecify
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// get signs of a and b, and get absolute values since Verilog '*' operator
// is an unsigned multiplication
assign ia_is_positive = ~signa_ipd | ~dataa_ipd[dataa_width-1];
assign ib_is_positive = ~signb_ipd | ~datab_ipd[datab_width-1];
assign iabsa = ia_is_positive == 1 ? dataa_ipd[dataa_width-1:0] : -(dataa_ipd | (i_ones << dataa_width));
assign iabsb = ib_is_positive == 1 ? datab_ipd[datab_width-1:0] : -(datab_ipd | (i_ones << datab_width));
// multiply a * b
assign iabsresult = iabsa * iabsb;
assign dataout_tmp = (ia_is_positive ^ ib_is_positive) == 1 ? -iabsresult : iabsresult;
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_mult
//
// Description : Cyclone II MAC_MULT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_mult
(
dataa,
datab,
signa,
signb,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 18;
parameter datab_width = 18;
parameter dataout_width = dataa_width + datab_width;
parameter dataa_clock = "none";
parameter datab_clock = "none";
parameter signa_clock = "none";
parameter signb_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneii_mac_mult";
input [dataa_width-1:0] dataa;
input [datab_width-1:0] datab;
input signa;
input signb;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
wire [dataout_width-1:0] dataout_tmp;
wire [17:0] idataa_reg; // optional register for dataa input
wire [17:0] idatab_reg; // optional register for datab input
wire [17:0] dataa_pad; // padded dataa input
wire [17:0] datab_pad; // padded datab input
wire isigna_reg; // optional register for signa input
wire isignb_reg; // optional register for signb input
wire [17:0] idataa_int; // dataa as seen by the multiplier input
wire [17:0] idatab_int; // datab as seen by the multiplier input
wire isigna_int; // signa as seen by the multiplier input
wire isignb_int; // signb as seen by the multiplier input
wire ia_is_positive;
wire ib_is_positive;
wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
wire dataa_use_reg; // equivalent to dataa_clock parameter
wire datab_use_reg; // equivalent to datab_clock parameter
wire signa_use_reg; // equivalent to signa_clock parameter
wire signb_use_reg; // equivalent to signb_clock parameter
reg [17:0] i_ones; // padding with 1's for input negation
wire reg_aclr;
assign reg_aclr = (!devpor) || (!devclrn) || (aclr);
// optional registering parameters
assign dataa_use_reg = (dataa_clock != "none") ? 1'b1 : 1'b0;
assign datab_use_reg = (datab_clock != "none") ? 1'b1 : 1'b0;
assign signa_use_reg = (signa_clock != "none") ? 1'b1 : 1'b0;
assign signb_use_reg = (signb_clock != "none") ? 1'b1 : 1'b0;
assign dataa_pad = ((18-dataa_width) == 0) ? dataa : {{(18-dataa_width){1'b0}},dataa};
assign datab_pad = ((18-datab_width) == 0) ? datab : {{(18-datab_width){1'b0}},datab};
initial
begin
// 1's padding for 18-bit wide inputs
i_ones = ~0;
end
// Optional input registers for dataa,b and signa,b
cycloneii_mac_data_reg dataa_reg (
.clk(clk),
.data(dataa_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idataa_reg)
);
defparam dataa_reg.data_width = dataa_width;
cycloneii_mac_data_reg datab_reg (
.clk(clk),
.data(datab_pad),
.ena(ena),
.aclr(reg_aclr),
.dataout(idatab_reg)
);
defparam datab_reg.data_width = datab_width;
cycloneii_mac_sign_reg signa_reg (
.clk(clk),
.d(signa),
.ena(ena),
.aclr(reg_aclr),
.q(isigna_reg)
);
cycloneii_mac_sign_reg signb_reg (
.clk(clk),
.d(signb),
.ena(ena),
.aclr(reg_aclr),
.q(isignb_reg)
);
// mux input sources from direct inputs or optional registers
assign idataa_int = dataa_use_reg == 1'b1 ? idataa_reg : dataa;
assign idatab_int = datab_use_reg == 1'b1 ? idatab_reg : datab;
assign isigna_int = signa_use_reg == 1'b1 ? isigna_reg : signa;
assign isignb_int = signb_use_reg == 1'b1 ? isignb_reg : signb;
cycloneii_mac_mult_internal mac_multiply (
.dataa(idataa_int[dataa_width-1:0]),
.datab(idatab_int[datab_width-1:0]),
.signa(isigna_int),
.signb(isignb_int),
.dataout(dataout)
);
defparam mac_multiply.dataa_width = dataa_width;
defparam mac_multiply.datab_width = datab_width;
defparam mac_multiply.dataout_width = dataout_width;
endmodule
//------------------------------------------------------------------
//
// Module Name : cycloneii_mac_out
//
// Description : Cyclone II MAC_OUT Verilog simulation model
//
//------------------------------------------------------------------
`timescale 1 ps/1 ps
module cycloneii_mac_out
(
dataa,
clk,
aclr,
ena,
dataout,
devclrn,
devpor
);
parameter dataa_width = 1;
parameter dataout_width = dataa_width;
parameter output_clock = "none";
parameter lpm_hint = "true";
parameter lpm_type = "cycloneii_mac_out";
input [dataa_width-1:0] dataa;
input clk;
input aclr;
input ena;
input devclrn;
input devpor;
output [dataout_width-1:0] dataout;
wire [dataa_width-1:0] dataa_ipd; // internal dataa
wire clk_ipd; // internal clk
wire aclr_ipd; // internal aclr
wire ena_ipd; // internal ena
// internal variable
wire [dataout_width-1:0] dataout_tmp;
reg [dataa_width-1:0] idataout_reg; // optional register for dataout output
wire use_reg; // equivalent to dataout_clock parameter
wire enable;
wire no_aclr;
// Input buffers
buf (clk_ipd, clk);
buf (aclr_ipd, aclr);
buf (ena_ipd, ena);
buf dataa_buf [dataa_width-1:0] (dataa_ipd, dataa);
// optional registering parameter
assign use_reg = (output_clock != "none") ? 1 : 0;
assign enable = (!aclr) && (ena) && use_reg;
assign no_aclr = (!aclr) && use_reg;
specify
if (use_reg)
(posedge clk => (dataout +: dataout_tmp)) = 0;
(posedge aclr => (dataout +: 1'b0)) = 0;
ifnone
(dataa *> dataout) = (0, 0);
$setuphold (posedge clk &&& enable, dataa, 0, 0);
$setuphold (posedge clk &&& no_aclr, ena, 0, 0);
endspecify
initial
begin
// initial values for optional register
idataout_reg = 0;
end
// Optional input registers for dataa,b and signa,b
always @ (posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
begin
if (devclrn == 0 || devpor == 0 || aclr_ipd == 1)
begin
idataout_reg <= 0;
end
else if (ena_ipd == 1)
begin
idataout_reg <= dataa_ipd;
end
end
// mux input sources from direct inputs or optional registers
assign dataout_tmp = use_reg == 1 ? idataout_reg : dataa_ipd;
// accelerate outputs
buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_1_V
`define SKY130_FD_SC_HDLL__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfrtp_1 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 23:24:41 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, SDIO0_WP, TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID,
M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_proposition (reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input reset, enable;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_PROPOSITION";
`include "std_ovl_reset.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_proposition_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_proposition_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_proposition_psl_logic.v"
`else
`endmodule // ovl_proposition
`endif
|
// ============================================================================
// Copyright (c) 2010 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
// Major Functions/Design Description:
//
// Please refer to DE4_UserManual.pdf in DE4 system CD.
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |EricChen |10/06/30 |
// ============================================================================
`define NET0
`define NET1
`define NET2
`define NET3
module DE4_Ethernet(
//////// CLOCK //////////
GCLKIN,
GCLKOUT_FPGA,
OSC_50_BANK2,
OSC_50_BANK3,
OSC_50_BANK4,
OSC_50_BANK5,
OSC_50_BANK6,
OSC_50_BANK7,
PLL_CLKIN_p,
//////// External PLL //////////
MAX_I2C_SCLK,
MAX_I2C_SDAT,
//////// LED x 8 //////////
LED,
//////// BUTTON x 4, EXT_IO and CPU_RESET_n //////////
BUTTON,
CPU_RESET_n,
EXT_IO,
//////// DIP SWITCH x 8 //////////
SW,
//////// SLIDE SWITCH x 4 //////////
SLIDE_SW,
//////// SEG7 //////////
SEG0_D,
SEG0_DP,
SEG1_D,
SEG1_DP,
//////// Temperature //////////
TEMP_INT_n,
TEMP_SMCLK,
TEMP_SMDAT,
//////// Current //////////
CSENSE_ADC_FO,
CSENSE_CS_n,
CSENSE_SCK,
CSENSE_SDI,
CSENSE_SDO,
//////// Fan //////////
FAN_CTRL,
//////// EEPROM //////////
EEP_SCL,
EEP_SDA,
//////// SDCARD //////////
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_n,
//////// RS232 //////////
UART_CTS,
UART_RTS,
UART_RXD,
UART_TXD,
//////// Ethernet x 4 //////////
ETH_INT_n,
ETH_MDC,
ETH_MDIO,
ETH_RST_n,
ETH_RX_p,
ETH_TX_p,
//////// Flash and SRAM Address/Data Share Bus //////////
FSM_A,
FSM_D,
//////// Flash Control //////////
FLASH_ADV_n,
FLASH_CE_n,
FLASH_CLK,
FLASH_OE_n,
FLASH_RESET_n,
FLASH_RYBY_n,
FLASH_WE_n,
//////// SSRAM Control //////////
SSRAM_ADV,
SSRAM_BWA_n,
SSRAM_BWB_n,
SSRAM_CE_n,
SSRAM_CKE_n,
SSRAM_CLK,
SSRAM_OE_n,
SSRAM_WE_n,
///////// DRAM interfaces ///////
//////// DDR2 SODIMM //////////
M1_DDR2_addr,
M1_DDR2_ba,
M1_DDR2_cas_n,
M1_DDR2_cke,
M1_DDR2_clk,
M1_DDR2_clk_n,
M1_DDR2_cs_n,
M1_DDR2_dm,
M1_DDR2_dq,
M1_DDR2_dqs,
M1_DDR2_dqsn,
M1_DDR2_odt,
M1_DDR2_ras_n,
M1_DDR2_SA,
M1_DDR2_SCL,
M1_DDR2_SDA,
M1_DDR2_we_n,
M1_DDR2_RDN,
M1_DDR2_RUP
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input GCLKIN;
output GCLKOUT_FPGA;
input OSC_50_BANK2;
input OSC_50_BANK3;
input OSC_50_BANK4;
input OSC_50_BANK5;
input OSC_50_BANK6;
input OSC_50_BANK7;
input PLL_CLKIN_p;
//////////// External PLL //////////
output MAX_I2C_SCLK;
inout MAX_I2C_SDAT;
//////////// LED x 8 //////////
output [7:0] LED;
//////////// BUTTON x 4, EXT_IO and CPU_RESET_n //////////
input [3:0] BUTTON;
input CPU_RESET_n;
inout EXT_IO;
//////////// DIP SWITCH x 8 //////////
input [7:0] SW;
//////////// SLIDE SWITCH x 4 //////////
input [3:0] SLIDE_SW;
//////////// SEG7 //////////
output [6:0] SEG0_D;
output SEG0_DP;
output [6:0] SEG1_D;
output SEG1_DP;
//////////// Temperature //////////
input TEMP_INT_n;
output TEMP_SMCLK;
inout TEMP_SMDAT;
//////////// Current //////////
output CSENSE_ADC_FO;
output [1:0] CSENSE_CS_n;
output CSENSE_SCK;
output CSENSE_SDI;
input CSENSE_SDO;
//////////// Fan //////////
output FAN_CTRL;
//////////// EEPROM //////////
output EEP_SCL;
inout EEP_SDA;
//////////// SDCARD //////////
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
input SD_WP_n;
//////////// RS232 //////////
output UART_CTS;
input UART_RTS;
input UART_RXD;
output UART_TXD;
//////////// Ethernet x 4 //////////
input [3:0] ETH_INT_n;
output [3:0] ETH_MDC;
inout [3:0] ETH_MDIO;
output ETH_RST_n;
input [3:0] ETH_RX_p;
output [3:0] ETH_TX_p;
//////////// Flash and SRAM Address/Data Share Bus //////////
output [25:0] FSM_A;
inout [15:0] FSM_D;
//////////// Flash Control //////////
output FLASH_ADV_n;
output FLASH_CE_n;
output FLASH_CLK;
output FLASH_OE_n;
output FLASH_RESET_n;
input FLASH_RYBY_n;
output FLASH_WE_n;
//////////// SSRAM Control //////////
output SSRAM_ADV;
output SSRAM_BWA_n;
output SSRAM_BWB_n;
output SSRAM_CE_n;
output SSRAM_CKE_n;
output SSRAM_CLK;
output SSRAM_OE_n;
output SSRAM_WE_n;
/////////// DDR2 signals /////////////
//////////// DDR2 SODIMM //////////
output [13:0] M1_DDR2_addr;
output [2:0] M1_DDR2_ba;
output M1_DDR2_cas_n;
output [1:0] M1_DDR2_cke;
output [1:0] M1_DDR2_clk;
output [1:0] M1_DDR2_clk_n;
output [1:0] M1_DDR2_cs_n;
output [7:0] M1_DDR2_dm;
inout [63:0] M1_DDR2_dq;
inout [7:0] M1_DDR2_dqs;
inout [7:0] M1_DDR2_dqsn;
output [1:0] M1_DDR2_odt;
output M1_DDR2_ras_n;
output [1:0] M1_DDR2_SA;
output M1_DDR2_SCL;
inout M1_DDR2_SDA;
output M1_DDR2_we_n;
input M1_DDR2_RDN;
input M1_DDR2_RUP;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire global_reset_n;
wire enet_reset_n;
//// Ethernet
wire enet_mdc0;
wire enet_mdio_in0;
wire enet_mdio_oen0;
wire enet_mdio_out0;
wire enet_refclk_125MHz;
wire lvds_rxp0;
wire lvds_txp0;
wire enet_mdc1;
wire enet_mdio_in1;
wire enet_mdio_oen1;
wire enet_mdio_out1;
wire lvds_rxp1;
wire lvds_txp1;
wire enet_mdc2;
wire enet_mdio_in2;
wire enet_mdio_oen2;
wire enet_mdio_out2;
wire lvds_rxp2;
wire lvds_txp2;
wire enet_mdc3;
wire enet_mdio_in3;
wire enet_mdio_oen3;
wire enet_mdio_out3;
wire lvds_rxp3;
wire lvds_txp3;
//=======================================================
// External PLL Configuration ==========================
//=======================================================
// Signal declarations
wire [ 3: 0] clk1_set_wr, clk2_set_wr, clk3_set_wr;
wire rstn;
wire conf_ready;
wire counter_max;
wire [7:0] counter_inc;
reg [7:0] auto_set_counter;
reg conf_wr;
//interrupt wires
wire interrupt_in_export;
/////////////////////////////////////////////
//Interface from DRAM read interface to compute system (control)
wire control_fixed_location;
wire [30:0] read_length;
wire control_go;
wire control_done;
wire [30:0] read_base;
//Interface from DRAM read interface to compute system (user)
wire user_read_buffer;
wire [255:0] user_buffer_output_data;
wire user_data_available;
//////////////////////////////////////////////
// Structural coding
assign clk1_set_wr = 4'd4; //100 MHZ
assign clk2_set_wr = 4'd4; //100 MHZ
assign clk3_set_wr = 4'd4; //100 MHZ
assign rstn = CPU_RESET_n;
assign counter_max = &auto_set_counter;
assign counter_inc = auto_set_counter + 1'b1;
always @(posedge OSC_50_BANK2 or negedge rstn)
if(!rstn)
begin
auto_set_counter <= 0;
conf_wr <= 0;
end
else if (counter_max)
conf_wr <= 1;
else
auto_set_counter <= counter_inc;
ext_pll_ctrl ext_pll_ctrl_Inst(
.osc_50(OSC_50_BANK2), //50MHZ
.rstn(rstn),
// device 1 (HSMA_REFCLK)
.clk1_set_wr(clk1_set_wr),
.clk1_set_rd(),
// device 2 (HSMB_REFCLK)
.clk2_set_wr(clk2_set_wr),
.clk2_set_rd(),
// device 3 (PLL_CLKIN/SATA_REFCLK)
.clk3_set_wr(clk3_set_wr),
.clk3_set_rd(),
// setting trigger
.conf_wr(conf_wr), // 1T 50MHz
.conf_rd(), // 1T 50MHz
// status
.conf_ready(conf_ready),
// 2-wire interface
.max_sclk(MAX_I2C_SCLK),
.max_sdat(MAX_I2C_SDAT)
);
//=======================================================
// Structural coding
//=======================================================
//// Ethernet
assign ETH_RST_n = enet_reset_n;
`ifdef NET0
//input [0:0] ETH_RX_p;
//output [0:0] ETH_TX_p;
assign lvds_rxp0 = ETH_RX_p[0];
assign ETH_TX_p[0] = lvds_txp0;
assign enet_mdio_in0 = ETH_MDIO[0];
assign ETH_MDIO[0] = !enet_mdio_oen0 ? enet_mdio_out0 : 1'bz;
assign ETH_MDC[0] = enet_mdc0;
`endif
//`elsif NET1
`ifdef NET1
//input [1:1] ETH_RX_p;
//output [1:1] ETH_TX_p;
assign lvds_rxp1 = ETH_RX_p[1];
assign ETH_TX_p[1] = lvds_txp1;
assign enet_mdio_in1 = ETH_MDIO[1];
assign ETH_MDIO[1] = !enet_mdio_oen1 ? enet_mdio_out1 : 1'bz;
assign ETH_MDC[1] = enet_mdc1;
`endif
//`elsif NET2
`ifdef NET2
//input [2:2] ETH_RX_p;
//output [2:2] ETH_TX_p;
assign lvds_rxp2 = ETH_RX_p[2];
assign ETH_TX_p[2] = lvds_txp2;
assign enet_mdio_in2 = ETH_MDIO[2];
assign ETH_MDIO[2] = !enet_mdio_oen2 ? enet_mdio_out2 : 1'bz;
assign ETH_MDC[2] = enet_mdc2;
`endif
//`elsif NET3
`ifdef NET3
//input [3:3] ETH_RX_p;
//output [3:3] ETH_TX_p;
assign lvds_rxp3 = ETH_RX_p[3];
assign ETH_TX_p[3] = lvds_txp3;
assign enet_mdio_in3 = ETH_MDIO[3];
assign ETH_MDIO[3] = !enet_mdio_oen3 ? enet_mdio_out3 : 1'bz;
assign ETH_MDC[3] = enet_mdc3;
`endif
//// FLASH and SSRAM share bus
assign FLASH_ADV_n = 1'b0; // not used
assign FLASH_CLK = 1'b0; // not used
assign FLASH_RESET_n = global_reset_n;
//// SSRAM
//// Fan Control
assign FAN_CTRL = 1'bz; // don't control
// === Ethernet clock PLL
pll_125 pll_125_ins (
.inclk0(OSC_50_BANK3),
.c0(enet_refclk_125MHz)
);
gen_reset_n system_gen_reset_n (
.tx_clk(OSC_50_BANK3),
.reset_n_in(CPU_RESET_n),
.reset_n_out(global_reset_n)
);
gen_reset_n net_gen_reset_n(
.tx_clk(OSC_50_BANK3),
.reset_n_in(global_reset_n),
.reset_n_out(enet_reset_n)
);
DE4_SOPC SOPC_INST (
// 1) global signals:
//.ext_clk(OSC_50_BANK6), //Deepak comment
//.ext_clk_clk_in_clk(OSC_50_BANK6),
.ext_clk(OSC_50_BANK6),
.pll_peripheral_clk(),
.pll_sys_clk(),
.ext_clk_clk_in_reset_reset_n(global_reset_n),
//.reset_n(global_reset_n),
// the_flash_tristate_bridge_avalon_slave
/*
.flash_tristate_bridge_address(FSM_A[24:0]),
.flash_tristate_bridge_data(FSM_D),
.flash_tristate_bridge_readn(FLASH_OE_n),
.flash_tristate_bridge_writen(FLASH_WE_n),
.select_n_to_the_ext_flash(FLASH_CE_n),
*/
// the_tse_mac
.led_an_from_the_tse_mac(led_an_from_the_tse_mac),
.led_char_err_from_the_tse_mac(led_char_err_from_the_tse_mac),
.led_col_from_the_tse_mac(led_col_from_the_tse_mac),
.led_crs_from_the_tse_mac(led_crs_from_the_tse_mac),
.led_disp_err_from_the_tse_mac(led_disp_err_from_the_tse_mac),
.led_link_from_the_tse_mac(led_link_from_the_tse_mac),
.mdc_from_the_tse_mac(enet_mdc0),
.mdio_in_to_the_tse_mac(enet_mdio_in0),
.mdio_oen_from_the_tse_mac(enet_mdio_oen0),
.mdio_out_from_the_tse_mac(enet_mdio_out0),
.ref_clk_to_the_tse_mac(enet_refclk_125MHz),
.rxp_to_the_tse_mac(lvds_rxp0),
.txp_from_the_tse_mac(lvds_txp0),
// the_tse_mac1
.led_an_from_the_tse_mac1(),
.led_char_err_from_the_tse_mac1(),
.led_col_from_the_tse_mac1(),
.led_crs_from_the_tse_mac1(),
.led_disp_err_from_the_tse_mac1(),
.led_link_from_the_tse_mac1(),
.mdc_from_the_tse_mac1(enet_mdc1),
.mdio_in_to_the_tse_mac1(enet_mdio_in1),
.mdio_oen_from_the_tse_mac1(enet_mdio_oen1),
.mdio_out_from_the_tse_mac1(enet_mdio_out1),
.ref_clk_to_the_tse_mac1(enet_refclk_125MHz),
.rxp_to_the_tse_mac1(lvds_rxp1),
.txp_from_the_tse_mac1(lvds_txp1),
/*
// the_tse_mac2
.led_an_from_the_tse_mac2(),
.led_char_err_from_the_tse_mac2(),
.led_col_from_the_tse_mac2(),
.led_crs_from_the_tse_mac2(),
.led_disp_err_from_the_tse_mac2(),
.led_link_from_the_tse_mac2(),
.mdc_from_the_tse_mac2(enet_mdc2),
.mdio_in_to_the_tse_mac2(enet_mdio_in2),
.mdio_oen_from_the_tse_mac2(enet_mdio_oen2),
.mdio_out_from_the_tse_mac2(enet_mdio_out2),
.ref_clk_to_the_tse_mac2(enet_refclk_125MHz),
.rxp_to_the_tse_mac2(lvds_rxp2),
.txp_from_the_tse_mac2(lvds_txp2),
// the_tse_mac3
.led_an_from_the_tse_mac3(),
.led_char_err_from_the_tse_mac3(),
.led_col_from_the_tse_mac3(),
.led_crs_from_the_tse_mac3(),
.led_disp_err_from_the_tse_mac3(),
.led_link_from_the_tse_mac3(),
.mdc_from_the_tse_mac3(enet_mdc3),
.mdio_in_to_the_tse_mac3(enet_mdio_in3),
.mdio_oen_from_the_tse_mac3(enet_mdio_oen3),
.mdio_out_from_the_tse_mac3(enet_mdio_out3),
.ref_clk_to_the_tse_mac3(enet_refclk_125MHz),
.rxp_to_the_tse_mac3(lvds_rxp3),
.txp_from_the_tse_mac3(lvds_txp3),
*/
//.interrupt_in_export(interrupt_in_export),
//.dma_transfer_done_out_export(interrupt_in_export),
/*
// the_pb_pio
.in_port_to_the_pb_pio(BUTTON),
// the_sw_pio
.in_port_to_the_sw_pio(SW),
// the_seven_seg_pio
.out_port_from_the_seven_seg_pio({SEG1_DP,SEG1_D[6:0],SEG0_DP,SEG0_D[6:0]}),
// the_led_pio
.out_port_from_the_led_pio({dummy_LED,LED[6:0]})
*/
.memory_mem_a(M1_DDR2_addr),
.memory_mem_ba(M1_DDR2_ba),
.memory_mem_cas_n(M1_DDR2_cas_n),
.memory_mem_cke(M1_DDR2_cke),
.memory_mem_ck_n(M1_DDR2_clk_n),
.memory_mem_ck(M1_DDR2_clk),
.memory_mem_cs_n(M1_DDR2_cs_n),
.memory_mem_dm(M1_DDR2_dm),
.memory_mem_dq(M1_DDR2_dq),
.memory_mem_dqs(M1_DDR2_dqs),
.memory_mem_dqs_n(M1_DDR2_dqsn),
.memory_mem_odt(M1_DDR2_odt),
.memory_mem_ras_n(M1_DDR2_ras_n),
.memory_mem_we_n(M1_DDR2_we_n),
.oct_rdn(M1_DDR2_RDN),
.oct_rup(M1_DDR2_RUP),
.mem_if_ddr2_emif_0_global_reset_reset_n(1'b1), //Deepak tying dram reset to 1
.mem_if_ddr2_emif_0_soft_reset_reset_n(1'b1), //tying dram pll rset to 1
);
///////////////////////////////////////////////////////////////////////////////
assign LED[7] = count[21];
reg [31:0] count;
always @ (negedge global_reset_n or posedge OSC_50_BANK3)
begin
if (!global_reset_n) begin
count <= 0;
end
else begin
count <= count + 1;
end
end
///////////////////////////////////////////////////////////////////////////////
endmodule
|
// Check that the signedness of the element type of a queue is correctly handled
// whenn calling one of the pop methods with parenthesis.
module test;
bit failed = 1'b0;
`define check(x) \
if (!(x)) begin \
$display("FAILED(%0d): ", `__LINE__, `"x`"); \
failed = 1'b1; \
end
int unsigned x = 10;
int y = 10;
int z;
longint w;
shortint qs[$];
bit [15:0] qu[$];
initial begin
for (int i = 0; i < 16; i++) begin
qu.push_back(-1);
qs.push_back(-1);
end
// These all evaluate as signed
`check($signed(qu.pop_back) < 0)
`check(qs.pop_back < 0)
`check($signed(qu.pop_front) < 0)
`check(qs.pop_front < 0)
// These all evaluate as unsigned
`check(qu.pop_back > 0)
`check({qs.pop_back} > 0)
`check($unsigned(qs.pop_back) > 0)
`check(qs.pop_back > 16'h0)
`check(qu.pop_front > 0)
`check({qs.pop_front} > 0)
`check($unsigned(qs.pop_front) > 0)
`check(qs.pop_front > 16'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = qu.pop_back + x;
`check(z === 65545)
z = qu.pop_back + y;
`check(z === 65545)
z = qu.pop_front + x;
`check(z === 65545)
z = qu.pop_front + y;
`check(z === 65545)
z = qs.pop_back + x;
`check(z === 65545)
z = qs.pop_back + y;
`check(z === 9)
z = qs.pop_front + x;
`check(z === 65545)
z = qs.pop_front + y;
`check(z === 9)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? qu.pop_back : x;
`check(z === 65535)
z = x ? qu.pop_back : y;
`check(z === 65535)
z = x ? qu.pop_front : x;
`check(z === 65535)
z = x ? qu.pop_front : y;
`check(z === 65535)
z = x ? qs.pop_back : x;
`check(z === 65535)
z = x ? qs.pop_back : y;
`check(z === -1)
z = x ? qs.pop_front : x;
`check(z === 65535)
z = x ? qs.pop_front : y;
`check(z === -1)
// Size return value is always positive, but check that it gets padded
// properly
w = x ? qu.size : 64'h123;
`check(w === 64'h4)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
// Define an ALU with 16 functions
module alu (A, B, function_sel,
aluout, zero_flag, parity_flag, carry_flag);
// Define I/O for the ALU
output [15:0] aluout;
output zero_flag, parity_flag, carry_flag;
input [15:0] A, B;
input [3:0] function_sel;
reg [15:0] aluout;
reg zero_flag, parity_flag, carry_flag;
// Define text macros for ALU opcodes
`define move 4'b0000 /* aluout = B */
`define comp 4'b0001 /* aluout = bit-wise complement(B) */
`define and 4'b0010 /* aluout = A & B */
`define or 4'b0011 /* aluout = A | B */
`define xor 4'b0100 /* aluout = A ^ B */
`define add 4'b0101 /* aluout = A + B */
`define incr 4'b0110 /* aluout = B + 1 */
`define sub 4'b0111 /* aluout = A - B */
`define rotl 4'b1000 /* aluout = rotate B left one bit */
`define lshl 4'b1001 /* aluout = logical shift B left one bit, zero fill */
`define rotr 4'b1010 /* aluout = rotate B right one bit */
`define lshr 4'b1011 /* aluout = logical shift B right one bit, zero fill */
`define xnor 4'b1100 /* aluout = A ~^ B */
`define nor 4'b1101 /* aluout = ~(A | B) */
`define decr 4'b1110 /* aluout = B - 1 */
`define nand 4'b1111 /* aluout = ~(A & B) */
always @(A or B or function_sel)
begin
case (function_sel)
`move : {carry_flag, aluout} = {1'b0, B};
`comp : {carry_flag, aluout} = {1'b1, ~B};
`and : {carry_flag, aluout} = {1'b0, A & B};
`or : {carry_flag, aluout} = {1'b0, A | B};
`xor : {carry_flag, aluout} = {1'b0, A ^ B};
`add : {carry_flag, aluout} = A + B;
`incr : {carry_flag, aluout} = B + 1;
`sub : {carry_flag, aluout} = {1'b1, A} - B;
`rotl : {carry_flag, aluout} = {B[15:0], B[15]};
`lshl : {carry_flag, aluout} = {B[15:0], 1'b0};
`rotr : {carry_flag, aluout} = {B[0], B[0], B[15:1]};
`lshr : {carry_flag, aluout} = {2'b0, B[15:1]};
`xnor : {carry_flag, aluout} = {1'b1, A ~^ B};
`nor : {carry_flag, aluout} = {1'b1, ~(A | B)};
`decr : {carry_flag, aluout} = B - 1;
`nand : {carry_flag, aluout} = {1'b1, ~(A & B)};
endcase
zero_flag = ~|aluout;
parity_flag = ^aluout;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__SDFBBP_PP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_PP_BLACKBOX_V
|
module top (
input wire i_clk,
input wire i_rst,
input wire i_ce,
input wire i_d1,
input wire i_d2,
output wire [23:0] io,
);
// BUFGs
wire clk;
BUFG bufg_1 (.I(i_clk), .O(clk));
genvar sa, e, i, sr;
generate begin
// SRTYPE
for (sa=0; sa<2; sa=sa+1) begin
localparam SRTYPE = (sa != 0) ? "SYNC" : "ASYNC";
// DDR_CLK_EDGE
for (e=0; e<2; e=e+1) begin
localparam EDGE = (e == 0) ? "SAME_EDGE" :
/*(e == 1) ?*/ "OPPOSITE_EDGE";
// Set, Reset or neither
for (sr=0; sr<3; sr=sr+1) begin
wire r;
wire s;
assign r = ((sr & 1) != 0) ? i_rst : 1'b0;
assign s = ((sr & 2) != 0) ? i_rst : 1'b0;
// INIT_Q
for (i=0; i<2; i=i+1) begin
localparam idx = sa*12 + e*6 + sr*2 + i;
wire [0:0] t;
wire [0:0] i_sig;
ODDR # (
.SRTYPE (SRTYPE),
.INIT (i == 1),
.DDR_CLK_EDGE (EDGE)
) tddr (
.C(clk), .CE(i_ce), .D1(i_d1), .D2(i_d2),
.R(r), .S(s),
.Q(t)
);
ODDR # (
.SRTYPE (SRTYPE),
.INIT (i == 1),
.DDR_CLK_EDGE (EDGE)
) oddr (
.C(clk), .CE(i_ce), .D1(i_d1), .D2(i_d2),
.R(r), .S(s),
.Q(i_sig)
);
// Cannot instance OBUFT because Yosys infers IOBs and
// inserts an inferred OBUF after the OBUFT...
assign io[idx] = (t == 1'b0) ? i_sig : 1'bz;
end
end
end
end
end endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2_BLACKBOX_V
`define SKY130_FD_SC_LS__OR2_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2_BLACKBOX_V
|
`timescale 1 ns / 1 ps
module AXIOutputRegisters_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 6
)
(
// Users to add ports here
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg0_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg1_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg2_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg3_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg4_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg5_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg6_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg7_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg8_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg9_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg10_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg11_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg12_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg13_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg14_output,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] reg15_output,
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
AXIOutputRegisters_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) AXIOutputRegisters_v1_0_S00_AXI_inst (
.reg0_output(reg0_output),
.reg1_output(reg1_output),
.reg2_output(reg2_output),
.reg3_output(reg3_output),
.reg4_output(reg4_output),
.reg5_output(reg5_output),
.reg6_output(reg6_output),
.reg7_output(reg7_output),
.reg8_output(reg8_output),
.reg9_output(reg9_output),
.reg10_output(reg10_output),
.reg11_output(reg11_output),
.reg12_output(reg12_output),
.reg13_output(reg13_output),
.reg14_output(reg14_output),
.reg15_output(reg15_output),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
//`#start header` -- edit after this line, do not edit this line
/*
IambicV: Iambic keyer in Verilog
Copyright © 2011 Stephen C. Trier
This file is part of IambicV
IambicV is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
IambicV is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with IambicV. If not, see <http://www.gnu.org/licenses/>.
*/
// Iambic Keyer
// Stephen Trier KG8IH
// http://skywired.net/
// sct (at) skywired.net
`include "cypress.v"
//
// Inputs:
// rst_n - Asynchronous reset input, internally synchronized to clk.
// clk - input clock signal, active rising edge, 100 Hz nominal
// speed = (f(clk) * 60) / (wpm * 50) (Using PARIS standard timing.)
// At 1000 Hz clk, 12 wpm is speed=100, 5 wpm is speed = 240, and 20 wpm is speed = 60
// modeb - Mode B flag. Set to 1 if operating in mode B, 0 if in mode A.
// dit - dit paddle input
// dah - dah paddle input
//
// Output:
// key - Morse code keyed output
//
module iambic(input clk, input dit, input dah, output key);
// Definition of the control register.
wire [7:0] iambic_control;
wire modeb;
wire skey;
wire autospace;
wire rst_n;
assign modeb = iambic_control[0];
assign skey = iambic_control[1];
assign autospace = iambic_control[2];
assign rst_n = iambic_control[7];
cy_psoc3_control #(.cy_init_value(8'b10000001), .cy_force_order(`TRUE))
IAMBIC_CONTROL(.control(iambic_control));
reg [1:0] reps;
wire start, nextDah;
reg isDah, iamb;
reg rst_q1, rst_local;
/* ==================== Wire and Register Declarations ==================== */
wire Zero_Detect;
wire cntr8_d0_load;
wire cntr8_d1_load;
wire cntr8_f0_load;
wire cntr8_f1_load;
wire cntr8_route_si;
wire cntr8_route_ci;
wire [2:0] cntr8_select;
/* ==================== Assignment of Combinatorial Variables ==================== */
assign cntr8_d0_load = (1'b0);
assign cntr8_d1_load = (1'b0);
assign cntr8_f0_load = (1'b0);
assign cntr8_f1_load = (1'b0);
assign cntr8_route_si = (1'b0);
assign cntr8_route_ci = (1'b0);
// 0 - count down to zero, 1 - keep at zero.
assign cntr8_select[0] = (Zero_Detect);
// Reload the counter.
assign cntr8_select[1] = (Zero_Detect && (start || (reps != 0)));
// Reset the whole counter -> reset the keyer.
assign cntr8_select[2] = (! rst_local);
/*
* Local reset: Synchronize the release of reset with the clk
*
* This means that the keyer won't be available for two clock cycles after reset is released.
*/
always @(negedge rst_n or posedge clk)
begin
if (rst_n == 0)
{rst_q1,rst_local} <= 2'b00;
else
{rst_q1,rst_local} <= {1'b1,rst_q1};
end
/*
* start is true when we have something to send.
*
* Those times are when the dit paddle is down, when the dah paddle is down, and when we have
* a pending inserted dit or dah (when iamb == 1)
*
* start is not a complete calculation of whether to send. It is only examined when the counter
* is 0, and some extra qualifications kick in if modeb == 0.
*/
assign start = (modeb && iamb) || dit || dah;
/*
* nextDah is true when the next symbol should be a dah.
*
* If iamb == 1, nextDah is the opposite of our current dah state (isDah)
* Otherwise, nextDah is 1 if and only if the dah paddle is 1.
*/
assign nextDah = iamb ? !isDah : dah;
always @(posedge clk or negedge rst_local)
begin
if (rst_local == 0)
begin
/*
* Handle reset by clearing our state
*/
reps <= 0;
//isDah <= 0;
iamb <= 0;
end
else if (reps == 0 && Zero_Detect) /* If the counter is stopped at zero */
begin
if (!modeb && !dit && !dah)
begin
/*
* Special case for mode A: if neither paddle is depressed,
* don't start another dit or dah. Also, clear the iamb flag
* so the keyer doesn't accidentally pick the wrong value of
* nextDah when the start condition does come around.
*/
iamb <= 0;
end
else if (start)
begin
reps <= nextDah ? 3 : 1; /* Dahs are three times as long as dits */
isDah <= nextDah; /* Save whether this is a dit or a dah */
iamb <= 0; /* Clear the iamb flag to get ready for another iamb */
end
end
else /* Otherwise, the counter is running... */
begin
if (reps != 0 && Zero_Detect) // and count == 0
begin
reps <= reps - 1; /* ... and decrement the reps count that makes dahs longer than dits */
end
if (isDah ? dit : dah) /* Check for an iamb, including dot/dash insertion */
iamb <= 1; /* This is an iamb -- flag it for later */
end
end
/*
* The reps counter goes from 3 to 0 for dahs and 1 to 0 for dits.
* The non-zero values are the key-down intervals, so dahs are three times as long as dits.
* When reps == 0, though, the keyer is either timing an inter-symbol space (if count != 0)
* or is idle and waiting (if count == 0). Hence, the key should be down when reps == 0 and
* down when reps == 0.
*/
assign key = skey ? dah : (reps != 0);
/* ==================== cntr8 (Width: 8) Instantiation ==================== */
parameter cntr8_dpconfig0 =
{
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA, /*CFGRAM0: Decrement to Zero */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0, `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA, /*CFGRAM1: Maintain Zero */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA, /*CFGRAM2: Reload Count */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA, /*CFGRAM3: Reload Count */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0, `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA, /*CFGRAM4: Reset */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0, `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA, /*CFGRAM5: Reset */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0, `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA, /*CFGRAM6: Reset */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0, `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, `CS_CMP_SEL_CFGA, /*CFGRAM7: Reset */
8'hFF, 8'h00, /* CFG9 */
8'hFF, 8'hFF, /* CFG11-10 */
`SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH, `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI, `SC_SI_A_DEFSI, /* CFG13-12 */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0, `SC_SR_SRC_REG, `SC_FIFO1_BUS, `SC_FIFO0_BUS, `SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_NOCHN, `SC_FB_NOCHN, `SC_CMP1_NOCHN, `SC_CMP0_NOCHN, /* CFG15-14 */
3'b000, `SC_FIFO_SYNC__ADD, 2'b000, `SC_FIFO1_DYN_OF, `SC_FIFO0_DYN_OF, `SC_FIFO_CLK1_POS, `SC_FIFO_CLK0_POS, `SC_FIFO_CLK__DP, `SC_FIFO_CAP_AX, `SC_FIFO_LEVEL, `SC_FIFO__SYNC, `SC_EXTCRC_DSBL, `SC_WRK16CAT_DSBL /* CFG17-16 */
};
cy_psoc3_dp8 #(
.cy_dpconfig_a( cntr8_dpconfig0 ),
.d0_init_a( 8'b00111111 ),
.d1_init_a( 8'b00000000 ),
.a0_init_a( 8'b00000000 ),
.a1_init_a( 8'b00000000 ))
cntr8(
.clk( clk ),
.cs_addr( cntr8_select ),
.route_si( cntr8_route_si ),
.route_ci( cntr8_route_ci ),
.f0_load( cntr8_f0_load ),
.f1_load( cntr8_f1_load ),
.d0_load( cntr8_d0_load ),
.d1_load( cntr8_d1_load ),
.ce0( ),
.cl0( ),
.z0( Zero_Detect ),
.ff0( ),
.ce1( ),
.cl1( ),
.z1( ),
.ff1( ),
.ov_msb( ),
.co_msb( ),
.cmsb( ),
.so( ),
.f0_bus_stat( ),
.f0_blk_stat( ),
.f1_bus_stat( ),
.f1_blk_stat( )
);
endmodule
//[] END OF FILE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V
|
module chanOffsetMUX (
input clk,
input signed [12:0] chanOffset,
input [3:0] chanOffsetSel,
output reg signed [12:0] chan1_offset = 13'sd0, // program static offsets here!
output reg signed [12:0] chan2_offset = 13'sd0,
output reg signed [12:0] chan3_offset = 13'sd0,
output reg signed [12:0] chan4_offset = 13'sd0,
output reg signed [12:0] chan5_offset = 13'sd0,
output reg signed [12:0] chan6_offset = 13'sd0,
output reg signed [12:0] chan7_offset = 13'sd0,
output reg signed [12:0] chan8_offset = 13'sd0,
output reg signed [12:0] chan9_offset = 13'sd0
);
(* async_reg = "TRUE" *) reg signed [12:0] chanOffset_a = 13'sd0, chanOffset_b = 13'sd0;
(* async_reg = "TRUE" *) reg [3:0] chanOffsetSel_a = 4'h0, chanOffsetSel_b = 4'h0;
always @(posedge clk) begin
chanOffset_a <= chanOffset;
chanOffset_b <= chanOffset_a;
chanOffsetSel_a <= chanOffsetSel;
chanOffsetSel_b <= chanOffsetSel_a;
/*chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;*/
(* full_case, parallel_case *)
case (chanOffsetSel_b)
4'h1: begin
chan1_offset <= chanOffset_b;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h2: begin
chan1_offset <= chan1_offset;
chan2_offset <= chanOffset_b;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h3: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chanOffset_b;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h4: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chanOffset_b;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h5: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chanOffset_b;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h6: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chanOffset_b;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h7: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chanOffset_b;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
4'h8: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chanOffset_b;
chan9_offset <= chan9_offset;
end
4'h9: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chanOffset_b;
end
default: begin
chan1_offset <= chan1_offset;
chan2_offset <= chan2_offset;
chan3_offset <= chan3_offset;
chan4_offset <= chan4_offset;
chan5_offset <= chan5_offset;
chan6_offset <= chan6_offset;
chan7_offset <= chan7_offset;
chan8_offset <= chan8_offset;
chan9_offset <= chan9_offset;
end
endcase
end
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Mon Aug 21 16:17:20 2017
//Host : WK115 running 64-bit major release (build 9200)
//Command : generate_target PmodJSTK.bd
//Design : PmodJSTK
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "PmodJSTK,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=PmodJSTK,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=3,numReposBlks=3,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,synth_mode=Global}" *) (* HW_HANDOFF = "PmodJSTK.hwdef" *)
module PmodJSTK
(AXI_LITE_GPIO_araddr,
AXI_LITE_GPIO_arready,
AXI_LITE_GPIO_arvalid,
AXI_LITE_GPIO_awaddr,
AXI_LITE_GPIO_awready,
AXI_LITE_GPIO_awvalid,
AXI_LITE_GPIO_bready,
AXI_LITE_GPIO_bresp,
AXI_LITE_GPIO_bvalid,
AXI_LITE_GPIO_rdata,
AXI_LITE_GPIO_rready,
AXI_LITE_GPIO_rresp,
AXI_LITE_GPIO_rvalid,
AXI_LITE_GPIO_wdata,
AXI_LITE_GPIO_wready,
AXI_LITE_GPIO_wstrb,
AXI_LITE_GPIO_wvalid,
AXI_LITE_SPI_araddr,
AXI_LITE_SPI_arready,
AXI_LITE_SPI_arvalid,
AXI_LITE_SPI_awaddr,
AXI_LITE_SPI_awready,
AXI_LITE_SPI_awvalid,
AXI_LITE_SPI_bready,
AXI_LITE_SPI_bresp,
AXI_LITE_SPI_bvalid,
AXI_LITE_SPI_rdata,
AXI_LITE_SPI_rready,
AXI_LITE_SPI_rresp,
AXI_LITE_SPI_rvalid,
AXI_LITE_SPI_wdata,
AXI_LITE_SPI_wready,
AXI_LITE_SPI_wstrb,
AXI_LITE_SPI_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
ext_spi_clk,
s_axi_aclk,
s_axi_aresetn);
input [8:0]AXI_LITE_GPIO_araddr;
output AXI_LITE_GPIO_arready;
input AXI_LITE_GPIO_arvalid;
input [8:0]AXI_LITE_GPIO_awaddr;
output AXI_LITE_GPIO_awready;
input AXI_LITE_GPIO_awvalid;
input AXI_LITE_GPIO_bready;
output [1:0]AXI_LITE_GPIO_bresp;
output AXI_LITE_GPIO_bvalid;
output [31:0]AXI_LITE_GPIO_rdata;
input AXI_LITE_GPIO_rready;
output [1:0]AXI_LITE_GPIO_rresp;
output AXI_LITE_GPIO_rvalid;
input [31:0]AXI_LITE_GPIO_wdata;
output AXI_LITE_GPIO_wready;
input [3:0]AXI_LITE_GPIO_wstrb;
input AXI_LITE_GPIO_wvalid;
input [6:0]AXI_LITE_SPI_araddr;
output AXI_LITE_SPI_arready;
input AXI_LITE_SPI_arvalid;
input [6:0]AXI_LITE_SPI_awaddr;
output AXI_LITE_SPI_awready;
input AXI_LITE_SPI_awvalid;
input AXI_LITE_SPI_bready;
output [1:0]AXI_LITE_SPI_bresp;
output AXI_LITE_SPI_bvalid;
output [31:0]AXI_LITE_SPI_rdata;
input AXI_LITE_SPI_rready;
output [1:0]AXI_LITE_SPI_rresp;
output AXI_LITE_SPI_rvalid;
input [31:0]AXI_LITE_SPI_wdata;
output AXI_LITE_SPI_wready;
input [3:0]AXI_LITE_SPI_wstrb;
input AXI_LITE_SPI_wvalid;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
wire [6:0]AXI_LITE_1_ARADDR;
wire AXI_LITE_1_ARREADY;
wire AXI_LITE_1_ARVALID;
wire [6:0]AXI_LITE_1_AWADDR;
wire AXI_LITE_1_AWREADY;
wire AXI_LITE_1_AWVALID;
wire AXI_LITE_1_BREADY;
wire [1:0]AXI_LITE_1_BRESP;
wire AXI_LITE_1_BVALID;
wire [31:0]AXI_LITE_1_RDATA;
wire AXI_LITE_1_RREADY;
wire [1:0]AXI_LITE_1_RRESP;
wire AXI_LITE_1_RVALID;
wire [31:0]AXI_LITE_1_WDATA;
wire AXI_LITE_1_WREADY;
wire [3:0]AXI_LITE_1_WSTRB;
wire AXI_LITE_1_WVALID;
wire [8:0]S_AXI_1_ARADDR;
wire S_AXI_1_ARREADY;
wire S_AXI_1_ARVALID;
wire [8:0]S_AXI_1_AWADDR;
wire S_AXI_1_AWREADY;
wire S_AXI_1_AWVALID;
wire S_AXI_1_BREADY;
wire [1:0]S_AXI_1_BRESP;
wire S_AXI_1_BVALID;
wire [31:0]S_AXI_1_RDATA;
wire S_AXI_1_RREADY;
wire [1:0]S_AXI_1_RRESP;
wire S_AXI_1_RVALID;
wire [31:0]S_AXI_1_WDATA;
wire S_AXI_1_WREADY;
wire [3:0]S_AXI_1_WSTRB;
wire S_AXI_1_WVALID;
wire [0:0]axi_gpio_0_gpio_io_o;
wire [0:0]axi_gpio_0_gpio_io_t;
wire axi_quad_spi_0_io0_o;
wire axi_quad_spi_0_io0_t;
wire axi_quad_spi_0_io1_o;
wire axi_quad_spi_0_io1_t;
wire axi_quad_spi_0_sck_o;
wire axi_quad_spi_0_sck_t;
wire ext_spi_clk_1;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire pmod_bridge_0_in0_I;
wire pmod_bridge_0_in1_I;
wire pmod_bridge_0_in2_I;
wire pmod_bridge_0_in3_I;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
assign AXI_LITE_1_ARADDR = AXI_LITE_SPI_araddr[6:0];
assign AXI_LITE_1_ARVALID = AXI_LITE_SPI_arvalid;
assign AXI_LITE_1_AWADDR = AXI_LITE_SPI_awaddr[6:0];
assign AXI_LITE_1_AWVALID = AXI_LITE_SPI_awvalid;
assign AXI_LITE_1_BREADY = AXI_LITE_SPI_bready;
assign AXI_LITE_1_RREADY = AXI_LITE_SPI_rready;
assign AXI_LITE_1_WDATA = AXI_LITE_SPI_wdata[31:0];
assign AXI_LITE_1_WSTRB = AXI_LITE_SPI_wstrb[3:0];
assign AXI_LITE_1_WVALID = AXI_LITE_SPI_wvalid;
assign AXI_LITE_GPIO_arready = S_AXI_1_ARREADY;
assign AXI_LITE_GPIO_awready = S_AXI_1_AWREADY;
assign AXI_LITE_GPIO_bresp[1:0] = S_AXI_1_BRESP;
assign AXI_LITE_GPIO_bvalid = S_AXI_1_BVALID;
assign AXI_LITE_GPIO_rdata[31:0] = S_AXI_1_RDATA;
assign AXI_LITE_GPIO_rresp[1:0] = S_AXI_1_RRESP;
assign AXI_LITE_GPIO_rvalid = S_AXI_1_RVALID;
assign AXI_LITE_GPIO_wready = S_AXI_1_WREADY;
assign AXI_LITE_SPI_arready = AXI_LITE_1_ARREADY;
assign AXI_LITE_SPI_awready = AXI_LITE_1_AWREADY;
assign AXI_LITE_SPI_bresp[1:0] = AXI_LITE_1_BRESP;
assign AXI_LITE_SPI_bvalid = AXI_LITE_1_BVALID;
assign AXI_LITE_SPI_rdata[31:0] = AXI_LITE_1_RDATA;
assign AXI_LITE_SPI_rresp[1:0] = AXI_LITE_1_RRESP;
assign AXI_LITE_SPI_rvalid = AXI_LITE_1_RVALID;
assign AXI_LITE_SPI_wready = AXI_LITE_1_WREADY;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_1_ARADDR = AXI_LITE_GPIO_araddr[8:0];
assign S_AXI_1_ARVALID = AXI_LITE_GPIO_arvalid;
assign S_AXI_1_AWADDR = AXI_LITE_GPIO_awaddr[8:0];
assign S_AXI_1_AWVALID = AXI_LITE_GPIO_awvalid;
assign S_AXI_1_BREADY = AXI_LITE_GPIO_bready;
assign S_AXI_1_RREADY = AXI_LITE_GPIO_rready;
assign S_AXI_1_WDATA = AXI_LITE_GPIO_wdata[31:0];
assign S_AXI_1_WSTRB = AXI_LITE_GPIO_wstrb[3:0];
assign S_AXI_1_WVALID = AXI_LITE_GPIO_wvalid;
assign ext_spi_clk_1 = ext_spi_clk;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodJSTK_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i(pmod_bridge_0_in0_I),
.gpio_io_o(axi_gpio_0_gpio_io_o),
.gpio_io_t(axi_gpio_0_gpio_io_t),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_ARREADY),
.s_axi_arvalid(S_AXI_1_ARVALID),
.s_axi_awaddr(S_AXI_1_AWADDR),
.s_axi_awready(S_AXI_1_AWREADY),
.s_axi_awvalid(S_AXI_1_AWVALID),
.s_axi_bready(S_AXI_1_BREADY),
.s_axi_bresp(S_AXI_1_BRESP),
.s_axi_bvalid(S_AXI_1_BVALID),
.s_axi_rdata(S_AXI_1_RDATA),
.s_axi_rready(S_AXI_1_RREADY),
.s_axi_rresp(S_AXI_1_RRESP),
.s_axi_rvalid(S_AXI_1_RVALID),
.s_axi_wdata(S_AXI_1_WDATA),
.s_axi_wready(S_AXI_1_WREADY),
.s_axi_wstrb(S_AXI_1_WSTRB),
.s_axi_wvalid(S_AXI_1_WVALID));
PmodJSTK_axi_quad_spi_0_0 axi_quad_spi_0
(.ext_spi_clk(ext_spi_clk_1),
.io0_i(pmod_bridge_0_in1_I),
.io0_o(axi_quad_spi_0_io0_o),
.io0_t(axi_quad_spi_0_io0_t),
.io1_i(pmod_bridge_0_in2_I),
.io1_o(axi_quad_spi_0_io1_o),
.io1_t(axi_quad_spi_0_io1_t),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(AXI_LITE_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(AXI_LITE_1_ARREADY),
.s_axi_arvalid(AXI_LITE_1_ARVALID),
.s_axi_awaddr(AXI_LITE_1_AWADDR),
.s_axi_awready(AXI_LITE_1_AWREADY),
.s_axi_awvalid(AXI_LITE_1_AWVALID),
.s_axi_bready(AXI_LITE_1_BREADY),
.s_axi_bresp(AXI_LITE_1_BRESP),
.s_axi_bvalid(AXI_LITE_1_BVALID),
.s_axi_rdata(AXI_LITE_1_RDATA),
.s_axi_rready(AXI_LITE_1_RREADY),
.s_axi_rresp(AXI_LITE_1_RRESP),
.s_axi_rvalid(AXI_LITE_1_RVALID),
.s_axi_wdata(AXI_LITE_1_WDATA),
.s_axi_wready(AXI_LITE_1_WREADY),
.s_axi_wstrb(AXI_LITE_1_WSTRB),
.s_axi_wvalid(AXI_LITE_1_WVALID),
.sck_i(pmod_bridge_0_in3_I),
.sck_o(axi_quad_spi_0_sck_o),
.sck_t(axi_quad_spi_0_sck_t),
.ss_i(1'b0));
PmodJSTK_pmod_bridge_0_0 pmod_bridge_0
(.in0_I(pmod_bridge_0_in0_I),
.in0_O(axi_gpio_0_gpio_io_o),
.in0_T(axi_gpio_0_gpio_io_t),
.in1_I(pmod_bridge_0_in1_I),
.in1_O(axi_quad_spi_0_io0_o),
.in1_T(axi_quad_spi_0_io0_t),
.in2_I(pmod_bridge_0_in2_I),
.in2_O(axi_quad_spi_0_io1_o),
.in2_T(axi_quad_spi_0_io1_t),
.in3_I(pmod_bridge_0_in3_I),
.in3_O(axi_quad_spi_0_sck_o),
.in3_T(axi_quad_spi_0_sck_t),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
endmodule
|
/*!
* <b>Module:</b>drp_other_registers
* @file drp_other_registers.v
* @date 2016-03-13
* @author Andrey Filippov
*
* @brief Additional registers controlled/read back over DRP
*
* @copyright Copyright (c) 2016 Elphel, Inc .
*
* <b>License:</b>
*
* drp_other_registers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* drp_other_registers.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*/
`timescale 1ns/1ps
module drp_other_registers#(
parameter DRP_ABITS = 8,
parameter DRP_REG0 = 8,
parameter DRP_REG1 = 9,
parameter DRP_REG2 = 10,
parameter DRP_REG3 = 11
)(
input drp_rst,
input drp_clk,
input drp_en, // @aclk strobes drp_ad
input drp_we,
input [DRP_ABITS-1:0] drp_addr,
input [15:0] drp_di,
output reg drp_rdy,
output reg [15:0] drp_do,
output [15:0] drp_register0,
output [15:0] drp_register1,
output [15:0] drp_register2,
output [15:0] drp_register3
);
reg [DRP_ABITS-1:0] drp_addr_r;
reg drp_wr_r;
reg [ 1:0] drp_rd_r;
reg [15:0] drp_di_r;
reg drp_reg0_set;
reg drp_reg1_set;
reg drp_reg2_set;
reg drp_reg3_set;
reg drp_reg0_get;
reg drp_reg1_get;
reg drp_reg2_get;
reg drp_reg3_get;
reg [15:0] drp_register0_r;
reg [15:0] drp_register1_r;
reg [15:0] drp_register2_r;
reg [15:0] drp_register3_r;
assign drp_register0 = drp_register0_r;
assign drp_register1 = drp_register1_r;
assign drp_register2 = drp_register2_r;
assign drp_register3 = drp_register3_r;
// DRP interface
always @ (posedge drp_clk) begin
drp_addr_r <= drp_addr;
drp_wr_r <= drp_we && drp_en;
drp_rd_r <= {drp_rd_r[0],~drp_we & drp_en};
drp_di_r <= drp_di;
drp_reg0_set <= drp_wr_r && (drp_addr_r == DRP_REG0);
drp_reg1_set <= drp_wr_r && (drp_addr_r == DRP_REG1);
drp_reg2_set <= drp_wr_r && (drp_addr_r == DRP_REG2);
drp_reg3_set <= drp_wr_r && (drp_addr_r == DRP_REG3);
drp_reg0_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG0);
drp_reg1_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG1);
drp_reg2_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG2);
drp_reg3_get <= drp_rd_r[0] && (drp_addr_r == DRP_REG3);
drp_rdy <= drp_wr_r || drp_rd_r[1];
drp_do <= ({16{drp_reg0_get}} & drp_register0_r) |
({16{drp_reg1_get}} & drp_register1_r) |
({16{drp_reg2_get}} & drp_register2_r) |
({16{drp_reg3_get}} & drp_register3_r);
if (drp_rst) drp_register0_r <= 0;
else if (drp_reg0_set) drp_register0_r <= drp_di_r;
if (drp_rst) drp_register1_r <= 0;
else if (drp_reg1_set) drp_register1_r <= drp_di_r;
if (drp_rst) drp_register2_r <= 0;
else if (drp_reg2_set) drp_register2_r <= drp_di_r;
if (drp_rst) drp_register3_r <= 0;
else if (drp_reg3_set) drp_register3_r <= drp_di_r;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 14:29:09 09/24/2015
// Design Name: KeyScanController
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/Lab2-Part2-Controller7SegmentDisplayKeypadScanner/KeyScanControlleTest.v
// Project Name: Lab2-Part2-Controller7SegmentDisplayKeypadScanner
////////////////////////////////////////////////////////////////////////////////
module KeyScanControllerTest;
reg Clock, Found, Reset, Start;
wire Load, Shift;
wire [2:0] CurrentState = uut.CurrentState;
wire StartTimer = uut.StartTimer;
wire TimerDone = uut.TimerDone;
defparam uut.Timer.Divider = 3;
KeyScanController uut(Clock, Found, Reset, Start, Load, Shift);
always #10 Clock = ~Clock;
initial begin
Clock = 0; Found = 0; Reset = 1; Start = 0; #25;
Start = 1; #20;
Reset = 0; #20;
Start = 0; #90;
Found = 1; #30;
Found = 0; #40;
Start = 1; #20;
Start = 0; #40;
Found = 1; #80;
Found = 0; #450;
$stop;
end
endmodule
|
`timescale 1ns / 10ps
module cic_decim_8_12_20(clk, cken_in, cken_out, decimrate, reset, din, dout);
input [11:0] din;
input [2:0] decimrate; /* Set to decimrate - 1*/
output [19:0] dout;
reg [19:0] dout;
input clk, cken_in, reset;
output cken_out;
reg cken_out;
reg [35:0] i0, i1, i2, i3, i4, i5, i6, i7;
reg [35:0] d0, d1, d2, d3, d4, d5, d6, d7;
reg [2:0] decimcount;
always @(posedge clk)
if(reset == 1'b1)
decimcount <= 0;
else if(cken_in == 1'b1)
begin
/* Integrators */
i0 = i0 + {{24{din[11]}}, din};
i1 = i1 + i0;
i2 = i2 + i1;
i3 = i3 + i2;
i4 = i4 + i3;
i5 = i5 + i4;
i6 = i6 + i5;
i7 = i7 + i6;
/* Decimator */
if(decimcount == 0)
begin
decimcount <= decimrate;
cken_out <= 1'b1;
/* Differentiators */
d0 <= i7 - d0;
d1 <= d0 - d1;
d2 <= d1 - d2;
d3 <= d2 - d3;
d4 <= d3 - d4;
d5 <= d4 - d5;
d6 <= d5 - d6;
d7 <= d6 - d7;
/* Bit shifter */
if(decimrate[2] == 1'b1)
dout <= d7[35:16];
else if(decimrate[1] == 1'b1)
dout <= d7[27:8];
else
dout <= d7[19:0];
end // if (decimcount == 0)
else
begin
decimcount = decimcount - 1;
cken_out <= 1'b0;
end // else: !if(decimcount == 0)
end // if (cken_in)
endmodule // cic_decim_8_12_18
|
`timescale 1 ns/100 ps
// Name: WcaCordic12.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaCordic12 (reset,ngreset,clock, strobeData, X0, Y0, A0, XN, YN, AN);
parameter BIT_WIDTH = 12;
parameter ITERATIONS = 12;
parameter MODE = 0; // vectoring mode: MODE=1, rotationg mode: MODE=0
input clock, reset, ngreset,strobeData;
input signed [BIT_WIDTH-1:0] X0, Y0, A0;
output signed [BIT_WIDTH-1:0] XN, YN, AN;
wire signed [BIT_WIDTH-1:0] x_w [ITERATIONS-1:1];
wire signed [BIT_WIDTH-1:0] y_w [ITERATIONS-1:1];
wire signed [BIT_WIDTH-1:0] a_w [ITERATIONS-1:1];
//Arctan LUT
localparam [143:0] arctanLUT = { 12'h0, 12'h1, 12'h1, 12'h3, 12'h5, 12'ha, 12'h14, 12'h29, 12'h51, 12'ha0, 12'h12e, 12'h200 };
// to make initial connection with inputs
CordicCalc #(0,MODE,BIT_WIDTH) pcc_0(.reset(reset), .ngreset(ngreset), .clock(clock), .strobeData( strobeData),
.X0(X0), .Y0(Y0), .A0(A0), .aRom(arctanLUT[BIT_WIDTH-1:0]),
.XN(x_w[1]), .YN(y_w[1]), .AN(a_w[1]) );
genvar i;
generate for(i=1; i<ITERATIONS-1; i=i+1) begin: pcc_1
CordicCalc #(i,MODE,BIT_WIDTH) pcc_1(.reset(reset), .ngreset(ngreset), .clock(clock), .strobeData( strobeData),
.X0(x_w[i]), .Y0(y_w[i]), .A0(a_w[i]), .aRom(arctanLUT[(i+1)*BIT_WIDTH-1:i*BIT_WIDTH]),
.XN(x_w[i+1]), .YN(y_w[i+1]), .AN(a_w[i+1]) );
end
endgenerate
//make final connections with outputs
CordicCalc #(ITERATIONS-1,MODE,BIT_WIDTH) pcc_2(.reset(reset),.ngreset(ngreset),.clock(clock), .strobeData( strobeData),
.X0(x_w[ITERATIONS-1]), .Y0(y_w[ITERATIONS-1]), .A0(a_w[ITERATIONS-1]),
.aRom(arctanLUT[ITERATIONS*BIT_WIDTH-1:(ITERATIONS-1)*BIT_WIDTH]),
.XN(XN), .YN(YN), .AN(AN) );
endmodule
module CordicCalc(reset,ngreset,clock, strobeData, X0, Y0, A0, XN, YN, AN, aRom);
parameter RSHIFT = 0;
parameter MODE = 0; // vectoring mode: MODE=1, rotationg mode: MODE=0
parameter BIT_WIDTH = 12;
input reset, ngreset, clock, strobeData;
input signed [BIT_WIDTH-1:0] X0, Y0, A0;
input signed [BIT_WIDTH-1:0] aRom;
output signed [BIT_WIDTH-1:0] XN, YN, AN;
wire d;
reg signed [BIT_WIDTH-1:0] XN, YN, AN;
assign d = (MODE==0)? A0[BIT_WIDTH-1] : ~Y0[BIT_WIDTH-1]; // Sin : Sqrt
always @ (posedge clock or negedge ngreset) begin
if(!ngreset) begin
AN <= 0;
XN <= 0;
YN <= 0;
end
else
if(reset) begin
AN <= 0;
XN <= 0;
YN <= 0;
end
else
if (d & strobeData) begin
AN <= A0 + aRom;
XN <= X0 + (Y0>>>RSHIFT);
YN <= Y0 - (X0>>>RSHIFT);
end
else if (strobeData) begin
AN <= A0 - aRom;
XN <= X0 - (Y0>>>RSHIFT);
YN <= Y0 + (X0>>>RSHIFT);
end // processing
end // always
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND2B_PP_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__A21O_PP_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a21o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : DNA_PORTE2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 06/07/13 - Initial version.
// 08/27/13 - Added timing support.
// 01/21/14 - Added missing timing (CR 767382).
// 05/28/14 - New simulation library message format.
// 10/02/14 - Fixed shift in order.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//`celldefine
module DNA_PORTE2 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000
)(
output DOUT,
input CLK,
input DIN,
input READ,
input SHIFT
);
reg [95:0] SIM_DNA_VALUE_reg = SIM_DNA_VALUE;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DNA_PORTE2_dr.v"
`endif
tri0 GSR = glbl.GSR;
localparam MAX_DNA_BITS = 96;
localparam MSB_DNA_BITS = MAX_DNA_BITS - 1;
reg [MSB_DNA_BITS:0] dna_val = SIM_DNA_VALUE;
reg dout_out;
`ifdef XIL_TIMING //Simprim
reg notifier;
`endif
wire clk_in;
wire din_in;
wire read_in;
wire shift_in;
wire clk_delay;
wire din_delay;
wire read_delay;
wire shift_delay;
localparam MODULE_NAME = "DNA_PORTE2";
assign DOUT = dout_out;
`ifdef XIL_TIMING // inputs with timing checks
assign clk_in = clk_delay;
assign din_in = din_delay;
assign read_in = read_delay;
assign shift_in = shift_delay;
`endif // `ifdef XIL_TIMING
`ifndef XIL_TIMING // inputs with timing checks
assign clk_in = CLK;
assign din_in = DIN;
assign read_in = READ;
assign shift_in = SHIFT;
`endif // `ifndef XIL_TIMING
initial
if ((SIM_DNA_VALUE_reg < 96'h000000000000000000000000) || (SIM_DNA_VALUE_reg > 96'hFFFFFFFFFFFFFFFFFFFFFFFD)) begin
$display("Error: [Unisim %s-101] SIM_DNA_VALUE attribute is set to %h. Legal values for this attribute are 96'h000000000000000000000000 to 96'hFFFFFFFFFFFFFFFFFFFFFFFD. Instance: %m", MODULE_NAME, SIM_DNA_VALUE_reg);
#1 $finish;
end
always @(posedge clk_in) begin
if(read_in == 1'b1) begin
dna_val = SIM_DNA_VALUE_reg;
dout_out = SIM_DNA_VALUE_reg[0];
end // read_in == 1'b1
else if(read_in == 1'b0)
if(shift_in == 1'b1) begin
dna_val = {din_in, dna_val[MSB_DNA_BITS : 1]};
dout_out = dna_val[0];
end // shift_in == 1'b1
end // always @ (posedge clk_in)
specify
(CLK => DOUT) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING // Simprim
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier,,, clk_delay, din_delay);
$setuphold (posedge CLK, negedge READ, 0:0:0, 0:0:0, notifier,,, clk_delay, read_delay);
$setuphold (posedge CLK, negedge SHIFT, 0:0:0, 0:0:0, notifier,,, clk_delay, shift_delay);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier,,, clk_delay, din_delay);
$setuphold (posedge CLK, posedge READ, 0:0:0, 0:0:0, notifier,,, clk_delay, read_delay);
$setuphold (posedge CLK, posedge SHIFT, 0:0:0, 0:0:0, notifier,,, clk_delay, shift_delay);
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
//`endcelldefine
|
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