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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_4_V
`define SKY130_FD_SC_LS__HA_4_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ha_4 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ha_4 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DECAPHETAP_PP_SYMBOL_V
/**
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decaphetap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX2I_2_V
`define SKY130_FD_SC_LS__MUX2I_2_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux2i_2 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__mux2i_2 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX2I_2_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:34:12 11/19/2013
// Design Name: top_module
// Module Name: C:/Users/Fabian/Desktop/Respaldo taller/taller-diseno-digital-master/Proyecto Final/tec-drums/top_module_test.v
// Project Name: tec-drums
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module top_module_test;
// Inputs
reg clock;
reg reset;
// Outputs
wire lrck;
wire mclk;
wire sdin;
wire sclk;
wire [15:0] left_data_o;
wire [15:0] right_data_o;
// Instantiate the Unit Under Test (UUT)
top_module uut (
.clock(clock),
.reset(reset),
.lrck(lrck),
.mclk(mclk),
.sdin(sdin),
.left_data_o(left_data_o),
.right_data_o(right_data_o)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
module vid_timer16(clk,
rst_n,
vid_sync,
vid_time,
x,
y
);
input clk;
input rst_n;
output reg vid_sync;
output vid_time;
output reg[8:0] x;
output reg[8:0] y;
//50Mhz
//parameter FULL_TIMER = 3174;
//parameter HALF_TIMER = 1587;
//parameter TIMEA = 3174-235;
//parameter TIMEB = 1587-235;
//16Mhz
parameter FULL_TIMER = 1016;
parameter HALF_TIMER = 507;
parameter TIMEA = 1016-75;
parameter TIMEB = 507-75;
reg[10:0] sf_cnt;
reg[11:0] timer;
wire hs_time;
wire hs1_time;
reg[7:0] h_pulse;
reg[7:0] h1_pulse;
reg[4:0] state;
reg hs;
reg vid_time;
reg[4:0] x_timer;
always @(posedge clk) begin
vid_sync <= (~hs) ^ (h_pulse!=0 && (state != 1 && state!=5)) ^ (h1_pulse!=0 && (state==1 || state==5 ));
end
always @(posedge clk) begin
if(rst_n==0) begin
sf_cnt <= 0;
end else begin
//if(timer==3174 || timer==1587) begin
if(timer==FULL_TIMER || timer==HALF_TIMER) begin
sf_cnt <= (sf_cnt==1049) ? 11'h0 : sf_cnt+11'h1; //was 625
end
end
end
//assign hs_time = (timer==0 || (( sf_cnt<=17 || (sf_cnt>=524 && sf_cnt<=541 )) && timer==1587) );
//assign hs1_time = (state==1 && (timer==1587 || timer==(3174-235)) ) ||
// (state==5 && (timer==(3174-235)) || (timer==(1587-235)) );
assign hs_time = (timer==0 || (( sf_cnt<=17 || (sf_cnt>=524 && sf_cnt<=541 )) && timer==HALF_TIMER) );
assign hs1_time = (state==1 && (timer==HALF_TIMER || timer==TIMEA) ) ||
(state==5 && (timer==TIMEA) || (timer==TIMEB) );
always @(posedge clk) begin
if(rst_n==0) begin
hs <= 1;
state <= 0;
end else begin
case( state)
5'h0: begin //hs_pre_a
hs <= 0;
if(sf_cnt== 6) state <= 5'h1; //hsync time
end
5'h1: begin //hs_a
hs <= 1;
if(sf_cnt== 12) state <= 5'h2; //hsync time
end
5'h2: begin //hs_post_a
hs <= 0;
if(sf_cnt== 18) state <= 5'h3; //hsync time
end
5'h3: begin //vert
hs <= 0;
//if(sf_cnt== 524) state <= 5'h4; //hsync time
if(sf_cnt== 525) state <= 5'h4; //hsync time
end
5'h4: begin //hs_pre_b
hs <= 0;
if(sf_cnt== 531) state <= 5'h5; //hsync time
end
5'h5: begin //hs_b
hs <= 1;
if(sf_cnt== 537) state <= 5'h6; //hsync time
end
5'h6: begin //hs_post_a
hs <= 0;
if(sf_cnt== 542) state <= 5'h7; //hsync time
end
5'h7: begin //vert
hs <= 0;
if(sf_cnt== 1049) state <= 5'h0; //hsync time
end
endcase
end
end
always @(posedge clk) begin
if(rst_n==0) begin
vid_time <= 0;
x_timer <= 5'h0;
end else begin
vid_time <= (((state==3 && sf_cnt>21) || (state==7 && sf_cnt>545)) && h_pulse==0 && hs_time==0 ) ? 1'b1 : 1'b0;
x_timer <= (vid_time ==1'b0 || x_timer==3) ? 5'h0 : x_timer+1 ;
end
end
always @(posedge clk) begin
x <= (vid_time ==1'b0) ? 9'h000 : x_timer==3 ? x+1 : x;
end
always @(posedge clk) begin
y <= (state==3 && sf_cnt==22) ? 8'h00 : (state==7 && sf_cnt==546) ? 9'h001 : (timer==0) ? y+9'h002 : y;
end
always @(posedge clk) begin
if(rst_n==0) begin
h_pulse <= 8'h0;
h1_pulse <= 8'h0;
end else begin
h_pulse <= (hs_time ==1'b1 ) ? 75 : (h_pulse !=0) ? h_pulse -1 : 0;
h1_pulse <= (hs1_time==1'b1 ) ? 75 : (h1_pulse !=0) ? h1_pulse -1 : 0;
end
end
always @(posedge clk) begin
if(rst_n==0) begin
timer <= 12'h0;
end else begin
//timer <= (timer==3174) ? 12'h0 : timer+12'h001;
timer <= (timer==FULL_TIMER) ? 12'h0 : timer+12'h001;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: ram2port
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Max10, Cyclone IV and Cyclone 10 LP devices
// Tool versions: Altera Quartus Prime
// Description: simple line-multiplying
//
// Features: ip independent implementation of a ram (two port)
//
//////////////////////////////////////////////////////////////////////////////////
module ram2port(
wrCLK,
wren,
wrpage,
wraddr,
wrdata,
rdCLK,
rden,
rdpage,
rdaddr,
rddata
);
parameter num_of_pages = 1;
parameter pagesize = 1024;
parameter data_width = 32;
`define PAGE_WIDTH $clog2(num_of_pages)
`define ADDR_WIDTH $clog2(pagesize)
`define MEM_SPACE num_of_pages*pagesize
`define MEM_WIDTH $clog2(`MEM_SPACE)
input wrCLK;
input wren;
input [`PAGE_WIDTH-1:0] wrpage;
input [`ADDR_WIDTH-1:0] wraddr;
input [ data_width-1:0] wrdata;
input rdCLK;
input rden;
input [`PAGE_WIDTH-1:0] rdpage;
input [`ADDR_WIDTH-1:0] rdaddr;
output reg [ data_width-1:0] rddata;
reg [data_width-1:0] data_buf[0:`MEM_SPACE-1];
wire [31:0] wrpageoffset = (pagesize * wrpage);
reg wren_r = 1'b0;
reg [`MEM_WIDTH-1:0] wrmem_r = {`MEM_WIDTH{1'b0}};
reg [data_width-1:0] wrdata_r = {data_width{1'b0}};
always @(posedge wrCLK) begin
if ((wrpage < num_of_pages) && (wraddr < pagesize))
wren_r <= wren;
else
wren_r <= 1'b0; // do not write to invalid input pages or addresses
wrmem_r <= wrpageoffset[`MEM_WIDTH-1:0] + wraddr;
wrdata_r <= wrdata;
if (wren_r)
data_buf[wrmem_r] <= wrdata_r;
end
wire [31:0] rdpageoffset = (pagesize * rdpage);
reg rden_r = 1'b0;
reg [`MEM_WIDTH-1:0] rdmem_r = {`MEM_WIDTH{1'b0}};
always @(posedge rdCLK) begin
if ((rdpage < num_of_pages) && (rdaddr < pagesize))
rden_r <= rden;
else
rden_r <= 1'b0; // do not read from invalid input pages or addresses
rdmem_r <= rdpageoffset[`MEM_WIDTH-1:0] + rdaddr;
if (rden_r)
rddata <= data_buf[rdmem_r];
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
// licenses this file to you under the Apache License, Version 2.0
// (the "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// code distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module novena_fpga_tb;
// CPU EIM register interface mapping
reg EIM_BCLK;
reg [1:0] EIM_CS;
reg [18:16] EIM_A;
reg EIM_LBA;
reg EIM_OE;
reg EIM_RW;
wire [15:0] EIM_DA;
reg [15:0] EIM_DA_out;
wire [15:0] EIM_DA_in;
wire EIM_DA_t;
////// expansion connector side mapping
// CPU->DUT mappings bank A
wire F_LVDS_P15;
wire F_LVDS_N15;
wire F_LVDS_P0;
wire F_LVDS_N0;
wire F_LVDS_CK1_P;
wire F_LVDS_CK1_N;
wire F_DX14;
wire F_LVDS_P4;
// CPU->DUT mappings bank B
wire F_LVDS_P11;
wire F_LVDS_N11;
wire F_DX1;
wire F_LVDS_NC;
wire F_LVDS_PC;
wire F_DX17;
wire F_LVDS_NB;
wire F_LVDS_PB;
wire F_LVDS_P7; // OE_N control for CPU->DUT bank A mappings
wire F_LVDS_N7; // OE_N control for CPU->DUT bank B mappings
// DUT->CPU mappings
reg F_DX18;
reg F_LVDS_CK0_N;
reg F_LVDS_CK0_P;
reg F_LVDS_P9;
reg F_DX0;
reg F_DX3;
reg F_DX2;
reg F_DX11;
/// board control
wire F_DX15; // output voltage select; 1 = Low V; 0 = 5V
reg F_LVDS_NA; // OC flag
/// ADC
wire F_DX13; // CS
wire F_DX7; // SCLK
wire F_DX6; // DIN
reg F_DX12; // DOUT
reg I2C3_SCL;
wire I2C3_SDA;
reg I2C3_SDA_out;
wire I2C3_SDA_in;
reg I2C3_SDA_t;
//// clocks n stuff
reg CLK2_N; // free-runs at 50 MHz
reg CLK2_P;
wire FPGA_LED2;
reg RESETBMCU;
wire APOPTOSIS;
wire [15:0] eim_dout;
wire [15:0] eim_din;
wire clk; // free-runs at 50 MHz, unbuffered
wire clk50; // zero-delay, DLL version of above. Use this.
wire bclk; // NOTE: doesn't run until first CPU access to EIM; then free-runs at 133 MHz
reg [23:0] counter;
wire reset;
wire bclk_dll, bclk_div2_dll, bclk_div4_dll, bclk_locked;
wire bclk_early;
wire bclk_i, bclk_o;
wire clk25;
////////////
// This code section is specific to the GPBB
//
// The rest of the code is generic to creating EIM/I2C interfaces in the FPGA
////////////
wire [7:0] cpu_to_dutA; // this set of wires connected to EIM registers below
wire [7:0] cpu_to_dutB;
wire drive_dutA_N;
wire drive_dutB_N;
wire [7:0] dut_to_cpu;
wire [15:0] gpbb_ctl;
wire [15:0] gpbb_stat;
/// the following is a set of board/pin-name to logical mappings
// CPU->DUT mappings bank A
assign F_LVDS_P15 = cpu_to_dutA[0];
assign F_LVDS_N15 = cpu_to_dutA[1];
assign F_LVDS_P0 = cpu_to_dutA[2];
assign F_LVDS_N0 = cpu_to_dutA[3];
assign F_LVDS_CK1_P = cpu_to_dutA[4];
assign F_LVDS_CK1_N = cpu_to_dutA[5];
assign F_DX14 = cpu_to_dutA[6];
assign F_LVDS_P4 = cpu_to_dutA[7];
// CPU->DUT mappings bank B
assign F_LVDS_P11 = cpu_to_dutB[0]; // LED 0
assign F_LVDS_N11 = cpu_to_dutB[1]; // LED 1
assign F_DX1 = cpu_to_dutB[2]; // LED 2
assign F_LVDS_NC = cpu_to_dutB[3]; // LED 3
assign F_LVDS_PC = cpu_to_dutB[4];
assign F_DX17 = cpu_to_dutB[5];
assign F_LVDS_NB = cpu_to_dutB[6];
assign F_LVDS_PB = cpu_to_dutB[7];
assign F_LVDS_P7 = drive_dutA_N; // OE_N control for CPU->DUT mappings
assign F_LVDS_N7 = drive_dutB_N; // OE_N control for CPU->DUT mappings
assign drive_dutA_N = !gpbb_ctl[0]; // invert so drive is true from programming model
assign drive_dutB_N = !gpbb_ctl[1]; // invert so drive is true from programming model
assign F_DX15 = !gpbb_ctl[15]; // bit 15 selects output voltage
// invert so from software, default 0 = low voltage; 1 = drive 5V
// DUT->CPU mappings
assign dut_to_cpu[0] = F_DX18;
assign dut_to_cpu[1] = F_LVDS_CK0_N;
assign dut_to_cpu[2] = F_LVDS_CK0_P;
assign dut_to_cpu[3] = F_LVDS_P9;
assign dut_to_cpu[4] = F_DX0;
assign dut_to_cpu[5] = F_DX3;
assign dut_to_cpu[6] = F_DX2;
assign dut_to_cpu[7] = F_DX11;
assign gpbb_stat[15:0] = {15'b0, F_LVDS_NA}; // tie unused lines to 0
// bit 0 is overcurrent flag
/////////////
// right, so fwiw, we map the ADC to the I2C bus.
// you can also map this to EIM by making registers that
// map to ADC wires, but this is an instructive example of
// how to use I2C-to-FPGA mappings with something reasonably generic.
// the I2C interface block is called i2c_slave and is near the bottom of this file
/// ADC
wire adc_go;
wire [2:0] adc_chan;
wire [9:0] adc_in;
wire adc_valid;
wire slowclk;
adc10cs022 adc10cs022 (
.DIG_ADC_CS(F_DX13),
.DIG_ADC_IN(F_DX6),
.DIG_ADC_OUT(F_DX12),
.DIG_ADC_SCLK(F_DX7),
.adc_in(adc_in),
.adc_chan(adc_chan),
.adc_valid(adc_valid),
.adc_go(adc_go),
.clk_3p2MHz(slowclk),
.reset(reset)
);
//////////////////////////////
///// The following code is used to create the EIM interface to the CPU
/////
///// Copy-and-paste the memory-mapped register templates to make
///// more control registers. If you're working on your own design,
///// I recommend you start with all the code below this area as a baseline.
/////
///// It's tricky to change code that relates to
///// the details of talking to the i.MX6 EIM -- it's difficult to
///// close timing, so you'll need to understand a bit about FPGA timing
///// closure to make chages to that section
//////////////////////////////
////////////////////////////////////
///// EIM Register set
/////
///// All registers split into write or read only blanks
/////
///// bank 0 maps to CS0 in EIM space, and the CPU timings should
///// be configured for "word mode" (e.g. 16-bit accesses) only
///// This address space has the fundamental C type of (unsigned short *)
///// 0x40000 - 0x40FFF is reserved for write-only bank 0
///// 0x41000 - 0x41FFF is reserved for read-only bank 0
/////
///// bank 1 maps to CS1 in EIM space. The CPU timings should be
///// configured for "burst mode". Accessing this space is most
///// efficient using memcpy() with a block size of 8 bytes, as all
///// registers in this space are 64-bit values. You can also try
///// using a fundamental C type of (unsigned long long *)
/////
///// 0xC040000 - 0xC040FFF is reserved for w/o bank 1
///// 0xC041000 - 0xC041FFF is reserved for r/o bank 1
////////////////////////////////////
////////// VERSION LOG (major version 000B) /////////////
////// by convention, I reserve 0x41FFC and 0x41FFE for
////// minor and major version codes, respectively
////// I try to give every FPGA design type a unique version
////// code, and keep track of the rev of the design with the
////// minor code.
//////
////// This particular design gets Major version 0xB.
//////
// Minor version 0001, October 19 2014
// Initial design to validate GPBB
//
reg cs0_r, rw_r;
reg [15:0] din_r;
reg [18:0] bus_addr_r;
reg adv_r;
reg cs0_in, rw_in, adv_in;
reg [15:0] din_in;
reg [2:0] a_in;
/// pipeline the inputs to allow for s/h closure
always @(posedge bclk_i) begin
cs0_in <= EIM_CS[0];
rw_in <= EIM_RW;
din_in <= eim_din;
adv_in <= !EIM_LBA; // latch address on LBA low
a_in <= EIM_A[18:16];
cs0_r <= cs0_in;
rw_r <= rw_in;
din_r <= din_in;
adv_r <= adv_in;
end
always @(posedge bclk_i) begin
if( adv_in ) begin
bus_addr_r <= {a_in, din_in};
end else begin
bus_addr_r <= bus_addr_r;
end
end
/// retime and mux between cs0 and cs1 banks on the output
wire [15:0] ro_d_b;
reg [15:0] ro_d_r;
reg [15:0] ro_d_b_r;
reg [1:0] eim_rdcs;
reg [15:0] eim_dout_pipe;
reg [15:0] eim_dout_pipe2;
always @(posedge bclk_i) begin
ro_d_b_r[15:0] <= ro_d_b[15:0];
end
always @(posedge bclk_dll) begin
ro_d_r <= ro_d;
eim_rdcs[1:0] <= EIM_CS[1:0];
eim_dout_pipe <= (eim_rdcs[1:0] == 2'b10) ? ro_d_r : ro_d_b_r;
end
always @(posedge bclk_o) begin
eim_dout_pipe2 <= eim_dout_pipe; // retime near the source to allow max time for wire delay
end;
wire [15:0] r40000wo;
wire [15:0] r40002wo;
wire [15:0] ro_d;
//////// write-only registers
reg_wo reg_wo_40000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40000),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( r40000wo[15:0] ) );
reg_wo reg_wo_40002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40002),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(1'b0), .rbk_d(ro_d), // unreadable for testing
.reg_d( r40002wo[15:0] ) );
reg_wo reg_wo_40010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40010),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( {cpu_to_dutB[7:0], cpu_to_dutA[7:0]} ) );
reg_wo reg_wo_40012 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h40012),
.bus_d(din_r), .we(!cs0_r && !rw_r), .re(!cs0_r && rw_r), .rbk_d(ro_d),
.reg_d( gpbb_ctl[15:0] ) );
//////// read-only registers
// loopback readback
reg_ro reg_ro_41000 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41000),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( r40000wo[15:0] ) );
reg_ro reg_ro_41002 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41002),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( r40002wo[15:0] ) );
reg_ro reg_ro_41010 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41010),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( {8'b0,dut_to_cpu[7:0]} ) );
reg_ro reg_ro_41012 ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41012),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( gpbb_stat[15:0] ) );
///////////////////////
// CS1 bank registers: minimum size here is 64-bit, tuned for synchronous burst access only
///////////////////////
wire [63:0] rC04_0000wo;
wire [63:0] rC04_0008wo;
///////// write registers
// loopback test
reg_wo_4burst reg_wo_4b_C04_0000( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_0000),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
reg_wo_4burst reg_wo_4b_C04_0008( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_0008),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
///////// read registers
// loopback test
reg_ro_4burst reg_ro_4b_C04_1000( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_1000),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0000wo[63:0] ), .rbk_d(ro_d_b) );
reg_ro_4burst reg_ro_4b_C04_1008( .clk(bclk_i), .bus_ad(eim_din), .my_a(19'h4_1008),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.reg_d( rC04_0008wo[63:0] ), .rbk_d(ro_d_b) );
// FPGA minor version code
reg_ro reg_ro_41FFC ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFC),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( 16'h0001 ) ); // minor version
// FPGA major version code
reg_ro reg_ro_41FFE ( .clk(bclk_dll), .bus_a(bus_addr_r), .my_a(19'h41FFE),
.bus_d(ro_d), .re(!cs0_r && rw_r),
.reg_d( 16'h000B ) ); // 000B is for GPBB release
////////////////////////////////////
///// I2C register set -- for those who don't want to use EIM
////////////////////////////////////
wire [7:0] reg_0_test;
wire SDA_pd;
wire SDA_int;
IOBUF #(.DRIVE(8), .SLEW("SLOW")) IOBUF_sda (.IO(I2C3_SDA), .I(1'b0), .T(!SDA_pd), .O(SDA_int));
i2c_slave i2c_slave(
.SCL(I2C3_SCL),
.SDA(SDA_int),
.SDA_pd(SDA_pd),
.clk(clk25), // nominally 26 MHz, this is close enough
.glbl_reset(reset),
.i2c_device_addr(8'h3C),
// outputs from I2C block (CPU->FPGA) 0-3F
.reg_0(reg_0_test),
.reg_2({adc_go,adc_chan[2:0]}),
// bit 2-0: ADC channel
// bit 3: initiate conversion
// inputs to I2C block (FPGA->CPU) 40-7F
.reg_40(adc_in[7:0]),
.reg_41({6'b0,adc_in[9:8]}),
.reg_42({7'b0, adc_valid}),
// ID / version code
// minor / major
.reg_fc(8'h00), .reg_fd(8'h02), .reg_fe(8'h00), .reg_ff(8'h04)
);
////////////////////////////////////
///// MASTER RESET
////////////////////////////////////
// synced to a 3.2MHz clock
sync_reset dll_res_sync( .glbl_reset(!RESETBMCU), .clk(slowclk), .reset(reset) );
////////////////////////////////////
///// BCLK DLL -- generate zero-delay clock plus slower versions for internal use
////////////////////////////////////
wire bclk_int_in, bclk_io_in;
IBUFG clkibufg (.I(EIM_BCLK), .O(bclk) );
BUFG bclk_dll_bufg(.I(bclk), .O(bclk_int_in) );
bclk_dll bclk_dll_mod( .clk133in(bclk_int_in), .clk133(bclk_dll),
.RESET(reset), .LOCKED(bclk_locked));
wire o_reset, o_locked;
wire i_fbk_out, i_fbk_in;
wire o_fbk_out, o_fbk_in;
dcm_delay bclk_i_dll( .clk133(bclk_int_in), .clk133out(bclk_i),
.CLKFB_IN(i_fbk_in), .CLKFB_OUT(i_fbk_out),
.RESET(reset), .LOCKED(i_locked));
dcm_delay bclk_o_dll( .clk133(bclk_int_in), .clk133out(bclk_o),
.CLKFB_IN(o_fbk_in), .CLKFB_OUT(o_fbk_out),
.RESET(reset), .LOCKED(o_locked));
// lock it to the input path
BUFIO2FB bclk_o_fbk(.I(bclk_o), .O(o_fbk_in)); // was this
// assign o_fbk_in = bclk_o;
// BUFG bclk_io_fbk(.I(bclk_io), .O(io_fbk_in));
assign i_fbk_in = bclk_i;
////////////////////////////////////
///// create 3.2MHz, 25MHz, and 50MHz buffered clocks from clk using DLL
////////////////////////////////////
wire dll_locked;
clk_dll clk_dll
(// Clock in ports
.clk50in(clk), // IN
// Clock out ports
.clk50(clk50), // OUT
.clk25(clk25), // OUT
.clk3p2(slowclk), // OUT
// Status and control signals
.RESET(!RESETBMCU),// IN
.LOCKED(dll_locked)); // OUT
//////////////
// Output pipeline registers -- explicit instantiation as their LOCs are controlled in the UCF.
//////////////
FDSE oddr2_eim0( .D( eim_dout_pipe2[0] ),
.C( bclk_o ),
.Q( eim_dout[0] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim1( .D( eim_dout_pipe2[1] ),
.C( bclk_o ),
.Q( eim_dout[1] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim2( .D( eim_dout_pipe2[2] ),
.C( bclk_o ),
.Q( eim_dout[2] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim3( .D( eim_dout_pipe2[3] ),
.C( bclk_o ),
.Q( eim_dout[3] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim4( .D( eim_dout_pipe2[4] ),
.C( bclk_o ),
.Q( eim_dout[4] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim5( .D( eim_dout_pipe2[5] ),
.C( bclk_o ),
.Q( eim_dout[5] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim6( .D( eim_dout_pipe2[6] ),
.C( bclk_o ),
.Q( eim_dout[6] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim7( .D( eim_dout_pipe2[7] ),
.C( bclk_o ),
.Q( eim_dout[7] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim8( .D( eim_dout_pipe2[8] ),
.C( bclk_o ),
.Q( eim_dout[8] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eim9( .D( eim_dout_pipe2[9] ),
.C( bclk_o ),
.Q( eim_dout[9] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eimA( .D( eim_dout_pipe2[10] ),
.C( bclk_o ),
.Q( eim_dout[10] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eimB( .D( eim_dout_pipe2[11] ),
.C( bclk_o ),
.Q( eim_dout[11] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eimC( .D( eim_dout_pipe2[12] ),
.C( bclk_o ),
.Q( eim_dout[12] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eimD( .D( eim_dout_pipe2[13] ),
.C( bclk_o ),
.Q( eim_dout[13] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eimE( .D( eim_dout_pipe2[14] ),
.C( bclk_o ),
.Q( eim_dout[14] ),
.CE( 1'b1 ), .S(1'b0) );
FDSE oddr2_eimF( .D( eim_dout_pipe2[15] ),
.C( bclk_o ),
.Q( eim_dout[15] ),
.CE( 1'b1 ), .S(1'b0) );
//////////////
/// "heartbeat" counter
//////////////
always @(posedge clk50) begin
counter <= counter + 1;
end
assign FPGA_LED2 = counter[23];
//////////////
// IOBUFs as required by design
//////////////
IBUFGDS clkibufgds( .I(CLK2_P), .IB(CLK2_N), .O(clk) );
reg [15:0] eim_d_t;
reg eim_lba_reg;
reg eim_oe_reg;
always @(posedge bclk_i) begin
eim_lba_reg <= EIM_LBA;
eim_oe_reg <= EIM_OE;
end
always @(posedge bclk_o) begin
eim_d_t[ 0] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 1] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 2] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 3] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 4] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 5] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 6] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 7] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 8] = eim_oe_reg | !eim_lba_reg;
eim_d_t[ 9] = eim_oe_reg | !eim_lba_reg;
eim_d_t[10] = eim_oe_reg | !eim_lba_reg;
eim_d_t[11] = eim_oe_reg | !eim_lba_reg;
eim_d_t[12] = eim_oe_reg | !eim_lba_reg;
eim_d_t[13] = eim_oe_reg | !eim_lba_reg;
eim_d_t[14] = eim_oe_reg | !eim_lba_reg;
eim_d_t[15] = eim_oe_reg | !eim_lba_reg;
end
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim0 (.IO(EIM_DA[ 0]), .I(eim_dout[ 0]), .T(eim_d_t[0]), .O(eim_din[ 0]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim1 (.IO(EIM_DA[ 1]), .I(eim_dout[ 1]), .T(eim_d_t[1]), .O(eim_din[ 1]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim2 (.IO(EIM_DA[ 2]), .I(eim_dout[ 2]), .T(eim_d_t[2]), .O(eim_din[ 2]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim3 (.IO(EIM_DA[ 3]), .I(eim_dout[ 3]), .T(eim_d_t[3]), .O(eim_din[ 3]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim4 (.IO(EIM_DA[ 4]), .I(eim_dout[ 4]), .T(eim_d_t[4]), .O(eim_din[ 4]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim5 (.IO(EIM_DA[ 5]), .I(eim_dout[ 5]), .T(eim_d_t[5]), .O(eim_din[ 5]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim6 (.IO(EIM_DA[ 6]), .I(eim_dout[ 6]), .T(eim_d_t[6]), .O(eim_din[ 6]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim7 (.IO(EIM_DA[ 7]), .I(eim_dout[ 7]), .T(eim_d_t[7]), .O(eim_din[ 7]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim8 (.IO(EIM_DA[ 8]), .I(eim_dout[ 8]), .T(eim_d_t[8]), .O(eim_din[ 8]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim9 (.IO(EIM_DA[ 9]), .I(eim_dout[ 9]), .T(eim_d_t[9]), .O(eim_din[ 9]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim10 (.IO(EIM_DA[10]), .I(eim_dout[10]), .T(eim_d_t[10]), .O(eim_din[10]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim11 (.IO(EIM_DA[11]), .I(eim_dout[11]), .T(eim_d_t[11]), .O(eim_din[11]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim12 (.IO(EIM_DA[12]), .I(eim_dout[12]), .T(eim_d_t[12]), .O(eim_din[12]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim13 (.IO(EIM_DA[13]), .I(eim_dout[13]), .T(eim_d_t[13]), .O(eim_din[13]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim14 (.IO(EIM_DA[14]), .I(eim_dout[14]), .T(eim_d_t[14]), .O(eim_din[14]));
IOBUF #(.DRIVE(12), .SLEW("FAST")) IOBUF_eim15 (.IO(EIM_DA[15]), .I(eim_dout[15]), .T(eim_d_t[15]), .O(eim_din[15]));
//////////////
// tie downs (unused signals as of this rev of design)
//////////////
assign APOPTOSIS = 1'b0; // make apoptosis inactive, tigh high to force reboot on config
//////////////
// Simulation testbench code
//////////////
parameter PERIOD_CLK = 16'd8; // 125 MHz
always begin
EIM_BCLK = 1'b0;
#(PERIOD_CLK/2) EIM_BCLK = 1'b1;
#(PERIOD_CLK/2);
end
parameter PERIOD_CLK2 = 16'd20; // 50 MHz
always begin
CLK2_N = 1'b0;
#(PERIOD_CLK2/2) CLK2_N = 1'b1;
#(PERIOD_CLK2/2);
end
always begin
CLK2_P = 1'b1;
#(PERIOD_CLK2/2) CLK2_P = 1'b0;
#(PERIOD_CLK2/2);
end
assign EIM_DA = EIM_DA_t ? 16'hZZZZ : EIM_DA_out;
assign EIM_DA_in = EIM_DA;
assign I2C3_SDA = I2C3_SDA_t ? 1'bZ : I2C3_SDA_out;
assign I2C3_SDA_in = I2C3_SDA;
assign EIM_DA_t = EIM_LBA;
task eim_rd_cycle_cs0;
input [18:0] adr;
begin
EIM_LBA = 0;
EIM_CS = 2'b10;
EIM_A[18:16] = adr[18:16];
EIM_RW = 1'b1;
EIM_DA_out = 16'h3042;
#(PERIOD_CLK);
EIM_DA_out = adr[15:0];
#(PERIOD_CLK);
EIM_LBA = 1;
EIM_DA_out = 16'hzzzz;
#(PERIOD_CLK*5);
#(PERIOD_CLK*16); // readback data here
EIM_CS = 2'b11;
end
endtask; // eim_rd_cycle_cs0
initial begin
EIM_CS = 2'b11;
EIM_A[18:16] = 3'b000;
EIM_LBA = 1'b0;
EIM_OE = 1'b1;
EIM_RW = 1'b0;
EIM_DA_out = 16'b0;
F_DX18 = 1'b0;
F_LVDS_CK0_N = 1'b0;
F_LVDS_CK0_P = 1'b0;
F_LVDS_P9 = 1'b0;
F_DX0 = 1'b0;
F_DX3 = 1'b0;
F_DX2 = 1'b0;
F_DX11 = 1'b0;
F_LVDS_NA = 1'b0;
F_DX12 = 1'b0;
I2C3_SDA_out = 1'b0;
I2C3_SDA_t = 1'b1;
RESETBMCU = 1'b0;
counter = 24'b0;
#(PERIOD_CLK*16);
RESETBMCU = 1'b1;
$stop;
#(PERIOD_CLK*16);
repeat( 10 ) begin
eim_rd_cycle_cs0(19'h41FFE); // read the version ID registers
#(PERIOD_CLK*30);
eim_rd_cycle_cs0(19'h41FFC);
#(PERIOD_CLK*30);
end
$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_8_V
`define SKY130_FD_SC_LS__NAND2_8_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_FUNCTIONAL_PP_V
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
// *********************************************************************************************************************
// IMPORTANT
// This helper block was chosen for exclusion from the IP core, and is therefore delivered within the example design.
// However, it is still customized for the chosen core configuration. If you wish to modify its behavior, refer to this
// core's Product Guide for possible guidance and be careful to understand the existing behavior and the effects of any
// modifications you may choose to make.
// *********************************************************************************************************************
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_ultrascale_tx_userclk #(
parameter integer P_CONTENTS = 0,
parameter integer P_FREQ_RATIO_SOURCE_TO_USRCLK = 1,
parameter integer P_FREQ_RATIO_USRCLK_TO_USRCLK2 = 1
)(
input wire gtwiz_userclk_tx_srcclk_in,
input wire gtwiz_userclk_tx_reset_in,
output wire gtwiz_userclk_tx_usrclk_out,
output wire gtwiz_userclk_tx_usrclk2_out,
output reg gtwiz_userclk_tx_active_out = 1'b0
);
// -------------------------------------------------------------------------------------------------------------------
// Local parameters
// -------------------------------------------------------------------------------------------------------------------
// Convert integer parameters with known, limited legal range to a 3-bit local parameter values
localparam integer P_USRCLK_INT_DIV = P_FREQ_RATIO_SOURCE_TO_USRCLK - 1;
localparam [2:0] P_USRCLK_DIV = P_USRCLK_INT_DIV[2:0];
localparam integer P_USRCLK2_INT_DIV = (P_FREQ_RATIO_SOURCE_TO_USRCLK * P_FREQ_RATIO_USRCLK_TO_USRCLK2) - 1;
localparam [2:0] P_USRCLK2_DIV = P_USRCLK2_INT_DIV[2:0];
// -------------------------------------------------------------------------------------------------------------------
// Transmitter user clocking network conditional generation, based on parameter values in module instantiation
// -------------------------------------------------------------------------------------------------------------------
generate if (1) begin: gen_gtwiz_userclk_tx_main
// Use BUFG_GT instance(s) to drive TXUSRCLK and TXUSRCLK2, inferred for integral source to TXUSRCLK frequency ratio
if (P_CONTENTS == 0) begin
// Drive TXUSRCLK with BUFG_GT-buffered source clock, dividing the input by the integral source clock to TXUSRCLK
// frequency ratio
BUFG_GT bufg_gt_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_tx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK_DIV),
.I (gtwiz_userclk_tx_srcclk_in),
.O (gtwiz_userclk_tx_usrclk_out)
);
// If TXUSRCLK and TXUSRCLK2 frequencies are identical, drive both from the same BUFG_GT. Otherwise, drive
// TXUSRCLK2 from a second BUFG_GT instance, dividing the source clock down to the TXUSRCLK2 frequency.
if (P_FREQ_RATIO_USRCLK_TO_USRCLK2 == 1)
assign gtwiz_userclk_tx_usrclk2_out = gtwiz_userclk_tx_usrclk_out;
else begin
BUFG_GT bufg_gt_usrclk2_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gtwiz_userclk_tx_reset_in),
.CLRMASK (1'b0),
.DIV (P_USRCLK2_DIV),
.I (gtwiz_userclk_tx_srcclk_in),
.O (gtwiz_userclk_tx_usrclk2_out)
);
end
// Indicate active helper block functionality when the BUFG_GT divider is not held in reset
always @(posedge gtwiz_userclk_tx_usrclk2_out, posedge gtwiz_userclk_tx_reset_in) begin
if (gtwiz_userclk_tx_reset_in)
gtwiz_userclk_tx_active_out <= 1'b0;
else
gtwiz_userclk_tx_active_out <= 1'b1;
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__OR2_PP_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_PP_BLACKBOX_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconstant_0_0 (
dout
);
output wire [4-1 : 0] dout;
xlconstant #(
.CONST_VAL(4'd3),
.CONST_WIDTH(4)
) inst (
.dout(dout)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_BLACKBOX_V
`define SKY130_FD_SC_MS__A31O_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_BLACKBOX_V
|
(** * Equiv: Program Equivalence *)
Set Warnings "-notation-overridden,-parsing".
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Lists.List.
Require Import Coq.Logic.FunctionalExtensionality.
Import ListNotations.
Require Import Maps.
Require Import Imp.
(** *** Some Advice for Working on Exercises:
- Most of the Coq proofs we ask you to do are similar to proofs
that we've provided. Before starting to work on exercises
problems, take the time to work through our proofs (both
informally, on paper, and in Coq) and make sure you understand
them in detail. This will save you a lot of time.
- The Coq proofs we're doing now are sufficiently complicated that
it is more or less impossible to complete them simply by random
experimentation or "following your nose." You need to start
with an idea about why the property is true and how the proof is
going to go. The best way to do this is to write out at least a
sketch of an informal proof on paper -- one that intuitively
convinces you of the truth of the theorem -- before starting to
work on the formal one. Alternately, grab a friend and try to
convince them that the theorem is true; then try to formalize
your explanation.
- Use automation to save work! The proofs in this chapter's
exercises can get pretty long if you try to write out all the
cases explicitly. *)
(* ################################################################# *)
(** * Behavioral Equivalence *)
(** In an earlier chapter, we investigated the correctness of a very
simple program transformation: the [optimize_0plus] function. The
programming language we were considering was the first version of
the language of arithmetic expressions -- with no variables -- so
in that setting it was very easy to define what it means for a
program transformation to be correct: it should always yield a
program that evaluates to the same number as the original.
To talk about the correctness of program transformations for the
full Imp language, including assignment and other commands, we
need to consider the role of variables and state. *)
(* ================================================================= *)
(** ** Definitions *)
(** For [aexp]s and [bexp]s with variables, the definition we want is
clear. We say that two [aexp]s or [bexp]s are _behaviorally
equivalent_ if they evaluate to the same result in every state. *)
Definition aequiv (a1 a2 : aexp) : Prop :=
forall (st:state),
aeval st a1 = aeval st a2.
Definition bequiv (b1 b2 : bexp) : Prop :=
forall (st:state),
beval st b1 = beval st b2.
(** Here are some simple examples of equivalences of arithmetic
and boolean expressions. *)
Theorem aequiv_example:
aequiv (AMinus (AId X) (AId X)) (ANum 0).
Proof.
intros st. simpl. omega.
Qed.
Theorem bequiv_example:
bequiv (BEq (AMinus (AId X) (AId X)) (ANum 0)) BTrue.
Proof.
intros st. unfold beval.
rewrite aequiv_example. reflexivity.
Qed.
(** For commands, the situation is a little more subtle. We can't
simply say "two commands are behaviorally equivalent if they
evaluate to the same ending state whenever they are started in the
same initial state," because some commands, when run in some
starting states, don't terminate in any final state at all! What
we need instead is this: two commands are behaviorally equivalent
if, for any given starting state, they either (1) both diverge
or (2) both terminate in the same final state. A compact way to
express this is "if the first one terminates in a particular state
then so does the second, and vice versa." *)
Definition cequiv (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st \\ st') <-> (c2 / st \\ st').
(* ================================================================= *)
(** ** Simple Examples *)
(** For examples of command equivalence, let's start by looking at
some trivial program transformations involving [SKIP]: *)
Theorem skip_left: forall c,
cequiv
(SKIP;; c)
c.
Proof.
(* WORKED IN CLASS *)
intros c st st'.
split; intros H.
- (* -> *)
inversion H. subst.
inversion H2. subst.
assumption.
- (* <- *)
apply E_Seq with st.
apply E_Skip.
assumption.
Qed.
(** **** Exercise: 2 stars (skip_right) *)
(** Prove that adding a [SKIP] after a command results in an
equivalent program *)
Theorem skip_right: forall c,
cequiv
(c ;; SKIP)
c.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Similarly, here is a simple transformation that optimizes [IFB]
commands: *)
Theorem IFB_true_simple: forall c1 c2,
cequiv
(IFB BTrue THEN c1 ELSE c2 FI)
c1.
Proof.
intros c1 c2.
split; intros H.
- (* -> *)
inversion H; subst. assumption. inversion H5.
- (* <- *)
apply E_IfTrue. reflexivity. assumption. Qed.
(** Of course, few programmers would be tempted to write a conditional
whose guard is literally [BTrue]. A more interesting case is when
the guard is _equivalent_ to true: *)
(** _Theorem_: If [b] is equivalent to [BTrue], then [IFB b THEN c1
ELSE c2 FI] is equivalent to [c1]. *)
(**
_Proof_:
- ([->]) We must show, for all [st] and [st'], that if [IFB b
THEN c1 ELSE c2 FI / st \\ st'] then [c1 / st \\ st'].
Proceed by cases on the rules that could possibly have been
used to show [IFB b THEN c1 ELSE c2 FI / st \\ st'], namely
[E_IfTrue] and [E_IfFalse].
- Suppose the final rule rule in the derivation of [IFB b THEN
c1 ELSE c2 FI / st \\ st'] was [E_IfTrue]. We then have, by
the premises of [E_IfTrue], that [c1 / st \\ st']. This is
exactly what we set out to prove.
- On the other hand, suppose the final rule in the derivation
of [IFB b THEN c1 ELSE c2 FI / st \\ st'] was [E_IfFalse].
We then know that [beval st b = false] and [c2 / st \\ st'].
Recall that [b] is equivalent to [BTrue], i.e., forall [st],
[beval st b = beval st BTrue]. In particular, this means
that [beval st b = true], since [beval st BTrue = true]. But
this is a contradiction, since [E_IfFalse] requires that
[beval st b = false]. Thus, the final rule could not have
been [E_IfFalse].
- ([<-]) We must show, for all [st] and [st'], that if [c1 / st
\\ st'] then [IFB b THEN c1 ELSE c2 FI / st \\ st'].
Since [b] is equivalent to [BTrue], we know that [beval st b] =
[beval st BTrue] = [true]. Together with the assumption that
[c1 / st \\ st'], we can apply [E_IfTrue] to derive [IFB b THEN
c1 ELSE c2 FI / st \\ st']. []
Here is the formal version of this proof: *)
Theorem IFB_true: forall b c1 c2,
bequiv b BTrue ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c1.
Proof.
intros b c1 c2 Hb.
split; intros H.
- (* -> *)
inversion H; subst.
+ (* b evaluates to true *)
assumption.
+ (* b evaluates to false (contradiction) *)
unfold bequiv in Hb. simpl in Hb.
rewrite Hb in H5.
inversion H5.
- (* <- *)
apply E_IfTrue; try assumption.
unfold bequiv in Hb. simpl in Hb.
rewrite Hb. reflexivity. Qed.
(** **** Exercise: 2 stars, recommended (IFB_false) *)
Theorem IFB_false: forall b c1 c2,
bequiv b BFalse ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (swap_if_branches) *)
(** Show that we can swap the branches of an IF if we also negate its
guard. *)
Theorem swap_if_branches: forall b e1 e2,
cequiv
(IFB b THEN e1 ELSE e2 FI)
(IFB BNot b THEN e2 ELSE e1 FI).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** For [WHILE] loops, we can give a similar pair of theorems. A loop
whose guard is equivalent to [BFalse] is equivalent to [SKIP],
while a loop whose guard is equivalent to [BTrue] is equivalent to
[WHILE BTrue DO SKIP END] (or any other non-terminating program).
The first of these facts is easy. *)
Theorem WHILE_false : forall b c,
bequiv b BFalse ->
cequiv
(WHILE b DO c END)
SKIP.
Proof.
intros b c Hb. split; intros H.
- (* -> *)
inversion H; subst.
+ (* E_WhileFalse *)
apply E_Skip.
+ (* E_WhileTrue *)
rewrite Hb in H2. inversion H2.
- (* <- *)
inversion H; subst.
apply E_WhileFalse.
rewrite Hb.
reflexivity. Qed.
(** **** Exercise: 2 stars, advanced, optional (WHILE_false_informal) *)
(** Write an informal proof of [WHILE_false].
(* FILL IN HERE *)
[]
*)
(** To prove the second fact, we need an auxiliary lemma stating that
[WHILE] loops whose guards are equivalent to [BTrue] never
terminate. *)
(** _Lemma_: If [b] is equivalent to [BTrue], then it cannot be the
case that [(WHILE b DO c END) / st \\ st'].
_Proof_: Suppose that [(WHILE b DO c END) / st \\ st']. We show,
by induction on a derivation of [(WHILE b DO c END) / st \\ st'],
that this assumption leads to a contradiction.
- Suppose [(WHILE b DO c END) / st \\ st'] is proved using rule
[E_WhileFalse]. Then by assumption [beval st b = false]. But
this contradicts the assumption that [b] is equivalent to
[BTrue].
- Suppose [(WHILE b DO c END) / st \\ st'] is proved using rule
[E_WhileTrue]. Then we are given the induction hypothesis
that [(WHILE b DO c END) / st \\ st'] is contradictory, which
is exactly what we are trying to prove!
- Since these are the only rules that could have been used to
prove [(WHILE b DO c END) / st \\ st'], the other cases of
the induction are immediately contradictory. [] *)
Lemma WHILE_true_nonterm : forall b c st st',
bequiv b BTrue ->
~( (WHILE b DO c END) / st \\ st' ).
Proof.
(* WORKED IN CLASS *)
intros b c st st' Hb.
intros H.
remember (WHILE b DO c END) as cw eqn:Heqcw.
induction H;
(* Most rules don't apply, and we can rule them out
by inversion *)
inversion Heqcw; subst; clear Heqcw.
(* The two interesting cases are the ones for WHILE loops: *)
- (* E_WhileFalse *) (* contradictory -- b is always true! *)
unfold bequiv in Hb.
(* [rewrite] is able to instantiate the quantifier in [st] *)
rewrite Hb in H. inversion H.
- (* E_WhileTrue *) (* immediate from the IH *)
apply IHceval2. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (WHILE_true_nonterm_informal) *)
(** Explain what the lemma [WHILE_true_nonterm] means in English.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars, recommended (WHILE_true) *)
(** Prove the following theorem. _Hint_: You'll want to use
[WHILE_true_nonterm] here. *)
Theorem WHILE_true: forall b c,
bequiv b BTrue ->
cequiv
(WHILE b DO c END)
(WHILE BTrue DO SKIP END).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A more interesting fact about [WHILE] commands is that any finite
number of copies of the body can be "unrolled" without changing
meaning. Unrolling is a common transformation in real compilers. *)
Theorem loop_unrolling: forall b c,
cequiv
(WHILE b DO c END)
(IFB b THEN (c ;; WHILE b DO c END) ELSE SKIP FI).
Proof.
(* WORKED IN CLASS *)
intros b c st st'.
split; intros Hce.
- (* -> *)
inversion Hce; subst.
+ (* loop doesn't run *)
apply E_IfFalse. assumption. apply E_Skip.
+ (* loop runs *)
apply E_IfTrue. assumption.
apply E_Seq with (st' := st'0). assumption. assumption.
- (* <- *)
inversion Hce; subst.
+ (* loop runs *)
inversion H5; subst.
apply E_WhileTrue with (st' := st'0).
assumption. assumption. assumption.
+ (* loop doesn't run *)
inversion H5; subst. apply E_WhileFalse. assumption. Qed.
(** **** Exercise: 2 stars, optional (seq_assoc) *)
Theorem seq_assoc : forall c1 c2 c3,
cequiv ((c1;;c2);;c3) (c1;;(c2;;c3)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Proving program properties involving assignments is one place
where the Functional Extensionality axiom often comes in handy. *)
Theorem identity_assignment : forall (X:id),
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
- (* -> *)
inversion H; subst. simpl.
replace (t_update st X (st X)) with st.
+ constructor.
+ apply functional_extensionality. intro.
rewrite t_update_same; reflexivity.
- (* <- *)
replace st' with (t_update st' X (aeval st' (AId X))).
+ inversion H. subst. apply E_Ass. reflexivity.
+ apply functional_extensionality. intro.
rewrite t_update_same. reflexivity.
Qed.
(** **** Exercise: 2 stars, recommended (assign_aequiv) *)
Theorem assign_aequiv : forall X e,
aequiv (AId X) e ->
cequiv SKIP (X ::= e).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (equiv_classes) *)
(** Given the following programs, group together those that are
equivalent in Imp. Your answer should be given as a list of lists,
where each sub-list represents a group of equivalent programs. For
example, if you think programs (a) through (h) are all equivalent
to each other, but not to (i), your answer should look like this:
[ [prog_a;prog_b;prog_c;prog_d;prog_e;prog_f;prog_g;prog_h] ;
[prog_i] ]
Write down your answer below in the definition of
[equiv_classes]. *)
Definition prog_a : com :=
WHILE BNot (BLe (AId X) (ANum 0)) DO
X ::= APlus (AId X) (ANum 1)
END.
Definition prog_b : com :=
IFB BEq (AId X) (ANum 0) THEN
X ::= APlus (AId X) (ANum 1);;
Y ::= ANum 1
ELSE
Y ::= ANum 0
FI;;
X ::= AMinus (AId X) (AId Y);;
Y ::= ANum 0.
Definition prog_c : com :=
SKIP.
Definition prog_d : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= APlus (AMult (AId X) (AId Y)) (ANum 1)
END.
Definition prog_e : com :=
Y ::= ANum 0.
Definition prog_f : com :=
Y ::= APlus (AId X) (ANum 1);;
WHILE BNot (BEq (AId X) (AId Y)) DO
Y ::= APlus (AId X) (ANum 1)
END.
Definition prog_g : com :=
WHILE BTrue DO
SKIP
END.
Definition prog_h : com :=
WHILE BNot (BEq (AId X) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END.
Definition prog_i : com :=
WHILE BNot (BEq (AId X) (AId Y)) DO
X ::= APlus (AId Y) (ANum 1)
END.
Definition equiv_classes : list (list com)
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(* ################################################################# *)
(** * Properties of Behavioral Equivalence *)
(** We next consider some fundamental properties of the program
equivalence relations. *)
(* ================================================================= *)
(** ** Behavioral Equivalence Is an Equivalence *)
(** First, we verify that the equivalences on [aexps], [bexps], and
[com]s really are _equivalences_ -- i.e., that they are reflexive,
symmetric, and transitive. The proofs are all easy. *)
Lemma refl_aequiv : forall (a : aexp), aequiv a a.
Proof.
intros a st. reflexivity. Qed.
Lemma sym_aequiv : forall (a1 a2 : aexp),
aequiv a1 a2 -> aequiv a2 a1.
Proof.
intros a1 a2 H. intros st. symmetry. apply H. Qed.
Lemma trans_aequiv : forall (a1 a2 a3 : aexp),
aequiv a1 a2 -> aequiv a2 a3 -> aequiv a1 a3.
Proof.
unfold aequiv. intros a1 a2 a3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_bequiv : forall (b : bexp), bequiv b b.
Proof.
unfold bequiv. intros b st. reflexivity. Qed.
Lemma sym_bequiv : forall (b1 b2 : bexp),
bequiv b1 b2 -> bequiv b2 b1.
Proof.
unfold bequiv. intros b1 b2 H. intros st. symmetry. apply H. Qed.
Lemma trans_bequiv : forall (b1 b2 b3 : bexp),
bequiv b1 b2 -> bequiv b2 b3 -> bequiv b1 b3.
Proof.
unfold bequiv. intros b1 b2 b3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_cequiv : forall (c : com), cequiv c c.
Proof.
unfold cequiv. intros c st st'. apply iff_refl. Qed.
Lemma sym_cequiv : forall (c1 c2 : com),
cequiv c1 c2 -> cequiv c2 c1.
Proof.
unfold cequiv. intros c1 c2 H st st'.
assert (c1 / st \\ st' <-> c2 / st \\ st') as H'.
{ (* Proof of assertion *) apply H. }
apply iff_sym. assumption.
Qed.
Lemma iff_trans : forall (P1 P2 P3 : Prop),
(P1 <-> P2) -> (P2 <-> P3) -> (P1 <-> P3).
Proof.
intros P1 P2 P3 H12 H23.
inversion H12. inversion H23.
split; intros A.
apply H1. apply H. apply A.
apply H0. apply H2. apply A. Qed.
Lemma trans_cequiv : forall (c1 c2 c3 : com),
cequiv c1 c2 -> cequiv c2 c3 -> cequiv c1 c3.
Proof.
unfold cequiv. intros c1 c2 c3 H12 H23 st st'.
apply iff_trans with (c2 / st \\ st'). apply H12. apply H23. Qed.
(* ================================================================= *)
(** ** Behavioral Equivalence Is a Congruence *)
(** Less obviously, behavioral equivalence is also a _congruence_.
That is, the equivalence of two subprograms implies the
equivalence of the larger programs in which they are embedded:
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;;c2) (c1';;c2')
...and so on for the other forms of commands. *)
(** (Note that we are using the inference rule notation here not
as part of a definition, but simply to write down some valid
implications in a readable format. We prove these implications
below.) *)
(** We will see a concrete example of why these congruence
properties are important in the following section (in the proof of
[fold_constants_com_sound]), but the main idea is that they allow
us to replace a small part of a large program with an equivalent
small part and know that the whole large programs are equivalent
_without_ doing an explicit proof about the non-varying parts --
i.e., the "proof burden" of a small change to a large program is
proportional to the size of the change, not the program. *)
Theorem CAss_congruence : forall i a1 a1',
aequiv a1 a1' ->
cequiv (CAss i a1) (CAss i a1').
Proof.
intros i a1 a2 Heqv st st'.
split; intros Hceval.
- (* -> *)
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity.
- (* <- *)
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity. Qed.
(** The congruence property for loops is a little more interesting,
since it requires induction.
_Theorem_: Equivalence is a congruence for [WHILE] -- that is, if
[b1] is equivalent to [b1'] and [c1] is equivalent to [c1'], then
[WHILE b1 DO c1 END] is equivalent to [WHILE b1' DO c1' END].
_Proof_: Suppose [b1] is equivalent to [b1'] and [c1] is
equivalent to [c1']. We must show, for every [st] and [st'], that
[WHILE b1 DO c1 END / st \\ st'] iff [WHILE b1' DO c1' END / st
\\ st']. We consider the two directions separately.
- ([->]) We show that [WHILE b1 DO c1 END / st \\ st'] implies
[WHILE b1' DO c1' END / st \\ st'], by induction on a
derivation of [WHILE b1 DO c1 END / st \\ st']. The only
nontrivial cases are when the final rule in the derivation is
[E_WhileFalse] or [E_WhileTrue].
- [E_WhileFalse]: In this case, the form of the rule gives us
[beval st b1 = false] and [st = st']. But then, since
[b1] and [b1'] are equivalent, we have [beval st b1' =
false], and [E-WhileFalse] applies, giving us [WHILE b1' DO
c1' END / st \\ st'], as required.
- [E_WhileTrue]: The form of the rule now gives us [beval st
b1 = true], with [c1 / st \\ st'0] and [WHILE b1 DO c1
END / st'0 \\ st'] for some state [st'0], with the
induction hypothesis [WHILE b1' DO c1' END / st'0 \\
st'].
Since [c1] and [c1'] are equivalent, we know that [c1' /
st \\ st'0]. And since [b1] and [b1'] are equivalent, we
have [beval st b1' = true]. Now [E-WhileTrue] applies,
giving us [WHILE b1' DO c1' END / st \\ st'], as
required.
- ([<-]) Similar. [] *)
Theorem CWhile_congruence : forall b1 b1' c1 c1',
bequiv b1 b1' -> cequiv c1 c1' ->
cequiv (WHILE b1 DO c1 END) (WHILE b1' DO c1' END).
Proof.
(* WORKED IN CLASS *)
unfold bequiv,cequiv.
intros b1 b1' c1 c1' Hb1e Hc1e st st'.
split; intros Hce.
- (* -> *)
remember (WHILE b1 DO c1 END) as cwhile
eqn:Heqcwhile.
induction Hce; inversion Heqcwhile; subst.
+ (* E_WhileFalse *)
apply E_WhileFalse. rewrite <- Hb1e. apply H.
+ (* E_WhileTrue *)
apply E_WhileTrue with (st' := st').
* (* show loop runs *) rewrite <- Hb1e. apply H.
* (* body execution *)
apply (Hc1e st st'). apply Hce1.
* (* subsequent loop execution *)
apply IHHce2. reflexivity.
- (* <- *)
remember (WHILE b1' DO c1' END) as c'while
eqn:Heqc'while.
induction Hce; inversion Heqc'while; subst.
+ (* E_WhileFalse *)
apply E_WhileFalse. rewrite -> Hb1e. apply H.
+ (* E_WhileTrue *)
apply E_WhileTrue with (st' := st').
* (* show loop runs *) rewrite -> Hb1e. apply H.
* (* body execution *)
apply (Hc1e st st'). apply Hce1.
* (* subsequent loop execution *)
apply IHHce2. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (CSeq_congruence) *)
Theorem CSeq_congruence : forall c1 c1' c2 c2',
cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (c1;;c2) (c1';;c2').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (CIf_congruence) *)
Theorem CIf_congruence : forall b b' c1 c1' c2 c2',
bequiv b b' -> cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (IFB b THEN c1 ELSE c2 FI)
(IFB b' THEN c1' ELSE c2' FI).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** For example, here are two equivalent programs and a proof of their
equivalence... *)
Example congruence_example:
cequiv
(* Program 1: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= ANum 0
ELSE
Y ::= ANum 42
FI)
(* Program 2: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= AMinus (AId X) (AId X) (* <--- changed here *)
ELSE
Y ::= ANum 42
FI).
Proof.
apply CSeq_congruence.
apply refl_cequiv.
apply CIf_congruence.
apply refl_bequiv.
apply CAss_congruence. unfold aequiv. simpl.
symmetry. apply minus_diag.
apply refl_cequiv.
Qed.
(** **** Exercise: 3 stars, advanced, optional (not_congr) *)
(** We've shown that the [cequiv] relation is both an equivalence and
a congruence on commands. Can you think of a relation on commands
that is an equivalence but _not_ a congruence? *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * Program Transformations *)
(** A _program transformation_ is a function that takes a program as
input and produces some variant of the program as output.
Compiler optimizations such as constant folding are a canonical
example, but there are many others. *)
(** A program transformation is _sound_ if it preserves the
behavior of the original program. *)
Definition atrans_sound (atrans : aexp -> aexp) : Prop :=
forall (a : aexp),
aequiv a (atrans a).
Definition btrans_sound (btrans : bexp -> bexp) : Prop :=
forall (b : bexp),
bequiv b (btrans b).
Definition ctrans_sound (ctrans : com -> com) : Prop :=
forall (c : com),
cequiv c (ctrans c).
(* ================================================================= *)
(** ** The Constant-Folding Transformation *)
(** An expression is _constant_ when it contains no variable
references.
Constant folding is an optimization that finds constant
expressions and replaces them by their values. *)
Fixpoint fold_constants_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2)
with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2)
with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2)
with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
Example fold_aexp_ex1 :
fold_constants_aexp
(AMult (APlus (ANum 1) (ANum 2)) (AId X))
= AMult (ANum 3) (AId X).
Proof. reflexivity. Qed.
(** Note that this version of constant folding doesn't eliminate
trivial additions, etc. -- we are focusing attention on a single
optimization for the sake of simplicity. It is not hard to
incorporate other ways of simplifying expressions; the definitions
and proofs just get longer. *)
Example fold_aexp_ex2 :
fold_constants_aexp
(AMinus (AId X) (APlus (AMult (ANum 0) (ANum 6))
(AId Y)))
= AMinus (AId X) (APlus (ANum 0) (AId Y)).
Proof. reflexivity. Qed.
(** Not only can we lift [fold_constants_aexp] to [bexp]s (in the
[BEq] and [BLe] cases); we can also look for constant _boolean_
expressions and evaluate them in-place. *)
Fixpoint fold_constants_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) =>
if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') =>
BEq a1' a2'
end
| BLe a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) =>
if leb n1 n2 then BTrue else BFalse
| (a1', a2') =>
BLe a1' a2'
end
| BNot b1 =>
match (fold_constants_bexp b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (fold_constants_bexp b1, fold_constants_bexp b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example fold_bexp_ex1 :
fold_constants_bexp (BAnd BTrue (BNot (BAnd BFalse BTrue)))
= BTrue.
Proof. reflexivity. Qed.
Example fold_bexp_ex2 :
fold_constants_bexp
(BAnd (BEq (AId X) (AId Y))
(BEq (ANum 0)
(AMinus (ANum 2) (APlus (ANum 1)
(ANum 1)))))
= BAnd (BEq (AId X) (AId Y)) BTrue.
Proof. reflexivity. Qed.
(** To fold constants in a command, we apply the appropriate folding
functions on all embedded expressions. *)
Fixpoint fold_constants_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (fold_constants_aexp a)
| c1 ;; c2 =>
(fold_constants_com c1) ;; (fold_constants_com c2)
| IFB b THEN c1 ELSE c2 FI =>
match fold_constants_bexp b with
| BTrue => fold_constants_com c1
| BFalse => fold_constants_com c2
| b' => IFB b' THEN fold_constants_com c1
ELSE fold_constants_com c2 FI
end
| WHILE b DO c END =>
match fold_constants_bexp b with
| BTrue => WHILE BTrue DO SKIP END
| BFalse => SKIP
| b' => WHILE b' DO (fold_constants_com c) END
end
end.
Example fold_com_ex1 :
fold_constants_com
(* Original program: *)
(X ::= APlus (ANum 4) (ANum 5);;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y))
(APlus (ANum 2) (ANum 4)) THEN
SKIP
ELSE
Y ::= ANum 0
FI;;
IFB BLe (ANum 0)
(AMinus (ANum 4) (APlus (ANum 2) (ANum 1)))
THEN
Y ::= ANum 0
ELSE
SKIP
FI;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END)
= (* After constant folding: *)
(X ::= ANum 9;;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (ANum 6) THEN
SKIP
ELSE
(Y ::= ANum 0)
FI;;
Y ::= ANum 0;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END).
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Soundness of Constant Folding *)
(** Now we need to show that what we've done is correct. *)
(** Here's the proof for arithmetic expressions: *)
Theorem fold_constants_aexp_sound :
atrans_sound fold_constants_aexp.
Proof.
unfold atrans_sound. intros a. unfold aequiv. intros st.
induction a; simpl;
(* ANum and AId follow immediately *)
try reflexivity;
(* APlus, AMinus, and AMult follow from the IH
and the observation that
aeval st (APlus a1 a2)
= ANum ((aeval st a1) + (aeval st a2))
= aeval st (ANum ((aeval st a1) + (aeval st a2)))
(and similarly for AMinus/minus and AMult/mult) *)
try (destruct (fold_constants_aexp a1);
destruct (fold_constants_aexp a2);
rewrite IHa1; rewrite IHa2; reflexivity). Qed.
(** **** Exercise: 3 stars, optional (fold_bexp_Eq_informal) *)
(** Here is an informal proof of the [BEq] case of the soundness
argument for boolean expression constant folding. Read it
carefully and compare it to the formal proof that follows. Then
fill in the [BLe] case of the formal proof (without looking at the
[BEq] case, if possible).
_Theorem_: The constant folding function for booleans,
[fold_constants_bexp], is sound.
_Proof_: We must show that [b] is equivalent to [fold_constants_bexp],
for all boolean expressions [b]. Proceed by induction on [b]. We
show just the case where [b] has the form [BEq a1 a2].
In this case, we must show
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
There are two cases to consider:
- First, suppose [fold_constants_aexp a1 = ANum n1] and
[fold_constants_aexp a2 = ANum n2] for some [n1] and [n2].
In this case, we have
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
and
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
By the soundness of constant folding for arithmetic
expressions (Lemma [fold_constants_aexp_sound]), we know
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
and
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
so
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
Also, it is easy to see (by considering the cases [n1 = n2] and
[n1 <> n2] separately) that
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
So
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
as required.
- Otherwise, one of [fold_constants_aexp a1] and
[fold_constants_aexp a2] is not a constant. In this case, we
must show
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
which, by the definition of [beval], is the same as showing
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
But the soundness of constant folding for arithmetic
expressions ([fold_constants_aexp_sound]) gives us
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
completing the case. []
*)
Theorem fold_constants_bexp_sound:
btrans_sound fold_constants_bexp.
Proof.
unfold btrans_sound. intros b. unfold bequiv. intros st.
induction b;
(* BTrue and BFalse are immediate *)
try reflexivity.
- (* BEq *)
rename a into a1. rename a0 into a2. simpl.
(** (Doing induction when there are a lot of constructors makes
specifying variable names a chore, but Coq doesn't always
choose nice variable names. We can rename entries in the
context with the [rename] tactic: [rename a into a1] will
change [a] to [a1] in the current goal and context.) *)
remember (fold_constants_aexp a1) as a1' eqn:Heqa1'.
remember (fold_constants_aexp a2) as a2' eqn:Heqa2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
(* The only interesting case is when both a1 and a2
become constants after folding *)
simpl. destruct (beq_nat n n0); reflexivity.
- (* BLe *)
(* FILL IN HERE *) admit.
- (* BNot *)
simpl. remember (fold_constants_bexp b) as b' eqn:Heqb'.
rewrite IHb.
destruct b'; reflexivity.
- (* BAnd *)
simpl.
remember (fold_constants_bexp b1) as b1' eqn:Heqb1'.
remember (fold_constants_bexp b2) as b2' eqn:Heqb2'.
rewrite IHb1. rewrite IHb2.
destruct b1'; destruct b2'; reflexivity.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (fold_constants_com_sound) *)
(** Complete the [WHILE] case of the following proof. *)
Theorem fold_constants_com_sound :
ctrans_sound fold_constants_com.
Proof.
unfold ctrans_sound. intros c.
induction c; simpl.
- (* SKIP *) apply refl_cequiv.
- (* ::= *) apply CAss_congruence.
apply fold_constants_aexp_sound.
- (* ;; *) apply CSeq_congruence; assumption.
- (* IFB *)
assert (bequiv b (fold_constants_bexp b)). {
apply fold_constants_bexp_sound. }
destruct (fold_constants_bexp b) eqn:Heqb;
try (apply CIf_congruence; assumption).
(* (If the optimization doesn't eliminate the if, then the
result is easy to prove from the IH and
[fold_constants_bexp_sound].) *)
+ (* b always true *)
apply trans_cequiv with c1; try assumption.
apply IFB_true; assumption.
+ (* b always false *)
apply trans_cequiv with c2; try assumption.
apply IFB_false; assumption.
- (* WHILE *)
(* FILL IN HERE *) Admitted.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Soundness of (0 + n) Elimination, Redux *)
(** **** Exercise: 4 stars, advanced, optional (optimize_0plus) *)
(** Recall the definition [optimize_0plus] from the \CHAPV1{Imp} chapter of _Logical
Foundations_:
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
Note that this function is defined over the old [aexp]s,
without states.
Write a new version of this function that accounts for variables,
plus analogous ones for [bexp]s and commands:
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
Prove that these three functions are sound, as we did for
[fold_constants_*]. Make sure you use the congruence lemmas in
the proof of [optimize_0plus_com] -- otherwise it will be _long_!
Then define an optimizer on commands that first folds
constants (using [fold_constants_com]) and then eliminates [0 + n]
terms (using [optimize_0plus_com]).
- Give a meaningful example of this optimizer's output.
- Prove that the optimizer is sound. (This part should be _very_
easy.) *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * Proving That Programs Are _Not_ Equivalent *)
(** Suppose that [c1] is a command of the form [X ::= a1;; Y ::= a2]
and [c2] is the command [X ::= a1;; Y ::= a2'], where [a2'] is
formed by substituting [a1] for all occurrences of [X] in [a2].
For example, [c1] and [c2] might be:
c1 = (X ::= 42 + 53;;
Y ::= Y + X)
c2 = (X ::= 42 + 53;;
Y ::= Y + (42 + 53))
Clearly, this _particular_ [c1] and [c2] are equivalent. Is this
true in general? *)
(** We will see in a moment that it is not, but it is worthwhile
to pause, now, and see if you can find a counter-example on your
own. *)
(** More formally, here is the function that substitutes an arithmetic
expression for each occurrence of a given variable in another
expression: *)
Fixpoint subst_aexp (i : id) (u : aexp) (a : aexp) : aexp :=
match a with
| ANum n =>
ANum n
| AId i' =>
if beq_id i i' then u else AId i'
| APlus a1 a2 =>
APlus (subst_aexp i u a1) (subst_aexp i u a2)
| AMinus a1 a2 =>
AMinus (subst_aexp i u a1) (subst_aexp i u a2)
| AMult a1 a2 =>
AMult (subst_aexp i u a1) (subst_aexp i u a2)
end.
Example subst_aexp_ex :
subst_aexp X (APlus (ANum 42) (ANum 53))
(APlus (AId Y) (AId X))
= (APlus (AId Y) (APlus (ANum 42) (ANum 53))).
Proof. reflexivity. Qed.
(** And here is the property we are interested in, expressing the
claim that commands [c1] and [c2] as described above are
always equivalent. *)
Definition subst_equiv_property := forall i1 i2 a1 a2,
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
(** Sadly, the property does _not_ always hold -- i.e., it is not the
case that, for all [i1], [i2], [a1], and [a2],
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
To see this, suppose (for a contradiction) that for all [i1], [i2],
[a1], and [a2], we have
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Consider the following program:
X ::= APlus (AId X) (ANum 1);; Y ::= AId X
Note that
(X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
/ empty_state \\ st1,
where [st1 = { X |-> 1, Y |-> 1 }].
By assumption, we know that
cequiv (X ::= APlus (AId X) (ANum 1);;
Y ::= AId X)
(X ::= APlus (AId X) (ANum 1);;
Y ::= APlus (AId X) (ANum 1))
so, by the definition of [cequiv], we have
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state \\ st1.
But we can also derive
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state \\ st2,
where [st2 = { X |-> 1, Y |-> 2 }]. But [st1 <> st2], which is a
contradiction, since [ceval] is deterministic! [] *)
Theorem subst_inequiv :
~ subst_equiv_property.
Proof.
unfold subst_equiv_property.
intros Contra.
(* Here is the counterexample: assuming that [subst_equiv_property]
holds allows us to prove that these two programs are
equivalent... *)
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= AId X)
as c1.
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= APlus (AId X) (ANum 1))
as c2.
assert (cequiv c1 c2) by (subst; apply Contra).
(* ... allows us to show that the command [c2] can terminate
in two different final states:
st1 = {X |-> 1, Y |-> 1}
st2 = {X |-> 1, Y |-> 2}. *)
remember (t_update (t_update empty_state X 1) Y 1) as st1.
remember (t_update (t_update empty_state X 1) Y 2) as st2.
assert (H1: c1 / empty_state \\ st1);
assert (H2: c2 / empty_state \\ st2);
try (subst;
apply E_Seq with (st' := (t_update empty_state X 1));
apply E_Ass; reflexivity).
apply H in H1.
(* Finally, we use the fact that evaluation is deterministic
to obtain a contradiction. *)
assert (Hcontra: st1 = st2)
by (apply (ceval_deterministic c2 empty_state); assumption).
assert (Hcontra': st1 Y = st2 Y)
by (rewrite Hcontra; reflexivity).
subst. inversion Hcontra'. Qed.
(** **** Exercise: 4 stars, optional (better_subst_equiv) *)
(** The equivalence we had in mind above was not complete nonsense --
it was actually almost right. To make it correct, we just need to
exclude the case where the variable [X] occurs in the
right-hand-side of the first assignment statement. *)
Inductive var_not_used_in_aexp (X:id) : aexp -> Prop :=
| VNUNum: forall n, var_not_used_in_aexp X (ANum n)
| VNUId: forall Y, X <> Y -> var_not_used_in_aexp X (AId Y)
| VNUPlus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (APlus a1 a2)
| VNUMinus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMinus a1 a2)
| VNUMult: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMult a1 a2).
Lemma aeval_weakening : forall i st a ni,
var_not_used_in_aexp i a ->
aeval (t_update st i ni) a = aeval st a.
Proof.
(* FILL IN HERE *) Admitted.
(** Using [var_not_used_in_aexp], formalize and prove a correct verson
of [subst_equiv_property]. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (inequiv_exercise) *)
(** Prove that an infinite loop is not equivalent to [SKIP] *)
Theorem inequiv_exercise:
~ cequiv (WHILE BTrue DO SKIP END) SKIP.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Extended Exercise: Nondeterministic Imp *)
(** As we have seen (in theorem [ceval_deterministic] in the [Imp]
chapter), Imp's evaluation relation is deterministic. However,
_non_-determinism is an important part of the definition of many
real programming languages. For example, in many imperative
languages (such as C and its relatives), the order in which
function arguments are evaluated is unspecified. The program
fragment
x = 0;;
f(++x, x)
might call [f] with arguments [(1, 0)] or [(1, 1)], depending how
the compiler chooses to order things. This can be a little
confusing for programmers, but it gives the compiler writer useful
freedom.
In this exercise, we will extend Imp with a simple
nondeterministic command and study how this change affects
program equivalence. The new command has the syntax [HAVOC X],
where [X] is an identifier. The effect of executing [HAVOC X] is
to assign an _arbitrary_ number to the variable [X],
nondeterministically. For example, after executing the program:
HAVOC Y;;
Z ::= Y * 2
the value of [Y] can be any number, while the value of [Z] is
twice that of [Y] (so [Z] is always even). Note that we are not
saying anything about the _probabilities_ of the outcomes -- just
that there are (infinitely) many different outcomes that can
possibly happen after executing this nondeterministic code.
In a sense, a variable on which we do [HAVOC] roughly corresponds
to an unitialized variable in a low-level language like C. After
the [HAVOC], the variable holds a fixed but arbitrary number. Most
sources of nondeterminism in language definitions are there
precisely because programmers don't care which choice is made (and
so it is good to leave it open to the compiler to choose whichever
will run faster).
We call this new language _Himp_ (``Imp extended with [HAVOC]''). *)
Module Himp.
(** To formalize Himp, we first add a clause to the definition of
commands. *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com. (* <---- new *)
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' l" := (CHavoc l) (at level 60).
(** **** Exercise: 2 stars (himp_ceval) *)
(** Now, we must extend the operational semantics. We have provided
a template for the [ceval] relation below, specifying the big-step
semantics. What rule(s) must be added to the definition of [ceval]
to formalize the behavior of the [HAVOC] command? *)
Reserved Notation "c1 '/' st '\\' st'"
(at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st \\ st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n ->
(X ::= a1) / st \\ t_update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st \\ st' ->
c2 / st' \\ st'' ->
(c1 ;; c2) / st \\ st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st \\ st' ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st \\ st' ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_WhileFalse : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false ->
(WHILE b1 DO c1 END) / st \\ st
| E_WhileTrue : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st \\ st' ->
(WHILE b1 DO c1 END) / st' \\ st'' ->
(WHILE b1 DO c1 END) / st \\ st''
(* FILL IN HERE *)
where "c1 '/' st '\\' st'" := (ceval c1 st st').
(** As a sanity check, the following claims should be provable for
your definition: *)
Example havoc_example1 : (HAVOC X) / empty_state \\ t_update empty_state X 0.
Proof.
(* FILL IN HERE *) Admitted.
Example havoc_example2 :
(SKIP;; HAVOC Z) / empty_state \\ t_update empty_state Z 42.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Finally, we repeat the definition of command equivalence from above: *)
Definition cequiv (c1 c2 : com) : Prop := forall st st' : state,
c1 / st \\ st' <-> c2 / st \\ st'.
(** Let's apply this definition to prove some nondeterministic
programs equivalent / inequivalent. *)
(** **** Exercise: 3 stars (havoc_swap) *)
(** Are the following two programs equivalent? *)
Definition pXY :=
HAVOC X;; HAVOC Y.
Definition pYX :=
HAVOC Y;; HAVOC X.
(** If you think they are equivalent, prove it. If you think they are
not, prove that. *)
Theorem pXY_cequiv_pYX :
cequiv pXY pYX \/ ~cequiv pXY pYX.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (havoc_copy) *)
(** Are the following two programs equivalent? *)
Definition ptwice :=
HAVOC X;; HAVOC Y.
Definition pcopy :=
HAVOC X;; Y ::= AId X.
(** If you think they are equivalent, then prove it. If you think they
are not, then prove that. (Hint: You may find the [assert] tactic
useful.) *)
Theorem ptwice_cequiv_pcopy :
cequiv ptwice pcopy \/ ~cequiv ptwice pcopy.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** The definition of program equivalence we are using here has some
subtle consequences on programs that may loop forever. What
[cequiv] says is that the set of possible _terminating_ outcomes
of two equivalent programs is the same. However, in a language
with nondeterminism, like Himp, some programs always terminate,
some programs always diverge, and some programs can
nondeterministically terminate in some runs and diverge in
others. The final part of the following exercise illustrates this
phenomenon.
*)
(** **** Exercise: 4 stars, advanced (p1_p2_term) *)
(** Consider the following commands: *)
Definition p1 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC Y;;
X ::= APlus (AId X) (ANum 1)
END.
Definition p2 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
SKIP
END.
(** Intuitively, [p1] and [p2] have the same termination behavior:
either they loop forever, or they terminate in the same state they
started in. We can capture the termination behavior of [p1] and
[p2] individually with these lemmas: *)
Lemma p1_may_diverge : forall st st', st X <> 0 ->
~ p1 / st \\ st'.
Proof. (* FILL IN HERE *) Admitted.
Lemma p2_may_diverge : forall st st', st X <> 0 ->
~ p2 / st \\ st'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (p1_p2_equiv) *)
(** Use these two lemmas to prove that [p1] and [p2] are actually
equivalent. *)
Theorem p1_p2_equiv : cequiv p1 p2.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advancedM (p3_p4_inequiv) *)
(** Prove that the following programs are _not_ equivalent. (Hint:
What should the value of [Z] be when [p3] terminates? What about
[p4]?) *)
Definition p3 : com :=
Z ::= ANum 1;;
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC X;;
HAVOC Z
END.
Definition p4 : com :=
X ::= (ANum 0);;
Z ::= (ANum 1).
Theorem p3_p4_inequiv : ~ cequiv p3 p4.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (p5_p6_equiv) *)
(** Prove that the following commands are equivalent. (Hint: As
mentioned above, our definition of [cequiv] for Himp only takes
into account the sets of possible terminating configurations: two
programs are equivalent if and only if when given a same starting
state [st], the set of possible terminating states is the same for
both programs. If [p5] terminates, what should the final state be?
Conversely, is it always possible to make [p5] terminate?) *)
Definition p5 : com :=
WHILE (BNot (BEq (AId X) (ANum 1))) DO
HAVOC X
END.
Definition p6 : com :=
X ::= ANum 1.
Theorem p5_p6_equiv : cequiv p5 p6.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
End Himp.
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, optional (for_while_equiv) *)
(** This exercise extends the optional [add_for_loop] exercise from
the \CHAPV1{Imp} chapter, where you were asked to extend the language
of commands with C-style [for] loops. Prove that the command:
for (c1 ; b ; c2) {
c3
}
is equivalent to:
c1 ;
WHILE b DO
c3 ;
c2
END
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (swap_noninterfering_assignments) *)
(** (Hint: You'll need [functional_extensionality] for this one.) *)
Theorem swap_noninterfering_assignments: forall l1 l2 a1 a2,
l1 <> l2 ->
var_not_used_in_aexp l1 a2 ->
var_not_used_in_aexp l2 a1 ->
cequiv
(l1 ::= a1;; l2 ::= a2)
(l2 ::= a2;; l1 ::= a1).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (capprox) *)
(** In this exercise we define an asymmetric variant of program
equivalence we call _program approximation_. We say that a
program [c1] _approximates_ a program [c2] when, for each of
the initial states for which [c1] terminates, [c2] also terminates
and produces the same final state. Formally, program approximation
is defined as follows: *)
Definition capprox (c1 c2 : com) : Prop := forall (st st' : state),
c1 / st \\ st' -> c2 / st \\ st'.
(** For example, the program [c1 = WHILE X <> 1 DO X ::= X - 1 END]
approximates [c2 = X ::= 1], but [c2] does not approximate [c1]
since [c1] does not terminate when [X = 0] but [c2] does. If two
programs approximate each other in both directions, then they are
equivalent. *)
(** Find two programs [c3] and [c4] such that neither approximates
the other. *)
Definition c3 : com (* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Definition c4 : com (* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem c3_c4_different : ~ capprox c3 c4 /\ ~ capprox c4 c3.
Proof. (* FILL IN HERE *) Admitted.
(** Find a program [cmin] that approximates every other program. *)
Definition cmin : com
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem cmin_minimal : forall c, capprox cmin c.
Proof. (* FILL IN HERE *) Admitted.
(** Finally, find a non-trivial property which is preserved by
program approximation (when going from left to right). *)
Definition zprop (c : com) : Prop
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem zprop_preserving : forall c c',
zprop c -> capprox c c' -> zprop c'.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2017-05-24 10:56:51 -0400 (Wed, 24 May 2017) $ *)
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 20:34:59 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n7014, Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
left_right_SHT2, bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, N87, N88, N89, N90, N91, N92,
inst_FSM_INPUT_ENABLE_state_next_1_, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1121, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1209, n1210, n1211,
n1212, n1214, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1432,
n1433, n1434, n1435, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503,
n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623,
n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633,
n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643,
n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653,
n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663,
n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673,
n1674, n1675, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1695,
n1697, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1748, n1749, n1751,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1890, n1891, n1892,
sub_x_1_n33, sub_x_1_n32, sub_x_1_n31, sub_x_5_A_34_, sub_x_5_A_33_,
sub_x_5_A_17_, sub_x_5_B_34_, sub_x_5_B_33_, sub_x_5_B_17_,
sub_x_5_n634, sub_x_5_n627, sub_x_5_n624, sub_x_5_n615, sub_x_5_n611,
sub_x_5_n610, sub_x_5_n608, sub_x_5_n607, sub_x_5_n601, sub_x_5_n424,
sub_x_5_n266, sub_x_5_n260, add_x_6_A_45_, add_x_6_A_43_,
add_x_6_A_42_, add_x_6_A_34_, add_x_6_A_27_, add_x_6_A_21_,
add_x_6_A_20_, add_x_6_A_18_, add_x_6_A_13_, add_x_6_A_12_,
add_x_6_A_10_, add_x_6_A_7_, add_x_6_A_6_, add_x_6_A_5_, add_x_6_A_4_,
add_x_6_A_2_, add_x_6_B_45_, add_x_6_B_43_, add_x_6_B_42_,
add_x_6_B_34_, add_x_6_B_27_, add_x_6_B_21_, add_x_6_B_20_,
add_x_6_B_18_, add_x_6_B_13_, add_x_6_B_12_, add_x_6_B_10_,
add_x_6_B_6_, add_x_6_B_4_, add_x_6_B_2_, add_x_6_n536, add_x_6_n534,
add_x_6_n529, add_x_6_n526, add_x_6_n521, add_x_6_n515, add_x_6_n492,
add_x_6_n489, add_x_6_n488, add_x_6_n483, add_x_6_n477, add_x_6_n470,
add_x_6_n423, add_x_6_n418, add_x_6_n417, add_x_6_n412, add_x_6_n406,
add_x_6_n401, add_x_6_n343, add_x_6_n265, add_x_6_n260, add_x_6_n259,
add_x_6_n254, add_x_6_n251, add_x_6_n248, add_x_6_n244, add_x_6_n243,
add_x_6_n241, add_x_6_n193, add_x_6_n185, add_x_6_n163, n1895, n1896,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1929, n1935, n1937,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103,
n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113,
n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133,
n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143,
n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153,
n2154, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2265, n2266,
n2267, n2268, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2398,
n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408,
n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418,
n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428,
n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438,
n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448,
n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458,
n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468,
n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478,
n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488,
n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498,
n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508,
n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518,
n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528,
n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538,
n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548,
n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558,
n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568,
n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578,
n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588,
n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598,
n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608,
n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618,
n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628,
n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638,
n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648,
n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658,
n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668,
n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678,
n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688,
n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698,
n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708,
n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718,
n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728,
n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738,
n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748,
n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758,
n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768,
n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778,
n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798,
n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808,
n2809, n2810, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840,
n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850,
n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430,
n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440,
n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450,
n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460,
n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470,
n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480,
n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490,
n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500,
n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510,
n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530,
n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540,
n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550,
n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560,
n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570,
n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580,
n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590,
n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600,
n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610,
n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620,
n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630,
n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640,
n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650,
n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660,
n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670,
n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680,
n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690,
n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700,
n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710,
n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720,
n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730,
n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740,
n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750,
n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760,
n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770,
n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780,
n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790,
n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800,
n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810,
n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820,
n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830,
n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840,
n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850,
n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860,
n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870,
n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880,
n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890,
n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900,
n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910,
n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920,
n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930,
n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940,
n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950,
n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960,
n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970,
n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980,
n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990,
n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000,
n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010,
n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020,
n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030,
n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040,
n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050,
n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060,
n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070,
n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080,
n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090,
n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100,
n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110,
n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120,
n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130,
n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140,
n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150,
n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160,
n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170,
n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180,
n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190,
n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200,
n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210,
n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220,
n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230,
n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240,
n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250,
n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260,
n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270,
n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280,
n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290,
n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300,
n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310,
n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320,
n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330,
n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340,
n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351,
n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361,
n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371,
n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381,
n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391,
n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401,
n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411,
n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421,
n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431,
n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441,
n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451,
n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461,
n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471,
n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481,
n4482, n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491,
n4492, n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501,
n4502, n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511,
n4512, n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521,
n4522, n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531,
n4532, n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541,
n4542, n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551,
n4552, n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561,
n4562, n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571,
n4572, n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581,
n4582, n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591,
n4592, n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601,
n4602, n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611,
n4612, n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621,
n4622, n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631,
n4632, n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641,
n4642, n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651,
n4652, n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661,
n4662, n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671,
n4672, n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681,
n4682, n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691,
n4692, n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701,
n4702, n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711,
n4712, n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721,
n4722, n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731,
n4732, n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741,
n4742, n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751,
n4752, n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761,
n4762, n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771,
n4772, n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781,
n4782, n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791,
n4792, n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801,
n4802, n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811,
n4812, n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821,
n4822, n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831,
n4832, n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841,
n4842, n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851,
n4852, n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861,
n4862, n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871,
n4872, n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881,
n4882, n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891,
n4892, n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901,
n4902, n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911,
n4912, n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921,
n4922, n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931,
n4932, n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941,
n4942, n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951,
n4952, n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961,
n4962, n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971,
n4972, n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981,
n4982, n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991,
n4992, n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001,
n5002, n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011,
n5012, n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021,
n5022, n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031,
n5032, n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041,
n5042, n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051,
n5052, n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061,
n5062, n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071,
n5072, n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081,
n5082, n5083, n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091,
n5092, n5093, n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101,
n5102, n5103, n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111,
n5112, n5113, n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121,
n5122, n5123, n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131,
n5132, n5133, n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141,
n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151,
n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161,
n5162, n5163, n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171,
n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181,
n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191,
n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201,
n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211,
n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221,
n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231,
n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241,
n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251,
n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261,
n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271,
n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281,
n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291,
n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301,
n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311,
n5312, n5313, n5314, n5315, n5317, n5318, n5319, n5320, n5321, n5322,
n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332,
n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532,
n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542,
n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552,
n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562,
n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572,
n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582,
n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592,
n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602,
n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612,
n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622,
n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632,
n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642,
n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652,
n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662,
n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672,
n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682,
n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692,
n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702,
n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712,
n5713, n5714, n5715, n5716, n5718, n5719, n5720, n5721, n5722, n5723,
n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733,
n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743,
n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753,
n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5762, n5763, n5764,
n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774,
n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784,
n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794,
n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804,
n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814,
n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824,
n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834,
n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844,
n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854,
n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864,
n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874,
n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884,
n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894,
n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904,
n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914,
n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924,
n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934,
n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944,
n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954,
n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964,
n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974,
n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984,
n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994,
n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004,
n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014,
n6015, n6016, n6017, n6021, n6022, n6026, n6027, n6028, n6029, n6030,
n6031, n6032, n6033, n6034, n6035, n6036, n6037, n6038, n6039, n6040,
n6041, n6042, n6043, n6044, n6045, n6046, n6047, n6048, n6049, n6050,
n6051, n6052, n6053, n6054, n6055, n6056, n6057, n6058, n6059, n6060,
n6061, n6062, n6063, n6064, n6065, n6066, n6067, n6068, n6069, n6070,
n6071, n6072, n6073, n6074, n6075, n6076, n6077, n6078, n6079, n6080,
n6081, n6082, n6083, n6084, n6085, n6086, n6087, n6088, n6089, n6090,
n6091, n6092, n6093, n6094, n6095, n6096, n6097, n6098, n6099, n6100,
n6101, n6102, n6103, n6104, n6105, n6106, n6107, n6108, n6109, n6110,
n6111, n6112, n6113, n6114, n6115, n6116, n6117, n6118, n6119, n6120,
n6121, n6122, n6123, n6124, n6125, n6126, n6127, n6128, n6129, n6130,
n6131, n6132, n6133, n6134, n6135, n6136, n6137, n6138, n6139, n6140,
n6141, n6142, n6143, n6144, n6145, n6146, n6147, n6148, n6149, n6150,
n6151, n6152, n6153, n6154, n6155, n6156, n6157, n6158, n6159, n6160,
n6161, n6162, n6163, n6164, n6165, n6166, n6167, n6168, n6169, n6170,
n6171, n6172, n6173, n6174, n6175, n6176, n6177, n6178, n6179, n6180,
n6181, n6182, n6183, n6184, n6185, n6186, n6187, n6188, n6189, n6190,
n6191, n6192, n6193, n6194, n6195, n6196, n6197, n6198, n6199, n6200,
n6201, n6202, n6203, n6204, n6205, n6206, n6207, n6208, n6209, n6210,
n6211, n6212, n6213, n6214, n6215, n6216, n6217, n6218, n6219, n6220,
n6221, n6222, n6223, n6224, n6225, n6226, n6227, n6228, n6229, n6230,
n6231, n6232, n6233, n6234, n6235, n6236, n6237, n6238, n6239, n6240,
n6241, n6242, n6243, n6244, n6245, n6246, n6247, n6248, n6249, n6250,
n6251, n6252, n6253, n6254, n6255, n6256, n6257, n6258, n6259, n6260,
n6261, n6262, n6263, n6264, n6265, n6266, n6267, n6268, n6269, n6270,
n6271, n6272, n6273, n6274, n6275, n6276, n6277, n6278, n6279, n6280,
n6281, n6282, n6283, n6284, n6285, n6286, n6287, n6288, n6289, n6290,
n6291, n6292, n6293, n6294, n6295, n6296, n6297, n6298, n6299, n6300,
n6301, n6302, n6303, n6304, n6305, n6306, n6307, n6308, n6309, n6310,
n6311, n6312, n6313, n6314, n6315, n6316, n6317, n6318, n6319, n6320,
n6321, n6322, n6323, n6324, n6325, n6326, n6327, n6328, n6329, n6330,
n6331, n6332, n6333, n6334, n6335, n6336, n6337, n6338, n6339, n6340,
n6341, n6342, n6343, n6344, n6345, n6346, n6347, n6348, n6349, n6350,
n6351, n6352, n6353, n6354, n6355, n6356, n6357, n6358, n6359, n6360,
n6361, n6362, n6363, n6364, n6365, n6366, n6367, n6368, n6369, n6370,
n6371, n6372, n6373, n6374, n6375, n6376, n6377, n6378, n6379, n6380,
n6381, n6382, n6383, n6384, n6385, n6386, n6387, n6388, n6389, n6390,
n6391, n6392, n6393, n6394, n6395, n6396, n6397, n6398, n6399, n6400,
n6401, n6402, n6403, n6404, n6405, n6406, n6407, n6408, n6409, n6410,
n6411, n6412, n6413, n6414, n6415, n6416, n6417, n6418, n6419, n6420,
n6421, n6422, n6423, n6424, n6425, n6426, n6427, n6428, n6429, n6430,
n6431, n6432, n6433, n6434, n6435, n6436, n6437, n6438, n6439, n6440,
n6441, n6442, n6443, n6444, n6445, n6446, n6447, n6448, n6449, n6450,
n6451, n6452, n6453, n6454, n6455, n6456, n6457, n6458, n6459, n6460,
n6461, n6462, n6463, n6464, n6465, n6466, n6467, n6468, n6469, n6470,
n6471, n6472, n6473, n6474, n6475, n6477, n6478, n6479, n6480, n6481,
n6482, n6483, n6484, n6485, n6486, n6487, n6488, n6489, n6490, n6491,
n6492, n6493, n6494, n6495, n6496, n6497, n6498, n6499, n6500, n6501,
n6502, n6503, n6504, n6505, n6506, n6507, n6508, n6509, n6510, n6511,
n6512, n6513, n6514, n6515, n6516, n6517, n6518, n6519, n6520, n6521,
n6522, n6523, n6524, n6525, n6526, n6527, n6528, n6529, n6530, n6531,
n6532, n6533, n6534, n6535, n6536, n6537, n6538, n6539, n6540, n6541,
n6542, n6543, n6544, n6545, n6546, n6547, n6548, n6549, n6550, n6551,
n6552, n6553, n6554, n6555, n6556, n6557, n6558, n6559, n6560, n6561,
n6562, n6563, n6564, n6565, n6566, n6567, n6568, n6569, n6570, n6571,
n6572, n6573, n6574, n6575, n6576, n6577, n6578, n6579, n6580, n6581,
n6582, n6583, n6584, n6585, n6586, n6587, n6588, n6589, n6590, n6591,
n6592, n6593, n6594, n6595, n6596, n6597, n6598, n6599, n6600, n6601,
n6602, n6603, n6604, n6605, n6606, n6607, n6608, n6609, n6610, n6611,
n6612, n6613, n6614, n6615, n6616, n6617, n6618, n6619, n6620, n6621,
n6622, n6623, n6624, n6625, n6626, n6627, n6628, n6629, n6630, n6631,
n6632, n6633, n6634, n6635, n6636, n6637, n6638, n6639, n6640, n6641,
n6642, n6643, n6644, n6645, n6646, n6647, n6648, n6649, n6650, n6651,
n6652, n6653, n6654, n6655, n6656, n6657, n6658, n6659, n6660, n6661,
n6662, n6663, n6664, n6665, n6666, n6667, n6668, n6669, n6670, n6671,
n6672, n6673, n6674, n6675, n6676, n6677, n6678, n6679, n6680, n6681,
n6682, n6683, n6684, n6685, n6686, n6687, n6688, n6689, n6690, n6691,
n6692, n6693, n6694, n6695, n6696, n6697, n6698, n6699, n6700, n6701,
n6702, n6703, n6704, n6705, n6706, n6707, n6708, n6709, n6710, n6711,
n6712, n6713, n6714, n6715, n6716, n6717, n6718, n6719, n6720, n6721,
n6722, n6723, n6724, n6725, n6726, n6727, n6728, n6729, n6730, n6731,
n6732, n6733, n6734, n6735, n6736, n6737, n6738, n6739, n6740, n6741,
n6742, n6743, n6744, n6745, n6746, n6747, n6748, n6749, n6750, n6751,
n6752, n6753, n6754, n6755, n6756, n6757, n6758, n6759, n6760, n6761,
n6762, n6763, n6764, n6765, n6766, n6767, n6768, n6769, n6770, n6771,
n6772, n6773, n6774, n6776, n6777, n6778, n6779, n6780, n6781, n6782,
n6783, n6784, n6785, n6786, n6787, n6788, n6789, n6790, n6791, n6792,
n6793, n6794, n6795, n6796, n6797, n6798, n6799, n6800, n6801, n6802,
n6803, n6804, n6805, n6806, n6807, n6808, n6809, n6810, n6811, n6812,
n6813, n6814, n6815, n6816, n6817, n6818, n6819, n6820, n6821, n6822,
n6823, n6824, n6825, n6826, n6827, n6828, n6829, n6830, n6831, n6832,
n6833, n6834, n6835, n6836, n6837, n6838, n6839, n6840, n6841, n6842,
n6843, n6844, n6845, n6846, n6847, n6848, n6849, n6850, n6851, n6852,
n6853, n6854, n6855, n6856, n6857, n6858, n6859, n6860, n6861, n6862,
n6863, n6864, n6865, n6866, n6867, n6868, n6869, n6870, n6871, n6872,
n6873, n6874, n6875, n6876, n6877, n6878, n6879, n6880, n6881, n6882,
n6883, n6884, n6885, n6886, n6887, n6888, n6889, n6890, n6891, n6892,
n6893, n6894, n6895, n6896, n6897, n6898, n6899, n6900, n6901, n6902,
n6903, n6904, n6905, n6906, n6907, n6908, n6909, n6910, n6911, n6912,
n6913, n6914, n6915, n6916, n6917, n6918, n6919, n6920, n6921, n6922,
n6923, n6924, n6925, n6926, n6927, n6928, n6929, n6930, n6931, n6932,
n6933, n6934, n6935, n6936, n6937, n6938, n6939, n6940, n6941, n6942,
n6943, n6944, n6945, n6946, n6947, n6948, n6949, n6950, n6951, n6952,
n6953, n6954, n6955, n6956, n6957, n6958, n6959, n6960, n6961, n6962,
n6963, n6964, n6965, n6966, n6967, n6968, n6969, n6970, n6971, n6972,
n6973, n6974, n6975, n6976, n6977, n6978, n6979, n6980, n6981, n6982,
n6983, n6984, n6985, n6986, n6987, n6988, n6989, n6990, n6991, n6992,
n6993, n6994, n6995, n6996, n6997, n6998, n6999, n7000, n7001, n7002,
n7003, n7004, n7005, n7006, n7007, n7008, n7009, n7010, n7011, n7012,
n7013;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:2] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [48:0] Raw_mant_NRM_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:1] LZD_output_NRM2_EW;
wire [9:0] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [54:1] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1892), .CK(clk), .RN(
n6765), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n6265) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n6766), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n6264) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1891), .CK(clk), .RN(
n6766), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n6205) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n1890), .CK(clk), .RN(n6765), .Q(
Shift_reg_FLAGS_7_6), .QN(n7010) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1888), .CK(clk), .RN(n6757), .Q(
n7014), .QN(n6266) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1886), .CK(clk), .RN(n6757), .Q(
Shift_reg_FLAGS_7[2]), .QN(n3343) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n1885), .CK(clk), .RN(n6757), .Q(
Shift_reg_FLAGS_7[1]), .QN(n6267) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n1884), .CK(clk), .RN(n6757), .Q(
Shift_reg_FLAGS_7[0]), .QN(n6714) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1883), .CK(clk), .RN(n6363),
.Q(intDX_EWSW[0]), .QN(n3262) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1882), .CK(clk), .RN(n6364),
.Q(intDX_EWSW[1]), .QN(n3263) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1881), .CK(clk), .RN(n6363),
.Q(intDX_EWSW[2]), .QN(n3302) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1880), .CK(clk), .RN(n6374),
.Q(intDX_EWSW[3]), .QN(n3288) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1879), .CK(clk), .RN(n6350),
.Q(intDX_EWSW[4]), .QN(n3273) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1878), .CK(clk), .RN(n6372),
.Q(intDX_EWSW[5]), .QN(n3284) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1877), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[6]), .QN(n3264) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1876), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[7]), .QN(n3320) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1875), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[8]), .QN(n3309) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1874), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[9]), .QN(n3289) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1873), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[10]), .QN(n3296) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1872), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[11]), .QN(n3334) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1871), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[12]), .QN(n3276) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1870), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[13]), .QN(n3265) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1869), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[14]), .QN(n3325) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1868), .CK(clk), .RN(n6763),
.Q(intDX_EWSW[15]), .QN(n3315) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1867), .CK(clk), .RN(n6373),
.Q(intDX_EWSW[16]), .QN(n3297) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1866), .CK(clk), .RN(n6371),
.Q(intDX_EWSW[17]), .QN(n3303) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1865), .CK(clk), .RN(n6372),
.Q(intDX_EWSW[18]), .QN(n3306) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1864), .CK(clk), .RN(n6359),
.Q(intDX_EWSW[19]), .QN(n3310) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1863), .CK(clk), .RN(n6360),
.Q(intDX_EWSW[20]), .QN(n3285) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1862), .CK(clk), .RN(n6358),
.Q(intDX_EWSW[21]), .QN(n3290) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1861), .CK(clk), .RN(n6358),
.Q(intDX_EWSW[22]), .QN(n3293) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1860), .CK(clk), .RN(n5244),
.Q(intDX_EWSW[23]), .QN(n3269) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1859), .CK(clk), .RN(n2542),
.Q(intDX_EWSW[24]), .QN(n3271) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1858), .CK(clk), .RN(n6384),
.Q(intDX_EWSW[25]), .QN(n3274) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1857), .CK(clk), .RN(n6385),
.Q(intDX_EWSW[26]), .QN(n3275) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1856), .CK(clk), .RN(n6386),
.Q(intDX_EWSW[27]), .QN(n3277) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1855), .CK(clk), .RN(n6384),
.Q(intDX_EWSW[28]), .QN(n3280) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1854), .CK(clk), .RN(n6346),
.Q(intDX_EWSW[29]), .QN(n3266) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1853), .CK(clk), .RN(n6345),
.Q(intDX_EWSW[30]), .QN(n3324) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1852), .CK(clk), .RN(n6346),
.Q(intDX_EWSW[31]), .QN(n3326) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1851), .CK(clk), .RN(n6345),
.Q(intDX_EWSW[32]), .QN(n3329) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1850), .CK(clk), .RN(n6736),
.Q(intDX_EWSW[33]), .QN(n3316) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1849), .CK(clk), .RN(n6349),
.Q(intDX_EWSW[34]), .QN(n3318) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1848), .CK(clk), .RN(n6771),
.Q(intDX_EWSW[35]), .QN(n3298) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1847), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[36]), .QN(n3300) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1846), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[37]), .QN(n3304) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1845), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[38]), .QN(n3305) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1844), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[39]), .QN(n3307) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1843), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[40]), .QN(n3308) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1842), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[41]), .QN(n1952) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1841), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[42]), .QN(n3321) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1840), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[43]), .QN(n3286) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1839), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[44]), .QN(n3287) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1838), .CK(clk), .RN(n6764),
.Q(intDX_EWSW[45]), .QN(n3291) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1837), .CK(clk), .RN(n6766),
.Q(intDX_EWSW[46]), .QN(n3292) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1836), .CK(clk), .RN(n6766),
.Q(intDX_EWSW[47]), .QN(n3294) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1835), .CK(clk), .RN(n6766),
.Q(intDX_EWSW[48]), .QN(n3295) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1834), .CK(clk), .RN(n6767),
.Q(intDX_EWSW[49]), .QN(n3270) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1833), .CK(clk), .RN(n6767),
.Q(intDX_EWSW[50]), .QN(n3337) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1832), .CK(clk), .RN(n6767),
.Q(intDX_EWSW[51]), .QN(n3272) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1831), .CK(clk), .RN(n6767),
.Q(intDX_EWSW[52]), .QN(n3331) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1830), .CK(clk), .RN(n2526),
.Q(intDX_EWSW[53]), .QN(n3323) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1829), .CK(clk), .RN(n2526),
.Q(intDX_EWSW[54]), .QN(n3283) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1828), .CK(clk), .RN(n2526),
.Q(intDX_EWSW[55]), .QN(n3330) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1827), .CK(clk), .RN(n6765),
.Q(intDX_EWSW[56]), .QN(n3336) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1826), .CK(clk), .RN(n6765),
.Q(intDX_EWSW[57]), .QN(n3278) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1825), .CK(clk), .RN(n6765),
.Q(intDX_EWSW[58]), .QN(n3279) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1824), .CK(clk), .RN(n6765),
.Q(intDX_EWSW[59]), .QN(n3281) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1823), .CK(clk), .RN(n6765),
.Q(intDX_EWSW[60]), .QN(n3282) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1822), .CK(clk), .RN(n6765),
.Q(intDX_EWSW[61]), .QN(n3268) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1821), .CK(clk), .RN(n6765),
.Q(intDX_EWSW[62]), .QN(n3342) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1816), .CK(clk), .RN(n6733),
.Q(intDY_EWSW[2]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1815), .CK(clk), .RN(n6770),
.Q(intDY_EWSW[3]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1814), .CK(clk), .RN(n6745),
.Q(intDY_EWSW[4]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1813), .CK(clk), .RN(n6743),
.Q(intDY_EWSW[5]), .QN(n1921) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1812), .CK(clk), .RN(n2488),
.Q(intDY_EWSW[6]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1811), .CK(clk), .RN(n6728),
.Q(intDY_EWSW[7]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1810), .CK(clk), .RN(n6758),
.Q(intDY_EWSW[8]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1808), .CK(clk), .RN(n6758),
.Q(intDY_EWSW[10]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1806), .CK(clk), .RN(n6758),
.Q(intDY_EWSW[12]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1804), .CK(clk), .RN(n6758),
.Q(intDY_EWSW[14]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1803), .CK(clk), .RN(n6758),
.Q(intDY_EWSW[15]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1802), .CK(clk), .RN(n6758),
.Q(intDY_EWSW[16]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1801), .CK(clk), .RN(n6758),
.Q(intDY_EWSW[17]), .QN(n2307) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1800), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[18]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1799), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[19]), .QN(n1944) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1798), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[20]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1797), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[21]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1796), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[22]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1795), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[23]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1794), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[24]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1793), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[25]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1792), .CK(clk), .RN(n6759),
.Q(intDY_EWSW[26]), .QN(n2140) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1790), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[28]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1789), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[29]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1788), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[30]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1787), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[31]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1786), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[32]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1785), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[33]), .QN(n2152) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1783), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[35]), .QN(n2150) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1782), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[36]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1781), .CK(clk), .RN(n6760),
.Q(intDY_EWSW[37]), .QN(n2317) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1780), .CK(clk), .RN(n6761),
.Q(intDY_EWSW[38]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1779), .CK(clk), .RN(n6761),
.Q(intDY_EWSW[39]), .QN(n2136) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1778), .CK(clk), .RN(n6761),
.Q(intDY_EWSW[40]), .QN(n2138) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1776), .CK(clk), .RN(n6761),
.Q(intDY_EWSW[42]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1775), .CK(clk), .RN(n6761),
.Q(intDY_EWSW[43]), .QN(n2303) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1774), .CK(clk), .RN(n6761),
.Q(intDY_EWSW[44]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1772), .CK(clk), .RN(n6761),
.Q(intDY_EWSW[46]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1771), .CK(clk), .RN(n6761),
.Q(intDY_EWSW[47]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1770), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[48]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1769), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[49]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1768), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[50]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1767), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[51]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1766), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[52]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1765), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[53]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1764), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[54]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1763), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[55]), .QN(n2464) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1762), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[56]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1761), .CK(clk), .RN(n6762),
.Q(intDY_EWSW[57]), .QN(n1917) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1760), .CK(clk), .RN(n6367),
.Q(intDY_EWSW[58]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1759), .CK(clk), .RN(n6361),
.Q(intDY_EWSW[59]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1758), .CK(clk), .RN(n6363),
.Q(intDY_EWSW[60]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1757), .CK(clk), .RN(n6364),
.Q(intDY_EWSW[61]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1756), .CK(clk), .RN(n6765),
.Q(intDY_EWSW[62]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1691), .CK(clk), .RN(n2487),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1675), .CK(clk), .RN(n6771), .Q(
DMP_EXP_EWSW[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1674), .CK(clk), .RN(n7013), .Q(
DMP_EXP_EWSW[1]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1673), .CK(clk), .RN(n2539), .Q(
DMP_EXP_EWSW[2]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1672), .CK(clk), .RN(n2538), .Q(
DMP_EXP_EWSW[3]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1670), .CK(clk), .RN(n6738), .Q(
DMP_EXP_EWSW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1669), .CK(clk), .RN(n6738), .Q(
DMP_EXP_EWSW[6]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1668), .CK(clk), .RN(n2541), .Q(
DMP_EXP_EWSW[7]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1667), .CK(clk), .RN(n2543), .Q(
DMP_EXP_EWSW[8]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1663), .CK(clk), .RN(n6740), .Q(
DMP_EXP_EWSW[12]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1662), .CK(clk), .RN(n6740), .Q(
DMP_EXP_EWSW[13]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1661), .CK(clk), .RN(n6741), .Q(
DMP_EXP_EWSW[14]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1660), .CK(clk), .RN(n6741), .Q(
DMP_EXP_EWSW[15]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1659), .CK(clk), .RN(n6742), .Q(
DMP_EXP_EWSW[16]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1658), .CK(clk), .RN(n2531), .Q(
DMP_EXP_EWSW[17]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1657), .CK(clk), .RN(n2531), .Q(
DMP_EXP_EWSW[18]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1656), .CK(clk), .RN(n6735), .Q(
DMP_EXP_EWSW[19]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1655), .CK(clk), .RN(n6748), .Q(
DMP_EXP_EWSW[20]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1654), .CK(clk), .RN(n6375), .Q(
DMP_EXP_EWSW[21]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1653), .CK(clk), .RN(n6744), .Q(
DMP_EXP_EWSW[22]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1652), .CK(clk), .RN(n6744), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1651), .CK(clk), .RN(n6745), .Q(
DMP_EXP_EWSW[24]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1650), .CK(clk), .RN(n6743), .Q(
DMP_EXP_EWSW[25]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1649), .CK(clk), .RN(n6735), .Q(
DMP_EXP_EWSW[26]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1647), .CK(clk), .RN(n6746), .Q(
DMP_EXP_EWSW[28]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1646), .CK(clk), .RN(n6747), .Q(
DMP_EXP_EWSW[29]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1645), .CK(clk), .RN(n6747), .Q(
DMP_EXP_EWSW[30]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1644), .CK(clk), .RN(n6747), .Q(
DMP_EXP_EWSW[31]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1643), .CK(clk), .RN(n2533), .Q(
DMP_EXP_EWSW[32]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1642), .CK(clk), .RN(n2533), .Q(
DMP_EXP_EWSW[33]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1641), .CK(clk), .RN(n2499), .Q(
DMP_EXP_EWSW[34]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1640), .CK(clk), .RN(n2499), .Q(
DMP_EXP_EWSW[35]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1639), .CK(clk), .RN(n2510), .Q(
DMP_EXP_EWSW[36]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1638), .CK(clk), .RN(n2531), .Q(
DMP_EXP_EWSW[37]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1637), .CK(clk), .RN(n2533), .Q(
DMP_EXP_EWSW[38]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1636), .CK(clk), .RN(n2522), .Q(
DMP_EXP_EWSW[39]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1635), .CK(clk), .RN(n2521), .Q(
DMP_EXP_EWSW[40]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1633), .CK(clk), .RN(n2503), .Q(
DMP_EXP_EWSW[42]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1631), .CK(clk), .RN(n6750), .Q(
DMP_EXP_EWSW[44]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1630), .CK(clk), .RN(n6750), .Q(
DMP_EXP_EWSW[45]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1629), .CK(clk), .RN(n6750), .Q(
DMP_EXP_EWSW[46]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1628), .CK(clk), .RN(n6730), .Q(
DMP_EXP_EWSW[47]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1627), .CK(clk), .RN(n2496), .Q(
DMP_EXP_EWSW[48]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1626), .CK(clk), .RN(n6751), .Q(
DMP_EXP_EWSW[49]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1625), .CK(clk), .RN(n6751), .Q(
DMP_EXP_EWSW[50]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1624), .CK(clk), .RN(n6751), .Q(
DMP_EXP_EWSW[51]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1618), .CK(clk), .RN(n6754), .Q(
DMP_EXP_EWSW[57]), .QN(n6338) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1616), .CK(clk), .RN(n6755), .Q(
DMP_EXP_EWSW[59]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1615), .CK(clk), .RN(n6756), .Q(
DMP_EXP_EWSW[60]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1614), .CK(clk), .RN(n6756), .Q(
DMP_EXP_EWSW[61]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1613), .CK(clk), .RN(n5250), .Q(
DMP_EXP_EWSW[62]) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1612), .CK(clk), .RN(n6737), .Q(
OP_FLAG_EXP) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1611), .CK(clk), .RN(n6723), .Q(
ZERO_FLAG_EXP), .QN(n6261) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1610), .CK(clk), .RN(n6724), .Q(
SIGN_FLAG_EXP) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1609), .CK(clk), .RN(n6771), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n2542), .Q(
DMP_SHT2_EWSW[0]), .QN(n6103) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1606), .CK(clk), .RN(n6771), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1605), .CK(clk), .RN(n2541), .Q(
DMP_SHT2_EWSW[1]), .QN(n6102) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1603), .CK(clk), .RN(n2539), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n2539), .Q(
DMP_SHT2_EWSW[2]), .QN(n6101) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1600), .CK(clk), .RN(n2539), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1599), .CK(clk), .RN(n2539), .Q(
DMP_SHT2_EWSW[3]), .QN(n6100) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1597), .CK(clk), .RN(n6738), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1596), .CK(clk), .RN(n2539), .Q(
DMP_SHT2_EWSW[4]), .QN(n6099) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1594), .CK(clk), .RN(n6738), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1593), .CK(clk), .RN(n6738), .Q(
DMP_SHT2_EWSW[5]), .QN(n6098) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1591), .CK(clk), .RN(n6738), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1590), .CK(clk), .RN(n6738), .Q(
DMP_SHT2_EWSW[6]), .QN(n6097) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1588), .CK(clk), .RN(n2509), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1585), .CK(clk), .RN(n2522), .Q(
DMP_SHT1_EWSW[8]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1584), .CK(clk), .RN(n2542), .Q(
DMP_SHT2_EWSW[8]), .QN(n6095) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1581), .CK(clk), .RN(n2492), .Q(
DMP_SHT2_EWSW[9]), .QN(n6184) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1579), .CK(clk), .RN(n6736), .Q(
DMP_SHT1_EWSW[10]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1578), .CK(clk), .RN(n6752), .Q(
DMP_SHT2_EWSW[10]), .QN(n6183) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(clk), .RN(n6739), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1575), .CK(clk), .RN(n6737), .Q(
DMP_SHT2_EWSW[11]), .QN(n6182) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1573), .CK(clk), .RN(n6740), .Q(
DMP_SHT1_EWSW[12]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1571), .CK(clk), .RN(n6740), .Q(
DMP_SFG[12]), .QN(n6280) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1570), .CK(clk), .RN(n6740), .Q(
DMP_SHT1_EWSW[13]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1569), .CK(clk), .RN(n6740), .Q(
DMP_SHT2_EWSW[13]), .QN(n6180) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1568), .CK(clk), .RN(n6740), .Q(
DMP_SFG[13]), .QN(n6276) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1567), .CK(clk), .RN(n6741), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1566), .CK(clk), .RN(n6740), .Q(
DMP_SHT2_EWSW[14]), .QN(n6179) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1565), .CK(clk), .RN(n6740), .Q(
DMP_SFG[14]), .QN(n6287) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1564), .CK(clk), .RN(n6741), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1563), .CK(clk), .RN(n6741), .Q(
DMP_SHT2_EWSW[15]), .QN(n6178) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1561), .CK(clk), .RN(n6741), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1560), .CK(clk), .RN(n6748), .Q(
DMP_SHT2_EWSW[16]), .QN(n6177) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1558), .CK(clk), .RN(n2532), .Q(
DMP_SHT1_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1557), .CK(clk), .RN(n2532), .Q(
DMP_SHT2_EWSW[17]), .QN(n6176) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1555), .CK(clk), .RN(n2532), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1552), .CK(clk), .RN(n6742), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1551), .CK(clk), .RN(n2532), .Q(
DMP_SHT2_EWSW[19]), .QN(n6174) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1549), .CK(clk), .RN(n6745), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1548), .CK(clk), .RN(n6748), .Q(
DMP_SHT2_EWSW[20]), .QN(n6173) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1546), .CK(clk), .RN(n6743), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1545), .CK(clk), .RN(n6375), .Q(
DMP_SHT2_EWSW[21]), .QN(n6172) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1543), .CK(clk), .RN(n6744), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1541), .CK(clk), .RN(n6744), .Q(
DMP_SFG[22]), .QN(n6272) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1540), .CK(clk), .RN(n6744), .Q(
DMP_SHT1_EWSW[23]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1539), .CK(clk), .RN(n6744), .Q(
DMP_SHT2_EWSW[23]), .QN(n6170) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1538), .CK(clk), .RN(n6744), .Q(
DMP_SFG[23]), .QN(n6285) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1537), .CK(clk), .RN(n6748), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1536), .CK(clk), .RN(n6744), .Q(
DMP_SHT2_EWSW[24]), .QN(n6169) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1534), .CK(clk), .RN(n6375), .Q(
DMP_SHT1_EWSW[25]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1533), .CK(clk), .RN(n6743), .Q(
DMP_SHT2_EWSW[25]), .QN(n6168) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1531), .CK(clk), .RN(n6742), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1530), .CK(clk), .RN(n6735), .Q(
DMP_SHT2_EWSW[26]), .QN(n6167) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1528), .CK(clk), .RN(n6746), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1527), .CK(clk), .RN(n6746), .Q(
DMP_SHT2_EWSW[27]), .QN(n6166) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1526), .CK(clk), .RN(n6746), .Q(
DMP_SFG[27]), .QN(n6292) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1525), .CK(clk), .RN(n6746), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1523), .CK(clk), .RN(n6746), .Q(
DMP_SFG[28]), .QN(n6290) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1522), .CK(clk), .RN(n6747), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1521), .CK(clk), .RN(n6746), .Q(
DMP_SHT2_EWSW[29]), .QN(n6164) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1520), .CK(clk), .RN(n6746), .Q(
DMP_SFG[29]), .QN(n6275) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1519), .CK(clk), .RN(n6747), .Q(
DMP_SHT1_EWSW[30]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1517), .CK(clk), .RN(n6747), .Q(
DMP_SFG[30]), .QN(n6284) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1516), .CK(clk), .RN(n6747), .Q(
DMP_SHT1_EWSW[31]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1515), .CK(clk), .RN(n6747), .Q(
DMP_SHT2_EWSW[31]), .QN(n6162) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1513), .CK(clk), .RN(n2534), .Q(
DMP_SHT1_EWSW[32]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1512), .CK(clk), .RN(n2534), .Q(
DMP_SHT2_EWSW[32]), .QN(n6161) );
DFFRXLTS R_1179 ( .D(n1511), .CK(clk), .RN(n2534), .QN(n6248) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1510), .CK(clk), .RN(n2533), .Q(
DMP_SHT1_EWSW[33]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1509), .CK(clk), .RN(n2534), .Q(
DMP_SHT2_EWSW[33]), .QN(n6160) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1507), .CK(clk), .RN(n2499), .Q(
DMP_SHT1_EWSW[34]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1504), .CK(clk), .RN(n2499), .Q(
DMP_SHT1_EWSW[35]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1503), .CK(clk), .RN(n2499), .Q(
DMP_SHT2_EWSW[35]), .QN(n6158) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1501), .CK(clk), .RN(n2499), .Q(
DMP_SHT1_EWSW[36]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1500), .CK(clk), .RN(n2499), .Q(
DMP_SHT2_EWSW[36]), .QN(n6157) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1498), .CK(clk), .RN(n6743), .Q(
DMP_SHT1_EWSW[37]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1497), .CK(clk), .RN(n2515), .Q(
DMP_SHT2_EWSW[37]), .QN(n6156) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1495), .CK(clk), .RN(n6745), .Q(
DMP_SHT1_EWSW[38]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1494), .CK(clk), .RN(n2538), .Q(
DMP_SHT2_EWSW[38]), .QN(n6155) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1492), .CK(clk), .RN(n2521), .Q(
DMP_SHT1_EWSW[39]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1491), .CK(clk), .RN(n6745), .Q(
DMP_SHT2_EWSW[39]), .QN(n6154) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1489), .CK(clk), .RN(n2522), .Q(
DMP_SHT1_EWSW[40]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1488), .CK(clk), .RN(n2522), .Q(
DMP_SHT2_EWSW[40]), .QN(n6153) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1486), .CK(clk), .RN(n2521), .Q(
DMP_SHT1_EWSW[41]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1485), .CK(clk), .RN(n2521), .Q(
DMP_SHT2_EWSW[41]), .QN(n6152) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1483), .CK(clk), .RN(n2504), .Q(
DMP_SHT1_EWSW[42]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1482), .CK(clk), .RN(n2504), .Q(
DMP_SHT2_EWSW[42]), .QN(n6151) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1480), .CK(clk), .RN(n2504), .Q(
DMP_SHT1_EWSW[43]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1479), .CK(clk), .RN(n2504), .Q(
DMP_SHT2_EWSW[43]), .QN(n6150) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1477), .CK(clk), .RN(n6750), .Q(
DMP_SHT1_EWSW[44]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1474), .CK(clk), .RN(n6750), .Q(
DMP_SHT1_EWSW[45]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1473), .CK(clk), .RN(n6750), .Q(
DMP_SHT2_EWSW[45]), .QN(n6148) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1471), .CK(clk), .RN(n6750), .Q(
DMP_SHT1_EWSW[46]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1470), .CK(clk), .RN(n6750), .Q(
DMP_SHT2_EWSW[46]), .QN(n6147) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1468), .CK(clk), .RN(n2496), .Q(
DMP_SHT1_EWSW[47]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1467), .CK(clk), .RN(n6730), .Q(
DMP_SHT2_EWSW[47]), .QN(n6146) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1465), .CK(clk), .RN(n6771), .Q(
DMP_SHT1_EWSW[48]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1464), .CK(clk), .RN(n6730), .Q(
DMP_SHT2_EWSW[48]), .QN(n6145) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1462), .CK(clk), .RN(n6751), .Q(
DMP_SHT1_EWSW[49]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1461), .CK(clk), .RN(n2496), .Q(
DMP_SHT2_EWSW[49]), .QN(n6144) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1459), .CK(clk), .RN(n6751), .Q(
DMP_SHT1_EWSW[50]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1458), .CK(clk), .RN(n6751), .Q(
DMP_SHT2_EWSW[50]), .QN(n6143) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1457), .CK(clk), .RN(n6751), .Q(
DMP_SFG[50]), .QN(n6288) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1456), .CK(clk), .RN(n6751), .Q(
DMP_SHT1_EWSW[51]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1454), .CK(clk), .RN(n6751), .Q(
DMP_SFG[51]), .QN(n6295) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1450), .CK(clk), .RN(n6752), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1440), .CK(clk), .RN(n6753), .Q(
DMP_exp_NRM_EW[2]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1439), .CK(clk), .RN(n6753), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1435), .CK(clk), .RN(n6753), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1434), .CK(clk), .RN(n6753), .Q(
DMP_exp_NRM2_EW[3]), .QN(n1948) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1430), .CK(clk), .RN(n2491), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1425), .CK(clk), .RN(n6754), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1423), .CK(clk), .RN(n6755), .Q(
DMP_SHT1_EWSW[58]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1422), .CK(clk), .RN(n6754), .Q(
DMP_SHT2_EWSW[58]), .QN(n6141) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1420), .CK(clk), .RN(n6754), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1419), .CK(clk), .RN(n6754), .Q(
DMP_exp_NRM2_EW[6]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1418), .CK(clk), .RN(n6755), .Q(
DMP_SHT1_EWSW[59]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1417), .CK(clk), .RN(n6755), .Q(
DMP_SHT2_EWSW[59]), .QN(n6140) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1415), .CK(clk), .RN(n6755), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1414), .CK(clk), .RN(n6755), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1413), .CK(clk), .RN(n6756), .Q(
DMP_SHT1_EWSW[60]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1412), .CK(clk), .RN(n6756), .Q(
DMP_SHT2_EWSW[60]), .QN(n6139) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1410), .CK(clk), .RN(n6755), .Q(
DMP_exp_NRM_EW[8]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1405), .CK(clk), .RN(n6756), .Q(
DMP_exp_NRM_EW[9]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1404), .CK(clk), .RN(n6756), .Q(
DMP_exp_NRM2_EW[9]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1403), .CK(clk), .RN(n6757), .Q(
DMP_SHT1_EWSW[62]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1402), .CK(clk), .RN(n6757), .Q(
DMP_SHT2_EWSW[62]), .QN(n6138) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1400), .CK(clk), .RN(n6757), .Q(
DMP_exp_NRM_EW[10]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1399), .CK(clk), .RN(n6757),
.Q(DMP_exp_NRM2_EW[10]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1398), .CK(clk), .RN(n2546), .Q(
DmP_EXP_EWSW[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1397), .CK(clk), .RN(n2544), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1395), .CK(clk), .RN(n2544), .Q(
DmP_mant_SHT1_SW[1]), .QN(n6221) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1393), .CK(clk), .RN(n2546), .Q(
DmP_mant_SHT1_SW[2]), .QN(n6220) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1391), .CK(clk), .RN(n6731), .Q(
DmP_mant_SHT1_SW[3]), .QN(n6225) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1390), .CK(clk), .RN(n6731), .Q(
DmP_EXP_EWSW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(n6731), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1388), .CK(clk), .RN(n7013), .Q(
DmP_EXP_EWSW[5]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(n2515), .Q(
DmP_EXP_EWSW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n6351), .Q(
DmP_mant_SHT1_SW[6]), .QN(n6226) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1384), .CK(clk), .RN(n6770), .Q(
DmP_EXP_EWSW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1383), .CK(clk), .RN(n6379), .Q(
DmP_mant_SHT1_SW[7]), .QN(n6222) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1382), .CK(clk), .RN(n2511), .Q(
DmP_EXP_EWSW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1381), .CK(clk), .RN(n6345), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1380), .CK(clk), .RN(n6754), .Q(
DmP_EXP_EWSW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1379), .CK(clk), .RN(n6379), .Q(
DmP_mant_SHT1_SW[9]), .QN(n6224) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1376), .CK(clk), .RN(n2510), .Q(
DmP_EXP_EWSW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1375), .CK(clk), .RN(n6768),
.Q(DmP_mant_SHT1_SW[11]), .QN(n3333) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1373), .CK(clk), .RN(n2508),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1372), .CK(clk), .RN(n6732), .Q(
DmP_EXP_EWSW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1371), .CK(clk), .RN(n6731),
.Q(DmP_mant_SHT1_SW[13]), .QN(n6228) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(n6731), .Q(
DmP_EXP_EWSW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(n6731),
.Q(DmP_mant_SHT1_SW[14]), .QN(n6227) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1368), .CK(clk), .RN(n6734), .Q(
DmP_EXP_EWSW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1367), .CK(clk), .RN(n6734),
.Q(DmP_mant_SHT1_SW[15]), .QN(n6210) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1366), .CK(clk), .RN(n6730), .Q(
DmP_EXP_EWSW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1365), .CK(clk), .RN(n2526),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1364), .CK(clk), .RN(n2492), .Q(
DmP_EXP_EWSW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1363), .CK(clk), .RN(n2528),
.Q(DmP_mant_SHT1_SW[17]), .QN(n6212) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1362), .CK(clk), .RN(n6749), .Q(
DmP_EXP_EWSW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1359), .CK(clk), .RN(n2535),
.Q(DmP_mant_SHT1_SW[19]), .QN(n6217) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1358), .CK(clk), .RN(n2535), .Q(
DmP_EXP_EWSW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1357), .CK(clk), .RN(n2535),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1355), .CK(clk), .RN(n2535),
.Q(DmP_mant_SHT1_SW[21]), .QN(n6219) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1353), .CK(clk), .RN(n2535),
.Q(DmP_mant_SHT1_SW[22]), .QN(n6218) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1352), .CK(clk), .RN(n2511), .Q(
DmP_EXP_EWSW[23]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1351), .CK(clk), .RN(n5251),
.Q(DmP_mant_SHT1_SW[23]), .QN(n6209) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1350), .CK(clk), .RN(n2504), .Q(
DmP_EXP_EWSW[24]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1349), .CK(clk), .RN(n6347),
.Q(DmP_mant_SHT1_SW[24]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1348), .CK(clk), .RN(n2509), .Q(
DmP_EXP_EWSW[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1347), .CK(clk), .RN(n2492),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1346), .CK(clk), .RN(n2511), .Q(
DmP_EXP_EWSW[26]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1345), .CK(clk), .RN(n2488),
.Q(DmP_mant_SHT1_SW[26]), .QN(n6208) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1344), .CK(clk), .RN(n2525), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1340), .CK(clk), .RN(n6734), .Q(
DmP_EXP_EWSW[29]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1339), .CK(clk), .RN(n6734),
.Q(DmP_mant_SHT1_SW[29]), .QN(n6216) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1338), .CK(clk), .RN(n6734), .Q(
DmP_EXP_EWSW[30]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1337), .CK(clk), .RN(n6734),
.Q(DmP_mant_SHT1_SW[30]), .QN(n6215) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1336), .CK(clk), .RN(n2524), .Q(
DmP_EXP_EWSW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1335), .CK(clk), .RN(n2487),
.Q(DmP_mant_SHT1_SW[31]), .QN(n6231) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1333), .CK(clk), .RN(n2508),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1332), .CK(clk), .RN(n6732), .Q(
DmP_EXP_EWSW[33]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1331), .CK(clk), .RN(n2487),
.Q(DmP_mant_SHT1_SW[33]), .QN(n6233) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1330), .CK(clk), .RN(n5249), .Q(
DmP_EXP_EWSW[34]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1329), .CK(clk), .RN(n6749),
.Q(DmP_mant_SHT1_SW[34]), .QN(n6232) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1328), .CK(clk), .RN(n2541), .Q(
DmP_EXP_EWSW[35]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1327), .CK(clk), .RN(n2543),
.Q(DmP_mant_SHT1_SW[35]), .QN(n6234) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1326), .CK(clk), .RN(n2541), .Q(
DmP_EXP_EWSW[36]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1325), .CK(clk), .RN(n2541),
.Q(DmP_mant_SHT1_SW[36]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1323), .CK(clk), .RN(n6352),
.Q(DmP_mant_SHT1_SW[37]), .QN(n6236) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1322), .CK(clk), .RN(n5250), .Q(
DmP_EXP_EWSW[38]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1321), .CK(clk), .RN(n2543),
.Q(DmP_mant_SHT1_SW[38]), .QN(n6235) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1320), .CK(clk), .RN(n2510), .Q(
DmP_EXP_EWSW[39]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1319), .CK(clk), .RN(n5249),
.Q(DmP_mant_SHT1_SW[39]), .QN(n6229) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1318), .CK(clk), .RN(n2511), .Q(
DmP_EXP_EWSW[40]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1317), .CK(clk), .RN(n6768),
.Q(DmP_mant_SHT1_SW[40]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1316), .CK(clk), .RN(n6743), .Q(
DmP_EXP_EWSW[41]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1315), .CK(clk), .RN(n6745),
.Q(DmP_mant_SHT1_SW[41]), .QN(n6230) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1314), .CK(clk), .RN(n2509), .Q(
DmP_EXP_EWSW[42]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1313), .CK(clk), .RN(n6768),
.Q(DmP_mant_SHT1_SW[42]), .QN(n3322) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1312), .CK(clk), .RN(n6741), .Q(
DmP_EXP_EWSW[43]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1311), .CK(clk), .RN(n7013),
.Q(DmP_mant_SHT1_SW[43]), .QN(n6237) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1310), .CK(clk), .RN(n2487), .Q(
DmP_EXP_EWSW[44]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1309), .CK(clk), .RN(n7013),
.Q(DmP_mant_SHT1_SW[44]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1308), .CK(clk), .RN(n2541), .Q(
DmP_EXP_EWSW[45]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1307), .CK(clk), .RN(n2511),
.Q(DmP_mant_SHT1_SW[45]), .QN(n6239) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1306), .CK(clk), .RN(n2504), .Q(
DmP_EXP_EWSW[46]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1305), .CK(clk), .RN(n2487),
.Q(DmP_mant_SHT1_SW[46]), .QN(n6238) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1304), .CK(clk), .RN(n2528), .Q(
DmP_EXP_EWSW[47]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1303), .CK(clk), .RN(n2528),
.Q(DmP_mant_SHT1_SW[47]), .QN(n6240) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1302), .CK(clk), .RN(n2528), .Q(
DmP_EXP_EWSW[48]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1301), .CK(clk), .RN(n2528),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1300), .CK(clk), .RN(n2528), .Q(
DmP_EXP_EWSW[49]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1299), .CK(clk), .RN(n2529),
.Q(DmP_mant_SHT1_SW[49]), .QN(n6241) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1298), .CK(clk), .RN(n7013), .Q(
DmP_EXP_EWSW[50]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1296), .CK(clk), .RN(n2528), .Q(
DmP_EXP_EWSW[51]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1295), .CK(clk), .RN(n2528),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1286), .CK(clk), .RN(n6728), .Q(
ZERO_FLAG_SHT1) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1283), .CK(clk), .RN(n5244), .Q(
ZERO_FLAG_NRM) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1280), .CK(clk), .RN(n6736), .Q(
OP_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1279), .CK(clk), .RN(n6739), .Q(
OP_FLAG_SHT2), .QN(n6247) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1275), .CK(clk), .RN(n6347), .Q(
SIGN_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1274), .CK(clk), .RN(n6347), .Q(
SIGN_FLAG_SHT2), .QN(n6185) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1271), .CK(clk), .RN(n6730),
.Q(SIGN_FLAG_SHT1SHT2), .QN(n6262) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n6377), .Q(
Raw_mant_NRM_SWR[0]), .QN(n6187) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1268), .CK(clk), .RN(n6382), .Q(
Raw_mant_NRM_SWR[1]), .QN(n6477) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1155), .CK(clk), .RN(n6382), .Q(
DmP_mant_SFG_SWR[1]), .QN(n3358) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1148), .CK(clk), .RN(n6726), .Q(
DmP_mant_SFG_SWR[8]), .QN(n3354) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1147), .CK(clk), .RN(n6726), .Q(
DmP_mant_SFG_SWR[9]), .QN(n3364) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1115), .CK(clk), .RN(n6729), .Q(
DmP_mant_SFG_SWR[41]), .QN(n6303) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1112), .CK(clk), .RN(n6729), .Q(
DmP_mant_SFG_SWR[44]), .QN(n3312) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1110), .CK(clk), .RN(n6729), .Q(
DmP_mant_SFG_SWR[46]), .QN(n3355) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1109), .CK(clk), .RN(n6729), .Q(
DmP_mant_SFG_SWR[47]), .QN(n3359) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1108), .CK(clk), .RN(n6729), .Q(
DmP_mant_SFG_SWR[48]), .QN(n6301) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1102), .CK(clk), .RN(n6725), .Q(
DmP_mant_SFG_SWR[54]), .QN(n3356) );
DFFSX2TS R_1 ( .D(n6902), .CK(clk), .SN(n6359), .Q(n6712) );
DFFSX2TS R_3 ( .D(n6901), .CK(clk), .SN(n6358), .Q(n6711) );
DFFSX1TS R_5 ( .D(n6998), .CK(clk), .SN(n6347), .Q(n6710) );
DFFSX1TS R_10 ( .D(n6974), .CK(clk), .SN(n6348), .Q(n6708) );
DFFSX2TS R_15 ( .D(n6905), .CK(clk), .SN(n6359), .Q(n6706) );
DFFSX2TS R_17 ( .D(n6904), .CK(clk), .SN(n6359), .Q(n6705) );
DFFSX1TS R_19 ( .D(n7003), .CK(clk), .SN(n6346), .Q(n6704) );
DFFSX1TS R_24 ( .D(n6924), .CK(clk), .SN(n6355), .Q(n6702) );
DFFSX1TS R_27 ( .D(n6932), .CK(clk), .SN(n6351), .Q(n6701) );
DFFSX1TS R_33 ( .D(n6938), .CK(clk), .SN(n6352), .Q(n6699) );
DFFSX1TS R_36 ( .D(n6934), .CK(clk), .SN(n6352), .Q(n6698) );
DFFSX1TS R_39 ( .D(n6954), .CK(clk), .SN(n6723), .Q(n6697) );
DFFSX1TS R_42 ( .D(n6944), .CK(clk), .SN(n6352), .Q(n6696) );
DFFSX1TS R_45 ( .D(n6941), .CK(clk), .SN(n6352), .Q(n6695) );
DFFSX1TS R_48 ( .D(n6977), .CK(clk), .SN(n6349), .Q(n6694) );
DFFSX1TS R_51 ( .D(n6931), .CK(clk), .SN(n6352), .Q(n6693) );
DFFSX1TS R_54 ( .D(n6947), .CK(clk), .SN(n6352), .Q(n6692) );
DFFSX1TS R_57 ( .D(n6899), .CK(clk), .SN(n6359), .Q(n6691) );
DFFSX1TS R_60 ( .D(n6900), .CK(clk), .SN(n6359), .Q(n6690) );
DFFSX1TS R_62 ( .D(n7005), .CK(clk), .SN(n6346), .Q(n6689) );
DFFSX2TS R_64 ( .D(exp_rslt_NRM2_EW1[7]), .CK(clk), .SN(n6346), .Q(n6688) );
DFFSX1TS R_67 ( .D(n6909), .CK(clk), .SN(n6359), .Q(n6687) );
DFFSX1TS R_70 ( .D(n6910), .CK(clk), .SN(n6359), .Q(n6686) );
DFFSX1TS R_73 ( .D(n6906), .CK(clk), .SN(n6359), .Q(n6685) );
DFFSX1TS R_76 ( .D(n6907), .CK(clk), .SN(n6359), .Q(n6684) );
DFFSX1TS R_79 ( .D(n6908), .CK(clk), .SN(n6358), .Q(n6683) );
DFFSX1TS R_81 ( .D(n6999), .CK(clk), .SN(n6346), .Q(n6682) );
DFFSX2TS R_85 ( .D(n6987), .CK(clk), .SN(n6349), .Q(n6680) );
DFFSX2TS R_87 ( .D(n6986), .CK(clk), .SN(n6349), .Q(n6679) );
DFFSX1TS R_89 ( .D(n7004), .CK(clk), .SN(n6345), .Q(n6678) );
DFFSX2TS R_91 ( .D(n2279), .CK(clk), .SN(n6345), .Q(n6677) );
DFFSX2TS R_93 ( .D(n6964), .CK(clk), .SN(n6350), .Q(n6676) );
DFFSX2TS R_95 ( .D(n6963), .CK(clk), .SN(n6350), .Q(n6675) );
DFFSX1TS R_97 ( .D(n7002), .CK(clk), .SN(n6345), .Q(n6674) );
DFFSX2TS R_99 ( .D(exp_rslt_NRM2_EW1[4]), .CK(clk), .SN(n6345), .Q(n6673) );
DFFSX2TS R_101 ( .D(n6950), .CK(clk), .SN(n6350), .Q(n6672) );
DFFSX1TS R_105 ( .D(n7007), .CK(clk), .SN(n2526), .Q(n6670) );
DFFSX2TS R_109 ( .D(n6912), .CK(clk), .SN(n6354), .Q(n6668) );
DFFSX2TS R_111 ( .D(n6911), .CK(clk), .SN(n6354), .Q(n6667) );
DFFSX1TS R_113 ( .D(n7006), .CK(clk), .SN(n6374), .Q(n6666) );
DFFSX2TS R_115 ( .D(exp_rslt_NRM2_EW1[8]), .CK(clk), .SN(n2526), .Q(n6665)
);
DFFSX2TS R_117 ( .D(n6918), .CK(clk), .SN(n6354), .Q(n6664) );
DFFSX2TS R_119 ( .D(n6917), .CK(clk), .SN(n6354), .Q(n6663) );
DFFSX1TS R_121 ( .D(n7001), .CK(clk), .SN(n6345), .Q(n6662) );
DFFSX2TS R_123 ( .D(n2297), .CK(clk), .SN(n6345), .Q(n6661) );
DFFSX1TS R_145 ( .D(n7000), .CK(clk), .SN(n6344), .Q(n6660) );
DFFSX2TS R_165 ( .D(n6916), .CK(clk), .SN(n6355), .Q(n6658) );
DFFSX2TS R_167 ( .D(n6915), .CK(clk), .SN(n6354), .Q(n6657) );
DFFSX2TS R_185 ( .D(n6968), .CK(clk), .SN(n6349), .Q(n6656) );
DFFSX2TS R_187 ( .D(n6967), .CK(clk), .SN(n6349), .Q(n6655) );
DFFSX2TS R_205 ( .D(n6962), .CK(clk), .SN(n6360), .Q(n6654) );
DFFSX2TS R_207 ( .D(n6961), .CK(clk), .SN(n6350), .Q(n6653) );
DFFSX2TS R_240 ( .D(n6960), .CK(clk), .SN(n6360), .Q(n6652) );
DFFSX2TS R_243 ( .D(n6959), .CK(clk), .SN(n6723), .Q(n6651) );
DFFSX2TS R_261 ( .D(n2349), .CK(clk), .SN(n6360), .Q(n6650) );
DFFSX2TS R_263 ( .D(n6951), .CK(clk), .SN(n5244), .Q(n6649) );
DFFSX2TS R_267 ( .D(n7008), .CK(clk), .SN(n6381), .Q(n6647) );
DFFSX2TS R_316 ( .D(n6922), .CK(clk), .SN(n6355), .Q(n6646) );
DFFSX2TS R_319 ( .D(n6921), .CK(clk), .SN(n6355), .Q(n6645) );
DFFSX1TS R_320 ( .D(n6782), .CK(clk), .SN(n2522), .Q(n6644) );
DFFSX2TS R_336 ( .D(n6920), .CK(clk), .SN(n6355), .Q(n6643) );
DFFSX2TS R_338 ( .D(n6919), .CK(clk), .SN(n6355), .Q(n6642) );
DFFSX2TS R_339 ( .D(n6926), .CK(clk), .SN(n6356), .Q(n6641) );
DFFSX2TS R_342 ( .D(n6925), .CK(clk), .SN(n6355), .Q(n6640) );
DFFSX2TS R_344 ( .D(n6958), .CK(clk), .SN(n6386), .Q(n6639) );
DFFSX2TS R_346 ( .D(n6957), .CK(clk), .SN(n5251), .Q(n6638) );
DFFSX1TS R_349 ( .D(n6993), .CK(clk), .SN(n6344), .Q(n6637) );
DFFSX1TS R_352 ( .D(n6983), .CK(clk), .SN(n6349), .Q(n6636) );
DFFSX1TS R_355 ( .D(n6980), .CK(clk), .SN(n6349), .Q(n6635) );
DFFSX1TS R_358 ( .D(n6991), .CK(clk), .SN(n6349), .Q(n6634) );
DFFSX1TS R_361 ( .D(n6997), .CK(clk), .SN(n6344), .Q(n6633) );
DFFSX2TS R_362 ( .D(n6949), .CK(clk), .SN(n6386), .Q(n6632) );
DFFSX2TS R_365 ( .D(n6948), .CK(clk), .SN(n5252), .Q(n6631) );
DFFSX2TS R_367 ( .D(n6928), .CK(clk), .SN(n6356), .Q(n6630) );
DFFSX2TS R_369 ( .D(n6927), .CK(clk), .SN(n6356), .Q(n6629) );
DFFSX2TS R_373 ( .D(n6984), .CK(clk), .SN(n6348), .Q(n6627) );
DFFSX2TS R_371 ( .D(n6985), .CK(clk), .SN(n6348), .Q(n6628) );
DFFSX2TS R_375 ( .D(n6966), .CK(clk), .SN(n5243), .Q(n6626) );
DFFSX2TS R_377 ( .D(n6965), .CK(clk), .SN(n5252), .Q(n6625) );
DFFSX1TS R_378 ( .D(n6808), .CK(clk), .SN(n6378), .Q(n6624) );
DFFSX2TS R_382 ( .D(n6956), .CK(clk), .SN(n6350), .Q(n6623) );
DFFSX2TS R_384 ( .D(n6955), .CK(clk), .SN(n5252), .Q(n6622) );
DFFSX2TS R_386 ( .D(n6204), .CK(clk), .SN(n6352), .Q(n6621) );
DFFSX2TS R_388 ( .D(n6935), .CK(clk), .SN(n6352), .Q(n6620) );
DFFSX2TS R_390 ( .D(n6914), .CK(clk), .SN(n6356), .Q(n6619) );
DFFSX2TS R_392 ( .D(n6913), .CK(clk), .SN(n6356), .Q(n6618) );
DFFSX2TS R_398 ( .D(n6930), .CK(clk), .SN(n6351), .Q(n6615) );
DFFSX2TS R_400 ( .D(n6929), .CK(clk), .SN(n6352), .Q(n6614) );
DFFSX2TS R_402 ( .D(n5616), .CK(clk), .SN(n6357), .Q(n6613) );
DFFSX2TS R_404 ( .D(n6923), .CK(clk), .SN(n6356), .Q(n6612) );
DFFSX2TS R_406 ( .D(n6903), .CK(clk), .SN(n6358), .Q(n6611) );
DFFRX1TS R_433 ( .D(n6717), .CK(clk), .RN(n6361), .Q(n6608) );
DFFSX1TS R_432 ( .D(n1713), .CK(clk), .SN(n6363), .Q(n6609) );
DFFSX1TS R_440 ( .D(n1721), .CK(clk), .SN(n6363), .Q(n6605) );
DFFRX1TS R_445 ( .D(n6717), .CK(clk), .RN(n6361), .Q(n6603) );
DFFRX1TS R_449 ( .D(n6717), .CK(clk), .RN(n6368), .Q(n6601) );
DFFSX1TS R_459 ( .D(n6798), .CK(clk), .SN(n6349), .Q(n6599) );
DFFSX1TS R_463 ( .D(n6817), .CK(clk), .SN(n6376), .Q(n6598) );
DFFSX2TS R_464 ( .D(n1700), .CK(clk), .SN(n6376), .Q(n6597) );
DFFSX2TS R_466 ( .D(n2471), .CK(clk), .SN(n6376), .Q(n6595) );
DFFSX2TS R_468 ( .D(n1740), .CK(clk), .SN(n6370), .QN(n2253) );
DFFRX1TS R_473 ( .D(n6719), .CK(clk), .RN(n6377), .Q(n6593) );
DFFSX1TS R_476 ( .D(n1703), .CK(clk), .SN(n6732), .Q(n6592) );
DFFSX2TS R_480 ( .D(n1736), .CK(clk), .SN(n6371), .Q(n6591) );
DFFSX2TS R_482 ( .D(n1919), .CK(clk), .SN(n6370), .Q(n6589) );
DFFSX2TS R_486 ( .D(n2471), .CK(clk), .SN(n6370), .Q(n6586) );
DFFRX1TS R_489 ( .D(n6719), .CK(clk), .RN(n6377), .Q(n6584) );
DFFSX1TS R_492 ( .D(n1707), .CK(clk), .SN(n5243), .Q(n6583) );
DFFSX2TS R_496 ( .D(n1732), .CK(clk), .SN(n6370), .Q(n6582) );
DFFSX2TS R_498 ( .D(n1919), .CK(clk), .SN(n6371), .Q(n6580) );
DFFSX2TS R_500 ( .D(n1704), .CK(clk), .SN(n6768), .Q(n6579) );
DFFRX1TS R_505 ( .D(n6719), .CK(clk), .RN(n6377), .Q(n6575) );
DFFSX1TS R_508 ( .D(n1711), .CK(clk), .SN(n2509), .Q(n6574) );
DFFSX2TS R_512 ( .D(n1708), .CK(clk), .SN(n5250), .Q(n6573) );
DFFRX1TS R_513 ( .D(n6718), .CK(clk), .RN(n6735), .Q(n6572) );
DFFSX2TS R_514 ( .D(n1919), .CK(clk), .SN(n6361), .Q(n6571) );
DFFSX2TS R_518 ( .D(n1919), .CK(clk), .SN(n6370), .Q(n6568) );
DFFRX1TS R_521 ( .D(n6719), .CK(clk), .RN(n6377), .Q(n6566) );
DFFSX1TS R_524 ( .D(n1719), .CK(clk), .SN(n2545), .Q(n6565) );
DFFSX2TS R_528 ( .D(n1712), .CK(clk), .SN(n5247), .Q(n6564) );
DFFSX2TS R_532 ( .D(n1733), .CK(clk), .SN(n6371), .Q(n6561) );
DFFSX2TS R_534 ( .D(n2471), .CK(clk), .SN(n6371), .Q(n6559) );
DFFSX2TS R_544 ( .D(n1716), .CK(clk), .SN(n5250), .Q(n6556) );
DFFRX1TS R_545 ( .D(n6718), .CK(clk), .RN(n6376), .Q(n6555) );
DFFSX2TS R_548 ( .D(n1701), .CK(clk), .SN(n6367), .Q(n6554) );
DFFSX2TS R_550 ( .D(n1919), .CK(clk), .SN(n6367), .Q(n6553) );
DFFSX1TS R_552 ( .D(n1734), .CK(clk), .SN(n6383), .Q(n6552) );
DFFRX1TS R_557 ( .D(n6719), .CK(clk), .RN(n2542), .Q(n6550) );
DFFSX2TS R_560 ( .D(n1720), .CK(clk), .SN(n6768), .Q(n6549) );
DFFSX2TS R_564 ( .D(n1709), .CK(clk), .SN(n6367), .Q(n6547) );
DFFSX2TS R_566 ( .D(n2471), .CK(clk), .SN(n6366), .Q(n6546) );
DFFRX1TS R_569 ( .D(n6719), .CK(clk), .RN(n6382), .Q(n6544) );
DFFSX2TS R_578 ( .D(n2471), .CK(clk), .SN(n6755), .Q(n6540) );
DFFSX2TS R_580 ( .D(n1737), .CK(clk), .SN(n6366), .Q(n2255) );
DFFSX2TS R_592 ( .D(n1705), .CK(clk), .SN(n6366), .Q(n6536) );
DFFSX2TS R_594 ( .D(n1919), .CK(clk), .SN(n6365), .Q(n6535) );
DFFSX2TS R_596 ( .D(n1741), .CK(clk), .SN(n6372), .Q(n6534) );
DFFSX2TS R_598 ( .D(n1919), .CK(clk), .SN(n6372), .Q(n6532) );
DFFRX1TS R_605 ( .D(n6719), .CK(clk), .RN(n6377), .Q(n6529) );
DFFSX2TS R_608 ( .D(n1718), .CK(clk), .SN(n2543), .Q(n6528) );
DFFSX2TS R_610 ( .D(n2471), .CK(clk), .SN(n6381), .Q(n6526) );
DFFSX2TS R_612 ( .D(n1749), .CK(clk), .SN(n6372), .Q(n6525) );
DFFRX1TS R_613 ( .D(n6718), .CK(clk), .RN(n6369), .Q(n6524) );
DFFSX1TS R_616 ( .D(n1726), .CK(clk), .SN(n6379), .Q(n6523) );
DFFRX1TS R_617 ( .D(n6719), .CK(clk), .RN(n6378), .Q(n6522) );
DFFSX2TS R_654 ( .D(n1727), .CK(clk), .SN(n2536), .Q(n6520) );
DFFSX2TS R_658 ( .D(n1715), .CK(clk), .SN(n6739), .Q(n6518) );
DFFSX2TS R_660 ( .D(n2471), .CK(clk), .SN(n2510), .Q(n6517) );
DFFRX1TS R_728 ( .D(n6883), .CK(clk), .RN(n6361), .Q(n6515) );
DFFRX1TS R_730 ( .D(n6797), .CK(clk), .RN(n2544), .Q(n6514) );
DFFRX1TS R_732 ( .D(n6788), .CK(clk), .RN(n6382), .Q(n6513) );
DFFRX1TS R_734 ( .D(n6812), .CK(clk), .RN(n6378), .Q(n6512) );
DFFRX1TS R_742 ( .D(n6863), .CK(clk), .RN(n6362), .Q(n6511) );
DFFRX1TS R_744 ( .D(n6796), .CK(clk), .RN(n6382), .Q(n6510) );
DFFRX1TS R_746 ( .D(n6805), .CK(clk), .RN(n2508), .Q(n6509) );
DFFRX1TS R_748 ( .D(n6822), .CK(clk), .RN(n6376), .Q(n6508) );
DFFRX1TS R_750 ( .D(n6827), .CK(clk), .RN(n6368), .Q(n6507) );
DFFRX1TS R_766 ( .D(n6844), .CK(clk), .RN(n6369), .Q(n6506) );
DFFRX1TS R_768 ( .D(n6802), .CK(clk), .RN(n6377), .Q(n6505) );
DFFRX1TS R_770 ( .D(n6824), .CK(clk), .RN(n6376), .Q(n6504) );
DFFRX1TS R_772 ( .D(n6803), .CK(clk), .RN(n6731), .Q(n6503) );
DFFRX1TS R_774 ( .D(n6804), .CK(clk), .RN(n6378), .Q(n6502) );
DFFRX1TS R_782 ( .D(n6888), .CK(clk), .RN(n6362), .Q(n6501) );
DFFRX1TS R_784 ( .D(n6828), .CK(clk), .RN(n6369), .Q(n6500) );
DFFRX1TS R_786 ( .D(n6800), .CK(clk), .RN(n6377), .Q(n6499) );
DFFRX1TS R_788 ( .D(n6801), .CK(clk), .RN(n6351), .Q(n6498) );
DFFRX1TS R_794 ( .D(n6994), .CK(clk), .RN(n6344), .Q(n6496) );
DFFRX1TS R_797 ( .D(n6873), .CK(clk), .RN(n6362), .Q(n6495) );
DFFRX1TS R_799 ( .D(n6823), .CK(clk), .RN(n6745), .Q(n6494) );
DFFRX1TS R_801 ( .D(n6818), .CK(clk), .RN(n6376), .Q(n6493) );
DFFRX1TS R_805 ( .D(n6790), .CK(clk), .RN(n6383), .Q(n6491) );
DFFRX1TS R_812 ( .D(n6826), .CK(clk), .RN(n6368), .Q(n6489) );
DFFRX1TS R_814 ( .D(n6820), .CK(clk), .RN(n6375), .Q(n6488) );
DFFRX1TS R_816 ( .D(n6789), .CK(clk), .RN(n2543), .Q(n6487) );
DFFRX1TS R_818 ( .D(n6792), .CK(clk), .RN(n6382), .Q(n6486) );
DFFSX1TS R_821 ( .D(n6814), .CK(clk), .SN(n6379), .Q(n6485) );
DFFRX1TS R_840 ( .D(n6849), .CK(clk), .RN(n6369), .Q(n6468) );
DFFRX1TS R_842 ( .D(n6825), .CK(clk), .RN(n6376), .Q(n6467) );
DFFRX1TS R_844 ( .D(n6791), .CK(clk), .RN(n2541), .Q(n6466) );
DFFRX1TS R_846 ( .D(n6893), .CK(clk), .RN(n6362), .Q(n6465) );
DFFRX1TS R_848 ( .D(n6786), .CK(clk), .RN(n6383), .Q(n6464) );
DFFRX1TS R_856 ( .D(n6878), .CK(clk), .RN(n6362), .Q(n6462) );
DFFRX1TS R_862 ( .D(n6787), .CK(clk), .RN(n2487), .Q(n6459) );
DFFRX1TS R_880 ( .D(n6793), .CK(clk), .RN(n6749), .Q(n6454) );
DFFRX1TS R_882 ( .D(n6810), .CK(clk), .RN(n6734), .Q(n6453) );
DFFRX1TS R_884 ( .D(n6819), .CK(clk), .RN(n6745), .Q(n6452) );
DFFSX2TS R_885 ( .D(n2418), .CK(clk), .SN(n6364), .Q(n6451) );
DFFRX1TS R_890 ( .D(n6795), .CK(clk), .RN(n2528), .Q(n6448) );
DFFRX1TS R_893 ( .D(n6854), .CK(clk), .RN(n6362), .Q(n6447) );
DFFRX1TS R_895 ( .D(n6839), .CK(clk), .RN(n6369), .Q(n6446) );
DFFRX1TS R_897 ( .D(n6807), .CK(clk), .RN(n6378), .Q(n6445) );
DFFSX2TS R_961 ( .D(n6832), .CK(clk), .SN(n6384), .Q(n6436) );
DFFSX2TS R_962 ( .D(n6720), .CK(clk), .SN(n6384), .Q(n6435) );
DFFSX2TS R_978 ( .D(n6784), .CK(clk), .SN(n2529), .Q(n6433) );
DFFSX2TS R_979 ( .D(n6720), .CK(clk), .SN(n2529), .Q(n6432) );
DFFSX2TS R_987 ( .D(n6874), .CK(clk), .SN(n6364), .Q(n6430) );
DFFSX2TS R_1024 ( .D(n6834), .CK(clk), .SN(n2529), .Q(n6426) );
DFFSX2TS R_1254 ( .D(n6815), .CK(clk), .SN(n5251), .Q(n6392) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1284), .CK(clk), .RN(n5244), .Q(
ZERO_FLAG_SFG), .QN(n6319) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1273), .CK(clk), .RN(n6347), .Q(
SIGN_FLAG_SFG), .QN(n6318) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1451), .CK(clk), .RN(n6739), .Q(
DMP_SFG[52]), .QN(n6315) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1446), .CK(clk), .RN(n6736), .Q(
DMP_SFG[53]), .QN(n6314) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1441), .CK(clk), .RN(n6753), .Q(
DMP_SFG[54]), .QN(n6313) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_55_ ( .D(n2378), .CK(clk), .RN(n2542), .Q(
DMP_SFG[55]), .QN(n6312) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_56_ ( .D(n2377), .CK(clk), .RN(n2508), .Q(
DMP_SFG[56]), .QN(n6311) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1426), .CK(clk), .RN(n6754), .Q(
DMP_SFG[57]), .QN(n6310) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1421), .CK(clk), .RN(n6754), .Q(
DMP_SFG[58]), .QN(n6309) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1416), .CK(clk), .RN(n6755), .Q(
DMP_SFG[59]), .QN(n6308) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1411), .CK(clk), .RN(n6756), .Q(
DMP_SFG[60]), .QN(n6307) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1406), .CK(clk), .RN(n6756), .Q(
DMP_SFG[61]), .QN(n6306) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1401), .CK(clk), .RN(n6757), .Q(
DMP_SFG[62]), .QN(n6305) );
DFFRXLTS R_865 ( .D(final_result_ieee[63]), .CK(clk), .RN(n2510), .Q(n6457)
);
DFFRXLTS R_850 ( .D(overflow_flag), .CK(clk), .RN(n6723), .Q(n6463) );
DFFSX2TS R_1196 ( .D(n7012), .CK(clk), .SN(n6723), .Q(n6402) );
DFFSX2TS R_1195 ( .D(n2325), .CK(clk), .SN(n5244), .Q(n6403) );
DFFSX2TS R_1197 ( .D(n6772), .CK(clk), .SN(n6728), .Q(n6401) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1281), .CK(clk), .RN(n5244), .Q(
zero_flag) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1452), .CK(clk), .RN(n6737), .QN(
n6108) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1447), .CK(clk), .RN(n6752), .QN(
n6107) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1442), .CK(clk), .RN(n6753), .QN(
n6106) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1437), .CK(clk), .RN(n6735), .QN(
n6105) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1432), .CK(clk), .RN(n2503), .QN(
n6104) );
DFFSX2TS R_951 ( .D(n2383), .CK(clk), .SN(n6379), .Q(n6437) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1289), .CK(clk), .RN(n2543), .Q(
DmP_EXP_EWSW[57]), .QN(n6268) );
DFFSX2TS R_966 ( .D(n2383), .CK(clk), .SN(n6380), .Q(n6434) );
DFFSX2TS R_980 ( .D(n2415), .CK(clk), .SN(n6384), .Q(n6431) );
DFFSX2TS R_990 ( .D(n2383), .CK(clk), .SN(n6385), .Q(n6429) );
DFFSX2TS R_1000 ( .D(n2415), .CK(clk), .SN(n6385), .Q(n6428) );
DFFSX2TS R_1048 ( .D(n2484), .CK(clk), .SN(n6365), .Q(n6424) );
DFFSX2TS R_1058 ( .D(n2485), .CK(clk), .SN(n6365), .Q(n6422) );
DFFSX2TS R_1068 ( .D(n2418), .CK(clk), .SN(n6365), .Q(n6420) );
DFFSX2TS R_1088 ( .D(n2485), .CK(clk), .SN(n2510), .Q(n6418) );
DFFSX2TS R_1102 ( .D(n2418), .CK(clk), .SN(n6365), .Q(n6412) );
DFFSX2TS R_1114 ( .D(n2484), .CK(clk), .SN(n6366), .Q(n6411) );
DFFSX2TS R_1129 ( .D(n2484), .CK(clk), .SN(n6367), .Q(n6409) );
DFFSX2TS R_1256 ( .D(n6859), .CK(clk), .SN(n6367), .Q(n6391) );
DFFSX2TS R_1015 ( .D(n2383), .CK(clk), .SN(n2536), .Q(n6427) );
DFFSX2TS R_656 ( .D(n1919), .CK(clk), .SN(n2536), .Q(n6519) );
DFFSX2TS R_887 ( .D(n6897), .CK(clk), .SN(n6364), .Q(n6450) );
DFFSX2TS R_888 ( .D(n6720), .CK(clk), .SN(n6365), .Q(n6449) );
DFFSX2TS R_949 ( .D(n1751), .CK(clk), .SN(n6384), .Q(n6438) );
DFFSX2TS R_1080 ( .D(n2485), .CK(clk), .SN(n2545), .Q(n6419) );
DFFSX2TS R_1090 ( .D(n2418), .CK(clk), .SN(n2511), .Q(n6417) );
DFFSX2TS R_1261 ( .D(n6894), .CK(clk), .SN(n6383), .Q(n6387) );
DFFSX2TS sub_x_5_R_755 ( .D(n6081), .CK(clk), .SN(n2516), .Q(sub_x_5_n266),
.QN(n6088) );
DFFSX2TS sub_x_5_R_1166 ( .D(n6083), .CK(clk), .SN(n6730), .Q(sub_x_5_n627)
);
DFFSX2TS sub_x_5_R_756 ( .D(n6082), .CK(clk), .SN(n2516), .Q(sub_x_5_n611)
);
DFFSX2TS sub_x_5_R_1181 ( .D(n2683), .CK(clk), .SN(n2516), .Q(sub_x_5_n610)
);
DFFSX2TS sub_x_5_R_1168 ( .D(n6084), .CK(clk), .SN(n2508), .Q(sub_x_5_n424),
.QN(n6087) );
DFFRXLTS add_x_6_R_1202 ( .D(n1135), .CK(clk), .RN(n2532), .Q(add_x_6_B_21_)
);
DFFSX2TS add_x_6_R_1139 ( .D(n6037), .CK(clk), .SN(n2521), .Q(add_x_6_n193)
);
DFFSX2TS add_x_6_R_704 ( .D(n6030), .CK(clk), .SN(n2522), .Q(add_x_6_n185),
.QN(n6064) );
DFFSX2TS add_x_6_R_1219 ( .D(n6051), .CK(clk), .SN(n2504), .Q(add_x_6_n163),
.QN(n6063) );
DFFSX2TS add_x_6_R_1189 ( .D(n6045), .CK(clk), .SN(n2539), .Q(add_x_6_n521),
.QN(n6076) );
DFFSX2TS add_x_6_R_1241 ( .D(n6055), .CK(clk), .SN(n6737), .Q(add_x_6_n477),
.QN(n6080) );
DFFSX2TS add_x_6_R_1244 ( .D(n2344), .CK(clk), .SN(n2487), .Q(add_x_6_n488),
.QN(n6069) );
DFFSX2TS add_x_6_R_1142 ( .D(n6026), .CK(clk), .SN(n2534), .Q(add_x_6_n259),
.QN(n6070) );
DFFSX2TS add_x_6_R_1204 ( .D(n6028), .CK(clk), .SN(n2534), .Q(add_x_6_n248),
.QN(n6079) );
DFFSX2TS add_x_6_R_1035 ( .D(n6032), .CK(clk), .SN(n6742), .Q(add_x_6_n423),
.QN(n6074) );
DFFSX1TS add_x_6_R_1245 ( .D(n6036), .CK(clk), .SN(n2492), .Q(add_x_6_n492)
);
DFFRX2TS add_x_6_R_1246 ( .D(n6056), .CK(clk), .RN(n2492), .Q(add_x_6_n483),
.QN(n6075) );
DFFSX2TS add_x_6_R_1235 ( .D(n6054), .CK(clk), .SN(n6735), .Q(add_x_6_n343),
.QN(n6072) );
DFFRX1TS add_x_6_R_1221 ( .D(n1111), .CK(clk), .RN(n2504), .Q(add_x_6_B_45_)
);
DFFRX2TS add_x_6_R_1220 ( .D(n1478), .CK(clk), .RN(n2503), .Q(add_x_6_A_45_)
);
DFFRX2TS add_x_6_R_1206 ( .D(n6048), .CK(clk), .RN(n2533), .Q(add_x_6_n241)
);
DFFSX2TS add_x_6_R_1203 ( .D(n6047), .CK(clk), .SN(n2499), .Q(add_x_6_n244)
);
DFFSX1TS add_x_6_R_1186 ( .D(n6044), .CK(clk), .SN(n6766), .Q(add_x_6_n534)
);
DFFRX2TS add_x_6_R_1158 ( .D(n2135), .CK(clk), .RN(n2524), .Q(add_x_6_B_2_)
);
DFFSX1TS add_x_6_R_1184 ( .D(n6040), .CK(clk), .SN(n6767), .Q(add_x_6_n536)
);
DFFSX1TS add_x_6_R_1144 ( .D(n6031), .CK(clk), .SN(n2534), .Q(add_x_6_n260)
);
DFFRX2TS add_x_6_R_1145 ( .D(n6038), .CK(clk), .RN(n2533), .Q(add_x_6_n254),
.QN(n6078) );
DFFSX1TS add_x_6_R_1037 ( .D(n6035), .CK(clk), .SN(n2532), .Q(add_x_6_n418)
);
DFFRX2TS add_x_6_R_1036 ( .D(n6034), .CK(clk), .RN(n2531), .Q(add_x_6_n412),
.QN(n6077) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1130), .CK(clk), .RN(n6727), .Q(
DmP_mant_SFG_SWR[26]), .QN(n3327) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1239), .CK(clk), .RN(n6757), .Q(
Raw_mant_NRM_SWR[30]), .QN(n6116) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1127), .CK(clk), .RN(n6727), .Q(
DmP_mant_SFG_SWR[29]), .QN(sub_x_5_n615) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1499), .CK(clk), .RN(n2499), .Q(
DMP_SFG[36]), .QN(n6269) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1128), .CK(clk), .RN(n6727), .Q(
DmP_mant_SFG_SWR[28]), .QN(n3313) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1237), .CK(clk), .RN(n2509), .Q(
Raw_mant_NRM_SWR[32]), .QN(n6243) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1586), .CK(clk), .RN(n2522), .Q(
DMP_SFG[7]), .QN(n6270) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1131), .CK(clk), .RN(n6727), .Q(
DmP_mant_SFG_SWR[25]), .QN(n3344) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1547), .CK(clk), .RN(n6735), .Q(
DMP_SFG[20]), .QN(n6273) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1529), .CK(clk), .RN(n6745), .Q(
DMP_SFG[26]), .QN(n6279) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1140), .CK(clk), .RN(n6725), .Q(
DmP_mant_SFG_SWR[16]), .QN(n3351) );
DFFRX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1276), .CK(clk), .RN(n6725),
.Q(ADD_OVRFLW_NRM2), .QN(n6715) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1133), .CK(clk), .RN(n6727), .Q(
DmP_mant_SFG_SWR[23]), .QN(n3345) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1472), .CK(clk), .RN(n6750), .Q(
DMP_SFG[45]), .QN(n6291) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1141), .CK(clk), .RN(n5245), .Q(
DmP_mant_SFG_SWR[15]), .QN(n6299) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1126), .CK(clk), .RN(n6727), .Q(
DmP_mant_SFG_SWR[30]), .QN(n3347) );
DFFRX4TS R_923 ( .D(n1145), .CK(clk), .RN(n5245), .Q(DmP_mant_SFG_SWR[11]),
.QN(n3317) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1228), .CK(clk), .RN(n6737), .Q(
Raw_mant_NRM_SWR[41]), .QN(n6207) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1235), .CK(clk), .RN(n6733), .Q(
Raw_mant_NRM_SWR[34]), .QN(n6124) );
DFFRX4TS R_425 ( .D(n1121), .CK(clk), .RN(n2516), .Q(DmP_mant_SFG_SWR[35]),
.QN(n3319) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1469), .CK(clk), .RN(n6750), .Q(
DMP_SFG[46]), .QN(n6293) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1142), .CK(clk), .RN(n5245), .Q(
DmP_mant_SFG_SWR[14]), .QN(n6302) );
DFFRX4TS R_1161 ( .D(n1153), .CK(clk), .RN(n6726), .Q(DmP_mant_SFG_SWR[3]),
.QN(n3363) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1132), .CK(clk), .RN(n6727), .Q(
DmP_mant_SFG_SWR[24]), .QN(n3348) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1117), .CK(clk), .RN(n2516), .Q(
DmP_mant_SFG_SWR[39]), .QN(n6304) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1263), .CK(clk), .RN(n5250), .Q(
Raw_mant_NRM_SWR[6]), .QN(n6110) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1125), .CK(clk), .RN(n2515), .Q(
DmP_mant_SFG_SWR[31]), .QN(n3346) );
DFFRX4TS R_1150 ( .D(n1136), .CK(clk), .RN(n2511), .Q(DmP_mant_SFG_SWR[20]),
.QN(sub_x_5_n624) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1481), .CK(clk), .RN(n2503), .Q(
DMP_SFG[42]), .QN(n6278) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1105), .CK(clk), .RN(n6361), .Q(
DmP_mant_SFG_SWR[51]), .QN(n3362) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1124), .CK(clk), .RN(n2515), .Q(
DmP_mant_SFG_SWR[32]), .QN(n6297) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1259), .CK(clk), .RN(n2511), .Q(
Raw_mant_NRM_SWR[10]), .QN(n6193) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1460), .CK(clk), .RN(n6730), .Q(
DMP_SFG[49]), .QN(n6294) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1490), .CK(clk), .RN(n6731), .Q(
DMP_SFG[39]), .QN(n6282) );
DFFRX2TS R_1212 ( .D(n1574), .CK(clk), .RN(n6739), .Q(DMP_SFG[11]), .QN(
n6326) );
DFFRX4TS R_630 ( .D(n2851), .CK(clk), .RN(n2516), .Q(DmP_mant_SFG_SWR[36]),
.QN(sub_x_5_n608) );
DFFRX4TS R_674 ( .D(n2016), .CK(clk), .RN(n2515), .Q(DmP_mant_SFG_SWR[37]),
.QN(sub_x_5_n607) );
DFFRX4TS R_703 ( .D(n1113), .CK(clk), .RN(n6729), .Q(DmP_mant_SFG_SWR[43]),
.QN(sub_x_5_n601) );
DFFRX2TS add_x_6_R_1153 ( .D(n1136), .CK(clk), .RN(n2531), .Q(add_x_6_B_20_)
);
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1103), .CK(clk), .RN(n6375), .Q(
DmP_mant_SFG_SWR[53]), .QN(n3357) );
DFFRX2TS add_x_6_R_628 ( .D(sub_x_5_B_34_), .CK(clk), .RN(n2533), .Q(
add_x_6_B_34_) );
DFFRX2TS R_1239 ( .D(n1577), .CK(clk), .RN(n6737), .Q(DMP_SFG[10]), .QN(
n6327) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1118), .CK(clk), .RN(n2515), .Q(
DmP_mant_SFG_SWR[38]), .QN(n3349) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1253), .CK(clk), .RN(n2491), .Q(
Raw_mant_NRM_SWR[16]), .QN(n6242) );
DFFRX2TS R_922 ( .D(n1580), .CK(clk), .RN(n2543), .Q(DMP_SFG[9]), .QN(n6256)
);
DFFRX2TS add_x_6_R_1152 ( .D(n1553), .CK(clk), .RN(n2531), .Q(add_x_6_A_20_)
);
DFFRX4TS R_1229 ( .D(n1149), .CK(clk), .RN(n6726), .Q(DmP_mant_SFG_SWR[7]),
.QN(n3360) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1224), .CK(clk), .RN(n6745), .Q(
Raw_mant_NRM_SWR[45]), .QN(n6713) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1697), .CK(clk), .RN(n2541),
.Q(shift_value_SHT2_EWR[2]), .QN(n6200) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1695), .CK(clk), .RN(n6748),
.Q(shift_value_SHT2_EWR[4]), .QN(n6198) );
DFFRX2TS add_x_6_R_1140 ( .D(n1487), .CK(clk), .RN(n2520), .Q(add_x_6_A_42_)
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1240), .CK(clk), .RN(n5243), .Q(
Raw_mant_NRM_SWR[29]), .QN(n6131) );
DFFRX4TS R_1218 ( .D(n1111), .CK(clk), .RN(n6729), .Q(DmP_mant_SFG_SWR[45]),
.QN(n3365) );
DFFRX4TS R_1160 ( .D(n1604), .CK(clk), .RN(n7013), .Q(DMP_SFG[1]), .QN(n6250) );
DFFRX2TS sub_x_5_R_1180 ( .D(n6085), .CK(clk), .RN(n2516), .Q(sub_x_5_n260),
.QN(n6086) );
DFFRX4TS R_1123 ( .D(n1146), .CK(clk), .RN(n6726), .Q(DmP_mant_SFG_SWR[10]),
.QN(sub_x_5_n634) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1267), .CK(clk), .RN(n6735), .Q(
Raw_mant_NRM_SWR[2]), .QN(n6194) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1246), .CK(clk), .RN(n2491), .Q(
Raw_mant_NRM_SWR[23]), .QN(n6111) );
DFFRX2TS add_x_6_R_706 ( .D(n1113), .CK(clk), .RN(n2520), .Q(add_x_6_B_43_)
);
DFFSX4TS R_1222 ( .D(n6894), .CK(clk), .SN(n2529), .Q(n6400) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1475), .CK(clk), .RN(n2503), .Q(
DMP_SFG[44]), .QN(n6289) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1493), .CK(clk), .RN(n2541), .Q(
DMP_SFG[38]), .QN(n6271) );
DFFRX4TS R_1149 ( .D(n1553), .CK(clk), .RN(n2531), .Q(DMP_SFG[18]), .QN(
n6325) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1496), .CK(clk), .RN(n2496), .Q(
DMP_SFG[37]), .QN(n6283) );
DFFRX4TS R_1154 ( .D(n1607), .CK(clk), .RN(n7013), .Q(DMP_SFG[0]), .QN(n6254) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n1754), .CK(clk), .RN(n2526),
.Q(bit_shift_SHT2), .QN(n6203) );
DFFRX4TS R_1228 ( .D(n1592), .CK(clk), .RN(n6728), .Q(DMP_SFG[5]), .QN(n6321) );
DFFRX2TS add_x_6_R_1191 ( .D(n1150), .CK(clk), .RN(n2538), .Q(add_x_6_B_6_)
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1229), .CK(clk), .RN(n6752), .Q(
Raw_mant_NRM_SWR[40]), .QN(n6244) );
DFFRX4TS R_1234 ( .D(n1129), .CK(clk), .RN(n6727), .Q(DmP_mant_SFG_SWR[27]),
.QN(n6335) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1589), .CK(clk), .RN(n6723), .Q(
DMP_SFG[6]), .QN(n6274) );
DFFRX4TS R_1208 ( .D(n1151), .CK(clk), .RN(n6726), .Q(n2134), .QN(n6333) );
DFFRX2TS R_1198 ( .D(n1550), .CK(clk), .RN(n2531), .Q(DMP_SFG[19]), .QN(
n6320) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1222), .CK(clk), .RN(n2546), .Q(
Raw_mant_NRM_SWR[47]), .QN(n6115) );
DFFRX2TS R_1138 ( .D(n1114), .CK(clk), .RN(n6729), .Q(DmP_mant_SFG_SWR[42]),
.QN(n6334) );
DFFRX4TS R_424 ( .D(n1508), .CK(clk), .RN(n2533), .Q(DMP_SFG[33]), .QN(n6249) );
DFFRX4TS R_1240 ( .D(n1144), .CK(clk), .RN(n5248), .Q(n2382), .QN(n6331) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1236), .CK(clk), .RN(n2508), .Q(
Raw_mant_NRM_SWR[33]), .QN(n6126) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1248), .CK(clk), .RN(n2491), .Q(
Raw_mant_NRM_SWR[21]), .QN(n6136) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1291), .CK(clk), .RN(n6737), .Q(
DmP_EXP_EWSW[55]), .QN(sub_x_1_n31) );
DFFRX4TS R_629 ( .D(n1505), .CK(clk), .RN(n2533), .Q(DMP_SFG[34]), .QN(n6255) );
DFFRX2TS add_x_6_R_1242 ( .D(n1577), .CK(clk), .RN(n6752), .Q(add_x_6_A_12_)
);
DFFRX4TS R_1213 ( .D(n1143), .CK(clk), .RN(n2491), .Q(DmP_mant_SFG_SWR[13]),
.QN(n6336) );
DFFSX4TS R_1101 ( .D(n6894), .CK(clk), .SN(n6380), .Q(n6413) );
DFFRX2TS sub_x_5_R_1182 ( .D(n1511), .CK(clk), .RN(n2516), .Q(sub_x_5_A_34_)
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1223), .CK(clk), .RN(n6375), .Q(
Raw_mant_NRM_SWR[46]), .QN(n6122) );
DFFRX4TS R_1224 ( .D(n1152), .CK(clk), .RN(n6726), .Q(n2424), .QN(n6337) );
DFFRX4TS R_1187 ( .D(n1595), .CK(clk), .RN(n2538), .Q(DMP_SFG[4]), .QN(n6316) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1234), .CK(clk), .RN(n6743), .Q(
Raw_mant_NRM_SWR[35]), .QN(n6127) );
DFFSX4TS add_x_6_R_1159 ( .D(n6041), .CK(clk), .SN(n2534), .Q(add_x_6_n251)
);
DFFSRHQX4TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1272), .CK(clk), .SN(1'b1), .RN(
n2525), .Q(SIGN_FLAG_NRM) );
DFFSRHQX4TS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1407), .CK(clk), .SN(1'b1), .RN(
n2524), .Q(DMP_SHT2_EWSW[61]) );
DFFSRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1387), .CK(clk), .SN(1'b1),
.RN(n2525), .Q(DmP_mant_SHT1_SW[5]) );
DFFRHQX2TS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1427), .CK(clk), .RN(n2524), .Q(
n6022) );
DFFRHQX2TS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1428), .CK(clk), .RN(n2525), .Q(
n6021) );
DFFSRHQX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1282), .CK(clk), .SN(1'b1),
.RN(n2524), .Q(ZERO_FLAG_SHT1SHT2) );
DFFSRHQX4TS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1408), .CK(clk), .SN(1'b1), .RN(
n2524), .Q(DMP_SHT1_EWSW[61]) );
DFFSRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1297), .CK(clk), .SN(1'b1),
.RN(n2525), .Q(DmP_mant_SHT1_SW[50]) );
DFFRHQX1TS add_x_6_R_1157 ( .D(n1607), .CK(clk), .RN(n6769), .Q(add_x_6_A_2_) );
DFFSX4TS R_620 ( .D(n1699), .CK(clk), .SN(n2545), .Q(n6521) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1617), .CK(clk), .RN(n2524), .Q(
DMP_EXP_EWSW[58]) );
DFFRHQX8TS inst_ShiftRegister_Q_reg_3_ ( .D(n1887), .CK(clk), .RN(n2524),
.Q(Shift_reg_FLAGS_7[3]) );
DFFRHQX1TS R_1178 ( .D(sub_x_5_B_34_), .CK(clk), .RN(n2525), .Q(n6017) );
DFFSX1TS R_83 ( .D(exp_rslt_NRM2_EW1[1]), .CK(clk), .SN(n6346), .Q(n6681) );
DFFSX4TS R_832 ( .D(n6777), .CK(clk), .SN(n2544), .Q(n6475), .QN(n2343) );
DFFSX4TS add_x_6_R_1151 ( .D(n6039), .CK(clk), .SN(n5244), .Q(add_x_6_n406),
.QN(n6060) );
DFFSHQX8TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n6016), .CK(clk), .SN(n6769),
.Q(n6120) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1572), .CK(clk), .RN(n6740), .Q(
DMP_SHT2_EWSW[12]), .QN(n6181) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1554), .CK(clk), .RN(n2532), .Q(
DMP_SHT2_EWSW[18]), .QN(n6175) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1518), .CK(clk), .RN(n6747), .Q(
DMP_SHT2_EWSW[30]), .QN(n6163) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1476), .CK(clk), .RN(n2504), .Q(
DMP_SHT2_EWSW[44]), .QN(n6149) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1455), .CK(clk), .RN(n6751), .Q(
DMP_SHT2_EWSW[51]), .QN(n6142) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1343), .CK(clk), .RN(n2536),
.Q(DmP_mant_SHT1_SW[27]), .QN(n6213) );
DFFSX1TS R_7 ( .D(exp_rslt_NRM2_EW1[0]), .CK(clk), .SN(n6347), .Q(n6709) );
DFFSX1TS R_21 ( .D(n2330), .CK(clk), .SN(n6346), .Q(n6703) );
DFFRXLTS R_103 ( .D(final_result_ieee[31]), .CK(clk), .RN(n6350), .Q(n6671)
);
DFFSX1TS R_147 ( .D(n2276), .CK(clk), .SN(n6345), .Q(n6659) );
DFFRXLTS R_437 ( .D(n6717), .CK(clk), .RN(n6361), .Q(n6606) );
DFFRXLTS R_790 ( .D(n6809), .CK(clk), .RN(n6378), .Q(n6497) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1264), .CK(clk), .RN(n2520), .Q(
Raw_mant_NRM_SWR[5]), .QN(n6117) );
DFFRX4TS R_1008 ( .D(n1556), .CK(clk), .RN(n2531), .Q(DMP_SFG[17]), .QN(
n6251) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1262), .CK(clk), .RN(n2508), .Q(
Raw_mant_NRM_SWR[7]), .QN(n6113) );
DFFRX4TS R_754 ( .D(n1514), .CK(clk), .RN(n6747), .Q(DMP_SFG[31]), .QN(n6329) );
DFFRX4TS R_753 ( .D(sub_x_5_B_33_), .CK(clk), .RN(n2515), .Q(
DmP_mant_SFG_SWR[33]), .QN(n6258) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1227), .CK(clk), .RN(n6742), .Q(
Raw_mant_NRM_SWR[42]), .QN(n6135) );
DFFRX4TS R_1223 ( .D(n1601), .CK(clk), .RN(n2538), .Q(DMP_SFG[2]), .QN(n6322) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1623), .CK(clk), .RN(n6770), .Q(
DMP_EXP_EWSW[52]), .QN(n6343) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1622), .CK(clk), .RN(n6753), .Q(
DMP_EXP_EWSW[53]), .QN(n6342) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1252), .CK(clk), .RN(n6735), .Q(
Raw_mant_NRM_SWR[17]), .QN(n6125) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1257), .CK(clk), .RN(n2535), .Q(
Raw_mant_NRM_SWR[12]), .QN(n6245) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1226), .CK(clk), .RN(n6735), .Q(
Raw_mant_NRM_SWR[43]), .QN(n6137) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1243), .CK(clk), .RN(n6375), .Q(
Raw_mant_NRM_SWR[26]), .QN(n6133) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1249), .CK(clk), .RN(n2528), .Q(
Raw_mant_NRM_SWR[20]), .QN(n6202) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1242), .CK(clk), .RN(n2510), .Q(
Raw_mant_NRM_SWR[27]), .QN(n6260) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1466), .CK(clk), .RN(n2496), .Q(
DMP_SFG[47]), .QN(n6281) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1225), .CK(clk), .RN(n6748), .Q(
Raw_mant_NRM_SWR[44]), .QN(n6197) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n6121), .CK(clk), .RN(n6725),
.Q(LZD_output_NRM2_EW[3]), .QN(n6199) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1231), .CK(clk), .RN(n6770), .Q(
Raw_mant_NRM_SWR[38]), .QN(n6128) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1247), .CK(clk), .RN(n6730), .Q(
Raw_mant_NRM_SWR[22]), .QN(n6109) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1212), .CK(clk), .RN(n6725),
.Q(LZD_output_NRM2_EW[1]), .QN(n6201) );
DFFRX4TS R_837 ( .D(N89), .CK(clk), .RN(n6733), .Q(n6470) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1621), .CK(clk), .RN(n6753), .Q(
DMP_EXP_EWSW[54]), .QN(n6341) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1266), .CK(clk), .RN(n2503), .Q(
Raw_mant_NRM_SWR[3]), .QN(n6091) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1463), .CK(clk), .RN(n2496), .Q(
DMP_SFG[48]), .QN(n6277) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1230), .CK(clk), .RN(n6739), .Q(
Raw_mant_NRM_SWR[39]), .QN(n6129) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1232), .CK(clk), .RN(n6736), .Q(
Raw_mant_NRM_SWR[37]), .QN(n6134) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1209), .CK(clk), .RN(n6725),
.Q(LZD_output_NRM2_EW[5]), .QN(n6196) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1294), .CK(clk), .RN(n6752), .Q(
DmP_EXP_EWSW[52]), .QN(n3332) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1293), .CK(clk), .RN(n6770), .Q(
DmP_EXP_EWSW[53]), .QN(sub_x_1_n33) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1753), .CK(clk), .RN(n6725),
.Q(left_right_SHT2), .QN(n2381) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1255), .CK(clk), .RN(n2496), .Q(
Raw_mant_NRM_SWR[14]), .QN(n6114) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1544), .CK(clk), .RN(n6748), .Q(
DMP_SFG[21]), .QN(n6286) );
DFFRX4TS add_x_6_R_1226 ( .D(n1601), .CK(clk), .RN(n2538), .Q(add_x_6_A_4_)
);
DFFRX4TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1620), .CK(clk), .RN(n2491), .Q(
DMP_EXP_EWSW[55]), .QN(n6340) );
DFFRX4TS add_x_6_R_871 ( .D(n1559), .CK(clk), .RN(n6742), .Q(add_x_6_A_18_)
);
DFFSX4TS R_1192 ( .D(n6894), .CK(clk), .SN(n6374), .Q(n6405) );
DFFRX4TS sub_x_5_R_757 ( .D(n1514), .CK(clk), .RN(n2515), .Q(sub_x_5_A_33_)
);
DFFRX4TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1292), .CK(clk), .RN(n6736), .Q(
DmP_EXP_EWSW[54]), .QN(sub_x_1_n32) );
DFFSX4TS R_1165 ( .D(n6894), .CK(clk), .SN(n2536), .Q(n6407) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1250), .CK(clk), .RN(n6730), .Q(
Raw_mant_NRM_SWR[19]), .QN(n6119) );
DFFSX2TS R_540 ( .D(n2151), .CK(clk), .SN(n6354), .Q(n6557) );
DFFSX2TS R_556 ( .D(n1735), .CK(clk), .SN(n2542), .Q(n6551) );
DFFRX2TS add_x_6_R_627 ( .D(n1511), .CK(clk), .RN(n2533), .Q(add_x_6_A_34_)
);
DFFRX4TS R_869 ( .D(n1138), .CK(clk), .RN(n5249), .Q(DmP_mant_SFG_SWR[18]),
.QN(n3352) );
DFFRX2TS add_x_6_R_1216 ( .D(n1143), .CK(clk), .RN(n6736), .Q(add_x_6_B_13_)
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1251), .CK(clk), .RN(n2496), .Q(
Raw_mant_NRM_SWR[18]), .QN(n6123) );
DFFRX4TS add_x_6_R_872 ( .D(n1138), .CK(clk), .RN(n6748), .Q(add_x_6_B_18_)
);
DFFSX4TS R_516 ( .D(n1748), .CK(clk), .SN(n6371), .Q(n6570) );
DFFRX2TS add_x_6_R_1215 ( .D(n1574), .CK(clk), .RN(n6739), .Q(add_x_6_A_13_)
);
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1116), .CK(clk), .RN(n2515), .Q(
DmP_mant_SFG_SWR[40]), .QN(n6296) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1245), .CK(clk), .RN(n2488), .Q(
Raw_mant_NRM_SWR[24]), .QN(n6132) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1693), .CK(clk), .RN(n6739),
.Q(shift_value_SHT2_EWR[5]), .QN(n6093) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1221), .CK(clk), .RN(n6733), .Q(
Raw_mant_NRM_SWR[48]), .QN(n6195) );
DFFRX4TS R_1137 ( .D(n1487), .CK(clk), .RN(n2520), .Q(DMP_SFG[40]), .QN(
n6324) );
DFFSX4TS R_838 ( .D(n6776), .CK(clk), .SN(n2487), .Q(n6469), .QN(n1961) );
DFFSX4TS R_1148 ( .D(n6894), .CK(clk), .SN(n6367), .Q(n6408) );
DFFRX2TS add_x_6_R_1231 ( .D(n1592), .CK(clk), .RN(n6738), .Q(add_x_6_A_7_)
);
DFFRX4TS add_x_6_R_1125 ( .D(n1583), .CK(clk), .RN(n2515), .Q(add_x_6_A_10_)
);
DFFRX4TS R_1199 ( .D(n1135), .CK(clk), .RN(n6727), .Q(DmP_mant_SFG_SWR[21]),
.QN(n3353) );
DFFRX2TS add_x_6_R_1210 ( .D(n1598), .CK(clk), .RN(n2538), .Q(add_x_6_A_5_)
);
DFFSX4TS R_824 ( .D(n6722), .CK(clk), .SN(n2545), .Q(n6483) );
DFFSX2TS R_600 ( .D(n1743), .CK(clk), .SN(n2524), .Q(n6531) );
DFFSX4TS R_836 ( .D(n6721), .CK(clk), .SN(n2545), .Q(n6471) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1256), .CK(clk), .RN(n6725), .Q(
Raw_mant_NRM_SWR[13]), .QN(n6112) );
DFFRX2TS R_561 ( .D(n6718), .CK(clk), .RN(n6376), .Q(n6548) );
DFFRX4TS R_825 ( .D(N92), .CK(clk), .RN(n6733), .Q(n6482) );
DFFRX2TS R_860 ( .D(n6794), .CK(clk), .RN(n6382), .Q(n6460) );
DFFRX4TS add_x_6_R_1237 ( .D(n1129), .CK(clk), .RN(n6743), .Q(add_x_6_B_27_)
);
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1619), .CK(clk), .RN(n6360), .Q(
DMP_EXP_EWSW[56]), .QN(n6339) );
DFFSX4TS R_833 ( .D(n6722), .CK(clk), .SN(n2509), .Q(n6474) );
DFFSX4TS R_835 ( .D(n6781), .CK(clk), .SN(n2544), .Q(n6472) );
DFFRX2TS add_x_6_R_705 ( .D(n1484), .CK(clk), .RN(n2520), .Q(add_x_6_A_43_)
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n6375), .Q(
Raw_mant_NRM_SWR[11]), .QN(n6090) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1449), .CK(clk), .RN(n6739), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRX2TS add_x_6_R_1201 ( .D(n1550), .CK(clk), .RN(n2531), .Q(add_x_6_A_21_)
);
DFFSX4TS R_1098 ( .D(n6722), .CK(clk), .SN(n2544), .Q(n6416) );
DFFRX4TS R_834 ( .D(N88), .CK(clk), .RN(n6733), .Q(n6473) );
DFFRX2TS R_533 ( .D(n6717), .CK(clk), .RN(n6369), .Q(n6560) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1265), .CK(clk), .RN(n2520), .Q(
Raw_mant_NRM_SWR[4]), .QN(n6246) );
DFFSX4TS add_x_6_R_1034 ( .D(n6033), .CK(clk), .SN(n2532), .Q(add_x_6_n417),
.QN(n6067) );
DFFRX4TS R_1233 ( .D(n1532), .CK(clk), .RN(n6742), .Q(DMP_SFG[25]), .QN(
n6330) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1214), .CK(clk), .RN(n6725),
.Q(LZD_output_NRM2_EW[2]), .QN(n2292) );
DFFRX4TS R_1146 ( .D(sub_x_5_B_17_), .CK(clk), .RN(n5249), .Q(
DmP_mant_SFG_SWR[17]) );
DFFSX4TS add_x_6_R_1209 ( .D(n6049), .CK(clk), .SN(n2539), .Q(add_x_6_n526),
.QN(n6058) );
DFFSX4TS add_x_6_R_1200 ( .D(n6046), .CK(clk), .SN(n2532), .Q(add_x_6_n401),
.QN(n6062) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1444), .CK(clk), .RN(n6736), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX4TS R_1099 ( .D(N87), .CK(clk), .RN(n6733), .Q(n6415) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1107), .CK(clk), .RN(n6729), .Q(
DmP_mant_SFG_SWR[49]), .QN(n6300) );
DFFSX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n2319), .CK(clk), .SN(n2525), .Q(
n6774), .QN(n3340) );
DFFSX4TS R_1258 ( .D(n2418), .CK(clk), .SN(n6370), .Q(n6390) );
DFFSX2TS R_1253 ( .D(n2383), .CK(clk), .SN(n6367), .Q(n6393) );
DFFSX2TS R_1238 ( .D(n2415), .CK(clk), .SN(n2529), .Q(n6399) );
DFFRX4TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1819), .CK(clk), .RN(n6752), .Q(
intAS) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1690), .CK(clk), .RN(n2508),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1689), .CK(clk), .RN(n2509),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRX4TS add_x_6_R_1185 ( .D(n6043), .CK(clk), .RN(n2526), .QN(n6059) );
DFFSX2TS R_903 ( .D(n2415), .CK(clk), .SN(n6749), .Q(n6443) );
DFFSX2TS R_927 ( .D(n2415), .CK(clk), .SN(n6384), .Q(n6441) );
DFFRX4TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1582), .CK(clk), .RN(n6770), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX4TS add_x_6_R_1243 ( .D(n1144), .CK(clk), .RN(n6770), .Q(add_x_6_B_12_)
);
DFFRX4TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1445), .CK(clk), .RN(n6770), .Q(
DMP_exp_NRM_EW[1]) );
DFFRHQX4TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1692), .CK(clk), .RN(n6769),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFSX4TS R_1100 ( .D(n6780), .CK(clk), .SN(n2488), .Q(n6414) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n6725),
.Q(LZD_output_NRM2_EW[4]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1254), .CK(clk), .RN(n2487), .Q(
Raw_mant_NRM_SWR[15]), .QN(n6092) );
DFFSX2TS R_436 ( .D(n1717), .CK(clk), .SN(n6363), .Q(n6607) );
DFFRHQX2TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1277), .CK(clk), .RN(n6726), .Q(
n2466) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1648), .CK(clk), .RN(n6746), .Q(
n2465) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1210), .CK(clk), .RN(n6769),
.QN(n6118) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1807), .CK(clk), .RN(n6758),
.Q(n2462) );
DFFRHQX2TS add_x_6_R_1211 ( .D(n1151), .CK(clk), .RN(n2539), .Q(n2461) );
DFFRX4TS R_868 ( .D(n1559), .CK(clk), .RN(n6741), .Q(DMP_SFG[16]), .QN(n6253) );
DFFRHQX2TS R_1167 ( .D(n1562), .CK(clk), .RN(n6741), .Q(n2444) );
DFFRX4TS R_828 ( .D(N91), .CK(clk), .RN(n6733), .Q(n6479) );
DFFRX4TS R_673 ( .D(n1502), .CK(clk), .RN(n2510), .Q(DMP_SFG[35]), .QN(n6252) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1260), .CK(clk), .RN(n2511), .Q(
Raw_mant_NRM_SWR[9]), .QN(n6130) );
DFFRX4TS R_1193 ( .D(n6898), .CK(clk), .RN(n6344), .Q(n6404) );
DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1817), .CK(clk), .RN(n2488),
.Q(n2438) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1261), .CK(clk), .RN(n2491), .Q(
Raw_mant_NRM_SWR[8]), .QN(n6206) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1809), .CK(clk), .RN(n6758),
.Q(n2431) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1805), .CK(clk), .RN(n6758),
.Q(n2427) );
DFFSX4TS R_394 ( .D(n6988), .CK(clk), .SN(n6348), .Q(n6617) );
DFFRX4TS add_x_6_R_1227 ( .D(n1152), .CK(clk), .RN(n2538), .Q(add_x_6_B_4_)
);
DFFRHQX2TS R_1155 ( .D(n2135), .CK(clk), .RN(n6726), .Q(n2425) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1134), .CK(clk), .RN(n6727),
.Q(n2421) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1374), .CK(clk), .RN(n6768), .Q(
n2410) );
DFFSX4TS add_x_6_R_1214 ( .D(n6050), .CK(clk), .SN(n6752), .Q(add_x_6_n470),
.QN(n6065) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1818), .CK(clk), .RN(n6749),
.Q(n2407) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1156), .CK(clk), .RN(n6377),
.Q(n2405) );
DFFSX4TS R_830 ( .D(n6722), .CK(clk), .SN(n6749), .QN(n2327) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1687), .CK(clk), .RN(n6736),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1755), .CK(clk), .RN(n6739),
.Q(intDY_EWSW[63]) );
DFFRX4TS R_1188 ( .D(n1150), .CK(clk), .RN(n6726), .Q(DmP_mant_SFG_SWR[6]),
.QN(n6332) );
DFFRX4TS R_1122 ( .D(n1583), .CK(clk), .RN(n2492), .Q(DMP_SFG[8]), .QN(n6257) );
DFFSX1TS R_107 ( .D(exp_rslt_NRM2_EW1[9]), .CK(clk), .SN(n6366), .Q(n6669)
);
DFFRHQX2TS add_x_6_R_1232 ( .D(n1149), .CK(clk), .RN(n6738), .Q(n2282) );
DFFSX2TS R_484 ( .D(n1744), .CK(clk), .SN(n6370), .Q(n6588) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1453), .CK(clk), .RN(n6736), .QN(
n6192) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1448), .CK(clk), .RN(n6753), .QN(
n6191) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1443), .CK(clk), .RN(n6753), .QN(
n6190) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1438), .CK(clk), .RN(n2487), .QN(
n6189) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1433), .CK(clk), .RN(n6723), .QN(
n6188) );
DFFRX1TS R_396 ( .D(final_result_ieee[48]), .CK(clk), .RN(n6357), .Q(n6616)
);
DFFRXLTS R_408 ( .D(final_result_ieee[3]), .CK(clk), .RN(n6728), .Q(n6610)
);
DFFSX2TS R_502 ( .D(n2471), .CK(clk), .SN(n2526), .Q(n6577) );
DFFSX2TS R_1060 ( .D(n2418), .CK(clk), .SN(n6732), .Q(n6421) );
DFFSX2TS R_448 ( .D(n1745), .CK(clk), .SN(n6369), .Q(n6602) );
DFFRX4TS R_1262 ( .D(n3153), .CK(clk), .RN(n6353), .Q(n2272) );
DFFSX2TS R_1264 ( .D(n4414), .CK(clk), .SN(n1924), .Q(n2271) );
DFFRX2TS R_1265 ( .D(n1966), .CK(clk), .RN(n1924), .Q(n2270) );
DFFRX4TS R_1268 ( .D(n1969), .CK(clk), .RN(n6731), .Q(n2268) );
DFFSX2TS R_588 ( .D(n1739), .CK(clk), .SN(n2541), .Q(n6537) );
DFFSX1TS R_520 ( .D(n1714), .CK(clk), .SN(n2534), .Q(n6567) );
DFFSX4TS R_1252 ( .D(n2470), .CK(clk), .SN(n2546), .Q(n6394), .QN(n2267) );
DFFSX4TS R_604 ( .D(n1722), .CK(clk), .SN(n6769), .Q(n6530) );
DFFSX1TS R_488 ( .D(n1706), .CK(clk), .SN(n6378), .Q(n6585) );
DFFRX4TS R_517 ( .D(n6717), .CK(clk), .RN(n6368), .Q(n6569) );
DFFSX4TS R_576 ( .D(n1728), .CK(clk), .SN(n6768), .Q(n6542) );
DFFRX2TS R_497 ( .D(n6717), .CK(clk), .RN(n6369), .Q(n6581) );
DFFRX1TS R_465 ( .D(n6718), .CK(clk), .RN(n6743), .Q(n6596) );
DFFRX1TS R_529 ( .D(n6718), .CK(clk), .RN(n6376), .Q(n6563) );
DFFRX1TS R_501 ( .D(n6718), .CK(clk), .RN(n6748), .Q(n6578) );
DFFRX2TS R_948 ( .D(n6785), .CK(clk), .RN(n6383), .Q(n6439) );
DFFSX1TS R_452 ( .D(n1723), .CK(clk), .SN(n2520), .Q(n6600) );
DFFRX2TS R_899 ( .D(n6783), .CK(clk), .RN(n2535), .Q(n6444) );
DFFRX1TS R_876 ( .D(n6834), .CK(clk), .RN(n6368), .Q(n6456) );
DFFSX1TS R_444 ( .D(n1729), .CK(clk), .SN(n6362), .Q(n6604) );
DFFSX4TS R_827 ( .D(n6722), .CK(clk), .SN(n2546), .Q(n6480) );
DFFSX4TS R_826 ( .D(n6779), .CK(clk), .SN(n5249), .Q(n6481) );
DFFRX4TS R_1283 ( .D(n1969), .CK(clk), .RN(n5250), .Q(n2258) );
DFFSX2TS R_1285 ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .SN(n6356), .Q(n2251)
);
DFFSX2TS R_1289 ( .D(n6865), .CK(clk), .SN(n6365), .Q(n2246) );
DFFSX2TS R_1290 ( .D(n6886), .CK(clk), .SN(n2509), .Q(n2245) );
DFFSX2TS R_1291 ( .D(n6896), .CK(clk), .SN(n6365), .Q(n2244), .QN(n2243) );
DFFSX2TS R_1292 ( .D(n6866), .CK(clk), .SN(n2536), .Q(n2242) );
DFFSX2TS R_1293 ( .D(n6881), .CK(clk), .SN(n6756), .Q(n2241) );
DFFSX2TS R_1294 ( .D(n6876), .CK(clk), .SN(n2545), .Q(n2240) );
DFFSX2TS R_1295 ( .D(n6875), .CK(clk), .SN(n6366), .Q(n2239) );
DFFSX2TS R_1297 ( .D(n6887), .CK(clk), .SN(n2511), .Q(n2237) );
DFFSX2TS R_1298 ( .D(n6892), .CK(clk), .SN(n6732), .Q(n2236) );
DFFSX2TS R_1299 ( .D(n6836), .CK(clk), .SN(n6374), .Q(n2235) );
DFFSX2TS R_1300 ( .D(n6880), .CK(clk), .SN(n6732), .Q(n2234), .QN(n2233) );
DFFSX2TS R_1301 ( .D(n6891), .CK(clk), .SN(n6732), .Q(n2232) );
DFFSX2TS R_1305 ( .D(n6870), .CK(clk), .SN(n6366), .Q(n2227), .QN(n2226) );
DFFSX2TS R_1307 ( .D(n6860), .CK(clk), .SN(n6380), .Q(n2224) );
DFFSX2TS R_1308 ( .D(n6867), .CK(clk), .SN(n2536), .Q(n2223) );
DFFSX2TS R_1309 ( .D(n6842), .CK(clk), .SN(n6385), .Q(n2222), .QN(n2221) );
DFFSX2TS R_1310 ( .D(n6872), .CK(clk), .SN(n6730), .Q(n2220) );
DFFSX2TS R_1311 ( .D(n6861), .CK(clk), .SN(n2510), .Q(n2219) );
DFFSX2TS R_1312 ( .D(n6885), .CK(clk), .SN(n6365), .Q(n2218) );
DFFSX2TS R_1313 ( .D(n6855), .CK(clk), .SN(n6386), .Q(n2217), .QN(n2216) );
DFFSX2TS R_1315 ( .D(n6869), .CK(clk), .SN(n6385), .Q(n2214) );
DFFSX2TS R_1316 ( .D(n6877), .CK(clk), .SN(n5250), .Q(n2213) );
DFFSX2TS R_1318 ( .D(n6871), .CK(clk), .SN(n2545), .Q(n2211), .QN(n2210) );
DFFSX2TS R_1319 ( .D(n6882), .CK(clk), .SN(n5252), .Q(n2209) );
DFFSX2TS R_1322 ( .D(n6833), .CK(clk), .SN(n6385), .Q(n2202) );
DFFSX2TS R_1323 ( .D(n6890), .CK(clk), .SN(n6367), .Q(n2201) );
DFFSX2TS R_1324 ( .D(n6862), .CK(clk), .SN(n6766), .Q(n2200) );
DFFSX2TS R_1326 ( .D(n6879), .CK(clk), .SN(n6380), .Q(n2198) );
DFFSX2TS R_1327 ( .D(n6895), .CK(clk), .SN(n6380), .Q(n2197) );
DFFSX2TS R_1329 ( .D(n6889), .CK(clk), .SN(n6380), .Q(n2195) );
DFFSX2TS R_1330 ( .D(n6884), .CK(clk), .SN(n6380), .Q(n2194) );
DFFSX2TS R_1331 ( .D(n6864), .CK(clk), .SN(n6381), .Q(n2193) );
DFFSX4TS R_1248 ( .D(n2470), .CK(clk), .SN(n2529), .Q(n6398) );
DFFSX2TS R_1334 ( .D(n6846), .CK(clk), .SN(n6374), .Q(n2191) );
DFFSX2TS R_1338 ( .D(n6773), .CK(clk), .SN(n6346), .Q(n2187) );
DFFSX2TS R_1339 ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .SN(n6360), .Q(n2186)
);
DFFSX2TS R_1341 ( .D(n6799), .CK(clk), .SN(n2546), .Q(n2184) );
DFFRX2TS R_1342 ( .D(n6945), .CK(clk), .RN(n5247), .Q(n2183) );
DFFRX2TS R_1343 ( .D(n6979), .CK(clk), .RN(n6347), .Q(n2182) );
DFFSX2TS R_1344 ( .D(n6821), .CK(clk), .SN(n6748), .Q(n2181) );
DFFSX2TS R_1345 ( .D(n6773), .CK(clk), .SN(n6344), .Q(n2180) );
DFFSX2TS R_1346 ( .D(n6816), .CK(clk), .SN(n2508), .Q(n2179) );
DFFRX2TS R_1347 ( .D(n6981), .CK(clk), .RN(n6358), .Q(n2178) );
DFFRX2TS R_1348 ( .D(n6992), .CK(clk), .RN(n6344), .Q(n2177) );
DFFRX2TS R_1349 ( .D(n6982), .CK(clk), .RN(n6358), .Q(n2176) );
DFFRX2TS R_1350 ( .D(n6978), .CK(clk), .RN(n6358), .Q(n2175) );
DFFRX2TS R_1351 ( .D(n6946), .CK(clk), .RN(n6351), .Q(n2174) );
DFFRX2TS R_1352 ( .D(n6990), .CK(clk), .RN(n6357), .Q(n2173) );
DFFRX2TS R_1353 ( .D(n6943), .CK(clk), .RN(n6351), .Q(n2172) );
DFFRX2TS R_1354 ( .D(n6937), .CK(clk), .RN(n5247), .Q(n2171) );
DFFRX2TS R_1355 ( .D(n6936), .CK(clk), .RN(n6351), .Q(n2170) );
DFFRX2TS R_1356 ( .D(n6975), .CK(clk), .RN(n6358), .Q(n2169) );
DFFRX2TS R_1357 ( .D(n6976), .CK(clk), .RN(n6347), .Q(n2168) );
DFFRX2TS R_1358 ( .D(n6973), .CK(clk), .RN(n6348), .Q(n2167) );
DFFRX2TS R_1359 ( .D(n6939), .CK(clk), .RN(n5247), .Q(n2166) );
DFFRX2TS R_1361 ( .D(n6972), .CK(clk), .RN(n6728), .Q(n2164) );
DFFRX2TS R_1362 ( .D(n6942), .CK(clk), .RN(n6351), .Q(n2163) );
DFFRX2TS R_1363 ( .D(n6952), .CK(clk), .RN(n6350), .Q(n2162) );
DFFRX2TS R_1364 ( .D(n6953), .CK(clk), .RN(n6350), .Q(n2161) );
DFFRX2TS R_1365 ( .D(n6989), .CK(clk), .RN(n6766), .Q(n2160) );
DFFRX2TS R_1366 ( .D(n6970), .CK(clk), .RN(n6348), .Q(n2159) );
DFFRX4TS R_1367 ( .D(n6858), .CK(clk), .RN(n6362), .Q(n2158) );
DFFRX2TS R_1368 ( .D(n2329), .CK(clk), .RN(n6344), .Q(n2157) );
DFFRX2TS R_1369 ( .D(n6969), .CK(clk), .RN(n6357), .Q(n2156) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1665), .CK(clk), .RN(n6752), .Q(
n2144) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1666), .CK(clk), .RN(n6737), .Q(
n2143) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1671), .CK(clk), .RN(n6738), .Q(
n2142) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1634), .CK(clk), .RN(n2522), .Q(
n2141) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1773), .CK(clk), .RN(n6761),
.Q(n2139) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1777), .CK(clk), .RN(n6761),
.Q(n2137) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1394), .CK(clk), .RN(n2544), .Q(
DmP_EXP_EWSW[2]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1356), .CK(clk), .RN(n2535), .Q(
DmP_EXP_EWSW[21]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1360), .CK(clk), .RN(n2536), .Q(
DmP_EXP_EWSW[19]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1342), .CK(clk), .RN(n6734), .Q(
DmP_EXP_EWSW[28]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1378), .CK(clk), .RN(n2545), .Q(
DmP_EXP_EWSW[10]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1354), .CK(clk), .RN(n2535), .Q(
DmP_EXP_EWSW[22]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1396), .CK(clk), .RN(n2545), .Q(
DmP_EXP_EWSW[1]) );
DFFRX4TS R_1207 ( .D(n1598), .CK(clk), .RN(n2538), .Q(DMP_SFG[3]), .QN(n6317) );
DFFRHQX2TS R_1009 ( .D(n1137), .CK(clk), .RN(n5248), .Q(n2131) );
DFFRX4TS R_1286 ( .D(n6716), .CK(clk), .RN(n6361), .Q(n2250) );
DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1784), .CK(clk), .RN(n6760),
.Q(n2130) );
DFFSX4TS R_1260 ( .D(n2415), .CK(clk), .SN(n6367), .Q(n6388) );
DFFSX4TS R_1317 ( .D(n6835), .CK(clk), .SN(n6385), .Q(n2212) );
DFFSX4TS R_1250 ( .D(n2383), .CK(clk), .SN(n6374), .Q(n6396), .QN(n2203) );
DFFSX4TS R_1284 ( .D(n2470), .CK(clk), .SN(n6372), .Q(n2257) );
DFFSX4TS R_1304 ( .D(n6847), .CK(clk), .SN(n6385), .Q(n2228) );
DFFSX4TS R_1288 ( .D(n6857), .CK(clk), .SN(n6364), .Q(n2247) );
DFFRX4TS R_831 ( .D(N90), .CK(clk), .RN(n6733), .QN(n1960) );
DFFSX4TS R_1321 ( .D(n6840), .CK(clk), .SN(n6385), .Q(n2207) );
DFFSX4TS R_1314 ( .D(n6841), .CK(clk), .SN(n6373), .Q(n2215) );
DFFSX4TS R_1340 ( .D(n6831), .CK(clk), .SN(n6374), .Q(n2185) );
DFFSX4TS R_1333 ( .D(n6853), .CK(clk), .SN(n6373), .Q(n2192) );
DFFSX4TS R_1325 ( .D(n6850), .CK(clk), .SN(n6386), .Q(n2199) );
DFFSX4TS R_1280 ( .D(n2419), .CK(clk), .SN(n6374), .Q(n2261) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1244), .CK(clk), .RN(n6741), .Q(
Raw_mant_NRM_SWR[25]), .QN(n6089) );
DFFRX2TS R_577 ( .D(n6718), .CK(clk), .RN(n6742), .Q(n6541) );
DFFRX4TS add_x_6_R_1236 ( .D(n1532), .CK(clk), .RN(n6742), .Q(add_x_6_A_27_)
);
DFFSX4TS R_1259 ( .D(n2470), .CK(clk), .SN(n6378), .Q(n6389) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1238), .CK(clk), .RN(n2521),
.Q(n2432) );
DFFSX4TS R_1320 ( .D(n6837), .CK(clk), .SN(n6384), .Q(n2208) );
DFFSX2TS R_572 ( .D(n1738), .CK(clk), .SN(n6356), .Q(n6543) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(n2516), .Q(
DMP_SHT2_EWSW[7]), .QN(n6096) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1542), .CK(clk), .RN(n6744), .Q(
DMP_SHT2_EWSW[22]), .QN(n6171) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1524), .CK(clk), .RN(n6746), .Q(
DMP_SHT2_EWSW[28]), .QN(n6165) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1506), .CK(clk), .RN(n2534), .Q(
DMP_SHT2_EWSW[34]), .QN(n6159) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1377), .CK(clk), .RN(n2546),
.Q(DmP_mant_SHT1_SW[10]), .QN(n6223) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1361), .CK(clk), .RN(n2521),
.Q(DmP_mant_SHT1_SW[18]), .QN(n6211) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1341), .CK(clk), .RN(n6734),
.Q(DmP_mant_SHT1_SW[28]), .QN(n6214) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1285), .CK(clk), .RN(n6723), .Q(
ZERO_FLAG_SHT2), .QN(n6186) );
DFFRXLTS R_803 ( .D(n6813), .CK(clk), .RN(n2544), .Q(n6492) );
DFFRXLTS R_878 ( .D(n6806), .CK(clk), .RN(n2504), .Q(n6455) );
DFFRX1TS R_609 ( .D(n6718), .CK(clk), .RN(n6378), .Q(n6527) );
DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1791), .CK(clk), .RN(n6759),
.Q(n2437) );
DFFSX1TS R_504 ( .D(n1710), .CK(clk), .SN(n6769), .Q(n6576) );
DFFRX1TS R_1360 ( .D(n6940), .CK(clk), .RN(n6351), .Q(n2165) );
DFFRX4TS R_1337 ( .D(n3249), .CK(clk), .RN(n6353), .Q(n2188) );
DFFSX4TS R_829 ( .D(n6778), .CK(clk), .SN(n6732), .Q(n6478) );
DFFSX4TS R_1251 ( .D(n2484), .CK(clk), .SN(n6386), .Q(n6395), .QN(n2206) );
DFFSX4TS R_1303 ( .D(n6848), .CK(clk), .SN(n6374), .Q(n2229) );
DFFSX4TS R_1328 ( .D(n6845), .CK(clk), .SN(n6385), .Q(n2196) );
DFFSX4TS R_1336 ( .D(n6852), .CK(clk), .SN(n6384), .Q(n2189) );
DFFRX4TS R_726 ( .D(n6830), .CK(clk), .RN(n6369), .Q(n6516) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1290), .CK(clk), .RN(n6770), .Q(
DmP_EXP_EWSW[56]), .QN(n6263) );
DFFSX2TS R_584 ( .D(n1746), .CK(clk), .SN(n6356), .Q(n6539) );
DFFRX4TS R_597 ( .D(n6717), .CK(clk), .RN(n6369), .Q(n6533) );
DFFRX4TS R_585 ( .D(n6719), .CK(clk), .RN(n6382), .Q(n6538) );
DFFSX4TS R_1306 ( .D(n6856), .CK(clk), .SN(n6365), .Q(n2225) );
DFFSX2TS R_568 ( .D(n1742), .CK(clk), .SN(n5251), .Q(n6545) );
DFFSX4TS R_1296 ( .D(n6843), .CK(clk), .SN(n6373), .Q(n2238) );
DFFSX4TS R_1335 ( .D(n6838), .CK(clk), .SN(n6373), .Q(n2190) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1241), .CK(clk), .RN(n6767),
.Q(n2286) );
DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1233), .CK(clk), .RN(n6733),
.Q(n2429) );
DFFSX4TS R_1249 ( .D(n2485), .CK(clk), .SN(n6381), .Q(n6397) );
DFFRX2TS R_864 ( .D(n6811), .CK(clk), .RN(n6377), .Q(n6458) );
DFFRX2TS add_x_6_R_1190 ( .D(n1595), .CK(clk), .RN(n2538), .Q(add_x_6_A_6_)
);
DFFSX1TS R_912 ( .D(n2415), .CK(clk), .SN(n6384), .Q(n6442) );
DFFSX2TS R_536 ( .D(n1730), .CK(clk), .SN(n6383), .Q(n6558) );
DFFSX2TS R_1302 ( .D(n6851), .CK(clk), .SN(n6373), .Q(n2231), .QN(n2230) );
DFFRHQX4TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1535), .CK(clk), .RN(n6744), .Q(
n2436) );
DFFSX1TS R_1170 ( .D(n2485), .CK(clk), .SN(n2536), .Q(n6406) );
DFFRX2TS R_481 ( .D(n6717), .CK(clk), .RN(n6368), .Q(n6590) );
DFFRX1TS R_858 ( .D(n6829), .CK(clk), .RN(n6368), .Q(n6461) );
DFFRX2TS R_485 ( .D(n6719), .CK(clk), .RN(n6368), .Q(n6587) );
DFFRX2TS R_469 ( .D(n6718), .CK(clk), .RN(n6368), .QN(n2254) );
DFFSX2TS add_x_6_R_1225 ( .D(n6052), .CK(clk), .SN(n2539), .Q(add_x_6_n529),
.QN(n6066) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1429), .CK(clk), .RN(n2509), .Q(
DMP_exp_NRM2_EW[4]), .QN(n1953) );
DFFSX2TS add_x_6_R_1230 ( .D(n6053), .CK(clk), .SN(n6728), .Q(add_x_6_n515),
.QN(n6061) );
DFFRX2TS add_x_6_R_1126 ( .D(n1146), .CK(clk), .RN(n2491), .Q(add_x_6_B_10_)
);
DFFRX1TS R_810 ( .D(n6868), .CK(clk), .RN(n6362), .Q(n6490) );
DFFRX2TS sub_x_5_R_1169 ( .D(n1562), .CK(clk), .RN(n5249), .Q(sub_x_5_A_17_)
);
DFFSX1TS R_530 ( .D(n2470), .CK(clk), .SN(n2526), .Q(n6562) );
DFFRX2TS R_581 ( .D(n6717), .CK(clk), .RN(n6361), .Q(n2256) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1424), .CK(clk), .RN(n6754), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1409), .CK(clk), .RN(n2525),
.Q(DMP_exp_NRM2_EW[8]) );
DFFSX1TS R_1127 ( .D(n2484), .CK(clk), .SN(n2529), .Q(n6410) );
DFFSX1TS R_1040 ( .D(n2484), .CK(clk), .SN(n2488), .Q(n6425) );
DFFRX2TS R_702 ( .D(n1484), .CK(clk), .RN(n2520), .Q(DMP_SFG[41]), .QN(n6328) );
DFFSX1TS R_1050 ( .D(n2485), .CK(clk), .SN(n2542), .Q(n6423) );
DFFSX2TS add_x_6_R_1205 ( .D(n6029), .CK(clk), .SN(n2499), .Q(add_x_6_n243),
.QN(n6071) );
DFFRX2TS R_1217 ( .D(n1478), .CK(clk), .RN(n2503), .Q(DMP_SFG[43]), .QN(
n6323) );
DFFRX2TS add_x_6_R_1141 ( .D(n1114), .CK(clk), .RN(n2521), .Q(add_x_6_B_42_)
);
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1104), .CK(clk), .RN(n6368), .Q(
DmP_mant_SFG_SWR[52]), .QN(n2320) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1106), .CK(clk), .RN(n6729), .Q(
DmP_mant_SFG_SWR[50]), .QN(n6298) );
DFFSX1TS R_937 ( .D(n2383), .CK(clk), .SN(n6379), .Q(n6440) );
DFFSX1TS R_472 ( .D(n1702), .CK(clk), .SN(n6769), .Q(n6594) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1278), .CK(clk), .RN(n6770), .Q(
OP_FLAG_SFG), .QN(n6094) );
DFFSX1TS add_x_6_R_1143 ( .D(n6027), .CK(clk), .SN(n6771), .Q(add_x_6_n265),
.QN(n6073) );
DFFSX1TS add_x_6_R_1183 ( .D(n6042), .CK(clk), .SN(n6769), .QN(n6068) );
DFFSX1TS add_x_6_R_1247 ( .D(n6057), .CK(clk), .SN(n6353), .Q(add_x_6_n489)
);
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1820), .CK(clk), .RN(n6737),
.Q(intDX_EWSW[63]), .QN(n6259) );
DFFSX4TS R_1274 ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .SN(n5244), .QN(n1896)
);
DFFSX4TS R_1269 ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .SN(n6356), .QN(n1895)
);
DFFSX4TS R_1266 ( .D(n6714), .CK(clk), .SN(n1924), .QN(ready) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1688), .CK(clk), .RN(n6737),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRX2TS R_823 ( .D(n6995), .CK(clk), .RN(n6344), .Q(n6484) );
DFFSX4TS R_1287 ( .D(n7009), .CK(clk), .SN(n6354), .Q(n2249), .QN(n2248) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1324), .CK(clk), .RN(n2542), .Q(
n2413) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1632), .CK(clk), .RN(n2503), .Q(
n2146) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1334), .CK(clk), .RN(n6347), .Q(
n2412) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1392), .CK(clk), .RN(n6731), .Q(
n2411) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1664), .CK(clk), .RN(n2525), .Q(
n2145) );
DFFSX1TS R_13 ( .D(n6971), .CK(clk), .SN(n6353), .Q(n6707) );
DFFSX1TS R_30 ( .D(n6933), .CK(clk), .SN(n6353), .Q(n6700) );
DFFSX1TS R_265 ( .D(n2481), .CK(clk), .SN(n6346), .Q(n6648) );
MX2X2TS U1897 ( .A(Data_Y[14]), .B(intDY_EWSW[14]), .S0(n5893), .Y(n1804) );
CLKMX2X2TS U1898 ( .A(Data_Y[3]), .B(n2565), .S0(n5892), .Y(n1815) );
INVX12TS U1899 ( .A(n2469), .Y(n2471) );
MXI2X1TS U1900 ( .A(n6096), .B(n6270), .S0(n2489), .Y(n1586) );
NAND2X2TS U1901 ( .A(n2627), .B(Shift_reg_FLAGS_7[0]), .Y(n3249) );
INVX2TS U1902 ( .A(n6791), .Y(n6845) );
BUFX3TS U1903 ( .A(n1154), .Y(n2135) );
INVX4TS U1904 ( .A(n3405), .Y(n6016) );
MXI2X1TS U1905 ( .A(n6247), .B(n6094), .S0(n2514), .Y(n1278) );
CLKMX2X3TS U1906 ( .A(Data_Y[51]), .B(n1914), .S0(n5895), .Y(n1767) );
CLKMX2X3TS U1907 ( .A(Data_Y[36]), .B(intDY_EWSW[36]), .S0(n5899), .Y(n1782)
);
CLKMX2X3TS U1908 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n5897), .Y(n1788)
);
CLKMX2X3TS U1909 ( .A(Data_Y[15]), .B(intDY_EWSW[15]), .S0(n5893), .Y(n1803)
);
CLKMX2X3TS U1910 ( .A(Data_Y[25]), .B(intDY_EWSW[25]), .S0(n5906), .Y(n1793)
);
OAI22X2TS U1911 ( .A0(n2400), .A1(n5911), .B0(Shift_reg_FLAGS_7_6), .B1(
n6261), .Y(n1611) );
NAND3X2TS U1912 ( .A(n4229), .B(n4228), .C(n4227), .Y(n1394) );
NAND3X2TS U1913 ( .A(n4111), .B(n4110), .C(n4109), .Y(n1308) );
CLKINVX1TS U1914 ( .A(n1923), .Y(n1924) );
NAND3X2TS U1915 ( .A(n3756), .B(n3755), .C(n3754), .Y(n1660) );
NAND3X4TS U1916 ( .A(n3773), .B(n3774), .C(n3772), .Y(n1665) );
NAND3X4TS U1917 ( .A(n4263), .B(n4262), .C(n4261), .Y(n1362) );
NAND3X4TS U1918 ( .A(n4104), .B(n4105), .C(n4103), .Y(n1312) );
NAND3X4TS U1919 ( .A(n3709), .B(n3710), .C(n3708), .Y(n1649) );
NAND3X2TS U1920 ( .A(n3823), .B(n3824), .C(n3822), .Y(n1638) );
INVX2TS U1921 ( .A(n6865), .Y(n6812) );
INVX2TS U1922 ( .A(n6860), .Y(n6783) );
NAND2X1TS U1923 ( .A(n2994), .B(intDX_EWSW[45]), .Y(n4111) );
NAND2X1TS U1924 ( .A(n3775), .B(n2137), .Y(n3793) );
NAND2X1TS U1925 ( .A(n2514), .B(DmP_mant_SFG_SWR[15]), .Y(n2014) );
NAND2X2TS U1926 ( .A(n5349), .B(intDX_EWSW[26]), .Y(n3709) );
NAND2X1TS U1927 ( .A(n2994), .B(intDY_EWSW[35]), .Y(n3827) );
NAND2X2TS U1928 ( .A(n2993), .B(intDY_EWSW[15]), .Y(n3756) );
NAND2X1TS U1929 ( .A(n2507), .B(DmP_mant_SFG_SWR[16]), .Y(n2972) );
NAND2X2TS U1930 ( .A(n2550), .B(intDX_EWSW[31]), .Y(n4282) );
NAND2X1TS U1931 ( .A(n6973), .B(n2557), .Y(n5559) );
NAND2X1TS U1932 ( .A(n5878), .B(DmP_EXP_EWSW[44]), .Y(n4115) );
NAND2XLTS U1933 ( .A(n5878), .B(DmP_EXP_EWSW[43]), .Y(n4103) );
NAND2XLTS U1934 ( .A(n5878), .B(DmP_EXP_EWSW[48]), .Y(n4122) );
NAND2X1TS U1935 ( .A(n2414), .B(DmP_mant_SFG_SWR[48]), .Y(n2128) );
NAND2X2TS U1936 ( .A(n2848), .B(intDX_EWSW[15]), .Y(n3755) );
NAND2X1TS U1937 ( .A(n2414), .B(DmP_mant_SFG_SWR[49]), .Y(n3041) );
BUFX3TS U1938 ( .A(n5280), .Y(n5928) );
NAND2X1TS U1939 ( .A(n2414), .B(DmP_mant_SFG_SWR[41]), .Y(n2744) );
OAI22X1TS U1940 ( .A0(n2249), .A1(n6628), .B0(n1935), .B1(n6627), .Y(
final_result_ieee[46]) );
OAI22X1TS U1941 ( .A0(n2249), .A1(n6626), .B0(n1935), .B1(n6625), .Y(
final_result_ieee[39]) );
OAI22X1TS U1942 ( .A0(n2249), .A1(n6619), .B0(n1935), .B1(n6618), .Y(
final_result_ieee[11]) );
INVX2TS U1943 ( .A(n2106), .Y(n2108) );
NAND2X4TS U1944 ( .A(n3017), .B(n4966), .Y(n3016) );
NAND2X1TS U1945 ( .A(n2994), .B(intDY_EWSW[32]), .Y(n3781) );
NAND2X2TS U1946 ( .A(n6981), .B(n2766), .Y(n2767) );
NAND2X1TS U1947 ( .A(n5730), .B(DmP_mant_SFG_SWR[29]), .Y(n5501) );
NOR2X6TS U1948 ( .A(n2851), .B(n1505), .Y(n6028) );
NOR2X2TS U1949 ( .A(n5332), .B(n5880), .Y(n6835) );
NAND2X2TS U1950 ( .A(n1920), .B(intDX_EWSW[43]), .Y(n3817) );
NAND2X2TS U1951 ( .A(n5349), .B(intDX_EWSW[55]), .Y(n3649) );
INVX2TS U1952 ( .A(n2071), .Y(n1922) );
NAND2X1TS U1953 ( .A(n2414), .B(DmP_mant_SFG_SWR[32]), .Y(n2983) );
NAND2XLTS U1954 ( .A(n5462), .B(LZD_output_NRM2_EW[5]), .Y(n2656) );
NAND2XLTS U1955 ( .A(n5878), .B(DmP_EXP_EWSW[47]), .Y(n4100) );
NAND2XLTS U1956 ( .A(n5878), .B(DmP_EXP_EWSW[50]), .Y(n4118) );
NAND2XLTS U1957 ( .A(n5878), .B(DmP_EXP_EWSW[49]), .Y(n4106) );
NAND2X6TS U1958 ( .A(n4967), .B(n4966), .Y(n2844) );
NAND2X2TS U1959 ( .A(n3809), .B(intDY_EWSW[56]), .Y(n3673) );
INVX12TS U1960 ( .A(n3179), .Y(n1967) );
NAND4X4TS U1961 ( .A(n5549), .B(n5548), .C(n5547), .D(n5546), .Y(n6978) );
BUFX4TS U1962 ( .A(n2304), .Y(n2092) );
OR2X1TS U1963 ( .A(n2459), .B(n6129), .Y(n2000) );
NAND2X2TS U1964 ( .A(n2821), .B(intDY_EWSW[29]), .Y(n3701) );
INVX3TS U1965 ( .A(Shift_reg_FLAGS_7[0]), .Y(n5273) );
OR2X2TS U1966 ( .A(n2721), .B(n2720), .Y(n2070) );
NAND2X2TS U1967 ( .A(n4121), .B(n2565), .Y(n4209) );
NAND2X2TS U1968 ( .A(n6942), .B(n2558), .Y(n5511) );
NAND2X6TS U1969 ( .A(n1154), .B(n1607), .Y(n6040) );
NAND2X2TS U1970 ( .A(n3828), .B(intDX_EWSW[10]), .Y(n3773) );
NAND2X4TS U1971 ( .A(n1146), .B(n1583), .Y(n6036) );
NAND2X2TS U1972 ( .A(n1920), .B(intDX_EWSW[53]), .Y(n3661) );
NAND2BX1TS U1973 ( .AN(n5856), .B(LZD_output_NRM2_EW[1]), .Y(n4514) );
NAND2X2TS U1974 ( .A(n3845), .B(n2011), .Y(n3719) );
AOI22X1TS U1975 ( .A0(n5483), .A1(n5626), .B0(Raw_mant_NRM_SWR[10]), .B1(
n5991), .Y(n5484) );
NAND2X4TS U1976 ( .A(n2565), .B(n4245), .Y(n3731) );
NAND2X2TS U1977 ( .A(n2820), .B(intDX_EWSW[14]), .Y(n3764) );
NAND2X4TS U1978 ( .A(n3404), .B(n3403), .Y(n3405) );
XOR2X2TS U1979 ( .A(n4735), .B(n4734), .Y(n4737) );
XNOR2X2TS U1980 ( .A(n2442), .B(n4837), .Y(n4854) );
XOR2X2TS U1981 ( .A(n4859), .B(n4858), .Y(n4868) );
XOR2X2TS U1982 ( .A(n4776), .B(n4775), .Y(n4783) );
XNOR2X2TS U1983 ( .A(n5479), .B(n5478), .Y(n5485) );
XNOR2X1TS U1984 ( .A(n5519), .B(n5518), .Y(n5530) );
XNOR2X1TS U1985 ( .A(n4534), .B(n4533), .Y(n4539) );
NAND2X1TS U1986 ( .A(n2271), .B(n2270), .Y(n7011) );
BUFX16TS U1987 ( .A(n2822), .Y(n4307) );
BUFX6TS U1988 ( .A(n2649), .Y(n2819) );
NAND2X1TS U1989 ( .A(n5817), .B(Raw_mant_NRM_SWR[38]), .Y(n5293) );
AND2X2TS U1990 ( .A(n5814), .B(Raw_mant_NRM_SWR[9]), .Y(n5816) );
NOR2X1TS U1991 ( .A(n5792), .B(n6477), .Y(n5793) );
BUFX16TS U1992 ( .A(n2822), .Y(n5349) );
AND2X2TS U1993 ( .A(n5814), .B(Raw_mant_NRM_SWR[11]), .Y(n5811) );
OR2X1TS U1994 ( .A(n5792), .B(n6242), .Y(n5294) );
INVX12TS U1995 ( .A(ready), .Y(n1929) );
INVX12TS U1996 ( .A(n1896), .Y(n1935) );
NAND2X1TS U1997 ( .A(n5848), .B(n2164), .Y(n5843) );
NAND2X1TS U1998 ( .A(n5945), .B(n6006), .Y(n5946) );
NOR2X1TS U1999 ( .A(n6015), .B(n5786), .Y(n5782) );
NAND2X1TS U2000 ( .A(n5764), .B(n6496), .Y(n5772) );
AOI21X2TS U2001 ( .A0(n2549), .A1(n5617), .B0(n6087), .Y(n5622) );
NAND2X1TS U2002 ( .A(n1984), .B(n5789), .Y(n3350) );
NAND2X1TS U2003 ( .A(n4162), .B(n4794), .Y(n5240) );
NAND2X1TS U2004 ( .A(n2453), .B(n2497), .Y(n5568) );
AND2X2TS U2005 ( .A(n5817), .B(Raw_mant_NRM_SWR[5]), .Y(n5788) );
NAND2X1TS U2006 ( .A(n4673), .B(n5579), .Y(n5589) );
NAND2X1TS U2007 ( .A(n5232), .B(n5231), .Y(n5583) );
NAND2X1TS U2008 ( .A(n4803), .B(n4872), .Y(n5611) );
NAND2X1TS U2009 ( .A(n4807), .B(n4871), .Y(n5221) );
BUFX3TS U2010 ( .A(n4966), .Y(n5527) );
NAND2X1TS U2011 ( .A(n5789), .B(Raw_mant_NRM_SWR[46]), .Y(n5314) );
NAND2X1TS U2012 ( .A(n2453), .B(n5572), .Y(n5573) );
INVX12TS U2013 ( .A(n2991), .Y(n2992) );
BUFX3TS U2014 ( .A(n4966), .Y(n5626) );
MXI2X1TS U2015 ( .A(n2259), .B(n6187), .S0(n5913), .Y(n5332) );
BUFX4TS U2016 ( .A(n1974), .Y(n4211) );
BUFX4TS U2017 ( .A(n1974), .Y(n4308) );
BUFX4TS U2018 ( .A(n1974), .Y(n3841) );
BUFX12TS U2019 ( .A(n2822), .Y(n5444) );
BUFX12TS U2020 ( .A(n2649), .Y(n2648) );
BUFX16TS U2021 ( .A(n5239), .Y(n1927) );
CLKBUFX2TS U2022 ( .A(intDY_EWSW[4]), .Y(n2011) );
BUFX4TS U2023 ( .A(n1974), .Y(n4296) );
BUFX4TS U2024 ( .A(n1974), .Y(n3833) );
CLKBUFX2TS U2025 ( .A(intDY_EWSW[46]), .Y(n1988) );
NOR2BX1TS U2026 ( .AN(n5789), .B(n5807), .Y(n5312) );
AND2X2TS U2027 ( .A(n5814), .B(Raw_mant_NRM_SWR[3]), .Y(n5809) );
NAND2X4TS U2028 ( .A(n2402), .B(n2401), .Y(n2400) );
OR2X2TS U2029 ( .A(n5792), .B(n6194), .Y(n5532) );
NAND2X2TS U2030 ( .A(n4484), .B(n5913), .Y(n3404) );
INVX2TS U2031 ( .A(n5638), .Y(n2459) );
NAND2X1TS U2032 ( .A(n5764), .B(n2178), .Y(n5768) );
NAND2X1TS U2033 ( .A(n5764), .B(n2157), .Y(n5770) );
NAND2X1TS U2034 ( .A(n5764), .B(n2175), .Y(n5774) );
AND2X2TS U2035 ( .A(n5799), .B(n2429), .Y(n5803) );
NOR2X1TS U2036 ( .A(n2706), .B(n1580), .Y(n2705) );
NAND2X2TS U2037 ( .A(n4562), .B(n2518), .Y(n2129) );
NAND2XLTS U2038 ( .A(n5730), .B(DmP_mant_SFG_SWR[26]), .Y(n5493) );
CLKBUFX2TS U2039 ( .A(intDY_EWSW[47]), .Y(n1987) );
BUFX4TS U2040 ( .A(n4966), .Y(n5639) );
BUFX3TS U2041 ( .A(n4869), .Y(n5030) );
AND2X2TS U2042 ( .A(n5823), .B(Raw_mant_NRM_SWR[30]), .Y(n3328) );
AND2X2TS U2043 ( .A(n5823), .B(Raw_mant_NRM_SWR[29]), .Y(n3339) );
AND2X2TS U2044 ( .A(n5823), .B(Raw_mant_NRM_SWR[32]), .Y(n2316) );
AND2X2TS U2045 ( .A(n5823), .B(Raw_mant_NRM_SWR[19]), .Y(n3267) );
NAND2XLTS U2046 ( .A(n5736), .B(DmP_mant_SHT1_SW[20]), .Y(n5283) );
NAND2XLTS U2047 ( .A(n5736), .B(DmP_mant_SHT1_SW[12]), .Y(n5286) );
NAND2XLTS U2048 ( .A(n5732), .B(DmP_mant_SFG_SWR[13]), .Y(n2380) );
NAND2XLTS U2049 ( .A(n5462), .B(DmP_mant_SHT1_SW[48]), .Y(n5305) );
NAND2XLTS U2050 ( .A(n5462), .B(DmP_mant_SHT1_SW[36]), .Y(n5292) );
AOI21X1TS U2051 ( .A0(n5980), .A1(n5972), .B0(n5974), .Y(n5964) );
NOR2X2TS U2052 ( .A(n2071), .B(n2720), .Y(n2069) );
NAND3X6TS U2053 ( .A(n4018), .B(n4017), .C(n4019), .Y(n1145) );
XOR2X1TS U2054 ( .A(n5525), .B(n5482), .Y(n5483) );
BUFX3TS U2055 ( .A(n4869), .Y(n5991) );
NAND2BX2TS U2056 ( .AN(n5236), .B(n5208), .Y(n3207) );
OAI21X1TS U2057 ( .A0(n5746), .A1(n5475), .B0(n5474), .Y(n5479) );
OAI21X1TS U2058 ( .A0(n5746), .A1(n5515), .B0(n5514), .Y(n5519) );
NOR2BX2TS U2059 ( .AN(n4682), .B(n2783), .Y(n2782) );
OAI21X1TS U2060 ( .A0(n5746), .A1(n4529), .B0(n4528), .Y(n4534) );
AND2X2TS U2061 ( .A(n5823), .B(n2003), .Y(n3299) );
OR2X2TS U2062 ( .A(n5780), .B(n5295), .Y(n5298) );
NOR2BX1TS U2063 ( .AN(n2280), .B(n5861), .Y(n3098) );
NAND2X2TS U2064 ( .A(n2591), .B(n5647), .Y(n5650) );
NOR2X2TS U2065 ( .A(n4883), .B(n4882), .Y(n6816) );
NAND2X6TS U2066 ( .A(n2655), .B(n4370), .Y(n4879) );
NOR2X2TS U2067 ( .A(n5646), .B(n5645), .Y(n5651) );
BUFX4TS U2068 ( .A(n4966), .Y(n5925) );
OR2X2TS U2069 ( .A(n5780), .B(n6244), .Y(n5288) );
NAND2X1TS U2070 ( .A(n2514), .B(n2424), .Y(n2903) );
NAND2X1TS U2071 ( .A(n2323), .B(n5701), .Y(n2704) );
NAND2X2TS U2072 ( .A(n2078), .B(n4563), .Y(n2077) );
AOI21X2TS U2073 ( .A0(n5618), .A1(n5061), .B0(n5060), .Y(n5066) );
BUFX3TS U2074 ( .A(n4869), .Y(n5924) );
NOR2X2TS U2075 ( .A(n5235), .B(n4676), .Y(n4672) );
NAND2X1TS U2076 ( .A(n2540), .B(n6258), .Y(n3009) );
NAND2X1TS U2077 ( .A(n2489), .B(DmP_mant_SFG_SWR[20]), .Y(n2877) );
NOR2X1TS U2078 ( .A(n3057), .B(n3058), .Y(n3055) );
MXI2X2TS U2079 ( .A(n6177), .B(n6253), .S0(n5884), .Y(n1559) );
AOI22X1TS U2080 ( .A0(n5699), .A1(Shift_amount_SHT1_EWR[3]), .B0(n3461),
.B1(n1969), .Y(n3403) );
NAND2XLTS U2081 ( .A(n5732), .B(n2382), .Y(n2940) );
NOR2X1TS U2082 ( .A(n3057), .B(n2302), .Y(n3056) );
NAND2X2TS U2083 ( .A(n5674), .B(n5673), .Y(n5675) );
BUFX4TS U2084 ( .A(n1974), .Y(n3732) );
OAI21X1TS U2085 ( .A0(n5019), .A1(n4923), .B0(n4922), .Y(n4924) );
NAND2X4TS U2086 ( .A(n2552), .B(n5045), .Y(n2801) );
AOI21X2TS U2087 ( .A0(n2506), .A1(n4891), .B0(n4894), .Y(n3246) );
NOR2X1TS U2088 ( .A(n5712), .B(n5644), .Y(n5646) );
NAND2X1TS U2089 ( .A(n2363), .B(n5020), .Y(n5028) );
NAND2X1TS U2090 ( .A(n1956), .B(n4441), .Y(n4449) );
NAND2X1TS U2091 ( .A(n5789), .B(n5912), .Y(n5791) );
NAND2X1TS U2092 ( .A(n4980), .B(n4979), .Y(n4988) );
INVX2TS U2093 ( .A(n2626), .Y(n4513) );
NAND2X1TS U2094 ( .A(n4818), .B(n4817), .Y(n4827) );
INVX8TS U2095 ( .A(n2423), .Y(n5618) );
NAND2X1TS U2096 ( .A(n4841), .B(n4839), .Y(n4750) );
NAND2X1TS U2097 ( .A(n5064), .B(n5063), .Y(n5071) );
NAND2X1TS U2098 ( .A(n4733), .B(n4822), .Y(n4736) );
NAND2X1TS U2099 ( .A(n5705), .B(n2498), .Y(n4561) );
NAND2X1TS U2100 ( .A(n5099), .B(n5097), .Y(n5051) );
NAND2X1TS U2101 ( .A(n5003), .B(n5001), .Y(n4864) );
OA21X1TS U2102 ( .A0(n5525), .A1(n5524), .B0(n5523), .Y(n2455) );
OA21X1TS U2103 ( .A0(n5525), .A1(n4535), .B0(n6075), .Y(n2460) );
NAND2X1TS U2104 ( .A(n4702), .B(n1996), .Y(n4707) );
NAND2X1TS U2105 ( .A(n4997), .B(n4996), .Y(n5009) );
NAND2X2TS U2106 ( .A(n2323), .B(n5572), .Y(n2723) );
NAND2X4TS U2107 ( .A(n1911), .B(n5036), .Y(n3063) );
INVX3TS U2108 ( .A(n5853), .Y(n5800) );
INVX3TS U2109 ( .A(n5853), .Y(n5818) );
NAND2X1TS U2110 ( .A(n2607), .B(DmP_mant_SFG_SWR[35]), .Y(n4519) );
INVX3TS U2111 ( .A(n2500), .Y(n2501) );
INVX2TS U2112 ( .A(n2449), .Y(n5217) );
NAND2XLTS U2113 ( .A(n2453), .B(n2512), .Y(n5571) );
NAND2X1TS U2114 ( .A(n4632), .B(n4630), .Y(n4549) );
INVX2TS U2115 ( .A(n4589), .Y(n5786) );
NAND2X4TS U2116 ( .A(n2104), .B(n1972), .Y(n2103) );
NAND2XLTS U2117 ( .A(n5164), .B(n5163), .Y(n5165) );
OAI21X1TS U2118 ( .A0(n5634), .A1(n5633), .B0(n2315), .Y(n4876) );
NAND2X2TS U2119 ( .A(n5497), .B(n1971), .Y(n2078) );
NOR2X6TS U2120 ( .A(n1981), .B(n2518), .Y(n2756) );
CLKAND2X2TS U2121 ( .A(n5115), .B(n5114), .Y(n2376) );
NAND2X2TS U2122 ( .A(n4559), .B(n5653), .Y(n3890) );
NAND2XLTS U2123 ( .A(n2687), .B(n2697), .Y(n2686) );
AND2X2TS U2124 ( .A(n5732), .B(DmP_mant_SFG_SWR[6]), .Y(n2720) );
AND2X2TS U2125 ( .A(n5435), .B(n5436), .Y(n2402) );
OA21X2TS U2126 ( .A0(n5159), .A1(n5044), .B0(n5043), .Y(n1957) );
BUFX16TS U2127 ( .A(n2609), .Y(n1918) );
NOR2X1TS U2128 ( .A(n2301), .B(n2554), .Y(n2367) );
NOR2X2TS U2129 ( .A(n5274), .B(n6259), .Y(n5438) );
NAND2X2TS U2130 ( .A(n5545), .B(n5653), .Y(n2620) );
NAND2X1TS U2131 ( .A(n5730), .B(n2131), .Y(n4522) );
NOR2X2TS U2132 ( .A(n2619), .B(n5645), .Y(n2618) );
NAND2X1TS U2133 ( .A(n2453), .B(n5727), .Y(n3036) );
NAND2X2TS U2134 ( .A(n4616), .B(n5701), .Y(n4178) );
NAND3X4TS U2135 ( .A(n4348), .B(n4347), .C(n4346), .Y(n4380) );
NOR2BX2TS U2136 ( .AN(n5656), .B(n5496), .Y(n2741) );
CLKAND2X2TS U2137 ( .A(n2607), .B(DmP_mant_SFG_SWR[43]), .Y(n5201) );
CLKBUFX2TS U2138 ( .A(n5591), .Y(n1984) );
NAND2X2TS U2139 ( .A(n5654), .B(n5716), .Y(n4319) );
CLKAND2X2TS U2140 ( .A(n4954), .B(n3213), .Y(n3212) );
OAI21X2TS U2141 ( .A0(n5159), .A1(n4976), .B0(n4975), .Y(n3030) );
NOR2X1TS U2142 ( .A(n5605), .B(n4805), .Y(n4806) );
NOR2X1TS U2143 ( .A(n5012), .B(n4741), .Y(n4743) );
BUFX3TS U2144 ( .A(n4869), .Y(n5638) );
INVX2TS U2145 ( .A(n5246), .Y(n1923) );
NOR2X2TS U2146 ( .A(n3059), .B(n2302), .Y(n3058) );
OAI21X1TS U2147 ( .A0(n5708), .A1(n5707), .B0(n5706), .Y(n5709) );
NOR2X2TS U2148 ( .A(n5633), .B(n5605), .Y(n5636) );
BUFX4TS U2149 ( .A(n1974), .Y(n5278) );
NAND4X2TS U2150 ( .A(n5719), .B(n5718), .C(n2184), .D(n6599), .Y(n5908) );
INVX4TS U2151 ( .A(n2414), .Y(n2071) );
OAI21X2TS U2152 ( .A0(n5019), .A1(n4770), .B0(n4769), .Y(n4771) );
AOI21X2TS U2153 ( .A0(n5625), .A1(n4846), .B0(n4845), .Y(n4851) );
OA21X2TS U2154 ( .A0(n5025), .A1(n4748), .B0(n4747), .Y(n2318) );
AOI21X1TS U2155 ( .A0(n5078), .A1(n5081), .B0(n5042), .Y(n5043) );
BUFX3TS U2156 ( .A(n5683), .Y(n2456) );
INVX1TS U2157 ( .A(n3136), .Y(n4692) );
INVX8TS U2158 ( .A(n4884), .Y(n5019) );
BUFX3TS U2159 ( .A(n4050), .Y(n2486) );
AND2X6TS U2160 ( .A(n3047), .B(n3046), .Y(n2007) );
INVX12TS U2161 ( .A(n2423), .Y(n2549) );
NOR2X1TS U2162 ( .A(n5095), .B(n4861), .Y(n4863) );
NAND2X2TS U2163 ( .A(n2512), .B(n4609), .Y(n3044) );
NOR2X4TS U2164 ( .A(n4556), .B(n2746), .Y(n2745) );
NAND2XLTS U2165 ( .A(n2453), .B(n5701), .Y(n5704) );
NAND2X1TS U2166 ( .A(n5224), .B(n4681), .Y(n4683) );
NOR2X2TS U2167 ( .A(n6263), .B(DMP_EXP_EWSW[56]), .Y(n6007) );
OR2X2TS U2168 ( .A(n1997), .B(n2181), .Y(n5718) );
NAND2X2TS U2169 ( .A(n5730), .B(DmP_mant_SFG_SWR[11]), .Y(n4017) );
INVX4TS U2170 ( .A(n2974), .Y(n2414) );
NAND2X4TS U2171 ( .A(n5674), .B(n5721), .Y(n3045) );
NAND2X6TS U2172 ( .A(n2876), .B(n2512), .Y(n2696) );
NAND2X2TS U2173 ( .A(n2806), .B(Raw_mant_NRM_SWR[12]), .Y(n5695) );
NAND2X2TS U2174 ( .A(n5487), .B(n5727), .Y(n2961) );
NAND2X2TS U2175 ( .A(n5653), .B(n5550), .Y(n3034) );
NAND2X1TS U2176 ( .A(n4629), .B(n4632), .Y(n4634) );
NOR2X1TS U2177 ( .A(n2551), .B(n5495), .Y(n5496) );
CLKBUFX2TS U2178 ( .A(n6728), .Y(n5246) );
CLKINVX1TS U2179 ( .A(n5732), .Y(n3001) );
INVX2TS U2180 ( .A(n2351), .Y(n2807) );
OA21X1TS U2181 ( .A0(n5103), .A1(n5169), .B0(add_x_6_n193), .Y(n1949) );
NAND2X2TS U2182 ( .A(n2323), .B(n1970), .Y(n2976) );
NOR2X6TS U2183 ( .A(n2685), .B(n2684), .Y(n2689) );
NAND2X2TS U2184 ( .A(n5489), .B(n5673), .Y(n5490) );
OAI21X1TS U2185 ( .A0(n5103), .A1(n4861), .B0(n4860), .Y(n4862) );
OR2X2TS U2186 ( .A(n4548), .B(n4464), .Y(n2834) );
BUFX3TS U2187 ( .A(n1981), .Y(n5756) );
NAND2X2TS U2188 ( .A(n5666), .B(n1970), .Y(n4612) );
AOI2BB2X2TS U2189 ( .B0(n4912), .B1(n4911), .A0N(n6124), .A1N(n2573), .Y(
n2778) );
NAND2X2TS U2190 ( .A(n4921), .B(n5011), .Y(n4923) );
AOI21X2TS U2191 ( .A0(n3201), .A1(n4974), .B0(n4973), .Y(n4975) );
NAND2X4TS U2192 ( .A(n2842), .B(n1971), .Y(n2691) );
NOR2X4TS U2193 ( .A(n2693), .B(n3004), .Y(n2692) );
AOI21X1TS U2194 ( .A0(n3201), .A1(n4991), .B0(n4990), .Y(n4992) );
NAND2X2TS U2195 ( .A(n4157), .B(n5000), .Y(n4159) );
OAI21X2TS U2196 ( .A0(n5025), .A1(n4778), .B0(n1996), .Y(n4779) );
NAND3BX2TS U2197 ( .AN(n3004), .B(n4480), .C(n4482), .Y(n3010) );
OAI21X1TS U2198 ( .A0(n5103), .A1(n5102), .B0(n5101), .Y(n5104) );
INVX3TS U2199 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n2629) );
NOR2X2TS U2200 ( .A(n4398), .B(n4417), .Y(n4403) );
AOI2BB1X2TS U2201 ( .A0N(n4547), .A1N(n4464), .B0(n4465), .Y(n2833) );
AOI2BB2X2TS U2202 ( .B0(n2827), .B1(n1716), .A0N(n4039), .A1N(n4025), .Y(
n3963) );
NOR2X2TS U2203 ( .A(n5712), .B(n6897), .Y(n4314) );
NOR2X2TS U2204 ( .A(n5022), .B(n4936), .Y(n4938) );
NOR2X4TS U2205 ( .A(n5539), .B(n5712), .Y(n2619) );
OAI22X1TS U2206 ( .A0(n5186), .A1(n5712), .B0(n2494), .B1(n2887), .Y(n5188)
);
NOR2X2TS U2207 ( .A(n3210), .B(n4856), .Y(n3209) );
CLKINVX2TS U2208 ( .A(n1970), .Y(n4567) );
AOI21X1TS U2209 ( .A0(n4934), .A1(n4759), .B0(n4758), .Y(n4760) );
NOR2X4TS U2210 ( .A(n3221), .B(n5078), .Y(n3220) );
OR2X2TS U2211 ( .A(n1981), .B(left_right_SHT2), .Y(n5556) );
INVX6TS U2212 ( .A(n5159), .Y(n2785) );
NOR2BX2TS U2213 ( .AN(n1968), .B(n3909), .Y(n2124) );
NAND2X2TS U2214 ( .A(n5054), .B(n2512), .Y(n5055) );
INVX6TS U2215 ( .A(n4705), .Y(n5025) );
INVX2TS U2216 ( .A(n5641), .Y(n2658) );
NAND2X1TS U2217 ( .A(sub_x_1_n31), .B(DMP_EXP_EWSW[55]), .Y(n6001) );
INVX4TS U2218 ( .A(n1734), .Y(n5539) );
INVX4TS U2219 ( .A(n4727), .Y(n4810) );
INVX12TS U2220 ( .A(n4444), .Y(n2506) );
INVX8TS U2221 ( .A(n4885), .Y(n5012) );
CLKBUFX2TS U2222 ( .A(n5077), .Y(n5078) );
CLKINVX3TS U2223 ( .A(n4548), .Y(n4629) );
NAND2X2TS U2224 ( .A(n4516), .B(n5673), .Y(n2580) );
INVX8TS U2225 ( .A(n5329), .Y(n5780) );
INVX2TS U2226 ( .A(n4544), .Y(n4632) );
NOR2X2TS U2227 ( .A(sub_x_1_n33), .B(DMP_EXP_EWSW[53]), .Y(n5938) );
NOR2X2TS U2228 ( .A(n3332), .B(DMP_EXP_EWSW[52]), .Y(n5937) );
BUFX3TS U2229 ( .A(n4823), .Y(n2866) );
INVX2TS U2230 ( .A(n5525), .Y(n3090) );
NOR2X2TS U2231 ( .A(n2551), .B(n3951), .Y(n3953) );
BUFX4TS U2232 ( .A(n1981), .Y(n5730) );
CLKAND2X4TS U2233 ( .A(n5167), .B(n4801), .Y(n1962) );
AOI21X2TS U2234 ( .A0(n5004), .A1(n5003), .B0(n5002), .Y(n5005) );
INVX3TS U2235 ( .A(n5087), .Y(n4989) );
NAND2X4TS U2236 ( .A(n5551), .B(n2381), .Y(n4563) );
NOR2X4TS U2237 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[16]), .Y(
n4361) );
AOI21X2TS U2238 ( .A0(n5606), .A1(n4875), .B0(n4874), .Y(n5632) );
AOI21X1TS U2239 ( .A0(n4934), .A1(n2363), .B0(n4445), .Y(n4446) );
AND2X2TS U2240 ( .A(n3397), .B(Raw_mant_NRM_SWR[22]), .Y(n2351) );
NOR2X2TS U2241 ( .A(n5086), .B(n3214), .Y(n3210) );
NAND4X4TS U2242 ( .A(n2703), .B(n2702), .C(n2701), .D(n2700), .Y(n5705) );
INVX8TS U2243 ( .A(n5156), .Y(n4954) );
INVX4TS U2244 ( .A(n1710), .Y(n5711) );
OR2X2TS U2245 ( .A(n4468), .B(n4467), .Y(n3085) );
NAND2BX2TS U2246 ( .AN(n2389), .B(n5421), .Y(n5431) );
NAND2X2TS U2247 ( .A(n4609), .B(n2556), .Y(n4480) );
NAND2X2TS U2248 ( .A(n4904), .B(n4903), .Y(n5533) );
INVX4TS U2249 ( .A(n5198), .Y(n5553) );
NOR2X2TS U2250 ( .A(n5087), .B(n3214), .Y(n3213) );
NAND2X2TS U2251 ( .A(n4931), .B(n4933), .Y(n4936) );
NAND2X2TS U2252 ( .A(n5000), .B(n4983), .Y(n4985) );
OR2X1TS U2253 ( .A(n5661), .B(n2213), .Y(n5663) );
NAND2X2TS U2254 ( .A(n2842), .B(n2556), .Y(n2881) );
AND2X2TS U2255 ( .A(n4603), .B(n6267), .Y(n2301) );
NOR2X6TS U2256 ( .A(n5159), .B(n5079), .Y(n3221) );
INVX4TS U2257 ( .A(n2507), .Y(n2974) );
NAND2X2TS U2258 ( .A(n2453), .B(n5721), .Y(n3459) );
CLKBUFX2TS U2259 ( .A(n4777), .Y(n1996) );
CLKINVX2TS U2260 ( .A(n2980), .Y(n2109) );
NAND2X2TS U2261 ( .A(n4931), .B(n2363), .Y(n4447) );
NOR2X1TS U2262 ( .A(n5129), .B(n5127), .Y(n5131) );
NAND2BX2TS U2263 ( .AN(n4557), .B(n1968), .Y(n3047) );
BUFX3TS U2264 ( .A(n1981), .Y(n5732) );
NAND2X4TS U2265 ( .A(n5054), .B(n5673), .Y(n4058) );
OAI21X2TS U2266 ( .A0(n4919), .A1(n4918), .B0(n4917), .Y(n4920) );
NAND2X2TS U2267 ( .A(n5094), .B(n5099), .Y(n5102) );
NAND2X2TS U2268 ( .A(n2502), .B(n1716), .Y(n2892) );
NAND2X1TS U2269 ( .A(n5876), .B(n2478), .Y(n2701) );
NAND2X1TS U2270 ( .A(n2841), .B(n6499), .Y(n4338) );
AND2X6TS U2271 ( .A(n5716), .B(n2517), .Y(n5572) );
NAND2X1TS U2272 ( .A(n2476), .B(n1743), .Y(n3915) );
BUFX6TS U2273 ( .A(n2995), .Y(n2573) );
INVX2TS U2274 ( .A(n1735), .Y(n5495) );
NAND2X1TS U2275 ( .A(n1742), .B(n2475), .Y(n3968) );
NOR2X1TS U2276 ( .A(n3357), .B(DMP_SFG[51]), .Y(n5214) );
CLKINVX6TS U2277 ( .A(n1711), .Y(n5668) );
NAND2X1TS U2278 ( .A(n2523), .B(n1739), .Y(n3889) );
NAND2X1TS U2279 ( .A(n5505), .B(n1743), .Y(n3884) );
INVX2TS U2280 ( .A(n3201), .Y(n5086) );
NAND2X1TS U2281 ( .A(n1723), .B(n5505), .Y(n3911) );
CLKINVX6TS U2282 ( .A(n2080), .Y(n2076) );
NAND2X4TS U2283 ( .A(n2502), .B(n1718), .Y(n2945) );
NAND2X6TS U2284 ( .A(n5551), .B(left_right_SHT2), .Y(n4613) );
CLKINVX6TS U2285 ( .A(n3089), .Y(n3087) );
NAND2X2TS U2286 ( .A(n2477), .B(n1748), .Y(n3960) );
INVX4TS U2287 ( .A(n3919), .Y(n5673) );
NOR2X6TS U2288 ( .A(n4799), .B(n4861), .Y(n4801) );
NAND2X2TS U2289 ( .A(n2713), .B(n2151), .Y(n3913) );
INVX4TS U2290 ( .A(n5656), .Y(n2577) );
NAND2X4TS U2291 ( .A(n5669), .B(n2512), .Y(n3006) );
CLKBUFX2TS U2292 ( .A(n4842), .Y(n2015) );
NAND3X2TS U2293 ( .A(Raw_mant_NRM_SWR[25]), .B(n4487), .C(n4587), .Y(n4906)
);
NAND2X2TS U2294 ( .A(n4389), .B(n1727), .Y(n3886) );
NAND2X2TS U2295 ( .A(n5729), .B(n3919), .Y(n5198) );
NAND2X2TS U2296 ( .A(n5563), .B(n1714), .Y(n5564) );
NAND2X2TS U2297 ( .A(n1732), .B(n4388), .Y(n2702) );
NOR2BX2TS U2298 ( .AN(n2827), .B(n4038), .Y(n2826) );
NAND2BX2TS U2299 ( .AN(n5024), .B(n4759), .Y(n3109) );
CLKBUFX2TS U2300 ( .A(n5109), .Y(n2408) );
NOR2X2TS U2301 ( .A(n4870), .B(n4873), .Y(n4875) );
CLKAND2X2TS U2302 ( .A(n4089), .B(n4094), .Y(n2448) );
XNOR2X1TS U2303 ( .A(intDX_EWSW[45]), .B(n2139), .Y(n5360) );
XNOR2X1TS U2304 ( .A(intDX_EWSW[9]), .B(n2431), .Y(n5397) );
XNOR2X1TS U2305 ( .A(intDX_EWSW[11]), .B(n2462), .Y(n5427) );
XNOR2X1TS U2306 ( .A(intDX_EWSW[34]), .B(n2130), .Y(n5361) );
XNOR2X1TS U2307 ( .A(intDX_EWSW[1]), .B(n2438), .Y(n5363) );
OR2X4TS U2308 ( .A(n4130), .B(n2333), .Y(n2463) );
NAND2X6TS U2309 ( .A(n2842), .B(n5716), .Y(n2670) );
XNOR2X1TS U2310 ( .A(intDX_EWSW[55]), .B(intDY_EWSW[55]), .Y(n5421) );
XNOR2X1TS U2311 ( .A(intDX_EWSW[18]), .B(intDY_EWSW[18]), .Y(n5387) );
NAND2X6TS U2312 ( .A(n2806), .B(n3100), .Y(n3393) );
NAND2X2TS U2313 ( .A(n2840), .B(Raw_mant_NRM_SWR[19]), .Y(n2969) );
XNOR2X1TS U2314 ( .A(intDX_EWSW[8]), .B(intDY_EWSW[8]), .Y(n5410) );
AND2X4TS U2315 ( .A(n3402), .B(n3401), .Y(n2347) );
NAND2X2TS U2316 ( .A(n5561), .B(n1740), .Y(n3957) );
OR2X2TS U2317 ( .A(n5661), .B(n2236), .Y(n4166) );
XNOR2X2TS U2318 ( .A(intDX_EWSW[13]), .B(n2427), .Y(n5390) );
NAND2X2TS U2319 ( .A(n2476), .B(n1732), .Y(n3955) );
NAND3X6TS U2320 ( .A(n3079), .B(n3078), .C(n3163), .Y(n3077) );
NAND2X2TS U2321 ( .A(n2523), .B(n4020), .Y(n3966) );
XNOR2X2TS U2322 ( .A(intDX_EWSW[36]), .B(intDY_EWSW[36]), .Y(n5367) );
INVX2TS U2323 ( .A(n5127), .Y(n3215) );
XNOR2X2TS U2324 ( .A(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n5411) );
XNOR2X2TS U2325 ( .A(intDX_EWSW[25]), .B(intDY_EWSW[25]), .Y(n5377) );
XNOR2X2TS U2326 ( .A(intDX_EWSW[10]), .B(intDY_EWSW[10]), .Y(n5399) );
XNOR2X2TS U2327 ( .A(intDX_EWSW[32]), .B(intDY_EWSW[32]), .Y(n5378) );
XNOR2X2TS U2328 ( .A(intDX_EWSW[50]), .B(intDY_EWSW[50]), .Y(n5426) );
XNOR2X2TS U2329 ( .A(intDX_EWSW[38]), .B(n2154), .Y(n5365) );
NAND2X2TS U2330 ( .A(n1720), .B(n4315), .Y(n2703) );
NAND3X4TS U2331 ( .A(n3160), .B(n5641), .C(n4603), .Y(n3081) );
XNOR2X2TS U2332 ( .A(intDX_EWSW[44]), .B(n2149), .Y(n5359) );
XNOR2X2TS U2333 ( .A(intDX_EWSW[51]), .B(n1914), .Y(n5418) );
NOR2X2TS U2334 ( .A(n4026), .B(n2494), .Y(n2725) );
XNOR2X1TS U2335 ( .A(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n5388) );
XNOR2X1TS U2336 ( .A(intDX_EWSW[52]), .B(intDY_EWSW[52]), .Y(n5419) );
XNOR2X1TS U2337 ( .A(intDX_EWSW[49]), .B(intDY_EWSW[49]), .Y(n5420) );
NOR2X4TS U2338 ( .A(n5130), .B(n3050), .Y(n3049) );
NAND2X2TS U2339 ( .A(n5054), .B(n2497), .Y(n4479) );
NAND2X2TS U2340 ( .A(n1734), .B(n2479), .Y(n5560) );
AND2X6TS U2341 ( .A(n5716), .B(left_right_SHT2), .Y(n5701) );
INVX2TS U2342 ( .A(n1720), .Y(n4025) );
INVX2TS U2343 ( .A(n5647), .Y(n2049) );
NAND2X1TS U2344 ( .A(DMP_SFG[51]), .B(DmP_mant_SFG_SWR[53]), .Y(n4871) );
NAND2X1TS U2345 ( .A(n2841), .B(n6505), .Y(n4334) );
INVX2TS U2346 ( .A(n1715), .Y(n4557) );
BUFX4TS U2347 ( .A(n5593), .Y(n1982) );
AOI21X2TS U2348 ( .A0(n3453), .A1(n5563), .B0(n4171), .Y(n5728) );
NOR2X4TS U2349 ( .A(DMP_SFG[49]), .B(DmP_mant_SFG_SWR[51]), .Y(n5230) );
NAND2X1TS U2350 ( .A(n3335), .B(n4084), .Y(n2372) );
CLKINVX6TS U2351 ( .A(n1708), .Y(n4026) );
INVX4TS U2352 ( .A(n5703), .Y(n3004) );
INVX8TS U2353 ( .A(n2494), .Y(n2827) );
INVX4TS U2354 ( .A(n2551), .Y(n1968) );
NAND2X2TS U2355 ( .A(n2479), .B(n1718), .Y(n5565) );
NAND2X2TS U2356 ( .A(n1730), .B(n2477), .Y(n2623) );
NOR2X4TS U2357 ( .A(n5024), .B(n4145), .Y(n4147) );
NAND2X6TS U2358 ( .A(n5691), .B(Raw_mant_NRM_SWR[15]), .Y(n4357) );
NOR2X2TS U2359 ( .A(n4756), .B(n4926), .Y(n4759) );
NOR2X6TS U2360 ( .A(n4905), .B(n3384), .Y(n4581) );
NOR2X4TS U2361 ( .A(n6093), .B(n6198), .Y(n5721) );
INVX2TS U2362 ( .A(n3082), .Y(n3078) );
INVX2TS U2363 ( .A(n5645), .Y(n5656) );
NAND2X2TS U2364 ( .A(n2478), .B(n4020), .Y(n3463) );
INVX4TS U2365 ( .A(n5538), .Y(n4555) );
OR2X2TS U2366 ( .A(n4040), .B(n3455), .Y(n2829) );
CLKINVX1TS U2367 ( .A(n5110), .Y(n3050) );
OR2X2TS U2368 ( .A(n1997), .B(n2198), .Y(n4332) );
BUFX4TS U2369 ( .A(n4593), .Y(n2446) );
NOR2X6TS U2370 ( .A(n4821), .B(n4139), .Y(n4706) );
NAND2X2TS U2371 ( .A(n5505), .B(n1736), .Y(n2057) );
BUFX3TS U2372 ( .A(n1731), .Y(n2151) );
AND2X2TS U2373 ( .A(n4064), .B(n3091), .Y(n2368) );
INVX4TS U2374 ( .A(n4564), .Y(n2513) );
OAI21X2TS U2375 ( .A0(n4510), .A1(n4509), .B0(n2435), .Y(n2584) );
INVX2TS U2376 ( .A(n3197), .Y(n5130) );
BUFX4TS U2377 ( .A(n3152), .Y(n2806) );
OR2X2TS U2378 ( .A(n4598), .B(n3392), .Y(n3100) );
NAND2X6TS U2379 ( .A(n5488), .B(n5544), .Y(n2736) );
NAND2X6TS U2380 ( .A(n1719), .B(n4315), .Y(n2126) );
BUFX2TS U2381 ( .A(n4085), .Y(n2852) );
NAND2X2TS U2382 ( .A(n4059), .B(n1964), .Y(n4060) );
NAND3X6TS U2383 ( .A(n2634), .B(n4349), .C(n2644), .Y(n5641) );
CLKAND2X2TS U2384 ( .A(n4091), .B(n4089), .Y(n3139) );
NOR2X4TS U2385 ( .A(n5789), .B(n4602), .Y(n4603) );
NAND2X2TS U2386 ( .A(n1708), .B(n5720), .Y(n2729) );
NAND2X2TS U2387 ( .A(n1748), .B(n5561), .Y(n2056) );
BUFX4TS U2388 ( .A(n4597), .Y(n2840) );
NAND2X2TS U2389 ( .A(n1734), .B(n2490), .Y(n2625) );
NAND2X4TS U2390 ( .A(n4597), .B(n4488), .Y(n2780) );
NAND4X2TS U2391 ( .A(n3423), .B(n3422), .C(n3421), .D(n3420), .Y(n1704) );
NAND2X4TS U2392 ( .A(n2293), .B(n4086), .Y(n2096) );
NAND2X4TS U2393 ( .A(n4786), .B(n4792), .Y(n4788) );
NOR2X2TS U2394 ( .A(n2887), .B(n3455), .Y(n4010) );
AO22X1TS U2395 ( .A0(n6583), .A1(n2265), .B0(n2267), .B1(n2243), .Y(n2266)
);
OR2X6TS U2396 ( .A(n6784), .B(n2083), .Y(n2082) );
INVX2TS U2397 ( .A(n4085), .Y(n4082) );
BUFX3TS U2398 ( .A(n3958), .Y(n5713) );
AOI2BB2X1TS U2399 ( .B0(n6574), .B1(n2265), .A0N(n5660), .A1N(n2218), .Y(
n3898) );
NAND2X6TS U2400 ( .A(n4070), .B(n3131), .Y(n3154) );
AND2X6TS U2401 ( .A(n2711), .B(n3949), .Y(n2374) );
NAND2X1TS U2402 ( .A(n2523), .B(n1746), .Y(n3950) );
NAND2X4TS U2403 ( .A(n5653), .B(n2517), .Y(n5707) );
NAND2X4TS U2404 ( .A(DMP_SFG[44]), .B(DmP_mant_SFG_SWR[46]), .Y(n5001) );
NAND2X6TS U2405 ( .A(n1964), .B(n2483), .Y(n2293) );
OR2X2TS U2406 ( .A(n5661), .B(n2237), .Y(n3896) );
NAND2X2TS U2407 ( .A(n1730), .B(n5563), .Y(n2664) );
INVX3TS U2408 ( .A(n1709), .Y(n2887) );
BUFX4TS U2409 ( .A(n3958), .Y(n5647) );
NAND2X4TS U2410 ( .A(n4893), .B(n4137), .Y(n4139) );
INVX2TS U2411 ( .A(n4093), .Y(n4089) );
NOR2X4TS U2412 ( .A(n4754), .B(sub_x_5_n260), .Y(n5174) );
NAND2X2TS U2413 ( .A(n2553), .B(n1743), .Y(n4176) );
INVX2TS U2414 ( .A(n5685), .Y(n2441) );
NAND2X4TS U2415 ( .A(n4721), .B(n4135), .Y(n4821) );
NAND2X2TS U2416 ( .A(DMP_SFG[45]), .B(DmP_mant_SFG_SWR[47]), .Y(n4996) );
NOR2X4TS U2417 ( .A(n4646), .B(n4833), .Y(n4647) );
NOR2X2TS U2418 ( .A(n6300), .B(DMP_SFG[47]), .Y(n4676) );
NAND2X2TS U2419 ( .A(n4020), .B(n2713), .Y(n2715) );
NAND2X2TS U2420 ( .A(DmP_mant_SFG_SWR[39]), .B(DMP_SFG[37]), .Y(n5141) );
INVX4TS U2421 ( .A(n4463), .Y(n4464) );
NAND2X2TS U2422 ( .A(n1991), .B(n6504), .Y(n3422) );
INVX8TS U2423 ( .A(n3962), .Y(n5716) );
OR2X2TS U2424 ( .A(n5661), .B(n2209), .Y(n3904) );
BUFX12TS U2425 ( .A(n5702), .Y(n2512) );
NAND2X6TS U2426 ( .A(n4838), .B(n4141), .Y(n5024) );
INVX12TS U2427 ( .A(n2493), .Y(n2494) );
INVX4TS U2428 ( .A(n2274), .Y(n4065) );
NOR2X6TS U2429 ( .A(n3136), .B(n3134), .Y(n4824) );
NAND2X6TS U2430 ( .A(n4933), .B(n4143), .Y(n4145) );
CLKINVX6TS U2431 ( .A(n4564), .Y(n1971) );
NAND4X4TS U2432 ( .A(n3415), .B(n3414), .C(n3413), .D(n3412), .Y(n1708) );
NAND2XLTS U2433 ( .A(n2420), .B(n6508), .Y(n4053) );
INVX6TS U2434 ( .A(n3455), .Y(n5720) );
NOR3X1TS U2435 ( .A(n4351), .B(Raw_mant_NRM_SWR[9]), .C(n4350), .Y(n4352) );
CLKAND2X2TS U2436 ( .A(n4571), .B(n3227), .Y(n3226) );
NAND2X2TS U2437 ( .A(n2475), .B(n1735), .Y(n4373) );
NAND2X2TS U2438 ( .A(n1742), .B(n2523), .Y(n2662) );
NOR2X2TS U2439 ( .A(n4785), .B(n6716), .Y(n4792) );
INVX3TS U2440 ( .A(n4171), .Y(n2044) );
BUFX6TS U2441 ( .A(n3454), .Y(n5505) );
NAND2X2TS U2442 ( .A(n4095), .B(n4094), .Y(n4096) );
NOR2X4TS U2443 ( .A(n4948), .B(add_x_6_n259), .Y(n5122) );
NAND2X2TS U2444 ( .A(n2490), .B(n1751), .Y(n3882) );
NAND3X2TS U2445 ( .A(n2110), .B(n3076), .C(n2371), .Y(n3188) );
OAI21X2TS U2446 ( .A0(n4055), .A1(n2495), .B0(n5538), .Y(n2731) );
NAND4X4TS U2447 ( .A(n2735), .B(n2734), .C(n2733), .D(n2732), .Y(n5489) );
NOR2X1TS U2448 ( .A(n4601), .B(n5779), .Y(n4602) );
BUFX8TS U2449 ( .A(n3451), .Y(n2551) );
NOR2BX1TS U2450 ( .AN(n4595), .B(n3162), .Y(n3161) );
BUFX12TS U2451 ( .A(n3451), .Y(n5712) );
AND2X6TS U2452 ( .A(n3171), .B(n3181), .Y(n2861) );
NAND2X4TS U2453 ( .A(n3947), .B(n2517), .Y(n4564) );
AND2X6TS U2454 ( .A(n5653), .B(left_right_SHT2), .Y(n5702) );
INVX4TS U2455 ( .A(n1749), .Y(n4041) );
OR2X2TS U2456 ( .A(n2262), .B(n2195), .Y(n4342) );
NAND2X2TS U2457 ( .A(n1732), .B(n4372), .Y(n2735) );
NAND2X4TS U2458 ( .A(n4489), .B(n3177), .Y(n4500) );
NAND2X6TS U2459 ( .A(n3947), .B(n5561), .Y(n3451) );
AND2X6TS U2460 ( .A(n2024), .B(n2023), .Y(n1947) );
NAND2X4TS U2461 ( .A(DMP_SFG[42]), .B(DmP_mant_SFG_SWR[44]), .Y(n5097) );
NAND2X1TS U2462 ( .A(n3312), .B(DMP_SFG[42]), .Y(n4659) );
CLKINVX1TS U2463 ( .A(Shift_amount_SHT1_EWR[0]), .Y(n4601) );
NAND2X6TS U2464 ( .A(n5645), .B(shift_value_SHT2_EWR[4]), .Y(n5538) );
BUFX3TS U2465 ( .A(n4808), .Y(n5912) );
NAND2X2TS U2466 ( .A(sub_x_5_n607), .B(DMP_SFG[35]), .Y(n5128) );
NAND2X2TS U2467 ( .A(DMP_SFG[39]), .B(DmP_mant_SFG_SWR[41]), .Y(n4956) );
BUFX16TS U2468 ( .A(n3171), .Y(n3169) );
NOR2BX1TS U2469 ( .AN(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .Y(
n3227) );
NAND2X2TS U2470 ( .A(n1991), .B(n6494), .Y(n3414) );
NAND2X4TS U2471 ( .A(n1734), .B(n4315), .Y(n3949) );
BUFX6TS U2472 ( .A(n3101), .Y(n2768) );
NAND2X6TS U2473 ( .A(n2310), .B(n4424), .Y(n4727) );
CLKINVX6TS U2474 ( .A(n4584), .Y(n4487) );
NOR2X6TS U2475 ( .A(n1951), .B(n2359), .Y(n2737) );
NAND2X6TS U2476 ( .A(n4655), .B(n5110), .Y(n4657) );
NAND2X1TS U2477 ( .A(n2420), .B(n6465), .Y(n4031) );
INVX4TS U2478 ( .A(n2473), .Y(n2475) );
NAND2X2TS U2479 ( .A(n4315), .B(n1718), .Y(n3946) );
OR2X4TS U2480 ( .A(n4000), .B(n2196), .Y(n3973) );
NOR2BX2TS U2481 ( .AN(n4574), .B(n4573), .Y(n3076) );
INVX2TS U2482 ( .A(n4648), .Y(n2814) );
INVX3TS U2483 ( .A(n5563), .Y(n2083) );
NAND2X2TS U2484 ( .A(n1744), .B(n2480), .Y(n2891) );
OR2X4TS U2485 ( .A(n2262), .B(n2209), .Y(n3412) );
AOI21X2TS U2486 ( .A0(n4916), .A1(n4644), .B0(n4643), .Y(n4645) );
NOR2X4TS U2487 ( .A(n3355), .B(DMP_SFG[44]), .Y(n4663) );
NOR2X4TS U2488 ( .A(n4744), .B(n4847), .Y(n4141) );
CLKINVX3TS U2489 ( .A(n4061), .Y(n4064) );
OR2X6TS U2490 ( .A(n5880), .B(n2467), .Y(n3341) );
OR2X4TS U2491 ( .A(n5661), .B(n2229), .Y(n3860) );
AND2X6TS U2492 ( .A(n1740), .B(n4389), .Y(n1951) );
INVX6TS U2493 ( .A(n2474), .Y(n2479) );
NOR2BX2TS U2494 ( .AN(DMP_exp_NRM2_EW[8]), .B(n3092), .Y(n3093) );
NAND2X2TS U2495 ( .A(n4504), .B(n6197), .Y(n3400) );
AND2X2TS U2496 ( .A(n3461), .B(bit_shift_SHT2), .Y(n2373) );
OR2X2TS U2497 ( .A(n6423), .B(n2189), .Y(n3868) );
INVX6TS U2498 ( .A(n2474), .Y(n2480) );
NOR2X4TS U2499 ( .A(n5058), .B(n4428), .Y(n4430) );
INVX2TS U2500 ( .A(n2085), .Y(n2280) );
NAND2X1TS U2501 ( .A(n5345), .B(n4589), .Y(n4590) );
NAND2X4TS U2502 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n5063) );
NAND2X4TS U2503 ( .A(DmP_mant_SFG_SWR[32]), .B(DMP_SFG[30]), .Y(n4927) );
INVX2TS U2504 ( .A(n2205), .Y(n3936) );
NOR2X6TS U2505 ( .A(n3453), .B(n2473), .Y(n2880) );
NOR2BX2TS U2506 ( .AN(n6109), .B(n2003), .Y(n4571) );
OR2X2TS U2507 ( .A(n6395), .B(n2199), .Y(n3424) );
INVX2TS U2508 ( .A(n3391), .Y(n4359) );
INVX12TS U2509 ( .A(n2559), .Y(n2667) );
NAND2X2TS U2510 ( .A(n2841), .B(n6454), .Y(n3862) );
NAND2X2TS U2511 ( .A(add_x_6_A_27_), .B(add_x_6_B_27_), .Y(n4781) );
NAND2X2TS U2512 ( .A(n2420), .B(n6493), .Y(n3410) );
NAND2X2TS U2513 ( .A(DMP_SFG[29]), .B(DmP_mant_SFG_SWR[31]), .Y(n4441) );
AND2X4TS U2514 ( .A(n6273), .B(n1985), .Y(n4823) );
NAND2BX2TS U2515 ( .AN(n3092), .B(DMP_exp_NRM2_EW[9]), .Y(n4095) );
OAI21X2TS U2516 ( .A0(n3642), .A1(n3641), .B0(n3640), .Y(n2116) );
NAND2X2TS U2517 ( .A(n2420), .B(n6488), .Y(n3438) );
NAND2X6TS U2518 ( .A(DmP_mant_SFG_SWR[29]), .B(n1994), .Y(n4848) );
NAND2X4TS U2519 ( .A(n2815), .B(n5038), .Y(n4648) );
OR2X4TS U2520 ( .A(n5661), .B(n2192), .Y(n3869) );
NAND2X6TS U2521 ( .A(n5520), .B(n4131), .Y(n4548) );
NAND2X2TS U2522 ( .A(n2420), .B(n6502), .Y(n4330) );
NOR2X6TS U2523 ( .A(n3228), .B(n1961), .Y(n5807) );
BUFX12TS U2524 ( .A(n3454), .Y(n4315) );
BUFX12TS U2525 ( .A(n3454), .Y(n5563) );
NOR2X2TS U2526 ( .A(n6410), .B(n2202), .Y(n2335) );
NAND2X4TS U2527 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n4817) );
INVX3TS U2528 ( .A(n3115), .Y(n3111) );
OR2X4TS U2529 ( .A(n4033), .B(n2194), .Y(n3993) );
NAND2X2TS U2530 ( .A(n2017), .B(n6466), .Y(n3870) );
NAND2X4TS U2531 ( .A(n1715), .B(n4389), .Y(n2599) );
BUFX8TS U2532 ( .A(n3885), .Y(n2523) );
AND2X4TS U2533 ( .A(n4599), .B(n4598), .Y(n3148) );
OR2X2TS U2534 ( .A(n4001), .B(n2185), .Y(n3440) );
OR2X6TS U2535 ( .A(n2086), .B(n1953), .Y(n1964) );
OR2X6TS U2536 ( .A(n4033), .B(n2217), .Y(n3970) );
NOR2X2TS U2537 ( .A(n3230), .B(n2343), .Y(n5295) );
OR2X2TS U2538 ( .A(sub_x_5_A_17_), .B(sub_x_5_n627), .Y(n5617) );
OR2X2TS U2539 ( .A(n6411), .B(n2225), .Y(n3969) );
BUFX6TS U2540 ( .A(n3885), .Y(n4388) );
NOR2X6TS U2541 ( .A(DMP_SFG[37]), .B(DmP_mant_SFG_SWR[39]), .Y(n5140) );
NAND2X6TS U2542 ( .A(n2062), .B(n3446), .Y(n1740) );
NOR2X6TS U2543 ( .A(DMP_SFG[39]), .B(DmP_mant_SFG_SWR[41]), .Y(n4955) );
INVX6TS U2544 ( .A(n5591), .Y(n5345) );
OR2X2TS U2545 ( .A(n6395), .B(n2212), .Y(n2366) );
NAND2X2TS U2546 ( .A(n2420), .B(n6452), .Y(n3434) );
OR2X4TS U2547 ( .A(n4033), .B(n6430), .Y(n3989) );
OR2X2TS U2548 ( .A(n4001), .B(n2192), .Y(n3448) );
NAND2X2TS U2549 ( .A(n3346), .B(DMP_SFG[29]), .Y(n4917) );
NAND2X2TS U2550 ( .A(n2420), .B(n6512), .Y(n3929) );
NAND2BX1TS U2551 ( .AN(n2260), .B(n2210), .Y(n3891) );
NAND2X2TS U2552 ( .A(n1991), .B(n6456), .Y(n3999) );
NAND2X2TS U2553 ( .A(n1991), .B(n6467), .Y(n3418) );
BUFX16TS U2554 ( .A(n3171), .Y(n2634) );
OR2X4TS U2555 ( .A(n4001), .B(n2238), .Y(n3428) );
NAND2X2TS U2556 ( .A(n6408), .B(n6495), .Y(n3990) );
NAND2X2TS U2557 ( .A(n2841), .B(n6448), .Y(n3879) );
NAND2X6TS U2558 ( .A(n3570), .B(n3643), .Y(n3644) );
NOR2X6TS U2559 ( .A(n5594), .B(n4716), .Y(n4424) );
NAND2X2TS U2560 ( .A(sub_x_5_n608), .B(DMP_SFG[34]), .Y(n5038) );
AND2X4TS U2561 ( .A(n3442), .B(n2147), .Y(n2936) );
OR2X4TS U2562 ( .A(n1997), .B(n2196), .Y(n3933) );
NAND2X1TS U2563 ( .A(n3348), .B(DMP_SFG[22]), .Y(n4427) );
NOR2X4TS U2564 ( .A(n4467), .B(n4469), .Y(n4133) );
NOR2X4TS U2565 ( .A(n6296), .B(DMP_SFG[38]), .Y(n4653) );
NAND2X4TS U2566 ( .A(n3338), .B(n3335), .Y(n4079) );
OAI21X2TS U2567 ( .A0(n4469), .A1(n4466), .B0(n4470), .Y(n4132) );
NOR2X4TS U2568 ( .A(n3474), .B(n3507), .Y(n2030) );
NAND3X6TS U2569 ( .A(n3525), .B(n2764), .C(n2763), .Y(n3528) );
INVX2TS U2570 ( .A(n3520), .Y(n2764) );
NAND2X1TS U2571 ( .A(n3277), .B(n2437), .Y(n3533) );
INVX6TS U2572 ( .A(n2473), .Y(n2476) );
NAND2X2TS U2573 ( .A(n3391), .B(n6193), .Y(n4351) );
CLKINVX2TS U2574 ( .A(n3310), .Y(n2036) );
OR2X6TS U2575 ( .A(n4033), .B(n2200), .Y(n3900) );
NAND2X4TS U2576 ( .A(n3551), .B(n3591), .Y(n3554) );
NAND2X4TS U2577 ( .A(DmP_mant_SFG_SWR[16]), .B(DMP_SFG[14]), .Y(n4466) );
NAND2X4TS U2578 ( .A(DMP_SFG[6]), .B(DmP_mant_SFG_SWR[8]), .Y(n5982) );
INVX3TS U2579 ( .A(n3922), .Y(n2902) );
AND2X4TS U2580 ( .A(n1991), .B(n6461), .Y(n2332) );
OAI21X2TS U2581 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n6113), .B0(n6130), .Y(n3149) );
NAND2X4TS U2582 ( .A(n2132), .B(DMP_SFG[17]), .Y(n5595) );
NOR2X4TS U2583 ( .A(n4642), .B(n4918), .Y(n4644) );
NOR2X6TS U2584 ( .A(n3319), .B(DMP_SFG[33]), .Y(n5175) );
NAND2X2TS U2585 ( .A(n3352), .B(DMP_SFG[16]), .Y(n5620) );
NOR2X6TS U2586 ( .A(DmP_mant_SFG_SWR[14]), .B(DMP_SFG[12]), .Y(n4544) );
NAND2X2TS U2587 ( .A(n2444), .B(DmP_mant_SFG_SWR[17]), .Y(n4470) );
NAND2X2TS U2588 ( .A(n3280), .B(intDY_EWSW[28]), .Y(n3540) );
CLKAND2X2TS U2589 ( .A(n3342), .B(intDY_EWSW[62]), .Y(n3637) );
NOR2X4TS U2590 ( .A(n4738), .B(n4433), .Y(n4434) );
INVX2TS U2591 ( .A(n4494), .Y(n2771) );
NAND2X2TS U2592 ( .A(n2841), .B(n6464), .Y(n3941) );
NAND2X2TS U2593 ( .A(n2841), .B(n6513), .Y(n3921) );
NAND2X4TS U2594 ( .A(n2274), .B(n4067), .Y(n3128) );
NAND2X6TS U2595 ( .A(n2996), .B(n2567), .Y(n2850) );
CLKBUFX3TS U2596 ( .A(n5247), .Y(n6353) );
AND2X4TS U2597 ( .A(n2461), .B(add_x_6_A_5_), .Y(n3238) );
NOR2X6TS U2598 ( .A(n4836), .B(n4436), .Y(n4914) );
NOR2X2TS U2599 ( .A(n4000), .B(n2212), .Y(n2931) );
INVX12TS U2600 ( .A(n5854), .Y(n5890) );
NOR2X6TS U2601 ( .A(n3013), .B(n5475), .Y(n4523) );
OAI21X2TS U2602 ( .A0(n3501), .A1(n3500), .B0(n3499), .Y(n3506) );
CLKAND2X4TS U2603 ( .A(n3313), .B(DMP_SFG[26]), .Y(n3067) );
NAND2X4TS U2604 ( .A(n3599), .B(n3553), .Y(n3602) );
NOR2X4TS U2605 ( .A(n2040), .B(n2034), .Y(n3517) );
INVX4TS U2606 ( .A(n3095), .Y(n3335) );
NOR2X4TS U2607 ( .A(n3516), .B(n2033), .Y(n2032) );
OR2X4TS U2608 ( .A(n3996), .B(n2212), .Y(n1943) );
OR2X6TS U2609 ( .A(n4001), .B(n2190), .Y(n3445) );
INVX2TS U2610 ( .A(n2099), .Y(n2252) );
NAND2X1TS U2611 ( .A(n3265), .B(n2427), .Y(n3499) );
BUFX8TS U2612 ( .A(n6394), .Y(n5660) );
INVX2TS U2613 ( .A(n2436), .Y(n3070) );
INVX2TS U2614 ( .A(n2432), .Y(n2433) );
BUFX8TS U2615 ( .A(n3180), .Y(n2110) );
NOR2X4TS U2616 ( .A(n3347), .B(DMP_SFG[28]), .Y(n4436) );
NOR2X6TS U2617 ( .A(n3996), .B(n2228), .Y(n2934) );
OAI2BB1X2TS U2618 ( .A0N(n2438), .A1N(n3263), .B0(n2791), .Y(n2790) );
NAND2X4TS U2619 ( .A(add_x_6_B_4_), .B(add_x_6_A_4_), .Y(n5956) );
OR2X4TS U2620 ( .A(n4001), .B(n2229), .Y(n3443) );
BUFX8TS U2621 ( .A(n2261), .Y(n2260) );
INVX2TS U2622 ( .A(n2064), .Y(n2063) );
NAND2X4TS U2623 ( .A(n6332), .B(DMP_SFG[4]), .Y(n5452) );
NOR2X4TS U2624 ( .A(n4432), .B(DMP_SFG[25]), .Y(n4738) );
NAND2X2TS U2625 ( .A(sub_x_5_n634), .B(DMP_SFG[8]), .Y(n5476) );
NAND2X4TS U2626 ( .A(DMP_SFG[25]), .B(n4432), .Y(n4773) );
NOR2X4TS U2627 ( .A(n3277), .B(n2437), .Y(n3535) );
OR2X4TS U2628 ( .A(n6589), .B(n2196), .Y(n2417) );
OR2X4TS U2629 ( .A(n4000), .B(n2225), .Y(n3449) );
NAND2X2TS U2630 ( .A(n3270), .B(intDY_EWSW[49]), .Y(n3606) );
NAND2X2TS U2631 ( .A(n3330), .B(intDY_EWSW[55]), .Y(n3618) );
NOR2X4TS U2632 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[37]), .Y(
n4910) );
INVX4TS U2633 ( .A(n5477), .Y(n3013) );
NAND2X2TS U2634 ( .A(n3354), .B(DMP_SFG[6]), .Y(n4393) );
BUFX12TS U2635 ( .A(n4068), .Y(n2274) );
NOR2X6TS U2636 ( .A(n3306), .B(intDY_EWSW[18]), .Y(n2034) );
NOR2X6TS U2637 ( .A(n3552), .B(n3594), .Y(n3553) );
NOR2X4TS U2638 ( .A(n6297), .B(DMP_SFG[30]), .Y(n4642) );
NOR2X4TS U2639 ( .A(n2674), .B(n3590), .Y(n3551) );
OR2X4TS U2640 ( .A(n2275), .B(DMP_exp_NRM2_EW[0]), .Y(n2350) );
INVX4TS U2641 ( .A(n3636), .Y(n2638) );
OR2X6TS U2642 ( .A(n3282), .B(intDY_EWSW[60]), .Y(n2637) );
BUFX12TS U2643 ( .A(n6390), .Y(n4001) );
NOR2X4TS U2644 ( .A(n3334), .B(n2462), .Y(n3495) );
NOR2X4TS U2645 ( .A(n3265), .B(n2427), .Y(n3501) );
NAND2BX2TS U2646 ( .AN(ADD_OVRFLW_NRM2), .B(DMP_exp_NRM2_EW[0]), .Y(n4073)
);
BUFX6TS U2647 ( .A(n2257), .Y(n2099) );
NAND2X4TS U2648 ( .A(n3305), .B(n2154), .Y(n3582) );
OR2X4TS U2649 ( .A(n3342), .B(intDY_EWSW[62]), .Y(n3638) );
NOR2X6TS U2650 ( .A(n3632), .B(n2642), .Y(n3634) );
NAND2X2TS U2651 ( .A(n3291), .B(n2139), .Y(n3592) );
NOR2X6TS U2652 ( .A(n2641), .B(n3629), .Y(n2640) );
NAND2X2TS U2653 ( .A(n3298), .B(intDY_EWSW[35]), .Y(n3574) );
NAND2X2TS U2654 ( .A(n3289), .B(n2431), .Y(n3490) );
CLKINVX6TS U2655 ( .A(DmP_mant_SFG_SWR[27]), .Y(n4432) );
NOR2X4TS U2656 ( .A(n3308), .B(intDY_EWSW[40]), .Y(n2674) );
OR2X4TS U2657 ( .A(intDX_EWSW[5]), .B(n1921), .Y(n3478) );
NOR2X6TS U2658 ( .A(n2594), .B(n2596), .Y(n2636) );
INVX8TS U2659 ( .A(n2795), .Y(n2794) );
CLKINVX3TS U2660 ( .A(n2294), .Y(n2122) );
INVX8TS U2661 ( .A(n3923), .Y(n2900) );
INVX2TS U2662 ( .A(n1952), .Y(n1916) );
NAND2X4TS U2663 ( .A(n2420), .B(n6458), .Y(n3925) );
NAND2X2TS U2664 ( .A(n2113), .B(n6132), .Y(n2112) );
NOR2X2TS U2665 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[10]), .Y(n3371) );
NOR2X6TS U2666 ( .A(n3279), .B(intDY_EWSW[58]), .Y(n2642) );
AND2X4TS U2667 ( .A(DMP_exp_NRM2_EW[1]), .B(n6201), .Y(n2365) );
NOR2X6TS U2668 ( .A(n3272), .B(intDY_EWSW[51]), .Y(n3611) );
INVX2TS U2669 ( .A(n2137), .Y(n2753) );
AND2X4TS U2670 ( .A(n6197), .B(n6137), .Y(n3374) );
INVX4TS U2671 ( .A(n6120), .Y(n3461) );
NOR2X4TS U2672 ( .A(Raw_mant_NRM_SWR[39]), .B(n2429), .Y(n2595) );
INVX2TS U2673 ( .A(n2286), .Y(n2287) );
CLKINVX6TS U2674 ( .A(n2285), .Y(n4362) );
INVX3TS U2675 ( .A(Raw_mant_NRM_SWR[13]), .Y(n1993) );
XNOR2X4TS U2676 ( .A(n4458), .B(n4457), .Y(n4459) );
INVX16TS U2677 ( .A(n2991), .Y(n2403) );
OAI2BB1X4TS U2678 ( .A0N(n5280), .A1N(n5530), .B0(n5529), .Y(n1256) );
OAI2BB1X4TS U2679 ( .A0N(n5928), .A1N(n4461), .B0(n4460), .Y(n1258) );
XNOR2X2TS U2680 ( .A(n4456), .B(n4455), .Y(n4461) );
NAND3X6TS U2681 ( .A(n4123), .B(n4124), .C(n4122), .Y(n1302) );
NAND2X4TS U2682 ( .A(n2403), .B(intDX_EWSW[48]), .Y(n4124) );
AOI22X2TS U2683 ( .A0(n4537), .A1(n5527), .B0(Raw_mant_NRM_SWR[12]), .B1(
n5030), .Y(n4538) );
NAND2X2TS U2684 ( .A(n4609), .B(n2498), .Y(n4611) );
OR2X4TS U2685 ( .A(n2675), .B(n1946), .Y(n2890) );
OAI2BB1X4TS U2686 ( .A0N(n5996), .A1N(n5075), .B0(n5074), .Y(n1245) );
OAI21X2TS U2687 ( .A0(n5059), .A1(n5058), .B0(n5057), .Y(n5060) );
NAND2X4TS U2688 ( .A(n4879), .B(n5856), .Y(n2657) );
NAND2X2TS U2689 ( .A(n4307), .B(intDY_EWSW[5]), .Y(n4243) );
OAI2BB1X4TS U2690 ( .A0N(n5928), .A1N(n4766), .B0(n4765), .Y(n1236) );
XNOR2X2TS U2691 ( .A(n5239), .B(n4755), .Y(n4766) );
NAND3X6TS U2692 ( .A(n3758), .B(n3759), .C(n3757), .Y(n1630) );
NAND2X4TS U2693 ( .A(n3775), .B(n2139), .Y(n3759) );
NAND2X4TS U2694 ( .A(n4306), .B(intDX_EWSW[18]), .Y(n4263) );
NAND2X4TS U2695 ( .A(n2992), .B(intDX_EWSW[9]), .Y(n4232) );
NAND3X4TS U2696 ( .A(n3807), .B(n3808), .C(n3806), .Y(n1664) );
NAND2X4TS U2697 ( .A(n2012), .B(n2462), .Y(n3808) );
NAND3X6TS U2698 ( .A(n3685), .B(n3686), .C(n3684), .Y(n1675) );
NAND2X4TS U2699 ( .A(n4306), .B(n2407), .Y(n3686) );
NAND3X6TS U2700 ( .A(n3718), .B(n3719), .C(n3717), .Y(n1671) );
NAND2X4TS U2701 ( .A(n1138), .B(n1559), .Y(n6032) );
OR2X4TS U2702 ( .A(n4000), .B(n2201), .Y(n3417) );
NOR2X4TS U2703 ( .A(n4000), .B(n2215), .Y(n2064) );
OR2X8TS U2704 ( .A(n4000), .B(n2231), .Y(n3444) );
NAND4BX4TS U2705 ( .AN(n5726), .B(n5725), .C(n5724), .D(n5723), .Y(n5735) );
NAND2BX4TS U2706 ( .AN(n2909), .B(n5513), .Y(n1126) );
NAND4X4TS U2707 ( .A(n5576), .B(n5575), .C(n5574), .D(n5573), .Y(n5681) );
NAND3X4TS U2708 ( .A(n5504), .B(n5503), .C(n5502), .Y(n1131) );
MX2X4TS U2709 ( .A(n6013), .B(Shift_amount_SHT1_EWR[5]), .S0(n2555), .Y(
n1687) );
NAND2X6TS U2710 ( .A(n3035), .B(n3034), .Y(n6943) );
AOI2BB1X2TS U2711 ( .A0N(n2494), .A1N(n5668), .B0(n3910), .Y(n2125) );
NAND2X6TS U2712 ( .A(n2939), .B(n5490), .Y(n6936) );
NOR4X2TS U2713 ( .A(n5396), .B(n5394), .C(n5395), .D(n5393), .Y(n5435) );
NAND4X2TS U2714 ( .A(n5388), .B(n5387), .C(n5386), .D(n5385), .Y(n5394) );
INVX16TS U2715 ( .A(n6720), .Y(n6719) );
NOR4X2TS U2716 ( .A(n5376), .B(n5375), .C(n5374), .D(n5373), .Y(n5436) );
NAND4X2TS U2717 ( .A(n5368), .B(n5367), .C(n5366), .D(n5365), .Y(n5374) );
OAI2BB1X4TS U2718 ( .A0N(n2756), .A1N(n6945), .B0(n5677), .Y(n1133) );
NAND3X6TS U2719 ( .A(n5651), .B(n5650), .C(n5649), .Y(n6945) );
NAND2X4TS U2720 ( .A(n2973), .B(n2972), .Y(n1140) );
NAND2X6TS U2721 ( .A(n2066), .B(n2065), .Y(n1150) );
NAND3X8TS U2722 ( .A(n5657), .B(n5656), .C(n5655), .Y(n6946) );
MXI2X8TS U2723 ( .A(n6204), .B(n6335), .S0(n2514), .Y(n1129) );
AND3X8TS U2724 ( .A(n5206), .B(n5656), .C(n5205), .Y(n6204) );
NOR2X2TS U2725 ( .A(n1574), .B(n1143), .Y(n6050) );
OAI2BB1X4TS U2726 ( .A0N(n5928), .A1N(n4753), .B0(n4752), .Y(n1241) );
AOI21X2TS U2727 ( .A0(n4621), .A1(n5517), .B0(n4541), .Y(n4542) );
INVX8TS U2728 ( .A(n5514), .Y(n4621) );
NAND2X4TS U2729 ( .A(n5543), .B(n5713), .Y(n5547) );
NAND4X6TS U2730 ( .A(n3436), .B(n3438), .C(n3437), .D(n3439), .Y(n1720) );
NAND2X8TS U2731 ( .A(n2883), .B(n2882), .Y(n1111) );
NAND2X8TS U2732 ( .A(n4561), .B(n2073), .Y(n2072) );
NOR4X2TS U2733 ( .A(n5432), .B(n5431), .C(n5430), .D(n5429), .Y(n5433) );
NAND4X2TS U2734 ( .A(n5420), .B(n5419), .C(n5418), .D(n5417), .Y(n5432) );
OAI21X2TS U2735 ( .A0(n6987), .A1(n5732), .B0(n3041), .Y(n1107) );
INVX2TS U2736 ( .A(n6867), .Y(n6868) );
OAI22X2TS U2737 ( .A0(n5712), .A1(n5537), .B0(n2494), .B1(n5711), .Y(n5542)
);
NOR2X2TS U2738 ( .A(n4312), .B(n2494), .Y(n2709) );
NAND2X4TS U2739 ( .A(n2910), .B(n5512), .Y(n2909) );
NAND2X2TS U2740 ( .A(n6943), .B(n2558), .Y(n2910) );
AOI21X4TS U2741 ( .A0(n5239), .A1(n4672), .B0(n4671), .Y(n4675) );
OAI2BB1X4TS U2742 ( .A0N(n5928), .A1N(n4451), .B0(n4450), .Y(n1238) );
XOR2X2TS U2743 ( .A(n4443), .B(n4442), .Y(n4451) );
NAND2X2TS U2744 ( .A(n5715), .B(n1971), .Y(n2989) );
NAND2X2TS U2745 ( .A(n5715), .B(n2498), .Y(n2982) );
NAND2X2TS U2746 ( .A(n5505), .B(n1738), .Y(n3965) );
NAND3X6TS U2747 ( .A(n3205), .B(n5215), .C(n3207), .Y(n3204) );
INVX6TS U2748 ( .A(n5474), .Y(n3015) );
NOR2X6TS U2749 ( .A(n1963), .B(n2006), .Y(n2005) );
NAND2X8TS U2750 ( .A(n2358), .B(n2875), .Y(n5536) );
OR2X4TS U2751 ( .A(n4033), .B(n2198), .Y(n4035) );
AOI2BB2X4TS U2752 ( .B0(n6579), .B1(n6578), .A0N(n6577), .A1N(n2198), .Y(
n3423) );
NAND2X8TS U2753 ( .A(n2981), .B(n3462), .Y(n5722) );
NAND3X6TS U2754 ( .A(n3780), .B(n3781), .C(n3779), .Y(n1643) );
OR2X4TS U2755 ( .A(n4033), .B(n2195), .Y(n3985) );
NAND2X2TS U2756 ( .A(n6942), .B(n5557), .Y(n5513) );
XOR2X4TS U2757 ( .A(n5242), .B(n5241), .Y(N87) );
BUFX20TS U2758 ( .A(n6413), .Y(n2420) );
NOR2X2TS U2759 ( .A(n1577), .B(n1144), .Y(n6055) );
NAND3X6TS U2760 ( .A(n4113), .B(n4114), .C(n4112), .Y(n1306) );
NAND2X4TS U2761 ( .A(n2813), .B(n1988), .Y(n4113) );
NAND2X6TS U2762 ( .A(n2084), .B(n5202), .Y(n1113) );
NAND2X4TS U2763 ( .A(sub_x_5_B_34_), .B(n1511), .Y(n6027) );
BUFX20TS U2764 ( .A(n6400), .Y(n2841) );
INVX6TS U2765 ( .A(n2468), .Y(n4569) );
INVX16TS U2766 ( .A(n6720), .Y(n6717) );
AOI21X4TS U2767 ( .A0(n2609), .A1(n5588), .B0(n5587), .Y(n5590) );
NAND2X2TS U2768 ( .A(n2848), .B(intDX_EWSW[13]), .Y(n3795) );
NAND2X4TS U2769 ( .A(n2848), .B(n2149), .Y(n4116) );
OAI21X2TS U2770 ( .A0(n6964), .A1(n2540), .B0(n2893), .Y(n1116) );
NAND2X4TS U2771 ( .A(n2715), .B(n4023), .Y(n2714) );
NAND2X6TS U2772 ( .A(n4640), .B(n1970), .Y(n2690) );
XNOR2X4TS U2773 ( .A(n3260), .B(n4723), .Y(n4724) );
NAND2X6TS U2774 ( .A(n3088), .B(n2360), .Y(n3084) );
NAND4X8TS U2775 ( .A(n3427), .B(n3424), .C(n3425), .D(n3426), .Y(n1746) );
OAI2BB1X2TS U2776 ( .A0N(n5928), .A1N(n4413), .B0(n4412), .Y(n1253) );
NOR2X4TS U2777 ( .A(n3352), .B(DMP_SFG[16]), .Y(n5619) );
AOI21X4TS U2778 ( .A0(n4161), .A1(n2609), .B0(n4160), .Y(n4163) );
AOI21X4TS U2779 ( .A0(n5618), .A1(n4772), .B0(n4771), .Y(n4776) );
NOR2X8TS U2780 ( .A(n2901), .B(n2900), .Y(n2899) );
NOR2X8TS U2781 ( .A(n2356), .B(n2728), .Y(n2727) );
NAND3X8TS U2782 ( .A(n2736), .B(n2730), .C(n2729), .Y(n2728) );
NOR2X8TS U2783 ( .A(n1963), .B(n2775), .Y(n5535) );
NAND2X4TS U2784 ( .A(n1991), .B(n6446), .Y(n4002) );
NAND2X4TS U2785 ( .A(n1991), .B(n6507), .Y(n3430) );
NAND2X4TS U2786 ( .A(n4245), .B(n1983), .Y(n3832) );
AND4X8TS U2787 ( .A(n3002), .B(n3005), .C(n3003), .D(n3006), .Y(n2346) );
NAND2X6TS U2788 ( .A(n3176), .B(n2367), .Y(n3174) );
CLKINVX6TS U2789 ( .A(n2862), .Y(n3176) );
NAND3X4TS U2790 ( .A(n4197), .B(n4198), .C(n4196), .Y(n1322) );
NAND3X2TS U2791 ( .A(n4181), .B(n4182), .C(n4180), .Y(n1398) );
NAND2X8TS U2792 ( .A(n2076), .B(n3884), .Y(n4559) );
OR2X6TS U2793 ( .A(n2659), .B(n2658), .Y(n2654) );
NAND3X2TS U2794 ( .A(n4201), .B(n4200), .C(n4199), .Y(n1378) );
XOR2X2TS U2795 ( .A(n5752), .B(n5751), .Y(n5753) );
AOI21X2TS U2796 ( .A0(n5988), .A1(n5750), .B0(n5749), .Y(n5752) );
NAND2X2TS U2797 ( .A(n2420), .B(n6497), .Y(n4344) );
NAND3X8TS U2798 ( .A(n2353), .B(n3939), .C(n3940), .Y(n1738) );
OAI21X2TS U2799 ( .A0(n5746), .A1(n4405), .B0(n4404), .Y(n4408) );
XOR2X4TS U2800 ( .A(n5637), .B(DmP_mant_SFG_SWR[54]), .Y(n5640) );
NAND3X6TS U2801 ( .A(n3848), .B(n3849), .C(n3847), .Y(n1668) );
NAND2X8TS U2802 ( .A(n4670), .B(n4954), .Y(n5235) );
NAND2X8TS U2803 ( .A(n2932), .B(n2927), .Y(n5654) );
NAND2X4TS U2804 ( .A(n2648), .B(n2462), .Y(n4234) );
NAND2X4TS U2805 ( .A(n2648), .B(intDX_EWSW[7]), .Y(n3848) );
NAND2X4TS U2806 ( .A(n2648), .B(intDX_EWSW[4]), .Y(n3718) );
NAND2X4TS U2807 ( .A(n2648), .B(intDY_EWSW[39]), .Y(n4278) );
NAND2X4TS U2808 ( .A(n2648), .B(intDX_EWSW[6]), .Y(n3694) );
NAND2X4TS U2809 ( .A(n2648), .B(n2438), .Y(n4184) );
NAND2X4TS U2810 ( .A(n2648), .B(intDY_EWSW[10]), .Y(n4200) );
AND2X6TS U2811 ( .A(n1736), .B(n2479), .Y(n2345) );
OAI21X2TS U2812 ( .A0(n5236), .A1(n5218), .B0(n5217), .Y(n5219) );
NOR2X2TS U2813 ( .A(n1532), .B(n1129), .Y(n6054) );
NAND2X8TS U2814 ( .A(n3947), .B(n3454), .Y(n3455) );
NAND2X4TS U2815 ( .A(n2648), .B(intDX_EWSW[49]), .Y(n3831) );
NAND3X6TS U2816 ( .A(n4116), .B(n4117), .C(n4115), .Y(n1310) );
NAND3X6TS U2817 ( .A(n3740), .B(n3741), .C(n3739), .Y(n1624) );
NAND3X6TS U2818 ( .A(n3700), .B(n3701), .C(n3699), .Y(n1646) );
NAND3X6TS U2819 ( .A(n3676), .B(n3677), .C(n3675), .Y(n1289) );
NAND2X2TS U2820 ( .A(n4388), .B(n1737), .Y(n4008) );
NAND2X2TS U2821 ( .A(n2490), .B(n1737), .Y(n4317) );
NAND4BX4TS U2822 ( .AN(n2348), .B(n3053), .C(n3062), .D(n3051), .Y(n1233) );
AND2X8TS U2823 ( .A(n3063), .B(n3055), .Y(n2348) );
NAND3X2TS U2824 ( .A(n5353), .B(n5352), .C(n5351), .Y(n1618) );
AOI2BB2X2TS U2825 ( .B0(n2502), .B1(n1707), .A0N(n5712), .A1N(n5668), .Y(
n5671) );
NAND3X2TS U2826 ( .A(n4214), .B(n4213), .C(n4212), .Y(n1382) );
NAND2X6TS U2827 ( .A(n2898), .B(n2896), .Y(n2895) );
NAND3X6TS U2828 ( .A(n5441), .B(n5440), .C(n5439), .Y(n1610) );
NAND2X2TS U2829 ( .A(n1731), .B(n4388), .Y(n2586) );
NOR2X6TS U2830 ( .A(n2931), .B(n2930), .Y(n2929) );
INVX12TS U2831 ( .A(n4444), .Y(n5625) );
NAND2X2TS U2832 ( .A(n5561), .B(n1751), .Y(n3917) );
XOR2X2TS U2833 ( .A(n4820), .B(n4819), .Y(n4831) );
OR2X4TS U2834 ( .A(n6397), .B(n2200), .Y(n3408) );
AOI2BB2X4TS U2835 ( .B0(n6556), .B1(n6555), .A0N(n2257), .A1N(n2195), .Y(
n3411) );
INVX2TS U2836 ( .A(n6857), .Y(n6811) );
AOI2BB2X4TS U2837 ( .B0(n6528), .B1(n6527), .A0N(n6526), .A1N(n2200), .Y(
n3930) );
NAND3X4TS U2838 ( .A(n3652), .B(n3653), .C(n3651), .Y(n1623) );
NAND2X4TS U2839 ( .A(n1991), .B(n6489), .Y(n3447) );
BUFX20TS U2840 ( .A(n6405), .Y(n1991) );
NAND2X2TS U2841 ( .A(n2505), .B(intDX_EWSW[27]), .Y(n4285) );
NAND2X2TS U2842 ( .A(n2505), .B(n2154), .Y(n3802) );
NAND2X4TS U2843 ( .A(n2505), .B(intDX_EWSW[0]), .Y(n4182) );
NAND2X4TS U2844 ( .A(n3775), .B(intDY_EWSW[26]), .Y(n3710) );
CLKINVX12TS U2845 ( .A(n1992), .Y(n3183) );
NOR2X8TS U2846 ( .A(n2600), .B(n2598), .Y(n2597) );
INVX4TS U2847 ( .A(n4371), .Y(n2600) );
AOI21X2TS U2848 ( .A0(n5980), .A1(n5450), .B0(n2133), .Y(n5455) );
CLKINVX12TS U2849 ( .A(n2133), .Y(n5449) );
OR2X8TS U2850 ( .A(n6397), .B(n2179), .Y(n3465) );
INVX16TS U2851 ( .A(n2439), .Y(n4444) );
MX2X6TS U2852 ( .A(n5578), .B(DmP_mant_SFG_SWR[17]), .S0(n2489), .Y(
sub_x_5_B_17_) );
NAND2X4TS U2853 ( .A(n2012), .B(n2431), .Y(n3799) );
NAND3X6TS U2854 ( .A(n4248), .B(n4247), .C(n4246), .Y(n1384) );
NAND2X4TS U2855 ( .A(n5348), .B(intDX_EWSW[7]), .Y(n4248) );
AOI2BB2X4TS U2856 ( .B0(n6564), .B1(n6563), .A0N(n6562), .A1N(n2194), .Y(
n3419) );
NOR2X2TS U2857 ( .A(n1598), .B(n1151), .Y(n6049) );
AOI22X2TS U2858 ( .A0(n2497), .A1(n4616), .B0(n4609), .B1(n2513), .Y(n4608)
);
NAND2X4TS U2859 ( .A(n4616), .B(n2513), .Y(n3002) );
AND2X4TS U2860 ( .A(n4616), .B(n5702), .Y(n2334) );
NAND2X6TS U2861 ( .A(n3152), .B(n4352), .Y(n4358) );
NAND3X6TS U2862 ( .A(n4207), .B(n4206), .C(n4205), .Y(n1318) );
NAND2X4TS U2863 ( .A(n2993), .B(intDX_EWSW[40]), .Y(n4207) );
NAND3X6TS U2864 ( .A(n4251), .B(n4250), .C(n4249), .Y(n1346) );
NAND2X4TS U2865 ( .A(n4306), .B(intDX_EWSW[26]), .Y(n4251) );
NAND3X6TS U2866 ( .A(n3778), .B(n3777), .C(n3776), .Y(n1645) );
NAND2X4TS U2867 ( .A(n4121), .B(intDX_EWSW[30]), .Y(n3777) );
XOR2X4TS U2868 ( .A(n5968), .B(n5967), .Y(n5969) );
AOI21X4TS U2869 ( .A0(n5988), .A1(n5965), .B0(n6076), .Y(n5968) );
OAI21X2TS U2870 ( .A0(n5634), .A1(n5580), .B0(n5579), .Y(n5581) );
NAND3X4TS U2871 ( .A(n3671), .B(n3670), .C(n3669), .Y(n1294) );
NAND4X8TS U2872 ( .A(n3435), .B(n3434), .C(n3433), .D(n3432), .Y(n1728) );
OR2X4TS U2873 ( .A(n3179), .B(n4953), .Y(n2419) );
AOI22X2TS U2874 ( .A0(n5993), .A1(n5992), .B0(Raw_mant_NRM_SWR[8]), .B1(
n5991), .Y(n5994) );
XOR2X2TS U2875 ( .A(n5990), .B(n5989), .Y(n5993) );
NAND3X4TS U2876 ( .A(n4225), .B(n4226), .C(n4224), .Y(n1358) );
NAND2X4TS U2877 ( .A(n2403), .B(intDX_EWSW[20]), .Y(n4226) );
NAND2X4TS U2878 ( .A(n2992), .B(intDX_EWSW[14]), .Y(n4195) );
NAND2X4TS U2879 ( .A(n2802), .B(n4906), .Y(n2805) );
NAND2BX4TS U2880 ( .AN(n2991), .B(intDX_EWSW[13]), .Y(n4241) );
NAND2X4TS U2881 ( .A(n4494), .B(n2433), .Y(n3395) );
NAND2X4TS U2882 ( .A(n4306), .B(n2847), .Y(n3849) );
NAND2X4TS U2883 ( .A(n4306), .B(intDX_EWSW[38]), .Y(n4198) );
NAND3X2TS U2884 ( .A(n4587), .B(n4487), .C(n4582), .Y(n3402) );
NAND3X2TS U2885 ( .A(n3695), .B(n3694), .C(n3693), .Y(n1669) );
INVX12TS U2886 ( .A(n2818), .Y(n2820) );
NAND3X6TS U2887 ( .A(n3820), .B(n3821), .C(n3819), .Y(n1636) );
NAND2X4TS U2888 ( .A(n5348), .B(intDY_EWSW[39]), .Y(n3821) );
NAND2X4TS U2889 ( .A(n2993), .B(intDX_EWSW[43]), .Y(n4105) );
NAND3X6TS U2890 ( .A(n3836), .B(n3835), .C(n3834), .Y(n1656) );
NAND2X4TS U2891 ( .A(n4295), .B(intDY_EWSW[19]), .Y(n3836) );
NAND2X4TS U2892 ( .A(n4295), .B(intDX_EWSW[4]), .Y(n4217) );
NAND3X6TS U2893 ( .A(n3715), .B(n3716), .C(n3714), .Y(n1673) );
NAND2X4TS U2894 ( .A(n2993), .B(intDY_EWSW[2]), .Y(n3716) );
INVX16TS U2895 ( .A(n2093), .Y(n2304) );
NOR2X6TS U2896 ( .A(sub_x_5_n608), .B(DMP_SFG[34]), .Y(n5037) );
NAND2X8TS U2897 ( .A(n6415), .B(n6416), .Y(n2652) );
NOR2X6TS U2898 ( .A(n6304), .B(DMP_SFG[37]), .Y(n5112) );
NAND3X8TS U2899 ( .A(n2737), .B(n4027), .C(n2891), .Y(n5488) );
NOR2X8TS U2900 ( .A(n2458), .B(n3008), .Y(n3007) );
INVX16TS U2901 ( .A(n2818), .Y(n2848) );
NOR2X4TS U2902 ( .A(n2456), .B(n2966), .Y(n3232) );
NAND2X4TS U2903 ( .A(n2325), .B(n2518), .Y(n6898) );
NAND2X4TS U2904 ( .A(n5444), .B(intDX_EWSW[1]), .Y(n3703) );
NAND2X4TS U2905 ( .A(n5444), .B(intDX_EWSW[45]), .Y(n3758) );
NAND2X4TS U2906 ( .A(n5444), .B(intDX_EWSW[32]), .Y(n3780) );
NAND2X4TS U2907 ( .A(n5444), .B(intDX_EWSW[2]), .Y(n3715) );
NAND2X4TS U2908 ( .A(n5444), .B(intDX_EWSW[31]), .Y(n3811) );
NAND2X4TS U2909 ( .A(n5444), .B(intDX_EWSW[29]), .Y(n3700) );
NAND2X4TS U2910 ( .A(n5444), .B(intDX_EWSW[51]), .Y(n3740) );
NAND2X4TS U2911 ( .A(n5444), .B(intDX_EWSW[25]), .Y(n3727) );
NAND2X4TS U2912 ( .A(n5444), .B(intDX_EWSW[0]), .Y(n3685) );
NAND2X4TS U2913 ( .A(n5444), .B(intDY_EWSW[6]), .Y(n4222) );
BUFX20TS U2914 ( .A(n2994), .Y(n2505) );
NAND3X8TS U2915 ( .A(n2707), .B(n2710), .C(n2708), .Y(n6969) );
OAI2BB1X2TS U2916 ( .A0N(n5007), .A1N(n2846), .B0(n3314), .Y(n5008) );
NAND2X4TS U2917 ( .A(n5239), .B(n3206), .Y(n3205) );
OAI21X4TS U2918 ( .A0(n5921), .A1(n5918), .B0(n5919), .Y(n5929) );
NAND2X8TS U2919 ( .A(n3358), .B(n2406), .Y(n5921) );
NAND2X6TS U2920 ( .A(n3122), .B(n6721), .Y(n3121) );
BUFX16TS U2921 ( .A(n2552), .Y(n1911) );
NAND2X4TS U2922 ( .A(n6859), .B(n1967), .Y(n6782) );
NAND3X6TS U2923 ( .A(n2393), .B(n2394), .C(n4083), .Y(n1977) );
BUFX6TS U2924 ( .A(Raw_mant_NRM_SWR[47]), .Y(n1912) );
INVX12TS U2925 ( .A(n2295), .Y(n4086) );
NAND2X4TS U2926 ( .A(n2304), .B(n6806), .Y(n3175) );
NAND2X8TS U2927 ( .A(n3175), .B(n3174), .Y(n6815) );
AOI21X4TS U2928 ( .A0(n3591), .A1(n1913), .B0(n2395), .Y(n3603) );
OAI22X4TS U2929 ( .A0(n2398), .A1(n3590), .B0(n2753), .B1(n1916), .Y(n1913)
);
BUFX6TS U2930 ( .A(intDY_EWSW[51]), .Y(n1914) );
NAND2X2TS U2931 ( .A(n2820), .B(intDX_EWSW[16]), .Y(n3752) );
BUFX12TS U2932 ( .A(intDY_EWSW[54]), .Y(n1915) );
BUFX12TS U2933 ( .A(n2994), .Y(n2821) );
OR2X4TS U2934 ( .A(n2818), .B(n1917), .Y(n3676) );
NAND2X4TS U2935 ( .A(Shift_reg_FLAGS_7_6), .B(n3645), .Y(n2013) );
NAND2X4TS U2936 ( .A(n1979), .B(n3647), .Y(n2860) );
NAND3X6TS U2937 ( .A(n4241), .B(n4240), .C(n4239), .Y(n1372) );
NOR2X6TS U2938 ( .A(n3287), .B(n2149), .Y(n3552) );
NAND3X6TS U2939 ( .A(n3712), .B(n3713), .C(n3711), .Y(n1651) );
NAND2X4TS U2940 ( .A(n3023), .B(intDY_EWSW[24]), .Y(n3713) );
NAND2X4TS U2941 ( .A(n4307), .B(intDX_EWSW[24]), .Y(n3712) );
BUFX20TS U2942 ( .A(n4287), .Y(n2649) );
NAND2X8TS U2943 ( .A(n2789), .B(n2788), .Y(n2787) );
INVX12TS U2944 ( .A(n2469), .Y(n1919) );
INVX12TS U2945 ( .A(n2469), .Y(n2470) );
INVX16TS U2946 ( .A(n2385), .Y(n2469) );
BUFX20TS U2947 ( .A(n2649), .Y(n1920) );
BUFX16TS U2948 ( .A(n2822), .Y(n3809) );
BUFX16TS U2949 ( .A(n2649), .Y(n3828) );
INVX2TS U2950 ( .A(n1923), .Y(n1925) );
INVX2TS U2951 ( .A(n1923), .Y(n1926) );
NAND3X4TS U2952 ( .A(n2667), .B(n3154), .C(n2443), .Y(n2393) );
NAND3X4TS U2953 ( .A(n3154), .B(n4086), .C(n2667), .Y(n2097) );
AND4X4TS U2954 ( .A(n2297), .B(exp_rslt_NRM2_EW1[1]), .C(
exp_rslt_NRM2_EW1[0]), .D(n2276), .Y(n3189) );
AOI22X2TS U2955 ( .A0(n2497), .A1(n5669), .B0(n5572), .B1(n5666), .Y(n4378)
);
AOI22X2TS U2956 ( .A0(n2556), .A1(n5669), .B0(n5702), .B1(n5666), .Y(n4607)
);
NOR2X8TS U2957 ( .A(n1502), .B(n1119), .Y(n6029) );
NAND2X8TS U2958 ( .A(n2922), .B(n2917), .Y(n2916) );
MXI2X4TS U2959 ( .A(n6138), .B(n6305), .S0(n2514), .Y(n1401) );
MXI2X4TS U2960 ( .A(n6186), .B(n6319), .S0(n2514), .Y(n1284) );
MXI2X4TS U2961 ( .A(n6185), .B(n6318), .S0(n2514), .Y(n1273) );
INVX16TS U2962 ( .A(n1972), .Y(n2514) );
NAND2X2TS U2963 ( .A(n3846), .B(intDX_EWSW[22]), .Y(n3721) );
AOI21X4TS U2964 ( .A0(n5239), .A1(n5238), .B0(n5237), .Y(n5242) );
NAND2X2TS U2965 ( .A(n2813), .B(intDX_EWSW[62]), .Y(n4382) );
NAND2X2TS U2966 ( .A(n3846), .B(intDX_EWSW[46]), .Y(n3786) );
INVX16TS U2967 ( .A(n1895), .Y(n1937) );
NAND2X2TS U2968 ( .A(n3334), .B(n2462), .Y(n3493) );
NOR2X4TS U2969 ( .A(n3289), .B(n2431), .Y(n3492) );
NAND2X2TS U2970 ( .A(n3517), .B(n2032), .Y(n3509) );
NOR2X4TS U2971 ( .A(n3528), .B(n3509), .Y(n2023) );
NAND2X4TS U2972 ( .A(n3368), .B(n3367), .Y(n3369) );
NAND2X1TS U2973 ( .A(n2320), .B(DMP_SFG[50]), .Y(n5209) );
NOR2X4TS U2974 ( .A(n5046), .B(add_x_6_n163), .Y(n4154) );
NOR2X4TS U2975 ( .A(n1985), .B(DMP_SFG[20]), .Y(n4426) );
NOR2X6TS U2976 ( .A(n5129), .B(n4651), .Y(n5110) );
NOR2X6TS U2977 ( .A(n4660), .B(n5041), .Y(n4661) );
AND2X4TS U2978 ( .A(n1731), .B(n5563), .Y(n2458) );
XNOR2X1TS U2979 ( .A(intDX_EWSW[28]), .B(intDY_EWSW[28]), .Y(n5402) );
XNOR2X1TS U2980 ( .A(intDX_EWSW[37]), .B(intDY_EWSW[37]), .Y(n5368) );
AOI21X1TS U2981 ( .A0(n5016), .A1(n4914), .B0(n4916), .Y(n4437) );
OR2X4TS U2982 ( .A(n6784), .B(n2474), .Y(n3883) );
OAI21X1TS U2983 ( .A0(n5103), .A1(n4985), .B0(n4984), .Y(n4986) );
INVX4TS U2984 ( .A(n2131), .Y(n2132) );
INVX2TS U2985 ( .A(n5022), .Y(n3105) );
INVX2TS U2986 ( .A(n5103), .Y(n2409) );
NAND2X2TS U2987 ( .A(DMP_SFG[31]), .B(DmP_mant_SFG_SWR[33]), .Y(n4762) );
NOR2X2TS U2988 ( .A(n5012), .B(n5018), .Y(n3074) );
AND2X4TS U2989 ( .A(n4388), .B(n1744), .Y(n2298) );
NAND2X2TS U2990 ( .A(n2479), .B(n1746), .Y(n4021) );
NOR3X4TS U2991 ( .A(n2102), .B(n2653), .C(n2654), .Y(n2655) );
NAND2X1TS U2992 ( .A(n4403), .B(n4618), .Y(n4405) );
INVX6TS U2993 ( .A(n5707), .Y(n2497) );
INVX2TS U2994 ( .A(n4063), .Y(n4059) );
NOR3X6TS U2995 ( .A(n2805), .B(n2804), .C(n2809), .Y(n2808) );
NAND2X1TS U2996 ( .A(n5732), .B(DmP_mant_SFG_SWR[37]), .Y(n2999) );
OAI21X2TS U2997 ( .A0(n4784), .A1(n5854), .B0(n5804), .Y(n2313) );
AOI2BB2X2TS U2998 ( .B0(n2502), .B1(n1721), .A0N(n2495), .A1N(n5186), .Y(
n4321) );
AOI21X2TS U2999 ( .A0(n4082), .A1(n3338), .B0(n4081), .Y(n4083) );
BUFX3TS U3000 ( .A(n5280), .Y(n5630) );
NAND2X4TS U3001 ( .A(n6940), .B(n4050), .Y(n5502) );
AOI21X2TS U3002 ( .A0(n5702), .A1(n5705), .B0(n2699), .Y(n2698) );
AND2X2TS U3003 ( .A(n3338), .B(n4076), .Y(n2288) );
AOI22X2TS U3004 ( .A0(n6982), .A1(n2558), .B0(n5756), .B1(
DmP_mant_SFG_SWR[47]), .Y(n5659) );
NAND2X2TS U3005 ( .A(n3845), .B(intDX_EWSW[47]), .Y(n4102) );
CLKBUFX2TS U3006 ( .A(intDY_EWSW[49]), .Y(n1983) );
NAND2X1TS U3007 ( .A(n5764), .B(n2160), .Y(n5766) );
NOR2X2TS U3008 ( .A(n2072), .B(n2721), .Y(n6905) );
OA21X4TS U3009 ( .A0(n4085), .A1(n4079), .B0(n4078), .Y(n1945) );
OR2X8TS U3010 ( .A(n3460), .B(n2381), .Y(n1946) );
NAND2X2TS U3011 ( .A(n2478), .B(n1733), .Y(n1950) );
AND2X8TS U3012 ( .A(n3647), .B(n3646), .Y(n1954) );
OR2X8TS U3013 ( .A(DmP_mant_SFG_SWR[31]), .B(DMP_SFG[29]), .Y(n1956) );
AND2X8TS U3014 ( .A(n3195), .B(n4670), .Y(n1958) );
AND2X8TS U3015 ( .A(n4912), .B(n4910), .Y(n1959) );
OR3X6TS U3016 ( .A(n2772), .B(n2351), .C(n2308), .Y(n1963) );
XNOR2X4TS U3017 ( .A(n1965), .B(n2288), .Y(n2279) );
AND3X8TS U3018 ( .A(n2097), .B(n2852), .C(n2096), .Y(n1965) );
AND2X8TS U3019 ( .A(n2627), .B(Shift_reg_FLAGS_7[0]), .Y(n1966) );
NAND3X2TS U3020 ( .A(n3786), .B(n3787), .C(n3785), .Y(n1629) );
NAND2X2TS U3021 ( .A(n3052), .B(n3056), .Y(n3051) );
NAND2X4TS U3022 ( .A(n3890), .B(n2739), .Y(n6940) );
NAND2X2TS U3023 ( .A(n2959), .B(n5493), .Y(n2958) );
NAND3X6TS U3024 ( .A(n2888), .B(n2890), .C(n2109), .Y(n2106) );
NAND2X4TS U3025 ( .A(n4559), .B(n5544), .Y(n2074) );
NAND2X2TS U3026 ( .A(n6943), .B(n5557), .Y(n3033) );
NAND2X4TS U3027 ( .A(n2785), .B(n3213), .Y(n3211) );
INVX2TS U3028 ( .A(n4056), .Y(n2668) );
NAND2X4TS U3029 ( .A(n3164), .B(n4579), .Y(n3233) );
NAND2X2TS U3030 ( .A(n5654), .B(n5653), .Y(n5655) );
NOR2X2TS U3031 ( .A(n2316), .B(n5472), .Y(n6867) );
NOR2X2TS U3032 ( .A(n3328), .B(n5473), .Y(n6860) );
INVX3TS U3033 ( .A(n5497), .Y(n4565) );
NOR2X2TS U3034 ( .A(n3299), .B(n5822), .Y(n6865) );
NOR2X2TS U3035 ( .A(n3339), .B(n5826), .Y(n6857) );
AOI21X2TS U3036 ( .A0(n1969), .A1(n2750), .B0(n5910), .Y(n6814) );
NOR2X4TS U3037 ( .A(n2052), .B(n2051), .Y(n2050) );
NAND2X6TS U3038 ( .A(n2760), .B(n2759), .Y(n5545) );
OAI2BB1X1TS U3039 ( .A0N(n5996), .A1N(n5935), .B0(n5934), .Y(n1266) );
CLKMX2X2TS U3040 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n5906), .Y(n1798)
);
CLKMX2X2TS U3041 ( .A(Data_Y[38]), .B(n2154), .S0(n5899), .Y(n1780) );
CLKMX2X2TS U3042 ( .A(Data_Y[42]), .B(intDY_EWSW[42]), .S0(n5899), .Y(n1776)
);
INVX3TS U3043 ( .A(n4046), .Y(n2047) );
INVX12TS U3044 ( .A(n6720), .Y(n6718) );
CLKMX2X2TS U3045 ( .A(Data_Y[18]), .B(intDY_EWSW[18]), .S0(n5906), .Y(n1800)
);
MXI2X1TS U3046 ( .A(n6139), .B(n6307), .S0(n2607), .Y(n1411) );
MXI2X1TS U3047 ( .A(n6140), .B(n6308), .S0(n2607), .Y(n1416) );
XNOR2X2TS U3048 ( .A(n6012), .B(n6011), .Y(n6013) );
NOR2X6TS U3049 ( .A(n4902), .B(n4364), .Y(n3182) );
INVX16TS U3050 ( .A(n5804), .Y(n5329) );
INVX12TS U3051 ( .A(n5556), .Y(n2558) );
INVX2TS U3052 ( .A(n5035), .Y(n3059) );
NAND2X1TS U3053 ( .A(n4211), .B(DMP_EXP_EWSW[2]), .Y(n3714) );
NAND2X1TS U3054 ( .A(n3732), .B(DMP_EXP_EWSW[29]), .Y(n3699) );
NAND2X1TS U3055 ( .A(n4296), .B(DmP_EXP_EWSW[46]), .Y(n4112) );
NAND2X1TS U3056 ( .A(n4211), .B(DMP_EXP_EWSW[1]), .Y(n3702) );
NAND2X1TS U3057 ( .A(n4296), .B(DmP_EXP_EWSW[35]), .Y(n3853) );
NAND2X1TS U3058 ( .A(n3841), .B(DMP_EXP_EWSW[31]), .Y(n3810) );
NAND2X1TS U3059 ( .A(n3841), .B(DMP_EXP_EWSW[32]), .Y(n3779) );
NOR2X6TS U3060 ( .A(n2869), .B(n2868), .Y(n2867) );
NAND2X1TS U3061 ( .A(n5888), .B(DmP_mant_SFG_SWR[50]), .Y(n2911) );
BUFX12TS U3062 ( .A(n4050), .Y(n5557) );
BUFX8TS U3063 ( .A(n5888), .Y(n2607) );
NAND2X1TS U3064 ( .A(n5445), .B(DmP_EXP_EWSW[56]), .Y(n3672) );
NAND2X1TS U3065 ( .A(n4211), .B(DMP_EXP_EWSW[0]), .Y(n3684) );
NAND2X1TS U3066 ( .A(n5445), .B(DmP_EXP_EWSW[57]), .Y(n3675) );
BUFX4TS U3067 ( .A(n2713), .Y(n4372) );
NAND2X1TS U3068 ( .A(n3732), .B(DMP_EXP_EWSW[26]), .Y(n3708) );
NAND2X1TS U3069 ( .A(n3732), .B(DMP_EXP_EWSW[25]), .Y(n3726) );
BUFX8TS U3070 ( .A(n4050), .Y(n2766) );
NAND2X1TS U3071 ( .A(n3732), .B(DMP_EXP_EWSW[24]), .Y(n3711) );
BUFX8TS U3072 ( .A(n1974), .Y(n5878) );
INVX2TS U3073 ( .A(n2266), .Y(n3906) );
NAND2X4TS U3074 ( .A(n3935), .B(n3934), .Y(n2868) );
INVX2TS U3075 ( .A(n5091), .Y(n3214) );
NAND2X6TS U3076 ( .A(n3568), .B(n3622), .Y(n3625) );
NOR2X4TS U3077 ( .A(n4909), .B(n2771), .Y(n2770) );
BUFX20TS U3078 ( .A(n4015), .Y(n5888) );
NAND2X6TS U3079 ( .A(n1956), .B(n2363), .Y(n4756) );
NAND4X6TS U3080 ( .A(n3902), .B(n3901), .C(n3900), .D(n3899), .Y(n1715) );
INVX16TS U3081 ( .A(n5851), .Y(n4869) );
BUFX12TS U3082 ( .A(n5851), .Y(n2548) );
AND2X2TS U3083 ( .A(n5923), .B(add_x_6_n536), .Y(n3361) );
NOR2X6TS U3084 ( .A(n3407), .B(n3406), .Y(n5882) );
NAND2X2TS U3085 ( .A(sub_x_1_n32), .B(DMP_EXP_EWSW[54]), .Y(n5997) );
INVX4TS U3086 ( .A(n2248), .Y(n2547) );
INVX16TS U3087 ( .A(left_right_SHT2), .Y(n2517) );
NOR2X8TS U3088 ( .A(n2272), .B(n2188), .Y(n6996) );
BUFX6TS U3089 ( .A(n6267), .Y(n5462) );
INVX16TS U3090 ( .A(Shift_reg_FLAGS_7[1]), .Y(n5853) );
INVX16TS U3091 ( .A(n7014), .Y(n5854) );
NAND2X4TS U3092 ( .A(n3309), .B(intDY_EWSW[8]), .Y(n3491) );
NAND2X4TS U3093 ( .A(n6815), .B(n1967), .Y(n6808) );
NAND2X4TS U3094 ( .A(n2657), .B(n2656), .Y(n1209) );
INVX16TS U3095 ( .A(n2304), .Y(n4953) );
NAND3X2TS U3096 ( .A(n3730), .B(n3731), .C(n3729), .Y(n1672) );
NAND2X4TS U3097 ( .A(n2848), .B(n2139), .Y(n4110) );
NAND2X6TS U3098 ( .A(n2985), .B(n1972), .Y(n2984) );
NAND2X4TS U3099 ( .A(n3146), .B(n5992), .Y(n1999) );
NAND3X4TS U3100 ( .A(n2740), .B(n5501), .C(n2738), .Y(n1127) );
NAND2X4TS U3101 ( .A(n2072), .B(n2071), .Y(n2066) );
NOR2X4TS U3102 ( .A(n2779), .B(n2774), .Y(n2773) );
INVX3TS U3103 ( .A(n3063), .Y(n3052) );
INVX4TS U3104 ( .A(n3099), .Y(exp_rslt_NRM2_EW1[8]) );
NAND2X2TS U3105 ( .A(n2767), .B(n5659), .Y(n1109) );
NOR2X4TS U3106 ( .A(n5533), .B(n6194), .Y(n2774) );
NAND2X2TS U3107 ( .A(n4877), .B(n5992), .Y(n4878) );
INVX2TS U3108 ( .A(n2104), .Y(n2107) );
NAND2X6TS U3109 ( .A(n2106), .B(n1972), .Y(n2105) );
NAND2X4TS U3110 ( .A(n4907), .B(n4913), .Y(n2779) );
NAND2X6TS U3111 ( .A(n5689), .B(n4499), .Y(n2585) );
NOR2X4TS U3112 ( .A(n2069), .B(n2068), .Y(n2067) );
NAND2X4TS U3113 ( .A(n3211), .B(n3209), .Y(n3208) );
NAND2X4TS U3114 ( .A(n2042), .B(n2048), .Y(n2041) );
NAND2X4TS U3115 ( .A(n5335), .B(n5532), .Y(n6834) );
NAND2X4TS U3116 ( .A(n2961), .B(n2960), .Y(n6937) );
NAND2X6TS U3117 ( .A(n2591), .B(n5716), .Y(n5193) );
NAND2X6TS U3118 ( .A(n5543), .B(n5727), .Y(n2616) );
NAND4X4TS U3119 ( .A(n2125), .B(n2123), .C(n2884), .D(n3918), .Y(n6975) );
INVX2TS U3120 ( .A(n6842), .Y(n6827) );
NAND2X4TS U3121 ( .A(n2050), .B(n2055), .Y(n2042) );
NAND2X4TS U3122 ( .A(n2497), .B(n5053), .Y(n2695) );
OAI2BB1X1TS U3123 ( .A0N(n5280), .A1N(n5282), .B0(n5281), .Y(n1268) );
NAND2X4TS U3124 ( .A(n3562), .B(n3604), .Y(n2018) );
NAND2X6TS U3125 ( .A(n2045), .B(n2044), .Y(n2054) );
INVX2TS U3126 ( .A(n1595), .Y(n2068) );
AND2X4TS U3127 ( .A(n4099), .B(n3190), .Y(n3133) );
INVX12TS U3128 ( .A(n5913), .Y(n5792) );
INVX12TS U3129 ( .A(n3101), .Y(n2769) );
NAND2X1TS U3130 ( .A(n6015), .B(n3097), .Y(n1276) );
NOR2X4TS U3131 ( .A(n3109), .B(n5022), .Y(n3108) );
AND2X4TS U3132 ( .A(n3965), .B(n3967), .Y(n2759) );
NAND2X4TS U3133 ( .A(n4046), .B(n5538), .Y(n2052) );
INVX6TS U3134 ( .A(n6720), .Y(n1969) );
CLKMX2X2TS U3135 ( .A(Data_Y[10]), .B(intDY_EWSW[10]), .S0(n5893), .Y(n1808)
);
CLKMX2X2TS U3136 ( .A(Data_Y[8]), .B(intDY_EWSW[8]), .S0(n5893), .Y(n1810)
);
CLKMX2X2TS U3137 ( .A(Data_Y[19]), .B(intDY_EWSW[19]), .S0(n5906), .Y(n1799)
);
CLKMX2X2TS U3138 ( .A(Data_Y[21]), .B(intDY_EWSW[21]), .S0(n5906), .Y(n1797)
);
CLKMX2X2TS U3139 ( .A(Data_Y[22]), .B(intDY_EWSW[22]), .S0(n5906), .Y(n1796)
);
INVX8TS U3140 ( .A(n3452), .Y(n2493) );
AND2X4TS U3141 ( .A(n3966), .B(n3968), .Y(n2760) );
CLKMX2X2TS U3142 ( .A(Data_Y[28]), .B(intDY_EWSW[28]), .S0(n5897), .Y(n1790)
);
CLKMX2X2TS U3143 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n5897), .Y(n1789)
);
CLKMX2X2TS U3144 ( .A(Data_Y[31]), .B(intDY_EWSW[31]), .S0(n5897), .Y(n1787)
);
CLKMX2X3TS U3145 ( .A(Data_Y[45]), .B(n2139), .S0(n5899), .Y(n1773) );
CLKMX2X2TS U3146 ( .A(Data_Y[9]), .B(n2431), .S0(n5893), .Y(n1809) );
CLKMX2X3TS U3147 ( .A(Data_Y[34]), .B(n2130), .S0(n5897), .Y(n1784) );
INVX4TS U3148 ( .A(n4563), .Y(n2699) );
CLKMX2X2TS U3149 ( .A(Data_Y[48]), .B(intDY_EWSW[48]), .S0(n5895), .Y(n1770)
);
CLKMX2X2TS U3150 ( .A(Data_Y[49]), .B(n1983), .S0(n5895), .Y(n1769) );
CLKMX2X2TS U3151 ( .A(Data_Y[50]), .B(intDY_EWSW[50]), .S0(n5895), .Y(n1768)
);
INVX8TS U3152 ( .A(n5329), .Y(n5819) );
CLKMX2X2TS U3153 ( .A(Data_Y[52]), .B(intDY_EWSW[52]), .S0(n5895), .Y(n1766)
);
CLKMX2X2TS U3154 ( .A(Data_Y[11]), .B(n2462), .S0(n5893), .Y(n1807) );
BUFX12TS U3155 ( .A(n5329), .Y(n5913) );
INVX8TS U3156 ( .A(n5329), .Y(n5825) );
INVX8TS U3157 ( .A(n5329), .Y(n5801) );
INVX2TS U3158 ( .A(n6722), .Y(n2798) );
OAI2BB1X1TS U3159 ( .A0N(OP_FLAG_EXP), .A1N(n5278), .B0(n5911), .Y(n1612) );
INVX2TS U3160 ( .A(n2372), .Y(n1976) );
INVX2TS U3161 ( .A(n5208), .Y(n5216) );
NAND2X4TS U3162 ( .A(n5538), .B(n2049), .Y(n2048) );
BUFX12TS U3163 ( .A(n5902), .Y(n5898) );
INVX2TS U3164 ( .A(n2697), .Y(n2684) );
INVX16TS U3165 ( .A(n3341), .Y(n5789) );
INVX12TS U3166 ( .A(n1975), .Y(n2371) );
BUFX12TS U3167 ( .A(n5894), .Y(n5904) );
CLKMX2X3TS U3168 ( .A(Data_Y[1]), .B(n2438), .S0(n5892), .Y(n1817) );
BUFX12TS U3169 ( .A(n5896), .Y(n5899) );
INVX16TS U3170 ( .A(n1972), .Y(n2507) );
BUFX8TS U3171 ( .A(n5280), .Y(n6722) );
NAND2X4TS U3172 ( .A(n1720), .B(n2480), .Y(n2677) );
CLKMX2X3TS U3173 ( .A(add_subt), .B(intAS), .S0(n5892), .Y(n1819) );
CLKMX2X3TS U3174 ( .A(Data_Y[2]), .B(intDY_EWSW[2]), .S0(n5892), .Y(n1816)
);
BUFX12TS U3175 ( .A(n5894), .Y(n5897) );
CLKMX2X3TS U3176 ( .A(Data_Y[4]), .B(n2011), .S0(n5892), .Y(n1814) );
CLKMX2X3TS U3177 ( .A(Data_Y[5]), .B(intDY_EWSW[5]), .S0(n5892), .Y(n1813)
);
BUFX12TS U3178 ( .A(n5894), .Y(n5906) );
NAND2X4TS U3179 ( .A(n3311), .B(n4098), .Y(n4099) );
BUFX12TS U3180 ( .A(n5902), .Y(n5903) );
NAND2X4TS U3181 ( .A(n4328), .B(n2613), .Y(n1710) );
BUFX12TS U3182 ( .A(n5894), .Y(n5900) );
BUFX12TS U3183 ( .A(n5896), .Y(n5895) );
BUFX12TS U3184 ( .A(n5902), .Y(n5905) );
BUFX12TS U3185 ( .A(n5896), .Y(n5901) );
INVX2TS U3186 ( .A(n3096), .Y(n3311) );
BUFX16TS U3187 ( .A(n1981), .Y(n5885) );
INVX16TS U3188 ( .A(n5888), .Y(n1972) );
BUFX12TS U3189 ( .A(n5907), .Y(n5896) );
MX2X1TS U3190 ( .A(Data_Y[62]), .B(intDY_EWSW[62]), .S0(n5907), .Y(n1756) );
NOR2X8TS U3191 ( .A(n6094), .B(n5958), .Y(n5280) );
INVX2TS U3192 ( .A(n1704), .Y(n3456) );
INVX6TS U3193 ( .A(n5295), .Y(n5613) );
NOR2X4TS U3194 ( .A(n3068), .B(n3067), .Y(n3066) );
NAND2X4TS U3195 ( .A(n3904), .B(n2886), .Y(n2885) );
MX2X1TS U3196 ( .A(Data_X[63]), .B(intDX_EWSW[63]), .S0(n5907), .Y(n1820) );
INVX2TS U3197 ( .A(n1718), .Y(n5537) );
MX2X1TS U3198 ( .A(Data_X[62]), .B(intDX_EWSW[62]), .S0(n5907), .Y(n1821) );
BUFX20TS U3199 ( .A(n4015), .Y(n1981) );
NAND2X2TS U3200 ( .A(n2350), .B(n4073), .Y(n4074) );
AND2X2TS U3201 ( .A(n4763), .B(n4762), .Y(n2324) );
INVX6TS U3202 ( .A(n3443), .Y(n2060) );
INVX6TS U3203 ( .A(n3444), .Y(n2061) );
AND2X4TS U3204 ( .A(n3905), .B(n3903), .Y(n2886) );
NOR2X6TS U3205 ( .A(n2101), .B(n2100), .Y(n3439) );
NAND2X6TS U3206 ( .A(n3116), .B(n4620), .Y(n3115) );
BUFX16TS U3207 ( .A(n4869), .Y(n5958) );
INVX12TS U3208 ( .A(n3878), .Y(n2474) );
INVX8TS U3209 ( .A(n5880), .Y(n5824) );
INVX8TS U3210 ( .A(n5869), .Y(n5874) );
INVX8TS U3211 ( .A(Shift_reg_FLAGS_7[0]), .Y(n6772) );
NAND2X2TS U3212 ( .A(n5736), .B(LZD_output_NRM2_EW[4]), .Y(n2004) );
NOR2X4TS U3213 ( .A(n2193), .B(n2099), .Y(n2101) );
INVX2TS U3214 ( .A(n3238), .Y(n5339) );
INVX12TS U3215 ( .A(n2517), .Y(n2518) );
CLKAND2X2TS U3216 ( .A(n2632), .B(n2631), .Y(n2326) );
OA21X2TS U3217 ( .A0(n5211), .A1(n5210), .B0(n5209), .Y(n2450) );
INVX8TS U3218 ( .A(n5869), .Y(n5873) );
OR2X4TS U3219 ( .A(n4000), .B(n2244), .Y(n3421) );
OR2X4TS U3220 ( .A(n4001), .B(n2236), .Y(n3420) );
NAND2X4TS U3221 ( .A(n4658), .B(DMP_SFG[40]), .Y(n5163) );
CLKINVX6TS U3222 ( .A(shift_value_SHT2_EWR[2]), .Y(n2673) );
NOR2X2TS U3223 ( .A(n6264), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n3406) );
MXI2X2TS U3224 ( .A(n6265), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n3407) );
NAND2X4TS U3225 ( .A(n3306), .B(intDY_EWSW[18]), .Y(n2037) );
INVX8TS U3226 ( .A(n7010), .Y(n2500) );
NAND2X2TS U3227 ( .A(n3343), .B(Raw_mant_NRM_SWR[37]), .Y(n3019) );
BUFX8TS U3228 ( .A(n2249), .Y(n5763) );
CLKINVX2TS U3229 ( .A(Shift_reg_FLAGS_7[3]), .Y(n5881) );
NOR2X4TS U3230 ( .A(n3297), .B(intDY_EWSW[16]), .Y(n2033) );
NAND2X4TS U3231 ( .A(n3297), .B(intDY_EWSW[16]), .Y(n2039) );
BUFX8TS U3232 ( .A(n2249), .Y(n5762) );
NAND2X2TS U3233 ( .A(n3343), .B(Raw_mant_NRM_SWR[40]), .Y(n2856) );
AND2X4TS U3234 ( .A(n6549), .B(n6548), .Y(n2100) );
NAND2X2TS U3235 ( .A(n3343), .B(Raw_mant_NRM_SWR[41]), .Y(n2843) );
NOR2X4TS U3236 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[25]), .Y(
n2113) );
NOR2X4TS U3237 ( .A(DMP_SFG[51]), .B(DmP_mant_SFG_SWR[53]), .Y(n4873) );
NAND2X2TS U3238 ( .A(DMP_SFG[49]), .B(DmP_mant_SFG_SWR[51]), .Y(n5231) );
NOR2X4TS U3239 ( .A(DMP_SFG[50]), .B(DmP_mant_SFG_SWR[52]), .Y(n4870) );
NAND3X4TS U3240 ( .A(n4217), .B(n4216), .C(n4215), .Y(n1390) );
NAND2X2TS U3241 ( .A(n2824), .B(n2823), .Y(n1657) );
NAND3X4TS U3242 ( .A(n4195), .B(n4194), .C(n4193), .Y(n1370) );
NAND3X4TS U3243 ( .A(n4232), .B(n4231), .C(n4230), .Y(n1380) );
NAND3X2TS U3244 ( .A(n4284), .B(n4285), .C(n4283), .Y(n1344) );
NAND3X4TS U3245 ( .A(n3831), .B(n3832), .C(n3830), .Y(n1626) );
NAND3X4TS U3246 ( .A(n3698), .B(n3697), .C(n3696), .Y(n1655) );
NAND2X6TS U3247 ( .A(n5536), .B(n2974), .Y(n2572) );
NAND2X6TS U3248 ( .A(n5151), .B(n6721), .Y(n2001) );
NAND2X6TS U3249 ( .A(n3021), .B(n6721), .Y(n3020) );
NAND2X4TS U3250 ( .A(n5172), .B(n6722), .Y(n3259) );
NOR2X4TS U3251 ( .A(n1113), .B(n1484), .Y(n6030) );
NAND2X4TS U3252 ( .A(n4513), .B(n2773), .Y(n2006) );
NAND2X6TS U3253 ( .A(n2962), .B(n6721), .Y(n2855) );
NAND2X4TS U3254 ( .A(n2984), .B(n2983), .Y(n1124) );
NAND2X6TS U3255 ( .A(n4968), .B(n6721), .Y(n2845) );
OAI2BB1X2TS U3256 ( .A0N(n2466), .A1N(n3343), .B0(n4878), .Y(n1277) );
NAND2X4TS U3257 ( .A(n3054), .B(n5639), .Y(n3053) );
NAND2X6TS U3258 ( .A(n6950), .B(n2974), .Y(n2592) );
NAND2X6TS U3259 ( .A(n2965), .B(n4966), .Y(n2964) );
INVX2TS U3260 ( .A(n2985), .Y(n6949) );
NAND2X6TS U3261 ( .A(n1957), .B(n2801), .Y(n2800) );
NAND3X6TS U3262 ( .A(n2969), .B(n2337), .C(n3393), .Y(n2809) );
NAND2X4TS U3263 ( .A(n4566), .B(n2756), .Y(n2755) );
OAI2BB1X2TS U3264 ( .A0N(n5630), .A1N(n4726), .B0(n4725), .Y(n1249) );
AND4X6TS U3265 ( .A(n2129), .B(n2698), .C(n3467), .D(n2704), .Y(n6985) );
INVX2TS U3266 ( .A(n5680), .Y(n6920) );
AND2X2TS U3267 ( .A(n2108), .B(n2107), .Y(n5616) );
OAI2BB1X2TS U3268 ( .A0N(n5630), .A1N(n4639), .B0(n4638), .Y(n1254) );
NAND3X6TS U3269 ( .A(n3045), .B(n4172), .C(n2007), .Y(n4615) );
NAND2X4TS U3270 ( .A(n6936), .B(n5557), .Y(n2938) );
NOR2X6TS U3271 ( .A(n4369), .B(n6130), .Y(n2659) );
MX2X2TS U3272 ( .A(n5681), .B(n2421), .S0(n2507), .Y(n1134) );
NAND2X2TS U3273 ( .A(n3033), .B(n5510), .Y(n3032) );
NAND2X6TS U3274 ( .A(n6952), .B(n2557), .Y(n2579) );
NAND2X4TS U3275 ( .A(n2906), .B(n2905), .Y(n2904) );
INVX8TS U3276 ( .A(n2690), .Y(n2685) );
NAND2X4TS U3277 ( .A(n4562), .B(n2381), .Y(n2073) );
NAND2X6TS U3278 ( .A(n6953), .B(n5557), .Y(n2575) );
NAND2X6TS U3279 ( .A(n2878), .B(n2874), .Y(n2873) );
NAND2X6TS U3280 ( .A(n5055), .B(n2889), .Y(n2104) );
NAND4X4TS U3281 ( .A(n2982), .B(n2979), .C(n2977), .D(n2976), .Y(n2975) );
NAND4X4TS U3282 ( .A(n4613), .B(n4612), .C(n4611), .D(n4610), .Y(n4614) );
NAND2X4TS U3283 ( .A(n6937), .B(n2486), .Y(n2959) );
NAND2X4TS U3284 ( .A(n6975), .B(n2766), .Y(n2883) );
AND2X4TS U3285 ( .A(n5199), .B(n5198), .Y(n6982) );
NAND2X6TS U3286 ( .A(n2578), .B(n2576), .Y(n6953) );
NAND3X6TS U3287 ( .A(n5500), .B(n5499), .C(n2741), .Y(n6939) );
NAND4X4TS U3288 ( .A(n4322), .B(n4321), .C(n4320), .D(n4319), .Y(n4570) );
AOI22X2TS U3289 ( .A0(n5733), .A1(n2756), .B0(n2507), .B1(
DmP_mant_SFG_SWR[54]), .Y(n5734) );
NAND2X4TS U3290 ( .A(n2827), .B(n1707), .Y(n3046) );
NAND2X4TS U3291 ( .A(n2748), .B(n2747), .Y(n2746) );
NOR3X6TS U3292 ( .A(n2726), .B(n2725), .C(n3458), .Y(n2724) );
NAND2X4TS U3293 ( .A(n4558), .B(n5647), .Y(n2075) );
NAND2X4TS U3294 ( .A(n3036), .B(n5729), .Y(n5733) );
NAND3X6TS U3295 ( .A(n4629), .B(n3090), .C(n3089), .Y(n3088) );
NAND2X6TS U3296 ( .A(n2120), .B(n2119), .Y(n2118) );
NAND2X1TS U3297 ( .A(n5279), .B(n5780), .Y(n1753) );
OR2X4TS U3298 ( .A(n2054), .B(n2053), .Y(n2043) );
INVX8TS U3299 ( .A(n2054), .Y(n4517) );
NAND2X6TS U3300 ( .A(n2617), .B(n5507), .Y(n5543) );
XNOR2X2TS U3301 ( .A(n2832), .B(n4410), .Y(n4411) );
NAND2X4TS U3302 ( .A(n4792), .B(n5780), .Y(n4793) );
NAND4X6TS U3303 ( .A(n2625), .B(n2624), .C(n2623), .D(n2622), .Y(n5487) );
NOR2X2TS U3304 ( .A(n6015), .B(n6089), .Y(n5805) );
MXI2X2TS U3305 ( .A(n6142), .B(n6295), .S0(n2540), .Y(n1454) );
MXI2X2TS U3306 ( .A(n6143), .B(n6288), .S0(n2489), .Y(n1457) );
NAND2X4TS U3307 ( .A(n3198), .B(n4656), .Y(n3195) );
MXI2X2TS U3308 ( .A(n6146), .B(n6281), .S0(n2489), .Y(n1466) );
BUFX3TS U3309 ( .A(n6386), .Y(n6728) );
OA21X4TS U3310 ( .A0(n4591), .A1(n5912), .B0(n2259), .Y(n3082) );
INVX8TS U3311 ( .A(n5789), .Y(n6015) );
CLKMX2X2TS U3312 ( .A(Data_X[22]), .B(intDX_EWSW[22]), .S0(n5905), .Y(n1861)
);
NAND2X6TS U3313 ( .A(n2339), .B(n1978), .Y(n3112) );
NAND2X2TS U3314 ( .A(n5732), .B(DmP_mant_SFG_SWR[18]), .Y(n3145) );
CLKMX2X2TS U3315 ( .A(Data_Y[6]), .B(intDY_EWSW[6]), .S0(n5893), .Y(n1812)
);
CLKMX2X2TS U3316 ( .A(Data_Y[17]), .B(intDY_EWSW[17]), .S0(n5906), .Y(n1801)
);
NAND2X2TS U3317 ( .A(n5732), .B(DmP_mant_SFG_SWR[36]), .Y(n2870) );
CLKMX2X2TS U3318 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n5906), .Y(n1802)
);
CLKMX2X2TS U3319 ( .A(Data_Y[12]), .B(intDY_EWSW[12]), .S0(n5893), .Y(n1806)
);
MX2X2TS U3320 ( .A(n6005), .B(Shift_amount_SHT1_EWR[3]), .S0(n2555), .Y(
n1689) );
CLKMX2X3TS U3321 ( .A(Data_Y[27]), .B(n2437), .S0(n5897), .Y(n1791) );
CLKMX2X2TS U3322 ( .A(Data_Y[13]), .B(n2427), .S0(n5893), .Y(n1805) );
CLKMX2X2TS U3323 ( .A(Data_Y[7]), .B(n2847), .S0(n5893), .Y(n1811) );
MXI2X2TS U3324 ( .A(n6097), .B(n6274), .S0(n2507), .Y(n1589) );
OAI2BB2X1TS U3325 ( .B0(n5333), .B1(Shift_reg_FLAGS_7[1]), .A0N(n5823),
.A1N(n5613), .Y(n5334) );
CLKMX2X2TS U3326 ( .A(Data_X[26]), .B(intDX_EWSW[26]), .S0(n5903), .Y(n1857)
);
CLKMX2X2TS U3327 ( .A(Data_X[41]), .B(intDX_EWSW[41]), .S0(n5900), .Y(n1842)
);
CLKMX2X2TS U3328 ( .A(Data_X[13]), .B(intDX_EWSW[13]), .S0(n5898), .Y(n1870)
);
CLKMX2X2TS U3329 ( .A(Data_X[47]), .B(intDX_EWSW[47]), .S0(n5901), .Y(n1836)
);
CLKMX2X2TS U3330 ( .A(Data_X[12]), .B(intDX_EWSW[12]), .S0(n5898), .Y(n1871)
);
CLKMX2X2TS U3331 ( .A(Data_X[27]), .B(intDX_EWSW[27]), .S0(n5903), .Y(n1856)
);
MXI2X1TS U3332 ( .A(n6172), .B(n6286), .S0(n5885), .Y(n1544) );
CLKMX2X2TS U3333 ( .A(Data_X[11]), .B(intDX_EWSW[11]), .S0(n5898), .Y(n1872)
);
CLKMX2X2TS U3334 ( .A(Data_X[46]), .B(intDX_EWSW[46]), .S0(n5901), .Y(n1837)
);
CLKMX2X2TS U3335 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n5903), .Y(n1855)
);
CLKMX2X2TS U3336 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n5904), .Y(n1883)
);
CLKMX2X2TS U3337 ( .A(Data_X[10]), .B(intDX_EWSW[10]), .S0(n5898), .Y(n1873)
);
CLKMX2X2TS U3338 ( .A(Data_X[29]), .B(intDX_EWSW[29]), .S0(n5903), .Y(n1854)
);
NAND2X6TS U3339 ( .A(n5016), .B(n2955), .Y(n2854) );
CLKMX2X2TS U3340 ( .A(Data_X[9]), .B(intDX_EWSW[9]), .S0(n5898), .Y(n1874)
);
CLKMX2X2TS U3341 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n5903), .Y(n1853)
);
CLKMX2X2TS U3342 ( .A(Data_X[36]), .B(intDX_EWSW[36]), .S0(n5900), .Y(n1847)
);
CLKMX2X2TS U3343 ( .A(Data_X[8]), .B(intDX_EWSW[8]), .S0(n5898), .Y(n1875)
);
CLKMX2X2TS U3344 ( .A(Data_X[14]), .B(intDX_EWSW[14]), .S0(n5905), .Y(n1869)
);
BUFX12TS U3345 ( .A(n5728), .Y(n2453) );
CLKMX2X2TS U3346 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n5903), .Y(n1852)
);
CLKMX2X2TS U3347 ( .A(Data_X[45]), .B(intDX_EWSW[45]), .S0(n5901), .Y(n1838)
);
NAND2X4TS U3348 ( .A(n1722), .B(n2476), .Y(n2896) );
CLKMX2X2TS U3349 ( .A(Data_X[7]), .B(intDX_EWSW[7]), .S0(n5898), .Y(n1876)
);
CLKMX2X2TS U3350 ( .A(Data_X[32]), .B(intDX_EWSW[32]), .S0(n5903), .Y(n1851)
);
CLKMX2X2TS U3351 ( .A(Data_X[6]), .B(intDX_EWSW[6]), .S0(n5898), .Y(n1877)
);
CLKMX2X2TS U3352 ( .A(Data_X[44]), .B(intDX_EWSW[44]), .S0(n5901), .Y(n1839)
);
CLKMX2X2TS U3353 ( .A(Data_X[1]), .B(intDX_EWSW[1]), .S0(n5904), .Y(n1882)
);
CLKMX2X2TS U3354 ( .A(Data_X[5]), .B(intDX_EWSW[5]), .S0(n5898), .Y(n1878)
);
CLKMX2X2TS U3355 ( .A(Data_X[33]), .B(intDX_EWSW[33]), .S0(n5903), .Y(n1850)
);
CLKMX2X2TS U3356 ( .A(Data_X[4]), .B(intDX_EWSW[4]), .S0(n5898), .Y(n1879)
);
CLKMX2X2TS U3357 ( .A(Data_X[43]), .B(intDX_EWSW[43]), .S0(n5900), .Y(n1840)
);
CLKMX2X2TS U3358 ( .A(Data_X[34]), .B(intDX_EWSW[34]), .S0(n5900), .Y(n1849)
);
CLKMX2X2TS U3359 ( .A(Data_X[3]), .B(intDX_EWSW[3]), .S0(n5904), .Y(n1880)
);
CLKMX2X2TS U3360 ( .A(Data_Y[46]), .B(n1988), .S0(n5895), .Y(n1772) );
CLKMX2X2TS U3361 ( .A(Data_X[42]), .B(intDX_EWSW[42]), .S0(n5900), .Y(n1841)
);
CLKMX2X2TS U3362 ( .A(Data_X[52]), .B(intDX_EWSW[52]), .S0(n5901), .Y(n1831)
);
CLKMX2X2TS U3363 ( .A(Data_X[21]), .B(intDX_EWSW[21]), .S0(n5905), .Y(n1862)
);
CLKMX2X2TS U3364 ( .A(Data_Y[56]), .B(intDY_EWSW[56]), .S0(n5904), .Y(n1762)
);
CLKMX2X2TS U3365 ( .A(Data_X[53]), .B(intDX_EWSW[53]), .S0(n5901), .Y(n1830)
);
CLKMX2X2TS U3366 ( .A(Data_X[20]), .B(intDX_EWSW[20]), .S0(n5905), .Y(n1863)
);
CLKMX2X2TS U3367 ( .A(Data_Y[57]), .B(intDY_EWSW[57]), .S0(n5904), .Y(n1761)
);
CLKMX2X2TS U3368 ( .A(Data_X[40]), .B(intDX_EWSW[40]), .S0(n5900), .Y(n1843)
);
CLKMX2X2TS U3369 ( .A(Data_X[23]), .B(intDX_EWSW[23]), .S0(n5905), .Y(n1860)
);
INVX12TS U3370 ( .A(n5887), .Y(n2540) );
CLKMX2X2TS U3371 ( .A(Data_X[19]), .B(intDX_EWSW[19]), .S0(n5905), .Y(n1864)
);
CLKMX2X2TS U3372 ( .A(Data_X[38]), .B(intDX_EWSW[38]), .S0(n5900), .Y(n1845)
);
CLKMX2X2TS U3373 ( .A(Data_X[51]), .B(intDX_EWSW[51]), .S0(n5901), .Y(n1832)
);
CLKMX2X2TS U3374 ( .A(Data_X[18]), .B(intDX_EWSW[18]), .S0(n5905), .Y(n1865)
);
MXI2X2TS U3375 ( .A(n6145), .B(n6277), .S0(n2687), .Y(n1463) );
CLKMX2X2TS U3376 ( .A(Data_Y[26]), .B(intDY_EWSW[26]), .S0(n5897), .Y(n1792)
);
CLKMX2X2TS U3377 ( .A(Data_X[17]), .B(intDX_EWSW[17]), .S0(n5905), .Y(n1866)
);
CLKMX2X2TS U3378 ( .A(Data_X[50]), .B(intDX_EWSW[50]), .S0(n5901), .Y(n1833)
);
INVX2TS U3379 ( .A(n1719), .Y(n3909) );
CLKMX2X2TS U3380 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n5906), .Y(n1794)
);
CLKMX2X2TS U3381 ( .A(Data_X[24]), .B(intDX_EWSW[24]), .S0(n5903), .Y(n1859)
);
CLKMX2X2TS U3382 ( .A(Data_X[49]), .B(intDX_EWSW[49]), .S0(n5901), .Y(n1834)
);
CLKMX2X2TS U3383 ( .A(Data_X[16]), .B(intDX_EWSW[16]), .S0(n5905), .Y(n1867)
);
CLKMX2X2TS U3384 ( .A(Data_Y[53]), .B(intDY_EWSW[53]), .S0(n5895), .Y(n1765)
);
MXI2X2TS U3385 ( .A(n6148), .B(n6291), .S0(n2507), .Y(n1472) );
CLKMX2X2TS U3386 ( .A(Data_X[2]), .B(intDX_EWSW[2]), .S0(n5904), .Y(n1881)
);
CLKMX2X2TS U3387 ( .A(Data_X[48]), .B(intDX_EWSW[48]), .S0(n5901), .Y(n1835)
);
INVX12TS U3388 ( .A(n5887), .Y(n2489) );
CLKMX2X2TS U3389 ( .A(Data_X[15]), .B(intDX_EWSW[15]), .S0(n5905), .Y(n1868)
);
CLKMX2X2TS U3390 ( .A(Data_X[25]), .B(intDX_EWSW[25]), .S0(n5903), .Y(n1858)
);
CLKMX2X2TS U3391 ( .A(Data_X[37]), .B(intDX_EWSW[37]), .S0(n5900), .Y(n1846)
);
INVX2TS U3392 ( .A(n5155), .Y(n2554) );
NAND2X1TS U3393 ( .A(n5273), .B(final_result_ieee[29]), .Y(n6947) );
INVX12TS U3394 ( .A(n5562), .Y(n2490) );
NAND2X1TS U3395 ( .A(n5273), .B(final_result_ieee[27]), .Y(n6941) );
NAND2X1TS U3396 ( .A(n5273), .B(final_result_ieee[28]), .Y(n6944) );
NAND2X1TS U3397 ( .A(n5273), .B(final_result_ieee[33]), .Y(n6954) );
NAND2X1TS U3398 ( .A(n5273), .B(final_result_ieee[24]), .Y(n6934) );
NAND2X1TS U3399 ( .A(n5273), .B(final_result_ieee[26]), .Y(n6938) );
NAND2X1TS U3400 ( .A(n5273), .B(final_result_ieee[23]), .Y(n6933) );
NAND2X1TS U3401 ( .A(n5273), .B(final_result_ieee[22]), .Y(n6932) );
AOI21X2TS U3402 ( .A0(n5004), .A1(n4157), .B0(n4156), .Y(n4158) );
NAND2X1TS U3403 ( .A(n5273), .B(final_result_ieee[41]), .Y(n6971) );
NAND2X2TS U3404 ( .A(n5277), .B(n5276), .Y(n5911) );
BUFX12TS U3405 ( .A(n5892), .Y(n5893) );
NAND2X6TS U3406 ( .A(n2897), .B(n3932), .Y(n1722) );
BUFX12TS U3407 ( .A(n1981), .Y(n5883) );
AND2X4TS U3408 ( .A(n5433), .B(n5434), .Y(n2401) );
NAND2X1TS U3409 ( .A(n5273), .B(final_result_ieee[9]), .Y(n6910) );
NAND2X6TS U3410 ( .A(n3114), .B(n4527), .Y(n1978) );
MX2X2TS U3411 ( .A(n5941), .B(Shift_amount_SHT1_EWR[2]), .S0(n2555), .Y(
n1690) );
INVX8TS U3412 ( .A(n4657), .Y(n3199) );
CLKMX2X3TS U3413 ( .A(Data_Y[0]), .B(n2407), .S0(n5892), .Y(n1818) );
CLKMX2X3TS U3414 ( .A(Data_Y[63]), .B(intDY_EWSW[63]), .S0(n5892), .Y(n1755)
);
CLKMX2X3TS U3415 ( .A(Data_X[61]), .B(intDX_EWSW[61]), .S0(n5892), .Y(n1822)
);
NAND2X4TS U3416 ( .A(n5110), .B(n3215), .Y(n5136) );
INVX8TS U3417 ( .A(n3341), .Y(n5817) );
AND2X2TS U3418 ( .A(n2475), .B(n1729), .Y(n2370) );
MX2X2TS U3419 ( .A(n5947), .B(Shift_amount_SHT1_EWR[4]), .S0(n2555), .Y(
n1688) );
INVX8TS U3420 ( .A(n3341), .Y(n5814) );
CLKMX2X2TS U3421 ( .A(n5878), .B(n2555), .S0(n5882), .Y(n2319) );
NAND2X6TS U3422 ( .A(n4523), .B(n3114), .Y(n5515) );
BUFX12TS U3423 ( .A(n5907), .Y(n5892) );
BUFX12TS U3424 ( .A(n5907), .Y(n5894) );
OA21X2TS U3425 ( .A0(n5034), .A1(n5175), .B0(n5176), .Y(n5035) );
INVX2TS U3426 ( .A(n2434), .Y(n2435) );
NAND2X4TS U3427 ( .A(n5077), .B(n4661), .Y(n3200) );
CLKMX2X2TS U3428 ( .A(DmP_mant_SHT1_SW[25]), .B(Raw_mant_NRM_SWR[27]), .S0(
n5779), .Y(n5155) );
INVX4TS U3429 ( .A(n1751), .Y(n4169) );
NAND2X6TS U3430 ( .A(n3014), .B(n5476), .Y(n4527) );
NAND2X6TS U3431 ( .A(n2770), .B(n3376), .Y(n4584) );
NAND2X4TS U3432 ( .A(n4768), .B(n4434), .Y(n3069) );
INVX2TS U3433 ( .A(n4669), .Y(n3194) );
INVX8TS U3434 ( .A(n4756), .Y(n4933) );
NAND2X6TS U3435 ( .A(n4441), .B(n1995), .Y(n4932) );
INVX12TS U3436 ( .A(n1946), .Y(n1970) );
INVX2TS U3437 ( .A(n1701), .Y(n4040) );
AND2X2TS U3438 ( .A(n3732), .B(DMP_EXP_EWSW[18]), .Y(n2375) );
BUFX12TS U3439 ( .A(n5907), .Y(n5902) );
NOR2X8TS U3440 ( .A(n5958), .B(OP_FLAG_SFG), .Y(n4966) );
NAND2X4TS U3441 ( .A(n5888), .B(n6017), .Y(n2697) );
NAND2X2TS U3442 ( .A(n5132), .B(n5145), .Y(n5135) );
NAND2X2TS U3443 ( .A(n5170), .B(add_x_6_n193), .Y(n5171) );
NAND2X6TS U3444 ( .A(n3450), .B(n3449), .Y(n2719) );
NAND2X6TS U3445 ( .A(n4075), .B(n2350), .Y(n2567) );
INVX8TS U3446 ( .A(n3094), .Y(n3338) );
INVX4TS U3447 ( .A(n4076), .Y(n4081) );
AND2X2TS U3448 ( .A(n5142), .B(n5141), .Y(n5150) );
NAND2X4TS U3449 ( .A(n4396), .B(n5972), .Y(n4397) );
BUFX8TS U3450 ( .A(n2501), .Y(n5445) );
NAND2X6TS U3451 ( .A(n4445), .B(n1956), .Y(n1995) );
NAND2X6TS U3452 ( .A(n3634), .B(n2640), .Y(n2639) );
CLKMX2X2TS U3453 ( .A(DmP_mant_SHT1_SW[50]), .B(DmP_EXP_EWSW[50]), .S0(n5873), .Y(n1297) );
BUFX8TS U3454 ( .A(n2501), .Y(n3829) );
CLKMX2X2TS U3455 ( .A(DMP_SHT1_EWSW[61]), .B(DMP_EXP_EWSW[61]), .S0(n5866),
.Y(n1408) );
NAND2X1TS U3456 ( .A(n5880), .B(DmP_mant_SHT1_SW[16]), .Y(n5289) );
NAND2X6TS U3457 ( .A(n3184), .B(n4485), .Y(n2926) );
XOR2X1TS U3458 ( .A(n1998), .B(n5957), .Y(n5959) );
CLKMX2X2TS U3459 ( .A(DmP_mant_SHT1_SW[5]), .B(DmP_EXP_EWSW[5]), .S0(n5870),
.Y(n1387) );
BUFX8TS U3460 ( .A(n2501), .Y(n4288) );
CLKMX2X2TS U3461 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n5856),
.Y(n1429) );
BUFX8TS U3462 ( .A(n2501), .Y(n5350) );
NAND2X1TS U3463 ( .A(n5852), .B(n5759), .Y(n1892) );
NAND2X6TS U3464 ( .A(n3015), .B(n5477), .Y(n3014) );
BUFX8TS U3465 ( .A(n2501), .Y(n4276) );
NOR2X2TS U3466 ( .A(n3400), .B(n3398), .Y(n3399) );
INVX6TS U3467 ( .A(n2387), .Y(n3368) );
AND2X6TS U3468 ( .A(n3931), .B(n6624), .Y(n2897) );
NAND2X6TS U3469 ( .A(n3924), .B(n3925), .Y(n2901) );
AND2X4TS U3470 ( .A(n3921), .B(n3920), .Y(n2364) );
NAND2X6TS U3471 ( .A(n5987), .B(n4129), .Y(n3144) );
BUFX16TS U3472 ( .A(n3958), .Y(n5653) );
INVX8TS U3473 ( .A(n5865), .Y(n5863) );
INVX8TS U3474 ( .A(n5869), .Y(n5872) );
NAND2X6TS U3475 ( .A(n4945), .B(n2361), .Y(n5173) );
INVX8TS U3476 ( .A(n5865), .Y(n5862) );
INVX8TS U3477 ( .A(n5869), .Y(n5867) );
INVX8TS U3478 ( .A(n5865), .Y(n5864) );
INVX8TS U3479 ( .A(n5869), .Y(n5871) );
INVX4TS U3480 ( .A(n4023), .Y(n1973) );
INVX8TS U3481 ( .A(n5869), .Y(n5870) );
NAND2X6TS U3482 ( .A(n3461), .B(n2673), .Y(n2672) );
MX2X1TS U3483 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(
Shift_reg_FLAGS_7[0]), .Y(n1281) );
INVX8TS U3484 ( .A(Shift_reg_FLAGS_7[0]), .Y(n6773) );
NAND2X4TS U3485 ( .A(n4135), .B(add_x_6_n412), .Y(n3135) );
AOI2BB2X2TS U3486 ( .B0(n2187), .B1(n6704), .A0N(n2547), .A1N(n6703), .Y(
final_result_ieee[57]) );
BUFX8TS U3487 ( .A(n5764), .Y(n5831) );
BUFX8TS U3488 ( .A(n6996), .Y(n5832) );
OAI21X2TS U3489 ( .A0(n5938), .A1(n5937), .B0(n5936), .Y(n5944) );
BUFX8TS U3490 ( .A(n5764), .Y(n5847) );
INVX2TS U3491 ( .A(n5619), .Y(n2858) );
BUFX8TS U3492 ( .A(n6996), .Y(n5848) );
INVX8TS U3493 ( .A(n5869), .Y(n5868) );
CLKBUFX3TS U3494 ( .A(n5243), .Y(n5247) );
OR2X2TS U3495 ( .A(n6268), .B(DMP_EXP_EWSW[57]), .Y(n6010) );
INVX6TS U3496 ( .A(n2421), .Y(n1985) );
INVX6TS U3497 ( .A(n6266), .Y(busy) );
NAND2X4TS U3498 ( .A(add_x_6_A_13_), .B(add_x_6_B_13_), .Y(n2331) );
NAND2X4TS U3499 ( .A(add_x_6_A_20_), .B(add_x_6_B_20_), .Y(n4722) );
NAND2X4TS U3500 ( .A(sub_x_5_n610), .B(sub_x_5_A_34_), .Y(n4945) );
INVX2TS U3501 ( .A(n2282), .Y(n2283) );
NAND2X6TS U3502 ( .A(add_x_6_A_12_), .B(add_x_6_B_12_), .Y(n5521) );
BUFX8TS U3503 ( .A(n6267), .Y(n5736) );
NOR2X4TS U3504 ( .A(n3318), .B(n2130), .Y(n3559) );
BUFX16TS U3505 ( .A(Shift_reg_FLAGS_7[2]), .Y(n5851) );
NOR2X8TS U3506 ( .A(n6404), .B(n2188), .Y(n5764) );
INVX2TS U3507 ( .A(n6022), .Y(n5889) );
INVX2TS U3508 ( .A(DmP_mant_SHT1_SW[50]), .Y(n5333) );
INVX2TS U3509 ( .A(DmP_mant_SHT1_SW[5]), .Y(n5783) );
INVX2TS U3510 ( .A(DMP_SHT2_EWSW[61]), .Y(n5875) );
INVX2TS U3511 ( .A(n6021), .Y(n5886) );
INVX2TS U3512 ( .A(n2429), .Y(n2430) );
OR2X2TS U3513 ( .A(n6417), .B(n2245), .Y(n3895) );
NAND2X2TS U3514 ( .A(DMP_SFG[50]), .B(DmP_mant_SFG_SWR[52]), .Y(n4872) );
NAND2X6TS U3515 ( .A(n6471), .B(n6470), .Y(n3229) );
NAND2X6TS U3516 ( .A(n6474), .B(n6473), .Y(n2786) );
NOR4X6TS U3517 ( .A(Raw_mant_NRM_SWR[41]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .D(Raw_mant_NRM_SWR[47]), .Y(n2574) );
NAND2X4TS U3518 ( .A(n3317), .B(DMP_SFG[9]), .Y(n4524) );
NAND2X6TS U3519 ( .A(n3363), .B(DMP_SFG[1]), .Y(n5948) );
NAND2X1TS U3520 ( .A(n3357), .B(DMP_SFG[51]), .Y(n5213) );
NOR2X4TS U3521 ( .A(n6298), .B(DMP_SFG[48]), .Y(n4679) );
INVX8TS U3522 ( .A(n3340), .Y(n2555) );
INVX12TS U3523 ( .A(n2500), .Y(n1974) );
NAND2X6TS U3524 ( .A(n6257), .B(DmP_mant_SFG_SWR[10]), .Y(n5477) );
NAND2X4TS U3525 ( .A(n3365), .B(DMP_SFG[43]), .Y(n5090) );
BUFX12TS U3526 ( .A(n6774), .Y(n5869) );
INVX2TS U3527 ( .A(n3356), .Y(n3203) );
NAND2X6TS U3528 ( .A(DMP_SFG[28]), .B(DmP_mant_SFG_SWR[30]), .Y(n5020) );
AOI21X4TS U3529 ( .A0(n2876), .A1(n2498), .B0(n2336), .Y(n2875) );
NAND2X8TS U3530 ( .A(n4422), .B(n3113), .Y(n2947) );
NAND2X8TS U3531 ( .A(n3117), .B(n2957), .Y(n4422) );
BUFX16TS U3532 ( .A(n2649), .Y(n3846) );
INVX12TS U3533 ( .A(n2675), .Y(n2876) );
NAND2X8TS U3534 ( .A(n2645), .B(n2646), .Y(n1975) );
NOR2X8TS U3535 ( .A(n6332), .B(DMP_SFG[4]), .Y(n5451) );
BUFX20TS U3536 ( .A(n2822), .Y(n2813) );
BUFX20TS U3537 ( .A(n2822), .Y(n4121) );
NAND2X6TS U3538 ( .A(n3308), .B(intDY_EWSW[40]), .Y(n2398) );
NAND2X4TS U3539 ( .A(n4245), .B(intDX_EWSW[39]), .Y(n4279) );
NOR2X4TS U3540 ( .A(n3563), .B(n3608), .Y(n3565) );
OR2X4TS U3541 ( .A(n2818), .B(n2140), .Y(n4250) );
NAND3X8TS U3542 ( .A(n2481), .B(n3099), .C(n3168), .Y(n2566) );
NAND2X6TS U3543 ( .A(n3585), .B(n3557), .Y(n3588) );
NAND2X4TS U3544 ( .A(n4295), .B(n1914), .Y(n3741) );
NAND3X4TS U3545 ( .A(n3659), .B(n3658), .C(n3657), .Y(n1621) );
NAND3X4TS U3546 ( .A(n3650), .B(n3649), .C(n3648), .Y(n1620) );
XOR2X4TS U3547 ( .A(n1977), .B(n1976), .Y(exp_rslt_NRM2_EW1[7]) );
BUFX20TS U3548 ( .A(n4189), .Y(n4306) );
OAI2BB1X4TS U3549 ( .A0N(n5630), .A1N(n4553), .B0(n4552), .Y(n1255) );
OAI21X2TS U3550 ( .A0(n5746), .A1(n4543), .B0(n4542), .Y(n4546) );
OAI2BB2X4TS U3551 ( .B0(n4340), .B1(n2238), .A0N(n2265), .A1N(n6552), .Y(
n2869) );
NOR2X6TS U3552 ( .A(n4604), .B(n4790), .Y(n4605) );
BUFX12TS U3553 ( .A(n3026), .Y(n2570) );
NAND3X4TS U3554 ( .A(n2670), .B(n2671), .C(n4057), .Y(n2669) );
AND2X8TS U3555 ( .A(n3646), .B(Shift_reg_FLAGS_7_6), .Y(n1979) );
NAND2X8TS U3556 ( .A(n2022), .B(n2019), .Y(n3647) );
AOI22X4TS U3557 ( .A0(n1980), .A1(n4966), .B0(Raw_mant_NRM_SWR[48]), .B1(
n3343), .Y(n3027) );
XOR2X4TS U3558 ( .A(n3028), .B(n4988), .Y(n1980) );
NOR2X6TS U3559 ( .A(n3238), .B(n3237), .Y(n5456) );
NAND2X8TS U3560 ( .A(n6972), .B(n2557), .Y(n4028) );
NOR2X4TS U3561 ( .A(Raw_mant_NRM_SWR[27]), .B(n2432), .Y(n3377) );
INVX4TS U3562 ( .A(sub_x_5_B_34_), .Y(n2683) );
AND2X8TS U3563 ( .A(n2688), .B(n2686), .Y(sub_x_5_B_34_) );
OAI21X4TS U3564 ( .A0(n5948), .A1(n5951), .B0(n5952), .Y(n4391) );
OAI22X4TS U3565 ( .A0(n4698), .A1(n4431), .B0(DmP_mant_SFG_SWR[26]), .B1(
n3070), .Y(n4768) );
NOR2X8TS U3566 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n4816) );
NAND3X8TS U3567 ( .A(n3020), .B(n3016), .C(n3019), .Y(n1232) );
OR2X8TS U3568 ( .A(n5593), .B(n4423), .Y(n2952) );
NOR2X8TS U3569 ( .A(n4823), .B(n4816), .Y(n4893) );
BUFX20TS U3570 ( .A(n3026), .Y(n5239) );
NAND3X8TS U3571 ( .A(n2289), .B(n2628), .C(n2630), .Y(n2627) );
OAI21X4TS U3572 ( .A0(n4139), .A1(n4824), .B0(n4138), .Y(n4705) );
CLKINVX12TS U3573 ( .A(n2839), .Y(n2838) );
AOI21X4TS U3574 ( .A0(n2667), .A1(n3154), .B0(n2293), .Y(n4087) );
NAND2X2TS U3575 ( .A(n6302), .B(DMP_SFG[12]), .Y(n4399) );
NOR2X8TS U3576 ( .A(n1986), .B(n4150), .Y(n2859) );
NOR2X8TS U3577 ( .A(n4152), .B(n5146), .Y(n1986) );
NAND2X8TS U3578 ( .A(n4151), .B(n4961), .Y(n4152) );
NAND2X8TS U3579 ( .A(n2013), .B(n2860), .Y(n4286) );
NAND2X8TS U3580 ( .A(n2636), .B(n2635), .Y(n4495) );
CLKINVX12TS U3581 ( .A(n2643), .Y(n4904) );
OAI21X1TS U3582 ( .A0(n5236), .A1(n5227), .B0(n5226), .Y(n5228) );
NOR2X8TS U3583 ( .A(n1958), .B(n3193), .Y(n5236) );
BUFX12TS U3584 ( .A(intDY_EWSW[3]), .Y(n2565) );
NAND2X2TS U3585 ( .A(n3349), .B(DMP_SFG[36]), .Y(n4650) );
NAND3X6TS U3586 ( .A(n5697), .B(n2808), .C(n2807), .Y(n4484) );
AOI21X4TS U3587 ( .A0(n1927), .A1(n5220), .B0(n5219), .Y(n5223) );
NOR2X8TS U3588 ( .A(n5144), .B(n4152), .Y(n5168) );
XOR2X4TS U3589 ( .A(n5612), .B(n5611), .Y(n5614) );
AOI22X4TS U3590 ( .A0(n4852), .A1(n5925), .B0(Raw_mant_NRM_SWR[29]), .B1(
n5924), .Y(n4853) );
OAI21X2TS U3591 ( .A0(n4805), .A1(n5634), .B0(n4804), .Y(n3065) );
NOR2X2TS U3592 ( .A(n5012), .B(n4770), .Y(n4772) );
NAND3X8TS U3593 ( .A(n1989), .B(n4885), .C(n4647), .Y(n2956) );
NAND3X8TS U3594 ( .A(n2947), .B(n2948), .C(n3110), .Y(n1989) );
INVX2TS U3595 ( .A(n3964), .Y(n1990) );
OR2X8TS U3596 ( .A(n2761), .B(n1990), .Y(n4478) );
NAND3X8TS U3597 ( .A(n3391), .B(n6114), .C(n1993), .Y(n1992) );
NOR2X8TS U3598 ( .A(n3313), .B(DMP_SFG[26]), .Y(n4433) );
NAND2X6TS U3599 ( .A(n3287), .B(n2149), .Y(n3593) );
NOR2X8TS U3600 ( .A(n5591), .B(n4589), .Y(n2621) );
NAND2X8TS U3601 ( .A(n2786), .B(n6472), .Y(n5591) );
BUFX16TS U3602 ( .A(DMP_SFG[27]), .Y(n1994) );
NOR2X8TS U3603 ( .A(n2340), .B(n4498), .Y(n2776) );
INVX8TS U3604 ( .A(n4020), .Y(n6832) );
BUFX6TS U3605 ( .A(n6395), .Y(n1997) );
NAND2X8TS U3606 ( .A(n5054), .B(n5701), .Y(n2694) );
NAND4X6TS U3607 ( .A(n2692), .B(n2689), .C(n2691), .D(n2696), .Y(n2688) );
BUFX4TS U3608 ( .A(n3157), .Y(n2862) );
NAND2X8TS U3609 ( .A(n3140), .B(n3125), .Y(n3127) );
CLKBUFX2TS U3610 ( .A(n6059), .Y(n1998) );
NAND3X8TS U3611 ( .A(n2001), .B(n2000), .C(n1999), .Y(n1230) );
INVX8TS U3612 ( .A(n4409), .Y(n5525) );
INVX12TS U3613 ( .A(n2002), .Y(n3156) );
NAND2X8TS U3614 ( .A(n4600), .B(n3148), .Y(n2002) );
NOR2X6TS U3615 ( .A(n4653), .B(n5112), .Y(n4655) );
BUFX16TS U3616 ( .A(n2275), .Y(n2085) );
BUFX6TS U3617 ( .A(Raw_mant_NRM_SWR[21]), .Y(n2003) );
OAI21X4TS U3618 ( .A0(n2005), .A1(n5736), .B0(n2004), .Y(n1211) );
MX2X4TS U3619 ( .A(n5679), .B(DmP_mant_SFG_SWR[38]), .S0(n2489), .Y(n1118)
);
OAI21X4TS U3620 ( .A0(n3541), .A1(n3540), .B0(n3539), .Y(n3547) );
NOR2X8TS U3621 ( .A(n3025), .B(n2768), .Y(n3152) );
NAND2X8TS U3622 ( .A(n3171), .B(n4599), .Y(n3025) );
AOI22X4TS U3623 ( .A0(n4950), .A1(n5639), .B0(Raw_mant_NRM_SWR[34]), .B1(
n3343), .Y(n4951) );
NOR2X8TS U3624 ( .A(n6198), .B(shift_value_SHT2_EWR[5]), .Y(n3958) );
OAI21X4TS U3625 ( .A0(n5525), .A1(n4548), .B0(n4547), .Y(n4550) );
NAND2X8TS U3626 ( .A(n3235), .B(n3236), .Y(n2846) );
NAND2X8TS U3627 ( .A(n2552), .B(n5131), .Y(n3124) );
NAND2X8TS U3628 ( .A(n2008), .B(n2950), .Y(n4884) );
NAND4X8TS U3629 ( .A(n2952), .B(n2951), .C(n4430), .D(n4812), .Y(n2008) );
NOR2X6TS U3630 ( .A(n3507), .B(n3508), .Y(n2028) );
AOI22X4TS U3631 ( .A0(n4899), .A1(n5626), .B0(Raw_mant_NRM_SWR[25]), .B1(
n5030), .Y(n4900) );
OAI21X2TS U3632 ( .A0(n5068), .A1(n5062), .B0(n5063), .Y(n4895) );
AOI21X4TS U3633 ( .A0(n2506), .A1(n4896), .B0(n4895), .Y(n4898) );
AND2X4TS U3634 ( .A(n2553), .B(n1741), .Y(n2051) );
OAI21X4TS U3635 ( .A0(add_x_6_n401), .A1(n4722), .B0(n3135), .Y(n3134) );
NAND2X8TS U3636 ( .A(LZD_output_NRM2_EW[4]), .B(n2275), .Y(n2091) );
NAND2X8TS U3637 ( .A(n4080), .B(n2560), .Y(n2568) );
CLKINVX12TS U3638 ( .A(n2089), .Y(n2849) );
NOR2X8TS U3639 ( .A(n2566), .B(n2564), .Y(n2290) );
BUFX6TS U3640 ( .A(n5948), .Y(n2009) );
NOR2X6TS U3641 ( .A(n3292), .B(intDY_EWSW[46]), .Y(n2817) );
NAND2X4TS U3642 ( .A(n2606), .B(n2603), .Y(n2602) );
NOR2X6TS U3643 ( .A(n3345), .B(DMP_SFG[21]), .Y(n5058) );
INVX2TS U3644 ( .A(n5671), .Y(n2010) );
OR2X8TS U3645 ( .A(n2601), .B(n2010), .Y(n6994) );
NAND3X8TS U3646 ( .A(n3908), .B(n6644), .C(n3907), .Y(n1723) );
NAND3X6TS U3647 ( .A(n2568), .B(n2569), .C(n1945), .Y(n2482) );
NAND3X8TS U3648 ( .A(n2284), .B(n2667), .C(n2560), .Y(n2569) );
NOR2X8TS U3649 ( .A(exp_rslt_NRM2_EW1[9]), .B(n2330), .Y(n2571) );
NOR2X8TS U3650 ( .A(n2426), .B(DMP_SFG[0]), .Y(n5918) );
NOR2X8TS U3651 ( .A(n2428), .B(n3099), .Y(n2630) );
BUFX6TS U3652 ( .A(n4306), .Y(n2012) );
BUFX20TS U3653 ( .A(n2994), .Y(n3845) );
OAI21X4TS U3654 ( .A0(n3494), .A1(n3495), .B0(n3493), .Y(n3496) );
NAND2X4TS U3655 ( .A(n4295), .B(n1988), .Y(n3787) );
NOR2X6TS U3656 ( .A(n3156), .B(n2454), .Y(n3079) );
OA21X4TS U3657 ( .A0(n3603), .A1(n3602), .B0(n3601), .Y(n2114) );
OAI21X4TS U3658 ( .A0(n6918), .A1(n1922), .B0(n2014), .Y(n1141) );
NOR2X8TS U3659 ( .A(n3296), .B(intDY_EWSW[10]), .Y(n3472) );
NOR2X6TS U3660 ( .A(n4417), .B(n4420), .Y(n3116) );
NOR2X2TS U3661 ( .A(n5022), .B(n5024), .Y(n5027) );
NAND2X4TS U3662 ( .A(n5652), .B(n5647), .Y(n4320) );
AOI22X4TS U3663 ( .A0(n5031), .A1(n5527), .B0(Raw_mant_NRM_SWR[30]), .B1(
n5030), .Y(n5032) );
NAND2X2TS U3664 ( .A(n3347), .B(DMP_SFG[28]), .Y(n4435) );
OR2X8TS U3665 ( .A(n6059), .B(add_x_6_n526), .Y(n2369) );
NOR2X8TS U3666 ( .A(n5687), .B(n3369), .Y(n2635) );
NAND2X8TS U3667 ( .A(n3172), .B(n4508), .Y(n5687) );
INVX6TS U3668 ( .A(n3171), .Y(n2647) );
NAND2X2TS U3669 ( .A(n4389), .B(n5189), .Y(n4006) );
NOR2X4TS U3670 ( .A(n3351), .B(DMP_SFG[14]), .Y(n4420) );
OR2X8TS U3671 ( .A(n5456), .B(n3144), .Y(n3143) );
BUFX6TS U3672 ( .A(n1119), .Y(n2016) );
NAND3X6TS U3673 ( .A(n2795), .B(intDY_EWSW[2]), .C(n3302), .Y(n2789) );
NAND2X2TS U3674 ( .A(n4307), .B(intDY_EWSW[16]), .Y(n4259) );
NAND2X8TS U3675 ( .A(n2570), .B(n3223), .Y(n3222) );
AO21X4TS U3676 ( .A0(n3506), .A1(n3505), .B0(n3504), .Y(n2027) );
NOR2X8TS U3677 ( .A(n2573), .B(Raw_mant_NRM_SWR[35]), .Y(n5692) );
AOI21X4TS U3678 ( .A0(n4424), .A1(n1982), .B0(n4423), .Y(n4729) );
NOR2X8TS U3679 ( .A(n2132), .B(DMP_SFG[17]), .Y(n5594) );
OR2X8TS U3680 ( .A(n6397), .B(n2224), .Y(n3923) );
NAND2X4TS U3681 ( .A(n5000), .B(n5003), .Y(n5006) );
OR2X4TS U3682 ( .A(n6429), .B(n2228), .Y(n3937) );
NAND2X2TS U3683 ( .A(n4640), .B(n5702), .Y(n2913) );
XOR2X4TS U3684 ( .A(n4062), .B(n2095), .Y(n2440) );
NAND2X4TS U3685 ( .A(n4306), .B(intDY_EWSW[37]), .Y(n3824) );
NAND2X4TS U3686 ( .A(n4518), .B(n5716), .Y(n4047) );
OAI21X4TS U3687 ( .A0(add_x_6_n343), .A1(n4777), .B0(n4781), .Y(n4842) );
NAND2X8TS U3688 ( .A(DmP_mant_SFG_SWR[26]), .B(n2436), .Y(n4777) );
OR2X8TS U3689 ( .A(n2273), .B(n2242), .Y(n3924) );
NAND2X4TS U3690 ( .A(n2908), .B(n4613), .Y(n2907) );
AND2X6TS U3691 ( .A(n5487), .B(n5647), .Y(n2342) );
OR2X8TS U3692 ( .A(n2495), .B(n4387), .Y(n2946) );
NAND2X4TS U3693 ( .A(n3256), .B(n3259), .Y(n1227) );
AOI21X4TS U3694 ( .A0(n3234), .A1(n4863), .B0(n4862), .Y(n4865) );
BUFX12TS U3695 ( .A(n6407), .Y(n2017) );
NAND2X2TS U3696 ( .A(n6408), .B(n6511), .Y(n3982) );
AOI2BB2X4TS U3697 ( .B0(n6585), .B1(n6584), .A0N(n4340), .A1N(n2236), .Y(
n4339) );
NOR2X8TS U3698 ( .A(n2018), .B(n3644), .Y(n3646) );
AOI21X4TS U3699 ( .A0(n2021), .A1(n2024), .B0(n2020), .Y(n2019) );
OAI21X4TS U3700 ( .A0(n3550), .A1(n3549), .B0(n3548), .Y(n2020) );
OAI21X4TS U3701 ( .A0(n3529), .A1(n3528), .B0(n3527), .Y(n2021) );
NAND2X8TS U3702 ( .A(n2025), .B(n1947), .Y(n2022) );
NOR2X8TS U3703 ( .A(n3515), .B(n3549), .Y(n2024) );
NAND2X8TS U3704 ( .A(n2029), .B(n2026), .Y(n2025) );
NOR2X8TS U3705 ( .A(n2027), .B(n2028), .Y(n2026) );
NAND2X6TS U3706 ( .A(n2031), .B(n2030), .Y(n2029) );
OAI21X4TS U3707 ( .A0(n3489), .A1(n3488), .B0(n3487), .Y(n2031) );
NOR2X8TS U3708 ( .A(n3303), .B(intDY_EWSW[17]), .Y(n3516) );
NOR2X8TS U3709 ( .A(n3310), .B(intDY_EWSW[19]), .Y(n2040) );
NOR2X6TS U3710 ( .A(n1121), .B(n1508), .Y(n6026) );
NAND2X4TS U3711 ( .A(n1121), .B(n1508), .Y(n6031) );
NAND3X8TS U3712 ( .A(n4520), .B(n4519), .C(n4521), .Y(n1121) );
AOI21X4TS U3713 ( .A0(n2038), .A1(n3517), .B0(n2035), .Y(n3529) );
OAI22X4TS U3714 ( .A0(n2040), .A1(n2037), .B0(n2036), .B1(n1944), .Y(n2035)
);
OAI22X4TS U3715 ( .A0(n3516), .A1(n2039), .B0(intDX_EWSW[17]), .B1(n2307),
.Y(n2038) );
NAND3X8TS U3716 ( .A(n2580), .B(n2043), .C(n2041), .Y(n6952) );
NAND2X8TS U3717 ( .A(n4041), .B(n4315), .Y(n2045) );
NAND2X4TS U3718 ( .A(n2055), .B(n2046), .Y(n4518) );
NOR2X4TS U3719 ( .A(n2051), .B(n2047), .Y(n2046) );
INVX2TS U3720 ( .A(n5544), .Y(n2053) );
AOI22X4TS U3721 ( .A0(n1745), .A1(n4388), .B0(n1733), .B1(n4315), .Y(n2055)
);
XOR2X4TS U3722 ( .A(n2085), .B(n4062), .Y(n2121) );
NAND3X8TS U3723 ( .A(n2058), .B(n2057), .C(n2056), .Y(n2323) );
NAND3X8TS U3724 ( .A(n2936), .B(n3440), .C(n3441), .Y(n1748) );
NAND2X8TS U3725 ( .A(n2718), .B(n3448), .Y(n1736) );
AOI22X4TS U3726 ( .A0(n1740), .A1(n2479), .B0(n1744), .B1(n2490), .Y(n2058)
);
NAND2X8TS U3727 ( .A(n3031), .B(n2059), .Y(n1744) );
NOR2X8TS U3728 ( .A(n2061), .B(n2060), .Y(n2059) );
AND3X8TS U3729 ( .A(n2063), .B(n3445), .C(n3447), .Y(n2062) );
AOI21X4TS U3730 ( .A0(n2721), .A1(n2071), .B0(n2720), .Y(n2065) );
OAI21X4TS U3731 ( .A0(n2072), .A1(n2070), .B0(n2067), .Y(n6045) );
NAND3BX4TS U3732 ( .AN(n3457), .B(n2724), .C(n3459), .Y(n4562) );
NAND4X8TS U3733 ( .A(n2745), .B(n2314), .C(n2074), .D(n2075), .Y(n4566) );
AOI21X4TS U3734 ( .A0(n4566), .A1(n2518), .B0(n2077), .Y(n6966) );
NAND2X8TS U3735 ( .A(n2079), .B(n3915), .Y(n5497) );
AND3X8TS U3736 ( .A(n3916), .B(n3917), .C(n3914), .Y(n2079) );
NAND3BX4TS U3737 ( .AN(n1973), .B(n3883), .C(n3882), .Y(n2080) );
NOR2X8TS U3738 ( .A(n6200), .B(n3461), .Y(n3878) );
NAND2X8TS U3739 ( .A(n2082), .B(n2081), .Y(n5666) );
AOI21X4TS U3740 ( .A0(n2479), .A1(n1751), .B0(n2373), .Y(n2081) );
NOR2X8TS U3741 ( .A(n2743), .B(n2335), .Y(n6784) );
AOI21X4TS U3742 ( .A0(n6969), .A1(n5557), .B0(n5201), .Y(n2084) );
XOR2X4TS U3743 ( .A(n2091), .B(n2085), .Y(n2086) );
NAND2X8TS U3744 ( .A(n2087), .B(n2870), .Y(n2851) );
NAND2X8TS U3745 ( .A(n5615), .B(n1972), .Y(n2087) );
NAND3X8TS U3746 ( .A(n2088), .B(n2871), .C(n2680), .Y(n5615) );
AND2X8TS U3747 ( .A(n2682), .B(n2676), .Y(n2088) );
OR2X8TS U3748 ( .A(n4063), .B(n3091), .Y(n2483) );
OR2X8TS U3749 ( .A(n2089), .B(n1948), .Y(n3091) );
NAND2X8TS U3750 ( .A(n2085), .B(n6199), .Y(n2089) );
NOR2X8TS U3751 ( .A(n2090), .B(DMP_exp_NRM2_EW[4]), .Y(n4063) );
XNOR2X4TS U3752 ( .A(n2091), .B(n2275), .Y(n2090) );
NAND2X8TS U3753 ( .A(n1967), .B(n2092), .Y(n2485) );
NOR2X8TS U3754 ( .A(n3157), .B(n2301), .Y(n2093) );
NOR3X8TS U3755 ( .A(n3077), .B(n5683), .C(n3081), .Y(n3157) );
NAND2X8TS U3756 ( .A(n2094), .B(n2313), .Y(n3179) );
NAND2X8TS U3757 ( .A(n4605), .B(n2784), .Y(n2094) );
NOR2X8TS U3758 ( .A(n2626), .B(n2582), .Y(n2784) );
NOR2X2TS U3759 ( .A(n2095), .B(DMP_exp_NRM2_EW[9]), .Y(n4092) );
NOR2X2TS U3760 ( .A(n2095), .B(DMP_exp_NRM2_EW[8]), .Y(n4093) );
AOI21X4TS U3761 ( .A0(n2095), .A1(n6201), .B0(DMP_exp_NRM2_EW[1]), .Y(n4068)
);
NAND2X8TS U3762 ( .A(n2365), .B(n2095), .Y(n4067) );
XOR2X4TS U3763 ( .A(n2563), .B(n2095), .Y(n3168) );
INVX16TS U3764 ( .A(n3092), .Y(n2095) );
AND2X8TS U3765 ( .A(n2152), .B(intDX_EWSW[33]), .Y(n3573) );
NOR2X6TS U3766 ( .A(n2399), .B(n2098), .Y(n3591) );
OAI22X4TS U3767 ( .A0(n2396), .A1(n2098), .B0(intDX_EWSW[43]), .B1(n2303),
.Y(n2395) );
NOR2X8TS U3768 ( .A(n3286), .B(intDY_EWSW[43]), .Y(n2098) );
BUFX20TS U3769 ( .A(n2582), .Y(n2102) );
NOR3X8TS U3770 ( .A(n4360), .B(n4790), .C(n2102), .Y(n2583) );
NAND3X8TS U3771 ( .A(n4357), .B(n4356), .C(n4358), .Y(n2582) );
NAND3X8TS U3772 ( .A(n2105), .B(n3145), .C(n2103), .Y(n1138) );
NOR2X8TS U3773 ( .A(n2112), .B(n2111), .Y(n3180) );
NAND4BX4TS U3774 ( .AN(Raw_mant_NRM_SWR[23]), .B(n6109), .C(n6260), .D(n6243), .Y(n2111) );
CLKINVX12TS U3775 ( .A(n3645), .Y(n2863) );
NAND2X8TS U3776 ( .A(n2118), .B(n2115), .Y(n3645) );
AOI21X4TS U3777 ( .A0(n2117), .A1(n3643), .B0(n2116), .Y(n2115) );
OAI21X4TS U3778 ( .A0(n3626), .A1(n3625), .B0(n3624), .Y(n2117) );
CLKINVX6TS U3779 ( .A(n3644), .Y(n2119) );
OAI2BB1X4TS U3780 ( .A0N(n3604), .A1N(n3605), .B0(n2114), .Y(n2120) );
NOR2X8TS U3781 ( .A(n3363), .B(DMP_SFG[1]), .Y(n5949) );
NOR2X8TS U3782 ( .A(n2121), .B(DMP_exp_NRM2_EW[5]), .Y(n2295) );
NOR2X8TS U3783 ( .A(n2122), .B(n3092), .Y(n4062) );
AOI21X4TS U3784 ( .A0(n5716), .A1(n5497), .B0(n2124), .Y(n2123) );
NAND2X8TS U3785 ( .A(n2127), .B(n2126), .Y(n4609) );
NAND2X8TS U3786 ( .A(n2589), .B(n3894), .Y(n1719) );
AND3X8TS U3787 ( .A(n4173), .B(n2588), .C(n2586), .Y(n2127) );
OAI21X4TS U3788 ( .A0(n6985), .A1(n2414), .B0(n2128), .Y(n1108) );
MXI2X4TS U3789 ( .A(n6178), .B(n2445), .S0(n5884), .Y(n1562) );
NAND4X6TS U3790 ( .A(n4032), .B(n4031), .C(n4030), .D(n4029), .Y(n1705) );
AOI2BB2X2TS U3791 ( .B0(n6536), .B1(n2250), .A0N(n6535), .A1N(n2232), .Y(
n4032) );
AOI2BB2X4TS U3792 ( .B0(n6554), .B1(n2250), .A0N(n6553), .A1N(n2240), .Y(
n4037) );
AOI2BB2X4TS U3793 ( .B0(n6547), .B1(n2250), .A0N(n6546), .A1N(n2241), .Y(
n3995) );
OR2X8TS U3794 ( .A(n4423), .B(n4424), .Y(n2951) );
NAND2X4TS U3795 ( .A(n2480), .B(n1721), .Y(n4043) );
AOI21X4TS U3796 ( .A0(n4590), .A1(n5807), .B0(n5613), .Y(n4591) );
BUFX20TS U3797 ( .A(n4286), .Y(n2994) );
OAI22X1TS U3798 ( .A0(n2249), .A1(n6648), .B0(n1935), .B1(n6647), .Y(
final_result_ieee[62]) );
NOR2X4TS U3799 ( .A(n3558), .B(n3573), .Y(n3560) );
NOR2X6TS U3800 ( .A(n2134), .B(n6317), .Y(n2133) );
NAND2X2TS U3801 ( .A(n3809), .B(intDX_EWSW[56]), .Y(n3655) );
NAND2X2TS U3802 ( .A(n5349), .B(intDX_EWSW[61]), .Y(n4385) );
NAND2X2TS U3803 ( .A(n4121), .B(intDX_EWSW[60]), .Y(n3679) );
NAND3X4TS U3804 ( .A(n4185), .B(n4184), .C(n4183), .Y(n1396) );
NAND3X4TS U3805 ( .A(n4257), .B(n4256), .C(n4255), .Y(n1354) );
NAND3X4TS U3806 ( .A(n4266), .B(n4265), .C(n4264), .Y(n1342) );
NAND3X4TS U3807 ( .A(n4275), .B(n4274), .C(n4273), .Y(n1360) );
NAND3X4TS U3808 ( .A(n4291), .B(n4290), .C(n4289), .Y(n1356) );
NAND2X2TS U3809 ( .A(n3828), .B(n1987), .Y(n4101) );
OR2X4TS U3810 ( .A(n3307), .B(n2818), .Y(n3820) );
OAI21X2TS U3811 ( .A0(n6966), .A1(n2414), .B0(n2744), .Y(n1115) );
AND2X8TS U3812 ( .A(intDX_EWSW[39]), .B(n2136), .Y(n3583) );
NAND2X6TS U3813 ( .A(n4315), .B(n1717), .Y(n4042) );
OR2X4TS U3814 ( .A(n2818), .B(n2138), .Y(n4206) );
NAND2X2TS U3815 ( .A(n2819), .B(intDX_EWSW[37]), .Y(n3823) );
NAND2X2TS U3816 ( .A(n1920), .B(intDX_EWSW[48]), .Y(n3761) );
NAND2X2TS U3817 ( .A(n3846), .B(intDX_EWSW[44]), .Y(n3789) );
NAND2X2TS U3818 ( .A(n3828), .B(intDX_EWSW[47]), .Y(n3814) );
NAND2X4TS U3819 ( .A(n3288), .B(n2565), .Y(n2788) );
NOR2X8TS U3820 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n4886) );
NOR2X8TS U3821 ( .A(n3284), .B(intDY_EWSW[5]), .Y(n3480) );
NAND2X2TS U3822 ( .A(n2325), .B(n6262), .Y(n4414) );
NOR2X6TS U3823 ( .A(n3305), .B(n2154), .Y(n3555) );
INVX16TS U3824 ( .A(n2649), .Y(n2818) );
INVX12TS U3825 ( .A(n3178), .Y(n3177) );
NAND2X2TS U3826 ( .A(n3846), .B(intDX_EWSW[3]), .Y(n3730) );
NAND2X2TS U3827 ( .A(n3828), .B(intDX_EWSW[8]), .Y(n3688) );
NAND2X2TS U3828 ( .A(n3846), .B(intDX_EWSW[5]), .Y(n3706) );
NAND2X2TS U3829 ( .A(n6405), .B(n6516), .Y(n2147) );
NAND2X6TS U3830 ( .A(n6858), .B(n2304), .Y(n2385) );
NOR2X8TS U3831 ( .A(n6029), .B(n6028), .Y(n6048) );
AOI21X4TS U3832 ( .A0(n5666), .A1(n5701), .B0(n3004), .Y(n3003) );
NOR2X6TS U3833 ( .A(n3321), .B(intDY_EWSW[42]), .Y(n2399) );
NAND2X4TS U3834 ( .A(n3321), .B(intDY_EWSW[42]), .Y(n2396) );
NAND2X4TS U3835 ( .A(n2604), .B(n2599), .Y(n2598) );
NAND2X4TS U3836 ( .A(n1727), .B(n4388), .Y(n2604) );
CLKINVX12TS U3837 ( .A(intDY_EWSW[44]), .Y(n2148) );
INVX16TS U3838 ( .A(n2148), .Y(n2149) );
MX2X2TS U3839 ( .A(Data_Y[44]), .B(n2149), .S0(n5899), .Y(n1774) );
AND2X8TS U3840 ( .A(intDX_EWSW[35]), .B(n2150), .Y(n3576) );
NOR2X8TS U3841 ( .A(n2436), .B(DmP_mant_SFG_SWR[26]), .Y(n4778) );
OAI21X4TS U3842 ( .A0(n3611), .A1(n3610), .B0(n3609), .Y(n3612) );
CLKMX2X2TS U3843 ( .A(Data_Y[39]), .B(intDY_EWSW[39]), .S0(n5899), .Y(n1779)
);
XNOR2X1TS U3844 ( .A(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n5366) );
NAND2X4TS U3845 ( .A(n1966), .B(n2325), .Y(n7009) );
INVX16TS U3846 ( .A(n2290), .Y(n2325) );
NAND2X4TS U3847 ( .A(n2998), .B(n5558), .Y(n2997) );
NAND2X4TS U3848 ( .A(n6972), .B(n5557), .Y(n2998) );
NOR2X8TS U3849 ( .A(n6120), .B(n6200), .Y(n3885) );
BUFX20TS U3850 ( .A(n3885), .Y(n5561) );
NAND2X4TS U3851 ( .A(n3885), .B(bit_shift_SHT2), .Y(n4023) );
NOR2X6TS U3852 ( .A(n3555), .B(n3583), .Y(n3585) );
NAND2X4TS U3853 ( .A(n1716), .B(n5563), .Y(n2679) );
NAND4X8TS U3854 ( .A(n3411), .B(n3410), .C(n3409), .D(n3408), .Y(n1716) );
CLKINVX12TS U3855 ( .A(intDY_EWSW[38]), .Y(n2153) );
INVX16TS U3856 ( .A(n2153), .Y(n2154) );
AOI2BB2X4TS U3857 ( .B0(n6524), .B1(n6525), .A0N(n2099), .A1N(n2202), .Y(
n2928) );
INVX16TS U3858 ( .A(n4039), .Y(n2502) );
NAND2X1TS U3859 ( .A(n5848), .B(n2157), .Y(n5837) );
NAND2X4TS U3860 ( .A(n6392), .B(n2158), .Y(n3466) );
NAND2X1TS U3861 ( .A(n6391), .B(n2158), .Y(n4004) );
NAND2X2TS U3862 ( .A(n5832), .B(n2159), .Y(n5265) );
NAND2X2TS U3863 ( .A(n5848), .B(n2160), .Y(n5845) );
NAND2X2TS U3864 ( .A(n5832), .B(n2161), .Y(n5253) );
NAND2X2TS U3865 ( .A(n5832), .B(n2165), .Y(n5261) );
NAND2X2TS U3866 ( .A(n5832), .B(n2166), .Y(n5257) );
NAND2X2TS U3867 ( .A(n5832), .B(n2167), .Y(n5829) );
NAND2X2TS U3868 ( .A(n5832), .B(n2168), .Y(n5833) );
NAND2X2TS U3869 ( .A(n5832), .B(n2170), .Y(n5259) );
NAND2X2TS U3870 ( .A(n5832), .B(n2171), .Y(n5263) );
NAND2X2TS U3871 ( .A(n5832), .B(n2172), .Y(n5269) );
NAND2X1TS U3872 ( .A(n6996), .B(n2173), .Y(n5765) );
NAND2X2TS U3873 ( .A(n5832), .B(n2174), .Y(n5267) );
NAND2X1TS U3874 ( .A(n5848), .B(n2175), .Y(n5849) );
NAND2X1TS U3875 ( .A(n6996), .B(n2176), .Y(n5767) );
NAND2X1TS U3876 ( .A(n6996), .B(n2177), .Y(n5769) );
NAND2X2TS U3877 ( .A(n5848), .B(n2178), .Y(n5839) );
AOI2BB2X2TS U3878 ( .B0(n2180), .B1(n6660), .A0N(n5763), .A1N(n6659), .Y(
final_result_ieee[54]) );
AOI2BB2X2TS U3879 ( .B0(n2180), .B1(n6710), .A0N(n5763), .A1N(n6709), .Y(
final_result_ieee[52]) );
AOI2BB2X1TS U3880 ( .B0(n6597), .B1(n6596), .A0N(n6595), .A1N(n2181), .Y(
n4054) );
NAND2X1TS U3881 ( .A(n6996), .B(n2182), .Y(n5773) );
OAI22X2TS U3882 ( .A0(n2547), .A1(n6706), .B0(n2186), .B1(n6705), .Y(
final_result_ieee[4]) );
AOI2BB2X2TS U3883 ( .B0(n2187), .B1(n6682), .A0N(n5763), .A1N(n6681), .Y(
final_result_ieee[53]) );
OA21X2TS U3884 ( .A0(n1935), .A1(n6463), .B0(n2188), .Y(overflow_flag) );
OR2X4TS U3885 ( .A(n6442), .B(n2189), .Y(n3934) );
OR2X8TS U3886 ( .A(n5661), .B(n2190), .Y(n3865) );
OR2X4TS U3887 ( .A(n4001), .B(n2191), .Y(n3972) );
OR2X4TS U3888 ( .A(n4000), .B(n2191), .Y(n3429) );
OAI22X4TS U3889 ( .A0(n3996), .A1(n2231), .B0(n6433), .B1(n6432), .Y(n3881)
);
OAI22X4TS U3890 ( .A0(n6436), .A1(n6435), .B0(n2185), .B1(n6398), .Y(n2717)
);
OAI22X2TS U3891 ( .A0(n6451), .A1(n2247), .B0(n6450), .B1(n6449), .Y(n4005)
);
BUFX20TS U3892 ( .A(n6398), .Y(n3996) );
OR2X6TS U3893 ( .A(n4033), .B(n2193), .Y(n3981) );
OR2X4TS U3894 ( .A(n6397), .B(n2193), .Y(n3927) );
AOI2BB2X2TS U3895 ( .B0(n6573), .B1(n6572), .A0N(n6571), .A1N(n2197), .Y(
n3415) );
OR2X2TS U3896 ( .A(n6395), .B(n2197), .Y(n4336) );
AOI2BB2X4TS U3897 ( .B0(n6570), .B1(n6569), .A0N(n6568), .A1N(n2199), .Y(
n3442) );
AOI2BB2X4TS U3898 ( .B0(n6518), .B1(n2258), .A0N(n6517), .A1N(n2201), .Y(
n3902) );
OR2X2TS U3899 ( .A(n6412), .B(n2201), .Y(n3984) );
OR2X4TS U3900 ( .A(n6428), .B(n2202), .Y(n3425) );
NOR2BX4TS U3901 ( .AN(n2203), .B(n2207), .Y(n2921) );
BUFX16TS U3902 ( .A(n6396), .Y(n4000) );
OAI2BB2X4TS U3903 ( .B0(n2207), .B1(n6586), .A0N(n6588), .A1N(n6587), .Y(
n2204) );
NOR2BX4TS U3904 ( .AN(n2206), .B(n2207), .Y(n2205) );
OR2X4TS U3905 ( .A(n2260), .B(n2208), .Y(n3864) );
OR2X2TS U3906 ( .A(n6443), .B(n2208), .Y(n3940) );
AOI2BB2X2TS U3907 ( .B0(n6576), .B1(n6575), .A0N(n4340), .A1N(n2209), .Y(
n4331) );
OR2X2TS U3908 ( .A(n2262), .B(n2213), .Y(n4051) );
OR2X4TS U3909 ( .A(n4033), .B(n2214), .Y(n3977) );
OR2X4TS U3910 ( .A(n6395), .B(n2217), .Y(n3939) );
OR2X2TS U3911 ( .A(n6422), .B(n2218), .Y(n3992) );
AOI2BB2X2TS U3912 ( .B0(n6607), .B1(n6606), .A0N(n6398), .A1N(n2219), .Y(
n3983) );
OR2X2TS U3913 ( .A(n6418), .B(n2219), .Y(n3899) );
OR2X4TS U3914 ( .A(n5661), .B(n2220), .Y(n3892) );
AOI2BB2X2TS U3915 ( .B0(n6561), .B1(n6560), .A0N(n6559), .A1N(n2222), .Y(
n3975) );
OR2X2TS U3916 ( .A(n6431), .B(n2222), .Y(n3920) );
OR2X2TS U3917 ( .A(n6427), .B(n2223), .Y(n3875) );
OR2X6TS U3918 ( .A(n2273), .B(n2227), .Y(n3433) );
OR2X2TS U3919 ( .A(n6420), .B(n2227), .Y(n3976) );
OR2X2TS U3920 ( .A(n6425), .B(n2228), .Y(n3859) );
OR2X2TS U3921 ( .A(n6440), .B(n2232), .Y(n4333) );
OR2X2TS U3922 ( .A(n6421), .B(n2232), .Y(n4165) );
OR2X2TS U3923 ( .A(n6424), .B(n2234), .Y(n4034) );
OR2X4TS U3924 ( .A(n4001), .B(n2237), .Y(n3416) );
OR2X2TS U3925 ( .A(n6409), .B(n2239), .Y(n3988) );
OR2X2TS U3926 ( .A(n6441), .B(n2240), .Y(n5719) );
OR2X2TS U3927 ( .A(n6419), .B(n2240), .Y(n5662) );
OR2X2TS U3928 ( .A(n6437), .B(n2241), .Y(n4337) );
OR2X2TS U3929 ( .A(n2260), .B(n2241), .Y(n3903) );
OR2X2TS U3930 ( .A(n6406), .B(n2242), .Y(n3874) );
OR2X2TS U3931 ( .A(n2262), .B(n2244), .Y(n4029) );
OR2X2TS U3932 ( .A(n6434), .B(n2245), .Y(n4329) );
AOI2BB2X2TS U3933 ( .B0(n6565), .B1(n2258), .A0N(n5660), .A1N(n2246), .Y(
n3894) );
OR2X2TS U3934 ( .A(n2273), .B(n2246), .Y(n3409) );
OR2X2TS U3935 ( .A(n2260), .B(n2246), .Y(n3980) );
AOI2BB2X4TS U3936 ( .B0(n2252), .B1(n2216), .A0N(n2253), .A1N(n2254), .Y(
n3446) );
AOI2BB2X4TS U3937 ( .B0(n2255), .B1(n2256), .A0N(n2099), .A1N(n2189), .Y(
n2309) );
AOI2BB2X1TS U3938 ( .B0(n6521), .B1(n2258), .A0N(n5660), .A1N(n2184), .Y(
n5665) );
AOI2BB2X4TS U3939 ( .B0(n6600), .B1(n2258), .A0N(n3996), .A1N(n2239), .Y(
n3908) );
NAND2X8TS U3940 ( .A(n2652), .B(n6414), .Y(n4589) );
INVX2TS U3941 ( .A(n5909), .Y(n2259) );
OAI2BB1X4TS U3942 ( .A0N(n6482), .A1N(n6483), .B0(n6481), .Y(n5909) );
NAND4X8TS U3943 ( .A(n4042), .B(n4044), .C(n4045), .D(n4043), .Y(n4516) );
NAND2X2TS U3944 ( .A(n2480), .B(n1739), .Y(n4175) );
NAND2BX2TS U3945 ( .AN(n2260), .B(n2221), .Y(n3872) );
NAND2BX2TS U3946 ( .AN(n2261), .B(n2230), .Y(n3997) );
BUFX12TS U3947 ( .A(n6397), .Y(n2262) );
AOI21X4TS U3948 ( .A0(n6510), .A1(n6400), .B0(n2717), .Y(n2716) );
NAND2X2TS U3949 ( .A(n6407), .B(n6444), .Y(n3876) );
AND2X4TS U3950 ( .A(n6407), .B(n6487), .Y(n2311) );
NAND2X1TS U3951 ( .A(n2017), .B(n6509), .Y(n3897) );
NAND2X1TS U3952 ( .A(n2017), .B(n6498), .Y(n3905) );
NAND4X2TS U3953 ( .A(n4168), .B(n4167), .C(n4166), .D(n4165), .Y(n1703) );
NAND2X2TS U3954 ( .A(n2017), .B(n6492), .Y(n3893) );
NAND2X6TS U3955 ( .A(n1745), .B(n2478), .Y(n2922) );
NAND2X2TS U3956 ( .A(n6408), .B(n6447), .Y(n3971) );
NAND4X4TS U3957 ( .A(n3975), .B(n3974), .C(n3973), .D(n3972), .Y(n1733) );
NAND2X1TS U3958 ( .A(n6408), .B(n6501), .Y(n3986) );
NAND2X2TS U3959 ( .A(n6408), .B(n6490), .Y(n3978) );
AOI22X4TS U3960 ( .A0(n6387), .A1(n6439), .B0(n6438), .B1(n2258), .Y(n3863)
);
BUFX16TS U3961 ( .A(n6393), .Y(n4033) );
NAND4X2TS U3962 ( .A(n4339), .B(n4338), .C(n4337), .D(n4336), .Y(n1706) );
NAND4X4TS U3963 ( .A(n4335), .B(n4334), .C(n4333), .D(n4332), .Y(n1702) );
BUFX16TS U3964 ( .A(n6388), .Y(n2273) );
BUFX16TS U3965 ( .A(n6399), .Y(n5661) );
AOI22X4TS U3966 ( .A0(n6592), .A1(n2265), .B0(n2267), .B1(n2233), .Y(n4168)
);
AOI2BB2X4TS U3967 ( .B0(n6520), .B1(n2265), .A0N(n6519), .A1N(n2247), .Y(
n3877) );
AOI2BB2X4TS U3968 ( .B0(n6533), .B1(n6534), .A0N(n6532), .A1N(n2208), .Y(
n2918) );
AOI2BB2X4TS U3969 ( .B0(n6582), .B1(n6581), .A0N(n6580), .A1N(n2214), .Y(
n3431) );
AOI2BB2X4TS U3970 ( .B0(n6541), .B1(n6542), .A0N(n6540), .A1N(n2224), .Y(
n3435) );
NAND4X4TS U3971 ( .A(n4037), .B(n4036), .C(n4035), .D(n4034), .Y(n1701) );
AOI2BB2X2TS U3972 ( .B0(n6609), .B1(n6608), .A0N(n3996), .A1N(n2245), .Y(
n3987) );
AOI2BB2X4TS U3973 ( .B0(n6604), .B1(n6603), .A0N(n3996), .A1N(n2242), .Y(
n3979) );
AOI21X4TS U3974 ( .A0(n6602), .A1(n6601), .B0(n2934), .Y(n2933) );
OAI2BB1X4TS U3975 ( .A0N(n6590), .A1N(n6591), .B0(n2417), .Y(n2416) );
AND2X6TS U3976 ( .A(n5563), .B(n1732), .Y(n2305) );
AOI2BB2X2TS U3977 ( .B0(n6567), .B1(n6566), .A0N(n4340), .A1N(n2237), .Y(
n4345) );
AOI2BB2X4TS U3978 ( .B0(n6551), .B1(n6550), .A0N(n5660), .A1N(n2191), .Y(
n3871) );
AOI2BB2X4TS U3979 ( .B0(n6545), .B1(n6544), .A0N(n4340), .A1N(n2190), .Y(
n3938) );
AOI2BB2X4TS U3980 ( .B0(n6539), .B1(n6538), .A0N(n4340), .A1N(n2229), .Y(
n3427) );
AOI2BB2X4TS U3981 ( .B0(n6530), .B1(n6529), .A0N(n4340), .A1N(n2220), .Y(
n3932) );
AOI2BB2X4TS U3982 ( .B0(n6523), .B1(n6522), .A0N(n4340), .A1N(n2179), .Y(
n3926) );
AOI2BB2X1TS U3983 ( .B0(n6594), .B1(n6593), .A0N(n4340), .A1N(n2213), .Y(
n4335) );
BUFX20TS U3984 ( .A(n2268), .Y(n2265) );
AOI22X4TS U3985 ( .A0(n6557), .A1(n2265), .B0(n2267), .B1(n2226), .Y(n3873)
);
AOI2BB2X4TS U3986 ( .B0(n6558), .B1(n2265), .A0N(n4340), .A1N(n2223), .Y(
n3922) );
AOI2BB2X4TS U3987 ( .B0(n6543), .B1(n2265), .A0N(n5660), .A1N(n2192), .Y(
n3942) );
AOI2BB2X4TS U3988 ( .B0(n6531), .B1(n2265), .A0N(n5660), .A1N(n2215), .Y(
n3861) );
AOI2BB2X2TS U3989 ( .B0(n1929), .B1(n6666), .A0N(n2547), .A1N(n6665), .Y(
final_result_ieee[60]) );
OAI2BB1X2TS U3990 ( .A0N(n6457), .A1N(n1929), .B0(n7011), .Y(
final_result_ieee[63]) );
OAI2BB2X2TS U3991 ( .B0(n2249), .B1(n6672), .A0N(n1929), .A1N(n6671), .Y(
final_result_ieee[31]) );
OAI2BB2X2TS U3992 ( .B0(n2249), .B1(n6611), .A0N(n1929), .A1N(n6610), .Y(
final_result_ieee[3]) );
OAI2BB2X2TS U3993 ( .B0(n2547), .B1(n6617), .A0N(n1929), .A1N(n6616), .Y(
final_result_ieee[48]) );
OR2X6TS U3994 ( .A(n4063), .B(n4061), .Y(n2559) );
NAND2X6TS U3995 ( .A(n2838), .B(n2837), .Y(n2296) );
BUFX20TS U3996 ( .A(n6715), .Y(n2275) );
XOR2X4TS U3997 ( .A(n2281), .B(n4072), .Y(n2276) );
NOR2X8TS U3998 ( .A(shift_value_SHT2_EWR[5]), .B(shift_value_SHT2_EWR[4]),
.Y(n2277) );
INVX16TS U3999 ( .A(n2277), .Y(n3460) );
AND2X8TS U4000 ( .A(n3937), .B(n2278), .Y(n2608) );
NAND2X4TS U4001 ( .A(n2841), .B(n6486), .Y(n2278) );
NAND2X4TS U4002 ( .A(n4640), .B(n1971), .Y(n2878) );
NAND2X4TS U4003 ( .A(n1745), .B(n5505), .Y(n2932) );
NAND2X2TS U4004 ( .A(n6408), .B(n6455), .Y(n3907) );
NAND2X2TS U4005 ( .A(n6408), .B(n6468), .Y(n2935) );
INVX12TS U4006 ( .A(n5168), .Y(n5095) );
INVX16TS U4007 ( .A(n3878), .Y(n2473) );
NOR2X6TS U4008 ( .A(n3523), .B(n2765), .Y(n3525) );
NOR2X4TS U4009 ( .A(n3293), .B(intDY_EWSW[22]), .Y(n2765) );
NOR2X4TS U4010 ( .A(n3115), .B(n5515), .Y(n3113) );
INVX8TS U4011 ( .A(n4568), .Y(n2591) );
OR2X4TS U4012 ( .A(n3285), .B(intDY_EWSW[20]), .Y(n2763) );
NOR2X4TS U4013 ( .A(n5175), .B(n5037), .Y(n4649) );
NAND2X2TS U4014 ( .A(n3166), .B(n2433), .Y(n3165) );
AND2X4TS U4015 ( .A(n6116), .B(Raw_mant_NRM_SWR[27]), .Y(n3167) );
NOR2X4TS U4016 ( .A(n3327), .B(n2436), .Y(n4431) );
NAND2X4TS U4017 ( .A(n4908), .B(Raw_mant_NRM_SWR[30]), .Y(n2970) );
NOR3X6TS U4018 ( .A(n2768), .B(n3025), .C(n4359), .Y(n2803) );
NOR2X4TS U4019 ( .A(DMP_SFG[44]), .B(DmP_mant_SFG_SWR[46]), .Y(n4857) );
NOR2X6TS U4020 ( .A(n5169), .B(add_x_6_n185), .Y(n5094) );
OAI21X2TS U4021 ( .A0(n4642), .A1(n4917), .B0(n4641), .Y(n4643) );
OAI21X2TS U4022 ( .A0(n4761), .A1(n4927), .B0(n4762), .Y(n4142) );
NOR2X2TS U4023 ( .A(n4433), .B(n4773), .Y(n3068) );
NAND2X2TS U4024 ( .A(n2502), .B(n1719), .Y(n2747) );
NOR2X4TS U4025 ( .A(n6111), .B(Raw_mant_NRM_SWR[24]), .Y(n4582) );
NAND2X4TS U4026 ( .A(DmP_mant_SFG_SWR[15]), .B(DMP_SFG[13]), .Y(n4625) );
NAND2X4TS U4027 ( .A(n2632), .B(n3379), .Y(n4909) );
NAND2X4TS U4028 ( .A(n4812), .B(n4430), .Y(n2949) );
OAI21X2TS U4029 ( .A0(n4428), .A1(n5057), .B0(n4427), .Y(n4429) );
AND2X4TS U4030 ( .A(n4599), .B(n4359), .Y(n3170) );
NAND2X2TS U4031 ( .A(n5052), .B(n1971), .Y(n2888) );
NAND2X4TS U4032 ( .A(n2842), .B(n2512), .Y(n2682) );
NAND2X4TS U4033 ( .A(n2876), .B(n1971), .Y(n2680) );
NAND2X2TS U4034 ( .A(n5714), .B(n1971), .Y(n2977) );
NAND2X2TS U4035 ( .A(n1723), .B(n2476), .Y(n4173) );
NAND2X2TS U4036 ( .A(n1726), .B(n4389), .Y(n2624) );
NAND2X2TS U4037 ( .A(n1738), .B(n2523), .Y(n2622) );
AND2X4TS U4038 ( .A(n5506), .B(n5508), .Y(n2617) );
NAND2X2TS U4039 ( .A(n2713), .B(n1735), .Y(n3888) );
AND4X6TS U4040 ( .A(n4325), .B(n4323), .C(n4324), .D(n4326), .Y(n4568) );
NOR2X2TS U4041 ( .A(n3273), .B(intDY_EWSW[4]), .Y(n3475) );
NAND2X4TS U4042 ( .A(n3296), .B(intDY_EWSW[10]), .Y(n3494) );
NOR2X6TS U4043 ( .A(n3469), .B(n2650), .Y(n3505) );
NAND2X2TS U4044 ( .A(n3266), .B(intDY_EWSW[29]), .Y(n3539) );
NOR2X6TS U4045 ( .A(n3544), .B(n2990), .Y(n3546) );
NOR2X4TS U4046 ( .A(n3324), .B(intDY_EWSW[30]), .Y(n2990) );
NOR2X4TS U4047 ( .A(n4926), .B(n4761), .Y(n4143) );
NOR2X4TS U4048 ( .A(n4971), .B(n4665), .Y(n4667) );
NAND2X4TS U4049 ( .A(n4133), .B(n4463), .Y(n3216) );
NOR2X4TS U4050 ( .A(n3348), .B(DMP_SFG[22]), .Y(n4428) );
CLKINVX6TS U4051 ( .A(DmP_mant_SFG_SWR[42]), .Y(n4658) );
NOR2X6TS U4052 ( .A(n5981), .B(n5742), .Y(n4129) );
INVX2TS U4053 ( .A(n6196), .Y(n2294) );
NOR2X4TS U4054 ( .A(n4093), .B(n4092), .Y(n4097) );
NAND2BX2TS U4055 ( .AN(n2280), .B(DMP_exp_NRM2_EW[10]), .Y(n4098) );
NOR2BX2TS U4056 ( .AN(n2280), .B(DMP_exp_NRM2_EW[10]), .Y(n3096) );
AND2X2TS U4057 ( .A(n2003), .B(n6109), .Y(n3186) );
NOR2X4TS U4058 ( .A(n4978), .B(n4795), .Y(n4797) );
NAND2X4TS U4059 ( .A(n4991), .B(n4667), .Y(n4669) );
NOR2X6TS U4060 ( .A(n4857), .B(n4995), .Y(n4983) );
INVX8TS U4061 ( .A(n3202), .Y(n2816) );
NAND2X4TS U4062 ( .A(n3344), .B(DMP_SFG[23]), .Y(n4698) );
NAND3X2TS U4063 ( .A(n5691), .B(Raw_mant_NRM_SWR[14]), .C(n5690), .Y(n5694)
);
NAND2X2TS U4064 ( .A(n2512), .B(n5053), .Y(n2874) );
INVX4TS U4065 ( .A(n2493), .Y(n2495) );
NAND2X2TS U4066 ( .A(n1738), .B(n2480), .Y(n2711) );
NAND2X2TS U4067 ( .A(n4584), .B(n6127), .Y(n4585) );
NAND2X6TS U4068 ( .A(n4597), .B(n3161), .Y(n3160) );
INVX8TS U4069 ( .A(n3163), .Y(n3155) );
OAI2BB1X2TS U4070 ( .A0N(n5225), .A1N(n5212), .B0(n2450), .Y(n2449) );
NAND2X4TS U4071 ( .A(sub_x_5_n624), .B(DMP_SFG[18]), .Y(n4717) );
NAND2X6TS U4072 ( .A(n3319), .B(DMP_SFG[33]), .Y(n5176) );
OAI21X2TS U4073 ( .A0(n5525), .A1(n2834), .B0(n2833), .Y(n2832) );
NOR2X2TS U4074 ( .A(n5019), .B(n5018), .Y(n3075) );
NAND2X4TS U4075 ( .A(n2549), .B(n3074), .Y(n3073) );
NAND2X2TS U4076 ( .A(n5666), .B(n5721), .Y(n2606) );
NAND2X2TS U4077 ( .A(n5876), .B(n4389), .Y(n2732) );
OR2X6TS U4078 ( .A(n6784), .B(n5562), .Y(n3916) );
NAND2X2TS U4079 ( .A(n3892), .B(n3893), .Y(n2590) );
INVX8TS U4080 ( .A(n1946), .Y(n2556) );
NOR2X1TS U4081 ( .A(n3455), .B(n4055), .Y(n3952) );
INVX4TS U4082 ( .A(n5707), .Y(n2498) );
NAND2X4TS U4083 ( .A(n4330), .B(n4329), .Y(n2614) );
NAND2X2TS U4084 ( .A(n6970), .B(n2558), .Y(n5202) );
INVX2TS U4085 ( .A(n2472), .Y(n5548) );
NOR2X6TS U4086 ( .A(n2921), .B(n2920), .Y(n2919) );
NAND4X4TS U4087 ( .A(n3898), .B(n3897), .C(n3896), .D(n3895), .Y(n1711) );
NAND2X4TS U4088 ( .A(n3300), .B(intDY_EWSW[36]), .Y(n2384) );
NAND2X2TS U4089 ( .A(n3294), .B(intDY_EWSW[47]), .Y(n3595) );
NAND2X2TS U4090 ( .A(n3272), .B(intDY_EWSW[51]), .Y(n3609) );
NOR2X4TS U4091 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[47]), .Y(
n2651) );
INVX4TS U4092 ( .A(n4646), .Y(n2955) );
NOR2X2TS U4093 ( .A(n3329), .B(intDY_EWSW[32]), .Y(n3558) );
INVX4TS U4094 ( .A(n4489), .Y(n4491) );
NOR2X4TS U4095 ( .A(sub_x_5_n601), .B(DMP_SFG[41]), .Y(n5041) );
AND2X4TS U4096 ( .A(n6260), .B(Raw_mant_NRM_SWR[26]), .Y(n2631) );
NOR2X4TS U4097 ( .A(Raw_mant_NRM_SWR[42]), .B(Raw_mant_NRM_SWR[40]), .Y(
n3386) );
NOR2X4TS U4098 ( .A(n6333), .B(DMP_SFG[3]), .Y(n5337) );
INVX2TS U4099 ( .A(n5024), .Y(n4931) );
INVX6TS U4100 ( .A(n4374), .Y(n3008) );
NAND2X4TS U4101 ( .A(DmP_mant_SFG_SWR[9]), .B(DMP_SFG[7]), .Y(n5743) );
INVX6TS U4102 ( .A(n4861), .Y(n5000) );
NAND2X2TS U4103 ( .A(n6301), .B(DMP_SFG[46]), .Y(n4664) );
CLKINVX6TS U4104 ( .A(n3112), .Y(n5514) );
NOR2X4TS U4105 ( .A(n4548), .B(n3216), .Y(n3141) );
INVX4TS U4106 ( .A(n2803), .Y(n4369) );
NAND2X6TS U4107 ( .A(DMP_SFG[36]), .B(DmP_mant_SFG_SWR[38]), .Y(n5145) );
NOR2X4TS U4108 ( .A(n5156), .B(n5079), .Y(n3223) );
AND2X6TS U4109 ( .A(add_x_6_B_21_), .B(add_x_6_A_21_), .Y(n3136) );
INVX2TS U4110 ( .A(n4620), .Y(n4398) );
NAND2X4TS U4111 ( .A(n5134), .B(n4961), .Y(n5116) );
INVX12TS U4112 ( .A(n3947), .Y(n3919) );
NOR2X2TS U4113 ( .A(n3455), .B(n5668), .Y(n4556) );
INVX2TS U4114 ( .A(n1723), .Y(n4554) );
NAND2X4TS U4115 ( .A(n2478), .B(n1719), .Y(n2605) );
NAND2X2TS U4116 ( .A(n1710), .B(n5720), .Y(n2612) );
INVX2TS U4117 ( .A(n1722), .Y(n2615) );
OR2X6TS U4118 ( .A(n6784), .B(n2742), .Y(n4177) );
INVX2TS U4119 ( .A(n2523), .Y(n2742) );
XNOR2X2TS U4120 ( .A(intDX_EWSW[41]), .B(n2137), .Y(n5425) );
NAND3X4TS U4121 ( .A(n2392), .B(n2391), .C(n2390), .Y(n2389) );
INVX2TS U4122 ( .A(n4084), .Y(n4077) );
INVX4TS U4123 ( .A(n3253), .Y(n2561) );
INVX2TS U4124 ( .A(n4091), .Y(n3252) );
INVX2TS U4125 ( .A(n4094), .Y(n4088) );
NOR2X2TS U4126 ( .A(n4088), .B(n4089), .Y(n3251) );
INVX4TS U4127 ( .A(n4099), .Y(n2837) );
NOR2X2TS U4128 ( .A(n5235), .B(n5216), .Y(n3206) );
OAI21X2TS U4129 ( .A0(n5103), .A1(n5049), .B0(n5048), .Y(n2611) );
INVX2TS U4130 ( .A(n5025), .Y(n2452) );
NAND2X6TS U4131 ( .A(n3360), .B(DMP_SFG[5]), .Y(n5975) );
NAND2X4TS U4132 ( .A(n3107), .B(n4760), .Y(n3106) );
INVX2TS U4133 ( .A(n5016), .Y(n4832) );
NOR2X2TS U4134 ( .A(n5236), .B(n4683), .Y(n2783) );
INVX2TS U4135 ( .A(n5480), .Y(n5481) );
INVX2TS U4136 ( .A(n2297), .Y(n2751) );
NAND2X2TS U4137 ( .A(n5667), .B(n5713), .Y(n2603) );
NOR2X2TS U4138 ( .A(n5542), .B(n5541), .Y(n5549) );
NOR2X2TS U4139 ( .A(n4001), .B(n2235), .Y(n2930) );
NOR2X4TS U4140 ( .A(n4001), .B(n2215), .Y(n2920) );
NOR2X4TS U4141 ( .A(n1997), .B(n2214), .Y(n2666) );
NAND2X2TS U4142 ( .A(n3044), .B(n4563), .Y(n3043) );
NAND2X2TS U4143 ( .A(n2876), .B(n5701), .Y(n2915) );
NOR2X2TS U4144 ( .A(n5235), .B(n5218), .Y(n5220) );
NAND3X4TS U4145 ( .A(n3159), .B(n3158), .C(n3160), .Y(n5642) );
NAND2X1TS U4146 ( .A(n3775), .B(n2437), .Y(n3735) );
NOR2X4TS U4147 ( .A(n1550), .B(n1135), .Y(n6046) );
INVX4TS U4148 ( .A(n6082), .Y(sub_x_5_B_33_) );
OAI2BB1X2TS U4149 ( .A0N(n5996), .A1N(n4831), .B0(n4830), .Y(n1246) );
AND2X2TS U4150 ( .A(n5730), .B(DmP_mant_SFG_SWR[10]), .Y(n2379) );
NAND2X4TS U4151 ( .A(n3231), .B(n5700), .Y(n1697) );
AOI22X1TS U4152 ( .A0(n4411), .A1(n5527), .B0(Raw_mant_NRM_SWR[16]), .B1(
n5030), .Y(n4412) );
AOI22X1TS U4153 ( .A0(n6992), .A1(n2756), .B0(DmP_mant_SFG_SWR[52]), .B1(
n5730), .Y(n5682) );
AOI22X1TS U4154 ( .A0(n6990), .A1(n2756), .B0(n5756), .B1(
DmP_mant_SFG_SWR[51]), .Y(n5757) );
AOI22X2TS U4155 ( .A0(n6946), .A1(n2756), .B0(DmP_mant_SFG_SWR[31]), .B1(
n2507), .Y(n5658) );
AOI22X2TS U4156 ( .A0(n6990), .A1(n4050), .B0(n5732), .B1(
DmP_mant_SFG_SWR[3]), .Y(n3039) );
NAND2X4TS U4157 ( .A(n6953), .B(n2557), .Y(n4520) );
NAND2X1TS U4158 ( .A(n2607), .B(DmP_mant_SFG_SWR[30]), .Y(n5512) );
INVX2TS U4159 ( .A(n3098), .Y(n3097) );
NAND2BX2TS U4160 ( .AN(n2937), .B(n5492), .Y(n1128) );
NAND2X4TS U4161 ( .A(n2938), .B(n5491), .Y(n2937) );
NAND2X4TS U4162 ( .A(n6940), .B(n2558), .Y(n2738) );
NAND2X4TS U4163 ( .A(n6939), .B(n5557), .Y(n2740) );
AOI22X2TS U4164 ( .A0(n6992), .A1(n2486), .B0(n5756), .B1(n2425), .Y(n3037)
);
NAND2X4TS U4165 ( .A(n1153), .B(n1604), .Y(n6044) );
NOR2X4TS U4166 ( .A(n1592), .B(n1149), .Y(n6053) );
NAND2X2TS U4167 ( .A(n6082), .B(n1514), .Y(n6081) );
CLKBUFX3TS U4168 ( .A(n2510), .Y(n6769) );
NAND2X2TS U4169 ( .A(n5204), .B(n5647), .Y(n2710) );
NAND4X4TS U4170 ( .A(n3995), .B(n3994), .C(n3993), .D(n3992), .Y(n1709) );
AND2X4TS U4171 ( .A(n5817), .B(Raw_mant_NRM_SWR[15]), .Y(n5821) );
CLKBUFX3TS U4172 ( .A(n7013), .Y(n5243) );
INVX2TS U4173 ( .A(n5488), .Y(n4415) );
INVX2TS U4174 ( .A(n5545), .Y(n4476) );
NAND2X2TS U4175 ( .A(n2942), .B(n4613), .Y(n2941) );
NAND2X2TS U4176 ( .A(n2556), .B(n5488), .Y(n2942) );
NAND2X2TS U4177 ( .A(n2758), .B(n4563), .Y(n2757) );
NAND2X2TS U4178 ( .A(n5545), .B(n2513), .Y(n2758) );
NAND3X4TS U4179 ( .A(n2723), .B(n2722), .C(n4613), .Y(n2721) );
CLKBUFX3TS U4180 ( .A(n6728), .Y(n6360) );
AOI22X1TS U4181 ( .A0(n6995), .A1(n2766), .B0(n5756), .B1(
DmP_mant_SFG_SWR[1]), .Y(n5676) );
INVX2TS U4182 ( .A(n2527), .Y(n2529) );
NAND2X2TS U4183 ( .A(n5348), .B(intDX_EWSW[42]), .Y(n4192) );
NAND2X2TS U4184 ( .A(n2505), .B(intDX_EWSW[22]), .Y(n4257) );
CLKINVX3TS U4185 ( .A(n2519), .Y(n2535) );
INVX2TS U4186 ( .A(n2519), .Y(n2536) );
INVX3TS U4187 ( .A(n2527), .Y(n2528) );
NAND2X2TS U4188 ( .A(n4295), .B(intDX_EWSW[17]), .Y(n4269) );
CLKBUFX3TS U4189 ( .A(n5251), .Y(n6734) );
CLKBUFX3TS U4190 ( .A(n6768), .Y(n6732) );
INVX2TS U4191 ( .A(n2537), .Y(n2545) );
INVX2TS U4192 ( .A(n2530), .Y(n2544) );
INVX2TS U4193 ( .A(n2527), .Y(n2546) );
INVX3TS U4194 ( .A(rst), .Y(n2515) );
CLKINVX3TS U4195 ( .A(rst), .Y(n2534) );
CLKINVX3TS U4196 ( .A(n2530), .Y(n2532) );
BUFX3TS U4197 ( .A(n5251), .Y(n6736) );
CLKINVX3TS U4198 ( .A(n2519), .Y(n2516) );
INVX2TS U4199 ( .A(n2537), .Y(n2542) );
NAND3X4TS U4200 ( .A(n2403), .B(n5437), .C(n2400), .Y(n5441) );
NAND2X2TS U4201 ( .A(n3023), .B(intDY_EWSW[40]), .Y(n3744) );
CLKINVX3TS U4202 ( .A(n2519), .Y(n2499) );
BUFX3TS U4203 ( .A(n5245), .Y(n6748) );
AOI21X2TS U4204 ( .A0(n2820), .A1(intDX_EWSW[18]), .B0(n2375), .Y(n2823) );
NAND2X2TS U4205 ( .A(n4245), .B(intDY_EWSW[18]), .Y(n2824) );
INVX3TS U4206 ( .A(n2530), .Y(n2531) );
CLKBUFX3TS U4207 ( .A(n5245), .Y(n6742) );
INVX2TS U4208 ( .A(n2530), .Y(n2543) );
CLKINVX3TS U4209 ( .A(n2527), .Y(n2541) );
NAND2X2TS U4210 ( .A(n2550), .B(intDY_EWSW[6]), .Y(n3695) );
BUFX3TS U4211 ( .A(n6386), .Y(n6738) );
INVX3TS U4212 ( .A(n2537), .Y(n2538) );
CLKINVX3TS U4213 ( .A(n2537), .Y(n2539) );
NAND2X2TS U4214 ( .A(n3845), .B(n2438), .Y(n3704) );
CLKINVX3TS U4215 ( .A(n2527), .Y(n2487) );
XOR2X4TS U4216 ( .A(n2281), .B(n4072), .Y(exp_rslt_NRM2_EW1[2]) );
OA21X4TS U4217 ( .A0(n2274), .A1(n2306), .B0(n4067), .Y(n2281) );
NAND2X4TS U4218 ( .A(n2293), .B(n2443), .Y(n2394) );
NOR2X8TS U4219 ( .A(n2204), .B(n2332), .Y(n3031) );
NAND2X4TS U4220 ( .A(n1744), .B(n5505), .Y(n3961) );
XNOR2X4TS U4221 ( .A(n3147), .B(n5150), .Y(n3146) );
NAND2X8TS U4222 ( .A(n3131), .B(n4070), .Y(n2284) );
NAND3X8TS U4223 ( .A(n2749), .B(n2850), .C(n3128), .Y(n3131) );
OR2X8TS U4224 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[18]), .Y(n2285) );
CLKINVX6TS U4225 ( .A(n2482), .Y(n2563) );
NAND3X8TS U4226 ( .A(n2296), .B(n2835), .C(n3132), .Y(n3191) );
NOR2X6TS U4227 ( .A(n4454), .B(n4530), .Y(n3114) );
AOI21X4TS U4228 ( .A0(n5239), .A1(n4944), .B0(n6088), .Y(n4947) );
OAI21X4TS U4229 ( .A0(n6040), .A1(n6042), .B0(n6044), .Y(n6043) );
OR2X4TS U4230 ( .A(n2292), .B(ADD_OVRFLW_NRM2), .Y(n3255) );
AOI32X4TS U4231 ( .A0(n3947), .A1(n3878), .A2(n1704), .B0(n5720), .B1(n1700),
.Y(n4057) );
INVX16TS U4232 ( .A(n3460), .Y(n3947) );
NOR2X8TS U4233 ( .A(n2279), .B(exp_rslt_NRM2_EW1[7]), .Y(n3261) );
OAI2BB1X1TS U4234 ( .A0N(n2766), .A1N(n2329), .B0(n5682), .Y(n1104) );
NAND3X8TS U4235 ( .A(n2422), .B(n3261), .C(n2571), .Y(n2564) );
NAND3X8TS U4236 ( .A(n2836), .B(n2835), .C(n3132), .Y(n2481) );
AND3X6TS U4237 ( .A(exp_rslt_NRM2_EW1[9]), .B(n3189), .C(n2330), .Y(n2289)
);
XNOR2X4TS U4238 ( .A(n4087), .B(n2291), .Y(n2330) );
AND2X4TS U4239 ( .A(n4086), .B(n2852), .Y(n2291) );
NAND2X4TS U4240 ( .A(n3130), .B(n3091), .Y(n3129) );
XOR2X4TS U4241 ( .A(n3154), .B(n2368), .Y(n2297) );
NAND2X8TS U4242 ( .A(n2839), .B(n3133), .Y(n2835) );
AND2X8TS U4243 ( .A(n3151), .B(n2313), .Y(n2299) );
AND2X8TS U4244 ( .A(n2970), .B(n4581), .Y(n2300) );
AND2X4TS U4245 ( .A(n5039), .B(n5038), .Y(n2302) );
INVX6TS U4246 ( .A(n3093), .Y(n4094) );
INVX8TS U4247 ( .A(n2713), .Y(n5562) );
AND2X4TS U4248 ( .A(n2567), .B(n4073), .Y(n2306) );
AND2X2TS U4249 ( .A(n5692), .B(Raw_mant_NRM_SWR[33]), .Y(n2308) );
AND2X8TS U4250 ( .A(n5617), .B(n2858), .Y(n2310) );
AND2X4TS U4251 ( .A(n2971), .B(n2446), .Y(n2312) );
INVX8TS U4252 ( .A(n1981), .Y(n5887) );
BUFX3TS U4253 ( .A(n5245), .Y(n6745) );
INVX12TS U4254 ( .A(n5556), .Y(n2557) );
OR2X2TS U4255 ( .A(n5712), .B(n4554), .Y(n2314) );
AND2X2TS U4256 ( .A(n5632), .B(n3356), .Y(n2315) );
OA21X2TS U4257 ( .A0(n5130), .A1(n5129), .B0(n5128), .Y(n2321) );
AND2X2TS U4258 ( .A(n5081), .B(n5080), .Y(n2322) );
OA21X4TS U4259 ( .A0(n4660), .A1(n5080), .B0(n4659), .Y(n2328) );
NAND2X4TS U4260 ( .A(n4767), .B(n4434), .Y(n4833) );
OR2X8TS U4261 ( .A(n2669), .B(n2668), .Y(n2329) );
INVX12TS U4262 ( .A(n5562), .Y(n2553) );
NAND2X4TS U4263 ( .A(n3944), .B(n5645), .Y(n5703) );
AND2X8TS U4264 ( .A(n4131), .B(add_x_6_n483), .Y(n2333) );
NAND2X4TS U4265 ( .A(n4376), .B(n5645), .Y(n5574) );
INVX4TS U4266 ( .A(n5574), .Y(n2980) );
AND2X2TS U4267 ( .A(n5054), .B(n5572), .Y(n2336) );
NAND2X2TS U4268 ( .A(n5689), .B(n2326), .Y(n2337) );
AND4X8TS U4269 ( .A(n3374), .B(n2574), .C(n3386), .D(n4910), .Y(n2338) );
OA21X4TS U4270 ( .A0(n4530), .A1(n4524), .B0(n4531), .Y(n2339) );
AND3X6TS U4271 ( .A(n4587), .B(n4486), .C(n4487), .Y(n2340) );
AND2X8TS U4272 ( .A(n2621), .B(n6195), .Y(n2341) );
AND3X8TS U4273 ( .A(n4019), .B(n4018), .C(n2705), .Y(n2344) );
AND4X2TS U4274 ( .A(n2696), .B(n2692), .C(n2691), .D(n2690), .Y(n2349) );
AND2X8TS U4275 ( .A(n3877), .B(n3876), .Y(n2352) );
AND2X8TS U4276 ( .A(n3942), .B(n3941), .Y(n2353) );
NOR2X4TS U4277 ( .A(n5661), .B(n2238), .Y(n2354) );
NOR2X2TS U4278 ( .A(n5136), .B(n5112), .Y(n2355) );
NOR2X2TS U4279 ( .A(n2551), .B(n4025), .Y(n2356) );
AND3X6TS U4280 ( .A(n2664), .B(n2663), .C(n2662), .Y(n2357) );
AND2X8TS U4281 ( .A(n2872), .B(n2881), .Y(n2358) );
AND2X4TS U4282 ( .A(n2750), .B(n5561), .Y(n2359) );
AND3X2TS U4283 ( .A(n3086), .B(n3085), .C(n4466), .Y(n2360) );
OR2X4TS U4284 ( .A(sub_x_5_n260), .B(sub_x_5_n266), .Y(n2361) );
OR2X8TS U4285 ( .A(add_x_6_n515), .B(add_x_6_n521), .Y(n2362) );
OR2X4TS U4286 ( .A(DmP_mant_SFG_SWR[30]), .B(DMP_SFG[28]), .Y(n2363) );
INVX2TS U4287 ( .A(n4096), .Y(n3190) );
INVX4TS U4288 ( .A(n2966), .Y(n5697) );
MXI2X1TS U4289 ( .A(n6104), .B(n6311), .S0(n2607), .Y(n2377) );
MXI2X1TS U4290 ( .A(n6105), .B(n6312), .S0(n2607), .Y(n2378) );
NOR2X4TS U4291 ( .A(n4624), .B(n4544), .Y(n4463) );
INVX2TS U4292 ( .A(n4017), .Y(n2706) );
INVX2TS U4293 ( .A(n2302), .Y(n3060) );
BUFX3TS U4294 ( .A(n6724), .Y(n6733) );
INVX2TS U4295 ( .A(n2532), .Y(n2527) );
BUFX3TS U4296 ( .A(n2525), .Y(n6770) );
CLKBUFX3TS U4297 ( .A(n6769), .Y(n2496) );
BUFX3TS U4298 ( .A(n2496), .Y(n6730) );
CLKINVX3TS U4299 ( .A(n2537), .Y(n2510) );
BUFX3TS U4300 ( .A(n6768), .Y(n6731) );
INVX2TS U4301 ( .A(n6732), .Y(n2519) );
INVX2TS U4302 ( .A(n6743), .Y(n2530) );
BUFX3TS U4303 ( .A(n5245), .Y(n6741) );
CLKINVX3TS U4304 ( .A(n2530), .Y(n2526) );
INVX2TS U4305 ( .A(n6752), .Y(n2537) );
CLKBUFX2TS U4306 ( .A(n5250), .Y(n6749) );
INVX2TS U4307 ( .A(rst), .Y(n2522) );
INVX2TS U4308 ( .A(n2527), .Y(n2492) );
INVX2TS U4309 ( .A(rst), .Y(n2521) );
INVX2TS U4310 ( .A(n2537), .Y(n2491) );
INVX2TS U4311 ( .A(n2527), .Y(n2520) );
CLKINVX3TS U4312 ( .A(n2530), .Y(n2504) );
CLKINVX3TS U4313 ( .A(n2537), .Y(n2511) );
CLKBUFX2TS U4314 ( .A(n5244), .Y(n5249) );
NAND2X8TS U4315 ( .A(n2299), .B(n4953), .Y(n2383) );
OAI22X4TS U4316 ( .A0(n3580), .A1(n2384), .B0(intDX_EWSW[37]), .B1(n2317),
.Y(n3586) );
NOR2X8TS U4317 ( .A(n3304), .B(intDY_EWSW[37]), .Y(n3580) );
NAND2X6TS U4318 ( .A(n2769), .B(n3373), .Y(n4579) );
NAND2X8TS U4319 ( .A(n2769), .B(n3171), .Y(n3024) );
NAND2X8TS U4320 ( .A(n2386), .B(n4793), .Y(n6858) );
NAND2X8TS U4321 ( .A(n4791), .B(n2784), .Y(n2386) );
NAND3X8TS U4322 ( .A(n6207), .B(n6127), .C(n2388), .Y(n2387) );
NOR2X8TS U4323 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[42]), .Y(
n2388) );
XNOR2X4TS U4324 ( .A(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2390) );
XNOR2X4TS U4325 ( .A(intDX_EWSW[53]), .B(intDY_EWSW[53]), .Y(n2391) );
XNOR2X4TS U4326 ( .A(intDX_EWSW[57]), .B(intDY_EWSW[57]), .Y(n2392) );
AND2X8TS U4327 ( .A(n2753), .B(intDX_EWSW[41]), .Y(n3590) );
NAND2X4TS U4328 ( .A(n2404), .B(n3186), .Y(n3185) );
NAND4X2TS U4329 ( .A(n5684), .B(n2404), .C(n5685), .D(Raw_mant_NRM_SWR[22]),
.Y(n5686) );
NAND2X8TS U4330 ( .A(n5684), .B(n2404), .Y(n4572) );
NOR2X8TS U4331 ( .A(n2926), .B(n2925), .Y(n2404) );
OAI22X4TS U4332 ( .A0(n2369), .A1(add_x_6_n529), .B0(add_x_6_n526), .B1(
n5956), .Y(n3237) );
NAND2X8TS U4333 ( .A(n2299), .B(n4953), .Y(n2415) );
INVX6TS U4334 ( .A(n2968), .Y(n2967) );
INVX6TS U4335 ( .A(n2405), .Y(n2406) );
NAND2X4TS U4336 ( .A(n3295), .B(intDY_EWSW[48]), .Y(n3607) );
NOR2X4TS U4337 ( .A(n3082), .B(n2454), .Y(n3158) );
NAND2X2TS U4338 ( .A(n3828), .B(intDX_EWSW[17]), .Y(n3770) );
OAI21X4TS U4339 ( .A0(n3532), .A1(n3531), .B0(n3530), .Y(n3538) );
OAI2BB1X2TS U4340 ( .A0N(n5996), .A1N(n4697), .B0(n4696), .Y(n1248) );
NOR2X8TS U4341 ( .A(n4130), .B(n2333), .Y(n4547) );
INVX8TS U4342 ( .A(n5167), .Y(n5103) );
NAND2X4TS U4343 ( .A(n4787), .B(n2583), .Y(n4512) );
XNOR2X2TS U4344 ( .A(n4546), .B(n4545), .Y(n4553) );
CLKMX2X2TS U4345 ( .A(Data_Y[43]), .B(intDY_EWSW[43]), .S0(n5899), .Y(n1775)
);
NAND2X4TS U4346 ( .A(n4605), .B(n2784), .Y(n3151) );
OR2X8TS U4347 ( .A(n3179), .B(n4953), .Y(n2418) );
NAND2X2TS U4348 ( .A(n2553), .B(n1740), .Y(n3945) );
NAND2X2TS U4349 ( .A(n2553), .B(n1722), .Y(n5566) );
NAND2X4TS U4350 ( .A(n1726), .B(n2553), .Y(n2898) );
NAND2X4TS U4351 ( .A(n2750), .B(n2553), .Y(n3959) );
NAND2X2TS U4352 ( .A(n1738), .B(n2553), .Y(n2663) );
NAND2X2TS U4353 ( .A(n1742), .B(n2553), .Y(n2681) );
NAND2X2TS U4354 ( .A(n1728), .B(n2553), .Y(n2700) );
INVX12TS U4355 ( .A(n4353), .Y(n2644) );
AND3X6TS U4356 ( .A(n3192), .B(n2751), .C(n2752), .Y(n2422) );
AND3X6TS U4357 ( .A(n2947), .B(n2948), .C(n3110), .Y(n2423) );
NAND2X6TS U4358 ( .A(n3111), .B(n3112), .Y(n3110) );
NAND2X2TS U4359 ( .A(n6408), .B(n6462), .Y(n4036) );
OAI21X4TS U4360 ( .A0(n3520), .A1(n3519), .B0(n3518), .Y(n3526) );
AOI21X2TS U4361 ( .A0(n5122), .A1(n3234), .B0(add_x_6_n254), .Y(n3061) );
CLKMX2X2TS U4362 ( .A(Data_Y[35]), .B(intDY_EWSW[35]), .S0(n5897), .Y(n1783)
);
XNOR2X1TS U4363 ( .A(intDX_EWSW[35]), .B(intDY_EWSW[35]), .Y(n5362) );
INVX8TS U4364 ( .A(n1714), .Y(n4387) );
NAND2BX4TS U4365 ( .AN(n2424), .B(DMP_SFG[2]), .Y(n5952) );
NOR2X6TS U4366 ( .A(n3346), .B(DMP_SFG[29]), .Y(n4918) );
NAND2X4TS U4367 ( .A(n5203), .B(n5544), .Y(n4013) );
NOR2X4TS U4368 ( .A(n5551), .B(n5203), .Y(n4016) );
NAND2X2TS U4369 ( .A(n5203), .B(n5647), .Y(n5206) );
CLKMX2X2TS U4370 ( .A(Data_Y[33]), .B(intDY_EWSW[33]), .S0(n5897), .Y(n1785)
);
XNOR2X1TS U4371 ( .A(intDX_EWSW[33]), .B(intDY_EWSW[33]), .Y(n5364) );
NAND2X4TS U4372 ( .A(n4065), .B(n4067), .Y(n4066) );
OAI21X2TS U4373 ( .A0(n4515), .A1(n5462), .B0(n4514), .Y(n1212) );
AO21X4TS U4374 ( .A0(n5618), .A1(n2310), .B0(n1982), .Y(n2451) );
NAND2X4TS U4375 ( .A(n3477), .B(n3485), .Y(n3488) );
INVX6TS U4376 ( .A(n2425), .Y(n2426) );
OAI21X4TS U4377 ( .A0(n4847), .A1(n4839), .B0(n4848), .Y(n4140) );
NAND2X2TS U4378 ( .A(n2813), .B(intDX_EWSW[36]), .Y(n3838) );
NAND2X2TS U4379 ( .A(n2819), .B(intDX_EWSW[50]), .Y(n3783) );
NAND2X2TS U4380 ( .A(n5349), .B(intDX_EWSW[59]), .Y(n3737) );
NAND2X2TS U4381 ( .A(n1920), .B(intDX_EWSW[63]), .Y(n5440) );
NAND2X2TS U4382 ( .A(n2819), .B(n1914), .Y(n4126) );
NAND2X2TS U4383 ( .A(n4307), .B(intDX_EWSW[28]), .Y(n3749) );
NAND2X2TS U4384 ( .A(n3809), .B(n2137), .Y(n3857) );
NAND2X2TS U4385 ( .A(n2813), .B(intDY_EWSW[55]), .Y(n5447) );
NAND2X2TS U4386 ( .A(n3809), .B(intDY_EWSW[30]), .Y(n4253) );
NAND2X2TS U4387 ( .A(n4307), .B(intDY_EWSW[29]), .Y(n4271) );
NAND2X2TS U4388 ( .A(n3809), .B(intDY_EWSW[15]), .Y(n4301) );
NAND2X2TS U4389 ( .A(n4121), .B(intDY_EWSW[23]), .Y(n4310) );
NAND2X2TS U4390 ( .A(n2813), .B(intDY_EWSW[24]), .Y(n4187) );
NAND2X2TS U4391 ( .A(n2813), .B(intDY_EWSW[42]), .Y(n4191) );
NAND2X2TS U4392 ( .A(n1920), .B(n2154), .Y(n4197) );
NAND2X2TS U4393 ( .A(n3809), .B(n2130), .Y(n4203) );
NAND2X2TS U4394 ( .A(n3828), .B(intDY_EWSW[37]), .Y(n4293) );
NAND2X2TS U4395 ( .A(n3809), .B(intDY_EWSW[31]), .Y(n4281) );
NAND2X2TS U4396 ( .A(n3846), .B(intDY_EWSW[21]), .Y(n4290) );
NAND2X2TS U4397 ( .A(n3828), .B(intDY_EWSW[28]), .Y(n4265) );
NAND2X2TS U4398 ( .A(n1920), .B(intDY_EWSW[22]), .Y(n4256) );
NAND2X2TS U4399 ( .A(n3846), .B(intDY_EWSW[19]), .Y(n4274) );
NAND2X2TS U4400 ( .A(n3809), .B(intDY_EWSW[2]), .Y(n4228) );
NAND2X2TS U4401 ( .A(n3846), .B(n2437), .Y(n4284) );
NAND2X2TS U4402 ( .A(n1920), .B(n2407), .Y(n4181) );
NAND2X2TS U4403 ( .A(n2813), .B(intDY_EWSW[48]), .Y(n4123) );
NAND2X2TS U4404 ( .A(n3828), .B(intDX_EWSW[12]), .Y(n3746) );
INVX12TS U4405 ( .A(n4706), .Y(n5022) );
NAND2X2TS U4406 ( .A(n3276), .B(intDY_EWSW[12]), .Y(n3500) );
AOI2BB2X4TS U4407 ( .B0(n5720), .B1(n1703), .A0N(n4039), .A1N(n5668), .Y(
n4172) );
OAI21X2TS U4408 ( .A0(n6988), .A1(n5888), .B0(n2911), .Y(n1106) );
XNOR2X4TS U4409 ( .A(n2563), .B(n2280), .Y(n2428) );
INVX12TS U4410 ( .A(n4189), .Y(n2991) );
INVX4TS U4411 ( .A(n5020), .Y(n4445) );
OAI2BB1X2TS U4412 ( .A0N(n5996), .A1N(n5485), .B0(n5484), .Y(n1259) );
NAND2X4TS U4413 ( .A(n4989), .B(n4991), .Y(n4993) );
NOR2X6TS U4414 ( .A(DMP_SFG[42]), .B(DmP_mant_SFG_SWR[44]), .Y(n5046) );
NOR2X4TS U4415 ( .A(n3312), .B(DMP_SFG[42]), .Y(n4660) );
XOR2X4TS U4416 ( .A(n3123), .B(n5135), .Y(n3122) );
XOR2X4TS U4417 ( .A(n5143), .B(n5150), .Y(n5151) );
XOR2X4TS U4418 ( .A(n5179), .B(n5178), .Y(n5185) );
INVX4TS U4419 ( .A(n3192), .Y(exp_rslt_NRM2_EW1[4]) );
NOR2X4TS U4420 ( .A(n6303), .B(DMP_SFG[39]), .Y(n5158) );
INVX2TS U4421 ( .A(n4508), .Y(n2434) );
NOR2X6TS U4422 ( .A(n3567), .B(n3620), .Y(n3622) );
OAI21X2TS U4423 ( .A0(n3620), .A1(n3619), .B0(n3618), .Y(n3621) );
NAND2X4TS U4424 ( .A(n3329), .B(intDY_EWSW[32]), .Y(n3572) );
NAND4X8TS U4425 ( .A(n3979), .B(n3978), .C(n3977), .D(n3976), .Y(n1729) );
NAND2X2TS U4426 ( .A(n5349), .B(intDY_EWSW[18]), .Y(n4262) );
OAI2BB1X2TS U4427 ( .A0N(n5996), .A1N(n5995), .B0(n5994), .Y(n1261) );
OAI21X4TS U4428 ( .A0(n3483), .A1(n3482), .B0(n3481), .Y(n3484) );
NAND2X2TS U4429 ( .A(n3320), .B(intDY_EWSW[7]), .Y(n3481) );
OAI21X4TS U4430 ( .A0(n3617), .A1(n3616), .B0(n3615), .Y(n3623) );
NOR2X4TS U4431 ( .A(n3566), .B(n3617), .Y(n3568) );
NAND2X4TS U4432 ( .A(n4518), .B(n5673), .Y(n2578) );
OAI2BB1X4TS U4433 ( .A0N(n6110), .A1N(n6246), .B0(n4904), .Y(n3390) );
NAND2X4TS U4434 ( .A(n3331), .B(intDY_EWSW[52]), .Y(n3616) );
NAND2X2TS U4435 ( .A(n3775), .B(intDY_EWSW[20]), .Y(n3698) );
NAND2X2TS U4436 ( .A(n1920), .B(intDY_EWSW[20]), .Y(n4225) );
NOR2X8TS U4437 ( .A(n3291), .B(n2139), .Y(n3594) );
NAND2X4TS U4438 ( .A(n3336), .B(intDY_EWSW[56]), .Y(n3628) );
NOR2X4TS U4439 ( .A(n5207), .B(n5211), .Y(n5212) );
OAI21X4TS U4440 ( .A0(n3523), .A1(n3522), .B0(n3521), .Y(n3524) );
NAND2X8TS U4441 ( .A(n3125), .B(n3140), .Y(n2439) );
NAND2X4TS U4442 ( .A(n5498), .B(n5713), .Y(n3918) );
XOR2X4TS U4443 ( .A(n5119), .B(n2376), .Y(n2965) );
NAND2X8TS U4444 ( .A(n5691), .B(Raw_mant_NRM_SWR[16]), .Y(n4787) );
OR2X2TS U4445 ( .A(n2626), .B(n2779), .Y(n2775) );
AOI22X2TS U4446 ( .A0(n5753), .A1(n5992), .B0(Raw_mant_NRM_SWR[9]), .B1(
n5991), .Y(n5754) );
AOI2BB2X2TS U4447 ( .B0(n2803), .B1(Raw_mant_NRM_SWR[8]), .A0N(n4579), .A1N(
n2633), .Y(n2802) );
NAND2X6TS U4448 ( .A(n3169), .B(n3233), .Y(n4580) );
NAND2X4TS U4449 ( .A(n4064), .B(n2284), .Y(n3130) );
NAND2X6TS U4450 ( .A(n4071), .B(n4070), .Y(n4072) );
OAI21X2TS U4451 ( .A0(n5236), .A1(n4676), .B0(n4678), .Y(n4671) );
NOR2X6TS U4452 ( .A(n3559), .B(n3576), .Y(n3578) );
CLKMX2X3TS U4453 ( .A(Data_Y[41]), .B(n2137), .S0(n5899), .Y(n1777) );
AND2X8TS U4454 ( .A(n4067), .B(n4073), .Y(n2996) );
NAND2X4TS U4455 ( .A(n1991), .B(n6500), .Y(n3450) );
NAND2X4TS U4456 ( .A(n1736), .B(n2523), .Y(n2733) );
OAI21X4TS U4457 ( .A0(n3583), .A1(n3582), .B0(n3581), .Y(n3584) );
AOI2BB2X4TS U4458 ( .B0(n3083), .B1(n3226), .A0N(n6115), .A1N(n2441), .Y(
n3080) );
AO21X4TS U4459 ( .A0(n2549), .A1(n4835), .B0(n4834), .Y(n2442) );
NAND2X4TS U4460 ( .A(n1728), .B(n2476), .Y(n2734) );
NAND2X4TS U4461 ( .A(n2420), .B(n6445), .Y(n3931) );
INVX2TS U4462 ( .A(n3172), .Y(n4509) );
NAND2X4TS U4463 ( .A(n2762), .B(n3963), .Y(n2761) );
NOR4X2TS U4464 ( .A(n5416), .B(n5415), .C(n5414), .D(n5413), .Y(n5434) );
BUFX16TS U4465 ( .A(n2846), .Y(n2609) );
XOR2X4TS U4466 ( .A(n5622), .B(n5621), .Y(n5629) );
AND2X8TS U4467 ( .A(n4086), .B(n3338), .Y(n2443) );
NAND3X6TS U4468 ( .A(n2755), .B(n2754), .C(n2380), .Y(n1143) );
AOI21X1TS U4469 ( .A0(n4566), .A1(n2381), .B0(n4560), .Y(n6914) );
OAI21X4TS U4470 ( .A0(n4565), .A1(n4567), .B0(n4613), .Y(n4560) );
INVX2TS U4471 ( .A(n2444), .Y(n2445) );
NAND2X8TS U4472 ( .A(n2644), .B(n2634), .Y(n2643) );
OAI21X2TS U4473 ( .A0(n5140), .A1(n5145), .B0(n5141), .Y(n4960) );
NAND2X4TS U4474 ( .A(n6304), .B(DMP_SFG[37]), .Y(n5111) );
XOR2X4TS U4475 ( .A(n2482), .B(n2448), .Y(n2447) );
INVX8TS U4476 ( .A(n2447), .Y(n3099) );
INVX6TS U4477 ( .A(n4069), .Y(n4071) );
OAI21X4TS U4478 ( .A0(n3608), .A1(n3607), .B0(n3606), .Y(n3614) );
OAI21X4TS U4479 ( .A0(n3576), .A1(n3575), .B0(n3574), .Y(n3577) );
NAND2X4TS U4480 ( .A(n1748), .B(n5563), .Y(n3948) );
AOI22X2TS U4481 ( .A0(n5528), .A1(n5527), .B0(Raw_mant_NRM_SWR[13]), .B1(
n5924), .Y(n5529) );
NAND2X4TS U4482 ( .A(n3225), .B(n5925), .Y(n3224) );
OAI21X2TS U4483 ( .A0(n5634), .A1(n5633), .B0(n5632), .Y(n5635) );
AOI21X4TS U4484 ( .A0(n5618), .A1(n4732), .B0(n4731), .Y(n4735) );
XNOR2X4TS U4485 ( .A(n2451), .B(n5597), .Y(n5603) );
NAND2X2TS U4486 ( .A(n5561), .B(n1743), .Y(n4375) );
NAND2X4TS U4487 ( .A(n2854), .B(n4645), .Y(n2954) );
INVX6TS U4488 ( .A(n4422), .Y(n5746) );
AND3X8TS U4489 ( .A(n4587), .B(n4585), .C(n4586), .Y(n2454) );
NAND4X8TS U4490 ( .A(n4581), .B(n4580), .C(n3080), .D(n4575), .Y(n5683) );
XOR2X4TS U4491 ( .A(n2455), .B(n5526), .Y(n5528) );
AOI21X4TS U4492 ( .A0(n4994), .A1(n5239), .B0(n2857), .Y(n4999) );
XOR2X4TS U4493 ( .A(n2457), .B(n4981), .Y(n3029) );
AOI21X4TS U4494 ( .A0(n4977), .A1(n2552), .B0(n3030), .Y(n2457) );
NOR2X4TS U4495 ( .A(n5551), .B(n5486), .Y(n4024) );
NAND2X4TS U4496 ( .A(n6939), .B(n2557), .Y(n5504) );
NAND3X4TS U4497 ( .A(n2778), .B(n4906), .C(n5641), .Y(n2772) );
AND2X4TS U4498 ( .A(n4577), .B(n4578), .Y(n3164) );
NAND2X4TS U4499 ( .A(n3165), .B(n4494), .Y(n4578) );
AOI21X4TS U4500 ( .A0(n2552), .A1(n5089), .B0(n5088), .Y(n5093) );
OAI21X2TS U4501 ( .A0(n5159), .A1(n5087), .B0(n5086), .Y(n5088) );
AOI2BB2X4TS U4502 ( .B0(n3218), .B1(n6722), .A0N(n2459), .A1N(n6137), .Y(
n3217) );
AOI2BB2X4TS U4503 ( .B0(n4866), .B1(n5925), .A0N(n6122), .A1N(n2459), .Y(
n4867) );
OAI21X2TS U4504 ( .A0(n4444), .A1(n4689), .B0(n6077), .Y(n3260) );
XOR2X4TS U4505 ( .A(n2460), .B(n4536), .Y(n4537) );
AOI22X2TS U4506 ( .A0(n3102), .A1(n5527), .B0(n5924), .B1(n2432), .Y(n4450)
);
NAND3BX4TS U4507 ( .AN(n4447), .B(n2506), .C(n3105), .Y(n3104) );
NAND4X8TS U4508 ( .A(n3466), .B(n3465), .C(n3464), .D(n6598), .Y(n5876) );
BUFX4TS U4509 ( .A(n4495), .Y(n2633) );
NAND2X2TS U4510 ( .A(n3828), .B(intDY_EWSW[33]), .Y(n4298) );
NAND2X2TS U4511 ( .A(n3316), .B(intDY_EWSW[33]), .Y(n3571) );
NAND3X4TS U4512 ( .A(n4787), .B(n5779), .C(n4786), .Y(n4604) );
OR2X4TS U4513 ( .A(n4033), .B(n2199), .Y(n3998) );
NOR2X8TS U4514 ( .A(n5553), .B(n4016), .Y(n6970) );
OAI21X4TS U4515 ( .A0(n3480), .A1(n3479), .B0(n3478), .Y(n3486) );
OR2X4TS U4516 ( .A(DmP_mant_SFG_SWR[47]), .B(n6291), .Y(n4970) );
AOI21X2TS U4517 ( .A0(n5050), .A1(n2846), .B0(n2611), .Y(n2610) );
NAND4X8TS U4518 ( .A(n4177), .B(n4176), .C(n4175), .D(n4174), .Y(n4616) );
NOR2X8TS U4519 ( .A(n3554), .B(n3602), .Y(n3604) );
OAI21X2TS U4520 ( .A0(n5525), .A1(n5480), .B0(add_x_6_n492), .Y(n4458) );
NOR2X8TS U4521 ( .A(n5480), .B(add_x_6_n488), .Y(n5520) );
NOR2X8TS U4522 ( .A(add_x_6_A_10_), .B(add_x_6_B_10_), .Y(n5480) );
AOI21X4TS U4523 ( .A0(n4496), .A1(n4578), .B0(n2633), .Y(n4497) );
NOR3X4TS U4524 ( .A(exp_rslt_NRM2_EW1[2]), .B(exp_rslt_NRM2_EW1[1]), .C(
exp_rslt_NRM2_EW1[0]), .Y(n2752) );
AOI21X2TS U4525 ( .A0(n5618), .A1(n4885), .B0(n4884), .Y(n4890) );
AND2X8TS U4526 ( .A(intDX_EWSW[55]), .B(n2464), .Y(n3620) );
NOR2X4TS U4527 ( .A(n4790), .B(n4789), .Y(n4791) );
AOI22X2TS U4528 ( .A0(n4551), .A1(n5527), .B0(Raw_mant_NRM_SWR[14]), .B1(
n5030), .Y(n4552) );
OAI21X4TS U4529 ( .A0(n3573), .A1(n3572), .B0(n3571), .Y(n3579) );
XOR2X4TS U4530 ( .A(n5029), .B(n5028), .Y(n5031) );
AOI21X4TS U4531 ( .A0(n5027), .A1(n2506), .B0(n5026), .Y(n5029) );
OAI21X2TS U4532 ( .A0(n5025), .A1(n5024), .B0(n5023), .Y(n5026) );
OA22X4TS U4533 ( .A0(n4039), .A1(n5711), .B0(n3455), .B1(n5710), .Y(n4348)
);
INVX4TS U4534 ( .A(n1702), .Y(n5710) );
OR2X4TS U4535 ( .A(n6118), .B(ADD_OVRFLW_NRM2), .Y(n4075) );
NAND4X4TS U4536 ( .A(n2644), .B(n3169), .C(n4366), .D(n4355), .Y(n4356) );
XOR2X4TS U4537 ( .A(n3219), .B(n2322), .Y(n3218) );
NAND2BX4TS U4538 ( .AN(n5661), .B(n6426), .Y(n3880) );
NAND2X4TS U4539 ( .A(n2476), .B(n2151), .Y(n3887) );
NOR2X8TS U4540 ( .A(n1153), .B(n1604), .Y(n6042) );
NAND2X4TS U4541 ( .A(n4516), .B(n5713), .Y(n2831) );
XOR2X4TS U4542 ( .A(n4940), .B(n4939), .Y(n4941) );
INVX4TS U4543 ( .A(n5023), .Y(n4934) );
NAND2X4TS U4544 ( .A(n5737), .B(n5913), .Y(n3231) );
INVX6TS U4545 ( .A(n4860), .Y(n5004) );
OAI21X4TS U4546 ( .A0(add_x_6_n243), .A1(add_x_6_n251), .B0(add_x_6_n244),
.Y(n4149) );
INVX6TS U4547 ( .A(n2466), .Y(n2467) );
OA21X4TS U4548 ( .A0(n4568), .A1(n4567), .B0(n4613), .Y(n2468) );
OAI2BB1X1TS U4549 ( .A0N(n2486), .A1N(n6989), .B0(n5757), .Y(n1105) );
AOI21X2TS U4550 ( .A0(n2502), .A1(n1717), .B0(n2709), .Y(n2708) );
INVX4TS U4551 ( .A(n1717), .Y(n5186) );
NOR2X6TS U4552 ( .A(n2849), .B(DMP_exp_NRM2_EW[3]), .Y(n4061) );
NAND2X2TS U4553 ( .A(n3269), .B(intDY_EWSW[23]), .Y(n3521) );
MX2X2TS U4554 ( .A(Data_Y[23]), .B(intDY_EWSW[23]), .S0(n5906), .Y(n1795) );
XOR2X4TS U4555 ( .A(n5066), .B(n5065), .Y(n5075) );
OAI2BB2X2TS U4556 ( .B0(n4039), .B1(n4387), .A0N(n5720), .A1N(n1706), .Y(
n2472) );
OAI21X4TS U4557 ( .A0(n3632), .A1(n3631), .B0(n3630), .Y(n3633) );
INVX12TS U4558 ( .A(n2473), .Y(n2477) );
INVX12TS U4559 ( .A(n2474), .Y(n2478) );
NOR2X4TS U4560 ( .A(n3283), .B(intDY_EWSW[54]), .Y(n3567) );
OAI21X4TS U4561 ( .A0(n3594), .A1(n3593), .B0(n3592), .Y(n3600) );
AOI22X2TS U4562 ( .A0(n5592), .A1(n5639), .B0(n1984), .B1(n5638), .Y(n6781)
);
NAND2X4TS U4563 ( .A(n5669), .B(n2513), .Y(n4481) );
NAND2X4TS U4564 ( .A(n1727), .B(n2490), .Y(n2588) );
AOI22X2TS U4565 ( .A0(n5640), .A1(n5639), .B0(n5909), .B1(n5638), .Y(n6779)
);
MXI2X8TS U4566 ( .A(n6968), .B(n6334), .S0(n2507), .Y(n1114) );
OAI21X2TS U4567 ( .A0(n4415), .A1(n4564), .B0(n4563), .Y(n4390) );
BUFX20TS U4568 ( .A(n2846), .Y(n3234) );
NAND4X4TS U4569 ( .A(n2569), .B(n2568), .C(n1945), .D(n2561), .Y(n3248) );
OAI21X2TS U4570 ( .A0(n5159), .A1(n4993), .B0(n4992), .Y(n2857) );
NAND2X8TS U4571 ( .A(n2483), .B(n1964), .Y(n4080) );
NAND2X4TS U4572 ( .A(n5680), .B(n2974), .Y(n2973) );
AOI22X2TS U4573 ( .A0(n4941), .A1(n5527), .B0(Raw_mant_NRM_SWR[32]), .B1(
n5924), .Y(n4942) );
OAI21X1TS U4574 ( .A0(Raw_mant_NRM_SWR[34]), .A1(Raw_mant_NRM_SWR[32]), .B0(
n5692), .Y(n5693) );
NOR2X8TS U4575 ( .A(n4491), .B(n4490), .Y(n4588) );
OR2X8TS U4576 ( .A(n3179), .B(n4953), .Y(n2484) );
NOR2X1TS U4577 ( .A(Raw_mant_NRM_SWR[35]), .B(n2429), .Y(n4492) );
NOR2X6TS U4578 ( .A(n2980), .B(n2873), .Y(n2872) );
OR2X8TS U4579 ( .A(n4033), .B(n2224), .Y(n4003) );
NAND4X8TS U4580 ( .A(n3991), .B(n3990), .C(n3989), .D(n3988), .Y(n1721) );
CLKINVX3TS U4581 ( .A(n2519), .Y(n2488) );
MXI2X4TS U4582 ( .A(n6100), .B(n6317), .S0(n2514), .Y(n1598) );
NAND2X2TS U4583 ( .A(n1723), .B(n2490), .Y(n4371) );
NAND2X2TS U4584 ( .A(n1736), .B(n2490), .Y(n3956) );
NAND2X2TS U4585 ( .A(n1748), .B(n2490), .Y(n4027) );
INVX12TS U4586 ( .A(n2672), .Y(n2713) );
NAND2X8TS U4587 ( .A(n5727), .B(n4372), .Y(n4039) );
INVX2TS U4588 ( .A(rst), .Y(n2503) );
CLKBUFX3TS U4589 ( .A(n6353), .Y(n5251) );
AOI21X4TS U4590 ( .A0(n4938), .A1(n2506), .B0(n4937), .Y(n4940) );
CLKINVX3TS U4591 ( .A(n2537), .Y(n2508) );
CLKINVX3TS U4592 ( .A(rst), .Y(n2509) );
OR2X1TS U4593 ( .A(n2517), .B(shift_value_SHT2_EWR[4]), .Y(n3944) );
INVX2TS U4594 ( .A(rst), .Y(n7013) );
CLKINVX3TS U4595 ( .A(rst), .Y(n2524) );
CLKBUFX2TS U4596 ( .A(n2524), .Y(n6771) );
CLKINVX3TS U4597 ( .A(rst), .Y(n2525) );
BUFX3TS U4598 ( .A(n5251), .Y(n6739) );
INVX3TS U4599 ( .A(rst), .Y(n2533) );
MXI2X4TS U4600 ( .A(n6098), .B(n6321), .S0(n2489), .Y(n1592) );
MXI2X4TS U4601 ( .A(n6095), .B(n6257), .S0(n2540), .Y(n1583) );
OAI21X2TS U4602 ( .A0(n1998), .A1(add_x_6_n529), .B0(n5956), .Y(n5341) );
MXI2X4TS U4603 ( .A(n6103), .B(n6254), .S0(n2489), .Y(n1607) );
AOI22X2TS U4604 ( .A0(n5699), .A1(Shift_amount_SHT1_EWR[2]), .B0(
shift_value_SHT2_EWR[2]), .B1(n1969), .Y(n5700) );
XOR2X4TS U4605 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n5437) );
AOI21X2TS U4606 ( .A0(n5618), .A1(n4810), .B0(n4813), .Y(n4688) );
AOI21X4TS U4607 ( .A0(n2549), .A1(n4815), .B0(n4814), .Y(n4820) );
AOI21X2TS U4608 ( .A0(n2549), .A1(n4701), .B0(n4700), .Y(n4704) );
AOI21X4TS U4609 ( .A0(n2549), .A1(n4715), .B0(n4714), .Y(n4720) );
BUFX20TS U4610 ( .A(n4189), .Y(n2550) );
NAND2X2TS U4611 ( .A(n5348), .B(intDY_EWSW[25]), .Y(n3728) );
AOI2BB2X2TS U4612 ( .B0(n2502), .B1(n1708), .A0N(n2551), .A1N(n4055), .Y(
n4056) );
NOR2X2TS U4613 ( .A(n5712), .B(n4009), .Y(n4011) );
BUFX20TS U4614 ( .A(n3026), .Y(n2552) );
NAND2X2TS U4615 ( .A(n2713), .B(n5189), .Y(n4044) );
AOI22X2TS U4616 ( .A0(n6995), .A1(n2756), .B0(n5756), .B1(
DmP_mant_SFG_SWR[53]), .Y(n5678) );
NAND2X4TS U4617 ( .A(n5675), .B(n5729), .Y(n6995) );
OR2X1TS U4618 ( .A(shift_value_SHT2_EWR[4]), .B(left_right_SHT2), .Y(n4376)
);
NAND2X1TS U4619 ( .A(n6996), .B(n6484), .Y(n5771) );
NOR2X2TS U4620 ( .A(intDX_EWSW[63]), .B(n5437), .Y(n5275) );
NAND2X2TS U4621 ( .A(n5722), .B(n1970), .Y(n2722) );
NAND2X4TS U4622 ( .A(n5667), .B(n2556), .Y(n3005) );
NAND2X2TS U4623 ( .A(n5053), .B(n1970), .Y(n2908) );
NAND2X1TS U4624 ( .A(n2607), .B(DmP_mant_SFG_SWR[44]), .Y(n5558) );
NOR2X8TS U4625 ( .A(n2295), .B(n4079), .Y(n2560) );
NAND2X8TS U4626 ( .A(n2562), .B(n4097), .Y(n2839) );
NAND3X8TS U4627 ( .A(n2569), .B(n2568), .C(n1945), .Y(n2562) );
NAND2X4TS U4628 ( .A(n3139), .B(n2562), .Y(n3247) );
NAND2X8TS U4629 ( .A(n3040), .B(n3039), .Y(n1153) );
OAI21X4TS U4630 ( .A0(n5535), .A1(n5804), .B0(n5534), .Y(n1695) );
AOI21X2TS U4631 ( .A0(n2549), .A1(n4743), .B0(n4742), .Y(n4746) );
XOR2X4TS U4632 ( .A(n4746), .B(n4745), .Y(n4753) );
NAND2X2TS U4633 ( .A(n6299), .B(DMP_SFG[13]), .Y(n4419) );
NAND3X8TS U4634 ( .A(n2825), .B(n4047), .C(n4048), .Y(n6989) );
NAND2X8TS U4635 ( .A(n6989), .B(n2557), .Y(n3040) );
AOI21X4TS U4636 ( .A0(n3547), .A1(n3546), .B0(n3545), .Y(n3548) );
NAND2X4TS U4637 ( .A(n3505), .B(n3470), .Y(n3507) );
NOR2X4TS U4638 ( .A(n4676), .B(n4679), .Y(n5224) );
OAI21X4TS U4639 ( .A0(n3492), .A1(n3491), .B0(n3490), .Y(n3498) );
NAND3X2TS U4640 ( .A(n5685), .B(Raw_mant_NRM_SWR[45]), .C(n6122), .Y(n4592)
);
NOR2X2TS U4641 ( .A(n3271), .B(intDY_EWSW[24]), .Y(n3512) );
AOI21X4TS U4642 ( .A0(n5691), .A1(Raw_mant_NRM_SWR[13]), .B0(n4498), .Y(
n4368) );
NAND2X8TS U4643 ( .A(n2325), .B(n2381), .Y(n3153) );
NAND2X8TS U4644 ( .A(n3069), .B(n3066), .Y(n5016) );
MXI2X4TS U4645 ( .A(n6962), .B(n6304), .S0(n2414), .Y(n1117) );
NOR2X2TS U4646 ( .A(n3455), .B(n4312), .Y(n4313) );
NAND2X4TS U4647 ( .A(n3473), .B(n3497), .Y(n3474) );
NOR2X6TS U4648 ( .A(n3344), .B(DMP_SFG[23]), .Y(n4699) );
NAND2X2TS U4649 ( .A(n5011), .B(n5015), .Y(n5018) );
NAND2X8TS U4650 ( .A(n2572), .B(n2877), .Y(n1136) );
INVX12TS U4651 ( .A(n2995), .Y(n4587) );
NAND2X8TS U4652 ( .A(n2810), .B(n3177), .Y(n2995) );
NAND3X8TS U4653 ( .A(n2579), .B(n4522), .C(n2575), .Y(n1137) );
AOI21X4TS U4654 ( .A0(n4517), .A1(n5647), .B0(n2577), .Y(n2576) );
NAND2X8TS U4655 ( .A(n2581), .B(n3945), .Y(n2842) );
NOR3X8TS U4656 ( .A(n2298), .B(n2305), .C(n2345), .Y(n2581) );
NAND4X8TS U4657 ( .A(n2585), .B(n4511), .C(n2446), .D(n2584), .Y(n4790) );
NAND3X8TS U4658 ( .A(n3872), .B(n3873), .C(n2587), .Y(n1731) );
NOR2X8TS U4659 ( .A(n2354), .B(n2311), .Y(n2587) );
NAND3X8TS U4660 ( .A(n2352), .B(n3874), .C(n3875), .Y(n1727) );
NOR2BX4TS U4661 ( .AN(n3891), .B(n2590), .Y(n2589) );
NAND2X8TS U4662 ( .A(n2592), .B(n3009), .Y(n6082) );
NOR2X8TS U4663 ( .A(n2593), .B(n3010), .Y(n6950) );
OR2X8TS U4664 ( .A(n2334), .B(n3011), .Y(n2593) );
NAND4BX4TS U4665 ( .AN(Raw_mant_NRM_SWR[48]), .B(n4504), .C(n2595), .D(n2651), .Y(n2594) );
NAND2X4TS U4666 ( .A(n3374), .B(n2621), .Y(n2596) );
NAND2X8TS U4667 ( .A(n2605), .B(n2597), .Y(n5667) );
NAND3BX4TS U4668 ( .AN(n2602), .B(n5672), .C(n5670), .Y(n2601) );
NOR2X8TS U4669 ( .A(n4015), .B(n2517), .Y(n4050) );
NAND3X8TS U4670 ( .A(n3936), .B(n2608), .C(n3938), .Y(n1742) );
XOR2X4TS U4671 ( .A(n2610), .B(n5051), .Y(n2797) );
OAI21X4TS U4672 ( .A0(n2551), .A1(n2615), .B0(n2612), .Y(n2865) );
NOR2BX4TS U4673 ( .AN(n4331), .B(n2614), .Y(n2613) );
NAND3X8TS U4674 ( .A(n2620), .B(n2618), .C(n2616), .Y(n6942) );
NAND2X8TS U4675 ( .A(n2665), .B(n2364), .Y(n1730) );
NAND2X8TS U4676 ( .A(n2899), .B(n3926), .Y(n1726) );
NAND2X8TS U4677 ( .A(n3933), .B(n2867), .Y(n1734) );
NAND3X8TS U4678 ( .A(n2777), .B(n2776), .C(n2780), .Y(n2626) );
NOR2X8TS U4679 ( .A(n3191), .B(n2629), .Y(n2628) );
NAND2X2TS U4680 ( .A(n2632), .B(n3167), .Y(n3166) );
NAND3X8TS U4681 ( .A(n3377), .B(n3187), .C(n2632), .Y(n2925) );
NOR2X8TS U4682 ( .A(n2286), .B(Raw_mant_NRM_SWR[29]), .Y(n2632) );
INVX16TS U4683 ( .A(n4495), .Y(n3171) );
NOR2X8TS U4684 ( .A(n2639), .B(n3641), .Y(n3643) );
NAND3X8TS U4685 ( .A(n2638), .B(n3638), .C(n2637), .Y(n3641) );
NOR2X8TS U4686 ( .A(n3268), .B(intDY_EWSW[61]), .Y(n3636) );
NOR2X8TS U4687 ( .A(n3336), .B(intDY_EWSW[56]), .Y(n2641) );
NOR2X8TS U4688 ( .A(n3278), .B(intDY_EWSW[57]), .Y(n3629) );
NOR2X8TS U4689 ( .A(n3281), .B(intDY_EWSW[59]), .Y(n3632) );
AND4X8TS U4690 ( .A(n6133), .B(n3150), .C(n4362), .D(n2287), .Y(n2645) );
NOR2BX4TS U4691 ( .AN(n4596), .B(n2432), .Y(n2646) );
NOR2X8TS U4692 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[19]), .Y(
n4596) );
NOR2X8TS U4693 ( .A(n2647), .B(n3396), .Y(n5689) );
NOR2X8TS U4694 ( .A(n1954), .B(n3012), .Y(n4287) );
OAI21X4TS U4695 ( .A0(n3503), .A1(n2650), .B0(n3502), .Y(n3504) );
NOR2X8TS U4696 ( .A(n3315), .B(intDY_EWSW[15]), .Y(n2650) );
NOR2X8TS U4697 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n4504) );
NAND3BX4TS U4698 ( .AN(n4360), .B(n4368), .C(n4367), .Y(n2653) );
OAI21X4TS U4699 ( .A0(n3636), .A1(n2661), .B0(n2660), .Y(n3639) );
NAND2X4TS U4700 ( .A(n3268), .B(intDY_EWSW[61]), .Y(n2660) );
NAND2X4TS U4701 ( .A(n3282), .B(intDY_EWSW[60]), .Y(n2661) );
NOR2X8TS U4702 ( .A(n2902), .B(n2666), .Y(n2665) );
NAND3X8TS U4703 ( .A(n2341), .B(n4508), .C(n3172), .Y(n3178) );
NOR2X8TS U4704 ( .A(n5909), .B(n4808), .Y(n4508) );
OAI2BB1X4TS U4705 ( .A0N(n6479), .A1N(n6480), .B0(n6478), .Y(n4808) );
AOI22X4TS U4706 ( .A0(n5052), .A1(n5713), .B0(n5053), .B1(n5721), .Y(n2671)
);
NAND3X8TS U4707 ( .A(n2679), .B(n2678), .C(n2677), .Y(n5052) );
NAND2X8TS U4708 ( .A(n5779), .B(n2467), .Y(n5804) );
NOR2BX4TS U4709 ( .AN(n3377), .B(n3375), .Y(n3376) );
AOI22X4TS U4710 ( .A0(n5053), .A1(n5701), .B0(n2556), .B1(n5052), .Y(n2676)
);
AOI22X4TS U4711 ( .A0(n1728), .A1(n4388), .B0(n5876), .B1(n2553), .Y(n2678)
);
AND3X8TS U4712 ( .A(n2374), .B(n3950), .C(n2681), .Y(n2675) );
INVX12TS U4713 ( .A(n1972), .Y(n2687) );
NAND2X8TS U4714 ( .A(n2695), .B(n2694), .Y(n2693) );
NAND2X8TS U4715 ( .A(n1145), .B(n1580), .Y(n6057) );
AND2X8TS U4716 ( .A(n4013), .B(n4014), .Y(n2707) );
CLKINVX12TS U4717 ( .A(n1713), .Y(n4312) );
NAND4BX4TS U4718 ( .AN(n2370), .B(n4006), .C(n4008), .D(n4007), .Y(n5204) );
NAND2X4TS U4719 ( .A(n2876), .B(n5572), .Y(n2905) );
NAND2X8TS U4720 ( .A(n4028), .B(n2712), .Y(n1146) );
AOI21X4TS U4721 ( .A0(n6973), .A1(n5557), .B0(n2379), .Y(n2712) );
NAND3BX4TS U4722 ( .AN(n2714), .B(n4022), .C(n4021), .Y(n5486) );
NAND2X8TS U4723 ( .A(n2716), .B(n2366), .Y(n4020) );
NOR2X8TS U4724 ( .A(n2719), .B(n2416), .Y(n2718) );
AND2X8TS U4725 ( .A(n1968), .B(n1716), .Y(n2726) );
NAND2X8TS U4726 ( .A(n2727), .B(n2892), .Y(n6972) );
AOI21X4TS U4727 ( .A0(n5647), .A1(n5489), .B0(n2731), .Y(n2730) );
AOI21X4TS U4728 ( .A0(n4558), .A1(n5673), .B0(n2577), .Y(n2739) );
NAND3BX4TS U4729 ( .AN(n3881), .B(n3879), .C(n3880), .Y(n2743) );
OA21X4TS U4730 ( .A0(n4557), .A1(n2494), .B0(n5538), .Y(n2748) );
OR2X8TS U4731 ( .A(n3254), .B(DMP_exp_NRM2_EW[2]), .Y(n2749) );
INVX2TS U4732 ( .A(n2749), .Y(n4069) );
INVX12TS U4733 ( .A(n3453), .Y(n2750) );
AND2X8TS U4734 ( .A(n1943), .B(n6485), .Y(n3453) );
NAND3X8TS U4735 ( .A(n3247), .B(n3248), .C(n3250), .Y(exp_rslt_NRM2_EW1[9])
);
NAND2BX4TS U4736 ( .AN(n2687), .B(n4560), .Y(n2754) );
AOI21X4TS U4737 ( .A0(n4478), .A1(n2518), .B0(n2757), .Y(n6964) );
AOI22X4TS U4738 ( .A0(n5550), .A1(n5544), .B0(n5647), .B1(n5509), .Y(n2762)
);
NOR2X8TS U4739 ( .A(n3269), .B(intDY_EWSW[23]), .Y(n3523) );
AOI22X4TS U4740 ( .A0(n6979), .A1(n2766), .B0(n5756), .B1(
DmP_mant_SFG_SWR[8]), .Y(n5555) );
OAI2BB1X4TS U4741 ( .A0N(n2766), .A1N(n6978), .B0(n5554), .Y(n1110) );
OAI2BB1X4TS U4742 ( .A0N(n2766), .A1N(n6945), .B0(n5658), .Y(n1125) );
OAI2BB1X4TS U4743 ( .A0N(n2766), .A1N(n5735), .B0(n5734), .Y(n1102) );
OAI2BB1X4TS U4744 ( .A0N(n2766), .A1N(n6994), .B0(n5678), .Y(n1103) );
NAND2X8TS U4745 ( .A(n2371), .B(n3180), .Y(n3101) );
AOI21X4TS U4746 ( .A0(n1959), .A1(n4493), .B0(n4497), .Y(n2777) );
NAND2X6TS U4747 ( .A(n2440), .B(DMP_exp_NRM2_EW[5]), .Y(n4085) );
XNOR2X4TS U4748 ( .A(n2781), .B(n4685), .Y(N90) );
OAI2BB1X4TS U4749 ( .A0N(n1911), .A1N(n4684), .B0(n2782), .Y(n2781) );
AOI21X4TS U4750 ( .A0(n5239), .A1(n4954), .B0(n2785), .Y(n4959) );
AND2X8TS U4751 ( .A(n4656), .B(n3196), .Y(n5159) );
AOI21X4TS U4752 ( .A0(n2792), .A1(n2790), .B0(n2787), .Y(n3489) );
OAI22X4TS U4753 ( .A0(n3263), .A1(n2438), .B0(n3262), .B1(n2407), .Y(n2791)
);
NOR2X8TS U4754 ( .A(n2794), .B(n2793), .Y(n2792) );
NOR2X8TS U4755 ( .A(n3302), .B(intDY_EWSW[2]), .Y(n2793) );
OR2X8TS U4756 ( .A(n3288), .B(intDY_EWSW[3]), .Y(n2795) );
OAI21X4TS U4757 ( .A0(n2799), .A1(n2798), .B0(n2796), .Y(n1225) );
AOI22X4TS U4758 ( .A0(n2797), .A1(n5925), .B0(Raw_mant_NRM_SWR[44]), .B1(
n5638), .Y(n2796) );
XOR2X4TS U4759 ( .A(n2800), .B(n5047), .Y(n2799) );
NAND3X8TS U4760 ( .A(n2312), .B(n2300), .C(n2347), .Y(n2804) );
AND2X8TS U4761 ( .A(n2338), .B(n2595), .Y(n2810) );
NAND2X8TS U4762 ( .A(n2816), .B(n2814), .Y(n3197) );
OR2X8TS U4763 ( .A(n5176), .B(n5037), .Y(n2815) );
AND2X8TS U4764 ( .A(n4649), .B(n5173), .Y(n3202) );
NOR2X8TS U4765 ( .A(n3597), .B(n2817), .Y(n3599) );
NOR2X8TS U4766 ( .A(n3294), .B(intDY_EWSW[47]), .Y(n3597) );
BUFX20TS U4767 ( .A(n4287), .Y(n2822) );
NOR2X8TS U4768 ( .A(n2828), .B(n2826), .Y(n2825) );
NAND3X8TS U4769 ( .A(n2831), .B(n2830), .C(n2829), .Y(n2828) );
OA22X4TS U4770 ( .A0(n4312), .A1(n2551), .B0(n4039), .B1(n2887), .Y(n2830)
);
NAND2X8TS U4771 ( .A(n2838), .B(n2837), .Y(n2836) );
NOR2X4TS U4772 ( .A(Raw_mant_NRM_SWR[30]), .B(Raw_mant_NRM_SWR[26]), .Y(
n3379) );
NAND3X8TS U4773 ( .A(n2845), .B(n2844), .C(n2843), .Y(n1228) );
NAND2X6TS U4774 ( .A(n6952), .B(n5557), .Y(n4521) );
AOI2BB2X4TS U4775 ( .B0(n6605), .B1(n2250), .A0N(n3996), .A1N(n2211), .Y(
n3991) );
BUFX6TS U4776 ( .A(intDY_EWSW[7]), .Y(n2847) );
AOI21X4TS U4777 ( .A0(n3526), .A1(n3525), .B0(n3524), .Y(n3527) );
NAND2X2TS U4778 ( .A(n4389), .B(n1742), .Y(n4022) );
NOR2X8TS U4779 ( .A(n5553), .B(n4024), .Y(n6973) );
NOR2X2TS U4780 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[34]), .Y(
n3367) );
OAI21X2TS U4781 ( .A0(n6008), .A1(n6007), .B0(n6006), .Y(n6012) );
NOR2X4TS U4782 ( .A(n5318), .B(n5317), .Y(n6852) );
NOR2X4TS U4783 ( .A(n5326), .B(n5325), .Y(n6838) );
NOR2X4TS U4784 ( .A(n5320), .B(n5319), .Y(n6846) );
NOR2X4TS U4785 ( .A(n5322), .B(n5321), .Y(n6853) );
NOR2X4TS U4786 ( .A(sub_x_1_n32), .B(DMP_EXP_EWSW[54]), .Y(n5998) );
AOI22X4TS U4787 ( .A0(n4809), .A1(n5639), .B0(n5912), .B1(n5638), .Y(n6778)
);
OAI21X2TS U4788 ( .A0(n5999), .A1(n5998), .B0(n5997), .Y(n6004) );
NOR2X4TS U4789 ( .A(n3611), .B(n3564), .Y(n3613) );
NOR2X8TS U4790 ( .A(n1962), .B(n4800), .Y(n5634) );
AOI21X4TS U4791 ( .A0(n3613), .A1(n3614), .B0(n3612), .Y(n3626) );
AOI22X2TS U4792 ( .A0(n4751), .A1(n5925), .B0(n2286), .B1(n5924), .Y(n4752)
);
AOI2BB2X4TS U4793 ( .B0(n5585), .B1(n5639), .A0N(n5807), .A1N(n2459), .Y(
n6776) );
AOI21X4TS U4794 ( .A0(n1918), .A1(n5582), .B0(n5581), .Y(n5584) );
NAND2X4TS U4795 ( .A(n3121), .B(n3118), .Y(n1231) );
NAND2X4TS U4796 ( .A(n6970), .B(n5557), .Y(n4019) );
NAND2X4TS U4797 ( .A(n3565), .B(n3613), .Y(n3569) );
NOR2X8TS U4798 ( .A(n3569), .B(n3625), .Y(n3570) );
NAND2X4TS U4799 ( .A(n2490), .B(n1749), .Y(n4012) );
AND2X8TS U4800 ( .A(n4315), .B(n6832), .Y(n3943) );
XOR2X4TS U4801 ( .A(n4720), .B(n4719), .Y(n4726) );
AOI21X4TS U4802 ( .A0(n3116), .A1(n4619), .B0(n4421), .Y(n2948) );
NAND2X2TS U4803 ( .A(n4315), .B(n1729), .Y(n4316) );
AOI22X2TS U4804 ( .A0(n6946), .A1(n2486), .B0(DmP_mant_SFG_SWR[23]), .B1(
n5756), .Y(n5677) );
NAND3X6TS U4805 ( .A(n3127), .B(n4706), .C(n4147), .Y(n3236) );
OAI21X4TS U4806 ( .A0(n6032), .A1(n6033), .B0(n6035), .Y(n6034) );
NAND2X2TS U4807 ( .A(n5011), .B(n4914), .Y(n4438) );
AOI21X2TS U4808 ( .A0(n2549), .A1(n4440), .B0(n4439), .Y(n4443) );
XNOR2X4TS U4809 ( .A(n2853), .B(n4750), .Y(n4751) );
OAI2BB1X4TS U4810 ( .A0N(n4749), .A1N(n2506), .B0(n2318), .Y(n2853) );
NOR3X2TS U4811 ( .A(n4902), .B(Raw_mant_NRM_SWR[2]), .C(n6477), .Y(n4349) );
NAND2X2TS U4812 ( .A(n2490), .B(n1733), .Y(n4007) );
AOI21X4TS U4813 ( .A0(n4811), .A1(n4430), .B0(n4429), .Y(n2950) );
OAI2BB1X4TS U4814 ( .A0N(n5630), .A1N(n5629), .B0(n5628), .Y(n1251) );
NOR2X4TS U4815 ( .A(n4500), .B(n3383), .Y(n3384) );
NOR2X8TS U4816 ( .A(n6337), .B(DMP_SFG[2]), .Y(n5951) );
NAND2X2TS U4817 ( .A(n3264), .B(intDY_EWSW[6]), .Y(n3482) );
NAND2X2TS U4818 ( .A(n4388), .B(n1729), .Y(n4045) );
NAND2X6TS U4819 ( .A(n4090), .B(n4095), .Y(n4091) );
OAI21X4TS U4820 ( .A0(n4822), .A1(n4816), .B0(n4817), .Y(n4892) );
AOI21X4TS U4821 ( .A0(n5239), .A1(n5161), .B0(n5160), .Y(n5166) );
AOI22X2TS U4822 ( .A0(n2502), .A1(n1713), .B0(n5720), .B1(n1705), .Y(n5195)
);
AOI22X2TS U4823 ( .A0(n6976), .A1(n2486), .B0(DmP_mant_SFG_SWR[9]), .B1(
n5756), .Y(n5631) );
NAND2X6TS U4824 ( .A(n4914), .B(n4644), .Y(n4646) );
AOI21X4TS U4825 ( .A0(n3635), .A1(n3634), .B0(n3633), .Y(n3642) );
NOR2X8TS U4826 ( .A(shift_value_SHT2_EWR[2]), .B(n3461), .Y(n3454) );
NAND2X2TS U4827 ( .A(n3281), .B(intDY_EWSW[59]), .Y(n3630) );
AOI21X4TS U4828 ( .A0(n3579), .A1(n3578), .B0(n3577), .Y(n3589) );
AOI21X4TS U4829 ( .A0(n5004), .A1(n4983), .B0(n4982), .Y(n4984) );
NOR2X6TS U4830 ( .A(n3185), .B(n2995), .Y(n4905) );
NOR2X8TS U4831 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[15]), .Y(
n5690) );
NAND4X2TS U4832 ( .A(n5690), .B(n6194), .C(Raw_mant_NRM_SWR[0]), .D(n6477),
.Y(n4365) );
NAND2X2TS U4833 ( .A(n4388), .B(n1726), .Y(n5567) );
AOI22X2TS U4834 ( .A0(n5716), .A1(n5715), .B0(n5714), .B1(n5713), .Y(n5725)
);
NAND2X2TS U4835 ( .A(n6303), .B(DMP_SFG[39]), .Y(n5157) );
NAND3X8TS U4836 ( .A(n2964), .B(n2856), .C(n2855), .Y(n1229) );
OAI21X2TS U4837 ( .A0(n5159), .A1(n5158), .B0(n5157), .Y(n5160) );
NOR2X8TS U4838 ( .A(n3173), .B(n3230), .Y(n3172) );
NAND2X2TS U4839 ( .A(n3275), .B(intDY_EWSW[26]), .Y(n3534) );
AOI21X4TS U4840 ( .A0(n3538), .A1(n3537), .B0(n3536), .Y(n3550) );
NAND2X8TS U4841 ( .A(n2956), .B(n2953), .Y(n3026) );
OAI2BB1X4TS U4842 ( .A0N(n6721), .A1N(n3029), .B0(n3027), .Y(n1221) );
XOR2X4TS U4843 ( .A(n4999), .B(n4998), .Y(n5010) );
XOR2X4TS U4844 ( .A(n4688), .B(n4687), .Y(n4697) );
XOR2X4TS U4845 ( .A(n4890), .B(n4889), .Y(n4901) );
OAI2BB1X4TS U4846 ( .A0N(n5630), .A1N(n4901), .B0(n4900), .Y(n1244) );
NAND4X2TS U4847 ( .A(n5685), .B(n4588), .C(Raw_mant_NRM_SWR[37]), .D(n6128),
.Y(n4594) );
OR2X8TS U4848 ( .A(n4657), .B(n5127), .Y(n5156) );
OAI21X2TS U4849 ( .A0(n5025), .A1(n4936), .B0(n4935), .Y(n4937) );
NOR2X2TS U4850 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n4501) );
NAND2X4TS U4851 ( .A(n2421), .B(DMP_SFG[20]), .Y(n4822) );
NOR2X6TS U4852 ( .A(n6302), .B(DMP_SFG[12]), .Y(n4400) );
NOR2X4TS U4853 ( .A(n3535), .B(n3513), .Y(n3537) );
AOI21X4TS U4854 ( .A0(n3586), .A1(n3585), .B0(n3584), .Y(n3587) );
BUFX20TS U4855 ( .A(n4189), .Y(n2993) );
AOI22X2TS U4856 ( .A0(n2513), .A1(n5705), .B0(n5702), .B1(n5722), .Y(n5575)
);
XOR2X4TS U4857 ( .A(n5093), .B(n5092), .Y(n5108) );
AOI21X2TS U4858 ( .A0(n5689), .A1(n2286), .B0(n5688), .Y(n5696) );
NOR2X1TS U4859 ( .A(n3382), .B(Raw_mant_NRM_SWR[41]), .Y(n3383) );
NOR2X4TS U4860 ( .A(n3349), .B(DMP_SFG[36]), .Y(n4651) );
AOI22X2TS U4861 ( .A0(n1970), .A1(n4616), .B0(n5667), .B1(n2513), .Y(n4379)
);
NAND4X4TS U4862 ( .A(n4379), .B(n4378), .C(n5574), .D(n4377), .Y(n5578) );
NOR2X6TS U4863 ( .A(n3359), .B(DMP_SFG[45]), .Y(n4971) );
OR2X8TS U4864 ( .A(n5336), .B(n4397), .Y(n2957) );
AOI21X4TS U4865 ( .A0(n5929), .A1(n4392), .B0(n4391), .Y(n5336) );
OAI21X4TS U4866 ( .A0(n4972), .A1(n4971), .B0(n4970), .Y(n4973) );
NAND4X4TS U4867 ( .A(n3987), .B(n3986), .C(n3985), .D(n3984), .Y(n1713) );
OAI21X4TS U4868 ( .A0(n3544), .A1(n3543), .B0(n3542), .Y(n3545) );
NOR3X4TS U4869 ( .A(n4314), .B(n4313), .C(n4555), .Y(n4322) );
AOI21X4TS U4870 ( .A0(n3623), .A1(n3622), .B0(n3621), .Y(n3624) );
NAND2X2TS U4871 ( .A(n3323), .B(intDY_EWSW[53]), .Y(n3615) );
AOI21X4TS U4872 ( .A0(n2609), .A1(n5610), .B0(n5609), .Y(n5612) );
OAI2BB1X4TS U4873 ( .A0N(n4151), .A1N(n4960), .B0(n2859), .Y(n5167) );
AOI22X2TS U4874 ( .A0(n5614), .A1(n5639), .B0(n5613), .B1(n5638), .Y(n6777)
);
NAND2X2TS U4875 ( .A(n3845), .B(intDY_EWSW[60]), .Y(n3680) );
AOI21X2TS U4876 ( .A0(n2549), .A1(n4925), .B0(n4924), .Y(n4930) );
NAND2X2TS U4877 ( .A(DMP_SFG[48]), .B(DmP_mant_SFG_SWR[50]), .Y(n5579) );
NOR2X4TS U4878 ( .A(n4915), .B(n4918), .Y(n4921) );
AOI21X2TS U4879 ( .A0(n5016), .A1(n4921), .B0(n4920), .Y(n4922) );
AOI21X4TS U4880 ( .A0(n3600), .A1(n3599), .B0(n3598), .Y(n3601) );
NOR2X4TS U4881 ( .A(n3561), .B(n3588), .Y(n3562) );
XNOR2X4TS U4882 ( .A(n2609), .B(n4949), .Y(n4950) );
NAND2X2TS U4883 ( .A(DMP_SFG[23]), .B(DmP_mant_SFG_SWR[25]), .Y(n4887) );
AOI21X4TS U4884 ( .A0(n2609), .A1(n5636), .B0(n5635), .Y(n5637) );
AND2X8TS U4885 ( .A(n2935), .B(n2933), .Y(n2923) );
NAND4X4TS U4886 ( .A(n3419), .B(n3418), .C(n3417), .D(n3416), .Y(n1712) );
NAND2X2TS U4887 ( .A(n2848), .B(intDX_EWSW[21]), .Y(n3724) );
NAND2X2TS U4888 ( .A(n5563), .B(n1746), .Y(n3462) );
NAND2X4TS U4889 ( .A(n2841), .B(n6460), .Y(n3426) );
NAND2X2TS U4890 ( .A(n1985), .B(DMP_SFG[20]), .Y(n4425) );
NAND2X2TS U4891 ( .A(n3271), .B(intDY_EWSW[24]), .Y(n3531) );
AOI22X2TS U4892 ( .A0(n2513), .A1(n2323), .B0(n5701), .B1(n5722), .Y(n5569)
);
NAND4X4TS U4893 ( .A(n5570), .B(n5569), .C(n5703), .D(n5568), .Y(n5679) );
AOI21X4TS U4894 ( .A0(n3234), .A1(n5096), .B0(n5104), .Y(n3240) );
OAI21X2TS U4895 ( .A0(n5025), .A1(n4844), .B0(n4843), .Y(n4845) );
OAI21X4TS U4896 ( .A0(n6027), .A1(n6026), .B0(n6031), .Y(n6038) );
NAND3X4TS U4897 ( .A(n3913), .B(n3912), .C(n3911), .Y(n5498) );
OAI2BB1X2TS U4898 ( .A0N(n2558), .A1N(n6975), .B0(n5631), .Y(n1147) );
AND2X8TS U4899 ( .A(n2861), .B(n2769), .Y(n4498) );
NOR2X4TS U4900 ( .A(n5087), .B(n4669), .Y(n4670) );
OAI21X2TS U4901 ( .A0(n4886), .A1(n5063), .B0(n4887), .Y(n4136) );
XOR2X4TS U4902 ( .A(n4704), .B(n4703), .Y(n4711) );
AOI21X4TS U4903 ( .A0(n3486), .A1(n3485), .B0(n3484), .Y(n3487) );
AOI22X4TS U4904 ( .A0(n5183), .A1(n5925), .B0(Raw_mant_NRM_SWR[35]), .B1(
n5638), .Y(n5184) );
AOI22X2TS U4905 ( .A0(n5702), .A1(n5715), .B0(n5714), .B1(n1970), .Y(n5570)
);
NAND2X8TS U4906 ( .A(n5174), .B(n4649), .Y(n5127) );
NAND2X2TS U4907 ( .A(n4503), .B(n4502), .Y(n4511) );
AOI22X2TS U4908 ( .A0(n2498), .A1(n2323), .B0(n5715), .B1(n1970), .Y(n5576)
);
AOI22X2TS U4909 ( .A0(n4637), .A1(n5527), .B0(Raw_mant_NRM_SWR[15]), .B1(
n5030), .Y(n4638) );
XOR2X4TS U4910 ( .A(n5600), .B(n5599), .Y(n5601) );
XOR2X4TS U4911 ( .A(n4708), .B(n4707), .Y(n4709) );
NOR2X4TS U4912 ( .A(add_x_6_A_6_), .B(add_x_6_B_6_), .Y(n5457) );
NOR2X8TS U4913 ( .A(n5457), .B(add_x_6_n515), .Y(n5987) );
NAND2X4TS U4914 ( .A(n3318), .B(n2130), .Y(n3575) );
OAI21X4TS U4915 ( .A0(n3589), .A1(n3588), .B0(n3587), .Y(n3605) );
NAND2X4TS U4916 ( .A(n3217), .B(n3224), .Y(n1226) );
BUFX20TS U4917 ( .A(ADD_OVRFLW_NRM2), .Y(n3092) );
AOI21X4TS U4918 ( .A0(n4478), .A1(n2381), .B0(n4477), .Y(n6916) );
MXI2X4TS U4919 ( .A(n6916), .B(n6302), .S0(n5885), .Y(n1142) );
NOR2X2TS U4920 ( .A(n4081), .B(n4077), .Y(n4078) );
NAND2X8TS U4921 ( .A(n2863), .B(Shift_reg_FLAGS_7_6), .Y(n3012) );
NAND3X6TS U4922 ( .A(n2946), .B(n2945), .C(n5538), .Y(n2944) );
NAND2X4TS U4923 ( .A(n3514), .B(n3537), .Y(n3515) );
AOI21X4TS U4924 ( .A0(n4416), .A1(n2518), .B0(n4390), .Y(n6968) );
NAND2X8TS U4925 ( .A(n2943), .B(n2864), .Y(n4416) );
NOR2X8TS U4926 ( .A(n2342), .B(n2865), .Y(n2864) );
BUFX20TS U4927 ( .A(n2994), .Y(n3775) );
NAND2X2TS U4928 ( .A(n4121), .B(intDY_EWSW[17]), .Y(n4268) );
NAND2X6TS U4929 ( .A(n6083), .B(n1562), .Y(n6084) );
BUFX20TS U4930 ( .A(n2994), .Y(n3023) );
NAND2X2TS U4931 ( .A(n3846), .B(intDY_EWSW[32]), .Y(n4219) );
OAI21X4TS U4932 ( .A0(n3216), .A1(n4547), .B0(n4134), .Y(n3126) );
AOI21X4TS U4933 ( .A0(n3234), .A1(n5168), .B0(n2409), .Y(n3258) );
OAI21X2TS U4934 ( .A0(n4653), .A1(n5111), .B0(n4652), .Y(n4654) );
XNOR2X2TS U4935 ( .A(n4408), .B(n4407), .Y(n4413) );
INVX2TS U4936 ( .A(n5515), .Y(n4618) );
NAND2X4TS U4937 ( .A(n4891), .B(n4893), .Y(n5067) );
NOR2BX4TS U4938 ( .AN(n4479), .B(n3004), .Y(n2871) );
NAND2X8TS U4939 ( .A(n3948), .B(n2879), .Y(n5053) );
NOR2X8TS U4940 ( .A(n2880), .B(n2373), .Y(n2879) );
AOI22X4TS U4941 ( .A0(n6976), .A1(n2558), .B0(DmP_mant_SFG_SWR[45]), .B1(
n5756), .Y(n2882) );
OA21X4TS U4942 ( .A0(n4559), .A1(n5551), .B0(n5198), .Y(n6976) );
AOI22X2TS U4943 ( .A0(n2502), .A1(n1715), .B0(n5720), .B1(n1707), .Y(n2884)
);
NAND2BX4TS U4944 ( .AN(n2885), .B(n3906), .Y(n1707) );
OAI21X4TS U4945 ( .A0(n6036), .A1(n2344), .B0(n6057), .Y(n6056) );
NAND2X8TS U4946 ( .A(n6969), .B(n2557), .Y(n4018) );
AOI22X4TS U4947 ( .A0(n2842), .A1(n2497), .B0(n5053), .B1(n5572), .Y(n2889)
);
NAND2X2TS U4948 ( .A(n2607), .B(DmP_mant_SFG_SWR[40]), .Y(n2893) );
NAND2X8TS U4949 ( .A(n3946), .B(n2894), .Y(n4640) );
AOI21X4TS U4950 ( .A0(n2523), .A1(n1730), .B0(n2895), .Y(n2894) );
OAI21X4TS U4951 ( .A0(n6902), .A1(n2414), .B0(n2903), .Y(n1152) );
AOI21X4TS U4952 ( .A0(n4380), .A1(n2381), .B0(n2904), .Y(n6902) );
AOI21X4TS U4953 ( .A0(n4640), .A1(n2498), .B0(n2907), .Y(n2906) );
AOI21X4TS U4954 ( .A0(n4380), .A1(n2518), .B0(n2912), .Y(n6988) );
NAND3X4TS U4955 ( .A(n2915), .B(n2914), .C(n2913), .Y(n2912) );
AOI21X4TS U4956 ( .A0(n5053), .A1(n1971), .B0(n2699), .Y(n2914) );
NAND2BX4TS U4957 ( .AN(n2916), .B(n4012), .Y(n5203) );
AOI21X4TS U4958 ( .A0(n4389), .A1(n1741), .B0(n1973), .Y(n2917) );
NAND3X8TS U4959 ( .A(n4002), .B(n2919), .C(n2918), .Y(n1741) );
NAND3X8TS U4960 ( .A(n2923), .B(n3998), .C(n3997), .Y(n1745) );
INVX12TS U4961 ( .A(n3178), .Y(n5685) );
NOR2X8TS U4962 ( .A(n4572), .B(n2924), .Y(n4597) );
NAND2BX4TS U4963 ( .AN(n3178), .B(n4571), .Y(n2924) );
AND2X8TS U4964 ( .A(n2338), .B(n2595), .Y(n5684) );
AOI21X4TS U4965 ( .A0(n1749), .A1(n2477), .B0(n2373), .Y(n2927) );
NAND3X8TS U4966 ( .A(n3999), .B(n2929), .C(n2928), .Y(n1749) );
AOI21X4TS U4967 ( .A0(n5488), .A1(n5653), .B0(n2577), .Y(n2939) );
OAI21X4TS U4968 ( .A0(n6912), .A1(n2514), .B0(n2940), .Y(n1144) );
AOI21X4TS U4969 ( .A0(n4416), .A1(n2381), .B0(n2941), .Y(n6912) );
AOI21X4TS U4970 ( .A0(n5544), .A1(n5486), .B0(n2944), .Y(n2943) );
NOR2X8TS U4971 ( .A(n2949), .B(n4727), .Y(n4885) );
AOI21X4TS U4972 ( .A0(n4884), .A1(n4647), .B0(n2954), .Y(n2953) );
NAND2BX4TS U4973 ( .AN(n2958), .B(n5494), .Y(n1130) );
AOI21X4TS U4974 ( .A0(n5486), .A1(n5653), .B0(n2577), .Y(n2960) );
XOR2X4TS U4975 ( .A(n2963), .B(n2376), .Y(n2962) );
AOI21X4TS U4976 ( .A0(n2552), .A1(n2355), .B0(n3048), .Y(n2963) );
OAI2BB1X4TS U4977 ( .A0N(n2840), .A1N(Raw_mant_NRM_SWR[20]), .B0(n2967), .Y(
n2966) );
OAI2BB1X4TS U4978 ( .A0N(n3387), .A1N(n5685), .B0(n3390), .Y(n2968) );
NAND2X4TS U4979 ( .A(n3397), .B(Raw_mant_NRM_SWR[24]), .Y(n2971) );
NAND2BX4TS U4980 ( .AN(n2975), .B(n5571), .Y(n5680) );
NAND3X8TS U4981 ( .A(n5564), .B(n2978), .C(n5566), .Y(n5714) );
AND2X8TS U4982 ( .A(n5565), .B(n5567), .Y(n2978) );
AOI21X4TS U4983 ( .A0(n5722), .A1(n5572), .B0(n2980), .Y(n2979) );
NOR2BX4TS U4984 ( .AN(n3463), .B(n2373), .Y(n2981) );
NAND2X8TS U4985 ( .A(n2357), .B(n5560), .Y(n5715) );
OR2X8TS U4986 ( .A(n5709), .B(n2986), .Y(n2985) );
NAND2BX4TS U4987 ( .AN(n2987), .B(n5704), .Y(n2986) );
NAND2X4TS U4988 ( .A(n2989), .B(n2988), .Y(n2987) );
AOI21X4TS U4989 ( .A0(n2323), .A1(n5702), .B0(n3004), .Y(n2988) );
NOR2X8TS U4990 ( .A(n3326), .B(intDY_EWSW[31]), .Y(n3544) );
NOR2X4TS U4991 ( .A(n4584), .B(n2995), .Y(n3397) );
NAND2BX4TS U4992 ( .AN(n2997), .B(n5559), .Y(n1112) );
NAND2X8TS U4993 ( .A(n3000), .B(n2999), .Y(n1119) );
NAND2X8TS U4994 ( .A(n5577), .B(n3001), .Y(n3000) );
NAND2X8TS U4995 ( .A(n2346), .B(n4617), .Y(n5577) );
NOR2X8TS U4996 ( .A(n6093), .B(n6203), .Y(n5645) );
NAND3X8TS U4997 ( .A(n4375), .B(n4373), .C(n3007), .Y(n5669) );
OAI21X4TS U4998 ( .A0(n4483), .A1(n5707), .B0(n4481), .Y(n3011) );
XOR2X4TS U4999 ( .A(n3018), .B(n5126), .Y(n3017) );
AOI21X4TS U5000 ( .A0(n2609), .A1(n5125), .B0(n5124), .Y(n3018) );
XOR2X4TS U5001 ( .A(n3022), .B(n5121), .Y(n3021) );
AOI21X4TS U5002 ( .A0(n5239), .A1(n3215), .B0(n3197), .Y(n3022) );
NOR2X8TS U5003 ( .A(n3290), .B(intDY_EWSW[21]), .Y(n3520) );
INVX12TS U5004 ( .A(n3024), .Y(n4600) );
NOR2X8TS U5005 ( .A(n5337), .B(n5451), .Y(n5972) );
NOR2X8TS U5006 ( .A(n4394), .B(n5976), .Y(n4396) );
NOR2X8TS U5007 ( .A(n3360), .B(DMP_SFG[5]), .Y(n5976) );
NOR2X8TS U5008 ( .A(n3354), .B(DMP_SFG[6]), .Y(n4394) );
AOI21X4TS U5009 ( .A0(n2552), .A1(n5139), .B0(n5138), .Y(n5143) );
AOI21X4TS U5010 ( .A0(n2609), .A1(n4987), .B0(n4986), .Y(n3028) );
NAND2BX4TS U5011 ( .AN(n3032), .B(n5511), .Y(n1132) );
AOI21X4TS U5012 ( .A0(n5509), .A1(n5673), .B0(n2577), .Y(n3035) );
NAND2X4TS U5013 ( .A(n1137), .B(n1556), .Y(n6035) );
AOI22X4TS U5014 ( .A0(n6979), .A1(n2756), .B0(n5756), .B1(
DmP_mant_SFG_SWR[46]), .Y(n5554) );
NAND2X8TS U5015 ( .A(n2329), .B(n2558), .Y(n3038) );
OAI2BB1X4TS U5016 ( .A0N(n2557), .A1N(n5735), .B0(n5731), .Y(n1156) );
OAI2BB1X4TS U5017 ( .A0N(n2558), .A1N(n6981), .B0(n5200), .Y(n1149) );
OAI2BB1X4TS U5018 ( .A0N(n2756), .A1N(n6978), .B0(n5555), .Y(n1148) );
OAI2BB1X4TS U5019 ( .A0N(n2756), .A1N(n6994), .B0(n5676), .Y(n1155) );
NAND2X8TS U5020 ( .A(n3038), .B(n3037), .Y(n1154) );
AOI21X4TS U5021 ( .A0(n4615), .A1(n2518), .B0(n3042), .Y(n6987) );
NAND3BX4TS U5022 ( .AN(n3043), .B(n4178), .C(n4179), .Y(n3042) );
OAI21X4TS U5023 ( .A0(n5137), .A1(n5112), .B0(n5111), .Y(n3048) );
NOR2X8TS U5024 ( .A(n3049), .B(n2408), .Y(n5137) );
XOR2X4TS U5025 ( .A(n3061), .B(n5040), .Y(n3054) );
OAI21X4TS U5026 ( .A0(n5035), .A1(n3060), .B0(n6721), .Y(n3057) );
NAND2BX1TS U5027 ( .AN(n2459), .B(n2429), .Y(n3062) );
AND2X8TS U5028 ( .A(n4588), .B(n5685), .Y(n4912) );
XOR2X4TS U5029 ( .A(n3064), .B(n5221), .Y(n4809) );
AOI21X4TS U5030 ( .A0(n4806), .A1(n1918), .B0(n3065), .Y(n3064) );
OAI2BB1X4TS U5031 ( .A0N(n3071), .A1N(n5928), .B0(n5032), .Y(n1239) );
XNOR2X4TS U5032 ( .A(n3072), .B(n5021), .Y(n3071) );
NAND3BX4TS U5033 ( .AN(n3075), .B(n5017), .C(n3073), .Y(n3072) );
NOR2BX4TS U5034 ( .AN(n5685), .B(n4572), .Y(n3083) );
NOR2X8TS U5035 ( .A(DmP_mant_SFG_SWR[15]), .B(DMP_SFG[13]), .Y(n4624) );
XNOR2X4TS U5036 ( .A(n3084), .B(n4472), .Y(n4473) );
NAND2BX4TS U5037 ( .AN(n3087), .B(n2463), .Y(n3086) );
NOR2X8TS U5038 ( .A(n4464), .B(n4467), .Y(n3089) );
NAND2BX4TS U5039 ( .AN(n3092), .B(DMP_exp_NRM2_EW[6]), .Y(n4076) );
NOR2BX4TS U5040 ( .AN(n3092), .B(DMP_exp_NRM2_EW[6]), .Y(n3094) );
NAND2BX4TS U5041 ( .AN(n3092), .B(DMP_exp_NRM2_EW[7]), .Y(n4084) );
NOR2BX4TS U5042 ( .AN(n3092), .B(DMP_exp_NRM2_EW[7]), .Y(n3095) );
XNOR2X4TS U5043 ( .A(n3255), .B(n2275), .Y(n3254) );
INVX8TS U5044 ( .A(n3126), .Y(n3125) );
NAND2X8TS U5045 ( .A(n3947), .B(n2477), .Y(n3452) );
NAND3BX4TS U5046 ( .AN(n4005), .B(n4004), .C(n4003), .Y(n5189) );
NAND2X4TS U5047 ( .A(n3399), .B(n5685), .Y(n4593) );
OAI2BB1X4TS U5048 ( .A0N(n5928), .A1N(n4868), .B0(n4867), .Y(n1223) );
AOI21X4TS U5049 ( .A0(n4932), .A1(n4143), .B0(n4142), .Y(n4144) );
OAI21X4TS U5050 ( .A0(n4145), .A1(n5023), .B0(n4144), .Y(n4146) );
XOR2X4TS U5051 ( .A(n3103), .B(n4449), .Y(n3102) );
NOR2BX4TS U5052 ( .AN(n3104), .B(n4448), .Y(n3103) );
NOR2X8TS U5053 ( .A(DmP_mant_SFG_SWR[29]), .B(DMP_SFG[27]), .Y(n4847) );
NOR2X8TS U5054 ( .A(DmP_mant_SFG_SWR[28]), .B(DMP_SFG[26]), .Y(n4744) );
NOR2X8TS U5055 ( .A(n4778), .B(add_x_6_n343), .Y(n4838) );
XOR2X4TS U5056 ( .A(n3106), .B(n2324), .Y(n4764) );
AOI2BB2X4TS U5057 ( .B0(n5625), .B1(n3108), .A0N(n5025), .A1N(n3109), .Y(
n3107) );
OAI21X4TS U5058 ( .A0(n5449), .A1(n5451), .B0(n5452), .Y(n5974) );
NOR2X8TS U5059 ( .A(n4540), .B(n4400), .Y(n4620) );
AOI21X4TS U5060 ( .A0(n5974), .A1(n4396), .B0(n4395), .Y(n3117) );
AOI22X4TS U5061 ( .A0(n3119), .A1(n4966), .B0(Raw_mant_NRM_SWR[38]), .B1(
n3343), .Y(n3118) );
XOR2X4TS U5062 ( .A(n3120), .B(n5135), .Y(n3119) );
AOI21X4TS U5063 ( .A0(n3234), .A1(n5134), .B0(n5133), .Y(n3120) );
NAND2X8TS U5064 ( .A(n3124), .B(n2321), .Y(n3123) );
XOR2X4TS U5065 ( .A(n3129), .B(n4060), .Y(n3192) );
NOR2X8TS U5066 ( .A(DmP_mant_SFG_SWR[9]), .B(DMP_SFG[7]), .Y(n5742) );
NOR2X8TS U5067 ( .A(DmP_mant_SFG_SWR[8]), .B(DMP_SFG[6]), .Y(n5981) );
NAND2BX4TS U5068 ( .AN(n4099), .B(n4096), .Y(n3132) );
OAI2BB1X4TS U5069 ( .A0N(n6721), .A1N(n5010), .B0(n3137), .Y(n1222) );
AOI22X4TS U5070 ( .A0(n3138), .A1(n5639), .B0(n3343), .B1(n1912), .Y(n3137)
);
XNOR2X4TS U5071 ( .A(n5008), .B(n5009), .Y(n3138) );
NAND2X8TS U5072 ( .A(n4409), .B(n3141), .Y(n3140) );
NAND2X8TS U5073 ( .A(n3143), .B(n3142), .Y(n4409) );
AOI21X4TS U5074 ( .A0(n5986), .A1(n4129), .B0(n4128), .Y(n3142) );
AOI21X4TS U5075 ( .A0(n3234), .A1(n5149), .B0(n5148), .Y(n3147) );
NOR2BX4TS U5076 ( .AN(n3149), .B(n4351), .Y(n4598) );
NOR3X8TS U5077 ( .A(Raw_mant_NRM_SWR[30]), .B(Raw_mant_NRM_SWR[29]), .C(
Raw_mant_NRM_SWR[33]), .Y(n3150) );
NOR2X8TS U5078 ( .A(n3155), .B(n3156), .Y(n3159) );
NAND2X1TS U5079 ( .A(n4596), .B(n6123), .Y(n3162) );
AND3X8TS U5080 ( .A(n4594), .B(n4592), .C(n4593), .Y(n3163) );
NAND3X8TS U5081 ( .A(n3169), .B(n2769), .C(n3170), .Y(n4786) );
NAND3X8TS U5082 ( .A(n3389), .B(n2371), .C(n2110), .Y(n4353) );
NAND3X6TS U5083 ( .A(n3229), .B(n6469), .C(n6475), .Y(n3173) );
NOR2X8TS U5084 ( .A(n2327), .B(n1960), .Y(n3230) );
NOR2BX4TS U5085 ( .AN(n3182), .B(n4365), .Y(n3181) );
NAND3X8TS U5086 ( .A(n3371), .B(n3183), .C(n4350), .Y(n4364) );
AND2X8TS U5087 ( .A(n3379), .B(n6089), .Y(n3184) );
AND2X8TS U5088 ( .A(n4494), .B(n3378), .Y(n3187) );
AO21X4TS U5089 ( .A0(n3188), .A1(n6126), .B0(n2633), .Y(n4575) );
OAI2BB1X4TS U5090 ( .A0N(n3201), .A1N(n3194), .B0(n4668), .Y(n3193) );
NAND2X8TS U5091 ( .A(n3200), .B(n2328), .Y(n3201) );
NAND2X8TS U5092 ( .A(n3197), .B(n3199), .Y(n3196) );
OAI21X4TS U5093 ( .A0(n3202), .A1(n4648), .B0(n3199), .Y(n3198) );
OAI21X4TS U5094 ( .A0(n5157), .A1(n5162), .B0(n5163), .Y(n5077) );
XOR2X4TS U5095 ( .A(n3204), .B(n3203), .Y(N92) );
NAND2X8TS U5096 ( .A(n5076), .B(n4661), .Y(n5087) );
NOR2X8TS U5097 ( .A(n5162), .B(n5158), .Y(n5076) );
AOI21X4TS U5098 ( .A0(n2552), .A1(n3212), .B0(n3208), .Y(n4859) );
NAND2X8TS U5099 ( .A(n3222), .B(n3220), .Y(n3219) );
XNOR2X4TS U5100 ( .A(n5083), .B(n5085), .Y(n3225) );
INVX2TS U5101 ( .A(n3229), .Y(n3228) );
NAND2X8TS U5102 ( .A(n5698), .B(n3232), .Y(n5737) );
AOI21X4TS U5103 ( .A0(n4705), .A1(n4147), .B0(n4146), .Y(n3235) );
NOR2X8TS U5104 ( .A(DMP_SFG[30]), .B(DmP_mant_SFG_SWR[32]), .Y(n4926) );
NAND2X8TS U5105 ( .A(n5966), .B(n2362), .Y(n5986) );
NAND2BX4TS U5106 ( .AN(n2283), .B(add_x_6_A_7_), .Y(n5966) );
AOI22X4TS U5107 ( .A0(n3239), .A1(n5925), .B0(n5924), .B1(
Raw_mant_NRM_SWR[45]), .Y(n5107) );
XOR2X4TS U5108 ( .A(n3240), .B(n5106), .Y(n3239) );
OAI2BB1X4TS U5109 ( .A0N(n5630), .A1N(n4783), .B0(n3241), .Y(n1242) );
AOI22X4TS U5110 ( .A0(n3242), .A1(n5527), .B0(n5030), .B1(
Raw_mant_NRM_SWR[27]), .Y(n3241) );
XNOR2X4TS U5111 ( .A(n3243), .B(n4782), .Y(n3242) );
AO21X4TS U5112 ( .A0(n4780), .A1(n2506), .B0(n4779), .Y(n3243) );
OAI2BB1X4TS U5113 ( .A0N(n5630), .A1N(n4737), .B0(n3244), .Y(n1247) );
AOI22X4TS U5114 ( .A0(n3245), .A1(n5626), .B0(n5030), .B1(
Raw_mant_NRM_SWR[22]), .Y(n3244) );
XOR2X4TS U5115 ( .A(n3246), .B(n4736), .Y(n3245) );
OAI22X4TS U5116 ( .A0(n3252), .A1(n4088), .B0(n4091), .B1(n3251), .Y(n3250)
);
NAND2BX4TS U5117 ( .AN(n4091), .B(n4094), .Y(n3253) );
NAND2X4TS U5118 ( .A(DMP_exp_NRM2_EW[2]), .B(n3254), .Y(n4070) );
OAI21X4TS U5119 ( .A0(n5982), .A1(n5742), .B0(n5743), .Y(n4128) );
AOI22X4TS U5120 ( .A0(n3257), .A1(n5639), .B0(n5638), .B1(
Raw_mant_NRM_SWR[42]), .Y(n3256) );
XOR2X4TS U5121 ( .A(n3258), .B(n5171), .Y(n3257) );
NAND2X4TS U5122 ( .A(n4307), .B(n2847), .Y(n4247) );
NAND2X4TS U5123 ( .A(n3345), .B(DMP_SFG[21]), .Y(n5057) );
BUFX20TS U5124 ( .A(n4189), .Y(n4295) );
NAND2X4TS U5125 ( .A(n4121), .B(n2011), .Y(n4216) );
XNOR2X4TS U5126 ( .A(intDX_EWSW[4]), .B(intDY_EWSW[4]), .Y(n5389) );
NAND2X2TS U5127 ( .A(n3273), .B(intDY_EWSW[4]), .Y(n3479) );
NOR2X4TS U5128 ( .A(n5218), .B(n5214), .Y(n5208) );
NAND2X4TS U5129 ( .A(n5224), .B(n5212), .Y(n5218) );
NAND2X4TS U5130 ( .A(n2848), .B(intDX_EWSW[19]), .Y(n3835) );
NOR2X4TS U5131 ( .A(n3331), .B(intDY_EWSW[52]), .Y(n3566) );
NAND2X2TS U5132 ( .A(n3278), .B(intDY_EWSW[57]), .Y(n3627) );
XNOR2X4TS U5133 ( .A(intDX_EWSW[48]), .B(intDY_EWSW[48]), .Y(n5382) );
NOR2X4TS U5134 ( .A(n3295), .B(intDY_EWSW[48]), .Y(n3563) );
INVX2TS U5135 ( .A(n1721), .Y(n4009) );
NOR2X8TS U5136 ( .A(n4171), .B(n4170), .Y(n5674) );
AND2X8TS U5137 ( .A(n5563), .B(n4169), .Y(n4170) );
NAND2X4TS U5138 ( .A(sub_x_5_n601), .B(DMP_SFG[41]), .Y(n5080) );
NOR2X4TS U5139 ( .A(n3468), .B(n3501), .Y(n3470) );
NOR2X4TS U5140 ( .A(n3276), .B(intDY_EWSW[12]), .Y(n3468) );
NOR2X4TS U5141 ( .A(n3483), .B(n3476), .Y(n3485) );
NAND2X2TS U5142 ( .A(n4121), .B(intDY_EWSW[36]), .Y(n3851) );
NAND2X2TS U5143 ( .A(n3809), .B(intDY_EWSW[35]), .Y(n3854) );
NAND2X2TS U5144 ( .A(n5349), .B(intDY_EWSW[50]), .Y(n4119) );
NAND2X2TS U5145 ( .A(n4307), .B(intDY_EWSW[43]), .Y(n4104) );
NAND2X2TS U5146 ( .A(n6936), .B(n2558), .Y(n5494) );
CLKINVX12TS U5147 ( .A(sub_x_5_B_17_), .Y(n6083) );
NOR3X2TS U5148 ( .A(n3953), .B(n3952), .C(n4555), .Y(n3964) );
BUFX20TS U5149 ( .A(n4189), .Y(n5348) );
XOR2X4TS U5150 ( .A(n5590), .B(n5589), .Y(n5592) );
NAND2X4TS U5151 ( .A(DMP_SFG[47]), .B(DmP_mant_SFG_SWR[49]), .Y(n4794) );
NAND3X2TS U5152 ( .A(n5448), .B(n5447), .C(n5446), .Y(n1291) );
XOR2X4TS U5153 ( .A(n5072), .B(n5071), .Y(n5073) );
NAND2X6TS U5154 ( .A(n4049), .B(n5729), .Y(n6990) );
NAND2X4TS U5155 ( .A(n4517), .B(n5727), .Y(n4049) );
BUFX20TS U5156 ( .A(n4189), .Y(n4245) );
MX2X4TS U5157 ( .A(n5737), .B(LZD_output_NRM2_EW[2]), .S0(n5736), .Y(n1214)
);
NAND4X8TS U5158 ( .A(n3871), .B(n3870), .C(n3869), .D(n3868), .Y(n1735) );
XOR2X4TS U5159 ( .A(n4163), .B(n5240), .Y(n4164) );
OA21X2TS U5160 ( .A0(n5533), .A1(n5532), .B0(n5531), .Y(n5534) );
AOI21X4TS U5161 ( .A0(n4570), .A1(n2518), .B0(n4327), .Y(n6962) );
AOI21X2TS U5162 ( .A0(n4934), .A1(n4933), .B0(n4932), .Y(n4935) );
NAND2X4TS U5163 ( .A(n5652), .B(n5673), .Y(n5657) );
NAND2X4TS U5164 ( .A(n4245), .B(intDX_EWSW[57]), .Y(n3677) );
NAND2X8TS U5165 ( .A(n5094), .B(n4154), .Y(n4861) );
NAND2X4TS U5166 ( .A(n2648), .B(intDX_EWSW[20]), .Y(n3697) );
NAND2X2TS U5167 ( .A(n4307), .B(intDX_EWSW[23]), .Y(n3691) );
NOR2X2TS U5168 ( .A(n3492), .B(n3471), .Y(n3473) );
NOR2X4TS U5169 ( .A(n3309), .B(intDY_EWSW[8]), .Y(n3471) );
AOI21X4TS U5170 ( .A0(n3498), .A1(n3497), .B0(n3496), .Y(n3508) );
BUFX20TS U5171 ( .A(n2649), .Y(n3840) );
XOR2X4TS U5172 ( .A(n4828), .B(n4827), .Y(n4829) );
NOR2X6TS U5173 ( .A(n4699), .B(n4431), .Y(n4767) );
OAI2BB1X4TS U5174 ( .A0N(n5928), .A1N(n4854), .B0(n4853), .Y(n1240) );
NOR2X8TS U5175 ( .A(DMP_SFG[36]), .B(DmP_mant_SFG_SWR[38]), .Y(n5147) );
XOR2X4TS U5176 ( .A(n5223), .B(n5222), .Y(N91) );
NOR2X4TS U5177 ( .A(n1601), .B(n1152), .Y(n6052) );
NAND2X2TS U5178 ( .A(n5054), .B(n5721), .Y(n4347) );
NOR2X4TS U5179 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n4354)
);
NOR2X4TS U5180 ( .A(n2683), .B(n1511), .Y(n6085) );
NAND2X2TS U5181 ( .A(n4307), .B(intDX_EWSW[57]), .Y(n5352) );
NOR2X8TS U5182 ( .A(n3381), .B(n3385), .Y(n4489) );
OR2X4TS U5183 ( .A(Raw_mant_NRM_SWR[47]), .B(Raw_mant_NRM_SWR[43]), .Y(n3385) );
NOR2X4TS U5184 ( .A(n6301), .B(DMP_SFG[46]), .Y(n4665) );
NAND2X6TS U5185 ( .A(DMP_SFG[46]), .B(DmP_mant_SFG_SWR[48]), .Y(n4979) );
NOR2X8TS U5186 ( .A(DMP_SFG[46]), .B(DmP_mant_SFG_SWR[48]), .Y(n4978) );
OAI2BB1X4TS U5187 ( .A0N(n5996), .A1N(n5603), .B0(n5602), .Y(n1250) );
XOR2X4TS U5188 ( .A(n4898), .B(n4897), .Y(n4899) );
NOR2X4TS U5189 ( .A(n5949), .B(n5951), .Y(n4392) );
OAI21X4TS U5190 ( .A0(add_x_6_n470), .A1(n5521), .B0(n2331), .Y(n4130) );
XOR2X4TS U5191 ( .A(n4694), .B(n4693), .Y(n4695) );
OAI21X2TS U5192 ( .A0(n5025), .A1(n4447), .B0(n4446), .Y(n4448) );
NAND2X6TS U5193 ( .A(sub_x_5_n615), .B(n1994), .Y(n5013) );
NOR2X8TS U5194 ( .A(n4855), .B(n4663), .Y(n4991) );
XNOR2X4TS U5195 ( .A(intDX_EWSW[43]), .B(intDY_EWSW[43]), .Y(n5423) );
XNOR2X4TS U5196 ( .A(intDX_EWSW[23]), .B(intDY_EWSW[23]), .Y(n5384) );
XNOR2X4TS U5197 ( .A(intDX_EWSW[15]), .B(intDY_EWSW[15]), .Y(n5392) );
NAND2X2TS U5198 ( .A(n3315), .B(intDY_EWSW[15]), .Y(n3502) );
AOI21X2TS U5199 ( .A0(n4667), .A1(n4990), .B0(n4666), .Y(n4668) );
NAND2X4TS U5200 ( .A(n4121), .B(intDY_EWSW[14]), .Y(n4194) );
XNOR2X4TS U5201 ( .A(intDX_EWSW[14]), .B(intDY_EWSW[14]), .Y(n5391) );
NAND2X2TS U5202 ( .A(n3325), .B(intDY_EWSW[14]), .Y(n3503) );
NOR2X4TS U5203 ( .A(n3325), .B(intDY_EWSW[14]), .Y(n3469) );
XNOR2X4TS U5204 ( .A(intDX_EWSW[42]), .B(intDY_EWSW[42]), .Y(n5422) );
NOR2X2TS U5205 ( .A(n3480), .B(n3475), .Y(n3477) );
NAND2X2TS U5206 ( .A(n3337), .B(intDY_EWSW[50]), .Y(n3610) );
OAI21X2TS U5207 ( .A0(n5634), .A1(n5608), .B0(n5607), .Y(n5609) );
BUFX20TS U5208 ( .A(n4286), .Y(n4189) );
XNOR2X4TS U5209 ( .A(intDX_EWSW[22]), .B(intDY_EWSW[22]), .Y(n5383) );
NAND2X2TS U5210 ( .A(n3293), .B(intDY_EWSW[22]), .Y(n3522) );
NAND2X2TS U5211 ( .A(n3307), .B(intDY_EWSW[39]), .Y(n3581) );
MX2X4TS U5212 ( .A(Data_Y[40]), .B(intDY_EWSW[40]), .S0(n5899), .Y(n1778) );
XNOR2X4TS U5213 ( .A(intDX_EWSW[40]), .B(intDY_EWSW[40]), .Y(n5424) );
NAND2X4TS U5214 ( .A(n4121), .B(n2431), .Y(n4231) );
XNOR2X4TS U5215 ( .A(intDX_EWSW[20]), .B(intDY_EWSW[20]), .Y(n5369) );
NAND2X2TS U5216 ( .A(n3285), .B(intDY_EWSW[20]), .Y(n3519) );
NAND2X4TS U5217 ( .A(n4121), .B(intDY_EWSW[8]), .Y(n4213) );
NOR2X4TS U5218 ( .A(n3472), .B(n3495), .Y(n3497) );
NAND4X4TS U5219 ( .A(n4023), .B(n3960), .C(n3961), .D(n3959), .Y(n5550) );
NAND2X4TS U5220 ( .A(n4121), .B(n2427), .Y(n4240) );
XNOR2X4TS U5221 ( .A(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n5381) );
NAND2X4TS U5222 ( .A(n3290), .B(intDY_EWSW[21]), .Y(n3518) );
MX2X4TS U5223 ( .A(Data_Y[37]), .B(intDY_EWSW[37]), .S0(n5899), .Y(n1781) );
NOR2X8TS U5224 ( .A(n3323), .B(intDY_EWSW[53]), .Y(n3617) );
NOR2X4TS U5225 ( .A(n3365), .B(DMP_SFG[43]), .Y(n4855) );
OAI21X2TS U5226 ( .A0(add_x_6_n163), .A1(n5097), .B0(n5105), .Y(n4153) );
NAND2X4TS U5227 ( .A(add_x_6_A_45_), .B(add_x_6_B_45_), .Y(n5105) );
AOI22X2TS U5228 ( .A0(n6982), .A1(n2486), .B0(DmP_mant_SFG_SWR[7]), .B1(
n5732), .Y(n5200) );
NAND4X4TS U5229 ( .A(n3957), .B(n3956), .C(n3955), .D(n3954), .Y(n5509) );
NAND2X4TS U5230 ( .A(n4389), .B(n1728), .Y(n3954) );
XOR2X4TS U5231 ( .A(n5182), .B(n5181), .Y(n5183) );
XOR2X4TS U5232 ( .A(n4851), .B(n4850), .Y(n4852) );
NAND2X2TS U5233 ( .A(n4121), .B(n1983), .Y(n4107) );
NOR2X8TS U5234 ( .A(n3270), .B(intDY_EWSW[49]), .Y(n3608) );
NOR2X4TS U5235 ( .A(n3556), .B(n3580), .Y(n3557) );
NOR2X4TS U5236 ( .A(n3300), .B(intDY_EWSW[36]), .Y(n3556) );
NAND2X4TS U5237 ( .A(n4909), .B(n4908), .Y(n4913) );
AND2X8TS U5238 ( .A(n3169), .B(n3394), .Y(n4908) );
NAND2X2TS U5239 ( .A(n3279), .B(intDY_EWSW[58]), .Y(n3631) );
NOR2X4TS U5240 ( .A(n3264), .B(intDY_EWSW[6]), .Y(n3476) );
XNOR2X4TS U5241 ( .A(intDX_EWSW[31]), .B(intDY_EWSW[31]), .Y(n5372) );
NAND2X2TS U5242 ( .A(n3326), .B(intDY_EWSW[31]), .Y(n3542) );
BUFX20TS U5243 ( .A(n4600), .Y(n5691) );
OAI21X2TS U5244 ( .A0(n4401), .A1(n4417), .B0(n4419), .Y(n4402) );
OAI21X2TS U5245 ( .A0(n4420), .A1(n4419), .B0(n4418), .Y(n4421) );
NAND2X4TS U5246 ( .A(n2478), .B(n1737), .Y(n4046) );
NAND4X8TS U5247 ( .A(n2309), .B(n3971), .C(n3970), .D(n3969), .Y(n1737) );
NOR2X6TS U5248 ( .A(sub_x_5_n607), .B(DMP_SFG[35]), .Y(n5129) );
OR2X4TS U5249 ( .A(n4000), .B(n2235), .Y(n3441) );
NAND2X4TS U5250 ( .A(n6331), .B(DMP_SFG[10]), .Y(n4531) );
OAI21X4TS U5251 ( .A0(n3597), .A1(n3596), .B0(n3595), .Y(n3598) );
NAND2X2TS U5252 ( .A(n3292), .B(intDY_EWSW[46]), .Y(n3596) );
NOR2X4TS U5253 ( .A(n3337), .B(intDY_EWSW[50]), .Y(n3564) );
NAND2X2TS U5254 ( .A(n3283), .B(intDY_EWSW[54]), .Y(n3619) );
XNOR2X4TS U5255 ( .A(intDX_EWSW[29]), .B(intDY_EWSW[29]), .Y(n5370) );
NOR2X8TS U5256 ( .A(n3266), .B(intDY_EWSW[29]), .Y(n3541) );
INVX4TS U5257 ( .A(n4786), .Y(n4360) );
NAND2X6TS U5258 ( .A(n4058), .B(n5729), .Y(n6992) );
NOR2X8TS U5259 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n5062) );
OAI21X4TS U5260 ( .A0(n3629), .A1(n3628), .B0(n3627), .Y(n3635) );
OAI21X2TS U5261 ( .A0(n3535), .A1(n3534), .B0(n3533), .Y(n3536) );
OAI21X4TS U5262 ( .A0(add_x_6_n185), .A1(add_x_6_n193), .B0(n5084), .Y(n5100) );
NAND2X4TS U5263 ( .A(add_x_6_A_43_), .B(add_x_6_B_43_), .Y(n5084) );
OR2X4TS U5264 ( .A(n6397), .B(n2223), .Y(n3432) );
NAND2X2TS U5265 ( .A(n2813), .B(intDY_EWSW[25]), .Y(n4304) );
NAND2X4TS U5266 ( .A(n3274), .B(intDY_EWSW[25]), .Y(n3530) );
NOR2X8TS U5267 ( .A(n3274), .B(intDY_EWSW[25]), .Y(n3532) );
NOR2X4TS U5268 ( .A(n3510), .B(n3541), .Y(n3511) );
NOR2X4TS U5269 ( .A(n3280), .B(intDY_EWSW[28]), .Y(n3510) );
NOR2X8TS U5270 ( .A(n4658), .B(DMP_SFG[40]), .Y(n5162) );
NOR2X8TS U5271 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[11]), .Y(
n3391) );
NAND4X8TS U5272 ( .A(n3867), .B(n3866), .C(n3865), .D(n3864), .Y(n1739) );
AOI2BB2X4TS U5273 ( .B0(n6537), .B1(n2265), .A0N(n5660), .A1N(n2225), .Y(
n3867) );
NAND2X4TS U5274 ( .A(n2017), .B(n6459), .Y(n3866) );
NAND2X4TS U5275 ( .A(n2841), .B(n6491), .Y(n3935) );
NOR2X8TS U5276 ( .A(DMP_SFG[38]), .B(DmP_mant_SFG_SWR[40]), .Y(n5113) );
NOR2X8TS U5277 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[33]), .Y(
n4494) );
NOR2X4TS U5278 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .Y(n4350)
);
INVX12TS U5279 ( .A(n5729), .Y(n5551) );
NOR2X4TS U5280 ( .A(n3275), .B(intDY_EWSW[26]), .Y(n3513) );
NAND4X6TS U5281 ( .A(n4345), .B(n4344), .C(n4343), .D(n4342), .Y(n1714) );
NAND2X4TS U5282 ( .A(n3023), .B(intDY_EWSW[30]), .Y(n3778) );
XNOR2X4TS U5283 ( .A(intDX_EWSW[30]), .B(intDY_EWSW[30]), .Y(n5371) );
NAND2X2TS U5284 ( .A(n3324), .B(intDY_EWSW[30]), .Y(n3543) );
OAI2BB1X2TS U5285 ( .A0N(n4366), .A1N(n6194), .B0(n4904), .Y(n4367) );
NOR2X8TS U5286 ( .A(n6331), .B(DMP_SFG[10]), .Y(n4530) );
NOR2X2TS U5287 ( .A(n3512), .B(n3532), .Y(n3514) );
NOR2X8TS U5288 ( .A(n4389), .B(bit_shift_SHT2), .Y(n4171) );
BUFX20TS U5289 ( .A(n3454), .Y(n4389) );
NAND2X4TS U5290 ( .A(n3511), .B(n3546), .Y(n3549) );
NOR2X4TS U5291 ( .A(n3364), .B(DMP_SFG[7]), .Y(n5475) );
OAI21X2TS U5292 ( .A0(n4955), .A1(n5114), .B0(n4956), .Y(n4150) );
NAND2X4TS U5293 ( .A(DMP_SFG[38]), .B(DmP_mant_SFG_SWR[40]), .Y(n5114) );
AOI21X4TS U5294 ( .A0(n3639), .A1(n3638), .B0(n3637), .Y(n3640) );
NAND2X2TS U5295 ( .A(n5505), .B(n1739), .Y(n3914) );
NAND4X4TS U5296 ( .A(n3889), .B(n3888), .C(n3887), .D(n3886), .Y(n4558) );
NOR2X4TS U5297 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[23]), .Y(
n4485) );
NOR2X8TS U5298 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n4467) );
NOR2X4TS U5299 ( .A(add_x_6_A_42_), .B(add_x_6_B_42_), .Y(n5169) );
NAND4X6TS U5300 ( .A(n5196), .B(n5195), .C(n5194), .D(n5193), .Y(n6981) );
NOR2X4TS U5301 ( .A(n5188), .B(n5187), .Y(n5196) );
NOR2X2TS U5302 ( .A(Raw_mant_NRM_SWR[48]), .B(n1912), .Y(n4506) );
AOI21X4TS U5303 ( .A0(add_x_6_n254), .A1(add_x_6_n241), .B0(n4149), .Y(n5146) );
NOR2X4TS U5304 ( .A(n4148), .B(n4978), .Y(n4157) );
NOR2X4TS U5305 ( .A(sub_x_5_n615), .B(n1994), .Y(n4836) );
NOR2X8TS U5306 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n4366)
);
NOR2X6TS U5307 ( .A(n3353), .B(DMP_SFG[19]), .Y(n4730) );
NAND2X6TS U5308 ( .A(n3353), .B(DMP_SFG[19]), .Y(n4728) );
NOR2X8TS U5309 ( .A(n4730), .B(n4426), .Y(n4812) );
OAI21X2TS U5310 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n6091), .B0(n6117), .Y(n3370) );
NAND2X4TS U5311 ( .A(n4372), .B(n1739), .Y(n4374) );
NAND2X6TS U5312 ( .A(DMP_SFG[12]), .B(DmP_mant_SFG_SWR[14]), .Y(n4630) );
NAND4X8TS U5313 ( .A(n3862), .B(n3861), .C(n3860), .D(n3859), .Y(n1743) );
NAND2X4TS U5314 ( .A(n3364), .B(DMP_SFG[7]), .Y(n5474) );
INVX16TS U5315 ( .A(n3919), .Y(n5727) );
OR2X6TS U5316 ( .A(shift_value_SHT2_EWR[4]), .B(n6093), .Y(n3962) );
AOI21X4TS U5317 ( .A0(n4141), .A1(n4842), .B0(n4140), .Y(n5023) );
NOR2X4TS U5318 ( .A(n6299), .B(DMP_SFG[13]), .Y(n4417) );
NOR2X4TS U5319 ( .A(n4969), .B(n4971), .Y(n4974) );
NOR2X8TS U5320 ( .A(add_x_6_n477), .B(add_x_6_n470), .Y(n4131) );
OR2X4TS U5321 ( .A(n2273), .B(n2247), .Y(n3464) );
NAND2X4TS U5322 ( .A(n2017), .B(n6453), .Y(n3901) );
XOR2X4TS U5323 ( .A(n5234), .B(n5233), .Y(N89) );
NOR2X4TS U5324 ( .A(n6336), .B(DMP_SFG[11]), .Y(n4540) );
NOR2X4TS U5325 ( .A(sub_x_5_n611), .B(sub_x_5_A_33_), .Y(n4754) );
NAND2X6TS U5326 ( .A(n5122), .B(add_x_6_n241), .Y(n5144) );
NAND4X4TS U5327 ( .A(n3983), .B(n3982), .C(n3981), .D(n3980), .Y(n1717) );
MXI2X4TS U5328 ( .A(n6099), .B(n6316), .S0(n2540), .Y(n1595) );
BUFX16TS U5329 ( .A(n6389), .Y(n4340) );
AOI2BB2X2TS U5330 ( .B0(n2827), .B1(n1706), .A0N(n5712), .A1N(n4387), .Y(
n4346) );
NAND2X4TS U5331 ( .A(n2426), .B(DMP_SFG[0]), .Y(n5919) );
OAI21X2TS U5332 ( .A0(n4476), .A1(n4567), .B0(n4613), .Y(n4477) );
MX2X4TS U5333 ( .A(n4484), .B(LZD_output_NRM2_EW[3]), .S0(n5853), .Y(n6121)
);
NAND4X6TS U5334 ( .A(n3930), .B(n3929), .C(n3928), .D(n3927), .Y(n1718) );
AOI21X4TS U5335 ( .A0(n4570), .A1(n2381), .B0(n4569), .Y(n6918) );
NOR2X4TS U5336 ( .A(n4039), .B(n4055), .Y(n3458) );
CLKINVX6TS U5337 ( .A(n1712), .Y(n4055) );
OAI2BB1X2TS U5338 ( .A0N(n5630), .A1N(n4539), .B0(n4538), .Y(n1257) );
NAND2X6TS U5339 ( .A(DMP_SFG[26]), .B(DmP_mant_SFG_SWR[28]), .Y(n4839) );
NAND2X4TS U5340 ( .A(n4315), .B(n1735), .Y(n4174) );
MXI2X4TS U5341 ( .A(n6101), .B(n6322), .S0(n2540), .Y(n1601) );
NOR2X2TS U5342 ( .A(add_x_6_A_18_), .B(add_x_6_B_18_), .Y(n5598) );
NOR2X8TS U5343 ( .A(n4171), .B(n3943), .Y(n5054) );
MXI2X4TS U5344 ( .A(n6162), .B(n6329), .S0(n5883), .Y(n1514) );
NAND4X8TS U5345 ( .A(n3431), .B(n3430), .C(n3429), .D(n3428), .Y(n1732) );
OAI2BB1X2TS U5346 ( .A0N(n5996), .A1N(n5971), .B0(n5970), .Y(n1262) );
MXI2X4TS U5347 ( .A(n6152), .B(n6328), .S0(n2687), .Y(n1484) );
NOR2X6TS U5348 ( .A(n3320), .B(intDY_EWSW[7]), .Y(n3483) );
NOR3X2TS U5349 ( .A(n4011), .B(n4010), .C(n4555), .Y(n4014) );
NOR2X8TS U5350 ( .A(add_x_6_n406), .B(add_x_6_n401), .Y(n4135) );
OAI21X2TS U5351 ( .A0(n4568), .A1(n4564), .B0(n4563), .Y(n4327) );
MXI2X4TS U5352 ( .A(n6903), .B(n6333), .S0(n2514), .Y(n1151) );
AND2X2TS U5353 ( .A(n5823), .B(Raw_mant_NRM_SWR[24]), .Y(n3301) );
OA21X4TS U5354 ( .A0(n5103), .A1(n5006), .B0(n5005), .Y(n3314) );
CLKBUFX3TS U5355 ( .A(n2509), .Y(n6768) );
CLKBUFX3TS U5356 ( .A(n5252), .Y(n5250) );
NAND2X2TS U5357 ( .A(n3845), .B(intDY_EWSW[52]), .Y(n3653) );
NAND2X2TS U5358 ( .A(n2550), .B(intDX_EWSW[52]), .Y(n3671) );
NAND2X1TS U5359 ( .A(n5799), .B(Raw_mant_NRM_SWR[42]), .Y(n5464) );
NAND2X2TS U5360 ( .A(n5814), .B(Raw_mant_NRM_SWR[10]), .Y(n5300) );
NAND2X1TS U5361 ( .A(n5736), .B(DmP_mant_SHT1_SW[0]), .Y(n5296) );
NAND2X1TS U5362 ( .A(n5348), .B(intDX_EWSW[37]), .Y(n4294) );
NAND2X1TS U5363 ( .A(n5348), .B(intDX_EWSW[32]), .Y(n4220) );
NAND2X1TS U5364 ( .A(n5348), .B(intDX_EWSW[12]), .Y(n4238) );
NAND2X1TS U5365 ( .A(n4189), .B(intDX_EWSW[8]), .Y(n4214) );
NAND2X1TS U5366 ( .A(n5348), .B(intDX_EWSW[3]), .Y(n4210) );
CLKBUFX3TS U5367 ( .A(n6386), .Y(n5244) );
CLKBUFX2TS U5368 ( .A(n2543), .Y(n6357) );
BUFX3TS U5369 ( .A(n6360), .Y(n6725) );
BUFX3TS U5370 ( .A(n6375), .Y(n6377) );
INVX16TS U5371 ( .A(n5853), .Y(n5779) );
NOR2X8TS U5372 ( .A(n5779), .B(n5890), .Y(n3366) );
INVX16TS U5373 ( .A(n3366), .Y(n6720) );
INVX12TS U5374 ( .A(n6720), .Y(n6716) );
NAND3X1TS U5375 ( .A(n3370), .B(n5690), .C(n6110), .Y(n3372) );
NOR2X4TS U5376 ( .A(n3372), .B(n4364), .Y(n3373) );
NOR2X4TS U5377 ( .A(Raw_mant_NRM_SWR[34]), .B(Raw_mant_NRM_SWR[35]), .Y(
n3378) );
INVX2TS U5378 ( .A(n3378), .Y(n3375) );
NOR2X2TS U5379 ( .A(Raw_mant_NRM_SWR[42]), .B(Raw_mant_NRM_SWR[44]), .Y(
n3380) );
NAND2X4TS U5380 ( .A(n4504), .B(n3380), .Y(n3381) );
NOR2X1TS U5381 ( .A(Raw_mant_NRM_SWR[40]), .B(n6129), .Y(n3382) );
NOR3X1TS U5382 ( .A(n3400), .B(n3386), .C(n3385), .Y(n3387) );
INVX2TS U5383 ( .A(n5690), .Y(n3388) );
NOR2X4TS U5384 ( .A(n4364), .B(n3388), .Y(n3389) );
NAND2X4TS U5385 ( .A(n5690), .B(n6114), .Y(n4573) );
NOR2X4TS U5386 ( .A(n4573), .B(Raw_mant_NRM_SWR[13]), .Y(n4599) );
NOR2X1TS U5387 ( .A(n4359), .B(n6193), .Y(n3392) );
INVX2TS U5388 ( .A(n3395), .Y(n3394) );
NOR2X4TS U5389 ( .A(n3395), .B(Raw_mant_NRM_SWR[30]), .Y(n4576) );
INVX2TS U5390 ( .A(n4576), .Y(n3396) );
NAND2X1TS U5391 ( .A(n6115), .B(Raw_mant_NRM_SWR[43]), .Y(n3398) );
NAND3X1TS U5392 ( .A(n5685), .B(n6115), .C(n3400), .Y(n3401) );
NOR2X2TS U5393 ( .A(n6716), .B(n5779), .Y(n5699) );
OR2X2TS U5400 ( .A(n2273), .B(n2218), .Y(n3413) );
OR2X2TS U5401 ( .A(n2273), .B(n2239), .Y(n3437) );
OR2X2TS U5402 ( .A(n6397), .B(n2220), .Y(n3436) );
NOR2X1TS U5403 ( .A(n3455), .B(n3456), .Y(n3457) );
NAND2X6TS U5404 ( .A(n3460), .B(bit_shift_SHT2), .Y(n5729) );
NAND2X1TS U5405 ( .A(n5722), .B(n2513), .Y(n3467) );
NAND2X8TS U5406 ( .A(n6714), .B(Shift_reg_FLAGS_7[3]), .Y(n4015) );
NAND2X2TS U5407 ( .A(n3560), .B(n3578), .Y(n3561) );
NAND2X2TS U5408 ( .A(n5348), .B(intDY_EWSW[55]), .Y(n3650) );
NAND2X1TS U5409 ( .A(n5350), .B(DMP_EXP_EWSW[55]), .Y(n3648) );
NAND2X2TS U5410 ( .A(n3828), .B(intDX_EWSW[52]), .Y(n3652) );
NAND2X1TS U5411 ( .A(n5350), .B(DMP_EXP_EWSW[52]), .Y(n3651) );
NAND2X2TS U5412 ( .A(n4295), .B(intDY_EWSW[56]), .Y(n3656) );
NAND2X1TS U5413 ( .A(n5350), .B(DMP_EXP_EWSW[56]), .Y(n3654) );
NAND3X2TS U5414 ( .A(n3656), .B(n3655), .C(n3654), .Y(n1619) );
NAND2X2TS U5415 ( .A(n2993), .B(n1915), .Y(n3659) );
NAND2X2TS U5416 ( .A(n4121), .B(intDX_EWSW[54]), .Y(n3658) );
NAND2X1TS U5417 ( .A(n5350), .B(DMP_EXP_EWSW[54]), .Y(n3657) );
NAND2X2TS U5418 ( .A(n4245), .B(intDY_EWSW[53]), .Y(n3662) );
NAND2X1TS U5419 ( .A(n5350), .B(DMP_EXP_EWSW[53]), .Y(n3660) );
NAND3X2TS U5420 ( .A(n3662), .B(n3661), .C(n3660), .Y(n1622) );
NAND2X2TS U5421 ( .A(n4306), .B(intDX_EWSW[53]), .Y(n3665) );
NAND2X2TS U5422 ( .A(n5349), .B(intDY_EWSW[53]), .Y(n3664) );
NAND2X1TS U5423 ( .A(n5445), .B(DmP_EXP_EWSW[53]), .Y(n3663) );
NAND3X2TS U5424 ( .A(n3665), .B(n3664), .C(n3663), .Y(n1293) );
NAND2X2TS U5425 ( .A(n4245), .B(intDX_EWSW[54]), .Y(n3668) );
NAND2X2TS U5426 ( .A(n2813), .B(n1915), .Y(n3667) );
NAND2X1TS U5427 ( .A(n5445), .B(DmP_EXP_EWSW[54]), .Y(n3666) );
NAND3X2TS U5428 ( .A(n3667), .B(n3668), .C(n3666), .Y(n1292) );
NAND2X2TS U5429 ( .A(n3809), .B(intDY_EWSW[52]), .Y(n3670) );
NAND2X1TS U5430 ( .A(n5445), .B(DmP_EXP_EWSW[52]), .Y(n3669) );
NAND2X2TS U5431 ( .A(n2550), .B(intDX_EWSW[56]), .Y(n3674) );
NAND3X2TS U5432 ( .A(n3673), .B(n3674), .C(n3672), .Y(n1290) );
NAND2X1TS U5433 ( .A(n5278), .B(DMP_EXP_EWSW[60]), .Y(n3678) );
NAND3X2TS U5434 ( .A(n3679), .B(n3680), .C(n3678), .Y(n1615) );
NAND2X2TS U5435 ( .A(n2012), .B(intDY_EWSW[58]), .Y(n3683) );
NAND2X1TS U5436 ( .A(n4121), .B(intDX_EWSW[58]), .Y(n3682) );
NAND2X1TS U5437 ( .A(n5278), .B(DMP_EXP_EWSW[58]), .Y(n3681) );
NAND3X2TS U5438 ( .A(n3683), .B(n3682), .C(n3681), .Y(n1617) );
NAND2X2TS U5439 ( .A(n3845), .B(intDY_EWSW[8]), .Y(n3689) );
NAND2X1TS U5440 ( .A(n4211), .B(DMP_EXP_EWSW[8]), .Y(n3687) );
NAND3X2TS U5441 ( .A(n3688), .B(n3689), .C(n3687), .Y(n1667) );
NAND2X2TS U5442 ( .A(n4306), .B(intDY_EWSW[23]), .Y(n3692) );
NAND2X1TS U5443 ( .A(n3732), .B(DMP_EXP_EWSW[23]), .Y(n3690) );
NAND3X2TS U5444 ( .A(n3692), .B(n3691), .C(n3690), .Y(n1652) );
NAND2X1TS U5445 ( .A(n4211), .B(DMP_EXP_EWSW[6]), .Y(n3693) );
NAND2X1TS U5446 ( .A(n3732), .B(DMP_EXP_EWSW[20]), .Y(n3696) );
NAND3X2TS U5447 ( .A(n3703), .B(n3704), .C(n3702), .Y(n1674) );
NAND2X2TS U5448 ( .A(n2993), .B(intDY_EWSW[5]), .Y(n3707) );
NAND2X1TS U5449 ( .A(n4211), .B(DMP_EXP_EWSW[5]), .Y(n3705) );
NAND3X2TS U5450 ( .A(n3707), .B(n3706), .C(n3705), .Y(n1670) );
NAND2X1TS U5451 ( .A(n4211), .B(n2142), .Y(n3717) );
NAND2X2TS U5452 ( .A(n3023), .B(intDY_EWSW[22]), .Y(n3722) );
NAND2X1TS U5453 ( .A(n3732), .B(DMP_EXP_EWSW[22]), .Y(n3720) );
NAND3X2TS U5454 ( .A(n3722), .B(n3721), .C(n3720), .Y(n1653) );
NAND2X2TS U5455 ( .A(n4295), .B(intDY_EWSW[21]), .Y(n3725) );
NAND2X1TS U5456 ( .A(n3732), .B(DMP_EXP_EWSW[21]), .Y(n3723) );
NAND3X2TS U5457 ( .A(n3725), .B(n3724), .C(n3723), .Y(n1654) );
NAND3X2TS U5458 ( .A(n3727), .B(n3728), .C(n3726), .Y(n1650) );
NAND2X1TS U5459 ( .A(n4211), .B(DMP_EXP_EWSW[3]), .Y(n3729) );
NAND2X1TS U5460 ( .A(n4121), .B(intDX_EWSW[27]), .Y(n3734) );
NAND2X1TS U5461 ( .A(n3732), .B(n2465), .Y(n3733) );
NAND3X2TS U5462 ( .A(n3734), .B(n3735), .C(n3733), .Y(n1648) );
NAND2X2TS U5463 ( .A(n4245), .B(intDY_EWSW[59]), .Y(n3738) );
NAND2X1TS U5464 ( .A(n5350), .B(DMP_EXP_EWSW[59]), .Y(n3736) );
NAND3X2TS U5465 ( .A(n3738), .B(n3737), .C(n3736), .Y(n1616) );
NAND2X1TS U5466 ( .A(n5350), .B(DMP_EXP_EWSW[51]), .Y(n3739) );
NAND2X1TS U5467 ( .A(n3840), .B(intDX_EWSW[40]), .Y(n3743) );
NAND2X1TS U5468 ( .A(n3829), .B(DMP_EXP_EWSW[40]), .Y(n3742) );
NAND3X2TS U5469 ( .A(n3743), .B(n3744), .C(n3742), .Y(n1635) );
NAND2X2TS U5470 ( .A(n2550), .B(intDY_EWSW[12]), .Y(n3747) );
NAND2X1TS U5471 ( .A(n3833), .B(DMP_EXP_EWSW[12]), .Y(n3745) );
NAND3X2TS U5472 ( .A(n3747), .B(n3746), .C(n3745), .Y(n1663) );
NAND2X2TS U5473 ( .A(n2403), .B(intDY_EWSW[28]), .Y(n3750) );
NAND2X1TS U5474 ( .A(n3841), .B(DMP_EXP_EWSW[28]), .Y(n3748) );
NAND3X2TS U5475 ( .A(n3750), .B(n3749), .C(n3748), .Y(n1647) );
NAND2X2TS U5476 ( .A(n3023), .B(intDY_EWSW[16]), .Y(n3753) );
NAND2X1TS U5477 ( .A(n3833), .B(DMP_EXP_EWSW[16]), .Y(n3751) );
NAND3X2TS U5478 ( .A(n3752), .B(n3753), .C(n3751), .Y(n1659) );
NAND2X1TS U5479 ( .A(n3833), .B(DMP_EXP_EWSW[15]), .Y(n3754) );
NAND2X1TS U5480 ( .A(n3829), .B(DMP_EXP_EWSW[45]), .Y(n3757) );
NAND2X2TS U5481 ( .A(n3775), .B(intDY_EWSW[48]), .Y(n3762) );
NAND2X1TS U5482 ( .A(n5350), .B(DMP_EXP_EWSW[48]), .Y(n3760) );
NAND3X2TS U5483 ( .A(n3761), .B(n3762), .C(n3760), .Y(n1627) );
NAND2X2TS U5484 ( .A(n2993), .B(intDY_EWSW[14]), .Y(n3765) );
NAND2X1TS U5485 ( .A(n3833), .B(DMP_EXP_EWSW[14]), .Y(n3763) );
NAND3X2TS U5486 ( .A(n3764), .B(n3765), .C(n3763), .Y(n1661) );
NAND2X2TS U5487 ( .A(n2821), .B(n2130), .Y(n3768) );
NAND2X1TS U5488 ( .A(n3840), .B(intDX_EWSW[34]), .Y(n3767) );
NAND2X1TS U5489 ( .A(n3841), .B(DMP_EXP_EWSW[34]), .Y(n3766) );
NAND3X2TS U5490 ( .A(n3767), .B(n3768), .C(n3766), .Y(n1641) );
NAND2X2TS U5491 ( .A(n2550), .B(intDY_EWSW[17]), .Y(n3771) );
NAND2X1TS U5492 ( .A(n3833), .B(DMP_EXP_EWSW[17]), .Y(n3769) );
NAND3X2TS U5493 ( .A(n3771), .B(n3770), .C(n3769), .Y(n1658) );
NAND2X2TS U5494 ( .A(n2550), .B(intDY_EWSW[10]), .Y(n3774) );
NAND2X1TS U5495 ( .A(n3833), .B(n2144), .Y(n3772) );
NAND2X1TS U5496 ( .A(n3841), .B(DMP_EXP_EWSW[30]), .Y(n3776) );
NAND2X2TS U5497 ( .A(n3023), .B(intDY_EWSW[50]), .Y(n3784) );
NAND2X1TS U5498 ( .A(n5350), .B(DMP_EXP_EWSW[50]), .Y(n3782) );
NAND3X2TS U5499 ( .A(n3783), .B(n3784), .C(n3782), .Y(n1625) );
NAND2X1TS U5500 ( .A(n3829), .B(DMP_EXP_EWSW[46]), .Y(n3785) );
NAND2X2TS U5501 ( .A(n2821), .B(n2149), .Y(n3790) );
NAND2X1TS U5502 ( .A(n3829), .B(DMP_EXP_EWSW[44]), .Y(n3788) );
NAND3X2TS U5503 ( .A(n3789), .B(n3790), .C(n3788), .Y(n1631) );
NAND2X1TS U5504 ( .A(n1920), .B(intDX_EWSW[41]), .Y(n3792) );
NAND2X1TS U5505 ( .A(n3829), .B(n2141), .Y(n3791) );
NAND3X2TS U5506 ( .A(n3792), .B(n3793), .C(n3791), .Y(n1634) );
NAND2X2TS U5507 ( .A(n3023), .B(n2427), .Y(n3796) );
NAND2X1TS U5508 ( .A(n3833), .B(DMP_EXP_EWSW[13]), .Y(n3794) );
NAND3X2TS U5509 ( .A(n3795), .B(n3796), .C(n3794), .Y(n1662) );
NAND2X1TS U5510 ( .A(n3846), .B(intDX_EWSW[9]), .Y(n3798) );
NAND2X1TS U5511 ( .A(n3833), .B(n2143), .Y(n3797) );
NAND3X2TS U5512 ( .A(n3798), .B(n3799), .C(n3797), .Y(n1666) );
NAND2X1TS U5513 ( .A(n3840), .B(intDX_EWSW[38]), .Y(n3801) );
NAND2X1TS U5514 ( .A(n3829), .B(DMP_EXP_EWSW[38]), .Y(n3800) );
NAND3X2TS U5515 ( .A(n3801), .B(n3802), .C(n3800), .Y(n1637) );
NAND2X2TS U5516 ( .A(n3775), .B(intDY_EWSW[42]), .Y(n3805) );
NAND2X1TS U5517 ( .A(n3840), .B(intDX_EWSW[42]), .Y(n3804) );
NAND2X1TS U5518 ( .A(n3829), .B(DMP_EXP_EWSW[42]), .Y(n3803) );
NAND3X2TS U5519 ( .A(n3804), .B(n3805), .C(n3803), .Y(n1633) );
NAND2X1TS U5520 ( .A(n2819), .B(intDX_EWSW[11]), .Y(n3807) );
NAND2X1TS U5521 ( .A(n3833), .B(n2145), .Y(n3806) );
NAND2X2TS U5522 ( .A(n3775), .B(intDY_EWSW[31]), .Y(n3812) );
NAND3X2TS U5523 ( .A(n3811), .B(n3812), .C(n3810), .Y(n1644) );
NAND2X2TS U5524 ( .A(n3775), .B(n1987), .Y(n3815) );
NAND2X1TS U5525 ( .A(n3829), .B(DMP_EXP_EWSW[47]), .Y(n3813) );
NAND3X2TS U5526 ( .A(n3814), .B(n3815), .C(n3813), .Y(n1628) );
NAND2X2TS U5527 ( .A(n3775), .B(intDY_EWSW[43]), .Y(n3818) );
NAND2X1TS U5528 ( .A(n3829), .B(n2146), .Y(n3816) );
NAND3X2TS U5529 ( .A(n3817), .B(n3818), .C(n3816), .Y(n1632) );
NAND2X1TS U5530 ( .A(n3841), .B(DMP_EXP_EWSW[39]), .Y(n3819) );
NAND2X1TS U5531 ( .A(n3841), .B(DMP_EXP_EWSW[37]), .Y(n3822) );
NAND2X1TS U5532 ( .A(n3840), .B(intDX_EWSW[35]), .Y(n3826) );
NAND2X1TS U5533 ( .A(n3841), .B(DMP_EXP_EWSW[35]), .Y(n3825) );
NAND3X2TS U5534 ( .A(n3826), .B(n3827), .C(n3825), .Y(n1640) );
NAND2X1TS U5535 ( .A(n3829), .B(DMP_EXP_EWSW[49]), .Y(n3830) );
NAND2X1TS U5536 ( .A(n3833), .B(DMP_EXP_EWSW[19]), .Y(n3834) );
NAND2X2TS U5537 ( .A(n2821), .B(intDY_EWSW[36]), .Y(n3839) );
NAND2X1TS U5538 ( .A(n3841), .B(DMP_EXP_EWSW[36]), .Y(n3837) );
NAND3X2TS U5539 ( .A(n3839), .B(n3838), .C(n3837), .Y(n1639) );
NAND2X2TS U5540 ( .A(n3023), .B(intDY_EWSW[33]), .Y(n3844) );
NAND2X1TS U5541 ( .A(n3840), .B(intDX_EWSW[33]), .Y(n3843) );
NAND2X1TS U5542 ( .A(n3841), .B(DMP_EXP_EWSW[33]), .Y(n3842) );
NAND3X2TS U5543 ( .A(n3843), .B(n3844), .C(n3842), .Y(n1642) );
NAND2X1TS U5544 ( .A(n4211), .B(DMP_EXP_EWSW[7]), .Y(n3847) );
NAND2X2TS U5545 ( .A(n3845), .B(intDX_EWSW[36]), .Y(n3852) );
NAND2X1TS U5546 ( .A(n4296), .B(DmP_EXP_EWSW[36]), .Y(n3850) );
NAND3X2TS U5547 ( .A(n3851), .B(n3852), .C(n3850), .Y(n1326) );
NAND2X2TS U5548 ( .A(n2550), .B(intDX_EWSW[35]), .Y(n3855) );
NAND3X2TS U5549 ( .A(n3854), .B(n3855), .C(n3853), .Y(n1328) );
NAND2X2TS U5550 ( .A(n2505), .B(intDX_EWSW[41]), .Y(n3858) );
NAND2X1TS U5551 ( .A(n5445), .B(DmP_EXP_EWSW[41]), .Y(n3856) );
NAND3X2TS U5552 ( .A(n3858), .B(n3857), .C(n3856), .Y(n1316) );
OAI21X4TS U5553 ( .A0(n2235), .A1(n3996), .B0(n3863), .Y(n1751) );
MXI2X2TS U5554 ( .A(n6150), .B(n6323), .S0(n5888), .Y(n1478) );
NAND2X2TS U5555 ( .A(n5653), .B(n2523), .Y(n5540) );
OAI21X1TS U5556 ( .A0(n5540), .A1(n5495), .B0(n5538), .Y(n3910) );
NAND2X1TS U5557 ( .A(n2475), .B(n1727), .Y(n3912) );
NOR2X4TS U5558 ( .A(n1478), .B(n1111), .Y(n6051) );
MXI2X4TS U5559 ( .A(n6161), .B(n6248), .S0(n5883), .Y(n1511) );
OR2X2TS U5560 ( .A(n2273), .B(n2211), .Y(n3928) );
INVX2TS U5561 ( .A(n5876), .Y(n3951) );
INVX4TS U5562 ( .A(n3962), .Y(n5544) );
NAND2X1TS U5563 ( .A(n2713), .B(n1746), .Y(n3967) );
NAND2X2TS U5564 ( .A(n6408), .B(n6506), .Y(n3974) );
NAND2X2TS U5565 ( .A(n6408), .B(n6515), .Y(n3994) );
BUFX12TS U5566 ( .A(n1981), .Y(n5884) );
MXI2X4TS U5567 ( .A(n6184), .B(n6256), .S0(n5884), .Y(n1580) );
MXI2X4TS U5568 ( .A(n6102), .B(n6250), .S0(n2540), .Y(n1604) );
OR2X2TS U5569 ( .A(n2273), .B(n2197), .Y(n4030) );
INVX2TS U5570 ( .A(n1705), .Y(n4038) );
NAND2X2TS U5571 ( .A(n4517), .B(n5721), .Y(n4048) );
OR2X2TS U5572 ( .A(n2273), .B(n2234), .Y(n4052) );
NAND4X2TS U5573 ( .A(n4054), .B(n4053), .C(n4052), .D(n4051), .Y(n1700) );
CLKXOR2X4TS U5574 ( .A(n2306), .B(n4066), .Y(exp_rslt_NRM2_EW1[1]) );
XNOR2X4TS U5575 ( .A(n4075), .B(n4074), .Y(exp_rslt_NRM2_EW1[0]) );
INVX2TS U5576 ( .A(n4092), .Y(n4090) );
NAND3X2TS U5577 ( .A(n4101), .B(n4102), .C(n4100), .Y(n1304) );
NAND2X2TS U5578 ( .A(n3023), .B(intDX_EWSW[49]), .Y(n4108) );
NAND3X2TS U5579 ( .A(n4107), .B(n4108), .C(n4106), .Y(n1300) );
NAND2X1TS U5580 ( .A(n4296), .B(DmP_EXP_EWSW[45]), .Y(n4109) );
NAND2X2TS U5581 ( .A(n4189), .B(intDX_EWSW[46]), .Y(n4114) );
NAND2X2TS U5582 ( .A(n2994), .B(intDX_EWSW[44]), .Y(n4117) );
NAND2X2TS U5583 ( .A(n3023), .B(intDX_EWSW[50]), .Y(n4120) );
NAND3X2TS U5584 ( .A(n4119), .B(n4120), .C(n4118), .Y(n1298) );
NAND2X2TS U5585 ( .A(n4245), .B(intDX_EWSW[51]), .Y(n4127) );
NAND2X1TS U5586 ( .A(n5878), .B(DmP_EXP_EWSW[51]), .Y(n4125) );
NAND3X2TS U5587 ( .A(n4127), .B(n4126), .C(n4125), .Y(n1296) );
NOR2X6TS U5588 ( .A(n2444), .B(DmP_mant_SFG_SWR[17]), .Y(n4469) );
OAI21X4TS U5589 ( .A0(n4624), .A1(n4630), .B0(n4625), .Y(n4465) );
AOI21X4TS U5590 ( .A0(n4465), .A1(n4133), .B0(n4132), .Y(n4134) );
NOR2X4TS U5591 ( .A(n5598), .B(add_x_6_n417), .Y(n4721) );
NOR2X4TS U5592 ( .A(n5062), .B(n4886), .Y(n4137) );
NOR2X4TS U5593 ( .A(DMP_SFG[31]), .B(DmP_mant_SFG_SWR[33]), .Y(n4761) );
AOI21X4TS U5594 ( .A0(n4892), .A1(n4137), .B0(n4136), .Y(n4138) );
NOR2X2TS U5595 ( .A(add_x_6_A_34_), .B(add_x_6_B_34_), .Y(n4948) );
NOR2X8TS U5596 ( .A(n5147), .B(n5140), .Y(n4961) );
NOR2X4TS U5597 ( .A(n5113), .B(n4955), .Y(n4151) );
NOR2X4TS U5598 ( .A(DMP_SFG[45]), .B(DmP_mant_SFG_SWR[47]), .Y(n4995) );
INVX2TS U5599 ( .A(n4983), .Y(n4148) );
NOR2X1TS U5600 ( .A(n5095), .B(n4159), .Y(n4161) );
AOI21X4TS U5601 ( .A0(n5100), .A1(n4154), .B0(n4153), .Y(n4860) );
OAI21X4TS U5602 ( .A0(n4995), .A1(n5001), .B0(n4996), .Y(n4982) );
INVX2TS U5603 ( .A(n4982), .Y(n4155) );
OAI21X1TS U5604 ( .A0(n4155), .A1(n4978), .B0(n4979), .Y(n4156) );
OAI21X1TS U5605 ( .A0(n5103), .A1(n4159), .B0(n4158), .Y(n4160) );
NOR2X8TS U5606 ( .A(DMP_SFG[47]), .B(DmP_mant_SFG_SWR[49]), .Y(n4795) );
INVX2TS U5607 ( .A(n4795), .Y(n4162) );
AOI2BB2X2TS U5608 ( .B0(n4164), .B1(n5639), .A0N(n5786), .A1N(n2459), .Y(
n6780) );
NAND2X1TS U5609 ( .A(n2017), .B(n6503), .Y(n4167) );
NAND2X1TS U5610 ( .A(n5666), .B(n2513), .Y(n4179) );
NAND2X1TS U5611 ( .A(n4288), .B(DmP_EXP_EWSW[0]), .Y(n4180) );
NAND2X2TS U5612 ( .A(n4295), .B(intDX_EWSW[1]), .Y(n4185) );
NAND2X1TS U5613 ( .A(n4288), .B(DmP_EXP_EWSW[1]), .Y(n4183) );
NAND2X2TS U5614 ( .A(n2505), .B(intDX_EWSW[24]), .Y(n4188) );
NAND2X1TS U5615 ( .A(n5445), .B(DmP_EXP_EWSW[24]), .Y(n4186) );
NAND3X2TS U5616 ( .A(n4188), .B(n4187), .C(n4186), .Y(n1350) );
NAND2X1TS U5617 ( .A(n4276), .B(DmP_EXP_EWSW[42]), .Y(n4190) );
NAND3X2TS U5618 ( .A(n4191), .B(n4192), .C(n4190), .Y(n1314) );
NAND2X1TS U5619 ( .A(n4276), .B(DmP_EXP_EWSW[14]), .Y(n4193) );
NAND2X1TS U5620 ( .A(n4296), .B(DmP_EXP_EWSW[38]), .Y(n4196) );
NAND2X2TS U5621 ( .A(n2505), .B(intDX_EWSW[10]), .Y(n4201) );
NAND2X1TS U5622 ( .A(n4288), .B(DmP_EXP_EWSW[10]), .Y(n4199) );
NAND2X2TS U5623 ( .A(n3845), .B(intDX_EWSW[34]), .Y(n4204) );
NAND2X1TS U5624 ( .A(n4296), .B(DmP_EXP_EWSW[34]), .Y(n4202) );
NAND3X2TS U5625 ( .A(n4203), .B(n4204), .C(n4202), .Y(n1330) );
NAND2X1TS U5626 ( .A(n4276), .B(DmP_EXP_EWSW[40]), .Y(n4205) );
NAND2X1TS U5627 ( .A(n4276), .B(n2411), .Y(n4208) );
NAND3X2TS U5628 ( .A(n4210), .B(n4209), .C(n4208), .Y(n1392) );
NAND2X1TS U5629 ( .A(n4211), .B(DmP_EXP_EWSW[8]), .Y(n4212) );
NAND2X1TS U5630 ( .A(n4276), .B(DmP_EXP_EWSW[4]), .Y(n4215) );
NAND2X1TS U5631 ( .A(n4296), .B(n2412), .Y(n4218) );
NAND3X2TS U5632 ( .A(n4220), .B(n4219), .C(n4218), .Y(n1334) );
NAND2X2TS U5633 ( .A(n2993), .B(intDX_EWSW[6]), .Y(n4223) );
NAND2X1TS U5634 ( .A(n4288), .B(DmP_EXP_EWSW[6]), .Y(n4221) );
NAND3X2TS U5635 ( .A(n4222), .B(n4223), .C(n4221), .Y(n1386) );
NAND2X1TS U5636 ( .A(n4288), .B(DmP_EXP_EWSW[20]), .Y(n4224) );
NAND2X2TS U5637 ( .A(n2992), .B(intDX_EWSW[2]), .Y(n4229) );
NAND2X1TS U5638 ( .A(n4288), .B(DmP_EXP_EWSW[2]), .Y(n4227) );
NAND2X1TS U5639 ( .A(n4288), .B(DmP_EXP_EWSW[9]), .Y(n4230) );
NAND2X2TS U5640 ( .A(n3845), .B(intDX_EWSW[11]), .Y(n4235) );
NAND2X1TS U5641 ( .A(n4276), .B(DmP_EXP_EWSW[11]), .Y(n4233) );
NAND3X2TS U5642 ( .A(n4234), .B(n4235), .C(n4233), .Y(n1376) );
NAND2X1TS U5643 ( .A(n5349), .B(intDY_EWSW[12]), .Y(n4237) );
NAND2X1TS U5644 ( .A(n4276), .B(n2410), .Y(n4236) );
NAND3X2TS U5645 ( .A(n4238), .B(n4237), .C(n4236), .Y(n1374) );
NAND2X1TS U5646 ( .A(n4276), .B(DmP_EXP_EWSW[13]), .Y(n4239) );
NAND2X2TS U5647 ( .A(n4295), .B(intDX_EWSW[5]), .Y(n4244) );
NAND2X1TS U5648 ( .A(n4276), .B(DmP_EXP_EWSW[5]), .Y(n4242) );
NAND3X2TS U5649 ( .A(n4244), .B(n4243), .C(n4242), .Y(n1388) );
NAND2X1TS U5650 ( .A(n4288), .B(DmP_EXP_EWSW[7]), .Y(n4246) );
NAND2X1TS U5651 ( .A(n5445), .B(DmP_EXP_EWSW[26]), .Y(n4249) );
NAND2X2TS U5652 ( .A(n2505), .B(intDX_EWSW[30]), .Y(n4254) );
NAND2X1TS U5653 ( .A(n4308), .B(DmP_EXP_EWSW[30]), .Y(n4252) );
NAND3X2TS U5654 ( .A(n4254), .B(n4253), .C(n4252), .Y(n1338) );
NAND2X1TS U5655 ( .A(n4308), .B(DmP_EXP_EWSW[22]), .Y(n4255) );
NAND2X2TS U5656 ( .A(n2550), .B(intDX_EWSW[16]), .Y(n4260) );
NAND2X1TS U5657 ( .A(n4308), .B(DmP_EXP_EWSW[16]), .Y(n4258) );
NAND3X2TS U5658 ( .A(n4259), .B(n4260), .C(n4258), .Y(n1366) );
NAND2X1TS U5659 ( .A(n4308), .B(DmP_EXP_EWSW[18]), .Y(n4261) );
NAND2X2TS U5660 ( .A(n4245), .B(intDX_EWSW[28]), .Y(n4266) );
NAND2X1TS U5661 ( .A(n4308), .B(DmP_EXP_EWSW[28]), .Y(n4264) );
NAND2X1TS U5662 ( .A(n4308), .B(DmP_EXP_EWSW[17]), .Y(n4267) );
NAND3X2TS U5663 ( .A(n4269), .B(n4268), .C(n4267), .Y(n1364) );
NAND2X2TS U5664 ( .A(n2505), .B(intDX_EWSW[29]), .Y(n4272) );
NAND2X1TS U5665 ( .A(n4308), .B(DmP_EXP_EWSW[29]), .Y(n4270) );
NAND3X2TS U5666 ( .A(n4272), .B(n4271), .C(n4270), .Y(n1340) );
NAND2X2TS U5667 ( .A(n2992), .B(intDX_EWSW[19]), .Y(n4275) );
NAND2X1TS U5668 ( .A(n4288), .B(DmP_EXP_EWSW[19]), .Y(n4273) );
NAND2X1TS U5669 ( .A(n4276), .B(DmP_EXP_EWSW[39]), .Y(n4277) );
NAND3X2TS U5670 ( .A(n4278), .B(n4279), .C(n4277), .Y(n1320) );
NAND2X1TS U5671 ( .A(n4296), .B(DmP_EXP_EWSW[31]), .Y(n4280) );
NAND3X2TS U5672 ( .A(n4281), .B(n4282), .C(n4280), .Y(n1336) );
NAND2X1TS U5673 ( .A(n4308), .B(DmP_EXP_EWSW[27]), .Y(n4283) );
NAND2X2TS U5674 ( .A(n2992), .B(intDX_EWSW[21]), .Y(n4291) );
NAND2X1TS U5675 ( .A(n4288), .B(DmP_EXP_EWSW[21]), .Y(n4289) );
NAND2X1TS U5676 ( .A(n4296), .B(n2413), .Y(n4292) );
NAND3X2TS U5677 ( .A(n4294), .B(n4293), .C(n4292), .Y(n1324) );
NAND2X2TS U5678 ( .A(n3845), .B(intDX_EWSW[33]), .Y(n4299) );
NAND2X1TS U5679 ( .A(n4296), .B(DmP_EXP_EWSW[33]), .Y(n4297) );
NAND3X2TS U5680 ( .A(n4298), .B(n4299), .C(n4297), .Y(n1332) );
NAND2X2TS U5681 ( .A(n2505), .B(intDX_EWSW[15]), .Y(n4302) );
NAND2X1TS U5682 ( .A(n4308), .B(DmP_EXP_EWSW[15]), .Y(n4300) );
NAND3X2TS U5683 ( .A(n4302), .B(n4301), .C(n4300), .Y(n1368) );
NAND2X2TS U5684 ( .A(n2550), .B(intDX_EWSW[25]), .Y(n4305) );
NAND2X1TS U5685 ( .A(n5445), .B(DmP_EXP_EWSW[25]), .Y(n4303) );
NAND3X2TS U5686 ( .A(n4305), .B(n4304), .C(n4303), .Y(n1348) );
NAND2X2TS U5687 ( .A(n2993), .B(intDX_EWSW[23]), .Y(n4311) );
NAND2X1TS U5688 ( .A(n4308), .B(DmP_EXP_EWSW[23]), .Y(n4309) );
NAND3X2TS U5689 ( .A(n4311), .B(n4310), .C(n4309), .Y(n1352) );
INVX2TS U5690 ( .A(n5189), .Y(n6897) );
NAND2X1TS U5691 ( .A(n4388), .B(n1741), .Y(n4318) );
NAND4X4TS U5692 ( .A(n4318), .B(n4317), .C(n1950), .D(n4316), .Y(n5652) );
NAND2X1TS U5693 ( .A(n2523), .B(n1749), .Y(n4326) );
NAND2X1TS U5694 ( .A(n2713), .B(n1745), .Y(n4325) );
NAND2X1TS U5695 ( .A(n2477), .B(n1741), .Y(n4324) );
NAND2X1TS U5696 ( .A(n5505), .B(n1737), .Y(n4323) );
OR2X2TS U5697 ( .A(n1997), .B(n2194), .Y(n4328) );
OR2X2TS U5698 ( .A(n2273), .B(n2219), .Y(n4343) );
NAND2X4TS U5699 ( .A(n4366), .B(n4354), .Y(n4902) );
INVX2TS U5700 ( .A(n4354), .Y(n4355) );
INVX2TS U5701 ( .A(n4596), .Y(n4488) );
AOI21X1TS U5702 ( .A0(n4362), .A1(n4361), .B0(n4488), .Y(n4363) );
AOI22X1TS U5703 ( .A0(n4597), .A1(n4363), .B0(n4600), .B1(
Raw_mant_NRM_SWR[10]), .Y(n4370) );
NAND2X2TS U5704 ( .A(n5674), .B(n5702), .Y(n4377) );
NAND2X1TS U5705 ( .A(n2994), .B(intDY_EWSW[62]), .Y(n4383) );
NAND2X1TS U5706 ( .A(n5278), .B(DMP_EXP_EWSW[62]), .Y(n4381) );
NAND3X2TS U5707 ( .A(n4382), .B(n4383), .C(n4381), .Y(n1613) );
NAND2X1TS U5708 ( .A(n4189), .B(intDY_EWSW[61]), .Y(n4386) );
NAND2X1TS U5709 ( .A(n5278), .B(DMP_EXP_EWSW[61]), .Y(n4384) );
NAND3X2TS U5710 ( .A(n4385), .B(n4386), .C(n4384), .Y(n1614) );
MXI2X2TS U5711 ( .A(n6153), .B(n6324), .S0(n5888), .Y(n1487) );
NAND2X4TS U5712 ( .A(n1487), .B(n1114), .Y(n6037) );
OAI21X2TS U5713 ( .A0(n4394), .A1(n5975), .B0(n4393), .Y(n4395) );
NOR2X4TS U5714 ( .A(n3317), .B(DMP_SFG[9]), .Y(n4454) );
NAND2X4TS U5715 ( .A(n6336), .B(DMP_SFG[11]), .Y(n5516) );
OAI21X4TS U5716 ( .A0(n4400), .A1(n5516), .B0(n4399), .Y(n4619) );
INVX2TS U5717 ( .A(n4619), .Y(n4401) );
AOI21X1TS U5718 ( .A0(n4621), .A1(n4403), .B0(n4402), .Y(n4404) );
INVX2TS U5719 ( .A(n4467), .Y(n4406) );
NAND2X1TS U5720 ( .A(n4406), .B(n4466), .Y(n4410) );
INVX2TS U5721 ( .A(n4410), .Y(n4407) );
NAND2X1TS U5722 ( .A(n3351), .B(DMP_SFG[14]), .Y(n4418) );
NOR2X8TS U5723 ( .A(sub_x_5_n624), .B(DMP_SFG[18]), .Y(n4716) );
CLKINVX6TS U5724 ( .A(n4833), .Y(n5011) );
NOR2X1TS U5725 ( .A(n5012), .B(n4438), .Y(n4440) );
OAI21X4TS U5726 ( .A0(n5619), .A1(sub_x_5_n424), .B0(n5620), .Y(n5593) );
OAI21X4TS U5727 ( .A0(n4716), .A1(n5595), .B0(n4717), .Y(n4423) );
OAI21X4TS U5728 ( .A0(n4426), .A1(n4728), .B0(n4425), .Y(n4811) );
OAI21X4TS U5729 ( .A0(n4436), .A1(n5013), .B0(n4435), .Y(n4916) );
OAI21X1TS U5730 ( .A0(n5019), .A1(n4438), .B0(n4437), .Y(n4439) );
INVX2TS U5731 ( .A(n4449), .Y(n4442) );
INVX2TS U5732 ( .A(n4523), .Y(n4453) );
INVX2TS U5733 ( .A(n4527), .Y(n4452) );
OAI21X1TS U5734 ( .A0(n5746), .A1(n4453), .B0(n4452), .Y(n4456) );
INVX2TS U5735 ( .A(n4454), .Y(n4526) );
NAND2X1TS U5736 ( .A(n4526), .B(n4524), .Y(n4455) );
NAND2X1TS U5737 ( .A(n6069), .B(add_x_6_n489), .Y(n4457) );
AOI22X1TS U5738 ( .A0(n4459), .A1(n5925), .B0(Raw_mant_NRM_SWR[11]), .B1(
n5924), .Y(n4460) );
NAND2X1TS U5739 ( .A(n5617), .B(sub_x_5_n424), .Y(n4462) );
XNOR2X1TS U5740 ( .A(n2549), .B(n4462), .Y(n4475) );
INVX2TS U5741 ( .A(n4465), .Y(n4468) );
INVX2TS U5742 ( .A(n4469), .Y(n4471) );
NAND2X1TS U5743 ( .A(n4471), .B(n4470), .Y(n4472) );
AOI22X1TS U5744 ( .A0(n4473), .A1(n5626), .B0(Raw_mant_NRM_SWR[17]), .B1(
n5991), .Y(n4474) );
OAI2BB1X2TS U5745 ( .A0N(n5630), .A1N(n4475), .B0(n4474), .Y(n1252) );
MXI2X4TS U5746 ( .A(n6159), .B(n6255), .S0(n5883), .Y(n1505) );
NAND2X2TS U5747 ( .A(n5674), .B(n5701), .Y(n4482) );
INVX2TS U5748 ( .A(n5666), .Y(n4483) );
NOR2X1TS U5749 ( .A(n4485), .B(Raw_mant_NRM_SWR[25]), .Y(n4486) );
INVX2TS U5750 ( .A(n4501), .Y(n4490) );
NOR2X1TS U5751 ( .A(n4492), .B(Raw_mant_NRM_SWR[41]), .Y(n4493) );
NAND2X1TS U5752 ( .A(n6126), .B(Raw_mant_NRM_SWR[32]), .Y(n4496) );
NOR2X1TS U5753 ( .A(Raw_mant_NRM_SWR[29]), .B(n2287), .Y(n4499) );
INVX2TS U5754 ( .A(n4500), .Y(n4503) );
NOR2X1TS U5755 ( .A(n4501), .B(Raw_mant_NRM_SWR[41]), .Y(n4502) );
NAND2X1TS U5756 ( .A(n4504), .B(Raw_mant_NRM_SWR[44]), .Y(n4507) );
INVX2TS U5757 ( .A(n2621), .Y(n4505) );
AOI21X1TS U5758 ( .A0(n4507), .A1(n4506), .B0(n4505), .Y(n4510) );
NOR2BX4TS U5759 ( .AN(n4513), .B(n4512), .Y(n4515) );
MXI2X4TS U5760 ( .A(n6160), .B(n6249), .S0(n5883), .Y(n1508) );
MXI2X4TS U5761 ( .A(n6176), .B(n6251), .S0(n5884), .Y(n1556) );
NOR2X6TS U5762 ( .A(n1556), .B(n1137), .Y(n6033) );
NAND2X1TS U5763 ( .A(n4523), .B(n4526), .Y(n4529) );
INVX2TS U5764 ( .A(n4524), .Y(n4525) );
AOI21X1TS U5765 ( .A0(n4527), .A1(n4526), .B0(n4525), .Y(n4528) );
INVX2TS U5766 ( .A(n4530), .Y(n4532) );
NAND2X1TS U5767 ( .A(n4532), .B(n4531), .Y(n4533) );
INVX2TS U5768 ( .A(n5520), .Y(n4535) );
NAND2X1TS U5769 ( .A(n6080), .B(n5521), .Y(n4536) );
INVX2TS U5770 ( .A(n4540), .Y(n5517) );
NAND2X1TS U5771 ( .A(n4618), .B(n5517), .Y(n4543) );
INVX2TS U5772 ( .A(n5516), .Y(n4541) );
INVX2TS U5773 ( .A(n4549), .Y(n4545) );
XNOR2X1TS U5774 ( .A(n4550), .B(n4549), .Y(n4551) );
MXI2X2TS U5775 ( .A(n6182), .B(n6326), .S0(n5884), .Y(n1574) );
OAI21X1TS U5776 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n6090), .B0(n6112), .Y(
n4574) );
NAND2X1TS U5777 ( .A(n4576), .B(Raw_mant_NRM_SWR[29]), .Y(n4577) );
INVX2TS U5778 ( .A(n4582), .Y(n4583) );
NAND3X1TS U5779 ( .A(n4583), .B(n6127), .C(n6089), .Y(n4586) );
OAI21X1TS U5780 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n6092), .B0(n6125), .Y(
n4595) );
BUFX16TS U5781 ( .A(n5853), .Y(n5880) );
NAND2X2TS U5782 ( .A(n6267), .B(Shift_amount_SHT1_EWR[1]), .Y(n4784) );
NAND2X2TS U5783 ( .A(n5674), .B(n5572), .Y(n4606) );
NAND4X4TS U5784 ( .A(n4608), .B(n4607), .C(n5574), .D(n4606), .Y(n5586) );
MX2X6TS U5785 ( .A(n5586), .B(DmP_mant_SFG_SWR[21]), .S0(n2507), .Y(n1135)
);
NAND2X4TS U5786 ( .A(n4616), .B(n5572), .Y(n4610) );
AOI21X4TS U5787 ( .A0(n4615), .A1(n2381), .B0(n4614), .Y(n6903) );
MXI2X4TS U5788 ( .A(n6158), .B(n6252), .S0(n5883), .Y(n1502) );
NAND2X2TS U5789 ( .A(n5674), .B(n2497), .Y(n4617) );
NAND2X1TS U5790 ( .A(n4618), .B(n4620), .Y(n4623) );
AOI21X1TS U5791 ( .A0(n4621), .A1(n4620), .B0(n4619), .Y(n4622) );
OAI21X2TS U5792 ( .A0(n5746), .A1(n4623), .B0(n4622), .Y(n4628) );
INVX2TS U5793 ( .A(n4624), .Y(n4626) );
NAND2X1TS U5794 ( .A(n4626), .B(n4625), .Y(n4635) );
INVX2TS U5795 ( .A(n4635), .Y(n4627) );
XNOR2X1TS U5796 ( .A(n4628), .B(n4627), .Y(n4639) );
INVX2TS U5797 ( .A(n4630), .Y(n4631) );
AOI21X1TS U5798 ( .A0(n2463), .A1(n4632), .B0(n4631), .Y(n4633) );
OAI21X1TS U5799 ( .A0(n5525), .A1(n4634), .B0(n4633), .Y(n4636) );
XNOR2X1TS U5800 ( .A(n4636), .B(n4635), .Y(n4637) );
MXI2X2TS U5801 ( .A(n6175), .B(n6325), .S0(n5884), .Y(n1553) );
NOR2X4TS U5802 ( .A(n1553), .B(n1136), .Y(n6039) );
NAND2X1TS U5803 ( .A(n6297), .B(DMP_SFG[30]), .Y(n4641) );
OAI21X4TS U5804 ( .A0(n4651), .A1(n5128), .B0(n4650), .Y(n5109) );
NAND2X1TS U5805 ( .A(n6296), .B(DMP_SFG[38]), .Y(n4652) );
AOI21X4TS U5806 ( .A0(n5109), .A1(n4655), .B0(n4654), .Y(n4656) );
NAND2X1TS U5807 ( .A(n3355), .B(DMP_SFG[44]), .Y(n4662) );
OAI21X4TS U5808 ( .A0(n4663), .A1(n5090), .B0(n4662), .Y(n4990) );
OAI21X1TS U5809 ( .A0(n4665), .A1(n4970), .B0(n4664), .Y(n4666) );
NAND2X2TS U5810 ( .A(n6300), .B(DMP_SFG[47]), .Y(n4678) );
NOR2X4TS U5811 ( .A(DMP_SFG[48]), .B(DmP_mant_SFG_SWR[50]), .Y(n5580) );
INVX2TS U5812 ( .A(n5580), .Y(n4673) );
INVX2TS U5813 ( .A(n5589), .Y(n4674) );
XOR2X4TS U5814 ( .A(n4675), .B(n4674), .Y(N88) );
NOR2X2TS U5815 ( .A(n3362), .B(DMP_SFG[49]), .Y(n5207) );
INVX2TS U5816 ( .A(n5207), .Y(n4681) );
NOR2X1TS U5817 ( .A(n5235), .B(n4683), .Y(n4684) );
NAND2X2TS U5818 ( .A(n6298), .B(DMP_SFG[48]), .Y(n4677) );
OAI21X2TS U5819 ( .A0(n4679), .A1(n4678), .B0(n4677), .Y(n5225) );
NAND2X2TS U5820 ( .A(n3362), .B(DMP_SFG[49]), .Y(n5210) );
INVX2TS U5821 ( .A(n5210), .Y(n4680) );
AOI21X1TS U5822 ( .A0(n5225), .A1(n4681), .B0(n4680), .Y(n4682) );
INVX2TS U5823 ( .A(n4870), .Y(n4803) );
INVX2TS U5824 ( .A(n5611), .Y(n4685) );
BUFX8TS U5825 ( .A(n5280), .Y(n5996) );
INVX2TS U5826 ( .A(n4729), .Y(n4813) );
INVX2TS U5827 ( .A(n4730), .Y(n4686) );
NAND2X1TS U5828 ( .A(n4686), .B(n4728), .Y(n4687) );
INVX2TS U5829 ( .A(n4721), .Y(n4689) );
NOR2X1TS U5830 ( .A(n4689), .B(add_x_6_n406), .Y(n4691) );
OAI21X1TS U5831 ( .A0(n6077), .A1(add_x_6_n406), .B0(n4722), .Y(n4690) );
AOI21X4TS U5832 ( .A0(n5625), .A1(n4691), .B0(n4690), .Y(n4694) );
NAND2X1TS U5833 ( .A(n6062), .B(n4692), .Y(n4693) );
AOI22X1TS U5834 ( .A0(n4695), .A1(n5626), .B0(n2003), .B1(n5991), .Y(n4696)
);
NOR2X1TS U5835 ( .A(n5012), .B(n4699), .Y(n4701) );
OAI21X1TS U5836 ( .A0(n5019), .A1(n4699), .B0(n4698), .Y(n4700) );
INVX2TS U5837 ( .A(n4778), .Y(n4702) );
INVX2TS U5838 ( .A(n4707), .Y(n4703) );
AOI21X4TS U5839 ( .A0(n2506), .A1(n3105), .B0(n2452), .Y(n4708) );
AOI22X2TS U5840 ( .A0(n4709), .A1(n5527), .B0(Raw_mant_NRM_SWR[26]), .B1(
n5030), .Y(n4710) );
OAI2BB1X4TS U5841 ( .A0N(n5630), .A1N(n4711), .B0(n4710), .Y(n1243) );
INVX2TS U5842 ( .A(n2310), .Y(n4712) );
NOR2X1TS U5843 ( .A(n4712), .B(n5594), .Y(n4715) );
INVX2TS U5844 ( .A(n1982), .Y(n4713) );
OAI21X1TS U5845 ( .A0(n4713), .A1(n5594), .B0(n5595), .Y(n4714) );
INVX2TS U5846 ( .A(n4716), .Y(n4718) );
NAND2X1TS U5847 ( .A(n4718), .B(n4717), .Y(n4719) );
NAND2X1TS U5848 ( .A(n6060), .B(n4722), .Y(n4723) );
AOI22X2TS U5849 ( .A0(n4724), .A1(n5626), .B0(Raw_mant_NRM_SWR[20]), .B1(
n5030), .Y(n4725) );
NOR2X1TS U5850 ( .A(n4727), .B(n4730), .Y(n4732) );
OAI21X1TS U5851 ( .A0(n4730), .A1(n4729), .B0(n4728), .Y(n4731) );
INVX2TS U5852 ( .A(n2866), .Y(n4733) );
INVX2TS U5853 ( .A(n4736), .Y(n4734) );
INVX2TS U5854 ( .A(n4821), .Y(n4891) );
INVX2TS U5855 ( .A(n4824), .Y(n4894) );
INVX2TS U5856 ( .A(n4738), .Y(n4774) );
NAND2X1TS U5857 ( .A(n4767), .B(n4774), .Y(n4741) );
INVX2TS U5858 ( .A(n4773), .Y(n4739) );
AOI21X1TS U5859 ( .A0(n4768), .A1(n4774), .B0(n4739), .Y(n4740) );
OAI21X1TS U5860 ( .A0(n5019), .A1(n4741), .B0(n4740), .Y(n4742) );
INVX2TS U5861 ( .A(n4744), .Y(n4841) );
INVX2TS U5862 ( .A(n4750), .Y(n4745) );
INVX2TS U5863 ( .A(n4838), .Y(n4748) );
NOR2X1TS U5864 ( .A(n5022), .B(n4748), .Y(n4749) );
INVX2TS U5865 ( .A(n2015), .Y(n4747) );
INVX2TS U5866 ( .A(n4754), .Y(n4944) );
NAND2X1TS U5867 ( .A(n4944), .B(sub_x_5_n266), .Y(n4755) );
INVX2TS U5868 ( .A(n4932), .Y(n4757) );
OAI21X1TS U5869 ( .A0(n4757), .A1(n4926), .B0(n4927), .Y(n4758) );
INVX2TS U5870 ( .A(n4761), .Y(n4763) );
AOI22X2TS U5871 ( .A0(n4764), .A1(n5925), .B0(Raw_mant_NRM_SWR[33]), .B1(
n5924), .Y(n4765) );
INVX2TS U5872 ( .A(n4767), .Y(n4770) );
INVX2TS U5873 ( .A(n4768), .Y(n4769) );
NAND2X1TS U5874 ( .A(n4774), .B(n4773), .Y(n4775) );
NOR2X1TS U5875 ( .A(n5022), .B(n4778), .Y(n4780) );
NAND2X1TS U5876 ( .A(n6072), .B(n4781), .Y(n4782) );
INVX2TS U5877 ( .A(n4784), .Y(n4785) );
NAND2BX4TS U5878 ( .AN(n4788), .B(n4787), .Y(n4789) );
NAND2X4TS U5879 ( .A(n4983), .B(n4797), .Y(n4799) );
NAND2X4TS U5880 ( .A(n5168), .B(n4801), .Y(n5605) );
NOR2X4TS U5881 ( .A(n5580), .B(n5230), .Y(n5604) );
NAND2X1TS U5882 ( .A(n5604), .B(n4803), .Y(n4805) );
OAI21X1TS U5883 ( .A0(n4795), .A1(n4979), .B0(n4794), .Y(n4796) );
AOI21X2TS U5884 ( .A0(n4982), .A1(n4797), .B0(n4796), .Y(n4798) );
OAI21X4TS U5885 ( .A0(n4799), .A1(n4860), .B0(n4798), .Y(n4800) );
OAI21X4TS U5886 ( .A0(n5230), .A1(n5579), .B0(n5231), .Y(n5606) );
INVX2TS U5887 ( .A(n4872), .Y(n4802) );
AOI21X1TS U5888 ( .A0(n5606), .A1(n4803), .B0(n4802), .Y(n4804) );
INVX2TS U5889 ( .A(n4873), .Y(n4807) );
NAND2X4TS U5890 ( .A(n4810), .B(n4812), .Y(n5056) );
INVX2TS U5891 ( .A(n5056), .Y(n4815) );
AOI21X4TS U5892 ( .A0(n4813), .A1(n4812), .B0(n4811), .Y(n5059) );
INVX2TS U5893 ( .A(n5059), .Y(n4814) );
INVX2TS U5894 ( .A(n4816), .Y(n4818) );
INVX2TS U5895 ( .A(n4827), .Y(n4819) );
NOR2X1TS U5896 ( .A(n4821), .B(n2866), .Y(n4826) );
OAI21X1TS U5897 ( .A0(n4824), .A1(n2866), .B0(n4822), .Y(n4825) );
AOI21X4TS U5898 ( .A0(n5625), .A1(n4826), .B0(n4825), .Y(n4828) );
AOI22X1TS U5899 ( .A0(n4829), .A1(n5626), .B0(Raw_mant_NRM_SWR[23]), .B1(
n5991), .Y(n4830) );
NOR2X2TS U5900 ( .A(n5012), .B(n4833), .Y(n4835) );
OAI21X2TS U5901 ( .A0(n5019), .A1(n4833), .B0(n4832), .Y(n4834) );
INVX2TS U5902 ( .A(n4836), .Y(n5015) );
NAND2X1TS U5903 ( .A(n5015), .B(n5013), .Y(n4837) );
NAND2X1TS U5904 ( .A(n4838), .B(n4841), .Y(n4844) );
NOR2X1TS U5905 ( .A(n5022), .B(n4844), .Y(n4846) );
INVX2TS U5906 ( .A(n4839), .Y(n4840) );
AOI21X1TS U5907 ( .A0(n2015), .A1(n4841), .B0(n4840), .Y(n4843) );
INVX2TS U5908 ( .A(n4847), .Y(n4849) );
NAND2X1TS U5909 ( .A(n4849), .B(n4848), .Y(n4850) );
MXI2X2TS U5910 ( .A(n6183), .B(n6327), .S0(n5884), .Y(n1577) );
INVX2TS U5911 ( .A(n4855), .Y(n5091) );
INVX2TS U5912 ( .A(n5090), .Y(n4856) );
INVX2TS U5913 ( .A(n4857), .Y(n5003) );
INVX2TS U5914 ( .A(n4864), .Y(n4858) );
XOR2X4TS U5915 ( .A(n4865), .B(n4864), .Y(n4866) );
NAND2X2TS U5916 ( .A(n5604), .B(n4875), .Y(n5633) );
OAI21X1TS U5917 ( .A0(n4873), .A1(n4872), .B0(n4871), .Y(n4874) );
AO21X4TS U5918 ( .A0(n1918), .A1(n5636), .B0(n4876), .Y(n4877) );
BUFX8TS U5919 ( .A(n4966), .Y(n5992) );
NAND2X4TS U5920 ( .A(n4879), .B(n5913), .Y(n4881) );
AOI22X1TS U5921 ( .A0(n5699), .A1(Shift_amount_SHT1_EWR[5]), .B0(
shift_value_SHT2_EWR[5]), .B1(n1969), .Y(n4880) );
NAND2X4TS U5922 ( .A(n4881), .B(n4880), .Y(n1693) );
INVX6TS U5923 ( .A(n6267), .Y(n5861) );
OAI22X1TS U5924 ( .A0(n5819), .A1(n6133), .B0(n5861), .B1(n6208), .Y(n4883)
);
NOR2X2TS U5925 ( .A(n6015), .B(n2287), .Y(n4882) );
MXI2X4TS U5926 ( .A(n6816), .B(n2554), .S0(n2304), .Y(n6859) );
INVX2TS U5927 ( .A(n4886), .Y(n4888) );
NAND2X1TS U5928 ( .A(n4888), .B(n4887), .Y(n4897) );
INVX2TS U5929 ( .A(n4897), .Y(n4889) );
NOR2X1TS U5930 ( .A(n5067), .B(n5062), .Y(n4896) );
AOI21X4TS U5931 ( .A0(n4893), .A1(n4894), .B0(n4892), .Y(n5068) );
INVX2TS U5932 ( .A(n4902), .Y(n4903) );
INVX2TS U5933 ( .A(n4905), .Y(n4907) );
NOR2X1TS U5934 ( .A(n4910), .B(Raw_mant_NRM_SWR[41]), .Y(n4911) );
INVX2TS U5935 ( .A(n4914), .Y(n4915) );
NOR2X1TS U5936 ( .A(n5012), .B(n4923), .Y(n4925) );
INVX2TS U5937 ( .A(n4916), .Y(n4919) );
INVX2TS U5938 ( .A(n4926), .Y(n4928) );
NAND2X1TS U5939 ( .A(n4928), .B(n4927), .Y(n4939) );
INVX2TS U5940 ( .A(n4939), .Y(n4929) );
XOR2X4TS U5941 ( .A(n4930), .B(n4929), .Y(n4943) );
OAI2BB1X4TS U5942 ( .A0N(n5928), .A1N(n4943), .B0(n4942), .Y(n1237) );
BUFX8TS U5943 ( .A(n5280), .Y(n6721) );
NAND2X1TS U5944 ( .A(n6086), .B(n4945), .Y(n4946) );
XOR2X4TS U5945 ( .A(n4947), .B(n4946), .Y(n4952) );
INVX2TS U5946 ( .A(n4948), .Y(n5180) );
NAND2X1TS U5947 ( .A(n5180), .B(add_x_6_n265), .Y(n4949) );
OAI2BB1X4TS U5948 ( .A0N(n6721), .A1N(n4952), .B0(n4951), .Y(n1235) );
AND2X8TS U5949 ( .A(n4953), .B(n6858), .Y(n6894) );
INVX2TS U5950 ( .A(n4955), .Y(n4957) );
NAND2X1TS U5951 ( .A(n4957), .B(n4956), .Y(n4964) );
INVX2TS U5952 ( .A(n4964), .Y(n4958) );
XOR2X4TS U5953 ( .A(n4959), .B(n4958), .Y(n4968) );
INVX2TS U5954 ( .A(n5144), .Y(n5134) );
NOR2X1TS U5955 ( .A(n5116), .B(n5113), .Y(n4963) );
INVX2TS U5956 ( .A(n5146), .Y(n5133) );
AOI21X4TS U5957 ( .A0(n5133), .A1(n4961), .B0(n4960), .Y(n5117) );
OAI21X1TS U5958 ( .A0(n5117), .A1(n5113), .B0(n5114), .Y(n4962) );
AOI21X4TS U5959 ( .A0(n2609), .A1(n4963), .B0(n4962), .Y(n4965) );
XOR2X4TS U5960 ( .A(n4965), .B(n4964), .Y(n4967) );
INVX2TS U5961 ( .A(n4991), .Y(n4969) );
NAND2X4TS U5962 ( .A(n4974), .B(n4989), .Y(n4976) );
NOR2X1TS U5963 ( .A(n5156), .B(n4976), .Y(n4977) );
INVX2TS U5964 ( .A(n4990), .Y(n4972) );
INVX2TS U5965 ( .A(n4978), .Y(n4980) );
INVX2TS U5966 ( .A(n4988), .Y(n4981) );
NOR2X1TS U5967 ( .A(n5095), .B(n4985), .Y(n4987) );
NOR2X1TS U5968 ( .A(n5156), .B(n4993), .Y(n4994) );
INVX2TS U5969 ( .A(n4995), .Y(n4997) );
INVX2TS U5970 ( .A(n5009), .Y(n4998) );
NOR2X1TS U5971 ( .A(n5095), .B(n5006), .Y(n5007) );
INVX2TS U5972 ( .A(n5001), .Y(n5002) );
INVX2TS U5973 ( .A(n5013), .Y(n5014) );
AOI21X1TS U5974 ( .A0(n5016), .A1(n5015), .B0(n5014), .Y(n5017) );
INVX2TS U5975 ( .A(n5028), .Y(n5021) );
INVX2TS U5976 ( .A(n5174), .Y(n5033) );
NOR2X1TS U5977 ( .A(n5033), .B(n5175), .Y(n5036) );
INVX2TS U5978 ( .A(n5173), .Y(n5034) );
INVX2TS U5979 ( .A(n5037), .Y(n5039) );
NAND2X1TS U5980 ( .A(n6079), .B(add_x_6_n251), .Y(n5040) );
INVX2TS U5981 ( .A(n5041), .Y(n5081) );
NAND2X1TS U5982 ( .A(n5076), .B(n5081), .Y(n5044) );
NOR2X1TS U5983 ( .A(n5156), .B(n5044), .Y(n5045) );
INVX2TS U5984 ( .A(n5080), .Y(n5042) );
INVX2TS U5985 ( .A(n5046), .Y(n5099) );
INVX2TS U5986 ( .A(n5051), .Y(n5047) );
INVX2TS U5987 ( .A(n5094), .Y(n5049) );
NOR2X1TS U5988 ( .A(n5095), .B(n5049), .Y(n5050) );
INVX2TS U5989 ( .A(n5100), .Y(n5048) );
NOR2X1TS U5990 ( .A(n5056), .B(n5058), .Y(n5061) );
INVX2TS U5991 ( .A(n5062), .Y(n5064) );
INVX2TS U5992 ( .A(n5071), .Y(n5065) );
INVX2TS U5993 ( .A(n5067), .Y(n5070) );
INVX2TS U5994 ( .A(n5068), .Y(n5069) );
AOI21X4TS U5995 ( .A0(n2506), .A1(n5070), .B0(n5069), .Y(n5072) );
AOI22X2TS U5996 ( .A0(n5073), .A1(n5626), .B0(Raw_mant_NRM_SWR[24]), .B1(
n5991), .Y(n5074) );
INVX2TS U5997 ( .A(n5076), .Y(n5079) );
NOR2X1TS U5998 ( .A(n5095), .B(n5169), .Y(n5082) );
OAI2BB1X4TS U5999 ( .A0N(n3234), .A1N(n5082), .B0(n1949), .Y(n5083) );
NAND2X1TS U6000 ( .A(n6064), .B(n5084), .Y(n5085) );
NOR2X1TS U6001 ( .A(n5156), .B(n5087), .Y(n5089) );
NAND2X1TS U6002 ( .A(n5091), .B(n5090), .Y(n5092) );
NOR2X1TS U6003 ( .A(n5095), .B(n5102), .Y(n5096) );
INVX2TS U6004 ( .A(n5097), .Y(n5098) );
AOI21X1TS U6005 ( .A0(n5100), .A1(n5099), .B0(n5098), .Y(n5101) );
NAND2X1TS U6006 ( .A(n6063), .B(n5105), .Y(n5106) );
OAI2BB1X4TS U6007 ( .A0N(n6722), .A1N(n5108), .B0(n5107), .Y(n1224) );
INVX2TS U6008 ( .A(n5113), .Y(n5115) );
INVX2TS U6009 ( .A(n5116), .Y(n5118) );
OAI2BB1X4TS U6010 ( .A0N(n3234), .A1N(n5118), .B0(n5117), .Y(n5119) );
INVX2TS U6011 ( .A(n5129), .Y(n5120) );
NAND2X1TS U6012 ( .A(n5120), .B(n5128), .Y(n5121) );
INVX2TS U6013 ( .A(n5122), .Y(n5123) );
NOR2X1TS U6014 ( .A(n5123), .B(add_x_6_n248), .Y(n5125) );
OAI21X1TS U6015 ( .A0(n6078), .A1(add_x_6_n248), .B0(add_x_6_n251), .Y(n5124) );
NAND2X1TS U6016 ( .A(n6071), .B(add_x_6_n244), .Y(n5126) );
INVX2TS U6017 ( .A(n5147), .Y(n5132) );
INVX2TS U6018 ( .A(n5136), .Y(n5139) );
INVX2TS U6019 ( .A(n5137), .Y(n5138) );
INVX2TS U6020 ( .A(n5140), .Y(n5142) );
NOR2X1TS U6021 ( .A(n5144), .B(n5147), .Y(n5149) );
OAI21X1TS U6022 ( .A0(n5147), .A1(n5146), .B0(n5145), .Y(n5148) );
NAND2X2TS U6023 ( .A(n5789), .B(Raw_mant_NRM_SWR[26]), .Y(n5154) );
NAND2X2TS U6024 ( .A(n5913), .B(n2286), .Y(n5153) );
NAND2X1TS U6025 ( .A(n5880), .B(DmP_mant_SHT1_SW[24]), .Y(n5152) );
NAND3X2TS U6026 ( .A(n5154), .B(n5153), .C(n5152), .Y(n6806) );
INVX2TS U6027 ( .A(n6806), .Y(n6874) );
NOR2X1TS U6028 ( .A(n5156), .B(n5158), .Y(n5161) );
INVX2TS U6029 ( .A(n5162), .Y(n5164) );
XOR2X4TS U6030 ( .A(n5166), .B(n5165), .Y(n5172) );
INVX2TS U6031 ( .A(n5169), .Y(n5170) );
AOI21X4TS U6032 ( .A0(n2552), .A1(n5174), .B0(n5173), .Y(n5179) );
INVX2TS U6033 ( .A(n5175), .Y(n5177) );
NAND2X1TS U6034 ( .A(n5177), .B(n5176), .Y(n5178) );
AOI21X4TS U6035 ( .A0(n3234), .A1(n5180), .B0(n6073), .Y(n5182) );
NAND2X1TS U6036 ( .A(n6070), .B(add_x_6_n260), .Y(n5181) );
OAI2BB1X4TS U6037 ( .A0N(n6722), .A1N(n5185), .B0(n5184), .Y(n1234) );
MXI2X2TS U6038 ( .A(n6174), .B(n6320), .S0(n5885), .Y(n1550) );
NAND2X2TS U6039 ( .A(n1505), .B(n2851), .Y(n6041) );
NAND2X2TS U6040 ( .A(n1502), .B(n2016), .Y(n6047) );
INVX2TS U6041 ( .A(n1733), .Y(n5644) );
OAI21X1TS U6042 ( .A0(n5540), .A1(n5644), .B0(n5538), .Y(n5187) );
NAND2X1TS U6043 ( .A(n2713), .B(n1729), .Y(n5192) );
NAND2X1TS U6044 ( .A(n2475), .B(n5189), .Y(n5191) );
NAND2X1TS U6045 ( .A(n5505), .B(n1721), .Y(n5190) );
NAND3X2TS U6046 ( .A(n5192), .B(n5191), .C(n5190), .Y(n5648) );
NAND2X2TS U6047 ( .A(n5648), .B(n5713), .Y(n5194) );
INVX2TS U6048 ( .A(n5654), .Y(n5197) );
NAND2X1TS U6049 ( .A(n5197), .B(n5729), .Y(n5199) );
MXI2X2TS U6050 ( .A(n6168), .B(n6330), .S0(n5885), .Y(n1532) );
NAND2X2TS U6051 ( .A(n5204), .B(n5727), .Y(n5205) );
NOR2X2TS U6052 ( .A(n2320), .B(DMP_SFG[50]), .Y(n5211) );
OA21X4TS U6053 ( .A0(n5217), .A1(n5214), .B0(n5213), .Y(n5215) );
INVX2TS U6054 ( .A(n5221), .Y(n5222) );
INVX2TS U6055 ( .A(n5224), .Y(n5227) );
NOR2X1TS U6056 ( .A(n5235), .B(n5227), .Y(n5229) );
INVX2TS U6057 ( .A(n5225), .Y(n5226) );
AOI21X2TS U6058 ( .A0(n1927), .A1(n5229), .B0(n5228), .Y(n5234) );
INVX2TS U6059 ( .A(n5230), .Y(n5232) );
INVX2TS U6060 ( .A(n5583), .Y(n5233) );
INVX2TS U6061 ( .A(n5235), .Y(n5238) );
INVX2TS U6062 ( .A(n5236), .Y(n5237) );
INVX2TS U6063 ( .A(n5240), .Y(n5241) );
CLKBUFX3TS U6064 ( .A(n5243), .Y(n5252) );
CLKBUFX3TS U6065 ( .A(n2546), .Y(n6356) );
CLKBUFX2TS U6066 ( .A(n5251), .Y(n6381) );
CLKBUFX3TS U6067 ( .A(n6381), .Y(n6386) );
CLKBUFX3TS U6068 ( .A(n1925), .Y(n6374) );
CLKBUFX3TS U6069 ( .A(n6360), .Y(n5248) );
CLKBUFX2TS U6070 ( .A(n5248), .Y(n6363) );
CLKBUFX3TS U6071 ( .A(n5247), .Y(n6352) );
CLKBUFX3TS U6072 ( .A(n5244), .Y(n6359) );
CLKBUFX2TS U6073 ( .A(n6357), .Y(n6724) );
CLKBUFX3TS U6074 ( .A(n6724), .Y(n6346) );
CLKBUFX3TS U6075 ( .A(n6353), .Y(n6349) );
CLKBUFX3TS U6076 ( .A(n6724), .Y(n6345) );
CLKBUFX2TS U6077 ( .A(n2492), .Y(n6355) );
CLKBUFX3TS U6078 ( .A(n5248), .Y(n6367) );
CLKBUFX3TS U6079 ( .A(n5248), .Y(n6365) );
CLKBUFX2TS U6080 ( .A(n5248), .Y(n6366) );
CLKBUFX2TS U6081 ( .A(n6732), .Y(n6379) );
CLKBUFX2TS U6082 ( .A(n1926), .Y(n6370) );
CLKBUFX2TS U6083 ( .A(n2488), .Y(n6380) );
CLKBUFX2TS U6084 ( .A(n5248), .Y(n6364) );
CLKBUFX2TS U6085 ( .A(n1925), .Y(n6371) );
CLKBUFX2TS U6086 ( .A(n1926), .Y(n6373) );
CLKBUFX2TS U6087 ( .A(n1925), .Y(n6372) );
CLKBUFX2TS U6088 ( .A(n2529), .Y(n6354) );
CLKBUFX2TS U6089 ( .A(n5247), .Y(n6348) );
CLKBUFX3TS U6090 ( .A(n1926), .Y(n6350) );
BUFX3TS U6091 ( .A(n5248), .Y(n6740) );
CLKBUFX3TS U6092 ( .A(n6768), .Y(n6767) );
BUFX3TS U6093 ( .A(n6767), .Y(n6763) );
BUFX3TS U6094 ( .A(n6767), .Y(n6765) );
BUFX3TS U6095 ( .A(n5252), .Y(n6758) );
BUFX3TS U6096 ( .A(n5243), .Y(n6759) );
BUFX3TS U6097 ( .A(n5252), .Y(n6760) );
BUFX3TS U6098 ( .A(n5243), .Y(n6761) );
BUFX3TS U6099 ( .A(n6767), .Y(n6766) );
BUFX3TS U6100 ( .A(n5243), .Y(n6744) );
BUFX3TS U6101 ( .A(n5252), .Y(n6746) );
BUFX3TS U6102 ( .A(n5247), .Y(n6751) );
CLKBUFX3TS U6103 ( .A(n6360), .Y(n5245) );
BUFX3TS U6104 ( .A(n5245), .Y(n6743) );
BUFX3TS U6105 ( .A(n6357), .Y(n6747) );
BUFX3TS U6106 ( .A(n6360), .Y(n6727) );
CLKBUFX3TS U6107 ( .A(n5252), .Y(n6755) );
CLKBUFX3TS U6108 ( .A(n5243), .Y(n6756) );
BUFX3TS U6109 ( .A(n5252), .Y(n6757) );
BUFX3TS U6110 ( .A(n6723), .Y(n6750) );
CLKBUFX3TS U6111 ( .A(n5243), .Y(n6754) );
BUFX3TS U6112 ( .A(n6724), .Y(n6726) );
CLKBUFX3TS U6113 ( .A(n6724), .Y(n6347) );
BUFX3TS U6114 ( .A(n5250), .Y(n6729) );
BUFX3TS U6115 ( .A(n5251), .Y(n6737) );
BUFX3TS U6116 ( .A(n5250), .Y(n6753) );
BUFX3TS U6117 ( .A(n5251), .Y(n6752) );
CLKBUFX3TS U6118 ( .A(n6724), .Y(n6344) );
BUFX3TS U6119 ( .A(n1926), .Y(n6369) );
CLKBUFX3TS U6120 ( .A(n6728), .Y(n6358) );
CLKBUFX2TS U6121 ( .A(n2488), .Y(n6383) );
BUFX3TS U6122 ( .A(n5245), .Y(n6735) );
BUFX3TS U6123 ( .A(n1925), .Y(n6368) );
CLKBUFX3TS U6124 ( .A(n5247), .Y(n6351) );
BUFX3TS U6125 ( .A(n6374), .Y(n6376) );
CLKBUFX3TS U6126 ( .A(n2516), .Y(n6382) );
CLKBUFX3TS U6127 ( .A(n5248), .Y(n6362) );
CLKBUFX3TS U6128 ( .A(n2488), .Y(n6378) );
CLKBUFX3TS U6129 ( .A(n6386), .Y(n6723) );
CLKBUFX3TS U6130 ( .A(n5248), .Y(n6361) );
CLKBUFX3TS U6131 ( .A(n5245), .Y(n6375) );
MXI2X2TS U6132 ( .A(n6403), .B(n6402), .S0(n6401), .Y(underflow_flag) );
CLKMX2X2TS U6133 ( .A(DMP_exp_NRM_EW[8]), .B(DMP_SFG[60]), .S0(n5851), .Y(
n1410) );
CLKMX2X2TS U6134 ( .A(DMP_exp_NRM_EW[10]), .B(DMP_SFG[62]), .S0(n5851), .Y(
n1400) );
CLKMX2X2TS U6135 ( .A(DMP_exp_NRM_EW[9]), .B(DMP_SFG[61]), .S0(n5851), .Y(
n1405) );
CLKMX2X2TS U6136 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[54]), .S0(n2548), .Y(
n1440) );
CLKMX2X2TS U6137 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[59]), .S0(n2548), .Y(
n1415) );
CLKMX2X2TS U6138 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n2548), .Y(
n1272) );
CLKMX2X2TS U6139 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(n2548), .Y(
n1283) );
CLKMX2X2TS U6140 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[56]), .S0(n2548), .Y(
n1430) );
CLKMX2X2TS U6141 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[58]), .S0(n2548), .Y(
n1420) );
CLKMX2X2TS U6142 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[55]), .S0(n2548), .Y(
n1435) );
CLKMX2X2TS U6143 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[53]), .S0(n2548), .Y(
n1445) );
CLKMX2X2TS U6144 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[52]), .S0(n2548), .Y(
n1450) );
CLKMX2X2TS U6145 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[57]), .S0(n2548), .Y(
n1425) );
OAI22X2TS U6146 ( .A0(n2547), .A1(n6676), .B0(n1935), .B1(n6675), .Y(
final_result_ieee[38]) );
OAI22X2TS U6147 ( .A0(n2547), .A1(n6664), .B0(n1937), .B1(n6663), .Y(
final_result_ieee[13]) );
OAI22X2TS U6148 ( .A0(n2547), .A1(n6650), .B0(n1937), .B1(n6649), .Y(
final_result_ieee[32]) );
OAI22X2TS U6149 ( .A0(n2547), .A1(n6639), .B0(n1937), .B1(n6638), .Y(
final_result_ieee[35]) );
OAI22X2TS U6150 ( .A0(n2547), .A1(n6643), .B0(n1937), .B1(n6642), .Y(
final_result_ieee[14]) );
OAI22X2TS U6151 ( .A0(n5762), .A1(n6630), .B0(n1937), .B1(n6629), .Y(
final_result_ieee[19]) );
OAI22X2TS U6152 ( .A0(n2547), .A1(n6621), .B0(n1937), .B1(n6620), .Y(
final_result_ieee[25]) );
NAND2X2TS U6153 ( .A(n5831), .B(n2162), .Y(n5254) );
NAND3X2TS U6154 ( .A(n5254), .B(n5253), .C(n6697), .Y(final_result_ieee[33])
);
NAND2X2TS U6155 ( .A(n5847), .B(n2172), .Y(n5256) );
NAND2X2TS U6156 ( .A(n5848), .B(n2163), .Y(n5255) );
NAND3X2TS U6157 ( .A(n5256), .B(n5255), .C(n6701), .Y(final_result_ieee[22])
);
NAND2X2TS U6158 ( .A(n5831), .B(n2165), .Y(n5258) );
NAND3X2TS U6159 ( .A(n5258), .B(n5257), .C(n6700), .Y(final_result_ieee[23])
);
NAND2X2TS U6160 ( .A(n5831), .B(n2171), .Y(n5260) );
NAND3X2TS U6161 ( .A(n5260), .B(n5259), .C(n6698), .Y(final_result_ieee[24])
);
NAND2X2TS U6162 ( .A(n5831), .B(n2166), .Y(n5262) );
NAND3X2TS U6163 ( .A(n5262), .B(n5261), .C(n6695), .Y(final_result_ieee[27])
);
NAND2X2TS U6164 ( .A(n5831), .B(n2170), .Y(n5264) );
NAND3X2TS U6165 ( .A(n5264), .B(n5263), .C(n6699), .Y(final_result_ieee[26])
);
NAND2X2TS U6166 ( .A(n5831), .B(n2156), .Y(n5266) );
NAND3X2TS U6167 ( .A(n5266), .B(n5265), .C(n6707), .Y(final_result_ieee[41])
);
NAND2X2TS U6168 ( .A(n5831), .B(n2183), .Y(n5268) );
NAND3X2TS U6169 ( .A(n5268), .B(n5267), .C(n6692), .Y(final_result_ieee[29])
);
NAND2X2TS U6170 ( .A(n5831), .B(n2163), .Y(n5270) );
NAND3X2TS U6171 ( .A(n5270), .B(n5269), .C(n6696), .Y(final_result_ieee[28])
);
NAND2X2TS U6172 ( .A(n5847), .B(n2159), .Y(n5272) );
NAND2X2TS U6173 ( .A(n5848), .B(n2156), .Y(n5271) );
NAND3X2TS U6174 ( .A(n5272), .B(n5271), .C(n6686), .Y(final_result_ieee[9])
);
INVX2TS U6175 ( .A(n5437), .Y(n5274) );
INVX2TS U6176 ( .A(n5438), .Y(n5277) );
NOR2X1TS U6177 ( .A(n5275), .B(n5278), .Y(n5276) );
NAND2X1TS U6178 ( .A(n6716), .B(n2518), .Y(n5279) );
XNOR2X1TS U6179 ( .A(DmP_mant_SFG_SWR[1]), .B(n2406), .Y(n5282) );
AOI22X1TS U6180 ( .A0(n5992), .A1(DmP_mant_SFG_SWR[1]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n5958), .Y(n5281) );
OR2X4TS U6181 ( .A(n5792), .B(n6243), .Y(n5285) );
NAND2X2TS U6182 ( .A(n5814), .B(Raw_mant_NRM_SWR[22]), .Y(n5284) );
NAND3X2TS U6183 ( .A(n5285), .B(n5284), .C(n5283), .Y(n6813) );
INVX2TS U6184 ( .A(n6813), .Y(n6864) );
NAND2X2TS U6185 ( .A(n5817), .B(Raw_mant_NRM_SWR[14]), .Y(n5287) );
NAND3X2TS U6186 ( .A(n5288), .B(n5287), .C(n5286), .Y(n6805) );
INVX2TS U6187 ( .A(n6805), .Y(n6884) );
OR2X4TS U6188 ( .A(n5792), .B(n2430), .Y(n5291) );
INVX12TS U6189 ( .A(n3341), .Y(n5823) );
NAND2X2TS U6190 ( .A(n5823), .B(Raw_mant_NRM_SWR[18]), .Y(n5290) );
NAND3X2TS U6191 ( .A(n5291), .B(n5290), .C(n5289), .Y(n6810) );
INVX2TS U6192 ( .A(n6810), .Y(n6889) );
NAND3X2TS U6193 ( .A(n5294), .B(n5293), .C(n5292), .Y(n6791) );
NAND2X2TS U6194 ( .A(n5814), .B(Raw_mant_NRM_SWR[2]), .Y(n5297) );
NAND3X2TS U6195 ( .A(n5298), .B(n5297), .C(n5296), .Y(n6797) );
INVX2TS U6196 ( .A(n6797), .Y(n6821) );
OR2X2TS U6197 ( .A(n5780), .B(n6197), .Y(n5301) );
NAND2X1TS U6198 ( .A(n5736), .B(DmP_mant_SHT1_SW[8]), .Y(n5299) );
NAND3X2TS U6199 ( .A(n5301), .B(n5300), .C(n5299), .Y(n6801) );
INVX2TS U6200 ( .A(n6801), .Y(n6895) );
OR2X2TS U6201 ( .A(n5792), .B(n6195), .Y(n5304) );
NAND2X2TS U6202 ( .A(n5817), .B(Raw_mant_NRM_SWR[6]), .Y(n5303) );
NAND2X1TS U6203 ( .A(n5736), .B(DmP_mant_SHT1_SW[4]), .Y(n5302) );
NAND3X2TS U6204 ( .A(n5304), .B(n5303), .C(n5302), .Y(n6803) );
INVX2TS U6205 ( .A(n6803), .Y(n6879) );
OR2X4TS U6206 ( .A(n5792), .B(n6246), .Y(n5306) );
NAND3X2TS U6207 ( .A(n5306), .B(n3350), .C(n5305), .Y(n6795) );
INVX2TS U6208 ( .A(n6795), .Y(n6850) );
AND2X2TS U6209 ( .A(n5823), .B(Raw_mant_NRM_SWR[20]), .Y(n5308) );
OAI22X1TS U6210 ( .A0(n5804), .A1(n6124), .B0(n5824), .B1(n6211), .Y(n5307)
);
NOR2X2TS U6211 ( .A(n5308), .B(n5307), .Y(n6862) );
AND2X2TS U6212 ( .A(n5823), .B(Raw_mant_NRM_SWR[17]), .Y(n5310) );
OAI22X1TS U6213 ( .A0(n5804), .A1(n6134), .B0(n5861), .B1(n6210), .Y(n5309)
);
NOR2X2TS U6214 ( .A(n5310), .B(n5309), .Y(n6890) );
OAI22X1TS U6215 ( .A0(n5801), .A1(n6091), .B0(n5800), .B1(n6241), .Y(n5311)
);
NOR2X2TS U6216 ( .A(n5312), .B(n5311), .Y(n6833) );
OR2X2TS U6217 ( .A(n5792), .B(n6206), .Y(n5315) );
NAND2X1TS U6218 ( .A(n5462), .B(DmP_mant_SHT1_SW[44]), .Y(n5313) );
NAND3X2TS U6219 ( .A(n5315), .B(n5314), .C(n5313), .Y(n6793) );
INVX2TS U6220 ( .A(n6793), .Y(n6840) );
INVX8TS U6221 ( .A(n3341), .Y(n5799) );
AND2X4TS U6222 ( .A(n5799), .B(Raw_mant_NRM_SWR[39]), .Y(n5318) );
OAI22X1TS U6223 ( .A0(n5801), .A1(n6092), .B0(n5779), .B1(n6236), .Y(n5317)
);
AND2X4TS U6224 ( .A(n5799), .B(Raw_mant_NRM_SWR[37]), .Y(n5320) );
OAI22X1TS U6225 ( .A0(n5801), .A1(n6125), .B0(n5800), .B1(n6234), .Y(n5319)
);
AND2X4TS U6226 ( .A(n5799), .B(Raw_mant_NRM_SWR[40]), .Y(n5322) );
OAI22X1TS U6227 ( .A0(n5801), .A1(n6114), .B0(n5800), .B1(n6235), .Y(n5321)
);
AND2X4TS U6228 ( .A(n5799), .B(Raw_mant_NRM_SWR[43]), .Y(n5324) );
OAI22X1TS U6229 ( .A0(n5801), .A1(n6090), .B0(n5800), .B1(n6230), .Y(n5323)
);
NOR2X4TS U6230 ( .A(n5324), .B(n5323), .Y(n6837) );
AND2X4TS U6231 ( .A(n5799), .B(Raw_mant_NRM_SWR[44]), .Y(n5326) );
OAI22X1TS U6232 ( .A0(n5801), .A1(n6193), .B0(n5800), .B1(n3322), .Y(n5325)
);
AND2X2TS U6233 ( .A(n5814), .B(Raw_mant_NRM_SWR[12]), .Y(n5328) );
OAI22X1TS U6234 ( .A0(n5819), .A1(n6135), .B0(n5818), .B1(n6223), .Y(n5327)
);
NOR2X2TS U6235 ( .A(n5328), .B(n5327), .Y(n6882) );
AND2X2TS U6236 ( .A(n5814), .B(Raw_mant_NRM_SWR[23]), .Y(n5331) );
OAI22X1TS U6237 ( .A0(n5825), .A1(n2433), .B0(n5824), .B1(n6219), .Y(n5330)
);
NOR2X2TS U6238 ( .A(n5331), .B(n5330), .Y(n6871) );
INVX2TS U6239 ( .A(n5334), .Y(n5335) );
INVX2TS U6240 ( .A(n5336), .Y(n5980) );
INVX2TS U6241 ( .A(n5337), .Y(n5450) );
NAND2X1TS U6242 ( .A(n5450), .B(n5449), .Y(n5338) );
XNOR2X1TS U6243 ( .A(n5980), .B(n5338), .Y(n5344) );
NAND2X1TS U6244 ( .A(n6058), .B(n5339), .Y(n5340) );
XNOR2X1TS U6245 ( .A(n5341), .B(n5340), .Y(n5342) );
AOI22X1TS U6246 ( .A0(n5342), .A1(n5992), .B0(Raw_mant_NRM_SWR[5]), .B1(
n5958), .Y(n5343) );
OAI2BB1X2TS U6247 ( .A0N(n5280), .A1N(n5344), .B0(n5343), .Y(n1264) );
AND2X2TS U6248 ( .A(n5814), .B(Raw_mant_NRM_SWR[4]), .Y(n5347) );
OAI22X1TS U6249 ( .A0(n5825), .A1(n5345), .B0(n5824), .B1(n6220), .Y(n5346)
);
NOR2X2TS U6250 ( .A(n5347), .B(n5346), .Y(n6877) );
NAND2X2TS U6251 ( .A(n5348), .B(intDY_EWSW[57]), .Y(n5353) );
NAND2X1TS U6252 ( .A(n5350), .B(DMP_EXP_EWSW[57]), .Y(n5351) );
OR2X2TS U6253 ( .A(n5780), .B(n6202), .Y(n5356) );
NAND2X2TS U6254 ( .A(n5799), .B(Raw_mant_NRM_SWR[34]), .Y(n5355) );
NAND2X1TS U6255 ( .A(n5462), .B(DmP_mant_SHT1_SW[32]), .Y(n5354) );
NAND3X2TS U6256 ( .A(n5356), .B(n5355), .C(n5354), .Y(n6789) );
INVX2TS U6257 ( .A(n6789), .Y(n6869) );
XNOR2X1TS U6258 ( .A(intDX_EWSW[47]), .B(intDY_EWSW[47]), .Y(n5358) );
XNOR2X1TS U6259 ( .A(intDX_EWSW[46]), .B(intDY_EWSW[46]), .Y(n5357) );
NAND4X1TS U6260 ( .A(n5360), .B(n5359), .C(n5358), .D(n5357), .Y(n5376) );
NAND4X1TS U6261 ( .A(n5364), .B(n5363), .C(n5362), .D(n5361), .Y(n5375) );
NAND4X1TS U6262 ( .A(n5372), .B(n5371), .C(n5370), .D(n5369), .Y(n5373) );
XNOR2X1TS U6263 ( .A(intDX_EWSW[27]), .B(n2437), .Y(n5380) );
XNOR2X1TS U6264 ( .A(intDX_EWSW[26]), .B(intDY_EWSW[26]), .Y(n5379) );
NAND4X1TS U6265 ( .A(n5380), .B(n5379), .C(n5378), .D(n5377), .Y(n5396) );
NAND4X1TS U6266 ( .A(n5384), .B(n5383), .C(n5382), .D(n5381), .Y(n5395) );
XNOR2X1TS U6267 ( .A(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n5386) );
XNOR2X1TS U6268 ( .A(intDX_EWSW[17]), .B(intDY_EWSW[17]), .Y(n5385) );
NAND4X1TS U6269 ( .A(n5392), .B(n5391), .C(n5390), .D(n5389), .Y(n5393) );
XNOR2X1TS U6270 ( .A(intDX_EWSW[12]), .B(intDY_EWSW[12]), .Y(n5400) );
XNOR2X1TS U6271 ( .A(intDX_EWSW[16]), .B(intDY_EWSW[16]), .Y(n5398) );
NAND4X1TS U6272 ( .A(n5400), .B(n5399), .C(n5398), .D(n5397), .Y(n5416) );
XNOR2X1TS U6273 ( .A(intDX_EWSW[7]), .B(n2847), .Y(n5404) );
XNOR2X1TS U6274 ( .A(intDX_EWSW[6]), .B(intDY_EWSW[6]), .Y(n5403) );
XNOR2X1TS U6275 ( .A(intDX_EWSW[5]), .B(intDY_EWSW[5]), .Y(n5401) );
NAND4X1TS U6276 ( .A(n5404), .B(n5403), .C(n5402), .D(n5401), .Y(n5415) );
XNOR2X1TS U6277 ( .A(intDX_EWSW[58]), .B(intDY_EWSW[58]), .Y(n5408) );
XNOR2X1TS U6278 ( .A(intDX_EWSW[60]), .B(intDY_EWSW[60]), .Y(n5407) );
XNOR2X1TS U6279 ( .A(intDX_EWSW[59]), .B(intDY_EWSW[59]), .Y(n5406) );
XNOR2X1TS U6280 ( .A(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n5405) );
NAND4X1TS U6281 ( .A(n5408), .B(n5407), .C(n5406), .D(n5405), .Y(n5414) );
XNOR2X1TS U6282 ( .A(intDX_EWSW[3]), .B(n2565), .Y(n5412) );
XNOR2X1TS U6283 ( .A(intDX_EWSW[0]), .B(n2407), .Y(n5409) );
NAND4X1TS U6284 ( .A(n5412), .B(n5411), .C(n5410), .D(n5409), .Y(n5413) );
XNOR2X1TS U6285 ( .A(intDX_EWSW[54]), .B(n1915), .Y(n5417) );
NAND4X1TS U6286 ( .A(n5425), .B(n5424), .C(n5423), .D(n5422), .Y(n5430) );
XNOR2X1TS U6287 ( .A(intDX_EWSW[61]), .B(intDY_EWSW[61]), .Y(n5428) );
NAND3X1TS U6288 ( .A(n5428), .B(n5427), .C(n5426), .Y(n5429) );
MXI2X1TS U6289 ( .A(n5438), .B(SIGN_FLAG_EXP), .S0(n5878), .Y(n5439) );
AND2X2TS U6290 ( .A(n5789), .B(Raw_mant_NRM_SWR[45]), .Y(n5443) );
OAI22X1TS U6291 ( .A0(n5780), .A1(n6130), .B0(n5800), .B1(n6237), .Y(n5442)
);
NOR2X2TS U6292 ( .A(n5443), .B(n5442), .Y(n6841) );
NAND2X2TS U6293 ( .A(n4295), .B(intDX_EWSW[55]), .Y(n5448) );
NAND2X1TS U6294 ( .A(n5445), .B(DmP_EXP_EWSW[55]), .Y(n5446) );
INVX2TS U6295 ( .A(n5451), .Y(n5453) );
NAND2X1TS U6296 ( .A(n5453), .B(n5452), .Y(n5454) );
XOR2X1TS U6297 ( .A(n5455), .B(n5454), .Y(n5461) );
INVX2TS U6298 ( .A(n5456), .Y(n5988) );
INVX2TS U6299 ( .A(n5457), .Y(n5965) );
NAND2X1TS U6300 ( .A(n5965), .B(add_x_6_n521), .Y(n5458) );
XNOR2X1TS U6301 ( .A(n5988), .B(n5458), .Y(n5459) );
AOI22X1TS U6302 ( .A0(n5459), .A1(n5992), .B0(Raw_mant_NRM_SWR[6]), .B1(
n5958), .Y(n5460) );
OAI2BB1X2TS U6303 ( .A0N(n5280), .A1N(n5461), .B0(n5460), .Y(n1263) );
OR2X2TS U6304 ( .A(n5792), .B(n6245), .Y(n5465) );
NAND2X1TS U6305 ( .A(n5462), .B(DmP_mant_SHT1_SW[40]), .Y(n5463) );
NAND3X2TS U6306 ( .A(n5465), .B(n5464), .C(n5463), .Y(n6787) );
INVX2TS U6307 ( .A(n6787), .Y(n6855) );
AND2X2TS U6308 ( .A(n5817), .B(Raw_mant_NRM_SWR[13]), .Y(n5467) );
OAI22X1TS U6309 ( .A0(n5819), .A1(n6207), .B0(n5818), .B1(n3333), .Y(n5466)
);
NOR2X2TS U6310 ( .A(n5467), .B(n5466), .Y(n6885) );
OAI22X1TS U6311 ( .A0(n5825), .A1(n6127), .B0(n5861), .B1(n6212), .Y(n5468)
);
NOR2X2TS U6312 ( .A(n3267), .B(n5468), .Y(n6861) );
OAI22X1TS U6313 ( .A0(n5825), .A1(n6116), .B0(n5824), .B1(n6218), .Y(n5469)
);
NOR2X2TS U6314 ( .A(n3301), .B(n5469), .Y(n6872) );
AND2X2TS U6315 ( .A(n5799), .B(Raw_mant_NRM_SWR[35]), .Y(n5471) );
OAI22X1TS U6316 ( .A0(n5801), .A1(n6119), .B0(n5800), .B1(n6233), .Y(n5470)
);
NOR2X2TS U6317 ( .A(n5471), .B(n5470), .Y(n6842) );
OAI22X1TS U6318 ( .A0(n5825), .A1(n6109), .B0(n5824), .B1(n6215), .Y(n5472)
);
OAI22X1TS U6319 ( .A0(n5825), .A1(n6132), .B0(n5824), .B1(n6214), .Y(n5473)
);
NAND2X1TS U6320 ( .A(n5477), .B(n5476), .Y(n5478) );
NAND2X1TS U6321 ( .A(n5481), .B(add_x_6_n492), .Y(n5482) );
NAND2X1TS U6322 ( .A(n6937), .B(n2557), .Y(n5492) );
NAND2X1TS U6323 ( .A(n5730), .B(DmP_mant_SFG_SWR[28]), .Y(n5491) );
NAND2X2TS U6324 ( .A(n5497), .B(n5653), .Y(n5500) );
NAND2X2TS U6325 ( .A(n5498), .B(n5727), .Y(n5499) );
NAND2X1TS U6326 ( .A(n5730), .B(DmP_mant_SFG_SWR[25]), .Y(n5503) );
NAND2X1TS U6327 ( .A(n2713), .B(n1730), .Y(n5508) );
NAND2X1TS U6328 ( .A(n2477), .B(n1726), .Y(n5507) );
NAND2X1TS U6329 ( .A(n5505), .B(n1722), .Y(n5506) );
NAND2X1TS U6330 ( .A(n5730), .B(DmP_mant_SFG_SWR[24]), .Y(n5510) );
NAND2X1TS U6331 ( .A(n5517), .B(n5516), .Y(n5518) );
NAND2X1TS U6332 ( .A(n5520), .B(n6080), .Y(n5524) );
INVX2TS U6333 ( .A(n5521), .Y(n5522) );
AOI21X1TS U6334 ( .A0(add_x_6_n483), .A1(n6080), .B0(n5522), .Y(n5523) );
NAND2X1TS U6335 ( .A(n6065), .B(n2331), .Y(n5526) );
AOI22X1TS U6336 ( .A0(n5699), .A1(Shift_amount_SHT1_EWR[4]), .B0(
shift_value_SHT2_EWR[4]), .B1(n1969), .Y(n5531) );
INVX2TS U6337 ( .A(n5536), .Y(n6926) );
OAI21X1TS U6338 ( .A0(n5540), .A1(n5539), .B0(n5538), .Y(n5541) );
NAND2X2TS U6339 ( .A(n5545), .B(n5544), .Y(n5546) );
NOR2X2TS U6340 ( .A(n5551), .B(n5550), .Y(n5552) );
NOR2X4TS U6341 ( .A(n5553), .B(n5552), .Y(n6979) );
INVX2TS U6342 ( .A(n5679), .Y(n6960) );
INVX2TS U6343 ( .A(n5681), .Y(n6930) );
INVX2TS U6344 ( .A(n5577), .Y(n6958) );
INVX2TS U6345 ( .A(n5578), .Y(n6922) );
NOR2X1TS U6346 ( .A(n5605), .B(n5580), .Y(n5582) );
XOR2X4TS U6347 ( .A(n5584), .B(n5583), .Y(n5585) );
INVX2TS U6348 ( .A(n5586), .Y(n6928) );
INVX2TS U6349 ( .A(n5605), .Y(n5588) );
INVX2TS U6350 ( .A(n5634), .Y(n5587) );
INVX2TS U6351 ( .A(n5594), .Y(n5596) );
NAND2X1TS U6352 ( .A(n5596), .B(n5595), .Y(n5597) );
INVX2TS U6353 ( .A(n5598), .Y(n5623) );
AOI21X4TS U6354 ( .A0(n2506), .A1(n5623), .B0(n6074), .Y(n5600) );
NAND2X1TS U6355 ( .A(n6067), .B(add_x_6_n418), .Y(n5599) );
AOI22X2TS U6356 ( .A0(n5601), .A1(n5626), .B0(Raw_mant_NRM_SWR[19]), .B1(
n5991), .Y(n5602) );
INVX2TS U6357 ( .A(n5604), .Y(n5608) );
NOR2X1TS U6358 ( .A(n5605), .B(n5608), .Y(n5610) );
INVX2TS U6359 ( .A(n5606), .Y(n5607) );
INVX2TS U6360 ( .A(n5615), .Y(n6956) );
NAND2X1TS U6361 ( .A(n2858), .B(n5620), .Y(n5621) );
NAND2X1TS U6362 ( .A(n5623), .B(add_x_6_n423), .Y(n5624) );
XNOR2X1TS U6363 ( .A(n2439), .B(n5624), .Y(n5627) );
AOI22X1TS U6364 ( .A0(n5627), .A1(n5626), .B0(Raw_mant_NRM_SWR[18]), .B1(
n5991), .Y(n5628) );
NOR3X1TS U6365 ( .A(n5642), .B(n2658), .C(n5683), .Y(n5643) );
OAI22X1TS U6366 ( .A0(n5643), .A1(n5853), .B0(n5779), .B1(n6118), .Y(n1210)
);
NAND2X2TS U6367 ( .A(n5648), .B(n5727), .Y(n5649) );
NAND2X1TS U6368 ( .A(n2017), .B(n6514), .Y(n5664) );
NAND4X2TS U6369 ( .A(n5665), .B(n5664), .C(n5663), .D(n5662), .Y(n1699) );
AOI22X1TS U6370 ( .A0(n2827), .A1(n1703), .B0(n5720), .B1(n1699), .Y(n5672)
);
NAND2X2TS U6371 ( .A(n5669), .B(n5716), .Y(n5670) );
OAI21X1TS U6372 ( .A0(n5687), .A1(n2341), .B0(n5686), .Y(n5688) );
AND4X4TS U6373 ( .A(n5696), .B(n5695), .C(n5694), .D(n5693), .Y(n5698) );
INVX2TS U6374 ( .A(n5722), .Y(n5708) );
NAND2X2TS U6375 ( .A(n5705), .B(n1970), .Y(n5706) );
OAI22X1TS U6376 ( .A0(n2551), .A1(n5711), .B0(n2494), .B1(n5710), .Y(n5726)
);
AOI22X1TS U6377 ( .A0(n2502), .A1(n1706), .B0(n5720), .B1(n5908), .Y(n5724)
);
NAND2X1TS U6378 ( .A(n5722), .B(n5721), .Y(n5723) );
AOI22X1TS U6379 ( .A0(n5733), .A1(n4050), .B0(n2405), .B1(n5730), .Y(n5731)
);
AND2X4TS U6380 ( .A(n5817), .B(Raw_mant_NRM_SWR[41]), .Y(n5739) );
OAI22X1TS U6381 ( .A0(n5801), .A1(n6112), .B0(n5818), .B1(n6229), .Y(n5738)
);
NOR2X4TS U6382 ( .A(n5739), .B(n5738), .Y(n6856) );
AND2X4TS U6383 ( .A(n5799), .B(Raw_mant_NRM_SWR[33]), .Y(n5741) );
OAI22X1TS U6384 ( .A0(n5801), .A1(n6136), .B0(n5800), .B1(n6231), .Y(n5740)
);
NOR2X4TS U6385 ( .A(n5741), .B(n5740), .Y(n6870) );
INVX2TS U6386 ( .A(n5742), .Y(n5744) );
NAND2X1TS U6387 ( .A(n5744), .B(n5743), .Y(n5751) );
INVX2TS U6388 ( .A(n5751), .Y(n5745) );
XOR2X1TS U6389 ( .A(n5746), .B(n5745), .Y(n5755) );
INVX2TS U6390 ( .A(n5987), .Y(n5747) );
NOR2X1TS U6391 ( .A(n5747), .B(n5981), .Y(n5750) );
INVX2TS U6392 ( .A(n5986), .Y(n5748) );
OAI21X1TS U6393 ( .A0(n5748), .A1(n5981), .B0(n5982), .Y(n5749) );
OAI2BB1X1TS U6394 ( .A0N(n5996), .A1N(n5755), .B0(n5754), .Y(n1260) );
CLKBUFX3TS U6395 ( .A(n6381), .Y(n6385) );
CLKBUFX3TS U6396 ( .A(n6381), .Y(n6384) );
BUFX3TS U6397 ( .A(n6766), .Y(n6762) );
BUFX3TS U6398 ( .A(n6766), .Y(n6764) );
INVX2TS U6399 ( .A(underflow_flag), .Y(n7012) );
NOR2X6TS U6400 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n6205), .Y(n5877) );
INVX2TS U6401 ( .A(n5877), .Y(n5852) );
NOR2X1TS U6402 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n5758) );
NAND2X2TS U6403 ( .A(n5758), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n5759) );
MXI2X1TS U6404 ( .A(beg_OP), .B(n6265), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n5760) );
OAI21X1TS U6405 ( .A0(n5760), .A1(n5877), .B0(n5759), .Y(n1891) );
INVX2TS U6406 ( .A(final_result_ieee[38]), .Y(n6963) );
INVX2TS U6407 ( .A(final_result_ieee[13]), .Y(n6917) );
INVX2TS U6408 ( .A(final_result_ieee[32]), .Y(n6951) );
INVX2TS U6409 ( .A(final_result_ieee[4]), .Y(n6904) );
INVX2TS U6410 ( .A(final_result_ieee[35]), .Y(n6957) );
INVX2TS U6411 ( .A(final_result_ieee[14]), .Y(n6919) );
INVX2TS U6412 ( .A(final_result_ieee[19]), .Y(n6927) );
INVX2TS U6413 ( .A(final_result_ieee[25]), .Y(n6935) );
INVX2TS U6414 ( .A(final_result_ieee[46]), .Y(n6984) );
OAI22X2TS U6415 ( .A0(n2249), .A1(n6613), .B0(n1937), .B1(n6612), .Y(
final_result_ieee[16]) );
INVX2TS U6416 ( .A(final_result_ieee[16]), .Y(n6923) );
INVX2TS U6417 ( .A(final_result_ieee[39]), .Y(n6965) );
INVX2TS U6418 ( .A(final_result_ieee[62]), .Y(n7008) );
OAI22X2TS U6419 ( .A0(n2249), .A1(n6623), .B0(n1937), .B1(n6622), .Y(
final_result_ieee[34]) );
INVX2TS U6420 ( .A(final_result_ieee[34]), .Y(n6955) );
INVX2TS U6421 ( .A(final_result_ieee[11]), .Y(n6913) );
OAI22X2TS U6422 ( .A0(n5762), .A1(n6712), .B0(n2186), .B1(n6711), .Y(
final_result_ieee[2]) );
INVX2TS U6423 ( .A(final_result_ieee[2]), .Y(n6901) );
OAI22X2TS U6424 ( .A0(n5762), .A1(n6680), .B0(n1935), .B1(n6679), .Y(
final_result_ieee[47]) );
INVX2TS U6425 ( .A(final_result_ieee[47]), .Y(n6986) );
OAI22X2TS U6426 ( .A0(n5762), .A1(n6615), .B0(n2251), .B1(n6614), .Y(
final_result_ieee[20]) );
INVX2TS U6427 ( .A(final_result_ieee[20]), .Y(n6929) );
OAI22X2TS U6428 ( .A0(n5762), .A1(n6658), .B0(n1935), .B1(n6657), .Y(
final_result_ieee[12]) );
INVX2TS U6429 ( .A(final_result_ieee[12]), .Y(n6915) );
OAI22X2TS U6430 ( .A0(n5762), .A1(n6668), .B0(n2251), .B1(n6667), .Y(
final_result_ieee[10]) );
INVX2TS U6431 ( .A(final_result_ieee[10]), .Y(n6911) );
INVX2TS U6432 ( .A(final_result_ieee[54]), .Y(n7000) );
INVX2TS U6433 ( .A(final_result_ieee[52]), .Y(n6998) );
INVX2TS U6434 ( .A(final_result_ieee[60]), .Y(n7006) );
AOI2BB2X2TS U6435 ( .B0(n1929), .B1(n6662), .A0N(n5763), .A1N(n6661), .Y(
final_result_ieee[55]) );
INVX2TS U6436 ( .A(final_result_ieee[55]), .Y(n7001) );
AOI2BB2X2TS U6437 ( .B0(n1929), .B1(n6678), .A0N(n5763), .A1N(n6677), .Y(
final_result_ieee[58]) );
INVX2TS U6438 ( .A(final_result_ieee[58]), .Y(n7004) );
INVX2TS U6439 ( .A(final_result_ieee[53]), .Y(n6999) );
AOI2BB2X2TS U6440 ( .B0(n1929), .B1(n6670), .A0N(n5763), .A1N(n6669), .Y(
final_result_ieee[61]) );
INVX2TS U6441 ( .A(final_result_ieee[61]), .Y(n7007) );
AOI2BB2X2TS U6442 ( .B0(n2187), .B1(n6689), .A0N(n5763), .A1N(n6688), .Y(
final_result_ieee[59]) );
INVX2TS U6443 ( .A(final_result_ieee[59]), .Y(n7005) );
AOI2BB2X2TS U6444 ( .B0(n1929), .B1(n6674), .A0N(n5763), .A1N(n6673), .Y(
final_result_ieee[56]) );
INVX2TS U6445 ( .A(final_result_ieee[56]), .Y(n7002) );
INVX2TS U6446 ( .A(final_result_ieee[57]), .Y(n7003) );
OAI22X2TS U6447 ( .A0(n5763), .A1(n6656), .B0(n1935), .B1(n6655), .Y(
final_result_ieee[40]) );
INVX2TS U6448 ( .A(final_result_ieee[40]), .Y(n6967) );
OAI22X2TS U6449 ( .A0(n5763), .A1(n6654), .B0(n1937), .B1(n6653), .Y(
final_result_ieee[37]) );
INVX2TS U6450 ( .A(final_result_ieee[37]), .Y(n6961) );
OAI22X2TS U6451 ( .A0(n6646), .A1(n5762), .B0(n2251), .B1(n6645), .Y(
final_result_ieee[15]) );
INVX2TS U6452 ( .A(final_result_ieee[15]), .Y(n6921) );
OAI22X2TS U6453 ( .A0(n6641), .A1(n5762), .B0(n2251), .B1(n6640), .Y(
final_result_ieee[18]) );
INVX2TS U6454 ( .A(final_result_ieee[18]), .Y(n6925) );
OAI22X2TS U6455 ( .A0(n6652), .A1(n5762), .B0(n1937), .B1(n6651), .Y(
final_result_ieee[36]) );
INVX2TS U6456 ( .A(final_result_ieee[36]), .Y(n6959) );
OAI22X2TS U6457 ( .A0(n6632), .A1(n5762), .B0(n2251), .B1(n6631), .Y(
final_result_ieee[30]) );
INVX2TS U6458 ( .A(final_result_ieee[30]), .Y(n6948) );
NAND3X2TS U6459 ( .A(n5766), .B(n5765), .C(n6634), .Y(final_result_ieee[49])
);
NAND3X2TS U6460 ( .A(n5768), .B(n5767), .C(n6636), .Y(final_result_ieee[45])
);
NAND3X2TS U6461 ( .A(n5770), .B(n5769), .C(n6637), .Y(final_result_ieee[50])
);
NAND3X2TS U6462 ( .A(n5772), .B(n5771), .C(n6633), .Y(final_result_ieee[51])
);
NAND3X2TS U6463 ( .A(n5774), .B(n5773), .C(n6635), .Y(final_result_ieee[44])
);
AND2X2TS U6464 ( .A(n5789), .B(n1912), .Y(n5776) );
OAI22X1TS U6465 ( .A0(n5780), .A1(n6113), .B0(n5800), .B1(n6239), .Y(n5775)
);
NOR2X4TS U6466 ( .A(n5776), .B(n5775), .Y(n6847) );
INVX2TS U6467 ( .A(n6847), .Y(n6829) );
AND2X2TS U6468 ( .A(n5789), .B(Raw_mant_NRM_SWR[48]), .Y(n5778) );
OAI22X1TS U6469 ( .A0(n5780), .A1(n6110), .B0(n5779), .B1(n6238), .Y(n5777)
);
NOR2X4TS U6470 ( .A(n5778), .B(n5777), .Y(n6848) );
INVX2TS U6471 ( .A(n6848), .Y(n6849) );
INVX2TS U6472 ( .A(n6862), .Y(n6863) );
INVX2TS U6473 ( .A(n6890), .Y(n6809) );
OAI22X1TS U6474 ( .A0(n5780), .A1(n6117), .B0(n5779), .B1(n6240), .Y(n5781)
);
NOR2X4TS U6475 ( .A(n5782), .B(n5781), .Y(n6851) );
INVX2TS U6476 ( .A(n6851), .Y(n6794) );
INVX2TS U6477 ( .A(n6833), .Y(n6830) );
AND2X4TS U6478 ( .A(n5817), .B(Raw_mant_NRM_SWR[7]), .Y(n5785) );
OAI22X1TS U6479 ( .A0(n5819), .A1(n6115), .B0(n5818), .B1(n5783), .Y(n5784)
);
NOR2X4TS U6480 ( .A(n5785), .B(n5784), .Y(n6891) );
INVX2TS U6481 ( .A(n6891), .Y(n6824) );
OAI22X1TS U6482 ( .A0(n5819), .A1(n5786), .B0(n5818), .B1(n6225), .Y(n5787)
);
NOR2X4TS U6483 ( .A(n5788), .B(n5787), .Y(n6880) );
INVX2TS U6484 ( .A(n6880), .Y(n6802) );
NAND2X1TS U6485 ( .A(n5853), .B(DmP_mant_SHT1_SW[51]), .Y(n5790) );
NAND2X2TS U6486 ( .A(n5791), .B(n5790), .Y(n5794) );
NOR2X4TS U6487 ( .A(n5794), .B(n5793), .Y(n6836) );
INVX2TS U6488 ( .A(n6836), .Y(n6796) );
AND2X4TS U6489 ( .A(n5817), .B(Raw_mant_NRM_SWR[8]), .Y(n5796) );
OAI22X1TS U6490 ( .A0(n5819), .A1(n6122), .B0(n5818), .B1(n6226), .Y(n5795)
);
NOR2X4TS U6491 ( .A(n5796), .B(n5795), .Y(n6892) );
INVX2TS U6492 ( .A(n6892), .Y(n6893) );
AND2X4TS U6493 ( .A(n5817), .B(Raw_mant_NRM_SWR[16]), .Y(n5798) );
OAI22X1TS U6494 ( .A0(n5819), .A1(n6128), .B0(n5818), .B1(n6227), .Y(n5797)
);
NOR2X4TS U6495 ( .A(n5798), .B(n5797), .Y(n6887) );
INVX2TS U6496 ( .A(n6856), .Y(n6786) );
INVX2TS U6497 ( .A(n6852), .Y(n6828) );
INVX2TS U6498 ( .A(n6846), .Y(n6790) );
INVX2TS U6499 ( .A(n6853), .Y(n6854) );
OAI22X1TS U6500 ( .A0(n5801), .A1(n6123), .B0(n5800), .B1(n6232), .Y(n5802)
);
NOR2X4TS U6501 ( .A(n5803), .B(n5802), .Y(n6843) );
INVX2TS U6502 ( .A(n6843), .Y(n6844) );
INVX2TS U6503 ( .A(n6837), .Y(n6826) );
INVX2TS U6504 ( .A(n6838), .Y(n6839) );
OAI22X1TS U6505 ( .A0(n5804), .A1(n6131), .B0(n5861), .B1(n6209), .Y(n5806)
);
NOR2X4TS U6506 ( .A(n5806), .B(n5805), .Y(n6875) );
INVX2TS U6507 ( .A(n6875), .Y(n6807) );
OAI22X1TS U6508 ( .A0(n5825), .A1(n5807), .B0(n5824), .B1(n6221), .Y(n5808)
);
NOR2X4TS U6509 ( .A(n5809), .B(n5808), .Y(n6876) );
INVX2TS U6510 ( .A(n6876), .Y(n6822) );
INVX2TS U6511 ( .A(n6882), .Y(n6883) );
OAI22X1TS U6512 ( .A0(n5819), .A1(n6137), .B0(n5818), .B1(n6224), .Y(n5810)
);
NOR2X4TS U6513 ( .A(n5811), .B(n5810), .Y(n6881) );
INVX2TS U6514 ( .A(n6881), .Y(n6823) );
AND2X4TS U6515 ( .A(n5814), .B(n2432), .Y(n5813) );
OAI22X1TS U6516 ( .A0(n5825), .A1(n6111), .B0(n5824), .B1(n6216), .Y(n5812)
);
NOR2X4TS U6517 ( .A(n5813), .B(n5812), .Y(n6866) );
INVX2TS U6518 ( .A(n6866), .Y(n6819) );
OAI22X1TS U6519 ( .A0(n5819), .A1(n6713), .B0(n5818), .B1(n6222), .Y(n5815)
);
NOR2X4TS U6520 ( .A(n5816), .B(n5815), .Y(n6896) );
INVX2TS U6521 ( .A(n6896), .Y(n6800) );
INVX2TS U6522 ( .A(n6871), .Y(n6820) );
INVX2TS U6523 ( .A(n6835), .Y(n6785) );
INVX2TS U6524 ( .A(n6877), .Y(n6878) );
OAI22X1TS U6525 ( .A0(n5819), .A1(n6129), .B0(n5818), .B1(n6228), .Y(n5820)
);
NOR2X4TS U6526 ( .A(n5821), .B(n5820), .Y(n6886) );
INVX2TS U6527 ( .A(n6886), .Y(n6825) );
INVX2TS U6528 ( .A(n6841), .Y(n6792) );
INVX2TS U6529 ( .A(n6885), .Y(n6804) );
INVX2TS U6530 ( .A(n6861), .Y(n6818) );
OAI22X1TS U6531 ( .A0(n5825), .A1(n6126), .B0(n5824), .B1(n6217), .Y(n5822)
);
INVX2TS U6532 ( .A(n6872), .Y(n6873) );
OAI22X1TS U6533 ( .A0(n5825), .A1(n6089), .B0(n5824), .B1(n6213), .Y(n5826)
);
NAND2X2TS U6534 ( .A(n5847), .B(n2161), .Y(n5828) );
NAND2X2TS U6535 ( .A(n5848), .B(n2162), .Y(n5827) );
NAND3X2TS U6536 ( .A(n5828), .B(n5827), .C(n6702), .Y(final_result_ieee[17])
);
NAND2X2TS U6537 ( .A(n5831), .B(n2164), .Y(n5830) );
NAND3X2TS U6538 ( .A(n5830), .B(n5829), .C(n6708), .Y(final_result_ieee[42])
);
NAND2X2TS U6539 ( .A(n5831), .B(n2169), .Y(n5834) );
NAND3X2TS U6540 ( .A(n5834), .B(n5833), .C(n6694), .Y(final_result_ieee[43])
);
NAND2X2TS U6541 ( .A(n5847), .B(n2174), .Y(n5836) );
NAND2X2TS U6542 ( .A(n5848), .B(n2183), .Y(n5835) );
NAND3X2TS U6543 ( .A(n5836), .B(n5835), .C(n6693), .Y(final_result_ieee[21])
);
NAND2X2TS U6544 ( .A(n5847), .B(n2177), .Y(n5838) );
NAND3X2TS U6545 ( .A(n5838), .B(n5837), .C(n6691), .Y(final_result_ieee[0])
);
NAND2X2TS U6546 ( .A(n5847), .B(n2176), .Y(n5840) );
NAND3X2TS U6547 ( .A(n5840), .B(n5839), .C(n6685), .Y(final_result_ieee[5])
);
NAND2X2TS U6548 ( .A(n5847), .B(n2168), .Y(n5842) );
NAND2X2TS U6549 ( .A(n5848), .B(n2169), .Y(n5841) );
NAND3X2TS U6550 ( .A(n5842), .B(n5841), .C(n6683), .Y(final_result_ieee[7])
);
NAND2X2TS U6551 ( .A(n5847), .B(n2167), .Y(n5844) );
NAND3X2TS U6552 ( .A(n5844), .B(n5843), .C(n6687), .Y(final_result_ieee[8])
);
NAND2X2TS U6553 ( .A(n5847), .B(n2173), .Y(n5846) );
NAND3X2TS U6554 ( .A(n5846), .B(n5845), .C(n6690), .Y(final_result_ieee[1])
);
NAND2X2TS U6555 ( .A(n5847), .B(n2182), .Y(n5850) );
NAND3X2TS U6556 ( .A(n5850), .B(n5849), .C(n6684), .Y(final_result_ieee[6])
);
MXI2X1TS U6557 ( .A(n6187), .B(n2406), .S0(n5851), .Y(n1269) );
MXI2X1TS U6558 ( .A(n5852), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
INVX6TS U6559 ( .A(n5853), .Y(n5856) );
CLKMX2X2TS U6560 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n5856),
.Y(n1271) );
CLKMX2X2TS U6561 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n5856),
.Y(n1404) );
CLKMX2X2TS U6562 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n5856),
.Y(n1414) );
CLKMX2X2TS U6563 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n5856),
.Y(n1419) );
CLKMX2X2TS U6564 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n5856),
.Y(n1409) );
CLKMX2X2TS U6565 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n5856),
.Y(n1424) );
CLKMX2X2TS U6566 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n5890), .Y(
n1274) );
CLKMX2X2TS U6567 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n5890), .Y(
n1285) );
CLKMX2X2TS U6568 ( .A(DMP_SHT2_EWSW[62]), .B(DMP_SHT1_EWSW[62]), .S0(n5890),
.Y(n1402) );
INVX8TS U6569 ( .A(n5854), .Y(n5855) );
CLKMX2X2TS U6570 ( .A(DMP_SHT2_EWSW[42]), .B(DMP_SHT1_EWSW[42]), .S0(n5855),
.Y(n1482) );
CLKMX2X2TS U6571 ( .A(DMP_SHT2_EWSW[43]), .B(DMP_SHT1_EWSW[43]), .S0(n5855),
.Y(n1479) );
CLKMX2X2TS U6572 ( .A(DMP_SHT2_EWSW[40]), .B(DMP_SHT1_EWSW[40]), .S0(n5855),
.Y(n1488) );
CLKMX2X2TS U6573 ( .A(DMP_SHT2_EWSW[44]), .B(DMP_SHT1_EWSW[44]), .S0(n5855),
.Y(n1476) );
CLKMX2X2TS U6574 ( .A(DMP_SHT2_EWSW[45]), .B(DMP_SHT1_EWSW[45]), .S0(n5855),
.Y(n1473) );
CLKMX2X2TS U6575 ( .A(DMP_SHT2_EWSW[49]), .B(DMP_SHT1_EWSW[49]), .S0(n5855),
.Y(n1461) );
CLKMX2X2TS U6576 ( .A(DMP_SHT2_EWSW[39]), .B(DMP_SHT1_EWSW[39]), .S0(n5855),
.Y(n1491) );
CLKMX2X2TS U6577 ( .A(DMP_SHT2_EWSW[46]), .B(DMP_SHT1_EWSW[46]), .S0(n5855),
.Y(n1470) );
CLKMX2X2TS U6578 ( .A(DMP_SHT2_EWSW[47]), .B(DMP_SHT1_EWSW[47]), .S0(n5855),
.Y(n1467) );
CLKMX2X2TS U6579 ( .A(DMP_SHT2_EWSW[41]), .B(DMP_SHT1_EWSW[41]), .S0(n5855),
.Y(n1485) );
CLKMX2X2TS U6580 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
n5856), .Y(n1399) );
INVX8TS U6581 ( .A(n5854), .Y(n5858) );
CLKMX2X2TS U6582 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n5858),
.Y(n1560) );
CLKMX2X2TS U6583 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n5858),
.Y(n1581) );
INVX8TS U6584 ( .A(n5854), .Y(n5859) );
CLKMX2X2TS U6585 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n5859),
.Y(n1542) );
CLKMX2X2TS U6586 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n5858),
.Y(n1572) );
INVX8TS U6587 ( .A(n5854), .Y(n5857) );
CLKMX2X2TS U6588 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n5857),
.Y(n1593) );
CLKMX2X2TS U6589 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n5858),
.Y(n1554) );
CLKMX2X2TS U6590 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n5857),
.Y(n1596) );
CLKMX2X2TS U6591 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n5858),
.Y(n1551) );
CLKMX2X2TS U6592 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(n5857), .Y(n1279)
);
CLKMX2X2TS U6593 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n5859),
.Y(n1545) );
CLKMX2X2TS U6594 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n5858),
.Y(n1578) );
CLKMX2X2TS U6595 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SHT1_EWSW[25]), .S0(n5859),
.Y(n1533) );
CLKMX2X2TS U6596 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n5857),
.Y(n1587) );
CLKMX2X2TS U6597 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n5859),
.Y(n1548) );
CLKMX2X2TS U6598 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n5859),
.Y(n1536) );
CLKMX2X2TS U6599 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n5857),
.Y(n1599) );
CLKMX2X2TS U6600 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n5858),
.Y(n1557) );
CLKMX2X2TS U6601 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n5857),
.Y(n1605) );
CLKMX2X2TS U6602 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n5858),
.Y(n1569) );
CLKMX2X2TS U6603 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n5859),
.Y(n1524) );
CLKMX2X2TS U6604 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n5859),
.Y(n1530) );
CLKMX2X2TS U6605 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n5859),
.Y(n1575) );
CLKMX2X2TS U6606 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n5857),
.Y(n1608) );
CLKMX2X2TS U6607 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n5857),
.Y(n1590) );
CLKMX2X2TS U6608 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n5857),
.Y(n1584) );
CLKMX2X2TS U6609 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n5857),
.Y(n1602) );
CLKMX2X2TS U6610 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n5858),
.Y(n1563) );
CLKMX2X2TS U6611 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n5859),
.Y(n1527) );
CLKMX2X2TS U6612 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n5858),
.Y(n1566) );
CLKMX2X2TS U6613 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n5859),
.Y(n1539) );
INVX8TS U6614 ( .A(n6266), .Y(n5860) );
CLKMX2X2TS U6615 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SHT1_EWSW[31]), .S0(n5860),
.Y(n1515) );
CLKMX2X2TS U6616 ( .A(DMP_SHT2_EWSW[38]), .B(DMP_SHT1_EWSW[38]), .S0(n5860),
.Y(n1494) );
CLKMX2X2TS U6617 ( .A(DMP_SHT2_EWSW[35]), .B(DMP_SHT1_EWSW[35]), .S0(n5860),
.Y(n1503) );
CLKMX2X2TS U6618 ( .A(DMP_SHT2_EWSW[36]), .B(DMP_SHT1_EWSW[36]), .S0(n5860),
.Y(n1500) );
CLKMX2X2TS U6619 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SHT1_EWSW[34]), .S0(n5860),
.Y(n1506) );
CLKMX2X2TS U6620 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n5860),
.Y(n1518) );
CLKMX2X2TS U6621 ( .A(DMP_SHT2_EWSW[37]), .B(DMP_SHT1_EWSW[37]), .S0(n5860),
.Y(n1497) );
CLKMX2X2TS U6622 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n5860),
.Y(n1521) );
CLKMX2X2TS U6623 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SHT1_EWSW[32]), .S0(n5860),
.Y(n1512) );
CLKMX2X2TS U6624 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SHT1_EWSW[33]), .S0(n5860),
.Y(n1509) );
CLKMX2X2TS U6625 ( .A(DMP_SHT2_EWSW[60]), .B(DMP_SHT1_EWSW[60]), .S0(busy),
.Y(n1412) );
CLKMX2X2TS U6626 ( .A(DMP_SHT2_EWSW[59]), .B(DMP_SHT1_EWSW[59]), .S0(busy),
.Y(n1417) );
CLKMX2X2TS U6627 ( .A(DMP_SHT2_EWSW[48]), .B(DMP_SHT1_EWSW[48]), .S0(busy),
.Y(n1464) );
CLKMX2X2TS U6628 ( .A(DMP_SHT2_EWSW[50]), .B(DMP_SHT1_EWSW[50]), .S0(busy),
.Y(n1458) );
CLKMX2X2TS U6629 ( .A(DMP_SHT2_EWSW[51]), .B(DMP_SHT1_EWSW[51]), .S0(busy),
.Y(n1455) );
CLKMX2X2TS U6630 ( .A(DMP_SHT2_EWSW[58]), .B(DMP_SHT1_EWSW[58]), .S0(busy),
.Y(n1422) );
CLKMX2X2TS U6631 ( .A(DMP_SHT2_EWSW[61]), .B(DMP_SHT1_EWSW[61]), .S0(busy),
.Y(n1407) );
CLKMX2X2TS U6632 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n5861),
.Y(n1282) );
CLKMX2X2TS U6633 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n5861),
.Y(n1449) );
CLKMX2X2TS U6634 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n5861),
.Y(n1434) );
CLKMX2X2TS U6635 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n5861),
.Y(n1439) );
CLKMX2X2TS U6636 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n5861),
.Y(n1444) );
MXI2X1TS U6637 ( .A(n5886), .B(n6338), .S0(n5862), .Y(n1428) );
MXI2X1TS U6638 ( .A(n6191), .B(n6342), .S0(n5862), .Y(n1448) );
MXI2X1TS U6639 ( .A(n6190), .B(n6341), .S0(n5862), .Y(n1443) );
MXI2X1TS U6640 ( .A(n6189), .B(n6340), .S0(n5862), .Y(n1438) );
MXI2X1TS U6641 ( .A(n6188), .B(n6339), .S0(n5862), .Y(n1433) );
MXI2X1TS U6642 ( .A(n6192), .B(n6343), .S0(n5862), .Y(n1453) );
CLKMX2X2TS U6643 ( .A(DmP_mant_SHT1_SW[51]), .B(DmP_EXP_EWSW[51]), .S0(n5862), .Y(n1295) );
CLKMX2X2TS U6644 ( .A(SIGN_FLAG_SHT1), .B(SIGN_FLAG_EXP), .S0(n5862), .Y(
n1275) );
CLKMX2X2TS U6645 ( .A(DmP_mant_SHT1_SW[48]), .B(DmP_EXP_EWSW[48]), .S0(n5862), .Y(n1301) );
CLKMX2X2TS U6646 ( .A(DMP_SHT1_EWSW[62]), .B(DMP_EXP_EWSW[62]), .S0(n5862),
.Y(n1403) );
BUFX8TS U6647 ( .A(n6774), .Y(n5865) );
CLKMX2X2TS U6648 ( .A(DMP_SHT1_EWSW[35]), .B(DMP_EXP_EWSW[35]), .S0(n5863),
.Y(n1504) );
CLKMX2X2TS U6649 ( .A(DMP_SHT1_EWSW[34]), .B(DMP_EXP_EWSW[34]), .S0(n5863),
.Y(n1507) );
CLKMX2X2TS U6650 ( .A(DMP_SHT1_EWSW[36]), .B(DMP_EXP_EWSW[36]), .S0(n5863),
.Y(n1501) );
CLKMX2X2TS U6651 ( .A(DMP_SHT1_EWSW[40]), .B(DMP_EXP_EWSW[40]), .S0(n5864),
.Y(n1489) );
CLKMX2X2TS U6652 ( .A(DMP_SHT1_EWSW[37]), .B(DMP_EXP_EWSW[37]), .S0(n5863),
.Y(n1498) );
CLKMX2X2TS U6653 ( .A(DMP_SHT1_EWSW[39]), .B(DMP_EXP_EWSW[39]), .S0(n5864),
.Y(n1492) );
CLKMX2X2TS U6654 ( .A(DMP_SHT1_EWSW[38]), .B(DMP_EXP_EWSW[38]), .S0(n5864),
.Y(n1495) );
CLKMX2X2TS U6655 ( .A(DMP_SHT1_EWSW[31]), .B(DMP_EXP_EWSW[31]), .S0(n5863),
.Y(n1516) );
CLKMX2X2TS U6656 ( .A(DMP_SHT1_EWSW[42]), .B(DMP_EXP_EWSW[42]), .S0(n5864),
.Y(n1483) );
CLKMX2X2TS U6657 ( .A(DMP_SHT1_EWSW[30]), .B(DMP_EXP_EWSW[30]), .S0(n5863),
.Y(n1519) );
CLKMX2X2TS U6658 ( .A(DMP_SHT1_EWSW[29]), .B(DMP_EXP_EWSW[29]), .S0(n5863),
.Y(n1522) );
CLKMX2X2TS U6659 ( .A(DMP_SHT1_EWSW[28]), .B(DMP_EXP_EWSW[28]), .S0(n5863),
.Y(n1525) );
CLKMX2X2TS U6660 ( .A(DMP_SHT1_EWSW[32]), .B(DMP_EXP_EWSW[32]), .S0(n5863),
.Y(n1513) );
CLKMX2X2TS U6661 ( .A(DMP_SHT1_EWSW[33]), .B(DMP_EXP_EWSW[33]), .S0(n5863),
.Y(n1510) );
CLKMX2X2TS U6662 ( .A(DMP_SHT1_EWSW[46]), .B(DMP_EXP_EWSW[46]), .S0(n5864),
.Y(n1471) );
CLKMX2X2TS U6663 ( .A(DMP_SHT1_EWSW[44]), .B(DMP_EXP_EWSW[44]), .S0(n5864),
.Y(n1477) );
CLKMX2X2TS U6664 ( .A(DMP_SHT1_EWSW[45]), .B(DMP_EXP_EWSW[45]), .S0(n5864),
.Y(n1474) );
CLKMX2X2TS U6665 ( .A(DMP_SHT1_EWSW[43]), .B(n2146), .S0(n5864), .Y(n1480)
);
CLKMX2X2TS U6666 ( .A(DMP_SHT1_EWSW[41]), .B(n2141), .S0(n5864), .Y(n1486)
);
CLKMX2X2TS U6667 ( .A(DMP_SHT1_EWSW[47]), .B(DMP_EXP_EWSW[47]), .S0(n5864),
.Y(n1468) );
INVX8TS U6668 ( .A(n5865), .Y(n5866) );
CLKMX2X2TS U6669 ( .A(DMP_SHT1_EWSW[60]), .B(DMP_EXP_EWSW[60]), .S0(n5866),
.Y(n1413) );
CLKMX2X2TS U6670 ( .A(DMP_SHT1_EWSW[48]), .B(DMP_EXP_EWSW[48]), .S0(n5866),
.Y(n1465) );
CLKMX2X2TS U6671 ( .A(DMP_SHT1_EWSW[58]), .B(DMP_EXP_EWSW[58]), .S0(n5866),
.Y(n1423) );
CLKMX2X2TS U6672 ( .A(DMP_SHT1_EWSW[59]), .B(DMP_EXP_EWSW[59]), .S0(n5866),
.Y(n1418) );
CLKMX2X2TS U6673 ( .A(DMP_SHT1_EWSW[49]), .B(DMP_EXP_EWSW[49]), .S0(n5866),
.Y(n1462) );
CLKMX2X2TS U6674 ( .A(DMP_SHT1_EWSW[51]), .B(DMP_EXP_EWSW[51]), .S0(n5866),
.Y(n1456) );
CLKMX2X2TS U6675 ( .A(DMP_SHT1_EWSW[50]), .B(DMP_EXP_EWSW[50]), .S0(n5866),
.Y(n1459) );
CLKMX2X2TS U6676 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n5866), .Y(
n1286) );
CLKMX2X2TS U6677 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n5866), .Y(n1280)
);
CLKMX2X2TS U6678 ( .A(DmP_mant_SHT1_SW[41]), .B(DmP_EXP_EWSW[41]), .S0(n5867), .Y(n1315) );
CLKMX2X2TS U6679 ( .A(DMP_SHT1_EWSW[4]), .B(n2142), .S0(n3340), .Y(n1597) );
CLKMX2X2TS U6680 ( .A(DmP_mant_SHT1_SW[0]), .B(DmP_EXP_EWSW[0]), .S0(n5872),
.Y(n1397) );
CLKMX2X2TS U6681 ( .A(DMP_SHT1_EWSW[5]), .B(DMP_EXP_EWSW[5]), .S0(n3340),
.Y(n1594) );
CLKMX2X2TS U6682 ( .A(DMP_SHT1_EWSW[0]), .B(DMP_EXP_EWSW[0]), .S0(n3340),
.Y(n1609) );
CLKMX2X2TS U6683 ( .A(DMP_SHT1_EWSW[2]), .B(DMP_EXP_EWSW[2]), .S0(n3340),
.Y(n1603) );
CLKMX2X2TS U6684 ( .A(DMP_SHT1_EWSW[3]), .B(DMP_EXP_EWSW[3]), .S0(n3340),
.Y(n1600) );
CLKMX2X2TS U6685 ( .A(DMP_SHT1_EWSW[1]), .B(DMP_EXP_EWSW[1]), .S0(n3340),
.Y(n1606) );
CLKMX2X2TS U6686 ( .A(DMP_SHT1_EWSW[6]), .B(DMP_EXP_EWSW[6]), .S0(n3340),
.Y(n1591) );
CLKMX2X2TS U6687 ( .A(DMP_SHT1_EWSW[7]), .B(DMP_EXP_EWSW[7]), .S0(n3340),
.Y(n1588) );
CLKMX2X2TS U6688 ( .A(DMP_SHT1_EWSW[8]), .B(DMP_EXP_EWSW[8]), .S0(n5868),
.Y(n1585) );
CLKMX2X2TS U6689 ( .A(DMP_SHT1_EWSW[9]), .B(n2143), .S0(n5868), .Y(n1582) );
CLKMX2X2TS U6690 ( .A(DmP_mant_SHT1_SW[30]), .B(DmP_EXP_EWSW[30]), .S0(n5867), .Y(n1337) );
CLKMX2X2TS U6691 ( .A(DmP_mant_SHT1_SW[29]), .B(DmP_EXP_EWSW[29]), .S0(n5872), .Y(n1339) );
CLKMX2X2TS U6692 ( .A(DMP_SHT1_EWSW[10]), .B(n2144), .S0(n5868), .Y(n1579)
);
CLKMX2X2TS U6693 ( .A(DmP_mant_SHT1_SW[28]), .B(DmP_EXP_EWSW[28]), .S0(n5872), .Y(n1341) );
CLKMX2X2TS U6694 ( .A(DmP_mant_SHT1_SW[27]), .B(DmP_EXP_EWSW[27]), .S0(n5872), .Y(n1343) );
CLKMX2X2TS U6695 ( .A(DmP_mant_SHT1_SW[26]), .B(DmP_EXP_EWSW[26]), .S0(n5867), .Y(n1345) );
CLKMX2X2TS U6696 ( .A(DmP_mant_SHT1_SW[25]), .B(DmP_EXP_EWSW[25]), .S0(n5867), .Y(n1347) );
CLKMX2X2TS U6697 ( .A(DMP_SHT1_EWSW[11]), .B(n2145), .S0(n5868), .Y(n1576)
);
CLKMX2X2TS U6698 ( .A(DmP_mant_SHT1_SW[24]), .B(DmP_EXP_EWSW[24]), .S0(n5867), .Y(n1349) );
CLKMX2X2TS U6699 ( .A(DMP_SHT1_EWSW[12]), .B(DMP_EXP_EWSW[12]), .S0(n5868),
.Y(n1573) );
CLKMX2X2TS U6700 ( .A(DmP_mant_SHT1_SW[23]), .B(DmP_EXP_EWSW[23]), .S0(n5867), .Y(n1351) );
CLKMX2X2TS U6701 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n5872), .Y(n1353) );
CLKMX2X2TS U6702 ( .A(DMP_SHT1_EWSW[13]), .B(DMP_EXP_EWSW[13]), .S0(n5868),
.Y(n1570) );
CLKMX2X2TS U6703 ( .A(DmP_mant_SHT1_SW[21]), .B(DmP_EXP_EWSW[21]), .S0(n5872), .Y(n1355) );
CLKMX2X2TS U6704 ( .A(DMP_SHT1_EWSW[14]), .B(DMP_EXP_EWSW[14]), .S0(n5868),
.Y(n1567) );
CLKMX2X2TS U6705 ( .A(DmP_mant_SHT1_SW[20]), .B(DmP_EXP_EWSW[20]), .S0(n5872), .Y(n1357) );
CLKMX2X2TS U6706 ( .A(DMP_SHT1_EWSW[15]), .B(DMP_EXP_EWSW[15]), .S0(n5868),
.Y(n1564) );
CLKMX2X2TS U6707 ( .A(DmP_mant_SHT1_SW[18]), .B(DmP_EXP_EWSW[18]), .S0(n5867), .Y(n1361) );
CLKMX2X2TS U6708 ( .A(DmP_mant_SHT1_SW[17]), .B(DmP_EXP_EWSW[17]), .S0(n5867), .Y(n1363) );
CLKMX2X2TS U6709 ( .A(DMP_SHT1_EWSW[16]), .B(DMP_EXP_EWSW[16]), .S0(n5868),
.Y(n1561) );
CLKMX2X2TS U6710 ( .A(DmP_mant_SHT1_SW[16]), .B(DmP_EXP_EWSW[16]), .S0(n5867), .Y(n1365) );
CLKMX2X2TS U6711 ( .A(DmP_mant_SHT1_SW[15]), .B(DmP_EXP_EWSW[15]), .S0(n5867), .Y(n1367) );
CLKMX2X2TS U6712 ( .A(DMP_SHT1_EWSW[17]), .B(DMP_EXP_EWSW[17]), .S0(n5868),
.Y(n1558) );
CLKMX2X2TS U6713 ( .A(DmP_mant_SHT1_SW[14]), .B(DmP_EXP_EWSW[14]), .S0(n5870), .Y(n1369) );
CLKMX2X2TS U6714 ( .A(DmP_mant_SHT1_SW[13]), .B(DmP_EXP_EWSW[13]), .S0(n5870), .Y(n1371) );
CLKMX2X2TS U6715 ( .A(DMP_SHT1_EWSW[18]), .B(DMP_EXP_EWSW[18]), .S0(n5871),
.Y(n1555) );
CLKMX2X2TS U6716 ( .A(DMP_SHT1_EWSW[19]), .B(DMP_EXP_EWSW[19]), .S0(n5871),
.Y(n1552) );
CLKMX2X2TS U6717 ( .A(DMP_SHT1_EWSW[20]), .B(DMP_EXP_EWSW[20]), .S0(n5871),
.Y(n1549) );
CLKMX2X2TS U6718 ( .A(DmP_mant_SHT1_SW[10]), .B(DmP_EXP_EWSW[10]), .S0(n5870), .Y(n1377) );
CLKMX2X2TS U6719 ( .A(DmP_mant_SHT1_SW[9]), .B(DmP_EXP_EWSW[9]), .S0(n5870),
.Y(n1379) );
CLKMX2X2TS U6720 ( .A(DMP_SHT1_EWSW[21]), .B(DMP_EXP_EWSW[21]), .S0(n5871),
.Y(n1546) );
CLKMX2X2TS U6721 ( .A(DmP_mant_SHT1_SW[8]), .B(DmP_EXP_EWSW[8]), .S0(n5870),
.Y(n1381) );
CLKMX2X2TS U6722 ( .A(DMP_SHT1_EWSW[22]), .B(DMP_EXP_EWSW[22]), .S0(n5871),
.Y(n1543) );
CLKMX2X2TS U6723 ( .A(DmP_mant_SHT1_SW[7]), .B(DmP_EXP_EWSW[7]), .S0(n5870),
.Y(n1383) );
CLKMX2X2TS U6724 ( .A(DmP_mant_SHT1_SW[6]), .B(DmP_EXP_EWSW[6]), .S0(n5870),
.Y(n1385) );
CLKMX2X2TS U6725 ( .A(DMP_SHT1_EWSW[23]), .B(DMP_EXP_EWSW[23]), .S0(n5871),
.Y(n1540) );
CLKMX2X2TS U6726 ( .A(DMP_SHT1_EWSW[24]), .B(DMP_EXP_EWSW[24]), .S0(n5871),
.Y(n1537) );
CLKMX2X2TS U6727 ( .A(DmP_mant_SHT1_SW[4]), .B(DmP_EXP_EWSW[4]), .S0(n5870),
.Y(n1389) );
CLKMX2X2TS U6728 ( .A(DMP_SHT1_EWSW[25]), .B(DMP_EXP_EWSW[25]), .S0(n5871),
.Y(n1534) );
CLKMX2X2TS U6729 ( .A(DmP_mant_SHT1_SW[3]), .B(n2411), .S0(n5870), .Y(n1391)
);
CLKMX2X2TS U6730 ( .A(DMP_SHT1_EWSW[26]), .B(DMP_EXP_EWSW[26]), .S0(n5871),
.Y(n1531) );
CLKMX2X2TS U6731 ( .A(DmP_mant_SHT1_SW[2]), .B(DmP_EXP_EWSW[2]), .S0(n5872),
.Y(n1393) );
CLKMX2X2TS U6732 ( .A(DMP_SHT1_EWSW[27]), .B(n2465), .S0(n5871), .Y(n1528)
);
CLKMX2X2TS U6733 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n5872),
.Y(n1395) );
CLKMX2X2TS U6734 ( .A(DmP_mant_SHT1_SW[19]), .B(DmP_EXP_EWSW[19]), .S0(n5872), .Y(n1359) );
CLKMX2X2TS U6735 ( .A(DmP_mant_SHT1_SW[40]), .B(DmP_EXP_EWSW[40]), .S0(n5874), .Y(n1317) );
CLKMX2X2TS U6736 ( .A(DmP_mant_SHT1_SW[32]), .B(n2412), .S0(n5874), .Y(n1333) );
CLKMX2X2TS U6737 ( .A(DmP_mant_SHT1_SW[37]), .B(n2413), .S0(n5873), .Y(n1323) );
CLKMX2X2TS U6738 ( .A(DmP_mant_SHT1_SW[36]), .B(DmP_EXP_EWSW[36]), .S0(n5873), .Y(n1325) );
CLKMX2X2TS U6739 ( .A(DmP_mant_SHT1_SW[35]), .B(DmP_EXP_EWSW[35]), .S0(n5873), .Y(n1327) );
CLKMX2X2TS U6740 ( .A(DmP_mant_SHT1_SW[34]), .B(DmP_EXP_EWSW[34]), .S0(n5874), .Y(n1329) );
CLKMX2X2TS U6741 ( .A(DmP_mant_SHT1_SW[38]), .B(DmP_EXP_EWSW[38]), .S0(n5874), .Y(n1321) );
CLKMX2X2TS U6742 ( .A(DmP_mant_SHT1_SW[33]), .B(DmP_EXP_EWSW[33]), .S0(n5874), .Y(n1331) );
CLKMX2X2TS U6743 ( .A(DmP_mant_SHT1_SW[42]), .B(DmP_EXP_EWSW[42]), .S0(n5874), .Y(n1313) );
CLKMX2X2TS U6744 ( .A(DmP_mant_SHT1_SW[43]), .B(DmP_EXP_EWSW[43]), .S0(n5873), .Y(n1311) );
CLKMX2X2TS U6745 ( .A(DmP_mant_SHT1_SW[31]), .B(DmP_EXP_EWSW[31]), .S0(n5874), .Y(n1335) );
CLKMX2X2TS U6746 ( .A(DmP_mant_SHT1_SW[46]), .B(DmP_EXP_EWSW[46]), .S0(n5873), .Y(n1305) );
CLKMX2X2TS U6747 ( .A(DmP_mant_SHT1_SW[44]), .B(DmP_EXP_EWSW[44]), .S0(n5873), .Y(n1309) );
CLKMX2X2TS U6748 ( .A(DmP_mant_SHT1_SW[45]), .B(DmP_EXP_EWSW[45]), .S0(n5873), .Y(n1307) );
CLKMX2X2TS U6749 ( .A(DmP_mant_SHT1_SW[11]), .B(DmP_EXP_EWSW[11]), .S0(n5874), .Y(n1375) );
CLKMX2X2TS U6750 ( .A(DmP_mant_SHT1_SW[47]), .B(DmP_EXP_EWSW[47]), .S0(n5873), .Y(n1303) );
CLKMX2X2TS U6751 ( .A(DmP_mant_SHT1_SW[49]), .B(DmP_EXP_EWSW[49]), .S0(n5873), .Y(n1299) );
CLKMX2X2TS U6752 ( .A(DmP_mant_SHT1_SW[39]), .B(DmP_EXP_EWSW[39]), .S0(n5874), .Y(n1319) );
CLKMX2X2TS U6753 ( .A(DmP_mant_SHT1_SW[12]), .B(n2410), .S0(n5874), .Y(n1373) );
MXI2X1TS U6754 ( .A(n6141), .B(n6309), .S0(n2607), .Y(n1421) );
MXI2X1TS U6755 ( .A(n5875), .B(n6306), .S0(n2507), .Y(n1406) );
NAND2X1TS U6756 ( .A(n6716), .B(n5876), .Y(n6817) );
MXI2X4TS U6757 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n5877), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n5891) );
CLKINVX1TS U6758 ( .A(n5891), .Y(n5879) );
MXI2X1TS U6759 ( .A(n5879), .B(n5878), .S0(n5882), .Y(n1890) );
MXI2X1TS U6760 ( .A(n5881), .B(n5958), .S0(n5882), .Y(n1886) );
MXI2X1TS U6761 ( .A(n5958), .B(n5880), .S0(n5882), .Y(n1885) );
MXI2X1TS U6762 ( .A(n5880), .B(n6772), .S0(n5882), .Y(n1884) );
MXI2X1TS U6763 ( .A(n5854), .B(n5881), .S0(n5882), .Y(n1887) );
MXI2X1TS U6764 ( .A(n6157), .B(n6269), .S0(n5883), .Y(n1499) );
MXI2X1TS U6765 ( .A(n6144), .B(n6294), .S0(n2687), .Y(n1460) );
MXI2X1TS U6766 ( .A(n6147), .B(n6293), .S0(n2687), .Y(n1469) );
MXI2X1TS U6767 ( .A(n6156), .B(n6283), .S0(n5883), .Y(n1496) );
MXI2X1TS U6768 ( .A(n6154), .B(n6282), .S0(n2687), .Y(n1490) );
MXI2X1TS U6769 ( .A(n6149), .B(n6289), .S0(n2687), .Y(n1475) );
MXI2X1TS U6770 ( .A(n6155), .B(n6271), .S0(n2687), .Y(n1493) );
MXI2X1TS U6771 ( .A(n6151), .B(n6278), .S0(n2687), .Y(n1481) );
MXI2X1TS U6772 ( .A(n2555), .B(n5854), .S0(n5882), .Y(n1888) );
MXI2X1TS U6773 ( .A(n6167), .B(n6279), .S0(n5885), .Y(n1529) );
MXI2X1TS U6774 ( .A(n6173), .B(n6273), .S0(n5885), .Y(n1547) );
MXI2X1TS U6775 ( .A(n6163), .B(n6284), .S0(n5883), .Y(n1517) );
MXI2X1TS U6776 ( .A(n6165), .B(n6290), .S0(n5883), .Y(n1523) );
MXI2X1TS U6777 ( .A(n6164), .B(n6275), .S0(n5883), .Y(n1520) );
MXI2X1TS U6778 ( .A(n6181), .B(n6280), .S0(n5884), .Y(n1571) );
MXI2X1TS U6779 ( .A(n6170), .B(n6285), .S0(n5885), .Y(n1538) );
MXI2X1TS U6780 ( .A(n6166), .B(n6292), .S0(n5885), .Y(n1526) );
MXI2X1TS U6781 ( .A(n6169), .B(n3070), .S0(n5885), .Y(n1535) );
MXI2X1TS U6782 ( .A(n6179), .B(n6287), .S0(n5884), .Y(n1565) );
MXI2X1TS U6783 ( .A(n6180), .B(n6276), .S0(n5884), .Y(n1568) );
MXI2X1TS U6784 ( .A(n6171), .B(n6272), .S0(n5885), .Y(n1541) );
MXI2X1TS U6785 ( .A(n5889), .B(n5886), .S0(n5890), .Y(n1427) );
MXI2X1TS U6786 ( .A(n6107), .B(n6314), .S0(n2489), .Y(n1446) );
MXI2X1TS U6787 ( .A(n6108), .B(n6192), .S0(n5890), .Y(n1452) );
MXI2X1TS U6788 ( .A(n6108), .B(n6315), .S0(n2489), .Y(n1451) );
MXI2X1TS U6789 ( .A(n6106), .B(n6190), .S0(n5890), .Y(n1442) );
MXI2X1TS U6790 ( .A(n6104), .B(n6188), .S0(n5890), .Y(n1432) );
MXI2X1TS U6791 ( .A(n6106), .B(n6313), .S0(n5888), .Y(n1441) );
MXI2X1TS U6792 ( .A(n6105), .B(n6189), .S0(n5890), .Y(n1437) );
MXI2X1TS U6793 ( .A(n5889), .B(n6310), .S0(n5888), .Y(n1426) );
MXI2X1TS U6794 ( .A(n6107), .B(n6191), .S0(n5890), .Y(n1447) );
NAND2X8TS U6795 ( .A(n5891), .B(beg_OP), .Y(n5907) );
NAND2X1TS U6796 ( .A(n6773), .B(final_result_ieee[17]), .Y(n6924) );
NAND2X1TS U6797 ( .A(n6772), .B(final_result_ieee[42]), .Y(n6974) );
NAND2X1TS U6798 ( .A(n6772), .B(final_result_ieee[43]), .Y(n6977) );
NAND2X1TS U6799 ( .A(n6773), .B(final_result_ieee[21]), .Y(n6931) );
NAND2X1TS U6800 ( .A(n6773), .B(final_result_ieee[0]), .Y(n6899) );
NAND2X1TS U6801 ( .A(n6773), .B(final_result_ieee[5]), .Y(n6906) );
NAND2X1TS U6802 ( .A(n6773), .B(final_result_ieee[7]), .Y(n6908) );
NAND2X1TS U6803 ( .A(n6773), .B(final_result_ieee[8]), .Y(n6909) );
NAND2X1TS U6804 ( .A(n6773), .B(final_result_ieee[1]), .Y(n6900) );
NAND2X1TS U6805 ( .A(n6773), .B(final_result_ieee[6]), .Y(n6907) );
NAND2X1TS U6806 ( .A(n6772), .B(final_result_ieee[49]), .Y(n6991) );
NAND2X1TS U6807 ( .A(n6772), .B(final_result_ieee[45]), .Y(n6983) );
NAND2X1TS U6808 ( .A(n6772), .B(final_result_ieee[50]), .Y(n6993) );
NAND2X1TS U6809 ( .A(n6772), .B(final_result_ieee[51]), .Y(n6997) );
NAND2X1TS U6810 ( .A(n6772), .B(final_result_ieee[44]), .Y(n6980) );
CLKMX2X2TS U6811 ( .A(Data_X[58]), .B(intDX_EWSW[58]), .S0(n5902), .Y(n1825)
);
CLKMX2X2TS U6812 ( .A(Data_X[54]), .B(intDX_EWSW[54]), .S0(n5896), .Y(n1829)
);
CLKMX2X2TS U6813 ( .A(Data_X[56]), .B(intDX_EWSW[56]), .S0(n5902), .Y(n1827)
);
CLKMX2X2TS U6814 ( .A(Data_X[59]), .B(intDX_EWSW[59]), .S0(n5896), .Y(n1824)
);
CLKMX2X2TS U6815 ( .A(Data_X[55]), .B(intDX_EWSW[55]), .S0(n5902), .Y(n1828)
);
CLKMX2X2TS U6816 ( .A(Data_X[57]), .B(intDX_EWSW[57]), .S0(n5894), .Y(n1826)
);
CLKMX2X2TS U6817 ( .A(Data_X[60]), .B(intDX_EWSW[60]), .S0(n5902), .Y(n1823)
);
CLKMX2X2TS U6818 ( .A(Data_Y[55]), .B(intDY_EWSW[55]), .S0(n5895), .Y(n1763)
);
CLKMX2X2TS U6819 ( .A(Data_Y[58]), .B(intDY_EWSW[58]), .S0(n5904), .Y(n1760)
);
CLKMX2X2TS U6820 ( .A(Data_Y[54]), .B(n1915), .S0(n5895), .Y(n1764) );
CLKMX2X3TS U6821 ( .A(Data_Y[32]), .B(intDY_EWSW[32]), .S0(n5897), .Y(n1786)
);
CLKMX2X2TS U6822 ( .A(Data_Y[47]), .B(n1987), .S0(n5895), .Y(n1771) );
CLKMX2X3TS U6823 ( .A(Data_X[35]), .B(intDX_EWSW[35]), .S0(n5900), .Y(n1848)
);
CLKMX2X3TS U6824 ( .A(Data_X[39]), .B(intDX_EWSW[39]), .S0(n5900), .Y(n1844)
);
CLKMX2X2TS U6825 ( .A(Data_Y[59]), .B(intDY_EWSW[59]), .S0(n5904), .Y(n1759)
);
CLKMX2X2TS U6826 ( .A(Data_Y[60]), .B(intDY_EWSW[60]), .S0(n5904), .Y(n1758)
);
CLKMX2X2TS U6827 ( .A(Data_Y[61]), .B(intDY_EWSW[61]), .S0(n5904), .Y(n1757)
);
AOI22X1TS U6828 ( .A0(n5913), .A1(n5909), .B0(n6716), .B1(n5908), .Y(n6798)
);
INVX2TS U6829 ( .A(n6015), .Y(n5910) );
AOI2BB2X1TS U6830 ( .B0(n5913), .B1(n5912), .A0N(n6015), .A1N(n6477), .Y(
n6799) );
XNOR2X1TS U6831 ( .A(n3332), .B(DMP_EXP_EWSW[52]), .Y(n5914) );
CLKMX2X2TS U6832 ( .A(n5914), .B(Shift_amount_SHT1_EWR[0]), .S0(n2555), .Y(
n1692) );
INVX2TS U6833 ( .A(n5938), .Y(n5915) );
NAND2X1TS U6834 ( .A(sub_x_1_n33), .B(DMP_EXP_EWSW[53]), .Y(n5936) );
NAND2X1TS U6835 ( .A(n5915), .B(n5936), .Y(n5916) );
XOR2X1TS U6836 ( .A(n5916), .B(n5937), .Y(n5917) );
CLKMX2X2TS U6837 ( .A(n5917), .B(Shift_amount_SHT1_EWR[1]), .S0(n2555), .Y(
n1691) );
INVX2TS U6838 ( .A(n6887), .Y(n6888) );
INVX2TS U6839 ( .A(n5918), .Y(n5920) );
NAND2X1TS U6840 ( .A(n5920), .B(n5919), .Y(n5922) );
XOR2X1TS U6841 ( .A(n5922), .B(n5921), .Y(n5927) );
OR2X2TS U6842 ( .A(add_x_6_A_2_), .B(add_x_6_B_2_), .Y(n5923) );
AOI22X1TS U6843 ( .A0(n3361), .A1(n5925), .B0(Raw_mant_NRM_SWR[2]), .B1(
n5924), .Y(n5926) );
OAI2BB1X1TS U6844 ( .A0N(n5928), .A1N(n5927), .B0(n5926), .Y(n1267) );
INVX2TS U6845 ( .A(n6870), .Y(n6788) );
INVX2TS U6846 ( .A(n6834), .Y(n6831) );
INVX2TS U6847 ( .A(n5929), .Y(n5950) );
INVX2TS U6848 ( .A(n5949), .Y(n5930) );
NAND2X1TS U6849 ( .A(n5930), .B(n2009), .Y(n5931) );
XOR2X1TS U6850 ( .A(n5950), .B(n5931), .Y(n5935) );
NAND2X1TS U6851 ( .A(n6068), .B(add_x_6_n534), .Y(n5932) );
XOR2X1TS U6852 ( .A(n5932), .B(add_x_6_n536), .Y(n5933) );
AOI22X1TS U6853 ( .A0(n5933), .A1(n5992), .B0(Raw_mant_NRM_SWR[3]), .B1(
n5958), .Y(n5934) );
INVX2TS U6854 ( .A(n5944), .Y(n5999) );
INVX2TS U6855 ( .A(n5998), .Y(n5939) );
NAND2X1TS U6856 ( .A(n5939), .B(n5997), .Y(n5940) );
XOR2X1TS U6857 ( .A(n5999), .B(n5940), .Y(n5941) );
NOR2X2TS U6858 ( .A(sub_x_1_n31), .B(DMP_EXP_EWSW[55]), .Y(n6000) );
NOR2X1TS U6859 ( .A(n5998), .B(n6000), .Y(n5943) );
OAI21X1TS U6860 ( .A0(n6000), .A1(n5997), .B0(n6001), .Y(n5942) );
AOI21X2TS U6861 ( .A0(n5943), .A1(n5944), .B0(n5942), .Y(n6008) );
INVX2TS U6862 ( .A(n6007), .Y(n5945) );
NAND2X1TS U6863 ( .A(n6263), .B(DMP_EXP_EWSW[56]), .Y(n6006) );
XOR2X1TS U6864 ( .A(n6008), .B(n5946), .Y(n5947) );
OAI21X1TS U6865 ( .A0(n5950), .A1(n5949), .B0(n2009), .Y(n5955) );
INVX2TS U6866 ( .A(n5951), .Y(n5953) );
NAND2X1TS U6867 ( .A(n5953), .B(n5952), .Y(n5954) );
XNOR2X1TS U6868 ( .A(n5955), .B(n5954), .Y(n5961) );
NAND2X1TS U6869 ( .A(n6066), .B(n5956), .Y(n5957) );
AOI22X1TS U6870 ( .A0(n5959), .A1(n5992), .B0(Raw_mant_NRM_SWR[4]), .B1(
n5958), .Y(n5960) );
OAI2BB1X1TS U6871 ( .A0N(n5996), .A1N(n5961), .B0(n5960), .Y(n1265) );
INVX2TS U6872 ( .A(n5976), .Y(n5962) );
NAND2X1TS U6873 ( .A(n5962), .B(n5975), .Y(n5963) );
XOR2X1TS U6874 ( .A(n5964), .B(n5963), .Y(n5971) );
NAND2X1TS U6875 ( .A(n6061), .B(n5966), .Y(n5967) );
AOI22X1TS U6876 ( .A0(n5969), .A1(n5992), .B0(Raw_mant_NRM_SWR[7]), .B1(
n5991), .Y(n5970) );
INVX2TS U6877 ( .A(n5972), .Y(n5973) );
NOR2X1TS U6878 ( .A(n5973), .B(n5976), .Y(n5979) );
INVX2TS U6879 ( .A(n5974), .Y(n5977) );
OAI21X1TS U6880 ( .A0(n5977), .A1(n5976), .B0(n5975), .Y(n5978) );
AOI21X1TS U6881 ( .A0(n5980), .A1(n5979), .B0(n5978), .Y(n5985) );
INVX2TS U6882 ( .A(n5981), .Y(n5983) );
NAND2X1TS U6883 ( .A(n5983), .B(n5982), .Y(n5989) );
INVX2TS U6884 ( .A(n5989), .Y(n5984) );
XOR2X1TS U6885 ( .A(n5985), .B(n5984), .Y(n5995) );
AOI21X1TS U6886 ( .A0(n5988), .A1(n5987), .B0(n5986), .Y(n5990) );
INVX2TS U6887 ( .A(n6000), .Y(n6002) );
NAND2X1TS U6888 ( .A(n6002), .B(n6001), .Y(n6003) );
XNOR2X1TS U6889 ( .A(n6004), .B(n6003), .Y(n6005) );
NAND2X1TS U6890 ( .A(n6268), .B(DMP_EXP_EWSW[57]), .Y(n6009) );
NAND2X1TS U6891 ( .A(n6010), .B(n6009), .Y(n6011) );
NAND2X1TS U6892 ( .A(n6716), .B(bit_shift_SHT2), .Y(n6014) );
NAND2X1TS U6893 ( .A(n6015), .B(n6014), .Y(n1754) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_DW_ADDER_syn.sdf");
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
eth1_rgmii_rd,
eth1_rgmii_rx_ctl,
eth1_rgmii_rxc,
eth1_rgmii_td,
eth1_rgmii_tx_ctl,
eth1_rgmii_txc,
eth2_rgmii_rd,
eth2_rgmii_rx_ctl,
eth2_rgmii_rxc,
eth2_rgmii_td,
eth2_rgmii_tx_ctl,
eth2_rgmii_txc,
eth_mdio_p,
eth_mdio_mdc,
eth_phy_rst_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
position_m1_i,
position_m2_i,
adc_clk_o,
adc_m1_ia_dat_i,
adc_m1_ib_dat_i,
adc_m1_vbus_dat_i,
fmc_m1_en_o,
fmc_m2_en_o,
adc_m2_ia_dat_i,
adc_m2_ib_dat_i,
adc_m2_vbus_dat_i,
pwm_m1_ah_o,
pwm_m1_al_o,
pwm_m1_bh_o,
pwm_m1_bl_o,
pwm_m1_ch_o,
pwm_m1_cl_o,
pwm_m1_dh_o,
pwm_m1_dl_o,
pwm_m2_ah_o,
pwm_m2_al_o,
pwm_m2_bh_o,
pwm_m2_bl_o,
pwm_m2_ch_o,
pwm_m2_cl_o,
pwm_m2_dh_o,
pwm_m2_dl_o,
vt_enable,
vauxn0,
vauxn8,
vauxp0,
vauxp8,
muxaddr_out,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
iic_ee2_scl_io,
iic_ee2_sda_io,
fmc_spi1_sel1_rdc,
fmc_spi1_miso,
fmc_spi1_mosi,
fmc_spi1_sck,
fmc_sample_n,
gpo,
otg_vbusoc);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
input [3:0] eth1_rgmii_rd;
input eth1_rgmii_rx_ctl;
input eth1_rgmii_rxc;
output [3:0] eth1_rgmii_td;
output eth1_rgmii_tx_ctl;
output eth1_rgmii_txc;
input [3:0] eth2_rgmii_rd;
input eth2_rgmii_rx_ctl;
input eth2_rgmii_rxc;
output [3:0] eth2_rgmii_td;
output eth2_rgmii_tx_ctl;
output eth2_rgmii_txc;
inout eth_mdio_p;
output eth_mdio_mdc;
output eth_phy_rst_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
input [2:0] position_m1_i;
input [2:0] position_m2_i;
output adc_clk_o;
output fmc_m1_en_o;
input adc_m1_ia_dat_i;
input adc_m1_ib_dat_i;
input adc_m1_vbus_dat_i;
output fmc_m2_en_o;
input adc_m2_ia_dat_i;
input adc_m2_ib_dat_i;
input adc_m2_vbus_dat_i;
output pwm_m1_ah_o;
output pwm_m1_al_o;
output pwm_m1_bh_o;
output pwm_m1_bl_o;
output pwm_m1_ch_o;
output pwm_m1_cl_o;
output pwm_m1_dh_o;
output pwm_m1_dl_o;
output pwm_m2_ah_o;
output pwm_m2_al_o;
output pwm_m2_bh_o;
output pwm_m2_bl_o;
output pwm_m2_ch_o;
output pwm_m2_cl_o;
output pwm_m2_dh_o;
output pwm_m2_dl_o;
output vt_enable;
input vauxn0;
input vauxn8;
input vauxp0;
input vauxp8;
output [ 1:0] muxaddr_out;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
inout iic_ee2_scl_io;
inout iic_ee2_sda_io;
output fmc_spi1_sel1_rdc;
input fmc_spi1_miso;
output fmc_spi1_mosi;
output fmc_spi1_sck;
output fmc_sample_n;
output [ 3:0] gpo;
input otg_vbusoc;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire eth_mdio_o;
wire eth_mdio_i;
wire eth_mdio_t;
// assignments
assign fmc_sample_n = gpio_o[32];
assign vt_enable = 1'b1;
assign pwm_m1_dh_o = 1'b0;
assign pwm_m1_dl_o = 1'b0;
assign pwm_m2_dh_o = 1'b0;
assign pwm_m2_dl_o = 1'b0;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32))
i_gpio_bd (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2))
i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
ad_iobuf #(
.DATA_WIDTH(1))
i_mdio_p (
.dio_t(eth_mdio_t),
.dio_i(eth_mdio_o),
.dio_o(eth_mdio_i),
.dio_p(eth_mdio_p));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.eth1_rgmii_rd(eth1_rgmii_rd),
.eth1_rgmii_rx_ctl(eth1_rgmii_rx_ctl),
.eth1_rgmii_rxc(eth1_rgmii_rxc),
.eth1_rgmii_td(eth1_rgmii_td),
.eth1_rgmii_tx_ctl(eth1_rgmii_tx_ctl),
.eth1_rgmii_txc(eth1_rgmii_txc),
.eth2_rgmii_rd(eth2_rgmii_rd),
.eth2_rgmii_rx_ctl(eth2_rgmii_rx_ctl),
.eth2_rgmii_rxc(eth2_rgmii_rxc),
.eth2_rgmii_td(eth2_rgmii_td),
.eth2_rgmii_tx_ctl(eth2_rgmii_tx_ctl),
.eth2_rgmii_txc(eth2_rgmii_txc),
.eth_phy_rst_n(eth_phy_rst_n),
.eth_mdio_o(eth_mdio_o),
.eth_mdio_t(eth_mdio_t),
.eth_mdio_i(eth_mdio_i),
.eth_mdio_mdc(eth_mdio_mdc),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.position_m1_i(position_m1_i),
.position_m2_i(position_m2_i),
.adc_clk_o(adc_clk_o),
.fmc_m1_en_o(fmc_m1_en_o),
.adc_m1_ia_dat_i(adc_m1_ia_dat_i),
.adc_m1_ib_dat_i(adc_m1_ib_dat_i),
.adc_m1_vbus_dat_i(adc_m1_vbus_dat_i),
.fmc_m2_en_o(fmc_m2_en_o),
.adc_m2_ia_dat_i(adc_m2_ia_dat_i),
.adc_m2_ib_dat_i(adc_m2_ib_dat_i),
.adc_m2_vbus_dat_i(adc_m2_vbus_dat_i),
.gpo_o(gpo),
.pwm_m1_ah_o(pwm_m1_ah_o),
.pwm_m1_al_o(pwm_m1_al_o),
.pwm_m1_bh_o(pwm_m1_bh_o),
.pwm_m1_bl_o(pwm_m1_bl_o),
.pwm_m1_ch_o(pwm_m1_ch_o),
.pwm_m1_cl_o(pwm_m1_cl_o),
.pwm_m2_ah_o(pwm_m2_ah_o),
.pwm_m2_al_o(pwm_m2_al_o),
.pwm_m2_bh_o(pwm_m2_bh_o),
.pwm_m2_bl_o(pwm_m2_bl_o),
.pwm_m2_ch_o(pwm_m2_ch_o),
.pwm_m2_cl_o(pwm_m2_cl_o),
.vaux0_v_n(vauxn0),
.vaux0_v_p(vauxp0),
.vaux8_v_n(vauxn8),
.vaux8_v_p(vauxp8),
.muxaddr_out(muxaddr_out),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.iic_ee2_scl_io(iic_ee2_scl_io),
.iic_ee2_sda_io(iic_ee2_sda_io),
.spi0_clk_i (1'b0),
.spi0_clk_o (fmc_spi1_sck),
.spi0_csn_0_o (fmc_spi1_sel1_rdc),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (fmc_spi1_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (fmc_spi1_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o (),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//-----------------------------------------------------------------------------
// File : test_setup.v
// Creation date : 28.11.2017
// Creation time : 12:45:33
// Description : Test arrangement for the example core with data memory, instuction memory and clock source. Peripheral access is unused, as it is tested in other setups.
// Created by : TermosPullo
// Tool : Kactus2 3.4.1184 32-bit
// Plugin : Verilog generator 2.1
// This file was generated based on IP-XACT component tut.fi:cpu.subsystem.test:core_example.setup:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.subsystem.test/core_example.setup/1.0/core_example.setup.1.0.xml
//-----------------------------------------------------------------------------
module test_setup();
// core_example_0_instructions_to_instruction_memory_0_slave wires:
wire [7:0] core_example_0_instructions_to_instruction_memory_0_slaveaddress;
wire [27:0] core_example_0_instructions_to_instruction_memory_0_slaveread_data;
// data_memory_0_slave_to_core_example_0_local_data wires:
wire [8:0] data_memory_0_slave_to_core_example_0_local_dataaddress;
wire [31:0] data_memory_0_slave_to_core_example_0_local_dataread_data;
wire data_memory_0_slave_to_core_example_0_local_datawrite;
wire [31:0] data_memory_0_slave_to_core_example_0_local_datawrite_data;
// Ad-hoc wires:
wire clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
wire clock_generator_0_clk_o_to_core_example_0_clk_i;
wire core_example_0_rst_i_to_clock_generator_0_rst_o;
wire clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
wire data_memory_0_rst_i_to_clock_generator_0_rst_o;
wire data_memory_0_clk_i_to_clock_generator_0_clk_o;
// clock_generator_0 port wires:
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
// core_example_0 port wires:
wire core_example_0_clk_i;
wire [7:0] core_example_0_iaddr_o;
wire [27:0] core_example_0_instruction_feed;
wire [8:0] core_example_0_local_address_o;
wire [31:0] core_example_0_local_read_data;
wire [31:0] core_example_0_local_write_data;
wire core_example_0_local_write_o;
wire core_example_0_rst_i;
// data_memory_0 port wires:
wire [8:0] data_memory_0_adr_i;
wire data_memory_0_clk_i;
wire [31:0] data_memory_0_read_data;
wire data_memory_0_rst_i;
wire data_memory_0_write;
wire [31:0] data_memory_0_write_data;
// instruction_memory_0 port wires:
wire instruction_memory_0_clk_i;
wire [7:0] instruction_memory_0_iaddr_i;
wire [27:0] instruction_memory_0_instruction_feed;
wire instruction_memory_0_rst_i;
// clock_generator_0 assignments:
assign clock_generator_0_clk_o_to_core_example_0_clk_i = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_instruction_memory_0_clk_i = clock_generator_0_clk_o;
assign data_memory_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_rst_o_to_instruction_memory_0_rst_i = clock_generator_0_rst_o;
assign core_example_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign data_memory_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
// core_example_0 assignments:
assign core_example_0_clk_i = clock_generator_0_clk_o_to_core_example_0_clk_i;
assign core_example_0_instructions_to_instruction_memory_0_slaveaddress[7:0] = core_example_0_iaddr_o[7:0];
assign core_example_0_instruction_feed[27:0] = core_example_0_instructions_to_instruction_memory_0_slaveread_data[27:0];
assign data_memory_0_slave_to_core_example_0_local_dataaddress[8:0] = core_example_0_local_address_o[8:0];
assign core_example_0_local_read_data[31:0] = data_memory_0_slave_to_core_example_0_local_dataread_data[31:0];
assign data_memory_0_slave_to_core_example_0_local_datawrite_data[31:0] = core_example_0_local_write_data[31:0];
assign data_memory_0_slave_to_core_example_0_local_datawrite = core_example_0_local_write_o;
assign core_example_0_rst_i = core_example_0_rst_i_to_clock_generator_0_rst_o;
// data_memory_0 assignments:
assign data_memory_0_adr_i[8:0] = data_memory_0_slave_to_core_example_0_local_dataaddress[8:0];
assign data_memory_0_clk_i = data_memory_0_clk_i_to_clock_generator_0_clk_o;
assign data_memory_0_slave_to_core_example_0_local_dataread_data[31:0] = data_memory_0_read_data[31:0];
assign data_memory_0_rst_i = data_memory_0_rst_i_to_clock_generator_0_rst_o;
assign data_memory_0_write = data_memory_0_slave_to_core_example_0_local_datawrite;
assign data_memory_0_write_data[31:0] = data_memory_0_slave_to_core_example_0_local_datawrite_data[31:0];
// instruction_memory_0 assignments:
assign instruction_memory_0_clk_i = clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
assign instruction_memory_0_iaddr_i[7:0] = core_example_0_instructions_to_instruction_memory_0_slaveaddress[7:0];
assign core_example_0_instructions_to_instruction_memory_0_slaveread_data[27:0] = instruction_memory_0_instruction_feed[27:0];
assign instruction_memory_0_rst_i = clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
// IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1
clock_generator clock_generator_0(
// Interface: wb_system
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
// IP-XACT VLNV: tut.fi:cpu.subsystem:core_example:1.0
core_example_0 #(
.DATA_WIDTH (32),
.ADDR_WIDTH (9),
.SUPPORTED_MEMORY (512),
.PERIPHERAL_BASE (128),
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
core_example_0(
// Interface: instructions
.instruction_feed (core_example_0_instruction_feed),
.iaddr_o (core_example_0_iaddr_o),
// Interface: local_data
.local_read_data (core_example_0_local_read_data),
.local_address_o (core_example_0_local_address_o),
.local_write_data (core_example_0_local_write_data),
.local_write_o (core_example_0_local_write_o),
// Interface: peripheral_access
.mem_data_i (0),
.mem_slave_rdy (0),
.mem_address_o (),
.mem_data_o (),
.mem_master_rdy (),
.mem_we_o (),
// These ports are not in any interface
.clk_i (core_example_0_clk_i),
.rst_i (core_example_0_rst_i));
// IP-XACT VLNV: tut.fi:cpu.logic.test:data_memory:1.0
data_memory #(
.DATA_WIDTH (32),
.ADDR_WIDTH (9),
.MEMORY_SIZE (128),
.AUB (8))
data_memory_0(
// Interface: slave
.adr_i (data_memory_0_adr_i),
.write (data_memory_0_write),
.write_data (data_memory_0_write_data),
.read_data (data_memory_0_read_data),
// These ports are not in any interface
.clk_i (data_memory_0_clk_i),
.rst_i (data_memory_0_rst_i));
// IP-XACT VLNV: tut.fi:cpu.logic.test:instruction_memory:1.0
instruction_memory #(
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_memory_0(
// Interface: slave
.iaddr_i (instruction_memory_0_iaddr_i),
.instruction_feed (instruction_memory_0_instruction_feed),
// These ports are not in any interface
.clk_i (instruction_memory_0_clk_i),
.rst_i (instruction_memory_0_rst_i));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_FUNCTIONAL_PP_V
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
//
// Generated by Bluespec Compiler, version 2012.01.A (build 26572, 2012-01-17)
//
// On Sat Feb 11 18:26:43 EST 2017
//
// Method conflict info:
// Method: input_arbs_0_select
// Conflict-free: input_arbs_0_select,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
// Sequenced before: input_arbs_0_next
//
// Method: input_arbs_0_next
// Conflict-free: input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
// Sequenced after: input_arbs_0_select
// Conflicts: input_arbs_0_next
//
// Method: input_arbs_1_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
// Sequenced before: input_arbs_1_next
//
// Method: input_arbs_1_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
// Sequenced after: input_arbs_1_select
// Conflicts: input_arbs_1_next
//
// Method: input_arbs_2_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
// Sequenced before: input_arbs_2_next
//
// Method: input_arbs_2_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select,
// input_arbs_4_next
// Sequenced after: input_arbs_2_select
// Conflicts: input_arbs_2_next
//
// Method: input_arbs_3_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_4_select,
// input_arbs_4_next
// Sequenced before: input_arbs_3_next
//
// Method: input_arbs_3_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_4_select,
// input_arbs_4_next
// Sequenced after: input_arbs_3_select
// Conflicts: input_arbs_3_next
//
// Method: input_arbs_4_select
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next,
// input_arbs_4_select
// Sequenced before: input_arbs_4_next
//
// Method: input_arbs_4_next
// Conflict-free: input_arbs_0_select,
// input_arbs_0_next,
// input_arbs_1_select,
// input_arbs_1_next,
// input_arbs_2_select,
// input_arbs_2_next,
// input_arbs_3_select,
// input_arbs_3_next
// Sequenced after: input_arbs_4_select
// Conflicts: input_arbs_4_next
//
//
// Ports:
// Name I/O size props
// input_arbs_0_select O 5
// input_arbs_1_select O 5
// input_arbs_2_select O 5
// input_arbs_3_select O 5
// input_arbs_4_select O 5
// CLK I 1 clock
// RST_N I 1 reset
// input_arbs_0_select_requests I 5
// input_arbs_1_select_requests I 5
// input_arbs_2_select_requests I 5
// input_arbs_3_select_requests I 5
// input_arbs_4_select_requests I 5
// EN_input_arbs_0_next I 1
// EN_input_arbs_1_next I 1
// EN_input_arbs_2_next I 1
// EN_input_arbs_3_next I 1
// EN_input_arbs_4_next I 1
//
// Combinational paths from inputs to outputs:
// input_arbs_0_select_requests -> input_arbs_0_select
// input_arbs_1_select_requests -> input_arbs_1_select
// input_arbs_2_select_requests -> input_arbs_2_select
// input_arbs_3_select_requests -> input_arbs_3_select
// input_arbs_4_select_requests -> input_arbs_4_select
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module mkRouterInputArbitersRoundRobin(CLK,
RST_N,
input_arbs_0_select_requests,
input_arbs_0_select,
EN_input_arbs_0_next,
input_arbs_1_select_requests,
input_arbs_1_select,
EN_input_arbs_1_next,
input_arbs_2_select_requests,
input_arbs_2_select,
EN_input_arbs_2_next,
input_arbs_3_select_requests,
input_arbs_3_select,
EN_input_arbs_3_next,
input_arbs_4_select_requests,
input_arbs_4_select,
EN_input_arbs_4_next);
input CLK;
input RST_N;
// value method input_arbs_0_select
input [4 : 0] input_arbs_0_select_requests;
output [4 : 0] input_arbs_0_select;
// action method input_arbs_0_next
input EN_input_arbs_0_next;
// value method input_arbs_1_select
input [4 : 0] input_arbs_1_select_requests;
output [4 : 0] input_arbs_1_select;
// action method input_arbs_1_next
input EN_input_arbs_1_next;
// value method input_arbs_2_select
input [4 : 0] input_arbs_2_select_requests;
output [4 : 0] input_arbs_2_select;
// action method input_arbs_2_next
input EN_input_arbs_2_next;
// value method input_arbs_3_select
input [4 : 0] input_arbs_3_select_requests;
output [4 : 0] input_arbs_3_select;
// action method input_arbs_3_next
input EN_input_arbs_3_next;
// value method input_arbs_4_select
input [4 : 0] input_arbs_4_select_requests;
output [4 : 0] input_arbs_4_select;
// action method input_arbs_4_next
input EN_input_arbs_4_next;
// signals for module outputs
wire [4 : 0] input_arbs_0_select,
input_arbs_1_select,
input_arbs_2_select,
input_arbs_3_select,
input_arbs_4_select;
// register ias_0_token
reg [4 : 0] ias_0_token;
wire [4 : 0] ias_0_token$D_IN;
wire ias_0_token$EN;
// register ias_1_token
reg [4 : 0] ias_1_token;
wire [4 : 0] ias_1_token$D_IN;
wire ias_1_token$EN;
// register ias_2_token
reg [4 : 0] ias_2_token;
wire [4 : 0] ias_2_token$D_IN;
wire ias_2_token$EN;
// register ias_3_token
reg [4 : 0] ias_3_token;
wire [4 : 0] ias_3_token$D_IN;
wire ias_3_token$EN;
// register ias_4_token
reg [4 : 0] ias_4_token;
wire [4 : 0] ias_4_token$D_IN;
wire ias_4_token$EN;
// remaining internal signals
wire [1 : 0] ab__h12572,
ab__h12587,
ab__h12602,
ab__h12617,
ab__h12632,
ab__h14013,
ab__h14460,
ab__h14853,
ab__h15197,
ab__h15492,
ab__h19612,
ab__h19627,
ab__h19642,
ab__h19657,
ab__h19672,
ab__h21053,
ab__h21500,
ab__h21893,
ab__h22237,
ab__h22532,
ab__h26652,
ab__h26667,
ab__h26682,
ab__h26697,
ab__h26712,
ab__h28093,
ab__h28540,
ab__h28933,
ab__h29277,
ab__h29572,
ab__h33692,
ab__h33707,
ab__h33722,
ab__h33737,
ab__h33752,
ab__h35133,
ab__h35580,
ab__h35973,
ab__h36317,
ab__h36612,
ab__h5532,
ab__h5547,
ab__h5562,
ab__h5577,
ab__h5592,
ab__h6973,
ab__h7420,
ab__h7813,
ab__h8157,
ab__h8452;
wire NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328,
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68,
NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276,
NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267,
NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136,
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278,
NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206,
NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208,
NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127,
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346,
NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337,
ab_BIT_0___h13184,
ab_BIT_0___h13291,
ab_BIT_0___h13398,
ab_BIT_0___h13505,
ab_BIT_0___h14084,
ab_BIT_0___h14220,
ab_BIT_0___h14613,
ab_BIT_0___h14957,
ab_BIT_0___h15252,
ab_BIT_0___h20224,
ab_BIT_0___h20331,
ab_BIT_0___h20438,
ab_BIT_0___h20545,
ab_BIT_0___h21124,
ab_BIT_0___h21260,
ab_BIT_0___h21653,
ab_BIT_0___h21997,
ab_BIT_0___h22292,
ab_BIT_0___h27264,
ab_BIT_0___h27371,
ab_BIT_0___h27478,
ab_BIT_0___h27585,
ab_BIT_0___h28164,
ab_BIT_0___h28300,
ab_BIT_0___h28693,
ab_BIT_0___h29037,
ab_BIT_0___h29332,
ab_BIT_0___h34304,
ab_BIT_0___h34411,
ab_BIT_0___h34518,
ab_BIT_0___h34625,
ab_BIT_0___h35204,
ab_BIT_0___h35340,
ab_BIT_0___h35733,
ab_BIT_0___h36077,
ab_BIT_0___h36372,
ab_BIT_0___h6144,
ab_BIT_0___h6251,
ab_BIT_0___h6358,
ab_BIT_0___h6465,
ab_BIT_0___h7044,
ab_BIT_0___h7180,
ab_BIT_0___h7573,
ab_BIT_0___h7917,
ab_BIT_0___h8212,
ias_0_token_BIT_0___h6142,
ias_0_token_BIT_1___h6249,
ias_0_token_BIT_2___h6356,
ias_0_token_BIT_3___h6463,
ias_0_token_BIT_4___h6570,
ias_1_token_BIT_0___h13182,
ias_1_token_BIT_1___h13289,
ias_1_token_BIT_2___h13396,
ias_1_token_BIT_3___h13503,
ias_1_token_BIT_4___h13610,
ias_2_token_BIT_0___h20222,
ias_2_token_BIT_1___h20329,
ias_2_token_BIT_2___h20436,
ias_2_token_BIT_3___h20543,
ias_2_token_BIT_4___h20650,
ias_3_token_BIT_0___h27262,
ias_3_token_BIT_1___h27369,
ias_3_token_BIT_2___h27476,
ias_3_token_BIT_3___h27583,
ias_3_token_BIT_4___h27690,
ias_4_token_BIT_0___h34302,
ias_4_token_BIT_1___h34409,
ias_4_token_BIT_2___h34516,
ias_4_token_BIT_3___h34623,
ias_4_token_BIT_4___h34730;
// value method input_arbs_0_select
assign input_arbs_0_select =
{ ab__h5532[1] || ab__h6973[1],
!ab__h5532[1] && !ab__h6973[1] &&
(ab__h5547[1] || ab__h7420[1]),
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48,
!ab__h5532[1] && !ab__h6973[1] &&
NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57,
NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 } ;
// value method input_arbs_1_select
assign input_arbs_1_select =
{ ab__h12572[1] || ab__h14013[1],
!ab__h12572[1] && !ab__h14013[1] &&
(ab__h12587[1] || ab__h14460[1]),
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118,
!ab__h12572[1] && !ab__h14013[1] &&
NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127,
NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138 } ;
// value method input_arbs_2_select
assign input_arbs_2_select =
{ ab__h19612[1] || ab__h21053[1],
!ab__h19612[1] && !ab__h21053[1] &&
(ab__h19627[1] || ab__h21500[1]),
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188,
!ab__h19612[1] && !ab__h21053[1] &&
NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197,
NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208 } ;
// value method input_arbs_3_select
assign input_arbs_3_select =
{ ab__h26652[1] || ab__h28093[1],
!ab__h26652[1] && !ab__h28093[1] &&
(ab__h26667[1] || ab__h28540[1]),
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258,
!ab__h26652[1] && !ab__h28093[1] &&
NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267,
NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278 } ;
// value method input_arbs_4_select
assign input_arbs_4_select =
{ ab__h33692[1] || ab__h35133[1],
!ab__h33692[1] && !ab__h35133[1] &&
(ab__h33707[1] || ab__h35580[1]),
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328,
!ab__h33692[1] && !ab__h35133[1] &&
NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337,
NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348 } ;
// register ias_0_token
assign ias_0_token$D_IN = { ias_0_token[0], ias_0_token[4:1] } ;
assign ias_0_token$EN = EN_input_arbs_0_next ;
// register ias_1_token
assign ias_1_token$D_IN = { ias_1_token[0], ias_1_token[4:1] } ;
assign ias_1_token$EN = EN_input_arbs_1_next ;
// register ias_2_token
assign ias_2_token$D_IN = { ias_2_token[0], ias_2_token[4:1] } ;
assign ias_2_token$EN = EN_input_arbs_2_next ;
// register ias_3_token
assign ias_3_token$D_IN = { ias_3_token[0], ias_3_token[4:1] } ;
assign ias_3_token$EN = EN_input_arbs_3_next ;
// register ias_4_token
assign ias_4_token$D_IN = { ias_4_token[0], ias_4_token[4:1] } ;
assign ias_4_token$EN = EN_input_arbs_4_next ;
// remaining internal signals
module_gen_grant_carry instance_gen_grant_carry_45(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(input_arbs_0_select_requests[0]),
.gen_grant_carry_p(ias_0_token_BIT_0___h6142),
.gen_grant_carry(ab__h5592));
module_gen_grant_carry instance_gen_grant_carry_1(.gen_grant_carry_c(ab_BIT_0___h6144),
.gen_grant_carry_r(input_arbs_0_select_requests[1]),
.gen_grant_carry_p(ias_0_token_BIT_1___h6249),
.gen_grant_carry(ab__h5577));
module_gen_grant_carry instance_gen_grant_carry_0(.gen_grant_carry_c(ab_BIT_0___h6251),
.gen_grant_carry_r(input_arbs_0_select_requests[2]),
.gen_grant_carry_p(ias_0_token_BIT_2___h6356),
.gen_grant_carry(ab__h5562));
module_gen_grant_carry instance_gen_grant_carry_2(.gen_grant_carry_c(ab_BIT_0___h6358),
.gen_grant_carry_r(input_arbs_0_select_requests[3]),
.gen_grant_carry_p(ias_0_token_BIT_3___h6463),
.gen_grant_carry(ab__h5547));
module_gen_grant_carry instance_gen_grant_carry_3(.gen_grant_carry_c(ab_BIT_0___h6465),
.gen_grant_carry_r(input_arbs_0_select_requests[4]),
.gen_grant_carry_p(ias_0_token_BIT_4___h6570),
.gen_grant_carry(ab__h5532));
module_gen_grant_carry instance_gen_grant_carry_4(.gen_grant_carry_c(ab_BIT_0___h7044),
.gen_grant_carry_r(input_arbs_0_select_requests[0]),
.gen_grant_carry_p(ias_0_token_BIT_0___h6142),
.gen_grant_carry(ab__h8452));
module_gen_grant_carry instance_gen_grant_carry_5(.gen_grant_carry_c(ab_BIT_0___h8212),
.gen_grant_carry_r(input_arbs_0_select_requests[1]),
.gen_grant_carry_p(ias_0_token_BIT_1___h6249),
.gen_grant_carry(ab__h8157));
module_gen_grant_carry instance_gen_grant_carry_6(.gen_grant_carry_c(ab_BIT_0___h7917),
.gen_grant_carry_r(input_arbs_0_select_requests[2]),
.gen_grant_carry_p(ias_0_token_BIT_2___h6356),
.gen_grant_carry(ab__h7813));
module_gen_grant_carry instance_gen_grant_carry_7(.gen_grant_carry_c(ab_BIT_0___h7573),
.gen_grant_carry_r(input_arbs_0_select_requests[3]),
.gen_grant_carry_p(ias_0_token_BIT_3___h6463),
.gen_grant_carry(ab__h7420));
module_gen_grant_carry instance_gen_grant_carry_8(.gen_grant_carry_c(ab_BIT_0___h7180),
.gen_grant_carry_r(input_arbs_0_select_requests[4]),
.gen_grant_carry_p(ias_0_token_BIT_4___h6570),
.gen_grant_carry(ab__h6973));
module_gen_grant_carry instance_gen_grant_carry_46(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(input_arbs_1_select_requests[0]),
.gen_grant_carry_p(ias_1_token_BIT_0___h13182),
.gen_grant_carry(ab__h12632));
module_gen_grant_carry instance_gen_grant_carry_9(.gen_grant_carry_c(ab_BIT_0___h13184),
.gen_grant_carry_r(input_arbs_1_select_requests[1]),
.gen_grant_carry_p(ias_1_token_BIT_1___h13289),
.gen_grant_carry(ab__h12617));
module_gen_grant_carry instance_gen_grant_carry_10(.gen_grant_carry_c(ab_BIT_0___h13291),
.gen_grant_carry_r(input_arbs_1_select_requests[2]),
.gen_grant_carry_p(ias_1_token_BIT_2___h13396),
.gen_grant_carry(ab__h12602));
module_gen_grant_carry instance_gen_grant_carry_11(.gen_grant_carry_c(ab_BIT_0___h13398),
.gen_grant_carry_r(input_arbs_1_select_requests[3]),
.gen_grant_carry_p(ias_1_token_BIT_3___h13503),
.gen_grant_carry(ab__h12587));
module_gen_grant_carry instance_gen_grant_carry_12(.gen_grant_carry_c(ab_BIT_0___h13505),
.gen_grant_carry_r(input_arbs_1_select_requests[4]),
.gen_grant_carry_p(ias_1_token_BIT_4___h13610),
.gen_grant_carry(ab__h12572));
module_gen_grant_carry instance_gen_grant_carry_13(.gen_grant_carry_c(ab_BIT_0___h14084),
.gen_grant_carry_r(input_arbs_1_select_requests[0]),
.gen_grant_carry_p(ias_1_token_BIT_0___h13182),
.gen_grant_carry(ab__h15492));
module_gen_grant_carry instance_gen_grant_carry_14(.gen_grant_carry_c(ab_BIT_0___h15252),
.gen_grant_carry_r(input_arbs_1_select_requests[1]),
.gen_grant_carry_p(ias_1_token_BIT_1___h13289),
.gen_grant_carry(ab__h15197));
module_gen_grant_carry instance_gen_grant_carry_15(.gen_grant_carry_c(ab_BIT_0___h14957),
.gen_grant_carry_r(input_arbs_1_select_requests[2]),
.gen_grant_carry_p(ias_1_token_BIT_2___h13396),
.gen_grant_carry(ab__h14853));
module_gen_grant_carry instance_gen_grant_carry_16(.gen_grant_carry_c(ab_BIT_0___h14613),
.gen_grant_carry_r(input_arbs_1_select_requests[3]),
.gen_grant_carry_p(ias_1_token_BIT_3___h13503),
.gen_grant_carry(ab__h14460));
module_gen_grant_carry instance_gen_grant_carry_17(.gen_grant_carry_c(ab_BIT_0___h14220),
.gen_grant_carry_r(input_arbs_1_select_requests[4]),
.gen_grant_carry_p(ias_1_token_BIT_4___h13610),
.gen_grant_carry(ab__h14013));
module_gen_grant_carry instance_gen_grant_carry_47(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(input_arbs_2_select_requests[0]),
.gen_grant_carry_p(ias_2_token_BIT_0___h20222),
.gen_grant_carry(ab__h19672));
module_gen_grant_carry instance_gen_grant_carry_18(.gen_grant_carry_c(ab_BIT_0___h20224),
.gen_grant_carry_r(input_arbs_2_select_requests[1]),
.gen_grant_carry_p(ias_2_token_BIT_1___h20329),
.gen_grant_carry(ab__h19657));
module_gen_grant_carry instance_gen_grant_carry_19(.gen_grant_carry_c(ab_BIT_0___h20331),
.gen_grant_carry_r(input_arbs_2_select_requests[2]),
.gen_grant_carry_p(ias_2_token_BIT_2___h20436),
.gen_grant_carry(ab__h19642));
module_gen_grant_carry instance_gen_grant_carry_20(.gen_grant_carry_c(ab_BIT_0___h20438),
.gen_grant_carry_r(input_arbs_2_select_requests[3]),
.gen_grant_carry_p(ias_2_token_BIT_3___h20543),
.gen_grant_carry(ab__h19627));
module_gen_grant_carry instance_gen_grant_carry_21(.gen_grant_carry_c(ab_BIT_0___h20545),
.gen_grant_carry_r(input_arbs_2_select_requests[4]),
.gen_grant_carry_p(ias_2_token_BIT_4___h20650),
.gen_grant_carry(ab__h19612));
module_gen_grant_carry instance_gen_grant_carry_22(.gen_grant_carry_c(ab_BIT_0___h21124),
.gen_grant_carry_r(input_arbs_2_select_requests[0]),
.gen_grant_carry_p(ias_2_token_BIT_0___h20222),
.gen_grant_carry(ab__h22532));
module_gen_grant_carry instance_gen_grant_carry_23(.gen_grant_carry_c(ab_BIT_0___h22292),
.gen_grant_carry_r(input_arbs_2_select_requests[1]),
.gen_grant_carry_p(ias_2_token_BIT_1___h20329),
.gen_grant_carry(ab__h22237));
module_gen_grant_carry instance_gen_grant_carry_24(.gen_grant_carry_c(ab_BIT_0___h21997),
.gen_grant_carry_r(input_arbs_2_select_requests[2]),
.gen_grant_carry_p(ias_2_token_BIT_2___h20436),
.gen_grant_carry(ab__h21893));
module_gen_grant_carry instance_gen_grant_carry_25(.gen_grant_carry_c(ab_BIT_0___h21653),
.gen_grant_carry_r(input_arbs_2_select_requests[3]),
.gen_grant_carry_p(ias_2_token_BIT_3___h20543),
.gen_grant_carry(ab__h21500));
module_gen_grant_carry instance_gen_grant_carry_26(.gen_grant_carry_c(ab_BIT_0___h21260),
.gen_grant_carry_r(input_arbs_2_select_requests[4]),
.gen_grant_carry_p(ias_2_token_BIT_4___h20650),
.gen_grant_carry(ab__h21053));
module_gen_grant_carry instance_gen_grant_carry_48(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(input_arbs_3_select_requests[0]),
.gen_grant_carry_p(ias_3_token_BIT_0___h27262),
.gen_grant_carry(ab__h26712));
module_gen_grant_carry instance_gen_grant_carry_27(.gen_grant_carry_c(ab_BIT_0___h27264),
.gen_grant_carry_r(input_arbs_3_select_requests[1]),
.gen_grant_carry_p(ias_3_token_BIT_1___h27369),
.gen_grant_carry(ab__h26697));
module_gen_grant_carry instance_gen_grant_carry_28(.gen_grant_carry_c(ab_BIT_0___h27371),
.gen_grant_carry_r(input_arbs_3_select_requests[2]),
.gen_grant_carry_p(ias_3_token_BIT_2___h27476),
.gen_grant_carry(ab__h26682));
module_gen_grant_carry instance_gen_grant_carry_29(.gen_grant_carry_c(ab_BIT_0___h27478),
.gen_grant_carry_r(input_arbs_3_select_requests[3]),
.gen_grant_carry_p(ias_3_token_BIT_3___h27583),
.gen_grant_carry(ab__h26667));
module_gen_grant_carry instance_gen_grant_carry_30(.gen_grant_carry_c(ab_BIT_0___h27585),
.gen_grant_carry_r(input_arbs_3_select_requests[4]),
.gen_grant_carry_p(ias_3_token_BIT_4___h27690),
.gen_grant_carry(ab__h26652));
module_gen_grant_carry instance_gen_grant_carry_31(.gen_grant_carry_c(ab_BIT_0___h28164),
.gen_grant_carry_r(input_arbs_3_select_requests[0]),
.gen_grant_carry_p(ias_3_token_BIT_0___h27262),
.gen_grant_carry(ab__h29572));
module_gen_grant_carry instance_gen_grant_carry_32(.gen_grant_carry_c(ab_BIT_0___h29332),
.gen_grant_carry_r(input_arbs_3_select_requests[1]),
.gen_grant_carry_p(ias_3_token_BIT_1___h27369),
.gen_grant_carry(ab__h29277));
module_gen_grant_carry instance_gen_grant_carry_33(.gen_grant_carry_c(ab_BIT_0___h29037),
.gen_grant_carry_r(input_arbs_3_select_requests[2]),
.gen_grant_carry_p(ias_3_token_BIT_2___h27476),
.gen_grant_carry(ab__h28933));
module_gen_grant_carry instance_gen_grant_carry_34(.gen_grant_carry_c(ab_BIT_0___h28693),
.gen_grant_carry_r(input_arbs_3_select_requests[3]),
.gen_grant_carry_p(ias_3_token_BIT_3___h27583),
.gen_grant_carry(ab__h28540));
module_gen_grant_carry instance_gen_grant_carry_35(.gen_grant_carry_c(ab_BIT_0___h28300),
.gen_grant_carry_r(input_arbs_3_select_requests[4]),
.gen_grant_carry_p(ias_3_token_BIT_4___h27690),
.gen_grant_carry(ab__h28093));
module_gen_grant_carry instance_gen_grant_carry_49(.gen_grant_carry_c(1'd0),
.gen_grant_carry_r(input_arbs_4_select_requests[0]),
.gen_grant_carry_p(ias_4_token_BIT_0___h34302),
.gen_grant_carry(ab__h33752));
module_gen_grant_carry instance_gen_grant_carry_36(.gen_grant_carry_c(ab_BIT_0___h34304),
.gen_grant_carry_r(input_arbs_4_select_requests[1]),
.gen_grant_carry_p(ias_4_token_BIT_1___h34409),
.gen_grant_carry(ab__h33737));
module_gen_grant_carry instance_gen_grant_carry_37(.gen_grant_carry_c(ab_BIT_0___h34411),
.gen_grant_carry_r(input_arbs_4_select_requests[2]),
.gen_grant_carry_p(ias_4_token_BIT_2___h34516),
.gen_grant_carry(ab__h33722));
module_gen_grant_carry instance_gen_grant_carry_38(.gen_grant_carry_c(ab_BIT_0___h34518),
.gen_grant_carry_r(input_arbs_4_select_requests[3]),
.gen_grant_carry_p(ias_4_token_BIT_3___h34623),
.gen_grant_carry(ab__h33707));
module_gen_grant_carry instance_gen_grant_carry_39(.gen_grant_carry_c(ab_BIT_0___h34625),
.gen_grant_carry_r(input_arbs_4_select_requests[4]),
.gen_grant_carry_p(ias_4_token_BIT_4___h34730),
.gen_grant_carry(ab__h33692));
module_gen_grant_carry instance_gen_grant_carry_40(.gen_grant_carry_c(ab_BIT_0___h35204),
.gen_grant_carry_r(input_arbs_4_select_requests[0]),
.gen_grant_carry_p(ias_4_token_BIT_0___h34302),
.gen_grant_carry(ab__h36612));
module_gen_grant_carry instance_gen_grant_carry_41(.gen_grant_carry_c(ab_BIT_0___h36372),
.gen_grant_carry_r(input_arbs_4_select_requests[1]),
.gen_grant_carry_p(ias_4_token_BIT_1___h34409),
.gen_grant_carry(ab__h36317));
module_gen_grant_carry instance_gen_grant_carry_42(.gen_grant_carry_c(ab_BIT_0___h36077),
.gen_grant_carry_r(input_arbs_4_select_requests[2]),
.gen_grant_carry_p(ias_4_token_BIT_2___h34516),
.gen_grant_carry(ab__h35973));
module_gen_grant_carry instance_gen_grant_carry_43(.gen_grant_carry_c(ab_BIT_0___h35733),
.gen_grant_carry_r(input_arbs_4_select_requests[3]),
.gen_grant_carry_p(ias_4_token_BIT_3___h34623),
.gen_grant_carry(ab__h35580));
module_gen_grant_carry instance_gen_grant_carry_44(.gen_grant_carry_c(ab_BIT_0___h35340),
.gen_grant_carry_r(input_arbs_4_select_requests[4]),
.gen_grant_carry_p(ias_4_token_BIT_4___h34730),
.gen_grant_carry(ab__h35133));
assign NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d328 =
!ab__h33692[1] && !ab__h35133[1] && !ab__h33707[1] &&
!ab__h35580[1] &&
(ab__h33722[1] || ab__h35973[1]) ;
assign NOT_gen_grant_carry_00_BIT_1_01_14_AND_NOT_gen_ETC___d348 =
!ab__h33692[1] && !ab__h35133[1] && !ab__h33707[1] &&
!ab__h35580[1] &&
NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346 ;
assign NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d118 =
!ab__h12572[1] && !ab__h14013[1] && !ab__h12587[1] &&
!ab__h14460[1] &&
(ab__h12602[1] || ab__h14853[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_04_AND_NOT_gen_g_ETC___d138 =
!ab__h12572[1] && !ab__h14013[1] && !ab__h12587[1] &&
!ab__h14460[1] &&
NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136 ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d48 =
!ab__h5532[1] && !ab__h6973[1] && !ab__h5547[1] &&
!ab__h7420[1] &&
(ab__h5562[1] || ab__h7813[1]) ;
assign NOT_gen_grant_carry_0_BIT_1_1_4_AND_NOT_gen_gr_ETC___d68 =
!ab__h5532[1] && !ab__h6973[1] && !ab__h5547[1] &&
!ab__h7420[1] &&
NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 ;
assign NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276 =
!ab__h26682[1] && !ab__h28933[1] && !ab__h26697[1] &&
!ab__h29277[1] &&
(ab__h26712[1] || ab__h29572[1]) ;
assign NOT_gen_grant_carry_26_BIT_1_47_51_AND_NOT_gen_ETC___d267 =
!ab__h26667[1] && !ab__h28540[1] && !ab__h26682[1] &&
!ab__h28933[1] &&
(ab__h26697[1] || ab__h29277[1]) ;
assign NOT_gen_grant_carry_2_BIT_1_14_20_AND_NOT_gen__ETC___d136 =
!ab__h12602[1] && !ab__h14853[1] && !ab__h12617[1] &&
!ab__h15197[1] &&
(ab__h12632[1] || ab__h15492[1]) ;
assign NOT_gen_grant_carry_2_BIT_1_4_0_AND_NOT_gen_gr_ETC___d66 =
!ab__h5562[1] && !ab__h7813[1] && !ab__h5577[1] &&
!ab__h8157[1] &&
(ab__h5592[1] || ab__h8452[1]) ;
assign NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d258 =
!ab__h26652[1] && !ab__h28093[1] && !ab__h26667[1] &&
!ab__h28540[1] &&
(ab__h26682[1] || ab__h28933[1]) ;
assign NOT_gen_grant_carry_30_BIT_1_31_44_AND_NOT_gen_ETC___d278 =
!ab__h26652[1] && !ab__h28093[1] && !ab__h26667[1] &&
!ab__h28540[1] &&
NOT_gen_grant_carry_22_BIT_1_54_60_AND_NOT_gen_ETC___d276 ;
assign NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206 =
!ab__h19642[1] && !ab__h21893[1] && !ab__h19657[1] &&
!ab__h22237[1] &&
(ab__h19672[1] || ab__h22532[1]) ;
assign NOT_gen_grant_carry_56_BIT_1_77_81_AND_NOT_gen_ETC___d197 =
!ab__h19627[1] && !ab__h21500[1] && !ab__h19642[1] &&
!ab__h21893[1] &&
(ab__h19657[1] || ab__h22237[1]) ;
assign NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d188 =
!ab__h19612[1] && !ab__h21053[1] && !ab__h19627[1] &&
!ab__h21500[1] &&
(ab__h19642[1] || ab__h21893[1]) ;
assign NOT_gen_grant_carry_60_BIT_1_61_74_AND_NOT_gen_ETC___d208 =
!ab__h19612[1] && !ab__h21053[1] && !ab__h19627[1] &&
!ab__h21500[1] &&
NOT_gen_grant_carry_52_BIT_1_84_90_AND_NOT_gen_ETC___d206 ;
assign NOT_gen_grant_carry_6_BIT_1_07_11_AND_NOT_gen__ETC___d127 =
!ab__h12587[1] && !ab__h14460[1] && !ab__h12602[1] &&
!ab__h14853[1] &&
(ab__h12617[1] || ab__h15197[1]) ;
assign NOT_gen_grant_carry_6_BIT_1_7_1_AND_NOT_gen_gr_ETC___d57 =
!ab__h5547[1] && !ab__h7420[1] && !ab__h5562[1] &&
!ab__h7813[1] &&
(ab__h5577[1] || ab__h8157[1]) ;
assign NOT_gen_grant_carry_92_BIT_1_24_30_AND_NOT_gen_ETC___d346 =
!ab__h33722[1] && !ab__h35973[1] && !ab__h33737[1] &&
!ab__h36317[1] &&
(ab__h33752[1] || ab__h36612[1]) ;
assign NOT_gen_grant_carry_96_BIT_1_17_21_AND_NOT_gen_ETC___d337 =
!ab__h33707[1] && !ab__h35580[1] && !ab__h33722[1] &&
!ab__h35973[1] &&
(ab__h33737[1] || ab__h36317[1]) ;
assign ab_BIT_0___h13184 = ab__h12632[0] ;
assign ab_BIT_0___h13291 = ab__h12617[0] ;
assign ab_BIT_0___h13398 = ab__h12602[0] ;
assign ab_BIT_0___h13505 = ab__h12587[0] ;
assign ab_BIT_0___h14084 = ab__h12572[0] ;
assign ab_BIT_0___h14220 = ab__h14460[0] ;
assign ab_BIT_0___h14613 = ab__h14853[0] ;
assign ab_BIT_0___h14957 = ab__h15197[0] ;
assign ab_BIT_0___h15252 = ab__h15492[0] ;
assign ab_BIT_0___h20224 = ab__h19672[0] ;
assign ab_BIT_0___h20331 = ab__h19657[0] ;
assign ab_BIT_0___h20438 = ab__h19642[0] ;
assign ab_BIT_0___h20545 = ab__h19627[0] ;
assign ab_BIT_0___h21124 = ab__h19612[0] ;
assign ab_BIT_0___h21260 = ab__h21500[0] ;
assign ab_BIT_0___h21653 = ab__h21893[0] ;
assign ab_BIT_0___h21997 = ab__h22237[0] ;
assign ab_BIT_0___h22292 = ab__h22532[0] ;
assign ab_BIT_0___h27264 = ab__h26712[0] ;
assign ab_BIT_0___h27371 = ab__h26697[0] ;
assign ab_BIT_0___h27478 = ab__h26682[0] ;
assign ab_BIT_0___h27585 = ab__h26667[0] ;
assign ab_BIT_0___h28164 = ab__h26652[0] ;
assign ab_BIT_0___h28300 = ab__h28540[0] ;
assign ab_BIT_0___h28693 = ab__h28933[0] ;
assign ab_BIT_0___h29037 = ab__h29277[0] ;
assign ab_BIT_0___h29332 = ab__h29572[0] ;
assign ab_BIT_0___h34304 = ab__h33752[0] ;
assign ab_BIT_0___h34411 = ab__h33737[0] ;
assign ab_BIT_0___h34518 = ab__h33722[0] ;
assign ab_BIT_0___h34625 = ab__h33707[0] ;
assign ab_BIT_0___h35204 = ab__h33692[0] ;
assign ab_BIT_0___h35340 = ab__h35580[0] ;
assign ab_BIT_0___h35733 = ab__h35973[0] ;
assign ab_BIT_0___h36077 = ab__h36317[0] ;
assign ab_BIT_0___h36372 = ab__h36612[0] ;
assign ab_BIT_0___h6144 = ab__h5592[0] ;
assign ab_BIT_0___h6251 = ab__h5577[0] ;
assign ab_BIT_0___h6358 = ab__h5562[0] ;
assign ab_BIT_0___h6465 = ab__h5547[0] ;
assign ab_BIT_0___h7044 = ab__h5532[0] ;
assign ab_BIT_0___h7180 = ab__h7420[0] ;
assign ab_BIT_0___h7573 = ab__h7813[0] ;
assign ab_BIT_0___h7917 = ab__h8157[0] ;
assign ab_BIT_0___h8212 = ab__h8452[0] ;
assign ias_0_token_BIT_0___h6142 = ias_0_token[0] ;
assign ias_0_token_BIT_1___h6249 = ias_0_token[1] ;
assign ias_0_token_BIT_2___h6356 = ias_0_token[2] ;
assign ias_0_token_BIT_3___h6463 = ias_0_token[3] ;
assign ias_0_token_BIT_4___h6570 = ias_0_token[4] ;
assign ias_1_token_BIT_0___h13182 = ias_1_token[0] ;
assign ias_1_token_BIT_1___h13289 = ias_1_token[1] ;
assign ias_1_token_BIT_2___h13396 = ias_1_token[2] ;
assign ias_1_token_BIT_3___h13503 = ias_1_token[3] ;
assign ias_1_token_BIT_4___h13610 = ias_1_token[4] ;
assign ias_2_token_BIT_0___h20222 = ias_2_token[0] ;
assign ias_2_token_BIT_1___h20329 = ias_2_token[1] ;
assign ias_2_token_BIT_2___h20436 = ias_2_token[2] ;
assign ias_2_token_BIT_3___h20543 = ias_2_token[3] ;
assign ias_2_token_BIT_4___h20650 = ias_2_token[4] ;
assign ias_3_token_BIT_0___h27262 = ias_3_token[0] ;
assign ias_3_token_BIT_1___h27369 = ias_3_token[1] ;
assign ias_3_token_BIT_2___h27476 = ias_3_token[2] ;
assign ias_3_token_BIT_3___h27583 = ias_3_token[3] ;
assign ias_3_token_BIT_4___h27690 = ias_3_token[4] ;
assign ias_4_token_BIT_0___h34302 = ias_4_token[0] ;
assign ias_4_token_BIT_1___h34409 = ias_4_token[1] ;
assign ias_4_token_BIT_2___h34516 = ias_4_token[2] ;
assign ias_4_token_BIT_3___h34623 = ias_4_token[3] ;
assign ias_4_token_BIT_4___h34730 = ias_4_token[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
ias_0_token <= `BSV_ASSIGNMENT_DELAY 5'd1;
ias_1_token <= `BSV_ASSIGNMENT_DELAY 5'd2;
ias_2_token <= `BSV_ASSIGNMENT_DELAY 5'd4;
ias_3_token <= `BSV_ASSIGNMENT_DELAY 5'd8;
ias_4_token <= `BSV_ASSIGNMENT_DELAY 5'd16;
end
else
begin
if (ias_0_token$EN)
ias_0_token <= `BSV_ASSIGNMENT_DELAY ias_0_token$D_IN;
if (ias_1_token$EN)
ias_1_token <= `BSV_ASSIGNMENT_DELAY ias_1_token$D_IN;
if (ias_2_token$EN)
ias_2_token <= `BSV_ASSIGNMENT_DELAY ias_2_token$D_IN;
if (ias_3_token$EN)
ias_3_token <= `BSV_ASSIGNMENT_DELAY ias_3_token$D_IN;
if (ias_4_token$EN)
ias_4_token <= `BSV_ASSIGNMENT_DELAY ias_4_token$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
ias_0_token = 5'h0A;
ias_1_token = 5'h0A;
ias_2_token = 5'h0A;
ias_3_token = 5'h0A;
ias_4_token = 5'h0A;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkRouterInputArbitersRoundRobin
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2013, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : cur_mb.v
// Author : Yibo FAN
// Created : 2013-12-28
// Description : Current MB
//
//-------------------------------------------------------------------
//
// Modified : 2014-07-17 by HLL
// Description : lcu size changed into 64x64 (prediction to 64x64 block remains to be added)
// Modified : 2014-08-23 by HLL
// Description : optional mode for minimal tu size added
// Modified : 2015-03-12 by HLL
// Description : ping-pong logic removed
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module cur_mb (
clk ,
rst_n ,
mb_x_i ,
mb_y_i ,
pre_min_size_i ,
start_i ,
done_o ,
pinc_o ,
pvalid_i ,
pdata_i ,
fmeif_bank_i ,
fmeif_ren_i ,
fmeif_size_i ,
fmeif_4x4_x_i ,
fmeif_4x4_y_i ,
fmeif_idx_i ,
fmeif_data_o ,
tqif_sel_i ,
tqif_ren_i ,
tqif_size_i ,
tqif_4x4_x_i ,
tqif_4x4_y_i ,
tqif_idx_i ,
tqif_data_o ,
intraif_md_ren_i ,
intraif_md_addr_i ,
intraif_md_data_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock
input rst_n ; //reset signal
// ctrl if
input [`PIC_X_WIDTH-1 : 0] mb_x_i ; // load mb x
input [`PIC_Y_WIDTH-1 : 0] mb_y_i ; // load mb y
input pre_min_size_i ; // minimal tu size
input start_i ; // start load new mb from outside
output done_o ; // load done
// pixel if
output pinc_o ; // read next pixel
input pvalid_i ; // pixel valid for input
input [`PIXEL_WIDTH*8-1 : 0] pdata_i ; // pixel data : 8 pixel input parallel
// fme if
input fmeif_ren_i ; // cmb read enable
input [1 : 0] fmeif_bank_i ; // 0x: luma, 10: cb; 11:cr
input [1 : 0] fmeif_size_i ; // cmb read size (00:4x4 01:8x8 10:16x16 11:32x32)
input [4 : 0] fmeif_idx_i ; // read index ({blk_index, line_number})
input [3 : 0] fmeif_4x4_x_i ; // cmb read block top/left 4x4 x
input [3 : 0] fmeif_4x4_y_i ; // cmb read block top/left 4x4 y
output [`PIXEL_WIDTH*32-1 : 0] fmeif_data_o ; // pixel data
// tq if
input tqif_sel_i ; // luma/chroma selector
input tqif_ren_i ; // cmb read enable
input [1 : 0] tqif_size_i ; // cmb read size (00:4x4 01:8x8 10:16x16 11:32x32)
input [4 : 0] tqif_idx_i ; // read index ({blk_index, line_number})
input [3 : 0] tqif_4x4_x_i ; // cmb read block top/left 4x4 x
input [3 : 0] tqif_4x4_y_i ; // cmb read block top/left 4x4 y
output [`PIXEL_WIDTH*32-1 : 0] tqif_data_o ; // pixel data
// intra if
input intraif_md_ren_i ; // intra predicted mode read enable
input [9 : 0] intraif_md_addr_i ; // intra predicted mode read address
output [5 : 0] intraif_md_data_o ; // intra predicted mode read data
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg done_o ;
reg imode_sel ;
reg cmb_sel ;
reg imode_sel_r ;
reg cmb_sel_r ;
integer cmb_tp ;
integer mode_amount ;
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire [5:0] intraif_md_data_0, intraif_md_data_1;
wire [`PIXEL_WIDTH*32-1:0] tqif_data_0, tqif_data_1;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(posedge clk) begin
if (start_i) begin
imode_sel_r <= 1 ;
cmb_sel_r <= 1 ;
end
end
assign intraif_md_data_o = imode_sel_r ? intraif_md_data_1 : intraif_md_data_0;
assign tqif_data_o = cmb_sel_r ? tqif_data_1 : tqif_data_0 ;
buf_ram_1p_6x85 imode_buf_0(
.clk ( clk ),
.ce ( intraif_md_ren_i ),
.we ( 1'b0 ),
.addr ( intraif_md_addr_i ),
.data_i ( 6'b0 ),
.data_o ( intraif_md_data_0 )
);
buf_ram_1p_6x85 imode_buf_1(
.clk ( clk ),
.ce ( intraif_md_ren_i ),
.we ( 1'b0 ),
.addr ( intraif_md_addr_i ),
.data_i ( 6'b0 ),
.data_o ( intraif_md_data_1 )
);
mem_lipo_1p cmb_buf_0 (
.clk ( clk ),
.rst_n ( rst_n ),
.a_wen_i ( 1'b0 ),
.a_addr_i ( 8'b0 ),
.a_wdata_i ( 256'b0 ),
.b_ren_i ( tqif_ren_i ),
.b_sel_i ( tqif_sel_i ),
.b_size_i ( tqif_size_i ),
.b_4x4_x_i ( tqif_4x4_x_i ),
.b_4x4_y_i ( tqif_4x4_y_i ),
.b_idx_i ( tqif_idx_i ),
.b_rdata_o ( tqif_data_0 )
);
mem_lipo_1p cmb_buf_1 (
.clk ( clk ),
.rst_n ( rst_n ),
.a_wen_i ( 1'b0 ),
.a_addr_i ( 8'b0 ),
.a_wdata_i ( 256'b0 ),
.b_ren_i ( tqif_ren_i ),
.b_sel_i ( tqif_sel_i ),
.b_size_i ( tqif_size_i ),
.b_4x4_x_i ( tqif_4x4_x_i ),
.b_4x4_y_i ( tqif_4x4_y_i ),
.b_idx_i ( tqif_idx_i ),
.b_rdata_o ( tqif_data_1 )
);
// -------------------------------------------------------
// CMB LOAD Pixel Simulator
// -------------------------------------------------------
localparam YUV_FILE = "./tv/cur_mb_p32.dat";
localparam IMODE_FILE = "./tv/intra_mode.dat";
reg [`PIXEL_WIDTH*32-1:0] scan_pixel_32;
reg [5:0] scan_intra_mode;
integer i, fp_input, fp_intra_mode;
initial begin
fp_input = $fopen( YUV_FILE ,"r" );
fp_intra_mode = $fopen( IMODE_FILE ,"r" );
done_o = 0 ;
cmb_sel = 0 ;
imode_sel = 0 ;
mode_amount = 0 ;
end
always @(posedge clk) begin
if (start_i) begin
if( pre_min_size_i=='d1 )
mode_amount = 21 ;
else begin
mode_amount = 85 ;
end
if (cmb_sel == 'd0) begin
// load luma
for (i=0; i<32; i=i+1) begin
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_1.buf_org_0.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_1.buf_org_1.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_1.buf_org_2.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_1.buf_org_3.u_ram_1p_64x192.mem_array[i*4+0]} =
{scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8-1 :`PIXEL_WIDTH*0]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_1.buf_org_0.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_1.buf_org_1.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_1.buf_org_2.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_1.buf_org_3.u_ram_1p_64x192.mem_array[i*4+1]} =
{scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_1.buf_org_0.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_1.buf_org_1.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_1.buf_org_2.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_1.buf_org_3.u_ram_1p_64x192.mem_array[i*4+2]} =
{scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_1.buf_org_0.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_1.buf_org_1.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_1.buf_org_2.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_1.buf_org_3.u_ram_1p_64x192.mem_array[i*4+3]} =
{scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24]};
end
// load chroma
for (i=0; i<16; i=i+1) begin
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_1.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_1.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_1.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_1.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+0]} =
{scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_1.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_1.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_1.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_1.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+1]} =
{scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_1.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_1.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_1.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_1.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+2]} =
{scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_1.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_1.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_1.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_1.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+3]} =
{scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24]};
end
// Load Mode
for (i=0; i<mode_amount*4; i=i+1) begin
cmb_tp = $fscanf(fp_intra_mode, "%h", scan_intra_mode);
imode_buf_1.u_ram_1p_6x85.mem_array[i] = scan_intra_mode;
end
cmb_tp = $fscanf(fp_intra_mode, "%h", scan_intra_mode);
end
else if (cmb_sel == 'd1) begin
// load luma
for (i=0; i<32; i=i+1) begin
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[i*4+0],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[i*4+0]} =
{scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8-1 :`PIXEL_WIDTH*0]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[i*4+1],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[i*4+1]} =
{scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[i*4+2],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[i*4+2]} =
{scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[i*4+3],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[i*4+3]} =
{scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24]};
end
// load chroma
for (i=0; i<16; i=i+1) begin
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+0],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+0]} =
{scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+1],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+1]} =
{scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+2],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+2]} =
{scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24],
scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ]};
cmb_tp = $fscanf(fp_input, "%h", scan_pixel_32 );
{cmb_buf_0.buf_org_0.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_0.buf_org_1.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_0.buf_org_2.u_ram_1p_64x192.mem_array[128+i*4+3],
cmb_buf_0.buf_org_3.u_ram_1p_64x192.mem_array[128+i*4+3]} =
{scan_pixel_32[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*8 ],
scan_pixel_32[`PIXEL_WIDTH*24-1:`PIXEL_WIDTH*16],
scan_pixel_32[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*0 ],
scan_pixel_32[`PIXEL_WIDTH*32-1:`PIXEL_WIDTH*24]};
end
// Load Mode
for (i=0; i<mode_amount*4; i=i+1) begin
cmb_tp = $fscanf(fp_intra_mode, "%h", scan_intra_mode);
imode_buf_0.u_ram_1p_6x85.mem_array[i] = scan_intra_mode;
end
cmb_tp = $fscanf(fp_intra_mode, "%h", scan_intra_mode);
end
// cmb_sel <= ~cmb_sel ;
// imode_sel <= ~imode_sel;
#55 done_o <= 1'b1;
#10 done_o <= 1'b0;
end
end
endmodule
|
module asyc_sub_tb;
reg reset = 1;
reg button = 0;
reg clk = 0;
wire [6:0] leds;
asyc_sub sub1(leds, reset, button, clk);
initial begin
$monitor($time, " reset: %b, button: %b, digit: %b, leds: %b",
reset, button, sub1.digit, leds);
#0 reset = 1'b0;
#10 reset = 1'b1;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#10 reset = 1'b0;
#10 reset = 1'b1;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
end
initial forever #1 clk <= ~clk;
initial #400 $finish;
endmodule
|
(*
Copyright © 2006 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Import CoRN.algebra.RSetoid.
Require Import CoRN.metric2.Metric.
Require Import CoRN.metric2.UniformContinuity.
Require Export CoRN.reals.fast.CRArith.
Require Import CoRN.reals.fast.CRIR.
Require Import CoRN.reals.Q_in_CReals.
Require Import CoRN.model.totalorder.QMinMax.
Require Import CoRN.reals.fast.CRarctan_small.
Require Import CoRN.transc.MoreArcTan.
Require Import CoRN.tactics.CornTac.
Require Import MathClasses.interfaces.abstract_algebra.
Require Import CoRN.stdlib_omissions.Q.
Set Implicit Arguments.
Local Open Scope Q_scope.
Local Open Scope uc_scope.
Opaque inj_Q CR.
(**
** Pi
(Please import CRpi instead)
This version is faster to compute than CRpi_slow; however it is slower to
compile.
Pi is defined as
176*arctan(1/57) + 28*arctan(1/239) - 48*arctan(1/682) + 96*arctan(1/12943).
*)
Section Pi.
Lemma small_per_57 : (0 <= (1#(57%positive)) < 1)%Q.
Proof. split; easy. Qed.
Lemma small_per_239 : (0 <= (1#(239%positive)) < 1)%Q.
Proof. split; easy. Qed.
Lemma small_per_682 : (0 <= (1#(682%positive)) < 1)%Q.
Proof. split; easy. Qed.
Lemma small_per_12943 : (0 <= (1#(12943%positive)) < 1)%Q.
Proof. split; easy. Qed.
Definition r_pi (r:Q) : CR :=
((scale (176%Z*r) (rational_arctan_small_pos small_per_57) +
scale (28%Z*r) (rational_arctan_small_pos small_per_239)) +
(scale (-(48%Z)*r) (rational_arctan_small_pos small_per_682) +
scale (96%Z*r) (rational_arctan_small_pos small_per_12943)))%CR.
(** To prove that pi is is correct we repeatedly use the arctan sum law.
The problem is that the arctan sum law only works for input between -1
and 1. We use reflect to show that our use of arctan sum law always
satifies this restriction. *)
Let f (a b:Q) : Q :=
let (x,y) := a in
let (z,w) := b in
Qred ((x*w + y*z)%Z/(y*w-x*z)%Z).
Lemma f_char : forall a b, f a b == (a+b)/(1-a*b).
Proof.
intros [x y] [w z].
unfold f.
rewrite -> Qred_correct.
destruct (Z.eq_dec (y*z) (x*w)) as [H|H].
unfold Qmult.
simpl ((Qnum (x # y) * Qnum (w # z) # Qden (x # y) * Qden (w # z))).
repeat rewrite <- H.
replace (y * z - y * z)%Z with 0%Z by ring.
setoid_replace (1-(y * z # y * z)) with 0.
change ((x * z + y * w)%Z * 0 == ((x # y) + (w # z)) * 0).
ring.
rewrite -> (Qmake_Qdiv (y*z)).
change (1 - (y * z)%positive / (y * z)%positive == 0).
field; discriminate.
unfold Zminus.
repeat rewrite -> injz_plus.
change (((x * Zpos z) + (Zpos y * w)) / (Zpos y * Zpos z - x * w) == ((x # y) + (w # z)) / (1 - (x #y)*(w # z))).
repeat rewrite -> Qmake_Qdiv.
field.
repeat split; try discriminate.
cut (~(y * z)%Z == (x * w)%Z).
intros X Y.
apply X.
replace RHS with ((x * w)%Z + 0) by simpl; ring.
rewrite <- Y.
change ((y * z) == (x * w) + (y * z - x * w)).
ring.
intros X; apply H.
unfold Qeq in X.
simpl in X.
rewrite Pmult_1_r in X.
change ((y * z)%Z = (x * w * 1)%Z) in X.
rewrite X.
ring.
Qed.
Lemma ArcTan_plus_ArcTan_Q : forall x y, -(1) <= x <= 1 -> -(1) <= y <= 1 -> ~1-x*y==0 ->
(ArcTan (inj_Q _ x)[+]ArcTan (inj_Q _ y)[=]ArcTan (inj_Q _ (f x y))).
Proof.
intros x y [Hx0 Hx1] [Hy0 Hy1] H.
assert (X:forall z, -(1) <= z -> [--][1][<=]inj_Q IR z).
intros z Hz.
stepl ((inj_Q IR (-(1)))).
apply inj_Q_leEq; assumption.
eapply eq_transitive.
apply (inj_Q_inv IR (1)).
apply un_op_wd_unfolded.
rstepr (nring 1:IR).
apply (inj_Q_nring IR 1).
assert (X0:forall z, z <= 1 -> inj_Q IR z[<=][1]).
intros z Hz.
stepr ((inj_Q IR ((1)))).
apply inj_Q_leEq; assumption.
rstepr (nring 1:IR).
apply (inj_Q_nring IR 1).
assert ([1][-](inj_Q IR x)[*](inj_Q IR y)[#][0]).
stepl (inj_Q IR (1[-]x[*]y)).
(stepr (inj_Q IR [0]); [| now apply (inj_Q_nring IR 0)]).
apply inj_Q_ap; assumption.
eapply eq_transitive.
apply inj_Q_minus.
apply bin_op_wd_unfolded.
rstepr (nring 1:IR); apply (inj_Q_nring IR 1).
apply un_op_wd_unfolded.
apply inj_Q_mult.
apply eq_transitive with (ArcTan (inj_Q IR x[+]inj_Q IR y[/]([1][-]inj_Q IR x[*]inj_Q IR y)[//]X1)).
apply ArcTan_plus_ArcTan; first [apply X; assumption |apply X0; assumption].
apply ArcTan_wd.
stepl (inj_Q IR ((x[+]y)/([1][-]x*y))).
apply inj_Q_wd.
simpl.
symmetry.
apply f_char.
assert (H0:(inj_Q IR ([1][-]x * y))[#][0]).
(stepr (inj_Q IR 0); [| now apply (inj_Q_nring IR 0)]).
apply inj_Q_ap; assumption.
apply eq_transitive with (inj_Q IR (x[+]y)[/]inj_Q IR ([1][-]x * y)[//]H0).
apply (inj_Q_div).
apply div_wd.
apply inj_Q_plus.
eapply eq_transitive.
apply inj_Q_minus.
apply bin_op_wd_unfolded.
rstepr (nring 1:IR).
apply (inj_Q_nring IR 1).
apply un_op_wd_unfolded.
apply inj_Q_mult.
Qed.
Definition ArcTan_multiple : forall x, -(1) <= x <= 1 -> forall n,
sumbool True ((nring n)[*]ArcTan (inj_Q _ x)[=]ArcTan (inj_Q _ (iter_nat n _ (f x) 0))).
Proof.
intros x Hx.
induction n.
right.
abstract ( rstepl ([0]:IR); (stepl (ArcTan [0]); [| now apply ArcTan_zero]); apply ArcTan_wd;
apply eq_symmetric; apply (inj_Q_nring IR 0)).
simpl.
destruct (IHn) as [H|H].
left; constructor.
set (y:=(iter_nat n Q (f x) 0)) in *.
destruct (Qlt_le_dec_fast 1 y) as [_|Y0].
left; constructor.
destruct (Qlt_le_dec_fast y (-(1))) as [_|Y1].
left; constructor.
destruct (Qeq_dec (1-x*y) 0) as [_|Y2].
left; constructor.
right.
abstract ( rstepl (ArcTan (inj_Q IR x)[+](nring n[*]ArcTan (inj_Q IR x))); csetoid_rewrite H;
apply ArcTan_plus_ArcTan_Q; try assumption; split; assumption).
Defined.
Lemma reflect_right : forall A B (x:{A}+{B}), (match x with left _ => False | right _ => True end) -> B.
Proof.
intros A B x.
elim x.
contradiction.
trivial.
Qed.
Lemma Pi_Formula :
(((nring 44)[*]ArcTan (inj_Q IR (1 / 57%Z))[-]
(nring 12)[*]ArcTan (inj_Q IR (1 / 682%Z))[+]
(nring 7)[*]ArcTan (inj_Q IR (1 / 239%Z))[+]
(nring 24)[*]ArcTan (inj_Q IR (1 / 12943%Z)))[=]
Pi[/]FourNZ).
Proof.
assert (H0:-(1) <= (1/(57%Z)) <= 1).
split; discriminate.
assert (H1:-(1) <= (1/(239%Z)) <= 1).
split; discriminate.
assert (H2:-(1) <= (1/(682%Z)) <= 1).
split; discriminate.
assert (H3:-(1) <= (1/(12943%Z)) <= 1).
split; discriminate.
set (y0:=(iter_nat 44 _ (f (1/57%Z)) 0)).
set (y1:=(iter_nat 7 _ (f (1/239%Z)) 0)).
set (y2:=(iter_nat 12 _ (f (1/682%Z)) 0)).
set (y3:=(iter_nat 24 _ (f (1/12943%Z)) 0)).
rstepl (nring 44[*]ArcTan (inj_Q IR (1 / 57%Z))[+]
[--](nring 12[*]ArcTan (inj_Q IR (1 / 682%Z)))[+]
(nring 7[*]ArcTan (inj_Q IR (1 / 239%Z))[+]
nring 24[*]ArcTan (inj_Q IR (1 / 12943%Z)))).
csetoid_replace ((nring 44)[*]ArcTan (inj_Q IR (1 / 57%Z)))
(ArcTan (inj_Q IR y0)); [|apply: (reflect_right (ArcTan_multiple H0 44)); now vm_compute].
csetoid_replace ((nring 7)[*]ArcTan (inj_Q IR (1 / 239%Z))) (ArcTan (inj_Q IR y1));
[|apply: (reflect_right (ArcTan_multiple H1 7)); now vm_compute].
csetoid_replace ((nring 12)[*]ArcTan (inj_Q IR (1 / 682%Z))) (ArcTan (inj_Q IR y2));
[|apply: (reflect_right (ArcTan_multiple H2 12)); now vm_compute].
csetoid_replace ((nring 24)[*]ArcTan (inj_Q IR (1 / 12943%Z))) (ArcTan (inj_Q IR y3));
[|apply: (reflect_right (ArcTan_multiple H3 24)); now vm_compute].
vm_compute in y0.
vm_compute in y1.
vm_compute in y2.
vm_compute in y3.
csetoid_replace ([--](ArcTan (inj_Q IR y2))) (ArcTan (inj_Q IR (-y2)));
[|csetoid_rewrite_rev (ArcTan_inv (inj_Q IR y2));
apply ArcTan_wd; apply eq_symmetric; apply (inj_Q_inv IR y2)].
csetoid_replace (ArcTan (inj_Q IR y0)[+]ArcTan (inj_Q IR (-y2))) (ArcTan (inj_Q IR (f y0 (-y2))));
[|apply ArcTan_plus_ArcTan_Q; try split; now vm_compute].
csetoid_replace (ArcTan (inj_Q IR y1)[+]ArcTan (inj_Q IR y3)) (ArcTan (inj_Q IR (f y1 y3)));
[|apply ArcTan_plus_ArcTan_Q; try split; now vm_compute].
set (z0 := (f y0 (-y2))).
set (z1 := (f y1 y3)).
vm_compute in z0.
vm_compute in z1.
csetoid_replace (ArcTan (inj_Q IR z0)[+]ArcTan (inj_Q IR z1)) (ArcTan (inj_Q IR (f z0 z1)));
[|apply ArcTan_plus_ArcTan_Q; try split; now vm_compute].
set (z3:= (f z0 z1)).
vm_compute in z3.
eapply eq_transitive;[|apply ArcTan_one].
apply ArcTan_wd.
rstepr (nring 1:IR).
apply (inj_Q_nring IR 1).
Qed.
Lemma r_pi_correct : forall r, (r_pi r == IRasCR ((inj_Q IR r)[*]Pi))%CR.
Proof.
intros r.
unfold r_pi.
repeat rewrite <- (CRmult_scale).
setoid_replace (176%Z* r) with (4%Z * r * 44%Z) by (simpl; ring).
setoid_replace (28%Z * r) with (4%Z * r * 7%Z) by (simpl; ring).
setoid_replace (-(48)%Z * r) with (4%Z * r * -(12)%Z) by (simpl; ring).
setoid_replace (96%Z * r) with (4%Z * r * 24%Z) by (simpl; ring).
repeat rewrite <- CRmult_Qmult.
transitivity ('4%Z * 'r *(' 44%Z * rational_arctan_small_pos small_per_57 +
' 7%Z * rational_arctan_small_pos small_per_239 +
(' (-12)%Z * rational_arctan_small_pos small_per_682 +
' 24%Z * rational_arctan_small_pos small_per_12943)))%CR.
ring.
repeat rewrite rational_arctan_small_pos_correct.
repeat rewrite <- IR_inj_Q_as_CR.
repeat (rewrite <- IR_mult_as_CR || rewrite <- IR_plus_as_CR).
apply IRasCR_wd.
rstepr (Four[*]inj_Q IR r[*]Pi[/]FourNZ).
apply mult_wd.
apply mult_wdl.
apply (inj_Q_nring IR 4).
eapply eq_transitive;[|apply Pi_Formula].
rstepr (nring 44[*]ArcTan (inj_Q IR (1 / 57%Z))[+]
nring 7[*]ArcTan (inj_Q IR (1 / 239%Z))[+]
(([--](nring 12))[*]ArcTan (inj_Q IR (1 / 682%Z))[+]
nring 24[*]ArcTan (inj_Q IR (1 / 12943%Z)))).
repeat apply bin_op_wd_unfolded; try apply eq_reflexive.
apply (inj_Q_nring IR 44).
apply (inj_Q_nring IR 7).
eapply eq_transitive.
apply (inj_Q_inv IR (nring 12)).
csetoid_rewrite (inj_Q_nring IR 12).
apply eq_reflexive.
apply (inj_Q_nring IR 24).
Qed.
Global Instance: Proper (Qeq ==> msp_eq) r_pi.
Proof.
intros ? ? E. unfold r_pi.
apply ucFun2_wd.
apply ucFun2_wd.
apply Cmap_wd. 2: reflexivity. simpl.
split. discriminate. intro q. simpl.
unfold Qmetric.Qball, Qmetric.QAbsSmall.
rewrite E. unfold Qminus. rewrite Qplus_opp_r.
split; discriminate.
apply Cmap_wd. 2: reflexivity. simpl.
split. discriminate. intro q. simpl.
unfold Qmetric.Qball, Qmetric.QAbsSmall.
rewrite E. unfold Qminus. rewrite Qplus_opp_r.
split; discriminate.
apply ucFun2_wd.
apply Cmap_wd. 2: reflexivity. simpl.
split. discriminate. intro q. simpl.
unfold Qmetric.Qball, Qmetric.QAbsSmall.
rewrite E. unfold Qminus. rewrite Qplus_opp_r.
split; discriminate.
apply Cmap_wd. 2: reflexivity. simpl.
split. discriminate. intro q. simpl.
unfold Qmetric.Qball, Qmetric.QAbsSmall.
rewrite E. unfold Qminus. rewrite Qplus_opp_r.
split; discriminate.
Qed.
Definition CRpi : CR := (r_pi 1).
Lemma CRpi_correct : (IRasCR Pi == CRpi)%CR.
Proof.
unfold CRpi.
rewrite -> r_pi_correct.
apply IRasCR_wd.
rstepl ((nring 1)[*]Pi).
apply mult_wdl.
apply eq_symmetric.
apply (inj_Q_nring IR 1).
Qed.
End Pi.
(* begin hide *)
Hint Rewrite CRpi_correct : IRtoCR.
(* end hide *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N (
Q ,
D ,
CLK ,
SET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input SET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* IP ethernet frame receiver (Ethernet frame in, IP frame out, 64 bit datapath)
*/
module ip_eth_rx_64
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_header_early_termination,
output wire error_payload_early_termination,
output wire error_invalid_header,
output wire error_invalid_checksum
);
/*
IP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
payload length octets
This module receives an Ethernet frame with header fields in parallel and
payload on an AXI stream interface, decodes and strips the IP header fields,
then produces the header fields in parallel along with the IP payload in a
separate AXI stream.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_READ_HEADER = 3'd1,
STATE_READ_PAYLOAD = 3'd2,
STATE_READ_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_eth_hdr;
reg store_hdr_word_0;
reg store_hdr_word_1;
reg store_hdr_word_2;
reg store_last_word;
reg flush_save;
reg transfer_in_save;
reg [5:0] hdr_ptr_reg = 6'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [16:0] hdr_sum_high_reg = 17'd0;
reg [16:0] hdr_sum_low_reg = 17'd0;
reg [19:0] hdr_sum_temp;
reg [19:0] hdr_sum_reg = 20'd0, hdr_sum_next;
reg check_hdr_reg = 1'b0, check_hdr_next;
reg [63:0] last_word_data_reg = 64'd0;
reg [7:0] last_word_keep_reg = 8'd0;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg busy_reg = 1'b0;
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
reg error_invalid_header_reg = 1'b0, error_invalid_header_next;
reg error_invalid_checksum_reg = 1'b0, error_invalid_checksum_next;
reg [63:0] save_eth_payload_axis_tdata_reg = 64'd0;
reg [7:0] save_eth_payload_axis_tkeep_reg = 8'd0;
reg save_eth_payload_axis_tlast_reg = 1'b0;
reg save_eth_payload_axis_tuser_reg = 1'b0;
reg [63:0] shift_eth_payload_axis_tdata;
reg [7:0] shift_eth_payload_axis_tkeep;
reg shift_eth_payload_axis_tvalid;
reg shift_eth_payload_axis_tlast;
reg shift_eth_payload_axis_tuser;
reg shift_eth_payload_s_tready;
reg shift_eth_payload_extra_cycle_reg = 1'b0;
// internal datapath
reg [63:0] m_ip_payload_axis_tdata_int;
reg [7:0] m_ip_payload_axis_tkeep_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign busy = busy_reg;
assign error_header_early_termination = error_header_early_termination_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
assign error_invalid_header = error_invalid_header_reg;
assign error_invalid_checksum = error_invalid_checksum_reg;
function [3:0] keep2count;
input [7:0] k;
casez (k)
8'bzzzzzzz0: keep2count = 4'd0;
8'bzzzzzz01: keep2count = 4'd1;
8'bzzzzz011: keep2count = 4'd2;
8'bzzzz0111: keep2count = 4'd3;
8'bzzz01111: keep2count = 4'd4;
8'bzz011111: keep2count = 4'd5;
8'bz0111111: keep2count = 4'd6;
8'b01111111: keep2count = 4'd7;
8'b11111111: keep2count = 4'd8;
endcase
endfunction
function [7:0] count2keep;
input [3:0] k;
case (k)
4'd0: count2keep = 8'b00000000;
4'd1: count2keep = 8'b00000001;
4'd2: count2keep = 8'b00000011;
4'd3: count2keep = 8'b00000111;
4'd4: count2keep = 8'b00001111;
4'd5: count2keep = 8'b00011111;
4'd6: count2keep = 8'b00111111;
4'd7: count2keep = 8'b01111111;
4'd8: count2keep = 8'b11111111;
endcase
endfunction
always @* begin
shift_eth_payload_axis_tdata[31:0] = save_eth_payload_axis_tdata_reg[63:32];
shift_eth_payload_axis_tkeep[3:0] = save_eth_payload_axis_tkeep_reg[7:4];
if (shift_eth_payload_extra_cycle_reg) begin
shift_eth_payload_axis_tdata[63:32] = 32'd0;
shift_eth_payload_axis_tkeep[7:4] = 4'd0;
shift_eth_payload_axis_tvalid = 1'b1;
shift_eth_payload_axis_tlast = save_eth_payload_axis_tlast_reg;
shift_eth_payload_axis_tuser = save_eth_payload_axis_tuser_reg;
shift_eth_payload_s_tready = flush_save;
end else begin
shift_eth_payload_axis_tdata[63:32] = s_eth_payload_axis_tdata[31:0];
shift_eth_payload_axis_tkeep[7:4] = s_eth_payload_axis_tkeep[3:0];
shift_eth_payload_axis_tvalid = s_eth_payload_axis_tvalid;
shift_eth_payload_axis_tlast = (s_eth_payload_axis_tlast && (s_eth_payload_axis_tkeep[7:4] == 0));
shift_eth_payload_axis_tuser = (s_eth_payload_axis_tuser && (s_eth_payload_axis_tkeep[7:4] == 0));
shift_eth_payload_s_tready = !(s_eth_payload_axis_tlast && s_eth_payload_axis_tvalid && transfer_in_save);
end
end
always @* begin
state_next = STATE_IDLE;
flush_save = 1'b0;
transfer_in_save = 1'b0;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
store_eth_hdr = 1'b0;
store_hdr_word_0 = 1'b0;
store_hdr_word_1 = 1'b0;
store_hdr_word_2 = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
hdr_sum_temp = 32'd0;
hdr_sum_next = hdr_sum_reg;
check_hdr_next = check_hdr_reg;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
error_header_early_termination_next = 1'b0;
error_payload_early_termination_next = 1'b0;
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_payload_axis_tdata_int = 64'd0;
m_ip_payload_axis_tkeep_int = 8'd0;
m_ip_payload_axis_tvalid_int = 1'b0;
m_ip_payload_axis_tlast_int = 1'b0;
m_ip_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for header
hdr_ptr_next = 6'd0;
hdr_sum_next = 32'd0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b1;
store_eth_hdr = 1'b1;
state_next = STATE_READ_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_READ_HEADER: begin
// read header
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
word_count_next = m_ip_length_reg - 5*4;
if (s_eth_payload_axis_tvalid) begin
// word transfer in - store it
hdr_ptr_next = hdr_ptr_reg + 6'd8;
transfer_in_save = 1'b1;
state_next = STATE_READ_HEADER;
case (hdr_ptr_reg)
6'h00: begin
store_hdr_word_0 = 1'b1;
end
6'h08: begin
store_hdr_word_1 = 1'b1;
hdr_sum_next = hdr_sum_high_reg + hdr_sum_low_reg;
end
6'h10: begin
store_hdr_word_2 = 1'b1;
hdr_sum_next = hdr_sum_reg + hdr_sum_high_reg + hdr_sum_low_reg;
// check header checksum on next cycle for improved timing
check_hdr_next = 1'b1;
if (m_ip_version_reg != 4'd4 || m_ip_ihl_reg != 4'd5) begin
error_invalid_header_next = 1'b1;
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
state_next = STATE_WAIT_LAST;
end else begin
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
state_next = STATE_READ_PAYLOAD;
end
end
endcase
if (shift_eth_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_hdr_valid_next = 1'b0;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_READ_HEADER;
end
end
STATE_READ_PAYLOAD: begin
// read payload
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
m_ip_payload_axis_tdata_int = shift_eth_payload_axis_tdata;
m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep;
m_ip_payload_axis_tvalid_int = shift_eth_payload_axis_tvalid;
m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast;
m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser;
store_last_word = 1'b1;
if (m_ip_payload_axis_tready_int_reg && shift_eth_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd8;
transfer_in_save = 1'b1;
if (word_count_reg <= 8) begin
// have entire payload
m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep & count2keep(word_count_reg);
if (shift_eth_payload_axis_tlast) begin
if (keep2count(shift_eth_payload_axis_tkeep) < word_count_reg[4:0]) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
end
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
m_ip_payload_axis_tvalid_int = 1'b0;
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
if (shift_eth_payload_axis_tlast) begin
// end of frame, but length does not match
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD;
end
end
end else begin
state_next = STATE_READ_PAYLOAD;
end
if (check_hdr_reg) begin
check_hdr_next = 1'b0;
hdr_sum_temp = hdr_sum_reg[15:0] + hdr_sum_reg[19:16] + hdr_sum_low_reg;
if (hdr_sum_temp != 19'h0ffff && hdr_sum_temp != 19'h1fffe) begin
// bad checksum
error_invalid_checksum_next = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b0;
if (shift_eth_payload_axis_tlast && shift_eth_payload_axis_tvalid) begin
// only one payload cycle; return to idle now
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg && !check_hdr_reg;
state_next = STATE_IDLE;
end else begin
// drop payload
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
state_next = STATE_WAIT_LAST;
end
end else begin
// good checksum; transfer header
m_ip_hdr_valid_next = 1'b1;
end
end
end
STATE_READ_PAYLOAD_LAST: begin
// read and discard until end of frame
s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early && shift_eth_payload_s_tready;
m_ip_payload_axis_tdata_int = last_word_data_reg;
m_ip_payload_axis_tkeep_int = last_word_keep_reg;
m_ip_payload_axis_tvalid_int = shift_eth_payload_axis_tvalid && shift_eth_payload_axis_tlast;
m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast;
m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser;
if (m_ip_payload_axis_tready_int_reg && shift_eth_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// read and discard until end of frame
s_eth_payload_axis_tready_next = shift_eth_payload_s_tready;
if (shift_eth_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 1'b0;
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_extra_cycle_reg <= 1'b0;
busy_reg <= 1'b0;
error_header_early_termination_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
error_invalid_header_reg <= 1'b0;
error_invalid_checksum_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
error_header_early_termination_reg <= error_header_early_termination_next;
error_payload_early_termination_reg <= error_payload_early_termination_next;
error_invalid_header_reg <= error_invalid_header_next;
error_invalid_checksum_reg <= error_invalid_checksum_next;
busy_reg <= state_next != STATE_IDLE;
// datapath
if (flush_save) begin
save_eth_payload_axis_tlast_reg <= 1'b0;
shift_eth_payload_extra_cycle_reg <= 1'b0;
end else if (transfer_in_save) begin
save_eth_payload_axis_tlast_reg <= s_eth_payload_axis_tlast;
shift_eth_payload_extra_cycle_reg <= s_eth_payload_axis_tlast && (s_eth_payload_axis_tkeep[7:4] != 0);
end
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
hdr_sum_reg <= hdr_sum_next;
check_hdr_reg <= check_hdr_next;
if (s_eth_payload_axis_tvalid) begin
hdr_sum_low_reg <= s_eth_payload_axis_tdata[15:0] + s_eth_payload_axis_tdata[31:16];
hdr_sum_high_reg <= s_eth_payload_axis_tdata[47:32] + s_eth_payload_axis_tdata[63:48];
end
// datapath
if (store_eth_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
end
if (store_last_word) begin
last_word_data_reg <= m_ip_payload_axis_tdata_int;
last_word_keep_reg <= m_ip_payload_axis_tkeep_int;
end
if (store_hdr_word_0) begin
{m_ip_version_reg, m_ip_ihl_reg} <= s_eth_payload_axis_tdata[ 7: 0];
{m_ip_dscp_reg, m_ip_ecn_reg} <= s_eth_payload_axis_tdata[15: 8];
m_ip_length_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_length_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
m_ip_identification_reg[15: 8] <= s_eth_payload_axis_tdata[39:32];
m_ip_identification_reg[ 7: 0] <= s_eth_payload_axis_tdata[47:40];
{m_ip_flags_reg, m_ip_fragment_offset_reg[12:8]} <= s_eth_payload_axis_tdata[55:48];
m_ip_fragment_offset_reg[ 7:0] <= s_eth_payload_axis_tdata[63:56];
end
if (store_hdr_word_1) begin
m_ip_ttl_reg <= s_eth_payload_axis_tdata[ 7: 0];
m_ip_protocol_reg <= s_eth_payload_axis_tdata[15: 8];
m_ip_header_checksum_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_header_checksum_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
m_ip_source_ip_reg[31:24] <= s_eth_payload_axis_tdata[39:32];
m_ip_source_ip_reg[23:16] <= s_eth_payload_axis_tdata[47:40];
m_ip_source_ip_reg[15: 8] <= s_eth_payload_axis_tdata[55:48];
m_ip_source_ip_reg[ 7: 0] <= s_eth_payload_axis_tdata[63:56];
end
if (store_hdr_word_2) begin
m_ip_dest_ip_reg[31:24] <= s_eth_payload_axis_tdata[ 7: 0];
m_ip_dest_ip_reg[23:16] <= s_eth_payload_axis_tdata[15: 8];
m_ip_dest_ip_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
m_ip_dest_ip_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
end
if (transfer_in_save) begin
save_eth_payload_axis_tdata_reg <= s_eth_payload_axis_tdata;
save_eth_payload_axis_tkeep_reg <= s_eth_payload_axis_tkeep;
save_eth_payload_axis_tuser_reg <= s_eth_payload_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] m_ip_payload_axis_tkeep_reg = 8'd0;
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg m_ip_payload_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_ip_payload_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_ip_payload_axis_tkeep_reg = 8'd0;
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg temp_m_ip_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_ip_payload_int_to_output;
reg store_ip_payload_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tkeep = m_ip_payload_axis_tkeep_reg;
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_ip_payload_int_to_output = 1'b0;
store_ip_payload_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
end
// datapath
if (store_ip_payload_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tkeep_reg <= temp_m_ip_payload_axis_tkeep_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_ip_payload_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tkeep_reg <= m_ip_payload_axis_tkeep_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
end
endmodule
|
//date: 2016/3/13
//engineer :ZhaiShaoMin
//module name :ring_node
//module function: It includes network_interface , commu_assist ,core ,inst cache ,data cache and memory.
module ring_node(//input
clk,
rst,
ctrl_in, //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
flit_in,
dest_fifo_in,
en_local_req_in,
en_local_rep_in,
en_pass_req_in,
en_pass_rep_in,
used_slots_pass_req_in,
used_slots_pass_rep_in,
//output
en_local_req, // to previous node refer to below notes
en_local_rep,
en_pass_req, // from next node //local_in_req fifo in next node says that it can receive
en_pass_rep, // refer to notes below
used_slots_pass_req,
used_slots_pass_rep,
flit_out,
ctrl_out,
dest_fifo_out
);
//input
input clk;
input rst;
input [1:0] ctrl_in; //[1:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
input [15:0] flit_in;
input [1:0] dest_fifo_in;
input en_local_req_in;
input en_local_rep_in;
input en_pass_req_in;
input en_pass_rep_in;
input [3:0] used_slots_pass_req_in;
input [3:0] used_slots_pass_rep_in;
//output
output en_local_req; // to previous node refer to below notes
output en_local_rep;
output en_pass_req; // from next node //local_in_req fifo in next node says that it can receive
output en_pass_rep; // refer to notes below
output [3:0] used_slots_pass_req;
output [3:0] used_slots_pass_rep;
output [15:0] flit_out;
output [1:0] ctrl_out;
output [1:0] dest_fifo_out;
// top- down
// network interface output
wire [17:0] deq_req_data; //[17:0]cache or memory dequeue a flit from IN_local req fifo
wire [17:0] deq_rep_data; //[17:0]cache or memory dequeue a flit from IN_local rep fifo
wire en_local_req; // to previous node refer to below notes
wire en_local_rep;
wire en_pass_req; // from next node //local_in_req fifo in next node says that it can receive
wire en_pass_rep; // refer to notes below
wire [3:0] used_slots_pass_req;
wire [3:0] used_slots_pass_rep;
wire [15:0] flit_out;
wire [1:0] ctrl_out;
wire [1:0] dest_fifo_out;
wire req_rdy;
wire rep_rdy;
wire OUT_req_rdy;
wire OUT_rep_rdy;
//commu assist output
// output
wire ack_rep; // arbiter tell IN rep fifo that it's ready to receive flit,
// as well as been used by IN rep fifo as a deq rdy signal
wire ack_req; //req_rep and req_req are better!
// output
wire [1:0] OUT_req_ctrl; // used to tell the frame of msg. 00 means nothing 01 means head flit,
// 10 means body flit,11 means tail flit, exception is invrep which has only one flit.
wire [15:0] OUT_req_flit; // flit outputed to OUT req fifo
wire OUT_req_ack; // same as rdy signal saying now I'm a valid flit, also a enq signal for OUT req fifo
wire [1:0] OUT_rep_ctrl; // similar function as above
wire [15:0] OUT_rep_flit;
wire OUT_rep_ack;
wire v_inst_rep; // saying that is a valid rep data back to pipeline
wire [31:0] inst_data; // rep data (inst word) back to pipeline.
wire [143:0] flits_dcache; // arbiter select a flits to dcache
wire v_flits_dcache; // means it's a valid flits to dcache
// output
wire v_m_download; // valic flits from m_download to mem
wire [175:0] m_donwload; //flits from m_download to mem
wire v_d_m_areg; // valid flits from d_m_areg to mem
wire [175:0] d_m_areg; // flits from d_m_areg to mem
wire v_i_m_areg;
wire [31:0] i_m_areg;
wire [1:0] ic_download_fsm_state; //here are some fsm state indicating whether some state elements is idle or busy
wire m_d_areg_fsm_state; // which is useful to decide whether or not to output flits from mem to these elements
wire m_rep_fsm_state;
wire m_req_fsm_state;
wire [1:0] d_m_areg_fsm_state; // fsm state outputed from commu_assist intended to tell dcache if it's able
// to send flits to these units
wire [1:0] dc_req_fsm_state;
wire [1:0] dc_rep_fsm_state;
//dcache_cpu_network_ctrler output
//output to cpu access regs saying that data cache doesn't need cpu_addr anymore!
wire done_access_cpu_addr;
//output to tell arbiter that data cache has been accessed!
wire dcache_done_access;
//output to d_m_areg when the generated msg is a local msg
wire [175:0] flits_d_m_areg; // at most 11 flits
wire v_flits_d_m_areg;
//output to dc_upload_req regs
wire [47:0] flits_dc_upload_req; // always 3 flits
wire v_flits_dc_upload_req;
wire en_flit_max_req_d;
wire [1:0] flit_max_req_d;
//output to dc_upload_rep regs
wire [175:0] flits_dc_upload_rep; // at most 11 flits
wire v_flits_dc_upload_rep;
wire en_flit_max_rep_d;
wire [3:0] flit_max_rep_d;
// output to cpu tell whether cpu access has done
wire [31:0] data_cpu;
wire v_rep_cpu;
//inst cache output
wire v_ic_req;
wire local_or_OUT; //1:local ,0:OUT_req
wire [47:0] req_msg;
wire v_inst;
wire [31:0] inst;
//memory output
// output to local d cache
wire v_req_d;
wire v_rep_d;
wire [15:0] head_out_local_d;
wire [31:0] addr_out_local_d;
wire [127:0] data_out_local_d;
// output to local i cahce
wire v_rep_i;
wire [127:0] data_out_local_i;
// output to OUT req fifo
wire en_inv_ids;
wire [3:0] inv_ids_in;
wire [1:0] flit_max_req_m;
wire en_flit_max_req_m;
wire v_req_out;
wire [15:0] head_out_req_out;
wire [31:0] addr_out_req_out;
wire [127:0] data_out_req_out;
// output to OUT rep fifo
wire [3:0] flit_max_rep_m;
wire en_flit_max_rep_m;
wire v_rep_out;
wire [15:0] head_out_rep_out;
wire [31:0] addr_out_rep_out;
wire [127:0] data_out_rep_out;
// core output
//output
wire [31:0] pc;
wire v_pc;
wire v_mem;
wire [3:0] mem_head;
wire [31:0] mem_addr;
wire [31:0] mem_data;
network_interface my_NI (
//input
.clk(clk), //global clock
.rst(rst), //global reset
.ctrl_in(ctrl_in), //[2:0] for guiding flit flowing ; 00:nothing, 01:head flit, 10:body flit, 11:tail flit
//ctrl[2] 1:next_node; 0:not_next_node;
.flit_in(flit_in),
.dest_fifo_in(dest_fifo_in),
.en_IN_req_deq(ack_req), // from arbiter_for_IN_node in commu_assist
.en_IN_rep_deq(ack_rep),
.enq_req_data({OUT_req_ctrl,OUT_req_flit}), // from arbiter_for_OUT_req fifo in commu_assist (include ctrl)
.enq_rep_data({OUT_rep_ctrl,OUT_rep_flit}), // from arbiter_for_OUT_rep fifo in commu_assist (include ctrl)
.en_OUT_req_enq(OUT_req_ack), // from arbiter_for_OUT_req fifo in commu_assist
.en_OUT_rep_enq(OUT_rep_ack), // from arbiter_for_OUT_rep fifo in commu_assist
.en_local_req_in(en_local_req_in),
.en_local_rep_in(en_local_rep_in),
.en_pass_req_in(en_pass_req_in),
.en_pass_rep_in(en_pass_rep_in),
.used_slots_pass_req_in(used_slots_pass_req_in),
.used_slots_pass_rep_in(used_slots_pass_rep_in), //the pass req fifo of next node says it can receive a flit
//output
.deq_req_data(deq_req_data), //[17:0]cache or memory dequeue a flit from IN_local req fifo
.deq_rep_data(deq_rep_data), //[17:0]cache or memory dequeue a flit from IN_local rep fifo
.req_rdy(req_rdy),
.rep_rdy(rep_rdy),
.en_local_req(en_local_req), // to previous node refer to below notes
.en_local_rep(en_local_rep),
.en_pass_req(en_pass_req), // from next node //local_in_req fifo in next node says that it can receive
.en_pass_rep(en_pass_rep), // refer to notes below
.used_slots_pass_req(used_slots_pass_req),
.used_slots_pass_rep(used_slots_pass_rep),
.flit_out(flit_out),
.ctrl_out(ctrl_out),
.dest_fifo_out(dest_fifo_out),
.OUT_req_rdy(OUT_req_rdy),
.OUT_rep_rdy(OUT_rep_rdy)
);
commu_assist my_CA(//input
.clk(clk),
.rst(rst),
// I/O between arbiter and IN fifos
// input
.req_flit_in(deq_req_data[15:0]), //flit from IN req fifo
.req_rdy(req_rdy), // it's ready for arbiter_IN_node to dequeue flit from In req fifo
.req_ctrl_in(deq_req_data[17:16]), //control signals from In fifo indicate what kind of flit under transfering
.rep_flit_in(deq_rep_data[15:0]),
.rep_rdy(rep_rdy),
.rep_ctrl_in(deq_rep_data[17:16]),
// output
.ack_rep(ack_rep), // arbiter tell IN rep fifo that it's ready to receive flit,
// as well as been used by IN rep fifo as a deq rdy signal
.ack_req(ack_req), //req_rep and req_req are better!
/// I/O about OUT_req/rep fifo
//input
.OUT_req_rdy(OUT_req_rdy), // arbiter_OUT_req tell OUT req fifo to be ready to receive flit from commu_assist
.OUT_rep_rdy(OUT_rep_rdy), // arbiter_OUT_rep ......
// output
.OUT_req_ctrl(OUT_req_ctrl), // used to tell the frame of msg. 00 means nothing 01 means head flit,
// 10 means body flit,11 means tail flit, exception is invrep which has only one flit.
.OUT_req_flit(OUT_req_flit), // flit outputed to OUT req fifo
.OUT_req_ack(OUT_req_ack), // same as rdy signal saying now I'm a valid flit, also a enq signal for OUT req fifo
.OUT_rep_ctrl(OUT_rep_ctrl), // similar function as above
.OUT_rep_flit(OUT_rep_flit),
.OUT_rep_ack(OUT_rep_ack),
/// I/O about inst cache
// input
// .v_req_inst(), // indicate that's a valid inst request from pc
// .pc_addr(), // addr of pc used to look up inst cache to find intended inst
// to OUT_req
.v_flits_2_ic_req(local_or_OUT), // saying I'm a valid req flits to OUT req fifo
.flits_2_ic_req(req_msg), // req flits output to OUT req fifo
// to local mem
.v_req_i_m_areg(!local_or_OUT), // saying I'm a valid req flits to local home(memory)
.req_i_m_areg(req_msg[31:0]), // req flits output to local home
// output
.v_inst_rep(v_inst_rep), // saying that is a valid rep data back to pipeline
.inst_data(inst_data), // rep data (inst word) back to inst cahe.
/// I/O about data cache
// input
.dcache_done_access(dcache_done_access), // data cache tell arbiter_for_dcache previous access had done via this signal
// output
.flits_dcache(flits_dcache), // arbiter select a flits to dcache
.v_flits_dcache(v_flits_dcache), // means it's a valid flits to dcache
/// I/O about cpu_req_cache about ll/ld/st/sc
// input
.v_cpu_access(v_mem), // means it's a valid access from pipeline
.cpu_head(mem_head), // this part include access ctrl info such as ll or ld ,sc or st ,wr or rd
.cpu_addr(mem_addr), //addr of mem ops
.cpu_data(mem_data), // data of store or store-condition
/// I/O about memory
// input
.ack_m_donwload(v_m_download), // response to m_download saying i'm now reading flits
.ack_d_m_donwload(v_d_m_areg), // similar as above
.ack_i_m_donwload(v_i_m_areg), //similar as above
.mem_access_done(mem_access_done),
.mem_ic_download(data_out_local_i), // flits from mem to ic_download
.v_mem_ic_download(v_rep_i), // flit above is valid
.mem_m_d_areg({head_out_local_d,addr_out_local_d,data_out_local_d}), // flits from mem to m_d_areg
.v_mem_m_d_areg(v_req_d||v_rep_d), // it's a valid flits to m_d_areg
.mem_m_req({head_out_rep_out,addr_out_rep_out}), // similar as above
.v_mem_m_req(v_req_out),
.mem_m_rep({head_out_rep_out,addr_out_rep_out,data_out_rep_out}),
.v_mem_m_rep(v_rep_out), //similar as above
.en_m_flits_max_rep(en_flit_max_rep_m),
.m_flits_max_rep(flit_max_rep_m),
.en_m_flits_max_req(en_flit_max_req_m),
.m_flits_max_req(flit_max_req_m),
.en_inv_ids(en_inv_ids),
.inv_ids_in(inv_ids_in),
// output
.v_m_download(v_m_download), // valic flits from m_download to mem
.m_donwload(m_donwload), //flits from m_download to mem
.v_d_m_areg(v_d_m_areg), // valid flits from d_m_areg to mem
.d_m_areg(d_m_areg), // flits from d_m_areg to mem
.v_i_m_areg(v_i_m_areg),
.i_m_areg(i_m_areg),
.ic_download_fsm_state(ic_download_fsm_state), //here are some fsm state indicating whether some state elements is idle or busy
.m_d_areg_fsm_state(m_d_areg_fsm_state), // which is useful to decide whether or not to output flits from mem to these elements
.m_rep_fsm_state(m_rep_fsm_state),
.m_req_fsm_state(m_req_fsm_state),
/// I/O about data cache
//input
.dcache_d_m_areg(flits_d_m_areg), //access via flits from data cache to local mem
.v_dcache_d_m_areg(v_flits_d_m_areg), // means it's avalid access
.dcache_dc_req(flits_dc_upload_req), // access via flits to OUT_req_upload corresponding to dcache
.v_dcache_dc_req(v_flits_dc_upload_req), // means it's avalid access
.dcache_dc_rep(flits_dc_upload_rep),
.v_dcache_dc_rep(v_flits_dc_upload_rep),
.en_dc_flits_max_rep(en_flit_max_rep_d),
.dc_flits_max_rep(flit_max_rep_d),
/// output
.d_m_areg_fsm_state(d_m_areg_fsm_state), // fsm state outputed from commu_assist intended to tell dcache if it's able
// to send flits to these units
.dc_req_fsm_state(dc_req_fsm_state),
.dc_rep_fsm_state(dc_rep_fsm_state)
);
dcache_cpu_network_ctrler
my_dc( //global ctrl signals
.clk(clk),
.rst(rst),
//input from arbiter_for_dcache
.flits_in(flits_dcache),
.v_flits_in(v_flits_dcache),
.v_cpu_req(v_mem),
// input from cpu access regs used for cpu_side wait state:shrep or exrep or SH_exrep or invrep
.cpu_addr_for_wait(mem_addr),
.v_cpu_addr_for_wait(v_mem),
.cpu_access_head(mem_head),
//input from dc_upload_req regs : fsm_state to tell dcache whether it's idle
.d_req_state(dc_req_fsm_state),
//input from dc_upload_rep regs : fsm state to tell dcache whether it's idle
.d_rep_state(dc_rep_fsm_state),
// input from d_m_areg(=>data cache to mem access regs) :fsm state. used to tell dcache whether it's idle
.m_fsm_state(d_m_areg_fsm_state),
//output to cpu access regs saying that data cache doesn't need cpu_addr anymore!
.done_access_cpu_addr(done_access_cpu_addr),
//output to tell arbiter that data cache has been accessed!
.dcache_done_access(dcache_done_access),
//output to d_m_areg when the generated msg is a local msg
.flits_d_m_areg(flits_d_m_areg), // at most 11 flits
.v_flits_d_m_areg(v_flits_d_m_areg),
//output to dc_upload_req regs
.flits_dc_upload_req(flits_dc_upload_req), // always 3 flits
.v_flits_dc_upload_req(v_flits_dc_upload_req),
.en_flit_max_req(en_flit_max_req_d),
.flit_max_req(flit_max_req_d),
//output to dc_upload_rep regs
.flits_dc_upload_rep(flits_dc_upload_rep), // at most 11 flits
.v_flits_dc_upload_rep(v_flits_dc_upload_rep),
.en_flit_max_rep(en_flit_max_rep_d),
.flit_max_rep(flit_max_rep_d),
// output to cpu tell whether cpu access has done
.data_cpu(data_cpu),
.v_rep_cpu(v_rep_cpu)
);
//wire [47:0] req_msg_local;
//wire [47:0] req_msg_OUT;
//assign req_msg_local=local_or_OUT?48'hzzzz:req_msg;
//assign req_msg_OUT=local_or_OUT?req_msg:48'hzzzz;
// here should be inst cache ,but by now i haven't written it
inst_cache my_ic(//input
.clk(clk),
.rst(rst),
// from pc
.v_pc(v_pc),
.pc(pc),
//from ic_download
.inst_4word(inst_data),
.v_inst_4word(v_inst_rep),
//output
// to local mem or OUT_req upload
.v_ic_req(v_ic_req),
.local_or_OUT(local_or_OUT), //1:local ,0:OUT_req
.req_msg(req_msg),
.v_inst(v_inst),
.inst(inst)
);
memory my_mem(//input
.clk(clk),
.rst(rst),
//fsm state of rep paralle-serial port corresponding to mem
.m_rep_fsm_state(m_rep_fsm_state),
//fsm state of req paralle-serial port corresponding to mem
.m_req_fsm_state(m_req_fsm_state),
// fsm state of req paralle-serial port corresponding to data cache
.d_fsm_state(m_d_areg_fsm_state),
// input from local d cache
.v_d_req(v_flits_d_m_areg),
.v_d_rep(v_flits_d_m_areg),
.local_d_head_in(flits_d_m_areg[175:160]),
.local_d_addr_in(flits_d_m_areg[159:128]),
.local_d_data_in(flits_d_m_areg[127:0]),
// input from local i cache
.v_i_rep(!local_or_OUT),
// local_i_head, // no need for local i cache miss
.local_i_addr_in(req_msg[31:0]),
// input form INfifos
.v_INfifos(v_m_download),
.infifos_head_in(m_donwload[175:160]),
.infifos_addr_in(m_donwload[159:128]),
.infifos_data_in(m_donwload[127:0]),
// output to local d cache
.v_req_d(v_req_d),
.v_rep_d(v_rep_d),
.head_out_local_d(head_out_local_d),
.addr_out_local_d(addr_out_local_d),
.data_out_local_d(data_out_local_d),
// output to local i cahce
.v_rep_i(v_rep_i),
.data_out_local_i(data_out_local_i),
// output to OUT req fifo
.en_inv_ids(en_inv_ids),
.inv_ids_in(inv_ids_in),
.flit_max_req(flit_max_req_m),
.en_flit_max_req(en_flit_max_req_m),
.v_req_out(v_req_out),
.head_out_req_out(head_out_req_out),
.addr_out_req_out(addr_out_req_out),
// .data_out_req_out(data_out_req_out),
// output to OUT rep fifo
.flit_max_rep(flit_max_rep_m),
.en_flit_max_rep(en_flit_max_rep_m),
.v_rep_out(v_rep_out),
.head_out_rep_out(head_out_rep_out),
.addr_out_rep_out(addr_out_rep_out),
.data_out_rep_out(data_out_rep_out),
//
.mem_access_done(mem_access_done)
);
core my_core(//input
.clk(clk),
.rst(rst),
.v_inst(v_inst),
.inst(inst),
.v_data(v_rep_cpu),
.data(data_cpu),
//output
.pc(pc),
.v_pc(v_pc),
.v_mem(v_mem),
.mem_head(mem_head),
.mem_addr(mem_addr),
.mem_data(mem_data)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32AI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O32AI_FUNCTIONAL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o32ai (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32AI_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_1_V
`define SKY130_FD_SC_LS__DFRBP_1_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog wrapper for dfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Mauricio Carvajal Delgado
//
// Create Date: 03.17.2013 10:36:22
// Design Name:
// Module Name: FSM_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_test(
input wire clk,
input wire rst,
input wire ready_op,
input wire max_tick_address,
input wire max_tick_ch,
input wire TX_DONE,
output reg beg_op,
output reg ack_op,
output reg load_address,
output reg enab_address,
output reg enab_ch,
output reg load_ch,
output reg TX_START
);
//symbolic state declaration
localparam [3:0] est0 = 4'b0000,
est1 = 4'b0001,
est2 = 4'b0010,
est3 = 4'b0011,
est4 = 4'b0100,
est5 = 4'b0101,
est6 = 4'b0110,
est7 = 4'b0111,
est8 = 4'b1000,
est9 = 4'b1001,
est10 = 4'b1010,
est11 = 4'b1011;
//signal declaration
reg [3:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge rst)
begin
if(rst) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
beg_op = 1'b0;
ack_op = 1'b0;
load_address = 1'b0;
enab_address = 1'b0;
enab_ch = 1'b0;
load_ch = 1'b0;
TX_START = 1'b0;
case(state_reg)
est0:
begin
state_next = est1;
end
est1:
begin
load_address = 1'b1;
enab_address = 1'b1;
state_next = est2;
end
est2:
begin
beg_op = 1'b1;
state_next=est3;
end
est3:
begin
beg_op = 1'b1;
enab_ch = 1'b1;
load_ch = 1'b1;
state_next=est4;
end
est4:
begin
if(ready_op)
state_next=est5;
else
state_next=est4;
end
est5:
begin
state_next=est6;
end
est6:
begin
TX_START = 1'b1;
state_next=est7;
end
est7:
begin
if(TX_DONE)
if(max_tick_ch)
state_next=est9;
else
begin
state_next=est8;
end
else
state_next=est7;
end
est8:
begin
enab_ch = 1'b1;
state_next=est5;
end
est9:
begin
if(max_tick_address)
state_next=est11;
else
begin
state_next=est10;
end
end
est10:
begin
enab_address = 1'b1;
ack_op = 1'b1;
state_next=est2;
end
est11:
begin
state_next=est11;
end
default:
state_next=est0;
endcase
end
endmodule
|
module ex_div(
input wire clock,
input wire reset,
input wire is_signed,
input wire[`REGS_DATA_BUS] operand1,
input wire[`REGS_DATA_BUS] operand2,
input wire is_start,
input wire is_annul,
output reg is_ended,
output reg[`DOUBLE_REGS_DATA_BUS] result
);
wire[`EXT_REGS_DATA_BUS] div_temp;
reg[`EXT_DOUBLE_REGS_DATA_BUS] dividend;
reg[`REGS_DATA_BUS] divisor;
reg[5 : 0] cycle;
reg[1 : 0] state;
assign div_temp = {1'b0, dividend[63 : 32]} - {1'b0, divisor};
always @ (posedge clock) begin
if (reset == `ENABLE) begin
state <= `DIV_FREE;
is_ended <= `FALSE;
result <= 0; // FIXME: {`ZEROWORD, `ZEROWORD} should be used
end else begin
case (state)
`DIV_FREE: begin
if (is_start == `TRUE && is_annul == `FALSE) begin
if (operand2 == 0) begin // FIXME: ZERO_WORD should be used
state <= `DIV_BY_ZERO;
end else begin
state <= `DIV_ON;
cycle <= 6'b000000;
dividend = 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used
if (is_signed == `TRUE && operand1[31] == 1'b1) begin
dividend[32 : 1] <= ~operand1 + 1; // FIXME: may be = should be used here
end else begin
dividend[32 : 1] <= operand1; // FIXME: may be = should be used here
end
if (is_signed == `TRUE && operand2[31] == 1'b1) begin
divisor <= ~operand2 + 1;
end else begin
divisor <= operand2;
end
end
end else begin
is_ended <= `FALSE;
result <= 0; // FIXME: {`ZEROWORD, `ZEROWORD} should be used
end
end
`DIV_BY_ZERO: begin
dividend <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used
state <= `DIV_END;
end
`DIV_ON: begin
if (is_annul == `FALSE) begin
if (cycle != 6'b100000) begin
if (div_temp[32] == 1'b1) begin
dividend <= {dividend[63 : 0], 1'b0};
end else begin
dividend <= {div_temp[31 : 0], dividend[31 : 0], 1'b1};
end
cycle <= cycle + 1;
end else begin
if (is_signed && (operand1[31] ^ operand2[31])) begin
dividend[31 : 0] <= ~dividend[31 : 0] + 1;
end
if (is_signed && (operand1[31] ^ dividend[64])) begin
dividend[64 : 33] <= ~dividend[64 : 33] + 1;
end
state <= `DIV_END;
cycle <= 6'b000000;
end
end else begin
state <= `DIV_FREE;
end
end
`DIV_END: begin
result <= {dividend[64 : 33], dividend[31 : 0]};
is_ended <= `TRUE;
if (is_start <= `FALSE) begin
state <= `DIV_FREE;
is_ended <= `FALSE;
result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used
end
end
endcase
end
end
endmodule // ex_div
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
// Date : Wed Apr 8 23:17:21 2015
// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
// Command : write_verilog -force -mode funcsim
// /home/aolofsson/Work_all/parallella-hw/fpga/ip/xilinx/axi_bram_ctrl_16b/axi_bram_ctrl_16b_funcsim.v
// Design : axi_bram_ctrl_16b
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_bram_ctrl,Vivado 2014.3.1" *) (* CHECK_LICENSE_TYPE = "axi_bram_ctrl_16b,axi_bram_ctrl,{}" *)
(* core_generation_info = "axi_bram_ctrl_16b,axi_bram_ctrl,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=16384,C_BRAM_ADDR_WIDTH=14,C_S_AXI_ADDR_WIDTH=16,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4LITE,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}" *)
(* NotValidForBitStream *)
module axi_bram_ctrl_16b
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input s_axi_aresetn;
input [15:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
input [15:0]s_axi_araddr;
input [2:0]s_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) output bram_rst_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) output bram_clk_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
wire [15:0]bram_addr_a;
wire bram_clk_a;
wire bram_en_a;
wire [31:0]bram_rddata_a;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire s_axi_aresetn;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_bram_clk_b_UNCONNECTED;
wire NLW_U0_bram_en_b_UNCONNECTED;
wire NLW_U0_bram_rst_b_UNCONNECTED;
wire NLW_U0_ecc_interrupt_UNCONNECTED;
wire NLW_U0_ecc_ue_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_arready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_awready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_wready_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire [15:0]NLW_U0_bram_addr_b_UNCONNECTED;
wire [3:0]NLW_U0_bram_we_b_UNCONNECTED;
wire [31:0]NLW_U0_bram_wrdata_b_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_ctrl_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
(* C_BRAM_ADDR_WIDTH = "14" *)
(* C_BRAM_INST_MODE = "EXTERNAL" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *)
(* C_ECC_TYPE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *)
(* C_MEMORY_DEPTH = "16384" *)
(* C_SINGLE_PORT_BRAM = "1" *)
(* C_S_AXI_ADDR_WIDTH = "16" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "1" *)
(* C_S_AXI_PROTOCOL = "AXI4LITE" *)
(* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
axi_bram_ctrl_16b_axi_bram_ctrl__parameterized0 U0
(.bram_addr_a(bram_addr_a),
.bram_addr_b(NLW_U0_bram_addr_b_UNCONNECTED[15:0]),
.bram_clk_a(bram_clk_a),
.bram_clk_b(NLW_U0_bram_clk_b_UNCONNECTED),
.bram_en_a(bram_en_a),
.bram_en_b(NLW_U0_bram_en_b_UNCONNECTED),
.bram_rddata_a(bram_rddata_a),
.bram_rddata_b({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.bram_rst_a(bram_rst_a),
.bram_rst_b(NLW_U0_bram_rst_b_UNCONNECTED),
.bram_we_a(bram_we_a),
.bram_we_b(NLW_U0_bram_we_b_UNCONNECTED[3:0]),
.bram_wrdata_a(bram_wrdata_a),
.bram_wrdata_b(NLW_U0_bram_wrdata_b_UNCONNECTED[31:0]),
.ecc_interrupt(NLW_U0_ecc_interrupt_UNCONNECTED),
.ecc_ue(NLW_U0_ecc_ue_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_ctrl_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_arready(NLW_U0_s_axi_ctrl_arready_UNCONNECTED),
.s_axi_ctrl_arvalid(1'b0),
.s_axi_ctrl_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_awready(NLW_U0_s_axi_ctrl_awready_UNCONNECTED),
.s_axi_ctrl_awvalid(1'b0),
.s_axi_ctrl_bready(1'b0),
.s_axi_ctrl_bresp(NLW_U0_s_axi_ctrl_bresp_UNCONNECTED[1:0]),
.s_axi_ctrl_bvalid(NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED),
.s_axi_ctrl_rdata(NLW_U0_s_axi_ctrl_rdata_UNCONNECTED[31:0]),
.s_axi_ctrl_rready(1'b0),
.s_axi_ctrl_rresp(NLW_U0_s_axi_ctrl_rresp_UNCONNECTED[1:0]),
.s_axi_ctrl_rvalid(NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED),
.s_axi_ctrl_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_wready(NLW_U0_s_axi_ctrl_wready_UNCONNECTED),
.s_axi_ctrl_wvalid(1'b0),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(1'b0),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_bram_ctrl" *) (* C_BRAM_INST_MODE = "EXTERNAL" *) (* C_MEMORY_DEPTH = "16384" *)
(* C_BRAM_ADDR_WIDTH = "14" *) (* C_S_AXI_ADDR_WIDTH = "16" *) (* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "1" *) (* C_S_AXI_PROTOCOL = "AXI4LITE" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* C_SINGLE_PORT_BRAM = "1" *) (* C_FAMILY = "zynq" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_ECC = "0" *) (* C_ECC_TYPE = "0" *)
(* C_FAULT_INJECT = "0" *) (* C_ECC_ONOFF_RESET_VALUE = "0" *) (* downgradeipidentifiedwarnings = "yes" *)
module axi_bram_ctrl_16b_axi_bram_ctrl__parameterized0
(s_axi_aclk,
s_axi_aresetn,
ecc_interrupt,
ecc_ue,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_ctrl_awvalid,
s_axi_ctrl_awready,
s_axi_ctrl_awaddr,
s_axi_ctrl_wdata,
s_axi_ctrl_wvalid,
s_axi_ctrl_wready,
s_axi_ctrl_bresp,
s_axi_ctrl_bvalid,
s_axi_ctrl_bready,
s_axi_ctrl_araddr,
s_axi_ctrl_arvalid,
s_axi_ctrl_arready,
s_axi_ctrl_rdata,
s_axi_ctrl_rresp,
s_axi_ctrl_rvalid,
s_axi_ctrl_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
input s_axi_aclk;
input s_axi_aresetn;
output ecc_interrupt;
output ecc_ue;
input [0:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_ctrl_awvalid;
output s_axi_ctrl_awready;
input [31:0]s_axi_ctrl_awaddr;
input [31:0]s_axi_ctrl_wdata;
input s_axi_ctrl_wvalid;
output s_axi_ctrl_wready;
output [1:0]s_axi_ctrl_bresp;
output s_axi_ctrl_bvalid;
input s_axi_ctrl_bready;
input [31:0]s_axi_ctrl_araddr;
input s_axi_ctrl_arvalid;
output s_axi_ctrl_arready;
output [31:0]s_axi_ctrl_rdata;
output [1:0]s_axi_ctrl_rresp;
output s_axi_ctrl_rvalid;
input s_axi_ctrl_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
wire \<const0> ;
wire [15:2]\^bram_addr_a ;
wire bram_en_a;
wire [31:0]bram_rddata_a;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire \n_0_bram_we_a[0]_INST_0_i_1 ;
wire \n_0_bram_we_a[1]_INST_0_i_1 ;
wire \n_0_bram_we_a[2]_INST_0_i_1 ;
wire \n_0_bram_we_a[3]_INST_0_i_2 ;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arlock;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awlock;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_ctrl_araddr;
wire s_axi_ctrl_arvalid;
wire [31:0]s_axi_ctrl_awaddr;
wire s_axi_ctrl_awvalid;
wire s_axi_ctrl_bready;
wire s_axi_ctrl_rready;
wire [31:0]s_axi_ctrl_wdata;
wire s_axi_ctrl_wvalid;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign bram_addr_a[15:2] = \^bram_addr_a [15:2];
assign bram_addr_a[1] = \<const0> ;
assign bram_addr_a[0] = \<const0> ;
assign bram_addr_b[15] = \<const0> ;
assign bram_addr_b[14] = \<const0> ;
assign bram_addr_b[13] = \<const0> ;
assign bram_addr_b[12] = \<const0> ;
assign bram_addr_b[11] = \<const0> ;
assign bram_addr_b[10] = \<const0> ;
assign bram_addr_b[9] = \<const0> ;
assign bram_addr_b[8] = \<const0> ;
assign bram_addr_b[7] = \<const0> ;
assign bram_addr_b[6] = \<const0> ;
assign bram_addr_b[5] = \<const0> ;
assign bram_addr_b[4] = \<const0> ;
assign bram_addr_b[3] = \<const0> ;
assign bram_addr_b[2] = \<const0> ;
assign bram_addr_b[1] = \<const0> ;
assign bram_addr_b[0] = \<const0> ;
assign bram_clk_a = s_axi_aclk;
assign bram_clk_b = \<const0> ;
assign bram_en_b = \<const0> ;
assign bram_rst_b = \<const0> ;
assign bram_we_b[3] = \<const0> ;
assign bram_we_b[2] = \<const0> ;
assign bram_we_b[1] = \<const0> ;
assign bram_we_b[0] = \<const0> ;
assign bram_wrdata_a[31:0] = s_axi_wdata;
assign bram_wrdata_b[31] = \<const0> ;
assign bram_wrdata_b[30] = \<const0> ;
assign bram_wrdata_b[29] = \<const0> ;
assign bram_wrdata_b[28] = \<const0> ;
assign bram_wrdata_b[27] = \<const0> ;
assign bram_wrdata_b[26] = \<const0> ;
assign bram_wrdata_b[25] = \<const0> ;
assign bram_wrdata_b[24] = \<const0> ;
assign bram_wrdata_b[23] = \<const0> ;
assign bram_wrdata_b[22] = \<const0> ;
assign bram_wrdata_b[21] = \<const0> ;
assign bram_wrdata_b[20] = \<const0> ;
assign bram_wrdata_b[19] = \<const0> ;
assign bram_wrdata_b[18] = \<const0> ;
assign bram_wrdata_b[17] = \<const0> ;
assign bram_wrdata_b[16] = \<const0> ;
assign bram_wrdata_b[15] = \<const0> ;
assign bram_wrdata_b[14] = \<const0> ;
assign bram_wrdata_b[13] = \<const0> ;
assign bram_wrdata_b[12] = \<const0> ;
assign bram_wrdata_b[11] = \<const0> ;
assign bram_wrdata_b[10] = \<const0> ;
assign bram_wrdata_b[9] = \<const0> ;
assign bram_wrdata_b[8] = \<const0> ;
assign bram_wrdata_b[7] = \<const0> ;
assign bram_wrdata_b[6] = \<const0> ;
assign bram_wrdata_b[5] = \<const0> ;
assign bram_wrdata_b[4] = \<const0> ;
assign bram_wrdata_b[3] = \<const0> ;
assign bram_wrdata_b[2] = \<const0> ;
assign bram_wrdata_b[1] = \<const0> ;
assign bram_wrdata_b[0] = \<const0> ;
assign ecc_interrupt = \<const0> ;
assign ecc_ue = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_ctrl_arready = \<const0> ;
assign s_axi_ctrl_awready = \<const0> ;
assign s_axi_ctrl_bresp[1] = \<const0> ;
assign s_axi_ctrl_bresp[0] = \<const0> ;
assign s_axi_ctrl_bvalid = \<const0> ;
assign s_axi_ctrl_rdata[31] = \<const0> ;
assign s_axi_ctrl_rdata[30] = \<const0> ;
assign s_axi_ctrl_rdata[29] = \<const0> ;
assign s_axi_ctrl_rdata[28] = \<const0> ;
assign s_axi_ctrl_rdata[27] = \<const0> ;
assign s_axi_ctrl_rdata[26] = \<const0> ;
assign s_axi_ctrl_rdata[25] = \<const0> ;
assign s_axi_ctrl_rdata[24] = \<const0> ;
assign s_axi_ctrl_rdata[23] = \<const0> ;
assign s_axi_ctrl_rdata[22] = \<const0> ;
assign s_axi_ctrl_rdata[21] = \<const0> ;
assign s_axi_ctrl_rdata[20] = \<const0> ;
assign s_axi_ctrl_rdata[19] = \<const0> ;
assign s_axi_ctrl_rdata[18] = \<const0> ;
assign s_axi_ctrl_rdata[17] = \<const0> ;
assign s_axi_ctrl_rdata[16] = \<const0> ;
assign s_axi_ctrl_rdata[15] = \<const0> ;
assign s_axi_ctrl_rdata[14] = \<const0> ;
assign s_axi_ctrl_rdata[13] = \<const0> ;
assign s_axi_ctrl_rdata[12] = \<const0> ;
assign s_axi_ctrl_rdata[11] = \<const0> ;
assign s_axi_ctrl_rdata[10] = \<const0> ;
assign s_axi_ctrl_rdata[9] = \<const0> ;
assign s_axi_ctrl_rdata[8] = \<const0> ;
assign s_axi_ctrl_rdata[7] = \<const0> ;
assign s_axi_ctrl_rdata[6] = \<const0> ;
assign s_axi_ctrl_rdata[5] = \<const0> ;
assign s_axi_ctrl_rdata[4] = \<const0> ;
assign s_axi_ctrl_rdata[3] = \<const0> ;
assign s_axi_ctrl_rdata[2] = \<const0> ;
assign s_axi_ctrl_rdata[1] = \<const0> ;
assign s_axi_ctrl_rdata[0] = \<const0> ;
assign s_axi_ctrl_rresp[1] = \<const0> ;
assign s_axi_ctrl_rresp[0] = \<const0> ;
assign s_axi_ctrl_rvalid = \<const0> ;
assign s_axi_ctrl_wready = \<const0> ;
assign s_axi_rdata[31:0] = bram_rddata_a;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = s_axi_rlast;
assign s_axi_wready = s_axi_awready;
GND GND
(.G(\<const0> ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBFFF))
\bram_we_a[0]_INST_0_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(s_axi_wstrb[0]),
.O(\n_0_bram_we_a[0]_INST_0_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBFFF))
\bram_we_a[1]_INST_0_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(s_axi_wstrb[1]),
.O(\n_0_bram_we_a[1]_INST_0_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hBFFF))
\bram_we_a[2]_INST_0_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(s_axi_wstrb[2]),
.O(\n_0_bram_we_a[2]_INST_0_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hBFFF))
\bram_we_a[3]_INST_0_i_2
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(s_axi_wstrb[3]),
.O(\n_0_bram_we_a[3]_INST_0_i_2 ));
axi_bram_ctrl_16b_axi_bram_ctrl_top \gext_inst.abcv4_0_ext_inst
(.I1(\n_0_bram_we_a[0]_INST_0_i_1 ),
.I2(\n_0_bram_we_a[1]_INST_0_i_1 ),
.I3(\n_0_bram_we_a[2]_INST_0_i_1 ),
.I4(\n_0_bram_we_a[3]_INST_0_i_2 ),
.O1(s_axi_rlast),
.O2(bram_rst_a),
.O3(s_axi_bvalid),
.bram_addr_a(\^bram_addr_a ),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[15:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[15:2]),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_rid(s_axi_rid),
.s_axi_rready(s_axi_rready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_bram_ctrl_top" *)
module axi_bram_ctrl_16b_axi_bram_ctrl_top
(bram_we_a,
O1,
O2,
s_axi_awready,
s_axi_arready,
bram_en_a,
bram_addr_a,
O3,
s_axi_bid,
s_axi_rid,
s_axi_arvalid,
s_axi_wvalid,
s_axi_awvalid,
I1,
I2,
I3,
I4,
s_axi_rready,
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_araddr,
s_axi_bready,
s_axi_awid,
s_axi_arid);
output [3:0]bram_we_a;
output O1;
output O2;
output s_axi_awready;
output s_axi_arready;
output bram_en_a;
output [13:0]bram_addr_a;
output O3;
output [0:0]s_axi_bid;
output [0:0]s_axi_rid;
input s_axi_arvalid;
input s_axi_wvalid;
input s_axi_awvalid;
input I1;
input I2;
input I3;
input I4;
input s_axi_rready;
input s_axi_aclk;
input s_axi_aresetn;
input [13:0]s_axi_awaddr;
input [13:0]s_axi_araddr;
input s_axi_bready;
input [0:0]s_axi_awid;
input [0:0]s_axi_arid;
wire I1;
wire I2;
wire I3;
wire I4;
wire O1;
wire O2;
wire O3;
wire [13:0]bram_addr_a;
wire bram_en_a;
wire [3:0]bram_we_a;
wire \n_8_GEN_AXI4LITE.I_AXI_LITE ;
wire \n_9_GEN_AXI4LITE.I_AXI_LITE ;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [0:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [0:0]s_axi_rid;
wire s_axi_rready;
wire s_axi_wvalid;
FDRE #(
.INIT(1'b0))
\GEN_AXI4LITE.GEN_SIM_ONLY.S_AXI_BID_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_8_GEN_AXI4LITE.I_AXI_LITE ),
.Q(s_axi_bid),
.R(O2));
FDRE #(
.INIT(1'b0))
\GEN_AXI4LITE.GEN_SIM_ONLY.S_AXI_RID_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_9_GEN_AXI4LITE.I_AXI_LITE ),
.Q(s_axi_rid),
.R(O2));
axi_bram_ctrl_16b_axi_lite \GEN_AXI4LITE.I_AXI_LITE
(.I1(I1),
.I2(I2),
.I3(I3),
.I4(I4),
.O1(O2),
.O2(O3),
.O3(O1),
.O4(\n_8_GEN_AXI4LITE.I_AXI_LITE ),
.O5(\n_9_GEN_AXI4LITE.I_AXI_LITE ),
.bram_addr_a(bram_addr_a),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_rid(s_axi_rid),
.s_axi_rready(s_axi_rready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_lite" *)
module axi_bram_ctrl_16b_axi_lite
(s_axi_awready,
O1,
O2,
bram_we_a,
O3,
O4,
O5,
s_axi_arready,
bram_en_a,
bram_addr_a,
s_axi_aclk,
s_axi_aresetn,
s_axi_arvalid,
s_axi_wvalid,
s_axi_awvalid,
I1,
I2,
I3,
I4,
s_axi_rready,
s_axi_bready,
s_axi_awid,
s_axi_bid,
s_axi_arid,
s_axi_rid,
s_axi_awaddr,
s_axi_araddr);
output s_axi_awready;
output O1;
output O2;
output [3:0]bram_we_a;
output O3;
output O4;
output O5;
output s_axi_arready;
output bram_en_a;
output [13:0]bram_addr_a;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_arvalid;
input s_axi_wvalid;
input s_axi_awvalid;
input I1;
input I2;
input I3;
input I4;
input s_axi_rready;
input s_axi_bready;
input [0:0]s_axi_awid;
input [0:0]s_axi_bid;
input [0:0]s_axi_arid;
input [0:0]s_axi_rid;
input [13:0]s_axi_awaddr;
input [13:0]s_axi_araddr;
wire I1;
wire I2;
wire I3;
wire I4;
wire O1;
wire O2;
wire O3;
wire O4;
wire O5;
wire axi_aresetn_d1;
wire axi_wready_cmb;
wire [13:0]bram_addr_a;
wire bram_en_a;
wire [3:0]bram_we_a;
wire [2:0]bvalid_cnt;
(* RTL_KEEP = "yes" *) wire [2:0]lite_sm_cs;
wire lite_sm_ns0;
wire \n_0_FSM_sequential_lite_sm_cs[0]_i_1 ;
wire \n_0_FSM_sequential_lite_sm_cs[0]_i_2 ;
wire \n_0_FSM_sequential_lite_sm_cs[1]_i_1 ;
wire \n_0_FSM_sequential_lite_sm_cs[1]_i_2 ;
wire \n_0_FSM_sequential_lite_sm_cs[1]_i_3 ;
wire \n_0_FSM_sequential_lite_sm_cs[1]_i_4 ;
wire \n_0_FSM_sequential_lite_sm_cs[1]_i_5 ;
wire \n_0_FSM_sequential_lite_sm_cs[2]_i_1 ;
wire \n_0_FSM_sequential_lite_sm_cs[2]_i_2 ;
wire \n_0_GEN_ARREADY.axi_arready_int_i_1 ;
wire \n_0_GEN_R.axi_rvalid_int_i_1 ;
wire n_0_axi_bvalid_int_i_1;
wire n_0_axi_wready_int_i_2;
wire n_0_axi_wready_int_i_3;
wire n_0_bram_en_a_INST_0_i_1;
wire n_0_bram_en_a_INST_0_i_2;
wire n_0_bram_en_a_INST_0_i_3;
wire n_0_bram_en_a_INST_0_i_4;
wire \n_0_bram_we_a[3]_INST_0_i_1 ;
wire \n_0_bvalid_cnt[0]_i_1 ;
wire \n_0_bvalid_cnt[1]_i_1 ;
wire \n_0_bvalid_cnt[1]_i_2 ;
wire \n_0_bvalid_cnt[2]_i_1 ;
wire \n_0_bvalid_cnt[2]_i_2 ;
wire \n_0_bvalid_cnt[2]_i_3 ;
wire \n_0_bvalid_cnt[2]_i_4 ;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [0:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [0:0]s_axi_rid;
wire s_axi_rready;
wire s_axi_wvalid;
LUT6 #(
.INIT(64'hAAABBBABAAA888A8))
\FSM_sequential_lite_sm_cs[0]_i_1
(.I0(\n_0_FSM_sequential_lite_sm_cs[0]_i_2 ),
.I1(\n_0_FSM_sequential_lite_sm_cs[1]_i_3 ),
.I2(\n_0_FSM_sequential_lite_sm_cs[1]_i_4 ),
.I3(n_0_bram_en_a_INST_0_i_2),
.I4(\n_0_FSM_sequential_lite_sm_cs[1]_i_5 ),
.I5(lite_sm_cs[0]),
.O(\n_0_FSM_sequential_lite_sm_cs[0]_i_1 ));
LUT3 #(
.INIT(8'h02))
\FSM_sequential_lite_sm_cs[0]_i_2
(.I0(s_axi_arvalid),
.I1(lite_sm_cs[2]),
.I2(lite_sm_cs[0]),
.O(\n_0_FSM_sequential_lite_sm_cs[0]_i_2 ));
LUT6 #(
.INIT(64'hAAABBBABAAA888A8))
\FSM_sequential_lite_sm_cs[1]_i_1
(.I0(\n_0_FSM_sequential_lite_sm_cs[1]_i_2 ),
.I1(\n_0_FSM_sequential_lite_sm_cs[1]_i_3 ),
.I2(\n_0_FSM_sequential_lite_sm_cs[1]_i_4 ),
.I3(n_0_bram_en_a_INST_0_i_2),
.I4(\n_0_FSM_sequential_lite_sm_cs[1]_i_5 ),
.I5(lite_sm_cs[1]),
.O(\n_0_FSM_sequential_lite_sm_cs[1]_i_1 ));
LUT4 #(
.INIT(16'h0001))
\FSM_sequential_lite_sm_cs[1]_i_2
(.I0(lite_sm_cs[2]),
.I1(lite_sm_cs[1]),
.I2(s_axi_arvalid),
.I3(lite_sm_cs[0]),
.O(\n_0_FSM_sequential_lite_sm_cs[1]_i_2 ));
LUT2 #(
.INIT(4'hE))
\FSM_sequential_lite_sm_cs[1]_i_3
(.I0(lite_sm_cs[1]),
.I1(lite_sm_cs[2]),
.O(\n_0_FSM_sequential_lite_sm_cs[1]_i_3 ));
LUT4 #(
.INIT(16'h8F80))
\FSM_sequential_lite_sm_cs[1]_i_4
(.I0(s_axi_rready),
.I1(O3),
.I2(lite_sm_cs[0]),
.I3(s_axi_arvalid),
.O(\n_0_FSM_sequential_lite_sm_cs[1]_i_4 ));
LUT6 #(
.INIT(64'h8F8F8F808F808F80))
\FSM_sequential_lite_sm_cs[1]_i_5
(.I0(s_axi_rready),
.I1(O3),
.I2(lite_sm_cs[0]),
.I3(s_axi_arvalid),
.I4(s_axi_wvalid),
.I5(s_axi_awvalid),
.O(\n_0_FSM_sequential_lite_sm_cs[1]_i_5 ));
LUT2 #(
.INIT(4'h4))
\FSM_sequential_lite_sm_cs[2]_i_1
(.I0(\n_0_FSM_sequential_lite_sm_cs[2]_i_2 ),
.I1(lite_sm_cs[2]),
.O(\n_0_FSM_sequential_lite_sm_cs[2]_i_1 ));
LUT6 #(
.INIT(64'hFEAEFEAEFFAFFEAE))
\FSM_sequential_lite_sm_cs[2]_i_2
(.I0(\n_0_FSM_sequential_lite_sm_cs[1]_i_3 ),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[0]),
.I3(lite_sm_ns0),
.I4(n_0_bram_en_a_INST_0_i_2),
.I5(n_0_axi_wready_int_i_2),
.O(\n_0_FSM_sequential_lite_sm_cs[2]_i_2 ));
LUT2 #(
.INIT(4'h8))
\FSM_sequential_lite_sm_cs[2]_i_3
(.I0(s_axi_rready),
.I1(O3),
.O(lite_sm_ns0));
(* KEEP = "yes" *)
FDRE \FSM_sequential_lite_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_0_FSM_sequential_lite_sm_cs[0]_i_1 ),
.Q(lite_sm_cs[0]),
.R(O1));
(* KEEP = "yes" *)
FDRE \FSM_sequential_lite_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_0_FSM_sequential_lite_sm_cs[1]_i_1 ),
.Q(lite_sm_cs[1]),
.R(O1));
(* KEEP = "yes" *)
FDRE \FSM_sequential_lite_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_0_FSM_sequential_lite_sm_cs[2]_i_1 ),
.Q(lite_sm_cs[2]),
.R(O1));
LUT6 #(
.INIT(64'h0000FF00D500D500))
\GEN_ARREADY.axi_arready_int_i_1
(.I0(axi_aresetn_d1),
.I1(s_axi_rready),
.I2(O3),
.I3(s_axi_aresetn),
.I4(s_axi_arvalid),
.I5(s_axi_arready),
.O(\n_0_GEN_ARREADY.axi_arready_int_i_1 ));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_0_GEN_ARREADY.axi_arready_int_i_1 ),
.Q(s_axi_arready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hBF80))
\GEN_AXI4LITE.GEN_SIM_ONLY.S_AXI_BID_int[0]_i_1
(.I0(s_axi_awid),
.I1(s_axi_awready),
.I2(s_axi_awvalid),
.I3(s_axi_bid),
.O(O4));
LUT4 #(
.INIT(16'hBF80))
\GEN_AXI4LITE.GEN_SIM_ONLY.S_AXI_RID_int[0]_i_1
(.I0(s_axi_arid),
.I1(s_axi_arvalid),
.I2(s_axi_arready),
.I3(s_axi_rid),
.O(O5));
LUT6 #(
.INIT(64'h0000FF0010001000))
\GEN_R.axi_rvalid_int_i_1
(.I0(lite_sm_cs[2]),
.I1(lite_sm_cs[0]),
.I2(s_axi_arvalid),
.I3(s_axi_aresetn),
.I4(s_axi_rready),
.I5(O3),
.O(\n_0_GEN_R.axi_rvalid_int_i_1 ));
FDRE #(
.INIT(1'b0))
\GEN_R.axi_rvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_0_GEN_R.axi_rvalid_int_i_1 ),
.Q(O3),
.R(1'b0));
FDRE #(
.INIT(1'b0))
axi_aresetn_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn),
.Q(axi_aresetn_d1),
.R(1'b0));
LUT6 #(
.INIT(64'hA8A8AAA8AAA8AAA8))
axi_bvalid_int_i_1
(.I0(s_axi_aresetn),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.I4(O2),
.I5(s_axi_bready),
.O(n_0_axi_bvalid_int_i_1));
FDRE #(
.INIT(1'b0))
axi_bvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(n_0_axi_bvalid_int_i_1),
.Q(O2),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFF101100000000))
axi_wready_int_i_1
(.I0(s_axi_arvalid),
.I1(n_0_axi_wready_int_i_2),
.I2(\n_0_bram_we_a[3]_INST_0_i_1 ),
.I3(bvalid_cnt[2]),
.I4(lite_sm_cs[2]),
.I5(n_0_axi_wready_int_i_3),
.O(axi_wready_cmb));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h7))
axi_wready_int_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(n_0_axi_wready_int_i_2));
LUT2 #(
.INIT(4'h1))
axi_wready_int_i_3
(.I0(lite_sm_cs[1]),
.I1(lite_sm_cs[0]),
.O(n_0_axi_wready_int_i_3));
FDRE #(
.INIT(1'b0))
axi_wready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wready_cmb),
.Q(s_axi_awready),
.R(O1));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[10]_INST_0
(.I0(s_axi_awaddr[8]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[8]),
.O(bram_addr_a[8]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[11]_INST_0
(.I0(s_axi_awaddr[9]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[9]),
.O(bram_addr_a[9]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[12]_INST_0
(.I0(s_axi_awaddr[10]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[10]),
.O(bram_addr_a[10]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[13]_INST_0
(.I0(s_axi_awaddr[11]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[11]),
.O(bram_addr_a[11]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[14]_INST_0
(.I0(s_axi_awaddr[12]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[12]),
.O(bram_addr_a[12]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[15]_INST_0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[13]),
.O(bram_addr_a[13]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[2]_INST_0
(.I0(s_axi_awaddr[0]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[0]),
.O(bram_addr_a[0]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[3]_INST_0
(.I0(s_axi_awaddr[1]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[1]),
.O(bram_addr_a[1]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[4]_INST_0
(.I0(s_axi_awaddr[2]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[2]),
.O(bram_addr_a[2]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[5]_INST_0
(.I0(s_axi_awaddr[3]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[3]),
.O(bram_addr_a[3]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[6]_INST_0
(.I0(s_axi_awaddr[4]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[4]),
.O(bram_addr_a[4]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[7]_INST_0
(.I0(s_axi_awaddr[5]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[5]),
.O(bram_addr_a[5]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[8]_INST_0
(.I0(s_axi_awaddr[6]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[6]),
.O(bram_addr_a[6]));
LUT6 #(
.INIT(64'hAAAFAAEEAAA0AA22))
\bram_addr_a[9]_INST_0
(.I0(s_axi_awaddr[7]),
.I1(s_axi_arvalid),
.I2(lite_sm_cs[1]),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(s_axi_araddr[7]),
.O(bram_addr_a[7]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
bram_en_a_INST_0
(.I0(s_axi_aresetn),
.I1(n_0_bram_en_a_INST_0_i_1),
.I2(n_0_bram_en_a_INST_0_i_2),
.I3(n_0_bram_en_a_INST_0_i_3),
.I4(lite_sm_cs[0]),
.I5(n_0_bram_en_a_INST_0_i_4),
.O(bram_en_a));
LUT2 #(
.INIT(4'h2))
bram_en_a_INST_0_i_1
(.I0(s_axi_arvalid),
.I1(lite_sm_cs[2]),
.O(n_0_bram_en_a_INST_0_i_1));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h7F))
bram_en_a_INST_0_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.O(n_0_bram_en_a_INST_0_i_2));
LUT5 #(
.INIT(32'h0000FF40))
bram_en_a_INST_0_i_3
(.I0(lite_sm_cs[1]),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(s_axi_arvalid),
.I4(lite_sm_cs[2]),
.O(n_0_bram_en_a_INST_0_i_3));
LUT2 #(
.INIT(4'h2))
bram_en_a_INST_0_i_4
(.I0(lite_sm_cs[2]),
.I1(lite_sm_cs[1]),
.O(n_0_bram_en_a_INST_0_i_4));
LUT1 #(
.INIT(2'h1))
bram_rst_a_INST_0
(.I0(s_axi_aresetn),
.O(O1));
LUT6 #(
.INIT(64'h00000000AAAA0051))
\bram_we_a[0]_INST_0
(.I0(lite_sm_cs[2]),
.I1(bvalid_cnt[2]),
.I2(\n_0_bram_we_a[3]_INST_0_i_1 ),
.I3(I1),
.I4(lite_sm_cs[0]),
.I5(lite_sm_cs[1]),
.O(bram_we_a[0]));
LUT6 #(
.INIT(64'h00000000AAAA0051))
\bram_we_a[1]_INST_0
(.I0(lite_sm_cs[2]),
.I1(bvalid_cnt[2]),
.I2(\n_0_bram_we_a[3]_INST_0_i_1 ),
.I3(I2),
.I4(lite_sm_cs[0]),
.I5(lite_sm_cs[1]),
.O(bram_we_a[1]));
LUT6 #(
.INIT(64'h00000000AAAA0051))
\bram_we_a[2]_INST_0
(.I0(lite_sm_cs[2]),
.I1(bvalid_cnt[2]),
.I2(\n_0_bram_we_a[3]_INST_0_i_1 ),
.I3(I3),
.I4(lite_sm_cs[0]),
.I5(lite_sm_cs[1]),
.O(bram_we_a[2]));
LUT6 #(
.INIT(64'h00000000AAAA0051))
\bram_we_a[3]_INST_0
(.I0(lite_sm_cs[2]),
.I1(bvalid_cnt[2]),
.I2(\n_0_bram_we_a[3]_INST_0_i_1 ),
.I3(I4),
.I4(lite_sm_cs[0]),
.I5(lite_sm_cs[1]),
.O(bram_we_a[3]));
LUT2 #(
.INIT(4'h7))
\bram_we_a[3]_INST_0_i_1
(.I0(bvalid_cnt[0]),
.I1(bvalid_cnt[1]),
.O(\n_0_bram_we_a[3]_INST_0_i_1 ));
LUT6 #(
.INIT(64'hB0F08F0F4F0F70F0))
\bvalid_cnt[0]_i_1
(.I0(\n_0_bvalid_cnt[2]_i_2 ),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(\n_0_bvalid_cnt[2]_i_3 ),
.I5(\n_0_bvalid_cnt[1]_i_2 ),
.O(\n_0_bvalid_cnt[0]_i_1 ));
LUT6 #(
.INIT(64'hFF00F00F4FF07F00))
\bvalid_cnt[1]_i_1
(.I0(\n_0_bvalid_cnt[2]_i_2 ),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(\n_0_bvalid_cnt[2]_i_3 ),
.I5(\n_0_bvalid_cnt[1]_i_2 ),
.O(\n_0_bvalid_cnt[1]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFE000000))
\bvalid_cnt[1]_i_2
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[1]),
.I2(bvalid_cnt[0]),
.I3(O2),
.I4(s_axi_bready),
.O(\n_0_bvalid_cnt[1]_i_2 ));
LUT6 #(
.INIT(64'h5FFFFFFCC0000000))
\bvalid_cnt[2]_i_1
(.I0(\n_0_bvalid_cnt[2]_i_2 ),
.I1(\n_0_bvalid_cnt[2]_i_3 ),
.I2(\n_0_bvalid_cnt[2]_i_4 ),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[1]),
.I5(bvalid_cnt[2]),
.O(\n_0_bvalid_cnt[2]_i_1 ));
LUT3 #(
.INIT(8'h02))
\bvalid_cnt[2]_i_2
(.I0(lite_sm_cs[2]),
.I1(lite_sm_cs[0]),
.I2(lite_sm_cs[1]),
.O(\n_0_bvalid_cnt[2]_i_2 ));
LUT6 #(
.INIT(64'h000000000000FF40))
\bvalid_cnt[2]_i_3
(.I0(s_axi_arvalid),
.I1(s_axi_wvalid),
.I2(s_axi_awvalid),
.I3(lite_sm_cs[2]),
.I4(lite_sm_cs[0]),
.I5(lite_sm_cs[1]),
.O(\n_0_bvalid_cnt[2]_i_3 ));
LUT2 #(
.INIT(4'h7))
\bvalid_cnt[2]_i_4
(.I0(s_axi_bready),
.I1(O2),
.O(\n_0_bvalid_cnt[2]_i_4 ));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_0_bvalid_cnt[0]_i_1 ),
.Q(bvalid_cnt[0]),
.R(O1));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_0_bvalid_cnt[1]_i_1 ),
.Q(bvalid_cnt[1]),
.R(O1));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\n_0_bvalid_cnt[2]_i_1 ),
.Q(bvalid_cnt[2]),
.R(O1));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_4_V
`define SKY130_FD_SC_HS__DLRTN_4_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtn_4 (
RESET_B,
D ,
GATE_N ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrtn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrtn_4 (
RESET_B,
D ,
GATE_N ,
Q
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrtn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_4_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : xilinx_pcie_2_1_ep_7x.v
// Version : 1.3
//--
//-- Description: PCI Express Endpoint example FPGA design
//--
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
module xilinx_pcie_2_1_ep_7x # (
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
output [7:0] pci_exp_txp,
output [7:0] pci_exp_txn,
input [7:0] pci_exp_rxp,
input [7:0] pci_exp_rxn,
`ifdef ENABLE_LEDS
output led_0,
output led_1,
output led_2,
output led_3,
`endif
input sys_clk_p,
input sys_clk_n,
input sys_rst_n
);
localparam TCQ = 1;
wire user_clk;
wire user_reset;
wire user_lnk_up;
// Tx
wire [5:0] tx_buf_av;
wire tx_cfg_req;
wire tx_err_drop;
wire tx_cfg_gnt;
wire s_axis_tx_tready;
wire [3:0] s_axis_tx_tuser;
wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata;
wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
// Rx
wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata;
wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire rx_np_ok;
wire rx_np_req;
// Flow Control
wire [11:0] fc_cpld;
wire [7:0] fc_cplh;
wire [11:0] fc_npd;
wire [7:0] fc_nph;
wire [11:0] fc_pd;
wire [7:0] fc_ph;
wire [2:0] fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
wire cfg_err_cor;
wire cfg_err_ur;
wire cfg_err_ecrc;
wire cfg_err_cpl_timeout;
wire cfg_err_cpl_abort;
wire cfg_err_cpl_unexpect;
wire cfg_err_posted;
wire cfg_err_locked;
wire [47:0] cfg_err_tlp_cpl_header;
wire cfg_err_cpl_rdy;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_di;
wire [7:0] cfg_interrupt_do;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire [4:0] cfg_pciecap_interrupt_msgnum;
wire cfg_turnoff_ok;
wire cfg_to_turnoff;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
wire [15:0] cfg_dcommand2;
wire [2:0] cfg_pcie_link_state;
wire [63:0] cfg_dsn;
wire [127:0] cfg_err_aer_headerlog;
wire [4:0] cfg_aer_interrupt_msgnum;
wire cfg_err_aer_headerlog_set;
wire cfg_aer_ecrc_check_en;
wire cfg_aer_ecrc_gen_en;
wire [31:0] cfg_mgmt_di;
wire [3:0] cfg_mgmt_byte_en;
wire [9:0] cfg_mgmt_dwaddr;
wire cfg_mgmt_wr_en;
wire cfg_mgmt_rd_en;
wire cfg_mgmt_wr_readonly;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
wire [2:0] pl_initial_link_width;
wire [1:0] pl_lane_reversal_mode;
wire pl_link_gen2_cap;
wire pl_link_partner_gen2_supported;
wire pl_link_upcfg_cap;
wire [5:0] pl_ltssm_state;
wire pl_received_hot_rst;
wire pl_sel_lnk_rate;
wire [1:0] pl_sel_lnk_width;
wire pl_directed_link_auton;
wire [1:0] pl_directed_link_change;
wire pl_directed_link_speed;
wire [1:0] pl_directed_link_width;
wire pl_upstream_prefer_deemph;
wire sys_rst_n_c;
// Wires used for external clocking connectivity
wire PIPE_PCLK_IN;
wire [7:0] PIPE_RXUSRCLK_IN;
wire PIPE_RXOUTCLK_IN;
wire PIPE_DCLK_IN;
wire PIPE_USERCLK1_IN;
wire PIPE_USERCLK2_IN;
wire PIPE_MMCM_LOCK_IN;
wire PIPE_TXOUTCLK_OUT;
wire [7:0] PIPE_RXOUTCLK_OUT;
wire [7:0] PIPE_PCLK_SEL_OUT;
wire PIPE_GEN3_OUT;
localparam USER_CLK_FREQ = 4;
localparam USER_CLK2_DIV2 = "TRUE";
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ
: USER_CLK_FREQ;
//-------------------------------------------------------
IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n));
`ifdef SIMULATION
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n));
`else
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .IB(sys_clk_n));
`endif
`ifdef ENABLE_LEDS
// Uncomment UCF location constraints
OBUF led_0_obuf (.O(led_0), .I(sys_rst_n_c));
OBUF led_1_obuf (.O(led_1), .I(!user_reset));
OBUF led_2_obuf (.O(led_2), .I(user_lnk_up));
OBUF led_3_obuf (.O(led_3), .I(user_clk_heartbeat[25]));
`endif
reg user_reset_q;
reg user_lnk_up_q;
always @(posedge user_clk) begin
user_reset_q <= user_reset;
user_lnk_up_q <= user_lnk_up;
end
// Generate External Clock Module if External Clocking is selected
generate
if (PCIE_EXT_CLK == "TRUE") begin : ext_clk
//---------- PIPE Clock Module -------------------------------------------------
pcie_7x_v1_3_pipe_clock #
(
.PCIE_ASYNC_EN ( "FALSE" ), // PCIe async enable
.PCIE_TXBUF_EN ( "FALSE" ), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE ( 6'h08 ), // PCIe number of lanes
`ifdef SIMULATION // PCIe Link Speed
.PCIE_LINK_SPEED ( 2 ),
`else
.PCIE_LINK_SPEED ( 3 ),
`endif
.PCIE_REFCLK_FREQ ( 0 ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ), // PCIe user clock 2 frequency
.PCIE_DEBUG_MODE ( 0 )
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK ( sys_clk ),
.CLK_TXOUTCLK ( PIPE_TXOUTCLK_OUT ), // Reference clock from lane 0
.CLK_RXOUTCLK_IN ( PIPE_RXOUTCLK_OUT ),
.CLK_RST_N ( 1'b1 ),
.CLK_PCLK_SEL ( PIPE_PCLK_SEL_OUT ),
.CLK_GEN3 ( PIPE_GEN3_OUT ),
//---------- Output ------------------------------------
.CLK_PCLK ( PIPE_PCLK_IN ),
.CLK_RXUSRCLK ( PIPE_RXUSRCLK_IN ),
.CLK_RXOUTCLK_OUT ( PIPE_RXOUTCLK_IN ),
.CLK_DCLK ( PIPE_DCLK_IN ),
.CLK_USERCLK1 ( PIPE_USERCLK1_IN ),
.CLK_USERCLK2 ( PIPE_USERCLK2_IN ),
.CLK_MMCM_LOCK ( PIPE_MMCM_LOCK_IN )
);
end
endgenerate
pcie_7x_v1_3 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK )
) pcie_7x_v1_3_i
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
// Rx
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Clocking Interface //
//----------------------------------------------------------------------------------------------------------------//
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_OOBCLK_IN ( 1'b0 ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
// TX
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
// Flow Control
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
.cfg_mgmt_do ( ),
.cfg_mgmt_rd_wr_done ( ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( ),
.cfg_pmcsr_powerstate ( ),
.cfg_pmcsr_pme_status ( ),
.cfg_received_func_lvl_rst ( ),
// Management Interface
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( cfg_mgmt_wr_en ),
.cfg_mgmt_rd_en ( cfg_mgmt_rd_en ),
.cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ),
// Error Reporting Interface
.cfg_err_ecrc ( cfg_err_ecrc ),
.cfg_err_ur ( cfg_err_ur ),
.cfg_err_cpl_timeout ( cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ),
.cfg_err_cpl_abort ( cfg_err_cpl_abort ),
.cfg_err_posted ( cfg_err_posted ),
.cfg_err_cor ( cfg_err_cor ),
.cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ),
.cfg_err_internal_cor ( cfg_err_internal_cor ),
.cfg_err_malformed ( cfg_err_malformed ),
.cfg_err_mc_blocked ( cfg_err_mc_blocked ),
.cfg_err_poisoned ( cfg_err_poisoned ),
.cfg_err_norecovery ( cfg_err_norecovery ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_err_locked ( cfg_err_locked ),
.cfg_err_acs ( cfg_err_acs ),
.cfg_err_internal_uncor ( cfg_err_internal_uncor ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_pm_wake ( cfg_pm_wake ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
.cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ),
.cfg_msg_received ( ),
.cfg_msg_data ( ),
.cfg_bridge_serr_en ( ),
.cfg_slot_control_electromech_il_ctl_pulse ( ),
.cfg_root_control_syserr_corr_err_en ( ),
.cfg_root_control_syserr_non_fatal_err_en ( ),
.cfg_root_control_syserr_fatal_err_en ( ),
.cfg_root_control_pme_int_en ( ),
.cfg_aer_rooterr_corr_err_reporting_en ( ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_corr_err_received ( ),
.cfg_aer_rooterr_non_fatal_err_received ( ),
.cfg_aer_rooterr_fatal_err_received ( ),
.cfg_msg_received_err_cor ( ),
.cfg_msg_received_err_non_fatal ( ),
.cfg_msg_received_err_fatal ( ),
.cfg_msg_received_pm_as_nak ( ),
.cfg_msg_received_pme_to_ack ( ),
.cfg_msg_received_assert_int_a ( ),
.cfg_msg_received_assert_int_b ( ),
.cfg_msg_received_assert_int_c ( ),
.cfg_msg_received_assert_int_d ( ),
.cfg_msg_received_deassert_int_a ( ),
.cfg_msg_received_deassert_int_b ( ),
.cfg_msg_received_deassert_int_c ( ),
.cfg_msg_received_deassert_int_d ( ),
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_phy_lnk_up ( ),
.pl_tx_pm_state ( ),
.pl_rx_pm_state ( ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_directed_change_done ( ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.pl_received_hot_rst ( pl_received_hot_rst ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.pl_transmit_hot_rst ( 1'b0 ),
.pl_downstream_deemph_source ( 1'b0 ),
//----------------------------------------------------------------------------------------------------------------//
// 6. AER Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_vc_tcvc_map ( ),
//----------------------------------------------------------------------------------------------------------------//
// 8. System (SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
.sys_clk ( sys_clk ),
.sys_reset ( ~sys_rst_n_c )
);
pcie_app_7x #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ )
)app (
//----------------------------------------------------------------------------------------------------------------//
// 1. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk ( user_clk ),
.user_reset ( user_reset_q ),
.user_lnk_up ( user_lnk_up_q ),
// Tx
.tx_buf_av ( tx_buf_av ),
.tx_cfg_req ( tx_cfg_req ),
.tx_err_drop ( tx_err_drop ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
// Flow Control
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_cor ( cfg_err_cor ),
.cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ),
.cfg_err_internal_cor ( cfg_err_internal_cor ),
.cfg_err_malformed ( cfg_err_malformed ),
.cfg_err_mc_blocked ( cfg_err_mc_blocked ),
.cfg_err_poisoned ( cfg_err_poisoned ),
.cfg_err_norecovery ( cfg_err_norecovery ),
.cfg_err_ur ( cfg_err_ur ),
.cfg_err_ecrc ( cfg_err_ecrc ),
.cfg_err_cpl_timeout ( cfg_err_cpl_timeout ),
.cfg_err_cpl_abort ( cfg_err_cpl_abort ),
.cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ),
.cfg_err_posted ( cfg_err_posted ),
.cfg_err_locked ( cfg_err_locked ),
.cfg_err_acs ( cfg_err_acs ), //1'b0 ),
.cfg_err_internal_uncor ( cfg_err_internal_uncor ), //1'b0 ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_dsn ( cfg_dsn ),
//----------------------------------------------------------------------------------------------------------------//
// 3. Management (MGMT) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( cfg_mgmt_wr_en ),
.cfg_mgmt_rd_en ( cfg_mgmt_rd_en ),
.cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ),
//----------------------------------------------------------------------------------------------------------------//
// 3. Advanced Error Reporting (AER) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_received_hot_rst ( pl_received_hot_rst ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_PP_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:56:57 08/14/2013
// Design Name: controlador
// Module Name: C:/Users/Fabian/Desktop/Laboratorio 1/SieteSegmentosCompuertas/asdasd.v
// Project Name: controlador_7seg
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: controlador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module asdasd;
// Inputs
reg ent1;
reg ent2;
reg ent3;
reg ent4;
reg clk;
reg btn0;
reg btn1;
reg btn2;
reg btn3;
// Outputs
wire salA;
wire salB;
wire salC;
wire salD;
wire salE;
wire salF;
wire salG;
wire led0;
wire led1;
wire led2;
wire led3;
// Instantiate the Unit Under Test (UUT)
controlador uut (
.ent1(ent1),
.ent2(ent2),
.ent3(ent3),
.ent4(ent4),
.salA(salA),
.salB(salB),
.salC(salC),
.salD(salD),
.salE(salE),
.salF(salF),
.salG(salG),
.clk(clk),
.btn0(btn0),
.btn1(btn1),
.btn2(btn2),
.btn3(btn3),
.led0(led0),
.led1(led1),
.led2(led2),
.led3(led3)
);
initial begin
// Initialize Inputs
ent1 = 0;
ent2 = 0;
ent3 = 0;
ent4 = 0;
clk = 0;
btn0 = 0;
btn1 = 0;
btn2 = 0;
btn3 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "m26_rx/m26_rx.v"
`include "m26_rx/m26_rx_core.v"
`include "m26_rx/m26_rx_ch.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/cdc_reset_sync.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "utils/IDDR_sim.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam SEQ_GEN_BASEADDR = 32'h1000;
localparam SEQ_GEN_HIGHADDR = 32'h3000-1;
localparam M26_RX_BASEADDR = 32'h3000;
localparam M26_RX_HIGHADDR = 32'h5000 - 1;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000 - 1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire [7:0] SEQ_OUT;
seq_gen
#(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(8*1024),
.OUT_BITS(8)
) i_seq_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(1'b0),
.SEQ_CLK(BUS_CLK),
.SEQ_OUT(SEQ_OUT)
);
wire FIFO_READ_RX;
wire FIFO_EMPTY_RX;
wire [31:0] FIFO_DATA_RX;
//safe clock domain crossing synchronization
reg [31:0] TIMESTAMP, timestamp_gray;
always@(posedge BUS_CLK)
TIMESTAMP <= 32'haa55bb44;
always@(posedge BUS_CLK)
timestamp_gray <= (TIMESTAMP>>1) ^ TIMESTAMP;
reg [31:0] timestamp_cdc0, timestamp_cdc1, timestamp_m26;
always@(posedge BUS_CLK) begin
timestamp_cdc0 <= timestamp_gray;
timestamp_cdc1 <= timestamp_cdc0;
end
integer gbi;
always@(*) begin
timestamp_m26[31] = timestamp_cdc1[31];
for(gbi =30; gbi >= 0; gbi = gbi -1) begin
timestamp_m26[gbi] = timestamp_cdc1[gbi] ^ timestamp_m26[gbi+1];
end
end
m26_rx
#(
.BASEADDR(M26_RX_BASEADDR),
.HIGHADDR(M26_RX_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_m26_rx
(
.CLK_RX(BUS_CLK),
.MKD_RX(SEQ_OUT[0]),
.DATA_RX(SEQ_OUT[2:1]),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ(FIFO_READ_RX),
.FIFO_EMPTY(FIFO_EMPTY_RX),
.FIFO_DATA(FIFO_DATA_RX),
.TIMESTAMP(timestamp_m26),
.LOST_ERROR()
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_RX;
assign FIFO_EMPTY = FIFO_EMPTY_RX;
assign FIFO_READ_RX = FIFO_READ;
bram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("m26.vcd");
$dumpvars(0);
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8. The
// currently supported write data delays do not require this
// functionality, but preserve for future use.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr
always @(wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
wire [4:0] wb_wr_data_addr_w;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data_w;
reg [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff
app_wdf_mask_ns1, app_wdf_data_ns1};
wire [4:0] rd_addr_w;
assign rd_addr_w = {wr_data_addr, wr_data_offset};
always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data_w[((i*6)+4)+:2]),
.DOB(wr_buf_out_data_w[((i*6)+2)+:2]),
.DOC(wr_buf_out_data_w[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_w),
.ADDRB(rd_addr_w),
.ADDRC(rd_addr_w),
.ADDRD(wb_wr_data_addr_w),
.WE(wdf_rdy_ns),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [2*nCK_PER_CLK-1:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:4];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_4_V
`define SKY130_FD_SC_LS__OR3_4_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_4_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_streeOg_DSP48_3(
input [9 - 1:0] in0,
input [23 - 1:0] in1,
input [31 - 1:0] in2,
output [32 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in1);
assign b = $signed(in0);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_streeOg(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_streeOg_DSP48_3 hls_contrast_streeOg_DSP48_3_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221AI_SYMBOL_V
`define SKY130_FD_SC_HDLL__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221AI_SYMBOL_V
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 30th May 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: PLL1_sim.v,v 1.2 2017/06/13 14:37:16 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/test/verilog/PLL1_sim.v,v $
//
//=============================================================
// Simple simulation model of the PLL1 component.
`timescale 1 ps / 1 ps
module PLL1 (
inclk0,
c0,
c1,
c2
);
input inclk0;
output c0;
output c1;
output c2;
altpll altpll_component (
.inclk0 (inclk0),
.c0 (c0),
.c1 (c1),
.c2 (c2)
);
endmodule
module altpll #(
parameter inclk0_input_frequency = 20000,
parameter clk0_multiply_by = 4,
parameter clk0_divide_by = 5,
parameter clk0_phase_shift = "0",
parameter clk1_multiply_by = 4,
parameter clk1_divide_by = 5,
parameter clk1_phase_shift = "0",
parameter clk2_multiply_by = 8,
parameter clk2_divide_by = 5,
parameter clk2_phase_shift = "0")(
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
reg c0;
reg c1;
reg c2;
integer phase0;
integer phase1;
integer phase2;
// Convert string to integer with sign
function integer str2int;
input [8*16:1] s;
reg [8*16:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
integer m, magnitude;
integer sign;
begin
sign = 1;
magnitude = 0;
reg_s = s;
for (m=1; m<=16; m=m+1)
begin
tmp = reg_s[128:121];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
// Accumulate ascii digits 0-9 only.
if ((tmp >= 48) && (tmp <= 57))
magnitude = (magnitude * 10) + digit;
if (tmp == 45)
sign = -1; // Found a '-' character, i.e. number is negative.
end
str2int = sign * magnitude;
end
endfunction
// Convert phase delay to integer
function integer get_int_phase_shift;
input [8*16:1] s;
input i_phase_shift;
integer i_phase_shift;
begin
if (i_phase_shift != 0)
begin
get_int_phase_shift = i_phase_shift;
end
else
begin
get_int_phase_shift = str2int(s);
end
end
endfunction
initial
begin
c0 = 1'b1;
phase0 = get_int_phase_shift(clk0_phase_shift, 0);
@(negedge inclk0);
@(posedge inclk0);
#(phase0)
forever #(((inclk0_input_frequency*clk0_divide_by)/clk0_multiply_by)/2) c0 = ~c0;
end
initial
begin
c1 = 1'b1;
phase1 = get_int_phase_shift(clk1_phase_shift, 0);
@(negedge inclk0);
@(posedge inclk0);
#(phase1)
forever #(((inclk0_input_frequency*clk1_divide_by)/clk1_multiply_by)/2) c1 = ~c1;
end
initial
begin
c2 = 1'b1;
phase2 = get_int_phase_shift(clk2_phase_shift, 0);
@(negedge inclk0);
@(posedge inclk0);
#(phase2)
forever #(((inclk0_input_frequency*clk2_divide_by)/clk2_multiply_by)/2) c2 = ~c2;
end
endmodule
|
// video_sys.v
// Generated using ACDS version 12.1sp1 243 at 2015.02.21.16:07:45
`timescale 1 ps / 1 ps
module video_sys (
output wire VGA_CLK_from_the_VGA_Controller, // VGA_Controller_external_interface.CLK
output wire VGA_HS_from_the_VGA_Controller, // .HS
output wire VGA_VS_from_the_VGA_Controller, // .VS
output wire VGA_BLANK_from_the_VGA_Controller, // .BLANK
output wire VGA_SYNC_from_the_VGA_Controller, // .SYNC
output wire [9:0] VGA_R_from_the_VGA_Controller, // .R
output wire [9:0] VGA_G_from_the_VGA_Controller, // .G
output wire [9:0] VGA_B_from_the_VGA_Controller, // .B
output wire clock_signals_sdram_clk_clk, // clock_signals_sdram_clk.clk
input wire clk_0, // clk_0_clk_in.clk
input wire reset_n, // clk_0_clk_in_reset.reset_n
inout wire I2C_SDAT_to_and_from_the_AV_Config, // AV_Config_external_interface.SDAT
output wire I2C_SCLK_from_the_AV_Config, // .SCLK
output wire [11:0] sdram_0_wire_addr, // sdram_0_wire.addr
output wire [1:0] sdram_0_wire_ba, // .ba
output wire sdram_0_wire_cas_n, // .cas_n
output wire sdram_0_wire_cke, // .cke
output wire sdram_0_wire_cs_n, // .cs_n
inout wire [15:0] sdram_0_wire_dq, // .dq
output wire [1:0] sdram_0_wire_dqm, // .dqm
output wire sdram_0_wire_ras_n, // .ras_n
output wire sdram_0_wire_we_n, // .we_n
inout wire [15:0] SRAM_DQ_to_and_from_the_Pixel_Buffer, // Pixel_Buffer_external_interface.DQ
output wire [17:0] SRAM_ADDR_from_the_Pixel_Buffer, // .ADDR
output wire SRAM_LB_N_from_the_Pixel_Buffer, // .LB_N
output wire SRAM_UB_N_from_the_Pixel_Buffer, // .UB_N
output wire SRAM_CE_N_from_the_Pixel_Buffer, // .CE_N
output wire SRAM_OE_N_from_the_Pixel_Buffer, // .OE_N
output wire SRAM_WE_N_from_the_Pixel_Buffer, // .WE_N
input wire TD_CLK27_to_the_Video_In_Decoder, // Video_In_Decoder_external_interface.TD_CLK27
input wire [7:0] TD_DATA_to_the_Video_In_Decoder, // .TD_DATA
input wire TD_HS_to_the_Video_In_Decoder, // .TD_HS
input wire TD_VS_to_the_Video_In_Decoder, // .TD_VS
output wire TD_RESET_from_the_Video_In_Decoder, // .TD_RESET
output wire overflow_flag_from_the_Video_In_Decoder, // .overflow_flag
output wire [7:0] led_external_connection_export // led_external_connection.export
);
wire pixel_scaler_avalon_scaler_source_endofpacket; // Pixel_Scaler:stream_out_endofpacket -> Dual_Clock_FIFO:stream_in_endofpacket
wire pixel_scaler_avalon_scaler_source_valid; // Pixel_Scaler:stream_out_valid -> Dual_Clock_FIFO:stream_in_valid
wire pixel_scaler_avalon_scaler_source_startofpacket; // Pixel_Scaler:stream_out_startofpacket -> Dual_Clock_FIFO:stream_in_startofpacket
wire [29:0] pixel_scaler_avalon_scaler_source_data; // Pixel_Scaler:stream_out_data -> Dual_Clock_FIFO:stream_in_data
wire pixel_scaler_avalon_scaler_source_ready; // Dual_Clock_FIFO:stream_in_ready -> Pixel_Scaler:stream_out_ready
wire pixel_rgb_resampler_avalon_rgb_source_endofpacket; // Pixel_RGB_Resampler:stream_out_endofpacket -> Pixel_Scaler:stream_in_endofpacket
wire pixel_rgb_resampler_avalon_rgb_source_valid; // Pixel_RGB_Resampler:stream_out_valid -> Pixel_Scaler:stream_in_valid
wire pixel_rgb_resampler_avalon_rgb_source_startofpacket; // Pixel_RGB_Resampler:stream_out_startofpacket -> Pixel_Scaler:stream_in_startofpacket
wire [29:0] pixel_rgb_resampler_avalon_rgb_source_data; // Pixel_RGB_Resampler:stream_out_data -> Pixel_Scaler:stream_in_data
wire pixel_rgb_resampler_avalon_rgb_source_ready; // Pixel_Scaler:stream_in_ready -> Pixel_RGB_Resampler:stream_out_ready
wire pixel_buffer_dma_avalon_pixel_source_endofpacket; // Pixel_Buffer_DMA:stream_endofpacket -> Pixel_RGB_Resampler:stream_in_endofpacket
wire pixel_buffer_dma_avalon_pixel_source_valid; // Pixel_Buffer_DMA:stream_valid -> Pixel_RGB_Resampler:stream_in_valid
wire pixel_buffer_dma_avalon_pixel_source_startofpacket; // Pixel_Buffer_DMA:stream_startofpacket -> Pixel_RGB_Resampler:stream_in_startofpacket
wire [15:0] pixel_buffer_dma_avalon_pixel_source_data; // Pixel_Buffer_DMA:stream_data -> Pixel_RGB_Resampler:stream_in_data
wire pixel_buffer_dma_avalon_pixel_source_ready; // Pixel_RGB_Resampler:stream_in_ready -> Pixel_Buffer_DMA:stream_ready
wire dual_clock_fifo_avalon_dc_buffer_source_endofpacket; // Dual_Clock_FIFO:stream_out_endofpacket -> VGA_Controller:endofpacket
wire dual_clock_fifo_avalon_dc_buffer_source_valid; // Dual_Clock_FIFO:stream_out_valid -> VGA_Controller:valid
wire dual_clock_fifo_avalon_dc_buffer_source_startofpacket; // Dual_Clock_FIFO:stream_out_startofpacket -> VGA_Controller:startofpacket
wire [29:0] dual_clock_fifo_avalon_dc_buffer_source_data; // Dual_Clock_FIFO:stream_out_data -> VGA_Controller:data
wire dual_clock_fifo_avalon_dc_buffer_source_ready; // VGA_Controller:ready -> Dual_Clock_FIFO:stream_out_ready
wire video_in_decoder_avalon_decoder_source_endofpacket; // Video_In_Decoder:stream_out_endofpacket -> Chroma_Resampler:stream_in_endofpacket
wire video_in_decoder_avalon_decoder_source_valid; // Video_In_Decoder:stream_out_valid -> Chroma_Resampler:stream_in_valid
wire video_in_decoder_avalon_decoder_source_startofpacket; // Video_In_Decoder:stream_out_startofpacket -> Chroma_Resampler:stream_in_startofpacket
wire [15:0] video_in_decoder_avalon_decoder_source_data; // Video_In_Decoder:stream_out_data -> Chroma_Resampler:stream_in_data
wire video_in_decoder_avalon_decoder_source_ready; // Chroma_Resampler:stream_in_ready -> Video_In_Decoder:stream_out_ready
wire chroma_resampler_avalon_chroma_source_endofpacket; // Chroma_Resampler:stream_out_endofpacket -> Color_Space_Converter:stream_in_endofpacket
wire chroma_resampler_avalon_chroma_source_valid; // Chroma_Resampler:stream_out_valid -> Color_Space_Converter:stream_in_valid
wire chroma_resampler_avalon_chroma_source_startofpacket; // Chroma_Resampler:stream_out_startofpacket -> Color_Space_Converter:stream_in_startofpacket
wire [23:0] chroma_resampler_avalon_chroma_source_data; // Chroma_Resampler:stream_out_data -> Color_Space_Converter:stream_in_data
wire chroma_resampler_avalon_chroma_source_ready; // Color_Space_Converter:stream_in_ready -> Chroma_Resampler:stream_out_ready
wire color_space_converter_avalon_csc_source_endofpacket; // Color_Space_Converter:stream_out_endofpacket -> Video_RGB_Resampler:stream_in_endofpacket
wire color_space_converter_avalon_csc_source_valid; // Color_Space_Converter:stream_out_valid -> Video_RGB_Resampler:stream_in_valid
wire color_space_converter_avalon_csc_source_startofpacket; // Color_Space_Converter:stream_out_startofpacket -> Video_RGB_Resampler:stream_in_startofpacket
wire [23:0] color_space_converter_avalon_csc_source_data; // Color_Space_Converter:stream_out_data -> Video_RGB_Resampler:stream_in_data
wire color_space_converter_avalon_csc_source_ready; // Video_RGB_Resampler:stream_in_ready -> Color_Space_Converter:stream_out_ready
wire video_rgb_resampler_avalon_rgb_source_endofpacket; // Video_RGB_Resampler:stream_out_endofpacket -> Video_Clipper:stream_in_endofpacket
wire video_rgb_resampler_avalon_rgb_source_valid; // Video_RGB_Resampler:stream_out_valid -> Video_Clipper:stream_in_valid
wire video_rgb_resampler_avalon_rgb_source_startofpacket; // Video_RGB_Resampler:stream_out_startofpacket -> Video_Clipper:stream_in_startofpacket
wire [15:0] video_rgb_resampler_avalon_rgb_source_data; // Video_RGB_Resampler:stream_out_data -> Video_Clipper:stream_in_data
wire video_rgb_resampler_avalon_rgb_source_ready; // Video_Clipper:stream_in_ready -> Video_RGB_Resampler:stream_out_ready
wire video_clipper_avalon_clipper_source_endofpacket; // Video_Clipper:stream_out_endofpacket -> Video_Scaler:stream_in_endofpacket
wire video_clipper_avalon_clipper_source_valid; // Video_Clipper:stream_out_valid -> Video_Scaler:stream_in_valid
wire video_clipper_avalon_clipper_source_startofpacket; // Video_Clipper:stream_out_startofpacket -> Video_Scaler:stream_in_startofpacket
wire [15:0] video_clipper_avalon_clipper_source_data; // Video_Clipper:stream_out_data -> Video_Scaler:stream_in_data
wire video_clipper_avalon_clipper_source_ready; // Video_Scaler:stream_in_ready -> Video_Clipper:stream_out_ready
wire video_scaler_avalon_scaler_source_endofpacket; // Video_Scaler:stream_out_endofpacket -> Video_DMA:stream_endofpacket
wire video_scaler_avalon_scaler_source_valid; // Video_Scaler:stream_out_valid -> Video_DMA:stream_valid
wire video_scaler_avalon_scaler_source_startofpacket; // Video_Scaler:stream_out_startofpacket -> Video_DMA:stream_startofpacket
wire [15:0] video_scaler_avalon_scaler_source_data; // Video_Scaler:stream_out_data -> Video_DMA:stream_data
wire video_scaler_avalon_scaler_source_ready; // Video_DMA:stream_ready -> Video_Scaler:stream_out_ready
wire clock_signals_sys_clk_clk; // Clock_Signals:sys_clk -> [AV_Config:clk, AV_Config_avalon_av_config_slave_translator:clk, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:clk, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, CPU:clk, CPU_data_master_translator:clk, CPU_data_master_translator_avalon_universal_master_0_agent:clk, CPU_instruction_master_translator:clk, CPU_instruction_master_translator_avalon_universal_master_0_agent:clk, CPU_jtag_debug_module_translator:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Chroma_Resampler:clk, Color_Space_Converter:clk, Dual_Clock_FIFO:clk_stream_in, LED:clk, LED_s1_translator:clk, LED_s1_translator_avalon_universal_slave_0_agent:clk, LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Onchip_Memory:clk, Onchip_Memory_s1_translator:clk, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:clk, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer:clk, Pixel_Buffer_DMA:clk, Pixel_Buffer_DMA_avalon_control_slave_translator:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:clk, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:clk, Pixel_Buffer_avalon_sram_slave_translator:clk, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Pixel_RGB_Resampler:clk, Pixel_Scaler:clk, Video_Clipper:clk, Video_DMA:clk, Video_DMA_avalon_dma_control_slave_translator:clk, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:clk, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, Video_DMA_avalon_dma_master_translator:clk, Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:clk, Video_In_Decoder:clk, Video_RGB_Resampler:clk, Video_Scaler:clk, addr_router:clk, addr_router_001:clk, addr_router_002:clk, addr_router_003:clk, burst_adapter:clk, burst_adapter_001:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_demux_002:clk, cmd_xbar_demux_003:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, id_router_008:clk, id_router_009:clk, id_router_010:clk, irq_mapper:clk, jtag_uart_0:clk, jtag_uart_0_avalon_jtag_slave_translator:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_demux_008:clk, rsp_xbar_demux_009:clk, rsp_xbar_demux_010:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid_qsys_0:clock, sysid_qsys_0_control_slave_translator:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, timer_0:clk, timer_0_s1_translator:clk, timer_0_s1_translator_avalon_universal_slave_0_agent:clk, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk, width_adapter_006:clk, width_adapter_007:clk]
wire clock_signals_vga_clk_clk; // Clock_Signals:VGA_CLK -> [Dual_Clock_FIFO:clk_stream_out, VGA_Controller:clk, rst_controller_001:clk]
wire cpu_instruction_master_waitrequest; // CPU_instruction_master_translator:av_waitrequest -> CPU:i_waitrequest
wire [24:0] cpu_instruction_master_address; // CPU:i_address -> CPU_instruction_master_translator:av_address
wire cpu_instruction_master_read; // CPU:i_read -> CPU_instruction_master_translator:av_read
wire [31:0] cpu_instruction_master_readdata; // CPU_instruction_master_translator:av_readdata -> CPU:i_readdata
wire cpu_data_master_waitrequest; // CPU_data_master_translator:av_waitrequest -> CPU:d_waitrequest
wire [31:0] cpu_data_master_writedata; // CPU:d_writedata -> CPU_data_master_translator:av_writedata
wire [24:0] cpu_data_master_address; // CPU:d_address -> CPU_data_master_translator:av_address
wire cpu_data_master_write; // CPU:d_write -> CPU_data_master_translator:av_write
wire cpu_data_master_read; // CPU:d_read -> CPU_data_master_translator:av_read
wire [31:0] cpu_data_master_readdata; // CPU_data_master_translator:av_readdata -> CPU:d_readdata
wire cpu_data_master_debugaccess; // CPU:jtag_debug_module_debugaccess_to_roms -> CPU_data_master_translator:av_debugaccess
wire [3:0] cpu_data_master_byteenable; // CPU:d_byteenable -> CPU_data_master_translator:av_byteenable
wire pixel_buffer_dma_avalon_pixel_dma_master_waitrequest; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_waitrequest -> Pixel_Buffer_DMA:master_waitrequest
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_address; // Pixel_Buffer_DMA:master_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_address
wire pixel_buffer_dma_avalon_pixel_dma_master_lock; // Pixel_Buffer_DMA:master_arbiterlock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_lock
wire pixel_buffer_dma_avalon_pixel_dma_master_read; // Pixel_Buffer_DMA:master_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_read
wire [15:0] pixel_buffer_dma_avalon_pixel_dma_master_readdata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdata -> Pixel_Buffer_DMA:master_readdata
wire pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:av_readdatavalid -> Pixel_Buffer_DMA:master_readdatavalid
wire video_dma_avalon_dma_master_waitrequest; // Video_DMA_avalon_dma_master_translator:av_waitrequest -> Video_DMA:master_waitrequest
wire [15:0] video_dma_avalon_dma_master_writedata; // Video_DMA:master_writedata -> Video_DMA_avalon_dma_master_translator:av_writedata
wire [31:0] video_dma_avalon_dma_master_address; // Video_DMA:master_address -> Video_DMA_avalon_dma_master_translator:av_address
wire video_dma_avalon_dma_master_write; // Video_DMA:master_write -> Video_DMA_avalon_dma_master_translator:av_write
wire [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // CPU_jtag_debug_module_translator:av_writedata -> CPU:jtag_debug_module_writedata
wire [8:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_address; // CPU_jtag_debug_module_translator:av_address -> CPU:jtag_debug_module_address
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // CPU_jtag_debug_module_translator:av_chipselect -> CPU:jtag_debug_module_select
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_write; // CPU_jtag_debug_module_translator:av_write -> CPU:jtag_debug_module_write
wire [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // CPU:jtag_debug_module_readdata -> CPU_jtag_debug_module_translator:av_readdata
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // CPU_jtag_debug_module_translator:av_begintransfer -> CPU:jtag_debug_module_begintransfer
wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // CPU_jtag_debug_module_translator:av_debugaccess -> CPU:jtag_debug_module_debugaccess
wire [3:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // CPU_jtag_debug_module_translator:av_byteenable -> CPU:jtag_debug_module_byteenable
wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_writedata; // Onchip_Memory_s1_translator:av_writedata -> Onchip_Memory:writedata
wire [11:0] onchip_memory_s1_translator_avalon_anti_slave_0_address; // Onchip_Memory_s1_translator:av_address -> Onchip_Memory:address
wire onchip_memory_s1_translator_avalon_anti_slave_0_chipselect; // Onchip_Memory_s1_translator:av_chipselect -> Onchip_Memory:chipselect
wire onchip_memory_s1_translator_avalon_anti_slave_0_clken; // Onchip_Memory_s1_translator:av_clken -> Onchip_Memory:clken
wire onchip_memory_s1_translator_avalon_anti_slave_0_write; // Onchip_Memory_s1_translator:av_write -> Onchip_Memory:write
wire [31:0] onchip_memory_s1_translator_avalon_anti_slave_0_readdata; // Onchip_Memory:readdata -> Onchip_Memory_s1_translator:av_readdata
wire [3:0] onchip_memory_s1_translator_avalon_anti_slave_0_byteenable; // Onchip_Memory_s1_translator:av_byteenable -> Onchip_Memory:byteenable
wire sdram_0_s1_translator_avalon_anti_slave_0_waitrequest; // sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_writedata; // sdram_0_s1_translator:av_writedata -> sdram_0:az_data
wire [21:0] sdram_0_s1_translator_avalon_anti_slave_0_address; // sdram_0_s1_translator:av_address -> sdram_0:az_addr
wire sdram_0_s1_translator_avalon_anti_slave_0_chipselect; // sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
wire sdram_0_s1_translator_avalon_anti_slave_0_write; // sdram_0_s1_translator:av_write -> sdram_0:az_wr_n
wire sdram_0_s1_translator_avalon_anti_slave_0_read; // sdram_0_s1_translator:av_read -> sdram_0:az_rd_n
wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_readdata; // sdram_0:za_data -> sdram_0_s1_translator:av_readdata
wire sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid; // sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
wire [1:0] sdram_0_s1_translator_avalon_anti_slave_0_byteenable; // sdram_0_s1_translator:av_byteenable -> sdram_0:az_be_n
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata; // Pixel_Buffer_avalon_sram_slave_translator:av_writedata -> Pixel_Buffer:writedata
wire [17:0] pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address; // Pixel_Buffer_avalon_sram_slave_translator:av_address -> Pixel_Buffer:address
wire pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write; // Pixel_Buffer_avalon_sram_slave_translator:av_write -> Pixel_Buffer:write
wire pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read; // Pixel_Buffer_avalon_sram_slave_translator:av_read -> Pixel_Buffer:read
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata; // Pixel_Buffer:readdata -> Pixel_Buffer_avalon_sram_slave_translator:av_readdata
wire pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid; // Pixel_Buffer:readdatavalid -> Pixel_Buffer_avalon_sram_slave_translator:av_readdatavalid
wire [1:0] pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable; // Pixel_Buffer_avalon_sram_slave_translator:av_byteenable -> Pixel_Buffer:byteenable
wire av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest; // AV_Config:waitrequest -> AV_Config_avalon_av_config_slave_translator:av_waitrequest
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata; // AV_Config_avalon_av_config_slave_translator:av_writedata -> AV_Config:writedata
wire [1:0] av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address; // AV_Config_avalon_av_config_slave_translator:av_address -> AV_Config:address
wire av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write; // AV_Config_avalon_av_config_slave_translator:av_write -> AV_Config:write
wire av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read; // AV_Config_avalon_av_config_slave_translator:av_read -> AV_Config:read
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata; // AV_Config:readdata -> AV_Config_avalon_av_config_slave_translator:av_readdata
wire [3:0] av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable; // AV_Config_avalon_av_config_slave_translator:av_byteenable -> AV_Config:byteenable
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata; // Video_DMA_avalon_dma_control_slave_translator:av_writedata -> Video_DMA:slave_writedata
wire [1:0] video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address; // Video_DMA_avalon_dma_control_slave_translator:av_address -> Video_DMA:slave_address
wire video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write; // Video_DMA_avalon_dma_control_slave_translator:av_write -> Video_DMA:slave_write
wire video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read; // Video_DMA_avalon_dma_control_slave_translator:av_read -> Video_DMA:slave_read
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata; // Video_DMA:slave_readdata -> Video_DMA_avalon_dma_control_slave_translator:av_readdata
wire [3:0] video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable; // Video_DMA_avalon_dma_control_slave_translator:av_byteenable -> Video_DMA:slave_byteenable
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_writedata -> Pixel_Buffer_DMA:slave_writedata
wire [1:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_address -> Pixel_Buffer_DMA:slave_address
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_write -> Pixel_Buffer_DMA:slave_write
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_read -> Pixel_Buffer_DMA:slave_read
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata; // Pixel_Buffer_DMA:slave_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator:av_readdata
wire [3:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable; // Pixel_Buffer_DMA_avalon_control_slave_translator:av_byteenable -> Pixel_Buffer_DMA:slave_byteenable
wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_writedata; // timer_0_s1_translator:av_writedata -> timer_0:writedata
wire [2:0] timer_0_s1_translator_avalon_anti_slave_0_address; // timer_0_s1_translator:av_address -> timer_0:address
wire timer_0_s1_translator_avalon_anti_slave_0_chipselect; // timer_0_s1_translator:av_chipselect -> timer_0:chipselect
wire timer_0_s1_translator_avalon_anti_slave_0_write; // timer_0_s1_translator:av_write -> timer_0:write_n
wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_readdata; // timer_0:readdata -> timer_0_s1_translator:av_readdata
wire [0:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address; // sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata; // sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
wire [0:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0:av_write_n
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0:av_read_n
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
wire [31:0] led_s1_translator_avalon_anti_slave_0_writedata; // LED_s1_translator:av_writedata -> LED:writedata
wire [1:0] led_s1_translator_avalon_anti_slave_0_address; // LED_s1_translator:av_address -> LED:address
wire led_s1_translator_avalon_anti_slave_0_chipselect; // LED_s1_translator:av_chipselect -> LED:chipselect
wire led_s1_translator_avalon_anti_slave_0_write; // LED_s1_translator:av_write -> LED:write_n
wire [31:0] led_s1_translator_avalon_anti_slave_0_readdata; // LED:readdata -> LED_s1_translator:av_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // CPU_instruction_master_translator:uav_burstcount -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // CPU_instruction_master_translator:uav_writedata -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // CPU_instruction_master_translator:uav_address -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // CPU_instruction_master_translator:uav_lock -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // CPU_instruction_master_translator:uav_write -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // CPU_instruction_master_translator:uav_read -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // CPU_instruction_master_translator:uav_debugaccess -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // CPU_instruction_master_translator:uav_byteenable -> CPU_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // CPU_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_instruction_master_translator:uav_readdatavalid
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // CPU_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> CPU_data_master_translator:uav_waitrequest
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // CPU_data_master_translator:uav_burstcount -> CPU_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // CPU_data_master_translator:uav_writedata -> CPU_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_address; // CPU_data_master_translator:uav_address -> CPU_data_master_translator_avalon_universal_master_0_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_lock; // CPU_data_master_translator:uav_lock -> CPU_data_master_translator_avalon_universal_master_0_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // CPU_data_master_translator:uav_write -> CPU_data_master_translator_avalon_universal_master_0_agent:av_write
wire cpu_data_master_translator_avalon_universal_master_0_read; // CPU_data_master_translator:uav_read -> CPU_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // CPU_data_master_translator_avalon_universal_master_0_agent:av_readdata -> CPU_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // CPU_data_master_translator:uav_debugaccess -> CPU_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // CPU_data_master_translator:uav_byteenable -> CPU_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // CPU_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> CPU_data_master_translator:uav_readdatavalid
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_waitrequest
wire [1:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_burstcount -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [15:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_writedata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_address -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_address
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_lock -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_lock
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_write -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_write
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_read -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_read
wire [15:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdata
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_debugaccess -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [1:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_byteenable -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:uav_readdatavalid
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_waitrequest -> Video_DMA_avalon_dma_master_translator:uav_waitrequest
wire [1:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount; // Video_DMA_avalon_dma_master_translator:uav_burstcount -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [15:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata; // Video_DMA_avalon_dma_master_translator:uav_writedata -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_writedata
wire [31:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_address; // Video_DMA_avalon_dma_master_translator:uav_address -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_address
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock; // Video_DMA_avalon_dma_master_translator:uav_lock -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_lock
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_write; // Video_DMA_avalon_dma_master_translator:uav_write -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_write
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_read; // Video_DMA_avalon_dma_master_translator:uav_read -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_read
wire [15:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_readdata -> Video_DMA_avalon_dma_master_translator:uav_readdata
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess; // Video_DMA_avalon_dma_master_translator:uav_debugaccess -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [1:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable; // Video_DMA_avalon_dma_master_translator:uav_byteenable -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_byteenable
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> Video_DMA_avalon_dma_master_translator:uav_readdatavalid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // CPU_jtag_debug_module_translator:uav_waitrequest -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> CPU_jtag_debug_module_translator:uav_burstcount
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> CPU_jtag_debug_module_translator:uav_writedata
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> CPU_jtag_debug_module_translator:uav_address
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> CPU_jtag_debug_module_translator:uav_write
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> CPU_jtag_debug_module_translator:uav_lock
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> CPU_jtag_debug_module_translator:uav_read
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // CPU_jtag_debug_module_translator:uav_readdata -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // CPU_jtag_debug_module_translator:uav_readdatavalid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> CPU_jtag_debug_module_translator:uav_debugaccess
wire [3:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> CPU_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Onchip_Memory_s1_translator:uav_waitrequest -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> Onchip_Memory_s1_translator:uav_burstcount
wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> Onchip_Memory_s1_translator:uav_writedata
wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_address -> Onchip_Memory_s1_translator:uav_address
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_write -> Onchip_Memory_s1_translator:uav_write
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_lock -> Onchip_Memory_s1_translator:uav_lock
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_read -> Onchip_Memory_s1_translator:uav_read
wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // Onchip_Memory_s1_translator:uav_readdata -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Onchip_Memory_s1_translator:uav_readdatavalid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Onchip_Memory_s1_translator:uav_debugaccess
wire [3:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> Onchip_Memory_s1_translator:uav_byteenable
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
wire [31:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [89:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [89:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Pixel_Buffer_avalon_sram_slave_translator:uav_waitrequest -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_avalon_sram_slave_translator:uav_burstcount
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_avalon_sram_slave_translator:uav_writedata
wire [31:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_avalon_sram_slave_translator:uav_address
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_avalon_sram_slave_translator:uav_write
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_avalon_sram_slave_translator:uav_lock
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_avalon_sram_slave_translator:uav_read
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Pixel_Buffer_avalon_sram_slave_translator:uav_readdata -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Pixel_Buffer_avalon_sram_slave_translator:uav_readdatavalid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_avalon_sram_slave_translator:uav_debugaccess
wire [1:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_avalon_sram_slave_translator:uav_byteenable
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [89:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [89:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [15:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // AV_Config_avalon_av_config_slave_translator:uav_waitrequest -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> AV_Config_avalon_av_config_slave_translator:uav_burstcount
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> AV_Config_avalon_av_config_slave_translator:uav_writedata
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_address -> AV_Config_avalon_av_config_slave_translator:uav_address
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_write -> AV_Config_avalon_av_config_slave_translator:uav_write
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_lock -> AV_Config_avalon_av_config_slave_translator:uav_lock
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_read -> AV_Config_avalon_av_config_slave_translator:uav_read
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // AV_Config_avalon_av_config_slave_translator:uav_readdata -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // AV_Config_avalon_av_config_slave_translator:uav_readdatavalid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> AV_Config_avalon_av_config_slave_translator:uav_debugaccess
wire [3:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> AV_Config_avalon_av_config_slave_translator:uav_byteenable
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Video_DMA_avalon_dma_control_slave_translator:uav_waitrequest -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Video_DMA_avalon_dma_control_slave_translator:uav_burstcount
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Video_DMA_avalon_dma_control_slave_translator:uav_writedata
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Video_DMA_avalon_dma_control_slave_translator:uav_address
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Video_DMA_avalon_dma_control_slave_translator:uav_write
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Video_DMA_avalon_dma_control_slave_translator:uav_lock
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Video_DMA_avalon_dma_control_slave_translator:uav_read
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Video_DMA_avalon_dma_control_slave_translator:uav_readdata -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Video_DMA_avalon_dma_control_slave_translator:uav_readdatavalid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Video_DMA_avalon_dma_control_slave_translator:uav_debugaccess
wire [3:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Video_DMA_avalon_dma_control_slave_translator:uav_byteenable
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_waitrequest -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_burstcount
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_writedata
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_address
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_write
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_lock
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_read
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdata -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // Pixel_Buffer_DMA_avalon_control_slave_translator:uav_readdatavalid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_debugaccess
wire [3:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> Pixel_Buffer_DMA_avalon_control_slave_translator:uav_byteenable
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
wire [3:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
wire [3:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // LED_s1_translator:uav_waitrequest -> LED_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // LED_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> LED_s1_translator:uav_burstcount
wire [31:0] led_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // LED_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> LED_s1_translator:uav_writedata
wire [31:0] led_s1_translator_avalon_universal_slave_0_agent_m0_address; // LED_s1_translator_avalon_universal_slave_0_agent:m0_address -> LED_s1_translator:uav_address
wire led_s1_translator_avalon_universal_slave_0_agent_m0_write; // LED_s1_translator_avalon_universal_slave_0_agent:m0_write -> LED_s1_translator:uav_write
wire led_s1_translator_avalon_universal_slave_0_agent_m0_lock; // LED_s1_translator_avalon_universal_slave_0_agent:m0_lock -> LED_s1_translator:uav_lock
wire led_s1_translator_avalon_universal_slave_0_agent_m0_read; // LED_s1_translator_avalon_universal_slave_0_agent:m0_read -> LED_s1_translator:uav_read
wire [31:0] led_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // LED_s1_translator:uav_readdata -> LED_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // LED_s1_translator:uav_readdatavalid -> LED_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // LED_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> LED_s1_translator:uav_debugaccess
wire [3:0] led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // LED_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> LED_s1_translator:uav_byteenable
wire led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // LED_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // LED_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // LED_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [107:0] led_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // LED_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> LED_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> LED_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> LED_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> LED_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [107:0] led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> LED_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // LED_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // LED_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> LED_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [31:0] led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // LED_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> LED_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // LED_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> LED_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [106:0] cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> CPU_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [106:0] cpu_data_master_translator_avalon_universal_master_0_agent_cp_data; // CPU_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> CPU_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_002:sink_endofpacket
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_002:sink_valid
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_002:sink_startofpacket
wire [88:0] pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_002:sink_data
wire pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_002:sink_ready -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:cp_ready
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_003:sink_endofpacket
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_003:sink_valid
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_003:sink_startofpacket
wire [88:0] video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_003:sink_data
wire video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_003:sink_ready -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:cp_ready
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [106:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [106:0] onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [88:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [88:0] pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [106:0] av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [106:0] video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
wire [106:0] pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
wire pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
wire [106:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
wire [106:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
wire [106:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // LED_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
wire led_s1_translator_avalon_universal_slave_0_agent_rp_valid; // LED_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
wire led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // LED_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
wire [106:0] led_s1_translator_avalon_universal_slave_0_agent_rp_data; // LED_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
wire led_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> LED_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [88:0] burst_adapter_source0_data; // burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [10:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire burst_adapter_001_source0_endofpacket; // burst_adapter_001:source0_endofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_001_source0_valid; // burst_adapter_001:source0_valid -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_001_source0_startofpacket; // burst_adapter_001:source0_startofpacket -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [88:0] burst_adapter_001_source0_data; // burst_adapter_001:source0_data -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_001_source0_ready; // Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
wire [10:0] burst_adapter_001_source0_channel; // burst_adapter_001:source0_channel -> Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [AV_Config:reset, AV_Config_avalon_av_config_slave_translator:reset, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:reset, AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, CPU:reset_n, CPU_data_master_translator:reset, CPU_data_master_translator_avalon_universal_master_0_agent:reset, CPU_instruction_master_translator:reset, CPU_instruction_master_translator_avalon_universal_master_0_agent:reset, CPU_jtag_debug_module_translator:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Chroma_Resampler:reset, Color_Space_Converter:reset, Dual_Clock_FIFO:reset_stream_in, LED:reset_n, LED_s1_translator:reset, LED_s1_translator_avalon_universal_slave_0_agent:reset, LED_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Onchip_Memory:reset, Onchip_Memory_s1_translator:reset, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:reset, Onchip_Memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer:reset, Pixel_Buffer_DMA:reset, Pixel_Buffer_DMA_avalon_control_slave_translator:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator:reset, Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:reset, Pixel_Buffer_avalon_sram_slave_translator:reset, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, Pixel_Buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Pixel_RGB_Resampler:reset, Pixel_Scaler:reset, Video_Clipper:reset, Video_DMA:reset, Video_DMA_avalon_dma_control_slave_translator:reset, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:reset, Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, Video_DMA_avalon_dma_master_translator:reset, Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:reset, Video_In_Decoder:reset, Video_RGB_Resampler:reset, Video_Scaler:reset, addr_router:reset, addr_router_001:reset, addr_router_002:reset, addr_router_003:reset, burst_adapter:reset, burst_adapter_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_demux_002:reset, cmd_xbar_demux_003:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_003:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, irq_mapper:reset, jtag_uart_0:rst_n, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sdram_0:reset_n, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0:reset_n, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0:reset_n, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset, width_adapter_006:reset, width_adapter_007:reset]
wire cpu_jtag_debug_module_reset_reset; // CPU:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
wire clock_signals_sys_clk_reset_reset; // Clock_Signals:sys_reset_n -> [rst_controller:reset_in2, rst_controller_001:reset_in2, rst_controller_002:reset_in2]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [Dual_Clock_FIFO:reset_stream_out, VGA_Controller:reset]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> Clock_Signals:reset
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [106:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [10:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [106:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [10:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [106:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [10:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [106:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [10:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> LED_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> LED_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> LED_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> LED_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> LED_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_002_src0_endofpacket; // cmd_xbar_demux_002:src0_endofpacket -> cmd_xbar_mux_003:sink2_endofpacket
wire cmd_xbar_demux_002_src0_valid; // cmd_xbar_demux_002:src0_valid -> cmd_xbar_mux_003:sink2_valid
wire cmd_xbar_demux_002_src0_startofpacket; // cmd_xbar_demux_002:src0_startofpacket -> cmd_xbar_mux_003:sink2_startofpacket
wire [88:0] cmd_xbar_demux_002_src0_data; // cmd_xbar_demux_002:src0_data -> cmd_xbar_mux_003:sink2_data
wire [10:0] cmd_xbar_demux_002_src0_channel; // cmd_xbar_demux_002:src0_channel -> cmd_xbar_mux_003:sink2_channel
wire cmd_xbar_demux_002_src0_ready; // cmd_xbar_mux_003:sink2_ready -> cmd_xbar_demux_002:src0_ready
wire cmd_xbar_demux_003_src0_endofpacket; // cmd_xbar_demux_003:src0_endofpacket -> cmd_xbar_mux_003:sink3_endofpacket
wire cmd_xbar_demux_003_src0_valid; // cmd_xbar_demux_003:src0_valid -> cmd_xbar_mux_003:sink3_valid
wire cmd_xbar_demux_003_src0_startofpacket; // cmd_xbar_demux_003:src0_startofpacket -> cmd_xbar_mux_003:sink3_startofpacket
wire [88:0] cmd_xbar_demux_003_src0_data; // cmd_xbar_demux_003:src0_data -> cmd_xbar_mux_003:sink3_data
wire [10:0] cmd_xbar_demux_003_src0_channel; // cmd_xbar_demux_003:src0_channel -> cmd_xbar_mux_003:sink3_channel
wire cmd_xbar_demux_003_src0_ready; // cmd_xbar_mux_003:sink3_ready -> cmd_xbar_demux_003:src0_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [106:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [10:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [106:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [10:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [106:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [10:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [106:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [10:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_003_src2_endofpacket; // rsp_xbar_demux_003:src2_endofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_003_src2_valid; // rsp_xbar_demux_003:src2_valid -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_003_src2_startofpacket; // rsp_xbar_demux_003:src2_startofpacket -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [88:0] rsp_xbar_demux_003_src2_data; // rsp_xbar_demux_003:src2_data -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_data
wire [10:0] rsp_xbar_demux_003_src2_channel; // rsp_xbar_demux_003:src2_channel -> Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_demux_003_src3_endofpacket; // rsp_xbar_demux_003:src3_endofpacket -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_demux_003_src3_valid; // rsp_xbar_demux_003:src3_valid -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_demux_003_src3_startofpacket; // rsp_xbar_demux_003:src3_startofpacket -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [88:0] rsp_xbar_demux_003_src3_data; // rsp_xbar_demux_003:src3_data -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_data
wire [10:0] rsp_xbar_demux_003_src3_channel; // rsp_xbar_demux_003:src3_channel -> Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
wire [106:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
wire [10:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
wire [106:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
wire [10:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
wire [106:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
wire [10:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
wire [106:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
wire [10:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket
wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid
wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket
wire [106:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data
wire [10:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel
wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready
wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket
wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid
wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket
wire [106:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data
wire [10:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel
wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready
wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket
wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid
wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket
wire [106:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data
wire [10:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel
wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [106:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [10:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [106:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [10:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_src_ready; // CPU_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [106:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
wire [10:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [106:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [10:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> CPU_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_001_src_ready; // CPU_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready
wire addr_router_002_src_endofpacket; // addr_router_002:src_endofpacket -> cmd_xbar_demux_002:sink_endofpacket
wire addr_router_002_src_valid; // addr_router_002:src_valid -> cmd_xbar_demux_002:sink_valid
wire addr_router_002_src_startofpacket; // addr_router_002:src_startofpacket -> cmd_xbar_demux_002:sink_startofpacket
wire [88:0] addr_router_002_src_data; // addr_router_002:src_data -> cmd_xbar_demux_002:sink_data
wire [10:0] addr_router_002_src_channel; // addr_router_002:src_channel -> cmd_xbar_demux_002:sink_channel
wire addr_router_002_src_ready; // cmd_xbar_demux_002:sink_ready -> addr_router_002:src_ready
wire rsp_xbar_demux_003_src2_ready; // Pixel_Buffer_DMA_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_003:src2_ready
wire addr_router_003_src_endofpacket; // addr_router_003:src_endofpacket -> cmd_xbar_demux_003:sink_endofpacket
wire addr_router_003_src_valid; // addr_router_003:src_valid -> cmd_xbar_demux_003:sink_valid
wire addr_router_003_src_startofpacket; // addr_router_003:src_startofpacket -> cmd_xbar_demux_003:sink_startofpacket
wire [88:0] addr_router_003_src_data; // addr_router_003:src_data -> cmd_xbar_demux_003:sink_data
wire [10:0] addr_router_003_src_channel; // addr_router_003:src_channel -> cmd_xbar_demux_003:sink_channel
wire addr_router_003_src_ready; // cmd_xbar_demux_003:sink_ready -> addr_router_003:src_ready
wire rsp_xbar_demux_003_src3_ready; // Video_DMA_avalon_dma_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_demux_003:src3_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // CPU_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [106:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [10:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [106:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_001_src_ready; // Onchip_Memory_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [106:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [10:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire cmd_xbar_mux_002_src_endofpacket; // cmd_xbar_mux_002:src_endofpacket -> burst_adapter:sink0_endofpacket
wire cmd_xbar_mux_002_src_valid; // cmd_xbar_mux_002:src_valid -> burst_adapter:sink0_valid
wire cmd_xbar_mux_002_src_startofpacket; // cmd_xbar_mux_002:src_startofpacket -> burst_adapter:sink0_startofpacket
wire [88:0] cmd_xbar_mux_002_src_data; // cmd_xbar_mux_002:src_data -> burst_adapter:sink0_data
wire [10:0] cmd_xbar_mux_002_src_channel; // cmd_xbar_mux_002:src_channel -> burst_adapter:sink0_channel
wire cmd_xbar_mux_002_src_ready; // burst_adapter:sink0_ready -> cmd_xbar_mux_002:src_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [88:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [10:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> burst_adapter_001:sink0_endofpacket
wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> burst_adapter_001:sink0_valid
wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> burst_adapter_001:sink0_startofpacket
wire [88:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> burst_adapter_001:sink0_data
wire [10:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> burst_adapter_001:sink0_channel
wire cmd_xbar_mux_003_src_ready; // burst_adapter_001:sink0_ready -> cmd_xbar_mux_003:src_ready
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [88:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data
wire [10:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel
wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready
wire cmd_xbar_demux_001_src4_ready; // AV_Config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [106:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [10:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_001_src5_ready; // Video_DMA_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [106:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [10:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire cmd_xbar_demux_001_src6_ready; // Pixel_Buffer_DMA_avalon_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
wire [106:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
wire [10:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
wire cmd_xbar_demux_001_src7_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
wire [106:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
wire [10:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
wire cmd_xbar_demux_001_src8_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready
wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
wire [106:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data
wire [10:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
wire cmd_xbar_demux_001_src9_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready
wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
wire [106:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data
wire [10:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
wire cmd_xbar_demux_001_src10_ready; // LED_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready
wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
wire [106:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data
wire [10:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> width_adapter:in_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> width_adapter:in_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> width_adapter:in_startofpacket
wire [106:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> width_adapter:in_data
wire [10:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> width_adapter:in_channel
wire cmd_xbar_demux_src2_ready; // width_adapter:in_ready -> cmd_xbar_demux:src2_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> cmd_xbar_mux_002:sink0_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
wire [88:0] width_adapter_src_data; // width_adapter:out_data -> cmd_xbar_mux_002:sink0_data
wire width_adapter_src_ready; // cmd_xbar_mux_002:sink0_ready -> width_adapter:out_ready
wire [10:0] width_adapter_src_channel; // width_adapter:out_channel -> cmd_xbar_mux_002:sink0_channel
wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> width_adapter_001:in_endofpacket
wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> width_adapter_001:in_valid
wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> width_adapter_001:in_startofpacket
wire [106:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> width_adapter_001:in_data
wire [10:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> width_adapter_001:in_channel
wire cmd_xbar_demux_src3_ready; // width_adapter_001:in_ready -> cmd_xbar_demux:src3_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> cmd_xbar_mux_003:sink0_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
wire [88:0] width_adapter_001_src_data; // width_adapter_001:out_data -> cmd_xbar_mux_003:sink0_data
wire width_adapter_001_src_ready; // cmd_xbar_mux_003:sink0_ready -> width_adapter_001:out_ready
wire [10:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> cmd_xbar_mux_003:sink0_channel
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> width_adapter_002:in_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> width_adapter_002:in_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> width_adapter_002:in_startofpacket
wire [106:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> width_adapter_002:in_data
wire [10:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> width_adapter_002:in_channel
wire cmd_xbar_demux_001_src2_ready; // width_adapter_002:in_ready -> cmd_xbar_demux_001:src2_ready
wire width_adapter_002_src_endofpacket; // width_adapter_002:out_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
wire width_adapter_002_src_valid; // width_adapter_002:out_valid -> cmd_xbar_mux_002:sink1_valid
wire width_adapter_002_src_startofpacket; // width_adapter_002:out_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
wire [88:0] width_adapter_002_src_data; // width_adapter_002:out_data -> cmd_xbar_mux_002:sink1_data
wire width_adapter_002_src_ready; // cmd_xbar_mux_002:sink1_ready -> width_adapter_002:out_ready
wire [10:0] width_adapter_002_src_channel; // width_adapter_002:out_channel -> cmd_xbar_mux_002:sink1_channel
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> width_adapter_003:in_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> width_adapter_003:in_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> width_adapter_003:in_startofpacket
wire [106:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> width_adapter_003:in_data
wire [10:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> width_adapter_003:in_channel
wire cmd_xbar_demux_001_src3_ready; // width_adapter_003:in_ready -> cmd_xbar_demux_001:src3_ready
wire width_adapter_003_src_endofpacket; // width_adapter_003:out_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
wire width_adapter_003_src_valid; // width_adapter_003:out_valid -> cmd_xbar_mux_003:sink1_valid
wire width_adapter_003_src_startofpacket; // width_adapter_003:out_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
wire [88:0] width_adapter_003_src_data; // width_adapter_003:out_data -> cmd_xbar_mux_003:sink1_data
wire width_adapter_003_src_ready; // cmd_xbar_mux_003:sink1_ready -> width_adapter_003:out_ready
wire [10:0] width_adapter_003_src_channel; // width_adapter_003:out_channel -> cmd_xbar_mux_003:sink1_channel
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> width_adapter_004:in_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> width_adapter_004:in_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> width_adapter_004:in_startofpacket
wire [88:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> width_adapter_004:in_data
wire [10:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> width_adapter_004:in_channel
wire rsp_xbar_demux_002_src0_ready; // width_adapter_004:in_ready -> rsp_xbar_demux_002:src0_ready
wire width_adapter_004_src_endofpacket; // width_adapter_004:out_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire width_adapter_004_src_valid; // width_adapter_004:out_valid -> rsp_xbar_mux:sink2_valid
wire width_adapter_004_src_startofpacket; // width_adapter_004:out_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [106:0] width_adapter_004_src_data; // width_adapter_004:out_data -> rsp_xbar_mux:sink2_data
wire width_adapter_004_src_ready; // rsp_xbar_mux:sink2_ready -> width_adapter_004:out_ready
wire [10:0] width_adapter_004_src_channel; // width_adapter_004:out_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src1_endofpacket; // rsp_xbar_demux_002:src1_endofpacket -> width_adapter_005:in_endofpacket
wire rsp_xbar_demux_002_src1_valid; // rsp_xbar_demux_002:src1_valid -> width_adapter_005:in_valid
wire rsp_xbar_demux_002_src1_startofpacket; // rsp_xbar_demux_002:src1_startofpacket -> width_adapter_005:in_startofpacket
wire [88:0] rsp_xbar_demux_002_src1_data; // rsp_xbar_demux_002:src1_data -> width_adapter_005:in_data
wire [10:0] rsp_xbar_demux_002_src1_channel; // rsp_xbar_demux_002:src1_channel -> width_adapter_005:in_channel
wire rsp_xbar_demux_002_src1_ready; // width_adapter_005:in_ready -> rsp_xbar_demux_002:src1_ready
wire width_adapter_005_src_endofpacket; // width_adapter_005:out_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire width_adapter_005_src_valid; // width_adapter_005:out_valid -> rsp_xbar_mux_001:sink2_valid
wire width_adapter_005_src_startofpacket; // width_adapter_005:out_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [106:0] width_adapter_005_src_data; // width_adapter_005:out_data -> rsp_xbar_mux_001:sink2_data
wire width_adapter_005_src_ready; // rsp_xbar_mux_001:sink2_ready -> width_adapter_005:out_ready
wire [10:0] width_adapter_005_src_channel; // width_adapter_005:out_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> width_adapter_006:in_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> width_adapter_006:in_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> width_adapter_006:in_startofpacket
wire [88:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> width_adapter_006:in_data
wire [10:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> width_adapter_006:in_channel
wire rsp_xbar_demux_003_src0_ready; // width_adapter_006:in_ready -> rsp_xbar_demux_003:src0_ready
wire width_adapter_006_src_endofpacket; // width_adapter_006:out_endofpacket -> rsp_xbar_mux:sink3_endofpacket
wire width_adapter_006_src_valid; // width_adapter_006:out_valid -> rsp_xbar_mux:sink3_valid
wire width_adapter_006_src_startofpacket; // width_adapter_006:out_startofpacket -> rsp_xbar_mux:sink3_startofpacket
wire [106:0] width_adapter_006_src_data; // width_adapter_006:out_data -> rsp_xbar_mux:sink3_data
wire width_adapter_006_src_ready; // rsp_xbar_mux:sink3_ready -> width_adapter_006:out_ready
wire [10:0] width_adapter_006_src_channel; // width_adapter_006:out_channel -> rsp_xbar_mux:sink3_channel
wire rsp_xbar_demux_003_src1_endofpacket; // rsp_xbar_demux_003:src1_endofpacket -> width_adapter_007:in_endofpacket
wire rsp_xbar_demux_003_src1_valid; // rsp_xbar_demux_003:src1_valid -> width_adapter_007:in_valid
wire rsp_xbar_demux_003_src1_startofpacket; // rsp_xbar_demux_003:src1_startofpacket -> width_adapter_007:in_startofpacket
wire [88:0] rsp_xbar_demux_003_src1_data; // rsp_xbar_demux_003:src1_data -> width_adapter_007:in_data
wire [10:0] rsp_xbar_demux_003_src1_channel; // rsp_xbar_demux_003:src1_channel -> width_adapter_007:in_channel
wire rsp_xbar_demux_003_src1_ready; // width_adapter_007:in_ready -> rsp_xbar_demux_003:src1_ready
wire width_adapter_007_src_endofpacket; // width_adapter_007:out_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire width_adapter_007_src_valid; // width_adapter_007:out_valid -> rsp_xbar_mux_001:sink3_valid
wire width_adapter_007_src_startofpacket; // width_adapter_007:out_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [106:0] width_adapter_007_src_data; // width_adapter_007:out_data -> rsp_xbar_mux_001:sink3_data
wire width_adapter_007_src_ready; // rsp_xbar_mux_001:sink3_ready -> width_adapter_007:out_ready
wire [10:0] width_adapter_007_src_channel; // width_adapter_007:out_channel -> rsp_xbar_mux_001:sink3_channel
wire irq_mapper_receiver0_irq; // timer_0:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver1_irq
wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> CPU:d_irq
video_sys_Onchip_Memory onchip_memory (
.clk (clock_signals_sys_clk_clk), // clk1.clk
.address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // s1.address
.chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken
.readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write
.writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset) // reset1.reset
);
video_sys_Dual_Clock_FIFO dual_clock_fifo (
.clk_stream_in (clock_signals_sys_clk_clk), // clock_stream_in.clk
.reset_stream_in (rst_controller_reset_out_reset), // clock_stream_in_reset.reset
.clk_stream_out (clock_signals_vga_clk_clk), // clock_stream_out.clk
.reset_stream_out (rst_controller_001_reset_out_reset), // clock_stream_out_reset.reset
.stream_in_ready (pixel_scaler_avalon_scaler_source_ready), // avalon_dc_buffer_sink.ready
.stream_in_startofpacket (pixel_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_in_endofpacket (pixel_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_in_valid (pixel_scaler_avalon_scaler_source_valid), // .valid
.stream_in_data (pixel_scaler_avalon_scaler_source_data), // .data
.stream_out_ready (dual_clock_fifo_avalon_dc_buffer_source_ready), // avalon_dc_buffer_source.ready
.stream_out_startofpacket (dual_clock_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.stream_out_endofpacket (dual_clock_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.stream_out_valid (dual_clock_fifo_avalon_dc_buffer_source_valid), // .valid
.stream_out_data (dual_clock_fifo_avalon_dc_buffer_source_data) // .data
);
video_sys_Pixel_Buffer pixel_buffer (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.SRAM_DQ (SRAM_DQ_to_and_from_the_Pixel_Buffer), // external_interface.export
.SRAM_ADDR (SRAM_ADDR_from_the_Pixel_Buffer), // .export
.SRAM_LB_N (SRAM_LB_N_from_the_Pixel_Buffer), // .export
.SRAM_UB_N (SRAM_UB_N_from_the_Pixel_Buffer), // .export
.SRAM_CE_N (SRAM_CE_N_from_the_Pixel_Buffer), // .export
.SRAM_OE_N (SRAM_OE_N_from_the_Pixel_Buffer), // .export
.SRAM_WE_N (SRAM_WE_N_from_the_Pixel_Buffer), // .export
.address (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_sram_slave.address
.byteenable (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.read (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read
.write (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write
.writedata (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.readdatavalid (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid) // .readdatavalid
);
video_sys_Pixel_Buffer_DMA pixel_buffer_dma (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid), // avalon_pixel_dma_master.readdatavalid
.master_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_waitrequest), // .waitrequest
.master_address (pixel_buffer_dma_avalon_pixel_dma_master_address), // .address
.master_arbiterlock (pixel_buffer_dma_avalon_pixel_dma_master_lock), // .lock
.master_read (pixel_buffer_dma_avalon_pixel_dma_master_read), // .read
.master_readdata (pixel_buffer_dma_avalon_pixel_dma_master_readdata), // .readdata
.slave_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address), // avalon_control_slave.address
.slave_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.slave_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read), // .read
.slave_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write), // .write
.slave_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.slave_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.stream_ready (pixel_buffer_dma_avalon_pixel_source_ready), // avalon_pixel_source.ready
.stream_startofpacket (pixel_buffer_dma_avalon_pixel_source_startofpacket), // .startofpacket
.stream_endofpacket (pixel_buffer_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_valid (pixel_buffer_dma_avalon_pixel_source_valid), // .valid
.stream_data (pixel_buffer_dma_avalon_pixel_source_data) // .data
);
video_sys_Pixel_RGB_Resampler pixel_rgb_resampler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (pixel_buffer_dma_avalon_pixel_source_startofpacket), // avalon_rgb_sink.startofpacket
.stream_in_endofpacket (pixel_buffer_dma_avalon_pixel_source_endofpacket), // .endofpacket
.stream_in_valid (pixel_buffer_dma_avalon_pixel_source_valid), // .valid
.stream_in_ready (pixel_buffer_dma_avalon_pixel_source_ready), // .ready
.stream_in_data (pixel_buffer_dma_avalon_pixel_source_data), // .data
.stream_out_ready (pixel_rgb_resampler_avalon_rgb_source_ready), // avalon_rgb_source.ready
.stream_out_startofpacket (pixel_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_out_endofpacket (pixel_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_out_valid (pixel_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_out_data (pixel_rgb_resampler_avalon_rgb_source_data) // .data
);
video_sys_Pixel_Scaler pixel_scaler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (pixel_rgb_resampler_avalon_rgb_source_startofpacket), // avalon_scaler_sink.startofpacket
.stream_in_endofpacket (pixel_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_in_valid (pixel_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_in_ready (pixel_rgb_resampler_avalon_rgb_source_ready), // .ready
.stream_in_data (pixel_rgb_resampler_avalon_rgb_source_data), // .data
.stream_out_ready (pixel_scaler_avalon_scaler_source_ready), // avalon_scaler_source.ready
.stream_out_startofpacket (pixel_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_out_endofpacket (pixel_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_out_valid (pixel_scaler_avalon_scaler_source_valid), // .valid
.stream_out_data (pixel_scaler_avalon_scaler_source_data) // .data
);
video_sys_VGA_Controller vga_controller (
.clk (clock_signals_vga_clk_clk), // clock_reset.clk
.reset (rst_controller_001_reset_out_reset), // clock_reset_reset.reset
.data (dual_clock_fifo_avalon_dc_buffer_source_data), // avalon_vga_sink.data
.startofpacket (dual_clock_fifo_avalon_dc_buffer_source_startofpacket), // .startofpacket
.endofpacket (dual_clock_fifo_avalon_dc_buffer_source_endofpacket), // .endofpacket
.valid (dual_clock_fifo_avalon_dc_buffer_source_valid), // .valid
.ready (dual_clock_fifo_avalon_dc_buffer_source_ready), // .ready
.VGA_CLK (VGA_CLK_from_the_VGA_Controller), // external_interface.export
.VGA_HS (VGA_HS_from_the_VGA_Controller), // .export
.VGA_VS (VGA_VS_from_the_VGA_Controller), // .export
.VGA_BLANK (VGA_BLANK_from_the_VGA_Controller), // .export
.VGA_SYNC (VGA_SYNC_from_the_VGA_Controller), // .export
.VGA_R (VGA_R_from_the_VGA_Controller), // .export
.VGA_G (VGA_G_from_the_VGA_Controller), // .export
.VGA_B (VGA_B_from_the_VGA_Controller) // .export
);
video_sys_Video_In_Decoder video_in_decoder (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_out_ready (video_in_decoder_avalon_decoder_source_ready), // avalon_decoder_source.ready
.stream_out_startofpacket (video_in_decoder_avalon_decoder_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_in_decoder_avalon_decoder_source_endofpacket), // .endofpacket
.stream_out_valid (video_in_decoder_avalon_decoder_source_valid), // .valid
.stream_out_data (video_in_decoder_avalon_decoder_source_data), // .data
.TD_CLK27 (TD_CLK27_to_the_Video_In_Decoder), // external_interface.export
.TD_DATA (TD_DATA_to_the_Video_In_Decoder), // .export
.TD_HS (TD_HS_to_the_Video_In_Decoder), // .export
.TD_VS (TD_VS_to_the_Video_In_Decoder), // .export
.TD_RESET (TD_RESET_from_the_Video_In_Decoder), // .export
.overflow_flag (overflow_flag_from_the_Video_In_Decoder) // .export
);
video_sys_Chroma_Resampler chroma_resampler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (video_in_decoder_avalon_decoder_source_startofpacket), // avalon_chroma_sink.startofpacket
.stream_in_endofpacket (video_in_decoder_avalon_decoder_source_endofpacket), // .endofpacket
.stream_in_valid (video_in_decoder_avalon_decoder_source_valid), // .valid
.stream_in_ready (video_in_decoder_avalon_decoder_source_ready), // .ready
.stream_in_data (video_in_decoder_avalon_decoder_source_data), // .data
.stream_out_ready (chroma_resampler_avalon_chroma_source_ready), // avalon_chroma_source.ready
.stream_out_startofpacket (chroma_resampler_avalon_chroma_source_startofpacket), // .startofpacket
.stream_out_endofpacket (chroma_resampler_avalon_chroma_source_endofpacket), // .endofpacket
.stream_out_valid (chroma_resampler_avalon_chroma_source_valid), // .valid
.stream_out_data (chroma_resampler_avalon_chroma_source_data) // .data
);
video_sys_Color_Space_Converter color_space_converter (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (chroma_resampler_avalon_chroma_source_startofpacket), // avalon_csc_sink.startofpacket
.stream_in_endofpacket (chroma_resampler_avalon_chroma_source_endofpacket), // .endofpacket
.stream_in_valid (chroma_resampler_avalon_chroma_source_valid), // .valid
.stream_in_ready (chroma_resampler_avalon_chroma_source_ready), // .ready
.stream_in_data (chroma_resampler_avalon_chroma_source_data), // .data
.stream_out_ready (color_space_converter_avalon_csc_source_ready), // avalon_csc_source.ready
.stream_out_startofpacket (color_space_converter_avalon_csc_source_startofpacket), // .startofpacket
.stream_out_endofpacket (color_space_converter_avalon_csc_source_endofpacket), // .endofpacket
.stream_out_valid (color_space_converter_avalon_csc_source_valid), // .valid
.stream_out_data (color_space_converter_avalon_csc_source_data) // .data
);
video_sys_Video_RGB_Resampler video_rgb_resampler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (color_space_converter_avalon_csc_source_startofpacket), // avalon_rgb_sink.startofpacket
.stream_in_endofpacket (color_space_converter_avalon_csc_source_endofpacket), // .endofpacket
.stream_in_valid (color_space_converter_avalon_csc_source_valid), // .valid
.stream_in_ready (color_space_converter_avalon_csc_source_ready), // .ready
.stream_in_data (color_space_converter_avalon_csc_source_data), // .data
.stream_out_ready (video_rgb_resampler_avalon_rgb_source_ready), // avalon_rgb_source.ready
.stream_out_startofpacket (video_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_out_valid (video_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_out_data (video_rgb_resampler_avalon_rgb_source_data) // .data
);
video_sys_Video_Clipper video_clipper (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_data (video_rgb_resampler_avalon_rgb_source_data), // avalon_clipper_sink.data
.stream_in_startofpacket (video_rgb_resampler_avalon_rgb_source_startofpacket), // .startofpacket
.stream_in_endofpacket (video_rgb_resampler_avalon_rgb_source_endofpacket), // .endofpacket
.stream_in_valid (video_rgb_resampler_avalon_rgb_source_valid), // .valid
.stream_in_ready (video_rgb_resampler_avalon_rgb_source_ready), // .ready
.stream_out_ready (video_clipper_avalon_clipper_source_ready), // avalon_clipper_source.ready
.stream_out_data (video_clipper_avalon_clipper_source_data), // .data
.stream_out_startofpacket (video_clipper_avalon_clipper_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_clipper_avalon_clipper_source_endofpacket), // .endofpacket
.stream_out_valid (video_clipper_avalon_clipper_source_valid) // .valid
);
video_sys_Video_Scaler video_scaler (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_in_startofpacket (video_clipper_avalon_clipper_source_startofpacket), // avalon_scaler_sink.startofpacket
.stream_in_endofpacket (video_clipper_avalon_clipper_source_endofpacket), // .endofpacket
.stream_in_valid (video_clipper_avalon_clipper_source_valid), // .valid
.stream_in_ready (video_clipper_avalon_clipper_source_ready), // .ready
.stream_in_data (video_clipper_avalon_clipper_source_data), // .data
.stream_out_ready (video_scaler_avalon_scaler_source_ready), // avalon_scaler_source.ready
.stream_out_startofpacket (video_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_out_valid (video_scaler_avalon_scaler_source_valid), // .valid
.stream_out_data (video_scaler_avalon_scaler_source_data) // .data
);
video_sys_Video_DMA video_dma (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.stream_data (video_scaler_avalon_scaler_source_data), // avalon_dma_sink.data
.stream_startofpacket (video_scaler_avalon_scaler_source_startofpacket), // .startofpacket
.stream_endofpacket (video_scaler_avalon_scaler_source_endofpacket), // .endofpacket
.stream_valid (video_scaler_avalon_scaler_source_valid), // .valid
.stream_ready (video_scaler_avalon_scaler_source_ready), // .ready
.slave_address (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address), // avalon_dma_control_slave.address
.slave_byteenable (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.slave_read (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read), // .read
.slave_write (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write), // .write
.slave_writedata (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.slave_readdata (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.master_address (video_dma_avalon_dma_master_address), // avalon_dma_master.address
.master_waitrequest (video_dma_avalon_dma_master_waitrequest), // .waitrequest
.master_write (video_dma_avalon_dma_master_write), // .write
.master_writedata (video_dma_avalon_dma_master_writedata) // .writedata
);
video_sys_AV_Config av_config (
.clk (clock_signals_sys_clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.address (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address), // avalon_av_config_slave.address
.byteenable (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.read (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read), // .read
.write (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write), // .write
.writedata (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.waitrequest (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.I2C_SDAT (I2C_SDAT_to_and_from_the_AV_Config), // external_interface.export
.I2C_SCLK (I2C_SCLK_from_the_AV_Config) // .export
);
video_sys_CPU cpu (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_begintransfer (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.jtag_debug_module_byteenable (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_readdata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_select (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.jtag_debug_module_write (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
video_sys_Clock_Signals clock_signals (
.CLOCK_50 (clk_0), // clk_in_primary.clk
.reset (rst_controller_002_reset_out_reset), // clk_in_primary_reset.reset
.sys_clk (clock_signals_sys_clk_clk), // sys_clk.clk
.sys_reset_n (clock_signals_sys_clk_reset_reset), // sys_clk_reset.reset_n
.SDRAM_CLK (clock_signals_sdram_clk_clk), // sdram_clk.clk
.VGA_CLK (clock_signals_vga_clk_clk) // vga_clk.clk
);
video_sys_timer_0 timer_0 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (timer_0_s1_translator_avalon_anti_slave_0_address), // s1.address
.writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.write_n (~timer_0_s1_translator_avalon_anti_slave_0_write), // .write_n
.irq (irq_mapper_receiver0_irq) // irq.irq
);
video_sys_sysid_qsys_0 sysid_qsys_0 (
.clock (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
.address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address) // .address
);
video_sys_jtag_uart_0 jtag_uart_0 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address
.av_read_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver1_irq) // irq.irq
);
video_sys_sdram_0 sdram_0 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (sdram_0_s1_translator_avalon_anti_slave_0_address), // s1.address
.az_be_n (~sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable_n
.az_cs (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.az_data (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.az_rd_n (~sdram_0_s1_translator_avalon_anti_slave_0_read), // .read_n
.az_wr_n (~sdram_0_s1_translator_avalon_anti_slave_0_write), // .write_n
.za_data (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.za_valid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.za_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.zs_addr (sdram_0_wire_addr), // wire.export
.zs_ba (sdram_0_wire_ba), // .export
.zs_cas_n (sdram_0_wire_cas_n), // .export
.zs_cke (sdram_0_wire_cke), // .export
.zs_cs_n (sdram_0_wire_cs_n), // .export
.zs_dq (sdram_0_wire_dq), // .export
.zs_dqm (sdram_0_wire_dqm), // .export
.zs_ras_n (sdram_0_wire_ras_n), // .export
.zs_we_n (sdram_0_wire_we_n) // .export
);
video_sys_LED led (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (led_s1_translator_avalon_anti_slave_0_address), // s1.address
.write_n (~led_s1_translator_avalon_anti_slave_0_write), // .write_n
.writedata (led_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.chipselect (led_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.readdata (led_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.out_port (led_external_connection_export) // external_connection.export
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) pixel_buffer_dma_avalon_pixel_dma_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read), // .read
.uav_write (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (pixel_buffer_dma_avalon_pixel_dma_master_address), // avalon_anti_master_0.address
.av_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_waitrequest), // .waitrequest
.av_read (pixel_buffer_dma_avalon_pixel_dma_master_read), // .read
.av_readdata (pixel_buffer_dma_avalon_pixel_dma_master_readdata), // .readdata
.av_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_readdatavalid), // .readdatavalid
.av_lock (pixel_buffer_dma_avalon_pixel_dma_master_lock), // .lock
.av_burstcount (1'b1), // (terminated)
.av_byteenable (2'b11), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (16'b0000000000000000), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.USE_READ (0),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) video_dma_avalon_dma_master_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (video_dma_avalon_dma_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (video_dma_avalon_dma_master_translator_avalon_universal_master_0_read), // .read
.uav_write (video_dma_avalon_dma_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (video_dma_avalon_dma_master_address), // avalon_anti_master_0.address
.av_waitrequest (video_dma_avalon_dma_master_waitrequest), // .waitrequest
.av_write (video_dma_avalon_dma_master_write), // .write
.av_writedata (video_dma_avalon_dma_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (2'b11), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_read (1'b0), // (terminated)
.av_readdata (), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_readdata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer
.av_byteenable (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_debugaccess (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory_s1_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (onchip_memory_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (onchip_memory_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (onchip_memory_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (onchip_memory_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (onchip_memory_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (onchip_memory_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_0_s1_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sdram_0_s1_translator_avalon_anti_slave_0_write), // .write
.av_read (sdram_0_s1_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (18),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pixel_buffer_avalon_sram_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (pixel_buffer_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) av_config_avalon_av_config_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (av_config_avalon_av_config_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) video_dma_avalon_dma_control_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (video_dma_avalon_dma_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pixel_buffer_dma_avalon_control_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) timer_0_s1_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (timer_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (timer_0_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_0_control_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) led_s1_translator (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (led_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (led_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (led_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (led_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (led_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (led_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (led_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (led_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (led_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (led_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_chipselect (led_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_THREAD_ID_H (97),
.PKT_THREAD_ID_L (97),
.PKT_CACHE_H (104),
.PKT_CACHE_L (101),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (107),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (4'b0000)
) cpu_instruction_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_src_data), // .data
.rp_channel (rsp_xbar_mux_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_BEGIN_BURST (87),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_THREAD_ID_H (97),
.PKT_THREAD_ID_L (97),
.PKT_CACHE_H (104),
.PKT_CACHE_L (101),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.ST_DATA_W (107),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) cpu_data_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_001_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_001_src_data), // .data
.rp_channel (rsp_xbar_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_001_src_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (82),
.PKT_PROTECTION_L (80),
.PKT_BEGIN_BURST (69),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (74),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (78),
.PKT_DEST_ID_L (75),
.PKT_THREAD_ID_H (79),
.PKT_THREAD_ID_L (79),
.PKT_CACHE_H (86),
.PKT_CACHE_L (83),
.PKT_DATA_SIDEBAND_H (68),
.PKT_DATA_SIDEBAND_L (68),
.PKT_QOS_H (70),
.PKT_QOS_L (70),
.PKT_ADDR_SIDEBAND_H (67),
.PKT_ADDR_SIDEBAND_L (67),
.ST_DATA_W (89),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (2),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_address), // av.address
.av_write (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_write), // .write
.av_read (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_003_src2_valid), // rp.valid
.rp_data (rsp_xbar_demux_003_src2_data), // .data
.rp_channel (rsp_xbar_demux_003_src2_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_003_src2_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_003_src2_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_003_src2_ready) // .ready
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (82),
.PKT_PROTECTION_L (80),
.PKT_BEGIN_BURST (69),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (74),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (78),
.PKT_DEST_ID_L (75),
.PKT_THREAD_ID_H (79),
.PKT_THREAD_ID_L (79),
.PKT_CACHE_H (86),
.PKT_CACHE_L (83),
.PKT_DATA_SIDEBAND_H (68),
.PKT_DATA_SIDEBAND_L (68),
.PKT_QOS_H (70),
.PKT_QOS_L (70),
.PKT_ADDR_SIDEBAND_H (67),
.PKT_ADDR_SIDEBAND_L (67),
.ST_DATA_W (89),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (3),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (4'b0000)
) video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (video_dma_avalon_dma_master_translator_avalon_universal_master_0_address), // av.address
.av_write (video_dma_avalon_dma_master_translator_avalon_universal_master_0_write), // .write
.av_read (video_dma_avalon_dma_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (video_dma_avalon_dma_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (video_dma_avalon_dma_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (video_dma_avalon_dma_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (video_dma_avalon_dma_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (video_dma_avalon_dma_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (video_dma_avalon_dma_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (video_dma_avalon_dma_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_demux_003_src3_valid), // rp.valid
.rp_data (rsp_xbar_demux_003_src3_data), // .data
.rp_channel (rsp_xbar_demux_003_src3_channel), // .channel
.rp_startofpacket (rsp_xbar_demux_003_src3_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_demux_003_src3_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_demux_003_src3_ready) // .ready
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) onchip_memory_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (onchip_memory_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_001_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_001_src_valid), // .valid
.cp_data (cmd_xbar_mux_001_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_001_src_channel), // .channel
.rf_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (69),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (74),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (78),
.PKT_DEST_ID_L (75),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (82),
.PKT_PROTECTION_L (80),
.PKT_RESPONSE_STATUS_H (88),
.PKT_RESPONSE_STATUS_L (87),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.ST_CHANNEL_W (11),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1)
) sdram_0_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (69),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (74),
.PKT_SRC_ID_L (71),
.PKT_DEST_ID_H (78),
.PKT_DEST_ID_L (75),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (82),
.PKT_PROTECTION_L (80),
.PKT_RESPONSE_STATUS_H (88),
.PKT_RESPONSE_STATUS_L (87),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.ST_CHANNEL_W (11),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1)
) pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_001_source0_ready), // cp.ready
.cp_valid (burst_adapter_001_source0_valid), // .valid
.cp_data (burst_adapter_001_source0_data), // .data
.cp_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_001_source0_channel), // .channel
.rf_sink_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
.cp_data (cmd_xbar_demux_001_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
.rf_sink_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
.cp_data (cmd_xbar_demux_001_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
.rf_sink_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src6_valid), // .valid
.cp_data (cmd_xbar_demux_001_src6_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src6_channel), // .channel
.rf_sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) timer_0_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
.cp_data (cmd_xbar_demux_001_src7_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
.rf_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src8_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src8_valid), // .valid
.cp_data (cmd_xbar_demux_001_src8_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src8_channel), // .channel
.rf_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src9_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src9_valid), // .valid
.cp_data (cmd_xbar_demux_001_src9_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src9_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (87),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_TRANS_LOCK (72),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (96),
.PKT_DEST_ID_L (93),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_PROTECTION_H (100),
.PKT_PROTECTION_L (98),
.PKT_RESPONSE_STATUS_H (106),
.PKT_RESPONSE_STATUS_L (105),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.ST_CHANNEL_W (11),
.ST_DATA_W (107),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1)
) led_s1_translator_avalon_universal_slave_0_agent (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (led_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (led_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (led_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (led_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (led_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (led_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (led_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (led_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (led_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src10_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src10_valid), // .valid
.cp_data (cmd_xbar_demux_001_src10_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src10_channel), // .channel
.rf_sink_ready (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (led_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (108),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (led_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
video_sys_addr_router addr_router (
.sink_ready (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
video_sys_addr_router_001 addr_router_001 (
.sink_ready (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
video_sys_addr_router_002 addr_router_002 (
.sink_ready (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_dma_avalon_pixel_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_002_src_ready), // src.ready
.src_valid (addr_router_002_src_valid), // .valid
.src_data (addr_router_002_src_data), // .data
.src_channel (addr_router_002_src_channel), // .channel
.src_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_002_src_endofpacket) // .endofpacket
);
video_sys_addr_router_002 addr_router_003 (
.sink_ready (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (video_dma_avalon_dma_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_003_src_ready), // src.ready
.src_valid (addr_router_003_src_valid), // .valid
.src_data (addr_router_003_src_data), // .data
.src_channel (addr_router_003_src_channel), // .channel
.src_startofpacket (addr_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_003_src_endofpacket) // .endofpacket
);
video_sys_id_router id_router (
.sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
video_sys_id_router id_router_001 (
.sink_ready (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
video_sys_id_router_002 id_router_002 (
.sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
video_sys_id_router_003 id_router_003 (
.sink_ready (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
video_sys_id_router_004 id_router_004 (
.sink_ready (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (av_config_avalon_av_config_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
video_sys_id_router_004 id_router_005 (
.sink_ready (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (video_dma_avalon_dma_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
video_sys_id_router_004 id_router_006 (
.sink_ready (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pixel_buffer_dma_avalon_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_006_src_ready), // src.ready
.src_valid (id_router_006_src_valid), // .valid
.src_data (id_router_006_src_data), // .data
.src_channel (id_router_006_src_channel), // .channel
.src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
);
video_sys_id_router_004 id_router_007 (
.sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_007_src_ready), // src.ready
.src_valid (id_router_007_src_valid), // .valid
.src_data (id_router_007_src_data), // .data
.src_channel (id_router_007_src_channel), // .channel
.src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
);
video_sys_id_router_004 id_router_008 (
.sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_008_src_ready), // src.ready
.src_valid (id_router_008_src_valid), // .valid
.src_data (id_router_008_src_data), // .data
.src_channel (id_router_008_src_channel), // .channel
.src_startofpacket (id_router_008_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_008_src_endofpacket) // .endofpacket
);
video_sys_id_router_004 id_router_009 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_009_src_ready), // src.ready
.src_valid (id_router_009_src_valid), // .valid
.src_data (id_router_009_src_data), // .data
.src_channel (id_router_009_src_channel), // .channel
.src_startofpacket (id_router_009_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_009_src_endofpacket) // .endofpacket
);
video_sys_id_router_004 id_router_010 (
.sink_ready (led_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (led_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (led_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_010_src_ready), // src.ready
.src_valid (id_router_010_src_valid), // .valid
.src_data (id_router_010_src_data), // .data
.src_channel (id_router_010_src_channel), // .channel
.src_startofpacket (id_router_010_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_010_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (69),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (11),
.OUT_BYTE_CNT_H (57),
.OUT_BURSTWRAP_H (61),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (0),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3)
) burst_adapter (
.clk (clock_signals_sys_clk_clk), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.sink0_valid (cmd_xbar_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_xbar_mux_002_src_data), // .data
.sink0_channel (cmd_xbar_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_mux_002_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (69),
.PKT_BYTE_CNT_H (58),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (64),
.PKT_BURST_SIZE_L (62),
.PKT_BURST_TYPE_H (66),
.PKT_BURST_TYPE_L (65),
.PKT_BURSTWRAP_H (61),
.PKT_BURSTWRAP_L (59),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (11),
.OUT_BYTE_CNT_H (57),
.OUT_BURSTWRAP_H (61),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (0),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3)
) burst_adapter_001 (
.clk (clock_signals_sys_clk_clk), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.sink0_valid (cmd_xbar_mux_003_src_valid), // sink0.valid
.sink0_data (cmd_xbar_mux_003_src_data), // .data
.sink0_channel (cmd_xbar_mux_003_src_channel), // .channel
.sink0_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_mux_003_src_ready), // .ready
.source0_valid (burst_adapter_001_source0_valid), // source0.valid
.source0_data (burst_adapter_001_source0_data), // .data
.source0_channel (burst_adapter_001_source0_channel), // .channel
.source0_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_001_source0_ready) // .ready
);
altera_reset_controller #(
.NUM_RESET_INPUTS (3),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.reset_in2 (~clock_signals_sys_clk_reset_reset), // reset_in2.reset
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (3),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller_001 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.reset_in2 (~clock_signals_sys_clk_reset_reset), // reset_in2.reset
.clk (clock_signals_vga_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (3),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller_002 (
.reset_in0 (~reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.reset_in2 (~clock_signals_sys_clk_reset_reset), // reset_in2.reset
.clk (clk_0), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
video_sys_cmd_xbar_demux cmd_xbar_demux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_src3_valid), // .valid
.src3_data (cmd_xbar_demux_src3_data), // .data
.src3_channel (cmd_xbar_demux_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_src3_endofpacket) // .endofpacket
);
video_sys_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_001_src_ready), // sink.ready
.sink_channel (addr_router_001_src_channel), // .channel
.sink_data (addr_router_001_src_data), // .data
.sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.sink_valid (addr_router_001_src_valid), // .valid
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
.src4_data (cmd_xbar_demux_001_src4_data), // .data
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
.src5_data (cmd_xbar_demux_001_src5_data), // .data
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
.src6_data (cmd_xbar_demux_001_src6_data), // .data
.src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
.src7_data (cmd_xbar_demux_001_src7_data), // .data
.src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.src8_ready (cmd_xbar_demux_001_src8_ready), // src8.ready
.src8_valid (cmd_xbar_demux_001_src8_valid), // .valid
.src8_data (cmd_xbar_demux_001_src8_data), // .data
.src8_channel (cmd_xbar_demux_001_src8_channel), // .channel
.src8_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket
.src9_ready (cmd_xbar_demux_001_src9_ready), // src9.ready
.src9_valid (cmd_xbar_demux_001_src9_valid), // .valid
.src9_data (cmd_xbar_demux_001_src9_data), // .data
.src9_channel (cmd_xbar_demux_001_src9_channel), // .channel
.src9_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket
.src10_ready (cmd_xbar_demux_001_src10_ready), // src10.ready
.src10_valid (cmd_xbar_demux_001_src10_valid), // .valid
.src10_data (cmd_xbar_demux_001_src10_data), // .data
.src10_channel (cmd_xbar_demux_001_src10_channel), // .channel
.src10_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_xbar_demux_001_src10_endofpacket) // .endofpacket
);
video_sys_cmd_xbar_demux_002 cmd_xbar_demux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_002_src_ready), // sink.ready
.sink_channel (addr_router_002_src_channel), // .channel
.sink_data (addr_router_002_src_data), // .data
.sink_startofpacket (addr_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_002_src_endofpacket), // .endofpacket
.sink_valid (addr_router_002_src_valid), // .valid
.src0_ready (cmd_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_002_src0_valid), // .valid
.src0_data (cmd_xbar_demux_002_src0_data), // .data
.src0_channel (cmd_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_002_src0_endofpacket) // .endofpacket
);
video_sys_cmd_xbar_demux_002 cmd_xbar_demux_003 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_003_src_ready), // sink.ready
.sink_channel (addr_router_003_src_channel), // .channel
.sink_data (addr_router_003_src_data), // .data
.sink_startofpacket (addr_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_003_src_endofpacket), // .endofpacket
.sink_valid (addr_router_003_src_valid), // .valid
.src0_ready (cmd_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_003_src0_valid), // .valid
.src0_data (cmd_xbar_demux_003_src0_data), // .data
.src0_channel (cmd_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket
);
video_sys_cmd_xbar_mux cmd_xbar_mux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
video_sys_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
video_sys_cmd_xbar_mux_002 cmd_xbar_mux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_002_src_ready), // src.ready
.src_valid (cmd_xbar_mux_002_src_valid), // .valid
.src_data (cmd_xbar_mux_002_src_data), // .data
.src_channel (cmd_xbar_mux_002_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_src_ready), // sink0.ready
.sink0_valid (width_adapter_src_valid), // .valid
.sink0_channel (width_adapter_src_channel), // .channel
.sink0_data (width_adapter_src_data), // .data
.sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.sink1_ready (width_adapter_002_src_ready), // sink1.ready
.sink1_valid (width_adapter_002_src_valid), // .valid
.sink1_channel (width_adapter_002_src_channel), // .channel
.sink1_data (width_adapter_002_src_data), // .data
.sink1_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.sink1_endofpacket (width_adapter_002_src_endofpacket) // .endofpacket
);
video_sys_cmd_xbar_mux_003 cmd_xbar_mux_003 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_003_src_ready), // src.ready
.src_valid (cmd_xbar_mux_003_src_valid), // .valid
.src_data (cmd_xbar_mux_003_src_data), // .data
.src_channel (cmd_xbar_mux_003_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_001_src_ready), // sink0.ready
.sink0_valid (width_adapter_001_src_valid), // .valid
.sink0_channel (width_adapter_001_src_channel), // .channel
.sink0_data (width_adapter_001_src_data), // .data
.sink0_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.sink1_ready (width_adapter_003_src_ready), // sink1.ready
.sink1_valid (width_adapter_003_src_valid), // .valid
.sink1_channel (width_adapter_003_src_channel), // .channel
.sink1_data (width_adapter_003_src_data), // .data
.sink1_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.sink1_endofpacket (width_adapter_003_src_endofpacket), // .endofpacket
.sink2_ready (cmd_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_xbar_demux_002_src0_valid), // .valid
.sink2_channel (cmd_xbar_demux_002_src0_channel), // .channel
.sink2_data (cmd_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (cmd_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (cmd_xbar_demux_003_src0_valid), // .valid
.sink3_channel (cmd_xbar_demux_003_src0_channel), // .channel
.sink3_data (cmd_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (cmd_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (cmd_xbar_demux_003_src0_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux rsp_xbar_demux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_002 rsp_xbar_demux_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_002_src1_valid), // .valid
.src1_data (rsp_xbar_demux_002_src1_data), // .data
.src1_channel (rsp_xbar_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_002_src1_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_003 rsp_xbar_demux_003 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_003_src_ready), // sink.ready
.sink_channel (id_router_003_src_channel), // .channel
.sink_data (id_router_003_src_data), // .data
.sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.sink_valid (id_router_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.src1_data (rsp_xbar_demux_003_src1_data), // .data
.src1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket
.src2_ready (rsp_xbar_demux_003_src2_ready), // src2.ready
.src2_valid (rsp_xbar_demux_003_src2_valid), // .valid
.src2_data (rsp_xbar_demux_003_src2_data), // .data
.src2_channel (rsp_xbar_demux_003_src2_channel), // .channel
.src2_startofpacket (rsp_xbar_demux_003_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_xbar_demux_003_src2_endofpacket), // .endofpacket
.src3_ready (rsp_xbar_demux_003_src3_ready), // src3.ready
.src3_valid (rsp_xbar_demux_003_src3_valid), // .valid
.src3_data (rsp_xbar_demux_003_src3_data), // .data
.src3_channel (rsp_xbar_demux_003_src3_channel), // .channel
.src3_startofpacket (rsp_xbar_demux_003_src3_startofpacket), // .startofpacket
.src3_endofpacket (rsp_xbar_demux_003_src3_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_004 rsp_xbar_demux_004 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_004 rsp_xbar_demux_005 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_004 rsp_xbar_demux_006 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_006_src_ready), // sink.ready
.sink_channel (id_router_006_src_channel), // .channel
.sink_data (id_router_006_src_data), // .data
.sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
.sink_valid (id_router_006_src_valid), // .valid
.src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
.src0_data (rsp_xbar_demux_006_src0_data), // .data
.src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_004 rsp_xbar_demux_007 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_007_src_ready), // sink.ready
.sink_channel (id_router_007_src_channel), // .channel
.sink_data (id_router_007_src_data), // .data
.sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
.sink_valid (id_router_007_src_valid), // .valid
.src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
.src0_data (rsp_xbar_demux_007_src0_data), // .data
.src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_004 rsp_xbar_demux_008 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_008_src_ready), // sink.ready
.sink_channel (id_router_008_src_channel), // .channel
.sink_data (id_router_008_src_data), // .data
.sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket
.sink_valid (id_router_008_src_valid), // .valid
.src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_008_src0_valid), // .valid
.src0_data (rsp_xbar_demux_008_src0_data), // .data
.src0_channel (rsp_xbar_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_004 rsp_xbar_demux_009 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_009_src_ready), // sink.ready
.sink_channel (id_router_009_src_channel), // .channel
.sink_data (id_router_009_src_data), // .data
.sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket
.sink_valid (id_router_009_src_valid), // .valid
.src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_009_src0_valid), // .valid
.src0_data (rsp_xbar_demux_009_src0_data), // .data
.src0_channel (rsp_xbar_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_demux_004 rsp_xbar_demux_010 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_010_src_ready), // sink.ready
.sink_channel (id_router_010_src_channel), // .channel
.sink_data (id_router_010_src_data), // .data
.sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket
.sink_valid (id_router_010_src_valid), // .valid
.src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_010_src0_valid), // .valid
.src0_data (rsp_xbar_demux_010_src0_data), // .data
.src0_channel (rsp_xbar_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_mux rsp_xbar_mux (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (width_adapter_004_src_ready), // sink2.ready
.sink2_valid (width_adapter_004_src_valid), // .valid
.sink2_channel (width_adapter_004_src_channel), // .channel
.sink2_data (width_adapter_004_src_data), // .data
.sink2_startofpacket (width_adapter_004_src_startofpacket), // .startofpacket
.sink2_endofpacket (width_adapter_004_src_endofpacket), // .endofpacket
.sink3_ready (width_adapter_006_src_ready), // sink3.ready
.sink3_valid (width_adapter_006_src_valid), // .valid
.sink3_channel (width_adapter_006_src_channel), // .channel
.sink3_data (width_adapter_006_src_data), // .data
.sink3_startofpacket (width_adapter_006_src_startofpacket), // .startofpacket
.sink3_endofpacket (width_adapter_006_src_endofpacket) // .endofpacket
);
video_sys_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (width_adapter_005_src_ready), // sink2.ready
.sink2_valid (width_adapter_005_src_valid), // .valid
.sink2_channel (width_adapter_005_src_channel), // .channel
.sink2_data (width_adapter_005_src_data), // .data
.sink2_startofpacket (width_adapter_005_src_startofpacket), // .startofpacket
.sink2_endofpacket (width_adapter_005_src_endofpacket), // .endofpacket
.sink3_ready (width_adapter_007_src_ready), // sink3.ready
.sink3_valid (width_adapter_007_src_valid), // .valid
.sink3_channel (width_adapter_007_src_channel), // .channel
.sink3_data (width_adapter_007_src_data), // .data
.sink3_startofpacket (width_adapter_007_src_startofpacket), // .startofpacket
.sink3_endofpacket (width_adapter_007_src_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid
.sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel
.sink6_data (rsp_xbar_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid
.sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel
.sink7_data (rsp_xbar_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_xbar_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_xbar_demux_008_src0_valid), // .valid
.sink8_channel (rsp_xbar_demux_008_src0_channel), // .channel
.sink8_data (rsp_xbar_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket
.sink9_ready (rsp_xbar_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_xbar_demux_009_src0_valid), // .valid
.sink9_channel (rsp_xbar_demux_009_src0_channel), // .channel
.sink9_data (rsp_xbar_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket
.sink10_ready (rsp_xbar_demux_010_src0_ready), // sink10.ready
.sink10_valid (rsp_xbar_demux_010_src0_valid), // .valid
.sink10_channel (rsp_xbar_demux_010_src0_channel), // .channel
.sink10_data (rsp_xbar_demux_010_src0_data), // .data
.sink10_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (76),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (79),
.IN_PKT_BURSTWRAP_L (77),
.IN_PKT_BURST_SIZE_H (82),
.IN_PKT_BURST_SIZE_L (80),
.IN_PKT_RESPONSE_STATUS_H (106),
.IN_PKT_RESPONSE_STATUS_L (105),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (84),
.IN_PKT_BURST_TYPE_L (83),
.IN_ST_DATA_W (107),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (58),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (64),
.OUT_PKT_BURST_SIZE_L (62),
.OUT_PKT_RESPONSE_STATUS_H (88),
.OUT_PKT_RESPONSE_STATUS_L (87),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (66),
.OUT_PKT_BURST_TYPE_L (65),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (0)
) width_adapter (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_demux_src2_valid), // sink.valid
.in_channel (cmd_xbar_demux_src2_channel), // .channel
.in_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.in_ready (cmd_xbar_demux_src2_ready), // .ready
.in_data (cmd_xbar_demux_src2_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (76),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (79),
.IN_PKT_BURSTWRAP_L (77),
.IN_PKT_BURST_SIZE_H (82),
.IN_PKT_BURST_SIZE_L (80),
.IN_PKT_RESPONSE_STATUS_H (106),
.IN_PKT_RESPONSE_STATUS_L (105),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (84),
.IN_PKT_BURST_TYPE_L (83),
.IN_ST_DATA_W (107),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (58),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (64),
.OUT_PKT_BURST_SIZE_L (62),
.OUT_PKT_RESPONSE_STATUS_H (88),
.OUT_PKT_RESPONSE_STATUS_L (87),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (66),
.OUT_PKT_BURST_TYPE_L (65),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (0)
) width_adapter_001 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_demux_src3_valid), // sink.valid
.in_channel (cmd_xbar_demux_src3_channel), // .channel
.in_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.in_ready (cmd_xbar_demux_src3_ready), // .ready
.in_data (cmd_xbar_demux_src3_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (76),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (79),
.IN_PKT_BURSTWRAP_L (77),
.IN_PKT_BURST_SIZE_H (82),
.IN_PKT_BURST_SIZE_L (80),
.IN_PKT_RESPONSE_STATUS_H (106),
.IN_PKT_RESPONSE_STATUS_L (105),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (84),
.IN_PKT_BURST_TYPE_L (83),
.IN_ST_DATA_W (107),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (58),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (64),
.OUT_PKT_BURST_SIZE_L (62),
.OUT_PKT_RESPONSE_STATUS_H (88),
.OUT_PKT_RESPONSE_STATUS_L (87),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (66),
.OUT_PKT_BURST_TYPE_L (65),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (0)
) width_adapter_002 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_demux_001_src2_valid), // sink.valid
.in_channel (cmd_xbar_demux_001_src2_channel), // .channel
.in_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.in_ready (cmd_xbar_demux_001_src2_ready), // .ready
.in_data (cmd_xbar_demux_001_src2_data), // .data
.out_endofpacket (width_adapter_002_src_endofpacket), // src.endofpacket
.out_data (width_adapter_002_src_data), // .data
.out_channel (width_adapter_002_src_channel), // .channel
.out_valid (width_adapter_002_src_valid), // .valid
.out_ready (width_adapter_002_src_ready), // .ready
.out_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (76),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_BURSTWRAP_H (79),
.IN_PKT_BURSTWRAP_L (77),
.IN_PKT_BURST_SIZE_H (82),
.IN_PKT_BURST_SIZE_L (80),
.IN_PKT_RESPONSE_STATUS_H (106),
.IN_PKT_RESPONSE_STATUS_L (105),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (84),
.IN_PKT_BURST_TYPE_L (83),
.IN_ST_DATA_W (107),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (58),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (64),
.OUT_PKT_BURST_SIZE_L (62),
.OUT_PKT_RESPONSE_STATUS_H (88),
.OUT_PKT_RESPONSE_STATUS_L (87),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (66),
.OUT_PKT_BURST_TYPE_L (65),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (0)
) width_adapter_003 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_demux_001_src3_valid), // sink.valid
.in_channel (cmd_xbar_demux_001_src3_channel), // .channel
.in_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.in_ready (cmd_xbar_demux_001_src3_ready), // .ready
.in_data (cmd_xbar_demux_001_src3_data), // .data
.out_endofpacket (width_adapter_003_src_endofpacket), // src.endofpacket
.out_data (width_adapter_003_src_data), // .data
.out_channel (width_adapter_003_src_channel), // .channel
.out_valid (width_adapter_003_src_valid), // .valid
.out_ready (width_adapter_003_src_ready), // .ready
.out_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (58),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (61),
.IN_PKT_BURSTWRAP_L (59),
.IN_PKT_BURST_SIZE_H (64),
.IN_PKT_BURST_SIZE_L (62),
.IN_PKT_RESPONSE_STATUS_H (88),
.IN_PKT_RESPONSE_STATUS_L (87),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (66),
.IN_PKT_BURST_TYPE_L (65),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (76),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (82),
.OUT_PKT_BURST_SIZE_L (80),
.OUT_PKT_RESPONSE_STATUS_H (106),
.OUT_PKT_RESPONSE_STATUS_L (105),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (84),
.OUT_PKT_BURST_TYPE_L (83),
.OUT_ST_DATA_W (107),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (1)
) width_adapter_004 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (rsp_xbar_demux_002_src0_valid), // sink.valid
.in_channel (rsp_xbar_demux_002_src0_channel), // .channel
.in_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.in_ready (rsp_xbar_demux_002_src0_ready), // .ready
.in_data (rsp_xbar_demux_002_src0_data), // .data
.out_endofpacket (width_adapter_004_src_endofpacket), // src.endofpacket
.out_data (width_adapter_004_src_data), // .data
.out_channel (width_adapter_004_src_channel), // .channel
.out_valid (width_adapter_004_src_valid), // .valid
.out_ready (width_adapter_004_src_ready), // .ready
.out_startofpacket (width_adapter_004_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (58),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (61),
.IN_PKT_BURSTWRAP_L (59),
.IN_PKT_BURST_SIZE_H (64),
.IN_PKT_BURST_SIZE_L (62),
.IN_PKT_RESPONSE_STATUS_H (88),
.IN_PKT_RESPONSE_STATUS_L (87),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (66),
.IN_PKT_BURST_TYPE_L (65),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (76),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (82),
.OUT_PKT_BURST_SIZE_L (80),
.OUT_PKT_RESPONSE_STATUS_H (106),
.OUT_PKT_RESPONSE_STATUS_L (105),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (84),
.OUT_PKT_BURST_TYPE_L (83),
.OUT_ST_DATA_W (107),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (1)
) width_adapter_005 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (rsp_xbar_demux_002_src1_valid), // sink.valid
.in_channel (rsp_xbar_demux_002_src1_channel), // .channel
.in_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_002_src1_endofpacket), // .endofpacket
.in_ready (rsp_xbar_demux_002_src1_ready), // .ready
.in_data (rsp_xbar_demux_002_src1_data), // .data
.out_endofpacket (width_adapter_005_src_endofpacket), // src.endofpacket
.out_data (width_adapter_005_src_data), // .data
.out_channel (width_adapter_005_src_channel), // .channel
.out_valid (width_adapter_005_src_valid), // .valid
.out_ready (width_adapter_005_src_ready), // .ready
.out_startofpacket (width_adapter_005_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (58),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (61),
.IN_PKT_BURSTWRAP_L (59),
.IN_PKT_BURST_SIZE_H (64),
.IN_PKT_BURST_SIZE_L (62),
.IN_PKT_RESPONSE_STATUS_H (88),
.IN_PKT_RESPONSE_STATUS_L (87),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (66),
.IN_PKT_BURST_TYPE_L (65),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (76),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (82),
.OUT_PKT_BURST_SIZE_L (80),
.OUT_PKT_RESPONSE_STATUS_H (106),
.OUT_PKT_RESPONSE_STATUS_L (105),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (84),
.OUT_PKT_BURST_TYPE_L (83),
.OUT_ST_DATA_W (107),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (1)
) width_adapter_006 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (rsp_xbar_demux_003_src0_valid), // sink.valid
.in_channel (rsp_xbar_demux_003_src0_channel), // .channel
.in_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.in_ready (rsp_xbar_demux_003_src0_ready), // .ready
.in_data (rsp_xbar_demux_003_src0_data), // .data
.out_endofpacket (width_adapter_006_src_endofpacket), // src.endofpacket
.out_data (width_adapter_006_src_data), // .data
.out_channel (width_adapter_006_src_channel), // .channel
.out_valid (width_adapter_006_src_valid), // .valid
.out_ready (width_adapter_006_src_ready), // .ready
.out_startofpacket (width_adapter_006_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (58),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (61),
.IN_PKT_BURSTWRAP_L (59),
.IN_PKT_BURST_SIZE_H (64),
.IN_PKT_BURST_SIZE_L (62),
.IN_PKT_RESPONSE_STATUS_H (88),
.IN_PKT_RESPONSE_STATUS_L (87),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (66),
.IN_PKT_BURST_TYPE_L (65),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (76),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (82),
.OUT_PKT_BURST_SIZE_L (80),
.OUT_PKT_RESPONSE_STATUS_H (106),
.OUT_PKT_RESPONSE_STATUS_L (105),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (84),
.OUT_PKT_BURST_TYPE_L (83),
.OUT_ST_DATA_W (107),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (1)
) width_adapter_007 (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (rsp_xbar_demux_003_src1_valid), // sink.valid
.in_channel (rsp_xbar_demux_003_src1_channel), // .channel
.in_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket
.in_ready (rsp_xbar_demux_003_src1_ready), // .ready
.in_data (rsp_xbar_demux_003_src1_data), // .data
.out_endofpacket (width_adapter_007_src_endofpacket), // src.endofpacket
.out_data (width_adapter_007_src_data), // .data
.out_channel (width_adapter_007_src_channel), // .channel
.out_valid (width_adapter_007_src_valid), // .valid
.out_ready (width_adapter_007_src_ready), // .ready
.out_startofpacket (width_adapter_007_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
video_sys_irq_mapper irq_mapper (
.clk (clock_signals_sys_clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (cpu_d_irq_irq) // sender.irq
);
endmodule
|
/* -----------------------------------------------------------------------
*
* Copyright 2008 Tommy Thorn - All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
* Bostom MA 02111-1307, USA; either version 2 of the License, or
* (at your option) any later version; incorporated herein by reference.
*
* -----------------------------------------------------------------------
*/
`timescale 1ns/10ps
module sram_ctrl
(input wire clock
,input wire rst
,output mem_waitrequest
,input [1:0] mem_id
,input [29:0] mem_address
,input mem_read
,input mem_write
,input [31:0] mem_writedata
,input [3:0] mem_writedatamask
,output reg [31:0] mem_readdata
,output reg [1:0] mem_readdataid = 0
,output reg [29:0] sram_a
,inout wire [31:0] sram_d
,output reg sram_cs_n = 1
,output reg [3:0] sram_be_n
,output reg sram_oe_n = 1
,output reg sram_we_n = 1
);
parameter burst_bits = 2;
parameter need_wait = 0;
parameter burst_length = 1 << burst_bits;
parameter S_IDLE = 0;
parameter S_READWAIT = 1;
parameter S_WRITE1 = 2;
parameter S_WRITE2 = 3;
reg [1:0] state = S_IDLE;
reg [burst_bits:0] cnt = ~0;
reg int_we_n = 1;
reg [1:0] pendingid;
reg [31:0] sram_dout;
assign mem_waitrequest = state != S_IDLE || !cnt[burst_bits];
reg sram_dout_en = 0;
assign sram_d = sram_dout_en ? sram_dout : 'hZ;
always @(negedge clock)
sram_we_n <= int_we_n;
// XXX It's a concern that the SRAM D drivers may be fighting
// briefly with our sram_dout when transitioning directly from
// reading to writing. It seems to work, but it would probably be
// safer to wait for a cycle for those cases.
/*
* NOTE: It is important that sram_dout_en be (redundantly)
* assigned in every state to insure that the enable is packed into
* the IO buffer. Credit to Martin Schoeberl for finding this
* obscure fact.
*/
always @(posedge clock) begin
mem_readdataid <= 0;
case (state)
S_IDLE:
if (!cnt[burst_bits]) begin
// Burst reading.
cnt <= cnt - 1;
sram_a <= sram_a + 1;
mem_readdata <= sram_d;
mem_readdataid <= pendingid;
state <= need_wait ? S_READWAIT : S_IDLE;
sram_dout_en <= 0;
end else if (mem_read) begin
pendingid <= mem_id;
sram_a <= mem_address;
sram_cs_n <= 0;
sram_oe_n <= 0;
sram_be_n <= 0;
int_we_n <= 1;
sram_dout_en <= 0;
cnt <= burst_length - 1;
state <= need_wait ? S_READWAIT : S_IDLE;
end else if (mem_write) begin
sram_a <= mem_address;
sram_dout_en <= 1;
sram_dout <= mem_writedata;
sram_be_n <= ~mem_writedatamask;
sram_cs_n <= 0;
sram_oe_n <= 1;
int_we_n <= 0;
state <= S_WRITE1;
end else begin
sram_cs_n <= 0;
sram_oe_n <= 1;
sram_dout_en <= 0;
int_we_n <= 1;
end
S_READWAIT: begin
state <= S_IDLE;
sram_dout_en <= 0;
end
S_WRITE1: begin
sram_dout_en <= 1;
if (need_wait)
state <= S_WRITE2;
else begin
int_we_n <= 1;
state <= S_IDLE;
end
end
S_WRITE2: begin
sram_dout_en <= 1;
int_we_n <= 1;
state <= S_IDLE;
end
endcase
end
//`define DEBUG_SRAM 1
`ifdef DEBUG_SRAM
always @(negedge clock)
$display("%05d SRAM cs# %x a %x d %x we# %x oe# %x", $time,
sram_cs_n, sram_a, sram_d, sram_we_n, sram_oe_n);
always @(posedge clock) begin
if (!mem_waitrequest & sel & mem_read)
$display("%05d sram[%x] -> ? for %d", $time,
{mem_address,2'd0}, mem_id);
if (!mem_waitrequest & sel & mem_write)
$display("%05d sram[%x] <- %8x/%x", $time,
{mem_address,2'd0}, mem_writedata, mem_writedatamask);
if (mem_readdataid)
$display("%05d sram[%x] -> %8x for %d", $time,
32'h3fff_fffc + (sram_a << 2), mem_readdata, mem_readdataid);
$display("%05d SRAM cs# %x a %x d %x we# %x oe# %x", $time,
sram_cs_n, sram_a, sram_d, sram_we_n, sram_oe_n);
end
`endif
endmodule
|
`timescale 1ns / 1ns
`default_nettype none
module spi(
input wire clk,
input wire rsth, // H:reset
// MCS©çÌüÍ
input wire mod_sel, // H:module select
input wire req, // H:request
input wire [3:0] command, // SPI command
// 0000 : write command
// 0001 : write data
// 0100 : read 8bit command
// 0101 : read 16bit command
// 0110 : read 24bit command
// 0111 : read 32bit command
// 1000 : start write pixel data (only down cs)
// 1001 : write pixel data (scl, sda)
// 1010 : end write pixel data (only up cs)
input wire [17:0] wdata, //
// MCSÖÌoÍ
output wire [31:0] rdata, //
output wire ack, // H:ack
// FPGAOÖÌüoÍ
output wire oSCL, //
output wire oDCX, //
output wire oCSX, //
inout wire oSDA //
);
// W
[ZNgÆreqðand
wire mod_req = mod_sel & req;
reg r_rw;
reg r_dcx;
reg [17:0] r_wdata;
reg [1:0] r_readsize;
reg [7:0] r_state;
// SPI R}h
parameter C_WRITE_COMMAND = 4'b0000;
parameter C_WRITE_DATA = 4'b0001;
parameter C_READ8_COMMAND = 4'b0100;
parameter C_READ16_COMMAND = 4'b0101;
parameter C_READ24_COMMAND = 4'b0110;
parameter C_READ32_COMMAND = 4'b0111;
parameter C_START_PIXEL = 4'b1000;
parameter C_WRITE_PIXEL = 4'b1001;
parameter C_END_PIXEL = 4'b1010;
// R/WXe[g
parameter S_IDLE = 0;
parameter S_WRITE = 1;
parameter S_READ = 2;
parameter S_READ_DMY = 3;
parameter S_END = 4;
// SPINbN¶¬
// NbNÍ1Xe[gÔŧ¿ãªèA§¿ºªè
// E«ÝÍ1SCL = 8cyc
// =X=======X=======
// ___|~~~|___|~~~|___
// -0123456701234567
// EÇÝoµÍ1SCL = 16cyc
// =X===============X===============
// _____|~~~~~~~|_______|~~~~~~~|___
// -0123456789ABCDEF0123456789ABCDEF
//
// SCLKJE^ÌTCN(read:8cyc / write:4cyc)
// SCLK§¿º°JE^ (read:3cyc / write 1cyc)
// IDLEAENDÍíÉâ~
wire [4:0] w_scl_cyc = (r_rw) ? 5'd31 : 5'd15; //
wire [4:0] w_scl_downcyc = (r_rw) ? 5'd24 : 5'd12; //
wire [4:0] w_scl_upcyc = (r_rw) ? 5'd8 : 5'd4; //
reg [4:0] r_sclcnt;
always @(posedge clk) begin
if(rsth) r_sclcnt <= 5'd0;
else if(r_sclcnt == w_scl_cyc) r_sclcnt <= 5'd0;
else r_sclcnt <= r_sclcnt + 5'd1;
end
reg r_scl;
wire w_scl_stop = (r_state == S_IDLE) | (r_state == S_END);
always @(posedge clk) begin
if(rsth | w_scl_stop) r_scl <= 1'b0;
else if(r_sclcnt == w_scl_downcyc) r_scl <= 1'b0;
else if(r_sclcnt == w_scl_upcyc) r_scl <= 1'b1;
end
//
wire w_en_state = (r_rw) ? (r_sclcnt == 5'd4) : (r_sclcnt == 5'd0);
// req§¿ãªèmÅp[^¶¬
reg r_req;
always @(posedge clk) begin
if(rsth) r_req <= 1'b0;
else r_req <= mod_req;
end
wire w_req_pe = ~r_req & mod_req;
// reqÅeíf[^ðb`
reg [3:0] r_command;
reg [1:0] w_readsize;
reg w_rw;
always @(*) begin
case (command)
C_READ16_COMMAND : w_readsize = 2'b01;
C_READ24_COMMAND : w_readsize = 2'b10;
C_READ32_COMMAND : w_readsize = 2'b11;
default : w_readsize = 2'b00;
endcase
end
always @(*) begin
case (command)
C_READ8_COMMAND : w_rw = 1'b1;
C_READ16_COMMAND : w_rw = 1'b1;
C_READ24_COMMAND : w_rw = 1'b1;
C_READ32_COMMAND : w_rw = 1'b1;
default : w_rw = 1'b0;
endcase
end
always @(posedge clk) begin
if(rsth) begin
r_rw <= 1'b0;
r_dcx <= 1'b0;
r_wdata <= 18'd0;
r_readsize <= 2'b00;
r_command <= 4'd0;
end
else if(w_req_pe) begin
r_rw <= w_rw;
r_dcx <= ~( (command == C_WRITE_COMMAND)
| (command == C_READ8_COMMAND)
| (command == C_READ16_COMMAND)
| (command == C_READ24_COMMAND)
| (command == C_READ32_COMMAND));
r_wdata <= wdata;
r_readsize <= w_readsize;
r_command <= command;
end
end
wire is_pixel_command = (r_command == C_START_PIXEL) | (r_command == C_WRITE_PIXEL) | (r_command == C_END_PIXEL);
// req§¿ãªèmÌÛ
reg r_req_detected;
always @(posedge clk) begin
if(rsth) r_req_detected <= 1'b0;
else if(w_req_pe & ~((command == C_START_PIXEL) | (command == C_END_PIXEL))) r_req_detected <= 1'b1;
else if(r_state == S_END) r_req_detected <= 1'b0;
end
// Xe[g}V
// Xe[gÌJÚÍAread:1cycÅAwrite:0cycÅs¤
// pÓ·éXe[gÍ
// IDLE:
// WRITE:
// READ:
reg [4:0] r_remain_transdata;
reg [4:0] r_remain_read;
always @(posedge clk) begin
if(rsth) r_state <= S_IDLE;
else if(w_en_state) begin
case(r_state)
S_IDLE: begin
// reqªüͳê½çàêÈWRITEXe[gÉJÚ
if(r_req_detected) begin
r_state <= S_WRITE;
end
end
S_WRITE: begin
// f[^oÍXe[g
// cèÌoÍf[^ª0ÉÈÁ½ç
// r_rw = 1ÌêAREAD_DMYXe[gÉJÚ
// r_rw = 0ÌêAENDXe[gÉJÚ
if(r_remain_transdata == 5'd0) begin
r_state <= (r_rw) ? ((r_readsize == 0) ? S_READ : S_READ_DMY) : S_END;
end
end
S_READ_DMY: r_state <= S_READ; // ½àµÈ¢ÅREADÉJÚ
S_READ: begin
// f[^ÇÝoµXe[g
// cèÌÇÝoµf[^ª0ÉÈÁ½çENDÉJÚ
if(r_remain_read == 5'd0) r_state <= S_END;
end
S_END: begin
r_state <= S_IDLE;
end
default: r_state <= S_IDLE;
endcase
end
end
// f[^ÇÝoµ
reg [31:0] r_rdata;
always @(posedge clk) begin
if(rsth) r_remain_read <= 5'd0;
else if(w_en_state) begin
if(r_state == S_IDLE) r_remain_read <= (r_readsize * 8 + 5'd7);
else if(r_state == S_READ) r_remain_read <= r_remain_read - 5'd1;
end
end
always @(posedge clk) begin
if(rsth) r_rdata <= 32'd0;
else if((r_state == S_IDLE) && r_req_detected) r_rdata <= 32'd0;
else if(w_scl_upcyc) begin
if(r_state == S_READ) r_rdata[r_remain_read] <= oSDA;
end
end
// f[^]
// SDA
reg [4:0] w_remain_transdata;
always @(*) begin
case(command)
C_WRITE_PIXEL : w_remain_transdata = 5'd23;
default : w_remain_transdata = 5'd7;
endcase
end
always @(posedge clk) begin
if(rsth) r_remain_transdata <= 5'd0;
else if(w_en_state) begin
if((r_state == S_IDLE) && r_req_detected) r_remain_transdata <= w_remain_transdata;
else if(r_remain_transdata == 5'd0) r_remain_transdata <= 5'd0;
else r_remain_transdata <= r_remain_transdata - 5'd1;
end
end
reg r_sda;
reg [22:0] r_wdata_sda;
always @(posedge clk) begin
if(rsth) r_wdata_sda <= 23'd0;
else if(w_en_state) begin
if((r_state == S_IDLE) && r_req_detected) begin
if(r_command == C_WRITE_PIXEL) begin
r_wdata_sda[22:0] <= {
2'b00,
r_wdata[0],
r_wdata[1],
r_wdata[2],
r_wdata[3],
r_wdata[4],
r_wdata[5],
2'b00,
r_wdata[6],
r_wdata[7],
r_wdata[8],
r_wdata[9],
r_wdata[10],
r_wdata[11],
2'b00,
r_wdata[12],
r_wdata[13],
r_wdata[14],
r_wdata[15],
r_wdata[16]
};
end
else begin
r_wdata_sda[22:0] <= {
16'd0,
r_wdata[0], r_wdata[1], r_wdata[2], r_wdata[3], r_wdata[4], r_wdata[5], r_wdata[6]};
end
end
else if(r_state == S_WRITE) r_wdata_sda[22:0] <= {1'b0, r_wdata_sda[22:1]};
end
end
always @(posedge clk) begin
if(rsth) r_sda <= 1'bz;
else if(w_en_state) begin
if((r_state == S_IDLE) && r_req_detected) r_sda <= (r_command == C_WRITE_PIXEL) ? r_wdata[17]
: r_wdata[7]; // «ÝÍMSB©ç
else if(r_state == S_WRITE) begin
if(r_remain_transdata == 5'd0)
r_sda <= 1'bz;
else
r_sda <= r_wdata_sda[0]; // r_wdata_sdaÍCgf[^ðMSB/LSB½]µ½àÌ
end
end
end
// CS
// «ÝÉAT[g
// I¹ÉlQ[g
reg r_cs;
always @(posedge clk) begin
if(rsth) begin
r_cs <= 1'b1;
end
else if(w_req_pe & (command == C_START_PIXEL)) begin
r_cs <= 1'b0;
end
else if(w_req_pe & (command == C_END_PIXEL)) begin
r_cs <= 1'b1;
end
else if(w_en_state & ~is_pixel_command) begin
if((r_state == S_IDLE) && r_req_detected) begin
r_cs <= 1'b0;
end
else if(~r_rw) begin // «ÝÍ«Ý®¹ÅlQ[g
if((r_state == S_WRITE) && (r_remain_transdata == 3'd0)) begin
r_cs <= 1'b1;
end
end
else begin // ÇÝoµÍÇÝoµ®¹ÅlQ[g
if((r_state == S_READ) && (r_remain_read == 5'd0)) begin
// else begin // ÇÝoµÍENDÉJڵĩçlQ[g
// if(r_state == S_END) begin
r_cs <= 1'b1;
end
end
end
end
// D/CX
// «ÝÉb`µ½dcxðAT[g
// I¹ÉlQ[g
reg r_dcx_out;
always @(posedge clk) begin
if(rsth) begin
r_dcx_out <= 1'b1;
end
else if(w_en_state) begin
if((r_state == S_IDLE) && r_req_detected) begin
r_dcx_out <= r_dcx;
end
else if((r_state == S_WRITE) && (r_remain_transdata == 3'd0)) begin
r_dcx_out <= 1'b1;
end
end
end
// ACK
// ACKÍREQÅNAAXe[gªI¹ÜÅJÚµ½çAT[g
reg r_ack;
always @(posedge clk) begin
if(rsth) r_ack <= 1'b1;
else if(w_req_pe & ~((command == C_START_PIXEL) | (command == C_END_PIXEL))) r_ack <= 1'b0;
else if(w_en_state) begin
if(r_state == S_END) r_ack <= 1'b1;
end
end
// oÍ
assign rdata = r_rdata;
assign ack = r_ack;
assign oSCL = r_scl;
assign oDCX = r_dcx_out;
assign oCSX = r_cs;
assign oSDA = r_sda;
endmodule
`default_nettype wire
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:50:25 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_xbar_0_stub.v
// Design : DemoInterconnect_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[95:0],s_axi_awprot[8:0],s_axi_awvalid[2:0],s_axi_awready[2:0],s_axi_wdata[95:0],s_axi_wstrb[11:0],s_axi_wvalid[2:0],s_axi_wready[2:0],s_axi_bresp[5:0],s_axi_bvalid[2:0],s_axi_bready[2:0],s_axi_araddr[95:0],s_axi_arprot[8:0],s_axi_arvalid[2:0],s_axi_arready[2:0],s_axi_rdata[95:0],s_axi_rresp[5:0],s_axi_rvalid[2:0],s_axi_rready[2:0],m_axi_awaddr[223:0],m_axi_awprot[20:0],m_axi_awvalid[6:0],m_axi_awready[6:0],m_axi_wdata[223:0],m_axi_wstrb[27:0],m_axi_wvalid[6:0],m_axi_wready[6:0],m_axi_bresp[13:0],m_axi_bvalid[6:0],m_axi_bready[6:0],m_axi_araddr[223:0],m_axi_arprot[20:0],m_axi_arvalid[6:0],m_axi_arready[6:0],m_axi_rdata[223:0],m_axi_rresp[13:0],m_axi_rvalid[6:0],m_axi_rready[6:0]" */;
input aclk;
input aresetn;
input [95:0]s_axi_awaddr;
input [8:0]s_axi_awprot;
input [2:0]s_axi_awvalid;
output [2:0]s_axi_awready;
input [95:0]s_axi_wdata;
input [11:0]s_axi_wstrb;
input [2:0]s_axi_wvalid;
output [2:0]s_axi_wready;
output [5:0]s_axi_bresp;
output [2:0]s_axi_bvalid;
input [2:0]s_axi_bready;
input [95:0]s_axi_araddr;
input [8:0]s_axi_arprot;
input [2:0]s_axi_arvalid;
output [2:0]s_axi_arready;
output [95:0]s_axi_rdata;
output [5:0]s_axi_rresp;
output [2:0]s_axi_rvalid;
input [2:0]s_axi_rready;
output [223:0]m_axi_awaddr;
output [20:0]m_axi_awprot;
output [6:0]m_axi_awvalid;
input [6:0]m_axi_awready;
output [223:0]m_axi_wdata;
output [27:0]m_axi_wstrb;
output [6:0]m_axi_wvalid;
input [6:0]m_axi_wready;
input [13:0]m_axi_bresp;
input [6:0]m_axi_bvalid;
output [6:0]m_axi_bready;
output [223:0]m_axi_araddr;
output [20:0]m_axi_arprot;
output [6:0]m_axi_arvalid;
input [6:0]m_axi_arready;
input [223:0]m_axi_rdata;
input [13:0]m_axi_rresp;
input [6:0]m_axi_rvalid;
output [6:0]m_axi_rready;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: swrvr_clib.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
//
// Module Name: swrvr_clib.v
// Description: Design control behavioural library
*/
`ifdef FPGA_SYN
`define NO_SCAN
`endif
// POSITVE-EDGE TRIGGERED FLOP with SCAN
module dff (din, clk, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
`ifdef NO_SCAN
always @ (posedge clk)
q[SIZE-1:0] <= din[SIZE-1:0] ;
`else
always @ (posedge clk)
q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : din[SIZE-1:0] ;
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`endif
endmodule // dff
// POSITVE-EDGE TRIGGERED FLOP with SCAN for Shadow-scan
module dff_sscan (din, clk, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
`ifdef CONNECT_SHADOW_SCAN
always @ (posedge clk)
q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : din[SIZE-1:0] ;
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`else
always @ (posedge clk)
q[SIZE-1:0] <= din[SIZE-1:0] ;
assign so={SIZE{1'b0}};
`endif
endmodule // dff
// POSITVE-EDGE TRIGGERED FLOP without SCAN
module dff_ns (din, clk, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
always @ (posedge clk)
q[SIZE-1:0] <= din[SIZE-1:0] ;
endmodule // dff_ns
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET
module dffr (din, clk, rst, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input rst ; // reset
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
`ifdef NO_SCAN
always @ (posedge clk)
q[SIZE-1:0] <= ((rst) ? {SIZE{1'b0}} : din[SIZE-1:0] );
`else
// Scan-Enable dominates
always @ (posedge clk)
q[SIZE-1:0] <= se ? si[SIZE-1:0] : ((rst) ? {SIZE{1'b0}} : din[SIZE-1:0] );
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`endif
endmodule // dffr
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, RESET_L
module dffrl (din, clk, rst_l, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input rst_l ; // reset
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
`ifdef NO_SCAN
always @ (posedge clk)
q[SIZE-1:0] <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
`else
// Reset dominates
always @ (posedge clk)
q[SIZE-1:0] <= rst_l ? ((se) ? si[SIZE-1:0] : din[SIZE-1:0] ) : {SIZE{1'b0}};
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`endif
endmodule // dffr_l
// POSITIVE-EDGE TRIGGERED FLOP with RESET, without SCAN
module dffr_ns (din, clk, rst, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk
input rst ; // reset
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// synopsys sync_set_reset "rst"
always @ (posedge clk)
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
endmodule // dffr_ns
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, without SCAN
module dffrl_ns (din, clk, rst_l, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk
input rst_l ; // reset
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// synopsys sync_set_reset "rst_l"
always @ (posedge clk)
q[SIZE-1:0] <= rst_l ? din[SIZE-1:0] : {SIZE{1'b0}};
endmodule // dffrl_ns
// POSITIVE-EDGE TRIGGERED FLOP with SCAN and FUNCTIONAL ENABLE
module dffe (din, en, clk, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input en ; // functional enable
input clk ; // clk or scan clk
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
// Enable Interpretation. Ultimate interpretation depends on design
//
// en se out
//------------------
// x 1 sin ; scan dominates
// 1 0 din
// 0 0 q
//
`ifdef NO_SCAN
always @ (posedge clk)
q[SIZE-1:0] <= ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
`else
always @ (posedge clk)
q[SIZE-1:0] <= (se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) ;
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`endif
endmodule // dffe
// POSITIVE-EDGE TRIGGERED FLOP with enable, without SCAN
module dffe_ns (din, en, clk, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input en ; // functional enable
input clk ; // clk
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
always @ (posedge clk)
q[SIZE-1:0] <= en ? din[SIZE-1:0] : q[SIZE-1:0];
endmodule // dffe_ns
// POSITIVE-EDGE TRIGGERED FLOP with RESET, FUNCTIONAL ENABLE, SCAN.
module dffre (din, rst, en, clk, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input en ; // functional enable
input rst ; // reset
input clk ; // clk or scan clk
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
// Enable Interpretation. Ultimate interpretation depends on design
//
// rst en se out
//------------------
// 1 x x 0 ; reset dominates
// 0 x 1 sin ; scan dominates
// 0 1 0 din
// 0 0 0 q
//
`ifdef NO_SCAN
always @ (posedge clk)
q[SIZE-1:0] <= (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
`else
always @ (posedge clk)
// q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
q[SIZE-1:0] <= se ? si[SIZE-1:0] : (rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) ;
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`endif
endmodule // dffre
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, FUNCTIONAL ENABLE, SCAN.
module dffrle (din, rst_l, en, clk, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input en ; // functional enable
input rst_l ; // reset
input clk ; // clk or scan clk
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
// Enable Interpretation. Ultimate interpretation depends on design
//
// rst en se out
//------------------
// 0 x x 0 ; reset dominates
// 1 x 1 sin ; scan dominates
// 1 1 0 din
// 1 0 0 q
//
`ifdef NO_SCAN
always @ (posedge clk)
q[SIZE-1:0] <= (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
`else
always @ (posedge clk)
// q[SIZE-1:0] <= rst_l ? ((se) ? si[SIZE-1:0] : ((en) ? din[SIZE-1:0] : q[SIZE-1:0])) : {SIZE{1'b0}} ;
q[SIZE-1:0] <= se ? si[SIZE-1:0] : (rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}}) ;
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`endif
endmodule // dffrle
// POSITIVE-EDGE TRIGGERED FLOP with RESET, ENABLE, without SCAN.
module dffre_ns (din, rst, en, clk, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input en ; // functional enable
input rst ; // reset
input clk ; // clk
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// Enable Interpretation. Ultimate interpretation depends on design
//
// rst en out
//------------------
// 1 x 0 ; reset dominates
// 0 1 din
// 0 0 q
//
// synopsys sync_set_reset "rst"
always @ (posedge clk)
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((en) ? din[SIZE-1:0] : q[SIZE-1:0]);
endmodule // dffre_ns
// POSITIVE-EDGE TRIGGERED FLOP with RESET_L, ENABLE, without SCAN.
module dffrle_ns (din, rst_l, en, clk, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input en ; // functional enable
input rst_l ; // reset
input clk ; // clk
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// Enable Interpretation. Ultimate interpretation depends on design
//
// rst en out
//------------------
// 0 x 0 ; reset dominates
// 1 1 din
// 1 0 q
//
// synopsys sync_set_reset "rst_l"
always @ (posedge clk)
q[SIZE-1:0] <= rst_l ? ((en) ? din[SIZE-1:0] : q[SIZE-1:0]) : {SIZE{1'b0}} ;
endmodule // dffrle_ns
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET
module dffr_async (din, clk, rst, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input rst ; // reset
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
`ifdef NO_SCAN
always @ (posedge clk or posedge rst)
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
`else
// Reset dominates
always @ (posedge clk or posedge rst)
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : din[SIZE-1:0] );
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`endif
endmodule // dffr_async
// POSITIVE-EDGE TRIGGERED FLOP with SCAN, and ASYNC RESET_L
module dffrl_async (din, clk, rst_l, q, se, si, so);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input rst_l ; // reset
output [SIZE-1:0] q ; // output
input se ; // scan-enable
input [SIZE-1:0] si ; // scan-input
output [SIZE-1:0] so ; // scan-output
reg [SIZE-1:0] q ;
`ifdef NO_SCAN
always @ (posedge clk or negedge rst_l)
q[SIZE-1:0] <= (!rst_l) ? {SIZE{1'b0}} : din[SIZE-1:0];
`else
// Reset dominates
always @ (posedge clk or negedge rst_l)
q[SIZE-1:0] <= (!rst_l) ? {SIZE{1'b0}} : ((se) ? si[SIZE-1:0] : din[SIZE-1:0] );
assign so[SIZE-1:0] = q[SIZE-1:0] ;
`endif
endmodule // dffrl_async
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET, without SCAN
//module dffr_async_ns (din, clk, rst, q);
//
//parameter SIZE = 1;
//input [SIZE-1:0] din ; // data in
//input clk ; // clk or scan clk
//input rst ; // reset
//output [SIZE-1:0] q ; // output
//reg [SIZE-1:0] q ;
// Reset dominates
//// synopsys async_set_reset "rst"
//always @ (posedge clk or posedge rst)
// if(rst) q[SIZE-1:0] <= {SIZE{1'b0}};
// else if(clk) q[SIZE-1:0] <= din[SIZE-1:0];
//endmodule // dffr_async_ns
// POSITIVE-EDGE TRIGGERED FLOP with ASYNC RESET_L, without SCAN
module dffrl_async_ns (din, clk, rst_l, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input rst_l ; // reset
output [SIZE-1:0] q ; // output
// Reset dominates
// synopsys async_set_reset "rst_l"
reg [SIZE-1:0] q;
always @ (posedge clk or negedge rst_l)
q[SIZE-1:0] <= ~rst_l ? {SIZE{1'b0}} : ({SIZE{rst_l}} & din[SIZE-1:0]);
// reg [SIZE-1:0] qm, qs, qm_l, qs_l, qm_f, qs_f;
// wire s_l;
// assign s_l = 1'b1;
//
// always @ (rst_l or qm) qm_l = ~(qm & {SIZE{rst_l}});
// always @ (s_l or qs) qs_l = ~(qs & {SIZE{s_l}});
// always @ (s_l or qm_l) qm_f = ~(qm_l & {SIZE{s_l}});
// always @ (rst_l or qs_l) qs_f = ~(qs_l & {SIZE{rst_l}});
//
// always @ (clk or din or qm_f)
// qm <= clk ? qm_f : din;
//
// always @ (clk or qm_l or qs_f)
// qs <= clk ? qm_l : qs_f;
//
// assign q = ~qs;
endmodule // dffrl_async_ns
// 2:1 MUX WITH DECODED SELECTS
module mux2ds (dout, in0, in1, sel0, sel1) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input sel0;
input sel1;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
// priority encoding takes care of mutex'ing selects.
`ifdef VERPLEX
$constraint cl_1h_chk2 ($one_hot ({sel1,sel0}));
`endif
wire [1:0] sel = {sel1, sel0}; // 0in one_hot
always @ (sel0 or sel1 or in0 or in1)
case ({sel1,sel0}) // synopsys infer_mux
2'b01 : dout = in0 ;
2'b10 : dout = in1 ;
2'b11 : dout = {SIZE{1'bx}} ;
2'b00 : dout = {SIZE{1'bx}} ;
// 2'b00 : // E.g. 4state vs. 2state modelling.
// begin
// `ifdef FOUR_STATE
// dout = {SIZE{1'bx}};
// `else
// begin
// dout = {SIZE{1'b0}};
// $error();
// end
// `endif
// end
default : dout = {SIZE{1'bx}};
endcase
endmodule // mux2ds
// 3:1 MUX WITH DECODED SELECTS
module mux3ds (dout, in0, in1, in2, sel0, sel1, sel2) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input sel0;
input sel1;
input sel2;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint cl_1h_chk3 ($one_hot ({sel2,sel1,sel0}));
`endif
wire [2:0] sel = {sel2,sel1,sel0}; // 0in one_hot
// priority encoding takes care of mutex'ing selects.
always @ (sel0 or sel1 or sel2 or in0 or in1 or in2)
case ({sel2,sel1,sel0})
3'b001 : dout = in0 ;
3'b010 : dout = in1 ;
3'b100 : dout = in2 ;
3'b000 : dout = {SIZE{1'bx}} ;
3'b011 : dout = {SIZE{1'bx}} ;
3'b101 : dout = {SIZE{1'bx}} ;
3'b110 : dout = {SIZE{1'bx}} ;
3'b111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}};
// two state vs four state modelling will be added.
endcase
endmodule // mux3ds
// 4:1 MUX WITH DECODED SELECTS
module mux4ds (dout, in0, in1, in2, in3, sel0, sel1, sel2, sel3) ;
parameter SIZE = 1;
output [SIZE-1:0] dout;
input [SIZE-1:0] in0;
input [SIZE-1:0] in1;
input [SIZE-1:0] in2;
input [SIZE-1:0] in3;
input sel0;
input sel1;
input sel2;
input sel3;
// reg declaration does not imply state being maintained
// across cycles. Used to construct case statement and
// always updated by inputs every cycle.
reg [SIZE-1:0] dout ;
`ifdef VERPLEX
$constraint cl_1h_chk4 ($one_hot ({sel3,sel2,sel1,sel0}));
`endif
wire [3:0] sel = {sel3,sel2,sel1,sel0}; // 0in one_hot
// priority encoding takes care of mutex'ing selects.
always @ (sel0 or sel1 or sel2 or sel3 or in0 or in1 or in2 or in3)
case ({sel3,sel2,sel1,sel0})
4'b0001 : dout = in0 ;
4'b0010 : dout = in1 ;
4'b0100 : dout = in2 ;
4'b1000 : dout = in3 ;
4'b0000 : dout = {SIZE{1'bx}} ;
4'b0011 : dout = {SIZE{1'bx}} ;
4'b0101 : dout = {SIZE{1'bx}} ;
4'b0110 : dout = {SIZE{1'bx}} ;
4'b0111 : dout = {SIZE{1'bx}} ;
4'b1001 : dout = {SIZE{1'bx}} ;
4'b1010 : dout = {SIZE{1'bx}} ;
4'b1011 : dout = {SIZE{1'bx}} ;
4'b1100 : dout = {SIZE{1'bx}} ;
4'b1101 : dout = {SIZE{1'bx}} ;
4'b1110 : dout = {SIZE{1'bx}} ;
4'b1111 : dout = {SIZE{1'bx}} ;
default : dout = {SIZE{1'bx}};
// two state vs four state modelling will be added.
endcase
endmodule // mux4ds
// SINK FOR UNLOADED INPUT PORTS
module sink (in);
parameter SIZE = 1;
input [SIZE-1:0] in;
`ifdef FPGA_SYN
// As of version 8.2 XST does not remove this module without the
// following additional dead code
wire a;
assign a = | in;
`endif
endmodule //sink
// SOURCE FOR UNDRIVEN OUTPUT PORTS
module source (out) ;
parameter SIZE = 1;
output [SIZE-1:0] out;
//
// Once 4state/2state model established
// then enable check.
// `ifdef FOUR_STATE
// leda check for x_or_z_in rhs_of assign turned off
// assign out = {SIZE{1'bx}};
//`else
assign out = {SIZE{1'b0}};
//`endif
endmodule //source
// 2:1 MUX WITH PRIORITY ENCODED SELECTS
//module mux2es (dout, in0, in1, sel0, sel1) ;
//
//parameter SIZE = 1;
//
//output [SIZE-1:0] dout;
//input [SIZE-1:0] in0;
//input [SIZE-1:0] in1;
//input sel0;
//input sel1;
//
//// reg declaration does not imply state being maintained
//// across cycles. Used to construct case statement and
//// always updated by inputs every cycle.
//reg [SIZE-1:0] dout ;
//
//// must take into account lack of mutex selects.
//// there is no reason for handling of x and z conditions.
//// This will be dictated by design.
//always @ (sel0 or sel1 or in0 or in1)
//
// case ({sel1,sel0})
// 2'b1x : dout = in1 ; // 10(in1),11(z)
// 2'b0x : dout = in0 ; // 01(in0),00(x)
// endcase
//
//endmodule // mux2es
// CLK Header for gating off the clock of
// a FF.
// clk - output of the clk header
// rclk - input clk
// enb_l - Active low clock enable
// tmb_l - Active low clock enable ( in scan mode, this input is !se )
module clken_buf (clk, rclk, enb_l, tmb_l);
output clk;
input rclk, enb_l, tmb_l;
reg clken;
always @ (rclk or enb_l or tmb_l)
if (!rclk) //latch opens on rclk low phase
clken = !enb_l | !tmb_l;
assign clk = clken & rclk;
endmodule
// The following flops are maintained and used in ENET , MAC IP ONLY
// -- Mimi X61467
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
module dffsl_ns (din, clk, set_l, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input set_l ; // set
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// synopsys sync_set_reset "set_l"
always @ (posedge clk)
q[SIZE-1:0] <= set_l ? din[SIZE-1:0] : {SIZE{1'b1}};
endmodule // dffsl_ns
// POSITIVE-EDGE TRIGGERED FLOP with SET_L, without SCAN.
module dffsl_async_ns (din, clk, set_l, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input set_l ; // set
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// synopsys async_set_reset "set_l"
always @ (posedge clk or negedge set_l)
q[SIZE-1:0] <= ~set_l ? {SIZE{1'b1}} : ({SIZE{~set_l}} | din[SIZE-1:0]);
endmodule // dffsl_async_ns
// POSITIVE-EDGE TRIGGERED FLOP WITH SET_H , without SCAN.
module dffr_ns_r1 (din, clk, rst, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input rst ; // reset
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// Set to 1
// synopsys sync_set_reset "rst"
always @ (posedge clk)
q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
endmodule // dffr_ns_r1
// POSITIVE-EDGE TRIGGERED ASYNC RESET_H FLOP , without SCAN.
module dffr_async_ns (din, clk, rst, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input rst; // reset
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// Reset dominates
// synopsys async_set_reset "rst"
always @ (posedge clk or posedge rst)
q[SIZE-1:0] <= rst ? {SIZE{1'b0}} : din[SIZE-1:0];
endmodule // dffr_async_ns
// POSITIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
module dffr_async_ns_r1 (din, clk, rst, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clk ; // clk or scan clk
input rst; // reset
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// Reset to 1
// synopsys async_set_reset "rst"
always @ (posedge clk or posedge rst)
q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
endmodule // dffr_async_ns_r1
// NEGATIVE-EDGE TRIGGERED ASYNC SET_H FLOP , without SCAN.
module dffr_async_ns_cl_r1 (din, clkl, rst, q);
parameter SIZE = 1;
input [SIZE-1:0] din ; // data in
input clkl ; // clk or scan clk
input rst ; // reset
output [SIZE-1:0] q ; // output
reg [SIZE-1:0] q ;
// Set to 1
// synopsys sync_set_reset "rst"
always @ (negedge clkl or posedge rst)
q[SIZE-1:0] <= rst ? {SIZE{1'b1}} : din[SIZE-1:0];
endmodule // dffr_async_ns_cl_r1
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Mon Mar 14 19:31:48 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
GND GND
(.G(GND_1));
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.USB0_VBUS_PWRFAULT(GND_1));
endmodule
|
module Forward(
input [1:0]RegDst,
input[4:0] Rt_From_ID_EX,
input[4:0] Rs_From_ID_EX,
input[4:0] Rd_From_EX_MEM,
input[3:0] RegWrite_From_EX_MEM,
input[4:0] Rd_From_MEM_WB,
input[3:0] RegWrite_From_MEM_WB,
output [1:0] Rs_EX_Forward,Rt_EX_Forward,
//LoudUse_Forward
input[4:0] Rt_From_IF_ID,
input[4:0] Rs_From_IF_ID,
input[1:0] RegRead,
output Rs_LoudUse_Forward,Rt_LoudUse_Forward
);
assign Rs_EX_Forward = ((RegDst[1] === 1'b1)&&((Rs_From_ID_EX === Rd_From_EX_MEM) && (RegWrite_From_EX_MEM !== 4'b0000)))?(2'b01):((RegDst[1] === 1'b1) && (Rs_From_ID_EX === Rd_From_MEM_WB) && (RegWrite_From_MEM_WB !== 4'b0000)?2'b10:2'b00);
assign Rt_EX_Forward = ((RegDst[0] === 1'b1)&&((Rt_From_ID_EX === Rd_From_EX_MEM) && (RegWrite_From_EX_MEM !== 4'b0000)))?(2'b01):((RegDst[0] === 1'b1) && (Rt_From_ID_EX === Rd_From_MEM_WB) && (RegWrite_From_MEM_WB !== 4'b0000)?2'b10:2'b00);
assign Rs_LoudUse_Forward = (RegRead[0] & Rs_From_IF_ID === Rd_From_MEM_WB && RegWrite_From_MEM_WB !== 4'b0)?1'b1:1'b0;
assign Rt_LoudUse_Forward = (RegRead[1] & Rt_From_IF_ID === Rd_From_MEM_WB && RegWrite_From_MEM_WB !== 4'b0)?1'b1:1'b0;
//RegRead[0] & RegRead[1] &
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Juan Jose Rojas Salazar
//
// Create Date: 07/07/2016 09:29:49 AM
// Design Name:
// Module Name: Coprocesador_CORDIC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Coprocesador_CORDIC#(parameter P = 32, parameter S=8, parameter D=5, parameter W_Exp = 8,
parameter W_Sgf = 23, parameter S_Exp = 9) (
input wire [31:0] T,
input wire CLK, //RELOJ DEL SISTEMA
input wire RST, //RESET PARA LOS REGISTROS
input wire MS_1, //SELECCION DEL MUX 1 VALOR INICIAL DE Z
input wire EN_REG3, //ENABLE REG 3 RESULTADO EXP
//input wire EN_REGMult, //ENABLE REG MULT
input wire ADD_SUBT, //SELECCION DE OPERACION PARA EL ADD/SUBT FLOTANTE
input wire Begin_SUMX, //INICIA LA OPERACION EN ADD/SUBT FLOTANTE
input wire Begin_SUMY, //INICIA LA OPERACION EN ADD/SUBT FLOTANTE
input wire Begin_SUMZ, //INICIA LA OPERACION EN ADD/SUBT FLOTANTE
input wire EN_REG1X, //ENABLE PARA REGISTROS X,Y,Z DE LA PRIMERA ETAPA
input wire EN_REG1Y, //ENABLE PARA REGISTROS X,Y,Z DE LA PRIMERA ETAPA
input wire EN_REG1Z, //ENABLE PARA REGISTROS X,Y,Z DE LA PRIMERA ETAPA
input wire MS_2, //SELECCION MUX 2
input wire EN_REG2, //ENABLE PARA EL REGISTRO QUE GUARDA LOS VALORES DESPLAZADOS EN LA SEGUNDA ETAPA
input wire CLK_CDIR, //CLK PARA EL CONTADOR DE ITERACIONES
input wire EN_REG2XYZ, //ENABLE PARA REGISTROS QUE GUARDAN EL VALOR ANTERIOR DE X,Y,Z
output wire ACK_SUMX, //ACK PARA DETERMINAR CUANDO LA SUMA FLOTANTE X SE COMPLETO
output wire ACK_SUMY, //ACK PARA DETERMINAR CUANDO LA SUMA FLOTANTE Y SE COMPLETO
output wire ACK_SUMZ, //ACK PARA DETERMINAR CUANDO LA SUMA FLOTANTE Z SE COMPLETO
output wire O_FX, //BANDERA DE OVERFLOW X
output wire O_FY, //BANDERA DE OVERFLOW Y
output wire O_FZ, //BANDERA DE OVERFLOW Z
output wire U_FX, //BANDERA DE UNDERFLOW X
output wire U_FY, //BANDERA DE UNDERFLOW Y
output wire U_FZ, //BANDERA DE UNDERFLOW Z
output wire [P-1:0] RESULT, //RESULTADO FINAL
output wire [D-1:0] CONT_ITERA //NUMERO DE LA ITERACION
);
//salidas mux MS_1 a REG1X,Y,Z
wire [P-1:0] MUX0;
wire [P-1:0] MUX1;
wire [P-1:0] MUX2;
//salidas registros 1 a mux MS_2, signo y desplazador de exponente
wire [P-1:0] X_ant;
wire [P-1:0] Y_ant;
wire [P-1:0] Z_ant;
//salida LUT valores arctan
wire [P-1:0] LUT_arctan;
//salida valores exponentes y mantissas desplazados)
wire [P-1:0] MULT_RESULTX;
wire [P-1:0] MULT_RESULTY;
//salida CONTADOR DE ITER A LUT'S
wire [D-1:0] DIR_LUT;
// salida de signos
wire SIGNO_Z;
//SIGNO + EXPONENTE + MANTISA
wire [P-1:0] X_act;
wire [P-1:0] Y_act;
wire [P-1:0] Z_act;
//salidas registros 2 a sumadores punto flotante, signo y desplazador de exponente
wire [P-1:0] REG2X;
wire [P-1:0] REG2Y;
wire [P-1:0] REG2Z;
wire [P-1:0] REG2Xa;
wire [P-1:0] REG2Ya;
wire [P-1:0] REG2Za;
wire [P-1:0] DESP;
//wire [P-1:0] DESPX;
//wire [P-1:0] DESPXY;
//wire [P-1:0] DESPY;
//wire [P-1:0] DESPZ;
//salidas MUX's MS_2 a ADD/SUBT flotante (esto pertenece al registro de Z)
wire [P-1:0] A;
wire [P-1:0] B;
//resultado ADD/SUBT flotante X,Y,Z
wire [P-1:0] X_RESULT;
wire [P-1:0] Y_RESULT;
wire [P-1:0] Z_RESULT;
//ASIGNA VALOR DE LA ITERACION A LA DIRECCION DE LAS LUT
assign CONT_ITERA = DIR_LUT;
Mux_2x1 #(.P(P)) MUX2x1_0 (
.MS(MS_1),
.D_0(X_RESULT),
.D_1(32'b01000110001100000010010110011010), //11273.4 7 iteraciones negativas (0,1,2,3,4,5,6)
//.D_1(32'b01000001101011101100001010001111), //21.845 4 iteraciones negativas (0,1,2,3)
//.D_1(32'b00111111111100010101100000010000), //1.8855 2 iteraciones negativas (0 y 1)
.D_out(MUX0)
);
Mux_2x1 #(.P(P)) MUX2x1_1 (
.MS(MS_1),
.D_0(Y_RESULT),
.D_1(32'b01000110001100000010010110011010), //11273.4 7 iteraciones negativas (0,1,2,3,4,5,6)
//.D_1(32'b01000001101011101100001010001111), //21.845 4 iteraciones negativas (0,1,2,3)
//.D_1(32'b00111111111100010101100000010000), //1.8855 2 iteraciones negativas (0 y 1)
.D_out(MUX1)
);
Mux_2x1 #(.P(P)) MUX2x1_2 (
.MS(MS_1),
.D_0(Z_RESULT),
.D_1(T), //Entrada T, dato en coma flotante para calcular el exp(T)=sinh(T)+cosh(T)
.D_out(MUX2)
);
FF_D #(.P(P)) REG1_X (
.CLK(CLK),
.RST(RST),
.EN(EN_REG1X),
.D(MUX0),
.Q(X_ant)
);
FF_D #(.P(P)) REG1_Y (
.CLK(CLK),
.RST(RST),
.EN(EN_REG1Y),
.D(MUX1),
.Q(Y_ant)
);
FF_D #(.P(P)) REG1_Z (
.CLK(CLK),
.RST(RST),
.EN(EN_REG1Z),
.D(MUX2),
.Q(Z_ant)
);
FF_D #(.P(P)) REG2_Xa (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2XYZ),
.D(X_ant),
.Q(REG2Xa)
);
FF_D #(.P(P)) REG2_Ya (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2XYZ),
.D(Y_ant),
.Q(REG2Ya)
);
FF_D #(.P(P)) REG2_Za (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2XYZ),
.D(Z_ant),
.Q(REG2Za)
);
COUNTER_5B #(.P(D)) CONT_ITER (
.CLK(CLK),
.RST(RST),
.EN(CLK_CDIR),
.Y(DIR_LUT)
);
LUT_SHIFT #(.P(P),.D(D)) LUT_ITER (
.CLK(CLK),
.EN_ROM1(1'b1),
.ADRS(DIR_LUT),
.O_D(DESP)
);
LUT_Z #(.P(P),.D(D)) LUT_ARCTAN (
.CLK(CLK),
.EN_ROM1(1'b1),
.ADRS(DIR_LUT),
.O_D(LUT_arctan)
);
FP_Mul #(.P(P)) MULTX(
.clk(CLK),
.a(X_ant),
.b(DESP),
.p(MULT_RESULTX)
);
/*FP_Mul #(.P(P)) MULTY(
.clk(CLK),
.a(Y_ant),
.b(DESP),
.p(MULT_RESULTY)
); */
assign X_act = {Z_ant[31],MULT_RESULTX[30:0]};
assign Y_act = {Z_ant[31],MULT_RESULTX[30:0]};
assign Z_act = {~Z_ant[31],LUT_arctan[30:0]};
FF_D #(.P(P)) REG2_X (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2),
.D(X_act),
.Q(REG2X)
);
FF_D #(.P(P)) REG2_Y (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2),
.D(Y_act),
.Q(REG2Y)
);
FF_D #(.P(P)) REG2_Z (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2),
.D(Z_act),
.Q(REG2Z)
);
Mux_2x1 #(.P(P)) MUX2x1_4_1 (
.MS(MS_2),
.D_0(X_ant),
.D_1(REG2Za),
.D_out(A)
);
Mux_2x1 #(.P(P)) MUX2x1_4_2 (
.MS(MS_2),
.D_0(Y_ant),
.D_1(REG2Z),
.D_out(B)
);
FPU_Add_Subtract_Function #(.W(32),.EW(8),.SW(23),.SWR(26), .EWR(5)) SUM_SUBTX(
.clk(CLK),
.rst(RST),
.beg_FSM(Begin_SUMX),
.ack_FSM(ACK_SUMX),
.Data_X(REG2Xa),
.Data_Y(REG2X),
.add_subt(ADD_SUBT),
.r_mode(2'b00),
.overflow_flag(O_FX),
.underflow_flag(U_FX),
.ready(ACK_SUMX),
.final_result_ieee(X_RESULT)
);
FPU_Add_Subtract_Function #(.W(32),.EW(8),.SW(23),.SWR(26), .EWR(5)) SUM_SUBTY(
.clk(CLK),
.rst(RST),
.beg_FSM(Begin_SUMY),
.ack_FSM(ACK_SUMY),
.Data_X(REG2Ya),
.Data_Y(REG2Y),
.add_subt(ADD_SUBT),
.r_mode(2'b00),
.overflow_flag(O_FY),
.underflow_flag(U_FY),
.ready(ACK_SUMY),
.final_result_ieee(Y_RESULT)
);
FPU_Add_Subtract_Function #(.W(32),.EW(8),.SW(23),.SWR(26), .EWR(5)) SUM_SUBTZ(
.clk(CLK),
.rst(RST),
.beg_FSM(Begin_SUMZ),
.ack_FSM(ACK_SUMZ),
.Data_X(A),
.Data_Y(B),
.add_subt(ADD_SUBT),
.r_mode(2'b00),
.overflow_flag(O_FZ),
.underflow_flag(U_FZ),
.ready(ACK_SUMZ),
.final_result_ieee(Z_RESULT)
);
FF_D #(.P(P)) REG_3 (
.CLK(CLK),
.RST(RST),
.EN(EN_REG3),
.D(Z_RESULT),
.Q(RESULT)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_TB_V
`define SKY130_FD_SC_LP__SRDLSTP_TB_V
/**
* srdlstp: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__srdlstp.v"
module top();
// Inputs are registered
reg SET_B;
reg D;
reg SLEEP_B;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SET_B = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SET_B = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 KAPWR = 1'b1;
#220 SET_B = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 KAPWR = 1'b0;
#380 SET_B = 1'b0;
#400 SLEEP_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SLEEP_B = 1'b1;
#600 SET_B = 1'b1;
#620 KAPWR = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SLEEP_B = 1'bx;
#760 SET_B = 1'bx;
#780 KAPWR = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__srdlstp dut (.SET_B(SET_B), .D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_TB_V
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module main(
`ifdef MK2
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
output [22:0] ROM_ADDR,
output ROM_CE,
input MCU_OVR,
/* debug */
output p113_out,
`endif
`ifdef MK3
input SNES_CIC_CLK,
/* Bus 1: 2x PSRAM, 64Mbit, 16bit, 70ns */
output [21:0] ROM_ADDR,
output ROM_1CE,
output ROM_2CE,
output ROM_ZZ,
/* debug */
output PM6_out,
output PN6_out,
input PT5_in,
`endif
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
inout [15:0] ROM_DATA,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
input SPI_SCK,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
);
`define upper(i) (8*(i+1)-1)
`define lower(i) (8*(i+0)-0)
wire CLK2;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [7:0] SAVERAM_BASE;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [8:0] dac_ptr_addr;
//wire [7:0] dac_volume;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [7:0] DMA_SNES_DATA_IN;
wire [7:0] DMA_SNES_DATA_OUT;
wire [7:0] CTX_SNES_DATA_IN;
wire [14:0] bsx_regs;
wire [7:0] BSX_SNES_DATA_IN;
wire [7:0] BSX_SNES_DATA_OUT;
wire [7:0] bsx_regs_reset_bits;
wire [7:0] bsx_regs_set_bits;
wire [59:0] rtc_data;
wire [55:0] rtc_data_in;
wire [59:0] srtc_rtc_data_out;
wire [3:0] SRTC_SNES_DATA_IN;
wire [7:0] SRTC_SNES_DATA_OUT;
wire [15:0] featurebits;
wire feat_cmd_unlock = featurebits[5];
wire feat_bs_base_enable = featurebits[12];
wire r213f_enable;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [9:0] bs_page;
wire [8:0] bs_page_offset;
wire bs_page_enable;
wire [4:0] DBG_srtc_state;
wire DBG_srtc_we_rising;
wire [3:0] DBG_srtc_ptr;
wire [5:0] DBG_srtc_we_sreg;
wire [13:0] DBG_msu_address;
wire DBG_msu_reg_oe_rising;
wire DBG_msu_reg_oe_falling;
wire DBG_msu_reg_we_rising;
wire [2:0] SD_DMA_DBG_clkcnt;
wire [10:0] SD_DMA_DBG_cyclecnt;
wire [9:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
wire [7:0] reg_group;
wire [7:0] reg_index;
wire [7:0] reg_value;
wire [7:0] reg_invmask;
wire reg_we;
wire [7:0] reg_read;
reg [7:0] SNES_PARDr = 8'b11111111;
reg [7:0] SNES_PAWRr = 8'b11111111;
reg [7:0] SNES_READr = 8'b11111111;
reg [7:0] SNES_WRITEr = 8'b11111111;
reg [7:0] SNES_CPU_CLKr = 8'b00000000;
reg [7:0] SNES_ROMSELr = 8'b11111111;
reg [7:0] SNES_PULSEr = 8'b11111111;
reg [23:0] SNES_ADDRr [6:0];
reg [7:0] SNES_PAr [6:0];
reg [7:0] SNES_DATAr [4:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
reg loop_enable = 0;
reg [7:0] loop_data = 8'h80; // BRA
// exe region
reg exe_present; initial exe_present = 0;
wire map_unlock;
reg map_Fx_rd_unlock_r; initial map_Fx_rd_unlock_r = 0;
reg map_Fx_wr_unlock_r; initial map_Fx_wr_unlock_r = 0;
reg map_Ex_rd_unlock_r; initial map_Ex_rd_unlock_r = 0;
reg map_Ex_wr_unlock_r; initial map_Ex_wr_unlock_r = 0;
reg map_snescmd_rd_unlock_r; initial map_snescmd_rd_unlock_r = 0;
reg map_snescmd_wr_unlock_r; initial map_snescmd_wr_unlock_r = 0;
reg SNES_SNOOPRD_DATA_OE = 0;
reg SNES_SNOOPWR_DATA_OE = 0;
reg SNES_SNOOPPAWR_DATA_OE = 0;
reg SNES_SNOOPPARD_DATA_OE = 0;
reg [3:0] SNES_SNOOPRD_count;
reg [3:0] SNES_SNOOPWR_count;
reg [3:0] SNES_SNOOPPAWR_count;
reg [3:0] SNES_SNOOPPARD_count;
reg [7:0] CTX_DINr;
reg CTX_DIRr;
// early signals for snooping bus
wire SNES_PAWR_start_early = ((SNES_PAWRr[4:1] | SNES_PAWRr[5:2]) == 4'b1110);
wire SNES_RD_start_early = ((SNES_READr[6:1] | SNES_READr[7:2]) == 6'b111100);
wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
wire [7:0] SNES_PA = (SNES_PAr[5] & SNES_PAr[4]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
reg [23:0] SNES_ADDR_early; always @(posedge CLK2) SNES_ADDR_early <= (SNES_ADDRr[3] & SNES_ADDRr[2]);
wire SNES_PULSE_IN = SNES_READ_IN & SNES_WRITE_IN & ~SNES_CPU_CLK_IN;
wire SNES_PULSE_end = (SNES_PULSEr[6:1] == 6'b000011);
wire SNES_PARD_start = (SNES_PARDr[6:1] == 6'b111110);
wire SNES_PARD_end = (SNES_PARDr[6:1] == 6'b000001);
// Sample PAWR data earlier on CPU accesses, later on DMA accesses...
wire SNES_PAWR_start = (SNES_PAWRr[7:1] == (({SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h02100) ? 7'b1110000 : 7'b1000000));
wire SNES_PAWR_end = (SNES_PAWRr[6:1] == 6'b000001);
wire SNES_RD_start = (SNES_READr[6:1] == 6'b111110);
wire SNES_RD_end = (SNES_READr[6:1] == 6'b000001);
wire SNES_WR_start = (SNES_WRITEr[6:1] == 6'b111000);
wire SNES_WR_end = (SNES_WRITEr[6:1] == 6'b000001);
wire SNES_cycle_start = (SNES_CPU_CLKr[6:1] == 6'b000001);
wire SNES_cycle_end = (SNES_CPU_CLKr[6:1] == 6'b111110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_READ_late = SNES_READr[5] & SNES_READr[4];
wire SNES_READ_narrow = SNES_READ | SNES_READ_late;
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_PAWR = SNES_PAWRr[2] & SNES_PAWRr[1];
wire SNES_ROMSEL_EARLY = (SNES_ROMSELr[2] & SNES_ROMSELr[1]);
wire SNES_WRITE_early = SNES_WRITEr[1] & SNES_WRITEr[0];
reg SNES_SNOOPPARD_end;
reg SNES_SNOOPPAWR_end;
reg SNES_SNOOPRD_end;
reg SNES_SNOOPWR_end;
always @(posedge CLK2) begin
if (SNES_reset_strobe) begin
SNES_SNOOPPARD_end <= 0;
SNES_SNOOPPAWR_end <= 0;
SNES_SNOOPRD_end <= 0;
SNES_SNOOPWR_end <= 0;
end
else begin
SNES_SNOOPPARD_end <= SNES_SNOOPPARD_count == 4;
SNES_SNOOPPAWR_end <= SNES_SNOOPPAWR_count == 4;
SNES_SNOOPRD_end <= SNES_SNOOPRD_count == 4;
SNES_SNOOPWR_end <= SNES_SNOOPWR_count == 4;
end
end
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire SD_DMA_TO_ROM;
wire free_slot = (SNES_PULSE_end | free_strobe) & ~SD_DMA_TO_ROM;
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= (~ROM_HIT | loop_enable);
end
always @(posedge CLK2) begin
SNES_PULSEr <= {SNES_PULSEr[6:0], SNES_PULSE_IN};
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[6] <= SNES_PAr[5];
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
// count of write low
if (SNES_reset_strobe | SNES_SNOOPPAWR_end) begin
SNES_SNOOPPAWR_count <= 0;
SNES_SNOOPPAWR_DATA_OE <= 0;
end
else if (SNES_PAWR_start_early) begin
SNES_SNOOPPAWR_count <= 1;
SNES_SNOOPPAWR_DATA_OE <= 1;
end
else if (|SNES_SNOOPPAWR_count) begin
SNES_SNOOPPAWR_count <= SNES_SNOOPPAWR_count + 1;
end
// count of write low
if (SNES_reset_strobe | SNES_SNOOPPARD_end) begin
SNES_SNOOPPARD_count <= 0;
SNES_SNOOPPARD_DATA_OE <= 0;
end
// avoid triggering OE signals on 213f to avoid problem with region override
// do not sniff external B-bus (>=$2184, e.g. Satellaview)
else if (SNES_PARD_start & ~r213f_enable & (SNES_PA < 8'h84)) begin
SNES_SNOOPPARD_count <= 1;
SNES_SNOOPPARD_DATA_OE <= 1;
end
else if (|SNES_SNOOPPARD_count) begin
SNES_SNOOPPARD_count <= SNES_SNOOPPARD_count + 1;
end
// count of write low
if (SNES_reset_strobe | SNES_SNOOPWR_end) begin
SNES_SNOOPWR_count <= 0;
SNES_SNOOPWR_DATA_OE <= 0;
end
else if (SNES_WR_start) begin
SNES_SNOOPWR_count <= 1;
SNES_SNOOPWR_DATA_OE <= 1;
end
else if (|SNES_SNOOPWR_count) begin
SNES_SNOOPWR_count <= SNES_SNOOPWR_count + 1;
end
// count of write low
if (SNES_reset_strobe | SNES_SNOOPRD_end) begin
SNES_SNOOPRD_count <= 0;
SNES_SNOOPRD_DATA_OE <= 0;
end
else if (SNES_RD_start_early) begin
SNES_SNOOPRD_count <= 1;
SNES_SNOOPRD_DATA_OE <= 1;
end
else if (|SNES_SNOOPRD_count) begin
SNES_SNOOPRD_count <= SNES_SNOOPRD_count + 1;
end
end
parameter ST_IDLE = 11'b00000000001;
parameter ST_MCU_RD_ADDR = 11'b00000000010;
parameter ST_MCU_RD_END = 11'b00000000100;
parameter ST_MCU_WR_ADDR = 11'b00000001000;
parameter ST_MCU_WR_END = 11'b00000010000;
parameter ST_CTX_WR_ADDR = 11'b00000100000;
parameter ST_CTX_WR_END = 11'b00001000000;
parameter ST_DMA_RD_ADDR = 11'b00010000000;
parameter ST_DMA_RD_END = 11'b00100000000;
parameter ST_DMA_WR_ADDR = 11'b01000000000;
parameter ST_DMA_WR_END = 11'b10000000000;
parameter SNES_DEAD_TIMEOUT = 17'd96000; // 1ms
parameter ROM_CYCLE_LEN = 4'd7;
reg [10:0] STATE;
initial STATE = ST_IDLE;
assign SRTC_SNES_DATA_IN = BUS_DATA[3:0];
assign MSU_SNES_DATA_IN = BUS_DATA;
assign DMA_SNES_DATA_IN = BUS_DATA;
assign BSX_SNES_DATA_IN = BUS_DATA;
assign CTX_SNES_DATA_IN = CTX_DIRr ? CTX_DINr : SNES_DATAr[0];
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
assign SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset),
.dac_address_ext(dac_ptr_addr)
);
srtc snes_srtc (
.clkin(CLK2),
.addr_in(SNES_ADDR[0]),
.data_in(SRTC_SNES_DATA_IN),
.data_out(SRTC_SNES_DATA_OUT),
.rtc_data_in(rtc_data),
.enable(srtc_enable),
.rtc_data_out(srtc_rtc_data_out),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.rtc_we(srtc_rtc_we),
.reset(srtc_reset),
.srtc_state(DBG_srtc_state),
.srtc_reg_we_rising(DBG_srtc_we_rising),
.srtc_rtc_ptr(DBG_srtc_ptr),
.srtc_we_sreg(DBG_srtc_we_sreg)
);
rtc snes_rtc (
.clkin(CLKIN),
.rtc_data(rtc_data),
.rtc_data_in(rtc_data_in),
.pgm_we(rtc_pgm_we),
.rtc_data_in1(srtc_rtc_data_out),
.we1(srtc_rtc_we)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
wire [23:0] CTX_ADDR;
wire [15:0] CTX_DOUT;
ctx snes_ctx (
.clkin(CLK2),
.reset(SNES_reset_strobe),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_RD_end_PRE(SNES_RD_end),
.SNES_WR_end_PRE(SNES_SNOOPWR_end),
.SNES_PARD_end_PRE(SNES_SNOOPPARD_end),
.SNES_PAWR_end_PRE(SNES_SNOOPPAWR_end),
.SNES_DATA_IN_PRE(CTX_SNES_DATA_IN), // needs to handle PA accesses, too
//.OE_RD_ENABLE(ctx_rd_enable),
.OE_WR_ENABLE(ctx_wr_enable),
.OE_PAWR_ENABLE(ctx_pawr_enable),
.OE_PARD_ENABLE(ctx_pard_enable),
.BUS_WRQ(CTX_WRQ),
.BUS_RDY(CTX_RDY),
.snescmd_unlock(snescmd_unlock),
.ROM_ADDR(CTX_ADDR),
.ROM_DATA(CTX_DOUT),
.ROM_WORD_ENABLE(CTX_WORD),
.DBG(CTX_DBG)
);
wire [23:0] DMA_ADDR;
wire [15:0] DMA_DOUT;
reg [15:0] DMA_DINr;
dma snes_dma (
.clkin(CLK2),
.reset(SNES_reset_strobe),
.enable(dma_enable),
.reg_addr(SNES_ADDR[3:0]),
.reg_data_in(DMA_SNES_DATA_IN),
.reg_data_out(DMA_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_we_rising(SNES_WR_end),
.loop_enable(DMA_LOOP_ENABLE),
.BUS_RDY(DMA_RDY),
.BUS_RRQ(DMA_RRQ),
.BUS_WRQ(DMA_WRQ),
.ROM_ADDR(DMA_ADDR),
.ROM_DATA_OUT(DMA_DOUT),
.ROM_DATA_IN(DMA_DINr),
.ROM_WORD_ENABLE(DMA_WORD)
);
bsx snes_bsx(
.clkin(CLK2),
.use_bsx(use_bsx),
.pgm_we(bsx_regs_reset_we),
.snes_addr_in(SNES_ADDR),
.reg_data_in(BSX_SNES_DATA_IN),
.reg_data_out(BSX_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.regs_out(bsx_regs),
.reg_reset_bits(bsx_regs_reset_bits),
.reg_set_bits(bsx_regs_set_bits),
.data_ovr(bsx_data_ovr),
.flash_writable(IS_FLASHWR),
.rtc_data_in(rtc_data[59:0]),
.bs_page_out(bs_page), // support only page 0000-03ff
.bs_page_enable(bs_page_enable),
.bs_page_offset(bs_page_offset),
.feat_bs_base_enable(feat_bs_base_enable)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_base_out(SAVERAM_BASE),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.dac_ptr_out(dac_ptr_addr),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.reg_group_out(reg_group),
.reg_index_out(reg_index),
.reg_value_out(reg_value),
.reg_invmask_out(reg_invmask),
.reg_we_out(reg_we),
.reg_read_out(reg_read),
//.trc_config_data_in(trc_config_data),
.bsx_regs_set_out(bsx_regs_set_bits),
.bsx_regs_reset_out(bsx_regs_reset_bits),
.bsx_regs_reset_we(bsx_regs_reset_we),
.rtc_data_out(rtc_data_in),
.rtc_pgm_we(rtc_pgm_we),
.srtc_reset(srtc_reset),
.featurebits_out(featurebits),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR_early(SNES_ADDR_early), // requested address from SNES
.SNES_WRITE_early(SNES_WRITE_early),
.SNES_PA(SNES_PA),
.SNES_ROMSEL(SNES_ROMSEL),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT), // want to access RAM0
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.IS_PATCH(IS_PATCH),
.SAVERAM_BASE(SAVERAM_BASE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
.map_unlock(map_unlock),
.map_Ex_rd_unlock(map_Ex_rd_unlock_r),
.map_Ex_wr_unlock(map_Ex_wr_unlock_r),
.map_Fx_rd_unlock(map_Fx_rd_unlock_r),
.map_Fx_wr_unlock(map_Fx_wr_unlock_r),
.snescmd_unlock(snescmd_unlock),
//MSU-1
.msu_enable(msu_enable),
//DMA-1
.dma_enable(dma_enable),
//BS-X
.use_bsx(use_bsx),
.bsx_regs(bsx_regs),
.bs_page_offset(bs_page_offset),
.bs_page(bs_page),
.bs_page_enable(bs_page_enable),
.bsx_tristate(bsx_tristate),
//SRTC
.srtc_enable(srtc_enable),
.r213f_enable(r213f_enable),
.r2100_hit(r2100_hit),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.branch3_enable(branch3_enable),
.exe_enable(exe_enable),
.map_enable(map_enable)
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.branch3_enable(branch3_enable),
.exe_present(exe_present),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.SNES_cycle_start(SNES_cycle_start),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.feat_cmd_unlock_in(feat_cmd_unlock),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock),
.map_unlock(map_unlock)
);
wire [7:0] snescmd_dout;
parameter ST_R213F_ARMED = 4'b0001;
parameter ST_R213F_WAITBUS = 4'b0010;
parameter ST_R213F_OVERRIDE = 4'b0100;
parameter ST_R213F_HOLD = 4'b1000;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [3:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 1;
initial r213f_state = ST_R213F_ARMED;
initial r213f_delay = 3'b001;
reg [7:0] r2100r = 0;
reg r2100_forcewrite = 0;
reg r2100_forcewrite_pre = 0;
wire [3:0] r2100_limit = featurebits[10:7];
wire [3:0] r2100_limited = (SNES_DATA[3:0] > r2100_limit) ? r2100_limit : SNES_DATA[3:0];
wire r2100_patch = featurebits[6];
wire r2100_enable = r2100_hit & (r2100_patch | ~(&r2100_limit));
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
r2100_forcewrite <= r2100_forcewrite_pre;
end
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
assign SNES_DATA = (r213f_enable & ~SNES_PARD) ? (r213f_forceread ? 8'bZ : r213fr)
:(r2100_enable & ~SNES_PAWR & r2100_forcewrite) ? r2100r
:(((~SNES_READ & ((~SNES_SNOOPPAWR_DATA_OE & ~SNES_SNOOPPARD_DATA_OE) | ~SNES_ROMSEL_EARLY)))
& ~(r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE))
? (srtc_enable ? SRTC_SNES_DATA_OUT
:msu_enable ? MSU_SNES_DATA_OUT
:dma_enable ? DMA_SNES_DATA_OUT
:(bsx_data_ovr & ~IS_PATCH) ? BSX_SNES_DATA_OUT
:(cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
// put spinloop below cheat so we don't overwrite jmp target after NMI
:loop_enable ? loop_data
:((snescmd_unlock | feat_cmd_unlock | map_snescmd_rd_unlock_r) & snescmd_enable) ? snescmd_dout
:(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
// CTX
reg CTX_WR_PENDr;
initial CTX_WR_PENDr = 0;
reg [23:0] CTX_ROM_ADDRr;
initial CTX_ROM_ADDRr = 24'h0;
reg [15:0] CTX_ROM_DATAr;
initial CTX_ROM_DATAr = 16'h0000;
reg CTX_ROM_WORDr;
initial CTX_ROM_WORDr = 1'b0;
// DMA
reg DMA_WR_PENDr;
initial DMA_WR_PENDr = 0;
reg DMA_RD_PENDr;
initial DMA_RD_PENDr = 0;
reg [23:0] DMA_ROM_ADDRr;
initial DMA_ROM_ADDRr = 24'h0;
reg [15:0] DMA_ROM_DATAr;
initial DMA_ROM_DATAr = 16'h0000;
reg DMA_ROM_WORDr;
initial DMA_ROM_WORDr = 1'b0;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
// CTX
reg RQ_CTX_RDYr;
initial RQ_CTX_RDYr = 1'b1;
assign CTX_RDY = RQ_CTX_RDYr;
// DMA
reg RQ_DMA_RDYr;
initial RQ_DMA_RDYr = 1'b1;
assign DMA_RDY = RQ_DMA_RDYr;
wire MCU_WE_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_WR_HIT = |(STATE & (ST_MCU_WR_ADDR | ST_MCU_WR_END));
wire MCU_RD_HIT = |(STATE & (ST_MCU_RD_ADDR | ST_MCU_RD_END));
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
// CTX
wire CTX_WE_HIT = |(STATE & ST_CTX_WR_ADDR);
wire CTX_WR_HIT = |(STATE & (ST_CTX_WR_ADDR | ST_CTX_WR_END));
wire CTX_HIT = CTX_WR_HIT;
// DMA
wire DMA_WE_HIT = |(STATE & ST_DMA_WR_ADDR);
wire DMA_WR_HIT = |(STATE & (ST_DMA_WR_ADDR | ST_DMA_WR_END));
wire DMA_RD_HIT = |(STATE & (ST_DMA_RD_ADDR | ST_DMA_RD_END));
wire DMA_HIT = DMA_WR_HIT | DMA_RD_HIT;
`ifdef MK2
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST)
);
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : CTX_HIT ? CTX_ROM_ADDRr[23:1] : DMA_HIT ? DMA_ROM_ADDRr[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : CTX_HIT ? CTX_ROM_ADDRr[0] : DMA_HIT ? DMA_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
//always @(posedge CLK2) ROM_ADDR_PRE <= (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : CTX_HIT ? CTX_ROM_ADDRr[23:1] : DMA_HIT ? DMA_ROM_ADDRr[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
//always @(posedge CLK2) ROM_ADDR0_PRE <= (SD_DMA_TO_ROM) ? MCU_ADDR[0] : CTX_HIT ? CTX_ROM_ADDRr[0] : DMA_HIT ? DMA_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_CE = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock | map_snescmd_wr_unlock_r) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[9:0]), // input [9 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [9 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
`ifdef MK3
pll snes_pll(
.inclk0(CLKIN),
.c0(CLK2),
// .c1(CLK192),
.locked(DCM_LOCKED),
.areset(DCM_RST)
);
wire ROM_ADDR22;
assign ROM_ADDR22 = (SD_DMA_TO_ROM) ? MCU_ADDR[1] : CTX_HIT ? CTX_ROM_ADDRr[1] : DMA_HIT ? DMA_ROM_ADDRr[1] : MCU_HIT ? ROM_ADDRr[1] : MAPPED_SNES_ADDR[1];
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:2] : CTX_HIT ? CTX_ROM_ADDRr[23:2] : DMA_HIT ? DMA_ROM_ADDRr[23:2] : MCU_HIT ? ROM_ADDRr[23:2] : MAPPED_SNES_ADDR[23:2];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : CTX_HIT ? CTX_ROM_ADDRr[0] : DMA_HIT ? DMA_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_ZZ = 1'b1;
assign ROM_1CE = ROM_ADDR22;
assign ROM_2CE = ~ROM_ADDR22;
snescmd_buf snescmd (
.clock(CLK2), // input clka
.wren_a(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock | map_snescmd_wr_unlock_r) & snescmd_enable)), // input [0 : 0] wea
.address_a(SNES_ADDR[9:0]), // input [8 : 0] addra
.data_a(SNES_DATA), // input [7 : 0] dina
.q_a(snescmd_dout), // output [7 : 0] douta
.wren_b(snescmd_we_mcu), // input [0 : 0] web
.address_b(snescmd_addr_mcu), // input [9 : 0] addrb
.data_b(snescmd_data_out_mcu), // input [7 : 0] dinb
.q_b(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
// context engine request
always @(posedge CLK2) begin
if(CTX_WRQ) begin
CTX_WR_PENDr <= 1'b1;
RQ_CTX_RDYr <= 1'b0;
CTX_ROM_ADDRr <= CTX_ADDR;
CTX_ROM_DATAr <= CTX_DOUT;
CTX_ROM_WORDr <= CTX_WORD;
end
else if(STATE & ST_CTX_WR_END) begin
CTX_WR_PENDr <= 1'b0;
RQ_CTX_RDYr <= 1'b1;
end
end
// MCU r/w request
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
// dma engine request
always @(posedge CLK2) begin
if(DMA_RRQ) begin
DMA_RD_PENDr <= 1'b1;
RQ_DMA_RDYr <= 1'b0;
DMA_ROM_ADDRr <= DMA_ADDR;
DMA_ROM_WORDr <= DMA_WORD;
end
else if(DMA_WRQ) begin
DMA_WR_PENDr <= 1'b1;
RQ_DMA_RDYr <= 1'b0;
DMA_ROM_ADDRr <= DMA_ADDR;
DMA_ROM_DATAr <= DMA_DOUT;
DMA_ROM_WORDr <= DMA_WORD;
end
else if(STATE & (ST_DMA_RD_END | ST_DMA_WR_END)) begin
DMA_RD_PENDr <= 1'b0;
DMA_WR_PENDr <= 1'b0;
RQ_DMA_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 18'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
CTX_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
CTX_DIRr <= SNES_DATABUS_DIR;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(free_slot | SNES_DEADr) begin
if(CTX_WR_PENDr) begin
STATE <= ST_CTX_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(DMA_RD_PENDr) begin
STATE <= ST_DMA_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(DMA_WR_PENDr) begin
STATE <= ST_DMA_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_CTX_WR_ADDR: begin
STATE <= ST_CTX_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_CTX_WR_END;
end
ST_DMA_RD_ADDR: begin
STATE <= ST_DMA_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_DMA_RD_END;
// FIXME: seems like the lower byte is the upper byte (BIG ENDIAN)? Maybe a bug in the DMA addressing logic.
DMA_DINr <= (ROM_ADDR0 ? ROM_DATA : {ROM_DATA[7:0],ROM_DATA[15:8]});
end
ST_DMA_WR_ADDR: begin
STATE <= ST_DMA_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_DMA_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END, ST_CTX_WR_END, ST_DMA_RD_END, ST_DMA_WR_END: begin
STATE <= ST_IDLE;
end
endcase
end
/***********************
* R213F read patching *
***********************/
always @(posedge CLK2) begin
case(r213f_state)
ST_R213F_HOLD: begin
r213f_state <= ST_R213F_HOLD;
if(SNES_PULSE_end) begin
r213f_forceread <= 1'b1;
r213f_state <= ST_R213F_ARMED;
end
end
ST_R213F_ARMED: begin
r213f_state <= ST_R213F_ARMED;
if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b001;
r213f_state <= ST_R213F_WAITBUS;
end
end
ST_R213F_WAITBUS: begin
r213f_state <= ST_R213F_WAITBUS;
r213f_delay <= r213f_delay - 1;
if(r213f_delay == 3'b000) begin
r213f_state <= ST_R213F_OVERRIDE;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
end
end
ST_R213F_OVERRIDE: begin
r213f_state <= ST_R213F_HOLD;
r213f_forceread <= 1'b0;
end
endcase
end
/*********************************
* R2100 patching (experimental) *
*********************************/
reg [3:0] r2100_bright = 0;
reg [3:0] r2100_bright_orig = 0;
always @(posedge CLK2) begin
if(SNES_PULSE_end) r2100_forcewrite_pre <= 1'b0;
else if(SNES_PAWR_start & r2100_hit) begin
if(r2100_patch & SNES_DATA[7]) begin
// keep previous brightness during forced blanking so there is no DAC step
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b010, r2100_bright}; // 0xAx
end else if (r2100_patch && SNES_DATA == 8'h00 && r2100r[7]) begin
// extend forced blanking when game goes from blanking to brightness 0 (Star Fox top of screen)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {1'b1, 3'b111, r2100_bright}; // 0xFx
end else if (r2100_patch && SNES_DATA[3:0] < 4'h8 && r2100_bright_orig > 4'hd) begin
// substitute big brightness changes with brightness 0 (so it is visible on 1CHIP)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b011, 4'h0}; // 0x3x / 0xBx(!)
end else if (r2100_patch | ~(&r2100_limit)) begin
// save brightness, limit brightness
r2100_bright <= r2100_limited;
r2100_bright_orig <= SNES_DATA[3:0];
if (~(&r2100_limit) && SNES_DATA[3:0] > r2100_limit) begin
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b100, r2100_limited}; // 0x4x / 0xCx
end
end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) begin
MCU_WRITE_1<= MCU_WRITE;
end
assign ROM_DATA[7:0] = (ROM_ADDR0 || (!SD_DMA_TO_ROM && CTX_HIT && CTX_ROM_WORDr) || (!SD_DMA_TO_ROM && DMA_HIT && DMA_ROM_WORDr))
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: CTX_WR_HIT ? CTX_ROM_DATAr[15:8]
: DMA_WR_HIT ? DMA_ROM_DATAr[15:8]
: (ROM_HIT & ~loop_enable & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: CTX_WR_HIT ? CTX_ROM_DATAr[7:0]
: DMA_WR_HIT ? DMA_ROM_DATAr[7:0]
: (ROM_HIT & ~loop_enable & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
? MCU_WRITE
: CTX_WE_HIT ? 1'b0
: DMA_WE_HIT ? 1'b0
: (ROM_HIT & ~loop_enable & (IS_WRITABLE | IS_FLASHWR) & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WE_HIT ? 1'b0
: 1'b1;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = ~ROM_ADDR0 & ~(~SD_DMA_TO_ROM & CTX_HIT & CTX_ROM_WORDr) & ~(~SD_DMA_TO_ROM & DMA_HIT & DMA_ROM_WORDr);
reg ReadOrWrite_r; always @(posedge CLK2) ReadOrWrite_r <= ~(SNES_READr[1] & SNES_READr[0] & SNES_WRITEr[1] & SNES_WRITEr[0]);
assign SNES_DATABUS_OE = (msu_enable & ReadOrWrite_r) ? 1'b0 :
(dma_enable & ReadOrWrite_r) ? 1'b0 :
(loop_enable & ~SNES_READ_narrow) ? 1'b0 :
(bsx_data_ovr & ~IS_PATCH & ReadOrWrite_r) ? 1'b0 :
(srtc_enable & ReadOrWrite_r) ? 1'b0 :
(snescmd_enable & ReadOrWrite_r) ? (~(snescmd_unlock | feat_cmd_unlock | (map_snescmd_wr_unlock_r & ~SNES_WRITE) | (map_snescmd_rd_unlock_r & ~SNES_READ_narrow))) :
(bs_page_enable & ~SNES_READ_narrow) ? 1'b0 :
(r213f_enable & ~SNES_PARD) ? 1'b0 :
(r2100_enable & ~SNES_PAWR) ? 1'b0 :
(snoop_4200_enable & ~SNES_WRITE) ? 1'b0 :
(ctx_wr_enable & SNES_SNOOPWR_DATA_OE) ? 1'b0 :
(ctx_pawr_enable & SNES_SNOOPPAWR_DATA_OE)? 1'b0 :
(ctx_pard_enable & SNES_SNOOPPARD_DATA_OE)? 1'b0 :
((IS_ROM & SNES_ROMSEL)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE & !IS_FLASHWR)
|(SNES_READ_narrow & SNES_WRITE)
| bsx_tristate
);
/* data bus direction: 0 = SNES -> FPGA; 1 = FPGA -> SNES
* data bus is always SNES -> FPGA to avoid fighting except when:
* a) the SNES wants to read
* b) we want to force a value on the bus
*/
assign SNES_DATABUS_DIR = ((~SNES_READ & ((~SNES_SNOOPPAWR_DATA_OE & ~SNES_SNOOPPARD_DATA_OE) | ROM_HIT)) | (~SNES_PARD & (r213f_enable)))
? (1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
^ (r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE))
: ((~SNES_PAWR & r2100_enable) ? r2100_forcewrite
: 1'b0);
assign SNES_IRQ = 1'b0;
// Detect writes and handle dynamic NMI hook and address map unlock registers.
reg snescmd_addr_exe_r; always @(posedge CLK2) snescmd_addr_exe_r <= {2'b11,snescmd_addr_mcu} == 12'hC00;
reg snescmd_addr_map_r; always @(posedge CLK2) snescmd_addr_map_r <= {2'b10,snescmd_addr_mcu} == 12'hBB2;
always @(posedge CLK2) begin
// dynamic NMI hook enable/disable detected on writes to $2C00 from either SNES or MCU
if (SNES_WR_end & (snescmd_unlock | feat_cmd_unlock | map_snescmd_wr_unlock_r) & exe_enable) exe_present <= (SNES_DATA != 0) ? 1 : 0;
// snescmd_addr_mcu is 10 bits. $2C00 is inteleaved with $2A00 such that $2C00 comes first at 0
else if (snescmd_we_mcu & snescmd_addr_exe_r) exe_present <= (snescmd_data_out_mcu != 0) ? 1 : 0;
// address map unlock detected on writes from either SNES or MCU
if (SNES_WR_end & (snescmd_unlock | feat_cmd_unlock | map_snescmd_wr_unlock_r) & map_enable) {map_Fx_rd_unlock_r,map_Fx_wr_unlock_r,map_Ex_rd_unlock_r,map_Ex_wr_unlock_r,map_snescmd_rd_unlock_r,map_snescmd_wr_unlock_r} <= SNES_DATA;
else if (snescmd_we_mcu & snescmd_addr_map_r) {map_Fx_rd_unlock_r,map_Fx_wr_unlock_r,map_Ex_rd_unlock_r,map_Ex_wr_unlock_r,map_snescmd_rd_unlock_r,map_snescmd_wr_unlock_r} <= snescmd_data_out_mcu;
end
// spin loop state machine
// This is used to put the SNES into a spin loop. It replaces the current instruction fetch with a branch
// to itself. Upon release it lets the SNES fetch. Currently, it's only used to increase DMA bandwidth
reg loop_state;
initial loop_state = 0;
parameter [`upper(2):0] loop_code = { 8'h80, 8'hFE }; // BRA $FE
always @(posedge CLK2) begin
if (!loop_enable) begin
loop_enable <= DMA_LOOP_ENABLE;
end
else begin
case (loop_state)
0: begin
if (SNES_RD_end) begin
loop_state <= 1;
loop_data <= loop_code[`upper(0):`lower(0)];
end
end
1: begin
if (SNES_RD_end) begin
loop_state <= 0;
loop_data <= loop_code[`upper(1):`lower(1)];
loop_enable <= DMA_LOOP_ENABLE;
end
end
endcase
end
end
`ifdef MK2_DEBUG
wire [35:0] CONTROL;
wire [7:0] TRIG0w = {
SNES_READ_IN,
SNES_WRITE_IN,
SNES_CPU_CLK_IN,
SNES_READ,
SNES_WRITE,
SNES_CPU_CLK,
SNES_DATABUS_OE,
SNES_DATABUS_DIR
};
wire [31:0] TRIG1w = {
SNES_ADDR_IN,
SNES_DATA_IN
};
wire [40:0] TRIG2w = {
SNES_ADDR,
SNES_DATA,
BUS_DATA
};
wire [3:0] TRIG3w = {
SNES_cycle_start,
SNES_RD_start,
SNES_RD_end,
SNES_WR_end
};
wire [25:0] TRIG4w = {
ROM_WE,
ROM_BHE,
ROM_BLE,
ROM_ADDR
};
reg [7:0] TRIG0;
reg [31:0] TRIG1;
reg [40:0] TRIG2;
reg [3:0] TRIG3;
reg [25:0] TRIG4;
always @(posedge CLK2) begin
TRIG0 <= TRIG0w;
TRIG1 <= TRIG1w;
TRIG2 <= TRIG2w;
TRIG3 <= TRIG3w;
TRIG4 <= TRIG4w;
end
chipscope_icon snes_icon (
.CONTROL0(CONTROL) // INOUT BUS [35:0]
);
chipscope_ila snes_ila (
.CONTROL(CONTROL), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(TRIG0), // IN BUS [7:0]
.TRIG1(TRIG1), // IN BUS [31:0]
.TRIG2(TRIG2), // IN BUS [39:0]
.TRIG3(TRIG3), // IN BUS [3:0]
.TRIG4(TRIG4) // IN BUS [25:0]
);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_2_V
`define SKY130_FD_SC_LS__CLKBUF_2_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_2_V
|
/***************************************************************************************************
** fpga_nes/hw/src/ppu/ppu_bg.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Background/playfield PPU sub-block.
***************************************************************************************************/
`timescale 1ps / 1ps
module ppu_bg
(
input wire clk_in, // 100MHz system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable background
input wire ls_clip_in, // clip background in left 8 pixels
input wire [ 2:0] fv_in, // fine vertical scroll reg value
input wire [ 4:0] vt_in, // vertical tile scroll reg value
input wire v_in, // vertical name table selection reg value
input wire [ 2:0] fh_in, // fine horizontal scroll reg value
input wire [ 4:0] ht_in, // horizontal tile scroll reg value
input wire h_in, // horizontal name table selection reg value
input wire s_in, // playfield pattern table selection reg value
input wire [ 9:0] nes_x_in, // nes x coordinate
input wire [ 9:0] nes_y_in, // nes y coordinate
input wire [ 9:0] nes_y_next_in, // next line's nes y coordinate
input wire pix_pulse_in, // pulse signal one clock immediately before nes x changes
input wire [ 7:0] vram_d_in, // vram data input bus
input wire ri_upd_cntrs_in, // update counters from scroll regs (after 0x2006 write)
input wire ri_inc_addr_in, // increment scroll regs for 0x2007 ri access
input wire ri_inc_addr_amt_in, // amount to inc addr on ri_inc_addr_in (1 or 32 bytes)
output reg [13:0] vram_a_out, // vram address bus for bg or ri 0x2007 access
output wire [ 3:0] palette_idx_out // background palette idx for the current pixel
);
//
// Background registers.
//
reg [ 2:0] q_fvc, d_fvc; // fine vertical scroll counter
reg [ 4:0] q_vtc, d_vtc; // vertical tile index counter
reg q_vc, d_vc; // vertical name table selection counter
reg [ 4:0] q_htc, d_htc; // horizontal tile index counter
reg q_hc, d_hc; // horizontal name table selection counter
reg [ 7:0] q_par, d_par; // picture address register (holds tile index)
reg [ 1:0] q_ar, d_ar; // tile attribute value latch (bits 3 and 2)
reg [ 7:0] q_pd0, d_pd0; // palette data 0 (bit 0 for tile)
reg [ 7:0] q_pd1, d_pd1; // palette data 1 (bit 1 for tile)
reg [ 8:0] q_bg_bit3_shift, d_bg_bit3_shift; // shift register with per-pixel bg palette idx bit 3
reg [ 8:0] q_bg_bit2_shift, d_bg_bit2_shift; // shift register with per-pixel bg palette idx bit 2
reg [15:0] q_bg_bit1_shift, d_bg_bit1_shift; // shift register with per-pixel bg palette idx bit 1
reg [15:0] q_bg_bit0_shift, d_bg_bit0_shift; // shift register with per-pixel bg palette idx bit 0
always @(posedge clk_in)
begin
if (rst_in)
begin
q_fvc <= 2'h0;
q_vtc <= 5'h00;
q_vc <= 1'h0;
q_htc <= 5'h00;
q_hc <= 1'h0;
q_par <= 8'h00;
q_ar <= 2'h0;
q_pd0 <= 8'h00;
q_pd1 <= 8'h00;
q_bg_bit3_shift <= 9'h000;
q_bg_bit2_shift <= 9'h000;
q_bg_bit1_shift <= 16'h0000;
q_bg_bit0_shift <= 16'h0000;
end
else
begin
q_fvc <= d_fvc;
q_vtc <= d_vtc;
q_vc <= d_vc;
q_htc <= d_htc;
q_hc <= d_hc;
q_par <= d_par;
q_ar <= d_ar;
q_pd0 <= d_pd0;
q_pd1 <= d_pd1;
q_bg_bit3_shift <= d_bg_bit3_shift;
q_bg_bit2_shift <= d_bg_bit2_shift;
q_bg_bit1_shift <= d_bg_bit1_shift;
q_bg_bit0_shift <= d_bg_bit0_shift;
end
end
//
// Scroll counter management.
//
reg upd_v_cntrs;
reg upd_h_cntrs;
reg inc_v_cntrs;
reg inc_h_cntrs;
always @*
begin
// Default to original values.
d_fvc = q_fvc;
d_vc = q_vc;
d_hc = q_hc;
d_vtc = q_vtc;
d_htc = q_htc;
if (ri_inc_addr_in)
begin
// If the VRAM address increment bit (2000.2) is clear (inc. amt. = 1), all the scroll
// counters are daisy-chained (in the order of HT, VT, H, V, FV) so that the carry out of
// each counter controls the next counter's clock rate. The result is that all 5 counters
// function as a single 15-bit one. Any access to 2007 clocks the HT counter here.
//
// If the VRAM address increment bit is set (inc. amt. = 32), the only difference is that
// the HT counter is no longer being clocked, and the VT counter is now being clocked by
// access to 2007.
if (ri_inc_addr_amt_in)
{ d_fvc, d_vc, d_hc, d_vtc } = { q_fvc, q_vc, q_hc, q_vtc } + 10'h001;
else
{ d_fvc, d_vc, d_hc, d_vtc, d_htc } = { q_fvc, q_vc, q_hc, q_vtc, q_htc } + 15'h0001;
end
else
begin
if (inc_v_cntrs)
begin
// The vertical scroll counter is 9 bits, and is made up by daisy-chaining FV to VT, and
// VT to V. FV is clocked by the PPU's horizontal blanking impulse, and therefore will
// increment every scanline. VT operates here as a divide-by-30 counter, and will only
// generate a carry condition when the count increments from 29 to 30 (the counter will
// also reset). Dividing by 30 is neccessary to prevent attribute data in the name
// tables from being used as tile index data.
if ({ q_vtc, q_fvc } == { 5'b1_1101, 3'b111 })
{ d_vc, d_vtc, d_fvc } = { ~q_vc, 8'h00 };
else
{ d_vc, d_vtc, d_fvc } = { q_vc, q_vtc, q_fvc } + 9'h001;
end
if (inc_h_cntrs)
begin
// The horizontal scroll counter consists of 6 bits, and is made up by daisy-chaining the
// HT counter to the H counter. The HT counter is then clocked every 8 pixel dot clocks
// (or every 8/3 CPU clock cycles).
{ d_hc, d_htc } = { q_hc, q_htc } + 6'h01;
end
// Counter loading. There are 2 conditions that update all 5 PPU scroll counters with the
// contents of the latches adjacent to them. The first is after a write to 2006/2. The
// second, is at the beginning of scanline 20, when the PPU starts rendering data for the
// first time in a frame (this update won't happen if all rendering is disabled via 2001.3
// and 2001.4).
//
// There is one condition that updates the H & HT counters, and that is at the end of the
// horizontal blanking period of a scanline. Again, image rendering must be occuring for
// this update to be effective.
if (upd_v_cntrs || ri_upd_cntrs_in)
begin
d_vc = v_in;
d_vtc = vt_in;
d_fvc = fv_in;
end
if (upd_h_cntrs || ri_upd_cntrs_in)
begin
d_hc = h_in;
d_htc = ht_in;
end
end
end
//
// VRAM address derivation logic.
//
localparam [2:0] VRAM_A_SEL_RI = 3'h0,
VRAM_A_SEL_NT_READ = 3'h1,
VRAM_A_SEL_AT_READ = 3'h2,
VRAM_A_SEL_PT0_READ = 3'h3,
VRAM_A_SEL_PT1_READ = 3'h4;
reg [2:0] vram_a_sel;
always @*
begin
case (vram_a_sel)
VRAM_A_SEL_NT_READ:
vram_a_out = { 2'b10, q_vc, q_hc, q_vtc, q_htc };
VRAM_A_SEL_AT_READ:
vram_a_out = { 2'b10, q_vc, q_hc, 4'b1111, q_vtc[4:2], q_htc[4:2] };
VRAM_A_SEL_PT0_READ:
vram_a_out = { 1'b0, s_in, q_par, 1'b0, q_fvc };
VRAM_A_SEL_PT1_READ:
vram_a_out = { 1'b0, s_in, q_par, 1'b1, q_fvc };
default:
vram_a_out = { q_fvc[1:0], q_vc, q_hc, q_vtc, q_htc };
endcase
end
//
// Background palette index derivation logic.
//
wire clip;
always @*
begin
// Default to original value.
d_par = q_par;
d_ar = q_ar;
d_pd0 = q_pd0;
d_pd1 = q_pd1;
d_bg_bit3_shift = q_bg_bit3_shift;
d_bg_bit2_shift = q_bg_bit2_shift;
d_bg_bit1_shift = q_bg_bit1_shift;
d_bg_bit0_shift = q_bg_bit0_shift;
upd_v_cntrs = 1'b0;
inc_v_cntrs = 1'b0;
upd_h_cntrs = 1'b0;
inc_h_cntrs = 1'b0;
vram_a_sel = VRAM_A_SEL_RI;
if (en_in && ((nes_y_in < 239) || (nes_y_next_in == 0)))
begin
if (pix_pulse_in && (nes_x_in == 319))
begin
upd_h_cntrs = 1'b1;
if (nes_y_next_in != nes_y_in)
begin
if (nes_y_next_in == 0)
upd_v_cntrs = 1'b1;
else
inc_v_cntrs = 1'b1;
end
end
if ((nes_x_in < 256) || ((nes_x_in >= 320 && nes_x_in < 336)))
begin
if (pix_pulse_in)
begin
d_bg_bit3_shift = { q_bg_bit3_shift[8], q_bg_bit3_shift[8:1] };
d_bg_bit2_shift = { q_bg_bit2_shift[8], q_bg_bit2_shift[8:1] };
d_bg_bit1_shift = { 1'b0, q_bg_bit1_shift[15:1] };
d_bg_bit0_shift = { 1'b0, q_bg_bit0_shift[15:1] };
end
if (pix_pulse_in && (nes_x_in[2:0] == 3'h7))
begin
inc_h_cntrs = 1'b1;
d_bg_bit3_shift[8] = q_ar[1];
d_bg_bit2_shift[8] = q_ar[0];
d_bg_bit1_shift[15] = q_pd1[0];
d_bg_bit1_shift[14] = q_pd1[1];
d_bg_bit1_shift[13] = q_pd1[2];
d_bg_bit1_shift[12] = q_pd1[3];
d_bg_bit1_shift[11] = q_pd1[4];
d_bg_bit1_shift[10] = q_pd1[5];
d_bg_bit1_shift[ 9] = q_pd1[6];
d_bg_bit1_shift[ 8] = q_pd1[7];
d_bg_bit0_shift[15] = q_pd0[0];
d_bg_bit0_shift[14] = q_pd0[1];
d_bg_bit0_shift[13] = q_pd0[2];
d_bg_bit0_shift[12] = q_pd0[3];
d_bg_bit0_shift[11] = q_pd0[4];
d_bg_bit0_shift[10] = q_pd0[5];
d_bg_bit0_shift[ 9] = q_pd0[6];
d_bg_bit0_shift[ 8] = q_pd0[7];
end
case (nes_x_in[2:0])
3'b000:
begin
vram_a_sel = VRAM_A_SEL_NT_READ;
d_par = vram_d_in;
end
3'b001:
begin
vram_a_sel = VRAM_A_SEL_AT_READ;
d_ar = vram_d_in >> { q_vtc[1], q_htc[1], 1'b0 };
end
3'b010:
begin
vram_a_sel = VRAM_A_SEL_PT0_READ;
d_pd0 = vram_d_in;
end
3'b011:
begin
vram_a_sel = VRAM_A_SEL_PT1_READ;
d_pd1 = vram_d_in;
end
endcase
end
end
end
assign clip = ls_clip_in && (nes_x_in >= 10'h000) && (nes_x_in < 10'h008);
assign palette_idx_out = (!clip && en_in) ? { q_bg_bit3_shift[fh_in],
q_bg_bit2_shift[fh_in],
q_bg_bit1_shift[fh_in],
q_bg_bit0_shift[fh_in] } : 4'h0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_21_V
`define SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_21_V
/**
* sleep_pargate_plv: ????.
*
* Verilog wrapper for sleep_pargate_plv with size of 21 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_pargate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_21 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_pargate_plv_21 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_pargate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_21_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_TB_V
`define SKY130_FD_SC_HVL__NAND2_TB_V
/**
* nand2: 2-input NAND.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__nand2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__nand2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 09 23:35:45 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_xbar_0_stub.v
// Design : design_1_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[95:0],m_axi_awprot[8:0],m_axi_awvalid[2:0],m_axi_awready[2:0],m_axi_wdata[95:0],m_axi_wstrb[11:0],m_axi_wvalid[2:0],m_axi_wready[2:0],m_axi_bresp[5:0],m_axi_bvalid[2:0],m_axi_bready[2:0],m_axi_araddr[95:0],m_axi_arprot[8:0],m_axi_arvalid[2:0],m_axi_arready[2:0],m_axi_rdata[95:0],m_axi_rresp[5:0],m_axi_rvalid[2:0],m_axi_rready[2:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [95:0]m_axi_awaddr;
output [8:0]m_axi_awprot;
output [2:0]m_axi_awvalid;
input [2:0]m_axi_awready;
output [95:0]m_axi_wdata;
output [11:0]m_axi_wstrb;
output [2:0]m_axi_wvalid;
input [2:0]m_axi_wready;
input [5:0]m_axi_bresp;
input [2:0]m_axi_bvalid;
output [2:0]m_axi_bready;
output [95:0]m_axi_araddr;
output [8:0]m_axi_arprot;
output [2:0]m_axi_arvalid;
input [2:0]m_axi_arready;
input [95:0]m_axi_rdata;
input [5:0]m_axi_rresp;
input [2:0]m_axi_rvalid;
output [2:0]m_axi_rready;
endmodule
|
//#############################################################################
//# Function: Clock mux #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockmux #(parameter N = 1) // number of clock inputs
(
input [N-1:0] en, // one hot enable vector (needs to be stable!)
input [N-1:0] clkin,// one hot clock inputs (only one is active!)
output clkout
);
localparam ASIC = `CFG_ASIC;
generate
if(ASIC& (N==2))
begin : asic
asic_clockmux2 imux (.clkin(clkin[N-1:0]),
.en(en[N-1:0]),
.clkout(clkout));
end
else if(ASIC & (N==4))
begin : asic
asic_clockmux4 imux (.clkin(clkin[N-1:0]),
.en(en[N-1:0]),
.clkout(clkout));
end
else
begin : generic
assign clkout = |(clkin[N-1:0] & en[N-1:0]);
end
endgenerate
endmodule // oh_clockmux
|
// ======================================================================
// Buttons.v generated from TopDesign.cysch
// 12/10/2014 at 17:59
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 17
// TCPWM_P4_v1_10(PWMCompare=1500, PWMCompareBuf=65535, PWMCompareSwap=0, PWMCountMode=3, PWMCountPresent=false, PWMDeadTimeCycle=0, PWMInterruptMask=1, PWMKillEvent=0, PWMLinenSignal=0, PWMLineSignal=0, PWMMode=4, PWMPeriod=20000, PWMPeriodBuf=65535, PWMPeriodSwap=0, PWMPrescaler=0, PWMReloadMode=0, PWMReloadPresent=false, PWMRunMode=0, PWMSetAlign=0, PWMStartMode=0, PWMStartPresent=false, PWMStopEvent=0, PWMStopMode=0, PWMStopPresent=false, PWMSwitchMode=0, PWMSwitchPresent=false, QuadEncodingModes=0, QuadIndexMode=0, QuadIndexPresent=false, QuadInterruptMask=1, QuadPhiAMode=3, QuadPhiBMode=3, QuadStopMode=0, QuadStopPresent=false, TCCaptureMode=0, TCCapturePresent=false, TCCompare=65535, TCCompareBuf=65535, TCCompareSwap=0, TCCompCapMode=2, TCCountingModes=1, TCCountMode=3, TCCountPresent=false, TCInterruptMask=1, TCPeriod=1000, TCPrescaler=0, TCPWMCapturePresent=false, TCPWMConfig=1, TCPWMCountPresent=false, TCPWMReloadPresent=false, TCPWMStartPresent=false, TCPWMStopPresent=false, TCReloadMode=0, TCReloadPresent=false, TCRunMode=0, TCStartMode=0, TCStartPresent=false, TCStopMode=0, TCStopPresent=false, CY_COMPONENT_NAME=TCPWM_P4_v1_10, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=Timer1, CY_INSTANCE_SHORT_NAME=Timer1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=Timer1, )
module TCPWM_P4_v1_10_0 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
// TCPWM_P4_v1_10(PWMCompare=1500, PWMCompareBuf=65535, PWMCompareSwap=0, PWMCountMode=3, PWMCountPresent=false, PWMDeadTimeCycle=0, PWMInterruptMask=0, PWMKillEvent=0, PWMLinenSignal=0, PWMLineSignal=0, PWMMode=4, PWMPeriod=20000, PWMPeriodBuf=65535, PWMPeriodSwap=0, PWMPrescaler=0, PWMReloadMode=0, PWMReloadPresent=false, PWMRunMode=0, PWMSetAlign=0, PWMStartMode=0, PWMStartPresent=false, PWMStopEvent=0, PWMStopMode=0, PWMStopPresent=false, PWMSwitchMode=0, PWMSwitchPresent=false, QuadEncodingModes=0, QuadIndexMode=0, QuadIndexPresent=false, QuadInterruptMask=1, QuadPhiAMode=3, QuadPhiBMode=3, QuadStopMode=0, QuadStopPresent=false, TCCaptureMode=0, TCCapturePresent=false, TCCompare=65535, TCCompareBuf=65535, TCCompareSwap=0, TCCompCapMode=2, TCCountingModes=0, TCCountMode=3, TCCountPresent=false, TCInterruptMask=1, TCPeriod=65535, TCPrescaler=0, TCPWMCapturePresent=false, TCPWMConfig=7, TCPWMCountPresent=false, TCPWMReloadPresent=false, TCPWMStartPresent=false, TCPWMStopPresent=false, TCReloadMode=0, TCReloadPresent=false, TCRunMode=0, TCStartMode=0, TCStartPresent=false, TCStopMode=0, TCStopPresent=false, CY_COMPONENT_NAME=TCPWM_P4_v1_10, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=PWM_Servo, CY_INSTANCE_SHORT_NAME=PWM_Servo, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=PWM_Servo, )
module TCPWM_P4_v1_10_1 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
parameter PWMCountMode = 3;
parameter PWMReloadMode = 0;
parameter PWMReloadPresent = 0;
parameter PWMStartMode = 0;
parameter PWMStopMode = 0;
parameter PWMSwitchMode = 0;
parameter QuadIndexMode = 0;
parameter QuadPhiAMode = 3;
parameter QuadPhiBMode = 3;
parameter QuadStopMode = 0;
parameter TCCaptureMode = 0;
parameter TCCountMode = 3;
parameter TCReloadMode = 0;
parameter TCStartMode = 0;
parameter TCStopMode = 0;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(capture),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(count),
.reload(reload),
.stop(stop),
.start(start),
.clock(clock));
endmodule
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// SCB_P4_v1_20(BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=true, DBGW_SCB_IP_V1=false, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cClkFreqDes=1600, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=100, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSubAddressSize=0, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cClkFreqDes=1600, I2cClockFromTerm=false, I2cDataRate=100, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cWakeEnable=false, PinName0Unconfig=spi_mosi_i2c_scl_uart_rx, PinName1Unconfig=spi_miso_i2c_sda_uart_tx, RemoveI2cPins=true, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=true, RemoveSpiMasterPins=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartRxPin=false, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=false, ScbClkFreqDes=1382.4, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=true, ScbMisoSdaTxEnable=true, ScbMode=4, ScbModeHw=2, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiInterruptMode=0, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxTriggerLevel=0, SpiWakeEnable=false, UartClkFreqDes=1382.4, UartClockFromTerm=false, UartDataRate=115200, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=2, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=true, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=12, UartParityType=2, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=4, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxTriggerLevel=0, UartWakeEnable=false, CY_COMPONENT_NAME=SCB_P4_v1_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=UART_1, CY_INSTANCE_SHORT_NAME=UART_1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=UART_1, )
module SCB_P4_v1_20_2 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("723379629.62963"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_379;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
tx
(.oe(tmpOE__tx_net),
.y({Net_656}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_379}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 2;
endmodule
// top
module top ;
wire Net_163;
wire Net_162;
wire Net_161;
wire Net_154;
wire Net_139;
wire Net_153;
wire Net_137;
wire Net_152;
wire Net_151;
wire Net_150;
wire Net_149;
wire Net_148;
wire Net_147;
wire Net_146;
wire Net_145;
wire Net_144;
wire Net_69;
wire Net_102;
wire Net_101;
wire Net_100;
wire Net_99;
wire Net_98;
wire Net_87;
wire Net_97;
wire Net_96;
wire Net_95;
wire Net_94;
wire Net_93;
wire Net_104;
wire Net_68;
wire Net_46;
wire [0:0] tmpOE__Btn0_net;
wire [0:0] tmpFB_0__Btn0_net;
wire [0:0] tmpIO_0__Btn0_net;
electrical [0:0] tmpSIOVREF__Btn0_net;
cy_psoc3_pins_v1_10
#(.id("552faf00-97dc-47bf-ad14-15574b2c6e9b"),
.drive_mode(3'b010),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b10),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
Btn0
(.oe(tmpOE__Btn0_net),
.y({1'b0}),
.fb({tmpFB_0__Btn0_net[0:0]}),
.io({tmpIO_0__Btn0_net[0:0]}),
.siovref(tmpSIOVREF__Btn0_net),
.interrupt({Net_46}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Btn0_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__LED_net;
wire [0:0] tmpFB_0__LED_net;
wire [0:0] tmpIO_0__LED_net;
wire [0:0] tmpINTERRUPT_0__LED_net;
electrical [0:0] tmpSIOVREF__LED_net;
cy_psoc3_pins_v1_10
#(.id("b0f37199-6c06-4e0a-98e7-b2170ef91497"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
LED
(.oe(tmpOE__LED_net),
.y({1'b0}),
.fb({tmpFB_0__LED_net[0:0]}),
.io({tmpIO_0__LED_net[0:0]}),
.siovref(tmpSIOVREF__LED_net),
.interrupt({tmpINTERRUPT_0__LED_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Btn1_net;
wire [0:0] tmpFB_0__Btn1_net;
wire [0:0] tmpIO_0__Btn1_net;
electrical [0:0] tmpSIOVREF__Btn1_net;
cy_psoc3_pins_v1_10
#(.id("bab6a988-52aa-4376-a76e-7dbb3ddd8f50"),
.drive_mode(3'b010),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b10),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
Btn1
(.oe(tmpOE__Btn1_net),
.y({1'b0}),
.fb({tmpFB_0__Btn1_net[0:0]}),
.io({tmpIO_0__Btn1_net[0:0]}),
.siovref(tmpSIOVREF__Btn1_net),
.interrupt({Net_104}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Btn1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
TCPWM_P4_v1_10_0 Timer1 (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_87),
.ov(Net_98),
.un(Net_99),
.cc(Net_100),
.line(Net_101),
.line_n(Net_102),
.clock(Net_68));
defparam Timer1.PWMCountMode = 3;
defparam Timer1.PWMReloadMode = 0;
defparam Timer1.PWMReloadPresent = 0;
defparam Timer1.PWMStartMode = 0;
defparam Timer1.PWMStopMode = 0;
defparam Timer1.PWMSwitchMode = 0;
defparam Timer1.QuadIndexMode = 0;
defparam Timer1.QuadPhiAMode = 3;
defparam Timer1.QuadPhiBMode = 3;
defparam Timer1.QuadStopMode = 0;
defparam Timer1.TCCaptureMode = 0;
defparam Timer1.TCCountMode = 3;
defparam Timer1.TCReloadMode = 0;
defparam Timer1.TCStartMode = 0;
defparam Timer1.TCStopMode = 0;
cy_clock_v1_0
#(.id("c4d993e1-c103-4e85-b1df-bc9c6402cfed"),
.source_clock_id(""),
.divisor(0),
.period("1000000000"),
.is_direct(0),
.is_digital(0))
Clock_1
(.clock_out(Net_68));
cy_isr_v1_0
#(.int_type(2'b10))
ISR_Btn0
(.int_signal(Net_46));
cy_isr_v1_0
#(.int_type(2'b10))
ISR_Timer1
(.int_signal(Net_87));
wire [0:0] tmpOE__LED1_net;
wire [0:0] tmpFB_0__LED1_net;
wire [0:0] tmpIO_0__LED1_net;
wire [0:0] tmpINTERRUPT_0__LED1_net;
electrical [0:0] tmpSIOVREF__LED1_net;
cy_psoc3_pins_v1_10
#(.id("0e0c9380-6965-4440-8709-ce08a91e474c"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
LED1
(.oe(tmpOE__LED1_net),
.y({1'b0}),
.fb({tmpFB_0__LED1_net[0:0]}),
.io({tmpIO_0__LED1_net[0:0]}),
.siovref(tmpSIOVREF__LED1_net),
.interrupt({tmpINTERRUPT_0__LED1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
ISR_Bnt1
(.int_signal(Net_104));
TCPWM_P4_v1_10_1 PWM_Servo (
.stop(1'b0),
.reload(1'b0),
.start(1'b0),
.count(1'b1),
.capture(1'b0),
.interrupt(Net_149),
.ov(Net_150),
.un(Net_151),
.cc(Net_152),
.line(Net_137),
.line_n(Net_153),
.clock(Net_139));
defparam PWM_Servo.PWMCountMode = 3;
defparam PWM_Servo.PWMReloadMode = 0;
defparam PWM_Servo.PWMReloadPresent = 0;
defparam PWM_Servo.PWMStartMode = 0;
defparam PWM_Servo.PWMStopMode = 0;
defparam PWM_Servo.PWMSwitchMode = 0;
defparam PWM_Servo.QuadIndexMode = 0;
defparam PWM_Servo.QuadPhiAMode = 3;
defparam PWM_Servo.QuadPhiBMode = 3;
defparam PWM_Servo.QuadStopMode = 0;
defparam PWM_Servo.TCCaptureMode = 0;
defparam PWM_Servo.TCCountMode = 3;
defparam PWM_Servo.TCReloadMode = 0;
defparam PWM_Servo.TCStartMode = 0;
defparam PWM_Servo.TCStopMode = 0;
cy_clock_v1_0
#(.id("2f98ca16-0407-4eeb-a907-2282a5b81a79"),
.source_clock_id(""),
.divisor(0),
.period("1000000000"),
.is_direct(0),
.is_digital(0))
Clock_2
(.clock_out(Net_139));
wire [0:0] tmpOE__Servo_1_net;
wire [0:0] tmpFB_0__Servo_1_net;
wire [0:0] tmpIO_0__Servo_1_net;
wire [0:0] tmpINTERRUPT_0__Servo_1_net;
electrical [0:0] tmpSIOVREF__Servo_1_net;
cy_psoc3_pins_v1_10
#(.id("e4e9a0b1-0370-4889-90ef-76026e833f55"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Servo_1
(.oe(tmpOE__Servo_1_net),
.y({Net_137}),
.fb({tmpFB_0__Servo_1_net[0:0]}),
.io({tmpIO_0__Servo_1_net[0:0]}),
.siovref(tmpSIOVREF__Servo_1_net),
.interrupt({tmpINTERRUPT_0__Servo_1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Servo_1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
SCB_P4_v1_20_2 UART_1 (
.sclk(Net_161),
.interrupt(Net_162),
.clock(1'b0));
cy_isr_v1_0
#(.int_type(2'b10))
ISR_UART_Rx
(.int_signal(Net_162));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_PP_BLACKBOX_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s6s (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns //Use a timescale that is best for simulation.
//------------------------------------------------------------------------------
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------
module axi_ad7091(/*autoport*/
//output
// physical
adc_sclk_o,
adc_cnv_o,
adc_cs_n_o,
// master-slave
adc_start_o,
dma_start_o,
// dma
s_axis_s2mm_tvalid,
s_axis_s2mm_tdata,
s_axis_s2mm_tlast,
s_axis_s2mm_tkeep,
// axi
s_axi_awready,
s_axi_wready,
s_axi_bvalid,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_bresp,
s_axi_rresp,
// monitor/debug
adc_mon_trig_o,
adc_mon_data_o,
//input
// clocks
ref_clk_i,
rx_clk_i,
//physical
adc_sdo_i,
// master-slave
adc_start_i,
dma_start_i,
// dma
s_axis_s2mm_clk,
s_axis_s2mm_tready,
// axi
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_wvalid,
s_axi_wdata,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_rready,
s_axi_wstrb
);
// core parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// physical interface
input ref_clk_i;
input rx_clk_i;
input adc_sdo_i;
output adc_sclk_o;
output adc_cnv_o;
output adc_cs_n_o;
// master-slave interface
output adc_start_o;
output dma_start_o;
input adc_start_i;
input dma_start_i;
// DMA interface
input s_axis_s2mm_clk;
output s_axis_s2mm_tvalid;
output [31:0] s_axis_s2mm_tdata;
output [ 3:0] s_axis_s2mm_tkeep;
output s_axis_s2mm_tlast;
input s_axis_s2mm_tready;
// AXI interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output [7:0] adc_mon_trig_o;
output [31:0] adc_mon_data_o;
// register input/outputs
reg adc_start_o;
// internal clock and reset
wire dma_clk_s;
wire up_rstn_s;
wire up_clk_s;
wire adc_rst_s;
wire adc_clk;
// internal signals
wire data_rd_ready_s;
wire [15:0] adc_data_s;
wire adc_status_s;
wire adc_start_s;
wire [31:0] pid_s;
wire dma_start_s;
wire [31:0] dma_data_s;
wire dma_valid_s;
wire dma_last_s;
wire dma_ovf_s;
wire dma_unf_s;
wire dma_status_s;
wire [31:0] dma_bw_s;
wire dma_rst_s;
wire dma_ready_s;
wire dma_stream_s;
wire [31:0] dma_count_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
// registers
reg adc_valid = 0;
reg [31:0] adc_data = 32'b0;
reg [31:0] up_rdata = 32'b0;
reg up_ack = 1'b0;
// signal assignments
assign dma_clk_s = s_axis_s2mm_clk;
assign dma_ready_s = s_axis_s2mm_tready;
assign up_clk_s = s_axi_aclk;
assign up_rstn_s = s_axi_aresetn;
assign s_axis_s2mm_tvalid = dma_valid_s;
assign s_axis_s2mm_tdata = dma_data_s;
assign s_axis_s2mm_tlast = dma_last_s;
assign s_axis_s2mm_tkeep = 4'hf;
assign adc_clk = s_axi_aclk;
// monitor / debug signals
assign adc_mon_trig_o = {4'h0, dma_clk_s, dma_start_s, s_axi_aclk, data_rd_ready_s};
assign adc_mon_data_o[15: 0] = adc_data[15:0];
assign adc_mon_data_o[31:16] = 16'h0;
// multiple instances synchronization
assign pid_s = 32'd0;
assign adc_start_s = (pid_s == 32'd0) ? adc_start_o : adc_start_i;
assign dma_start_s = (pid_s == 32'd0) ? dma_start_o : dma_start_i;
always @(posedge adc_clk) begin
if (adc_rst_s == 1'b1) begin
adc_start_o <= 1'b0;
end else begin
adc_start_o <= 1'b1;
end
end
// adc channels - dma interface
always @(posedge adc_clk)
begin
adc_valid <= data_rd_ready_s;
adc_data <= { 16'h0, adc_data_s };
end
// processor read interface
always @(negedge up_rstn_s or posedge up_clk_s) begin
if (up_rstn_s == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_adc_common_rdata_s;
up_ack <= up_adc_common_ack_s;
end
end
// device interface instance
axi_ad7091_dev_if #(
.ADC_DATAREADY_WIDTH (1)
) axi_ad7091_dev_if_inst(/*autoinst*/
.data_o(adc_data_s),
.data_rd_ready_o(data_rd_ready_s),
.adc_sclk_o(adc_sclk_o),
.adc_cs_n_o(adc_cs_n_o),
.adc_convst_n_o(adc_cnv_o),
.fpga_clk_i(ref_clk_i),
.adc_clk_i(rx_clk_i),
.reset_i(adc_rst_s),
.adc_sdo_i(adc_sdo_i),
.adc_status_o(adc_status_s)
);
// DMA transfer instance
dma_core #(
.DATA_WIDTH (32)
) dma_core_inst(/*autoinst*/
.dma_valid(dma_valid_s),
.dma_last(dma_last_s),
.dma_data(dma_data_s),
.dma_ovf(dma_ovf_s),
.dma_unf(dma_unf_s),
.dma_status(dma_status_s),
.dma_bw(dma_bw_s),
.dma_clk(dma_clk_s),
.dma_rst(dma_rst_s),
.dma_ready(dma_ready_s),
.adc_clk(adc_clk),
.adc_rst(adc_rst_s),
.adc_valid(adc_valid),
.adc_data(adc_data),
.dma_start(dma_start_s),
.dma_stream(dma_stream_s),
.dma_count(dma_count_s));
// common processor control
up_adc_common up_adc_common_inst(/*autoinst*/
.mmcm_rst(),
.delay_clk(1'b0),
.delay_ack_t(),
.delay_locked(),
.delay_rst(),
.delay_sel(),
.delay_rwn(),
.delay_addr(),
.delay_wdata(),
.delay_rdata(5'b0),
.adc_rst(adc_rst_s),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_clk(adc_clk),
.adc_status(adc_status_s),
.adc_status_pn_err(),
.adc_status_pn_oos(),
.adc_status_or(),
.adc_clk_ratio(32'b1),
.drp_clk(1'b0),
.drp_rdata(16'b0),
.drp_ack_t(1'b0),
.drp_rst(),
.drp_sel(),
.drp_wr(),
.drp_addr(),
.drp_wdata(),
.dma_rst(dma_rst_s),
.dma_start(dma_start_o),
.dma_stream(dma_stream_s),
.dma_count(dma_count_s),
.dma_clk(dma_clk_s),
.dma_ovf(dma_ovf_s),
.dma_unf(dma_unf_s),
.dma_status(dma_status_s),
.dma_bw(dma_bw_s),
.up_rstn(up_rstn_s),
.up_clk(up_clk_s),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rdata(up_adc_common_rdata_s),
.up_ack(up_adc_common_ack_s),
.up_usr_chanmax(),
.adc_usr_chanmax(8'b0)
);
// AXI wrapper instance
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
up_axi_inst(/*autoinst*/
.up_axi_awready(s_axi_awready),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rdata(s_axi_rdata),
.up_sel(up_sel_s),
.up_wr(up_wr_s),
.up_addr(up_addr_s),
.up_wdata(up_wdata_s),
.up_rstn(up_rstn_s),
.up_clk(up_clk_s),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_rready(s_axi_rready),
.up_rdata(up_rdata),
.up_ack(up_ack),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_bresp(s_axi_bresp),
.up_axi_rresp(s_axi_rresp));
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(* This file is (C) Copyright 2006-2015 Microsoft Corporation and Inria. *)
Require Bool.
Require Import ssreflect ssrfun.
(******************************************************************************)
(* A theory of boolean predicates and operators. A large part of this file is *)
(* concerned with boolean reflection. *)
(* Definitions and notations: *)
(* is_true b == the coercion of b : bool to Prop (:= b = true). *)
(* This is just input and displayed as `b''. *)
(* reflect P b == the reflection inductive predicate, asserting *)
(* that the logical proposition P : prop with the *)
(* formula b : bool. Lemmas asserting reflect P b *)
(* are often referred to as "views". *)
(* iffP, appP, sameP, rwP :: lemmas for direct manipulation of reflection *)
(* views: iffP is used to prove reflection from *)
(* logical equivalence, appP to compose views, and *)
(* sameP and rwP to perform boolean and setoid *)
(* rewriting. *)
(* elimT :: coercion reflect >-> Funclass, which allows the *)
(* direct application of `reflect' views to *)
(* boolean assertions. *)
(* decidable P <-> P is effectively decidable (:= {P} + {~ P}. *)
(* contra, contraL, ... :: contraposition lemmas. *)
(* altP my_viewP :: natural alternative for reflection; given *)
(* lemma myviewP: reflect my_Prop my_formula, *)
(* have [myP | not_myP] := altP my_viewP. *)
(* generates two subgoals, in which my_formula has *)
(* been replaced by true and false, resp., with *)
(* new assumptions myP : my_Prop and *)
(* not_myP: ~~ my_formula. *)
(* Caveat: my_formula must be an APPLICATION, not *)
(* a variable, constant, let-in, etc. (due to the *)
(* poor behaviour of dependent index matching). *)
(* boolP my_formula :: boolean disjunction, equivalent to *)
(* altP (idP my_formula) but circumventing the *)
(* dependent index capture issue; destructing *)
(* boolP my_formula generates two subgoals with *)
(* assumtions my_formula and ~~ myformula. As *)
(* with altP, my_formula must be an application. *)
(* \unless C, P <-> we can assume property P when a something that *)
(* holds under condition C (such as C itself). *)
(* := forall G : Prop, (C -> G) -> (P -> G) -> G. *)
(* This is just C \/ P or rather its impredicative *)
(* encoding, whose usage better fits the above *)
(* description: given a lemma UCP whose conclusion *)
(* is \unless C, P we can assume P by writing: *)
(* wlog hP: / P by apply/UCP; (prove C -> goal). *)
(* or even apply: UCP id _ => hP if the goal is C. *)
(* classically P <-> we can assume P when proving is_true b. *)
(* := forall b : bool, (P -> b) -> b. *)
(* This is equivalent to ~ (~ P) when P : Prop. *)
(* implies P Q == wrapper coinductive type that coerces to P -> Q *)
(* and can be used as a P -> Q view unambigously. *)
(* Useful to avoid spurious insertion of <-> views *)
(* when Q is a conjunction of foralls, as in Lemma *)
(* all_and2 below; conversely, avoids confusion in *)
(* apply views for impredicative properties, such *)
(* as \unless C, P. Also supports contrapositives. *)
(* a && b == the boolean conjunction of a and b. *)
(* a || b == the boolean disjunction of a and b. *)
(* a ==> b == the boolean implication of b by a. *)
(* ~~ a == the boolean negation of a. *)
(* a (+) b == the boolean exclusive or (or sum) of a and b. *)
(* [ /\ P1 , P2 & P3 ] == multiway logical conjunction, up to 5 terms. *)
(* [ \/ P1 , P2 | P3 ] == multiway logical disjunction, up to 4 terms. *)
(* [&& a, b, c & d] == iterated, right associative boolean conjunction *)
(* with arbitrary arity. *)
(* [|| a, b, c | d] == iterated, right associative boolean disjunction *)
(* with arbitrary arity. *)
(* [==> a, b, c => d] == iterated, right associative boolean implication *)
(* with arbitrary arity. *)
(* and3P, ... == specific reflection lemmas for iterated *)
(* connectives. *)
(* andTb, orbAC, ... == systematic names for boolean connective *)
(* properties (see suffix conventions below). *)
(* prop_congr == a tactic to move a boolean equality from *)
(* its coerced form in Prop to the equality *)
(* in bool. *)
(* bool_congr == resolution tactic for blindly weeding out *)
(* like terms from boolean equalities (can fail). *)
(* This file provides a theory of boolean predicates and relations: *)
(* pred T == the type of bool predicates (:= T -> bool). *)
(* simpl_pred T == the type of simplifying bool predicates, using *)
(* the simpl_fun from ssrfun.v. *)
(* rel T == the type of bool relations. *)
(* := T -> pred T or T -> T -> bool. *)
(* simpl_rel T == type of simplifying relations. *)
(* predType == the generic predicate interface, supported for *)
(* for lists and sets. *)
(* pred_class == a coercion class for the predType projection to *)
(* pred; declaring a coercion to pred_class is an *)
(* alternative way of equipping a type with a *)
(* predType structure, which interoperates better *)
(* with coercion subtyping. This is used, e.g., *)
(* for finite sets, so that finite groups inherit *)
(* the membership operation by coercing to sets. *)
(* If P is a predicate the proposition "x satisfies P" can be written *)
(* applicatively as (P x), or using an explicit connective as (x \in P); in *)
(* the latter case we say that P is a "collective" predicate. We use A, B *)
(* rather than P, Q for collective predicates: *)
(* x \in A == x satisfies the (collective) predicate A. *)
(* x \notin A == x doesn't satisfy the (collective) predicate A. *)
(* The pred T type can be used as a generic predicate type for either kind, *)
(* but the two kinds of predicates should not be confused. When a "generic" *)
(* pred T value of one type needs to be passed as the other the following *)
(* conversions should be used explicitly: *)
(* SimplPred P == a (simplifying) applicative equivalent of P. *)
(* mem A == an applicative equivalent of A: *)
(* mem A x simplifies to x \in A. *)
(* Alternatively one can use the syntax for explicit simplifying predicates *)
(* and relations (in the following x is bound in E): *)
(* [pred x | E] == simplifying (see ssrfun) predicate x => E. *)
(* [pred x : T | E] == predicate x => E, with a cast on the argument. *)
(* [pred : T | P] == constant predicate P on type T. *)
(* [pred x | E1 & E2] == [pred x | E1 && E2]; an x : T cast is allowed. *)
(* [pred x in A] == [pred x | x in A]. *)
(* [pred x in A | E] == [pred x | x in A & E]. *)
(* [pred x in A | E1 & E2] == [pred x in A | E1 && E2]. *)
(* [predU A & B] == union of two collective predicates A and B. *)
(* [predI A & B] == intersection of collective predicates A and B. *)
(* [predD A & B] == difference of collective predicates A and B. *)
(* [predC A] == complement of the collective predicate A. *)
(* [preim f of A] == preimage under f of the collective predicate A. *)
(* predU P Q, ... == union, etc of applicative predicates. *)
(* pred0 == the empty predicate. *)
(* predT == the total (always true) predicate. *)
(* if T : predArgType, then T coerces to predT. *)
(* {: T} == T cast to predArgType (e.g., {: bool * nat}) *)
(* In the following, x and y are bound in E: *)
(* [rel x y | E] == simplifying relation x, y => E. *)
(* [rel x y : T | E] == simplifying relation with arguments cast. *)
(* [rel x y in A & B | E] == [rel x y | [&& x \in A, y \in B & E]]. *)
(* [rel x y in A & B] == [rel x y | (x \in A) && (y \in B)]. *)
(* [rel x y in A | E] == [rel x y in A & A | E]. *)
(* [rel x y in A] == [rel x y in A & A]. *)
(* relU R S == union of relations R and S. *)
(* Explicit values of type pred T (i.e., lamdba terms) should always be used *)
(* applicatively, while values of collection types implementing the predType *)
(* interface, such as sequences or sets should always be used as collective *)
(* predicates. Defined constants and functions of type pred T or simpl_pred T *)
(* as well as the explicit simpl_pred T values described below, can generally *)
(* be used either way. Note however that x \in A will not auto-simplify when *)
(* A is an explicit simpl_pred T value; the generic simplification rule inE *)
(* must be used (when A : pred T, the unfold_in rule can be used). Constants *)
(* of type pred T with an explicit simpl_pred value do not auto-simplify when *)
(* used applicatively, but can still be expanded with inE. This behavior can *)
(* be controlled as follows: *)
(* Let A : collective_pred T := [pred x | ... ]. *)
(* The collective_pred T type is just an alias for pred T, but this cast *)
(* stops rewrite inE from expanding the definition of A, thus treating A *)
(* into an abstract collection (unfold_in or in_collective can be used to *)
(* expand manually). *)
(* Let A : applicative_pred T := [pred x | ...]. *)
(* This cast causes inE to turn x \in A into the applicative A x form; *)
(* A will then have to unfolded explicitly with the /A rule. This will *)
(* also apply to any definition that reduces to A (e.g., Let B := A). *)
(* Canonical A_app_pred := ApplicativePred A. *)
(* This declaration, given after definition of A, similarly causes inE to *)
(* turn x \in A into A x, but in addition allows the app_predE rule to *)
(* turn A x back into x \in A; it can be used for any definition of type *)
(* pred T, which makes it especially useful for ambivalent predicates *)
(* as the relational transitive closure connect, that are used in both *)
(* applicative and collective styles. *)
(* Purely for aesthetics, we provide a subtype of collective predicates: *)
(* qualifier q T == a pred T pretty-printing wrapper. An A : qualifier q T *)
(* coerces to pred_class and thus behaves as a collective *)
(* predicate, but x \in A and x \notin A are displayed as: *)
(* x \is A and x \isn't A when q = 0, *)
(* x \is a A and x \isn't a A when q = 1, *)
(* x \is an A and x \isn't an A when q = 2, respectively. *)
(* [qualify x | P] := Qualifier 0 (fun x => P), constructor for the above. *)
(* [qualify x : T | P], [qualify a x | P], [qualify an X | P], etc. *)
(* variants of the above with type constraints and different *)
(* values of q. *)
(* We provide an internal interface to support attaching properties (such as *)
(* being multiplicative) to predicates: *)
(* pred_key p == phantom type that will serve as a support for properties *)
(* to be attached to p : pred_class; instances should be *)
(* created with Fact/Qed so as to be opaque. *)
(* KeyedPred k_p == an instance of the interface structure that attaches *)
(* (k_p : pred_key P) to P; the structure projection is a *)
(* coercion to pred_class. *)
(* KeyedQualifier k_q == an instance of the interface structure that attaches *)
(* (k_q : pred_key q) to (q : qualifier n T). *)
(* DefaultPredKey p == a default value for pred_key p; the vernacular command *)
(* Import DefaultKeying attaches this key to all predicates *)
(* that are not explicitly keyed. *)
(* Keys can be used to attach properties to predicates, qualifiers and *)
(* generic nouns in a way that allows them to be used transparently. The key *)
(* projection of a predicate property structure such as unsignedPred should *)
(* be a pred_key, not a pred, and corresponding lemmas will have the form *)
(* Lemma rpredN R S (oppS : @opprPred R S) (kS : keyed_pred oppS) : *)
(* {mono -%R: x / x \in kS}. *)
(* Because x \in kS will be displayed as x \in S (or x \is S, etc), the *)
(* canonical instance of opprPred will not normally be exposed (it will also *)
(* be erased by /= simplification). In addition each predicate structure *)
(* should have a DefaultPredKey Canonical instance that simply issues the *)
(* property as a proof obligation (which can be caught by the Prop-irrelevant *)
(* feature of the ssreflect plugin). *)
(* Some properties of predicates and relations: *)
(* A =i B <-> A and B are extensionally equivalent. *)
(* {subset A <= B} <-> A is a (collective) subpredicate of B. *)
(* subpred P Q <-> P is an (applicative) subpredicate or Q. *)
(* subrel R S <-> R is a subrelation of S. *)
(* In the following R is in rel T: *)
(* reflexive R <-> R is reflexive. *)
(* irreflexive R <-> R is irreflexive. *)
(* symmetric R <-> R (in rel T) is symmetric (equation). *)
(* pre_symmetric R <-> R is symmetric (implication). *)
(* antisymmetric R <-> R is antisymmetric. *)
(* total R <-> R is total. *)
(* transitive R <-> R is transitive. *)
(* left_transitive R <-> R is a congruence on its left hand side. *)
(* right_transitive R <-> R is a congruence on its right hand side. *)
(* equivalence_rel R <-> R is an equivalence relation. *)
(* Localization of (Prop) predicates; if P1 is convertible to forall x, Qx, *)
(* P2 to forall x y, Qxy and P3 to forall x y z, Qxyz : *)
(* {for y, P1} <-> Qx{y / x}. *)
(* {in A, P1} <-> forall x, x \in A -> Qx. *)
(* {in A1 & A2, P2} <-> forall x y, x \in A1 -> y \in A2 -> Qxy. *)
(* {in A &, P2} <-> forall x y, x \in A -> y \in A -> Qxy. *)
(* {in A1 & A2 & A3, Q3} <-> forall x y z, *)
(* x \in A1 -> y \in A2 -> z \in A3 -> Qxyz. *)
(* {in A1 & A2 &, Q3} == {in A1 & A2 & A2, Q3}. *)
(* {in A1 && A3, Q3} == {in A1 & A1 & A3, Q3}. *)
(* {in A &&, Q3} == {in A & A & A, Q3}. *)
(* {in A, bijective f} == f has a right inverse in A. *)
(* {on C, P1} == forall x, (f x) \in C -> Qx *)
(* when P1 is also convertible to Pf f. *)
(* {on C &, P2} == forall x y, f x \in C -> f y \in C -> Qxy *)
(* when P2 is also convertible to Pf f. *)
(* {on C, P1' & g} == forall x, (f x) \in cd -> Qx *)
(* when P1' is convertible to Pf f *)
(* and P1' g is convertible to forall x, Qx. *)
(* {on C, bijective f} == f has a right inverse on C. *)
(* This file extends the lemma name suffix conventions of ssrfun as follows: *)
(* A -- associativity, as in andbA : associative andb. *)
(* AC -- right commutativity. *)
(* ACA -- self-interchange (inner commutativity), e.g., *)
(* orbACA : (a || b) || (c || d) = (a || c) || (b || d). *)
(* b -- a boolean argument, as in andbb : idempotent andb. *)
(* C -- commutativity, as in andbC : commutative andb, *)
(* or predicate complement, as in predC. *)
(* CA -- left commutativity. *)
(* D -- predicate difference, as in predD. *)
(* E -- elimination, as in negbFE : ~~ b = false -> b. *)
(* F or f -- boolean false, as in andbF : b && false = false. *)
(* I -- left/right injectivity, as in addbI : right_injective addb, *)
(* or predicate intersection, as in predI. *)
(* l -- a left-hand operation, as andb_orl : left_distributive andb orb. *)
(* N or n -- boolean negation, as in andbN : a && (~~ a) = false. *)
(* P -- a characteristic property, often a reflection lemma, as in *)
(* andP : reflect (a /\ b) (a && b). *)
(* r -- a right-hand operation, as orb_andr : rightt_distributive orb andb. *)
(* T or t -- boolean truth, as in andbT: right_id true andb. *)
(* U -- predicate union, as in predU. *)
(* W -- weakening, as in in1W : {in D, forall x, P} -> forall x, P. *)
(******************************************************************************)
Set Implicit Arguments.
Unset Strict Implicit.
Unset Printing Implicit Defensive.
Set Warnings "-projection-no-head-constant".
Notation reflect := Bool.reflect.
Notation ReflectT := Bool.ReflectT.
Notation ReflectF := Bool.ReflectF.
Reserved Notation "~~ b" (at level 35, right associativity).
Reserved Notation "b ==> c" (at level 55, right associativity).
Reserved Notation "b1 (+) b2" (at level 50, left associativity).
Reserved Notation "x \in A"
(at level 70, format "'[hv' x '/ ' \in A ']'", no associativity).
Reserved Notation "x \notin A"
(at level 70, format "'[hv' x '/ ' \notin A ']'", no associativity).
Reserved Notation "p1 =i p2"
(at level 70, format "'[hv' p1 '/ ' =i p2 ']'", no associativity).
(* We introduce a number of n-ary "list-style" notations that share a common *)
(* format, namely *)
(* [op arg1, arg2, ... last_separator last_arg] *)
(* This usually denotes a right-associative applications of op, e.g., *)
(* [&& a, b, c & d] denotes a && (b && (c && d)) *)
(* The last_separator must be a non-operator token. Here we use &, | or =>; *)
(* our default is &, but we try to match the intended meaning of op. The *)
(* separator is a workaround for limitations of the parsing engine; the same *)
(* limitations mean the separator cannot be omitted even when last_arg can. *)
(* The Notation declarations are complicated by the separate treatment for *)
(* some fixed arities (binary for bool operators, and all arities for Prop *)
(* operators). *)
(* We also use the square brackets in comprehension-style notations *)
(* [type var separator expr] *)
(* where "type" is the type of the comprehension (e.g., pred) and "separator" *)
(* is | or => . It is important that in other notations a leading square *)
(* bracket [ is always followed by an operator symbol or a fixed identifier. *)
Reserved Notation "[ /\ P1 & P2 ]" (at level 0, only parsing).
Reserved Notation "[ /\ P1 , P2 & P3 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 ']' '/ ' & P3 ] ']'").
Reserved Notation "[ /\ P1 , P2 , P3 & P4 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 , '/' P3 ']' '/ ' & P4 ] ']'").
Reserved Notation "[ /\ P1 , P2 , P3 , P4 & P5 ]" (at level 0, format
"'[hv' [ /\ '[' P1 , '/' P2 , '/' P3 , '/' P4 ']' '/ ' & P5 ] ']'").
Reserved Notation "[ \/ P1 | P2 ]" (at level 0, only parsing).
Reserved Notation "[ \/ P1 , P2 | P3 ]" (at level 0, format
"'[hv' [ \/ '[' P1 , '/' P2 ']' '/ ' | P3 ] ']'").
Reserved Notation "[ \/ P1 , P2 , P3 | P4 ]" (at level 0, format
"'[hv' [ \/ '[' P1 , '/' P2 , '/' P3 ']' '/ ' | P4 ] ']'").
Reserved Notation "[ && b1 & c ]" (at level 0, only parsing).
Reserved Notation "[ && b1 , b2 , .. , bn & c ]" (at level 0, format
"'[hv' [ && '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/ ' & c ] ']'").
Reserved Notation "[ || b1 | c ]" (at level 0, only parsing).
Reserved Notation "[ || b1 , b2 , .. , bn | c ]" (at level 0, format
"'[hv' [ || '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/ ' | c ] ']'").
Reserved Notation "[ ==> b1 => c ]" (at level 0, only parsing).
Reserved Notation "[ ==> b1 , b2 , .. , bn => c ]" (at level 0, format
"'[hv' [ ==> '[' b1 , '/' b2 , '/' .. , '/' bn ']' '/' => c ] ']'").
Reserved Notation "[ 'pred' : T => E ]" (at level 0, format
"'[hv' [ 'pred' : T => '/ ' E ] ']'").
Reserved Notation "[ 'pred' x => E ]" (at level 0, x at level 8, format
"'[hv' [ 'pred' x => '/ ' E ] ']'").
Reserved Notation "[ 'pred' x : T => E ]" (at level 0, x at level 8, format
"'[hv' [ 'pred' x : T => '/ ' E ] ']'").
Reserved Notation "[ 'rel' x y => E ]" (at level 0, x, y at level 8, format
"'[hv' [ 'rel' x y => '/ ' E ] ']'").
Reserved Notation "[ 'rel' x y : T => E ]" (at level 0, x, y at level 8, format
"'[hv' [ 'rel' x y : T => '/ ' E ] ']'").
(* Shorter delimiter *)
Delimit Scope bool_scope with B.
Open Scope bool_scope.
(* An alternative to xorb that behaves somewhat better wrt simplification. *)
Definition addb b := if b then negb else id.
(* Notation for && and || is declared in Init.Datatypes. *)
Notation "~~ b" := (negb b) : bool_scope.
Notation "b ==> c" := (implb b c) : bool_scope.
Notation "b1 (+) b2" := (addb b1 b2) : bool_scope.
(* Constant is_true b := b = true is defined in Init.Datatypes. *)
Coercion is_true : bool >-> Sortclass. (* Prop *)
Lemma prop_congr : forall b b' : bool, b = b' -> b = b' :> Prop.
Proof. by move=> b b' ->. Qed.
Ltac prop_congr := apply: prop_congr.
(* Lemmas for trivial. *)
Lemma is_true_true : true. Proof. by []. Qed.
Lemma not_false_is_true : ~ false. Proof. by []. Qed.
Lemma is_true_locked_true : locked true. Proof. by unlock. Qed.
Hint Resolve is_true_true not_false_is_true is_true_locked_true.
(* Shorter names. *)
Definition isT := is_true_true.
Definition notF := not_false_is_true.
(* Negation lemmas. *)
(* We generally take NEGATION as the standard form of a false condition: *)
(* negative boolean hypotheses should be of the form ~~ b, rather than ~ b or *)
(* b = false, as much as possible. *)
Lemma negbT b : b = false -> ~~ b. Proof. by case: b. Qed.
Lemma negbTE b : ~~ b -> b = false. Proof. by case: b. Qed.
Lemma negbF b : (b : bool) -> ~~ b = false. Proof. by case: b. Qed.
Lemma negbFE b : ~~ b = false -> b. Proof. by case: b. Qed.
Lemma negbK : involutive negb. Proof. by case. Qed.
Lemma negbNE b : ~~ ~~ b -> b. Proof. by case: b. Qed.
Lemma negb_inj : injective negb. Proof. exact: can_inj negbK. Qed.
Lemma negbLR b c : b = ~~ c -> ~~ b = c. Proof. exact: canLR negbK. Qed.
Lemma negbRL b c : ~~ b = c -> b = ~~ c. Proof. exact: canRL negbK. Qed.
Lemma contra (c b : bool) : (c -> b) -> ~~ b -> ~~ c.
Proof. by case: b => //; case: c. Qed.
Definition contraNN := contra.
Lemma contraL (c b : bool) : (c -> ~~ b) -> b -> ~~ c.
Proof. by case: b => //; case: c. Qed.
Definition contraTN := contraL.
Lemma contraR (c b : bool) : (~~ c -> b) -> ~~ b -> c.
Proof. by case: b => //; case: c. Qed.
Definition contraNT := contraR.
Lemma contraLR (c b : bool) : (~~ c -> ~~ b) -> b -> c.
Proof. by case: b => //; case: c. Qed.
Definition contraTT := contraLR.
Lemma contraT b : (~~ b -> false) -> b. Proof. by case: b => // ->. Qed.
Lemma wlog_neg b : (~~ b -> b) -> b. Proof. by case: b => // ->. Qed.
Lemma contraFT (c b : bool) : (~~ c -> b) -> b = false -> c.
Proof. by move/contraR=> notb_c /negbT. Qed.
Lemma contraFN (c b : bool) : (c -> b) -> b = false -> ~~ c.
Proof. by move/contra=> notb_notc /negbT. Qed.
Lemma contraTF (c b : bool) : (c -> ~~ b) -> b -> c = false.
Proof. by move/contraL=> b_notc /b_notc/negbTE. Qed.
Lemma contraNF (c b : bool) : (c -> b) -> ~~ b -> c = false.
Proof. by move/contra=> notb_notc /notb_notc/negbTE. Qed.
Lemma contraFF (c b : bool) : (c -> b) -> b = false -> c = false.
Proof. by move/contraFN=> bF_notc /bF_notc/negbTE. Qed.
(* Coercion of sum-style datatypes into bool, which makes it possible *)
(* to use ssr's boolean if rather than Coq's "generic" if. *)
Coercion isSome T (u : option T) := if u is Some _ then true else false.
Coercion is_inl A B (u : A + B) := if u is inl _ then true else false.
Coercion is_left A B (u : {A} + {B}) := if u is left _ then true else false.
Coercion is_inleft A B (u : A + {B}) := if u is inleft _ then true else false.
Prenex Implicits isSome is_inl is_left is_inleft.
Definition decidable P := {P} + {~ P}.
(* Lemmas for ifs with large conditions, which allow reasoning about the *)
(* condition without repeating it inside the proof (the latter IS *)
(* preferable when the condition is short). *)
(* Usage : *)
(* if the goal contains (if cond then ...) = ... *)
(* case: ifP => Hcond. *)
(* generates two subgoal, with the assumption Hcond : cond = true/false *)
(* Rewrite if_same eliminates redundant ifs *)
(* Rewrite (fun_if f) moves a function f inside an if *)
(* Rewrite if_arg moves an argument inside a function-valued if *)
Section BoolIf.
Variables (A B : Type) (x : A) (f : A -> B) (b : bool) (vT vF : A).
CoInductive if_spec (not_b : Prop) : bool -> A -> Set :=
| IfSpecTrue of b : if_spec not_b true vT
| IfSpecFalse of not_b : if_spec not_b false vF.
Lemma ifP : if_spec (b = false) b (if b then vT else vF).
Proof. by case def_b: b; constructor. Qed.
Lemma ifPn : if_spec (~~ b) b (if b then vT else vF).
Proof. by case def_b: b; constructor; rewrite ?def_b. Qed.
Lemma ifT : b -> (if b then vT else vF) = vT. Proof. by move->. Qed.
Lemma ifF : b = false -> (if b then vT else vF) = vF. Proof. by move->. Qed.
Lemma ifN : ~~ b -> (if b then vT else vF) = vF. Proof. by move/negbTE->. Qed.
Lemma if_same : (if b then vT else vT) = vT.
Proof. by case b. Qed.
Lemma if_neg : (if ~~ b then vT else vF) = if b then vF else vT.
Proof. by case b. Qed.
Lemma fun_if : f (if b then vT else vF) = if b then f vT else f vF.
Proof. by case b. Qed.
Lemma if_arg (fT fF : A -> B) :
(if b then fT else fF) x = if b then fT x else fF x.
Proof. by case b. Qed.
(* Turning a boolean "if" form into an application. *)
Definition if_expr := if b then vT else vF.
Lemma ifE : (if b then vT else vF) = if_expr. Proof. by []. Qed.
End BoolIf.
(* Core (internal) reflection lemmas, used for the three kinds of views. *)
Section ReflectCore.
Variables (P Q : Prop) (b c : bool).
Hypothesis Hb : reflect P b.
Lemma introNTF : (if c then ~ P else P) -> ~~ b = c.
Proof. by case c; case Hb. Qed.
Lemma introTF : (if c then P else ~ P) -> b = c.
Proof. by case c; case Hb. Qed.
Lemma elimNTF : ~~ b = c -> if c then ~ P else P.
Proof. by move <-; case Hb. Qed.
Lemma elimTF : b = c -> if c then P else ~ P.
Proof. by move <-; case Hb. Qed.
Lemma equivPif : (Q -> P) -> (P -> Q) -> if b then Q else ~ Q.
Proof. by case Hb; auto. Qed.
Lemma xorPif : Q \/ P -> ~ (Q /\ P) -> if b then ~ Q else Q.
Proof. by case Hb => [? _ H ? | ? H _]; case: H. Qed.
End ReflectCore.
(* Internal negated reflection lemmas *)
Section ReflectNegCore.
Variables (P Q : Prop) (b c : bool).
Hypothesis Hb : reflect P (~~ b).
Lemma introTFn : (if c then ~ P else P) -> b = c.
Proof. by move/(introNTF Hb) <-; case b. Qed.
Lemma elimTFn : b = c -> if c then ~ P else P.
Proof. by move <-; apply: (elimNTF Hb); case b. Qed.
Lemma equivPifn : (Q -> P) -> (P -> Q) -> if b then ~ Q else Q.
Proof. by rewrite -if_neg; apply: equivPif. Qed.
Lemma xorPifn : Q \/ P -> ~ (Q /\ P) -> if b then Q else ~ Q.
Proof. by rewrite -if_neg; apply: xorPif. Qed.
End ReflectNegCore.
(* User-oriented reflection lemmas *)
Section Reflect.
Variables (P Q : Prop) (b b' c : bool).
Hypotheses (Pb : reflect P b) (Pb' : reflect P (~~ b')).
Lemma introT : P -> b. Proof. exact: introTF true _. Qed.
Lemma introF : ~ P -> b = false. Proof. exact: introTF false _. Qed.
Lemma introN : ~ P -> ~~ b. Proof. exact: introNTF true _. Qed.
Lemma introNf : P -> ~~ b = false. Proof. exact: introNTF false _. Qed.
Lemma introTn : ~ P -> b'. Proof. exact: introTFn true _. Qed.
Lemma introFn : P -> b' = false. Proof. exact: introTFn false _. Qed.
Lemma elimT : b -> P. Proof. exact: elimTF true _. Qed.
Lemma elimF : b = false -> ~ P. Proof. exact: elimTF false _. Qed.
Lemma elimN : ~~ b -> ~P. Proof. exact: elimNTF true _. Qed.
Lemma elimNf : ~~ b = false -> P. Proof. exact: elimNTF false _. Qed.
Lemma elimTn : b' -> ~ P. Proof. exact: elimTFn true _. Qed.
Lemma elimFn : b' = false -> P. Proof. exact: elimTFn false _. Qed.
Lemma introP : (b -> Q) -> (~~ b -> ~ Q) -> reflect Q b.
Proof. by case b; constructor; auto. Qed.
Lemma iffP : (P -> Q) -> (Q -> P) -> reflect Q b.
Proof. by case: Pb; constructor; auto. Qed.
Lemma equivP : (P <-> Q) -> reflect Q b.
Proof. by case; apply: iffP. Qed.
Lemma sumboolP (decQ : decidable Q) : reflect Q decQ.
Proof. by case: decQ; constructor. Qed.
Lemma appP : reflect Q b -> P -> Q.
Proof. by move=> Qb; move/introT; case: Qb. Qed.
Lemma sameP : reflect P c -> b = c.
Proof. by case; [apply: introT | apply: introF]. Qed.
Lemma decPcases : if b then P else ~ P. Proof. by case Pb. Qed.
Definition decP : decidable P. by case: b decPcases; [left | right]. Defined.
Lemma rwP : P <-> b. Proof. by split; [apply: introT | apply: elimT]. Qed.
Lemma rwP2 : reflect Q b -> (P <-> Q).
Proof. by move=> Qb; split=> ?; [apply: appP | apply: elimT; case: Qb]. Qed.
(* Predicate family to reflect excluded middle in bool. *)
CoInductive alt_spec : bool -> Type :=
| AltTrue of P : alt_spec true
| AltFalse of ~~ b : alt_spec false.
Lemma altP : alt_spec b.
Proof. by case def_b: b / Pb; constructor; rewrite ?def_b. Qed.
End Reflect.
Hint View for move/ elimTF|3 elimNTF|3 elimTFn|3 introT|2 introTn|2 introN|2.
Hint View for apply/ introTF|3 introNTF|3 introTFn|3 elimT|2 elimTn|2 elimN|2.
Hint View for apply// equivPif|3 xorPif|3 equivPifn|3 xorPifn|3.
(* Allow the direct application of a reflection lemma to a boolean assertion. *)
Coercion elimT : reflect >-> Funclass.
CoInductive implies P Q := Implies of P -> Q.
Lemma impliesP P Q : implies P Q -> P -> Q. Proof. by case. Qed.
Lemma impliesPn (P Q : Prop) : implies P Q -> ~ Q -> ~ P.
Proof. by case=> iP ? /iP. Qed.
Coercion impliesP : implies >-> Funclass.
Hint View for move/ impliesPn|2 impliesP|2.
Hint View for apply/ impliesPn|2 impliesP|2.
(* Impredicative or, which can emulate a classical not-implies. *)
Definition unless condition property : Prop :=
forall goal : Prop, (condition -> goal) -> (property -> goal) -> goal.
Notation "\unless C , P" := (unless C P)
(at level 200, C at level 100,
format "'[' \unless C , '/ ' P ']'") : type_scope.
Lemma unlessL C P : implies C (\unless C, P).
Proof. by split=> hC G /(_ hC). Qed.
Lemma unlessR C P : implies P (\unless C, P).
Proof. by split=> hP G _ /(_ hP). Qed.
Lemma unless_sym C P : implies (\unless C, P) (\unless P, C).
Proof. by split; apply; [apply/unlessR | apply/unlessL]. Qed.
Lemma unlessP (C P : Prop) : (\unless C, P) <-> C \/ P.
Proof. by split=> [|[/unlessL | /unlessR]]; apply; [left | right]. Qed.
Lemma bind_unless C P {Q} : implies (\unless C, P) (\unless (\unless C, Q), P).
Proof. by split; apply=> [hC|hP]; [apply/unlessL/unlessL | apply/unlessR]. Qed.
Lemma unless_contra b C : implies (~~ b -> C) (\unless C, b).
Proof. by split; case: b => [_ | hC]; [apply/unlessR | apply/unlessL/hC]. Qed.
(* Classical reasoning becomes directly accessible for any bool subgoal. *)
(* Note that we cannot use "unless" here for lack of universe polymorphism. *)
Definition classically P : Prop := forall b : bool, (P -> b) -> b.
Lemma classicP (P : Prop) : classically P <-> ~ ~ P.
Proof.
split=> [cP nP | nnP [] // nP]; last by case nnP; move/nP.
by have: P -> false; [move/nP | move/cP].
Qed.
Lemma classicW P : P -> classically P. Proof. by move=> hP _ ->. Qed.
Lemma classic_bind P Q : (P -> classically Q) -> classically P -> classically Q.
Proof. by move=> iPQ cP b /iPQ-/cP. Qed.
Lemma classic_EM P : classically (decidable P).
Proof.
by case=> // undecP; apply/undecP; right=> notP; apply/notF/undecP; left.
Qed.
Lemma classic_pick T P : classically ({x : T | P x} + (forall x, ~ P x)).
Proof.
case=> // undecP; apply/undecP; right=> x Px.
by apply/notF/undecP; left; exists x.
Qed.
Lemma classic_imply P Q : (P -> classically Q) -> classically (P -> Q).
Proof.
move=> iPQ []// notPQ; apply/notPQ=> /iPQ-cQ.
by case: notF; apply: cQ => hQ; apply: notPQ.
Qed.
(* List notations for wider connectives; the Prop connectives have a fixed *)
(* width so as to avoid iterated destruction (we go up to width 5 for /\, and *)
(* width 4 for or). The bool connectives have arbitrary widths, but denote *)
(* expressions that associate to the RIGHT. This is consistent with the right *)
(* associativity of list expressions and thus more convenient in most proofs. *)
Inductive and3 (P1 P2 P3 : Prop) : Prop := And3 of P1 & P2 & P3.
Inductive and4 (P1 P2 P3 P4 : Prop) : Prop := And4 of P1 & P2 & P3 & P4.
Inductive and5 (P1 P2 P3 P4 P5 : Prop) : Prop :=
And5 of P1 & P2 & P3 & P4 & P5.
Inductive or3 (P1 P2 P3 : Prop) : Prop := Or31 of P1 | Or32 of P2 | Or33 of P3.
Inductive or4 (P1 P2 P3 P4 : Prop) : Prop :=
Or41 of P1 | Or42 of P2 | Or43 of P3 | Or44 of P4.
Notation "[ /\ P1 & P2 ]" := (and P1 P2) (only parsing) : type_scope.
Notation "[ /\ P1 , P2 & P3 ]" := (and3 P1 P2 P3) : type_scope.
Notation "[ /\ P1 , P2 , P3 & P4 ]" := (and4 P1 P2 P3 P4) : type_scope.
Notation "[ /\ P1 , P2 , P3 , P4 & P5 ]" := (and5 P1 P2 P3 P4 P5) : type_scope.
Notation "[ \/ P1 | P2 ]" := (or P1 P2) (only parsing) : type_scope.
Notation "[ \/ P1 , P2 | P3 ]" := (or3 P1 P2 P3) : type_scope.
Notation "[ \/ P1 , P2 , P3 | P4 ]" := (or4 P1 P2 P3 P4) : type_scope.
Notation "[ && b1 & c ]" := (b1 && c) (only parsing) : bool_scope.
Notation "[ && b1 , b2 , .. , bn & c ]" := (b1 && (b2 && .. (bn && c) .. ))
: bool_scope.
Notation "[ || b1 | c ]" := (b1 || c) (only parsing) : bool_scope.
Notation "[ || b1 , b2 , .. , bn | c ]" := (b1 || (b2 || .. (bn || c) .. ))
: bool_scope.
Notation "[ ==> b1 , b2 , .. , bn => c ]" :=
(b1 ==> (b2 ==> .. (bn ==> c) .. )) : bool_scope.
Notation "[ ==> b1 => c ]" := (b1 ==> c) (only parsing) : bool_scope.
Section AllAnd.
Variables (T : Type) (P1 P2 P3 P4 P5 : T -> Prop).
Local Notation a P := (forall x, P x).
Lemma all_and2 : implies (forall x, [/\ P1 x & P2 x]) [/\ a P1 & a P2].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and3 : implies (forall x, [/\ P1 x, P2 x & P3 x])
[/\ a P1, a P2 & a P3].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and4 : implies (forall x, [/\ P1 x, P2 x, P3 x & P4 x])
[/\ a P1, a P2, a P3 & a P4].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
Lemma all_and5 : implies (forall x, [/\ P1 x, P2 x, P3 x, P4 x & P5 x])
[/\ a P1, a P2, a P3, a P4 & a P5].
Proof. by split=> haveP; split=> x; case: (haveP x). Qed.
End AllAnd.
Arguments all_and2 {T P1 P2}.
Arguments all_and3 {T P1 P2 P3}.
Arguments all_and4 {T P1 P2 P3 P4}.
Arguments all_and5 {T P1 P2 P3 P4 P5}.
Lemma pair_andP P Q : P /\ Q <-> P * Q. Proof. by split; case. Qed.
Section ReflectConnectives.
Variable b1 b2 b3 b4 b5 : bool.
Lemma idP : reflect b1 b1.
Proof. by case b1; constructor. Qed.
Lemma boolP : alt_spec b1 b1 b1.
Proof. exact: (altP idP). Qed.
Lemma idPn : reflect (~~ b1) (~~ b1).
Proof. by case b1; constructor. Qed.
Lemma negP : reflect (~ b1) (~~ b1).
Proof. by case b1; constructor; auto. Qed.
Lemma negPn : reflect b1 (~~ ~~ b1).
Proof. by case b1; constructor. Qed.
Lemma negPf : reflect (b1 = false) (~~ b1).
Proof. by case b1; constructor. Qed.
Lemma andP : reflect (b1 /\ b2) (b1 && b2).
Proof. by case b1; case b2; constructor=> //; case. Qed.
Lemma and3P : reflect [/\ b1, b2 & b3] [&& b1, b2 & b3].
Proof. by case b1; case b2; case b3; constructor; try by case. Qed.
Lemma and4P : reflect [/\ b1, b2, b3 & b4] [&& b1, b2, b3 & b4].
Proof. by case b1; case b2; case b3; case b4; constructor; try by case. Qed.
Lemma and5P : reflect [/\ b1, b2, b3, b4 & b5] [&& b1, b2, b3, b4 & b5].
Proof.
by case b1; case b2; case b3; case b4; case b5; constructor; try by case.
Qed.
Lemma orP : reflect (b1 \/ b2) (b1 || b2).
Proof. by case b1; case b2; constructor; auto; case. Qed.
Lemma or3P : reflect [\/ b1, b2 | b3] [|| b1, b2 | b3].
Proof.
case b1; first by constructor; constructor 1.
case b2; first by constructor; constructor 2.
case b3; first by constructor; constructor 3.
by constructor; case.
Qed.
Lemma or4P : reflect [\/ b1, b2, b3 | b4] [|| b1, b2, b3 | b4].
Proof.
case b1; first by constructor; constructor 1.
case b2; first by constructor; constructor 2.
case b3; first by constructor; constructor 3.
case b4; first by constructor; constructor 4.
by constructor; case.
Qed.
Lemma nandP : reflect (~~ b1 \/ ~~ b2) (~~ (b1 && b2)).
Proof. by case b1; case b2; constructor; auto; case; auto. Qed.
Lemma norP : reflect (~~ b1 /\ ~~ b2) (~~ (b1 || b2)).
Proof. by case b1; case b2; constructor; auto; case; auto. Qed.
Lemma implyP : reflect (b1 -> b2) (b1 ==> b2).
Proof. by case b1; case b2; constructor; auto. Qed.
End ReflectConnectives.
Arguments idP [b1].
Arguments idPn [b1].
Arguments negP [b1].
Arguments negPn [b1].
Arguments negPf [b1].
Arguments andP [b1 b2].
Arguments and3P [b1 b2 b3].
Arguments and4P [b1 b2 b3 b4].
Arguments and5P [b1 b2 b3 b4 b5].
Arguments orP [b1 b2].
Arguments or3P [b1 b2 b3].
Arguments or4P [b1 b2 b3 b4].
Arguments nandP [b1 b2].
Arguments norP [b1 b2].
Arguments implyP [b1 b2].
Prenex Implicits idP idPn negP negPn negPf.
Prenex Implicits andP and3P and4P and5P orP or3P or4P nandP norP implyP.
(* Shorter, more systematic names for the boolean connectives laws. *)
Lemma andTb : left_id true andb. Proof. by []. Qed.
Lemma andFb : left_zero false andb. Proof. by []. Qed.
Lemma andbT : right_id true andb. Proof. by case. Qed.
Lemma andbF : right_zero false andb. Proof. by case. Qed.
Lemma andbb : idempotent andb. Proof. by case. Qed.
Lemma andbC : commutative andb. Proof. by do 2!case. Qed.
Lemma andbA : associative andb. Proof. by do 3!case. Qed.
Lemma andbCA : left_commutative andb. Proof. by do 3!case. Qed.
Lemma andbAC : right_commutative andb. Proof. by do 3!case. Qed.
Lemma andbACA : interchange andb andb. Proof. by do 4!case. Qed.
Lemma orTb : forall b, true || b. Proof. by []. Qed.
Lemma orFb : left_id false orb. Proof. by []. Qed.
Lemma orbT : forall b, b || true. Proof. by case. Qed.
Lemma orbF : right_id false orb. Proof. by case. Qed.
Lemma orbb : idempotent orb. Proof. by case. Qed.
Lemma orbC : commutative orb. Proof. by do 2!case. Qed.
Lemma orbA : associative orb. Proof. by do 3!case. Qed.
Lemma orbCA : left_commutative orb. Proof. by do 3!case. Qed.
Lemma orbAC : right_commutative orb. Proof. by do 3!case. Qed.
Lemma orbACA : interchange orb orb. Proof. by do 4!case. Qed.
Lemma andbN b : b && ~~ b = false. Proof. by case: b. Qed.
Lemma andNb b : ~~ b && b = false. Proof. by case: b. Qed.
Lemma orbN b : b || ~~ b = true. Proof. by case: b. Qed.
Lemma orNb b : ~~ b || b = true. Proof. by case: b. Qed.
Lemma andb_orl : left_distributive andb orb. Proof. by do 3!case. Qed.
Lemma andb_orr : right_distributive andb orb. Proof. by do 3!case. Qed.
Lemma orb_andl : left_distributive orb andb. Proof. by do 3!case. Qed.
Lemma orb_andr : right_distributive orb andb. Proof. by do 3!case. Qed.
Lemma andb_idl (a b : bool) : (b -> a) -> a && b = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma andb_idr (a b : bool) : (a -> b) -> a && b = a.
Proof. by case: a; case: b => // ->. Qed.
Lemma andb_id2l (a b c : bool) : (a -> b = c) -> a && b = a && c.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma andb_id2r (a b c : bool) : (b -> a = c) -> a && b = c && b.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma orb_idl (a b : bool) : (a -> b) -> a || b = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma orb_idr (a b : bool) : (b -> a) -> a || b = a.
Proof. by case: a; case: b => // ->. Qed.
Lemma orb_id2l (a b c : bool) : (~~ a -> b = c) -> a || b = a || c.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma orb_id2r (a b c : bool) : (~~ b -> a = c) -> a || b = c || b.
Proof. by case: a; case: b; case: c => // ->. Qed.
Lemma negb_and (a b : bool) : ~~ (a && b) = ~~ a || ~~ b.
Proof. by case: a; case: b. Qed.
Lemma negb_or (a b : bool) : ~~ (a || b) = ~~ a && ~~ b.
Proof. by case: a; case: b. Qed.
(* Pseudo-cancellation -- i.e, absorbtion *)
Lemma andbK a b : a && b || a = a. Proof. by case: a; case: b. Qed.
Lemma andKb a b : a || b && a = a. Proof. by case: a; case: b. Qed.
Lemma orbK a b : (a || b) && a = a. Proof. by case: a; case: b. Qed.
Lemma orKb a b : a && (b || a) = a. Proof. by case: a; case: b. Qed.
(* Imply *)
Lemma implybT b : b ==> true. Proof. by case: b. Qed.
Lemma implybF b : (b ==> false) = ~~ b. Proof. by case: b. Qed.
Lemma implyFb b : false ==> b. Proof. by []. Qed.
Lemma implyTb b : (true ==> b) = b. Proof. by []. Qed.
Lemma implybb b : b ==> b. Proof. by case: b. Qed.
Lemma negb_imply a b : ~~ (a ==> b) = a && ~~ b.
Proof. by case: a; case: b. Qed.
Lemma implybE a b : (a ==> b) = ~~ a || b.
Proof. by case: a; case: b. Qed.
Lemma implyNb a b : (~~ a ==> b) = a || b.
Proof. by case: a; case: b. Qed.
Lemma implybN a b : (a ==> ~~ b) = (b ==> ~~ a).
Proof. by case: a; case: b. Qed.
Lemma implybNN a b : (~~ a ==> ~~ b) = b ==> a.
Proof. by case: a; case: b. Qed.
Lemma implyb_idl (a b : bool) : (~~ a -> b) -> (a ==> b) = b.
Proof. by case: a; case: b => // ->. Qed.
Lemma implyb_idr (a b : bool) : (b -> ~~ a) -> (a ==> b) = ~~ a.
Proof. by case: a; case: b => // ->. Qed.
Lemma implyb_id2l (a b c : bool) : (a -> b = c) -> (a ==> b) = (a ==> c).
Proof. by case: a; case: b; case: c => // ->. Qed.
(* Addition (xor) *)
Lemma addFb : left_id false addb. Proof. by []. Qed.
Lemma addbF : right_id false addb. Proof. by case. Qed.
Lemma addbb : self_inverse false addb. Proof. by case. Qed.
Lemma addbC : commutative addb. Proof. by do 2!case. Qed.
Lemma addbA : associative addb. Proof. by do 3!case. Qed.
Lemma addbCA : left_commutative addb. Proof. by do 3!case. Qed.
Lemma addbAC : right_commutative addb. Proof. by do 3!case. Qed.
Lemma addbACA : interchange addb addb. Proof. by do 4!case. Qed.
Lemma andb_addl : left_distributive andb addb. Proof. by do 3!case. Qed.
Lemma andb_addr : right_distributive andb addb. Proof. by do 3!case. Qed.
Lemma addKb : left_loop id addb. Proof. by do 2!case. Qed.
Lemma addbK : right_loop id addb. Proof. by do 2!case. Qed.
Lemma addIb : left_injective addb. Proof. by do 3!case. Qed.
Lemma addbI : right_injective addb. Proof. by do 3!case. Qed.
Lemma addTb b : true (+) b = ~~ b. Proof. by []. Qed.
Lemma addbT b : b (+) true = ~~ b. Proof. by case: b. Qed.
Lemma addbN a b : a (+) ~~ b = ~~ (a (+) b).
Proof. by case: a; case: b. Qed.
Lemma addNb a b : ~~ a (+) b = ~~ (a (+) b).
Proof. by case: a; case: b. Qed.
Lemma addbP a b : reflect (~~ a = b) (a (+) b).
Proof. by case: a; case: b; constructor. Qed.
Arguments addbP [a b].
(* Resolution tactic for blindly weeding out common terms from boolean *)
(* equalities. When faced with a goal of the form (andb/orb/addb b1 b2) = b3 *)
(* they will try to locate b1 in b3 and remove it. This can fail! *)
Ltac bool_congr :=
match goal with
| |- (?X1 && ?X2 = ?X3) => first
[ symmetry; rewrite -1?(andbC X1) -?(andbCA X1); congr 1 (andb X1); symmetry
| case: (X1); [ rewrite ?andTb ?andbT // | by rewrite ?andbF /= ] ]
| |- (?X1 || ?X2 = ?X3) => first
[ symmetry; rewrite -1?(orbC X1) -?(orbCA X1); congr 1 (orb X1); symmetry
| case: (X1); [ by rewrite ?orbT //= | rewrite ?orFb ?orbF ] ]
| |- (?X1 (+) ?X2 = ?X3) =>
symmetry; rewrite -1?(addbC X1) -?(addbCA X1); congr 1 (addb X1); symmetry
| |- (~~ ?X1 = ?X2) => congr 1 negb
end.
(******************************************************************************)
(* Predicates, i.e., packaged functions to bool. *)
(* - pred T, the basic type for predicates over a type T, is simply an alias *)
(* for T -> bool. *)
(* We actually distinguish two kinds of predicates, which we call applicative *)
(* and collective, based on the syntax used to test them at some x in T: *)
(* - For an applicative predicate P, one uses prefix syntax: *)
(* P x *)
(* Also, most operations on applicative predicates use prefix syntax as *)
(* well (e.g., predI P Q). *)
(* - For a collective predicate A, one uses infix syntax: *)
(* x \in A *)
(* and all operations on collective predicates use infix syntax as well *)
(* (e.g., [predI A & B]). *)
(* There are only two kinds of applicative predicates: *)
(* - pred T, the alias for T -> bool mentioned above *)
(* - simpl_pred T, an alias for simpl_fun T bool with a coercion to pred T *)
(* that auto-simplifies on application (see ssrfun). *)
(* On the other hand, the set of collective predicate types is open-ended via *)
(* - predType T, a Structure that can be used to put Canonical collective *)
(* predicate interpretation on other types, such as lists, tuples, *)
(* finite sets, etc. *)
(* Indeed, we define such interpretations for applicative predicate types, *)
(* which can therefore also be used with the infix syntax, e.g., *)
(* x \in predI P Q *)
(* Moreover these infix forms are convertible to their prefix counterpart *)
(* (e.g., predI P Q x which in turn simplifies to P x && Q x). The converse *)
(* is not true, however; collective predicate types cannot, in general, be *)
(* general, be used applicatively, because of the "uniform inheritance" *)
(* restriction on implicit coercions. *)
(* However, we do define an explicit generic coercion *)
(* - mem : forall (pT : predType), pT -> mem_pred T *)
(* where mem_pred T is a variant of simpl_pred T that preserves the infix *)
(* syntax, i.e., mem A x auto-simplifies to x \in A. *)
(* Indeed, the infix "collective" operators are notation for a prefix *)
(* operator with arguments of type mem_pred T or pred T, applied to coerced *)
(* collective predicates, e.g., *)
(* Notation "x \in A" := (in_mem x (mem A)). *)
(* This prevents the variability in the predicate type from interfering with *)
(* the application of generic lemmas. Moreover this also makes it much easier *)
(* to define generic lemmas, because the simplest type -- pred T -- can be *)
(* used as the type of generic collective predicates, provided one takes care *)
(* not to use it applicatively; this avoids the burden of having to declare a *)
(* different predicate type for each predicate parameter of each section or *)
(* lemma. *)
(* This trick is made possible by the fact that the constructor of the *)
(* mem_pred T type aligns the unification process, forcing a generic *)
(* "collective" predicate A : pred T to unify with the actual collective B, *)
(* which mem has coerced to pred T via an internal, hidden implicit coercion, *)
(* supplied by the predType structure for B. Users should take care not to *)
(* inadvertently "strip" (mem B) down to the coerced B, since this will *)
(* expose the internal coercion: Coq will display a term B x that cannot be *)
(* typed as such. The topredE lemma can be used to restore the x \in B *)
(* syntax in this case. While -topredE can conversely be used to change *)
(* x \in P into P x, it is safer to use the inE and memE lemmas instead, as *)
(* they do not run the risk of exposing internal coercions. As a consequence *)
(* it is better to explicitly cast a generic applicative pred T to simpl_pred *)
(* using the SimplPred constructor, when it is used as a collective predicate *)
(* (see, e.g., Lemma eq_big in bigop). *)
(* We also sometimes "instantiate" the predType structure by defining a *)
(* coercion to the sort of the predPredType structure. This works better for *)
(* types such as {set T} that have subtypes that coerce to them, since the *)
(* same coercion will be inserted by the application of mem. It also lets us *)
(* turn any Type aT : predArgType into the total predicate over that type, *)
(* i.e., fun _: aT => true. This allows us to write, e.g., #|'I_n| for the *)
(* cardinal of the (finite) type of integers less than n. *)
(* Collective predicates have a specific extensional equality, *)
(* - A =i B, *)
(* while applicative predicates use the extensional equality of functions, *)
(* - P =1 Q *)
(* The two forms are convertible, however. *)
(* We lift boolean operations to predicates, defining: *)
(* - predU (union), predI (intersection), predC (complement), *)
(* predD (difference), and preim (preimage, i.e., composition) *)
(* For each operation we define three forms, typically: *)
(* - predU : pred T -> pred T -> simpl_pred T *)
(* - [predU A & B], a Notation for predU (mem A) (mem B) *)
(* - xpredU, a Notation for the lambda-expression inside predU, *)
(* which is mostly useful as an argument of =1, since it exposes the head *)
(* head constant of the expression to the ssreflect matching algorithm. *)
(* The syntax for the preimage of a collective predicate A is *)
(* - [preim f of A] *)
(* Finally, the generic syntax for defining a simpl_pred T is *)
(* - [pred x : T | P(x)], [pred x | P(x)], [pred x in A | P(x)], etc. *)
(* We also support boolean relations, but only the applicative form, with *)
(* types *)
(* - rel T, an alias for T -> pred T *)
(* - simpl_rel T, an auto-simplifying version, and syntax *)
(* [rel x y | P(x,y)], [rel x y in A & B | P(x,y)], etc. *)
(* The notation [rel of fA] can be used to coerce a function returning a *)
(* collective predicate to one returning pred T. *)
(* Finally, note that there is specific support for ambivalent predicates *)
(* that can work in either style, as per this file's head descriptor. *)
(******************************************************************************)
Definition pred T := T -> bool.
Identity Coercion fun_of_pred : pred >-> Funclass.
Definition rel T := T -> pred T.
Identity Coercion fun_of_rel : rel >-> Funclass.
Notation xpred0 := (fun _ => false).
Notation xpredT := (fun _ => true).
Notation xpredI := (fun (p1 p2 : pred _) x => p1 x && p2 x).
Notation xpredU := (fun (p1 p2 : pred _) x => p1 x || p2 x).
Notation xpredC := (fun (p : pred _) x => ~~ p x).
Notation xpredD := (fun (p1 p2 : pred _) x => ~~ p2 x && p1 x).
Notation xpreim := (fun f (p : pred _) x => p (f x)).
Notation xrelU := (fun (r1 r2 : rel _) x y => r1 x y || r2 x y).
Section Predicates.
Variables T : Type.
Definition subpred (p1 p2 : pred T) := forall x, p1 x -> p2 x.
Definition subrel (r1 r2 : rel T) := forall x y, r1 x y -> r2 x y.
Definition simpl_pred := simpl_fun T bool.
Definition applicative_pred := pred T.
Definition collective_pred := pred T.
Definition SimplPred (p : pred T) : simpl_pred := SimplFun p.
Coercion pred_of_simpl (p : simpl_pred) : pred T := fun_of_simpl p.
Coercion applicative_pred_of_simpl (p : simpl_pred) : applicative_pred :=
fun_of_simpl p.
Coercion collective_pred_of_simpl (p : simpl_pred) : collective_pred :=
fun x => (let: SimplFun f := p in fun _ => f x) x.
(* Note: applicative_of_simpl is convertible to pred_of_simpl, while *)
(* collective_of_simpl is not. *)
Definition pred0 := SimplPred xpred0.
Definition predT := SimplPred xpredT.
Definition predI p1 p2 := SimplPred (xpredI p1 p2).
Definition predU p1 p2 := SimplPred (xpredU p1 p2).
Definition predC p := SimplPred (xpredC p).
Definition predD p1 p2 := SimplPred (xpredD p1 p2).
Definition preim rT f (d : pred rT) := SimplPred (xpreim f d).
Definition simpl_rel := simpl_fun T (pred T).
Definition SimplRel (r : rel T) : simpl_rel := [fun x => r x].
Coercion rel_of_simpl_rel (r : simpl_rel) : rel T := fun x y => r x y.
Definition relU r1 r2 := SimplRel (xrelU r1 r2).
Lemma subrelUl r1 r2 : subrel r1 (relU r1 r2).
Proof. by move=> *; apply/orP; left. Qed.
Lemma subrelUr r1 r2 : subrel r2 (relU r1 r2).
Proof. by move=> *; apply/orP; right. Qed.
CoInductive mem_pred := Mem of pred T.
Definition isMem pT topred mem := mem = (fun p : pT => Mem [eta topred p]).
Structure predType := PredType {
pred_sort :> Type;
topred : pred_sort -> pred T;
_ : {mem | isMem topred mem}
}.
Definition mkPredType pT toP := PredType (exist (@isMem pT toP) _ (erefl _)).
Canonical predPredType := Eval hnf in @mkPredType (pred T) id.
Canonical simplPredType := Eval hnf in mkPredType pred_of_simpl.
Canonical boolfunPredType := Eval hnf in @mkPredType (T -> bool) id.
Coercion pred_of_mem mp : pred_sort predPredType := let: Mem p := mp in [eta p].
Canonical memPredType := Eval hnf in mkPredType pred_of_mem.
Definition clone_pred U :=
fun pT & pred_sort pT -> U =>
fun a mP (pT' := @PredType U a mP) & phant_id pT' pT => pT'.
End Predicates.
Arguments pred0 [T].
Arguments predT [T].
Prenex Implicits pred0 predT predI predU predC predD preim relU.
Notation "[ 'pred' : T | E ]" := (SimplPred (fun _ : T => E%B))
(at level 0, format "[ 'pred' : T | E ]") : fun_scope.
Notation "[ 'pred' x | E ]" := (SimplPred (fun x => E%B))
(at level 0, x ident, format "[ 'pred' x | E ]") : fun_scope.
Notation "[ 'pred' x | E1 & E2 ]" := [pred x | E1 && E2 ]
(at level 0, x ident, format "[ 'pred' x | E1 & E2 ]") : fun_scope.
Notation "[ 'pred' x : T | E ]" := (SimplPred (fun x : T => E%B))
(at level 0, x ident, only parsing) : fun_scope.
Notation "[ 'pred' x : T | E1 & E2 ]" := [pred x : T | E1 && E2 ]
(at level 0, x ident, only parsing) : fun_scope.
Notation "[ 'rel' x y | E ]" := (SimplRel (fun x y => E%B))
(at level 0, x ident, y ident, format "[ 'rel' x y | E ]") : fun_scope.
Notation "[ 'rel' x y : T | E ]" := (SimplRel (fun x y : T => E%B))
(at level 0, x ident, y ident, only parsing) : fun_scope.
Notation "[ 'predType' 'of' T ]" := (@clone_pred _ T _ id _ _ id)
(at level 0, format "[ 'predType' 'of' T ]") : form_scope.
(* This redundant coercion lets us "inherit" the simpl_predType canonical *)
(* instance by declaring a coercion to simpl_pred. This hack is the only way *)
(* to put a predType structure on a predArgType. We use simpl_pred rather *)
(* than pred to ensure that /= removes the identity coercion. Note that the *)
(* coercion will never be used directly for simpl_pred, since the canonical *)
(* instance should always be resolved. *)
Notation pred_class := (pred_sort (predPredType _)).
Coercion sort_of_simpl_pred T (p : simpl_pred T) : pred_class := p : pred T.
(* This lets us use some types as a synonym for their universal predicate. *)
(* Unfortunately, this won't work for existing types like bool, unless we *)
(* redefine bool, true, false and all bool ops. *)
Definition predArgType := Type.
Bind Scope type_scope with predArgType.
Identity Coercion sort_of_predArgType : predArgType >-> Sortclass.
Coercion pred_of_argType (T : predArgType) : simpl_pred T := predT.
Notation "{ : T }" := (T%type : predArgType)
(at level 0, format "{ : T }") : type_scope.
(* These must be defined outside a Section because "cooking" kills the *)
(* nosimpl tag. *)
Definition mem T (pT : predType T) : pT -> mem_pred T :=
nosimpl (let: @PredType _ _ _ (exist _ mem _) := pT return pT -> _ in mem).
Definition in_mem T x mp := nosimpl pred_of_mem T mp x.
Prenex Implicits mem.
Coercion pred_of_mem_pred T mp := [pred x : T | in_mem x mp].
Definition eq_mem T p1 p2 := forall x : T, in_mem x p1 = in_mem x p2.
Definition sub_mem T p1 p2 := forall x : T, in_mem x p1 -> in_mem x p2.
Typeclasses Opaque eq_mem.
Lemma sub_refl T (p : mem_pred T) : sub_mem p p. Proof. by []. Qed.
Arguments sub_refl {T p}.
Notation "x \in A" := (in_mem x (mem A)) : bool_scope.
Notation "x \in A" := (in_mem x (mem A)) : bool_scope.
Notation "x \notin A" := (~~ (x \in A)) : bool_scope.
Notation "A =i B" := (eq_mem (mem A) (mem B)) : type_scope.
Notation "{ 'subset' A <= B }" := (sub_mem (mem A) (mem B))
(at level 0, A, B at level 69,
format "{ '[hv' 'subset' A '/ ' <= B ']' }") : type_scope.
Notation "[ 'mem' A ]" := (pred_of_simpl (pred_of_mem_pred (mem A)))
(at level 0, only parsing) : fun_scope.
Notation "[ 'rel' 'of' fA ]" := (fun x => [mem (fA x)])
(at level 0, format "[ 'rel' 'of' fA ]") : fun_scope.
Notation "[ 'predI' A & B ]" := (predI [mem A] [mem B])
(at level 0, format "[ 'predI' A & B ]") : fun_scope.
Notation "[ 'predU' A & B ]" := (predU [mem A] [mem B])
(at level 0, format "[ 'predU' A & B ]") : fun_scope.
Notation "[ 'predD' A & B ]" := (predD [mem A] [mem B])
(at level 0, format "[ 'predD' A & B ]") : fun_scope.
Notation "[ 'predC' A ]" := (predC [mem A])
(at level 0, format "[ 'predC' A ]") : fun_scope.
Notation "[ 'preim' f 'of' A ]" := (preim f [mem A])
(at level 0, format "[ 'preim' f 'of' A ]") : fun_scope.
Notation "[ 'pred' x 'in' A ]" := [pred x | x \in A]
(at level 0, x ident, format "[ 'pred' x 'in' A ]") : fun_scope.
Notation "[ 'pred' x 'in' A | E ]" := [pred x | x \in A & E]
(at level 0, x ident, format "[ 'pred' x 'in' A | E ]") : fun_scope.
Notation "[ 'pred' x 'in' A | E1 & E2 ]" := [pred x | x \in A & E1 && E2 ]
(at level 0, x ident,
format "[ 'pred' x 'in' A | E1 & E2 ]") : fun_scope.
Notation "[ 'rel' x y 'in' A & B | E ]" :=
[rel x y | (x \in A) && (y \in B) && E]
(at level 0, x ident, y ident,
format "[ 'rel' x y 'in' A & B | E ]") : fun_scope.
Notation "[ 'rel' x y 'in' A & B ]" := [rel x y | (x \in A) && (y \in B)]
(at level 0, x ident, y ident,
format "[ 'rel' x y 'in' A & B ]") : fun_scope.
Notation "[ 'rel' x y 'in' A | E ]" := [rel x y in A & A | E]
(at level 0, x ident, y ident,
format "[ 'rel' x y 'in' A | E ]") : fun_scope.
Notation "[ 'rel' x y 'in' A ]" := [rel x y in A & A]
(at level 0, x ident, y ident,
format "[ 'rel' x y 'in' A ]") : fun_scope.
Section simpl_mem.
Variables (T : Type) (pT : predType T).
Implicit Types (x : T) (p : pred T) (sp : simpl_pred T) (pp : pT).
(* Bespoke structures that provide fine-grained control over matching the *)
(* various forms of the \in predicate; note in particular the different forms *)
(* of hoisting that are used. We had to work around several bugs in the *)
(* implementation of unification, notably improper expansion of telescope *)
(* projections and overwriting of a variable assignment by a later *)
(* unification (probably due to conversion cache cross-talk). *)
Structure manifest_applicative_pred p := ManifestApplicativePred {
manifest_applicative_pred_value :> pred T;
_ : manifest_applicative_pred_value = p
}.
Definition ApplicativePred p := ManifestApplicativePred (erefl p).
Canonical applicative_pred_applicative sp :=
ApplicativePred (applicative_pred_of_simpl sp).
Structure manifest_simpl_pred p := ManifestSimplPred {
manifest_simpl_pred_value :> simpl_pred T;
_ : manifest_simpl_pred_value = SimplPred p
}.
Canonical expose_simpl_pred p := ManifestSimplPred (erefl (SimplPred p)).
Structure manifest_mem_pred p := ManifestMemPred {
manifest_mem_pred_value :> mem_pred T;
_ : manifest_mem_pred_value= Mem [eta p]
}.
Canonical expose_mem_pred p := @ManifestMemPred p _ (erefl _).
Structure applicative_mem_pred p :=
ApplicativeMemPred {applicative_mem_pred_value :> manifest_mem_pred p}.
Canonical check_applicative_mem_pred p (ap : manifest_applicative_pred p) mp :=
@ApplicativeMemPred ap mp.
Lemma mem_topred (pp : pT) : mem (topred pp) = mem pp.
Proof. by rewrite /mem; case: pT pp => T1 app1 [mem1 /= ->]. Qed.
Lemma topredE x (pp : pT) : topred pp x = (x \in pp).
Proof. by rewrite -mem_topred. Qed.
Lemma app_predE x p (ap : manifest_applicative_pred p) : ap x = (x \in p).
Proof. by case: ap => _ /= ->. Qed.
Lemma in_applicative x p (amp : applicative_mem_pred p) : in_mem x amp = p x.
Proof. by case: amp => [[_ /= ->]]. Qed.
Lemma in_collective x p (msp : manifest_simpl_pred p) :
(x \in collective_pred_of_simpl msp) = p x.
Proof. by case: msp => _ /= ->. Qed.
Lemma in_simpl x p (msp : manifest_simpl_pred p) :
in_mem x (Mem [eta fun_of_simpl (msp : simpl_pred T)]) = p x.
Proof. by case: msp => _ /= ->. Qed.
(* Because of the explicit eta expansion in the left-hand side, this lemma *)
(* should only be used in a right-to-left direction. The 8.3 hack allowing *)
(* partial right-to-left use does not work with the improved expansion *)
(* heuristics in 8.4. *)
Lemma unfold_in x p : (x \in ([eta p] : pred T)) = p x.
Proof. by []. Qed.
Lemma simpl_predE p : SimplPred p =1 p.
Proof. by []. Qed.
Definition inE := (in_applicative, in_simpl, simpl_predE). (* to be extended *)
Lemma mem_simpl sp : mem sp = sp :> pred T.
Proof. by []. Qed.
Definition memE := mem_simpl. (* could be extended *)
Lemma mem_mem (pp : pT) : (mem (mem pp) = mem pp) * (mem [mem pp] = mem pp).
Proof. by rewrite -mem_topred. Qed.
End simpl_mem.
(* Qualifiers and keyed predicates. *)
CoInductive qualifier (q : nat) T := Qualifier of predPredType T.
Coercion has_quality n T (q : qualifier n T) : pred_class :=
fun x => let: Qualifier _ p := q in p x.
Arguments has_quality n [T].
Lemma qualifE n T p x : (x \in @Qualifier n T p) = p x. Proof. by []. Qed.
Notation "x \is A" := (x \in has_quality 0 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \is A ']'") : bool_scope.
Notation "x \is 'a' A" := (x \in has_quality 1 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \is 'a' A ']'") : bool_scope.
Notation "x \is 'an' A" := (x \in has_quality 2 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \is 'an' A ']'") : bool_scope.
Notation "x \isn't A" := (x \notin has_quality 0 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \isn't A ']'") : bool_scope.
Notation "x \isn't 'a' A" := (x \notin has_quality 1 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \isn't 'a' A ']'") : bool_scope.
Notation "x \isn't 'an' A" := (x \notin has_quality 2 A)
(at level 70, no associativity,
format "'[hv' x '/ ' \isn't 'an' A ']'") : bool_scope.
Notation "[ 'qualify' x | P ]" := (Qualifier 0 (fun x => P%B))
(at level 0, x at level 99,
format "'[hv' [ 'qualify' x | '/ ' P ] ']'") : form_scope.
Notation "[ 'qualify' x : T | P ]" := (Qualifier 0 (fun x : T => P%B))
(at level 0, x at level 99, only parsing) : form_scope.
Notation "[ 'qualify' 'a' x | P ]" := (Qualifier 1 (fun x => P%B))
(at level 0, x at level 99,
format "'[hv' [ 'qualify' 'a' x | '/ ' P ] ']'") : form_scope.
Notation "[ 'qualify' 'a' x : T | P ]" := (Qualifier 1 (fun x : T => P%B))
(at level 0, x at level 99, only parsing) : form_scope.
Notation "[ 'qualify' 'an' x | P ]" := (Qualifier 2 (fun x => P%B))
(at level 0, x at level 99,
format "'[hv' [ 'qualify' 'an' x | '/ ' P ] ']'") : form_scope.
Notation "[ 'qualify' 'an' x : T | P ]" := (Qualifier 2 (fun x : T => P%B))
(at level 0, x at level 99, only parsing) : form_scope.
(* Keyed predicates: support for property-bearing predicate interfaces. *)
Section KeyPred.
Variable T : Type.
CoInductive pred_key (p : predPredType T) := DefaultPredKey.
Variable p : predPredType T.
Structure keyed_pred (k : pred_key p) :=
PackKeyedPred {unkey_pred :> pred_class; _ : unkey_pred =i p}.
Variable k : pred_key p.
Definition KeyedPred := @PackKeyedPred k p (frefl _).
Variable k_p : keyed_pred k.
Lemma keyed_predE : k_p =i p. Proof. by case: k_p. Qed.
(* Instances that strip the mem cast; the first one has "pred_of_mem" as its *)
(* projection head value, while the second has "pred_of_simpl". The latter *)
(* has the side benefit of preempting accidental misdeclarations. *)
(* Note: pred_of_mem is the registered mem >-> pred_class coercion, while *)
(* simpl_of_mem; pred_of_simpl is the mem >-> pred >=> Funclass coercion. We *)
(* must write down the coercions explicitly as the Canonical head constant *)
(* computation does not strip casts !! *)
Canonical keyed_mem :=
@PackKeyedPred k (pred_of_mem (mem k_p)) keyed_predE.
Canonical keyed_mem_simpl :=
@PackKeyedPred k (pred_of_simpl (mem k_p)) keyed_predE.
End KeyPred.
Notation "x \i 'n' S" := (x \in @unkey_pred _ S _ _)
(at level 70, format "'[hv' x '/ ' \i 'n' S ']'") : bool_scope.
Section KeyedQualifier.
Variables (T : Type) (n : nat) (q : qualifier n T).
Structure keyed_qualifier (k : pred_key q) :=
PackKeyedQualifier {unkey_qualifier; _ : unkey_qualifier = q}.
Definition KeyedQualifier k := PackKeyedQualifier k (erefl q).
Variables (k : pred_key q) (k_q : keyed_qualifier k).
Fact keyed_qualifier_suproof : unkey_qualifier k_q =i q.
Proof. by case: k_q => /= _ ->. Qed.
Canonical keyed_qualifier_keyed := PackKeyedPred k keyed_qualifier_suproof.
End KeyedQualifier.
Notation "x \i 's' A" := (x \i n has_quality 0 A)
(at level 70, format "'[hv' x '/ ' \i 's' A ']'") : bool_scope.
Notation "x \i 's' 'a' A" := (x \i n has_quality 1 A)
(at level 70, format "'[hv' x '/ ' \i 's' 'a' A ']'") : bool_scope.
Notation "x \i 's' 'an' A" := (x \i n has_quality 2 A)
(at level 70, format "'[hv' x '/ ' \i 's' 'an' A ']'") : bool_scope.
Module DefaultKeying.
Canonical default_keyed_pred T p := KeyedPred (@DefaultPredKey T p).
Canonical default_keyed_qualifier T n (q : qualifier n T) :=
KeyedQualifier (DefaultPredKey q).
End DefaultKeying.
(* Skolemizing with conditions. *)
Lemma all_tag_cond_dep I T (C : pred I) U :
(forall x, T x) -> (forall x, C x -> {y : T x & U x y}) ->
{f : forall x, T x & forall x, C x -> U x (f x)}.
Proof.
move=> f0 fP; apply: all_tag (fun x y => C x -> U x y) _ => x.
by case Cx: (C x); [case/fP: Cx => y; exists y | exists (f0 x)].
Qed.
Lemma all_tag_cond I T (C : pred I) U :
T -> (forall x, C x -> {y : T & U x y}) ->
{f : I -> T & forall x, C x -> U x (f x)}.
Proof. by move=> y0; apply: all_tag_cond_dep. Qed.
Lemma all_sig_cond_dep I T (C : pred I) P :
(forall x, T x) -> (forall x, C x -> {y : T x | P x y}) ->
{f : forall x, T x | forall x, C x -> P x (f x)}.
Proof. by move=> f0 /(all_tag_cond_dep f0)[f]; exists f. Qed.
Lemma all_sig_cond I T (C : pred I) P :
T -> (forall x, C x -> {y : T | P x y}) ->
{f : I -> T | forall x, C x -> P x (f x)}.
Proof. by move=> y0; apply: all_sig_cond_dep. Qed.
Section RelationProperties.
(* Caveat: reflexive should not be used to state lemmas, as auto and trivial *)
(* will not expand the constant. *)
Variable T : Type.
Variable R : rel T.
Definition total := forall x y, R x y || R y x.
Definition transitive := forall y x z, R x y -> R y z -> R x z.
Definition symmetric := forall x y, R x y = R y x.
Definition antisymmetric := forall x y, R x y && R y x -> x = y.
Definition pre_symmetric := forall x y, R x y -> R y x.
Lemma symmetric_from_pre : pre_symmetric -> symmetric.
Proof. by move=> symR x y; apply/idP/idP; apply: symR. Qed.
Definition reflexive := forall x, R x x.
Definition irreflexive := forall x, R x x = false.
Definition left_transitive := forall x y, R x y -> R x =1 R y.
Definition right_transitive := forall x y, R x y -> R^~ x =1 R^~ y.
Section PER.
Hypotheses (symR : symmetric) (trR : transitive).
Lemma sym_left_transitive : left_transitive.
Proof. by move=> x y Rxy z; apply/idP/idP; apply: trR; rewrite // symR. Qed.
Lemma sym_right_transitive : right_transitive.
Proof. by move=> x y /sym_left_transitive Rxy z; rewrite !(symR z) Rxy. Qed.
End PER.
(* We define the equivalence property with prenex quantification so that it *)
(* can be localized using the {in ..., ..} form defined below. *)
Definition equivalence_rel := forall x y z, R z z * (R x y -> R x z = R y z).
Lemma equivalence_relP : equivalence_rel <-> reflexive /\ left_transitive.
Proof.
split=> [eqiR | [Rxx trR] x y z]; last by split=> [|/trR->].
by split=> [x | x y Rxy z]; [rewrite (eqiR x x x) | rewrite (eqiR x y z)].
Qed.
End RelationProperties.
Lemma rev_trans T (R : rel T) : transitive R -> transitive (fun x y => R y x).
Proof. by move=> trR x y z Ryx Rzy; apply: trR Rzy Ryx. Qed.
(* Property localization *)
Local Notation "{ 'all1' P }" := (forall x, P x : Prop) (at level 0).
Local Notation "{ 'all2' P }" := (forall x y, P x y : Prop) (at level 0).
Local Notation "{ 'all3' P }" := (forall x y z, P x y z: Prop) (at level 0).
Local Notation ph := (phantom _).
Section LocalProperties.
Variables T1 T2 T3 : Type.
Variables (d1 : mem_pred T1) (d2 : mem_pred T2) (d3 : mem_pred T3).
Local Notation ph := (phantom Prop).
Definition prop_for (x : T1) P & ph {all1 P} := P x.
Lemma forE x P phP : @prop_for x P phP = P x. Proof. by []. Qed.
Definition prop_in1 P & ph {all1 P} :=
forall x, in_mem x d1 -> P x.
Definition prop_in11 P & ph {all2 P} :=
forall x y, in_mem x d1 -> in_mem y d2 -> P x y.
Definition prop_in2 P & ph {all2 P} :=
forall x y, in_mem x d1 -> in_mem y d1 -> P x y.
Definition prop_in111 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d2 -> in_mem z d3 -> P x y z.
Definition prop_in12 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d2 -> in_mem z d2 -> P x y z.
Definition prop_in21 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d1 -> in_mem z d2 -> P x y z.
Definition prop_in3 P & ph {all3 P} :=
forall x y z, in_mem x d1 -> in_mem y d1 -> in_mem z d1 -> P x y z.
Variable f : T1 -> T2.
Definition prop_on1 Pf P & phantom T3 (Pf f) & ph {all1 P} :=
forall x, in_mem (f x) d2 -> P x.
Definition prop_on2 Pf P & phantom T3 (Pf f) & ph {all2 P} :=
forall x y, in_mem (f x) d2 -> in_mem (f y) d2 -> P x y.
End LocalProperties.
Definition inPhantom := Phantom Prop.
Definition onPhantom T P (x : T) := Phantom Prop (P x).
Definition bijective_in aT rT (d : mem_pred aT) (f : aT -> rT) :=
exists2 g, prop_in1 d (inPhantom (cancel f g))
& prop_on1 d (Phantom _ (cancel g)) (onPhantom (cancel g) f).
Definition bijective_on aT rT (cd : mem_pred rT) (f : aT -> rT) :=
exists2 g, prop_on1 cd (Phantom _ (cancel f)) (onPhantom (cancel f) g)
& prop_in1 cd (inPhantom (cancel g f)).
Notation "{ 'for' x , P }" :=
(prop_for x (inPhantom P))
(at level 0, format "{ 'for' x , P }") : type_scope.
Notation "{ 'in' d , P }" :=
(prop_in1 (mem d) (inPhantom P))
(at level 0, format "{ 'in' d , P }") : type_scope.
Notation "{ 'in' d1 & d2 , P }" :=
(prop_in11 (mem d1) (mem d2) (inPhantom P))
(at level 0, format "{ 'in' d1 & d2 , P }") : type_scope.
Notation "{ 'in' d & , P }" :=
(prop_in2 (mem d) (inPhantom P))
(at level 0, format "{ 'in' d & , P }") : type_scope.
Notation "{ 'in' d1 & d2 & d3 , P }" :=
(prop_in111 (mem d1) (mem d2) (mem d3) (inPhantom P))
(at level 0, format "{ 'in' d1 & d2 & d3 , P }") : type_scope.
Notation "{ 'in' d1 & & d3 , P }" :=
(prop_in21 (mem d1) (mem d3) (inPhantom P))
(at level 0, format "{ 'in' d1 & & d3 , P }") : type_scope.
Notation "{ 'in' d1 & d2 & , P }" :=
(prop_in12 (mem d1) (mem d2) (inPhantom P))
(at level 0, format "{ 'in' d1 & d2 & , P }") : type_scope.
Notation "{ 'in' d & & , P }" :=
(prop_in3 (mem d) (inPhantom P))
(at level 0, format "{ 'in' d & & , P }") : type_scope.
Notation "{ 'on' cd , P }" :=
(prop_on1 (mem cd) (inPhantom P) (inPhantom P))
(at level 0, format "{ 'on' cd , P }") : type_scope.
Notation "{ 'on' cd & , P }" :=
(prop_on2 (mem cd) (inPhantom P) (inPhantom P))
(at level 0, format "{ 'on' cd & , P }") : type_scope.
Local Arguments onPhantom {_%type_scope} _ _.
Notation "{ 'on' cd , P & g }" :=
(prop_on1 (mem cd) (Phantom (_ -> Prop) P) (onPhantom P g))
(at level 0, format "{ 'on' cd , P & g }") : type_scope.
Notation "{ 'in' d , 'bijective' f }" := (bijective_in (mem d) f)
(at level 0, f at level 8,
format "{ 'in' d , 'bijective' f }") : type_scope.
Notation "{ 'on' cd , 'bijective' f }" := (bijective_on (mem cd) f)
(at level 0, f at level 8,
format "{ 'on' cd , 'bijective' f }") : type_scope.
(* Weakening and monotonicity lemmas for localized predicates. *)
(* Note that using these lemmas in backward reasoning will force expansion of *)
(* the predicate definition, as Coq needs to expose the quantifier to apply *)
(* these lemmas. We define a few specialized variants to avoid this for some *)
(* of the ssrfun predicates. *)
Section LocalGlobal.
Variables T1 T2 T3 : predArgType.
Variables (D1 : pred T1) (D2 : pred T2) (D3 : pred T3).
Variables (d1 d1' : mem_pred T1) (d2 d2' : mem_pred T2) (d3 d3' : mem_pred T3).
Variables (f f' : T1 -> T2) (g : T2 -> T1) (h : T3).
Variables (P1 : T1 -> Prop) (P2 : T1 -> T2 -> Prop).
Variable P3 : T1 -> T2 -> T3 -> Prop.
Variable Q1 : (T1 -> T2) -> T1 -> Prop.
Variable Q1l : (T1 -> T2) -> T3 -> T1 -> Prop.
Variable Q2 : (T1 -> T2) -> T1 -> T1 -> Prop.
Hypothesis sub1 : sub_mem d1 d1'.
Hypothesis sub2 : sub_mem d2 d2'.
Hypothesis sub3 : sub_mem d3 d3'.
Lemma in1W : {all1 P1} -> {in D1, {all1 P1}}.
Proof. by move=> ? ?. Qed.
Lemma in2W : {all2 P2} -> {in D1 & D2, {all2 P2}}.
Proof. by move=> ? ?. Qed.
Lemma in3W : {all3 P3} -> {in D1 & D2 & D3, {all3 P3}}.
Proof. by move=> ? ?. Qed.
Lemma in1T : {in T1, {all1 P1}} -> {all1 P1}.
Proof. by move=> ? ?; auto. Qed.
Lemma in2T : {in T1 & T2, {all2 P2}} -> {all2 P2}.
Proof. by move=> ? ?; auto. Qed.
Lemma in3T : {in T1 & T2 & T3, {all3 P3}} -> {all3 P3}.
Proof. by move=> ? ?; auto. Qed.
Lemma sub_in1 (Ph : ph {all1 P1}) : prop_in1 d1' Ph -> prop_in1 d1 Ph.
Proof. by move=> allP x /sub1; apply: allP. Qed.
Lemma sub_in11 (Ph : ph {all2 P2}) : prop_in11 d1' d2' Ph -> prop_in11 d1 d2 Ph.
Proof. by move=> allP x1 x2 /sub1 d1x1 /sub2; apply: allP. Qed.
Lemma sub_in111 (Ph : ph {all3 P3}) :
prop_in111 d1' d2' d3' Ph -> prop_in111 d1 d2 d3 Ph.
Proof. by move=> allP x1 x2 x3 /sub1 d1x1 /sub2 d2x2 /sub3; apply: allP. Qed.
Let allQ1 f'' := {all1 Q1 f''}.
Let allQ1l f'' h' := {all1 Q1l f'' h'}.
Let allQ2 f'' := {all2 Q2 f''}.
Lemma on1W : allQ1 f -> {on D2, allQ1 f}. Proof. by move=> ? ?. Qed.
Lemma on1lW : allQ1l f h -> {on D2, allQ1l f & h}. Proof. by move=> ? ?. Qed.
Lemma on2W : allQ2 f -> {on D2 &, allQ2 f}. Proof. by move=> ? ?. Qed.
Lemma on1T : {on T2, allQ1 f} -> allQ1 f. Proof. by move=> ? ?; auto. Qed.
Lemma on1lT : {on T2, allQ1l f & h} -> allQ1l f h.
Proof. by move=> ? ?; auto. Qed.
Lemma on2T : {on T2 &, allQ2 f} -> allQ2 f.
Proof. by move=> ? ?; auto. Qed.
Lemma subon1 (Phf : ph (allQ1 f)) (Ph : ph (allQ1 f)) :
prop_on1 d2' Phf Ph -> prop_on1 d2 Phf Ph.
Proof. by move=> allQ x /sub2; apply: allQ. Qed.
Lemma subon1l (Phf : ph (allQ1l f)) (Ph : ph (allQ1l f h)) :
prop_on1 d2' Phf Ph -> prop_on1 d2 Phf Ph.
Proof. by move=> allQ x /sub2; apply: allQ. Qed.
Lemma subon2 (Phf : ph (allQ2 f)) (Ph : ph (allQ2 f)) :
prop_on2 d2' Phf Ph -> prop_on2 d2 Phf Ph.
Proof. by move=> allQ x y /sub2=> d2fx /sub2; apply: allQ. Qed.
Lemma can_in_inj : {in D1, cancel f g} -> {in D1 &, injective f}.
Proof. by move=> fK x y /fK{2}<- /fK{2}<- ->. Qed.
Lemma canLR_in x y : {in D1, cancel f g} -> y \in D1 -> x = f y -> g x = y.
Proof. by move=> fK D1y ->; rewrite fK. Qed.
Lemma canRL_in x y : {in D1, cancel f g} -> x \in D1 -> f x = y -> x = g y.
Proof. by move=> fK D1x <-; rewrite fK. Qed.
Lemma on_can_inj : {on D2, cancel f & g} -> {on D2 &, injective f}.
Proof. by move=> fK x y /fK{2}<- /fK{2}<- ->. Qed.
Lemma canLR_on x y : {on D2, cancel f & g} -> f y \in D2 -> x = f y -> g x = y.
Proof. by move=> fK D2fy ->; rewrite fK. Qed.
Lemma canRL_on x y : {on D2, cancel f & g} -> f x \in D2 -> f x = y -> x = g y.
Proof. by move=> fK D2fx <-; rewrite fK. Qed.
Lemma inW_bij : bijective f -> {in D1, bijective f}.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma onW_bij : bijective f -> {on D2, bijective f}.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma inT_bij : {in T1, bijective f} -> bijective f.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma onT_bij : {on T2, bijective f} -> bijective f.
Proof. by case=> g' fK g'K; exists g' => * ? *; auto. Qed.
Lemma sub_in_bij (D1' : pred T1) :
{subset D1 <= D1'} -> {in D1', bijective f} -> {in D1, bijective f}.
Proof.
by move=> subD [g' fK g'K]; exists g' => x; move/subD; [apply: fK | apply: g'K].
Qed.
Lemma subon_bij (D2' : pred T2) :
{subset D2 <= D2'} -> {on D2', bijective f} -> {on D2, bijective f}.
Proof.
by move=> subD [g' fK g'K]; exists g' => x; move/subD; [apply: fK | apply: g'K].
Qed.
End LocalGlobal.
Lemma sub_in2 T d d' (P : T -> T -> Prop) :
sub_mem d d' -> forall Ph : ph {all2 P}, prop_in2 d' Ph -> prop_in2 d Ph.
Proof. by move=> /= sub_dd'; apply: sub_in11. Qed.
Lemma sub_in3 T d d' (P : T -> T -> T -> Prop) :
sub_mem d d' -> forall Ph : ph {all3 P}, prop_in3 d' Ph -> prop_in3 d Ph.
Proof. by move=> /= sub_dd'; apply: sub_in111. Qed.
Lemma sub_in12 T1 T d1 d1' d d' (P : T1 -> T -> T -> Prop) :
sub_mem d1 d1' -> sub_mem d d' ->
forall Ph : ph {all3 P}, prop_in12 d1' d' Ph -> prop_in12 d1 d Ph.
Proof. by move=> /= sub1 sub; apply: sub_in111. Qed.
Lemma sub_in21 T T3 d d' d3 d3' (P : T -> T -> T3 -> Prop) :
sub_mem d d' -> sub_mem d3 d3' ->
forall Ph : ph {all3 P}, prop_in21 d' d3' Ph -> prop_in21 d d3 Ph.
Proof. by move=> /= sub sub3; apply: sub_in111. Qed.
Lemma equivalence_relP_in T (R : rel T) (A : pred T) :
{in A & &, equivalence_rel R}
<-> {in A, reflexive R} /\ {in A &, forall x y, R x y -> {in A, R x =1 R y}}.
Proof.
split=> [eqiR | [Rxx trR] x y z *]; last by split=> [|/trR-> //]; apply: Rxx.
by split=> [x Ax|x y Ax Ay Rxy z Az]; [rewrite (eqiR x x) | rewrite (eqiR x y)].
Qed.
Section MonoHomoMorphismTheory.
Variables (aT rT sT : Type) (f : aT -> rT) (g : rT -> aT).
Variables (aP : pred aT) (rP : pred rT) (aR : rel aT) (rR : rel rT).
Lemma monoW : {mono f : x / aP x >-> rP x} -> {homo f : x / aP x >-> rP x}.
Proof. by move=> hf x ax; rewrite hf. Qed.
Lemma mono2W :
{mono f : x y / aR x y >-> rR x y} -> {homo f : x y / aR x y >-> rR x y}.
Proof. by move=> hf x y axy; rewrite hf. Qed.
Hypothesis fgK : cancel g f.
Lemma homoRL :
{homo f : x y / aR x y >-> rR x y} -> forall x y, aR (g x) y -> rR x (f y).
Proof. by move=> Hf x y /Hf; rewrite fgK. Qed.
Lemma homoLR :
{homo f : x y / aR x y >-> rR x y} -> forall x y, aR x (g y) -> rR (f x) y.
Proof. by move=> Hf x y /Hf; rewrite fgK. Qed.
Lemma homo_mono :
{homo f : x y / aR x y >-> rR x y} -> {homo g : x y / rR x y >-> aR x y} ->
{mono g : x y / rR x y >-> aR x y}.
Proof.
move=> mf mg x y; case: (boolP (rR _ _))=> [/mg //|].
by apply: contraNF=> /mf; rewrite !fgK.
Qed.
Lemma monoLR :
{mono f : x y / aR x y >-> rR x y} -> forall x y, rR (f x) y = aR x (g y).
Proof. by move=> mf x y; rewrite -{1}[y]fgK mf. Qed.
Lemma monoRL :
{mono f : x y / aR x y >-> rR x y} -> forall x y, rR x (f y) = aR (g x) y.
Proof. by move=> mf x y; rewrite -{1}[x]fgK mf. Qed.
Lemma can_mono :
{mono f : x y / aR x y >-> rR x y} -> {mono g : x y / rR x y >-> aR x y}.
Proof. by move=> mf x y /=; rewrite -mf !fgK. Qed.
End MonoHomoMorphismTheory.
Section MonoHomoMorphismTheory_in.
Variables (aT rT sT : predArgType) (f : aT -> rT) (g : rT -> aT).
Variable (aD : pred aT).
Variable (aP : pred aT) (rP : pred rT) (aR : rel aT) (rR : rel rT).
Notation rD := [pred x | g x \in aD].
Lemma monoW_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in aD &, {homo f : x y / aR x y >-> rR x y}}.
Proof. by move=> hf x y hx hy axy; rewrite hf. Qed.
Lemma mono2W_in :
{in aD, {mono f : x / aP x >-> rP x}} ->
{in aD, {homo f : x / aP x >-> rP x}}.
Proof. by move=> hf x hx ax; rewrite hf. Qed.
Hypothesis fgK_on : {on aD, cancel g & f}.
Lemma homoRL_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in rD & aD, forall x y, aR (g x) y -> rR x (f y)}.
Proof. by move=> Hf x y hx hy /Hf; rewrite fgK_on //; apply. Qed.
Lemma homoLR_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in aD & rD, forall x y, aR x (g y) -> rR (f x) y}.
Proof. by move=> Hf x y hx hy /Hf; rewrite fgK_on //; apply. Qed.
Lemma homo_mono_in :
{in aD &, {homo f : x y / aR x y >-> rR x y}} ->
{in rD &, {homo g : x y / rR x y >-> aR x y}} ->
{in rD &, {mono g : x y / rR x y >-> aR x y}}.
Proof.
move=> mf mg x y hx hy; case: (boolP (rR _ _))=> [/mg //|]; first exact.
by apply: contraNF=> /mf; rewrite !fgK_on //; apply.
Qed.
Lemma monoLR_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in aD & rD, forall x y, rR (f x) y = aR x (g y)}.
Proof. by move=> mf x y hx hy; rewrite -{1}[y]fgK_on // mf. Qed.
Lemma monoRL_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in rD & aD, forall x y, rR x (f y) = aR (g x) y}.
Proof. by move=> mf x y hx hy; rewrite -{1}[x]fgK_on // mf. Qed.
Lemma can_mono_in :
{in aD &, {mono f : x y / aR x y >-> rR x y}} ->
{in rD &, {mono g : x y / rR x y >-> aR x y}}.
Proof. by move=> mf x y hx hy /=; rewrite -mf // !fgK_on. Qed.
End MonoHomoMorphismTheory_in.
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ledtest_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
// ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0.v
// This file was auto-generated from alt_mem_if_ddr3_tg_ed_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using SOPC Builder version 11.0sp1 208 at 2011.09.28.12:47:39
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_reset_n, // afi_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire [1:0] mem_dm, // .mem_dm
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [15:0] mem_dq, // .mem_dq
inout wire [1:0] mem_dqs, // .mem_dqs
inout wire [1:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire local_init_done, // emif_status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup
output wire drv_status_pass, // drv_status.pass
output wire drv_status_fail, // .fail
output wire drv_status_test_complete, // .test_complete
output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
input wire local_powerdn_req // .local_powerdn_req
);
wire [2:0] d0_avl_burstcount; // d0:avl_size -> d0_avl_translator:av_burstcount
wire d0_avl_waitrequest; // d0_avl_translator:av_waitrequest -> d0:avl_ready
wire [63:0] d0_avl_writedata; // d0:avl_wdata -> d0_avl_translator:av_writedata
wire [26:0] d0_avl_address; // d0:avl_addr -> d0_avl_translator:av_address
wire d0_avl_write; // d0:avl_write_req -> d0_avl_translator:av_write
wire d0_avl_beginbursttransfer; // d0:avl_burstbegin -> d0_avl_translator:av_beginbursttransfer
wire d0_avl_read; // d0:avl_read_req -> d0_avl_translator:av_read
wire [63:0] d0_avl_readdata; // d0_avl_translator:av_readdata -> d0:avl_rdata
wire [7:0] d0_avl_byteenable; // d0:avl_be -> d0_avl_translator:av_byteenable
wire d0_avl_readdatavalid; // d0_avl_translator:av_readdatavalid -> d0:avl_rdata_valid
wire d0_avl_translator_avalon_universal_master_0_waitrequest; // if0_avl_translator:uav_waitrequest -> d0_avl_translator:uav_waitrequest
wire [5:0] d0_avl_translator_avalon_universal_master_0_burstcount; // d0_avl_translator:uav_burstcount -> if0_avl_translator:uav_burstcount
wire [63:0] d0_avl_translator_avalon_universal_master_0_writedata; // d0_avl_translator:uav_writedata -> if0_avl_translator:uav_writedata
wire [26:0] d0_avl_translator_avalon_universal_master_0_address; // d0_avl_translator:uav_address -> if0_avl_translator:uav_address
wire d0_avl_translator_avalon_universal_master_0_lock; // d0_avl_translator:uav_lock -> if0_avl_translator:uav_lock
wire d0_avl_translator_avalon_universal_master_0_write; // d0_avl_translator:uav_write -> if0_avl_translator:uav_write
wire d0_avl_translator_avalon_universal_master_0_read; // d0_avl_translator:uav_read -> if0_avl_translator:uav_read
wire [63:0] d0_avl_translator_avalon_universal_master_0_readdata; // if0_avl_translator:uav_readdata -> d0_avl_translator:uav_readdata
wire d0_avl_translator_avalon_universal_master_0_debugaccess; // d0_avl_translator:uav_debugaccess -> if0_avl_translator:uav_debugaccess
wire [7:0] d0_avl_translator_avalon_universal_master_0_byteenable; // d0_avl_translator:uav_byteenable -> if0_avl_translator:uav_byteenable
wire d0_avl_translator_avalon_universal_master_0_readdatavalid; // if0_avl_translator:uav_readdatavalid -> d0_avl_translator:uav_readdatavalid
wire if0_avl_translator_avalon_anti_slave_0_waitrequest; // if0:avl_ready -> if0_avl_translator:av_waitrequest
wire [2:0] if0_avl_translator_avalon_anti_slave_0_burstcount; // if0_avl_translator:av_burstcount -> if0:avl_size
wire [63:0] if0_avl_translator_avalon_anti_slave_0_writedata; // if0_avl_translator:av_writedata -> if0:avl_wdata
wire [23:0] if0_avl_translator_avalon_anti_slave_0_address; // if0_avl_translator:av_address -> if0:avl_addr
wire if0_avl_translator_avalon_anti_slave_0_write; // if0_avl_translator:av_write -> if0:avl_write_req
wire if0_avl_translator_avalon_anti_slave_0_beginbursttransfer; // if0_avl_translator:av_beginbursttransfer -> if0:avl_burstbegin
wire if0_avl_translator_avalon_anti_slave_0_read; // if0_avl_translator:av_read -> if0:avl_read_req
wire [63:0] if0_avl_translator_avalon_anti_slave_0_readdata; // if0:avl_rdata -> if0_avl_translator:av_readdata
wire if0_avl_translator_avalon_anti_slave_0_readdatavalid; // if0:avl_rdata_valid -> if0_avl_translator:av_readdatavalid
wire [7:0] if0_avl_translator_avalon_anti_slave_0_byteenable; // if0_avl_translator:av_byteenable -> if0:avl_be
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [d0_avl_translator:reset, if0_avl_translator:reset]
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0 if0 (
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.avl_ready (if0_avl_translator_avalon_anti_slave_0_waitrequest), // avl.waitrequest_n
.avl_burstbegin (if0_avl_translator_avalon_anti_slave_0_beginbursttransfer), // .beginbursttransfer
.avl_addr (if0_avl_translator_avalon_anti_slave_0_address), // .address
.avl_rdata_valid (if0_avl_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.avl_rdata (if0_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.avl_wdata (if0_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.avl_be (if0_avl_translator_avalon_anti_slave_0_byteenable), // .byteenable
.avl_read_req (if0_avl_translator_avalon_anti_slave_0_read), // .read
.avl_write_req (if0_avl_translator_avalon_anti_slave_0_write), // .write
.avl_size (if0_avl_translator_avalon_anti_slave_0_burstcount), // .burstcount
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
.local_powerdn_req (local_powerdn_req) // .local_powerdn_req
);
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_d0 #(
.DEVICE_FAMILY ("Stratix IV"),
.TG_AVL_DATA_WIDTH (64),
.TG_AVL_ADDR_WIDTH (27),
.TG_AVL_WORD_ADDR_WIDTH (24),
.TG_AVL_SIZE_WIDTH (3),
.TG_AVL_BE_WIDTH (8),
.TG_GEN_BYTE_ADDR (1),
.TG_NUM_DRIVER_LOOP (1),
.TG_RANDOM_BYTE_ENABLE (1),
.TG_ENABLE_READ_COMPARE (1),
.TG_POWER_OF_TWO_BURSTS_ONLY (0),
.TG_BURST_ON_BURST_BOUNDARY (0),
.TG_TIMEOUT_COUNTER_WIDTH (30),
.TG_MAX_READ_LATENCY (20),
.TG_SINGLE_RW_SEQ_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_ADDR_COUNT (32),
.TG_SINGLE_RW_RAND_SEQ_ADDR_COUNT (32),
.TG_BLOCK_RW_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_ADDR_COUNT (8),
.TG_BLOCK_RW_RAND_SEQ_ADDR_COUNT (8),
.TG_BLOCK_RW_BLOCK_SIZE (8),
.TG_TEMPLATE_STAGE_COUNT (4),
.TG_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_SEQ_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_SEQ_ADDR_GEN_MIN_BURSTCOUNT (1),
.TG_RAND_SEQ_ADDR_GEN_MAX_BURSTCOUNT (4),
.TG_RAND_SEQ_ADDR_GEN_RAND_ADDR_PERCENT (50)
) d0 (
.clk (afi_clk), // avl_clock.clk
.reset_n (afi_reset_n), // avl_reset.reset_n
.pass (drv_status_pass), // status.pass
.fail (drv_status_fail), // .fail
.test_complete (drv_status_test_complete), // .test_complete
.avl_ready (~d0_avl_waitrequest), // avl.waitrequest_n
.avl_addr (d0_avl_address), // .address
.avl_size (d0_avl_burstcount), // .burstcount
.avl_wdata (d0_avl_writedata), // .writedata
.avl_rdata (d0_avl_readdata), // .readdata
.avl_write_req (d0_avl_write), // .write
.avl_read_req (d0_avl_read), // .read
.avl_rdata_valid (d0_avl_readdatavalid), // .readdatavalid
.avl_be (d0_avl_byteenable), // .byteenable
.avl_burstbegin (d0_avl_beginbursttransfer) // .beginbursttransfer
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (64),
.AV_BURSTCOUNT_W (3),
.AV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (1),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) d0_avl_translator (
.clk (afi_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (d0_avl_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (d0_avl_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (d0_avl_translator_avalon_universal_master_0_read), // .read
.uav_write (d0_avl_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (d0_avl_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (d0_avl_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (d0_avl_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (d0_avl_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (d0_avl_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (d0_avl_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (d0_avl_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (d0_avl_address), // avalon_anti_master_0.address
.av_waitrequest (d0_avl_waitrequest), // .waitrequest
.av_burstcount (d0_avl_burstcount), // .burstcount
.av_byteenable (d0_avl_byteenable), // .byteenable
.av_beginbursttransfer (d0_avl_beginbursttransfer), // .beginbursttransfer
.av_read (d0_avl_read), // .read
.av_readdata (d0_avl_readdata), // .readdata
.av_readdatavalid (d0_avl_readdatavalid), // .readdatavalid
.av_write (d0_avl_write), // .write
.av_writedata (d0_avl_writedata), // .writedata
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (3),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) if0_avl_translator (
.clk (afi_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (d0_avl_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (d0_avl_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (d0_avl_translator_avalon_universal_master_0_read), // .read
.uav_write (d0_avl_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (d0_avl_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (d0_avl_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (d0_avl_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (d0_avl_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (d0_avl_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (d0_avl_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (d0_avl_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (if0_avl_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (if0_avl_translator_avalon_anti_slave_0_write), // .write
.av_read (if0_avl_translator_avalon_anti_slave_0_read), // .read
.av_readdata (if0_avl_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (if0_avl_translator_avalon_anti_slave_0_writedata), // .writedata
.av_beginbursttransfer (if0_avl_translator_avalon_anti_slave_0_beginbursttransfer), // .beginbursttransfer
.av_burstcount (if0_avl_translator_avalon_anti_slave_0_burstcount), // .burstcount
.av_byteenable (if0_avl_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (if0_avl_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (~if0_avl_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable () // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2)
) rst_controller (
.reset_in0 (~afi_reset_n), // reset_in0.reset
.clk (afi_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_de5.v
// Version: 1.00a
// Verilog Standard: Verilog-2001
// Description: Wrapper file for all riffa logic for Altera DE5 boards
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "altera.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_de5
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Quartus IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
// Interface: Altera RX
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
// Interface: Altera TX
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
// Interface: Altera Config
input [`SIG_CFG_CTL_W-1:0] TL_CFG_CTL,
input [`SIG_CFG_ADD_W-1:0] TL_CFG_ADD,
input [`SIG_CFG_STS_W-1:0] TL_CFG_STS,
// Interface: Altera Flow Control
input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER,
input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA,
// Interface: Altera Interrupt
input APP_MSI_ACK,
output APP_MSI_REQ,
// Interface: Altera CLK/RESET
input PLD_CLK,
input RESET_STATUS,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN // Channel write data has been recieved
);
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
localparam C_VENDOR = "ALTERA";
localparam C_ALTERA_TX_READY_LATENCY = 2;
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
wire clk;
wire rst_in;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire wRxTlpReady;
wire [C_PCI_DATA_WIDTH-1:0] wRxTlp;
wire wRxTlpEndFlag;
wire [`SIG_OFFSET_W-1:0] wRxTlpEndOffset;
wire wRxTlpStartFlag;
wire [`SIG_OFFSET_W-1:0] wRxTlpStartOffset;
wire wRxTlpValid;
wire [`SIG_BARDECODE_W-1:0] wRxTlpBarDecode;
wire wTxTlpReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxTlp;
wire wTxTlpEndFlag;
wire [`SIG_OFFSET_W-1:0] wTxTlpEndOffset;
wire wTxTlpStartFlag;
wire [`SIG_OFFSET_W-1:0] wTxTlpStartOffset;
wire wTxTlpValid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = PLD_CLK;
assign rst_in = RESET_STATUS;
translation_altera
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(
// Outputs
.RX_TLP (wRxTlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (wRxTlpValid),
.RX_TLP_START_FLAG (wRxTlpStartFlag),
.RX_TLP_START_OFFSET (wRxTlpStartOffset[`SIG_OFFSET_W-1:0]),
.RX_TLP_END_FLAG (wRxTlpEndFlag),
.RX_TLP_END_OFFSET (wRxTlpEndOffset[`SIG_OFFSET_W-1:0]),
.RX_TLP_BAR_DECODE (wRxTlpBarDecode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (wTxTlpReady),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (wRxTlpReady),
.TX_TLP (wTxTlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (wTxTlpValid),
.TX_TLP_START_FLAG (wTxTlpStartFlag),
.TX_TLP_START_OFFSET (wTxTlpStartOffset[`SIG_OFFSET_W-1:0]),
.TX_TLP_END_FLAG (wTxTlpEndFlag),
.TX_TLP_END_OFFSET (wTxTlpEndOffset[`SIG_OFFSET_W-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
// Inputs
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (TL_CFG_ADD[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (TL_CFG_STS[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[`SIG_FC_CPLH_W-1:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[`SIG_FC_CPLD_W-1:0]),
.APP_MSI_ACK (APP_MSI_ACK));
engine_layer
#(// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
// Unconnected Outputs
.TX_TLP (wTxTlp),
.TX_TLP_VALID (wTxTlpValid),
.TX_TLP_START_FLAG (wTxTlpStartFlag),
.TX_TLP_START_OFFSET (wTxTlpStartOffset),
.TX_TLP_END_FLAG (wTxTlpEndFlag),
.TX_TLP_END_OFFSET (wTxTlpEndOffset),
.RX_TLP_READY (wRxTlpReady),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (wRxTlp),
.RX_TLP_VALID (wRxTlpValid),
.RX_TLP_START_FLAG (wRxTlpStartFlag),
.RX_TLP_START_OFFSET (wRxTlpStartOffset),
.RX_TLP_END_FLAG (wRxTlpEndFlag),
.RX_TLP_END_OFFSET (wRxTlpEndOffset),
.RX_TLP_BAR_DECODE (wRxTlpBarDecode),
.TX_TLP_READY (wTxTlpReady),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../engine/" "../../riffa/" "../../trans")
// End:
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkgn_nstep_cnt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_clkgn_nstep_cnt
//
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_clsp_clkgn_nstep_cnt(/*AUTOARG*/
// Outputs
nstep_sel,
// Inputs
io_pwron_rst_l, clk, jtag_clock_dr, jtag_nstep_count,
jtag_nstep_domain, jtag_nstep_vld, capture_l, testmode_l,
start_clk_early_jl, shadreg_div_mult, force_cken
);
// global inputs
input io_pwron_rst_l;
input clk;
input jtag_clock_dr;
input [3:0] jtag_nstep_count;
input jtag_nstep_domain;
input jtag_nstep_vld;
input capture_l;
input testmode_l;
input start_clk_early_jl;
input [13:0] shadreg_div_mult;
input force_cken;
output nstep_sel;
wire cnt_ld_sync;
wire cnt_ld_sync_dly_l;
wire cnt_ld_1sht;
wire [3:0] nstep_init_cnt_nxt;
wire [3:0] nstep_init_cnt;
wire [3:0] nstep_cnt_nxt;
wire [3:0] nstep_cnt;
wire [3:0] nstep_cnt_minus_1;
wire trigger_sync;
wire nstep_start;
wire nstep_start_1sht;
wire nstep_start_1sht_dly;
wire nstep_start_dly;
wire nstep_start_dly1;
wire nstep_start_nxt;
wire nstep_en_nxt;
wire nstep_active;
wire coin_edge_nxt;
wire nstep_sel_pre;
wire cnt_ld;
wire cnt_ld_nxt;
wire [13:0] lcm_cnt_minus_1;
wire [13:0] lcm_cnt_nxt;
wire [13:0] lcm_cnt;
wire coin_edge;
wire force_cken_l;
// -----------------------------------------------
//
// Synchronizers
//
// -----------------------------------------------
// tck -> clk
//assign nstep_active = jtag_clock_dr & ~capture_l ;
// to get rid of comb. logic
dffrl_async_ns u_nstep_active_nsr(
.din (~capture_l),
.rst_l(io_pwron_rst_l),
.clk (jtag_clock_dr),
.q (nstep_active));
ctu_synchronizer u_jtag_nstep_vld_nsr(
.presyncdata(jtag_nstep_vld),
.syncdata (cnt_ld_sync),
.clk(clk)
);
ctu_synchronizer u_jtag_trigger_nsr(
.presyncdata(nstep_active),
.syncdata (trigger_sync),
.clk(clk)
);
// -----------------------------------------------
//
// Synchronization checks
//
// -----------------------------------------------
// start the clock relative to coincident edge
assign nstep_start_nxt = coin_edge? trigger_sync: nstep_start;
dffrl_async_ns u_nstep_start_nsr(
.din (nstep_start_nxt),
.rst_l(io_pwron_rst_l),
.clk (clk),
.q (nstep_start));
dff_ns u_nstep_start_dly_nsr(
.din (nstep_start),
.clk (clk),
.q (nstep_start_dly));
assign nstep_start_1sht = nstep_start & ~nstep_start_dly ;
dff_ns u_nstep_start_dly1_nsr(
.din (nstep_start_dly),
.clk (clk),
.q (nstep_start_dly1));
assign nstep_start_1sht_dly = nstep_start_dly & ~nstep_start_dly1 ;
// -----------------------------------------------
//
// nstep_cnt
//
// -----------------------------------------------
dff_ns u_cnt_ld_sync_nsr(
.din (~cnt_ld_sync),
.clk (clk),
.q(cnt_ld_sync_dly_l));
assign cnt_ld_1sht = cnt_ld_sync & cnt_ld_sync_dly_l;
// jtag_nstep_domain and jtag_nstep_count must hold for 3 cycles min.
assign nstep_init_cnt_nxt = cnt_ld_1sht & jtag_nstep_domain ? jtag_nstep_count:
nstep_init_cnt;
dffrl_async_ns #(4) u_nstep_init_cnt_nsr(
.din (nstep_init_cnt_nxt),
.clk (clk),
.rst_l(io_pwron_rst_l),
.q(nstep_init_cnt));
// nstep =1 , nstep > 0 ; nstep = 15
assign nstep_en_nxt = ((nstep_init_cnt == 4'b0001) & nstep_start_1sht_dly) | // delay start if cnt == 1
(|(nstep_cnt[3:1])) // when cnt >= 1
| (&(nstep_init_cnt[3:0])); // always enable if count == 15
dffrl_async_ns u_nstep_en_nsr(
.din (nstep_en_nxt),
.clk (clk),
.rst_l(io_pwron_rst_l),
.q(nstep_sel_pre));
//assign nstep_sel = nstep_sel_pre & testmode_l;
ctu_inv u_force_cken_l(.a (force_cken), .z(force_cken_l));
ctu_and3 u_nstep_sel (.a (nstep_sel_pre), .b(force_cken_l), .c(testmode_l), .z(nstep_sel));
// clock gating is done in clksw block
//ctu_and2 u_nstep_clk_gated (.a (clk), .b(nstep_en), .z(nstep_clk));
assign nstep_cnt_minus_1 = nstep_cnt - 4'b0001;
assign nstep_cnt_nxt = nstep_start_1sht ? nstep_init_cnt :
nstep_sel & (|(nstep_init_cnt[3:0])) ? nstep_cnt_minus_1:
nstep_cnt;
dffrl_async_ns #(4) u_nstep_cnt_nsr(
.din (nstep_cnt_nxt),
.clk (clk),
.rst_l(io_pwron_rst_l),
.q(nstep_cnt));
// -----------------------------------------------
//
// lcm cnt for repeatability
// start nstep clock relative to coincident edge
//
// -----------------------------------------------
assign cnt_ld_nxt = cnt_ld ? 1'b0: cnt_ld;
dffsl_async_ns u_cnt_ld_nsr(
.din (cnt_ld_nxt),
.clk (clk),
.set_l (start_clk_early_jl),
.q(cnt_ld));
assign lcm_cnt_minus_1 = lcm_cnt - 14'h0001;
assign lcm_cnt_nxt = cnt_ld? shadreg_div_mult[13:0]:
(|(lcm_cnt[13:1])) ? lcm_cnt_minus_1:
shadreg_div_mult[13:0];
dffrl_async_ns #(14) u_lcm_ff_nsr (
.din (lcm_cnt_nxt),
.clk (clk),
.rst_l (start_clk_early_jl),
.q(lcm_cnt));
assign coin_edge_nxt = (lcm_cnt[13:0] == 14'd3) ;
dff_ns u_start_clk_edge_nsr(
.din (coin_edge_nxt),
.clk (clk),
.q (coin_edge));
// -----------------------------------------------
//
// Synchronization checks
//
// -----------------------------------------------
//synopsys translate_off
// values of jtag_nstep_domain & jtag_nstep_count should remain unchanged
// for at least 3 clocks
reg prev_jtag_nstep_domain;
reg [3:0] prev_jtag_nstep_count;
always @(posedge jtag_nstep_vld)
begin
prev_jtag_nstep_domain <= jtag_nstep_domain;
prev_jtag_nstep_count <= jtag_nstep_count;
@(posedge clk)
begin
if( `CTU_PATH.start_clk_jl &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
(prev_jtag_nstep_domain !== jtag_nstep_domain) &
(`CTU_PATH.io_trst_l === 1'b1))
`ifdef MODELSIM
$display ( "CTU_sync_check_error", "jtag_nstep_domain should hold for at least 3 cycles");
`else
$error ( "CTU_sync_check_error", "jtag_nstep_domain should hold for at least 3 cycles");
`endif
if( `CTU_PATH.start_clk_jl &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
( prev_jtag_nstep_count !== jtag_nstep_count) &
(`CTU_PATH.io_trst_l === 1'b1))
`ifdef MODELSIM
$display ( "CTU_sync_check_error", "jtag_nstep_count should hold for at least 3 cycles");
`else
$error ( "CTU_sync_check_error", "jtag_nstep_count should hold for at least 3 cycles");
`endif
end
@(posedge clk)
begin
if( `CTU_PATH.start_clk_jl &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
(prev_jtag_nstep_domain !== jtag_nstep_domain) &
(`CTU_PATH.io_trst_l === 1'b1))
`ifdef MODELSIM
$display ( "CTU_sync_check_error", "jtag_nstep_domain should hold for at least 3 cycles");
`else
$error ( "CTU_sync_check_error", "jtag_nstep_domain should hold for at least 3 cycles");
`endif
if( `CTU_PATH.start_clk_jl &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
(prev_jtag_nstep_count !== jtag_nstep_count) &
(`CTU_PATH.io_trst_l === 1'b1))
`ifdef MODELSIM
$display ( "CTU_sync_check_error", "jtag_nstep_count should hold for at least 3 cycles");
`else
$error ( "CTU_sync_check_error", "jtag_nstep_count should hold for at least 3 cycles");
`endif
end
@(posedge clk)
begin
if( `CTU_PATH.start_clk_jl &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
(prev_jtag_nstep_domain !== jtag_nstep_domain) &
(`CTU_PATH.io_trst_l === 1'b1))
`ifdef MODELSIM
$display ( "CTU_sync_check_error", "jtag_nstep_domain should hold for at least 3 cycles");
`else
$error ( "CTU_sync_check_error", "jtag_nstep_domain should hold for at least 3 cycles");
`endif
if( `CTU_PATH.start_clk_jl &
(`CTU_PATH.testmode_l === 1'b1) & (`CTU_PATH.pll_bypass === 1'b0) &
( prev_jtag_nstep_count !== jtag_nstep_count) &
(`CTU_PATH.io_trst_l === 1'b1))
`ifdef MODELSIM
$display ( "CTU_sync_check_error", "jtag_nstep_count should hold for at least 3 cycles");
`else
$error ( "CTU_sync_check_error", "jtag_nstep_count should hold for at least 3 cycles");
`endif
end
end
//synopsys translate_on
endmodule // ctu_clsp_clkgn_nstep
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_100mhz.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_100mhz (
inclk0,
c0);
input inclk0;
output c0;
wire [0:0] sub_wire2 = 1'h0;
wire [9:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_100mhz",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_100mhz.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100mhz.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100mhz.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100mhz.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100mhz.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100mhz.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100mhz_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100mhz_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//
// my_fpga_test_count_dn.v
//
`timescale 1ns/1ps
module my_fpga_test_count_dn;
reg clk = 0, n_rst = 0;
reg up = 0, dn = 0;
wire [31:0] cnt;
wire [3:0] cnt_1k;
reg in1 = 0, in2 = 0;
wire out1, out2;
my_fpga uut(clk, n_rst, up, dn, cnt, cnt_1k, in1, in2, out1, out2);
tbmsgs msgs();
always
#5 clk = ~clk;
initial
begin
msgs.testcase("my_fpga count dn", 2);
#1000
n_rst = 1;
#1000
// check count is 0xfffffff6 after 10 clocks
@(negedge clk);
dn <= 1;
repeat (10)
@(negedge clk);
msgs.check(cnt == 32'hfffffff6, "cnt should be 0xfffffff6");
msgs.tested("count down to 0xfffffff6");
// check count is 0xfffffc00 after another 1014 clocks
repeat (1014)
@(negedge clk);
msgs.check(cnt == 32'hfffffc00, "cnt should be 0xfffffc00");
msgs.tested("count down to 0xfffff400");
msgs.testcase_complete();
$finish;
end
endmodule
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
/*
* This is the top level or 'root' of the design.
*
* This level should contain device-specific changes, signal inversions,
* tri-state and testability logic.
*
* For example, PLL's and other device specific things would
* be instantiated at this level.
*
*
* Modules further down in the heirarchy should be generic so that
* different FPGA's can be retargeted with minimal fuss.
*
*/
module root(clk, rstn, datain_ch0, datain_ch1, datain_ch2, datain_ch3, serialout, clk20, locked, testout0, testout1, testout2, testout3);
input clk;
input rstn;
input datain_ch0;
input datain_ch1;
input datain_ch2;
input datain_ch3;
output clk20;
output locked;
output serialout;
output testout0;
output testout1;
output testout2;
output testout3;
wire fbouttofbin;
wire clk100;
wire rstn_int;
wire locked_int;
wire CLKOUT2;
wire CLKOUT3;
wire CLKOUT4;
wire CLKOUT5;
system sys0(
.clk(clk100),
.rstn(rstn_int),
.datain_ch0(datain_ch0),
.datain_ch1(datain_ch1),
.datain_ch2(datain_ch2),
.datain_ch3(datain_ch3),
.serialout(serialout),
.testout0(testout0),
.testout1(testout1),
.testout2(testout2),
.testout3(testout3)
);
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(12), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN_PERIOD(20.000), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(6), // Division factor for CLKOUT0 (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(30), // Division factor for CLKOUT1 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(1), // Division factor for CLKOUT2 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(1), // Division factor for CLKOUT3 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(0.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(1), // Division factor for CLKOUT4 (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(1), // Division factor for CLKOUT5 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(0.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
// "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL",
// "DCM2PLL", "PLL2DCM"
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
.REF_JITTER(0.100) // Input reference jitter (0.000 to 0.999 UI%)
) PLL_BASE_inst (
.CLKFBOUT(fbouttofbin), // General output feedback signal
.CLKOUT0(clk100), // One of six general clock output signals
.CLKOUT1(clk20), // One of six general clock output signals
.CLKOUT2(CLKOUT2), // One of six general clock output signals
.CLKOUT3(CLKOUT3), // One of six general clock output signals
.CLKOUT4(CLKOUT4), // One of six general clock output signals
.CLKOUT5(CLKOUT5), // One of six general clock output signals
.LOCKED(locked_int), // Active high PLL lock signal
.CLKFBIN(fbouttofbin), // Clock feedback input
.CLKIN(clk), // Clock input
.RST(~rstn) // Asynchronous PLL reset
);
assign locked = locked_int;
assign rstn_int = rstn & locked_int;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_r_idct.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: bw_r_idct.v
// Description:
// Contains the RTL for the icache and dcache tag blocks.
// This is a 1RW 512 entry X 33b macro, with 132b rd and 132b wr,
// broken into 4 33b segments with its own write enable.
// Address and Control inputs are available the stage before
// array access, which is referred to as "_x". Write data is
// available in the same stage as the write to the ram, referred
// to as "_y". Read data is also read out and available in "_y".
//
// X | Y
// index | ram access
// index sel | write_tag
// rd/wr req | -> read_tag
// way enable |
*/
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_IDCT
`endif
`ifdef FPGA_SYN_IDCT
module bw_r_idct(rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so, rclk, se,
si, reset_l, sehold, rst_tri_en, index0_x, index1_x, index_sel_x,
dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y, wrtag_w1_y, wrtag_w2_y,
wrtag_w3_y, adj);
input rclk;
input se;
input si;
input reset_l;
input sehold;
input rst_tri_en;
input [6:0] index0_x;
input [6:0] index1_x;
input index_sel_x;
input [3:0] dec_wrway_x;
input rdreq_x;
input wrreq_x;
input [32:0] wrtag_w0_y;
input [32:0] wrtag_w1_y;
input [32:0] wrtag_w2_y;
input [32:0] wrtag_w3_y;
input [3:0] adj;
output [32:0] rdtag_w0_y;
output [32:0] rdtag_w1_y;
output [32:0] rdtag_w2_y;
output [32:0] rdtag_w3_y;
output so;
wire clk;
reg [6:0] index_y;
reg rdreq_y;
reg wrreq_y;
reg [3:0] dec_wrway_y;
wire [6:0] index_x;
wire [3:0] we;
reg [131:0] rdtag_sa_y; //for error_inject XMR
assign clk = rclk;
assign index_x = (index_sel_x ? index1_x : index0_x);
assign we = ({4 {((wrreq_y & reset_l) & (~rst_tri_en))}} & dec_wrway_y);
always @(posedge clk) begin
if (~sehold) begin
rdreq_y <= rdreq_x;
wrreq_y <= wrreq_x;
index_y <= index_x;
dec_wrway_y <= dec_wrway_x;
end
end
bw_r_idct_array ictag_ary_00(
.we (we[0]),
.clk (clk),
.way (2'b00),
.rd_data(rdtag_w0_y),
.wr_data(wrtag_w0_y),
.addr (index_y),
.dec_wrway_y (dec_wrway_y));
bw_r_idct_array ictag_ary_01(
.we (we[1]),
.clk (clk),
.way (2'b01),
.rd_data(rdtag_w1_y),
.wr_data(wrtag_w1_y),
.addr (index_y),
.dec_wrway_y (dec_wrway_y));
bw_r_idct_array ictag_ary_10(
.we (we[2]),
.clk (clk),
.way(2'b10),
.rd_data(rdtag_w2_y),
.wr_data(wrtag_w2_y),
.addr (index_y),
.dec_wrway_y (dec_wrway_y));
bw_r_idct_array ictag_ary_11(
.we (we[3]),
.clk (clk),
.way(2'b11),
.rd_data(rdtag_w3_y),
.wr_data(wrtag_w3_y),
.addr (index_y),
.dec_wrway_y (dec_wrway_y));
endmodule
module bw_r_idct_array(we, clk, rd_data, wr_data, addr,dec_wrway_y,way);
input we;
input clk;
input [32:0] wr_data;
input [6:0] addr;
input [3:0] dec_wrway_y;
input [1:0] way;
output [32:0] rd_data;
reg [32:0] rd_data;
reg [32:0] array[511:0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
integer i;
initial begin
`ifdef DO_MEM_INIT
// Add the memory init file in the database
$readmemb("/import/dtg-data11/sandeep/niagara/design/sys/iop/srams/rtl/mem_init_idct.txt",array);
`endif
end
always @(negedge clk) begin
if (we)
begin
array[addr] <= wr_data;
end
else
rd_data <= array[addr];
end
endmodule
`else
module bw_r_idct(/*AUTOARG*/
// Outputs
rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so,
// Inputs
rclk, se, si, reset_l, sehold, rst_tri_en, index0_x, index1_x,
index_sel_x, dec_wrway_x, rdreq_x, wrreq_x, wrtag_w0_y,
wrtag_w1_y, wrtag_w2_y, wrtag_w3_y, adj
);
input rclk,
se,
si,
reset_l; // active LOW reset
input sehold;
input rst_tri_en;
input [6:0] index0_x; // read/write address0
input [6:0] index1_x; // read/write address1
input index_sel_x; // selects between index1 and index0
input [3:0] dec_wrway_x; // way -- functions as a write enable
// per 33b
input rdreq_x, // read enable
wrreq_x; // write enable
// Don't use rdreq and wrreq to gate off the clock, since these are
// critical. A separate power down signal can be supplied if
// needed.
input [32:0] wrtag_w0_y; // write data, not flopped
input [32:0] wrtag_w1_y; //
input [32:0] wrtag_w2_y; //
input [32:0] wrtag_w3_y; //
input [3:0] adj;
output [32:0] rdtag_w0_y; // read data split into 4 ports
output [32:0] rdtag_w1_y; // not flopped
output [32:0] rdtag_w2_y; //
output [32:0] rdtag_w3_y; //
output so;
// Declarations
// local signals
`ifdef DEFINE_0IN
`else
reg [32:0] ictag_ary [511:0];
reg [131:0] rdtag_bl_y,
rdtag_sa_y;
`endif
wire clk;
reg [6:0] index_y;
reg rdreq_y,
wrreq_y;
reg [3:0] dec_wrway_y;
wire [6:0] index_x;
//----------------
// Code start here
//----------------
assign clk = rclk;
//-------------------------
// 2:1 mux on address input
//-------------------------
// address inputs are critical and this mux needs to be merged with
// the receiving flop.
assign index_x = index_sel_x ? index1_x :
index0_x;
//------------------------
// input flops from x to y
//------------------------
// these need to be scannable
always @ (posedge clk)
begin
if (~sehold)
begin
rdreq_y <= rdreq_x;
wrreq_y <= wrreq_x;
index_y <= index_x;
dec_wrway_y <= dec_wrway_x;
end
end
`ifdef DEFINE_0IN
wire [131:0] wm = { {33{(dec_wrway_y[3])}},{33{(dec_wrway_y[2])}},{33{(dec_wrway_y[1])}},{33{(dec_wrway_y[0])}} };
wire we = wrreq_y & ~se;
l1_tag l1_tag ( .nclk(~clk), .adr(index_y[6:0]), .we(we), .wm(wm),
.din ({wrtag_w3_y,wrtag_w2_y,wrtag_w1_y,wrtag_w0_y}),
.dout({rdtag_w3_y,rdtag_w2_y,rdtag_w1_y,rdtag_w0_y}) );
`else
//----------------------------------------------------------------------
// Read Operation
//----------------------------------------------------------------------
always @(/*AUTOSENSE*/ /*memory or*/ index_y or rdreq_y or reset_l
or wrreq_y)
begin
if (rdreq_y & reset_l)
begin
if (wrreq_y) // rd_wr conflict
begin
rdtag_bl_y = {132{1'bx}};
end
else // no write, read only
begin
rdtag_bl_y[32:0] = ictag_ary[{index_y,2'b00}]; // way0
rdtag_bl_y[65:33] = ictag_ary[{index_y,2'b01}]; // way1
rdtag_bl_y[98:66] = ictag_ary[{index_y,2'b10}]; // way2
rdtag_bl_y[131:99] = ictag_ary[{index_y,2'b11}];// way3
end
end
else // no read
begin
rdtag_bl_y = {132{1'bx}};
end
end // always @ (...
// SA latch -- to make 0in happy
always @ (/*AUTOSENSE*/clk or rdreq_y or rdtag_bl_y or reset_l)
begin
if (rdreq_y & ~clk & reset_l)
begin
rdtag_sa_y <= rdtag_bl_y;
end
end
// Output is held the same if there is no read. This is not a
// hard requirement, please let me know if the output has to
// be something else for ease of implementation.
// Output behavior during reset is currently not coded.
// Functionally there is no preference, though it should be
// unchanging to keep the power low.
// Final Output
assign rdtag_w0_y = rdtag_sa_y[32:0];
assign rdtag_w1_y = rdtag_sa_y[65:33];
assign rdtag_w2_y = rdtag_sa_y[98:66];
assign rdtag_w3_y = rdtag_sa_y[131:99];
//----------------------------------------------------------------------
// Write Operation
//----------------------------------------------------------------------
// Writes should be blocked off during scan shift.
always @ (negedge clk)
begin
if (wrreq_y & reset_l & ~rst_tri_en)
begin
if (dec_wrway_y[0])
ictag_ary[{index_y, 2'b00}] = wrtag_w0_y;
if (dec_wrway_y[1])
ictag_ary[{index_y, 2'b01}] = wrtag_w1_y;
if (dec_wrway_y[2])
ictag_ary[{index_y, 2'b10}] = wrtag_w2_y;
if (dec_wrway_y[3])
ictag_ary[{index_y, 2'b11}] = wrtag_w3_y;
end
end
// TBD: Need to model rd-wr contention
`endif
//******************************************************
// The stuff below is not part of the main functionality
// and has no representation in the actual circuit.
//******************************************************
// synopsys translate_off
//-----------------------
// Contention Monitor
//-----------------------
`ifdef INNO_MUXEX
`else
always @ (negedge clk)
begin
if (rdreq_y & wrreq_y & reset_l)
begin
// 0in <fire -message "FATAL ERROR: rd and wr contention in idct"
//$error("IDtag Contention", "ERROR rd and wr contention in idct");
end
end // always @ (negedge clk)
`endif
//--------------------------------
// // For dump_cache.v
// //--------------------------------
// //fake to make dump_cache.v happy
// reg [29:0] w0 [127:0];
// reg [29:0] w1 [127:0];
// reg [29:0] w2 [127:0];
// reg [29:0] w3 [127:0];
//
// always @ (negedge clk)
// begin
// if (wrreq_y & ~se)
// begin
// if (rdreq_y) begin // rd/wr contention
// case (dec_wrway_y)
// 4'b0001 : w0[index_y[6:0]] ={30{1'bx}};
// 4'b0010 : w1[index_y[6:0]] ={30{1'bx}};
// 4'b0100 : w2[index_y[6:0]] ={30{1'bx}};
// 4'b1000 : w3[index_y[6:0]] ={30{1'bx}};
// endcase // case(wrway_y)
// end
// else begin
// case (dec_wrway_y)
// 4'b0001 : w0[index_y[6:0]] = wrtag_w0_y[29:0];
// 4'b0010 : w1[index_y[6:0]] = wrtag_w1_y[29:0];
// 4'b0100 : w2[index_y[6:0]] = wrtag_w2_y[29:0];
// 4'b1000 : w3[index_y[6:0]] = wrtag_w3_y[29:0];
// endcase // case(wrway_y)
// end
// end
// end
// synopsys translate_on
endmodule // bw_r_idct
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: NCTU DLAB
// Engineer: Gavin Lee
//
// Create Date: 21:56:27 11/27/2016
// Design Name:
// Module Name: lab07_0416037
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab07_0416037(
input rst,
input clk,
input BTN_WEST,
input BTN_NORTH,
input BTN_EAST,
input [3:0] SW,
output reg [7:0] LED
);
//---------------------------------------------------------------------
// PARAMETER DECLARATION
//---------------------------------------------------------------------
integer WAIT_TIME=2000000;
integer HAHA_STOP=1000;
parameter IDLE=0;
parameter OPT=1;
parameter NUM=2;
parameter RESET=0;
parameter ADD=1;
parameter SQRT=2;
parameter MULT=3;
//---------------------------------------------------------------------
// WIRE AND REG DECLARATION
//---------------------------------------------------------------------
reg [1:0] cState, nState;
reg [20:0] cnt;
reg [10:0] haha;
reg [7:0] ans;
reg [1:0] opt;
wire [4:0] sqrtAns;
reg can;
//---------------------------------------------------------------------
// COMBINATIONAL CIRCUIT
//---------------------------------------------------------------------
sqrt sqrt_module(
.x_in(ans), // input [7 : 0] x_in
.x_out(sqrtAns), // output [4 : 0] x_out
.clk(clk) // input clk
);
//---------------------------------------------------------------------
// Finite-State Mechine
//---------------------------------------------------------------------
// cState
always@(posedge clk, posedge rst)
begin
if(rst) cState <= IDLE;
else cState <= nState;
end
// nState
always@(*)
begin
case(cState)
IDLE: begin
if(BTN_WEST || BTN_NORTH || BTN_EAST) nState = OPT;
else nState = IDLE;
end
NUM: begin
if((haha > HAHA_STOP) && (BTN_WEST || BTN_NORTH || BTN_EAST)) nState = OPT;
else nState = NUM;
end
OPT: begin
if(cnt >= WAIT_TIME) nState = NUM;
else nState = OPT;
end
default: nState = IDLE;
endcase
end
//---------------------------------------------------------------------
// Design Description
//---------------------------------------------------------------------
// haha
always@(posedge clk, posedge rst)
begin
if(rst) haha <= 0;
else begin
case(cState)
IDLE: haha <= 0;
NUM: begin
if(haha > HAHA_STOP) haha <= haha;
else if(!(BTN_WEST || BTN_NORTH || BTN_EAST)) haha <= haha+1;
else haha <= 0;
end
OPT: haha <= 0;
endcase
end
end
// can
always@(posedge clk, posedge rst)
begin
if(rst) can <= 0;
else if(cState == OPT && !can) can <= 1;
else if(cState == OPT) can <= can;
else can <= 0;
end
// cnt
always@(posedge clk, posedge rst)
begin
if(rst) cnt <= 0;
else begin
case(cState)
IDLE: cnt <= 0;
NUM: cnt <= 0;
OPT: begin
if(BTN_WEST || BTN_NORTH || BTN_EAST) cnt <= cnt+1;
else cnt <= cnt;
end
endcase
end
end
// opt
always@(posedge clk, posedge rst)
begin
if(rst) opt <= RESET;
else begin
case(cState)
IDLE: opt <= RESET;
OPT: begin
if(BTN_WEST) opt <= SQRT;
else if(BTN_EAST) opt <= ADD;
else if(BTN_NORTH) opt <= MULT;
else opt <= RESET;
end
NUM: opt <= opt;
default opt <= opt;
endcase
end
end
// ans
always@(posedge clk, posedge rst)
begin
if(rst) ans <= 0;
else begin
case(cState)
IDLE: ans <= 0;
OPT: begin
if(!can) begin
case(opt)
RESET: ans <= SW;
ADD: ans <= ans+SW;
MULT: ans <= ans * SW;
SQRT: ans <= sqrtAns;
default: ans <= ans;
endcase
end
else ans <= ans;
end
NUM: ans <= ans;
default: ans <= ans;
endcase
end
end
// LED
always@(posedge clk, posedge rst)
begin
if(rst) LED <= 0;
else begin
case(cState)
IDLE: LED <= SW;
OPT: LED <= LED;
NUM: begin
case(opt)
RESET: LED <= SW;
ADD: LED <= ans + SW;
MULT: LED <= ans * SW;
SQRT: LED <= sqrtAns;
default: LED <= LED;
endcase
end
default: LED <= LED;
endcase
end
end
/*
always@(posedge clk, posedge rst)
begin
if(rst) LED <= 0;
else begin
LED <= cState;
end
end
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPMET1_PP_SYMBOL_V
`define SKY130_FD_SC_HS__TAPMET1_PP_SYMBOL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapmet1 (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPMET1_PP_SYMBOL_V
|
// megafunction wizard: %ALTPLL_RECONFIG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll_reconfig
// ============================================================
// File Name: pll_config_intf.v
// Megafunction Name(s):
// altpll_reconfig
//
// Simulation Library Files(s):
// altera_mf;arriaii;lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" pll_type="FAST" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
//VERSION_BEGIN 12.1SP1 cbx_altpll_reconfig 2013:01:31:18:05:07:SJ cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 84
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"ADV_NETLIST_OPT_ALLOWED=\"NEVER_ALLOW\";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1"} *)
module pll_config_intf_pllrcfg_dgr
(
busy,
clock,
counter_param,
counter_type,
data_in,
data_out,
pll_areset,
pll_areset_in,
pll_configupdate,
pll_scanclk,
pll_scanclkena,
pll_scandata,
pll_scandataout,
pll_scandone,
read_param,
reconfig,
reset,
write_param) /* synthesis synthesis_clearbox=2 */;
output busy;
input clock;
input [2:0] counter_param;
input [3:0] counter_type;
input [8:0] data_in;
output [8:0] data_out;
output pll_areset;
input pll_areset_in;
output pll_configupdate;
output pll_scanclk;
output pll_scanclkena;
output pll_scandata;
input pll_scandataout;
input pll_scandone;
input read_param;
input reconfig;
input reset;
input write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [2:0] counter_param;
tri0 [3:0] counter_type;
tri0 [8:0] data_in;
tri0 pll_areset_in;
tri0 pll_scandataout;
tri0 pll_scandone;
tri0 read_param;
tri0 reconfig;
tri0 write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_altsyncram4_q_a;
reg areset_init_state_1;
reg areset_state;
reg C0_data_state;
reg C0_ena_state;
reg C1_data_state;
reg C1_ena_state;
reg C2_data_state;
reg C2_ena_state;
reg C3_data_state;
reg C3_ena_state;
reg C4_data_state;
reg C4_ena_state;
reg C5_data_state;
reg C5_ena_state;
reg C6_data_state;
reg C6_ena_state;
reg configupdate2_state;
reg configupdate3_state;
reg configupdate_state;
reg [2:0] counter_param_latch_reg;
reg [3:0] counter_type_latch_reg;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg idle_state;
reg [0:0] nominal_data0;
reg [0:0] nominal_data1;
reg [0:0] nominal_data2;
reg [0:0] nominal_data3;
reg [0:0] nominal_data4;
reg [0:0] nominal_data5;
reg [0:0] nominal_data6;
reg [0:0] nominal_data7;
reg [0:0] nominal_data8;
reg [0:0] nominal_data9;
reg [0:0] nominal_data10;
reg [0:0] nominal_data11;
reg [0:0] nominal_data12;
reg [0:0] nominal_data13;
reg [0:0] nominal_data14;
reg [0:0] nominal_data15;
reg [0:0] nominal_data16;
reg [0:0] nominal_data17;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_data_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_first_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_first_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_init_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_last_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_last_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_counter_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_post_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_seq_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_seq_ena_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_wait_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg reset_state;
reg [0:0] shift_reg0;
reg [0:0] shift_reg1;
reg [0:0] shift_reg2;
reg [0:0] shift_reg3;
reg [0:0] shift_reg4;
reg [0:0] shift_reg5;
reg [0:0] shift_reg6;
reg [0:0] shift_reg7;
reg [0:0] shift_reg8;
reg [0:0] shift_reg9;
reg [0:0] shift_reg10;
reg [0:0] shift_reg11;
reg [0:0] shift_reg12;
reg [0:0] shift_reg13;
reg [0:0] shift_reg14;
reg [0:0] shift_reg15;
reg [0:0] shift_reg16;
reg [0:0] shift_reg17;
wire [17:0] wire_shift_reg_ena;
reg tmp_nominal_data_out_state;
reg tmp_seq_ena_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_init_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_nominal_state;
wire [8:0] wire_add_sub5_result;
wire [7:0] wire_add_sub6_result;
wire wire_cmpr7_aeb;
wire [7:0] wire_cntr1_q;
wire [7:0] wire_cntr12_q;
wire [5:0] wire_cntr13_q;
wire [4:0] wire_cntr14_q;
wire [7:0] wire_cntr15_q;
wire [7:0] wire_cntr2_q;
wire [4:0] wire_cntr3_q;
wire [6:0] wire_decode11_eq;
wire wire_le_comb10_combout;
wire wire_le_comb8_combout;
wire wire_le_comb9_combout;
wire addr_counter_enable;
wire [7:0] addr_counter_out;
wire addr_counter_sload;
wire [7:0] addr_counter_sload_value;
wire [7:0] addr_decoder_out;
wire [7:0] c0_wire;
wire [7:0] c1_wire;
wire [7:0] c2_wire;
wire [7:0] c3_wire;
wire [7:0] c4_wire;
wire [7:0] c5_wire;
wire [7:0] c6_wire;
wire [2:0] counter_param_latch;
wire [3:0] counter_type_latch;
wire [2:0] cuda_combout_wire;
wire dummy_scandataout;
wire [2:0] encode_out;
wire input_latch_enable;
wire power_up;
wire read_addr_counter_enable;
wire [7:0] read_addr_counter_out;
wire read_addr_counter_sload;
wire [7:0] read_addr_counter_sload_value;
wire [7:0] read_addr_decoder_out;
wire read_nominal_out;
wire reconfig_addr_counter_enable;
wire [7:0] reconfig_addr_counter_out;
wire reconfig_addr_counter_sload;
wire [7:0] reconfig_addr_counter_sload_value;
wire reconfig_done;
wire reconfig_post_done;
wire reconfig_width_counter_done;
wire reconfig_width_counter_enable;
wire reconfig_width_counter_sload;
wire [5:0] reconfig_width_counter_sload_value;
wire rotate_addr_counter_enable;
wire [7:0] rotate_addr_counter_out;
wire rotate_addr_counter_sload;
wire [7:0] rotate_addr_counter_sload_value;
wire [6:0] rotate_decoder_wires;
wire rotate_width_counter_done;
wire rotate_width_counter_enable;
wire rotate_width_counter_sload;
wire [4:0] rotate_width_counter_sload_value;
wire [7:0] scan_cache_address;
wire scan_cache_in;
wire scan_cache_out;
wire scan_cache_write_enable;
wire sel_param_bypass_LF_unused;
wire sel_param_c;
wire sel_param_high_i_postscale;
wire sel_param_low_r;
wire sel_param_nominal_count;
wire sel_param_odd_CP_unused;
wire sel_type_c0;
wire sel_type_c1;
wire sel_type_c2;
wire sel_type_c3;
wire sel_type_c4;
wire sel_type_c5;
wire sel_type_c6;
wire sel_type_cplf;
wire sel_type_m;
wire sel_type_n;
wire sel_type_vco;
wire [7:0] seq_addr_wire;
wire [5:0] seq_sload_value;
wire shift_reg_clear;
wire shift_reg_load_enable;
wire shift_reg_load_nominal_enable;
wire shift_reg_serial_in;
wire shift_reg_serial_out;
wire shift_reg_shift_enable;
wire shift_reg_shift_nominal_enable;
wire [7:0] shift_reg_width_select;
wire w1837w;
wire w1864w;
wire w64w;
wire width_counter_done;
wire width_counter_enable;
wire width_counter_sload;
wire [4:0] width_counter_sload_value;
wire [4:0] width_decoder_out;
wire [7:0] width_decoder_select;
wire write_from_rom;
altsyncram altsyncram4
(
.address_a(scan_cache_address),
.clock0(clock),
.data_a({scan_cache_in}),
.eccstatus(),
.q_a(wire_altsyncram4_q_a),
.q_b(),
.wren_a(scan_cache_write_enable)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr0(1'b0),
.aclr1(1'b0),
.address_b({1{1'b1}}),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({1{1'b1}}),
.byteena_b({1{1'b1}}),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_b({1{1'b1}}),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_b(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
altsyncram4.numwords_a = 180,
altsyncram4.operation_mode = "SINGLE_PORT",
altsyncram4.width_a = 1,
altsyncram4.width_byteena_a = 1,
altsyncram4.widthad_a = 8,
altsyncram4.intended_device_family = "Arria II GX",
altsyncram4.lpm_type = "altsyncram";
// synopsys translate_off
initial
areset_init_state_1 = 0;
// synopsys translate_on
always @ ( posedge clock)
areset_init_state_1 <= pll_scandone;
// synopsys translate_off
initial
areset_state = 0;
// synopsys translate_on
always @ ( posedge clock)
areset_state <= (areset_init_state_1 & (~ reset));
// synopsys translate_off
initial
C0_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C0_data_state <= (C0_ena_state | (C0_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C0_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C0_ena_state <= (C1_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C1_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C1_data_state <= (C1_ena_state | (C1_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C1_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C1_ena_state <= (C2_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C2_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C2_data_state <= (C2_ena_state | (C2_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C2_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C2_ena_state <= (C3_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C3_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C3_data_state <= (C3_ena_state | (C3_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C3_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C3_ena_state <= (C4_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C4_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C4_data_state <= (C4_ena_state | (C4_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C4_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C4_ena_state <= (C5_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C5_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C5_data_state <= (C5_ena_state | (C5_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C5_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C5_ena_state <= (C6_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C6_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C6_data_state <= (C6_ena_state | (C6_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C6_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C6_ena_state <= reconfig_init_state;
// synopsys translate_off
initial
configupdate2_state = 0;
// synopsys translate_on
always @ ( posedge clock)
configupdate2_state <= configupdate_state;
// synopsys translate_off
initial
configupdate3_state = 0;
// synopsys translate_on
always @ ( negedge clock)
configupdate3_state <= configupdate2_state;
// synopsys translate_off
initial
configupdate_state = 0;
// synopsys translate_on
always @ ( posedge clock)
configupdate_state <= reconfig_post_state;
// synopsys translate_off
initial
counter_param_latch_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) counter_param_latch_reg <= 3'b0;
else if (input_latch_enable == 1'b1) counter_param_latch_reg <= counter_param;
// synopsys translate_off
initial
counter_type_latch_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) counter_type_latch_reg <= 4'b0;
else if (input_latch_enable == 1'b1) counter_type_latch_reg <= counter_type;
// synopsys translate_off
initial
idle_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) idle_state <= 1'b0;
else idle_state <= ((((((((((idle_state & (~ read_param)) & (~ write_param)) & (~ reconfig)) & (~ write_from_rom)) | read_last_state) | (write_data_state & width_counter_done)) | (write_nominal_state & width_counter_done)) | read_last_nominal_state) | (reconfig_wait_state & reconfig_done)) | reset_state);
// synopsys translate_off
initial
nominal_data0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data0 <= 1'b0;
else nominal_data0 <= wire_add_sub6_result[0];
// synopsys translate_off
initial
nominal_data1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data1 <= 1'b0;
else nominal_data1 <= wire_add_sub6_result[1];
// synopsys translate_off
initial
nominal_data2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data2 <= 1'b0;
else nominal_data2 <= wire_add_sub6_result[2];
// synopsys translate_off
initial
nominal_data3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data3 <= 1'b0;
else nominal_data3 <= wire_add_sub6_result[3];
// synopsys translate_off
initial
nominal_data4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data4 <= 1'b0;
else nominal_data4 <= wire_add_sub6_result[4];
// synopsys translate_off
initial
nominal_data5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data5 <= 1'b0;
else nominal_data5 <= wire_add_sub6_result[5];
// synopsys translate_off
initial
nominal_data6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data6 <= 1'b0;
else nominal_data6 <= wire_add_sub6_result[6];
// synopsys translate_off
initial
nominal_data7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data7 <= 1'b0;
else nominal_data7 <= wire_add_sub6_result[7];
// synopsys translate_off
initial
nominal_data8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data8 <= 1'b0;
else nominal_data8 <= data_in[0];
// synopsys translate_off
initial
nominal_data9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data9 <= 1'b0;
else nominal_data9 <= data_in[1];
// synopsys translate_off
initial
nominal_data10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data10 <= 1'b0;
else nominal_data10 <= data_in[2];
// synopsys translate_off
initial
nominal_data11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data11 <= 1'b0;
else nominal_data11 <= data_in[3];
// synopsys translate_off
initial
nominal_data12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data12 <= 1'b0;
else nominal_data12 <= data_in[4];
// synopsys translate_off
initial
nominal_data13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data13 <= 1'b0;
else nominal_data13 <= data_in[5];
// synopsys translate_off
initial
nominal_data14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data14 <= 1'b0;
else nominal_data14 <= data_in[6];
// synopsys translate_off
initial
nominal_data15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data15 <= 1'b0;
else nominal_data15 <= data_in[7];
// synopsys translate_off
initial
nominal_data16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data16 <= 1'b0;
else nominal_data16 <= data_in[8];
// synopsys translate_off
initial
nominal_data17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data17 <= 1'b0;
else nominal_data17 <= wire_cmpr7_aeb;
// synopsys translate_off
initial
read_data_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_data_nominal_state <= 1'b0;
else read_data_nominal_state <= ((read_first_nominal_state & (~ width_counter_done)) | (read_data_nominal_state & (~ width_counter_done)));
// synopsys translate_off
initial
read_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_data_state <= 1'b0;
else read_data_state <= ((read_first_state & (~ width_counter_done)) | (read_data_state & (~ width_counter_done)));
// synopsys translate_off
initial
read_first_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_first_nominal_state <= 1'b0;
else read_first_nominal_state <= read_init_nominal_state;
// synopsys translate_off
initial
read_first_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_first_state <= 1'b0;
else read_first_state <= read_init_state;
// synopsys translate_off
initial
read_init_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_nominal_state <= 1'b0;
else read_init_nominal_state <= ((idle_state & read_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
// synopsys translate_off
initial
read_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_state <= 1'b0;
else read_init_state <= ((idle_state & read_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
// synopsys translate_off
initial
read_last_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_last_nominal_state <= 1'b0;
else read_last_nominal_state <= ((read_first_nominal_state & width_counter_done) | (read_data_nominal_state & width_counter_done));
// synopsys translate_off
initial
read_last_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_last_state <= 1'b0;
else read_last_state <= ((read_first_state & width_counter_done) | (read_data_state & width_counter_done));
// synopsys translate_off
initial
reconfig_counter_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_counter_state <= 1'b0;
else reconfig_counter_state <= ((((((((((((((reconfig_init_state | C0_data_state) | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state) | C5_data_state) | C6_data_state) | C0_ena_state) | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state) | C5_ena_state) | C6_ena_state);
// synopsys translate_off
initial
reconfig_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_init_state <= 1'b0;
else reconfig_init_state <= (idle_state & reconfig);
// synopsys translate_off
initial
reconfig_post_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_post_state <= 1'b0;
else reconfig_post_state <= ((reconfig_seq_data_state & reconfig_width_counter_done) | (reconfig_post_state & (~ reconfig_post_done)));
// synopsys translate_off
initial
reconfig_seq_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_seq_data_state <= 1'b0;
else reconfig_seq_data_state <= (reconfig_seq_ena_state | (reconfig_seq_data_state & (~ reconfig_width_counter_done)));
// synopsys translate_off
initial
reconfig_seq_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_seq_ena_state <= 1'b0;
else reconfig_seq_ena_state <= tmp_seq_ena_state;
// synopsys translate_off
initial
reconfig_wait_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_wait_state <= 1'b0;
else reconfig_wait_state <= ((reconfig_post_state & reconfig_post_done) | (reconfig_wait_state & (~ reconfig_done)));
// synopsys translate_off
initial
reset_state = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reset_state <= {1{1'b1}};
else reset_state <= power_up;
// synopsys translate_off
initial
shift_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg0 <= 1'b0;
else if (wire_shift_reg_ena[0:0] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg0 <= 1'b0;
else shift_reg0 <= ((((shift_reg_load_nominal_enable & nominal_data17[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg_serial_in)) | (shift_reg_shift_nominal_enable & shift_reg_serial_in));
// synopsys translate_off
initial
shift_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg1 <= 1'b0;
else if (wire_shift_reg_ena[1:1] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg1 <= 1'b0;
else shift_reg1 <= ((((shift_reg_load_nominal_enable & nominal_data16[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg0[0:0])) | (shift_reg_shift_nominal_enable & shift_reg0[0:0]));
// synopsys translate_off
initial
shift_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg2 <= 1'b0;
else if (wire_shift_reg_ena[2:2] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg2 <= 1'b0;
else shift_reg2 <= ((((shift_reg_load_nominal_enable & nominal_data15[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg1[0:0])) | (shift_reg_shift_nominal_enable & shift_reg1[0:0]));
// synopsys translate_off
initial
shift_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg3 <= 1'b0;
else if (wire_shift_reg_ena[3:3] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg3 <= 1'b0;
else shift_reg3 <= ((((shift_reg_load_nominal_enable & nominal_data14[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg2[0:0])) | (shift_reg_shift_nominal_enable & shift_reg2[0:0]));
// synopsys translate_off
initial
shift_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg4 <= 1'b0;
else if (wire_shift_reg_ena[4:4] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg4 <= 1'b0;
else shift_reg4 <= ((((shift_reg_load_nominal_enable & nominal_data13[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg3[0:0])) | (shift_reg_shift_nominal_enable & shift_reg3[0:0]));
// synopsys translate_off
initial
shift_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg5 <= 1'b0;
else if (wire_shift_reg_ena[5:5] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg5 <= 1'b0;
else shift_reg5 <= ((((shift_reg_load_nominal_enable & nominal_data12[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg4[0:0])) | (shift_reg_shift_nominal_enable & shift_reg4[0:0]));
// synopsys translate_off
initial
shift_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg6 <= 1'b0;
else if (wire_shift_reg_ena[6:6] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg6 <= 1'b0;
else shift_reg6 <= ((((shift_reg_load_nominal_enable & nominal_data11[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg5[0:0])) | (shift_reg_shift_nominal_enable & shift_reg5[0:0]));
// synopsys translate_off
initial
shift_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg7 <= 1'b0;
else if (wire_shift_reg_ena[7:7] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg7 <= 1'b0;
else shift_reg7 <= ((((shift_reg_load_nominal_enable & nominal_data10[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg6[0:0])) | (shift_reg_shift_nominal_enable & shift_reg6[0:0]));
// synopsys translate_off
initial
shift_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg8 <= 1'b0;
else if (wire_shift_reg_ena[8:8] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg8 <= 1'b0;
else shift_reg8 <= ((((shift_reg_load_nominal_enable & nominal_data9[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg7[0:0])) | (shift_reg_shift_nominal_enable & shift_reg7[0:0]));
// synopsys translate_off
initial
shift_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg9 <= 1'b0;
else if (wire_shift_reg_ena[9:9] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg9 <= 1'b0;
else shift_reg9 <= ((((shift_reg_load_nominal_enable & nominal_data8[0:0]) | (shift_reg_load_enable & data_in[8])) | (shift_reg_shift_enable & shift_reg8[0:0])) | (shift_reg_shift_nominal_enable & shift_reg8[0:0]));
// synopsys translate_off
initial
shift_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg10 <= 1'b0;
else if (wire_shift_reg_ena[10:10] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg10 <= 1'b0;
else shift_reg10 <= ((((shift_reg_load_nominal_enable & nominal_data7[0:0]) | (shift_reg_load_enable & data_in[7])) | (shift_reg_shift_enable & shift_reg9[0:0])) | (shift_reg_shift_nominal_enable & shift_reg9[0:0]));
// synopsys translate_off
initial
shift_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg11 <= 1'b0;
else if (wire_shift_reg_ena[11:11] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg11 <= 1'b0;
else shift_reg11 <= ((((shift_reg_load_nominal_enable & nominal_data6[0:0]) | (shift_reg_load_enable & data_in[6])) | (shift_reg_shift_enable & shift_reg10[0:0])) | (shift_reg_shift_nominal_enable & shift_reg10[0:0]));
// synopsys translate_off
initial
shift_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg12 <= 1'b0;
else if (wire_shift_reg_ena[12:12] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg12 <= 1'b0;
else shift_reg12 <= ((((shift_reg_load_nominal_enable & nominal_data5[0:0]) | (shift_reg_load_enable & data_in[5])) | (shift_reg_shift_enable & shift_reg11[0:0])) | (shift_reg_shift_nominal_enable & shift_reg11[0:0]));
// synopsys translate_off
initial
shift_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg13 <= 1'b0;
else if (wire_shift_reg_ena[13:13] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg13 <= 1'b0;
else shift_reg13 <= ((((shift_reg_load_nominal_enable & nominal_data4[0:0]) | (shift_reg_load_enable & data_in[4])) | (shift_reg_shift_enable & shift_reg12[0:0])) | (shift_reg_shift_nominal_enable & shift_reg12[0:0]));
// synopsys translate_off
initial
shift_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg14 <= 1'b0;
else if (wire_shift_reg_ena[14:14] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg14 <= 1'b0;
else shift_reg14 <= ((((shift_reg_load_nominal_enable & nominal_data3[0:0]) | (shift_reg_load_enable & data_in[3])) | (shift_reg_shift_enable & shift_reg13[0:0])) | (shift_reg_shift_nominal_enable & shift_reg13[0:0]));
// synopsys translate_off
initial
shift_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg15 <= 1'b0;
else if (wire_shift_reg_ena[15:15] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg15 <= 1'b0;
else shift_reg15 <= ((((shift_reg_load_nominal_enable & nominal_data2[0:0]) | (shift_reg_load_enable & data_in[2])) | (shift_reg_shift_enable & shift_reg14[0:0])) | (shift_reg_shift_nominal_enable & shift_reg14[0:0]));
// synopsys translate_off
initial
shift_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg16 <= 1'b0;
else if (wire_shift_reg_ena[16:16] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg16 <= 1'b0;
else shift_reg16 <= ((((shift_reg_load_nominal_enable & nominal_data1[0:0]) | (shift_reg_load_enable & data_in[1])) | (shift_reg_shift_enable & shift_reg15[0:0])) | (shift_reg_shift_nominal_enable & shift_reg15[0:0]));
// synopsys translate_off
initial
shift_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg17 <= 1'b0;
else if (wire_shift_reg_ena[17:17] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg17 <= 1'b0;
else shift_reg17 <= ((((shift_reg_load_nominal_enable & nominal_data0[0:0]) | (shift_reg_load_enable & data_in[0])) | (shift_reg_shift_enable & shift_reg16[0:0])) | (shift_reg_shift_nominal_enable & shift_reg16[0:0]));
assign
wire_shift_reg_ena = {18{((((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_load_nominal_enable) | shift_reg_shift_nominal_enable) | shift_reg_clear)}};
// synopsys translate_off
initial
tmp_nominal_data_out_state = 0;
// synopsys translate_on
always @ ( posedge clock)
tmp_nominal_data_out_state <= ((read_last_nominal_state & (~ idle_state)) | (tmp_nominal_data_out_state & idle_state));
// synopsys translate_off
initial
tmp_seq_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
tmp_seq_ena_state <= (reconfig_counter_state & (C0_data_state & rotate_width_counter_done));
// synopsys translate_off
initial
write_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_data_state <= 1'b0;
else write_data_state <= (write_init_state | (write_data_state & (~ width_counter_done)));
// synopsys translate_off
initial
write_init_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_nominal_state <= 1'b0;
else write_init_nominal_state <= ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
// synopsys translate_off
initial
write_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_state <= 1'b0;
else write_init_state <= ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
// synopsys translate_off
initial
write_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_nominal_state <= 1'b0;
else write_nominal_state <= (write_init_nominal_state | (write_nominal_state & (~ width_counter_done)));
lpm_add_sub add_sub5
(
.cin(1'b0),
.cout(),
.dataa({1'b0, shift_reg8[0:0], shift_reg7[0:0], shift_reg6[0:0], shift_reg5[0:0], shift_reg4[0:0], shift_reg3[0:0], shift_reg2[0:0], shift_reg1[0:0]}),
.datab({1'b0, shift_reg17[0:0], shift_reg16[0:0], shift_reg15[0:0], shift_reg14[0:0], shift_reg13[0:0], shift_reg12[0:0], shift_reg11[0:0], shift_reg10[0:0]}),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_width = 9,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cin(data_in[0]),
.cout(),
.dataa({data_in[8:1]}),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0),
.datab({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_width = 8,
add_sub6.lpm_type = "lpm_add_sub";
lpm_compare cmpr7
(
.aeb(wire_cmpr7_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa({data_in[7:0]}),
.datab(8'b00000001)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr7.lpm_width = 8,
cmpr7.lpm_type = "lpm_compare";
lpm_counter cntr1
(
.clock(clock),
.cnt_en(addr_counter_enable),
.cout(),
.data(addr_counter_sload_value),
.eq(),
.q(wire_cntr1_q),
.sload(addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr1.lpm_direction = "DOWN",
cntr1.lpm_modulus = 180,
cntr1.lpm_port_updown = "PORT_UNUSED",
cntr1.lpm_width = 8,
cntr1.lpm_type = "lpm_counter";
lpm_counter cntr12
(
.clock(clock),
.cnt_en(reconfig_addr_counter_enable),
.cout(),
.data(reconfig_addr_counter_sload_value),
.eq(),
.q(wire_cntr12_q),
.sload(reconfig_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr12.lpm_direction = "DOWN",
cntr12.lpm_modulus = 180,
cntr12.lpm_port_updown = "PORT_UNUSED",
cntr12.lpm_width = 8,
cntr12.lpm_type = "lpm_counter";
lpm_counter cntr13
(
.clock(clock),
.cnt_en(reconfig_width_counter_enable),
.cout(),
.data(reconfig_width_counter_sload_value),
.eq(),
.q(wire_cntr13_q),
.sload(reconfig_width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr13.lpm_direction = "DOWN",
cntr13.lpm_port_updown = "PORT_UNUSED",
cntr13.lpm_width = 6,
cntr13.lpm_type = "lpm_counter";
lpm_counter cntr14
(
.clock(clock),
.cnt_en(rotate_width_counter_enable),
.cout(),
.data(rotate_width_counter_sload_value),
.eq(),
.q(wire_cntr14_q),
.sload(rotate_width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr14.lpm_direction = "DOWN",
cntr14.lpm_port_updown = "PORT_UNUSED",
cntr14.lpm_width = 5,
cntr14.lpm_type = "lpm_counter";
lpm_counter cntr15
(
.clock(clock),
.cnt_en(rotate_addr_counter_enable),
.cout(),
.data(rotate_addr_counter_sload_value),
.eq(),
.q(wire_cntr15_q),
.sload(rotate_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr15.lpm_direction = "DOWN",
cntr15.lpm_modulus = 180,
cntr15.lpm_port_updown = "PORT_UNUSED",
cntr15.lpm_width = 8,
cntr15.lpm_type = "lpm_counter";
lpm_counter cntr2
(
.clock(clock),
.cnt_en(read_addr_counter_enable),
.cout(),
.data(read_addr_counter_sload_value),
.eq(),
.q(wire_cntr2_q),
.sload(read_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr2.lpm_direction = "UP",
cntr2.lpm_port_updown = "PORT_UNUSED",
cntr2.lpm_width = 8,
cntr2.lpm_type = "lpm_counter";
lpm_counter cntr3
(
.clock(clock),
.cnt_en(width_counter_enable),
.cout(),
.data(width_counter_sload_value),
.eq(),
.q(wire_cntr3_q),
.sload(width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr3.lpm_direction = "DOWN",
cntr3.lpm_port_updown = "PORT_UNUSED",
cntr3.lpm_width = 5,
cntr3.lpm_type = "lpm_counter";
lpm_decode decode11
(
.data(cuda_combout_wire),
.eq(wire_decode11_eq)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.enable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
decode11.lpm_decodes = 7,
decode11.lpm_width = 3,
decode11.lpm_type = "lpm_decode";
arriaii_lcell_comb le_comb10
(
.combout(wire_le_comb10_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.shareout(),
.sumout(),
.cin(1'b0),
.datad(1'b0),
.datae(1'b0),
.dataf(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
le_comb10.dont_touch = "on",
le_comb10.lut_mask = 64'hF0F0F0F0F0F0F0F0,
le_comb10.lpm_type = "arriaii_lcell_comb";
arriaii_lcell_comb le_comb8
(
.combout(wire_le_comb8_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.shareout(),
.sumout(),
.cin(1'b0),
.datad(1'b0),
.datae(1'b0),
.dataf(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
le_comb8.dont_touch = "on",
le_comb8.lut_mask = 64'hAAAAAAAAAAAAAAAA,
le_comb8.lpm_type = "arriaii_lcell_comb";
arriaii_lcell_comb le_comb9
(
.combout(wire_le_comb9_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.shareout(),
.sumout(),
.cin(1'b0),
.datad(1'b0),
.datae(1'b0),
.dataf(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
le_comb9.dont_touch = "on",
le_comb9.lut_mask = 64'hCCCCCCCCCCCCCCCC,
le_comb9.lpm_type = "arriaii_lcell_comb";
assign
addr_counter_enable = (write_data_state | write_nominal_state),
addr_counter_out = wire_cntr1_q,
addr_counter_sload = (write_init_state | write_init_nominal_state),
addr_counter_sload_value = (addr_decoder_out & {8{(write_init_state | write_init_nominal_state)}}),
addr_decoder_out = ((((((((((((((((((((((((((((((((((((((((((({{7{1'b0}}, (sel_type_cplf & sel_param_bypass_LF_unused)} | {{6{1'b0}}, {2{(sel_type_cplf & sel_param_c)}}}) | {{4{1'b0}}, (sel_type_cplf & sel_param_low_r), {3{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, {3{(sel_type_cplf & sel_param_odd_CP_unused)}}, 1'b0}) | {{3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale), {3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale)}) | {{3{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, {2{(sel_type_m & sel_param_high_i_postscale)}}, 1'b0, (sel_type_m & sel_param_high_i_postscale), 1'b0}) | {{3{1'b0}}, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}}) | {{2{1'b0}}, (sel_type_m & sel_param_low_r), {3{1'b0}}, {2{(sel_type_m & sel_param_low_r)}}}) | {{2{1'b0}}, (sel_type_m & sel_param_nominal_count), {3{1'b0}}, {2{(sel_type_m & sel_param_nominal_count)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_n & sel_param_high_i_postscale), 1'b0, {2{(sel_type_n & sel_param_high_i_postscale)}}, {2{1'b0}}}) | {{2{1'b0}}, (sel_type_n & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_n & sel_param_odd_CP_unused)}) | {{2{1'b0}}, {2{(sel_type_n & sel_param_low_r)}}, 1'b0, (sel_type_n & sel_param_low_r), 1'b0, (sel_type_n & sel_param_low_r)}) | {{2{1'b0}}, {2{(sel_type_n & sel_param_nominal_count)}}, 1'b0, (sel_type_n & sel_param_nominal_count), 1'b0, (sel_type_n & sel_param_nominal_count)}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {5{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r
), {3{1'b0}}, {3{(sel_type_c0 & sel_param_low_r)}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), 1'b0, (sel_type_c1 & sel_param_high_i_postscale), {4{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, {2{(sel_type_c1 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c1 & sel_param_low_r)}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, {3{1'b0}}, (sel_type_c2 & sel_param_high_i_postscale), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, 1'b0, (sel_type_c2 & sel_param_low_r), 1'b0, {2{(sel_type_c2 & sel_param_low_r)}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale), {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {5{(sel_type_c3 & sel_param_low_r)}}, 1'b0, (sel_type_c3 & sel_param_low_r)}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {(sel_type_c4 & sel_param_high_i_postscale), {4{1'b0}}, {2{(sel_type_c4 & sel_param_high_i_postscale)}}, 1'b0}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, {4{(sel_type_c4 & sel_param_low_r)}}}) | {(sel_type_c5 & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_c5 & sel_param_bypass_LF_unused),
{4{1'b0}}}) | {(sel_type_c5 & sel_param_high_i_postscale), {2{1'b0}}, {2{(sel_type_c5 & sel_param_high_i_postscale)}}, {3{1'b0}}}) | {(sel_type_c5 & sel_param_odd_CP_unused), {2{1'b0}}, {2{(sel_type_c5 & sel_param_odd_CP_unused)}}, {2{1'b0}}, (sel_type_c5 & sel_param_odd_CP_unused)}) | {(sel_type_c5 & sel_param_low_r), 1'b0, (sel_type_c5 & sel_param_low_r), {4{1'b0}}, (sel_type_c5 & sel_param_low_r)}) | {(sel_type_c6 & sel_param_bypass_LF_unused), 1'b0, (sel_type_c6 & sel_param_bypass_LF_unused), {3{1'b0}}, (sel_type_c6 & sel_param_bypass_LF_unused), 1'b0}) | {(sel_type_c6 & sel_param_high_i_postscale), 1'b0, (sel_type_c6 & sel_param_high_i_postscale), 1'b0, (sel_type_c6 & sel_param_high_i_postscale), 1'b0, (sel_type_c6 & sel_param_high_i_postscale), 1'b0}) | {(sel_type_c6 & sel_param_odd_CP_unused), 1'b0, (sel_type_c6 & sel_param_odd_CP_unused), 1'b0, (sel_type_c6 & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_c6 & sel_param_odd_CP_unused)}}}) | {(sel_type_c6 & sel_param_low_r), 1'b0, {2{(sel_type_c6 & sel_param_low_r)}}, {2{1'b0}}, {2{(sel_type_c6 & sel_param_low_r)}}}),
busy = ((~ idle_state) | areset_state),
c0_wire = 8'b01000111,
c1_wire = 8'b01011001,
c2_wire = 8'b01101011,
c3_wire = 8'b01111101,
c4_wire = 8'b10001111,
c5_wire = 8'b10100001,
c6_wire = 8'b10110011,
counter_param_latch = counter_param_latch_reg,
counter_type_latch = counter_type_latch_reg,
cuda_combout_wire = {wire_le_comb10_combout, wire_le_comb9_combout, wire_le_comb8_combout},
data_out = {((shift_reg8[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[8] & read_nominal_out)), ((shift_reg7[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[7] & read_nominal_out)), ((shift_reg6[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[6] & read_nominal_out)), ((shift_reg5[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[5] & read_nominal_out)), ((shift_reg4[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[4] & read_nominal_out)), ((shift_reg3[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[3] & read_nominal_out)), ((shift_reg2[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[2] & read_nominal_out)), ((shift_reg1[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[1] & read_nominal_out)), ((shift_reg0[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[0] & read_nominal_out))},
dummy_scandataout = pll_scandataout,
encode_out = {((C4_ena_state | C5_ena_state) | C6_ena_state), ((C2_ena_state | C3_ena_state) | C6_ena_state), ((C1_ena_state | C3_ena_state) | C5_ena_state)},
input_latch_enable = (idle_state & (write_param | read_param)),
pll_areset = (pll_areset_in | (areset_state & reconfig_wait_state)),
pll_configupdate = (configupdate_state & (~ configupdate3_state)),
pll_scanclk = clock,
pll_scanclkena = ((rotate_width_counter_enable & (~ rotate_width_counter_done)) | reconfig_seq_data_state),
pll_scandata = (scan_cache_out & ((rotate_width_counter_enable | reconfig_seq_data_state) | reconfig_post_state)),
power_up = ((((((((((((((((((((~ reset_state) & (~ idle_state)) & (~ read_init_state)) & (~ read_first_state)) & (~ read_data_state)) & (~ read_last_state)) & (~ read_init_nominal_state)) & (~ read_first_nominal_state)) & (~ read_data_nominal_state)) & (~ read_last_nominal_state)) & (~ write_init_state)) & (~ write_data_state)) & (~ write_init_nominal_state)) & (~ write_nominal_state)) & (~ reconfig_init_state)) & (~ reconfig_counter_state)) & (~ reconfig_seq_ena_state)) & (~ reconfig_seq_data_state)) & (~ reconfig_post_state)) & (~ reconfig_wait_state)),
read_addr_counter_enable = (((read_first_state | read_data_state) | read_first_nominal_state) | read_data_nominal_state),
read_addr_counter_out = wire_cntr2_q,
read_addr_counter_sload = (read_init_state | read_init_nominal_state),
read_addr_counter_sload_value = (read_addr_decoder_out & {8{(read_init_state | read_init_nominal_state)}}),
read_addr_decoder_out = ((((((((((((((((((((((((((((((((((((((((((({8{1'b0}} | {{6{1'b0}}, (sel_type_cplf & sel_param_c), 1'b0}) | {{5{1'b0}}, (sel_type_cplf & sel_param_low_r), {2{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0}) | {{4{1'b0}}, {4{(sel_type_cplf & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, (sel_type_m & sel_param_high_i_postscale), {2{1'b0}}, {2{(sel_type_m & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}}) | {{3{1'b0}}, {3{(sel_type_m & sel_param_low_r)}}, {2{1'b0}}}) | {{3{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}, (sel_type_m & sel_param_nominal_count), 1'b0}) | {{2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_n & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_n & sel_param_high_i_postscale), 1'b0, (sel_type_n & sel_param_high_i_postscale)}) | {{2{1'b0}}, (sel_type_n & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_n & sel_param_odd_CP_unused)}) | {{2{1'b0}}, (sel_type_n & sel_param_low_r), 1'b0, {3{(sel_type_n & sel_param_low_r)}}, 1'b0}) | {{2{1'b0}}, (sel_type_n & sel_param_nominal_count), {2{1'b0}}, (sel_type_n & sel_param_nominal_count), {2{1'b0}}}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0, {3{(sel_type_c0 & sel_param_high_i_postscale)}}}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r), {6{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused
), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale)}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, (sel_type_c1 & sel_param_low_r), {2{1'b0}}, (sel_type_c1 & sel_param_low_r), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_high_i_postscale), 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c2 & sel_param_low_r), {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale)}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {3{(sel_type_c3 & sel_param_low_r)}}, 1'b0, {2{(sel_type_c3 & sel_param_low_r)}}, 1'b0}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {1'b0, {7{(sel_type_c4 & sel_param_high_i_postscale)}}}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, (sel_type_c4 & sel_param_low_r), {3{1'b0}}}) | {(sel_type_c5 & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_c5 & sel_param_bypass_LF_unused), {4{1'b0}}}) | {(sel_type_c5 & sel_param_high_i_postscale
), {2{1'b0}}, (sel_type_c5 & sel_param_high_i_postscale), {3{1'b0}}, (sel_type_c5 & sel_param_high_i_postscale)}) | {(sel_type_c5 & sel_param_odd_CP_unused), {2{1'b0}}, {2{(sel_type_c5 & sel_param_odd_CP_unused)}}, {2{1'b0}}, (sel_type_c5 & sel_param_odd_CP_unused)}) | {(sel_type_c5 & sel_param_low_r), {2{1'b0}}, {2{(sel_type_c5 & sel_param_low_r)}}, 1'b0, (sel_type_c5 & sel_param_low_r), 1'b0}) | {(sel_type_c6 & sel_param_bypass_LF_unused), 1'b0, (sel_type_c6 & sel_param_bypass_LF_unused), {3{1'b0}}, (sel_type_c6 & sel_param_bypass_LF_unused), 1'b0}) | {(sel_type_c6 & sel_param_high_i_postscale), 1'b0, (sel_type_c6 & sel_param_high_i_postscale), {3{1'b0}}, {2{(sel_type_c6 & sel_param_high_i_postscale)}}}) | {(sel_type_c6 & sel_param_odd_CP_unused), 1'b0, (sel_type_c6 & sel_param_odd_CP_unused), 1'b0, (sel_type_c6 & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_c6 & sel_param_odd_CP_unused)}}}) | {(sel_type_c6 & sel_param_low_r), 1'b0, (sel_type_c6 & sel_param_low_r), 1'b0, {2{(sel_type_c6 & sel_param_low_r)}}, {2{1'b0}}}),
read_nominal_out = tmp_nominal_data_out_state,
reconfig_addr_counter_enable = reconfig_seq_data_state,
reconfig_addr_counter_out = wire_cntr12_q,
reconfig_addr_counter_sload = reconfig_seq_ena_state,
reconfig_addr_counter_sload_value = ({8{reconfig_seq_ena_state}} & seq_addr_wire),
reconfig_done = ((~ pll_scandone) & (dummy_scandataout | (~ dummy_scandataout))),
reconfig_post_done = pll_scandone,
reconfig_width_counter_done = ((((((~ wire_cntr13_q[0]) & (~ wire_cntr13_q[1])) & (~ wire_cntr13_q[2])) & (~ wire_cntr13_q[3])) & (~ wire_cntr13_q[4])) & (~ wire_cntr13_q[5])),
reconfig_width_counter_enable = reconfig_seq_data_state,
reconfig_width_counter_sload = reconfig_seq_ena_state,
reconfig_width_counter_sload_value = ({6{reconfig_seq_ena_state}} & seq_sload_value),
rotate_addr_counter_enable = ((((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state) | C5_data_state) | C6_data_state),
rotate_addr_counter_out = wire_cntr15_q,
rotate_addr_counter_sload = ((((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state) | C5_ena_state) | C6_ena_state),
rotate_addr_counter_sload_value = (((((((c0_wire & {8{rotate_decoder_wires[0]}}) | (c1_wire & {8{rotate_decoder_wires[1]}})) | (c2_wire & {8{rotate_decoder_wires[2]}})) | (c3_wire & {8{rotate_decoder_wires[3]}})) | (c4_wire & {8{rotate_decoder_wires[4]}})) | (c5_wire & {8{rotate_decoder_wires[5]}})) | (c6_wire & {8{rotate_decoder_wires[6]}})),
rotate_decoder_wires = wire_decode11_eq,
rotate_width_counter_done = (((((~ wire_cntr14_q[0]) & (~ wire_cntr14_q[1])) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[3])) & (~ wire_cntr14_q[4])),
rotate_width_counter_enable = ((((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state) | C5_data_state) | C6_data_state),
rotate_width_counter_sload = ((((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state) | C5_ena_state) | C6_ena_state),
rotate_width_counter_sload_value = 5'b10010,
scan_cache_address = ((((addr_counter_out & {8{addr_counter_enable}}) | (read_addr_counter_out & {8{read_addr_counter_enable}})) | (rotate_addr_counter_out & {8{rotate_addr_counter_enable}})) | (reconfig_addr_counter_out & {8{reconfig_addr_counter_enable}})),
scan_cache_in = shift_reg_serial_out,
scan_cache_out = wire_altsyncram4_q_a[0],
scan_cache_write_enable = (write_data_state | write_nominal_state),
sel_param_bypass_LF_unused = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & counter_param_latch[2]),
sel_param_c = (((~ counter_param_latch[0]) & counter_param_latch[1]) & (~ counter_param_latch[2])),
sel_param_high_i_postscale = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
sel_param_low_r = ((counter_param_latch[0] & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
sel_param_nominal_count = ((counter_param_latch[0] & counter_param_latch[1]) & counter_param_latch[2]),
sel_param_odd_CP_unused = ((counter_param_latch[0] & (~ counter_param_latch[1])) & counter_param_latch[2]),
sel_type_c0 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c1 = (((counter_type_latch[0] & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c2 = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c3 = (((counter_type_latch[0] & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c4 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & counter_type_latch[3]),
sel_type_c5 = (((counter_type_latch[0] & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & counter_type_latch[3]),
sel_type_c6 = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & (~ counter_type_latch[2])) & counter_type_latch[3]),
sel_type_cplf = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_m = (((counter_type_latch[0] & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_n = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_vco = (((counter_type_latch[0] & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
seq_addr_wire = 8'b00110101,
seq_sload_value = 6'b110110,
shift_reg_clear = (read_init_state | read_init_nominal_state),
shift_reg_load_enable = ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]))),
shift_reg_load_nominal_enable = ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])),
shift_reg_serial_in = scan_cache_out,
shift_reg_serial_out = ((((((((shift_reg17[0:0] & shift_reg_width_select[0]) | (shift_reg17[0:0] & shift_reg_width_select[1])) | (shift_reg17[0:0] & shift_reg_width_select[2])) | (shift_reg17[0:0] & shift_reg_width_select[3])) | (shift_reg17[0:0] & shift_reg_width_select[4])) | (shift_reg17[0:0] & shift_reg_width_select[5])) | (shift_reg17[0:0] & shift_reg_width_select[6])) | (shift_reg17[0:0] & shift_reg_width_select[7])),
shift_reg_shift_enable = ((read_data_state | read_last_state) | write_data_state),
shift_reg_shift_nominal_enable = ((read_data_nominal_state | read_last_nominal_state) | write_nominal_state),
shift_reg_width_select = width_decoder_select,
w1837w = 1'b0,
w1864w = 1'b0,
w64w = 1'b0,
width_counter_done = (((((~ wire_cntr3_q[0]) & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[2])) & (~ wire_cntr3_q[3])) & (~ wire_cntr3_q[4])),
width_counter_enable = ((((read_first_state | read_data_state) | write_data_state) | read_data_nominal_state) | write_nominal_state),
width_counter_sload = (((read_init_state | write_init_state) | read_init_nominal_state) | write_init_nominal_state),
width_counter_sload_value = width_decoder_out,
width_decoder_out = ((((({5{1'b0}} | {width_decoder_select[2], {3{1'b0}}, width_decoder_select[2]}) | {{4{1'b0}}, width_decoder_select[3]}) | {{2{1'b0}}, {3{width_decoder_select[5]}}}) | {{3{1'b0}}, width_decoder_select[6], 1'b0}) | {{2{1'b0}}, width_decoder_select[7], {2{1'b0}}}),
width_decoder_select = {((sel_type_cplf & sel_param_low_r) | (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((((((sel_type_m & sel_param_high_i_postscale) | (sel_type_m & sel_param_low_r)) | (sel_type_n & sel_param_high_i_postscale)) | (sel_type_n & sel_param_low_r)) | (sel_type_c0 & sel_param_high_i_postscale)) | (sel_type_c0 & sel_param_low_r)) | (sel_type_c1 & sel_param_high_i_postscale)) | (sel_type_c1 & sel_param_low_r)) | (sel_type_c2 & sel_param_high_i_postscale)) | (sel_type_c2 & sel_param_low_r)) | (sel_type_c3 & sel_param_high_i_postscale)) | (sel_type_c3 & sel_param_low_r)) | (sel_type_c4 & sel_param_high_i_postscale)) | (sel_type_c4 & sel_param_low_r)) | (sel_type_c5 & sel_param_high_i_postscale)) | (sel_type_c5 & sel_param_low_r)) | (sel_type_c6 & sel_param_high_i_postscale)) | (sel_type_c6 & sel_param_low_r)), w1864w, ((sel_type_cplf & sel_param_bypass_LF_unused) | (sel_type_cplf & sel_param_c)), ((sel_type_m & sel_param_nominal_count) | (sel_type_n & sel_param_nominal_count)), w1837w, (((((((((((((((((((sel_type_vco & sel_param_high_i_postscale) | (sel_type_m & sel_param_bypass_LF_unused)) | (sel_type_m & sel_param_odd_CP_unused)) | (sel_type_n & sel_param_bypass_LF_unused)) | (sel_type_n & sel_param_odd_CP_unused)) | (sel_type_c0 & sel_param_bypass_LF_unused)) | (sel_type_c0 & sel_param_odd_CP_unused)) | (sel_type_c1 & sel_param_bypass_LF_unused)) | (sel_type_c1 & sel_param_odd_CP_unused)) | (sel_type_c2 & sel_param_bypass_LF_unused)) | (sel_type_c2 & sel_param_odd_CP_unused)) | (sel_type_c3 & sel_param_bypass_LF_unused)) | (sel_type_c3 & sel_param_odd_CP_unused)) | (sel_type_c4 & sel_param_bypass_LF_unused)) | (sel_type_c4 & sel_param_odd_CP_unused)) | (sel_type_c5 & sel_param_bypass_LF_unused)) | (sel_type_c5 & sel_param_odd_CP_unused)) | (sel_type_c6 & sel_param_bypass_LF_unused)) | (sel_type_c6 & sel_param_odd_CP_unused))},
write_from_rom = 1'b0;
endmodule //pll_config_intf_pllrcfg_dgr
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_config_intf (
clock,
counter_param,
counter_type,
data_in,
pll_areset_in,
pll_scandataout,
pll_scandone,
read_param,
reconfig,
reset,
write_param,
busy,
data_out,
pll_areset,
pll_configupdate,
pll_scanclk,
pll_scanclkena,
pll_scandata)/* synthesis synthesis_clearbox = 2 */;
input clock;
input [2:0] counter_param;
input [3:0] counter_type;
input [8:0] data_in;
input pll_areset_in;
input pll_scandataout;
input pll_scandone;
input read_param;
input reconfig;
input reset;
input write_param;
output busy;
output [8:0] data_out;
output pll_areset;
output pll_configupdate;
output pll_scanclk;
output pll_scanclkena;
output pll_scandata;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 pll_areset_in;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [8:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire pll_configupdate = sub_wire0;
wire [8:0] data_out = sub_wire1[8:0];
wire pll_scanclk = sub_wire2;
wire pll_scanclkena = sub_wire3;
wire pll_scandata = sub_wire4;
wire busy = sub_wire5;
wire pll_areset = sub_wire6;
pll_config_intf_pllrcfg_dgr pll_config_intf_pllrcfg_dgr_component (
.counter_param (counter_param),
.data_in (data_in),
.counter_type (counter_type),
.pll_areset_in (pll_areset_in),
.reconfig (reconfig),
.pll_scandataout (pll_scandataout),
.pll_scandone (pll_scandone),
.reset (reset),
.write_param (write_param),
.clock (clock),
.read_param (read_param),
.pll_configupdate (sub_wire0),
.data_out (sub_wire1),
.pll_scanclk (sub_wire2),
.pll_scanclkena (sub_wire3),
.pll_scandata (sub_wire4),
.busy (sub_wire5),
.pll_areset (sub_wire6))/* synthesis synthesis_clearbox=2
clearbox_macroname = altpll_reconfig
clearbox_defparam = "intended_device_family=Arria II GX;pll_type=LEFT_RIGHT;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_NAME STRING ""
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_INIT_FILE STRING "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: PLL_TYPE STRING "LEFT_RIGHT"
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
// Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
// Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
// Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
// Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
// Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
// Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
// Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
// Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
// Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
// Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
// Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
// Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
// Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
// Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
// Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
// Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
// Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
// Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
// Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
// Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
// Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
// Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
// Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
// Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
// Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
// Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
// Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
// Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_intf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_intf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_intf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_intf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_intf_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_config_intf_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: arriaii
// Retrieval info: LIB_FILE: lpm
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions: I2C_CCD_Config
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module I2C_CCD_Config ( // Host Side
iCLK,
iRST_N,
iZOOM_MODE_SW,
iEXPOSURE_ADJ,
iEXPOSURE_DEC_p,
// I2C Side
I2C_SCLK,
I2C_SDAT
);
// Host Side
input iCLK;
input iRST_N;
input iZOOM_MODE_SW;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [31:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [23:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
////////////// CMOS sensor registers setting //////////////////////
input iEXPOSURE_ADJ;
input iEXPOSURE_DEC_p;
parameter default_exposure = 16'h07c0;
parameter exposure_change_value = 16'd200;
reg [24:0] combo_cnt;
wire combo_pulse;
reg [1:0] izoom_mode_sw_delay;
reg [3:0] iexposure_adj_delay;
wire exposure_adj_set;
wire exposure_adj_reset;
reg [15:0] senosr_exposure;
wire [17:0] senosr_exposure_temp;
wire [23:0] sensor_start_row;
wire [23:0] sensor_start_column;
wire [23:0] sensor_row_size;
wire [23:0] sensor_column_size;
wire [23:0] sensor_row_mode;
wire [23:0] sensor_column_mode;
//assign sensor_start_row = iZOOM_MODE_SW ? 24'h01029A : 24'h010132;
//assign sensor_start_column = iZOOM_MODE_SW ? 24'h0202A0 : 24'h020020;
assign sensor_start_row = iZOOM_MODE_SW ? 24'h010036 : 24'h010000;
assign sensor_start_column = iZOOM_MODE_SW ? 24'h020210 : 24'h020000;
assign sensor_row_size = iZOOM_MODE_SW ? 24'h0303BF : 24'h03077F;
assign sensor_column_size = iZOOM_MODE_SW ? 24'h0404FF : 24'h0409FF;
assign sensor_row_mode = iZOOM_MODE_SW ? 24'h220000 : 24'h220011;
assign sensor_column_mode = iZOOM_MODE_SW ? 24'h230000 : 24'h230011;
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
begin
iexposure_adj_delay <= 0;
end
else
begin
iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};
end
end
assign exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
assign exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;
assign senosr_exposure_temp = iEXPOSURE_DEC_p ? (senosr_exposure - exposure_change_value) : (senosr_exposure + exposure_change_value);
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
senosr_exposure <= default_exposure;
else if (exposure_adj_set|combo_pulse)
if (senosr_exposure_temp[17])
senosr_exposure <= 0;
else if (senosr_exposure_temp[16])
senosr_exposure <= 16'hffff;
else
senosr_exposure <= senosr_exposure_temp[15:0];
end
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
combo_cnt <= 0;
else if (!iexposure_adj_delay[3])
combo_cnt <= combo_cnt + 1;
else
combo_cnt <= 0;
end
assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;
wire i2c_reset;
assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
/////////////////////////////////////////////////////////////////////
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 25;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge i2c_reset)
begin
if(!i2c_reset)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(i2c_reset)
);
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
begin
if(!i2c_reset)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'hBA,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
0 : LUT_DATA <= 24'h000000;
1 : LUT_DATA <= 24'h20c000; // Mirror Row and Columns
2 : LUT_DATA <= {8'h09,senosr_exposure};// Exposure
3 : LUT_DATA <= 24'h050000; // H_Blanking
4 : LUT_DATA <= 24'h060019; // V_Blanking
5 : LUT_DATA <= 24'h0A8000; // change latch
6 : LUT_DATA <= 24'h2B0013; // Green 1 Gain
7 : LUT_DATA <= 24'h2C009A; // Blue Gain
8 : LUT_DATA <= 24'h2D019C; // Red Gain
9 : LUT_DATA <= 24'h2E0013; // Green 2 Gain
10 : LUT_DATA <= 24'h100051; // set up PLL power on
11 : LUT_DATA <= 24'h111805; // PLL_m_Factor<<8+PLL_n_Divider
12 : LUT_DATA <= 24'h120003; // PLL_p1_Divider
13 : LUT_DATA <= 24'h100053; // set USE PLL
14 : LUT_DATA <= 24'h980000; // disble calibration
15 : LUT_DATA <= 24'hA00000; // Test pattern control
16 : LUT_DATA <= 24'hA10000; // Test green pattern value
17 : LUT_DATA <= 24'hA20FFF; // Test red pattern value
18 : LUT_DATA <= sensor_start_row ; // set start row
19 : LUT_DATA <= sensor_start_column ; // set start column
20 : LUT_DATA <= sensor_row_size; // set row size
21 : LUT_DATA <= sensor_column_size; // set column size
22 : LUT_DATA <= sensor_row_mode; // set row mode in bin mode
23 : LUT_DATA <= sensor_column_mode; // set column mode in bin mode
24 : LUT_DATA <= 24'h4901A8; // row black target
default:LUT_DATA <= 24'h000000;
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/20/2017 09:46:54 PM
// Design Name:
// Module Name: fifo2shiftreg_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo2shiftreg_tb #(parameter WIDTH=32,
parameter CLK_DIV=2)();
reg CLK;
reg RESET;
reg WR_CLK;
reg [15:0] DIN;
reg WR_EN;
reg WR_PULSE;
wire FULL;
wire SCLK;
wire DOUT;
wire SYNCn;
fifo2shiftreg #(.WIDTH(WIDTH), .CLK_DIV(CLK_DIV))
uut(
.CLK(CLK), // clock
.RESET(RESET), // reset
// input data interface
.WR_CLK(WR_CLK), // FIFO write clock
.DIN(DIN),
.WR_EN(WR_EN),
.WR_PULSE(WR_PULSE), // one pulse writes one word, regardless of pulse duration
.FULL(FULL),
// output
.SCLK(SCLK),
.DOUT(DOUT),
.SYNCn(SYNCn)
);
//initial begin
//$dumpfile("fifo2shiftreg.dump");
//$dumpvars(0, fifo2shiftreg);
//end
initial begin
CLK=0;
forever #20 CLK=~CLK;
end
initial begin
WR_CLK=0;
forever #20 WR_CLK=~WR_CLK;
end
initial begin
RESET=0;
WR_EN=0;
#100 RESET=1;
#100 RESET=0;
end
initial begin
DIN=16'b1101_0100_1011_1001;
WR_PULSE=0;
#340 WR_PULSE=1;
#40 WR_PULSE=0;
#40 DIN=16'b1101_0101_1011_1001;
#40 WR_PULSE=1;
#40 WR_PULSE=0;
#40 DIN=16'b1101_0101_1011_1011;
#11960 WR_PULSE=1;
#40 WR_PULSE=0;
#40 DIN=16'b1101_0101_1001_1011;
#40 WR_PULSE=1;
#40 WR_PULSE=0;
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Tue Nov 5 11:24:29 EST 2013
//
//
// Ports:
// Name I/O size props
// RDY_server_request_put O 1
// server_response_get O 153
// RDY_server_response_get O 1
// RDY_cpServer_request_put O 1 reg
// cpServer_response_get O 40 reg
// RDY_cpServer_response_get O 1 reg
// led O 2 reg
// wci_m_0_MCmd O 3
// wci_m_0_MAddrSpace O 1
// wci_m_0_MByteEn O 4
// wci_m_0_MAddr O 32
// wci_m_0_MData O 32 reg
// wci_m_0_MFlag O 2 reg
// wci_m_1_MCmd O 3
// wci_m_1_MAddrSpace O 1
// wci_m_1_MByteEn O 4
// wci_m_1_MAddr O 32
// wci_m_1_MData O 32 reg
// wci_m_1_MFlag O 2 reg
// wci_m_2_MCmd O 3
// wci_m_2_MAddrSpace O 1
// wci_m_2_MByteEn O 4
// wci_m_2_MAddr O 32
// wci_m_2_MData O 32 reg
// wci_m_2_MFlag O 2 reg
// wci_m_3_MCmd O 3
// wci_m_3_MAddrSpace O 1
// wci_m_3_MByteEn O 4
// wci_m_3_MAddr O 32
// wci_m_3_MData O 32 reg
// wci_m_3_MFlag O 2 reg
// wci_m_4_MCmd O 3
// wci_m_4_MAddrSpace O 1
// wci_m_4_MByteEn O 4
// wci_m_4_MAddr O 32
// wci_m_4_MData O 32 reg
// wci_m_4_MFlag O 2 reg
// cpNow O 64 reg
// RDY_cpNow O 1 const
// wsi_s_adc_SThreadBusy O 1 const
// wsi_s_adc_SReset_n O 1 const
// wsi_m_dac_MCmd O 3 const
// wsi_m_dac_MReqLast O 1 const
// wsi_m_dac_MBurstPrecise O 1 const
// wsi_m_dac_MBurstLength O 12 const
// wsi_m_dac_MData O 32 const
// wsi_m_dac_MByteEn O 4 const
// wsi_m_dac_MReqInfo O 8 const
// wsi_m_dac_MReset_n O 1 const
// wmemiM0_MCmd O 3 reg
// wmemiM0_MReqLast O 1 reg
// wmemiM0_MAddr O 36 reg
// wmemiM0_MBurstLength O 12 reg
// wmemiM0_MDataValid O 1 reg
// wmemiM0_MDataLast O 1 reg
// wmemiM0_MData O 128 reg
// wmemiM0_MDataByteEn O 16 reg
// wmemiM0_MReset_n O 1
// gps_ppsSyncOut O 1
// RST_N_wci_m_0 O 1 reset
// RST_N_wci_m_1 O 1 reset
// RST_N_wci_m_2 O 1 reset
// RST_N_wci_m_3 O 1 reset
// RST_N_wci_m_4 O 1 reset
// pciDevice I 16
// CLK_sys0_clk I 1 clock
// RST_N_sys0_rst I 1 reset
// CLK I 1 clock
// RST_N I 1 reset
// server_request_put I 153
// cpServer_request_put I 59 reg
// switch_x I 3 reg
// wci_m_0_SResp I 2
// wci_m_0_SData I 32
// wci_m_0_SFlag I 2 reg
// wci_m_1_SResp I 2
// wci_m_1_SData I 32
// wci_m_1_SFlag I 2 reg
// wci_m_2_SResp I 2
// wci_m_2_SData I 32
// wci_m_2_SFlag I 2 reg
// wci_m_3_SResp I 2
// wci_m_3_SData I 32
// wci_m_3_SFlag I 2 reg
// wci_m_4_SResp I 2
// wci_m_4_SData I 32
// wci_m_4_SFlag I 2 reg
// wsi_s_adc_MCmd I 3 unused
// wsi_s_adc_MBurstLength I 12 unused
// wsi_s_adc_MData I 32 unused
// wsi_s_adc_MByteEn I 4 unused
// wsi_s_adc_MReqInfo I 8 unused
// wmemiM0_SResp I 2
// wmemiM0_SData I 128
// gps_ppsSyncIn_x I 1 reg
// EN_server_request_put I 1
// EN_cpServer_request_put I 1
// wci_m_0_SThreadBusy I 1 reg
// wci_m_1_SThreadBusy I 1 reg
// wci_m_2_SThreadBusy I 1 reg
// wci_m_3_SThreadBusy I 1 reg
// wci_m_4_SThreadBusy I 1 reg
// wsi_s_adc_MReqLast I 1 unused
// wsi_s_adc_MBurstPrecise I 1 unused
// wsi_s_adc_MReset_n I 1 unused
// wsi_m_dac_SThreadBusy I 1 unused
// wsi_m_dac_SReset_n I 1 unused
// wmemiM0_SRespLast I 1
// wmemiM0_SCmdAccept I 1
// wmemiM0_SDataAccept I 1
// EN_server_response_get I 1
// EN_cpServer_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCTop4B(pciDevice,
CLK_sys0_clk,
RST_N_sys0_rst,
CLK,
RST_N,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get,
cpServer_request_put,
EN_cpServer_request_put,
RDY_cpServer_request_put,
EN_cpServer_response_get,
cpServer_response_get,
RDY_cpServer_response_get,
led,
switch_x,
wci_m_0_MCmd,
wci_m_0_MAddrSpace,
wci_m_0_MByteEn,
wci_m_0_MAddr,
wci_m_0_MData,
wci_m_0_SResp,
wci_m_0_SData,
wci_m_0_SThreadBusy,
wci_m_0_SFlag,
wci_m_0_MFlag,
wci_m_1_MCmd,
wci_m_1_MAddrSpace,
wci_m_1_MByteEn,
wci_m_1_MAddr,
wci_m_1_MData,
wci_m_1_SResp,
wci_m_1_SData,
wci_m_1_SThreadBusy,
wci_m_1_SFlag,
wci_m_1_MFlag,
wci_m_2_MCmd,
wci_m_2_MAddrSpace,
wci_m_2_MByteEn,
wci_m_2_MAddr,
wci_m_2_MData,
wci_m_2_SResp,
wci_m_2_SData,
wci_m_2_SThreadBusy,
wci_m_2_SFlag,
wci_m_2_MFlag,
wci_m_3_MCmd,
wci_m_3_MAddrSpace,
wci_m_3_MByteEn,
wci_m_3_MAddr,
wci_m_3_MData,
wci_m_3_SResp,
wci_m_3_SData,
wci_m_3_SThreadBusy,
wci_m_3_SFlag,
wci_m_3_MFlag,
wci_m_4_MCmd,
wci_m_4_MAddrSpace,
wci_m_4_MByteEn,
wci_m_4_MAddr,
wci_m_4_MData,
wci_m_4_SResp,
wci_m_4_SData,
wci_m_4_SThreadBusy,
wci_m_4_SFlag,
wci_m_4_MFlag,
cpNow,
RDY_cpNow,
wsi_s_adc_MCmd,
wsi_s_adc_MReqLast,
wsi_s_adc_MBurstPrecise,
wsi_s_adc_MBurstLength,
wsi_s_adc_MData,
wsi_s_adc_MByteEn,
wsi_s_adc_MReqInfo,
wsi_s_adc_SThreadBusy,
wsi_s_adc_SReset_n,
wsi_s_adc_MReset_n,
wsi_m_dac_MCmd,
wsi_m_dac_MReqLast,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MBurstLength,
wsi_m_dac_MData,
wsi_m_dac_MByteEn,
wsi_m_dac_MReqInfo,
wsi_m_dac_SThreadBusy,
wsi_m_dac_MReset_n,
wsi_m_dac_SReset_n,
wmemiM0_MCmd,
wmemiM0_MReqLast,
wmemiM0_MAddr,
wmemiM0_MBurstLength,
wmemiM0_MDataValid,
wmemiM0_MDataLast,
wmemiM0_MData,
wmemiM0_MDataByteEn,
wmemiM0_SResp,
wmemiM0_SRespLast,
wmemiM0_SData,
wmemiM0_SCmdAccept,
wmemiM0_SDataAccept,
wmemiM0_MReset_n,
gps_ppsSyncIn_x,
gps_ppsSyncOut,
RST_N_wci_m_0,
RST_N_wci_m_1,
RST_N_wci_m_2,
RST_N_wci_m_3,
RST_N_wci_m_4);
input [15 : 0] pciDevice;
input CLK_sys0_clk;
input RST_N_sys0_rst;
input CLK;
input RST_N;
// action method server_request_put
input [152 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [152 : 0] server_response_get;
output RDY_server_response_get;
// action method cpServer_request_put
input [58 : 0] cpServer_request_put;
input EN_cpServer_request_put;
output RDY_cpServer_request_put;
// actionvalue method cpServer_response_get
input EN_cpServer_response_get;
output [39 : 0] cpServer_response_get;
output RDY_cpServer_response_get;
// value method led
output [1 : 0] led;
// action method switch
input [2 : 0] switch_x;
// value method wci_m_0_mCmd
output [2 : 0] wci_m_0_MCmd;
// value method wci_m_0_mAddrSpace
output wci_m_0_MAddrSpace;
// value method wci_m_0_mByteEn
output [3 : 0] wci_m_0_MByteEn;
// value method wci_m_0_mAddr
output [31 : 0] wci_m_0_MAddr;
// value method wci_m_0_mData
output [31 : 0] wci_m_0_MData;
// action method wci_m_0_sResp
input [1 : 0] wci_m_0_SResp;
// action method wci_m_0_sData
input [31 : 0] wci_m_0_SData;
// action method wci_m_0_sThreadBusy
input wci_m_0_SThreadBusy;
// action method wci_m_0_sFlag
input [1 : 0] wci_m_0_SFlag;
// value method wci_m_0_mFlag
output [1 : 0] wci_m_0_MFlag;
// value method wci_m_1_mCmd
output [2 : 0] wci_m_1_MCmd;
// value method wci_m_1_mAddrSpace
output wci_m_1_MAddrSpace;
// value method wci_m_1_mByteEn
output [3 : 0] wci_m_1_MByteEn;
// value method wci_m_1_mAddr
output [31 : 0] wci_m_1_MAddr;
// value method wci_m_1_mData
output [31 : 0] wci_m_1_MData;
// action method wci_m_1_sResp
input [1 : 0] wci_m_1_SResp;
// action method wci_m_1_sData
input [31 : 0] wci_m_1_SData;
// action method wci_m_1_sThreadBusy
input wci_m_1_SThreadBusy;
// action method wci_m_1_sFlag
input [1 : 0] wci_m_1_SFlag;
// value method wci_m_1_mFlag
output [1 : 0] wci_m_1_MFlag;
// value method wci_m_2_mCmd
output [2 : 0] wci_m_2_MCmd;
// value method wci_m_2_mAddrSpace
output wci_m_2_MAddrSpace;
// value method wci_m_2_mByteEn
output [3 : 0] wci_m_2_MByteEn;
// value method wci_m_2_mAddr
output [31 : 0] wci_m_2_MAddr;
// value method wci_m_2_mData
output [31 : 0] wci_m_2_MData;
// action method wci_m_2_sResp
input [1 : 0] wci_m_2_SResp;
// action method wci_m_2_sData
input [31 : 0] wci_m_2_SData;
// action method wci_m_2_sThreadBusy
input wci_m_2_SThreadBusy;
// action method wci_m_2_sFlag
input [1 : 0] wci_m_2_SFlag;
// value method wci_m_2_mFlag
output [1 : 0] wci_m_2_MFlag;
// value method wci_m_3_mCmd
output [2 : 0] wci_m_3_MCmd;
// value method wci_m_3_mAddrSpace
output wci_m_3_MAddrSpace;
// value method wci_m_3_mByteEn
output [3 : 0] wci_m_3_MByteEn;
// value method wci_m_3_mAddr
output [31 : 0] wci_m_3_MAddr;
// value method wci_m_3_mData
output [31 : 0] wci_m_3_MData;
// action method wci_m_3_sResp
input [1 : 0] wci_m_3_SResp;
// action method wci_m_3_sData
input [31 : 0] wci_m_3_SData;
// action method wci_m_3_sThreadBusy
input wci_m_3_SThreadBusy;
// action method wci_m_3_sFlag
input [1 : 0] wci_m_3_SFlag;
// value method wci_m_3_mFlag
output [1 : 0] wci_m_3_MFlag;
// value method wci_m_4_mCmd
output [2 : 0] wci_m_4_MCmd;
// value method wci_m_4_mAddrSpace
output wci_m_4_MAddrSpace;
// value method wci_m_4_mByteEn
output [3 : 0] wci_m_4_MByteEn;
// value method wci_m_4_mAddr
output [31 : 0] wci_m_4_MAddr;
// value method wci_m_4_mData
output [31 : 0] wci_m_4_MData;
// action method wci_m_4_sResp
input [1 : 0] wci_m_4_SResp;
// action method wci_m_4_sData
input [31 : 0] wci_m_4_SData;
// action method wci_m_4_sThreadBusy
input wci_m_4_SThreadBusy;
// action method wci_m_4_sFlag
input [1 : 0] wci_m_4_SFlag;
// value method wci_m_4_mFlag
output [1 : 0] wci_m_4_MFlag;
// value method cpNow
output [63 : 0] cpNow;
output RDY_cpNow;
// action method wsi_s_adc_mCmd
input [2 : 0] wsi_s_adc_MCmd;
// action method wsi_s_adc_mReqLast
input wsi_s_adc_MReqLast;
// action method wsi_s_adc_mBurstPrecise
input wsi_s_adc_MBurstPrecise;
// action method wsi_s_adc_mBurstLength
input [11 : 0] wsi_s_adc_MBurstLength;
// action method wsi_s_adc_mData
input [31 : 0] wsi_s_adc_MData;
// action method wsi_s_adc_mByteEn
input [3 : 0] wsi_s_adc_MByteEn;
// action method wsi_s_adc_mReqInfo
input [7 : 0] wsi_s_adc_MReqInfo;
// action method wsi_s_adc_mDataInfo
// value method wsi_s_adc_sThreadBusy
output wsi_s_adc_SThreadBusy;
// value method wsi_s_adc_sReset_n
output wsi_s_adc_SReset_n;
// action method wsi_s_adc_mReset_n
input wsi_s_adc_MReset_n;
// value method wsi_m_dac_mCmd
output [2 : 0] wsi_m_dac_MCmd;
// value method wsi_m_dac_mReqLast
output wsi_m_dac_MReqLast;
// value method wsi_m_dac_mBurstPrecise
output wsi_m_dac_MBurstPrecise;
// value method wsi_m_dac_mBurstLength
output [11 : 0] wsi_m_dac_MBurstLength;
// value method wsi_m_dac_mData
output [31 : 0] wsi_m_dac_MData;
// value method wsi_m_dac_mByteEn
output [3 : 0] wsi_m_dac_MByteEn;
// value method wsi_m_dac_mReqInfo
output [7 : 0] wsi_m_dac_MReqInfo;
// value method wsi_m_dac_mDataInfo
// action method wsi_m_dac_sThreadBusy
input wsi_m_dac_SThreadBusy;
// value method wsi_m_dac_mReset_n
output wsi_m_dac_MReset_n;
// action method wsi_m_dac_sReset_n
input wsi_m_dac_SReset_n;
// value method wmemiM0_mCmd
output [2 : 0] wmemiM0_MCmd;
// value method wmemiM0_mReqLast
output wmemiM0_MReqLast;
// value method wmemiM0_mAddr
output [35 : 0] wmemiM0_MAddr;
// value method wmemiM0_mBurstLength
output [11 : 0] wmemiM0_MBurstLength;
// value method wmemiM0_mDataValid
output wmemiM0_MDataValid;
// value method wmemiM0_mDataLast
output wmemiM0_MDataLast;
// value method wmemiM0_mData
output [127 : 0] wmemiM0_MData;
// value method wmemiM0_mDataByteEn
output [15 : 0] wmemiM0_MDataByteEn;
// action method wmemiM0_sResp
input [1 : 0] wmemiM0_SResp;
// action method wmemiM0_sRespLast
input wmemiM0_SRespLast;
// action method wmemiM0_sData
input [127 : 0] wmemiM0_SData;
// action method wmemiM0_sCmdAccept
input wmemiM0_SCmdAccept;
// action method wmemiM0_sDataAccept
input wmemiM0_SDataAccept;
// value method wmemiM0_mReset_n
output wmemiM0_MReset_n;
// action method gps_ppsSyncIn
input gps_ppsSyncIn_x;
// value method gps_ppsSyncOut
output gps_ppsSyncOut;
// output resets
output RST_N_wci_m_0;
output RST_N_wci_m_1;
output RST_N_wci_m_2;
output RST_N_wci_m_3;
output RST_N_wci_m_4;
// signals for module outputs
wire [152 : 0] server_response_get;
wire [127 : 0] wmemiM0_MData;
wire [63 : 0] cpNow;
wire [39 : 0] cpServer_response_get;
wire [35 : 0] wmemiM0_MAddr;
wire [31 : 0] wci_m_0_MAddr,
wci_m_0_MData,
wci_m_1_MAddr,
wci_m_1_MData,
wci_m_2_MAddr,
wci_m_2_MData,
wci_m_3_MAddr,
wci_m_3_MData,
wci_m_4_MAddr,
wci_m_4_MData,
wsi_m_dac_MData;
wire [15 : 0] wmemiM0_MDataByteEn;
wire [11 : 0] wmemiM0_MBurstLength, wsi_m_dac_MBurstLength;
wire [7 : 0] wsi_m_dac_MReqInfo;
wire [3 : 0] wci_m_0_MByteEn,
wci_m_1_MByteEn,
wci_m_2_MByteEn,
wci_m_3_MByteEn,
wci_m_4_MByteEn,
wsi_m_dac_MByteEn;
wire [2 : 0] wci_m_0_MCmd,
wci_m_1_MCmd,
wci_m_2_MCmd,
wci_m_3_MCmd,
wci_m_4_MCmd,
wmemiM0_MCmd,
wsi_m_dac_MCmd;
wire [1 : 0] led,
wci_m_0_MFlag,
wci_m_1_MFlag,
wci_m_2_MFlag,
wci_m_3_MFlag,
wci_m_4_MFlag;
wire RDY_cpNow,
RDY_cpServer_request_put,
RDY_cpServer_response_get,
RDY_server_request_put,
RDY_server_response_get,
RST_N_wci_m_0,
RST_N_wci_m_1,
RST_N_wci_m_2,
RST_N_wci_m_3,
RST_N_wci_m_4,
gps_ppsSyncOut,
wci_m_0_MAddrSpace,
wci_m_1_MAddrSpace,
wci_m_2_MAddrSpace,
wci_m_3_MAddrSpace,
wci_m_4_MAddrSpace,
wmemiM0_MDataLast,
wmemiM0_MDataValid,
wmemiM0_MReqLast,
wmemiM0_MReset_n,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MReqLast,
wsi_m_dac_MReset_n,
wsi_s_adc_SReset_n,
wsi_s_adc_SThreadBusy;
// inlined wires
wire wtiM_0_peerIsReady_1$wget,
wtiM_0_peerIsReady_1$whas,
wtiM_0_sThreadBusy_pw$whas,
wtiM_1_peerIsReady_1$wget,
wtiM_1_peerIsReady_1$whas,
wtiM_1_sThreadBusy_pw$whas,
wtiM_2_peerIsReady_1$wget,
wtiM_2_peerIsReady_1$whas,
wtiM_2_sThreadBusy_pw$whas;
// register wtiM_0_nowReq
reg [66 : 0] wtiM_0_nowReq;
wire [66 : 0] wtiM_0_nowReq$D_IN;
wire wtiM_0_nowReq$EN;
// register wtiM_0_peerIsReady
reg wtiM_0_peerIsReady;
wire wtiM_0_peerIsReady$D_IN, wtiM_0_peerIsReady$EN;
// register wtiM_0_sThreadBusy_d
reg wtiM_0_sThreadBusy_d;
wire wtiM_0_sThreadBusy_d$D_IN, wtiM_0_sThreadBusy_d$EN;
// register wtiM_1_nowReq
reg [66 : 0] wtiM_1_nowReq;
wire [66 : 0] wtiM_1_nowReq$D_IN;
wire wtiM_1_nowReq$EN;
// register wtiM_1_peerIsReady
reg wtiM_1_peerIsReady;
wire wtiM_1_peerIsReady$D_IN, wtiM_1_peerIsReady$EN;
// register wtiM_1_sThreadBusy_d
reg wtiM_1_sThreadBusy_d;
wire wtiM_1_sThreadBusy_d$D_IN, wtiM_1_sThreadBusy_d$EN;
// register wtiM_2_nowReq
reg [66 : 0] wtiM_2_nowReq;
wire [66 : 0] wtiM_2_nowReq$D_IN;
wire wtiM_2_nowReq$EN;
// register wtiM_2_peerIsReady
reg wtiM_2_peerIsReady;
wire wtiM_2_peerIsReady$D_IN, wtiM_2_peerIsReady$EN;
// register wtiM_2_sThreadBusy_d
reg wtiM_2_sThreadBusy_d;
wire wtiM_2_sThreadBusy_d$D_IN, wtiM_2_sThreadBusy_d$EN;
// ports of submodule app
wire [511 : 0] app$uuid;
wire [127 : 0] app$wmemiM0_MData, app$wmemiM0_SData;
wire [63 : 0] app$wti_s_0_MData, app$wti_s_1_MData, app$wti_s_2_MData;
wire [35 : 0] app$wmemiM0_MAddr;
wire [31 : 0] app$wci_s_0_MAddr,
app$wci_s_0_MData,
app$wci_s_0_SData,
app$wci_s_1_MAddr,
app$wci_s_1_MData,
app$wci_s_1_SData,
app$wci_s_2_MAddr,
app$wci_s_2_MData,
app$wci_s_2_SData,
app$wci_s_3_MAddr,
app$wci_s_3_MData,
app$wci_s_3_SData,
app$wci_s_4_MAddr,
app$wci_s_4_MData,
app$wci_s_4_SData,
app$wci_s_5_MAddr,
app$wci_s_5_MData,
app$wci_s_5_SData,
app$wci_s_6_MAddr,
app$wci_s_6_MData,
app$wci_s_6_SData,
app$wci_s_7_MAddr,
app$wci_s_7_MData,
app$wci_s_7_SData,
app$wmiM0_MData,
app$wmiM0_MFlag,
app$wmiM0_SData,
app$wmiM0_SFlag,
app$wmiM1_MData,
app$wmiM1_MFlag,
app$wmiM1_SData,
app$wmiM1_SFlag,
app$wsi_s_adc_MData;
wire [15 : 0] app$wmemiM0_MDataByteEn;
wire [13 : 0] app$wmiM0_MAddr, app$wmiM1_MAddr;
wire [11 : 0] app$wmemiM0_MBurstLength,
app$wmiM0_MBurstLength,
app$wmiM1_MBurstLength,
app$wsi_s_adc_MBurstLength;
wire [7 : 0] app$wsi_s_adc_MReqInfo;
wire [3 : 0] app$wci_s_0_MByteEn,
app$wci_s_1_MByteEn,
app$wci_s_2_MByteEn,
app$wci_s_3_MByteEn,
app$wci_s_4_MByteEn,
app$wci_s_5_MByteEn,
app$wci_s_6_MByteEn,
app$wci_s_7_MByteEn,
app$wmiM0_MDataByteEn,
app$wmiM1_MDataByteEn,
app$wsi_s_adc_MByteEn;
wire [2 : 0] app$wci_s_0_MCmd,
app$wci_s_1_MCmd,
app$wci_s_2_MCmd,
app$wci_s_3_MCmd,
app$wci_s_4_MCmd,
app$wci_s_5_MCmd,
app$wci_s_6_MCmd,
app$wci_s_7_MCmd,
app$wmemiM0_MCmd,
app$wmiM0_MCmd,
app$wmiM1_MCmd,
app$wsi_s_adc_MCmd,
app$wti_s_0_MCmd,
app$wti_s_1_MCmd,
app$wti_s_2_MCmd;
wire [1 : 0] app$wci_s_0_MFlag,
app$wci_s_0_SFlag,
app$wci_s_0_SResp,
app$wci_s_1_MFlag,
app$wci_s_1_SFlag,
app$wci_s_1_SResp,
app$wci_s_2_MFlag,
app$wci_s_2_SFlag,
app$wci_s_2_SResp,
app$wci_s_3_MFlag,
app$wci_s_3_SFlag,
app$wci_s_3_SResp,
app$wci_s_4_MFlag,
app$wci_s_4_SFlag,
app$wci_s_4_SResp,
app$wci_s_5_MFlag,
app$wci_s_5_SFlag,
app$wci_s_5_SResp,
app$wci_s_6_MFlag,
app$wci_s_6_SFlag,
app$wci_s_6_SResp,
app$wci_s_7_MFlag,
app$wci_s_7_SFlag,
app$wci_s_7_SResp,
app$wmemiM0_SResp,
app$wmiM0_SResp,
app$wmiM1_SResp;
wire app$wci_s_0_MAddrSpace,
app$wci_s_0_SThreadBusy,
app$wci_s_1_MAddrSpace,
app$wci_s_1_SThreadBusy,
app$wci_s_2_MAddrSpace,
app$wci_s_2_SThreadBusy,
app$wci_s_3_MAddrSpace,
app$wci_s_3_SThreadBusy,
app$wci_s_4_MAddrSpace,
app$wci_s_4_SThreadBusy,
app$wci_s_5_MAddrSpace,
app$wci_s_5_SThreadBusy,
app$wci_s_6_MAddrSpace,
app$wci_s_6_SThreadBusy,
app$wci_s_7_MAddrSpace,
app$wci_s_7_SThreadBusy,
app$wmemiM0_MDataLast,
app$wmemiM0_MDataValid,
app$wmemiM0_MReqLast,
app$wmemiM0_MReset_n,
app$wmemiM0_SCmdAccept,
app$wmemiM0_SDataAccept,
app$wmemiM0_SRespLast,
app$wmiM0_MAddrSpace,
app$wmiM0_MDataLast,
app$wmiM0_MDataValid,
app$wmiM0_MReqInfo,
app$wmiM0_MReqLast,
app$wmiM0_MReset_n,
app$wmiM0_SDataThreadBusy,
app$wmiM0_SReset_n,
app$wmiM0_SRespLast,
app$wmiM0_SThreadBusy,
app$wmiM1_MAddrSpace,
app$wmiM1_MDataLast,
app$wmiM1_MDataValid,
app$wmiM1_MReqInfo,
app$wmiM1_MReqLast,
app$wmiM1_MReset_n,
app$wmiM1_SDataThreadBusy,
app$wmiM1_SReset_n,
app$wmiM1_SRespLast,
app$wmiM1_SThreadBusy,
app$wsi_m_dac_SReset_n,
app$wsi_m_dac_SThreadBusy,
app$wsi_s_adc_MBurstPrecise,
app$wsi_s_adc_MReqLast,
app$wsi_s_adc_MReset_n,
app$wti_s_0_SReset_n,
app$wti_s_0_SThreadBusy,
app$wti_s_1_SReset_n,
app$wti_s_1_SThreadBusy,
app$wti_s_2_SReset_n,
app$wti_s_2_SThreadBusy;
// ports of submodule ctNow
wire [63 : 0] ctNow$dD_OUT, ctNow$sD_IN;
wire ctNow$sEN, ctNow$sRDY;
// ports of submodule inf
wire [511 : 0] inf$uuid_arg;
wire [152 : 0] inf$server_request_put, inf$server_response_get;
wire [63 : 0] inf$cpNow;
wire [58 : 0] inf$cpServer_request_put;
wire [39 : 0] inf$cpServer_response_get;
wire [31 : 0] inf$wci_m_0_MAddr,
inf$wci_m_0_MData,
inf$wci_m_0_SData,
inf$wci_m_10_MAddr,
inf$wci_m_10_MData,
inf$wci_m_10_SData,
inf$wci_m_11_MAddr,
inf$wci_m_11_MData,
inf$wci_m_11_SData,
inf$wci_m_12_MAddr,
inf$wci_m_12_MData,
inf$wci_m_12_SData,
inf$wci_m_1_MAddr,
inf$wci_m_1_MData,
inf$wci_m_1_SData,
inf$wci_m_2_MAddr,
inf$wci_m_2_MData,
inf$wci_m_2_SData,
inf$wci_m_3_MAddr,
inf$wci_m_3_MData,
inf$wci_m_3_SData,
inf$wci_m_4_MAddr,
inf$wci_m_4_MData,
inf$wci_m_4_SData,
inf$wci_m_5_MAddr,
inf$wci_m_5_MData,
inf$wci_m_5_SData,
inf$wci_m_6_MAddr,
inf$wci_m_6_MData,
inf$wci_m_6_SData,
inf$wci_m_7_MAddr,
inf$wci_m_7_MData,
inf$wci_m_7_SData,
inf$wci_m_8_MAddr,
inf$wci_m_8_MData,
inf$wci_m_8_SData,
inf$wci_m_9_MAddr,
inf$wci_m_9_MData,
inf$wci_m_9_SData,
inf$wmiDP0_MData,
inf$wmiDP0_SData,
inf$wmiDP0_SFlag,
inf$wmiDP0_arg_mFlag,
inf$wmiDP1_MData,
inf$wmiDP1_SData,
inf$wmiDP1_SFlag,
inf$wmiDP1_arg_mFlag;
wire [13 : 0] inf$wmiDP0_MAddr, inf$wmiDP1_MAddr;
wire [11 : 0] inf$wmiDP0_MBurstLength, inf$wmiDP1_MBurstLength;
wire [3 : 0] inf$wci_m_0_MByteEn,
inf$wci_m_10_MByteEn,
inf$wci_m_11_MByteEn,
inf$wci_m_12_MByteEn,
inf$wci_m_1_MByteEn,
inf$wci_m_2_MByteEn,
inf$wci_m_3_MByteEn,
inf$wci_m_4_MByteEn,
inf$wci_m_5_MByteEn,
inf$wci_m_6_MByteEn,
inf$wci_m_7_MByteEn,
inf$wci_m_8_MByteEn,
inf$wci_m_9_MByteEn,
inf$wmiDP0_MDataByteEn,
inf$wmiDP1_MDataByteEn;
wire [2 : 0] inf$switch_x,
inf$wci_m_0_MCmd,
inf$wci_m_10_MCmd,
inf$wci_m_11_MCmd,
inf$wci_m_12_MCmd,
inf$wci_m_1_MCmd,
inf$wci_m_2_MCmd,
inf$wci_m_3_MCmd,
inf$wci_m_4_MCmd,
inf$wci_m_5_MCmd,
inf$wci_m_6_MCmd,
inf$wci_m_7_MCmd,
inf$wci_m_8_MCmd,
inf$wci_m_9_MCmd,
inf$wmiDP0_MCmd,
inf$wmiDP1_MCmd;
wire [1 : 0] inf$led,
inf$wci_m_0_MFlag,
inf$wci_m_0_SFlag,
inf$wci_m_0_SResp,
inf$wci_m_10_MFlag,
inf$wci_m_10_SFlag,
inf$wci_m_10_SResp,
inf$wci_m_11_MFlag,
inf$wci_m_11_SFlag,
inf$wci_m_11_SResp,
inf$wci_m_12_MFlag,
inf$wci_m_12_SFlag,
inf$wci_m_12_SResp,
inf$wci_m_1_MFlag,
inf$wci_m_1_SFlag,
inf$wci_m_1_SResp,
inf$wci_m_2_MFlag,
inf$wci_m_2_SFlag,
inf$wci_m_2_SResp,
inf$wci_m_3_MFlag,
inf$wci_m_3_SFlag,
inf$wci_m_3_SResp,
inf$wci_m_4_MFlag,
inf$wci_m_4_SFlag,
inf$wci_m_4_SResp,
inf$wci_m_5_MFlag,
inf$wci_m_5_SFlag,
inf$wci_m_5_SResp,
inf$wci_m_6_MFlag,
inf$wci_m_6_SFlag,
inf$wci_m_6_SResp,
inf$wci_m_7_MFlag,
inf$wci_m_7_SFlag,
inf$wci_m_7_SResp,
inf$wci_m_8_MFlag,
inf$wci_m_8_SFlag,
inf$wci_m_8_SResp,
inf$wci_m_9_MFlag,
inf$wci_m_9_SFlag,
inf$wci_m_9_SResp,
inf$wmiDP0_SResp,
inf$wmiDP1_SResp;
wire inf$EN_cpServer_request_put,
inf$EN_cpServer_response_get,
inf$EN_server_request_put,
inf$EN_server_response_get,
inf$RDY_cpServer_request_put,
inf$RDY_cpServer_response_get,
inf$RDY_server_request_put,
inf$RDY_server_response_get,
inf$RST_N_wci_m_0,
inf$RST_N_wci_m_1,
inf$RST_N_wci_m_10,
inf$RST_N_wci_m_11,
inf$RST_N_wci_m_12,
inf$RST_N_wci_m_2,
inf$RST_N_wci_m_3,
inf$RST_N_wci_m_4,
inf$RST_N_wci_m_5,
inf$RST_N_wci_m_6,
inf$RST_N_wci_m_7,
inf$RST_N_wci_m_8,
inf$RST_N_wci_m_9,
inf$gps_ppsSyncIn_x,
inf$gps_ppsSyncOut,
inf$wci_m_0_MAddrSpace,
inf$wci_m_0_SThreadBusy,
inf$wci_m_10_MAddrSpace,
inf$wci_m_10_SThreadBusy,
inf$wci_m_11_MAddrSpace,
inf$wci_m_11_SThreadBusy,
inf$wci_m_12_MAddrSpace,
inf$wci_m_12_SThreadBusy,
inf$wci_m_1_MAddrSpace,
inf$wci_m_1_SThreadBusy,
inf$wci_m_2_MAddrSpace,
inf$wci_m_2_SThreadBusy,
inf$wci_m_3_MAddrSpace,
inf$wci_m_3_SThreadBusy,
inf$wci_m_4_MAddrSpace,
inf$wci_m_4_SThreadBusy,
inf$wci_m_5_MAddrSpace,
inf$wci_m_5_SThreadBusy,
inf$wci_m_6_MAddrSpace,
inf$wci_m_6_SThreadBusy,
inf$wci_m_7_MAddrSpace,
inf$wci_m_7_SThreadBusy,
inf$wci_m_8_MAddrSpace,
inf$wci_m_8_SThreadBusy,
inf$wci_m_9_MAddrSpace,
inf$wci_m_9_SThreadBusy,
inf$wmiDP0_MAddrSpace,
inf$wmiDP0_MDataLast,
inf$wmiDP0_MDataValid,
inf$wmiDP0_MReqInfo,
inf$wmiDP0_MReqLast,
inf$wmiDP0_MReset_n,
inf$wmiDP0_SDataThreadBusy,
inf$wmiDP0_SReset_n,
inf$wmiDP0_SRespLast,
inf$wmiDP0_SThreadBusy,
inf$wmiDP1_MAddrSpace,
inf$wmiDP1_MDataLast,
inf$wmiDP1_MDataValid,
inf$wmiDP1_MReqInfo,
inf$wmiDP1_MReqLast,
inf$wmiDP1_MReset_n,
inf$wmiDP1_SDataThreadBusy,
inf$wmiDP1_SReset_n,
inf$wmiDP1_SRespLast,
inf$wmiDP1_SThreadBusy;
// output resets
assign RST_N_wci_m_0 = inf$RST_N_wci_m_8 ;
assign RST_N_wci_m_1 = inf$RST_N_wci_m_9 ;
assign RST_N_wci_m_2 = inf$RST_N_wci_m_10 ;
assign RST_N_wci_m_3 = inf$RST_N_wci_m_11 ;
assign RST_N_wci_m_4 = inf$RST_N_wci_m_12 ;
// action method server_request_put
assign RDY_server_request_put = inf$RDY_server_request_put ;
// actionvalue method server_response_get
assign server_response_get = inf$server_response_get ;
assign RDY_server_response_get = inf$RDY_server_response_get ;
// action method cpServer_request_put
assign RDY_cpServer_request_put = inf$RDY_cpServer_request_put ;
// actionvalue method cpServer_response_get
assign cpServer_response_get = inf$cpServer_response_get ;
assign RDY_cpServer_response_get = inf$RDY_cpServer_response_get ;
// value method led
assign led = inf$led ;
// value method wci_m_0_mCmd
assign wci_m_0_MCmd = inf$wci_m_8_MCmd ;
// value method wci_m_0_mAddrSpace
assign wci_m_0_MAddrSpace = inf$wci_m_8_MAddrSpace ;
// value method wci_m_0_mByteEn
assign wci_m_0_MByteEn = inf$wci_m_8_MByteEn ;
// value method wci_m_0_mAddr
assign wci_m_0_MAddr = inf$wci_m_8_MAddr ;
// value method wci_m_0_mData
assign wci_m_0_MData = inf$wci_m_8_MData ;
// value method wci_m_0_mFlag
assign wci_m_0_MFlag = inf$wci_m_8_MFlag ;
// value method wci_m_1_mCmd
assign wci_m_1_MCmd = inf$wci_m_9_MCmd ;
// value method wci_m_1_mAddrSpace
assign wci_m_1_MAddrSpace = inf$wci_m_9_MAddrSpace ;
// value method wci_m_1_mByteEn
assign wci_m_1_MByteEn = inf$wci_m_9_MByteEn ;
// value method wci_m_1_mAddr
assign wci_m_1_MAddr = inf$wci_m_9_MAddr ;
// value method wci_m_1_mData
assign wci_m_1_MData = inf$wci_m_9_MData ;
// value method wci_m_1_mFlag
assign wci_m_1_MFlag = inf$wci_m_9_MFlag ;
// value method wci_m_2_mCmd
assign wci_m_2_MCmd = inf$wci_m_10_MCmd ;
// value method wci_m_2_mAddrSpace
assign wci_m_2_MAddrSpace = inf$wci_m_10_MAddrSpace ;
// value method wci_m_2_mByteEn
assign wci_m_2_MByteEn = inf$wci_m_10_MByteEn ;
// value method wci_m_2_mAddr
assign wci_m_2_MAddr = inf$wci_m_10_MAddr ;
// value method wci_m_2_mData
assign wci_m_2_MData = inf$wci_m_10_MData ;
// value method wci_m_2_mFlag
assign wci_m_2_MFlag = inf$wci_m_10_MFlag ;
// value method wci_m_3_mCmd
assign wci_m_3_MCmd = inf$wci_m_11_MCmd ;
// value method wci_m_3_mAddrSpace
assign wci_m_3_MAddrSpace = inf$wci_m_11_MAddrSpace ;
// value method wci_m_3_mByteEn
assign wci_m_3_MByteEn = inf$wci_m_11_MByteEn ;
// value method wci_m_3_mAddr
assign wci_m_3_MAddr = inf$wci_m_11_MAddr ;
// value method wci_m_3_mData
assign wci_m_3_MData = inf$wci_m_11_MData ;
// value method wci_m_3_mFlag
assign wci_m_3_MFlag = inf$wci_m_11_MFlag ;
// value method wci_m_4_mCmd
assign wci_m_4_MCmd = inf$wci_m_12_MCmd ;
// value method wci_m_4_mAddrSpace
assign wci_m_4_MAddrSpace = inf$wci_m_12_MAddrSpace ;
// value method wci_m_4_mByteEn
assign wci_m_4_MByteEn = inf$wci_m_12_MByteEn ;
// value method wci_m_4_mAddr
assign wci_m_4_MAddr = inf$wci_m_12_MAddr ;
// value method wci_m_4_mData
assign wci_m_4_MData = inf$wci_m_12_MData ;
// value method wci_m_4_mFlag
assign wci_m_4_MFlag = inf$wci_m_12_MFlag ;
// value method cpNow
assign cpNow = inf$cpNow ;
assign RDY_cpNow = 1'd1 ;
// value method wsi_s_adc_sThreadBusy
assign wsi_s_adc_SThreadBusy = 1'h0 ;
// value method wsi_s_adc_sReset_n
assign wsi_s_adc_SReset_n = 1'h0 ;
// value method wsi_m_dac_mCmd
assign wsi_m_dac_MCmd = 3'h2 ;
// value method wsi_m_dac_mReqLast
assign wsi_m_dac_MReqLast = 1'h0 ;
// value method wsi_m_dac_mBurstPrecise
assign wsi_m_dac_MBurstPrecise = 1'h0 ;
// value method wsi_m_dac_mBurstLength
assign wsi_m_dac_MBurstLength = 12'hAAA ;
// value method wsi_m_dac_mData
assign wsi_m_dac_MData = 32'hAAAAAAAA ;
// value method wsi_m_dac_mByteEn
assign wsi_m_dac_MByteEn = 4'hA ;
// value method wsi_m_dac_mReqInfo
assign wsi_m_dac_MReqInfo = 8'hAA ;
// value method wsi_m_dac_mReset_n
assign wsi_m_dac_MReset_n = 1'h0 ;
// value method wmemiM0_mCmd
assign wmemiM0_MCmd = app$wmemiM0_MCmd ;
// value method wmemiM0_mReqLast
assign wmemiM0_MReqLast = app$wmemiM0_MReqLast ;
// value method wmemiM0_mAddr
assign wmemiM0_MAddr = app$wmemiM0_MAddr ;
// value method wmemiM0_mBurstLength
assign wmemiM0_MBurstLength = app$wmemiM0_MBurstLength ;
// value method wmemiM0_mDataValid
assign wmemiM0_MDataValid = app$wmemiM0_MDataValid ;
// value method wmemiM0_mDataLast
assign wmemiM0_MDataLast = app$wmemiM0_MDataLast ;
// value method wmemiM0_mData
assign wmemiM0_MData = app$wmemiM0_MData ;
// value method wmemiM0_mDataByteEn
assign wmemiM0_MDataByteEn = app$wmemiM0_MDataByteEn ;
// value method wmemiM0_mReset_n
assign wmemiM0_MReset_n = app$wmemiM0_MReset_n ;
// value method gps_ppsSyncOut
assign gps_ppsSyncOut = inf$gps_ppsSyncOut ;
// submodule app
mkOCApp4B #(.hasDebugLogic(1'd1)) app(.RST_N_rst_0(inf$RST_N_wci_m_0),
.RST_N_rst_1(inf$RST_N_wci_m_1),
.RST_N_rst_2(inf$RST_N_wci_m_2),
.RST_N_rst_3(inf$RST_N_wci_m_3),
.RST_N_rst_4(inf$RST_N_wci_m_4),
.RST_N_rst_5(inf$RST_N_wci_m_5),
.RST_N_rst_6(inf$RST_N_wci_m_6),
.RST_N_rst_7(inf$RST_N_wci_m_7),
.CLK(CLK),
.RST_N(RST_N),
.wci_s_0_MAddr(app$wci_s_0_MAddr),
.wci_s_0_MAddrSpace(app$wci_s_0_MAddrSpace),
.wci_s_0_MByteEn(app$wci_s_0_MByteEn),
.wci_s_0_MCmd(app$wci_s_0_MCmd),
.wci_s_0_MData(app$wci_s_0_MData),
.wci_s_0_MFlag(app$wci_s_0_MFlag),
.wci_s_1_MAddr(app$wci_s_1_MAddr),
.wci_s_1_MAddrSpace(app$wci_s_1_MAddrSpace),
.wci_s_1_MByteEn(app$wci_s_1_MByteEn),
.wci_s_1_MCmd(app$wci_s_1_MCmd),
.wci_s_1_MData(app$wci_s_1_MData),
.wci_s_1_MFlag(app$wci_s_1_MFlag),
.wci_s_2_MAddr(app$wci_s_2_MAddr),
.wci_s_2_MAddrSpace(app$wci_s_2_MAddrSpace),
.wci_s_2_MByteEn(app$wci_s_2_MByteEn),
.wci_s_2_MCmd(app$wci_s_2_MCmd),
.wci_s_2_MData(app$wci_s_2_MData),
.wci_s_2_MFlag(app$wci_s_2_MFlag),
.wci_s_3_MAddr(app$wci_s_3_MAddr),
.wci_s_3_MAddrSpace(app$wci_s_3_MAddrSpace),
.wci_s_3_MByteEn(app$wci_s_3_MByteEn),
.wci_s_3_MCmd(app$wci_s_3_MCmd),
.wci_s_3_MData(app$wci_s_3_MData),
.wci_s_3_MFlag(app$wci_s_3_MFlag),
.wci_s_4_MAddr(app$wci_s_4_MAddr),
.wci_s_4_MAddrSpace(app$wci_s_4_MAddrSpace),
.wci_s_4_MByteEn(app$wci_s_4_MByteEn),
.wci_s_4_MCmd(app$wci_s_4_MCmd),
.wci_s_4_MData(app$wci_s_4_MData),
.wci_s_4_MFlag(app$wci_s_4_MFlag),
.wci_s_5_MAddr(app$wci_s_5_MAddr),
.wci_s_5_MAddrSpace(app$wci_s_5_MAddrSpace),
.wci_s_5_MByteEn(app$wci_s_5_MByteEn),
.wci_s_5_MCmd(app$wci_s_5_MCmd),
.wci_s_5_MData(app$wci_s_5_MData),
.wci_s_5_MFlag(app$wci_s_5_MFlag),
.wci_s_6_MAddr(app$wci_s_6_MAddr),
.wci_s_6_MAddrSpace(app$wci_s_6_MAddrSpace),
.wci_s_6_MByteEn(app$wci_s_6_MByteEn),
.wci_s_6_MCmd(app$wci_s_6_MCmd),
.wci_s_6_MData(app$wci_s_6_MData),
.wci_s_6_MFlag(app$wci_s_6_MFlag),
.wci_s_7_MAddr(app$wci_s_7_MAddr),
.wci_s_7_MAddrSpace(app$wci_s_7_MAddrSpace),
.wci_s_7_MByteEn(app$wci_s_7_MByteEn),
.wci_s_7_MCmd(app$wci_s_7_MCmd),
.wci_s_7_MData(app$wci_s_7_MData),
.wci_s_7_MFlag(app$wci_s_7_MFlag),
.wmemiM0_SData(app$wmemiM0_SData),
.wmemiM0_SResp(app$wmemiM0_SResp),
.wmiM0_SData(app$wmiM0_SData),
.wmiM0_SFlag(app$wmiM0_SFlag),
.wmiM0_SResp(app$wmiM0_SResp),
.wmiM1_SData(app$wmiM1_SData),
.wmiM1_SFlag(app$wmiM1_SFlag),
.wmiM1_SResp(app$wmiM1_SResp),
.wsi_s_adc_MBurstLength(app$wsi_s_adc_MBurstLength),
.wsi_s_adc_MByteEn(app$wsi_s_adc_MByteEn),
.wsi_s_adc_MCmd(app$wsi_s_adc_MCmd),
.wsi_s_adc_MData(app$wsi_s_adc_MData),
.wsi_s_adc_MReqInfo(app$wsi_s_adc_MReqInfo),
.wti_s_0_MCmd(app$wti_s_0_MCmd),
.wti_s_0_MData(app$wti_s_0_MData),
.wti_s_1_MCmd(app$wti_s_1_MCmd),
.wti_s_1_MData(app$wti_s_1_MData),
.wti_s_2_MCmd(app$wti_s_2_MCmd),
.wti_s_2_MData(app$wti_s_2_MData),
.wmiM0_SThreadBusy(app$wmiM0_SThreadBusy),
.wmiM0_SDataThreadBusy(app$wmiM0_SDataThreadBusy),
.wmiM0_SRespLast(app$wmiM0_SRespLast),
.wmiM0_SReset_n(app$wmiM0_SReset_n),
.wmiM1_SThreadBusy(app$wmiM1_SThreadBusy),
.wmiM1_SDataThreadBusy(app$wmiM1_SDataThreadBusy),
.wmiM1_SRespLast(app$wmiM1_SRespLast),
.wmiM1_SReset_n(app$wmiM1_SReset_n),
.wmemiM0_SRespLast(app$wmemiM0_SRespLast),
.wmemiM0_SCmdAccept(app$wmemiM0_SCmdAccept),
.wmemiM0_SDataAccept(app$wmemiM0_SDataAccept),
.wsi_s_adc_MReqLast(app$wsi_s_adc_MReqLast),
.wsi_s_adc_MBurstPrecise(app$wsi_s_adc_MBurstPrecise),
.wsi_s_adc_MReset_n(app$wsi_s_adc_MReset_n),
.wsi_m_dac_SThreadBusy(app$wsi_m_dac_SThreadBusy),
.wsi_m_dac_SReset_n(app$wsi_m_dac_SReset_n),
.wci_s_0_SResp(app$wci_s_0_SResp),
.wci_s_0_SData(app$wci_s_0_SData),
.wci_s_0_SThreadBusy(app$wci_s_0_SThreadBusy),
.wci_s_0_SFlag(app$wci_s_0_SFlag),
.wci_s_1_SResp(app$wci_s_1_SResp),
.wci_s_1_SData(app$wci_s_1_SData),
.wci_s_1_SThreadBusy(app$wci_s_1_SThreadBusy),
.wci_s_1_SFlag(app$wci_s_1_SFlag),
.wci_s_2_SResp(app$wci_s_2_SResp),
.wci_s_2_SData(app$wci_s_2_SData),
.wci_s_2_SThreadBusy(app$wci_s_2_SThreadBusy),
.wci_s_2_SFlag(app$wci_s_2_SFlag),
.wci_s_3_SResp(app$wci_s_3_SResp),
.wci_s_3_SData(app$wci_s_3_SData),
.wci_s_3_SThreadBusy(app$wci_s_3_SThreadBusy),
.wci_s_3_SFlag(app$wci_s_3_SFlag),
.wci_s_4_SResp(app$wci_s_4_SResp),
.wci_s_4_SData(app$wci_s_4_SData),
.wci_s_4_SThreadBusy(app$wci_s_4_SThreadBusy),
.wci_s_4_SFlag(app$wci_s_4_SFlag),
.wci_s_5_SResp(app$wci_s_5_SResp),
.wci_s_5_SData(app$wci_s_5_SData),
.wci_s_5_SThreadBusy(app$wci_s_5_SThreadBusy),
.wci_s_5_SFlag(app$wci_s_5_SFlag),
.wci_s_6_SResp(app$wci_s_6_SResp),
.wci_s_6_SData(app$wci_s_6_SData),
.wci_s_6_SThreadBusy(app$wci_s_6_SThreadBusy),
.wci_s_6_SFlag(app$wci_s_6_SFlag),
.wci_s_7_SResp(app$wci_s_7_SResp),
.wci_s_7_SData(app$wci_s_7_SData),
.wci_s_7_SThreadBusy(app$wci_s_7_SThreadBusy),
.wci_s_7_SFlag(app$wci_s_7_SFlag),
.wti_s_0_SThreadBusy(app$wti_s_0_SThreadBusy),
.wti_s_0_SReset_n(app$wti_s_0_SReset_n),
.wti_s_1_SThreadBusy(app$wti_s_1_SThreadBusy),
.wti_s_1_SReset_n(app$wti_s_1_SReset_n),
.wti_s_2_SThreadBusy(app$wti_s_2_SThreadBusy),
.wti_s_2_SReset_n(app$wti_s_2_SReset_n),
.wmiM0_MCmd(app$wmiM0_MCmd),
.wmiM0_MReqLast(app$wmiM0_MReqLast),
.wmiM0_MReqInfo(app$wmiM0_MReqInfo),
.wmiM0_MAddrSpace(app$wmiM0_MAddrSpace),
.wmiM0_MAddr(app$wmiM0_MAddr),
.wmiM0_MBurstLength(app$wmiM0_MBurstLength),
.wmiM0_MDataValid(app$wmiM0_MDataValid),
.wmiM0_MDataLast(app$wmiM0_MDataLast),
.wmiM0_MData(app$wmiM0_MData),
.wmiM0_MDataByteEn(app$wmiM0_MDataByteEn),
.wmiM0_MFlag(app$wmiM0_MFlag),
.wmiM0_MReset_n(app$wmiM0_MReset_n),
.wmiM1_MCmd(app$wmiM1_MCmd),
.wmiM1_MReqLast(app$wmiM1_MReqLast),
.wmiM1_MReqInfo(app$wmiM1_MReqInfo),
.wmiM1_MAddrSpace(app$wmiM1_MAddrSpace),
.wmiM1_MAddr(app$wmiM1_MAddr),
.wmiM1_MBurstLength(app$wmiM1_MBurstLength),
.wmiM1_MDataValid(app$wmiM1_MDataValid),
.wmiM1_MDataLast(app$wmiM1_MDataLast),
.wmiM1_MData(app$wmiM1_MData),
.wmiM1_MDataByteEn(app$wmiM1_MDataByteEn),
.wmiM1_MFlag(app$wmiM1_MFlag),
.wmiM1_MReset_n(app$wmiM1_MReset_n),
.wmemiM0_MCmd(app$wmemiM0_MCmd),
.wmemiM0_MReqLast(app$wmemiM0_MReqLast),
.wmemiM0_MAddr(app$wmemiM0_MAddr),
.wmemiM0_MBurstLength(app$wmemiM0_MBurstLength),
.wmemiM0_MDataValid(app$wmemiM0_MDataValid),
.wmemiM0_MDataLast(app$wmemiM0_MDataLast),
.wmemiM0_MData(app$wmemiM0_MData),
.wmemiM0_MDataByteEn(app$wmemiM0_MDataByteEn),
.wmemiM0_MReset_n(app$wmemiM0_MReset_n),
.wsi_s_adc_SThreadBusy(),
.wsi_s_adc_SReset_n(),
.wsi_m_dac_MCmd(),
.wsi_m_dac_MReqLast(),
.wsi_m_dac_MBurstPrecise(),
.wsi_m_dac_MBurstLength(),
.wsi_m_dac_MData(),
.wsi_m_dac_MByteEn(),
.wsi_m_dac_MReqInfo(),
.wsi_m_dac_MReset_n(),
.uuid(app$uuid));
// submodule ctNow
SyncRegister #(.width(32'd64), .init(64'd0)) ctNow(.sCLK(CLK_sys0_clk),
.dCLK(CLK),
.sRST(RST_N_sys0_rst),
.sD_IN(ctNow$sD_IN),
.sEN(ctNow$sEN),
.dD_OUT(ctNow$dD_OUT),
.sRDY(ctNow$sRDY));
// submodule inf
mkOCInf4B inf(.pciDevice(pciDevice),
.CLK_sys0_clk(CLK_sys0_clk),
.RST_N_sys0_rst(RST_N_sys0_rst),
.CLK(CLK),
.RST_N(RST_N),
.cpServer_request_put(inf$cpServer_request_put),
.gps_ppsSyncIn_x(inf$gps_ppsSyncIn_x),
.server_request_put(inf$server_request_put),
.switch_x(inf$switch_x),
.uuid_arg(inf$uuid_arg),
.wci_m_0_SData(inf$wci_m_0_SData),
.wci_m_0_SFlag(inf$wci_m_0_SFlag),
.wci_m_0_SResp(inf$wci_m_0_SResp),
.wci_m_10_SData(inf$wci_m_10_SData),
.wci_m_10_SFlag(inf$wci_m_10_SFlag),
.wci_m_10_SResp(inf$wci_m_10_SResp),
.wci_m_11_SData(inf$wci_m_11_SData),
.wci_m_11_SFlag(inf$wci_m_11_SFlag),
.wci_m_11_SResp(inf$wci_m_11_SResp),
.wci_m_12_SData(inf$wci_m_12_SData),
.wci_m_12_SFlag(inf$wci_m_12_SFlag),
.wci_m_12_SResp(inf$wci_m_12_SResp),
.wci_m_1_SData(inf$wci_m_1_SData),
.wci_m_1_SFlag(inf$wci_m_1_SFlag),
.wci_m_1_SResp(inf$wci_m_1_SResp),
.wci_m_2_SData(inf$wci_m_2_SData),
.wci_m_2_SFlag(inf$wci_m_2_SFlag),
.wci_m_2_SResp(inf$wci_m_2_SResp),
.wci_m_3_SData(inf$wci_m_3_SData),
.wci_m_3_SFlag(inf$wci_m_3_SFlag),
.wci_m_3_SResp(inf$wci_m_3_SResp),
.wci_m_4_SData(inf$wci_m_4_SData),
.wci_m_4_SFlag(inf$wci_m_4_SFlag),
.wci_m_4_SResp(inf$wci_m_4_SResp),
.wci_m_5_SData(inf$wci_m_5_SData),
.wci_m_5_SFlag(inf$wci_m_5_SFlag),
.wci_m_5_SResp(inf$wci_m_5_SResp),
.wci_m_6_SData(inf$wci_m_6_SData),
.wci_m_6_SFlag(inf$wci_m_6_SFlag),
.wci_m_6_SResp(inf$wci_m_6_SResp),
.wci_m_7_SData(inf$wci_m_7_SData),
.wci_m_7_SFlag(inf$wci_m_7_SFlag),
.wci_m_7_SResp(inf$wci_m_7_SResp),
.wci_m_8_SData(inf$wci_m_8_SData),
.wci_m_8_SFlag(inf$wci_m_8_SFlag),
.wci_m_8_SResp(inf$wci_m_8_SResp),
.wci_m_9_SData(inf$wci_m_9_SData),
.wci_m_9_SFlag(inf$wci_m_9_SFlag),
.wci_m_9_SResp(inf$wci_m_9_SResp),
.wmiDP0_MAddr(inf$wmiDP0_MAddr),
.wmiDP0_MAddrSpace(inf$wmiDP0_MAddrSpace),
.wmiDP0_MBurstLength(inf$wmiDP0_MBurstLength),
.wmiDP0_MCmd(inf$wmiDP0_MCmd),
.wmiDP0_MData(inf$wmiDP0_MData),
.wmiDP0_MDataByteEn(inf$wmiDP0_MDataByteEn),
.wmiDP0_MReqInfo(inf$wmiDP0_MReqInfo),
.wmiDP0_arg_mFlag(inf$wmiDP0_arg_mFlag),
.wmiDP1_MAddr(inf$wmiDP1_MAddr),
.wmiDP1_MAddrSpace(inf$wmiDP1_MAddrSpace),
.wmiDP1_MBurstLength(inf$wmiDP1_MBurstLength),
.wmiDP1_MCmd(inf$wmiDP1_MCmd),
.wmiDP1_MData(inf$wmiDP1_MData),
.wmiDP1_MDataByteEn(inf$wmiDP1_MDataByteEn),
.wmiDP1_MReqInfo(inf$wmiDP1_MReqInfo),
.wmiDP1_arg_mFlag(inf$wmiDP1_arg_mFlag),
.EN_server_request_put(inf$EN_server_request_put),
.EN_server_response_get(inf$EN_server_response_get),
.EN_cpServer_request_put(inf$EN_cpServer_request_put),
.EN_cpServer_response_get(inf$EN_cpServer_response_get),
.wci_m_0_SThreadBusy(inf$wci_m_0_SThreadBusy),
.wci_m_1_SThreadBusy(inf$wci_m_1_SThreadBusy),
.wci_m_2_SThreadBusy(inf$wci_m_2_SThreadBusy),
.wci_m_3_SThreadBusy(inf$wci_m_3_SThreadBusy),
.wci_m_4_SThreadBusy(inf$wci_m_4_SThreadBusy),
.wci_m_5_SThreadBusy(inf$wci_m_5_SThreadBusy),
.wci_m_6_SThreadBusy(inf$wci_m_6_SThreadBusy),
.wci_m_7_SThreadBusy(inf$wci_m_7_SThreadBusy),
.wci_m_8_SThreadBusy(inf$wci_m_8_SThreadBusy),
.wci_m_9_SThreadBusy(inf$wci_m_9_SThreadBusy),
.wci_m_10_SThreadBusy(inf$wci_m_10_SThreadBusy),
.wci_m_11_SThreadBusy(inf$wci_m_11_SThreadBusy),
.wci_m_12_SThreadBusy(inf$wci_m_12_SThreadBusy),
.wmiDP0_MReqLast(inf$wmiDP0_MReqLast),
.wmiDP0_MDataValid(inf$wmiDP0_MDataValid),
.wmiDP0_MDataLast(inf$wmiDP0_MDataLast),
.wmiDP0_MReset_n(inf$wmiDP0_MReset_n),
.wmiDP1_MReqLast(inf$wmiDP1_MReqLast),
.wmiDP1_MDataValid(inf$wmiDP1_MDataValid),
.wmiDP1_MDataLast(inf$wmiDP1_MDataLast),
.wmiDP1_MReset_n(inf$wmiDP1_MReset_n),
.RDY_server_request_put(inf$RDY_server_request_put),
.server_response_get(inf$server_response_get),
.RDY_server_response_get(inf$RDY_server_response_get),
.RDY_cpServer_request_put(inf$RDY_cpServer_request_put),
.cpServer_response_get(inf$cpServer_response_get),
.RDY_cpServer_response_get(inf$RDY_cpServer_response_get),
.led(inf$led),
.wci_m_0_MCmd(inf$wci_m_0_MCmd),
.wci_m_0_MAddrSpace(inf$wci_m_0_MAddrSpace),
.wci_m_0_MByteEn(inf$wci_m_0_MByteEn),
.wci_m_0_MAddr(inf$wci_m_0_MAddr),
.wci_m_0_MData(inf$wci_m_0_MData),
.wci_m_0_MFlag(inf$wci_m_0_MFlag),
.wci_m_1_MCmd(inf$wci_m_1_MCmd),
.wci_m_1_MAddrSpace(inf$wci_m_1_MAddrSpace),
.wci_m_1_MByteEn(inf$wci_m_1_MByteEn),
.wci_m_1_MAddr(inf$wci_m_1_MAddr),
.wci_m_1_MData(inf$wci_m_1_MData),
.wci_m_1_MFlag(inf$wci_m_1_MFlag),
.wci_m_2_MCmd(inf$wci_m_2_MCmd),
.wci_m_2_MAddrSpace(inf$wci_m_2_MAddrSpace),
.wci_m_2_MByteEn(inf$wci_m_2_MByteEn),
.wci_m_2_MAddr(inf$wci_m_2_MAddr),
.wci_m_2_MData(inf$wci_m_2_MData),
.wci_m_2_MFlag(inf$wci_m_2_MFlag),
.wci_m_3_MCmd(inf$wci_m_3_MCmd),
.wci_m_3_MAddrSpace(inf$wci_m_3_MAddrSpace),
.wci_m_3_MByteEn(inf$wci_m_3_MByteEn),
.wci_m_3_MAddr(inf$wci_m_3_MAddr),
.wci_m_3_MData(inf$wci_m_3_MData),
.wci_m_3_MFlag(inf$wci_m_3_MFlag),
.wci_m_4_MCmd(inf$wci_m_4_MCmd),
.wci_m_4_MAddrSpace(inf$wci_m_4_MAddrSpace),
.wci_m_4_MByteEn(inf$wci_m_4_MByteEn),
.wci_m_4_MAddr(inf$wci_m_4_MAddr),
.wci_m_4_MData(inf$wci_m_4_MData),
.wci_m_4_MFlag(inf$wci_m_4_MFlag),
.wci_m_5_MCmd(inf$wci_m_5_MCmd),
.wci_m_5_MAddrSpace(inf$wci_m_5_MAddrSpace),
.wci_m_5_MByteEn(inf$wci_m_5_MByteEn),
.wci_m_5_MAddr(inf$wci_m_5_MAddr),
.wci_m_5_MData(inf$wci_m_5_MData),
.wci_m_5_MFlag(inf$wci_m_5_MFlag),
.wci_m_6_MCmd(inf$wci_m_6_MCmd),
.wci_m_6_MAddrSpace(inf$wci_m_6_MAddrSpace),
.wci_m_6_MByteEn(inf$wci_m_6_MByteEn),
.wci_m_6_MAddr(inf$wci_m_6_MAddr),
.wci_m_6_MData(inf$wci_m_6_MData),
.wci_m_6_MFlag(inf$wci_m_6_MFlag),
.wci_m_7_MCmd(inf$wci_m_7_MCmd),
.wci_m_7_MAddrSpace(inf$wci_m_7_MAddrSpace),
.wci_m_7_MByteEn(inf$wci_m_7_MByteEn),
.wci_m_7_MAddr(inf$wci_m_7_MAddr),
.wci_m_7_MData(inf$wci_m_7_MData),
.wci_m_7_MFlag(inf$wci_m_7_MFlag),
.wci_m_8_MCmd(inf$wci_m_8_MCmd),
.wci_m_8_MAddrSpace(inf$wci_m_8_MAddrSpace),
.wci_m_8_MByteEn(inf$wci_m_8_MByteEn),
.wci_m_8_MAddr(inf$wci_m_8_MAddr),
.wci_m_8_MData(inf$wci_m_8_MData),
.wci_m_8_MFlag(inf$wci_m_8_MFlag),
.wci_m_9_MCmd(inf$wci_m_9_MCmd),
.wci_m_9_MAddrSpace(inf$wci_m_9_MAddrSpace),
.wci_m_9_MByteEn(inf$wci_m_9_MByteEn),
.wci_m_9_MAddr(inf$wci_m_9_MAddr),
.wci_m_9_MData(inf$wci_m_9_MData),
.wci_m_9_MFlag(inf$wci_m_9_MFlag),
.wci_m_10_MCmd(inf$wci_m_10_MCmd),
.wci_m_10_MAddrSpace(inf$wci_m_10_MAddrSpace),
.wci_m_10_MByteEn(inf$wci_m_10_MByteEn),
.wci_m_10_MAddr(inf$wci_m_10_MAddr),
.wci_m_10_MData(inf$wci_m_10_MData),
.wci_m_10_MFlag(inf$wci_m_10_MFlag),
.wci_m_11_MCmd(inf$wci_m_11_MCmd),
.wci_m_11_MAddrSpace(inf$wci_m_11_MAddrSpace),
.wci_m_11_MByteEn(inf$wci_m_11_MByteEn),
.wci_m_11_MAddr(inf$wci_m_11_MAddr),
.wci_m_11_MData(inf$wci_m_11_MData),
.wci_m_11_MFlag(inf$wci_m_11_MFlag),
.wci_m_12_MCmd(inf$wci_m_12_MCmd),
.wci_m_12_MAddrSpace(inf$wci_m_12_MAddrSpace),
.wci_m_12_MByteEn(inf$wci_m_12_MByteEn),
.wci_m_12_MAddr(inf$wci_m_12_MAddr),
.wci_m_12_MData(inf$wci_m_12_MData),
.wci_m_12_MFlag(inf$wci_m_12_MFlag),
.wmiDP0_SResp(inf$wmiDP0_SResp),
.wmiDP0_SData(inf$wmiDP0_SData),
.wmiDP0_SThreadBusy(inf$wmiDP0_SThreadBusy),
.wmiDP0_SDataThreadBusy(inf$wmiDP0_SDataThreadBusy),
.wmiDP0_SRespLast(inf$wmiDP0_SRespLast),
.wmiDP0_SFlag(inf$wmiDP0_SFlag),
.wmiDP0_SReset_n(inf$wmiDP0_SReset_n),
.wmiDP1_SResp(inf$wmiDP1_SResp),
.wmiDP1_SData(inf$wmiDP1_SData),
.wmiDP1_SThreadBusy(inf$wmiDP1_SThreadBusy),
.wmiDP1_SDataThreadBusy(inf$wmiDP1_SDataThreadBusy),
.wmiDP1_SRespLast(inf$wmiDP1_SRespLast),
.wmiDP1_SFlag(inf$wmiDP1_SFlag),
.wmiDP1_SReset_n(inf$wmiDP1_SReset_n),
.cpNow(inf$cpNow),
.RDY_cpNow(),
.gps_ppsSyncOut(inf$gps_ppsSyncOut),
.RDY_uuid(),
.RST_N_wci_m_0(inf$RST_N_wci_m_0),
.RST_N_wci_m_1(inf$RST_N_wci_m_1),
.RST_N_wci_m_2(inf$RST_N_wci_m_2),
.RST_N_wci_m_3(inf$RST_N_wci_m_3),
.RST_N_wci_m_4(inf$RST_N_wci_m_4),
.RST_N_wci_m_5(inf$RST_N_wci_m_5),
.RST_N_wci_m_6(inf$RST_N_wci_m_6),
.RST_N_wci_m_7(inf$RST_N_wci_m_7),
.RST_N_wci_m_8(inf$RST_N_wci_m_8),
.RST_N_wci_m_9(inf$RST_N_wci_m_9),
.RST_N_wci_m_10(inf$RST_N_wci_m_10),
.RST_N_wci_m_11(inf$RST_N_wci_m_11),
.RST_N_wci_m_12(inf$RST_N_wci_m_12));
// inlined wires
assign wtiM_0_peerIsReady_1$wget = 1'd1 ;
assign wtiM_0_peerIsReady_1$whas = app$wti_s_0_SReset_n ;
assign wtiM_1_peerIsReady_1$wget = 1'd1 ;
assign wtiM_1_peerIsReady_1$whas = app$wti_s_1_SReset_n ;
assign wtiM_2_peerIsReady_1$wget = 1'd1 ;
assign wtiM_2_peerIsReady_1$whas = app$wti_s_2_SReset_n ;
assign wtiM_0_sThreadBusy_pw$whas = app$wti_s_0_SThreadBusy ;
assign wtiM_1_sThreadBusy_pw$whas = app$wti_s_1_SThreadBusy ;
assign wtiM_2_sThreadBusy_pw$whas = app$wti_s_2_SThreadBusy ;
// register wtiM_0_nowReq
assign wtiM_0_nowReq$D_IN = { 3'd1, ctNow$dD_OUT } ;
assign wtiM_0_nowReq$EN = 1'd1 ;
// register wtiM_0_peerIsReady
assign wtiM_0_peerIsReady$D_IN = app$wti_s_0_SReset_n ;
assign wtiM_0_peerIsReady$EN = 1'd1 ;
// register wtiM_0_sThreadBusy_d
assign wtiM_0_sThreadBusy_d$D_IN = app$wti_s_0_SThreadBusy ;
assign wtiM_0_sThreadBusy_d$EN = 1'd1 ;
// register wtiM_1_nowReq
assign wtiM_1_nowReq$D_IN = wtiM_0_nowReq$D_IN ;
assign wtiM_1_nowReq$EN = 1'd1 ;
// register wtiM_1_peerIsReady
assign wtiM_1_peerIsReady$D_IN = app$wti_s_1_SReset_n ;
assign wtiM_1_peerIsReady$EN = 1'd1 ;
// register wtiM_1_sThreadBusy_d
assign wtiM_1_sThreadBusy_d$D_IN = app$wti_s_1_SThreadBusy ;
assign wtiM_1_sThreadBusy_d$EN = 1'd1 ;
// register wtiM_2_nowReq
assign wtiM_2_nowReq$D_IN = wtiM_0_nowReq$D_IN ;
assign wtiM_2_nowReq$EN = 1'd1 ;
// register wtiM_2_peerIsReady
assign wtiM_2_peerIsReady$D_IN = app$wti_s_2_SReset_n ;
assign wtiM_2_peerIsReady$EN = 1'd1 ;
// register wtiM_2_sThreadBusy_d
assign wtiM_2_sThreadBusy_d$D_IN = app$wti_s_2_SThreadBusy ;
assign wtiM_2_sThreadBusy_d$EN = 1'd1 ;
// submodule app
assign app$wci_s_0_MAddr = inf$wci_m_0_MAddr ;
assign app$wci_s_0_MAddrSpace = inf$wci_m_0_MAddrSpace ;
assign app$wci_s_0_MByteEn = inf$wci_m_0_MByteEn ;
assign app$wci_s_0_MCmd = inf$wci_m_0_MCmd ;
assign app$wci_s_0_MData = inf$wci_m_0_MData ;
assign app$wci_s_0_MFlag = inf$wci_m_0_MFlag ;
assign app$wci_s_1_MAddr = inf$wci_m_1_MAddr ;
assign app$wci_s_1_MAddrSpace = inf$wci_m_1_MAddrSpace ;
assign app$wci_s_1_MByteEn = inf$wci_m_1_MByteEn ;
assign app$wci_s_1_MCmd = inf$wci_m_1_MCmd ;
assign app$wci_s_1_MData = inf$wci_m_1_MData ;
assign app$wci_s_1_MFlag = inf$wci_m_1_MFlag ;
assign app$wci_s_2_MAddr = inf$wci_m_2_MAddr ;
assign app$wci_s_2_MAddrSpace = inf$wci_m_2_MAddrSpace ;
assign app$wci_s_2_MByteEn = inf$wci_m_2_MByteEn ;
assign app$wci_s_2_MCmd = inf$wci_m_2_MCmd ;
assign app$wci_s_2_MData = inf$wci_m_2_MData ;
assign app$wci_s_2_MFlag = inf$wci_m_2_MFlag ;
assign app$wci_s_3_MAddr = inf$wci_m_3_MAddr ;
assign app$wci_s_3_MAddrSpace = inf$wci_m_3_MAddrSpace ;
assign app$wci_s_3_MByteEn = inf$wci_m_3_MByteEn ;
assign app$wci_s_3_MCmd = inf$wci_m_3_MCmd ;
assign app$wci_s_3_MData = inf$wci_m_3_MData ;
assign app$wci_s_3_MFlag = inf$wci_m_3_MFlag ;
assign app$wci_s_4_MAddr = inf$wci_m_4_MAddr ;
assign app$wci_s_4_MAddrSpace = inf$wci_m_4_MAddrSpace ;
assign app$wci_s_4_MByteEn = inf$wci_m_4_MByteEn ;
assign app$wci_s_4_MCmd = inf$wci_m_4_MCmd ;
assign app$wci_s_4_MData = inf$wci_m_4_MData ;
assign app$wci_s_4_MFlag = inf$wci_m_4_MFlag ;
assign app$wci_s_5_MAddr = inf$wci_m_5_MAddr ;
assign app$wci_s_5_MAddrSpace = inf$wci_m_5_MAddrSpace ;
assign app$wci_s_5_MByteEn = inf$wci_m_5_MByteEn ;
assign app$wci_s_5_MCmd = inf$wci_m_5_MCmd ;
assign app$wci_s_5_MData = inf$wci_m_5_MData ;
assign app$wci_s_5_MFlag = inf$wci_m_5_MFlag ;
assign app$wci_s_6_MAddr = inf$wci_m_6_MAddr ;
assign app$wci_s_6_MAddrSpace = inf$wci_m_6_MAddrSpace ;
assign app$wci_s_6_MByteEn = inf$wci_m_6_MByteEn ;
assign app$wci_s_6_MCmd = inf$wci_m_6_MCmd ;
assign app$wci_s_6_MData = inf$wci_m_6_MData ;
assign app$wci_s_6_MFlag = inf$wci_m_6_MFlag ;
assign app$wci_s_7_MAddr = inf$wci_m_7_MAddr ;
assign app$wci_s_7_MAddrSpace = inf$wci_m_7_MAddrSpace ;
assign app$wci_s_7_MByteEn = inf$wci_m_7_MByteEn ;
assign app$wci_s_7_MCmd = inf$wci_m_7_MCmd ;
assign app$wci_s_7_MData = inf$wci_m_7_MData ;
assign app$wci_s_7_MFlag = inf$wci_m_7_MFlag ;
assign app$wmemiM0_SData = wmemiM0_SData ;
assign app$wmemiM0_SResp = wmemiM0_SResp ;
assign app$wmiM0_SData = inf$wmiDP0_SData ;
assign app$wmiM0_SFlag = inf$wmiDP0_SFlag ;
assign app$wmiM0_SResp = inf$wmiDP0_SResp ;
assign app$wmiM1_SData = inf$wmiDP1_SData ;
assign app$wmiM1_SFlag = inf$wmiDP1_SFlag ;
assign app$wmiM1_SResp = inf$wmiDP1_SResp ;
assign app$wsi_s_adc_MBurstLength = 12'h0 ;
assign app$wsi_s_adc_MByteEn = 4'h0 ;
assign app$wsi_s_adc_MCmd = 3'h0 ;
assign app$wsi_s_adc_MData = 32'h0 ;
assign app$wsi_s_adc_MReqInfo = 8'h0 ;
assign app$wti_s_0_MCmd =
wtiM_0_sThreadBusy_d ? 3'd0 : wtiM_0_nowReq[66:64] ;
assign app$wti_s_0_MData = wtiM_0_nowReq[63:0] ;
assign app$wti_s_1_MCmd =
wtiM_1_sThreadBusy_d ? 3'd0 : wtiM_1_nowReq[66:64] ;
assign app$wti_s_1_MData = wtiM_1_nowReq[63:0] ;
assign app$wti_s_2_MCmd =
wtiM_2_sThreadBusy_d ? 3'd0 : wtiM_2_nowReq[66:64] ;
assign app$wti_s_2_MData = wtiM_2_nowReq[63:0] ;
assign app$wmiM0_SThreadBusy = inf$wmiDP0_SThreadBusy ;
assign app$wmiM0_SDataThreadBusy = inf$wmiDP0_SDataThreadBusy ;
assign app$wmiM0_SRespLast = inf$wmiDP0_SRespLast ;
assign app$wmiM0_SReset_n = inf$wmiDP0_SReset_n ;
assign app$wmiM1_SThreadBusy = inf$wmiDP1_SThreadBusy ;
assign app$wmiM1_SDataThreadBusy = inf$wmiDP1_SDataThreadBusy ;
assign app$wmiM1_SRespLast = inf$wmiDP1_SRespLast ;
assign app$wmiM1_SReset_n = inf$wmiDP1_SReset_n ;
assign app$wmemiM0_SRespLast = wmemiM0_SRespLast ;
assign app$wmemiM0_SCmdAccept = wmemiM0_SCmdAccept ;
assign app$wmemiM0_SDataAccept = wmemiM0_SDataAccept ;
assign app$wsi_s_adc_MReqLast = 1'b0 ;
assign app$wsi_s_adc_MBurstPrecise = 1'b0 ;
assign app$wsi_s_adc_MReset_n = 1'b0 ;
assign app$wsi_m_dac_SThreadBusy = 1'b0 ;
assign app$wsi_m_dac_SReset_n = 1'b0 ;
// submodule ctNow
assign ctNow$sD_IN = inf$cpNow ;
assign ctNow$sEN = ctNow$sRDY ;
// submodule inf
assign inf$cpServer_request_put = cpServer_request_put ;
assign inf$gps_ppsSyncIn_x = gps_ppsSyncIn_x ;
assign inf$server_request_put = server_request_put ;
assign inf$switch_x = switch_x ;
assign inf$uuid_arg = app$uuid ;
assign inf$wci_m_0_SData = app$wci_s_0_SData ;
assign inf$wci_m_0_SFlag = app$wci_s_0_SFlag ;
assign inf$wci_m_0_SResp = app$wci_s_0_SResp ;
assign inf$wci_m_10_SData = wci_m_2_SData ;
assign inf$wci_m_10_SFlag = wci_m_2_SFlag ;
assign inf$wci_m_10_SResp = wci_m_2_SResp ;
assign inf$wci_m_11_SData = wci_m_3_SData ;
assign inf$wci_m_11_SFlag = wci_m_3_SFlag ;
assign inf$wci_m_11_SResp = wci_m_3_SResp ;
assign inf$wci_m_12_SData = wci_m_4_SData ;
assign inf$wci_m_12_SFlag = wci_m_4_SFlag ;
assign inf$wci_m_12_SResp = wci_m_4_SResp ;
assign inf$wci_m_1_SData = app$wci_s_1_SData ;
assign inf$wci_m_1_SFlag = app$wci_s_1_SFlag ;
assign inf$wci_m_1_SResp = app$wci_s_1_SResp ;
assign inf$wci_m_2_SData = app$wci_s_2_SData ;
assign inf$wci_m_2_SFlag = app$wci_s_2_SFlag ;
assign inf$wci_m_2_SResp = app$wci_s_2_SResp ;
assign inf$wci_m_3_SData = app$wci_s_3_SData ;
assign inf$wci_m_3_SFlag = app$wci_s_3_SFlag ;
assign inf$wci_m_3_SResp = app$wci_s_3_SResp ;
assign inf$wci_m_4_SData = app$wci_s_4_SData ;
assign inf$wci_m_4_SFlag = app$wci_s_4_SFlag ;
assign inf$wci_m_4_SResp = app$wci_s_4_SResp ;
assign inf$wci_m_5_SData = app$wci_s_5_SData ;
assign inf$wci_m_5_SFlag = app$wci_s_5_SFlag ;
assign inf$wci_m_5_SResp = app$wci_s_5_SResp ;
assign inf$wci_m_6_SData = app$wci_s_6_SData ;
assign inf$wci_m_6_SFlag = app$wci_s_6_SFlag ;
assign inf$wci_m_6_SResp = app$wci_s_6_SResp ;
assign inf$wci_m_7_SData = app$wci_s_7_SData ;
assign inf$wci_m_7_SFlag = app$wci_s_7_SFlag ;
assign inf$wci_m_7_SResp = app$wci_s_7_SResp ;
assign inf$wci_m_8_SData = wci_m_0_SData ;
assign inf$wci_m_8_SFlag = wci_m_0_SFlag ;
assign inf$wci_m_8_SResp = wci_m_0_SResp ;
assign inf$wci_m_9_SData = wci_m_1_SData ;
assign inf$wci_m_9_SFlag = wci_m_1_SFlag ;
assign inf$wci_m_9_SResp = wci_m_1_SResp ;
assign inf$wmiDP0_MAddr = app$wmiM0_MAddr ;
assign inf$wmiDP0_MAddrSpace = app$wmiM0_MAddrSpace ;
assign inf$wmiDP0_MBurstLength = app$wmiM0_MBurstLength ;
assign inf$wmiDP0_MCmd = app$wmiM0_MCmd ;
assign inf$wmiDP0_MData = app$wmiM0_MData ;
assign inf$wmiDP0_MDataByteEn = app$wmiM0_MDataByteEn ;
assign inf$wmiDP0_MReqInfo = app$wmiM0_MReqInfo ;
assign inf$wmiDP0_arg_mFlag = app$wmiM0_MFlag ;
assign inf$wmiDP1_MAddr = app$wmiM1_MAddr ;
assign inf$wmiDP1_MAddrSpace = app$wmiM1_MAddrSpace ;
assign inf$wmiDP1_MBurstLength = app$wmiM1_MBurstLength ;
assign inf$wmiDP1_MCmd = app$wmiM1_MCmd ;
assign inf$wmiDP1_MData = app$wmiM1_MData ;
assign inf$wmiDP1_MDataByteEn = app$wmiM1_MDataByteEn ;
assign inf$wmiDP1_MReqInfo = app$wmiM1_MReqInfo ;
assign inf$wmiDP1_arg_mFlag = app$wmiM1_MFlag ;
assign inf$EN_server_request_put = EN_server_request_put ;
assign inf$EN_server_response_get = EN_server_response_get ;
assign inf$EN_cpServer_request_put = EN_cpServer_request_put ;
assign inf$EN_cpServer_response_get = EN_cpServer_response_get ;
assign inf$wci_m_0_SThreadBusy = app$wci_s_0_SThreadBusy ;
assign inf$wci_m_1_SThreadBusy = app$wci_s_1_SThreadBusy ;
assign inf$wci_m_2_SThreadBusy = app$wci_s_2_SThreadBusy ;
assign inf$wci_m_3_SThreadBusy = app$wci_s_3_SThreadBusy ;
assign inf$wci_m_4_SThreadBusy = app$wci_s_4_SThreadBusy ;
assign inf$wci_m_5_SThreadBusy = app$wci_s_5_SThreadBusy ;
assign inf$wci_m_6_SThreadBusy = app$wci_s_6_SThreadBusy ;
assign inf$wci_m_7_SThreadBusy = app$wci_s_7_SThreadBusy ;
assign inf$wci_m_8_SThreadBusy = wci_m_0_SThreadBusy ;
assign inf$wci_m_9_SThreadBusy = wci_m_1_SThreadBusy ;
assign inf$wci_m_10_SThreadBusy = wci_m_2_SThreadBusy ;
assign inf$wci_m_11_SThreadBusy = wci_m_3_SThreadBusy ;
assign inf$wci_m_12_SThreadBusy = wci_m_4_SThreadBusy ;
assign inf$wmiDP0_MReqLast = app$wmiM0_MReqLast ;
assign inf$wmiDP0_MDataValid = app$wmiM0_MDataValid ;
assign inf$wmiDP0_MDataLast = app$wmiM0_MDataLast ;
assign inf$wmiDP0_MReset_n = app$wmiM0_MReset_n ;
assign inf$wmiDP1_MReqLast = app$wmiM1_MReqLast ;
assign inf$wmiDP1_MDataValid = app$wmiM1_MDataValid ;
assign inf$wmiDP1_MDataLast = app$wmiM1_MDataLast ;
assign inf$wmiDP1_MReset_n = app$wmiM1_MReset_n ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
wtiM_0_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wtiM_0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wtiM_0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wtiM_1_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wtiM_1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wtiM_1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wtiM_2_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wtiM_2_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wtiM_2_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wtiM_0_nowReq$EN)
wtiM_0_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_0_nowReq$D_IN;
if (wtiM_0_peerIsReady$EN)
wtiM_0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_0_peerIsReady$D_IN;
if (wtiM_0_sThreadBusy_d$EN)
wtiM_0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wtiM_0_sThreadBusy_d$D_IN;
if (wtiM_1_nowReq$EN)
wtiM_1_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_1_nowReq$D_IN;
if (wtiM_1_peerIsReady$EN)
wtiM_1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_1_peerIsReady$D_IN;
if (wtiM_1_sThreadBusy_d$EN)
wtiM_1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wtiM_1_sThreadBusy_d$D_IN;
if (wtiM_2_nowReq$EN)
wtiM_2_nowReq <= `BSV_ASSIGNMENT_DELAY wtiM_2_nowReq$D_IN;
if (wtiM_2_peerIsReady$EN)
wtiM_2_peerIsReady <= `BSV_ASSIGNMENT_DELAY wtiM_2_peerIsReady$D_IN;
if (wtiM_2_sThreadBusy_d$EN)
wtiM_2_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wtiM_2_sThreadBusy_d$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
wtiM_0_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wtiM_0_peerIsReady = 1'h0;
wtiM_0_sThreadBusy_d = 1'h0;
wtiM_1_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wtiM_1_peerIsReady = 1'h0;
wtiM_1_sThreadBusy_d = 1'h0;
wtiM_2_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wtiM_2_peerIsReady = 1'h0;
wtiM_2_sThreadBusy_d = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCTop4B
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_BEHAVIORAL_V
`define SKY130_FD_SC_LS__AND2B_BEHAVIORAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_BEHAVIORAL_V
|
(** * Rel: Properties of Relations *)
(** This short (and optional) chapter develops some basic definitions
and a few theorems about binary relations in Coq. The key
definitions are repeated where they are actually used (in the
[Smallstep] chapter), so readers who are already comfortable with
these ideas can safely skim or skip this chapter. However,
relations are also a good source of exercises for developing
facility with Coq's basic reasoning facilities, so it may be
useful to look at this material just after the [IndProp]
chapter. *)
Require Export IndProp.
(** A binary _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X -> X -> Prop.
(** Confusingly, the Coq standard library hijacks the generic term
"relation" for this specific instance of the idea. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, whereas the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-than-or-equal-to
relation, which we usually write [n1 <= n2]. *)
Print le.
(* ====> Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m *)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(** (Why did we write it this way instead of starting with [Inductive
le : relation nat...]? Because we wanted to put the first [nat]
to the left of the [:], which makes Coq generate a somewhat nicer
induction principle for reasoning about [<=].) *)
(* ################################################################# *)
(** * Basic Properties *)
(** As anyone knows who has taken an undergraduate discrete math
course, there is a lot to be said about relations in general,
including ways of classifying relations (as reflexive, transitive,
etc.), theorems that can be proved generically about certain sorts
of relations, constructions that build one relation from another,
etc. For example... *)
(* ----------------------------------------------------------------- *)
(** *** Partial Functions *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., [R x y1]
and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined earlier is a partial
function. *)
Print next_nat.
(* ====> Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n) *)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed.
(** However, the [<=] relation on numbers is not a partial
function. (Assume, for a contradiction, that [<=] is a partial
function. But then, since [0 <= 0] and [0 <= 1], it follows that
[0 = 1]. This is nonsense, so our assumption was
contradictory.) *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense. {
apply Hc with (x := 0).
- apply le_n.
- apply le_S. apply le_n. }
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in earlier is not a partial
function. *)
Theorem total_not_partial_function :
~ (partial_function total_relation).
Proof.
unfold not. unfold partial_function. intros.
assert (0 = 1). {
apply H with (x:=0).
- apply total.
- apply total. }
inversion H0.
Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] that we defined earlier is a
partial function. *)
Theorem empty_relation_partial_function :
partial_function empty_relation.
Proof.
unfold partial_function. intros. inversion H.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Reflexive Relations *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(* ----------------------------------------------------------------- *)
(** *** Transitive Relations *)
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
- (* le_n *) apply Hnm.
- (* le_S *) apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using [le_trans]. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
- apply le_S. apply Hnm.
- apply le_S. apply IHHm'o.
Qed.
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
- inversion Hmo.
- apply le_S. apply IHo'. admit.
Qed.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
- apply le_S. apply le_n.
- apply H.
Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~ (S n <= n)]
A formal proof of this is an optional exercise below, but try
writing an informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, let's look at a few other common ones... *)
(* ----------------------------------------------------------------- *)
(** *** Symmetric and Antisymmetric Relations *)
(** A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
unfold not. unfold symmetric. intros.
assert (1 <= 0). {
apply H. apply le_S. apply le_n.
} inversion H0.
Qed.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
unfold antisymmetric. intros. inversion H0.
+ reflexivity.
+ symmetry in H2. rewrite H2 in H. remember le_trans as T. unfold transitive in T.
apply T with (a:=S m) in H1. apply le_Sn_n in H1. inversion H1. apply H.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Equivalence Relations *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
Definition eq_nat := fun (a:nat) (b:nat) => a = b.
Theorem eq_nat_equivalence :
equivalence eq_nat.
Proof.
unfold equivalence. split.
- unfold reflexive. intros. unfold eq_nat. reflexivity.
- split.
+ unfold symmetric. unfold eq_nat. intros. symmetry. apply H.
+ unfold transitive. unfold eq_nat. intros. rewrite H0 in H. apply H.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Partial Orders and Preorders *)
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
- (* refl *) apply le_reflexive.
- split.
+ (* antisym *) apply le_antisymmetric.
+ (* transitive. *) apply le_trans. Qed.
(* ################################################################# *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
- (* -> *)
intro H. induction H.
+ (* le_n *) apply rt_refl.
+ (* le_S *)
apply rt_trans with m. apply IHle. apply rt_step.
apply nn.
- (* <- *)
intro H. induction H.
+ (* rt_step *) inversion H. apply le_S. apply le_n.
+ (* rt_refl *) apply le_n.
+ (* rt_trans *)
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is natural:
it says, explicitly, that the reflexive and transitive closure of
[R] is the least relation that includes [R] and that is closed
under rules of reflexivity and transitivity. But it turns out
that this definition is not very convenient for doing proofs,
since the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions. Here is a more useful definition: *)
Inductive clos_refl_trans_1n {A : Type}
(R : relation A) (x : A)
: A -> Prop :=
| rt1n_refl : clos_refl_trans_1n R x x
| rt1n_trans (y z : A) :
R x y -> clos_refl_trans_1n R y z ->
clos_refl_trans_1n R x z.
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [clos_refl_trans_1n] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Lemma rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> clos_refl_trans_1n R x y.
Proof.
intros X R x y H.
apply rt1n_trans with y. apply H. apply rt1n_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Lemma rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
clos_refl_trans_1n R x y ->
clos_refl_trans_1n R y z ->
clos_refl_trans_1n R x z.
Proof.
intros. induction H.
- apply H0.
- admit.
Qed.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> clos_refl_trans_1n R x y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
//////////////////////////////////////////////////////////////////////
//// ////
//// RMON_CTRL.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2006/01/19 14:07:55 maverickist
// verification is complete.
//
// Revision 1.2 2005/12/16 06:44:19 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module RMON_CTRL (
Clk ,
Reset ,
//RMON_CTRL
Reg_apply_0 ,
Reg_addr_0 ,
Reg_data_0 ,
Reg_next_0 ,
Reg_apply_1 ,
Reg_addr_1 ,
Reg_data_1 ,
Reg_next_1 ,
//dual-port ram
Addra ,
Dina ,
Douta ,
Wea ,
//CPU
CPU_rd_addr ,
CPU_rd_apply ,
CPU_rd_grant ,
CPU_rd_dout
);
input Clk ;
input Reset ;
//RMON_CTRL
input Reg_apply_0 ;
input [4:0] Reg_addr_0 ;
input [15:0] Reg_data_0 ;
output Reg_next_0 ;
input Reg_apply_1 ;
input [4:0] Reg_addr_1 ;
input [15:0] Reg_data_1 ;
output Reg_next_1 ;
//dual-port ram
//port-a for Rmon
output [5:0] Addra ;
output [31:0] Dina ;
input [31:0] Douta ;
output Wea ;
//CPU
input [5:0] CPU_rd_addr ;
input CPU_rd_apply ;
output CPU_rd_grant ;
output [31:0] CPU_rd_dout ;
//******************************************************************************
//internal signals
//******************************************************************************
parameter StateCPU =4'd00;
parameter StateMAC0 =4'd01;
parameter StateMAC1 =4'd02;
reg [3:0] CurrentState /* synthesys syn_keep=1 */;
reg [3:0] NextState;
reg [3:0] CurrentState_reg;
reg [4:0] StepCounter;
reg [31:0] DoutaReg;
reg [5:0] Addra ;
reg [31:0] Dina;
reg Reg_next_0 ;
reg Reg_next_1 ;
reg Write;
reg Read;
reg Pipeline;
reg [31:0] CPU_rd_dout ;
reg CPU_rd_apply_reg ;
//******************************************************************************
//State Machine
//******************************************************************************
always @(posedge Clk or posedge Reset)
if (Reset)
CurrentState <=StateMAC0;
else
CurrentState <=NextState;
always @(posedge Clk or posedge Reset)
if (Reset)
CurrentState_reg <=StateMAC0;
else if(CurrentState!=StateCPU)
CurrentState_reg <=CurrentState;
always @(CurrentState or CPU_rd_apply_reg or Reg_apply_0 or CurrentState_reg
or Reg_apply_1
or StepCounter
)
case(CurrentState)
StateMAC0:
if(!Reg_apply_0&&CPU_rd_apply_reg)
NextState =StateCPU;
else if(!Reg_apply_0)
NextState =StateMAC1;
else
NextState =CurrentState;
StateMAC1:
if(!Reg_apply_1&&CPU_rd_apply_reg)
NextState =StateCPU;
else if(!Reg_apply_1)
NextState =StateMAC0;
else
NextState =CurrentState;
StateCPU:
if (StepCounter==3)
case (CurrentState_reg)
StateMAC0 :NextState =StateMAC0 ;
StateMAC1 :NextState =StateMAC1 ;
default :NextState =StateMAC0;
endcase
else
NextState =CurrentState;
default:
NextState =StateMAC0;
endcase
always @(posedge Clk or posedge Reset)
if (Reset)
StepCounter <=0;
else if(NextState!=CurrentState)
StepCounter <=0;
else if (StepCounter!=4'hf)
StepCounter <=StepCounter + 1;
//******************************************************************************
//temp signals
//******************************************************************************
always @(StepCounter)
if( StepCounter==1||StepCounter==4||
StepCounter==7||StepCounter==10)
Read =1;
else
Read =0;
always @(StepCounter or CurrentState)
if( StepCounter==2||StepCounter==5||
StepCounter==8||StepCounter==11)
Pipeline =1;
else
Pipeline =0;
always @(StepCounter or CurrentState)
if( StepCounter==3||StepCounter==6||
StepCounter==9||StepCounter==12)
Write =1;
else
Write =0;
always @(posedge Clk or posedge Reset)
if (Reset)
DoutaReg <=0;
else if (Read)
DoutaReg <=Douta;
//******************************************************************************
//gen output signals
//******************************************************************************
//Addra
always @(*)
case(CurrentState)
StateMAC0 : Addra={1'd0 ,Reg_addr_0 };
StateMAC1 : Addra={1'd1 ,Reg_addr_1 };
StateCPU: Addra=CPU_rd_addr;
default: Addra=0;
endcase
//Dina
always @(posedge Clk or posedge Reset)
if (Reset)
Dina <=0;
else
case(CurrentState)
StateMAC0 : Dina<=Douta+Reg_data_0 ;
StateMAC1 : Dina<=Douta+Reg_data_1 ;
StateCPU: Dina<=0;
default: Dina<=0;
endcase
assign Wea =Write;
//Reg_next
always @(CurrentState or Pipeline)
if(CurrentState==StateMAC0)
Reg_next_0 =Pipeline;
else
Reg_next_0 =0;
always @(CurrentState or Pipeline)
if(CurrentState==StateMAC1)
Reg_next_1 =Pipeline;
else
Reg_next_1 =0;
//CPU_rd_grant
reg CPU_rd_apply_dl1;
reg CPU_rd_apply_dl2;
//rising edge
always @ (posedge Clk or posedge Reset)
if (Reset)
begin
CPU_rd_apply_dl1 <=0;
CPU_rd_apply_dl2 <=0;
end
else
begin
CPU_rd_apply_dl1 <=CPU_rd_apply;
CPU_rd_apply_dl2 <=CPU_rd_apply_dl1;
end
always @ (posedge Clk or posedge Reset)
if (Reset)
CPU_rd_apply_reg <=0;
else if (CPU_rd_apply_dl1&!CPU_rd_apply_dl2)
CPU_rd_apply_reg <=1;
else if (CurrentState==StateCPU&&Write)
CPU_rd_apply_reg <=0;
assign CPU_rd_grant =!CPU_rd_apply_reg;
always @ (posedge Clk or posedge Reset)
if (Reset)
CPU_rd_dout <=0;
else if (Pipeline&&CurrentState==StateCPU)
CPU_rd_dout <=Douta;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NOR4B_PP_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_PP_SYMBOL_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: player1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module player1 (
address,
clock,
q);
input [10:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "player1.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1190"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "player1.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1190"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
module ScanCodeModule(Clk,Reset, ClkKB, DataKB,NewScanCode, ScanCode);
input Clk,Reset,ClkKB, DataKB;
wire NewDataKB;
output NewScanCode;
output [7:0] ScanCode;
wire Load, New,Borrar,EndTras,ParityCoherente;
reg ClkKB_syn, DataKB_syn ;
always @(negedge Clk) begin
ClkKB_syn <= ClkKB;
DataKB_syn <= DataKB;
end
//module module Muestrear(ClkKB, NewDataKB, Clk , Reset);
Muestrear Muestrear (.Clk(Clk), .Reset(Reset),.ClkKB(ClkKB_syn), .NewDataKB(NewDataKB) );
//module ScanCodeControl(NewDataKB,Load, New , Borrar, EndTras, ParityCoherente, Clk , Reset);
ScanCodeControl Control (.Clk(Clk), .Reset(Reset),.NewDataKB(NewDataKB), .Load(Load) , .New(New), .Borrar(Borrar), .EndTras(EndTras), .ParityCoherente(ParityCoherente));
//module ModuloDato(Clk, Reset, DataKB,Load, New,Borrar,EndTras,ParityCoherente ,NewScanCode, ScanCode)
ModuloDato Dato (.Clk(Clk), .Reset(Reset), .DataKB(DataKB_syn), .NewScanCode(NewScanCode), .ScanCode(ScanCode), .Load(Load), .Borrar(Borrar), .EndTras(EndTras), .ParityCoherente(ParityCoherente),.New(New));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_BEHAVIORAL_PP_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__muxb16to1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input [15:0] D ;
input [15:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_d0 ;
wire pwrgood_pp1_out_s0 ;
wire pwrgood_pp2_out_d1 ;
wire pwrgood_pp3_out_s1 ;
wire pwrgood_pp4_out_d2 ;
wire pwrgood_pp5_out_s2 ;
wire pwrgood_pp6_out_d3 ;
wire pwrgood_pp7_out_s3 ;
wire pwrgood_pp8_out_d4 ;
wire pwrgood_pp9_out_s4 ;
wire pwrgood_pp10_out_d5 ;
wire pwrgood_pp11_out_s5 ;
wire pwrgood_pp12_out_d6 ;
wire pwrgood_pp13_out_s6 ;
wire pwrgood_pp14_out_d7 ;
wire pwrgood_pp15_out_s7 ;
wire pwrgood_pp16_out_d8 ;
wire pwrgood_pp17_out_s8 ;
wire pwrgood_pp18_out_d9 ;
wire pwrgood_pp19_out_s9 ;
wire pwrgood_pp20_out_d10;
wire pwrgood_pp21_out_s10;
wire pwrgood_pp22_out_d11;
wire pwrgood_pp23_out_s11;
wire pwrgood_pp24_out_d12;
wire pwrgood_pp25_out_s12;
wire pwrgood_pp26_out_d13;
wire pwrgood_pp27_out_s13;
wire pwrgood_pp28_out_d14;
wire pwrgood_pp29_out_s14;
wire pwrgood_pp30_out_d15;
wire pwrgood_pp31_out_s15;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_d0 , D[0], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_s0 , S[0], VPWR, VGND );
bufif1 bufif10 (Z , !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (pwrgood_pp2_out_d1 , D[1], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (pwrgood_pp3_out_s1 , S[1], VPWR, VGND );
bufif1 bufif11 (Z , !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (pwrgood_pp4_out_d2 , D[2], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (pwrgood_pp5_out_s2 , S[2], VPWR, VGND );
bufif1 bufif12 (Z , !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (pwrgood_pp6_out_d3 , D[3], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (pwrgood_pp7_out_s3 , S[3], VPWR, VGND );
bufif1 bufif13 (Z , !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp8 (pwrgood_pp8_out_d4 , D[4], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp9 (pwrgood_pp9_out_s4 , S[4], VPWR, VGND );
bufif1 bufif14 (Z , !pwrgood_pp8_out_d4, pwrgood_pp9_out_s4 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp10 (pwrgood_pp10_out_d5 , D[5], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp11 (pwrgood_pp11_out_s5 , S[5], VPWR, VGND );
bufif1 bufif15 (Z , !pwrgood_pp10_out_d5, pwrgood_pp11_out_s5 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp12 (pwrgood_pp12_out_d6 , D[6], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp13 (pwrgood_pp13_out_s6 , S[6], VPWR, VGND );
bufif1 bufif16 (Z , !pwrgood_pp12_out_d6, pwrgood_pp13_out_s6 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp14 (pwrgood_pp14_out_d7 , D[7], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp15 (pwrgood_pp15_out_s7 , S[7], VPWR, VGND );
bufif1 bufif17 (Z , !pwrgood_pp14_out_d7, pwrgood_pp15_out_s7 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp16 (pwrgood_pp16_out_d8 , D[8], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp17 (pwrgood_pp17_out_s8 , S[8], VPWR, VGND );
bufif1 bufif18 (Z , !pwrgood_pp16_out_d8, pwrgood_pp17_out_s8 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp18 (pwrgood_pp18_out_d9 , D[9], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp19 (pwrgood_pp19_out_s9 , S[9], VPWR, VGND );
bufif1 bufif19 (Z , !pwrgood_pp18_out_d9, pwrgood_pp19_out_s9 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp20 (pwrgood_pp20_out_d10, D[10], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp21 (pwrgood_pp21_out_s10, S[10], VPWR, VGND );
bufif1 bufif110 (Z , !pwrgood_pp20_out_d10, pwrgood_pp21_out_s10);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp22 (pwrgood_pp22_out_d11, D[11], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp23 (pwrgood_pp23_out_s11, S[11], VPWR, VGND );
bufif1 bufif111 (Z , !pwrgood_pp22_out_d11, pwrgood_pp23_out_s11);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp24 (pwrgood_pp24_out_d12, D[12], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp25 (pwrgood_pp25_out_s12, S[12], VPWR, VGND );
bufif1 bufif112 (Z , !pwrgood_pp24_out_d12, pwrgood_pp25_out_s12);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp26 (pwrgood_pp26_out_d13, D[13], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp27 (pwrgood_pp27_out_s13, S[13], VPWR, VGND );
bufif1 bufif113 (Z , !pwrgood_pp26_out_d13, pwrgood_pp27_out_s13);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp28 (pwrgood_pp28_out_d14, D[14], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp29 (pwrgood_pp29_out_s14, S[14], VPWR, VGND );
bufif1 bufif114 (Z , !pwrgood_pp28_out_d14, pwrgood_pp29_out_s14);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp30 (pwrgood_pp30_out_d15, D[15], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp31 (pwrgood_pp31_out_s15, S[15], VPWR, VGND );
bufif1 bufif115 (Z , !pwrgood_pp30_out_d15, pwrgood_pp31_out_s15);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_BEHAVIORAL_PP_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*
*
* @reminder December 1, 2007
* Remember to remove wrbyteen and ctrl_ppp from the inputs to
* the ALU and its testbench
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "/auto/home-scf-07/zhiyango/ee577b/projs/processor/syn/src/control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
// ======================================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:15]=reg_A[0:7]*reg_B[0:7];
result[16:31]=reg_A[16:23]*reg_B[16:23];
result[32:47]=reg_A[32:39]*reg_B[32:39];
result[48:63]=reg_A[48:55]*reg_B[48:55];
result[64:79]=reg_A[64:71]*reg_B[64:71];
result[80:95]=reg_A[80:87]*reg_B[80:87];
result[96:111]=reg_A[96:103]*reg_B[96:103];
result[112:127]=reg_A[112:119]*reg_B[112:119];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:31]=reg_A[0:15]*reg_B[0:15];
result[32:63]=reg_A[32:47]*reg_B[32:47];
result[64:95]=reg_A[64:79]*reg_B[64:79];
result[96:127]=reg_A[96:111]*reg_B[96:111];
end
default: // aluwsrl AND `aa AND Default
begin
result=128'd0;
end
endcase
end
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:15]=reg_A[8:15]*reg_B[8:15];
result[16:31]=reg_A[24:31]*reg_B[24:31];
result[32:47]=reg_A[40:47]*reg_B[40:47];
result[48:63]=reg_A[56:63]*reg_B[56:63];
result[64:79]=reg_A[72:79]*reg_B[72:79];
result[80:95]=reg_A[88:95]*reg_B[88:95];
result[96:111]=reg_A[104:111]*reg_B[104:111];
result[112:127]=reg_A[120:127]*reg_B[120:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:31]=reg_A[16:31]*reg_B[16:31];
result[32:63]=reg_A[48:63]*reg_B[48:63];
result[64:95]=reg_A[80:95]*reg_B[80:95];
result[96:127]=reg_A[112:127]*reg_B[112:127];
end
default: // aluwsrl AND `aa AND Default
begin
result=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result=128'd0;
end
endcase
end
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_gen.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:18 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates the addr_gen and the data_gen modules. It takes
// the user data stored in internal FIFOs and gives the data that is to be
// compared with the read data
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter DM_WIDTH = 9,
parameter DQ_WIDTH = 72,
parameter APPDATA_WIDTH = 144,
parameter ECC_ENABLE = 0,
parameter ROW_WIDTH = 14
)
(
input clk,
input rst,
input wr_addr_en,
input wr_data_en,
input rd_data_valid,
output app_af_wren,
output [2:0] app_af_cmd,
output [30:0] app_af_addr,
output app_wdf_wren,
output [APPDATA_WIDTH-1:0] app_wdf_data,
output [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output [APPDATA_WIDTH-1:0] app_cmp_data
);
//***************************************************************************
ddr2_tb_test_addr_gen #
(
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH)
)
u_addr_gen
(
.clk (clk),
.rst (rst),
.wr_addr_en (wr_addr_en),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren)
);
ddr2_tb_test_data_gen #
(
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ECC_ENABLE (ECC_ENABLE)
)
u_data_gen
(
.clk (clk),
.rst (rst),
.wr_data_en (wr_data_en),
.rd_data_valid (rd_data_valid),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.app_cmp_data (app_cmp_data)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx2mb_entry.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* pcx2mb_entry.v: A single buffer entry for the SPARC PCX to MicroBlaze
* FSL Fifo. This register entry will be instantiated 9 times.
*
* NOTE: Pipeline stages from SPARC point of view are
* PQ Initial Request
* PA Data sent for request.
* PX Grant returned, Request sent to cache
* PX2 Data sent to cache
*
* $Id: pcx2mb_entry.v,v 1.1 2007/06/30 00:23:40 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module pcx2mb_entry (
// Outputs
e_data,
e_active,
e_dest,
// Inputs
rclk,
reset_l,
any_req_pa,
spc_pcx_data_pa,
req_dest_pa,
req_atom_pa,
any_req_px,
req_dest_px,
req_atom_px,
load_data,
prev_data,
prev_active,
prev_dest,
next_active
);
`ifdef PCX2MB_5_BIT_REQ
parameter PCX_REQ_WIDTH = 5;
`else
parameter PCX_REQ_WIDTH = 2;
`endif
output [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
output e_active;
output [4:0] e_dest;
input rclk;
input reset_l;
input any_req_pa;
input [`PCX_WIDTH-1:0] spc_pcx_data_pa;
input [4:0] req_dest_pa;
input req_atom_pa;
input any_req_px;
input [4:0] req_dest_px;
input req_atom_px;
input load_data;
input [`PCX_WIDTH+PCX_REQ_WIDTH:0] prev_data;
input prev_active;
input [4:0] prev_dest;
input next_active;
reg [`PCX_WIDTH+PCX_REQ_WIDTH:0] e_data;
reg e_active;
reg [4:0] e_dest;
// Code for entry here. If a new request is received while the next entry
// is active, and this entry is not active, it will be placed into this one.
always @(posedge rclk) begin
if (!reset_l) begin
e_data <= {`PCX_WIDTH+PCX_REQ_WIDTH+1{1'b0}};
e_active <= 1'b0;
e_dest <= 5'b00000;
end
else if (load_data && prev_active) begin
e_data <= prev_data;
e_active <= prev_active;
e_dest <= prev_dest;
end
else if (any_req_pa && (
(next_active && !load_data && !e_active) ||
(next_active && load_data && e_active && !prev_active)))
begin
`ifdef PCX2MB_5_BIT_REQ
e_data <= { req_dest_pa[4:0], req_atom_pa, spc_pcx_data_pa};
`else
e_data <= { req_dest_pa[4], (|req_dest_pa[3:0]), req_atom_pa,
spc_pcx_data_pa};
`endif
e_active <= 1'b1;
e_dest <= req_dest_pa;
end
else if (any_req_px && req_atom_px && (
(next_active && !load_data && !e_active) ||
(next_active && load_data && e_active && !prev_active)))
begin
`ifdef PCX2MB_5_BIT_REQ
e_data <= { req_dest_px[4:0], req_atom_px, spc_pcx_data_pa};
`else
e_data <= { req_dest_px[4], (|req_dest_px[3:0]), 1'b0,
spc_pcx_data_pa};
`endif
e_active <= 1'b1;
e_dest <= req_dest_px;
end
else begin
e_data <= e_data;
e_dest <= e_dest;
if (load_data && e_active) begin
e_active <= 1'b0;
end
else begin
e_active <= e_active;
end
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 19:26:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ns
module prcfg_top(
clk,
// gpio
dac_gpio_input,
dac_gpio_output,
adc_gpio_input,
adc_gpio_output,
// TX side
dma_dac_0_enable,
dma_dac_0_data,
dma_dac_0_valid,
dma_dac_1_enable,
dma_dac_1_data,
dma_dac_1_valid,
dma_dac_2_enable,
dma_dac_2_data,
dma_dac_2_valid,
dma_dac_3_enable,
dma_dac_3_data,
dma_dac_3_valid,
core_dac_0_enable,
core_dac_0_data,
core_dac_0_valid,
core_dac_1_enable,
core_dac_1_data,
core_dac_1_valid,
core_dac_2_enable,
core_dac_2_data,
core_dac_2_valid,
core_dac_3_enable,
core_dac_3_data,
core_dac_3_valid,
// RX side
dma_adc_0_enable,
dma_adc_0_data,
dma_adc_0_valid,
dma_adc_1_enable,
dma_adc_1_data,
dma_adc_1_valid,
dma_adc_2_enable,
dma_adc_2_data,
dma_adc_2_valid,
dma_adc_3_enable,
dma_adc_3_data,
dma_adc_3_valid,
core_adc_0_enable,
core_adc_0_data,
core_adc_0_valid,
core_adc_1_enable,
core_adc_1_data,
core_adc_1_valid,
core_adc_2_enable,
core_adc_2_data,
core_adc_2_valid,
core_adc_3_enable,
core_adc_3_data,
core_adc_3_valid
);
localparam ENABELED = 1;
localparam DATA_WIDTH = 16;
parameter NUM_CHANNEL = 4;
parameter ADC_EN = 1;
parameter DAC_EN = 1;
localparam DBUS_WIDTH = DATA_WIDTH * NUM_CHANNEL;
input clk;
input [31:0] dac_gpio_input;
output [31:0] dac_gpio_output;
input [31:0] adc_gpio_input;
output [31:0] adc_gpio_output;
input dma_dac_0_enable;
output [(DBUS_WIDTH-1):0] dma_dac_0_data;
input dma_dac_0_valid;
input dma_dac_1_enable;
output [(DBUS_WIDTH-1):0] dma_dac_1_data;
input dma_dac_1_valid;
input dma_dac_2_enable;
output [(DBUS_WIDTH-1):0] dma_dac_2_data;
input dma_dac_2_valid;
input dma_dac_3_enable;
output [(DBUS_WIDTH-1):0] dma_dac_3_data;
input dma_dac_3_valid;
output core_dac_0_enable;
input [(DBUS_WIDTH-1):0] core_dac_0_data;
output core_dac_0_valid;
output core_dac_1_enable;
input [(DBUS_WIDTH-1):0] core_dac_1_data;
output core_dac_1_valid;
output core_dac_2_enable;
input [(DBUS_WIDTH-1):0] core_dac_2_data;
output core_dac_2_valid;
output core_dac_3_enable;
input [(DBUS_WIDTH-1):0] core_dac_3_data;
output core_dac_3_valid;
// RX side
input dma_adc_0_enable;
input [(DBUS_WIDTH-1):0] dma_adc_0_data;
input dma_adc_0_valid;
input dma_adc_1_enable;
input [(DBUS_WIDTH-1):0] dma_adc_1_data;
input dma_adc_1_valid;
input dma_adc_2_enable;
input [(DBUS_WIDTH-1):0] dma_adc_2_data;
input dma_adc_2_valid;
input dma_adc_3_enable;
input [(DBUS_WIDTH-1):0] dma_adc_3_data;
input dma_adc_3_valid;
output core_adc_0_enable;
output [(DBUS_WIDTH-1):0] core_adc_0_data;
output core_adc_0_valid;
output core_adc_1_enable;
output [(DBUS_WIDTH-1):0] core_adc_1_data;
output core_adc_1_valid;
output core_adc_2_enable;
output [(DBUS_WIDTH-1):0] core_adc_2_data;
output core_adc_2_valid;
output core_adc_3_enable;
output [(DBUS_WIDTH-1):0] core_adc_3_data;
output core_adc_3_valid;
wire [31:0] adc_gpio_out_s[(NUM_CHANNEL - 1):0];
wire [(NUM_CHANNEL - 1):0] adc_gpio_out_s_inv[31:0];
wire [31:0] dac_gpio_out_s[(NUM_CHANNEL - 1):0];
wire [(NUM_CHANNEL - 1):0] dac_gpio_out_s_inv[31:0];
wire [(NUM_CHANNEL - 1):0] core_adc_enable_s;
wire [(NUM_CHANNEL - 1):0] core_adc_valid_s;
wire [(NUM_CHANNEL - 1):0] core_adc_data_s[15:0];
wire [(NUM_CHANNEL - 1):0] dma_adc_enable_s;
wire [(NUM_CHANNEL - 1):0] dma_adc_valid_s;
wire [(NUM_CHANNEL - 1):0] dma_adc_data_s[15:0];
wire [(NUM_CHANNEL - 1):0] core_dac_enable_s;
wire [(NUM_CHANNEL - 1):0] core_dac_valid_s;
wire [(NUM_CHANNEL - 1):0] core_dac_data_s[15:0];
wire [(NUM_CHANNEL - 1):0] dma_dac_enable_s;
wire [(NUM_CHANNEL - 1):0] dma_dac_valid_s;
wire [(NUM_CHANNEL - 1):0] dma_dac_data_s[15:0];
genvar l_inst;
generate
for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
if(ADC_EN == ENABELED) begin
prcfg_adc #(
.CHANNEL_ID(l_inst)
) i_prcfg_adc_i (
.clk(clk),
.control(adc_gpio_input),
.status(adc_gpio_out_s[l_inst]),
.src_adc_enable(core_adc_enable_s[l_inst]),
.src_adc_valid(core_adc_valid_s[l_inst]),
.src_adc_data(core_adc_data_s[l_inst]),
.dst_adc_enable(dma_adc_enable_s[l_inst]),
.dst_adc_valid(dma_adc_valid_s[l_inst]),
.dst_adc_data(dma_adc_data_s[l_inst])
);
end
if(DAC_EN == ENABELED) begin
prcfg_dac #(
.CHANNEL_ID(l_inst)
) i_prcfg_dac_i (
.clk(clk),
.control(dac_gpio_input),
.status(dac_gpio_out_s[l_inst]),
.src_dac_enable(dma_dac_enable_s[l_inst]),
.src_dac_data(dma_dac_data_s[l_inst]),
.src_dac_valid(dma_dac_valid_s[l_inst]),
.dst_dac_enable(core_dac_enable_s[l_inst]),
.dst_dac_data(core_dac_data_s[l_inst]),
.dst_dac_valid(core_dac_valid_s[l_inst])
);
end
end
endgenerate
genvar i;
genvar j;
generate
for(i = 0; i < 32; i = i + 1) begin
for(j = 0; j < NUM_CHANNEL; j = j + 1) begin
assign adc_gpio_out_s_inv[i][j] = adc_gpio_out_s[j][i];
assign dac_gpio_out_s_inv[i][j] = dac_gpio_out_s[j][i];
end
end
endgenerate
// generate gpio_outputs
generate
for(i = 0; i < 32; i = i + 1) begin
assign adc_gpio_output[i] = |adc_gpio_out_s_inv[i];
assign dac_gpio_output[i] = |dac_gpio_out_s_inv[i];
end
endgenerate
// port connections
assign core_dac_0_enable = core_dac_enable_s[0];
assign core_dac_0_valid = core_dac_valid_s[0];
assign core_dac_data_s[0] = core_dac_0_data;
assign core_dac_1_enable = core_dac_enable_s[1];
assign core_dac_1_valid = core_dac_valid_s[1];
assign core_dac_data_s[1] = core_dac_1_data;
assign core_dac_2_enable = core_dac_enable_s[2];
assign core_dac_2_valid = core_dac_valid_s[2];
assign core_dac_data_s[2] = core_dac_2_data;
assign core_dac_3_enable = core_dac_enable_s[3];
assign core_dac_3_valid = core_dac_valid_s[3];
assign core_dac_data_s[3] = core_dac_3_data;
assign dma_dac_enable_s[0] = dma_dac_0_enable;
assign dma_dac_valid_s[0] = dma_dac_0_valid;
assign dma_dac_0_data = dma_dac_data_s[0];
assign dma_dac_enable_s[1] = dma_dac_1_enable;
assign dma_dac_valid_s[1] = dma_dac_1_valid;
assign dma_dac_1_data = dma_dac_data_s[1];
assign dma_dac_enable_s[2] = dma_dac_2_enable;
assign dma_dac_valid_s[2] = dma_dac_2_valid;
assign dma_dac_2_data = dma_dac_data_s[2];
assign dma_dac_enable_s[3] = dma_dac_3_enable;
assign dma_dac_valid_s[3] = dma_dac_3_valid;
assign dma_dac_3_data = dma_dac_data_s[3];
assign core_adc_0_enable = core_adc_enable_s[0];
assign core_adc_0_valid = core_adc_valid_s[0];
assign core_adc_0_data = core_adc_data_s[0];
assign core_adc_1_enable = core_adc_enable_s[1];
assign core_adc_1_valid = core_adc_valid_s[1];
assign core_adc_1_data = core_adc_data_s[1];
assign core_adc_2_enable = core_adc_enable_s[2];
assign core_adc_2_valid = core_adc_valid_s[2];
assign core_adc_2_data = core_adc_data_s[2];
assign core_adc_3_enable = core_adc_enable_s[3];
assign core_adc_3_valid = core_adc_valid_s[3];
assign core_adc_3_data = core_adc_data_s[3];
assign dma_adc_enable_s[0] = dma_adc_0_enable;
assign dma_adc_valid_s[0] = dma_adc_0_valid;
assign dma_adc_data_s[0] = dma_adc_0_data;
assign dma_adc_enable_s[1] = dma_adc_1_enable;
assign dma_adc_valid_s[1] = dma_adc_1_valid;
assign dma_adc_data_s[1] = dma_adc_1_data;
assign dma_adc_enable_s[2] = dma_adc_2_enable;
assign dma_adc_valid_s[2] = dma_adc_2_valid;
assign dma_adc_data_s[2] = dma_adc_2_data;
assign dma_adc_enable_s[3] = dma_adc_3_enable;
assign dma_adc_valid_s[3] = dma_adc_3_valid;
assign dma_adc_data_s[3] = dma_adc_3_data;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_PP_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s6s (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_PP_SYMBOL_V
|
module unpack_signed #(
parameter N = 64
)
(
input [ 0:M-1] in,
output reg [ N-1: 0] out,
output wire [$clog2(MB)-1: 0] len
);
localparam MB = N/7+1;
localparam M = MB*8;
wire[N-1:0] unsigned_output;
integer i;
reg [MB-1:0] gl, ub, ho, sb;
unpack_unsigned #(.N(N)) u64(in, unsigned_output, len);
always @* begin
for(i=0; i<=MB-1; i=i+1) begin
gl [i ] = in[i*8 ]; // Glue bits
out[i*7 +: 7] = in[i*8+1 +: 7]; // Data chunks
end
// Used bytes
ub[0] = 1;
for(i=1; i<=MB-1; i=i+1)
ub[i] = gl[i-1] & ub[i-1]; // Should use more optimus &gl[i-1:0] instead
// Get high order byte
for(i=0; i<=MB-2; i=i+1)
ho[i] = !ub[i+1] & ub[i];
ho[MB-1] = ub[MB-1];
// Get sign bit from high order byte
for(i=0; i<=MB-1; i=i+1)
sb[i] = ho[i] & in[i*8+1];
// If number is negative, extend sign to left
if(|sb) begin
for(i=0; i<=MB-1; i=i+1)
if(!ub[i])
out[i*7 +: 7] = 7'b1111111;
end
// Number is positive
else
out = unsigned_output;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_PP_V
/**
* maj3: 3-input majority vote.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire or1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B, A );
and and0 (and0_out , or0_out, C );
and and1 (and1_out , A, B );
or or1 (or1_out_X , and1_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: FSM_Convert_Float_To_Fixed
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_Convert_Float_To_Fixed(
//INPUTS
input wire CLK, //system clock
input wire RST_FF, //system reset
input wire Exp_out, // INDICA SI EL VALOR DEL EXPONENTE ES MAYOR QUE 127
input wire Begin_FSM_FF, //inicia la maquina de estados
input wire [7:0] Exp, //CONTIENE EL EXPONENTE DEL NUMERO EN PUNTO FLOTANTE
// OUTPUTS
output reg EN_REG1, //ENABLE PARA EL REGISTRO QUE GUARDA EL NUMERO EN PUNTO FLOTANTE
output reg LOAD, //SELECCION PARA EL REGISTRO DE DESPLAZAMIENTOS
output reg MS_1, // SELECCION DEL MUX 1 (VALOR INICIAL DEL EXPONENTE , VALOR MODIFICADO DEL EXPONENTE)
output reg ACK_FF, // INDICA QUE LA CONVERSION FUE REALIZADA
output reg EN_MS_1,
output reg EN_REG2,
output reg RST
);
parameter [3:0] //se definen los estados que se utilizaran en la maquina
a = 4'b0000,
b = 4'b0001,
c = 4'b0010,
d = 4'b0011,
e = 4'b0100,
f = 4'b0101,
g = 4'b0110,
h = 4'b0111,
i = 4'b1000;
reg [3:0] state_reg, state_next ; //state registers declaration
always @(posedge CLK, posedge RST_FF)
if (RST_FF) begin
state_reg <= a;
end
else begin
state_reg <= state_next;
end
always @*
begin
state_next = state_reg;
EN_REG1 = 1'b0;
EN_REG2 = 1'b0;
ACK_FF = 1'b0;
EN_MS_1=1'b0;
MS_1=1'b0;
LOAD = 1'b0;
RST = 1'b0;
case(state_reg)
a:
begin
if(Begin_FSM_FF)
begin
RST = 1'b1;
ACK_FF = 1'b0;
state_next = b;
end
else
state_next = a;
end
b:
begin
EN_REG1 = 1'b1;
state_next = c;
end
c:
begin
EN_MS_1 = 1'b1;
if(Exp == 8'b01111111)
state_next = i;
else
state_next = d;
end
d:
begin
EN_MS_1 = 1'b1;
MS_1 = 1'b1;
state_next = e;
end
e:
begin
state_next = f;
end
f:
begin
LOAD = 1'b1;
state_next = g;
end
g:
begin
EN_REG2 = 1'b1;
state_next = h;
end
h:
begin
ACK_FF = 1'b1;
if(RST_FF)
state_next = a;
else
state_next = h;
end
i:
begin
state_next = f;
end
default:
state_next=a;
endcase
end
endmodule
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_3_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_3_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={123.076920} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333374} /><PLL domain={Memory} vco={1066.666748} /><PLL domain={IO} vco={1600.000000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
module processing_system7_v5_3_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484"
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TD_I,
//# #9 JTAG_TD_I and JTAG_TD_O should be separate
output PJTAG_TD_T,
output PJTAG_TD_O,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [31:0] TRACE_DATA,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input [3:0] FTMT_F2P_TRIG,
output [3:0] FTMT_F2P_TRIGACK,
input [31:0] FTMT_F2P_DEBUG,
input [3:0] FTMT_P2F_TRIGACK,
output [3:0] FTMT_P2F_TRIG,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TD_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_3_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// EMIO PJTAG
assign PJTAG_TD_T = ~ PJTAG_TD_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TD_O),
.EMIOPJTAGTDTN (PJTAG_TD_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL),
.EMIOTRACEDATA (TRACE_DATA),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK (FTMT_F2P_TRIGACK),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG (FTMT_P2F_TRIG ),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TD_I),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG (FTMT_F2P_TRIG ),
.FTMTP2FTRIGACK (FTMT_P2F_TRIGACK),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TD_O),
.EMIOPJTAGTDTN (PJTAG_TD_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL),
.EMIOTRACEDATA (TRACE_DATA),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK (FTMT_F2P_TRIGACK),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG (FTMT_P2F_TRIG ),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TD_I),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG (FTMT_F2P_TRIG ),
.FTMTP2FTRIGACK (FTMT_P2F_TRIGACK),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_3_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_1_V
`define SKY130_FD_SC_LP__INV_1_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_1_V
|
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 22555b464a02d8b7f8ed23cbb87c57aa9acddc90
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_WFI 2'b10
`define EnvCtrlEnum_binary_sequential_ECALL 2'b11
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [2:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
reg CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire CsrPlugin_allowEbreakException;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
reg [1:0] CsrPlugin_misa_base;
reg [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg [31:0] CsrPlugin_mscratch;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
reg CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1108;
wire when_CsrPlugin_l1110;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1129;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_when_GenCoreDefault_l367;
wire when_GenCoreDefault_l367;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_when_GenCoreDefault_l367_1;
wire when_GenCoreDefault_l367_1;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_when_GenCoreDefault_l367_2;
wire when_GenCoreDefault_l367_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_when_GenCoreDefault_l367_3;
wire when_GenCoreDefault_l367_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_when_GenCoreDefault_l367_4;
wire when_GenCoreDefault_l367_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_when_GenCoreDefault_l367_5;
wire when_GenCoreDefault_l367_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_when_GenCoreDefault_l367_6;
wire when_GenCoreDefault_l367_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_when_GenCoreDefault_l367_7;
wire when_GenCoreDefault_l367_7;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_52;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_54;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_57;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_60;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_61;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_62;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_3857;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_3858;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_3859;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_3860;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_769;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_832;
wire when_CsrPlugin_l1264_12;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_13;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_14;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_15;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_16;
reg execute_CsrPlugin_csr_2818;
wire when_CsrPlugin_l1264_17;
reg execute_CsrPlugin_csr_2946;
wire when_CsrPlugin_l1264_18;
reg execute_CsrPlugin_csr_3072;
wire when_CsrPlugin_l1264_19;
reg execute_CsrPlugin_csr_3200;
wire when_CsrPlugin_l1264_20;
reg execute_CsrPlugin_csr_3074;
wire when_CsrPlugin_l1264_21;
reg execute_CsrPlugin_csr_3202;
wire when_CsrPlugin_l1264_22;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_23;
reg execute_CsrPlugin_csr_4032;
wire when_CsrPlugin_l1264_24;
reg execute_CsrPlugin_csr_2820;
wire when_CsrPlugin_l1264_25;
reg execute_CsrPlugin_csr_2821;
wire when_CsrPlugin_l1264_26;
reg execute_CsrPlugin_csr_2822;
wire when_CsrPlugin_l1264_27;
reg execute_CsrPlugin_csr_2823;
wire when_CsrPlugin_l1264_28;
reg execute_CsrPlugin_csr_2824;
wire when_CsrPlugin_l1264_29;
reg execute_CsrPlugin_csr_2825;
wire when_CsrPlugin_l1264_30;
reg execute_CsrPlugin_csr_2826;
wire when_CsrPlugin_l1264_31;
reg execute_CsrPlugin_csr_2827;
wire when_CsrPlugin_l1264_32;
reg execute_CsrPlugin_csr_2828;
wire when_CsrPlugin_l1264_33;
reg execute_CsrPlugin_csr_2829;
wire when_CsrPlugin_l1264_34;
reg execute_CsrPlugin_csr_2830;
wire when_CsrPlugin_l1264_35;
reg execute_CsrPlugin_csr_2831;
wire when_CsrPlugin_l1264_36;
reg execute_CsrPlugin_csr_2832;
wire when_CsrPlugin_l1264_37;
reg execute_CsrPlugin_csr_2833;
wire when_CsrPlugin_l1264_38;
reg execute_CsrPlugin_csr_2834;
wire when_CsrPlugin_l1264_39;
reg execute_CsrPlugin_csr_2835;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [2:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0;
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1108) begin
if(when_CsrPlugin_l1110) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
always @(*) begin
CsrPlugin_inWfi = 1'b0;
if(when_CsrPlugin_l1108) begin
CsrPlugin_inWfi = 1'b1;
end
end
assign CsrPlugin_thirdPartyWake = 1'b0;
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign CsrPlugin_allowEbreakException = 1'b1;
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake);
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3857) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3858) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3859) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3860) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_769) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_835) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2816) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2944) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2818) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2946) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_3072) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3200) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3074) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3202) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2820) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2821) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2822) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2823) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2824) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2825) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2826) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2827) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2828) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2829) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2830) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2831) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2832) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2833) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2834) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_2835) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_valid = 1'b1;
end
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1129) begin
CsrPlugin_selfException_payload_code = 4'b0010;
end
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction);
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0];
assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0];
assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0];
assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0];
assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0];
assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0];
assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0];
assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0];
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_3857) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_3858) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0;
if(execute_CsrPlugin_csr_3859) begin
_zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0;
if(execute_CsrPlugin_csr_769) begin
_zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base;
_zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0;
if(execute_CsrPlugin_csr_773) begin
_zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base;
_zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0;
if(execute_CsrPlugin_csr_832) begin
_zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0;
if(execute_CsrPlugin_csr_2818) begin
_zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0;
if(execute_CsrPlugin_csr_2946) begin
_zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0;
if(execute_CsrPlugin_csr_3072) begin
_zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0;
if(execute_CsrPlugin_csr_3200) begin
_zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0;
if(execute_CsrPlugin_csr_3074) begin
_zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0;
if(execute_CsrPlugin_csr_3202) begin
_zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0;
if(execute_CsrPlugin_csr_2820) begin
_zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0;
if(execute_CsrPlugin_csr_2822) begin
_zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0;
if(execute_CsrPlugin_csr_2824) begin
_zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0;
if(execute_CsrPlugin_csr_2826) begin
_zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0;
if(execute_CsrPlugin_csr_2828) begin
_zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0;
if(execute_CsrPlugin_csr_2830) begin
_zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0;
if(execute_CsrPlugin_csr_2832) begin
_zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0;
if(execute_CsrPlugin_csr_2834) begin
_zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9;
end
end
assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40)))));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_misa_base <= 2'b01;
CsrPlugin_misa_extensions <= 26'h0000042;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_lastStageWasWfi <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 3'b000;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI));
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_61) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_769) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30];
CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0];
end
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 3'b000;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_GenCoreDefault_l367) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001);
end
if(when_GenCoreDefault_l367_1) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001);
end
if(when_GenCoreDefault_l367_2) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001);
end
if(when_GenCoreDefault_l367_3) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001);
end
if(when_GenCoreDefault_l367_4) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001);
end
if(when_GenCoreDefault_l367_5) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001);
end
if(when_GenCoreDefault_l367_6) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001);
end
if(when_GenCoreDefault_l367_7) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001);
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_52) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_54) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_55) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_60) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_62) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340);
end
if(when_CsrPlugin_l1264_12) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_13) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_14) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_15) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_16) begin
execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02);
end
if(when_CsrPlugin_l1264_17) begin
execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82);
end
if(when_CsrPlugin_l1264_18) begin
execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00);
end
if(when_CsrPlugin_l1264_19) begin
execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80);
end
if(when_CsrPlugin_l1264_20) begin
execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02);
end
if(when_CsrPlugin_l1264_21) begin
execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82);
end
if(when_CsrPlugin_l1264_22) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_23) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(when_CsrPlugin_l1264_24) begin
execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04);
end
if(when_CsrPlugin_l1264_25) begin
execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05);
end
if(when_CsrPlugin_l1264_26) begin
execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06);
end
if(when_CsrPlugin_l1264_27) begin
execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07);
end
if(when_CsrPlugin_l1264_28) begin
execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08);
end
if(when_CsrPlugin_l1264_29) begin
execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09);
end
if(when_CsrPlugin_l1264_30) begin
execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a);
end
if(when_CsrPlugin_l1264_31) begin
execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b);
end
if(when_CsrPlugin_l1264_32) begin
execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c);
end
if(when_CsrPlugin_l1264_33) begin
execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d);
end
if(when_CsrPlugin_l1264_34) begin
execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e);
end
if(when_CsrPlugin_l1264_35) begin
execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f);
end
if(when_CsrPlugin_l1264_36) begin
execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10);
end
if(when_CsrPlugin_l1264_37) begin
execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11);
end
if(when_CsrPlugin_l1264_38) begin
execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12);
end
if(when_CsrPlugin_l1264_39) begin
execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_832) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31];
CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0];
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2818) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2946) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2820) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2821) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2822) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2823) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2824) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2825) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2826) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2827) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2828) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2829) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2830) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2831) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2832) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2833) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2834) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(execute_CsrPlugin_csr_2835) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [2:0] _zz_loader_counter_valueNext;
wire [0:0] _zz_loader_counter_valueNext_1;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [6:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [6:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [6:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [7:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement;
assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1};
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 7'bxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 7'bxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[6:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[7]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[4 : 0] = 5'h0;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = {1'd0, stageB_request_size};
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 3'b101;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext);
if(loader_counter_willClear) begin
loader_counter_valueNext = 3'b000;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 8'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 3'b000;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 8'h01);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 8'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [22:0] _zz_ways_0_tags_port1;
wire [22:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [6:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [5:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [20:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [8:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [20:0] fetchStage_read_waysValues_0_tag_address;
wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [31:0] banks_0 [0:511];
(* ram_style = "block" *) reg [22:0] ways_0_tags [0:63];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 7'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
*/
input wire init_clk,
/*
* GPIO
*/
output wire led_sreg_d,
output wire led_sreg_ld,
output wire led_sreg_clk,
output wire [1:0] led_bmc,
output wire [1:0] led_exp,
/*
* Board status
*/
input wire [1:0] pg,
/*
* Ethernet: QSFP28
*/
output wire qsfp_0_tx_0_p,
output wire qsfp_0_tx_0_n,
input wire qsfp_0_rx_0_p,
input wire qsfp_0_rx_0_n,
output wire qsfp_0_tx_1_p,
output wire qsfp_0_tx_1_n,
input wire qsfp_0_rx_1_p,
input wire qsfp_0_rx_1_n,
output wire qsfp_0_tx_2_p,
output wire qsfp_0_tx_2_n,
input wire qsfp_0_rx_2_p,
input wire qsfp_0_rx_2_n,
output wire qsfp_0_tx_3_p,
output wire qsfp_0_tx_3_n,
input wire qsfp_0_rx_3_p,
input wire qsfp_0_rx_3_n,
input wire qsfp_0_mgt_refclk_p,
input wire qsfp_0_mgt_refclk_n,
input wire qsfp_0_mod_prsnt_n,
output wire qsfp_0_reset_n,
output wire qsfp_0_lp_mode,
input wire qsfp_0_intr_n,
output wire qsfp_1_tx_0_p,
output wire qsfp_1_tx_0_n,
input wire qsfp_1_rx_0_p,
input wire qsfp_1_rx_0_n,
output wire qsfp_1_tx_1_p,
output wire qsfp_1_tx_1_n,
input wire qsfp_1_rx_1_p,
input wire qsfp_1_rx_1_n,
output wire qsfp_1_tx_2_p,
output wire qsfp_1_tx_2_n,
input wire qsfp_1_rx_2_p,
input wire qsfp_1_rx_2_n,
output wire qsfp_1_tx_3_p,
output wire qsfp_1_tx_3_n,
input wire qsfp_1_rx_3_p,
input wire qsfp_1_rx_3_n,
input wire qsfp_1_mgt_refclk_p,
input wire qsfp_1_mgt_refclk_n,
input wire qsfp_1_mod_prsnt_n,
output wire qsfp_1_reset_n,
output wire qsfp_1_lp_mode,
input wire qsfp_1_intr_n
);
// Clock and reset
wire init_clk_bufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
// Internal 156.25 MHz clock
wire clk_156mhz_int;
wire rst_156mhz_int;
wire mmcm_rst = !pg[0] || !pg[1];
wire mmcm_locked;
wire mmcm_clkfb;
BUFG
init_clk_bufg_inst (
.I(init_clk),
.O(init_clk_bufg)
);
// MMCM instance
// 50 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 800 MHz to 1600 MHz
// M = 20, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME3_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(20),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(20.000),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(init_clk_bufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire [7:0] led_red;
wire [7:0] led_green;
wire [15:0] led_merged;
assign led_merged[0] = led_red[0];
assign led_merged[1] = led_green[0];
assign led_merged[2] = led_red[1];
assign led_merged[3] = led_green[1];
assign led_merged[4] = led_red[2];
assign led_merged[5] = led_green[2];
assign led_merged[6] = led_red[3];
assign led_merged[7] = led_green[3];
assign led_merged[8] = led_red[4];
assign led_merged[9] = led_green[4];
assign led_merged[10] = led_red[5];
assign led_merged[11] = led_green[5];
assign led_merged[12] = led_red[6];
assign led_merged[13] = led_green[6];
assign led_merged[14] = led_red[7];
assign led_merged[15] = led_green[7];
led_sreg_driver #(
.COUNT(16),
.INVERT(1),
.PRESCALE(31)
)
led_sreg_driver_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.led(led_merged),
.sreg_d(led_sreg_d),
.sreg_ld(led_sreg_ld),
.sreg_clk(led_sreg_clk)
);
// XGMII 10G PHY
assign qsfp_0_reset_n = 1'b1;
assign qsfp_0_lp_mode = 1'b0;
wire qsfp_0_tx_clk_0_int;
wire qsfp_0_tx_rst_0_int;
wire [63:0] qsfp_0_txd_0_int;
wire [7:0] qsfp_0_txc_0_int;
wire qsfp_0_rx_clk_0_int;
wire qsfp_0_rx_rst_0_int;
wire [63:0] qsfp_0_rxd_0_int;
wire [7:0] qsfp_0_rxc_0_int;
wire qsfp_0_tx_clk_1_int;
wire qsfp_0_tx_rst_1_int;
wire [63:0] qsfp_0_txd_1_int;
wire [7:0] qsfp_0_txc_1_int;
wire qsfp_0_rx_clk_1_int;
wire qsfp_0_rx_rst_1_int;
wire [63:0] qsfp_0_rxd_1_int;
wire [7:0] qsfp_0_rxc_1_int;
wire qsfp_0_tx_clk_2_int;
wire qsfp_0_tx_rst_2_int;
wire [63:0] qsfp_0_txd_2_int;
wire [7:0] qsfp_0_txc_2_int;
wire qsfp_0_rx_clk_2_int;
wire qsfp_0_rx_rst_2_int;
wire [63:0] qsfp_0_rxd_2_int;
wire [7:0] qsfp_0_rxc_2_int;
wire qsfp_0_tx_clk_3_int;
wire qsfp_0_tx_rst_3_int;
wire [63:0] qsfp_0_txd_3_int;
wire [7:0] qsfp_0_txc_3_int;
wire qsfp_0_rx_clk_3_int;
wire qsfp_0_rx_rst_3_int;
wire [63:0] qsfp_0_rxd_3_int;
wire [7:0] qsfp_0_rxc_3_int;
assign qsfp_1_reset_n = 1'b1;
assign qsfp_1_lp_mode = 1'b0;
wire qsfp_1_tx_clk_0_int;
wire qsfp_1_tx_rst_0_int;
wire [63:0] qsfp_1_txd_0_int;
wire [7:0] qsfp_1_txc_0_int;
wire qsfp_1_rx_clk_0_int;
wire qsfp_1_rx_rst_0_int;
wire [63:0] qsfp_1_rxd_0_int;
wire [7:0] qsfp_1_rxc_0_int;
wire qsfp_1_tx_clk_1_int;
wire qsfp_1_tx_rst_1_int;
wire [63:0] qsfp_1_txd_1_int;
wire [7:0] qsfp_1_txc_1_int;
wire qsfp_1_rx_clk_1_int;
wire qsfp_1_rx_rst_1_int;
wire [63:0] qsfp_1_rxd_1_int;
wire [7:0] qsfp_1_rxc_1_int;
wire qsfp_1_tx_clk_2_int;
wire qsfp_1_tx_rst_2_int;
wire [63:0] qsfp_1_txd_2_int;
wire [7:0] qsfp_1_txc_2_int;
wire qsfp_1_rx_clk_2_int;
wire qsfp_1_rx_rst_2_int;
wire [63:0] qsfp_1_rxd_2_int;
wire [7:0] qsfp_1_rxc_2_int;
wire qsfp_1_tx_clk_3_int;
wire qsfp_1_tx_rst_3_int;
wire [63:0] qsfp_1_txd_3_int;
wire [7:0] qsfp_1_txc_3_int;
wire qsfp_1_rx_clk_3_int;
wire qsfp_1_rx_rst_3_int;
wire [63:0] qsfp_1_rxd_3_int;
wire [7:0] qsfp_1_rxc_3_int;
wire qsfp_0_rx_block_lock_0;
wire qsfp_0_rx_block_lock_1;
wire qsfp_0_rx_block_lock_2;
wire qsfp_0_rx_block_lock_3;
wire qsfp_1_rx_block_lock_0;
wire qsfp_1_rx_block_lock_1;
wire qsfp_1_rx_block_lock_2;
wire qsfp_1_rx_block_lock_3;
wire qsfp_0_gtpowergood_0;
wire qsfp_0_gtpowergood_1;
wire qsfp_0_gtpowergood_2;
wire qsfp_0_gtpowergood_3;
wire qsfp_1_gtpowergood_0;
wire qsfp_1_gtpowergood_1;
wire qsfp_1_gtpowergood_2;
wire qsfp_1_gtpowergood_3;
wire qsfp_0_mgt_refclk;
wire qsfp_1_mgt_refclk;
wire [7:0] gt_txclkout;
wire gt_txusrclk;
wire [7:0] gt_rxclkout;
wire [7:0] gt_rxusrclk;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [7:0] gt_txprgdivresetdone;
wire [7:0] gt_txpmaresetdone;
wire [7:0] gt_rxprgdivresetdone;
wire [7:0] gt_rxpmaresetdone;
wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone));
wire gt_rx_reset = ~>_rxpmaresetdone;
reg gt_userclk_tx_active = 1'b0;
reg [7:0] gt_userclk_rx_active = 1'b0;
IBUFDS_GTE4 ibufds_gte4_qsfp_0_mgt_refclk_inst (
.I (qsfp_0_mgt_refclk_p),
.IB (qsfp_0_mgt_refclk_n),
.CEB (1'b0),
.O (qsfp_0_mgt_refclk),
.ODIV2 ()
);
IBUFDS_GTE4 ibufds_gte4_qsfp_1_mgt_refclk_inst (
.I (qsfp_1_mgt_refclk_p),
.IB (qsfp_1_mgt_refclk_n),
.CEB (1'b0),
.O (qsfp_1_mgt_refclk),
.ODIV2 ()
);
BUFG_GT bufg_gt_tx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_txclkout[0]),
.O (gt_txusrclk)
);
assign clk_156mhz_int = gt_txusrclk;
always @(posedge gt_txusrclk, posedge gt_tx_reset) begin
if (gt_tx_reset) begin
gt_userclk_tx_active <= 1'b0;
end else begin
gt_userclk_tx_active <= 1'b1;
end
end
generate
genvar n;
for (n = 0; n < 8; n = n + 1) begin
BUFG_GT bufg_gt_rx_usrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxclkout[n]),
.O (gt_rxusrclk[n])
);
always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin
if (gt_rx_reset) begin
gt_userclk_rx_active[n] <= 1'b0;
end else begin
gt_userclk_rx_active[n] <= 1'b1;
end
end
end
endgenerate
sync_reset #(
.N(4)
)
sync_reset_156mhz_inst (
.clk(clk_156mhz_int),
.rst(~gt_reset_tx_done),
.out(rst_156mhz_int)
);
wire [5:0] qsfp_0_gt_txheader_0;
wire [63:0] qsfp_0_gt_txdata_0;
wire qsfp_0_gt_rxgearboxslip_0;
wire [5:0] qsfp_0_gt_rxheader_0;
wire [1:0] qsfp_0_gt_rxheadervalid_0;
wire [63:0] qsfp_0_gt_rxdata_0;
wire [1:0] qsfp_0_gt_rxdatavalid_0;
wire [5:0] qsfp_0_gt_txheader_1;
wire [63:0] qsfp_0_gt_txdata_1;
wire qsfp_0_gt_rxgearboxslip_1;
wire [5:0] qsfp_0_gt_rxheader_1;
wire [1:0] qsfp_0_gt_rxheadervalid_1;
wire [63:0] qsfp_0_gt_rxdata_1;
wire [1:0] qsfp_0_gt_rxdatavalid_1;
wire [5:0] qsfp_0_gt_txheader_2;
wire [63:0] qsfp_0_gt_txdata_2;
wire qsfp_0_gt_rxgearboxslip_2;
wire [5:0] qsfp_0_gt_rxheader_2;
wire [1:0] qsfp_0_gt_rxheadervalid_2;
wire [63:0] qsfp_0_gt_rxdata_2;
wire [1:0] qsfp_0_gt_rxdatavalid_2;
wire [5:0] qsfp_0_gt_txheader_3;
wire [63:0] qsfp_0_gt_txdata_3;
wire qsfp_0_gt_rxgearboxslip_3;
wire [5:0] qsfp_0_gt_rxheader_3;
wire [1:0] qsfp_0_gt_rxheadervalid_3;
wire [63:0] qsfp_0_gt_rxdata_3;
wire [1:0] qsfp_0_gt_rxdatavalid_3;
wire [5:0] qsfp_1_gt_txheader_0;
wire [63:0] qsfp_1_gt_txdata_0;
wire qsfp_1_gt_rxgearboxslip_0;
wire [5:0] qsfp_1_gt_rxheader_0;
wire [1:0] qsfp_1_gt_rxheadervalid_0;
wire [63:0] qsfp_1_gt_rxdata_0;
wire [1:0] qsfp_1_gt_rxdatavalid_0;
wire [5:0] qsfp_1_gt_txheader_1;
wire [63:0] qsfp_1_gt_txdata_1;
wire qsfp_1_gt_rxgearboxslip_1;
wire [5:0] qsfp_1_gt_rxheader_1;
wire [1:0] qsfp_1_gt_rxheadervalid_1;
wire [63:0] qsfp_1_gt_rxdata_1;
wire [1:0] qsfp_1_gt_rxdatavalid_1;
wire [5:0] qsfp_1_gt_txheader_2;
wire [63:0] qsfp_1_gt_txdata_2;
wire qsfp_1_gt_rxgearboxslip_2;
wire [5:0] qsfp_1_gt_rxheader_2;
wire [1:0] qsfp_1_gt_rxheadervalid_2;
wire [63:0] qsfp_1_gt_rxdata_2;
wire [1:0] qsfp_1_gt_rxdatavalid_2;
wire [5:0] qsfp_1_gt_txheader_3;
wire [63:0] qsfp_1_gt_txdata_3;
wire qsfp_1_gt_rxgearboxslip_3;
wire [5:0] qsfp_1_gt_rxheader_3;
wire [1:0] qsfp_1_gt_rxheadervalid_3;
wire [63:0] qsfp_1_gt_rxdata_3;
wire [1:0] qsfp_1_gt_rxdatavalid_3;
gtwizard_ultrascale_0
qsfp_gty_inst (
.gtwiz_userclk_tx_active_in(>_userclk_tx_active),
.gtwiz_userclk_rx_active_in(>_userclk_rx_active),
.gtwiz_reset_clk_freerun_in(clk_125mhz_int),
.gtwiz_reset_all_in(rst_125mhz_int),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(1'b0),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(1'b0),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.gtrefclk00_in({qsfp_1_mgt_refclk, qsfp_0_mgt_refclk}),
.qpll0outclk_out(),
.qpll0outrefclk_out(),
.gtyrxn_in({qsfp_1_rx_3_n, qsfp_1_rx_2_n, qsfp_1_rx_1_n, qsfp_1_rx_0_n, qsfp_0_rx_3_n, qsfp_0_rx_2_n, qsfp_0_rx_1_n, qsfp_0_rx_0_n}),
.gtyrxp_in({qsfp_1_rx_3_p, qsfp_1_rx_2_p, qsfp_1_rx_1_p, qsfp_1_rx_0_p, qsfp_0_rx_3_p, qsfp_0_rx_2_p, qsfp_0_rx_1_p, qsfp_0_rx_0_p}),
.rxusrclk_in(gt_rxusrclk),
.rxusrclk2_in(gt_rxusrclk),
.gtwiz_userdata_tx_in({qsfp_1_gt_txdata_3, qsfp_1_gt_txdata_2, qsfp_1_gt_txdata_1, qsfp_1_gt_txdata_0, qsfp_0_gt_txdata_3, qsfp_0_gt_txdata_2, qsfp_0_gt_txdata_1, qsfp_0_gt_txdata_0}),
.txheader_in({qsfp_1_gt_txheader_3, qsfp_1_gt_txheader_2, qsfp_1_gt_txheader_1, qsfp_1_gt_txheader_0, qsfp_0_gt_txheader_3, qsfp_0_gt_txheader_2, qsfp_0_gt_txheader_1, qsfp_0_gt_txheader_0}),
.txsequence_in({8{1'b0}}),
.txusrclk_in({8{gt_txusrclk}}),
.txusrclk2_in({8{gt_txusrclk}}),
.gtpowergood_out({qsfp_1_gtpowergood_3, qsfp_1_gtpowergood_2, qsfp_1_gtpowergood_1, qsfp_1_gtpowergood_0, qsfp_0_gtpowergood_3, qsfp_0_gtpowergood_2, qsfp_0_gtpowergood_1, qsfp_0_gtpowergood_0}),
.gtytxn_out({qsfp_1_tx_3_n, qsfp_1_tx_2_n, qsfp_1_tx_1_n, qsfp_1_tx_0_n, qsfp_0_tx_3_n, qsfp_0_tx_2_n, qsfp_0_tx_1_n, qsfp_0_tx_0_n}),
.gtytxp_out({qsfp_1_tx_3_p, qsfp_1_tx_2_p, qsfp_1_tx_1_p, qsfp_1_tx_0_p, qsfp_0_tx_3_p, qsfp_0_tx_2_p, qsfp_0_tx_1_p, qsfp_0_tx_0_p}),
.rxgearboxslip_in({qsfp_1_gt_rxgearboxslip_3, qsfp_1_gt_rxgearboxslip_2, qsfp_1_gt_rxgearboxslip_1, qsfp_1_gt_rxgearboxslip_0, qsfp_0_gt_rxgearboxslip_3, qsfp_0_gt_rxgearboxslip_2, qsfp_0_gt_rxgearboxslip_1, qsfp_0_gt_rxgearboxslip_0}),
.gtwiz_userdata_rx_out({qsfp_1_gt_rxdata_3, qsfp_1_gt_rxdata_2, qsfp_1_gt_rxdata_1, qsfp_1_gt_rxdata_0, qsfp_0_gt_rxdata_3, qsfp_0_gt_rxdata_2, qsfp_0_gt_rxdata_1, qsfp_0_gt_rxdata_0}),
.rxdatavalid_out({qsfp_1_gt_rxdatavalid_3, qsfp_1_gt_rxdatavalid_2, qsfp_1_gt_rxdatavalid_1, qsfp_1_gt_rxdatavalid_0, qsfp_0_gt_rxdatavalid_3, qsfp_0_gt_rxdatavalid_2, qsfp_0_gt_rxdatavalid_1, qsfp_0_gt_rxdatavalid_0}),
.rxheader_out({qsfp_1_gt_rxheader_3, qsfp_1_gt_rxheader_2, qsfp_1_gt_rxheader_1, qsfp_1_gt_rxheader_0, qsfp_0_gt_rxheader_3, qsfp_0_gt_rxheader_2, qsfp_0_gt_rxheader_1, qsfp_0_gt_rxheader_0}),
.rxheadervalid_out({qsfp_1_gt_rxheadervalid_3, qsfp_1_gt_rxheadervalid_2, qsfp_1_gt_rxheadervalid_1, qsfp_1_gt_rxheadervalid_0, qsfp_0_gt_rxheadervalid_3, qsfp_0_gt_rxheadervalid_2, qsfp_0_gt_rxheadervalid_1, qsfp_0_gt_rxheadervalid_0}),
.rxoutclk_out(gt_rxclkout),
.rxpmaresetdone_out(gt_rxpmaresetdone),
.rxprgdivresetdone_out(gt_rxprgdivresetdone),
.rxstartofseq_out(),
.txoutclk_out(gt_txclkout),
.txpmaresetdone_out(gt_txpmaresetdone),
.txprgdivresetdone_out(gt_txprgdivresetdone)
);
assign qsfp_0_tx_clk_0_int = clk_156mhz_int;
assign qsfp_0_tx_rst_0_int = rst_156mhz_int;
assign qsfp_0_rx_clk_0_int = gt_rxusrclk[0];
sync_reset #(
.N(4)
)
qsfp_0_rx_rst_0_reset_sync_inst (
.clk(qsfp_0_rx_clk_0_int),
.rst(~gt_reset_rx_done),
.out(qsfp_0_rx_rst_0_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_0_phy_0_inst (
.tx_clk(qsfp_0_tx_clk_0_int),
.tx_rst(qsfp_0_tx_rst_0_int),
.rx_clk(qsfp_0_rx_clk_0_int),
.rx_rst(qsfp_0_rx_rst_0_int),
.xgmii_txd(qsfp_0_txd_0_int),
.xgmii_txc(qsfp_0_txc_0_int),
.xgmii_rxd(qsfp_0_rxd_0_int),
.xgmii_rxc(qsfp_0_rxc_0_int),
.serdes_tx_data(qsfp_0_gt_txdata_0),
.serdes_tx_hdr(qsfp_0_gt_txheader_0),
.serdes_rx_data(qsfp_0_gt_rxdata_0),
.serdes_rx_hdr(qsfp_0_gt_rxheader_0),
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_0),
.rx_block_lock(qsfp_0_rx_block_lock_0),
.rx_high_ber()
);
assign qsfp_0_tx_clk_1_int = clk_156mhz_int;
assign qsfp_0_tx_rst_1_int = rst_156mhz_int;
assign qsfp_0_rx_clk_1_int = gt_rxusrclk[1];
sync_reset #(
.N(4)
)
qsfp_0_rx_rst_1_reset_sync_inst (
.clk(qsfp_0_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp_0_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_0_phy_1_inst (
.tx_clk(qsfp_0_tx_clk_1_int),
.tx_rst(qsfp_0_tx_rst_1_int),
.rx_clk(qsfp_0_rx_clk_1_int),
.rx_rst(qsfp_0_rx_rst_1_int),
.xgmii_txd(qsfp_0_txd_1_int),
.xgmii_txc(qsfp_0_txc_1_int),
.xgmii_rxd(qsfp_0_rxd_1_int),
.xgmii_rxc(qsfp_0_rxc_1_int),
.serdes_tx_data(qsfp_0_gt_txdata_1),
.serdes_tx_hdr(qsfp_0_gt_txheader_1),
.serdes_rx_data(qsfp_0_gt_rxdata_1),
.serdes_rx_hdr(qsfp_0_gt_rxheader_1),
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_1),
.rx_block_lock(qsfp_0_rx_block_lock_1),
.rx_high_ber()
);
assign qsfp_0_tx_clk_2_int = clk_156mhz_int;
assign qsfp_0_tx_rst_2_int = rst_156mhz_int;
assign qsfp_0_rx_clk_2_int = gt_rxusrclk[2];
sync_reset #(
.N(4)
)
qsfp_0_rx_rst_2_reset_sync_inst (
.clk(qsfp_0_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp_0_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_0_phy_2_inst (
.tx_clk(qsfp_0_tx_clk_2_int),
.tx_rst(qsfp_0_tx_rst_2_int),
.rx_clk(qsfp_0_rx_clk_2_int),
.rx_rst(qsfp_0_rx_rst_2_int),
.xgmii_txd(qsfp_0_txd_2_int),
.xgmii_txc(qsfp_0_txc_2_int),
.xgmii_rxd(qsfp_0_rxd_2_int),
.xgmii_rxc(qsfp_0_rxc_2_int),
.serdes_tx_data(qsfp_0_gt_txdata_2),
.serdes_tx_hdr(qsfp_0_gt_txheader_2),
.serdes_rx_data(qsfp_0_gt_rxdata_2),
.serdes_rx_hdr(qsfp_0_gt_rxheader_2),
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_2),
.rx_block_lock(qsfp_0_rx_block_lock_2),
.rx_high_ber()
);
assign qsfp_0_tx_clk_3_int = clk_156mhz_int;
assign qsfp_0_tx_rst_3_int = rst_156mhz_int;
assign qsfp_0_rx_clk_3_int = gt_rxusrclk[3];
sync_reset #(
.N(4)
)
qsfp_0_rx_rst_3_reset_sync_inst (
.clk(qsfp_0_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp_0_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_0_phy_3_inst (
.tx_clk(qsfp_0_tx_clk_3_int),
.tx_rst(qsfp_0_tx_rst_3_int),
.rx_clk(qsfp_0_rx_clk_3_int),
.rx_rst(qsfp_0_rx_rst_3_int),
.xgmii_txd(qsfp_0_txd_3_int),
.xgmii_txc(qsfp_0_txc_3_int),
.xgmii_rxd(qsfp_0_rxd_3_int),
.xgmii_rxc(qsfp_0_rxc_3_int),
.serdes_tx_data(qsfp_0_gt_txdata_3),
.serdes_tx_hdr(qsfp_0_gt_txheader_3),
.serdes_rx_data(qsfp_0_gt_rxdata_3),
.serdes_rx_hdr(qsfp_0_gt_rxheader_3),
.serdes_rx_bitslip(qsfp_0_gt_rxgearboxslip_3),
.rx_block_lock(qsfp_0_rx_block_lock_3),
.rx_high_ber()
);
assign qsfp_1_tx_clk_0_int = clk_156mhz_int;
assign qsfp_1_tx_rst_0_int = rst_156mhz_int;
assign qsfp_1_rx_clk_0_int = gt_rxusrclk[4];
sync_reset #(
.N(4)
)
qsfp_1_rx_rst_0_reset_sync_inst (
.clk(qsfp_1_rx_clk_0_int),
.rst(~gt_reset_rx_done),
.out(qsfp_1_rx_rst_0_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_1_phy_0_inst (
.tx_clk(qsfp_1_tx_clk_0_int),
.tx_rst(qsfp_1_tx_rst_0_int),
.rx_clk(qsfp_1_rx_clk_0_int),
.rx_rst(qsfp_1_rx_rst_0_int),
.xgmii_txd(qsfp_1_txd_0_int),
.xgmii_txc(qsfp_1_txc_0_int),
.xgmii_rxd(qsfp_1_rxd_0_int),
.xgmii_rxc(qsfp_1_rxc_0_int),
.serdes_tx_data(qsfp_1_gt_txdata_0),
.serdes_tx_hdr(qsfp_1_gt_txheader_0),
.serdes_rx_data(qsfp_1_gt_rxdata_0),
.serdes_rx_hdr(qsfp_1_gt_rxheader_0),
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_0),
.rx_block_lock(qsfp_1_rx_block_lock_0),
.rx_high_ber()
);
assign qsfp_1_tx_clk_1_int = clk_156mhz_int;
assign qsfp_1_tx_rst_1_int = rst_156mhz_int;
assign qsfp_1_rx_clk_1_int = gt_rxusrclk[5];
sync_reset #(
.N(4)
)
qsfp_1_rx_rst_1_reset_sync_inst (
.clk(qsfp_1_rx_clk_1_int),
.rst(~gt_reset_rx_done),
.out(qsfp_1_rx_rst_1_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_1_phy_1_inst (
.tx_clk(qsfp_1_tx_clk_1_int),
.tx_rst(qsfp_1_tx_rst_1_int),
.rx_clk(qsfp_1_rx_clk_1_int),
.rx_rst(qsfp_1_rx_rst_1_int),
.xgmii_txd(qsfp_1_txd_1_int),
.xgmii_txc(qsfp_1_txc_1_int),
.xgmii_rxd(qsfp_1_rxd_1_int),
.xgmii_rxc(qsfp_1_rxc_1_int),
.serdes_tx_data(qsfp_1_gt_txdata_1),
.serdes_tx_hdr(qsfp_1_gt_txheader_1),
.serdes_rx_data(qsfp_1_gt_rxdata_1),
.serdes_rx_hdr(qsfp_1_gt_rxheader_1),
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_1),
.rx_block_lock(qsfp_1_rx_block_lock_1),
.rx_high_ber()
);
assign qsfp_1_tx_clk_2_int = clk_156mhz_int;
assign qsfp_1_tx_rst_2_int = rst_156mhz_int;
assign qsfp_1_rx_clk_2_int = gt_rxusrclk[6];
sync_reset #(
.N(4)
)
qsfp_1_rx_rst_2_reset_sync_inst (
.clk(qsfp_1_rx_clk_2_int),
.rst(~gt_reset_rx_done),
.out(qsfp_1_rx_rst_2_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_1_phy_2_inst (
.tx_clk(qsfp_1_tx_clk_2_int),
.tx_rst(qsfp_1_tx_rst_2_int),
.rx_clk(qsfp_1_rx_clk_2_int),
.rx_rst(qsfp_1_rx_rst_2_int),
.xgmii_txd(qsfp_1_txd_2_int),
.xgmii_txc(qsfp_1_txc_2_int),
.xgmii_rxd(qsfp_1_rxd_2_int),
.xgmii_rxc(qsfp_1_rxc_2_int),
.serdes_tx_data(qsfp_1_gt_txdata_2),
.serdes_tx_hdr(qsfp_1_gt_txheader_2),
.serdes_rx_data(qsfp_1_gt_rxdata_2),
.serdes_rx_hdr(qsfp_1_gt_rxheader_2),
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_2),
.rx_block_lock(qsfp_1_rx_block_lock_2),
.rx_high_ber()
);
assign qsfp_1_tx_clk_3_int = clk_156mhz_int;
assign qsfp_1_tx_rst_3_int = rst_156mhz_int;
assign qsfp_1_rx_clk_3_int = gt_rxusrclk[7];
sync_reset #(
.N(4)
)
qsfp_1_rx_rst_3_reset_sync_inst (
.clk(qsfp_1_rx_clk_3_int),
.rst(~gt_reset_rx_done),
.out(qsfp_1_rx_rst_3_int)
);
eth_phy_10g #(
.BIT_REVERSE(1)
)
qsfp_1_phy_3_inst (
.tx_clk(qsfp_1_tx_clk_3_int),
.tx_rst(qsfp_1_tx_rst_3_int),
.rx_clk(qsfp_1_rx_clk_3_int),
.rx_rst(qsfp_1_rx_rst_3_int),
.xgmii_txd(qsfp_1_txd_3_int),
.xgmii_txc(qsfp_1_txc_3_int),
.xgmii_rxd(qsfp_1_rxd_3_int),
.xgmii_rxc(qsfp_1_rxc_3_int),
.serdes_tx_data(qsfp_1_gt_txdata_3),
.serdes_tx_hdr(qsfp_1_gt_txheader_3),
.serdes_rx_data(qsfp_1_gt_rxdata_3),
.serdes_rx_hdr(qsfp_1_gt_rxheader_3),
.serdes_rx_bitslip(qsfp_1_gt_rxgearboxslip_3),
.rx_block_lock(qsfp_1_rx_block_lock_3),
.rx_high_ber()
);
assign led_green = {qsfp_1_rx_block_lock_3, qsfp_1_rx_block_lock_2, qsfp_1_rx_block_lock_1, qsfp_1_rx_block_lock_0, qsfp_0_rx_block_lock_3, qsfp_0_rx_block_lock_2, qsfp_0_rx_block_lock_1, qsfp_0_rx_block_lock_0};
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.led_red(led_red),
// .led_green(led_green),
.led_bmc(led_bmc),
.led_exp(led_exp),
/*
* Ethernet: QSFP28
*/
.qsfp_0_tx_clk_0(qsfp_0_tx_clk_0_int),
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
.qsfp_0_txd_0(qsfp_0_txd_0_int),
.qsfp_0_txc_0(qsfp_0_txc_0_int),
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
.qsfp_0_txd_1(qsfp_0_txd_1_int),
.qsfp_0_txc_1(qsfp_0_txc_1_int),
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
.qsfp_0_txd_2(qsfp_0_txd_2_int),
.qsfp_0_txc_2(qsfp_0_txc_2_int),
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
.qsfp_0_txd_3(qsfp_0_txd_3_int),
.qsfp_0_txc_3(qsfp_0_txc_3_int),
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
.qsfp_1_tx_clk_0(qsfp_1_tx_clk_0_int),
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
.qsfp_1_txd_0(qsfp_1_txd_0_int),
.qsfp_1_txc_0(qsfp_1_txc_0_int),
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
.qsfp_1_txd_1(qsfp_1_txd_1_int),
.qsfp_1_txc_1(qsfp_1_txc_1_int),
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
.qsfp_1_txd_2(qsfp_1_txd_2_int),
.qsfp_1_txc_2(qsfp_1_txc_2_int),
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
.qsfp_1_txd_3(qsfp_1_txd_3_int),
.qsfp_1_txc_3(qsfp_1_txc_3_int),
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
.qsfp_1_rxc_3(qsfp_1_rxc_3_int)
);
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// RDY_set_addr_map O 1 const
// axi4_slave_awready O 1 reg
// axi4_slave_wready O 1 reg
// axi4_slave_bvalid O 1 reg
// axi4_slave_bid O 4 reg
// axi4_slave_bresp O 2 reg
// axi4_slave_arready O 1 reg
// axi4_slave_rvalid O 1 reg
// axi4_slave_rid O 4 reg
// axi4_slave_rdata O 64 reg
// axi4_slave_rresp O 2 reg
// axi4_slave_rlast O 1 reg
// get_timer_interrupt_req_get O 1 reg
// RDY_get_timer_interrupt_req_get O 1 reg
// get_sw_interrupt_req_get O 1 reg
// RDY_get_sw_interrupt_req_get O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_addr_map_addr_base I 64 reg
// set_addr_map_addr_lim I 64 reg
// axi4_slave_awvalid I 1
// axi4_slave_awid I 4 reg
// axi4_slave_awaddr I 64 reg
// axi4_slave_awlen I 8 reg
// axi4_slave_awsize I 3 reg
// axi4_slave_awburst I 2 reg
// axi4_slave_awlock I 1 reg
// axi4_slave_awcache I 4 reg
// axi4_slave_awprot I 3 reg
// axi4_slave_awqos I 4 reg
// axi4_slave_awregion I 4 reg
// axi4_slave_wvalid I 1
// axi4_slave_wdata I 64 reg
// axi4_slave_wstrb I 8 reg
// axi4_slave_wlast I 1 reg
// axi4_slave_bready I 1
// axi4_slave_arvalid I 1
// axi4_slave_arid I 4 reg
// axi4_slave_araddr I 64 reg
// axi4_slave_arlen I 8 reg
// axi4_slave_arsize I 3 reg
// axi4_slave_arburst I 2 reg
// axi4_slave_arlock I 1 reg
// axi4_slave_arcache I 4 reg
// axi4_slave_arprot I 3 reg
// axi4_slave_arqos I 4 reg
// axi4_slave_arregion I 4 reg
// axi4_slave_rready I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_set_addr_map I 1
// EN_get_timer_interrupt_req_get I 1
// EN_get_sw_interrupt_req_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkNear_Mem_IO_AXI4(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
set_addr_map_addr_base,
set_addr_map_addr_lim,
EN_set_addr_map,
RDY_set_addr_map,
axi4_slave_awvalid,
axi4_slave_awid,
axi4_slave_awaddr,
axi4_slave_awlen,
axi4_slave_awsize,
axi4_slave_awburst,
axi4_slave_awlock,
axi4_slave_awcache,
axi4_slave_awprot,
axi4_slave_awqos,
axi4_slave_awregion,
axi4_slave_awready,
axi4_slave_wvalid,
axi4_slave_wdata,
axi4_slave_wstrb,
axi4_slave_wlast,
axi4_slave_wready,
axi4_slave_bvalid,
axi4_slave_bid,
axi4_slave_bresp,
axi4_slave_bready,
axi4_slave_arvalid,
axi4_slave_arid,
axi4_slave_araddr,
axi4_slave_arlen,
axi4_slave_arsize,
axi4_slave_arburst,
axi4_slave_arlock,
axi4_slave_arcache,
axi4_slave_arprot,
axi4_slave_arqos,
axi4_slave_arregion,
axi4_slave_arready,
axi4_slave_rvalid,
axi4_slave_rid,
axi4_slave_rdata,
axi4_slave_rresp,
axi4_slave_rlast,
axi4_slave_rready,
EN_get_timer_interrupt_req_get,
get_timer_interrupt_req_get,
RDY_get_timer_interrupt_req_get,
EN_get_sw_interrupt_req_get,
get_sw_interrupt_req_get,
RDY_get_sw_interrupt_req_get);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method set_addr_map
input [63 : 0] set_addr_map_addr_base;
input [63 : 0] set_addr_map_addr_lim;
input EN_set_addr_map;
output RDY_set_addr_map;
// action method axi4_slave_m_awvalid
input axi4_slave_awvalid;
input [3 : 0] axi4_slave_awid;
input [63 : 0] axi4_slave_awaddr;
input [7 : 0] axi4_slave_awlen;
input [2 : 0] axi4_slave_awsize;
input [1 : 0] axi4_slave_awburst;
input axi4_slave_awlock;
input [3 : 0] axi4_slave_awcache;
input [2 : 0] axi4_slave_awprot;
input [3 : 0] axi4_slave_awqos;
input [3 : 0] axi4_slave_awregion;
// value method axi4_slave_m_awready
output axi4_slave_awready;
// action method axi4_slave_m_wvalid
input axi4_slave_wvalid;
input [63 : 0] axi4_slave_wdata;
input [7 : 0] axi4_slave_wstrb;
input axi4_slave_wlast;
// value method axi4_slave_m_wready
output axi4_slave_wready;
// value method axi4_slave_m_bvalid
output axi4_slave_bvalid;
// value method axi4_slave_m_bid
output [3 : 0] axi4_slave_bid;
// value method axi4_slave_m_bresp
output [1 : 0] axi4_slave_bresp;
// value method axi4_slave_m_buser
// action method axi4_slave_m_bready
input axi4_slave_bready;
// action method axi4_slave_m_arvalid
input axi4_slave_arvalid;
input [3 : 0] axi4_slave_arid;
input [63 : 0] axi4_slave_araddr;
input [7 : 0] axi4_slave_arlen;
input [2 : 0] axi4_slave_arsize;
input [1 : 0] axi4_slave_arburst;
input axi4_slave_arlock;
input [3 : 0] axi4_slave_arcache;
input [2 : 0] axi4_slave_arprot;
input [3 : 0] axi4_slave_arqos;
input [3 : 0] axi4_slave_arregion;
// value method axi4_slave_m_arready
output axi4_slave_arready;
// value method axi4_slave_m_rvalid
output axi4_slave_rvalid;
// value method axi4_slave_m_rid
output [3 : 0] axi4_slave_rid;
// value method axi4_slave_m_rdata
output [63 : 0] axi4_slave_rdata;
// value method axi4_slave_m_rresp
output [1 : 0] axi4_slave_rresp;
// value method axi4_slave_m_rlast
output axi4_slave_rlast;
// value method axi4_slave_m_ruser
// action method axi4_slave_m_rready
input axi4_slave_rready;
// actionvalue method get_timer_interrupt_req_get
input EN_get_timer_interrupt_req_get;
output get_timer_interrupt_req_get;
output RDY_get_timer_interrupt_req_get;
// actionvalue method get_sw_interrupt_req_get
input EN_get_sw_interrupt_req_get;
output get_sw_interrupt_req_get;
output RDY_get_sw_interrupt_req_get;
// signals for module outputs
wire [63 : 0] axi4_slave_rdata;
wire [3 : 0] axi4_slave_bid, axi4_slave_rid;
wire [1 : 0] axi4_slave_bresp, axi4_slave_rresp;
wire RDY_get_sw_interrupt_req_get,
RDY_get_timer_interrupt_req_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_addr_map,
axi4_slave_arready,
axi4_slave_awready,
axi4_slave_bvalid,
axi4_slave_rlast,
axi4_slave_rvalid,
axi4_slave_wready,
get_sw_interrupt_req_get,
get_timer_interrupt_req_get;
// inlined wires
wire [63 : 0] crg_time$port0__write_1,
crg_time$port1__write_1,
crg_time$port2__read,
crg_timecmp$port1__write_1,
crg_timecmp$port2__read;
wire crg_time$EN_port1__write, crg_timecmp$EN_port1__write;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register crg_time
reg [63 : 0] crg_time;
wire [63 : 0] crg_time$D_IN;
wire crg_time$EN;
// register crg_timecmp
reg [63 : 0] crg_timecmp;
wire [63 : 0] crg_timecmp$D_IN;
wire crg_timecmp$EN;
// register rg_addr_base
reg [63 : 0] rg_addr_base;
wire [63 : 0] rg_addr_base$D_IN;
wire rg_addr_base$EN;
// register rg_addr_lim
reg [63 : 0] rg_addr_lim;
wire [63 : 0] rg_addr_lim$D_IN;
wire rg_addr_lim$EN;
// register rg_msip
reg rg_msip;
wire rg_msip$D_IN, rg_msip$EN;
// register rg_mtip
reg rg_mtip;
wire rg_mtip$D_IN, rg_mtip$EN;
// register rg_state
reg rg_state;
wire rg_state$D_IN, rg_state$EN;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule f_sw_interrupt_req
wire f_sw_interrupt_req$CLR,
f_sw_interrupt_req$DEQ,
f_sw_interrupt_req$D_IN,
f_sw_interrupt_req$D_OUT,
f_sw_interrupt_req$EMPTY_N,
f_sw_interrupt_req$ENQ,
f_sw_interrupt_req$FULL_N;
// ports of submodule f_timer_interrupt_req
wire f_timer_interrupt_req$CLR,
f_timer_interrupt_req$DEQ,
f_timer_interrupt_req$D_IN,
f_timer_interrupt_req$D_OUT,
f_timer_interrupt_req$EMPTY_N,
f_timer_interrupt_req$ENQ,
f_timer_interrupt_req$FULL_N;
// ports of submodule slave_xactor_f_rd_addr
wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT;
wire slave_xactor_f_rd_addr$CLR,
slave_xactor_f_rd_addr$DEQ,
slave_xactor_f_rd_addr$EMPTY_N,
slave_xactor_f_rd_addr$ENQ,
slave_xactor_f_rd_addr$FULL_N;
// ports of submodule slave_xactor_f_rd_data
wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT;
wire slave_xactor_f_rd_data$CLR,
slave_xactor_f_rd_data$DEQ,
slave_xactor_f_rd_data$EMPTY_N,
slave_xactor_f_rd_data$ENQ,
slave_xactor_f_rd_data$FULL_N;
// ports of submodule slave_xactor_f_wr_addr
wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT;
wire slave_xactor_f_wr_addr$CLR,
slave_xactor_f_wr_addr$DEQ,
slave_xactor_f_wr_addr$EMPTY_N,
slave_xactor_f_wr_addr$ENQ,
slave_xactor_f_wr_addr$FULL_N;
// ports of submodule slave_xactor_f_wr_data
wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT;
wire slave_xactor_f_wr_data$CLR,
slave_xactor_f_wr_data$DEQ,
slave_xactor_f_wr_data$EMPTY_N,
slave_xactor_f_wr_data$ENQ,
slave_xactor_f_wr_data$FULL_N;
// ports of submodule slave_xactor_f_wr_resp
wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT;
wire slave_xactor_f_wr_resp$CLR,
slave_xactor_f_wr_resp$DEQ,
slave_xactor_f_wr_resp$EMPTY_N,
slave_xactor_f_wr_resp$ENQ,
slave_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_compare,
CAN_FIRE_RL_rl_process_rd_req,
CAN_FIRE_RL_rl_process_wr_req,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_soft_reset,
CAN_FIRE_RL_rl_tick_timer,
CAN_FIRE_axi4_slave_m_arvalid,
CAN_FIRE_axi4_slave_m_awvalid,
CAN_FIRE_axi4_slave_m_bready,
CAN_FIRE_axi4_slave_m_rready,
CAN_FIRE_axi4_slave_m_wvalid,
CAN_FIRE_get_sw_interrupt_req_get,
CAN_FIRE_get_timer_interrupt_req_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_addr_map,
WILL_FIRE_RL_rl_compare,
WILL_FIRE_RL_rl_process_rd_req,
WILL_FIRE_RL_rl_process_wr_req,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_soft_reset,
WILL_FIRE_RL_rl_tick_timer,
WILL_FIRE_axi4_slave_m_arvalid,
WILL_FIRE_axi4_slave_m_awvalid,
WILL_FIRE_axi4_slave_m_bready,
WILL_FIRE_axi4_slave_m_rready,
WILL_FIRE_axi4_slave_m_wvalid,
WILL_FIRE_get_sw_interrupt_req_get,
WILL_FIRE_get_timer_interrupt_req_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_addr_map;
// inputs to muxes for submodule ports
wire MUX_crg_time$port1__write_1__SEL_1,
MUX_crg_timecmp$port1__write_1__SEL_1,
MUX_rg_msip$write_1__SEL_1,
MUX_rg_state$write_1__SEL_1,
MUX_rg_state$write_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h10023;
reg [31 : 0] v__h10145;
reg [31 : 0] v__h1782;
reg [31 : 0] v__h2189;
reg [31 : 0] v__h2371;
reg [31 : 0] v__h2576;
reg [31 : 0] v__h2806;
reg [31 : 0] v__h2021;
reg [31 : 0] v__h3092;
reg [31 : 0] v__h3325;
reg [31 : 0] v__h8872;
reg [31 : 0] v__h9092;
reg [31 : 0] v__h9431;
reg [31 : 0] v__h9537;
reg [31 : 0] v__h9658;
reg [31 : 0] v__h1776;
reg [31 : 0] v__h2015;
reg [31 : 0] v__h2183;
reg [31 : 0] v__h2365;
reg [31 : 0] v__h2570;
reg [31 : 0] v__h2800;
reg [31 : 0] v__h3086;
reg [31 : 0] v__h3319;
reg [31 : 0] v__h8866;
reg [31 : 0] v__h9086;
reg [31 : 0] v__h9425;
reg [31 : 0] v__h9531;
reg [31 : 0] v__h9652;
reg [31 : 0] v__h10017;
reg [31 : 0] v__h10139;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] _theResult___fst__h2502;
reg [1 : 0] _theResult___snd__h2503, v__h3476;
wire [63 : 0] byte_addr__h2323,
byte_addr__h3287,
crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189,
mask__h3723,
new_time__h4999,
new_timecmp__h3698,
old_time__h7565,
rdata___1__h2498,
x__h2685,
x__h3734,
x__h5035,
y__h3735,
y__h3736;
wire [7 : 0] SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176,
SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173,
SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169,
SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166,
SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162,
SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159,
SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155,
SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152;
wire [1 : 0] rresp__h2484, v__h3291;
wire NOT_cfg_verbosity_read_ULE_1_0___d31,
NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24,
rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108,
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53,
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102,
slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method set_addr_map
assign RDY_set_addr_map = 1'd1 ;
assign CAN_FIRE_set_addr_map = 1'd1 ;
assign WILL_FIRE_set_addr_map = EN_set_addr_map ;
// action method axi4_slave_m_awvalid
assign CAN_FIRE_axi4_slave_m_awvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_awvalid = 1'd1 ;
// value method axi4_slave_m_awready
assign axi4_slave_awready = slave_xactor_f_wr_addr$FULL_N ;
// action method axi4_slave_m_wvalid
assign CAN_FIRE_axi4_slave_m_wvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_wvalid = 1'd1 ;
// value method axi4_slave_m_wready
assign axi4_slave_wready = slave_xactor_f_wr_data$FULL_N ;
// value method axi4_slave_m_bvalid
assign axi4_slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ;
// value method axi4_slave_m_bid
assign axi4_slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ;
// value method axi4_slave_m_bresp
assign axi4_slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ;
// action method axi4_slave_m_bready
assign CAN_FIRE_axi4_slave_m_bready = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_bready = 1'd1 ;
// action method axi4_slave_m_arvalid
assign CAN_FIRE_axi4_slave_m_arvalid = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_arvalid = 1'd1 ;
// value method axi4_slave_m_arready
assign axi4_slave_arready = slave_xactor_f_rd_addr$FULL_N ;
// value method axi4_slave_m_rvalid
assign axi4_slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ;
// value method axi4_slave_m_rid
assign axi4_slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ;
// value method axi4_slave_m_rdata
assign axi4_slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ;
// value method axi4_slave_m_rresp
assign axi4_slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ;
// value method axi4_slave_m_rlast
assign axi4_slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ;
// action method axi4_slave_m_rready
assign CAN_FIRE_axi4_slave_m_rready = 1'd1 ;
assign WILL_FIRE_axi4_slave_m_rready = 1'd1 ;
// actionvalue method get_timer_interrupt_req_get
assign get_timer_interrupt_req_get = f_timer_interrupt_req$D_OUT ;
assign RDY_get_timer_interrupt_req_get = f_timer_interrupt_req$EMPTY_N ;
assign CAN_FIRE_get_timer_interrupt_req_get =
f_timer_interrupt_req$EMPTY_N ;
assign WILL_FIRE_get_timer_interrupt_req_get =
EN_get_timer_interrupt_req_get ;
// actionvalue method get_sw_interrupt_req_get
assign get_sw_interrupt_req_get = f_sw_interrupt_req$D_OUT ;
assign RDY_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ;
assign CAN_FIRE_get_sw_interrupt_req_get = f_sw_interrupt_req$EMPTY_N ;
assign WILL_FIRE_get_sw_interrupt_req_get = EN_get_sw_interrupt_req_get ;
// submodule f_reset_reqs
FIFO20 #(.guarded(1'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule f_sw_interrupt_req
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_sw_interrupt_req(.RST(RST_N),
.CLK(CLK),
.D_IN(f_sw_interrupt_req$D_IN),
.ENQ(f_sw_interrupt_req$ENQ),
.DEQ(f_sw_interrupt_req$DEQ),
.CLR(f_sw_interrupt_req$CLR),
.D_OUT(f_sw_interrupt_req$D_OUT),
.FULL_N(f_sw_interrupt_req$FULL_N),
.EMPTY_N(f_sw_interrupt_req$EMPTY_N));
// submodule f_timer_interrupt_req
FIFO2 #(.width(32'd1), .guarded(1'd1)) f_timer_interrupt_req(.RST(RST_N),
.CLK(CLK),
.D_IN(f_timer_interrupt_req$D_IN),
.ENQ(f_timer_interrupt_req$ENQ),
.DEQ(f_timer_interrupt_req$DEQ),
.CLR(f_timer_interrupt_req$CLR),
.D_OUT(f_timer_interrupt_req$D_OUT),
.FULL_N(f_timer_interrupt_req$FULL_N),
.EMPTY_N(f_timer_interrupt_req$EMPTY_N));
// submodule slave_xactor_f_rd_addr
FIFO2 #(.width(32'd97), .guarded(1'd1)) slave_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_addr$D_IN),
.ENQ(slave_xactor_f_rd_addr$ENQ),
.DEQ(slave_xactor_f_rd_addr$DEQ),
.CLR(slave_xactor_f_rd_addr$CLR),
.D_OUT(slave_xactor_f_rd_addr$D_OUT),
.FULL_N(slave_xactor_f_rd_addr$FULL_N),
.EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N));
// submodule slave_xactor_f_rd_data
FIFO2 #(.width(32'd71), .guarded(1'd1)) slave_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_data$D_IN),
.ENQ(slave_xactor_f_rd_data$ENQ),
.DEQ(slave_xactor_f_rd_data$DEQ),
.CLR(slave_xactor_f_rd_data$CLR),
.D_OUT(slave_xactor_f_rd_data$D_OUT),
.FULL_N(slave_xactor_f_rd_data$FULL_N),
.EMPTY_N(slave_xactor_f_rd_data$EMPTY_N));
// submodule slave_xactor_f_wr_addr
FIFO2 #(.width(32'd97), .guarded(1'd1)) slave_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_addr$D_IN),
.ENQ(slave_xactor_f_wr_addr$ENQ),
.DEQ(slave_xactor_f_wr_addr$DEQ),
.CLR(slave_xactor_f_wr_addr$CLR),
.D_OUT(slave_xactor_f_wr_addr$D_OUT),
.FULL_N(slave_xactor_f_wr_addr$FULL_N),
.EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N));
// submodule slave_xactor_f_wr_data
FIFO2 #(.width(32'd73), .guarded(1'd1)) slave_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_data$D_IN),
.ENQ(slave_xactor_f_wr_data$ENQ),
.DEQ(slave_xactor_f_wr_data$DEQ),
.CLR(slave_xactor_f_wr_data$CLR),
.D_OUT(slave_xactor_f_wr_data$D_OUT),
.FULL_N(slave_xactor_f_wr_data$FULL_N),
.EMPTY_N(slave_xactor_f_wr_data$EMPTY_N));
// submodule slave_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(1'd1)) slave_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_resp$D_IN),
.ENQ(slave_xactor_f_wr_resp$ENQ),
.DEQ(slave_xactor_f_wr_resp$DEQ),
.CLR(slave_xactor_f_wr_resp$CLR),
.D_OUT(slave_xactor_f_wr_resp$D_OUT),
.FULL_N(slave_xactor_f_wr_resp$FULL_N),
.EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ;
assign WILL_FIRE_RL_rl_reset = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_soft_reset
assign CAN_FIRE_RL_rl_soft_reset = f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_soft_reset = MUX_rg_state$write_1__SEL_1 ;
// rule RL_rl_process_rd_req
assign CAN_FIRE_RL_rl_process_rd_req =
slave_xactor_f_rd_addr$EMPTY_N &&
slave_xactor_f_rd_data$FULL_N &&
rg_state &&
!f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ;
// rule RL_rl_compare
assign CAN_FIRE_RL_rl_compare =
f_timer_interrupt_req$FULL_N && rg_state &&
rg_mtip !=
NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 &&
!f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_compare = CAN_FIRE_RL_rl_compare ;
// rule RL_rl_tick_timer
assign CAN_FIRE_RL_rl_tick_timer =
rg_state && crg_time != 64'hFFFFFFFFFFFFFFFF &&
!f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_tick_timer = CAN_FIRE_RL_rl_tick_timer ;
// rule RL_rl_process_wr_req
assign CAN_FIRE_RL_rl_process_wr_req =
slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 &&
rg_state &&
!f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_process_wr_req =
CAN_FIRE_RL_rl_process_wr_req && !WILL_FIRE_RL_rl_compare ;
// inputs to muxes for submodule ports
assign MUX_crg_time$port1__write_1__SEL_1 =
WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
(byte_addr__h3287 == 64'h000000000000BFF8 ||
byte_addr__h3287 == 64'h000000000000BFFC) ;
assign MUX_crg_timecmp$port1__write_1__SEL_1 =
WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
(byte_addr__h3287 == 64'h0000000000004000 ||
byte_addr__h3287 == 64'h0000000000004004) ;
assign MUX_rg_msip$write_1__SEL_1 =
WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0 &&
!rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ;
assign MUX_rg_state$write_1__SEL_1 =
f_reset_reqs$EMPTY_N && !WILL_FIRE_RL_rl_reset ;
assign MUX_rg_state$write_1__SEL_2 =
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && !rg_state ;
// inlined wires
assign crg_time$port0__write_1 = crg_time + 64'd1 ;
assign crg_time$EN_port1__write =
WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
(byte_addr__h3287 == 64'h000000000000BFF8 ||
byte_addr__h3287 == 64'h000000000000BFFC) ||
WILL_FIRE_RL_rl_reset ;
assign crg_time$port1__write_1 =
MUX_crg_time$port1__write_1__SEL_1 ? new_time__h4999 : 64'd1 ;
assign crg_time$port2__read =
crg_time$EN_port1__write ?
crg_time$port1__write_1 :
old_time__h7565 ;
assign crg_timecmp$EN_port1__write =
WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
(byte_addr__h3287 == 64'h0000000000004000 ||
byte_addr__h3287 == 64'h0000000000004004) ||
WILL_FIRE_RL_rl_reset ;
assign crg_timecmp$port1__write_1 =
MUX_crg_timecmp$port1__write_1__SEL_1 ?
new_timecmp__h3698 :
64'd0 ;
assign crg_timecmp$port2__read =
crg_timecmp$EN_port1__write ?
crg_timecmp$port1__write_1 :
crg_timecmp ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 4'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register crg_time
assign crg_time$D_IN = crg_time$port2__read ;
assign crg_time$EN = 1'b1 ;
// register crg_timecmp
assign crg_timecmp$D_IN = crg_timecmp$port2__read ;
assign crg_timecmp$EN = 1'b1 ;
// register rg_addr_base
assign rg_addr_base$D_IN = set_addr_map_addr_base ;
assign rg_addr_base$EN = EN_set_addr_map ;
// register rg_addr_lim
assign rg_addr_lim$D_IN = set_addr_map_addr_lim ;
assign rg_addr_lim$EN = EN_set_addr_map ;
// register rg_msip
assign rg_msip$D_IN =
MUX_rg_msip$write_1__SEL_1 && slave_xactor_f_wr_data$D_OUT[9] ;
assign rg_msip$EN =
WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0 &&
!rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ||
WILL_FIRE_RL_rl_reset ;
// register rg_mtip
assign rg_mtip$D_IN =
!WILL_FIRE_RL_rl_compare ||
NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ;
assign rg_mtip$EN = WILL_FIRE_RL_rl_compare || WILL_FIRE_RL_rl_reset ;
// register rg_state
assign rg_state$D_IN = !WILL_FIRE_RL_rl_soft_reset ;
assign rg_state$EN = WILL_FIRE_RL_rl_soft_reset || WILL_FIRE_RL_rl_reset ;
// submodule f_reset_reqs
assign f_reset_reqs$ENQ = EN_server_reset_request_put ;
assign f_reset_reqs$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule f_sw_interrupt_req
assign f_sw_interrupt_req$D_IN = slave_xactor_f_wr_data$D_OUT[9] ;
assign f_sw_interrupt_req$ENQ = MUX_rg_msip$write_1__SEL_1 ;
assign f_sw_interrupt_req$DEQ = EN_get_sw_interrupt_req_get ;
assign f_sw_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ;
// submodule f_timer_interrupt_req
assign f_timer_interrupt_req$D_IN =
NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 ;
assign f_timer_interrupt_req$ENQ = CAN_FIRE_RL_rl_compare ;
assign f_timer_interrupt_req$DEQ = EN_get_timer_interrupt_req_get ;
assign f_timer_interrupt_req$CLR = MUX_rg_state$write_1__SEL_2 ;
// submodule slave_xactor_f_rd_addr
assign slave_xactor_f_rd_addr$D_IN =
{ axi4_slave_arid,
axi4_slave_araddr,
axi4_slave_arlen,
axi4_slave_arsize,
axi4_slave_arburst,
axi4_slave_arlock,
axi4_slave_arcache,
axi4_slave_arprot,
axi4_slave_arqos,
axi4_slave_arregion } ;
assign slave_xactor_f_rd_addr$ENQ =
axi4_slave_arvalid && slave_xactor_f_rd_addr$FULL_N ;
assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_2 ;
// submodule slave_xactor_f_rd_data
assign slave_xactor_f_rd_data$D_IN =
{ slave_xactor_f_rd_addr$D_OUT[96:93],
x__h2685,
rresp__h2484,
1'd1 } ;
assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_data$DEQ =
axi4_slave_rready && slave_xactor_f_rd_data$EMPTY_N ;
assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_2 ;
// submodule slave_xactor_f_wr_addr
assign slave_xactor_f_wr_addr$D_IN =
{ axi4_slave_awid,
axi4_slave_awaddr,
axi4_slave_awlen,
axi4_slave_awsize,
axi4_slave_awburst,
axi4_slave_awlock,
axi4_slave_awcache,
axi4_slave_awprot,
axi4_slave_awqos,
axi4_slave_awregion } ;
assign slave_xactor_f_wr_addr$ENQ =
axi4_slave_awvalid && slave_xactor_f_wr_addr$FULL_N ;
assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_2 ;
// submodule slave_xactor_f_wr_data
assign slave_xactor_f_wr_data$D_IN =
{ axi4_slave_wdata, axi4_slave_wstrb, axi4_slave_wlast } ;
assign slave_xactor_f_wr_data$ENQ =
axi4_slave_wvalid && slave_xactor_f_wr_data$FULL_N ;
assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_2 ;
// submodule slave_xactor_f_wr_resp
assign slave_xactor_f_wr_resp$D_IN =
{ slave_xactor_f_wr_addr$D_OUT[96:93], v__h3291 } ;
assign slave_xactor_f_wr_resp$ENQ = WILL_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_resp$DEQ =
axi4_slave_bready && slave_xactor_f_wr_resp$EMPTY_N ;
assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_2 ;
// remaining internal signals
assign NOT_cfg_verbosity_read_ULE_1_0___d31 = cfg_verbosity > 4'd1 ;
assign NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24 =
crg_time >= crg_timecmp ;
assign SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 =
{8{slave_xactor_f_wr_data$D_OUT[1]}} ;
assign SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173 =
{8{slave_xactor_f_wr_data$D_OUT[2]}} ;
assign SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169 =
{8{slave_xactor_f_wr_data$D_OUT[3]}} ;
assign SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166 =
{8{slave_xactor_f_wr_data$D_OUT[4]}} ;
assign SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162 =
{8{slave_xactor_f_wr_data$D_OUT[5]}} ;
assign SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159 =
{8{slave_xactor_f_wr_data$D_OUT[6]}} ;
assign SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155 =
{8{slave_xactor_f_wr_data$D_OUT[7]}} ;
assign SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152 =
{8{slave_xactor_f_wr_data$D_OUT[8]}} ;
assign byte_addr__h2323 =
slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ;
assign byte_addr__h3287 =
slave_xactor_f_wr_addr$D_OUT[92:29] - rg_addr_base ;
assign crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189 =
new_timecmp__h3698 - old_time__h7565 ;
assign mask__h3723 =
{ SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152,
SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155,
SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159,
SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162,
SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166,
SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169,
SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173,
SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 } ;
assign new_time__h4999 = x__h5035 | y__h3735 ;
assign new_timecmp__h3698 = x__h3734 | y__h3735 ;
assign old_time__h7565 =
CAN_FIRE_RL_rl_tick_timer ? crg_time$port0__write_1 : crg_time ;
assign rdata___1__h2498 = { 63'd0, rg_msip } ;
assign rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 =
rg_msip == slave_xactor_f_wr_data$D_OUT[9] ;
assign rresp__h2484 =
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ?
2'b11 :
_theResult___snd__h2503 ;
assign slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 =
slave_xactor_f_rd_addr$D_OUT[92:29] < rg_addr_base ;
assign slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 =
slave_xactor_f_wr_addr$D_OUT[92:29] < rg_addr_base ;
assign slave_xactor_f_wr_addr_i_notEmpty__7_AND_slave_ETC___d115 =
slave_xactor_f_wr_addr$EMPTY_N &&
slave_xactor_f_wr_data$EMPTY_N &&
slave_xactor_f_wr_resp$FULL_N &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 ||
rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 ||
f_sw_interrupt_req$FULL_N) ;
assign v__h3291 =
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ?
2'b11 :
v__h3476 ;
assign x__h2685 =
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ?
64'd0 :
_theResult___fst__h2502 ;
assign x__h3734 = crg_timecmp & y__h3736 ;
assign x__h5035 = old_time__h7565 & y__h3736 ;
assign y__h3735 = slave_xactor_f_wr_data$D_OUT[72:9] & mask__h3723 ;
assign y__h3736 =
{ ~SEXT_slave_xactor_f_wr_data_first__06_BIT_8_51___d152,
~SEXT_slave_xactor_f_wr_data_first__06_BIT_7_54___d155,
~SEXT_slave_xactor_f_wr_data_first__06_BIT_6_58___d159,
~SEXT_slave_xactor_f_wr_data_first__06_BIT_5_61___d162,
~SEXT_slave_xactor_f_wr_data_first__06_BIT_4_65___d166,
~SEXT_slave_xactor_f_wr_data_first__06_BIT_3_68___d169,
~SEXT_slave_xactor_f_wr_data_first__06_BIT_2_72___d173,
~SEXT_slave_xactor_f_wr_data_first__06_BIT_1_75___d176 } ;
always@(byte_addr__h2323)
begin
case (byte_addr__h2323)
64'h0,
64'h0000000000000004,
64'h0000000000004000,
64'h0000000000004004,
64'h000000000000BFF8,
64'h000000000000BFFC:
_theResult___snd__h2503 = 2'b0;
default: _theResult___snd__h2503 = 2'b11;
endcase
end
always@(byte_addr__h2323 or rdata___1__h2498 or crg_timecmp or crg_time)
begin
case (byte_addr__h2323)
64'h0: _theResult___fst__h2502 = rdata___1__h2498;
64'h0000000000000004: _theResult___fst__h2502 = 64'd0;
64'h0000000000004000, 64'h0000000000004004:
_theResult___fst__h2502 = crg_timecmp;
64'h000000000000BFF8, 64'h000000000000BFFC:
_theResult___fst__h2502 = crg_time;
default: _theResult___fst__h2502 = 64'd0;
endcase
end
always@(byte_addr__h3287)
begin
case (byte_addr__h3287)
64'h0,
64'h0000000000000004,
64'h0000000000004000,
64'h0000000000004004,
64'h000000000000BFF8,
64'h000000000000BFFC:
v__h3476 = 2'b0;
default: v__h3476 = 2'b11;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
crg_time <= `BSV_ASSIGNMENT_DELAY 64'd1;
crg_timecmp <= `BSV_ASSIGNMENT_DELAY 64'd0;
rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd1;
rg_state <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (crg_time$EN) crg_time <= `BSV_ASSIGNMENT_DELAY crg_time$D_IN;
if (crg_timecmp$EN)
crg_timecmp <= `BSV_ASSIGNMENT_DELAY crg_timecmp$D_IN;
if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (rg_addr_base$EN)
rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN;
if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN;
if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
crg_time = 64'hAAAAAAAAAAAAAAAA;
crg_timecmp = 64'hAAAAAAAAAAAAAAAA;
rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
rg_msip = 1'h0;
rg_mtip = 1'h0;
rg_state = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (EN_get_timer_interrupt_req_get &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
begin
v__h10023 = $stime;
#0;
end
v__h10017 = v__h10023 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_get_timer_interrupt_req_get &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display("%0d: Near_Mem_IO_AXI4: get_timer_interrupt_req: %x",
v__h10017,
f_timer_interrupt_req$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31)
begin
v__h10145 = $stime;
#0;
end
v__h10139 = v__h10145 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_get_sw_interrupt_req_get && NOT_cfg_verbosity_read_ULE_1_0___d31)
$display("%0d: Near_Mem_IO_AXI4: get_sw_interrupt_req: %x",
v__h10139,
f_sw_interrupt_req$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0)
begin
v__h1782 = $stime;
#0;
end
v__h1776 = v__h1782 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && cfg_verbosity != 4'd0)
$display("%0d: Near_Mem_IO_AXI4.rl_reset", v__h1776);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
begin
v__h2189 = $stime;
#0;
end
v__h2183 = v__h2189 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req: rg_mtip = %0d",
v__h2183,
rg_mtip);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
begin
v__h2371 = $stime;
#0;
end
v__h2365 = v__h2371 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr",
v__h2365);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
begin
v__h2576 = $stime;
#0;
end
v__h2570 = v__h2576 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_rd_req: unrecognized addr",
v__h2570);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
(slave_xactor_f_rd_addr_first__1_BITS_92_TO_29__ETC___d53 ||
byte_addr__h2323 != 64'h0 &&
byte_addr__h2323 != 64'h0000000000004000 &&
byte_addr__h2323 != 64'h000000000000BFF8 &&
byte_addr__h2323 != 64'h0000000000000004 &&
byte_addr__h2323 != 64'h0000000000004004 &&
byte_addr__h2323 != 64'h000000000000BFFC))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
begin
v__h2806 = $stime;
#0;
end
v__h2800 = v__h2806 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display("%0d: Near_Mem_IO_AXI4.rl_process_rd_req", v__h2800);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", x__h2685);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", rresp__h2484);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31)
begin
v__h2021 = $stime;
#0;
end
v__h2015 = v__h2021 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_compare && NOT_cfg_verbosity_read_ULE_1_0___d31)
$display("%0d: Near_Mem_IO_AXI4.rl_compare: new MTIP = %0d, time = %0d, timecmp = %0d",
v__h2015,
NOT_crg_time_port0__read__3_ULT_crg_timecmp_po_ETC___d24,
crg_time,
crg_timecmp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
begin
v__h3092 = $stime;
#0;
end
v__h3086 = v__h3092 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display("%0d: Near_Mem_IO_AXI4.rl_process_wr_req: rg_mtip = %0d",
v__h3086,
rg_mtip);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31 &&
slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31 &&
!slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
begin
v__h3325 = $stime;
#0;
end
v__h3319 = v__h3325 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr",
v__h3319);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
!slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0 &&
!rg_msip_7_EQ_slave_xactor_f_wr_data_first__06__ETC___d108 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" new MSIP = %0d", slave_xactor_f_wr_data$D_OUT[9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004000 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" Writing MTIMECMP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004000 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" old MTIMECMP = 0x%0h", crg_timecmp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004000 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" new MTIMECMP = 0x%0h", new_timecmp__h3698);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004000 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" cur MTIME = 0x%0h", old_time__h7565);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004000 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" new MTIMECMP - MTIME = 0x%0h",
crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h000000000000BFF8 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" Writing MTIME");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h000000000000BFF8 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" old MTIME = 0x%0h", old_time__h7565);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h000000000000BFF8 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" new MTIME = 0x%0h", new_time__h4999);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004004 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" Writing MTIMECMP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004004 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" old MTIMECMP = 0x%0h", crg_timecmp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004004 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" new MTIMECMP = 0x%0h", new_timecmp__h3698);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004004 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" cur MTIME = 0x%0h", old_time__h7565);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h0000000000004004 &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" new MTIMECMP - MTIME = 0x%0h",
crg_timecmp_port1__read__50_AND_INV_SEXT_slave_ETC___d189);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h000000000000BFFC &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" Writing MTIME");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h000000000000BFFC &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" old MTIME = 0x%0h", old_time__h7565);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
!slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 &&
byte_addr__h3287 == 64'h000000000000BFFC &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display(" new MTIME = 0x%0h", new_time__h4999);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
begin
v__h8872 = $stime;
#0;
end
v__h8866 = v__h8872 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$display("%0d: ERROR: Near_Mem_IO_AXI4.rl_process_wr_req: unrecognized addr",
v__h8866);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC) &&
slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC) &&
!slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
(slave_xactor_f_wr_addr_first__00_BITS_92_TO_29_ETC___d102 ||
byte_addr__h3287 != 64'h0 &&
byte_addr__h3287 != 64'h0000000000004000 &&
byte_addr__h3287 != 64'h000000000000BFF8 &&
byte_addr__h3287 != 64'h0000000000000004 &&
byte_addr__h3287 != 64'h0000000000004004 &&
byte_addr__h3287 != 64'h000000000000BFFC))
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
begin
v__h9092 = $stime;
#0;
end
v__h9086 = v__h9092 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$display("%0d: Near_Mem_IO.AXI4.rl_process_wr_req", v__h9086);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31 &&
slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31 &&
!slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", v__h3291);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_cfg_verbosity_read_ULE_1_0___d31)
$write("\n");
if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0)
begin
v__h9431 = $stime;
#0;
end
v__h9425 = v__h9431 / 32'd10;
if (EN_set_addr_map && set_addr_map_addr_base[1:0] != 2'd0)
$display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
v__h9425,
set_addr_map_addr_base);
if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0)
begin
v__h9537 = $stime;
#0;
end
v__h9531 = v__h9537 / 32'd10;
if (EN_set_addr_map && set_addr_map_addr_lim[1:0] != 2'd0)
$display("%0d: WARNING: Near_Mem_IO_AXI4.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
v__h9531,
set_addr_map_addr_lim);
if (EN_set_addr_map)
begin
v__h9658 = $stime;
#0;
end
v__h9652 = v__h9658 / 32'd10;
if (EN_set_addr_map)
$display("%0d: Near_Mem_IO_AXI4.set_addr_map: addr_base 0x%0h addr_lim 0x%0h",
v__h9652,
set_addr_map_addr_base,
set_addr_map_addr_lim);
end
// synopsys translate_on
endmodule // mkNear_Mem_IO_AXI4
|
module lcd(clk, lcd_rs, sf_d8, sf_d9, sf_d10, sf_d11, lcd_rw, lcd_e, sf_ce0);
parameter k = 15;
input clk;
output lcd_rs, sf_d8, sf_d9, sf_d10, sf_d11, lcd_rw, lcd_e, sf_ce0;
reg lcd_rs, sf_d8, sf_d9, sf_d10, sf_d11, lcd_rw, lcd_e, sf_ce0;
reg [k+8-1:0] count;
reg lcd_busy;
reg [5:0] lcd_char;
reg lcd_stb;
reg [6:0] lcd_intf_signals;
always @ (posedge clk)
begin
count <= count + 1;
lcd_busy <= 1'b1;
sf_ce0 <= 1; //-- disables Intel StrataFlash memory
case (count[k+7:k+2])
0: lcd_char <= 6'h03; //-- power-on initialization
1: lcd_char <= 6'h03;
2: lcd_char <= 6'h03; //-- power-on initialization continued
3: lcd_char <= 6'h02;
4: lcd_char <= 6'h02; //-- configures lcd for operation on Spartan 3E FPGA
5: lcd_char <= 6'h08;
6: lcd_char <= 6'h00; //-- sets lcd to automatically increment address pointer
7: lcd_char <= 6'h06;
8: lcd_char <= 6'h00; //-- turns lcd on and disables cursor and blinking
9: lcd_char <= 6'h0C;
10: lcd_char <= 6'h00; //-- clears lcd
11: lcd_char <= 6'h01;
12: lcd_char <= 6'h24; //-- H
13: lcd_char <= 6'h28;
14: lcd_char <= 6'h26; //-- e
15: lcd_char <= 6'h25;
16: lcd_char <= 6'h26; //-- l
17: lcd_char <= 6'h2C;
18: lcd_char <= 6'h26; //-- l
19: lcd_char <= 6'h2C;
20: lcd_char <= 6'h26; //-- o
21: lcd_char <= 6'h2F;
22: lcd_char <= 6'h22; //--
23: lcd_char <= 6'h20;
24: lcd_char <= 6'h25; //-- S
25: lcd_char <= 6'h23;
26: lcd_char <= 6'h26; //-- e
27: lcd_char <= 6'h25;
28: lcd_char <= 6'h26; //-- a
29: lcd_char <= 6'h21;
30: lcd_char <= 6'h26; //-- n
31: lcd_char <= 6'h2E;
32: lcd_char <= 6'h22; //-- !
33: lcd_char <= 6'h21;
default: lcd_char <= 6'h10;
endcase
lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy;
lcd_intf_signals <= {lcd_stb, lcd_char};
{lcd_rs, sf_d8, sf_d9, sf_d10, sf_d11, lcd_rw, lcd_e} <= lcd_intf_signals;
end
endmodule
/*
NETLIST
NET "lcd_e" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "lcd_rs" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "lcd_rw" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "sf_d8" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "sf_d9" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "sf_d10" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "sf_d11" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "sf_ce0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
*/
|
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