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1.05M
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`timescale 1ns/1ns
module usb_ctrl // usb control endpoint transfer
(input c, // bus clock
input rst,
output token_start,
output ack_start,
input tx_sie_done,
input [ 6:0] addr,
input [63:0] d,
output [18:0] token,
output [7:0] txd,
output txdv,
input [7:0] rxd,
input rxdv,
input start,
output done);
localparam ST_IDLE = 4'h0;
localparam ST_TX_SETUP = 4'h1;
localparam ST_TX_SETUP_WAIT = 4'h2;
localparam ST_TX_DATA_PID = 4'h3;
localparam ST_TX_DATA = 4'h4;
localparam ST_TX_DATA_WAIT = 4'h5;
localparam ST_TX_DATA_ACK_WAIT = 4'h6;
localparam ST_TX_IN = 4'h7;
localparam ST_TX_IN_WAIT = 4'h8;
localparam ST_RX_PID = 4'h9;
localparam ST_RX_DATA = 4'ha;
localparam ST_RX_NAK = 4'hb;
localparam ST_TX_ACK = 4'hc;
localparam ST_TX_ACK_WAIT = 4'hd;
localparam ST_SUCCESS = 4'he;
localparam ST_ERROR = 4'hf;
`include "usb_pids.v"
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(rst), .en(1'b1), .d(next_state), .q(state));
wire [18:0] token_setup = { 4'b0, addr, PID_SETUP };
wire [18:0] token_in = { 4'b0, addr, PID_IN };
wire [1:0] token_sel;
gmux #(.DWIDTH(19), .SELWIDTH(2)) token_gmux
(.d({19'hx, 19'hx, token_in, token_setup }),
.sel(token_sel), .z(token));
wire [2:0] cnt;
r #(3) cnt_r
(.c(c), .rst(state == ST_TX_DATA_PID), .en(1'b1), .d(cnt + 1'b1), .q(cnt));
localparam NAK_TIMEOUT = 11'h3ff; // this seems to be what linux does
wire nak_timer_rst;
wire [10:0] nak_timer;
r #(11) nak_timer_r
(.c(c), .rst(nak_timer_rst), .en(1'b1), .d(nak_timer+1'b1), .q(nak_timer));
always @* begin
case (state)
ST_IDLE:
if (start) ctrl = { ST_TX_SETUP , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_TX_SETUP: ctrl = { ST_TX_SETUP_WAIT , 5'b00000 };
ST_TX_SETUP_WAIT:
if (tx_sie_done) ctrl = { ST_TX_DATA_PID , 5'b00000 };
else ctrl = { ST_TX_SETUP_WAIT , 5'b00000 };
ST_TX_DATA_PID: ctrl = { ST_TX_DATA , 5'b00001 };
ST_TX_DATA:
if (cnt == 3'd7) ctrl = { ST_TX_DATA_WAIT , 5'b00001 };
else ctrl = { ST_TX_DATA , 5'b00001 };
ST_TX_DATA_WAIT:
if (tx_sie_done) ctrl = { ST_TX_DATA_ACK_WAIT , 5'b00000 };
else ctrl = { ST_TX_DATA_WAIT , 5'b00000 };
ST_TX_DATA_ACK_WAIT: // TODO: timeout
if (rxdv & rxd == PID_ACK) ctrl = { ST_TX_IN , 5'b00000 };
else ctrl = { ST_TX_DATA_ACK_WAIT , 5'b00000 };
ST_TX_IN: ctrl = { ST_TX_IN_WAIT , 5'b00010 };
ST_TX_IN_WAIT:
if (tx_sie_done) ctrl = { ST_RX_PID , 5'b00010 };
else ctrl = { ST_TX_IN_WAIT , 5'b00010 };
ST_RX_PID: // TODO: timeout
if (rxdv)
if (rxd == PID_DATA1) ctrl = { ST_RX_DATA , 5'b00000 };
else if (rxd == PID_NAK) ctrl = { ST_RX_NAK , 5'b01000 };
else ctrl = { ST_ERROR , 5'b00000 };
else ctrl = { ST_RX_PID , 5'b00000 };
ST_RX_NAK:
if (nak_timer == NAK_TIMEOUT) ctrl = { ST_TX_IN , 5'b00000 };
else ctrl = { ST_RX_NAK , 5'b00000 };
ST_RX_DATA:
if (~rxdv) ctrl = { ST_TX_ACK , 5'b00000 };
else ctrl = { ST_RX_DATA , 5'b00000 };
ST_TX_ACK: ctrl = { ST_TX_ACK_WAIT , 5'b00000 };
ST_TX_ACK_WAIT:
if (tx_sie_done) ctrl = { ST_SUCCESS , 5'b00000 };
else ctrl = { ST_TX_ACK_WAIT , 5'b00000 };
ST_SUCCESS: ctrl = { ST_IDLE , 5'b00000 };
ST_ERROR: ctrl = { ST_IDLE , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign token_start = state == ST_TX_SETUP |
state == ST_TX_IN ;
assign ack_start = state == ST_TX_ACK;
assign token_sel = ctrl[2:1];
assign nak_timer_rst = ctrl[3];
assign done = state == ST_ERROR | state == ST_SUCCESS; // todo: distinguish...
wire [63:0] shift;
r #(64) shift_r
(.c(c), .rst(1'b0), .en(state == ST_IDLE | state == ST_TX_DATA),
.d(state == ST_IDLE ? d : { 8'h0, shift[63:8] }), .q(shift));
assign txdv = ctrl[0];
assign txd = state == ST_TX_DATA_PID ? PID_DATA0 : shift[7:0];
endmodule
|
module testbench(input CLOCK_50, input [1:0] KEY, output [7:0] LED);
reg ready;
reg req;
reg running;
reg [7:0] reqCount;
reg [24:0] timer;
dfd_5 dfdUT(CLOCK_50, running, done,
1, result);
initial running = 0;
assign LED = 8'd0;
assign done = 1;
always @(posedge CLOCK_50) begin
if(running) begin
if(reqCount < 8'd10) begin
reqCount <= reqCount + 8'd1;
end else begin
reqCount <= 8'd0;
req <= ~req;
end
end else begin
req <= 1'b0;
reqCount <= 8'd0;
end
timer <= timer + 25'd1;
if(timer == 25'd0)
running <= ~running;
if(timer == 25'd0 && ~running)
req <= 1'b1;
end
endmodule
module list_testbench(input CLOCK_50, input [1:0] KEY, output [7:0] LED);
reg ready;
reg req;
reg running;
reg [7:0] reqCount;
reg [24:0] timer;
dfd_0 dfdUT(CLOCK_50, running, done,
1,
req, ack,
value_0, value_1, value_2,
value_0_valid, value_1_valid, value_2_valid);
initial running = 0;
assign LED = 8'd0;
assign done = 1;
always @(posedge CLOCK_50) begin
if(running) begin
if(ack & value_2_valid) begin
req <= 1'b0;
reqCount <= 8'd0;
end else begin
if(reqCount < 10) begin
reqCount <= reqCount + 8'd1;
end else begin
reqCount <= 8'd0;
req <= ~req;
end
end
end else begin
req <= 1'b0;
reqCount <= 8'd0;
end
timer <= timer + 25'd1;
if(timer == 25'd0)
running <= ~running;
if(timer == 25'd0 && ~running)
req <= 1'b1;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__NOR3_PP_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_PP_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:06:00 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_51 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13_50 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire enable_Pipeline_input, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5,
OP_FLAG_INIT, SIGN_FLAG_INIT, ZERO_FLAG_INIT, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, n_7_net_, left_right_SHT2,
bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, n_21_net_, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
N59, N60, ADD_OVRFLW_SGF, inst_ShiftRegister_net3663114,
SFT2FRMT_STAGE_VARS_net3663024, FRMT_STAGE_DATAOUT_net3662952,
SGF_STAGE_DMP_net3663006, NRM_STAGE_Raw_mant_net3662988,
INPUT_STAGE_OPERANDY_net3662952, EXP_STAGE_DMP_net3663006,
SHT1_STAGE_DMP_net3663006, SHT2_STAGE_DMP_net3663006,
SHT2_SHIFT_DATA_net3662988, array_comparators_GTComparator_N0,
array_comparators_LTComparator_N0, n388, n389, n390,
DP_OP_15J181_122_6956_n18, DP_OP_15J181_122_6956_n17,
DP_OP_15J181_122_6956_n16, DP_OP_15J181_122_6956_n15,
DP_OP_15J181_122_6956_n14, DP_OP_15J181_122_6956_n8,
DP_OP_15J181_122_6956_n7, DP_OP_15J181_122_6956_n6,
DP_OP_15J181_122_6956_n5, DP_OP_15J181_122_6956_n4,
DP_OP_15J181_122_6956_n3, DP_OP_15J181_122_6956_n2,
DP_OP_15J181_122_6956_n1, intadd_429_CI, intadd_429_SUM_2_,
intadd_429_SUM_1_, intadd_429_SUM_0_, intadd_429_n3, intadd_429_n2,
intadd_429_n1, n393, n395, n396, n397, n398, n399, n400, n401, n402,
n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501,
n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534,
n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556,
n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611,
n612, n613, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [30:0] intDY_EWSW;
wire [30:0] DMP_INIT_EWSW;
wire [27:0] DmP_INIT_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [4:0] Shift_amount_EXP_EW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [4:0] LZD_raw_out_EWR;
wire [4:2] shft_value_mux_o_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [51:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [25:0] sftr_odat_SHT2_SWR;
wire [4:0] LZD_output_NRM2_EW;
wire [7:0] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [24:2] DmP_mant_SFG_SWR;
wire [25:1] Raw_mant_SGF;
wire [31:0] formatted_number_W;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_51 inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n390), .ENCLK(inst_ShiftRegister_net3663114), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13_50 SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[1]), .ENCLK(
SFT2FRMT_STAGE_VARS_net3663024), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_6 FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[0]), .ENCLK(
FRMT_STAGE_DATAOUT_net3662952), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_5 SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(n_21_net_), .ENCLK(SGF_STAGE_DMP_net3663006), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_1 NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[2]), .ENCLK(
NRM_STAGE_Raw_mant_net3662988), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_7 INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(enable_Pipeline_input), .ENCLK(
INPUT_STAGE_OPERANDY_net3662952), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_9 EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_6), .ENCLK(EXP_STAGE_DMP_net3663006),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_8 SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_5), .ENCLK(SHT1_STAGE_DMP_net3663006),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_7 SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(SHT2_STAGE_DMP_net3663006), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_4 SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(n_7_net_), .ENCLK(SHT2_SHIFT_DATA_net3662988), .TE(1'b0) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1067), .CK(
inst_ShiftRegister_net3663114), .RN(n1037), .Q(Shift_reg_FLAGS_7_6) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(Shift_reg_FLAGS_7_6), .CK(
inst_ShiftRegister_net3663114), .RN(n1036), .Q(Shift_reg_FLAGS_7_5) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
inst_ShiftRegister_net3663114), .RN(n1035), .Q(Shift_reg_FLAGS_7[3])
);
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(Shift_reg_FLAGS_7[3]), .CK(
inst_ShiftRegister_net3663114), .RN(n1034), .Q(Shift_reg_FLAGS_7[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(Shift_amount_EXP_EW[0]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1055), .Q(Shift_amount_SHT1_EWR[0])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(Shift_amount_EXP_EW[1]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1035), .Q(Shift_amount_SHT1_EWR[1])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(Shift_amount_EXP_EW[2]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1055), .Q(Shift_amount_SHT1_EWR[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(Shift_amount_EXP_EW[3]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1034), .Q(Shift_amount_SHT1_EWR[3])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(Shift_amount_EXP_EW[4]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1040), .Q(Shift_amount_SHT1_EWR[4])
);
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1044),
.Q(ready) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(formatted_number_W[23]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1049), .Q(final_result_ieee[23])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(formatted_number_W[24]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1062), .Q(final_result_ieee[24])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(formatted_number_W[25]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1050), .Q(final_result_ieee[25])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(formatted_number_W[26]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1049), .Q(final_result_ieee[26])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(formatted_number_W[27]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1062), .Q(final_result_ieee[27])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(formatted_number_W[28]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1050), .Q(final_result_ieee[28])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(formatted_number_W[29]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[29])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(formatted_number_W[30]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[30])
);
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(array_comparators_LTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(array_comparators_GTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(overflow_flag) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(Data_X[28]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDX_EWSW[28]), .QN(
n403) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(DmP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1038), .Q(DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(DmP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1054), .Q(DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(DmP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1052), .Q(DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(DmP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1046), .Q(DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(DmP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1038), .Q(DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(DmP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1054), .Q(DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(DmP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(DmP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(DmP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(DmP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(DmP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(DmP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(DmP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(DmP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(DmP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1039), .Q(DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(DmP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1035), .Q(DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(DmP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1055), .Q(DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(DmP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1034), .Q(DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(DmP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1040), .Q(DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(DmP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1044), .Q(DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(DmP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1037), .Q(DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(DmP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1036), .Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(DmP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1035), .Q(DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(DmP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(DmP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(DmP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(DmP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(DmP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(DmP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(DmP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(DmP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1041), .Q(DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(DmP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1050), .Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(DmP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(DmP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(DmP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(DmP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(DmP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(DmP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(DmP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1042), .Q(DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(DmP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(DmP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1053), .Q(DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(DmP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(DmP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1047), .Q(DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(DmP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(DmP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1043), .Q(DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(DmP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DmP_mant_SHT1_SW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(DmP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1053), .Q(DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(DmP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1044), .Q(DmP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(DmP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1037), .Q(DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(DmP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1036), .Q(DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(DmP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1035), .Q(DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(DMP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(DMP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1060), .Q(DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(DMP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(DMP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(DMP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(DMP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(DMP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(DMP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1060), .Q(DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(DMP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(DMP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(DMP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(DMP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(DMP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(DMP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(DMP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(DMP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(DMP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(DMP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(DMP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(DMP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(DMP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(DMP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(DMP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1035), .Q(DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(DMP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_EXP_EWSW[23]), .QN(n406)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(DMP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_EXP_EWSW[24]), .QN(n1006) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(DMP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_EXP_EWSW[25]), .QN(n1032) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(DMP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_EXP_EWSW[26]), .QN(n1031) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(DMP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(DMP_INIT_EWSW[28]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(DMP_INIT_EWSW[29]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(DMP_INIT_EWSW[30]), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1062), .Q(ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1056), .Q(OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3663006), .RN(n1049), .Q(SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(DMP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(DMP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(DMP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(DMP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(DMP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(DMP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(DMP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1057), .Q(DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(DMP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(DMP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(DMP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(DMP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(DMP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(DMP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1054), .Q(DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(DMP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(DMP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(DMP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(DMP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(DMP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(DMP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(DMP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(DMP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(DMP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(DMP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(DMP_EXP_EWSW[23]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(DMP_EXP_EWSW[24]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(DMP_EXP_EWSW[25]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(DMP_EXP_EWSW[26]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(DMP_EXP_EWSW[27]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(DMP_EXP_EWSW[28]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(DMP_EXP_EWSW[29]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(DMP_EXP_EWSW[30]), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(ZERO_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(OP_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3663006), .RN(n1048), .Q(SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT1_EWSW[0]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT1_EWSW[1]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT1_EWSW[2]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT1_EWSW[3]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT1_EWSW[4]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1045), .Q(DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT1_EWSW[5]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT1_EWSW[6]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1060), .Q(DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT1_EWSW[7]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT1_EWSW[8]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT1_EWSW[9]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT1_EWSW[10]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT1_EWSW[11]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1057), .Q(DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT1_EWSW[12]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT1_EWSW[13]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT1_EWSW[14]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT1_EWSW[15]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1058), .Q(DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT1_EWSW[16]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1057), .Q(DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT1_EWSW[17]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT1_EWSW[18]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT1_EWSW[19]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT1_EWSW[20]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT1_EWSW[21]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT1_EWSW[22]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT1_EWSW[23]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1054), .Q(DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT2_EWSW[23]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(DMP_SFG[23]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(DMP_exp_NRM_EW[0]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1059), .Q(DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT1_EWSW[24]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT2_EWSW[24]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(DMP_SFG[24]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1058), .Q(DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(DMP_exp_NRM_EW[1]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1063), .Q(DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT1_EWSW[25]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1054), .Q(DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT2_EWSW[25]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1052), .Q(DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(DMP_SFG[25]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1057), .Q(DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(DMP_exp_NRM_EW[2]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1051), .Q(DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT1_EWSW[26]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1043), .Q(DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT2_EWSW[26]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(DMP_SFG[26]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n438), .Q(DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(DMP_exp_NRM_EW[3]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n395), .Q(DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT1_EWSW[27]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT2_EWSW[27]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(DMP_SFG[27]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(DMP_exp_NRM_EW[4]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1057), .Q(DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT1_EWSW[28]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT2_EWSW[28]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(DMP_SFG[28]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1059), .Q(DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(DMP_exp_NRM_EW[5]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1058), .Q(DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT1_EWSW[29]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT2_EWSW[29]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(DMP_SFG[29]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1063), .Q(DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(DMP_exp_NRM_EW[6]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n395), .Q(DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT1_EWSW[30]), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT2_EWSW[30]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n437), .Q(DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(DMP_SFG[30]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1051), .Q(DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(DMP_exp_NRM_EW[7]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1058), .Q(DMP_exp_NRM2_EW[7]) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1059), .Q(ZERO_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1050), .Q(OP_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3663006), .RN(n1054), .Q(SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1056), .Q(ZERO_FLAG_SFG) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(LZD_raw_out_EWR[3]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1050), .Q(LZD_output_NRM2_EW[3])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(LZD_raw_out_EWR[0]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1050), .Q(LZD_output_NRM2_EW[0])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(LZD_raw_out_EWR[2]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1049), .Q(LZD_output_NRM2_EW[2])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(LZD_raw_out_EWR[1]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1062), .Q(LZD_output_NRM2_EW[1])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(LZD_raw_out_EWR[4]), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1062), .Q(LZD_output_NRM2_EW[4])
);
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1059), .Q(SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n1063), .Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1SHT2), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1058), .Q(zero_flag) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1051), .Q(SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .RN(n395), .Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(formatted_number_W[31]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n438), .Q(final_result_ieee[31])
);
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(Data_array_SWR[3]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1050), .Q(Data_array_SWR[29]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(Data_array_SWR[2]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1051), .Q(Data_array_SWR[28]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(Data_array_SWR[1]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1057), .Q(Data_array_SWR[27]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(Data_array_SWR[0]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n395), .Q(Data_array_SWR[26]) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1064), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n438), .Q(left_right_SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(formatted_number_W[8]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n437), .Q(final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(formatted_number_W[9]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1058), .Q(final_result_ieee[9])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(formatted_number_W[10]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1058), .Q(final_result_ieee[10])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(formatted_number_W[11]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1051), .Q(final_result_ieee[11])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(formatted_number_W[12]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1057), .Q(final_result_ieee[12])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(formatted_number_W[13]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n395), .Q(final_result_ieee[13])
);
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(sftr_odat_SHT2_SWR[1]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n438), .Q(N60) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(formatted_number_W[0]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1035), .Q(final_result_ieee[0])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(formatted_number_W[1]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1035), .Q(final_result_ieee[1])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(formatted_number_W[2]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n437), .Q(final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(formatted_number_W[3]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1057), .Q(final_result_ieee[3])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(formatted_number_W[4]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1063), .Q(final_result_ieee[4])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(formatted_number_W[5]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1058), .Q(final_result_ieee[5])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(formatted_number_W[6]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1051), .Q(final_result_ieee[6])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(formatted_number_W[7]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[7])
);
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(sftr_odat_SHT2_SWR[25]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .QN(n405) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(formatted_number_W[14]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[14])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(formatted_number_W[15]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[15])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(formatted_number_W[16]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[16])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(formatted_number_W[17]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[17])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(formatted_number_W[18]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1060), .Q(final_result_ieee[18])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(formatted_number_W[19]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[19])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(formatted_number_W[20]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[20])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(formatted_number_W[21]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[21])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(formatted_number_W[22]), .CK(
FRMT_STAGE_DATAOUT_net3662952), .RN(n1061), .Q(final_result_ieee[22])
);
CMPR32X2TS DP_OP_15J181_122_6956_U9 ( .A(DMP_exp_NRM2_EW[0]), .B(n920), .C(
DP_OP_15J181_122_6956_n18), .CO(DP_OP_15J181_122_6956_n8), .S(
exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_15J181_122_6956_U8 ( .A(DP_OP_15J181_122_6956_n17), .B(
DMP_exp_NRM2_EW[1]), .C(DP_OP_15J181_122_6956_n8), .CO(
DP_OP_15J181_122_6956_n7), .S(exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J181_122_6956_U7 ( .A(DP_OP_15J181_122_6956_n16), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J181_122_6956_n7), .CO(
DP_OP_15J181_122_6956_n6), .S(exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J181_122_6956_U6 ( .A(DP_OP_15J181_122_6956_n15), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J181_122_6956_n6), .CO(
DP_OP_15J181_122_6956_n5), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS intadd_429_U4 ( .A(DmP_EXP_EWSW[24]), .B(n1006), .C(intadd_429_CI), .CO(intadd_429_n3), .S(intadd_429_SUM_0_) );
CMPR32X2TS intadd_429_U3 ( .A(DmP_EXP_EWSW[25]), .B(n1032), .C(intadd_429_n3), .CO(intadd_429_n2), .S(intadd_429_SUM_1_) );
CMPR32X2TS intadd_429_U2 ( .A(DmP_EXP_EWSW[26]), .B(n1031), .C(intadd_429_n2), .CO(intadd_429_n1), .S(intadd_429_SUM_2_) );
DFFSX2TS R_0 ( .D(n1033), .CK(INPUT_STAGE_OPERANDY_net3662952), .SN(n1035),
.Q(n1066) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(N59), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1052), .Q(Raw_mant_NRM_SWR[0]),
.QN(n1030) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(Data_Y[0]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1046), .Q(intDY_EWSW[0]), .QN(
n1029) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(Data_Y[26]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDY_EWSW[26]), .QN(
n1028) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(Data_Y[15]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1056), .Q(intDY_EWSW[15]), .QN(
n1027) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(Data_Y[3]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1054), .Q(intDY_EWSW[3]), .QN(
n1026) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(Data_Y[1]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1038), .Q(intDY_EWSW[1]), .QN(
n1025) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(Data_Y[11]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDY_EWSW[11]), .QN(
n1024) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(Data_Y[25]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDY_EWSW[25]), .QN(
n1023) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(Data_Y[18]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1042), .Q(intDY_EWSW[18]), .QN(
n1022) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(Data_Y[17]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1042), .Q(intDY_EWSW[17]), .QN(
n1021) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(Data_Y[8]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDY_EWSW[8]), .QN(
n1020) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(Data_Y[12]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1041), .Q(intDY_EWSW[12]), .QN(
n1019) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(Data_Y[27]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDY_EWSW[27]), .QN(
n1018) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(Data_Y[9]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDY_EWSW[9]), .QN(
n1017) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(Data_Y[22]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1053), .Q(intDY_EWSW[22]), .QN(
n1016) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(Data_Y[20]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1043), .Q(intDY_EWSW[20]), .QN(
n1015) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(Data_Y[2]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1052), .Q(intDY_EWSW[2]), .QN(
n1014) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(Data_Y[21]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1047), .Q(intDY_EWSW[21]), .QN(
n1013) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(Data_Y[13]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1041), .Q(intDY_EWSW[13]), .QN(
n1012) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(Data_Y[24]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDY_EWSW[24]), .QN(
n1011) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(Data_Y[10]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDY_EWSW[10]), .QN(
n1010) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(Data_Y[4]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1039), .Q(intDY_EWSW[4]), .QN(
n1009) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(Data_Y[16]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1042), .Q(intDY_EWSW[16]), .QN(
n1008) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(Data_Y[6]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1039), .Q(intDY_EWSW[6]), .QN(
n1007) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(Data_Y[5]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1054), .Q(intDY_EWSW[5]), .QN(
n1005) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(Data_Y[7]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1054), .Q(intDY_EWSW[7]), .QN(
n1004) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(Raw_mant_SGF[5]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1050), .Q(Raw_mant_NRM_SWR[5]),
.QN(n1003) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n389), .CK(clk), .RN(
n1035), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1002) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT2_EWSW[22]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1054), .Q(DMP_SFG[22]), .QN(n1001) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(Data_array_SWR[21]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1037), .Q(Data_array_SWR[47]), .QN(
n1000) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(Data_array_SWR[20]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1035), .Q(Data_array_SWR[46]), .QN(
n999) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(Data_array_SWR[23]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1035), .Q(Data_array_SWR[49]), .QN(
n998) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(Data_array_SWR[22]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1036), .Q(Data_array_SWR[48]), .QN(
n997) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(sftr_odat_SHT2_SWR[23]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1061), .Q(DmP_mant_SFG_SWR[23]), .QN(
n996) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT2_EWSW[20]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SFG[20]), .QN(n995) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(Data_X[23]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDX_EWSW[23]), .QN(
n994) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(Data_X[7]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .QN(n993) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(Data_X[5]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .QN(n992) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(Data_X[16]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[16]), .QN(
n991) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(Data_X[30]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[30]), .QN(
n990) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(Data_X[29]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[29]), .QN(
n989) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(Data_X[21]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[21]), .QN(
n988) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(Data_X[13]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDX_EWSW[13]), .QN(
n987) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(Data_X[26]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDX_EWSW[26]), .QN(
n986) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(Data_X[19]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDX_EWSW[19]), .QN(
n985) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(Data_X[14]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDX_EWSW[14]), .QN(
n984) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(Data_X[12]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[12]), .QN(
n983) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(Data_X[11]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[11]), .QN(
n982) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(Data_X[25]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDX_EWSW[25]), .QN(
n981) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(Data_X[17]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDX_EWSW[17]), .QN(
n980) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(Data_X[10]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDX_EWSW[10]), .QN(
n979) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(Data_X[1]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[1]), .QN(
n978) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(shft_value_mux_o_EWR[2]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1057), .Q(shift_value_SHT2_EWR[2]),
.QN(n977) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(sftr_odat_SHT2_SWR[21]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1061), .Q(DmP_mant_SFG_SWR[21]), .QN(
n975) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT2_EWSW[18]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1059), .Q(DMP_SFG[18]), .QN(n974) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(Data_Y[29]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1037), .Q(intDY_EWSW[29]), .QN(
n973) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(sftr_odat_SHT2_SWR[19]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[19]), .QN(
n972) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT2_EWSW[16]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1051), .Q(DMP_SFG[16]), .QN(n971) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(Raw_mant_SGF[20]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1052), .Q(Raw_mant_NRM_SWR[20]),
.QN(n970) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(Raw_mant_SGF[12]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1054), .Q(Raw_mant_NRM_SWR[12]),
.QN(n969) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(Raw_mant_SGF[14]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1052), .Q(Raw_mant_NRM_SWR[14]),
.QN(n968) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(sftr_odat_SHT2_SWR[17]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[17]), .QN(
n967) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(Raw_mant_SGF[17]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1038), .Q(Raw_mant_NRM_SWR[17]),
.QN(n966) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(Raw_mant_SGF[25]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1059), .Q(Raw_mant_NRM_SWR[25]),
.QN(n965) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(Raw_mant_SGF[18]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1046), .Q(Raw_mant_NRM_SWR[18]),
.QN(n964) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(sftr_odat_SHT2_SWR[15]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DmP_mant_SFG_SWR[15]), .QN(
n963) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT2_EWSW[14]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1063), .Q(DMP_SFG[14]), .QN(n962) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(Raw_mant_SGF[1]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1043), .Q(Raw_mant_NRM_SWR[1]),
.QN(n961) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(Raw_mant_SGF[3]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1045), .Q(Raw_mant_NRM_SWR[3]),
.QN(n960) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT2_EWSW[12]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SFG[12]), .QN(n959) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(sftr_odat_SHT2_SWR[13]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1063), .Q(DmP_mant_SFG_SWR[13]), .QN(
n958) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT2_EWSW[10]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1049), .Q(DMP_SFG[10]), .QN(n957) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(Raw_mant_SGF[6]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1056), .Q(Raw_mant_NRM_SWR[6]),
.QN(n956) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT2_EWSW[8]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1053), .Q(DMP_SFG[8]), .QN(n955) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT2_EWSW[6]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DMP_SFG[6]), .QN(n954) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(sftr_odat_SHT2_SWR[11]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DmP_mant_SFG_SWR[11]), .QN(
n953) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT2_EWSW[4]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SFG[4]), .QN(n952) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT2_EWSW[2]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1050), .Q(DMP_SFG[2]), .QN(n951) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT2_EWSW[0]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SFG[0]), .QN(n950) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(sftr_odat_SHT2_SWR[9]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1057), .Q(DmP_mant_SFG_SWR[9]), .QN(
n949) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(sftr_odat_SHT2_SWR[7]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DmP_mant_SFG_SWR[7]), .QN(
n948) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(sftr_odat_SHT2_SWR[5]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1059), .Q(DmP_mant_SFG_SWR[5]), .QN(
n947) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT2_EWSW[1]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1048), .Q(DMP_SFG[1]), .QN(n946) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(Data_Y[14]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1041), .Q(intDY_EWSW[14]), .QN(
n945) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(Data_Y[19]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1042), .Q(intDY_EWSW[19]), .QN(
n944) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n388), .CK(clk), .RN(
n1055), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n943) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(Data_Y[23]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1053), .Q(intDY_EWSW[23]), .QN(
n942) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(Data_array_SWR[24]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1055), .Q(Data_array_SWR[50]), .QN(
n941) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(Data_array_SWR[25]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1034), .Q(Data_array_SWR[51]), .QN(
n940) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT2_EWSW[21]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1038), .Q(DMP_SFG[21]), .QN(n939) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(Data_X[0]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1055), .Q(intDX_EWSW[0]), .QN(
n938) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(Data_X[24]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDX_EWSW[24]), .QN(
n937) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(Data_X[6]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[6]), .QN(
n936) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(Data_X[4]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[4]), .QN(
n935) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(Data_X[2]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1040), .Q(intDX_EWSW[2]), .QN(
n934) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(Data_X[15]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDX_EWSW[15]), .QN(
n933) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(Data_X[3]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDX_EWSW[3]), .QN(
n932) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(Data_X[27]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[27]), .QN(
n931) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(Data_X[22]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[22]), .QN(
n930) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(Data_X[20]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[20]), .QN(
n929) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(Data_X[18]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1034), .Q(intDX_EWSW[18]), .QN(
n928) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(Data_Y[30]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDY_EWSW[30]), .QN(
n927) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT2_EWSW[19]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DMP_SFG[19]), .QN(n926) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT2_EWSW[17]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1057), .Q(DMP_SFG[17]), .QN(n925) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(Raw_mant_SGF[22]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(Raw_mant_NRM_SWR[22]),
.QN(n923) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT2_EWSW[15]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DMP_SFG[15]), .QN(n922) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT2_EWSW[13]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DMP_SFG[13]), .QN(n921) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT2_EWSW[11]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SFG[11]), .QN(n919) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT2_EWSW[9]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1056), .Q(DMP_SFG[9]), .QN(n918) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT2_EWSW[7]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1046), .Q(DMP_SFG[7]), .QN(n917) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT2_EWSW[5]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1062), .Q(DMP_SFG[5]), .QN(n916) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT2_EWSW[3]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1047), .Q(DMP_SFG[3]), .QN(n915) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(sftr_odat_SHT2_SWR[3]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n438), .Q(DmP_mant_SFG_SWR[3]), .QN(
n914) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n1067), .CK(clk), .RN(
n1035), .Q(inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n913) );
CMPR32X2TS DP_OP_15J181_122_6956_U5 ( .A(DP_OP_15J181_122_6956_n14), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J181_122_6956_n5), .CO(
DP_OP_15J181_122_6956_n4), .S(exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_15J181_122_6956_U4 ( .A(n920), .B(DMP_exp_NRM2_EW[5]), .C(
DP_OP_15J181_122_6956_n4), .CO(DP_OP_15J181_122_6956_n3), .S(
exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_15J181_122_6956_U3 ( .A(n920), .B(DMP_exp_NRM2_EW[6]), .C(
DP_OP_15J181_122_6956_n3), .CO(DP_OP_15J181_122_6956_n2), .S(
exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_15J181_122_6956_U2 ( .A(n920), .B(DMP_exp_NRM2_EW[7]), .C(
DP_OP_15J181_122_6956_n2), .CO(DP_OP_15J181_122_6956_n1), .S(
exp_rslt_NRM2_EW1[7]) );
DFFSX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n404), .CK(
SFT2FRMT_STAGE_VARS_net3663024), .SN(n1049), .Q(n920), .QN(
ADD_OVRFLW_NRM2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(Raw_mant_SGF[11]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1046), .Q(Raw_mant_NRM_SWR[11])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(Raw_mant_SGF[23]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1057), .Q(Raw_mant_NRM_SWR[23])
);
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(sftr_odat_SHT2_SWR[24]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1053), .Q(DmP_mant_SFG_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(Raw_mant_SGF[24]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1059), .Q(Raw_mant_NRM_SWR[24])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(Raw_mant_SGF[10]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1054), .Q(Raw_mant_NRM_SWR[10])
);
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(sftr_odat_SHT2_SWR[8]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DmP_mant_SFG_SWR[8]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(sftr_odat_SHT2_SWR[6]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(DmP_mant_SFG_SWR[6]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(sftr_odat_SHT2_SWR[4]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n438), .Q(DmP_mant_SFG_SWR[4]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(sftr_odat_SHT2_SWR[10]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1051), .Q(DmP_mant_SFG_SWR[10]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(sftr_odat_SHT2_SWR[22]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1061), .Q(DmP_mant_SFG_SWR[22]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(sftr_odat_SHT2_SWR[20]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[20]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(sftr_odat_SHT2_SWR[18]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[18]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(sftr_odat_SHT2_SWR[16]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1060), .Q(DmP_mant_SFG_SWR[16]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(sftr_odat_SHT2_SWR[14]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1051), .Q(DmP_mant_SFG_SWR[14]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(sftr_odat_SHT2_SWR[12]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DmP_mant_SFG_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(Raw_mant_SGF[21]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n395), .Q(Raw_mant_NRM_SWR[21]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(shft_value_mux_o_EWR[3]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1057), .Q(shift_value_SHT2_EWR[3])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(Raw_mant_SGF[16]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1054), .Q(Raw_mant_NRM_SWR[16])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(Data_Y[28]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1044), .Q(intDY_EWSW[28]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1048), .Q(n407), .QN(n1065) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(Data_array_SWR[16]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1040), .Q(Data_array_SWR[42]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(Data_array_SWR[17]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1044), .Q(Data_array_SWR[43]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(Raw_mant_SGF[7]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1056), .Q(Raw_mant_NRM_SWR[7]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(Raw_mant_SGF[19]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1046), .Q(Raw_mant_NRM_SWR[19])
);
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(sftr_odat_SHT2_SWR[2]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n1058), .Q(DmP_mant_SFG_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(Data_array_SWR[18]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1037), .Q(Data_array_SWR[44]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(Data_array_SWR[19]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1036), .Q(Data_array_SWR[45]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(Raw_mant_SGF[8]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1050), .Q(Raw_mant_NRM_SWR[8]) );
DFFRX1TS inst_ShiftRegister_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[1]), .CK(
inst_ShiftRegister_net3663114), .RN(n1040), .Q(Shift_reg_FLAGS_7[0])
);
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(Shift_reg_FLAGS_7_5), .CK(
inst_ShiftRegister_net3663114), .RN(n1044), .Q(busy) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(Data_array_SWR[9]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1053), .Q(Data_array_SWR[35]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(Data_array_SWR[8]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1058), .Q(Data_array_SWR[34]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(Data_array_SWR[10]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1062), .Q(Data_array_SWR[36]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(Data_array_SWR[11]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1045), .Q(Data_array_SWR[37]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(Data_X[8]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1036), .Q(intDX_EWSW[8]), .QN(
n396) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n401), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1035), .Q(bit_shift_SHT2) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(Data_X[9]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1035), .Q(intDX_EWSW[9]), .QN(
n397) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(sftr_odat_SHT2_SWR[0]), .CK(
SGF_STAGE_DMP_net3663006), .RN(n395), .Q(N59) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(Raw_mant_SGF[4]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1050), .Q(Raw_mant_NRM_SWR[4]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(Data_X[31]), .CK(
INPUT_STAGE_OPERANDY_net3662952), .RN(n1054), .Q(intDX_EWSW[31]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(Raw_mant_SGF[13]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1054), .Q(Raw_mant_NRM_SWR[13])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(Raw_mant_SGF[2]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1053), .Q(Raw_mant_NRM_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(Data_array_SWR[13]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1054), .Q(Data_array_SWR[39]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(Data_array_SWR[12]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1059), .Q(Data_array_SWR[38]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(Data_array_SWR[14]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1050), .Q(Data_array_SWR[40]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(Data_array_SWR[15]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1034), .Q(Data_array_SWR[41]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(Raw_mant_SGF[9]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1038), .Q(Raw_mant_NRM_SWR[9]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(Raw_mant_SGF[15]), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1052), .Q(Raw_mant_NRM_SWR[15])
);
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(shft_value_mux_o_EWR[4]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1063), .Q(shift_value_SHT2_EWR[4]),
.QN(n976) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(ADD_OVRFLW_SGF), .CK(
NRM_STAGE_Raw_mant_net3662988), .RN(n1057), .Q(ADD_OVRFLW_NRM), .QN(
n404) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(Data_array_SWR[6]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1043), .Q(Data_array_SWR[32]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(Data_array_SWR[7]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1057), .Q(Data_array_SWR[33]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(Data_array_SWR[5]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1049), .Q(Data_array_SWR[31]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(Data_array_SWR[4]), .CK(
SHT2_SHIFT_DATA_net3662988), .RN(n1056), .Q(Data_array_SWR[30]) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(Shift_reg_FLAGS_7[2]), .CK(
inst_ShiftRegister_net3663114), .RN(n1040), .Q(Shift_reg_FLAGS_7[1]),
.QN(n924) );
AOI32X4TS U582 ( .A0(n840), .A1(n839), .A2(n838), .B0(n837), .B1(n840), .Y(
n895) );
AOI211X2TS U583 ( .A0(Data_array_SWR[42]), .A1(n439), .B0(n485), .C0(n456),
.Y(n531) );
AOI211X2TS U584 ( .A0(Data_array_SWR[43]), .A1(n439), .B0(n485), .C0(n440),
.Y(n489) );
AOI222X4TS U585 ( .A0(DMP_SFG[18]), .A1(DmP_mant_SFG_SWR[20]), .B0(
DMP_SFG[18]), .B1(n701), .C0(DmP_mant_SFG_SWR[20]), .C1(n701), .Y(n879) );
AOI222X4TS U586 ( .A0(DMP_SFG[16]), .A1(DmP_mant_SFG_SWR[18]), .B0(
DMP_SFG[16]), .B1(n695), .C0(DmP_mant_SFG_SWR[18]), .C1(n695), .Y(n874) );
AOI222X2TS U587 ( .A0(DMP_SFG[12]), .A1(DmP_mant_SFG_SWR[14]), .B0(
DMP_SFG[12]), .B1(n683), .C0(DmP_mant_SFG_SWR[14]), .C1(n683), .Y(n864) );
AOI222X2TS U588 ( .A0(DMP_SFG[10]), .A1(DmP_mant_SFG_SWR[12]), .B0(
DMP_SFG[10]), .B1(n677), .C0(DmP_mant_SFG_SWR[12]), .C1(n677), .Y(n859) );
CLKINVX6TS U589 ( .A(n672), .Y(n583) );
INVX4TS U590 ( .A(n643), .Y(n592) );
NAND4XLTS U591 ( .A(n712), .B(n431), .C(n430), .D(n429), .Y(
LZD_raw_out_EWR[0]) );
NAND4XLTS U592 ( .A(n729), .B(n421), .C(n420), .D(n419), .Y(
LZD_raw_out_EWR[1]) );
NOR2X1TS U593 ( .A(array_comparators_LTComparator_N0), .B(
array_comparators_GTComparator_N0), .Y(n450) );
BUFX6TS U594 ( .A(n899), .Y(n393) );
NOR2X1TS U595 ( .A(Raw_mant_NRM_SWR[10]), .B(n723), .Y(n408) );
NAND2BX1TS U596 ( .AN(n723), .B(Raw_mant_NRM_SWR[10]), .Y(n718) );
NAND2X4TS U597 ( .A(n560), .B(n976), .Y(n441) );
NOR2X4TS U598 ( .A(n560), .B(n482), .Y(n452) );
NOR2X6TS U599 ( .A(shift_value_SHT2_EWR[4]), .B(n493), .Y(n444) );
NOR2X6TS U600 ( .A(shift_value_SHT2_EWR[4]), .B(n455), .Y(n443) );
NAND2X4TS U601 ( .A(n564), .B(n976), .Y(n451) );
CLKINVX3TS U602 ( .A(n505), .Y(n442) );
INVX3TS U603 ( .A(n890), .Y(n855) );
NOR2X4TS U604 ( .A(n564), .B(n482), .Y(n448) );
NOR2X6TS U605 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n439) );
BUFX6TS U606 ( .A(n437), .Y(n395) );
NAND2BXLTS U607 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n802) );
CLKAND2X2TS U608 ( .A(DmP_mant_SFG_SWR[4]), .B(n951), .Y(n525) );
CLKAND2X2TS U609 ( .A(DmP_mant_SFG_SWR[8]), .B(n954), .Y(n577) );
CLKAND2X2TS U610 ( .A(DmP_mant_SFG_SWR[10]), .B(n955), .Y(n587) );
AOI211X1TS U611 ( .A0(n443), .A1(Data_array_SWR[45]), .B0(n507), .C0(n499),
.Y(n512) );
CLKAND2X2TS U612 ( .A(DmP_mant_SFG_SWR[6]), .B(n952), .Y(n546) );
AOI211X1TS U613 ( .A0(Data_array_SWR[44]), .A1(n443), .B0(n507), .C0(n484),
.Y(n514) );
AOI222X4TS U614 ( .A0(n924), .A1(DmP_mant_SHT1_SW[0]), .B0(n611), .B1(
Raw_mant_NRM_SWR[23]), .C0(Raw_mant_NRM_SWR[2]), .C1(n401), .Y(n631)
);
AOI222X4TS U615 ( .A0(n924), .A1(DmP_mant_SHT1_SW[1]), .B0(n611), .B1(
Raw_mant_NRM_SWR[22]), .C0(Raw_mant_NRM_SWR[3]), .C1(n401), .Y(n627)
);
NAND2BXLTS U616 ( .AN(n713), .B(Raw_mant_NRM_SWR[4]), .Y(n722) );
NAND2BXLTS U617 ( .AN(Raw_mant_NRM_SWR[23]), .B(n923), .Y(n412) );
AO22XLTS U618 ( .A0(n1064), .A1(LZD_raw_out_EWR[4]), .B0(
Shift_amount_SHT1_EWR[4]), .B1(n912), .Y(shft_value_mux_o_EWR[4]) );
OAI21XLTS U619 ( .A0(n652), .A1(n399), .B0(n639), .Y(Data_array_SWR[19]) );
OAI21XLTS U620 ( .A0(n652), .A1(n904), .B0(n605), .Y(Data_array_SWR[18]) );
XOR2XLTS U621 ( .A(n878), .B(n877), .Y(Raw_mant_SGF[19]) );
OAI21XLTS U622 ( .A0(n651), .A1(n399), .B0(n624), .Y(Data_array_SWR[17]) );
OAI21XLTS U623 ( .A0(n656), .A1(n399), .B0(n655), .Y(Data_array_SWR[16]) );
OAI21XLTS U624 ( .A0(n686), .A1(n688), .B0(n685), .Y(n684) );
AO22XLTS U625 ( .A0(n1064), .A1(LZD_raw_out_EWR[3]), .B0(
Shift_amount_SHT1_EWR[3]), .B1(n912), .Y(shft_value_mux_o_EWR[3]) );
XOR2XLTS U626 ( .A(n883), .B(n882), .Y(Raw_mant_SGF[21]) );
XOR2XLTS U627 ( .A(n894), .B(n893), .Y(Raw_mant_SGF[24]) );
XOR2XLTS U628 ( .A(n888), .B(n887), .Y(Raw_mant_SGF[23]) );
OAI21XLTS U629 ( .A0(n704), .A1(n732), .B0(n703), .Y(n702) );
OAI21XLTS U630 ( .A0(n692), .A1(n694), .B0(n691), .Y(n690) );
XOR2XLTS U631 ( .A(n735), .B(n405), .Y(Raw_mant_SGF[25]) );
XOR2XLTS U632 ( .A(n873), .B(n872), .Y(Raw_mant_SGF[17]) );
OAI21XLTS U633 ( .A0(n698), .A1(n700), .B0(n697), .Y(n696) );
AO22XLTS U634 ( .A0(n1064), .A1(LZD_raw_out_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n912), .Y(shft_value_mux_o_EWR[2]) );
OAI21XLTS U635 ( .A0(n906), .A1(n592), .B0(n599), .Y(Data_array_SWR[22]) );
OAI21XLTS U636 ( .A0(n674), .A1(n399), .B0(n673), .Y(Data_array_SWR[20]) );
OAI21XLTS U637 ( .A0(n669), .A1(n399), .B0(n630), .Y(Data_array_SWR[21]) );
OAI211XLTS U638 ( .A0(n631), .A1(n583), .B0(n635), .C0(n585), .Y(
Data_array_SWR[0]) );
OAI21XLTS U639 ( .A0(n635), .A1(n399), .B0(n634), .Y(Data_array_SWR[1]) );
OAI21XLTS U640 ( .A0(n631), .A1(n399), .B0(n616), .Y(Data_array_SWR[2]) );
OAI21XLTS U641 ( .A0(n627), .A1(n399), .B0(n626), .Y(Data_array_SWR[3]) );
AOI211X1TS U642 ( .A0(n717), .A1(n716), .B0(n715), .C0(n726), .Y(n719) );
CLKINVX6TS U643 ( .A(rst), .Y(n437) );
OAI221X1TS U644 ( .A0(n979), .A1(intDY_EWSW[10]), .B0(n934), .B1(
intDY_EWSW[2]), .C0(n741), .Y(n744) );
OAI221X1TS U645 ( .A0(n932), .A1(intDY_EWSW[3]), .B0(n986), .B1(
intDY_EWSW[26]), .C0(n749), .Y(n752) );
OAI221X1TS U646 ( .A0(n931), .A1(intDY_EWSW[27]), .B0(n985), .B1(
intDY_EWSW[19]), .C0(n757), .Y(n760) );
OAI221X1TS U647 ( .A0(n980), .A1(intDY_EWSW[17]), .B0(n991), .B1(
intDY_EWSW[16]), .C0(n765), .Y(n768) );
OAI221X1TS U648 ( .A0(n929), .A1(intDY_EWSW[20]), .B0(n990), .B1(
intDY_EWSW[30]), .C0(n763), .Y(n770) );
OAI21X1TS U649 ( .A0(n493), .A1(n998), .B0(n492), .Y(n465) );
OAI21X1TS U650 ( .A0(n493), .A1(n997), .B0(n492), .Y(n494) );
OAI21XLTS U651 ( .A0(n650), .A1(n399), .B0(n649), .Y(Data_array_SWR[4]) );
OAI21XLTS U652 ( .A0(n645), .A1(n399), .B0(n618), .Y(Data_array_SWR[5]) );
OAI21XLTS U653 ( .A0(n646), .A1(n904), .B0(n608), .Y(Data_array_SWR[6]) );
NOR2X2TS U654 ( .A(n492), .B(n977), .Y(n485) );
OAI211X1TS U655 ( .A0(n976), .A1(n535), .B0(n458), .C0(n457), .Y(n480) );
AOI21X2TS U656 ( .A0(n439), .A1(Data_array_SWR[51]), .B0(n491), .Y(n535) );
OAI211X1TS U657 ( .A0(n976), .A1(n538), .B0(n447), .C0(n446), .Y(n453) );
AOI21X2TS U658 ( .A0(n439), .A1(Data_array_SWR[50]), .B0(n491), .Y(n538) );
BUFX4TS U659 ( .A(n1051), .Y(n1060) );
BUFX4TS U660 ( .A(n1051), .Y(n1048) );
BUFX4TS U661 ( .A(n437), .Y(n1063) );
BUFX4TS U662 ( .A(n437), .Y(n1059) );
BUFX6TS U663 ( .A(n437), .Y(n1057) );
BUFX4TS U664 ( .A(n437), .Y(n1058) );
OAI211X1TS U665 ( .A0(n976), .A1(n552), .B0(n551), .C0(n550), .Y(n559) );
AOI21X2TS U666 ( .A0(n439), .A1(Data_array_SWR[49]), .B0(n491), .Y(n552) );
BUFX6TS U667 ( .A(n1063), .Y(n1035) );
BUFX4TS U668 ( .A(n1057), .Y(n1054) );
AOI21X2TS U669 ( .A0(Data_array_SWR[48]), .A1(n439), .B0(n491), .Y(n557) );
AOI21X2TS U670 ( .A0(n439), .A1(Data_array_SWR[46]), .B0(n460), .Y(n473) );
OAI21X1TS U671 ( .A0(n493), .A1(n941), .B0(n492), .Y(n460) );
AOI21X2TS U672 ( .A0(n439), .A1(Data_array_SWR[47]), .B0(n461), .Y(n479) );
OAI21X1TS U673 ( .A0(n493), .A1(n940), .B0(n492), .Y(n461) );
BUFX4TS U674 ( .A(n1059), .Y(n1053) );
BUFX4TS U675 ( .A(n1063), .Y(n1050) );
BUFX4TS U676 ( .A(n1058), .Y(n1056) );
CLKINVX6TS U677 ( .A(n564), .Y(n560) );
BUFX6TS U678 ( .A(left_right_SHT2), .Y(n564) );
INVX2TS U679 ( .A(n582), .Y(n398) );
INVX4TS U680 ( .A(n398), .Y(n399) );
OAI21X2TS U681 ( .A0(n968), .A1(n610), .B0(n609), .Y(n660) );
OAI21X2TS U682 ( .A0(n964), .A1(n610), .B0(n603), .Y(n654) );
OAI21X2TS U683 ( .A0(n956), .A1(n610), .B0(n606), .Y(n648) );
OAI21X2TS U684 ( .A0(n594), .A1(n960), .B0(n593), .Y(n671) );
CLKINVX3TS U685 ( .A(n610), .Y(n400) );
INVX3TS U686 ( .A(n610), .Y(n401) );
BUFX4TS U687 ( .A(n445), .Y(n554) );
BUFX4TS U688 ( .A(n924), .Y(n912) );
INVX2TS U689 ( .A(n895), .Y(n902) );
INVX4TS U690 ( .A(n895), .Y(n901) );
INVX4TS U691 ( .A(n895), .Y(n897) );
INVX3TS U692 ( .A(n594), .Y(n611) );
NOR3X1TS U693 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[16]), .C(
Raw_mant_NRM_SWR[17]), .Y(n714) );
OAI2BB1X1TS U694 ( .A0N(n1064), .A1N(Raw_mant_NRM_SWR[15]), .B0(n600), .Y(
n666) );
NOR2X1TS U695 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n724)
);
NOR4X1TS U696 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[11]), .D(n720), .Y(n427) );
OAI21XLTS U697 ( .A0(n658), .A1(n582), .B0(n641), .Y(Data_array_SWR[15]) );
OAI21XLTS U698 ( .A0(n658), .A1(n904), .B0(n613), .Y(Data_array_SWR[14]) );
OAI21XLTS U699 ( .A0(n662), .A1(n582), .B0(n661), .Y(Data_array_SWR[12]) );
OAI21XLTS U700 ( .A0(n657), .A1(n399), .B0(n620), .Y(Data_array_SWR[13]) );
NOR3X1TS U701 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[11]), .Y(n721) );
OAI221X1TS U702 ( .A0(n993), .A1(intDY_EWSW[7]), .B0(n984), .B1(
intDY_EWSW[14]), .C0(n747), .Y(n754) );
INVX1TS U703 ( .A(n575), .Y(enable_Pipeline_input) );
AOI221X1TS U704 ( .A0(intDX_EWSW[30]), .A1(n927), .B0(intDX_EWSW[29]), .B1(
n973), .C0(n782), .Y(n784) );
AOI31XLTS U705 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n426), .A2(n416), .B0(n715),
.Y(n420) );
NOR2X2TS U706 ( .A(n968), .B(n415), .Y(n715) );
OAI211X2TS U707 ( .A0(intDX_EWSW[12]), .A1(n1019), .B0(n812), .C0(n798), .Y(
n814) );
AOI211XLTS U708 ( .A0(intDY_EWSW[16]), .A1(n991), .B0(n826), .C0(n827), .Y(
n818) );
OAI211X2TS U709 ( .A0(intDX_EWSW[20]), .A1(n1015), .B0(n832), .C0(n817), .Y(
n826) );
NOR3X6TS U710 ( .A(n436), .B(exp_rslt_NRM2_EW1[7]), .C(n433), .Y(
array_comparators_LTComparator_N0) );
XNOR2X2TS U711 ( .A(DP_OP_15J181_122_6956_n1), .B(ADD_OVRFLW_NRM2), .Y(n436)
);
CLKINVX6TS U712 ( .A(n895), .Y(n898) );
NOR3X2TS U713 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[4]), .C(n713),
.Y(n710) );
OR2X1TS U714 ( .A(N60), .B(N59), .Y(n845) );
OAI21XLTS U715 ( .A0(n664), .A1(n399), .B0(n637), .Y(Data_array_SWR[11]) );
OAI21XLTS U716 ( .A0(n664), .A1(n904), .B0(n602), .Y(Data_array_SWR[10]) );
OAI21XLTS U717 ( .A0(n668), .A1(n399), .B0(n667), .Y(Data_array_SWR[8]) );
OAI21XLTS U718 ( .A0(n663), .A1(n582), .B0(n622), .Y(Data_array_SWR[9]) );
NOR2X4TS U719 ( .A(n596), .B(n595), .Y(n672) );
NOR2X4TS U720 ( .A(n584), .B(n596), .Y(n643) );
AOI22X2TS U721 ( .A0(n611), .A1(LZD_raw_out_EWR[1]), .B0(
Shift_amount_SHT1_EWR[1]), .B1(n924), .Y(n596) );
CLKBUFX2TS U722 ( .A(n907), .Y(n402) );
NAND2X2TS U723 ( .A(Shift_reg_FLAGS_7[1]), .B(ADD_OVRFLW_NRM), .Y(n610) );
OAI22X2TS U724 ( .A0(Shift_reg_FLAGS_7[1]), .A1(Shift_amount_SHT1_EWR[0]),
.B0(LZD_raw_out_EWR[0]), .B1(n594), .Y(n584) );
AOI21X2TS U725 ( .A0(n439), .A1(Data_array_SWR[45]), .B0(n465), .Y(n566) );
AOI21X2TS U726 ( .A0(n439), .A1(Data_array_SWR[44]), .B0(n494), .Y(n562) );
AOI222X4TS U727 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n950), .B0(
DmP_mant_SFG_SWR[2]), .B1(n845), .C0(n950), .C1(n845), .Y(n520) );
NOR3X1TS U728 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
Raw_mant_NRM_SWR[21]), .Y(n708) );
NOR2X2TS U729 ( .A(Raw_mant_NRM_SWR[7]), .B(n409), .Y(n727) );
NOR3X1TS U730 ( .A(n403), .B(n781), .C(intDY_EWSW[28]), .Y(n782) );
OAI221X1TS U731 ( .A0(n900), .A1(intDY_EWSW[28]), .B0(n936), .B1(
intDY_EWSW[6]), .C0(n755), .Y(n762) );
AOI31XLTS U732 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n426), .A2(n966), .B0(n715),
.Y(n431) );
NAND2X2TS U733 ( .A(bit_shift_SHT2), .B(shift_value_SHT2_EWR[3]), .Y(n492)
);
NAND3X2TS U734 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.C(n976), .Y(n505) );
OAI32X1TS U735 ( .A0(Raw_mant_NRM_SWR[23]), .A1(Raw_mant_NRM_SWR[21]), .A2(
n970), .B0(n923), .B1(Raw_mant_NRM_SWR[23]), .Y(n428) );
AOI222X4TS U736 ( .A0(DMP_SFG[14]), .A1(DmP_mant_SFG_SWR[16]), .B0(
DMP_SFG[14]), .B1(n689), .C0(DmP_mant_SFG_SWR[16]), .C1(n689), .Y(n869) );
AOI222X4TS U737 ( .A0(DMP_SFG[20]), .A1(DmP_mant_SFG_SWR[22]), .B0(
DMP_SFG[20]), .B1(n733), .C0(DmP_mant_SFG_SWR[22]), .C1(n733), .Y(n884) );
AOI222X4TS U738 ( .A0(DMP_SFG[8]), .A1(DmP_mant_SFG_SWR[10]), .B0(DMP_SFG[8]), .B1(n588), .C0(DmP_mant_SFG_SWR[10]), .C1(n588), .Y(n853) );
AOI222X4TS U739 ( .A0(DMP_SFG[2]), .A1(DmP_mant_SFG_SWR[4]), .B0(DMP_SFG[2]),
.B1(n526), .C0(DmP_mant_SFG_SWR[4]), .C1(n526), .Y(n541) );
AOI222X4TS U740 ( .A0(DMP_SFG[4]), .A1(DmP_mant_SFG_SWR[6]), .B0(DMP_SFG[4]),
.B1(n547), .C0(DmP_mant_SFG_SWR[6]), .C1(n547), .Y(n571) );
AOI222X4TS U741 ( .A0(DMP_SFG[6]), .A1(DmP_mant_SFG_SWR[8]), .B0(DMP_SFG[6]),
.B1(n578), .C0(DmP_mant_SFG_SWR[8]), .C1(n578), .Y(n848) );
NOR4X2TS U742 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[25]), .C(
Raw_mant_NRM_SWR[22]), .D(Raw_mant_NRM_SWR[23]), .Y(n705) );
AOI222X4TS U743 ( .A0(DMP_SFG[22]), .A1(DmP_mant_SFG_SWR[24]), .B0(
DMP_SFG[22]), .B1(n891), .C0(DmP_mant_SFG_SWR[24]), .C1(n891), .Y(n775) );
AOI31XLTS U744 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n425), .A2(n969), .B0(n424),
.Y(n419) );
INVX2TS U745 ( .A(intDX_EWSW[28]), .Y(n900) );
OAI21XLTS U746 ( .A0(intDX_EWSW[1]), .A1(n1025), .B0(intDX_EWSW[0]), .Y(n788) );
OAI21XLTS U747 ( .A0(intDX_EWSW[15]), .A1(n1027), .B0(intDX_EWSW[14]), .Y(
n808) );
NOR2XLTS U748 ( .A(n821), .B(intDY_EWSW[16]), .Y(n822) );
OAI21XLTS U749 ( .A0(intDX_EWSW[21]), .A1(n1013), .B0(intDX_EWSW[20]), .Y(
n820) );
OAI21XLTS U750 ( .A0(n505), .A1(n998), .B0(n498), .Y(n499) );
OAI211XLTS U751 ( .A0(n913), .A1(n908), .B0(n909), .C0(beg_OP), .Y(n575) );
OAI21XLTS U752 ( .A0(n581), .A1(n587), .B0(n580), .Y(n579) );
OAI21XLTS U753 ( .A0(n523), .A1(n525), .B0(n522), .Y(n521) );
OAI21XLTS U754 ( .A0(n906), .A1(n399), .B0(n610), .Y(Data_array_SWR[25]) );
OAI21XLTS U755 ( .A0(n646), .A1(n399), .B0(n644), .Y(Data_array_SWR[7]) );
OR2X1TS U756 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[4]), .Y(formatted_number_W[27]) );
NAND2X1TS U757 ( .A(n708), .B(n705), .Y(n418) );
NOR2X1TS U758 ( .A(Raw_mant_NRM_SWR[18]), .B(n418), .Y(n717) );
NAND2X1TS U759 ( .A(n717), .B(n714), .Y(n415) );
NOR2X1TS U760 ( .A(Raw_mant_NRM_SWR[14]), .B(n415), .Y(n417) );
NAND2X1TS U761 ( .A(n721), .B(n417), .Y(n723) );
NAND2X1TS U762 ( .A(n724), .B(n408), .Y(n409) );
NAND2X1TS U763 ( .A(n727), .B(n956), .Y(n713) );
OA21XLTS U764 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[2]), .B0(n710), .Y(n411) );
INVX2TS U765 ( .A(n409), .Y(n410) );
OAI31X1TS U766 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n411), .A2(
Raw_mant_NRM_SWR[6]), .B0(n410), .Y(n729) );
NOR2XLTS U767 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[21]), .Y(n414)
);
NOR2X1TS U768 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[25]), .Y(n413)
);
AOI32X1TS U769 ( .A0(n414), .A1(n413), .A2(Raw_mant_NRM_SWR[19]), .B0(n412),
.B1(n413), .Y(n421) );
INVX2TS U770 ( .A(n418), .Y(n426) );
NOR2XLTS U771 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[17]), .Y(n416)
);
INVX2TS U772 ( .A(n417), .Y(n720) );
NOR2X1TS U773 ( .A(Raw_mant_NRM_SWR[13]), .B(n720), .Y(n425) );
OAI21X1TS U774 ( .A0(n418), .A1(n964), .B0(n718), .Y(n424) );
AOI21X1TS U775 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n961), .B0(
Raw_mant_NRM_SWR[2]), .Y(n422) );
NAND2X1TS U776 ( .A(n710), .B(n960), .Y(n730) );
OAI22X1TS U777 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n722), .B0(n422), .B1(n730),
.Y(n423) );
AOI211X1TS U778 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n425), .B0(n424), .C0(n423),
.Y(n712) );
AOI22X1TS U779 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n427), .B0(
Raw_mant_NRM_SWR[6]), .B1(n727), .Y(n430) );
OAI21XLTS U780 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n428), .B0(n965), .Y(n429)
);
OR4X2TS U781 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[1]), .D(exp_rslt_NRM2_EW1[0]), .Y(n432) );
OR4X2TS U782 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n432), .Y(n433) );
AND4X1TS U783 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[1]), .D(exp_rslt_NRM2_EW1[0]), .Y(n434) );
AND4X1TS U784 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n434), .Y(n435) );
AND3X1TS U785 ( .A(n436), .B(exp_rslt_NRM2_EW1[7]), .C(n435), .Y(
array_comparators_GTComparator_N0) );
AOI33XLTS U786 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n943), .B1(n913), .B2(n1002),
.Y(n390) );
CLKBUFX2TS U787 ( .A(n437), .Y(n438) );
BUFX3TS U788 ( .A(n1057), .Y(n1046) );
BUFX3TS U789 ( .A(n1059), .Y(n1047) );
BUFX3TS U790 ( .A(n437), .Y(n1055) );
BUFX3TS U791 ( .A(n1057), .Y(n1052) );
BUFX3TS U792 ( .A(n1048), .Y(n1034) );
BUFX3TS U793 ( .A(n437), .Y(n1051) );
BUFX3TS U794 ( .A(n1063), .Y(n1049) );
BUFX3TS U795 ( .A(n1051), .Y(n1037) );
BUFX3TS U796 ( .A(n437), .Y(n1036) );
BUFX3TS U797 ( .A(n1058), .Y(n1045) );
BUFX3TS U798 ( .A(n1063), .Y(n1062) );
BUFX3TS U799 ( .A(n1059), .Y(n1061) );
BUFX3TS U800 ( .A(n1057), .Y(n1038) );
BUFX3TS U801 ( .A(n1058), .Y(n1041) );
BUFX3TS U802 ( .A(n1063), .Y(n1042) );
BUFX3TS U803 ( .A(n1053), .Y(n1044) );
BUFX3TS U804 ( .A(n1057), .Y(n1039) );
BUFX3TS U805 ( .A(n1059), .Y(n1043) );
BUFX3TS U806 ( .A(n1049), .Y(n1040) );
NAND2BX2TS U807 ( .AN(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n493) );
NAND2X1TS U808 ( .A(shift_value_SHT2_EWR[3]), .B(n977), .Y(n455) );
OAI22X1TS U809 ( .A0(n493), .A1(n1000), .B0(n455), .B1(n940), .Y(n440) );
NOR2BX2TS U810 ( .AN(bit_shift_SHT2), .B(n439), .Y(n491) );
AOI22X1TS U811 ( .A0(n442), .A1(Data_array_SWR[46]), .B0(n443), .B1(
Data_array_SWR[42]), .Y(n447) );
NOR2BX1TS U812 ( .AN(n439), .B(shift_value_SHT2_EWR[4]), .Y(n445) );
AOI22X1TS U813 ( .A0(n444), .A1(Data_array_SWR[38]), .B0(n554), .B1(
Data_array_SWR[34]), .Y(n446) );
NAND2X1TS U814 ( .A(shift_value_SHT2_EWR[4]), .B(bit_shift_SHT2), .Y(n482)
);
AOI21X1TS U815 ( .A0(n564), .A1(n453), .B0(n448), .Y(n449) );
OAI21X1TS U816 ( .A0(n489), .A1(n441), .B0(n449), .Y(sftr_odat_SHT2_SWR[17])
);
BUFX4TS U817 ( .A(n450), .Y(n907) );
CLKAND2X2TS U818 ( .A(n907), .B(sftr_odat_SHT2_SWR[17]), .Y(
formatted_number_W[15]) );
AOI21X1TS U819 ( .A0(n560), .A1(n453), .B0(n452), .Y(n454) );
OAI21X1TS U820 ( .A0(n489), .A1(n451), .B0(n454), .Y(sftr_odat_SHT2_SWR[8])
);
CLKAND2X2TS U821 ( .A(n907), .B(sftr_odat_SHT2_SWR[8]), .Y(
formatted_number_W[6]) );
OAI22X1TS U822 ( .A0(n493), .A1(n999), .B0(n455), .B1(n941), .Y(n456) );
AOI22X1TS U823 ( .A0(n444), .A1(Data_array_SWR[39]), .B0(n443), .B1(
Data_array_SWR[43]), .Y(n458) );
AOI22X1TS U824 ( .A0(n554), .A1(Data_array_SWR[35]), .B0(n442), .B1(
Data_array_SWR[47]), .Y(n457) );
AOI21X1TS U825 ( .A0(n560), .A1(n480), .B0(n452), .Y(n459) );
OAI21X1TS U826 ( .A0(n531), .A1(n451), .B0(n459), .Y(sftr_odat_SHT2_SWR[9])
);
CLKAND2X2TS U827 ( .A(n907), .B(sftr_odat_SHT2_SWR[9]), .Y(
formatted_number_W[7]) );
AOI22X1TS U828 ( .A0(n442), .A1(Data_array_SWR[43]), .B0(n443), .B1(
Data_array_SWR[39]), .Y(n463) );
AOI22X1TS U829 ( .A0(n444), .A1(Data_array_SWR[35]), .B0(n554), .B1(
Data_array_SWR[31]), .Y(n462) );
OAI211X1TS U830 ( .A0(n479), .A1(n976), .B0(n463), .C0(n462), .Y(n469) );
AOI21X1TS U831 ( .A0(n560), .A1(n469), .B0(n452), .Y(n464) );
OAI21X1TS U832 ( .A0(n473), .A1(n451), .B0(n464), .Y(sftr_odat_SHT2_SWR[5])
);
CLKAND2X2TS U833 ( .A(n907), .B(sftr_odat_SHT2_SWR[5]), .Y(
formatted_number_W[3]) );
AOI22X1TS U834 ( .A0(n442), .A1(Data_array_SWR[41]), .B0(n443), .B1(
Data_array_SWR[37]), .Y(n467) );
AOI22X1TS U835 ( .A0(n444), .A1(Data_array_SWR[33]), .B0(n554), .B1(
Data_array_SWR[29]), .Y(n466) );
OAI211X1TS U836 ( .A0(n566), .A1(n976), .B0(n467), .C0(n466), .Y(n475) );
AOI21X1TS U837 ( .A0(n564), .A1(n475), .B0(n448), .Y(n468) );
OAI21X1TS U838 ( .A0(n557), .A1(n441), .B0(n468), .Y(sftr_odat_SHT2_SWR[22])
);
CLKAND2X2TS U839 ( .A(n907), .B(sftr_odat_SHT2_SWR[22]), .Y(
formatted_number_W[20]) );
AOI21X1TS U840 ( .A0(n564), .A1(n469), .B0(n448), .Y(n470) );
OAI21X1TS U841 ( .A0(n473), .A1(n441), .B0(n470), .Y(sftr_odat_SHT2_SWR[20])
);
CLKAND2X2TS U842 ( .A(n907), .B(sftr_odat_SHT2_SWR[20]), .Y(
formatted_number_W[18]) );
AOI22X1TS U843 ( .A0(n442), .A1(Data_array_SWR[42]), .B0(n443), .B1(
Data_array_SWR[38]), .Y(n472) );
AOI22X1TS U844 ( .A0(n444), .A1(Data_array_SWR[34]), .B0(n554), .B1(
Data_array_SWR[30]), .Y(n471) );
OAI211X1TS U845 ( .A0(n473), .A1(n976), .B0(n472), .C0(n471), .Y(n477) );
AOI21X1TS U846 ( .A0(n560), .A1(n477), .B0(n452), .Y(n474) );
OAI21X1TS U847 ( .A0(n479), .A1(n451), .B0(n474), .Y(sftr_odat_SHT2_SWR[4])
);
CLKAND2X2TS U848 ( .A(n907), .B(sftr_odat_SHT2_SWR[4]), .Y(
formatted_number_W[2]) );
AOI21X1TS U849 ( .A0(n560), .A1(n475), .B0(n452), .Y(n476) );
OAI21X1TS U850 ( .A0(n451), .A1(n557), .B0(n476), .Y(sftr_odat_SHT2_SWR[3])
);
CLKAND2X2TS U851 ( .A(n907), .B(sftr_odat_SHT2_SWR[3]), .Y(
formatted_number_W[1]) );
AOI21X1TS U852 ( .A0(n564), .A1(n477), .B0(n448), .Y(n478) );
OAI21X1TS U853 ( .A0(n479), .A1(n441), .B0(n478), .Y(sftr_odat_SHT2_SWR[21])
);
CLKAND2X2TS U854 ( .A(n907), .B(sftr_odat_SHT2_SWR[21]), .Y(
formatted_number_W[19]) );
AOI21X1TS U855 ( .A0(n564), .A1(n480), .B0(n448), .Y(n481) );
OAI21X1TS U856 ( .A0(n531), .A1(n441), .B0(n481), .Y(sftr_odat_SHT2_SWR[16])
);
CLKAND2X2TS U857 ( .A(n907), .B(sftr_odat_SHT2_SWR[16]), .Y(
formatted_number_W[14]) );
INVX2TS U858 ( .A(n482), .Y(n507) );
AOI22X1TS U859 ( .A0(n444), .A1(Data_array_SWR[40]), .B0(n554), .B1(
Data_array_SWR[36]), .Y(n483) );
OAI21XLTS U860 ( .A0(n997), .A1(n505), .B0(n483), .Y(n484) );
OR2X1TS U861 ( .A(n485), .B(n507), .Y(n501) );
AO22XLTS U862 ( .A0(n444), .A1(Data_array_SWR[45]), .B0(n554), .B1(
Data_array_SWR[41]), .Y(n486) );
AOI211X1TS U863 ( .A0(n443), .A1(Data_array_SWR[49]), .B0(n501), .C0(n486),
.Y(n515) );
AOI22X1TS U864 ( .A0(n564), .A1(n514), .B0(n515), .B1(n560), .Y(
sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U865 ( .A(n907), .B(sftr_odat_SHT2_SWR[15]), .Y(
formatted_number_W[13]) );
AOI22X1TS U866 ( .A0(n444), .A1(Data_array_SWR[31]), .B0(n554), .B1(
Data_array_SWR[27]), .Y(n488) );
AOI22X1TS U867 ( .A0(n442), .A1(Data_array_SWR[39]), .B0(n443), .B1(
Data_array_SWR[35]), .Y(n487) );
OAI211X1TS U868 ( .A0(n489), .A1(n976), .B0(n488), .C0(n487), .Y(n536) );
AOI21X1TS U869 ( .A0(n564), .A1(n536), .B0(n448), .Y(n490) );
OAI21X1TS U870 ( .A0(n538), .A1(n441), .B0(n490), .Y(sftr_odat_SHT2_SWR[24])
);
CLKAND2X2TS U871 ( .A(n907), .B(sftr_odat_SHT2_SWR[24]), .Y(
formatted_number_W[22]) );
AOI22X1TS U872 ( .A0(n442), .A1(Data_array_SWR[40]), .B0(n443), .B1(
Data_array_SWR[36]), .Y(n496) );
AOI22X1TS U873 ( .A0(n444), .A1(Data_array_SWR[32]), .B0(n554), .B1(
Data_array_SWR[28]), .Y(n495) );
OAI211X1TS U874 ( .A0(n562), .A1(n976), .B0(n496), .C0(n495), .Y(n508) );
AOI21X1TS U875 ( .A0(n564), .A1(n508), .B0(n448), .Y(n497) );
OAI21X1TS U876 ( .A0(n552), .A1(n441), .B0(n497), .Y(sftr_odat_SHT2_SWR[23])
);
CLKAND2X2TS U877 ( .A(n907), .B(sftr_odat_SHT2_SWR[23]), .Y(
formatted_number_W[21]) );
AOI22X1TS U878 ( .A0(n444), .A1(Data_array_SWR[41]), .B0(n554), .B1(
Data_array_SWR[37]), .Y(n498) );
AO22XLTS U879 ( .A0(Data_array_SWR[44]), .A1(n444), .B0(n554), .B1(
Data_array_SWR[40]), .Y(n500) );
AOI211X1TS U880 ( .A0(Data_array_SWR[48]), .A1(n443), .B0(n501), .C0(n500),
.Y(n513) );
AOI22X1TS U881 ( .A0(n564), .A1(n512), .B0(n513), .B1(n560), .Y(
sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U882 ( .A(n907), .B(sftr_odat_SHT2_SWR[14]), .Y(
formatted_number_W[12]) );
AOI22X1TS U883 ( .A0(n444), .A1(Data_array_SWR[42]), .B0(n554), .B1(
Data_array_SWR[38]), .Y(n502) );
OAI21XLTS U884 ( .A0(n505), .A1(n941), .B0(n502), .Y(n503) );
AOI211X1TS U885 ( .A0(n443), .A1(Data_array_SWR[46]), .B0(n507), .C0(n503),
.Y(n510) );
AOI22X1TS U886 ( .A0(n444), .A1(Data_array_SWR[43]), .B0(n554), .B1(
Data_array_SWR[39]), .Y(n504) );
OAI21XLTS U887 ( .A0(n505), .A1(n940), .B0(n504), .Y(n506) );
AOI211X1TS U888 ( .A0(n443), .A1(Data_array_SWR[47]), .B0(n507), .C0(n506),
.Y(n511) );
AOI22X1TS U889 ( .A0(n564), .A1(n510), .B0(n511), .B1(n560), .Y(
sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U890 ( .A(n907), .B(sftr_odat_SHT2_SWR[13]), .Y(
formatted_number_W[11]) );
AOI21X1TS U891 ( .A0(n560), .A1(n508), .B0(n452), .Y(n509) );
OAI21X1TS U892 ( .A0(n552), .A1(n451), .B0(n509), .Y(sftr_odat_SHT2_SWR[2])
);
CLKAND2X2TS U893 ( .A(n907), .B(sftr_odat_SHT2_SWR[2]), .Y(
formatted_number_W[0]) );
AOI22X1TS U894 ( .A0(n564), .A1(n511), .B0(n510), .B1(n560), .Y(
sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U895 ( .A(n907), .B(sftr_odat_SHT2_SWR[12]), .Y(
formatted_number_W[10]) );
AOI22X1TS U896 ( .A0(n564), .A1(n513), .B0(n512), .B1(n560), .Y(
sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U897 ( .A(n907), .B(sftr_odat_SHT2_SWR[11]), .Y(
formatted_number_W[9]) );
AOI22X1TS U898 ( .A0(n564), .A1(n515), .B0(n514), .B1(n560), .Y(
sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U899 ( .A(n402), .B(sftr_odat_SHT2_SWR[10]), .Y(
formatted_number_W[8]) );
OR2X2TS U900 ( .A(ADD_OVRFLW_NRM), .B(n912), .Y(n594) );
INVX4TS U901 ( .A(n594), .Y(n1064) );
NAND2X1TS U902 ( .A(DmP_EXP_EWSW[23]), .B(n406), .Y(n516) );
OAI21XLTS U903 ( .A0(DmP_EXP_EWSW[23]), .A1(n406), .B0(n516), .Y(
Shift_amount_EXP_EW[0]) );
NAND2X1TS U904 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n913), .Y(n909)
);
NAND2X1TS U905 ( .A(n943), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n908)
);
OAI21XLTS U906 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(n909), .B0(
n908), .Y(n388) );
INVX2TS U907 ( .A(intadd_429_SUM_0_), .Y(Shift_amount_EXP_EW[1]) );
INVX2TS U908 ( .A(intadd_429_SUM_1_), .Y(Shift_amount_EXP_EW[2]) );
INVX2TS U909 ( .A(intadd_429_SUM_2_), .Y(Shift_amount_EXP_EW[3]) );
INVX2TS U910 ( .A(n516), .Y(intadd_429_CI) );
CLKBUFX2TS U911 ( .A(n1065), .Y(n890) );
NAND2X1TS U912 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n844) );
AOI22X1TS U913 ( .A0(n855), .A1(n520), .B0(n844), .B1(n890), .Y(n518) );
NAND2X1TS U914 ( .A(DmP_mant_SFG_SWR[3]), .B(n946), .Y(n519) );
OAI21XLTS U915 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n946), .B0(n519), .Y(n517) );
XOR2XLTS U916 ( .A(n518), .B(n517), .Y(Raw_mant_SGF[3]) );
NOR2X1TS U917 ( .A(DmP_mant_SFG_SWR[4]), .B(n951), .Y(n523) );
AOI22X1TS U918 ( .A0(DMP_SFG[1]), .A1(n914), .B0(n520), .B1(n519), .Y(n524)
);
AOI222X4TS U919 ( .A0(n946), .A1(n844), .B0(n946), .B1(n914), .C0(n844),
.C1(n914), .Y(n526) );
AOI22X1TS U920 ( .A0(n855), .A1(n524), .B0(n526), .B1(n1065), .Y(n522) );
OAI31X1TS U921 ( .A0(n523), .A1(n522), .A2(n525), .B0(n521), .Y(
Raw_mant_SGF[4]) );
OAI22X1TS U922 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n951), .B0(n525), .B1(n524),
.Y(n539) );
AOI22X1TS U923 ( .A0(n855), .A1(n539), .B0(n541), .B1(n1065), .Y(n528) );
NAND2X1TS U924 ( .A(DmP_mant_SFG_SWR[5]), .B(n915), .Y(n540) );
OAI21XLTS U925 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n915), .B0(n540), .Y(n527) );
XOR2XLTS U926 ( .A(n528), .B(n527), .Y(Raw_mant_SGF[5]) );
AOI22X1TS U927 ( .A0(n444), .A1(Data_array_SWR[30]), .B0(n443), .B1(
Data_array_SWR[34]), .Y(n530) );
AOI22X1TS U928 ( .A0(n554), .A1(Data_array_SWR[26]), .B0(n442), .B1(
Data_array_SWR[38]), .Y(n529) );
OAI211X1TS U929 ( .A0(n531), .A1(n976), .B0(n530), .C0(n529), .Y(n533) );
AOI21X1TS U930 ( .A0(n564), .A1(n533), .B0(n448), .Y(n532) );
OAI21XLTS U931 ( .A0(n535), .A1(n441), .B0(n532), .Y(sftr_odat_SHT2_SWR[25])
);
AOI21X1TS U932 ( .A0(n560), .A1(n533), .B0(n452), .Y(n534) );
OAI21XLTS U933 ( .A0(n451), .A1(n535), .B0(n534), .Y(sftr_odat_SHT2_SWR[0])
);
AOI21X1TS U934 ( .A0(n560), .A1(n536), .B0(n452), .Y(n537) );
OAI21XLTS U935 ( .A0(n451), .A1(n538), .B0(n537), .Y(sftr_odat_SHT2_SWR[1])
);
NOR2X1TS U936 ( .A(DmP_mant_SFG_SWR[6]), .B(n952), .Y(n544) );
AOI22X1TS U937 ( .A0(DMP_SFG[3]), .A1(n947), .B0(n540), .B1(n539), .Y(n545)
);
AOI222X4TS U938 ( .A0(n541), .A1(n915), .B0(n541), .B1(n947), .C0(n915),
.C1(n947), .Y(n547) );
AOI22X1TS U939 ( .A0(n855), .A1(n545), .B0(n547), .B1(n1065), .Y(n543) );
OAI21XLTS U940 ( .A0(n544), .A1(n546), .B0(n543), .Y(n542) );
OAI31X1TS U941 ( .A0(n544), .A1(n543), .A2(n546), .B0(n542), .Y(
Raw_mant_SGF[6]) );
OAI22X1TS U942 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n952), .B0(n546), .B1(n545),
.Y(n569) );
AOI22X1TS U943 ( .A0(n855), .A1(n569), .B0(n571), .B1(n1065), .Y(n549) );
NAND2X1TS U944 ( .A(DmP_mant_SFG_SWR[7]), .B(n916), .Y(n570) );
OAI21XLTS U945 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n916), .B0(n570), .Y(n548) );
XOR2XLTS U946 ( .A(n549), .B(n548), .Y(Raw_mant_SGF[7]) );
OR2X1TS U947 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[3]), .Y(formatted_number_W[26]) );
OR2X1TS U948 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[5]), .Y(formatted_number_W[28]) );
OR2X1TS U949 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[0]), .Y(formatted_number_W[23]) );
OR2X1TS U950 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[6]), .Y(formatted_number_W[29]) );
OR2X1TS U951 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[2]), .Y(formatted_number_W[25]) );
OR2X1TS U952 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[1]), .Y(formatted_number_W[24]) );
AOI22X1TS U953 ( .A0(n442), .A1(Data_array_SWR[45]), .B0(n443), .B1(
Data_array_SWR[41]), .Y(n551) );
AOI22X1TS U954 ( .A0(n444), .A1(Data_array_SWR[37]), .B0(n554), .B1(
Data_array_SWR[33]), .Y(n550) );
AOI21X1TS U955 ( .A0(n564), .A1(n559), .B0(n448), .Y(n553) );
OAI21X1TS U956 ( .A0(n562), .A1(n441), .B0(n553), .Y(sftr_odat_SHT2_SWR[18])
);
AOI22X1TS U957 ( .A0(Data_array_SWR[44]), .A1(n442), .B0(Data_array_SWR[40]),
.B1(n443), .Y(n556) );
AOI22X1TS U958 ( .A0(n444), .A1(Data_array_SWR[36]), .B0(Data_array_SWR[32]),
.B1(n554), .Y(n555) );
OAI211X1TS U959 ( .A0(n976), .A1(n557), .B0(n556), .C0(n555), .Y(n563) );
AOI21X1TS U960 ( .A0(n560), .A1(n563), .B0(n452), .Y(n558) );
OAI21X1TS U961 ( .A0(n566), .A1(n451), .B0(n558), .Y(sftr_odat_SHT2_SWR[6])
);
AOI21X1TS U962 ( .A0(n560), .A1(n559), .B0(n452), .Y(n561) );
OAI21X1TS U963 ( .A0(n562), .A1(n451), .B0(n561), .Y(sftr_odat_SHT2_SWR[7])
);
AOI21X1TS U964 ( .A0(n564), .A1(n563), .B0(n448), .Y(n565) );
OAI21X1TS U965 ( .A0(n566), .A1(n441), .B0(n565), .Y(sftr_odat_SHT2_SWR[19])
);
NOR2BX1TS U966 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n567)
);
XOR2X1TS U967 ( .A(n920), .B(n567), .Y(DP_OP_15J181_122_6956_n15) );
NOR2BX1TS U968 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n568)
);
XOR2X1TS U969 ( .A(n920), .B(n568), .Y(DP_OP_15J181_122_6956_n14) );
NOR2X1TS U970 ( .A(DmP_mant_SFG_SWR[8]), .B(n954), .Y(n574) );
AOI22X1TS U971 ( .A0(DMP_SFG[5]), .A1(n948), .B0(n570), .B1(n569), .Y(n576)
);
AOI222X4TS U972 ( .A0(n571), .A1(n916), .B0(n571), .B1(n948), .C0(n916),
.C1(n948), .Y(n578) );
AOI22X1TS U973 ( .A0(n855), .A1(n576), .B0(n578), .B1(n1065), .Y(n573) );
OAI21XLTS U974 ( .A0(n574), .A1(n577), .B0(n573), .Y(n572) );
OAI31X1TS U975 ( .A0(n574), .A1(n573), .A2(n577), .B0(n572), .Y(
Raw_mant_SGF[8]) );
NOR2X1TS U976 ( .A(DmP_mant_SFG_SWR[10]), .B(n955), .Y(n581) );
NAND2X1TS U977 ( .A(DmP_mant_SFG_SWR[9]), .B(n917), .Y(n850) );
OAI22X1TS U978 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n954), .B0(n577), .B1(n576),
.Y(n849) );
AOI22X1TS U979 ( .A0(DMP_SFG[7]), .A1(n949), .B0(n850), .B1(n849), .Y(n586)
);
AOI222X4TS U980 ( .A0(n848), .A1(n917), .B0(n848), .B1(n949), .C0(n917),
.C1(n949), .Y(n588) );
AOI22X1TS U981 ( .A0(n855), .A1(n586), .B0(n588), .B1(n1065), .Y(n580) );
OAI31X1TS U982 ( .A0(n581), .A1(n580), .A2(n587), .B0(n579), .Y(
Raw_mant_SGF[10]) );
AOI221X4TS U983 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n611), .B0(
Raw_mant_NRM_SWR[25]), .B1(n594), .C0(n924), .Y(n906) );
NAND2X1TS U984 ( .A(n596), .B(n584), .Y(n582) );
INVX2TS U985 ( .A(n584), .Y(n595) );
AOI22X1TS U986 ( .A0(n611), .A1(Raw_mant_NRM_SWR[24]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n401), .Y(n635) );
INVX2TS U987 ( .A(n627), .Y(n633) );
AOI22X1TS U988 ( .A0(n611), .A1(Raw_mant_NRM_SWR[25]), .B0(n643), .B1(n633),
.Y(n585) );
NOR2X1TS U989 ( .A(DmP_mant_SFG_SWR[12]), .B(n957), .Y(n591) );
NAND2X1TS U990 ( .A(DmP_mant_SFG_SWR[11]), .B(n918), .Y(n856) );
OAI22X1TS U991 ( .A0(DmP_mant_SFG_SWR[10]), .A1(n955), .B0(n587), .B1(n586),
.Y(n854) );
AOI22X1TS U992 ( .A0(DMP_SFG[9]), .A1(n953), .B0(n856), .B1(n854), .Y(n675)
);
AOI222X4TS U993 ( .A0(n853), .A1(n918), .B0(n853), .B1(n953), .C0(n918),
.C1(n953), .Y(n677) );
AOI22X1TS U994 ( .A0(n407), .A1(n675), .B0(n677), .B1(n1065), .Y(n590) );
CLKAND2X2TS U995 ( .A(DmP_mant_SFG_SWR[12]), .B(n957), .Y(n676) );
OAI21XLTS U996 ( .A0(n591), .A1(n676), .B0(n590), .Y(n589) );
OAI31X1TS U997 ( .A0(n591), .A1(n590), .A2(n676), .B0(n589), .Y(
Raw_mant_SGF[12]) );
AOI22X1TS U998 ( .A0(n400), .A1(Raw_mant_NRM_SWR[22]), .B0(
DmP_mant_SHT1_SW[20]), .B1(n924), .Y(n593) );
AOI222X4TS U999 ( .A0(n912), .A1(DmP_mant_SHT1_SW[22]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n401), .C0(Raw_mant_NRM_SWR[1]), .C1(n1064),
.Y(n903) );
AOI222X4TS U1000 ( .A0(n912), .A1(DmP_mant_SHT1_SW[21]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n401), .C0(Raw_mant_NRM_SWR[2]), .C1(n1064),
.Y(n905) );
NAND2X1TS U1001 ( .A(n596), .B(n595), .Y(n597) );
BUFX4TS U1002 ( .A(n597), .Y(n904) );
OAI22X1TS U1003 ( .A0(n903), .A1(n583), .B0(n905), .B1(n904), .Y(n598) );
AOI21X1TS U1004 ( .A0(n398), .A1(n671), .B0(n598), .Y(n599) );
AOI222X4TS U1005 ( .A0(n912), .A1(DmP_mant_SHT1_SW[9]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n400), .C0(Raw_mant_NRM_SWR[14]), .C1(n1064), .Y(n664) );
AOI22X1TS U1006 ( .A0(n400), .A1(Raw_mant_NRM_SWR[10]), .B0(
DmP_mant_SHT1_SW[8]), .B1(n924), .Y(n600) );
AOI222X4TS U1007 ( .A0(n912), .A1(DmP_mant_SHT1_SW[11]), .B0(n1064), .B1(
Raw_mant_NRM_SWR[12]), .C0(Raw_mant_NRM_SWR[13]), .C1(n400), .Y(n657)
);
AOI222X4TS U1008 ( .A0(n912), .A1(DmP_mant_SHT1_SW[10]), .B0(
Raw_mant_NRM_SWR[12]), .B1(n400), .C0(Raw_mant_NRM_SWR[13]), .C1(n1064), .Y(n662) );
OAI22X1TS U1009 ( .A0(n657), .A1(n592), .B0(n662), .B1(n583), .Y(n601) );
AOI21X1TS U1010 ( .A0(n398), .A1(n666), .B0(n601), .Y(n602) );
AOI222X4TS U1011 ( .A0(n912), .A1(DmP_mant_SHT1_SW[17]), .B0(
Raw_mant_NRM_SWR[19]), .B1(n401), .C0(Raw_mant_NRM_SWR[6]), .C1(n1064),
.Y(n652) );
AOI22X1TS U1012 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n611), .B0(
DmP_mant_SHT1_SW[16]), .B1(n924), .Y(n603) );
AOI222X4TS U1013 ( .A0(n912), .A1(DmP_mant_SHT1_SW[19]), .B0(
Raw_mant_NRM_SWR[21]), .B1(n401), .C0(Raw_mant_NRM_SWR[4]), .C1(n1064),
.Y(n669) );
AOI222X4TS U1014 ( .A0(n912), .A1(DmP_mant_SHT1_SW[18]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n401), .C0(Raw_mant_NRM_SWR[5]), .C1(n1064),
.Y(n674) );
OAI22X1TS U1015 ( .A0(n669), .A1(n592), .B0(n674), .B1(n583), .Y(n604) );
AOI21X1TS U1016 ( .A0(n398), .A1(n654), .B0(n604), .Y(n605) );
AOI222X4TS U1017 ( .A0(n924), .A1(DmP_mant_SHT1_SW[5]), .B0(n611), .B1(
Raw_mant_NRM_SWR[18]), .C0(Raw_mant_NRM_SWR[7]), .C1(n401), .Y(n646)
);
AOI22X1TS U1018 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n611), .B0(
DmP_mant_SHT1_SW[4]), .B1(n924), .Y(n606) );
AOI222X4TS U1019 ( .A0(n924), .A1(DmP_mant_SHT1_SW[7]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n400), .C0(Raw_mant_NRM_SWR[16]), .C1(n1064),
.Y(n663) );
AOI222X4TS U1020 ( .A0(n912), .A1(DmP_mant_SHT1_SW[6]), .B0(
Raw_mant_NRM_SWR[8]), .B1(n400), .C0(Raw_mant_NRM_SWR[17]), .C1(n1064),
.Y(n668) );
OAI22X1TS U1021 ( .A0(n663), .A1(n592), .B0(n668), .B1(n583), .Y(n607) );
AOI21X1TS U1022 ( .A0(n398), .A1(n648), .B0(n607), .Y(n608) );
AOI222X4TS U1023 ( .A0(n912), .A1(DmP_mant_SHT1_SW[13]), .B0(n611), .B1(
Raw_mant_NRM_SWR[10]), .C0(Raw_mant_NRM_SWR[15]), .C1(n400), .Y(n658)
);
AOI22X1TS U1024 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n611), .B0(
DmP_mant_SHT1_SW[12]), .B1(n924), .Y(n609) );
AOI222X4TS U1025 ( .A0(n912), .A1(DmP_mant_SHT1_SW[15]), .B0(n611), .B1(
Raw_mant_NRM_SWR[8]), .C0(Raw_mant_NRM_SWR[17]), .C1(n400), .Y(n651)
);
AOI222X4TS U1026 ( .A0(n912), .A1(DmP_mant_SHT1_SW[14]), .B0(n611), .B1(
Raw_mant_NRM_SWR[9]), .C0(Raw_mant_NRM_SWR[16]), .C1(n400), .Y(n656)
);
OAI22X1TS U1027 ( .A0(n651), .A1(n592), .B0(n656), .B1(n583), .Y(n612) );
AOI21X1TS U1028 ( .A0(n398), .A1(n660), .B0(n612), .Y(n613) );
INVX2TS U1029 ( .A(n904), .Y(n629) );
AOI222X4TS U1030 ( .A0(n924), .A1(DmP_mant_SHT1_SW[3]), .B0(n1064), .B1(
Raw_mant_NRM_SWR[20]), .C0(Raw_mant_NRM_SWR[5]), .C1(n401), .Y(n645)
);
AOI222X4TS U1031 ( .A0(n924), .A1(DmP_mant_SHT1_SW[2]), .B0(n1064), .B1(
Raw_mant_NRM_SWR[21]), .C0(Raw_mant_NRM_SWR[4]), .C1(n401), .Y(n650)
);
OAI22X1TS U1032 ( .A0(n645), .A1(n592), .B0(n650), .B1(n583), .Y(n615) );
AOI21X1TS U1033 ( .A0(n629), .A1(n633), .B0(n615), .Y(n616) );
OAI22X1TS U1034 ( .A0(n668), .A1(n592), .B0(n646), .B1(n583), .Y(n617) );
AOI21X1TS U1035 ( .A0(n629), .A1(n648), .B0(n617), .Y(n618) );
OAI22X1TS U1036 ( .A0(n656), .A1(n592), .B0(n658), .B1(n583), .Y(n619) );
AOI21X1TS U1037 ( .A0(n629), .A1(n660), .B0(n619), .Y(n620) );
OAI22X1TS U1038 ( .A0(n662), .A1(n592), .B0(n664), .B1(n583), .Y(n621) );
AOI21X1TS U1039 ( .A0(n629), .A1(n666), .B0(n621), .Y(n622) );
OAI22X1TS U1040 ( .A0(n674), .A1(n592), .B0(n652), .B1(n583), .Y(n623) );
AOI21X1TS U1041 ( .A0(n629), .A1(n654), .B0(n623), .Y(n624) );
OAI22X1TS U1042 ( .A0(n645), .A1(n583), .B0(n650), .B1(n904), .Y(n625) );
AOI21X1TS U1043 ( .A0(n643), .A1(n648), .B0(n625), .Y(n626) );
OAI22X1TS U1044 ( .A0(n903), .A1(n592), .B0(n905), .B1(n583), .Y(n628) );
AOI21X1TS U1045 ( .A0(n629), .A1(n671), .B0(n628), .Y(n630) );
OAI22X1TS U1046 ( .A0(n650), .A1(n592), .B0(n631), .B1(n904), .Y(n632) );
AOI21X1TS U1047 ( .A0(n672), .A1(n633), .B0(n632), .Y(n634) );
OAI22X1TS U1048 ( .A0(n657), .A1(n583), .B0(n662), .B1(n904), .Y(n636) );
AOI21X1TS U1049 ( .A0(n643), .A1(n660), .B0(n636), .Y(n637) );
OAI22X1TS U1050 ( .A0(n669), .A1(n583), .B0(n674), .B1(n904), .Y(n638) );
AOI21X1TS U1051 ( .A0(n643), .A1(n671), .B0(n638), .Y(n639) );
OAI22X1TS U1052 ( .A0(n651), .A1(n583), .B0(n656), .B1(n904), .Y(n640) );
AOI21X1TS U1053 ( .A0(n643), .A1(n654), .B0(n640), .Y(n641) );
OAI22X1TS U1054 ( .A0(n663), .A1(n583), .B0(n668), .B1(n904), .Y(n642) );
AOI21X1TS U1055 ( .A0(n643), .A1(n666), .B0(n642), .Y(n644) );
OAI22X1TS U1056 ( .A0(n646), .A1(n592), .B0(n645), .B1(n904), .Y(n647) );
AOI21X1TS U1057 ( .A0(n672), .A1(n648), .B0(n647), .Y(n649) );
OAI22X1TS U1058 ( .A0(n652), .A1(n592), .B0(n651), .B1(n904), .Y(n653) );
AOI21X1TS U1059 ( .A0(n672), .A1(n654), .B0(n653), .Y(n655) );
OAI22X1TS U1060 ( .A0(n658), .A1(n592), .B0(n657), .B1(n904), .Y(n659) );
AOI21X1TS U1061 ( .A0(n672), .A1(n660), .B0(n659), .Y(n661) );
OAI22X1TS U1062 ( .A0(n664), .A1(n592), .B0(n663), .B1(n904), .Y(n665) );
AOI21X1TS U1063 ( .A0(n672), .A1(n666), .B0(n665), .Y(n667) );
OAI22X1TS U1064 ( .A0(n905), .A1(n592), .B0(n669), .B1(n904), .Y(n670) );
AOI21X1TS U1065 ( .A0(n672), .A1(n671), .B0(n670), .Y(n673) );
NOR2X1TS U1066 ( .A(DmP_mant_SFG_SWR[14]), .B(n959), .Y(n680) );
NAND2X1TS U1067 ( .A(DmP_mant_SFG_SWR[13]), .B(n919), .Y(n861) );
OAI22X1TS U1068 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n957), .B0(n676), .B1(n675),
.Y(n860) );
AOI22X1TS U1069 ( .A0(DMP_SFG[11]), .A1(n958), .B0(n861), .B1(n860), .Y(n681) );
AOI222X4TS U1070 ( .A0(n859), .A1(n919), .B0(n859), .B1(n958), .C0(n919),
.C1(n958), .Y(n683) );
AOI22X1TS U1071 ( .A0(n407), .A1(n681), .B0(n683), .B1(n1065), .Y(n679) );
CLKAND2X2TS U1072 ( .A(DmP_mant_SFG_SWR[14]), .B(n959), .Y(n682) );
OAI21XLTS U1073 ( .A0(n680), .A1(n682), .B0(n679), .Y(n678) );
OAI31X1TS U1074 ( .A0(n680), .A1(n679), .A2(n682), .B0(n678), .Y(
Raw_mant_SGF[14]) );
NOR2X1TS U1075 ( .A(DmP_mant_SFG_SWR[16]), .B(n962), .Y(n686) );
NAND2X1TS U1076 ( .A(DmP_mant_SFG_SWR[15]), .B(n921), .Y(n866) );
OAI22X1TS U1077 ( .A0(DmP_mant_SFG_SWR[14]), .A1(n959), .B0(n682), .B1(n681),
.Y(n865) );
AOI22X1TS U1078 ( .A0(DMP_SFG[13]), .A1(n963), .B0(n866), .B1(n865), .Y(n687) );
AOI222X4TS U1079 ( .A0(n864), .A1(n921), .B0(n864), .B1(n963), .C0(n921),
.C1(n963), .Y(n689) );
AOI22X1TS U1080 ( .A0(n407), .A1(n687), .B0(n689), .B1(n1065), .Y(n685) );
CLKAND2X2TS U1081 ( .A(DmP_mant_SFG_SWR[16]), .B(n962), .Y(n688) );
OAI31X1TS U1082 ( .A0(n686), .A1(n685), .A2(n688), .B0(n684), .Y(
Raw_mant_SGF[16]) );
NOR2X1TS U1083 ( .A(DmP_mant_SFG_SWR[18]), .B(n971), .Y(n692) );
NAND2X1TS U1084 ( .A(DmP_mant_SFG_SWR[17]), .B(n922), .Y(n871) );
OAI22X1TS U1085 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n962), .B0(n688), .B1(n687),
.Y(n870) );
AOI22X1TS U1086 ( .A0(DMP_SFG[15]), .A1(n967), .B0(n871), .B1(n870), .Y(n693) );
AOI222X4TS U1087 ( .A0(n869), .A1(n922), .B0(n869), .B1(n967), .C0(n922),
.C1(n967), .Y(n695) );
AOI22X1TS U1088 ( .A0(n407), .A1(n693), .B0(n695), .B1(n1065), .Y(n691) );
CLKAND2X2TS U1089 ( .A(DmP_mant_SFG_SWR[18]), .B(n971), .Y(n694) );
OAI31X1TS U1090 ( .A0(n692), .A1(n691), .A2(n694), .B0(n690), .Y(
Raw_mant_SGF[18]) );
NOR2X1TS U1091 ( .A(DmP_mant_SFG_SWR[20]), .B(n974), .Y(n698) );
NAND2X1TS U1092 ( .A(DmP_mant_SFG_SWR[19]), .B(n925), .Y(n876) );
OAI22X1TS U1093 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n971), .B0(n694), .B1(n693),
.Y(n875) );
AOI22X1TS U1094 ( .A0(DMP_SFG[17]), .A1(n972), .B0(n876), .B1(n875), .Y(n699) );
AOI222X4TS U1095 ( .A0(n874), .A1(n925), .B0(n874), .B1(n972), .C0(n925),
.C1(n972), .Y(n701) );
AOI22X1TS U1096 ( .A0(n407), .A1(n699), .B0(n701), .B1(n1065), .Y(n697) );
CLKAND2X2TS U1097 ( .A(DmP_mant_SFG_SWR[20]), .B(n974), .Y(n700) );
OAI31X1TS U1098 ( .A0(n698), .A1(n697), .A2(n700), .B0(n696), .Y(
Raw_mant_SGF[20]) );
NOR2X1TS U1099 ( .A(DmP_mant_SFG_SWR[22]), .B(n995), .Y(n704) );
NAND2X1TS U1100 ( .A(DmP_mant_SFG_SWR[21]), .B(n926), .Y(n881) );
OAI22X1TS U1101 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n974), .B0(n700), .B1(n699),
.Y(n880) );
AOI22X1TS U1102 ( .A0(DMP_SFG[19]), .A1(n975), .B0(n881), .B1(n880), .Y(n731) );
AOI222X4TS U1103 ( .A0(n879), .A1(n926), .B0(n879), .B1(n975), .C0(n926),
.C1(n975), .Y(n733) );
AOI22X1TS U1104 ( .A0(n407), .A1(n731), .B0(n733), .B1(n890), .Y(n703) );
CLKAND2X2TS U1105 ( .A(DmP_mant_SFG_SWR[22]), .B(n995), .Y(n732) );
OAI31X1TS U1106 ( .A0(n704), .A1(n703), .A2(n732), .B0(n702), .Y(
Raw_mant_SGF[22]) );
INVX2TS U1107 ( .A(n705), .Y(n707) );
NOR2XLTS U1108 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[11]), .Y(n706) );
OAI22X1TS U1109 ( .A0(n708), .A1(n707), .B0(n706), .B1(n720), .Y(n709) );
AOI21X1TS U1110 ( .A0(n710), .A1(Raw_mant_NRM_SWR[3]), .B0(n709), .Y(n711)
);
OAI211X1TS U1111 ( .A0(n713), .A1(n1003), .B0(n712), .C0(n711), .Y(
LZD_raw_out_EWR[2]) );
INVX2TS U1112 ( .A(n714), .Y(n716) );
NOR3X1TS U1113 ( .A(Raw_mant_NRM_SWR[2]), .B(n730), .C(n961), .Y(n726) );
OAI211X1TS U1114 ( .A0(n721), .A1(n720), .B0(n719), .C0(n718), .Y(
LZD_raw_out_EWR[3]) );
OAI31X1TS U1115 ( .A0(n724), .A1(Raw_mant_NRM_SWR[10]), .A2(n723), .B0(n722),
.Y(n725) );
AOI211X1TS U1116 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n727), .B0(n726), .C0(n725),
.Y(n728) );
OAI211X1TS U1117 ( .A0(n1030), .A1(n730), .B0(n729), .C0(n728), .Y(
LZD_raw_out_EWR[4]) );
NOR2X1TS U1118 ( .A(DmP_mant_SFG_SWR[24]), .B(n1001), .Y(n889) );
NAND2X1TS U1119 ( .A(DmP_mant_SFG_SWR[23]), .B(n939), .Y(n886) );
OAI22X1TS U1120 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n995), .B0(n732), .B1(n731),
.Y(n885) );
AOI22X1TS U1121 ( .A0(DMP_SFG[21]), .A1(n996), .B0(n886), .B1(n885), .Y(n892) );
AOI21X1TS U1122 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1001), .B0(n892), .Y(n734)
);
AOI222X4TS U1123 ( .A0(n884), .A1(n939), .B0(n884), .B1(n996), .C0(n939),
.C1(n996), .Y(n891) );
OAI32X1TS U1124 ( .A0(n890), .A1(n889), .A2(n734), .B0(n775), .B1(n855), .Y(
n735) );
NOR2BX1TS U1125 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n736)
);
XOR2X1TS U1126 ( .A(n920), .B(n736), .Y(DP_OP_15J181_122_6956_n16) );
NOR2BX1TS U1127 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n737)
);
XOR2X1TS U1128 ( .A(n920), .B(n737), .Y(DP_OP_15J181_122_6956_n17) );
OR2X1TS U1129 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n738) );
XOR2X1TS U1130 ( .A(n920), .B(n738), .Y(DP_OP_15J181_122_6956_n18) );
NOR2BX1TS U1131 ( .AN(exp_rslt_NRM2_EW1[7]), .B(
array_comparators_GTComparator_N0), .Y(formatted_number_W[30]) );
AOI2BB1XLTS U1132 ( .A0N(array_comparators_LTComparator_N0), .A1N(
SIGN_FLAG_SHT1SHT2), .B0(array_comparators_GTComparator_N0), .Y(
formatted_number_W[31]) );
XOR2XLTS U1133 ( .A(DMP_EXP_EWSW[27]), .B(DmP_EXP_EWSW[27]), .Y(n739) );
XOR2XLTS U1134 ( .A(intadd_429_n1), .B(n739), .Y(Shift_amount_EXP_EW[4]) );
AOI22X1TS U1135 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n908), .B1(n913), .Y(n1067)
);
XNOR2X1TS U1136 ( .A(add_subt), .B(Data_Y[31]), .Y(n1033) );
XNOR2X1TS U1137 ( .A(intDX_EWSW[31]), .B(n1066), .Y(OP_FLAG_INIT) );
AOI22X1TS U1138 ( .A0(intDX_EWSW[23]), .A1(intDY_EWSW[23]), .B0(n942), .B1(
n994), .Y(n746) );
AOI22X1TS U1139 ( .A0(n933), .A1(intDY_EWSW[15]), .B0(n987), .B1(
intDY_EWSW[13]), .Y(n740) );
OAI221XLTS U1140 ( .A0(n933), .A1(intDY_EWSW[15]), .B0(n987), .B1(
intDY_EWSW[13]), .C0(n740), .Y(n745) );
AOI22X1TS U1141 ( .A0(n979), .A1(intDY_EWSW[10]), .B0(n934), .B1(
intDY_EWSW[2]), .Y(n741) );
AOI22X1TS U1142 ( .A0(n397), .A1(intDY_EWSW[9]), .B0(n982), .B1(
intDY_EWSW[11]), .Y(n742) );
OAI221XLTS U1143 ( .A0(n397), .A1(intDY_EWSW[9]), .B0(n982), .B1(
intDY_EWSW[11]), .C0(n742), .Y(n743) );
NOR4X1TS U1144 ( .A(n746), .B(n745), .C(n744), .D(n743), .Y(n774) );
AOI22X1TS U1145 ( .A0(n993), .A1(intDY_EWSW[7]), .B0(n984), .B1(
intDY_EWSW[14]), .Y(n747) );
AOI22X1TS U1146 ( .A0(n992), .A1(intDY_EWSW[5]), .B0(n935), .B1(
intDY_EWSW[4]), .Y(n748) );
OAI221XLTS U1147 ( .A0(n992), .A1(intDY_EWSW[5]), .B0(n935), .B1(
intDY_EWSW[4]), .C0(n748), .Y(n753) );
AOI22X1TS U1148 ( .A0(n932), .A1(intDY_EWSW[3]), .B0(n986), .B1(
intDY_EWSW[26]), .Y(n749) );
AOI22X1TS U1149 ( .A0(n978), .A1(intDY_EWSW[1]), .B0(n938), .B1(
intDY_EWSW[0]), .Y(n750) );
OAI221XLTS U1150 ( .A0(n978), .A1(intDY_EWSW[1]), .B0(n938), .B1(
intDY_EWSW[0]), .C0(n750), .Y(n751) );
NOR4X1TS U1151 ( .A(n754), .B(n753), .C(n752), .D(n751), .Y(n773) );
AOI22X1TS U1152 ( .A0(n900), .A1(intDY_EWSW[28]), .B0(n936), .B1(
intDY_EWSW[6]), .Y(n755) );
AOI22X1TS U1153 ( .A0(n928), .A1(intDY_EWSW[18]), .B0(n989), .B1(
intDY_EWSW[29]), .Y(n756) );
OAI221XLTS U1154 ( .A0(n928), .A1(intDY_EWSW[18]), .B0(n989), .B1(
intDY_EWSW[29]), .C0(n756), .Y(n761) );
AOI22X1TS U1155 ( .A0(n931), .A1(intDY_EWSW[27]), .B0(n985), .B1(
intDY_EWSW[19]), .Y(n757) );
AOI22X1TS U1156 ( .A0(n981), .A1(intDY_EWSW[25]), .B0(n937), .B1(
intDY_EWSW[24]), .Y(n758) );
OAI221XLTS U1157 ( .A0(n981), .A1(intDY_EWSW[25]), .B0(n937), .B1(
intDY_EWSW[24]), .C0(n758), .Y(n759) );
NOR4X1TS U1158 ( .A(n762), .B(n761), .C(n760), .D(n759), .Y(n772) );
AOI22X1TS U1159 ( .A0(n929), .A1(intDY_EWSW[20]), .B0(n990), .B1(
intDY_EWSW[30]), .Y(n763) );
AOI22X1TS U1160 ( .A0(n396), .A1(intDY_EWSW[8]), .B0(n988), .B1(
intDY_EWSW[21]), .Y(n764) );
OAI221XLTS U1161 ( .A0(n396), .A1(intDY_EWSW[8]), .B0(n988), .B1(
intDY_EWSW[21]), .C0(n764), .Y(n769) );
AOI22X1TS U1162 ( .A0(n980), .A1(intDY_EWSW[17]), .B0(n991), .B1(
intDY_EWSW[16]), .Y(n765) );
AOI22X1TS U1163 ( .A0(n930), .A1(intDY_EWSW[22]), .B0(n983), .B1(
intDY_EWSW[12]), .Y(n766) );
OAI221XLTS U1164 ( .A0(n930), .A1(intDY_EWSW[22]), .B0(n983), .B1(
intDY_EWSW[12]), .C0(n766), .Y(n767) );
NOR4X1TS U1165 ( .A(n770), .B(n769), .C(n768), .D(n767), .Y(n771) );
NAND4XLTS U1166 ( .A(n774), .B(n773), .C(n772), .D(n771), .Y(n841) );
NOR2BX1TS U1167 ( .AN(OP_FLAG_INIT), .B(n841), .Y(ZERO_FLAG_INIT) );
NOR2BX1TS U1168 ( .AN(Shift_reg_FLAGS_7[3]), .B(Shift_reg_FLAGS_7[0]), .Y(
n_21_net_) );
AOI21X1TS U1169 ( .A0(n775), .A1(n405), .B0(n855), .Y(ADD_OVRFLW_SGF) );
NOR2X1TS U1170 ( .A(n1023), .B(intDX_EWSW[25]), .Y(n835) );
NOR2XLTS U1171 ( .A(n835), .B(intDY_EWSW[24]), .Y(n776) );
AOI22X1TS U1172 ( .A0(intDX_EWSW[25]), .A1(n1023), .B0(intDX_EWSW[24]), .B1(
n776), .Y(n780) );
NAND2BXLTS U1173 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n777) );
OAI21X1TS U1174 ( .A0(intDX_EWSW[26]), .A1(n1028), .B0(n777), .Y(n836) );
NAND3XLTS U1175 ( .A(n1028), .B(n777), .C(intDX_EWSW[26]), .Y(n779) );
NAND2BXLTS U1176 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n778) );
OAI211XLTS U1177 ( .A0(n780), .A1(n836), .B0(n779), .C0(n778), .Y(n785) );
NOR2X1TS U1178 ( .A(n927), .B(intDX_EWSW[30]), .Y(n783) );
NOR2X1TS U1179 ( .A(n973), .B(intDX_EWSW[29]), .Y(n781) );
AOI211X1TS U1180 ( .A0(intDY_EWSW[28]), .A1(n900), .B0(n783), .C0(n781), .Y(
n834) );
AOI2BB2X1TS U1181 ( .B0(n785), .B1(n834), .A0N(n784), .A1N(n783), .Y(n840)
);
NOR2X1TS U1182 ( .A(n1021), .B(intDX_EWSW[17]), .Y(n821) );
NOR2X1TS U1183 ( .A(n1024), .B(intDX_EWSW[11]), .Y(n800) );
AOI21X1TS U1184 ( .A0(intDY_EWSW[10]), .A1(n979), .B0(n800), .Y(n805) );
OAI211XLTS U1185 ( .A0(intDX_EWSW[8]), .A1(n1020), .B0(n802), .C0(n805), .Y(
n816) );
OAI2BB1X1TS U1186 ( .A0N(n992), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]), .Y(
n786) );
OAI22X1TS U1187 ( .A0(intDY_EWSW[4]), .A1(n786), .B0(n992), .B1(
intDY_EWSW[5]), .Y(n797) );
OAI2BB1X1TS U1188 ( .A0N(n993), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]), .Y(
n787) );
OAI22X1TS U1189 ( .A0(intDY_EWSW[6]), .A1(n787), .B0(n993), .B1(
intDY_EWSW[7]), .Y(n796) );
OAI2BB2XLTS U1190 ( .B0(intDY_EWSW[0]), .B1(n788), .A0N(intDX_EWSW[1]),
.A1N(n1025), .Y(n790) );
NAND2BXLTS U1191 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n789) );
OAI211XLTS U1192 ( .A0(n1026), .A1(intDX_EWSW[3]), .B0(n790), .C0(n789), .Y(
n793) );
OAI21XLTS U1193 ( .A0(intDX_EWSW[3]), .A1(n1026), .B0(intDX_EWSW[2]), .Y(
n791) );
AOI2BB2XLTS U1194 ( .B0(intDX_EWSW[3]), .B1(n1026), .A0N(intDY_EWSW[2]),
.A1N(n791), .Y(n792) );
AOI222X1TS U1195 ( .A0(intDY_EWSW[4]), .A1(n935), .B0(n793), .B1(n792), .C0(
intDY_EWSW[5]), .C1(n992), .Y(n795) );
AOI22X1TS U1196 ( .A0(intDY_EWSW[7]), .A1(n993), .B0(intDY_EWSW[6]), .B1(
n936), .Y(n794) );
OAI32X1TS U1197 ( .A0(n797), .A1(n796), .A2(n795), .B0(n794), .B1(n796), .Y(
n815) );
OA22X1TS U1198 ( .A0(n945), .A1(intDX_EWSW[14]), .B0(n1027), .B1(
intDX_EWSW[15]), .Y(n812) );
NAND2BXLTS U1199 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n798) );
OAI21XLTS U1200 ( .A0(intDX_EWSW[13]), .A1(n1012), .B0(intDX_EWSW[12]), .Y(
n799) );
OAI2BB2XLTS U1201 ( .B0(intDY_EWSW[12]), .B1(n799), .A0N(intDX_EWSW[13]),
.A1N(n1012), .Y(n811) );
NOR2XLTS U1202 ( .A(n800), .B(intDY_EWSW[10]), .Y(n801) );
AOI22X1TS U1203 ( .A0(intDX_EWSW[11]), .A1(n1024), .B0(intDX_EWSW[10]), .B1(
n801), .Y(n807) );
NAND2BXLTS U1204 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n804) );
NAND3XLTS U1205 ( .A(n1020), .B(n802), .C(intDX_EWSW[8]), .Y(n803) );
AOI21X1TS U1206 ( .A0(n804), .A1(n803), .B0(n814), .Y(n806) );
OAI2BB2XLTS U1207 ( .B0(n807), .B1(n814), .A0N(n806), .A1N(n805), .Y(n810)
);
OAI2BB2XLTS U1208 ( .B0(intDY_EWSW[14]), .B1(n808), .A0N(intDX_EWSW[15]),
.A1N(n1027), .Y(n809) );
AOI211X1TS U1209 ( .A0(n812), .A1(n811), .B0(n810), .C0(n809), .Y(n813) );
OAI31X1TS U1210 ( .A0(n816), .A1(n815), .A2(n814), .B0(n813), .Y(n819) );
OA22X1TS U1211 ( .A0(n1016), .A1(intDX_EWSW[22]), .B0(n942), .B1(
intDX_EWSW[23]), .Y(n832) );
NAND2BXLTS U1212 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n817) );
NAND2BXLTS U1213 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n823) );
OAI21X1TS U1214 ( .A0(intDX_EWSW[18]), .A1(n1022), .B0(n823), .Y(n827) );
NAND3BXLTS U1215 ( .AN(n821), .B(n819), .C(n818), .Y(n839) );
OAI2BB2XLTS U1216 ( .B0(intDY_EWSW[20]), .B1(n820), .A0N(intDX_EWSW[21]),
.A1N(n1013), .Y(n831) );
AOI22X1TS U1217 ( .A0(intDX_EWSW[17]), .A1(n1021), .B0(intDX_EWSW[16]), .B1(
n822), .Y(n825) );
AOI32X1TS U1218 ( .A0(n1022), .A1(n823), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n944), .Y(n824) );
OAI32X1TS U1219 ( .A0(n827), .A1(n826), .A2(n825), .B0(n824), .B1(n826), .Y(
n830) );
OAI21XLTS U1220 ( .A0(intDX_EWSW[23]), .A1(n942), .B0(intDX_EWSW[22]), .Y(
n828) );
OAI2BB2XLTS U1221 ( .B0(intDY_EWSW[22]), .B1(n828), .A0N(intDX_EWSW[23]),
.A1N(n942), .Y(n829) );
AOI211X1TS U1222 ( .A0(n832), .A1(n831), .B0(n830), .C0(n829), .Y(n838) );
NAND2BXLTS U1223 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n833) );
NAND4BBX1TS U1224 ( .AN(n836), .BN(n835), .C(n834), .D(n833), .Y(n837) );
AOI21X1TS U1225 ( .A0(n841), .A1(n902), .B0(intDX_EWSW[31]), .Y(n842) );
AOI21X1TS U1226 ( .A0(n1066), .A1(n897), .B0(n842), .Y(SIGN_FLAG_INIT) );
NAND2X1TS U1227 ( .A(N59), .B(n855), .Y(n843) );
XNOR2X1TS U1228 ( .A(n843), .B(N60), .Y(Raw_mant_SGF[1]) );
OAI21XLTS U1229 ( .A0(DMP_SFG[0]), .A1(DmP_mant_SFG_SWR[2]), .B0(n844), .Y(
n847) );
NAND2X1TS U1230 ( .A(n845), .B(n855), .Y(n846) );
XOR2XLTS U1231 ( .A(n847), .B(n846), .Y(Raw_mant_SGF[2]) );
AOI22X1TS U1232 ( .A0(n855), .A1(n849), .B0(n848), .B1(n1065), .Y(n852) );
OAI21XLTS U1233 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n917), .B0(n850), .Y(n851)
);
XOR2XLTS U1234 ( .A(n852), .B(n851), .Y(Raw_mant_SGF[9]) );
AOI22X1TS U1235 ( .A0(n855), .A1(n854), .B0(n853), .B1(n1065), .Y(n858) );
OAI21XLTS U1236 ( .A0(DmP_mant_SFG_SWR[11]), .A1(n918), .B0(n856), .Y(n857)
);
XOR2XLTS U1237 ( .A(n858), .B(n857), .Y(Raw_mant_SGF[11]) );
AOI22X1TS U1238 ( .A0(n407), .A1(n860), .B0(n859), .B1(n1065), .Y(n863) );
OAI21XLTS U1239 ( .A0(DmP_mant_SFG_SWR[13]), .A1(n919), .B0(n861), .Y(n862)
);
XOR2XLTS U1240 ( .A(n863), .B(n862), .Y(Raw_mant_SGF[13]) );
AOI22X1TS U1241 ( .A0(n407), .A1(n865), .B0(n864), .B1(n1065), .Y(n868) );
OAI21XLTS U1242 ( .A0(DmP_mant_SFG_SWR[15]), .A1(n921), .B0(n866), .Y(n867)
);
XOR2XLTS U1243 ( .A(n868), .B(n867), .Y(Raw_mant_SGF[15]) );
AOI22X1TS U1244 ( .A0(n407), .A1(n870), .B0(n869), .B1(n1065), .Y(n873) );
OAI21XLTS U1245 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n922), .B0(n871), .Y(n872)
);
AOI22X1TS U1246 ( .A0(n407), .A1(n875), .B0(n874), .B1(n890), .Y(n878) );
OAI21XLTS U1247 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n925), .B0(n876), .Y(n877)
);
AOI22X1TS U1248 ( .A0(n407), .A1(n880), .B0(n879), .B1(n1065), .Y(n883) );
OAI21XLTS U1249 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n926), .B0(n881), .Y(n882)
);
AOI22X1TS U1250 ( .A0(n407), .A1(n885), .B0(n884), .B1(n1065), .Y(n888) );
OAI21XLTS U1251 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n939), .B0(n886), .Y(n887)
);
AOI21X1TS U1252 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1001), .B0(n889), .Y(n894)
);
AOI22X1TS U1253 ( .A0(n407), .A1(n892), .B0(n891), .B1(n890), .Y(n893) );
CLKBUFX3TS U1254 ( .A(n895), .Y(n896) );
AOI22X1TS U1255 ( .A0(n896), .A1(n1029), .B0(n938), .B1(n902), .Y(
DmP_INIT_EWSW[0]) );
AOI22X1TS U1256 ( .A0(n896), .A1(n1025), .B0(n978), .B1(n902), .Y(
DmP_INIT_EWSW[1]) );
AOI22X1TS U1257 ( .A0(n896), .A1(n1014), .B0(n934), .B1(n902), .Y(
DmP_INIT_EWSW[2]) );
AOI22X1TS U1258 ( .A0(n896), .A1(n1026), .B0(n932), .B1(n901), .Y(
DmP_INIT_EWSW[3]) );
AOI22X1TS U1259 ( .A0(n896), .A1(n1009), .B0(n935), .B1(n897), .Y(
DmP_INIT_EWSW[4]) );
AOI22X1TS U1260 ( .A0(n896), .A1(n1005), .B0(n992), .B1(n898), .Y(
DmP_INIT_EWSW[5]) );
AOI22X1TS U1261 ( .A0(n896), .A1(n1007), .B0(n936), .B1(n898), .Y(
DmP_INIT_EWSW[6]) );
AOI22X1TS U1262 ( .A0(n896), .A1(n1004), .B0(n993), .B1(n897), .Y(
DmP_INIT_EWSW[7]) );
AOI22X1TS U1263 ( .A0(n896), .A1(n1020), .B0(n396), .B1(n898), .Y(
DmP_INIT_EWSW[8]) );
AOI22X1TS U1264 ( .A0(n896), .A1(n1017), .B0(n397), .B1(n901), .Y(
DmP_INIT_EWSW[9]) );
AOI22X1TS U1265 ( .A0(n895), .A1(n1010), .B0(n979), .B1(n898), .Y(
DmP_INIT_EWSW[10]) );
AOI22X1TS U1266 ( .A0(n895), .A1(n1024), .B0(n982), .B1(n897), .Y(
DmP_INIT_EWSW[11]) );
AOI22X1TS U1267 ( .A0(n895), .A1(n1019), .B0(n983), .B1(n901), .Y(
DmP_INIT_EWSW[12]) );
AOI22X1TS U1268 ( .A0(n895), .A1(n1012), .B0(n987), .B1(n901), .Y(
DmP_INIT_EWSW[13]) );
AOI22X1TS U1269 ( .A0(n895), .A1(n945), .B0(n984), .B1(n897), .Y(
DmP_INIT_EWSW[14]) );
AOI22X1TS U1270 ( .A0(n895), .A1(n1027), .B0(n933), .B1(n897), .Y(
DmP_INIT_EWSW[15]) );
AOI22X1TS U1271 ( .A0(n895), .A1(n1008), .B0(n991), .B1(n898), .Y(
DmP_INIT_EWSW[16]) );
AOI22X1TS U1272 ( .A0(n895), .A1(n1021), .B0(n980), .B1(n898), .Y(
DmP_INIT_EWSW[17]) );
AOI22X1TS U1273 ( .A0(n895), .A1(n1022), .B0(n928), .B1(n897), .Y(
DmP_INIT_EWSW[18]) );
AOI22X1TS U1274 ( .A0(n895), .A1(n944), .B0(n985), .B1(n901), .Y(
DmP_INIT_EWSW[19]) );
BUFX4TS U1275 ( .A(n895), .Y(n899) );
AOI22X1TS U1276 ( .A0(n393), .A1(n1015), .B0(n929), .B1(n901), .Y(
DmP_INIT_EWSW[20]) );
AOI22X1TS U1277 ( .A0(n393), .A1(n1013), .B0(n988), .B1(n898), .Y(
DmP_INIT_EWSW[21]) );
AOI22X1TS U1278 ( .A0(n393), .A1(n1016), .B0(n930), .B1(n901), .Y(
DmP_INIT_EWSW[22]) );
AOI22X1TS U1279 ( .A0(n393), .A1(n942), .B0(n994), .B1(n897), .Y(
DmP_INIT_EWSW[23]) );
AOI22X1TS U1280 ( .A0(n393), .A1(n1011), .B0(n937), .B1(n898), .Y(
DmP_INIT_EWSW[24]) );
AOI22X1TS U1281 ( .A0(n393), .A1(n1023), .B0(n981), .B1(n901), .Y(
DmP_INIT_EWSW[25]) );
AOI22X1TS U1282 ( .A0(n393), .A1(n1028), .B0(n986), .B1(n897), .Y(
DmP_INIT_EWSW[26]) );
AOI22X1TS U1283 ( .A0(n393), .A1(n1018), .B0(n931), .B1(n898), .Y(
DmP_INIT_EWSW[27]) );
AOI22X1TS U1284 ( .A0(n393), .A1(n938), .B0(n1029), .B1(n897), .Y(
DMP_INIT_EWSW[0]) );
AOI22X1TS U1285 ( .A0(n393), .A1(n978), .B0(n1025), .B1(n901), .Y(
DMP_INIT_EWSW[1]) );
AOI22X1TS U1286 ( .A0(n393), .A1(n934), .B0(n1014), .B1(n898), .Y(
DMP_INIT_EWSW[2]) );
AOI22X1TS U1287 ( .A0(n393), .A1(n932), .B0(n1026), .B1(n898), .Y(
DMP_INIT_EWSW[3]) );
AOI22X1TS U1288 ( .A0(n393), .A1(n935), .B0(n1009), .B1(n898), .Y(
DMP_INIT_EWSW[4]) );
AOI22X1TS U1289 ( .A0(n393), .A1(n992), .B0(n1005), .B1(n898), .Y(
DMP_INIT_EWSW[5]) );
AOI22X1TS U1290 ( .A0(n393), .A1(n936), .B0(n1007), .B1(n898), .Y(
DMP_INIT_EWSW[6]) );
AOI22X1TS U1291 ( .A0(n393), .A1(n993), .B0(n1004), .B1(n901), .Y(
DMP_INIT_EWSW[7]) );
AOI22X1TS U1292 ( .A0(n393), .A1(n396), .B0(n1020), .B1(n897), .Y(
DMP_INIT_EWSW[8]) );
AOI22X1TS U1293 ( .A0(n393), .A1(n397), .B0(n1017), .B1(n898), .Y(
DMP_INIT_EWSW[9]) );
AOI22X1TS U1294 ( .A0(n393), .A1(n979), .B0(n1010), .B1(n901), .Y(
DMP_INIT_EWSW[10]) );
AOI22X1TS U1295 ( .A0(n393), .A1(n982), .B0(n1024), .B1(n897), .Y(
DMP_INIT_EWSW[11]) );
AOI22X1TS U1296 ( .A0(n899), .A1(n983), .B0(n1019), .B1(n898), .Y(
DMP_INIT_EWSW[12]) );
AOI22X1TS U1297 ( .A0(n899), .A1(n987), .B0(n1012), .B1(n901), .Y(
DMP_INIT_EWSW[13]) );
AOI22X1TS U1298 ( .A0(n899), .A1(n984), .B0(n945), .B1(n897), .Y(
DMP_INIT_EWSW[14]) );
AOI22X1TS U1299 ( .A0(n899), .A1(n933), .B0(n1027), .B1(n897), .Y(
DMP_INIT_EWSW[15]) );
AOI22X1TS U1300 ( .A0(n899), .A1(n991), .B0(n1008), .B1(n898), .Y(
DMP_INIT_EWSW[16]) );
AOI22X1TS U1301 ( .A0(n899), .A1(n980), .B0(n1021), .B1(n901), .Y(
DMP_INIT_EWSW[17]) );
AOI22X1TS U1302 ( .A0(n899), .A1(n928), .B0(n1022), .B1(n898), .Y(
DMP_INIT_EWSW[18]) );
AOI22X1TS U1303 ( .A0(n899), .A1(n985), .B0(n944), .B1(n901), .Y(
DMP_INIT_EWSW[19]) );
AOI22X1TS U1304 ( .A0(n899), .A1(n929), .B0(n1015), .B1(n898), .Y(
DMP_INIT_EWSW[20]) );
AOI22X1TS U1305 ( .A0(n899), .A1(n988), .B0(n1013), .B1(n901), .Y(
DMP_INIT_EWSW[21]) );
AOI22X1TS U1306 ( .A0(n899), .A1(n930), .B0(n1016), .B1(n901), .Y(
DMP_INIT_EWSW[22]) );
AOI22X1TS U1307 ( .A0(n899), .A1(n994), .B0(n942), .B1(n898), .Y(
DMP_INIT_EWSW[23]) );
AOI22X1TS U1308 ( .A0(n899), .A1(n937), .B0(n1011), .B1(n901), .Y(
DMP_INIT_EWSW[24]) );
AOI22X1TS U1309 ( .A0(n899), .A1(n981), .B0(n1023), .B1(n897), .Y(
DMP_INIT_EWSW[25]) );
AOI22X1TS U1310 ( .A0(n899), .A1(n986), .B0(n1028), .B1(n897), .Y(
DMP_INIT_EWSW[26]) );
AOI22X1TS U1311 ( .A0(n899), .A1(n931), .B0(n1018), .B1(n897), .Y(
DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U1312 ( .B0(n902), .B1(n900), .A0N(n902), .A1N(intDY_EWSW[28]),
.Y(DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U1313 ( .B0(n902), .B1(n989), .A0N(n902), .A1N(intDY_EWSW[29]),
.Y(DMP_INIT_EWSW[29]) );
OAI2BB2XLTS U1314 ( .B0(n902), .B1(n990), .A0N(n902), .A1N(intDY_EWSW[30]),
.Y(DMP_INIT_EWSW[30]) );
OAI22X1TS U1315 ( .A0(n903), .A1(n399), .B0(n906), .B1(n904), .Y(
Data_array_SWR[24]) );
OAI222X1TS U1316 ( .A0(n583), .A1(n906), .B0(n399), .B1(n905), .C0(n904),
.C1(n903), .Y(Data_array_SWR[23]) );
CLKAND2X2TS U1317 ( .A(n402), .B(sftr_odat_SHT2_SWR[6]), .Y(
formatted_number_W[4]) );
CLKAND2X2TS U1318 ( .A(n402), .B(sftr_odat_SHT2_SWR[7]), .Y(
formatted_number_W[5]) );
CLKAND2X2TS U1319 ( .A(n402), .B(sftr_odat_SHT2_SWR[18]), .Y(
formatted_number_W[16]) );
CLKAND2X2TS U1320 ( .A(n402), .B(sftr_odat_SHT2_SWR[19]), .Y(
formatted_number_W[17]) );
INVX2TS U1322 ( .A(n908), .Y(n911) );
AOI22X1TS U1323 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n943), .B0(
beg_OP), .B1(n913), .Y(n910) );
OAI22X1TS U1324 ( .A0(n911), .A1(n910), .B0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n909), .Y(n389) );
NAND2BXLTS U1325 ( .AN(busy), .B(n912), .Y(n_7_net_) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk30.tcl_GATED_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__OR2B_PP_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_PP_SYMBOL_V
|
module premuat_16(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
input signed [27:0] i_8;
input signed [27:0] i_9;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
output signed [27:0] o_8;
output signed [27:0] o_9;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [27:0] o1;
reg signed [27:0] o2;
reg signed [27:0] o3;
reg signed [27:0] o4;
reg signed [27:0] o5;
reg signed [27:0] o6;
reg signed [27:0] o7;
reg signed [27:0] o8;
reg signed [27:0] o9;
reg signed [27:0] o10;
reg signed [27:0] o11;
reg signed [27:0] o12;
reg signed [27:0] o13;
reg signed [27:0] o14;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1 =i_2;
o2 =i_4;
o3 =i_6;
o4 =i_8;
o5 =i_10;
o6 =i_12;
o7 =i_14;
o8 =i_1;
o9 =i_3;
o10=i_5;
o11=i_7;
o12=i_9;
o13=i_11;
o14=i_13;
end
else
begin
o1 =i_8;
o2 =i_1;
o3 =i_9;
o4 =i_2;
o5 =i_10;
o6 =i_3;
o7 =i_11;
o8 =i_4;
o9 =i_12;
o10=i_5;
o11=i_13;
o12=i_6;
o13=i_14;
o14=i_7;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=enable?o7:i_7;
assign o_8=enable?o8:i_8;
assign o_9=enable?o9:i_9;
assign o_10=enable?o10:i_10;
assign o_11=enable?o11:i_11;
assign o_12=enable?o12:i_12;
assign o_13=enable?o13:i_13;
assign o_14=enable?o14:i_14;
assign o_15=i_15;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V
/**
* lsbufiso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP ,
A ,
DESTPWR,
VPWR ,
VGND ,
DESTVPB,
VPB ,
VNB
);
// Module ports
output X ;
input SLEEP ;
input A ;
input DESTPWR;
input VPWR ;
input VGND ;
input DESTVPB;
input VPB ;
input VNB ;
// Local signals
wire sleepb ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
wire and0_out_X ;
// Name Output Other arguments
not not0 (sleepb , SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, sleepb, DESTPWR, VGND );
and and0 (and0_out_X , pwrgood_pp1_out_sleepb, pwrgood_pp0_out_A);
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp2 (X , and0_out_X, DESTPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_FUNCTIONAL_PP_V
|
//
// 2 read-port, 1 write-port ram
//
// reads are synchronous
//
//
module bsg_mem_2r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
wire unused = reset_i;
if ((width_p == 32) && (els_p == 32))
begin: macro
// synopsys translate_off
initial
begin
assert(read_write_same_addr_p==0)
else
begin
$error("%L: this configuration does not permit simultaneous read and writes! (%m)");
$finish();
end
end
// synopsys translate_on
// use two 1R1W rams to create
tsmc180_2rf_lg5_w32_m1_all mem0
(
// read port
.CLKA (clk_i)
,.AA (r0_addr_i)
,.CENA(~r0_v_i)
// output
,.QA (r0_data_o)
// write port
,.CLKB(clk_i)
,.AB (w_addr_i)
,.DB (w_data_i)
,.CENB(~w_v_i)
);
tsmc180_2rf_lg5_w32_m1_all mem1
(
// read port
.CLKA (clk_i)
,.AA (r1_addr_i)
,.CENA(~r1_v_i)
// output
,.QA (r1_data_o)
// write port
,.CLKB(clk_i)
,.AB (w_addr_i)
,.DB (w_data_i)
,.CENB(~w_v_i)
);
end // block: macro
else
begin: notmacro
bsg_mem_2r1w_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
end
//synopsys translate_off
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)"
,width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_2r1w_sync)
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:27 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_sim_netlist.v
// Design : ip_design_led_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_led_controller_0_0,led_controller_v1_0,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(LEDs_out,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready,
s00_axi_aclk,
s00_axi_aresetn);
output [7:0]LEDs_out;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [3:0]s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [3:0]s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s00_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 S00_AXI_RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW" *) input s00_axi_aresetn;
wire \<const0> ;
wire [7:0]LEDs_out;
wire s00_axi_aclk;
wire [3:0]s00_axi_araddr;
wire s00_axi_aresetn;
wire s00_axi_arready;
wire s00_axi_arvalid;
wire [3:0]s00_axi_awaddr;
wire s00_axi_awready;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire s00_axi_wready;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
assign s00_axi_bresp[1] = \<const0> ;
assign s00_axi_bresp[0] = \<const0> ;
assign s00_axi_rresp[1] = \<const0> ;
assign s00_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 inst
(.LEDs_out(LEDs_out),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WREADY(s00_axi_wready),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_araddr(s00_axi_araddr[3:2]),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_awaddr(s00_axi_awaddr[3:2]),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rready(s00_axi_rready),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0
(S_AXI_ARREADY,
S_AXI_AWREADY,
S_AXI_WREADY,
LEDs_out,
s00_axi_rdata,
s00_axi_rvalid,
s00_axi_bvalid,
s00_axi_arvalid,
s00_axi_aclk,
s00_axi_awaddr,
s00_axi_awvalid,
s00_axi_wvalid,
s00_axi_wdata,
s00_axi_araddr,
s00_axi_wstrb,
s00_axi_aresetn,
s00_axi_bready,
s00_axi_rready);
output S_AXI_ARREADY;
output S_AXI_AWREADY;
output S_AXI_WREADY;
output [7:0]LEDs_out;
output [31:0]s00_axi_rdata;
output s00_axi_rvalid;
output s00_axi_bvalid;
input s00_axi_arvalid;
input s00_axi_aclk;
input [1:0]s00_axi_awaddr;
input s00_axi_awvalid;
input s00_axi_wvalid;
input [31:0]s00_axi_wdata;
input [1:0]s00_axi_araddr;
input [3:0]s00_axi_wstrb;
input s00_axi_aresetn;
input s00_axi_bready;
input s00_axi_rready;
wire [7:0]LEDs_out;
wire S_AXI_ARREADY;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire s00_axi_aclk;
wire [1:0]s00_axi_araddr;
wire s00_axi_aresetn;
wire s00_axi_arvalid;
wire [1:0]s00_axi_awaddr;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI led_controller_v1_0_S00_AXI_inst
(.LEDs_out(LEDs_out),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WREADY(S_AXI_WREADY),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rready(s00_axi_rready),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI
(S_AXI_ARREADY,
S_AXI_AWREADY,
S_AXI_WREADY,
LEDs_out,
s00_axi_rdata,
s00_axi_rvalid,
s00_axi_bvalid,
s00_axi_arvalid,
s00_axi_aclk,
s00_axi_awaddr,
s00_axi_awvalid,
s00_axi_wvalid,
s00_axi_wdata,
s00_axi_araddr,
s00_axi_wstrb,
s00_axi_aresetn,
s00_axi_bready,
s00_axi_rready);
output S_AXI_ARREADY;
output S_AXI_AWREADY;
output S_AXI_WREADY;
output [7:0]LEDs_out;
output [31:0]s00_axi_rdata;
output s00_axi_rvalid;
output s00_axi_bvalid;
input s00_axi_arvalid;
input s00_axi_aclk;
input [1:0]s00_axi_awaddr;
input s00_axi_awvalid;
input s00_axi_wvalid;
input [31:0]s00_axi_wdata;
input [1:0]s00_axi_araddr;
input [3:0]s00_axi_wstrb;
input s00_axi_aresetn;
input s00_axi_bready;
input s00_axi_rready;
wire [7:0]LEDs_out;
wire S_AXI_ARREADY;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire aw_en_i_1_n_0;
wire aw_en_reg_n_0;
wire [3:2]axi_araddr;
wire \axi_araddr[2]_i_1_n_0 ;
wire \axi_araddr[3]_i_1_n_0 ;
wire axi_arready_i_1_n_0;
wire \axi_awaddr[2]_i_1_n_0 ;
wire \axi_awaddr[3]_i_1_n_0 ;
wire axi_awready0;
wire axi_bvalid_i_1_n_0;
wire axi_rvalid_i_1_n_0;
wire axi_wready0;
wire [1:0]p_0_in;
wire [31:7]p_1_in;
wire [31:0]reg_data_out;
wire s00_axi_aclk;
wire [1:0]s00_axi_araddr;
wire s00_axi_aresetn;
wire s00_axi_arvalid;
wire [1:0]s00_axi_awaddr;
wire s00_axi_awvalid;
wire s00_axi_bready;
wire s00_axi_bvalid;
wire [31:0]s00_axi_rdata;
wire s00_axi_rready;
wire s00_axi_rvalid;
wire [31:0]s00_axi_wdata;
wire [3:0]s00_axi_wstrb;
wire s00_axi_wvalid;
wire [31:8]slv_reg0;
wire \slv_reg0[7]_i_1_n_0 ;
wire [31:0]slv_reg1;
wire \slv_reg1[15]_i_1_n_0 ;
wire \slv_reg1[23]_i_1_n_0 ;
wire \slv_reg1[31]_i_1_n_0 ;
wire \slv_reg1[7]_i_1_n_0 ;
wire [31:0]slv_reg2;
wire \slv_reg2[15]_i_1_n_0 ;
wire \slv_reg2[23]_i_1_n_0 ;
wire \slv_reg2[31]_i_1_n_0 ;
wire \slv_reg2[7]_i_1_n_0 ;
wire [31:0]slv_reg3;
wire \slv_reg3[15]_i_1_n_0 ;
wire \slv_reg3[23]_i_1_n_0 ;
wire \slv_reg3[31]_i_1_n_0 ;
wire \slv_reg3[7]_i_1_n_0 ;
wire slv_reg_rden__0;
wire slv_reg_wren__0;
LUT6 #(
.INIT(64'hF7FFC4CCC4CCC4CC))
aw_en_i_1
(.I0(s00_axi_wvalid),
.I1(aw_en_reg_n_0),
.I2(S_AXI_AWREADY),
.I3(s00_axi_awvalid),
.I4(s00_axi_bready),
.I5(s00_axi_bvalid),
.O(aw_en_i_1_n_0));
FDSE aw_en_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(aw_en_i_1_n_0),
.Q(aw_en_reg_n_0),
.S(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFB08))
\axi_araddr[2]_i_1
(.I0(s00_axi_araddr[0]),
.I1(s00_axi_arvalid),
.I2(S_AXI_ARREADY),
.I3(axi_araddr[2]),
.O(\axi_araddr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFB08))
\axi_araddr[3]_i_1
(.I0(s00_axi_araddr[1]),
.I1(s00_axi_arvalid),
.I2(S_AXI_ARREADY),
.I3(axi_araddr[3]),
.O(\axi_araddr[3]_i_1_n_0 ));
FDRE \axi_araddr_reg[2]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\axi_araddr[2]_i_1_n_0 ),
.Q(axi_araddr[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_araddr_reg[3]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\axi_araddr[3]_i_1_n_0 ),
.Q(axi_araddr[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h2))
axi_arready_i_1
(.I0(s00_axi_arvalid),
.I1(S_AXI_ARREADY),
.O(axi_arready_i_1_n_0));
FDRE axi_arready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_arready_i_1_n_0),
.Q(S_AXI_ARREADY),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFBFFFFFF08000000))
\axi_awaddr[2]_i_1
(.I0(s00_axi_awaddr[0]),
.I1(s00_axi_awvalid),
.I2(S_AXI_AWREADY),
.I3(aw_en_reg_n_0),
.I4(s00_axi_wvalid),
.I5(p_0_in[0]),
.O(\axi_awaddr[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFBFFFFFF08000000))
\axi_awaddr[3]_i_1
(.I0(s00_axi_awaddr[1]),
.I1(s00_axi_awvalid),
.I2(S_AXI_AWREADY),
.I3(aw_en_reg_n_0),
.I4(s00_axi_wvalid),
.I5(p_0_in[1]),
.O(\axi_awaddr[3]_i_1_n_0 ));
FDRE \axi_awaddr_reg[2]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\axi_awaddr[2]_i_1_n_0 ),
.Q(p_0_in[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_awaddr_reg[3]
(.C(s00_axi_aclk),
.CE(1'b1),
.D(\axi_awaddr[3]_i_1_n_0 ),
.Q(p_0_in[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
axi_awready_i_1
(.I0(s00_axi_awvalid),
.I1(S_AXI_AWREADY),
.I2(aw_en_reg_n_0),
.I3(s00_axi_wvalid),
.O(axi_awready0));
FDRE axi_awready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_awready0),
.Q(S_AXI_AWREADY),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000FFFF80008000))
axi_bvalid_i_1
(.I0(S_AXI_WREADY),
.I1(S_AXI_AWREADY),
.I2(s00_axi_awvalid),
.I3(s00_axi_wvalid),
.I4(s00_axi_bready),
.I5(s00_axi_bvalid),
.O(axi_bvalid_i_1_n_0));
FDRE axi_bvalid_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_i_1_n_0),
.Q(s00_axi_bvalid),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[0]_i_1
(.I0(slv_reg1[0]),
.I1(LEDs_out[0]),
.I2(slv_reg3[0]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[0]),
.O(reg_data_out[0]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[10]_i_1
(.I0(slv_reg1[10]),
.I1(slv_reg0[10]),
.I2(slv_reg3[10]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[10]),
.O(reg_data_out[10]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[11]_i_1
(.I0(slv_reg1[11]),
.I1(slv_reg0[11]),
.I2(slv_reg3[11]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[11]),
.O(reg_data_out[11]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[12]_i_1
(.I0(slv_reg1[12]),
.I1(slv_reg0[12]),
.I2(slv_reg3[12]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[12]),
.O(reg_data_out[12]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[13]_i_1
(.I0(slv_reg1[13]),
.I1(slv_reg0[13]),
.I2(slv_reg3[13]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[13]),
.O(reg_data_out[13]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[14]_i_1
(.I0(slv_reg1[14]),
.I1(slv_reg0[14]),
.I2(slv_reg3[14]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[14]),
.O(reg_data_out[14]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[15]_i_1
(.I0(slv_reg1[15]),
.I1(slv_reg0[15]),
.I2(slv_reg3[15]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[15]),
.O(reg_data_out[15]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[16]_i_1
(.I0(slv_reg1[16]),
.I1(slv_reg0[16]),
.I2(slv_reg3[16]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[16]),
.O(reg_data_out[16]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[17]_i_1
(.I0(slv_reg1[17]),
.I1(slv_reg0[17]),
.I2(slv_reg3[17]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[17]),
.O(reg_data_out[17]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[18]_i_1
(.I0(slv_reg1[18]),
.I1(slv_reg0[18]),
.I2(slv_reg3[18]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[18]),
.O(reg_data_out[18]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[19]_i_1
(.I0(slv_reg1[19]),
.I1(slv_reg0[19]),
.I2(slv_reg3[19]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[19]),
.O(reg_data_out[19]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[1]_i_1
(.I0(slv_reg1[1]),
.I1(LEDs_out[1]),
.I2(slv_reg3[1]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[1]),
.O(reg_data_out[1]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[20]_i_1
(.I0(slv_reg1[20]),
.I1(slv_reg0[20]),
.I2(slv_reg3[20]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[20]),
.O(reg_data_out[20]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[21]_i_1
(.I0(slv_reg1[21]),
.I1(slv_reg0[21]),
.I2(slv_reg3[21]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[21]),
.O(reg_data_out[21]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[22]_i_1
(.I0(slv_reg1[22]),
.I1(slv_reg0[22]),
.I2(slv_reg3[22]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[22]),
.O(reg_data_out[22]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[23]_i_1
(.I0(slv_reg1[23]),
.I1(slv_reg0[23]),
.I2(slv_reg3[23]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[23]),
.O(reg_data_out[23]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[24]_i_1
(.I0(slv_reg1[24]),
.I1(slv_reg0[24]),
.I2(slv_reg3[24]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[24]),
.O(reg_data_out[24]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[25]_i_1
(.I0(slv_reg1[25]),
.I1(slv_reg0[25]),
.I2(slv_reg3[25]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[25]),
.O(reg_data_out[25]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[26]_i_1
(.I0(slv_reg1[26]),
.I1(slv_reg0[26]),
.I2(slv_reg3[26]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[26]),
.O(reg_data_out[26]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[27]_i_1
(.I0(slv_reg1[27]),
.I1(slv_reg0[27]),
.I2(slv_reg3[27]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[27]),
.O(reg_data_out[27]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[28]_i_1
(.I0(slv_reg1[28]),
.I1(slv_reg0[28]),
.I2(slv_reg3[28]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[28]),
.O(reg_data_out[28]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[29]_i_1
(.I0(slv_reg1[29]),
.I1(slv_reg0[29]),
.I2(slv_reg3[29]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[29]),
.O(reg_data_out[29]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[2]_i_1
(.I0(slv_reg1[2]),
.I1(LEDs_out[2]),
.I2(slv_reg3[2]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[2]),
.O(reg_data_out[2]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[30]_i_1
(.I0(slv_reg1[30]),
.I1(slv_reg0[30]),
.I2(slv_reg3[30]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[30]),
.O(reg_data_out[30]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[31]_i_1
(.I0(slv_reg1[31]),
.I1(slv_reg0[31]),
.I2(slv_reg3[31]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[31]),
.O(reg_data_out[31]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[3]_i_1
(.I0(slv_reg1[3]),
.I1(LEDs_out[3]),
.I2(slv_reg3[3]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[3]),
.O(reg_data_out[3]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[4]_i_1
(.I0(slv_reg1[4]),
.I1(LEDs_out[4]),
.I2(slv_reg3[4]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[4]),
.O(reg_data_out[4]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[5]_i_1
(.I0(slv_reg1[5]),
.I1(LEDs_out[5]),
.I2(slv_reg3[5]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[5]),
.O(reg_data_out[5]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[6]_i_1
(.I0(slv_reg1[6]),
.I1(LEDs_out[6]),
.I2(slv_reg3[6]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[6]),
.O(reg_data_out[6]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[7]_i_1
(.I0(slv_reg1[7]),
.I1(LEDs_out[7]),
.I2(slv_reg3[7]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[7]),
.O(reg_data_out[7]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[8]_i_1
(.I0(slv_reg1[8]),
.I1(slv_reg0[8]),
.I2(slv_reg3[8]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[8]),
.O(reg_data_out[8]));
LUT6 #(
.INIT(64'hF0AAFFCCF0AA00CC))
\axi_rdata[9]_i_1
(.I0(slv_reg1[9]),
.I1(slv_reg0[9]),
.I2(slv_reg3[9]),
.I3(axi_araddr[3]),
.I4(axi_araddr[2]),
.I5(slv_reg2[9]),
.O(reg_data_out[9]));
FDRE \axi_rdata_reg[0]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[0]),
.Q(s00_axi_rdata[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[10]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[10]),
.Q(s00_axi_rdata[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[11]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[11]),
.Q(s00_axi_rdata[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[12]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[12]),
.Q(s00_axi_rdata[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[13]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[13]),
.Q(s00_axi_rdata[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[14]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[14]),
.Q(s00_axi_rdata[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[15]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[15]),
.Q(s00_axi_rdata[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[16]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[16]),
.Q(s00_axi_rdata[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[17]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[17]),
.Q(s00_axi_rdata[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[18]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[18]),
.Q(s00_axi_rdata[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[19]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[19]),
.Q(s00_axi_rdata[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[1]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[1]),
.Q(s00_axi_rdata[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[20]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[20]),
.Q(s00_axi_rdata[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[21]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[21]),
.Q(s00_axi_rdata[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[22]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[22]),
.Q(s00_axi_rdata[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[23]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[23]),
.Q(s00_axi_rdata[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[24]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[24]),
.Q(s00_axi_rdata[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[25]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[25]),
.Q(s00_axi_rdata[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[26]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[26]),
.Q(s00_axi_rdata[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[27]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[27]),
.Q(s00_axi_rdata[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[28]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[28]),
.Q(s00_axi_rdata[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[29]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[29]),
.Q(s00_axi_rdata[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[2]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[2]),
.Q(s00_axi_rdata[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[30]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[30]),
.Q(s00_axi_rdata[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[31]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[31]),
.Q(s00_axi_rdata[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[3]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[3]),
.Q(s00_axi_rdata[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[4]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[4]),
.Q(s00_axi_rdata[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[5]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[5]),
.Q(s00_axi_rdata[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[6]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[6]),
.Q(s00_axi_rdata[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[7]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[7]),
.Q(s00_axi_rdata[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[8]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[8]),
.Q(s00_axi_rdata[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \axi_rdata_reg[9]
(.C(s00_axi_aclk),
.CE(slv_reg_rden__0),
.D(reg_data_out[9]),
.Q(s00_axi_rdata[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h08F8))
axi_rvalid_i_1
(.I0(S_AXI_ARREADY),
.I1(s00_axi_arvalid),
.I2(s00_axi_rvalid),
.I3(s00_axi_rready),
.O(axi_rvalid_i_1_n_0));
FDRE axi_rvalid_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_i_1_n_0),
.Q(s00_axi_rvalid),
.R(\slv_reg0[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h4000))
axi_wready_i_1
(.I0(S_AXI_WREADY),
.I1(s00_axi_wvalid),
.I2(s00_axi_awvalid),
.I3(aw_en_reg_n_0),
.O(axi_wready0));
FDRE axi_wready_reg
(.C(s00_axi_aclk),
.CE(1'b1),
.D(axi_wready0),
.Q(S_AXI_WREADY),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0200))
\slv_reg0[15]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(p_0_in[0]),
.I3(s00_axi_wstrb[1]),
.O(p_1_in[15]));
LUT4 #(
.INIT(16'h0200))
\slv_reg0[23]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(p_0_in[0]),
.I3(s00_axi_wstrb[2]),
.O(p_1_in[23]));
LUT4 #(
.INIT(16'h0200))
\slv_reg0[31]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(p_0_in[0]),
.I3(s00_axi_wstrb[3]),
.O(p_1_in[31]));
LUT1 #(
.INIT(2'h1))
\slv_reg0[7]_i_1
(.I0(s00_axi_aresetn),
.O(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0200))
\slv_reg0[7]_i_2
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(p_0_in[0]),
.I3(s00_axi_wstrb[0]),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h8000))
\slv_reg0[7]_i_3
(.I0(S_AXI_WREADY),
.I1(S_AXI_AWREADY),
.I2(s00_axi_awvalid),
.I3(s00_axi_wvalid),
.O(slv_reg_wren__0));
FDRE \slv_reg0_reg[0]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[0]),
.Q(LEDs_out[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[10]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[10]),
.Q(slv_reg0[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[11]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[11]),
.Q(slv_reg0[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[12]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[12]),
.Q(slv_reg0[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[13]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[13]),
.Q(slv_reg0[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[14]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[14]),
.Q(slv_reg0[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[15]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[15]),
.Q(slv_reg0[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[16]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[16]),
.Q(slv_reg0[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[17]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[17]),
.Q(slv_reg0[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[18]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[18]),
.Q(slv_reg0[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[19]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[19]),
.Q(slv_reg0[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[1]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[1]),
.Q(LEDs_out[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[20]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[20]),
.Q(slv_reg0[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[21]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[21]),
.Q(slv_reg0[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[22]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[22]),
.Q(slv_reg0[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[23]
(.C(s00_axi_aclk),
.CE(p_1_in[23]),
.D(s00_axi_wdata[23]),
.Q(slv_reg0[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[24]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[24]),
.Q(slv_reg0[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[25]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[25]),
.Q(slv_reg0[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[26]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[26]),
.Q(slv_reg0[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[27]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[27]),
.Q(slv_reg0[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[28]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[28]),
.Q(slv_reg0[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[29]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[29]),
.Q(slv_reg0[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[2]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[2]),
.Q(LEDs_out[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[30]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[30]),
.Q(slv_reg0[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[31]
(.C(s00_axi_aclk),
.CE(p_1_in[31]),
.D(s00_axi_wdata[31]),
.Q(slv_reg0[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[3]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[3]),
.Q(LEDs_out[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[4]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[4]),
.Q(LEDs_out[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[5]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[5]),
.Q(LEDs_out[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[6]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[6]),
.Q(LEDs_out[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[7]
(.C(s00_axi_aclk),
.CE(p_1_in[7]),
.D(s00_axi_wdata[7]),
.Q(LEDs_out[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[8]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[8]),
.Q(slv_reg0[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg0_reg[9]
(.C(s00_axi_aclk),
.CE(p_1_in[15]),
.D(s00_axi_wdata[9]),
.Q(slv_reg0[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
\slv_reg1[15]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[1]),
.I3(p_0_in[0]),
.O(\slv_reg1[15]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
\slv_reg1[23]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[2]),
.I3(p_0_in[0]),
.O(\slv_reg1[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
\slv_reg1[31]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[3]),
.I3(p_0_in[0]),
.O(\slv_reg1[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2000))
\slv_reg1[7]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[0]),
.I3(p_0_in[0]),
.O(\slv_reg1[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[0]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[0]),
.Q(slv_reg1[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[10]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[10]),
.Q(slv_reg1[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[11]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[11]),
.Q(slv_reg1[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[12]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[12]),
.Q(slv_reg1[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[13]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[13]),
.Q(slv_reg1[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[14]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[14]),
.Q(slv_reg1[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[15]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[15]),
.Q(slv_reg1[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[16]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[16]),
.Q(slv_reg1[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[17]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[17]),
.Q(slv_reg1[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[18]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[18]),
.Q(slv_reg1[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[19]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[19]),
.Q(slv_reg1[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[1]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[1]),
.Q(slv_reg1[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[20]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[20]),
.Q(slv_reg1[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[21]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[21]),
.Q(slv_reg1[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[22]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[22]),
.Q(slv_reg1[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[23]
(.C(s00_axi_aclk),
.CE(\slv_reg1[23]_i_1_n_0 ),
.D(s00_axi_wdata[23]),
.Q(slv_reg1[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[24]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[24]),
.Q(slv_reg1[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[25]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[25]),
.Q(slv_reg1[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[26]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[26]),
.Q(slv_reg1[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[27]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[27]),
.Q(slv_reg1[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[28]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[28]),
.Q(slv_reg1[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[29]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[29]),
.Q(slv_reg1[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[2]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[2]),
.Q(slv_reg1[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[30]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[30]),
.Q(slv_reg1[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[31]
(.C(s00_axi_aclk),
.CE(\slv_reg1[31]_i_1_n_0 ),
.D(s00_axi_wdata[31]),
.Q(slv_reg1[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[3]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[3]),
.Q(slv_reg1[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[4]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[4]),
.Q(slv_reg1[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[5]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[5]),
.Q(slv_reg1[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[6]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[6]),
.Q(slv_reg1[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[7]
(.C(s00_axi_aclk),
.CE(\slv_reg1[7]_i_1_n_0 ),
.D(s00_axi_wdata[7]),
.Q(slv_reg1[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[8]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[8]),
.Q(slv_reg1[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg1_reg[9]
(.C(s00_axi_aclk),
.CE(\slv_reg1[15]_i_1_n_0 ),
.D(s00_axi_wdata[9]),
.Q(slv_reg1[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0080))
\slv_reg2[15]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[1]),
.I3(p_0_in[0]),
.O(\slv_reg2[15]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0080))
\slv_reg2[23]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[2]),
.I3(p_0_in[0]),
.O(\slv_reg2[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0080))
\slv_reg2[31]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[3]),
.I3(p_0_in[0]),
.O(\slv_reg2[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0080))
\slv_reg2[7]_i_1
(.I0(slv_reg_wren__0),
.I1(p_0_in[1]),
.I2(s00_axi_wstrb[0]),
.I3(p_0_in[0]),
.O(\slv_reg2[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[0]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[0]),
.Q(slv_reg2[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[10]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[10]),
.Q(slv_reg2[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[11]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[11]),
.Q(slv_reg2[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[12]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[12]),
.Q(slv_reg2[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[13]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[13]),
.Q(slv_reg2[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[14]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[14]),
.Q(slv_reg2[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[15]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[15]),
.Q(slv_reg2[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[16]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[16]),
.Q(slv_reg2[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[17]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[17]),
.Q(slv_reg2[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[18]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[18]),
.Q(slv_reg2[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[19]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[19]),
.Q(slv_reg2[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[1]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[1]),
.Q(slv_reg2[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[20]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[20]),
.Q(slv_reg2[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[21]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[21]),
.Q(slv_reg2[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[22]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[22]),
.Q(slv_reg2[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[23]
(.C(s00_axi_aclk),
.CE(\slv_reg2[23]_i_1_n_0 ),
.D(s00_axi_wdata[23]),
.Q(slv_reg2[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[24]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[24]),
.Q(slv_reg2[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[25]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[25]),
.Q(slv_reg2[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[26]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[26]),
.Q(slv_reg2[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[27]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[27]),
.Q(slv_reg2[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[28]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[28]),
.Q(slv_reg2[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[29]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[29]),
.Q(slv_reg2[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[2]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[2]),
.Q(slv_reg2[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[30]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[30]),
.Q(slv_reg2[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[31]
(.C(s00_axi_aclk),
.CE(\slv_reg2[31]_i_1_n_0 ),
.D(s00_axi_wdata[31]),
.Q(slv_reg2[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[3]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[3]),
.Q(slv_reg2[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[4]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[4]),
.Q(slv_reg2[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[5]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[5]),
.Q(slv_reg2[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[6]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[6]),
.Q(slv_reg2[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[7]
(.C(s00_axi_aclk),
.CE(\slv_reg2[7]_i_1_n_0 ),
.D(s00_axi_wdata[7]),
.Q(slv_reg2[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[8]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[8]),
.Q(slv_reg2[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg2_reg[9]
(.C(s00_axi_aclk),
.CE(\slv_reg2[15]_i_1_n_0 ),
.D(s00_axi_wdata[9]),
.Q(slv_reg2[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8000))
\slv_reg3[15]_i_1
(.I0(slv_reg_wren__0),
.I1(s00_axi_wstrb[1]),
.I2(p_0_in[0]),
.I3(p_0_in[1]),
.O(\slv_reg3[15]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8000))
\slv_reg3[23]_i_1
(.I0(slv_reg_wren__0),
.I1(s00_axi_wstrb[2]),
.I2(p_0_in[0]),
.I3(p_0_in[1]),
.O(\slv_reg3[23]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8000))
\slv_reg3[31]_i_1
(.I0(slv_reg_wren__0),
.I1(s00_axi_wstrb[3]),
.I2(p_0_in[0]),
.I3(p_0_in[1]),
.O(\slv_reg3[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'h8000))
\slv_reg3[7]_i_1
(.I0(slv_reg_wren__0),
.I1(s00_axi_wstrb[0]),
.I2(p_0_in[0]),
.I3(p_0_in[1]),
.O(\slv_reg3[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[0]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[0]),
.Q(slv_reg3[0]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[10]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[10]),
.Q(slv_reg3[10]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[11]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[11]),
.Q(slv_reg3[11]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[12]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[12]),
.Q(slv_reg3[12]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[13]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[13]),
.Q(slv_reg3[13]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[14]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[14]),
.Q(slv_reg3[14]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[15]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[15]),
.Q(slv_reg3[15]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[16]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[16]),
.Q(slv_reg3[16]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[17]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[17]),
.Q(slv_reg3[17]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[18]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[18]),
.Q(slv_reg3[18]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[19]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[19]),
.Q(slv_reg3[19]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[1]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[1]),
.Q(slv_reg3[1]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[20]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[20]),
.Q(slv_reg3[20]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[21]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[21]),
.Q(slv_reg3[21]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[22]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[22]),
.Q(slv_reg3[22]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[23]
(.C(s00_axi_aclk),
.CE(\slv_reg3[23]_i_1_n_0 ),
.D(s00_axi_wdata[23]),
.Q(slv_reg3[23]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[24]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[24]),
.Q(slv_reg3[24]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[25]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[25]),
.Q(slv_reg3[25]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[26]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[26]),
.Q(slv_reg3[26]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[27]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[27]),
.Q(slv_reg3[27]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[28]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[28]),
.Q(slv_reg3[28]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[29]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[29]),
.Q(slv_reg3[29]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[2]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[2]),
.Q(slv_reg3[2]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[30]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[30]),
.Q(slv_reg3[30]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[31]
(.C(s00_axi_aclk),
.CE(\slv_reg3[31]_i_1_n_0 ),
.D(s00_axi_wdata[31]),
.Q(slv_reg3[31]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[3]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[3]),
.Q(slv_reg3[3]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[4]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[4]),
.Q(slv_reg3[4]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[5]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[5]),
.Q(slv_reg3[5]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[6]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[6]),
.Q(slv_reg3[6]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[7]
(.C(s00_axi_aclk),
.CE(\slv_reg3[7]_i_1_n_0 ),
.D(s00_axi_wdata[7]),
.Q(slv_reg3[7]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[8]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[8]),
.Q(slv_reg3[8]),
.R(\slv_reg0[7]_i_1_n_0 ));
FDRE \slv_reg3_reg[9]
(.C(s00_axi_aclk),
.CE(\slv_reg3[15]_i_1_n_0 ),
.D(s00_axi_wdata[9]),
.Q(slv_reg3[9]),
.R(\slv_reg0[7]_i_1_n_0 ));
LUT3 #(
.INIT(8'h40))
slv_reg_rden
(.I0(s00_axi_rvalid),
.I1(s00_axi_arvalid),
.I2(S_AXI_ARREADY),
.O(slv_reg_rden__0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_2_V
`define SKY130_FD_SC_LP__O41AI_2_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_2_V
|
module wb_stream_writer_ctrl
#(parameter WB_AW = 32,
parameter WB_DW = 32,
parameter FIFO_AW = 0,
parameter MAX_BURST_LEN = 0)
(//Stream data output
input wb_clk_i,
input wb_rst_i,
output [WB_AW-1:0] wbm_adr_o,
output [WB_DW-1:0] wbm_dat_o,
output [WB_DW/8-1:0] wbm_sel_o,
output wbm_we_o ,
output wbm_cyc_o,
output wbm_stb_o,
output reg [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
input [WB_DW-1:0] wbm_dat_i,
input wbm_ack_i,
input wbm_err_i,
//FIFO interface
output [WB_DW-1:0] fifo_d,
output fifo_wr,
input [FIFO_AW:0] fifo_cnt,
//Configuration interface
output reg busy,
input enable,
output reg [WB_DW-1:0] tx_cnt,
input [WB_AW-1:0] start_adr,
input [WB_AW-1:0] buf_size,
input [WB_AW-1:0] burst_size);
wire active;
wire timeout = 1'b0;
reg last_adr;
reg [$clog2(MAX_BURST_LEN-1):0] burst_cnt;
//FSM states
localparam S_IDLE = 0;
localparam S_ACTIVE = 1;
reg [1:0] state;
wire burst_end = (burst_cnt == burst_size-1);
wire fifo_ready = (fifo_cnt+burst_size <= 2**FIFO_AW);
always @(active or burst_end) begin
wbm_cti_o = !active ? 3'b000 :
burst_end ? 3'b111 :
3'b010; //LINEAR_BURST;
end
assign active = (state == S_ACTIVE);
assign fifo_d = wbm_dat_i;
assign fifo_wr = wbm_ack_i;
assign wbm_sel_o = 4'hf;
assign wbm_we_o = 1'b0;
assign wbm_cyc_o = active;
assign wbm_stb_o = active;
assign wbm_bte_o = 2'b00;
assign wbm_dat_o = {WB_DW{1'b0}};
assign wbm_adr_o = start_adr + tx_cnt*4;
always @(posedge wb_clk_i) begin
//Address generation
last_adr = (tx_cnt == buf_size[WB_AW-1:2]-1);
if (wbm_ack_i)
if (last_adr)
tx_cnt <= 0;
else
tx_cnt <= tx_cnt+1;
//Burst counter
if(!active)
burst_cnt <= 0;
else
if(wbm_ack_i)
burst_cnt <= burst_cnt + 1;
//FSM
case (state)
S_IDLE : begin
if (busy & fifo_ready)
state <= S_ACTIVE;
if (enable)
busy <= 1'b1;
end
S_ACTIVE : begin
if (burst_end & wbm_ack_i) begin
state <= S_IDLE;
if (last_adr)
busy <= 1'b0;
end
end
default : begin
state <= S_IDLE;
end
endcase // case (state)
if(wb_rst_i) begin
state <= S_IDLE;
tx_cnt <= 0;
busy <= 1'b0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_V
|
// system_acl_iface_acl_kernel_clk.v
// Generated using ACDS version 14.0 200 at 2015.05.04.18:11:39
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_clk (
output wire kernel_clk2x_clk, // kernel_clk2x.clk
input wire pll_refclk_clk, // pll_refclk.clk
output wire ctrl_waitrequest, // ctrl.waitrequest
output wire [31:0] ctrl_readdata, // .readdata
output wire ctrl_readdatavalid, // .readdatavalid
input wire [0:0] ctrl_burstcount, // .burstcount
input wire [31:0] ctrl_writedata, // .writedata
input wire [10:0] ctrl_address, // .address
input wire ctrl_write, // .write
input wire ctrl_read, // .read
input wire [3:0] ctrl_byteenable, // .byteenable
input wire ctrl_debugaccess, // .debugaccess
output wire kernel_clk_clk, // kernel_clk.clk
output wire kernel_pll_locked_export, // kernel_pll_locked.export
input wire clk_clk, // clk.clk
input wire reset_reset_n // reset.reset_n
);
wire [63:0] pll_reconfig_0_reconfig_to_pll_reconfig_to_pll; // pll_reconfig_0:reconfig_to_pll -> kernel_pll:reconfig_to_pll
wire [63:0] kernel_pll_reconfig_from_pll_reconfig_from_pll; // kernel_pll:reconfig_from_pll -> pll_reconfig_0:reconfig_from_pll
wire kernel_pll_outclk0_clk; // kernel_pll:outclk_0 -> global_routing_kernel_clk:s
wire kernel_pll_outclk1_clk; // kernel_pll:outclk_1 -> [counter:clk2x, global_routing_kernel_clk2x:s]
wire kernel_pll_locked_export_signal; // kernel_pll:locked -> pll_lock_avs_0:lock
wire [0:0] ctrl_m0_burstcount; // ctrl:m0_burstcount -> mm_interconnect_0:ctrl_m0_burstcount
wire ctrl_m0_waitrequest; // mm_interconnect_0:ctrl_m0_waitrequest -> ctrl:m0_waitrequest
wire [10:0] ctrl_m0_address; // ctrl:m0_address -> mm_interconnect_0:ctrl_m0_address
wire [31:0] ctrl_m0_writedata; // ctrl:m0_writedata -> mm_interconnect_0:ctrl_m0_writedata
wire ctrl_m0_write; // ctrl:m0_write -> mm_interconnect_0:ctrl_m0_write
wire ctrl_m0_read; // ctrl:m0_read -> mm_interconnect_0:ctrl_m0_read
wire [31:0] ctrl_m0_readdata; // mm_interconnect_0:ctrl_m0_readdata -> ctrl:m0_readdata
wire ctrl_m0_debugaccess; // ctrl:m0_debugaccess -> mm_interconnect_0:ctrl_m0_debugaccess
wire [3:0] ctrl_m0_byteenable; // ctrl:m0_byteenable -> mm_interconnect_0:ctrl_m0_byteenable
wire ctrl_m0_readdatavalid; // mm_interconnect_0:ctrl_m0_readdatavalid -> ctrl:m0_readdatavalid
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest; // pll_reconfig_0:mgmt_waitrequest -> mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_waitrequest
wire [31:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_writedata -> pll_reconfig_0:mgmt_writedata
wire [5:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_address -> pll_reconfig_0:mgmt_address
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_write -> pll_reconfig_0:mgmt_write
wire mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read; // mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_read -> pll_reconfig_0:mgmt_read
wire [31:0] mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata; // pll_reconfig_0:mgmt_readdata -> mm_interconnect_0:pll_reconfig_0_mgmt_avalon_slave_readdata
wire [31:0] mm_interconnect_0_pll_rom_s1_writedata; // mm_interconnect_0:pll_rom_s1_writedata -> pll_rom:writedata
wire [7:0] mm_interconnect_0_pll_rom_s1_address; // mm_interconnect_0:pll_rom_s1_address -> pll_rom:address
wire mm_interconnect_0_pll_rom_s1_chipselect; // mm_interconnect_0:pll_rom_s1_chipselect -> pll_rom:chipselect
wire mm_interconnect_0_pll_rom_s1_clken; // mm_interconnect_0:pll_rom_s1_clken -> pll_rom:clken
wire mm_interconnect_0_pll_rom_s1_write; // mm_interconnect_0:pll_rom_s1_write -> pll_rom:write
wire [31:0] mm_interconnect_0_pll_rom_s1_readdata; // pll_rom:readdata -> mm_interconnect_0:pll_rom_s1_readdata
wire mm_interconnect_0_pll_rom_s1_debugaccess; // mm_interconnect_0:pll_rom_s1_debugaccess -> pll_rom:debugaccess
wire [3:0] mm_interconnect_0_pll_rom_s1_byteenable; // mm_interconnect_0:pll_rom_s1_byteenable -> pll_rom:byteenable
wire mm_interconnect_0_counter_s_waitrequest; // counter:slave_waitrequest -> mm_interconnect_0:counter_s_waitrequest
wire [31:0] mm_interconnect_0_counter_s_writedata; // mm_interconnect_0:counter_s_writedata -> counter:slave_writedata
wire [1:0] mm_interconnect_0_counter_s_address; // mm_interconnect_0:counter_s_address -> counter:slave_address
wire mm_interconnect_0_counter_s_write; // mm_interconnect_0:counter_s_write -> counter:slave_write
wire mm_interconnect_0_counter_s_read; // mm_interconnect_0:counter_s_read -> counter:slave_read
wire [31:0] mm_interconnect_0_counter_s_readdata; // counter:slave_readdata -> mm_interconnect_0:counter_s_readdata
wire mm_interconnect_0_counter_s_readdatavalid; // counter:slave_readdatavalid -> mm_interconnect_0:counter_s_readdatavalid
wire [3:0] mm_interconnect_0_counter_s_byteenable; // mm_interconnect_0:counter_s_byteenable -> counter:slave_byteenable
wire mm_interconnect_0_pll_sw_reset_s_waitrequest; // pll_sw_reset:slave_waitrequest -> mm_interconnect_0:pll_sw_reset_s_waitrequest
wire [31:0] mm_interconnect_0_pll_sw_reset_s_writedata; // mm_interconnect_0:pll_sw_reset_s_writedata -> pll_sw_reset:slave_writedata
wire mm_interconnect_0_pll_sw_reset_s_write; // mm_interconnect_0:pll_sw_reset_s_write -> pll_sw_reset:slave_write
wire mm_interconnect_0_pll_sw_reset_s_read; // mm_interconnect_0:pll_sw_reset_s_read -> pll_sw_reset:slave_read
wire [31:0] mm_interconnect_0_pll_sw_reset_s_readdata; // pll_sw_reset:slave_readdata -> mm_interconnect_0:pll_sw_reset_s_readdata
wire [3:0] mm_interconnect_0_pll_sw_reset_s_byteenable; // mm_interconnect_0:pll_sw_reset_s_byteenable -> pll_sw_reset:slave_byteenable
wire mm_interconnect_0_pll_lock_avs_0_s_read; // mm_interconnect_0:pll_lock_avs_0_s_read -> pll_lock_avs_0:slave_read
wire [31:0] mm_interconnect_0_pll_lock_avs_0_s_readdata; // pll_lock_avs_0:slave_readdata -> mm_interconnect_0:pll_lock_avs_0_s_readdata
wire mm_interconnect_0_version_id_0_s_read; // mm_interconnect_0:version_id_0_s_read -> version_id_0:slave_read
wire [31:0] mm_interconnect_0_version_id_0_s_readdata; // version_id_0:slave_readdata -> mm_interconnect_0:version_id_0_s_readdata
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> kernel_pll:rst
wire pll_sw_reset_sw_reset_reset; // pll_sw_reset:sw_reset_n_out -> rst_controller:reset_in0
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [ctrl:reset, mm_interconnect_0:ctrl_reset_reset_bridge_in_reset_reset, pll_lock_avs_0:resetn, pll_reconfig_0:mgmt_reset, pll_rom:reset, pll_sw_reset:resetn, rst_translator:in_reset, version_id_0:resetn]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [pll_rom:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [counter:resetn, mm_interconnect_0:counter_clk_reset_reset_bridge_in_reset_reset]
system_acl_iface_acl_kernel_clk_kernel_pll kernel_pll (
.refclk (pll_refclk_clk), // refclk.clk
.rst (rst_controller_reset_out_reset), // reset.reset
.outclk_0 (kernel_pll_outclk0_clk), // outclk0.clk
.outclk_1 (kernel_pll_outclk1_clk), // outclk1.clk
.locked (kernel_pll_locked_export_signal), // locked.export
.reconfig_to_pll (pll_reconfig_0_reconfig_to_pll_reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (kernel_pll_reconfig_from_pll_reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll
);
altera_pll_reconfig_top #(
.device_family ("Cyclone V"),
.reconf_width (64),
.ENABLE_MIF (0),
.MIF_FILE_NAME ("")
) pll_reconfig_0 (
.mgmt_clk (clk_clk), // mgmt_clk.clk
.mgmt_reset (rst_controller_001_reset_out_reset), // mgmt_reset.reset
.mgmt_readdata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata), // mgmt_avalon_slave.readdata
.mgmt_waitrequest (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.mgmt_read (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read), // .read
.mgmt_write (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write), // .write
.mgmt_address (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address), // .address
.mgmt_writedata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.reconfig_to_pll (pll_reconfig_0_reconfig_to_pll_reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
.reconfig_from_pll (kernel_pll_reconfig_from_pll_reconfig_from_pll) // reconfig_from_pll.reconfig_from_pll
);
system_acl_iface_acl_kernel_clk_pll_rom pll_rom (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_pll_rom_s1_address), // s1.address
.debugaccess (mm_interconnect_0_pll_rom_s1_debugaccess), // .debugaccess
.clken (mm_interconnect_0_pll_rom_s1_clken), // .clken
.chipselect (mm_interconnect_0_pll_rom_s1_chipselect), // .chipselect
.write (mm_interconnect_0_pll_rom_s1_write), // .write
.readdata (mm_interconnect_0_pll_rom_s1_readdata), // .readdata
.writedata (mm_interconnect_0_pll_rom_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_pll_rom_s1_byteenable), // .byteenable
.reset (rst_controller_001_reset_out_reset), // reset1.reset
.reset_req (rst_controller_001_reset_out_reset_req) // .reset_req
);
timer #(
.WIDTH (32),
.S_WIDTH_A (2)
) counter (
.clk (kernel_clk_clk), // clk.clk
.clk2x (kernel_pll_outclk1_clk), // clk2x.clk
.resetn (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
.slave_address (mm_interconnect_0_counter_s_address), // s.address
.slave_writedata (mm_interconnect_0_counter_s_writedata), // .writedata
.slave_read (mm_interconnect_0_counter_s_read), // .read
.slave_write (mm_interconnect_0_counter_s_write), // .write
.slave_byteenable (mm_interconnect_0_counter_s_byteenable), // .byteenable
.slave_waitrequest (mm_interconnect_0_counter_s_waitrequest), // .waitrequest
.slave_readdata (mm_interconnect_0_counter_s_readdata), // .readdata
.slave_readdatavalid (mm_interconnect_0_counter_s_readdatavalid) // .readdatavalid
);
global_routing global_routing_kernel_clk (
.s (kernel_pll_outclk0_clk), // clk.clk
.g (kernel_clk_clk) // global_clk.clk
);
global_routing global_routing_kernel_clk2x (
.s (kernel_pll_outclk1_clk), // clk.clk
.g (kernel_clk2x_clk) // global_clk.clk
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (11),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (0),
.PIPELINE_RESPONSE (0)
) ctrl (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.s0_waitrequest (ctrl_waitrequest), // s0.waitrequest
.s0_readdata (ctrl_readdata), // .readdata
.s0_readdatavalid (ctrl_readdatavalid), // .readdatavalid
.s0_burstcount (ctrl_burstcount), // .burstcount
.s0_writedata (ctrl_writedata), // .writedata
.s0_address (ctrl_address), // .address
.s0_write (ctrl_write), // .write
.s0_read (ctrl_read), // .read
.s0_byteenable (ctrl_byteenable), // .byteenable
.s0_debugaccess (ctrl_debugaccess), // .debugaccess
.m0_waitrequest (ctrl_m0_waitrequest), // m0.waitrequest
.m0_readdata (ctrl_m0_readdata), // .readdata
.m0_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.m0_burstcount (ctrl_m0_burstcount), // .burstcount
.m0_writedata (ctrl_m0_writedata), // .writedata
.m0_address (ctrl_m0_address), // .address
.m0_write (ctrl_m0_write), // .write
.m0_read (ctrl_m0_read), // .read
.m0_byteenable (ctrl_m0_byteenable), // .byteenable
.m0_debugaccess (ctrl_m0_debugaccess) // .debugaccess
);
sw_reset #(
.WIDTH (32),
.LOG2_RESET_CYCLES (10)
) pll_sw_reset (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_0_pll_sw_reset_s_write), // s.write
.slave_writedata (mm_interconnect_0_pll_sw_reset_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_0_pll_sw_reset_s_byteenable), // .byteenable
.slave_read (mm_interconnect_0_pll_sw_reset_s_read), // .read
.slave_readdata (mm_interconnect_0_pll_sw_reset_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_0_pll_sw_reset_s_waitrequest), // .waitrequest
.sw_reset_n_out (pll_sw_reset_sw_reset_reset) // sw_reset.reset_n
);
pll_lock_avs #(
.WIDTH (32)
) pll_lock_avs_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.lock (kernel_pll_locked_export_signal), // lock.export
.lock_export (kernel_pll_locked_export), // lock_export.export
.slave_read (mm_interconnect_0_pll_lock_avs_0_s_read), // s.read
.slave_readdata (mm_interconnect_0_pll_lock_avs_0_s_readdata) // .readdata
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1598029823)
) version_id_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_001_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_0_version_id_0_s_read), // s.read
.slave_readdata (mm_interconnect_0_version_id_0_s_readdata) // .readdata
);
system_acl_iface_acl_kernel_clk_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.global_routing_kernel_clk_global_clk_clk (kernel_clk_clk), // global_routing_kernel_clk_global_clk.clk
.counter_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // counter_clk_reset_reset_bridge_in_reset.reset
.ctrl_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // ctrl_reset_reset_bridge_in_reset.reset
.ctrl_m0_address (ctrl_m0_address), // ctrl_m0.address
.ctrl_m0_waitrequest (ctrl_m0_waitrequest), // .waitrequest
.ctrl_m0_burstcount (ctrl_m0_burstcount), // .burstcount
.ctrl_m0_byteenable (ctrl_m0_byteenable), // .byteenable
.ctrl_m0_read (ctrl_m0_read), // .read
.ctrl_m0_readdata (ctrl_m0_readdata), // .readdata
.ctrl_m0_readdatavalid (ctrl_m0_readdatavalid), // .readdatavalid
.ctrl_m0_write (ctrl_m0_write), // .write
.ctrl_m0_writedata (ctrl_m0_writedata), // .writedata
.ctrl_m0_debugaccess (ctrl_m0_debugaccess), // .debugaccess
.counter_s_address (mm_interconnect_0_counter_s_address), // counter_s.address
.counter_s_write (mm_interconnect_0_counter_s_write), // .write
.counter_s_read (mm_interconnect_0_counter_s_read), // .read
.counter_s_readdata (mm_interconnect_0_counter_s_readdata), // .readdata
.counter_s_writedata (mm_interconnect_0_counter_s_writedata), // .writedata
.counter_s_byteenable (mm_interconnect_0_counter_s_byteenable), // .byteenable
.counter_s_readdatavalid (mm_interconnect_0_counter_s_readdatavalid), // .readdatavalid
.counter_s_waitrequest (mm_interconnect_0_counter_s_waitrequest), // .waitrequest
.pll_lock_avs_0_s_read (mm_interconnect_0_pll_lock_avs_0_s_read), // pll_lock_avs_0_s.read
.pll_lock_avs_0_s_readdata (mm_interconnect_0_pll_lock_avs_0_s_readdata), // .readdata
.pll_reconfig_0_mgmt_avalon_slave_address (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_address), // pll_reconfig_0_mgmt_avalon_slave.address
.pll_reconfig_0_mgmt_avalon_slave_write (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_write), // .write
.pll_reconfig_0_mgmt_avalon_slave_read (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_read), // .read
.pll_reconfig_0_mgmt_avalon_slave_readdata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_readdata), // .readdata
.pll_reconfig_0_mgmt_avalon_slave_writedata (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_writedata), // .writedata
.pll_reconfig_0_mgmt_avalon_slave_waitrequest (mm_interconnect_0_pll_reconfig_0_mgmt_avalon_slave_waitrequest), // .waitrequest
.pll_rom_s1_address (mm_interconnect_0_pll_rom_s1_address), // pll_rom_s1.address
.pll_rom_s1_write (mm_interconnect_0_pll_rom_s1_write), // .write
.pll_rom_s1_readdata (mm_interconnect_0_pll_rom_s1_readdata), // .readdata
.pll_rom_s1_writedata (mm_interconnect_0_pll_rom_s1_writedata), // .writedata
.pll_rom_s1_byteenable (mm_interconnect_0_pll_rom_s1_byteenable), // .byteenable
.pll_rom_s1_chipselect (mm_interconnect_0_pll_rom_s1_chipselect), // .chipselect
.pll_rom_s1_clken (mm_interconnect_0_pll_rom_s1_clken), // .clken
.pll_rom_s1_debugaccess (mm_interconnect_0_pll_rom_s1_debugaccess), // .debugaccess
.pll_sw_reset_s_write (mm_interconnect_0_pll_sw_reset_s_write), // pll_sw_reset_s.write
.pll_sw_reset_s_read (mm_interconnect_0_pll_sw_reset_s_read), // .read
.pll_sw_reset_s_readdata (mm_interconnect_0_pll_sw_reset_s_readdata), // .readdata
.pll_sw_reset_s_writedata (mm_interconnect_0_pll_sw_reset_s_writedata), // .writedata
.pll_sw_reset_s_byteenable (mm_interconnect_0_pll_sw_reset_s_byteenable), // .byteenable
.pll_sw_reset_s_waitrequest (mm_interconnect_0_pll_sw_reset_s_waitrequest), // .waitrequest
.version_id_0_s_read (mm_interconnect_0_version_id_0_s_read), // version_id_0_s.read
.version_id_0_s_readdata (mm_interconnect_0_version_id_0_s_readdata) // .readdata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~pll_sw_reset_sw_reset_reset), // reset_in0.reset
.reset_in1 (~reset_reset_n), // reset_in1.reset
.clk (pll_refclk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//==================================================================================================
// Filename : KOA_c_v2.v
// Created On : 2016-10-06 00:34:18
// Last Modified : 2016-10-24 23:31:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 08/31/2016 03:34:58 PM
// Design Name:
// Module Name: RKOA
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Recursive Karasuba Parameterized Algorithm
//
// Dependencies:
//
// Revision:
// Revision 0.03 - File Created
// Additional Comments: La primera version de este modulo se puede encontrar en la misma carpeta madre.
// The reason for a second version is the way the numbers with lenght lower than 8 are treated. Here, we change that
// by using an at the start before the case, so a multiplier below l = 7 is never instatiated.
//
// Revision 0.03
//
// 1. Width of KOA multipliers in the even case was fixed from the original version
// 2. Zero padding in the adders was fixed.
//////////////////////////////////////////////////////////////////////////////////
module RKOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 54)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-1)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
// localparam i;
// i = Stop_I;
////////////////////////////////////
`define STOP_SW1 3
`define STOP_SW2 4
generate
//assign i = Stop_I;
if (SW <=`STOP_SW1 || SW <=`STOP_SW2) begin
assign sgf_result_o = Data_A_i * Data_B_i;
end else begin
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
RKOA #(.SW(SW/2) /*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
RKOA #(.SW(SW/2)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
`ifndef STRAT1
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
`endif
`ifdef STRAT2
assign result_A_adder = (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
assign result_B_adder = (Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2]);
`endif
RKOA #(.SW(SW/2+1) ) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
///Subtractors for middle
`ifndef STRAT1
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
`endif
`ifdef STRAT2
assign S_B = ((Q_middle[2*(SW/2)+1:0] - Q_left) - {zero1,Q_right[2*(SW/2)-1:0]});
`endif
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
assign sgf_result_o = Result[2*SW-1:0];
// assign sgf_result_o = {Q_left,Q_right[2*(SW/2)-1:0]} + {S_B[2*(SW/2)+1:0],rightside1};
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
RKOA #(.SW(SW/2) ) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
RKOA #(.SW((SW/2)+1) ) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
`ifndef STRAT3
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
`endif
`ifdef STRAT4
assign result_A_adder = (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
assign result_B_adder = Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
`endif
//multiplication for middle
RKOA #(.SW(SW/2+2) ) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
`ifndef STRAT3
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
`endif
`ifdef STRAT4
assign S_B = ((Q_middle - Q_left) - Q_right);
`endif
//Final adder
`ifndef STRAT3
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
`endif
`ifdef STRAT4
assign Result[4*(SW/2)+2:0] = {S_B,rightside2} + {Q_left,Q_right};
`endif
assign sgf_result_o = Result[2*SW-1:0];
//assign sgf_result_o = ({Q_left,Q_right} + {S_B,rightside2});
end
endcase
end
endgenerate
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_14x16.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_14x16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [13:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [13:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [13:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [13:0] q = sub_wire3[13:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 14,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "14"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "14"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "14"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 14 0 INPUT NODEFVAL "data[13..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 14 0 OUTPUT NODEFVAL "q[13..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 14 0 data 0 0 14 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 14 0 @q 0 0 14 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_14x16_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`define PORTS_P 3
`define BANKS_P 3
`define BANK_SIZE_P 1024
`define DATA_WIDTH_P 32 // multiple of 8
/*************************** TEST RATIONALE **********************************
The instantiated multi-port banked memory is completely written by data in the
format {<data_width/8>{<src port number>, <dest bank number>}. The written data
is read and tallied. Then this module tries to fill the memory completely with 1s
by setting mask_i to 111...1 to test the masking capability of UUT.
******************************************************************************/
module test_bsg;
#(
parameter data_width_p = `DATA_WIDTH_P,
parameter bank_size_p = `BANK_SIZE_P,
parameter ports_p = `PORTS_P,
parameter banks_p = `BANKS_P,
parameter lg_banks_p = `BSG_SAFE_CLOG2(banks_p),
parameter bank_addr_width_p = `BSG_SAFE_CLOG2(bank_size_p),
parameter addr_width_p = ((banks_p == 1) ? 0 : lg_banks_p)
+ bank_addr_width_p,
parameter cycle_time_p = 20,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
// clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
/* TEST SIGNALS */
// input
logic [ports_p-1:0][0:0] test_input_v, test_input_w;
logic [ports_p-1:0][addr_width_p-1:0] test_input_addr, test_input_addr_r;
logic [ports_p-1:0][data_width_p-1:0] test_input_data;
logic [ports_p-1:0][(data_width_p>>3)-1:0] test_input_mask;
// output
logic [ports_p-1:0][0:0] test_output_yumi, test_output_v;
logic [ports_p-1:0][data_width_p-1:0] test_output_data;
/*always_ff @(negedge clk)
$strobe("v_i:%0p w_i:%0p addr_i:%b data_i:%b mask_i:%b\n"
, test_input_v, test_input_w, test_input_addr
, test_input_data, test_input_mask
, "v_o:%0p yumi_o:%0p data_o:%b\n"
, test_output_v, test_output_yumi, test_output_data
);*/
initial
begin
$display("\n");
$display("===========================================================");
$display("testing bsg_mem_banked_crossbar with ...");
$display("DATA_WIDTH : %0d", data_width_p);
$display("ADDR_WIDTH : %0d", addr_width_p);
$display("BANKS : %0d", banks_p);
$display("PORTS : %0d", ports_p);
$display("BANK_SIZE : %0d\n", bank_size_p);
end
/* TEST STIMULI */
logic [ports_p-1:0] finish_main_r, finish_mask_r;
logic [ports_p-1:0][lg_banks_p-1:0] bank_num, bank_num_r;
logic [ports_p-1:0][bank_addr_width_p-1:0] bank_addr;
genvar i;
for(i=0; i<ports_p; i=i+1)
begin
// address and control
assign test_input_addr[i] = (banks_p == 1) ?
bank_addr[i]
: {bank_num[i], bank_addr[i]};
always_ff @(posedge clk)
begin
if(reset)
begin
bank_num[i] <= 0;
bank_addr[i] <= i;
test_input_v[i] <= 1'b1;
test_input_w[i] <= 1'b1;
test_input_mask[i] <= {(data_width_p>>3){1'b1}}; // MBT
end
else
begin
if(test_output_yumi[i])
begin
if((bank_addr[i]+ports_p) < bank_size_p)
bank_addr[i] <= bank_addr[i] + ports_p;
else
begin
bank_addr[i] <= i;
bank_num[i] <= bank_num[i] + 1;
end
if((bank_num[i]==banks_p-1) & (bank_addr[i]+ports_p >= bank_size_p))
begin
test_input_v[i] <= test_input_w[i];
test_input_w[i] <= 1'b0;
bank_num[i] <= 0;
bank_addr[i] <= i;
end
end
if(~test_input_v[i] & ~finish_mask_r[i])
begin
test_input_v[i] <= 1'b1;
test_input_w[i] <= 1'b1;
test_input_mask[i] <= 0; // MBT
end
end
end
// data
assign test_input_data[i] = (test_input_mask[i])?
{(data_width_p/8){4'(i), 4'(bank_num[i])}}
:{data_width_p{1'b1}};
end
/* UUT */
bsg_mem_banked_crossbar #( .bank_size_p (bank_size_p)
,.num_ports_p (ports_p)
,.num_banks_p (banks_p)
,.data_width_p (data_width_p)
) UUT
( .clk_i (clk)
,.reset_i (reset)
,.reverse_pr_i(1'b0)
,.v_i (test_input_v)
,.w_i (test_input_w)
,.addr_i (test_input_addr)
,.data_i (test_input_data)
,.mask_i (test_input_mask)
,.yumi_o (test_output_yumi)
,.v_o (test_output_v)
,.data_o (test_output_data)
);
/* Verification */
always_ff @(posedge clk)
if(|test_input_v)
assert(|test_output_yumi)
else $error("Error at time: %d, no transaction in a cycle", $time);
for(i=0; i<ports_p; i=i+1)
begin
always_ff @(posedge clk)
begin
bank_num_r[i] <= bank_num[i];
test_input_addr_r[i] <= test_input_addr[i];
if(test_output_v[i] & ~reset)
assert(test_output_data[i] == {(data_width_p/8){4'(i), 4'(bank_num_r[i])}})
else $error("Error while accessing %b from port: %0d, data was %b", test_input_addr_r[i], i, test_output_data[i]);
end
end
/* FINISH */
for(i=0; i<ports_p; i=i+1)
always_ff @(posedge clk)
begin
if(reset)
begin
finish_main_r[i] <= 1'b0;
finish_mask_r[i] <= 1'b0;
end
else
begin
if(~test_input_v[i])
finish_main_r[i] <= 1'b1;
if(finish_main_r[i] & (~test_input_v[i]))
finish_mask_r[i] <= 1'b1;
end
end
always_ff @(posedge clk)
if((&finish_main_r) & (&finish_mask_r))
begin
$display("============================================================");
$finish;
end
endmodule
|
(*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*)
(** cNNRC is the core named nested relational calculus. It serves as
the foundations for NNRC, an intermediate language that we use to
facilitate code generation to non-functional targets. *)
(** cNNRC is a small pure language without functions. Expressions in
cNNRC are evaluated within a global and a local environment. *)
(** Summary:
- Language: cNNRC (Core Named Nested Relational Calculus)
- Based on: "Polymorphic type inference for the named nested
relational calculus." Jan Van den Bussche, and Stijn
Vansummeren. ACM Transactions on Computational Logic (TOCL) 9.1
(2007): 3.
- translating to cNNRC: NRA, cNRAEnv, NNRC
- translating from cNNRC: NNRC, CAMP *)
(** Compared to the version proposed by Van den Bussche and Vansummerren:
- We add a notion of global variables, distinct from local variables
- We add a let expression: [let x := e1 in e2]
- Conditional expressions allow arbitrary boolean conditions, not just equality, so
instead of: [e1 = e2 ? e3 : e4], we have: [e1 ? e2 : e3]
- We add a case expression for either values: [either e left v₁ : e₁ | right v₂ : e₂]
*)
Require Import String.
Require Import List.
Require Import Arith.
Require Import EquivDec.
Require Import Morphisms.
Require Import Utils.
Require Import DataRuntime.
Declare Scope nnrc_scope.
Section cNNRC.
Context {fruntime:foreign_runtime}.
(** * Abstract Syntax *)
Section Syntax.
(** Note that the AST is shared between cNNRC and NNRC. However,
semantics for extended operators are not defined for core
NNRC. *)
Inductive nnrc :=
| NNRCGetConstant : var -> nnrc (**r global variable lookup ([$$v]) *)
| NNRCVar : var -> nnrc (**r local variable lookup ([$v])*)
| NNRCConst : data -> nnrc (**r constant data ([d]) *)
| NNRCBinop : binary_op -> nnrc -> nnrc -> nnrc (**r binary operator ([e₁ ⊠ e₂]) *)
| NNRCUnop : unary_op -> nnrc -> nnrc (**r unary operator ([⊞ e]) *)
| NNRCLet : var -> nnrc -> nnrc -> nnrc (**r let expression ([let $v := e₁ in e₂]) *)
| NNRCFor : var -> nnrc -> nnrc -> nnrc (**r for loop ([{ e₂ | $v in e₁ }]) *)
| NNRCIf : nnrc -> nnrc -> nnrc -> nnrc (**r conditional ([e₁ ? e₂ : e₃]) *)
| NNRCEither : nnrc -> var -> nnrc -> var -> nnrc -> nnrc (**r case expression ([either e left $v₁ : e₁ | right $v₂ : e₂]) *)
| NNRCGroupBy : string -> list string -> nnrc -> nnrc. (**r group by expression ([e groupby g fields]) -- only in full NNRC *)
(** The [nnrcIsCore] predicate defines what fragment is part of
this abstract syntax is in the core named nested relational
calculus and which part is not. *)
Fixpoint nnrcIsCore (e:nnrc) : Prop :=
match e with
| NNRCGetConstant _ => True
| NNRCVar _ => True
| NNRCConst _ => True
| NNRCBinop _ e1 e2 => (nnrcIsCore e1) /\ (nnrcIsCore e2)
| NNRCUnop _ e1 => (nnrcIsCore e1)
| NNRCLet _ e1 e2 => (nnrcIsCore e1) /\ (nnrcIsCore e2)
| NNRCFor _ e1 e2 => (nnrcIsCore e1) /\ (nnrcIsCore e2)
| NNRCIf e1 e2 e3 => (nnrcIsCore e1) /\ (nnrcIsCore e2) /\ (nnrcIsCore e3)
| NNRCEither e1 _ e2 _ e3 => (nnrcIsCore e1) /\ (nnrcIsCore e2) /\ (nnrcIsCore e3)
| NNRCGroupBy _ _ _ => False
end.
(** cNNRC is defined as the expressions in that abstract syntax
for which the [nnrcIsCore] predicate holds. *)
Definition nnrc_core : Set := {e:nnrc | nnrcIsCore e}.
Definition nnrc_core_to_nnrc (e:nnrc_core) : nnrc :=
proj1_sig e.
Definition lift_nnrc_core {A} (f:nnrc -> A) (e:nnrc_core) : A :=
f (proj1_sig e).
Tactic Notation "nnrc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "NNRCGetConstants"%string
| Case_aux c "NNRCVar"%string
| Case_aux c "NNRCConst"%string
| Case_aux c "NNRCBinop"%string
| Case_aux c "NNRCUnop"%string
| Case_aux c "NNRCLet"%string
| Case_aux c "NNRCFor"%string
| Case_aux c "NNRCIf"%string
| Case_aux c "NNRCEither"%string
| Case_aux c "NNRCGroupBy"%string].
(** Equality between two NNRC expressions is decidable. *)
Global Instance nnrc_eqdec : EqDec nnrc eq.
Proof.
change (forall x y : nnrc, {x = y} + {x <> y}).
decide equality;
try solve [apply binary_op_eqdec | apply unary_op_eqdec
| apply data_eqdec | apply string_eqdec].
- decide equality; apply string_dec.
Defined.
Lemma nnrcIsCore_ext (e:nnrc) (pf1 pf2:nnrcIsCore e) : pf1 = pf2.
Proof.
induction e; simpl in *;
try (destruct pf1; destruct pf2; trivial);
try f_equal; auto.
- destruct a; destruct a0.
f_equal; auto.
- destruct a; destruct a0.
f_equal; auto.
Qed.
Lemma nnrc_core_ext e (pf1 pf2:nnrcIsCore e) :
exist _ e pf1 = exist _ e pf2.
Proof.
f_equal; apply nnrcIsCore_ext.
Qed.
Lemma nnrc_core_fequal (e1 e2:nnrc_core) :
proj1_sig e1 = proj1_sig e2 -> e1 = e2.
Proof.
destruct e1; destruct e2; simpl; intros eqq.
destruct eqq.
apply nnrc_core_ext.
Qed.
Global Instance nnrc_core_eqdec : EqDec nnrc_core eq.
Proof.
intros x y.
destruct x as [x xpf]; destruct y as [y ypf].
destruct (x == y).
- left. apply nnrc_core_fequal; simpl; trivial.
- right. inversion 1; congruence.
Defined.
End Syntax.
(** * Semantics *)
(** For cNNRC, we provide two kinds of semantics: a denotational
semantics, and an evaluation semantics. Both are shown to be
equivalent. The denotational semantics is used for documentation
purposes, as most of the rest of the code relies on evaluation as
the primary semantics. *)
Section Semantics.
(** Part of the context is fixed for the rest of the development:
- [h] is the brand relation
- [constant_env] is the global environment *)
Context (h:brand_relation_t).
Context (constant_env:list (string*data)).
(** ** Denotational Semantics *)
(** The semantics is defined using the main judgment [Γc ; Γ ⊢〚e
〛⇓ d] ([nnrc_core_sem]) where [Γc] is the global environment, [Γ]
is the local environment, [e] the cNNRC expression and [d] the
resulting value. *)
(** Conditionals and matching expressions only evaluate one of
their branches. The auxiliary judgment [Γc ; Γ ; v ; c₁ ⊢ 〚e〛φ ⇓ c₂]
([nnrc_core_sem_for]) is used in the definition of [for]
expressions. *)
Section Denotation.
Inductive nnrc_core_sem: bindings -> nnrc -> data -> Prop :=
| sem_cNNRCGetConstant : forall env v d,
edot constant_env v = Some d -> (**r [Γc(v) = d] *)
nnrc_core_sem env (NNRCGetConstant v) d (**r ⇒ [Γc ; Γ ⊢〚$$v〛⇓ d] *)
| sem_cNNRCVar : forall env v d,
lookup equiv_dec env v = Some d -> (**r [Γ(v) = d] *)
nnrc_core_sem env (NNRCVar v) d (**r ⇒ [Γc ; Γ ⊢〚$v〛⇓ d] *)
| sem_cNNRCConst : forall env d1 d2,
normalize_data h d1 = d2 -> (**r [norm(d₁) = d₂] *)
nnrc_core_sem env (NNRCConst d1) d2 (**r ⇒ [Γc ; Γ ⊢〚d₁〛⇓ d₂] *)
| sem_cNNRCBinop : forall bop env e1 e2 d1 d2 d3,
nnrc_core_sem env e1 d1 -> (**r [Γc ; Γ ⊢〚e₁〛⇓ d₁] *)
nnrc_core_sem env e2 d2 -> (**r ∧ [Γc ; Γ ⊢〚e₂〛⇓ d₂] *)
binary_op_eval h bop d1 d2 = Some d3 -> (**r ∧ [d₁ ⊠ d₂ = d₃] *)
nnrc_core_sem env (NNRCBinop bop e1 e2) d3 (**r ⇒ [Γc ; Γ ⊢〚e₁ ⊠ e₂〛⇓ d₃] *)
| sem_cNNRCUnop : forall uop env e d1 d2,
nnrc_core_sem env e d1 -> (**r [Γc ; Γ ⊢〚e〛⇓ d₁] *)
unary_op_eval h uop d1 = Some d2 -> (**r ∧ [⊞ d₁ = d₂] *)
nnrc_core_sem env (NNRCUnop uop e) d2 (**r ⇒ [Γc ; Γ ⊢〚⊞ e〛⇓ d₂] *)
| sem_cNNRCLet : forall env e1 v e2 d1 d2,
nnrc_core_sem env e1 d1 -> (**r [Γc ; Γ ⊢〚e₁〛⇓ d₁] *)
nnrc_core_sem ((v,d1)::env) e2 d2 -> (**r ∧ [Γc ; (v,d₁),Γ ⊢〚e₂〛⇓ d₂] *)
nnrc_core_sem env (NNRCLet v e1 e2) d2 (**r ⇒ [Γc ; Γ ⊢〚let 4v := e₁ in e₂〛⇓ d₂] *)
| sem_cNNRCFor : forall env e1 v e2 c1 c2,
nnrc_core_sem env e1 (dcoll c1) -> (**r [Γc ; Γ ⊢〚e₁〛= {c₁}] *)
nnrc_core_sem_for v env e2 c1 c2 -> (**r ∧ [Γc ; Γ ; v ; {c₁} ⊢〚e₂〛φ ⇓ {c₂}] *)
nnrc_core_sem env (NNRCFor v e1 e2) (dcoll c2) (**r ⇒ [Γc ; Γ ⊢ 〚{ e₂ | $v in e₁ }〛⇓ {c₂}] *)
| sem_cNNRCIf_true : forall env e1 e2 e3 d,
nnrc_core_sem env e1 (dbool true) -> (**r [Γc ; Γ ⊢〚e₁〛⇓ true] *)
nnrc_core_sem env e2 d -> (**r ∧ [Γc ; Γ ⊢〚e₂〛⇓ d] *)
nnrc_core_sem env (NNRCIf e1 e2 e3) d (**r ⇒ [Γc ; Γ ⊢〚e₁ ? e₂ : e₃〛⇓ d] *)
| sem_cNNRCIf_false : forall env e1 e2 e3 d,
nnrc_core_sem env e1 (dbool false) -> (**r [Γc ; Γ ⊢〚e₁〛⇓ false] *)
nnrc_core_sem env e3 d -> (**r ∧ [Γc ; Γ ⊢〚e₃〛⇓ d] *)
nnrc_core_sem env (NNRCIf e1 e2 e3) d (**r ⇒ [Γc ; Γ ⊢〚e₁ ? e₂ : e₃〛⇓ d] *)
| sem_cNNRCEither_left : forall env e v1 e1 v2 e2 d d1,
nnrc_core_sem env e (dleft d) -> (**r [Γc ; Γ ⊢〚e〛⇓ left d] *)
nnrc_core_sem ((v1,d)::env) e1 d1 -> (**r ∧ [Γc ; (v₁,d),Γ ⊢〚e₁〛⇓ d₁] *)
nnrc_core_sem env (NNRCEither e v1 e1 v2 e2) d1 (**r ⇒ [Γc ; Γ ⊢〚either e left $v₁ : e₁ | right $v₂ : e₂〛⇓ d₁] *)
| sem_cNNRCEither_right : forall env e v1 e1 v2 e2 d d2,
nnrc_core_sem env e (dright d) -> (**r [Γc ; Γ ⊢〚e〛⇓ right d] *)
nnrc_core_sem ((v2,d)::env) e2 d2 -> (**r ∧ [Γc ; (v₂,d),Γ ⊢〚e₂〛⇓ d₂] *)
nnrc_core_sem env (NNRCEither e v1 e1 v2 e2) d2 (**r ⇒ [Γc ; Γ ⊢〚either e left $v₁ : e₁ | right $v₂ : e₂〛⇓ d₂] *)
with nnrc_core_sem_for: var -> bindings -> nnrc -> list data -> list data -> Prop :=
| sem_cNNRCFor_empty v : forall env e,
nnrc_core_sem_for v env e nil nil (**r [Γc ; Γ ; v ; {} ⊢〚e〛φ ⇓ {}] *)
| sem_cNNRCFor_cons v : forall env e d1 c1 d2 c2,
nnrc_core_sem ((v,d1)::env) e d2 -> (**r [Γc ; (v,d₁),Γ ⊢〚e₂〛⇓ d₂] *)
nnrc_core_sem_for v env e c1 c2 -> (**r ∧ [Γc ; Γ ; v ; {c₁} ⊢〚e〛φ ⇓ {c₂}] *)
nnrc_core_sem_for v env e (d1::c1) (d2::c2). (**r ⇒ [Γc ; Γ ; v ; {d₁::c₁} ⊢〚e〛φ ⇓ {d₂::c₂}] *)
End Denotation.
(** ** Evaluation Semantics *)
Section Evaluation.
(** Evaluation takes a cNNRC expression and an environment. It
returns an optional value. When [None] is returned, it
denotes an error. An error is always propagated. *)
Fixpoint nnrc_core_eval (env:bindings) (e:nnrc) : option data :=
match e with
| NNRCGetConstant v =>
edot constant_env v
| NNRCVar v =>
lookup equiv_dec env v
| NNRCConst d =>
Some (normalize_data h d)
| NNRCBinop bop e1 e2 =>
olift2 (fun d1 d2 => binary_op_eval h bop d1 d2)
(nnrc_core_eval env e1)
(nnrc_core_eval env e2)
| NNRCUnop uop e =>
olift (fun d1 => unary_op_eval h uop d1)
(nnrc_core_eval env e)
| NNRCLet v e1 e2 =>
match nnrc_core_eval env e1 with
| Some d1 => nnrc_core_eval ((v,d1)::env) e2
| _ => None
end
| NNRCFor v e1 e2 =>
match nnrc_core_eval env e1 with
| Some (dcoll c1) =>
let for_fun :=
fun d1 => nnrc_core_eval ((v,d1)::env) e2
in
lift dcoll (lift_map for_fun c1)
| _ => None
end
| NNRCIf e1 e2 e3 =>
let cond_fun :=
fun d =>
match d with
| dbool true =>
nnrc_core_eval env e2
| dbool false =>
nnrc_core_eval env e3
| _ => None
end
in olift cond_fun (nnrc_core_eval env e1)
| NNRCEither e v1 e1 v2 e2 =>
match nnrc_core_eval env e with
| Some (dleft d) =>
nnrc_core_eval ((v1,d)::env) e1
| Some (dright d) =>
nnrc_core_eval ((v2,d)::env) e2
| _ => None
end
| NNRCGroupBy _ _ _ => None (**r Evaluation for GroupBy always fails for cNNRC *)
end.
(** cNNRC evaluation is only sensitive to the environment modulo
lookup. *)
Global Instance nnrc_core_eval_lookup_equiv_prop :
Proper (lookup_equiv ==> eq ==> eq) nnrc_core_eval.
Proof.
unfold Proper, respectful, lookup_equiv; intros; subst.
rename y0 into e.
revert x y H.
induction e; simpl; intros; trivial;
try rewrite (IHe1 _ _ H); try rewrite (IHe2 _ _ H);
try rewrite (IHe _ _ H); trivial.
- match_destr.
apply IHe2; intros.
simpl; match_destr.
- match_destr.
destruct d; simpl; trivial.
f_equal.
apply lift_map_ext; intros.
apply IHe2; intros.
simpl; match_destr.
- unfold olift.
match_destr.
destruct d; trivial.
destruct b; eauto.
- match_destr.
destruct d; trivial.
+ apply IHe2; intros.
simpl; match_destr.
+ apply IHe3; intros.
simpl; match_destr.
Qed.
End Evaluation.
(** * Correctness of evaluation *)
(** The evaluation and denotational semantics are equivalent. *)
Section EvaluationCorrect.
(** Auxiliary lemma on [for] loops used in the correctness theorem *)
Lemma nnrc_core_for_eval_correct v env e l1 l2:
(lift_map (fun d1 : data => nnrc_core_eval ((v, d1) :: env) e) l1 = Some l2) ->
(forall (env : bindings) (d : data),
nnrc_core_eval env e = Some d -> nnrc_core_sem env e d) ->
nnrc_core_sem_for v env e l1 l2.
Proof.
revert l2; induction l1; simpl; intros.
- inversion H; subst; econstructor.
- case_eq (nnrc_core_eval ((v, a) :: env) e); intros;
rewrite H1 in *.
+ unfold lift in H.
case_eq (lift_map (fun d1 : data => nnrc_core_eval ((v, d1) :: env) e) l1);
intros; rewrite H2 in *; clear H2; [|congruence].
inversion H; subst; clear H.
specialize (IHl1 l eq_refl H0).
econstructor.
apply H0; auto.
auto.
+ congruence.
Qed.
(** Evaluation is correct wrt. the cNNRC semantics. *)
Lemma nnrc_core_eval_correct : forall e env d,
nnrc_core_eval env e = Some d ->
nnrc_core_sem env e d.
Proof.
induction e; simpl; intros.
- constructor; trivial.
- constructor; trivial.
- constructor; inversion H; trivial.
- specialize (IHe1 env); specialize (IHe2 env).
case_eq (nnrc_core_eval env e1); intros; rewrite H0 in *.
+ case_eq (nnrc_core_eval env e2); intros; rewrite H1 in *.
* specialize (IHe1 d0 eq_refl); specialize (IHe2 d1 eq_refl);
econstructor; eauto.
* simpl in H; congruence.
+ simpl in H; congruence.
- specialize (IHe env).
case_eq (nnrc_core_eval env e); intros; rewrite H0 in *.
+ specialize (IHe d0 eq_refl); econstructor; eauto.
+ simpl in H; congruence.
- specialize (IHe1 env).
case_eq (nnrc_core_eval env e1); intros; rewrite H0 in *.
+ case_eq (nnrc_core_eval ((v,d0)::env) e2); intros.
* specialize (IHe2 ((v,d0)::env)).
rewrite H1 in *; inversion H; subst; clear H.
specialize (IHe2 d eq_refl);
econstructor; eauto.
* simpl in H; congruence.
+ simpl in H; congruence.
- specialize (IHe1 env).
case_eq (nnrc_core_eval env e1); intros; rewrite H0 in *.
+ destruct d0; simpl in H; try congruence.
specialize (IHe1 (dcoll l) eq_refl).
unfold lift in H.
case_eq (lift_map (fun d1 : data => nnrc_core_eval ((v, d1) :: env) e2) l);
intros; rewrite H1 in H; try congruence.
inversion H; subst; clear H.
econstructor; eauto.
apply nnrc_core_for_eval_correct; eauto.
+ simpl in H; congruence.
- specialize (IHe1 env); specialize (IHe2 env); specialize (IHe3 env).
case_eq (nnrc_core_eval env e1); intros; rewrite H0 in *; simpl in H.
destruct d0; simpl in H; try congruence.
destruct b.
(* condition true *)
+ case_eq (nnrc_core_eval env e2); intros; rewrite H1 in *.
* specialize (IHe1 (dbool true) eq_refl); specialize (IHe2 d0 eq_refl);
inversion H; subst; eapply sem_cNNRCIf_true; eauto.
* simpl in H; congruence.
(* condition false *)
+ case_eq (nnrc_core_eval env e3); intros; rewrite H1 in *.
* specialize (IHe1 (dbool false) eq_refl); specialize (IHe3 d0 eq_refl);
inversion H; subst; eapply sem_cNNRCIf_false; eauto.
* simpl in H; congruence.
+ simpl in H; congruence.
- specialize (IHe1 env).
case_eq (nnrc_core_eval env e1); intros; rewrite H0 in *; simpl in H.
destruct d0; simpl in H; try congruence.
(* left case *)
+ specialize (IHe2 ((v,d0)::env)).
* specialize (IHe1 (dleft d0) eq_refl); specialize (IHe2 d H);
inversion H; subst; eapply sem_cNNRCEither_left; eauto.
(* right case *)
+ specialize (IHe3 ((v0,d0)::env)).
* specialize (IHe1 (dright d0) eq_refl); specialize (IHe3 d H);
inversion H; subst; eapply sem_cNNRCEither_right; eauto.
+ simpl in H; congruence.
- congruence.
Qed.
(** Auxiliary lemma on [for] loops used in the completeness theorem *)
Lemma nnrc_core_for_eval_complete e v env c1 c2:
(forall (env : bindings) (d : data),
nnrc_core_sem env e d -> nnrc_core_eval env e = Some d) ->
(nnrc_core_sem_for v env e c1 c2) ->
lift dcoll (lift_map (fun d1 : data => nnrc_core_eval ((v, d1) :: env) e) c1) =
Some (dcoll c2).
Proof.
intro Hcomp.
revert c2; induction c1; intros; simpl in *.
- inversion H; auto.
- inversion H; subst.
rewrite (Hcomp ((v,a)::env) d2); auto.
unfold lift in *.
specialize (IHc1 c3 H7).
case_eq (lift_map (fun d1 : data => nnrc_core_eval ((v, d1) :: env) e) c1); intros;
rewrite H0 in *; [|congruence].
inversion IHc1; subst; auto.
Qed.
(** Evaluation is complete wrt. the cNNRC semantics. *)
Lemma nnrc_core_eval_complete : forall e env d,
nnrc_core_sem env e d ->
nnrc_core_eval env e = Some d.
Proof.
induction e; intros.
- inversion H; subst; simpl; auto.
- inversion H; subst; simpl; auto.
- inversion H; subst; simpl; auto.
- inversion H; subst; simpl.
rewrite (IHe1 env d1 H4);
rewrite (IHe2 env d2 H6); simpl; auto.
- inversion H; subst; simpl.
rewrite (IHe env d1 H3); simpl; auto.
- inversion H; subst; simpl.
rewrite (IHe1 env d1 H5);
rewrite (IHe2 ((v,d1)::env) d H6); simpl; auto.
- inversion H; subst; simpl.
rewrite (IHe1 env (dcoll c1) H5).
apply nnrc_core_for_eval_complete; auto.
- inversion H; subst; simpl; auto.
(* condition true *)
+ rewrite (IHe1 env (dbool true) H5); simpl; auto.
(* condition false *)
+ rewrite (IHe1 env (dbool false) H5); simpl; auto.
- inversion H; subst; simpl; auto.
(* left case *)
+ rewrite (IHe1 env (dleft d0) H7); simpl; auto.
(* right case *)
+ rewrite (IHe1 env (dright d0) H7); simpl; auto.
- inversion H.
Qed.
(** Main equivalence theorem. *)
Theorem nnrc_core_eval_correct_and_complete : forall e env d,
nnrc_core_eval env e = Some d <-> nnrc_core_sem env e d.
Proof.
split.
apply nnrc_core_eval_correct.
apply nnrc_core_eval_complete.
Qed.
End EvaluationCorrect.
End Semantics.
(** * Toplevel *)
(** The Top-level evaluation function is used externally by the
Q*cert compiler. It takes a cNNRC expression and an global
environment as input. *)
Section Top.
Context (h:brand_relation_t).
(** Top-level semantics is always with an initial empty environment *)
Inductive nnrc_core_sem_top : nnrc_core -> bindings -> data -> Prop :=
| sem_NNRCTop: forall e cenv d,
nnrc_core_sem h cenv nil (proj1_sig e) d ->
nnrc_core_sem_top e cenv d.
Definition nnrc_core_eval_top (q:nnrc_core) (cenv:bindings) : option data :=
lift_nnrc_core (nnrc_core_eval h (rec_sort cenv) nil) q.
(** If top-level NNRC eval returns a value, this value is
consistent with the semantics *)
Theorem nnrc_core_eval_top_correct:
forall cenv,
rec_sort cenv = cenv -> (* This assumption should be part of constant_env *)
forall (q:nnrc_core) (d:data),
nnrc_core_eval_top q cenv = Some d ->
nnrc_core_sem_top q cenv d.
Proof.
intros cenv HconstNorm q d.
destruct q; simpl in *.
econstructor; simpl.
unfold nnrc_core_eval_top in H.
unfold lift_nnrc_core in H; simpl in H.
apply nnrc_core_eval_correct.
rewrite HconstNorm in H.
assumption.
Qed.
End Top.
End cNNRC.
(** * Notations *)
(* begin hide *)
Notation "‵‵ c" := (NNRCConst (dconst c)) (at level 0) : nnrc_scope. (* ‵ = \backprime *)
Notation "‵ c" := (NNRCConst c) (at level 0) : nnrc_scope. (* ‵ = \backprime *)
Notation "‵{||}" := (NNRCConst (dcoll nil)) (at level 0) : nnrc_scope. (* ‵ = \backprime *)
Notation "‵[||]" := (NNRCConst (drec nil)) (at level 50) : nnrc_scope. (* ‵ = \backprime *)
Notation "r1 ∧ r2" := (NNRCBinop OpAnd r1 r2) (right associativity, at level 65): nnrc_scope. (* ∧ = \wedge *)
Notation "r1 ∨ r2" := (NNRCBinop OpOr r1 r2) (right associativity, at level 70): nnrc_scope. (* ∨ = \vee *)
Notation "r1 ≐ r2" := (NNRCBinop OpEqual r1 r2) (right associativity, at level 70): nnrc_scope. (* ≐ = \doteq *)
Notation "r1 ≤ r2" := (NNRCBinop OpLe r1 r2) (no associativity, at level 70): nnrc_scope. (* ≤ = \leq *)
Notation "r1 ⋃ r2" := (NNRCBinop OpBagUnion r1 r2) (right associativity, at level 70): nnrc_scope. (* ⋃ = \bigcup *)
Notation "r1 − r2" := (NNRCBinop OpBagDiff r1 r2) (right associativity, at level 70): nnrc_scope. (* − = \minus *)
Notation "r1 ⋂min r2" := (NNRCBinop OpBagMin r1 r2) (right associativity, at level 70): nnrc_scope. (* ♯ = \sharp *)
Notation "r1 ⋃max r2" := (NNRCBinop OpBagMax r1 r2) (right associativity, at level 70): nnrc_scope. (* ♯ = \sharp *)
Notation "p ⊕ r" := ((NNRCBinop OpRecConcat) p r) (at level 70) : nnrc_scope. (* ⊕ = \oplus *)
Notation "p ⊗ r" := ((NNRCBinop OpRecMerge) p r) (at level 70) : nnrc_scope. (* ⊗ = \otimes *)
Notation "¬( r1 )" := (NNRCUnop OpNeg r1) (right associativity, at level 70): nnrc_scope. (* ¬ = \neg *)
Notation "ε( r1 )" := (NNRCUnop OpDistinct r1) (right associativity, at level 70): nnrc_scope. (* ε = \epsilon *)
Notation "♯count( r1 )" := (NNRCUnop OpCount r1) (right associativity, at level 70): nnrc_scope. (* ♯ = \sharp *)
Notation "♯flatten( d )" := (NNRCUnop OpFlatten d) (at level 50) : nnrc_scope. (* ♯ = \sharp *)
Notation "‵{| d |}" := ((NNRCUnop OpBag) d) (at level 50) : nnrc_scope. (* ‵ = \backprime *)
Notation "‵[| ( s , r ) |]" := ((NNRCUnop (OpRec s)) r) (at level 50) : nnrc_scope. (* ‵ = \backprime *)
Notation "¬π[ s1 ]( r )" := ((NNRCUnop (OpRecRemove s1)) r) (at level 50) : nnrc_scope. (* ¬ = \neg and π = \pi *)
Notation "π[ s1 ]( r )" := ((NNRCUnop (OpRecProject s1)) r) (at level 50) : nnrc_scope. (* π = \pi *)
Notation "p · r" := ((NNRCUnop (OpDot r)) p) (left associativity, at level 40): nnrc_scope. (* · = \cdot *)
Notation "'$$' v" := (NNRCGetConstant v%string) (at level 50, format "'$$' v") : nnrc_scope.
Notation "'$' v" := (NNRCVar v%string) (at level 50, format "'$' v") : nnrc_scope.
Notation "{| e1 | '$' x ∈ e2 |}" := (NNRCFor x%string e2 e1) (at level 50, format "{| e1 '/ ' | '$' x ∈ e2 |}") : nnrc_scope. (* ∈ = \in *)
Notation "'let' '$' x ':=' e2 'in' e1" := (NNRCLet x%string e2 e1) (at level 50, format "'[hv' 'let' '$' x ':=' '[' e2 ']' '/' 'in' '[' e1 ']' ']'") : nnrc_scope.
Notation "e1 ? e2 : e3" := (NNRCIf e1 e2 e3) (at level 50, format "e1 '[hv' ? e2 '/' : e3 ']'") : nnrc_scope.
Notation "r1 ‵+ r2" := (NNRCBinop (OpNatBinary NatPlus) r1 r2) (right associativity, at level 65): nnrc_scope.
Notation "r1 ‵* r2" := (NNRCBinop (OpNatBinary NatMult) r1 r2) (right associativity, at level 65): nnrc_scope.
Notation "‵abs r" := (NNRCUnop (OpNatUnary NatAbs) r) (right associativity, at level 64): nnrc_scope.
Tactic Notation "nnrc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "NNRCGetConstant"%string
| Case_aux c "NNRCVar"%string
| Case_aux c "NNRCConst"%string
| Case_aux c "NNRCBinop"%string
| Case_aux c "NNRCUnop"%string
| Case_aux c "NNRCLet"%string
| Case_aux c "NNRCFor"%string
| Case_aux c "NNRCIf"%string
| Case_aux c "NNRCEither"%string
| Case_aux c "NNRCGroupBy"%string].
(* end hide *)
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// to_child_rsFromC_notFull O 1
// RDY_to_child_rsFromC_notFull O 1 const
// RDY_to_child_rsFromC_enq O 1
// to_child_rqFromC_notFull O 1
// RDY_to_child_rqFromC_notFull O 1 const
// RDY_to_child_rqFromC_enq O 1
// to_child_toC_notEmpty O 1
// RDY_to_child_toC_notEmpty O 1 const
// RDY_to_child_toC_deq O 1
// to_child_toC_first O 585
// RDY_to_child_toC_first O 1
// dma_memReq_notFull O 1
// RDY_dma_memReq_notFull O 1 const
// RDY_dma_memReq_enq O 1
// dma_respLd_notEmpty O 1
// RDY_dma_respLd_notEmpty O 1 const
// RDY_dma_respLd_deq O 1
// dma_respLd_first O 528
// RDY_dma_respLd_first O 1
// dma_respSt_notEmpty O 1
// RDY_dma_respSt_notEmpty O 1 const
// RDY_dma_respSt_deq O 1
// dma_respSt_first O 16
// RDY_dma_respSt_first O 1
// to_mem_toM_notEmpty O 1
// RDY_to_mem_toM_notEmpty O 1 const
// RDY_to_mem_toM_deq O 1
// to_mem_toM_first O 641
// RDY_to_mem_toM_first O 1
// to_mem_rsFromM_notFull O 1
// RDY_to_mem_rsFromM_notFull O 1 const
// RDY_to_mem_rsFromM_enq O 1
// cRqStuck_get O 103 const
// RDY_cRqStuck_get O 1 const
// RDY_perf_setStatus O 1 const
// RDY_perf_req O 1
// perf_resp O 68
// RDY_perf_resp O 1
// perf_respValid O 1
// RDY_perf_respValid O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// to_child_rsFromC_enq_x I 581
// to_child_rqFromC_enq_x I 74
// dma_memReq_enq_x I 656
// to_mem_rsFromM_enq_x I 517
// perf_setStatus_doStats I 1 unused
// perf_req_r I 4
// EN_to_child_rsFromC_enq I 1
// EN_to_child_rqFromC_enq I 1
// EN_to_child_toC_deq I 1
// EN_dma_memReq_enq I 1
// EN_dma_respLd_deq I 1
// EN_dma_respSt_deq I 1
// EN_to_mem_toM_deq I 1
// EN_to_mem_rsFromM_enq I 1
// EN_perf_setStatus I 1 unused
// EN_perf_req I 1
// EN_cRqStuck_get I 1 unused
// EN_perf_resp I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkLLCache(CLK,
RST_N,
to_child_rsFromC_notFull,
RDY_to_child_rsFromC_notFull,
to_child_rsFromC_enq_x,
EN_to_child_rsFromC_enq,
RDY_to_child_rsFromC_enq,
to_child_rqFromC_notFull,
RDY_to_child_rqFromC_notFull,
to_child_rqFromC_enq_x,
EN_to_child_rqFromC_enq,
RDY_to_child_rqFromC_enq,
to_child_toC_notEmpty,
RDY_to_child_toC_notEmpty,
EN_to_child_toC_deq,
RDY_to_child_toC_deq,
to_child_toC_first,
RDY_to_child_toC_first,
dma_memReq_notFull,
RDY_dma_memReq_notFull,
dma_memReq_enq_x,
EN_dma_memReq_enq,
RDY_dma_memReq_enq,
dma_respLd_notEmpty,
RDY_dma_respLd_notEmpty,
EN_dma_respLd_deq,
RDY_dma_respLd_deq,
dma_respLd_first,
RDY_dma_respLd_first,
dma_respSt_notEmpty,
RDY_dma_respSt_notEmpty,
EN_dma_respSt_deq,
RDY_dma_respSt_deq,
dma_respSt_first,
RDY_dma_respSt_first,
to_mem_toM_notEmpty,
RDY_to_mem_toM_notEmpty,
EN_to_mem_toM_deq,
RDY_to_mem_toM_deq,
to_mem_toM_first,
RDY_to_mem_toM_first,
to_mem_rsFromM_notFull,
RDY_to_mem_rsFromM_notFull,
to_mem_rsFromM_enq_x,
EN_to_mem_rsFromM_enq,
RDY_to_mem_rsFromM_enq,
EN_cRqStuck_get,
cRqStuck_get,
RDY_cRqStuck_get,
perf_setStatus_doStats,
EN_perf_setStatus,
RDY_perf_setStatus,
perf_req_r,
EN_perf_req,
RDY_perf_req,
EN_perf_resp,
perf_resp,
RDY_perf_resp,
perf_respValid,
RDY_perf_respValid);
input CLK;
input RST_N;
// value method to_child_rsFromC_notFull
output to_child_rsFromC_notFull;
output RDY_to_child_rsFromC_notFull;
// action method to_child_rsFromC_enq
input [580 : 0] to_child_rsFromC_enq_x;
input EN_to_child_rsFromC_enq;
output RDY_to_child_rsFromC_enq;
// value method to_child_rqFromC_notFull
output to_child_rqFromC_notFull;
output RDY_to_child_rqFromC_notFull;
// action method to_child_rqFromC_enq
input [73 : 0] to_child_rqFromC_enq_x;
input EN_to_child_rqFromC_enq;
output RDY_to_child_rqFromC_enq;
// value method to_child_toC_notEmpty
output to_child_toC_notEmpty;
output RDY_to_child_toC_notEmpty;
// action method to_child_toC_deq
input EN_to_child_toC_deq;
output RDY_to_child_toC_deq;
// value method to_child_toC_first
output [584 : 0] to_child_toC_first;
output RDY_to_child_toC_first;
// value method dma_memReq_notFull
output dma_memReq_notFull;
output RDY_dma_memReq_notFull;
// action method dma_memReq_enq
input [655 : 0] dma_memReq_enq_x;
input EN_dma_memReq_enq;
output RDY_dma_memReq_enq;
// value method dma_respLd_notEmpty
output dma_respLd_notEmpty;
output RDY_dma_respLd_notEmpty;
// action method dma_respLd_deq
input EN_dma_respLd_deq;
output RDY_dma_respLd_deq;
// value method dma_respLd_first
output [527 : 0] dma_respLd_first;
output RDY_dma_respLd_first;
// value method dma_respSt_notEmpty
output dma_respSt_notEmpty;
output RDY_dma_respSt_notEmpty;
// action method dma_respSt_deq
input EN_dma_respSt_deq;
output RDY_dma_respSt_deq;
// value method dma_respSt_first
output [15 : 0] dma_respSt_first;
output RDY_dma_respSt_first;
// value method to_mem_toM_notEmpty
output to_mem_toM_notEmpty;
output RDY_to_mem_toM_notEmpty;
// action method to_mem_toM_deq
input EN_to_mem_toM_deq;
output RDY_to_mem_toM_deq;
// value method to_mem_toM_first
output [640 : 0] to_mem_toM_first;
output RDY_to_mem_toM_first;
// value method to_mem_rsFromM_notFull
output to_mem_rsFromM_notFull;
output RDY_to_mem_rsFromM_notFull;
// action method to_mem_rsFromM_enq
input [516 : 0] to_mem_rsFromM_enq_x;
input EN_to_mem_rsFromM_enq;
output RDY_to_mem_rsFromM_enq;
// actionvalue method cRqStuck_get
input EN_cRqStuck_get;
output [102 : 0] cRqStuck_get;
output RDY_cRqStuck_get;
// action method perf_setStatus
input perf_setStatus_doStats;
input EN_perf_setStatus;
output RDY_perf_setStatus;
// action method perf_req
input [3 : 0] perf_req_r;
input EN_perf_req;
output RDY_perf_req;
// actionvalue method perf_resp
input EN_perf_resp;
output [67 : 0] perf_resp;
output RDY_perf_resp;
// value method perf_respValid
output perf_respValid;
output RDY_perf_respValid;
// signals for module outputs
reg [15 : 0] dma_respSt_first;
wire [640 : 0] to_mem_toM_first;
wire [584 : 0] to_child_toC_first;
wire [527 : 0] dma_respLd_first;
wire [102 : 0] cRqStuck_get;
wire [67 : 0] perf_resp;
wire RDY_cRqStuck_get,
RDY_dma_memReq_enq,
RDY_dma_memReq_notFull,
RDY_dma_respLd_deq,
RDY_dma_respLd_first,
RDY_dma_respLd_notEmpty,
RDY_dma_respSt_deq,
RDY_dma_respSt_first,
RDY_dma_respSt_notEmpty,
RDY_perf_req,
RDY_perf_resp,
RDY_perf_respValid,
RDY_perf_setStatus,
RDY_to_child_rqFromC_enq,
RDY_to_child_rqFromC_notFull,
RDY_to_child_rsFromC_enq,
RDY_to_child_rsFromC_notFull,
RDY_to_child_toC_deq,
RDY_to_child_toC_first,
RDY_to_child_toC_notEmpty,
RDY_to_mem_rsFromM_enq,
RDY_to_mem_rsFromM_notFull,
RDY_to_mem_toM_deq,
RDY_to_mem_toM_first,
RDY_to_mem_toM_notEmpty,
dma_memReq_notFull,
dma_respLd_notEmpty,
dma_respSt_notEmpty,
perf_respValid,
to_child_rqFromC_notFull,
to_child_rsFromC_notFull,
to_child_toC_notEmpty,
to_mem_rsFromM_notFull,
to_mem_toM_notEmpty;
// inlined wires
reg [641 : 0] cache_toMQ_enqReq_lat_0$wget;
reg [6 : 0] cache_rsToCIndexQ_enqReq_lat_0$wget;
wire [656 : 0] cache_rqFromDmaQ_enqReq_lat_0$wget;
wire [585 : 0] cache_toCQ_enqReq_lat_0$wget;
wire [581 : 0] cache_rsFromCQ_enqReq_lat_0$wget;
wire [528 : 0] cache_rsLdToDmaQ_enqReq_lat_0$wget;
wire [517 : 0] cache_rsFromMQ_enqReq_lat_0$wget;
wire [74 : 0] cache_rqFromCQ_enqReq_lat_0$wget;
wire [16 : 0] cache_rsStToDmaQ_enqReq_lat_0$wget;
wire [4 : 0] cache_cRqRetryIndexQ_enqReq_lat_0$wget,
perfReqQ_enqReq_lat_0$wget;
wire cache_cRqRetryIndexQ_enqReq_lat_0$whas,
cache_rsFromMQ_deqReq_lat_0$whas,
cache_rsToCIndexQ_enqReq_lat_0$whas,
cache_toCQ_enqReq_lat_0$whas,
cache_toMQ_enqReq_lat_0$whas;
// register cache_cRqRetryIndexQ_clearReq_rl
reg cache_cRqRetryIndexQ_clearReq_rl;
wire cache_cRqRetryIndexQ_clearReq_rl$D_IN,
cache_cRqRetryIndexQ_clearReq_rl$EN;
// register cache_cRqRetryIndexQ_data_0
reg [3 : 0] cache_cRqRetryIndexQ_data_0;
wire [3 : 0] cache_cRqRetryIndexQ_data_0$D_IN;
wire cache_cRqRetryIndexQ_data_0$EN;
// register cache_cRqRetryIndexQ_data_1
reg [3 : 0] cache_cRqRetryIndexQ_data_1;
wire [3 : 0] cache_cRqRetryIndexQ_data_1$D_IN;
wire cache_cRqRetryIndexQ_data_1$EN;
// register cache_cRqRetryIndexQ_data_10
reg [3 : 0] cache_cRqRetryIndexQ_data_10;
wire [3 : 0] cache_cRqRetryIndexQ_data_10$D_IN;
wire cache_cRqRetryIndexQ_data_10$EN;
// register cache_cRqRetryIndexQ_data_11
reg [3 : 0] cache_cRqRetryIndexQ_data_11;
wire [3 : 0] cache_cRqRetryIndexQ_data_11$D_IN;
wire cache_cRqRetryIndexQ_data_11$EN;
// register cache_cRqRetryIndexQ_data_12
reg [3 : 0] cache_cRqRetryIndexQ_data_12;
wire [3 : 0] cache_cRqRetryIndexQ_data_12$D_IN;
wire cache_cRqRetryIndexQ_data_12$EN;
// register cache_cRqRetryIndexQ_data_13
reg [3 : 0] cache_cRqRetryIndexQ_data_13;
wire [3 : 0] cache_cRqRetryIndexQ_data_13$D_IN;
wire cache_cRqRetryIndexQ_data_13$EN;
// register cache_cRqRetryIndexQ_data_14
reg [3 : 0] cache_cRqRetryIndexQ_data_14;
wire [3 : 0] cache_cRqRetryIndexQ_data_14$D_IN;
wire cache_cRqRetryIndexQ_data_14$EN;
// register cache_cRqRetryIndexQ_data_15
reg [3 : 0] cache_cRqRetryIndexQ_data_15;
wire [3 : 0] cache_cRqRetryIndexQ_data_15$D_IN;
wire cache_cRqRetryIndexQ_data_15$EN;
// register cache_cRqRetryIndexQ_data_2
reg [3 : 0] cache_cRqRetryIndexQ_data_2;
wire [3 : 0] cache_cRqRetryIndexQ_data_2$D_IN;
wire cache_cRqRetryIndexQ_data_2$EN;
// register cache_cRqRetryIndexQ_data_3
reg [3 : 0] cache_cRqRetryIndexQ_data_3;
wire [3 : 0] cache_cRqRetryIndexQ_data_3$D_IN;
wire cache_cRqRetryIndexQ_data_3$EN;
// register cache_cRqRetryIndexQ_data_4
reg [3 : 0] cache_cRqRetryIndexQ_data_4;
wire [3 : 0] cache_cRqRetryIndexQ_data_4$D_IN;
wire cache_cRqRetryIndexQ_data_4$EN;
// register cache_cRqRetryIndexQ_data_5
reg [3 : 0] cache_cRqRetryIndexQ_data_5;
wire [3 : 0] cache_cRqRetryIndexQ_data_5$D_IN;
wire cache_cRqRetryIndexQ_data_5$EN;
// register cache_cRqRetryIndexQ_data_6
reg [3 : 0] cache_cRqRetryIndexQ_data_6;
wire [3 : 0] cache_cRqRetryIndexQ_data_6$D_IN;
wire cache_cRqRetryIndexQ_data_6$EN;
// register cache_cRqRetryIndexQ_data_7
reg [3 : 0] cache_cRqRetryIndexQ_data_7;
wire [3 : 0] cache_cRqRetryIndexQ_data_7$D_IN;
wire cache_cRqRetryIndexQ_data_7$EN;
// register cache_cRqRetryIndexQ_data_8
reg [3 : 0] cache_cRqRetryIndexQ_data_8;
wire [3 : 0] cache_cRqRetryIndexQ_data_8$D_IN;
wire cache_cRqRetryIndexQ_data_8$EN;
// register cache_cRqRetryIndexQ_data_9
reg [3 : 0] cache_cRqRetryIndexQ_data_9;
wire [3 : 0] cache_cRqRetryIndexQ_data_9$D_IN;
wire cache_cRqRetryIndexQ_data_9$EN;
// register cache_cRqRetryIndexQ_deqP
reg [3 : 0] cache_cRqRetryIndexQ_deqP;
wire [3 : 0] cache_cRqRetryIndexQ_deqP$D_IN;
wire cache_cRqRetryIndexQ_deqP$EN;
// register cache_cRqRetryIndexQ_deqReq_rl
reg cache_cRqRetryIndexQ_deqReq_rl;
wire cache_cRqRetryIndexQ_deqReq_rl$D_IN, cache_cRqRetryIndexQ_deqReq_rl$EN;
// register cache_cRqRetryIndexQ_empty
reg cache_cRqRetryIndexQ_empty;
wire cache_cRqRetryIndexQ_empty$D_IN, cache_cRqRetryIndexQ_empty$EN;
// register cache_cRqRetryIndexQ_enqP
reg [3 : 0] cache_cRqRetryIndexQ_enqP;
wire [3 : 0] cache_cRqRetryIndexQ_enqP$D_IN;
wire cache_cRqRetryIndexQ_enqP$EN;
// register cache_cRqRetryIndexQ_enqReq_rl
reg [4 : 0] cache_cRqRetryIndexQ_enqReq_rl;
wire [4 : 0] cache_cRqRetryIndexQ_enqReq_rl$D_IN;
wire cache_cRqRetryIndexQ_enqReq_rl$EN;
// register cache_cRqRetryIndexQ_full
reg cache_cRqRetryIndexQ_full;
wire cache_cRqRetryIndexQ_full$D_IN, cache_cRqRetryIndexQ_full$EN;
// register cache_doLdAfterReplace
reg cache_doLdAfterReplace;
wire cache_doLdAfterReplace$D_IN, cache_doLdAfterReplace$EN;
// register cache_priorNewCRqSrc
reg cache_priorNewCRqSrc;
wire cache_priorNewCRqSrc$D_IN, cache_priorNewCRqSrc$EN;
// register cache_rqFromCQ_clearReq_rl
reg cache_rqFromCQ_clearReq_rl;
wire cache_rqFromCQ_clearReq_rl$D_IN, cache_rqFromCQ_clearReq_rl$EN;
// register cache_rqFromCQ_data_0
reg [73 : 0] cache_rqFromCQ_data_0;
wire [73 : 0] cache_rqFromCQ_data_0$D_IN;
wire cache_rqFromCQ_data_0$EN;
// register cache_rqFromCQ_data_1
reg [73 : 0] cache_rqFromCQ_data_1;
wire [73 : 0] cache_rqFromCQ_data_1$D_IN;
wire cache_rqFromCQ_data_1$EN;
// register cache_rqFromCQ_deqP
reg cache_rqFromCQ_deqP;
wire cache_rqFromCQ_deqP$D_IN, cache_rqFromCQ_deqP$EN;
// register cache_rqFromCQ_deqReq_rl
reg cache_rqFromCQ_deqReq_rl;
wire cache_rqFromCQ_deqReq_rl$D_IN, cache_rqFromCQ_deqReq_rl$EN;
// register cache_rqFromCQ_empty
reg cache_rqFromCQ_empty;
wire cache_rqFromCQ_empty$D_IN, cache_rqFromCQ_empty$EN;
// register cache_rqFromCQ_enqP
reg cache_rqFromCQ_enqP;
wire cache_rqFromCQ_enqP$D_IN, cache_rqFromCQ_enqP$EN;
// register cache_rqFromCQ_enqReq_rl
reg [74 : 0] cache_rqFromCQ_enqReq_rl;
wire [74 : 0] cache_rqFromCQ_enqReq_rl$D_IN;
wire cache_rqFromCQ_enqReq_rl$EN;
// register cache_rqFromCQ_full
reg cache_rqFromCQ_full;
wire cache_rqFromCQ_full$D_IN, cache_rqFromCQ_full$EN;
// register cache_rqFromDmaQ_clearReq_rl
reg cache_rqFromDmaQ_clearReq_rl;
wire cache_rqFromDmaQ_clearReq_rl$D_IN, cache_rqFromDmaQ_clearReq_rl$EN;
// register cache_rqFromDmaQ_data_0
reg [655 : 0] cache_rqFromDmaQ_data_0;
wire [655 : 0] cache_rqFromDmaQ_data_0$D_IN;
wire cache_rqFromDmaQ_data_0$EN;
// register cache_rqFromDmaQ_data_1
reg [655 : 0] cache_rqFromDmaQ_data_1;
wire [655 : 0] cache_rqFromDmaQ_data_1$D_IN;
wire cache_rqFromDmaQ_data_1$EN;
// register cache_rqFromDmaQ_deqP
reg cache_rqFromDmaQ_deqP;
wire cache_rqFromDmaQ_deqP$D_IN, cache_rqFromDmaQ_deqP$EN;
// register cache_rqFromDmaQ_deqReq_rl
reg cache_rqFromDmaQ_deqReq_rl;
wire cache_rqFromDmaQ_deqReq_rl$D_IN, cache_rqFromDmaQ_deqReq_rl$EN;
// register cache_rqFromDmaQ_empty
reg cache_rqFromDmaQ_empty;
wire cache_rqFromDmaQ_empty$D_IN, cache_rqFromDmaQ_empty$EN;
// register cache_rqFromDmaQ_enqP
reg cache_rqFromDmaQ_enqP;
wire cache_rqFromDmaQ_enqP$D_IN, cache_rqFromDmaQ_enqP$EN;
// register cache_rqFromDmaQ_enqReq_rl
reg [656 : 0] cache_rqFromDmaQ_enqReq_rl;
wire [656 : 0] cache_rqFromDmaQ_enqReq_rl$D_IN;
wire cache_rqFromDmaQ_enqReq_rl$EN;
// register cache_rqFromDmaQ_full
reg cache_rqFromDmaQ_full;
wire cache_rqFromDmaQ_full$D_IN, cache_rqFromDmaQ_full$EN;
// register cache_rsFromCQ_clearReq_rl
reg cache_rsFromCQ_clearReq_rl;
wire cache_rsFromCQ_clearReq_rl$D_IN, cache_rsFromCQ_clearReq_rl$EN;
// register cache_rsFromCQ_data_0
reg [580 : 0] cache_rsFromCQ_data_0;
wire [580 : 0] cache_rsFromCQ_data_0$D_IN;
wire cache_rsFromCQ_data_0$EN;
// register cache_rsFromCQ_data_1
reg [580 : 0] cache_rsFromCQ_data_1;
wire [580 : 0] cache_rsFromCQ_data_1$D_IN;
wire cache_rsFromCQ_data_1$EN;
// register cache_rsFromCQ_deqP
reg cache_rsFromCQ_deqP;
wire cache_rsFromCQ_deqP$D_IN, cache_rsFromCQ_deqP$EN;
// register cache_rsFromCQ_deqReq_rl
reg cache_rsFromCQ_deqReq_rl;
wire cache_rsFromCQ_deqReq_rl$D_IN, cache_rsFromCQ_deqReq_rl$EN;
// register cache_rsFromCQ_empty
reg cache_rsFromCQ_empty;
wire cache_rsFromCQ_empty$D_IN, cache_rsFromCQ_empty$EN;
// register cache_rsFromCQ_enqP
reg cache_rsFromCQ_enqP;
wire cache_rsFromCQ_enqP$D_IN, cache_rsFromCQ_enqP$EN;
// register cache_rsFromCQ_enqReq_rl
reg [581 : 0] cache_rsFromCQ_enqReq_rl;
wire [581 : 0] cache_rsFromCQ_enqReq_rl$D_IN;
wire cache_rsFromCQ_enqReq_rl$EN;
// register cache_rsFromCQ_full
reg cache_rsFromCQ_full;
wire cache_rsFromCQ_full$D_IN, cache_rsFromCQ_full$EN;
// register cache_rsFromMQ_clearReq_rl
reg cache_rsFromMQ_clearReq_rl;
wire cache_rsFromMQ_clearReq_rl$D_IN, cache_rsFromMQ_clearReq_rl$EN;
// register cache_rsFromMQ_data_0
reg [516 : 0] cache_rsFromMQ_data_0;
wire [516 : 0] cache_rsFromMQ_data_0$D_IN;
wire cache_rsFromMQ_data_0$EN;
// register cache_rsFromMQ_data_1
reg [516 : 0] cache_rsFromMQ_data_1;
wire [516 : 0] cache_rsFromMQ_data_1$D_IN;
wire cache_rsFromMQ_data_1$EN;
// register cache_rsFromMQ_deqP
reg cache_rsFromMQ_deqP;
wire cache_rsFromMQ_deqP$D_IN, cache_rsFromMQ_deqP$EN;
// register cache_rsFromMQ_deqReq_rl
reg cache_rsFromMQ_deqReq_rl;
wire cache_rsFromMQ_deqReq_rl$D_IN, cache_rsFromMQ_deqReq_rl$EN;
// register cache_rsFromMQ_empty
reg cache_rsFromMQ_empty;
wire cache_rsFromMQ_empty$D_IN, cache_rsFromMQ_empty$EN;
// register cache_rsFromMQ_enqP
reg cache_rsFromMQ_enqP;
wire cache_rsFromMQ_enqP$D_IN, cache_rsFromMQ_enqP$EN;
// register cache_rsFromMQ_enqReq_rl
reg [517 : 0] cache_rsFromMQ_enqReq_rl;
wire [517 : 0] cache_rsFromMQ_enqReq_rl$D_IN;
wire cache_rsFromMQ_enqReq_rl$EN;
// register cache_rsFromMQ_full
reg cache_rsFromMQ_full;
wire cache_rsFromMQ_full$D_IN, cache_rsFromMQ_full$EN;
// register cache_rsLdToDmaQ_clearReq_rl
reg cache_rsLdToDmaQ_clearReq_rl;
wire cache_rsLdToDmaQ_clearReq_rl$D_IN, cache_rsLdToDmaQ_clearReq_rl$EN;
// register cache_rsLdToDmaQ_data_0
reg [527 : 0] cache_rsLdToDmaQ_data_0;
wire [527 : 0] cache_rsLdToDmaQ_data_0$D_IN;
wire cache_rsLdToDmaQ_data_0$EN;
// register cache_rsLdToDmaQ_data_1
reg [527 : 0] cache_rsLdToDmaQ_data_1;
wire [527 : 0] cache_rsLdToDmaQ_data_1$D_IN;
wire cache_rsLdToDmaQ_data_1$EN;
// register cache_rsLdToDmaQ_deqP
reg cache_rsLdToDmaQ_deqP;
wire cache_rsLdToDmaQ_deqP$D_IN, cache_rsLdToDmaQ_deqP$EN;
// register cache_rsLdToDmaQ_deqReq_rl
reg cache_rsLdToDmaQ_deqReq_rl;
wire cache_rsLdToDmaQ_deqReq_rl$D_IN, cache_rsLdToDmaQ_deqReq_rl$EN;
// register cache_rsLdToDmaQ_empty
reg cache_rsLdToDmaQ_empty;
wire cache_rsLdToDmaQ_empty$D_IN, cache_rsLdToDmaQ_empty$EN;
// register cache_rsLdToDmaQ_enqP
reg cache_rsLdToDmaQ_enqP;
wire cache_rsLdToDmaQ_enqP$D_IN, cache_rsLdToDmaQ_enqP$EN;
// register cache_rsLdToDmaQ_enqReq_rl
reg [528 : 0] cache_rsLdToDmaQ_enqReq_rl;
wire [528 : 0] cache_rsLdToDmaQ_enqReq_rl$D_IN;
wire cache_rsLdToDmaQ_enqReq_rl$EN;
// register cache_rsLdToDmaQ_full
reg cache_rsLdToDmaQ_full;
wire cache_rsLdToDmaQ_full$D_IN, cache_rsLdToDmaQ_full$EN;
// register cache_rsStToDmaQ_clearReq_rl
reg cache_rsStToDmaQ_clearReq_rl;
wire cache_rsStToDmaQ_clearReq_rl$D_IN, cache_rsStToDmaQ_clearReq_rl$EN;
// register cache_rsStToDmaQ_data_0
reg [15 : 0] cache_rsStToDmaQ_data_0;
wire [15 : 0] cache_rsStToDmaQ_data_0$D_IN;
wire cache_rsStToDmaQ_data_0$EN;
// register cache_rsStToDmaQ_data_1
reg [15 : 0] cache_rsStToDmaQ_data_1;
wire [15 : 0] cache_rsStToDmaQ_data_1$D_IN;
wire cache_rsStToDmaQ_data_1$EN;
// register cache_rsStToDmaQ_deqP
reg cache_rsStToDmaQ_deqP;
wire cache_rsStToDmaQ_deqP$D_IN, cache_rsStToDmaQ_deqP$EN;
// register cache_rsStToDmaQ_deqReq_rl
reg cache_rsStToDmaQ_deqReq_rl;
wire cache_rsStToDmaQ_deqReq_rl$D_IN, cache_rsStToDmaQ_deqReq_rl$EN;
// register cache_rsStToDmaQ_empty
reg cache_rsStToDmaQ_empty;
wire cache_rsStToDmaQ_empty$D_IN, cache_rsStToDmaQ_empty$EN;
// register cache_rsStToDmaQ_enqP
reg cache_rsStToDmaQ_enqP;
wire cache_rsStToDmaQ_enqP$D_IN, cache_rsStToDmaQ_enqP$EN;
// register cache_rsStToDmaQ_enqReq_rl
reg [16 : 0] cache_rsStToDmaQ_enqReq_rl;
wire [16 : 0] cache_rsStToDmaQ_enqReq_rl$D_IN;
wire cache_rsStToDmaQ_enqReq_rl$EN;
// register cache_rsStToDmaQ_full
reg cache_rsStToDmaQ_full;
wire cache_rsStToDmaQ_full$D_IN, cache_rsStToDmaQ_full$EN;
// register cache_rsToCIndexQ_clearReq_rl
reg cache_rsToCIndexQ_clearReq_rl;
wire cache_rsToCIndexQ_clearReq_rl$D_IN, cache_rsToCIndexQ_clearReq_rl$EN;
// register cache_rsToCIndexQ_data_0
reg [5 : 0] cache_rsToCIndexQ_data_0;
wire [5 : 0] cache_rsToCIndexQ_data_0$D_IN;
wire cache_rsToCIndexQ_data_0$EN;
// register cache_rsToCIndexQ_data_1
reg [5 : 0] cache_rsToCIndexQ_data_1;
wire [5 : 0] cache_rsToCIndexQ_data_1$D_IN;
wire cache_rsToCIndexQ_data_1$EN;
// register cache_rsToCIndexQ_data_10
reg [5 : 0] cache_rsToCIndexQ_data_10;
wire [5 : 0] cache_rsToCIndexQ_data_10$D_IN;
wire cache_rsToCIndexQ_data_10$EN;
// register cache_rsToCIndexQ_data_11
reg [5 : 0] cache_rsToCIndexQ_data_11;
wire [5 : 0] cache_rsToCIndexQ_data_11$D_IN;
wire cache_rsToCIndexQ_data_11$EN;
// register cache_rsToCIndexQ_data_12
reg [5 : 0] cache_rsToCIndexQ_data_12;
wire [5 : 0] cache_rsToCIndexQ_data_12$D_IN;
wire cache_rsToCIndexQ_data_12$EN;
// register cache_rsToCIndexQ_data_13
reg [5 : 0] cache_rsToCIndexQ_data_13;
wire [5 : 0] cache_rsToCIndexQ_data_13$D_IN;
wire cache_rsToCIndexQ_data_13$EN;
// register cache_rsToCIndexQ_data_14
reg [5 : 0] cache_rsToCIndexQ_data_14;
wire [5 : 0] cache_rsToCIndexQ_data_14$D_IN;
wire cache_rsToCIndexQ_data_14$EN;
// register cache_rsToCIndexQ_data_15
reg [5 : 0] cache_rsToCIndexQ_data_15;
wire [5 : 0] cache_rsToCIndexQ_data_15$D_IN;
wire cache_rsToCIndexQ_data_15$EN;
// register cache_rsToCIndexQ_data_2
reg [5 : 0] cache_rsToCIndexQ_data_2;
wire [5 : 0] cache_rsToCIndexQ_data_2$D_IN;
wire cache_rsToCIndexQ_data_2$EN;
// register cache_rsToCIndexQ_data_3
reg [5 : 0] cache_rsToCIndexQ_data_3;
wire [5 : 0] cache_rsToCIndexQ_data_3$D_IN;
wire cache_rsToCIndexQ_data_3$EN;
// register cache_rsToCIndexQ_data_4
reg [5 : 0] cache_rsToCIndexQ_data_4;
wire [5 : 0] cache_rsToCIndexQ_data_4$D_IN;
wire cache_rsToCIndexQ_data_4$EN;
// register cache_rsToCIndexQ_data_5
reg [5 : 0] cache_rsToCIndexQ_data_5;
wire [5 : 0] cache_rsToCIndexQ_data_5$D_IN;
wire cache_rsToCIndexQ_data_5$EN;
// register cache_rsToCIndexQ_data_6
reg [5 : 0] cache_rsToCIndexQ_data_6;
wire [5 : 0] cache_rsToCIndexQ_data_6$D_IN;
wire cache_rsToCIndexQ_data_6$EN;
// register cache_rsToCIndexQ_data_7
reg [5 : 0] cache_rsToCIndexQ_data_7;
wire [5 : 0] cache_rsToCIndexQ_data_7$D_IN;
wire cache_rsToCIndexQ_data_7$EN;
// register cache_rsToCIndexQ_data_8
reg [5 : 0] cache_rsToCIndexQ_data_8;
wire [5 : 0] cache_rsToCIndexQ_data_8$D_IN;
wire cache_rsToCIndexQ_data_8$EN;
// register cache_rsToCIndexQ_data_9
reg [5 : 0] cache_rsToCIndexQ_data_9;
wire [5 : 0] cache_rsToCIndexQ_data_9$D_IN;
wire cache_rsToCIndexQ_data_9$EN;
// register cache_rsToCIndexQ_deqP
reg [3 : 0] cache_rsToCIndexQ_deqP;
wire [3 : 0] cache_rsToCIndexQ_deqP$D_IN;
wire cache_rsToCIndexQ_deqP$EN;
// register cache_rsToCIndexQ_deqReq_rl
reg cache_rsToCIndexQ_deqReq_rl;
wire cache_rsToCIndexQ_deqReq_rl$D_IN, cache_rsToCIndexQ_deqReq_rl$EN;
// register cache_rsToCIndexQ_empty
reg cache_rsToCIndexQ_empty;
wire cache_rsToCIndexQ_empty$D_IN, cache_rsToCIndexQ_empty$EN;
// register cache_rsToCIndexQ_enqP
reg [3 : 0] cache_rsToCIndexQ_enqP;
wire [3 : 0] cache_rsToCIndexQ_enqP$D_IN;
wire cache_rsToCIndexQ_enqP$EN;
// register cache_rsToCIndexQ_enqReq_rl
reg [6 : 0] cache_rsToCIndexQ_enqReq_rl;
wire [6 : 0] cache_rsToCIndexQ_enqReq_rl$D_IN;
wire cache_rsToCIndexQ_enqReq_rl$EN;
// register cache_rsToCIndexQ_full
reg cache_rsToCIndexQ_full;
wire cache_rsToCIndexQ_full$D_IN, cache_rsToCIndexQ_full$EN;
// register cache_toCQ_clearReq_rl
reg cache_toCQ_clearReq_rl;
wire cache_toCQ_clearReq_rl$D_IN, cache_toCQ_clearReq_rl$EN;
// register cache_toCQ_data_0
reg [584 : 0] cache_toCQ_data_0;
wire [584 : 0] cache_toCQ_data_0$D_IN;
wire cache_toCQ_data_0$EN;
// register cache_toCQ_data_1
reg [584 : 0] cache_toCQ_data_1;
wire [584 : 0] cache_toCQ_data_1$D_IN;
wire cache_toCQ_data_1$EN;
// register cache_toCQ_deqP
reg cache_toCQ_deqP;
wire cache_toCQ_deqP$D_IN, cache_toCQ_deqP$EN;
// register cache_toCQ_deqReq_rl
reg cache_toCQ_deqReq_rl;
wire cache_toCQ_deqReq_rl$D_IN, cache_toCQ_deqReq_rl$EN;
// register cache_toCQ_empty
reg cache_toCQ_empty;
wire cache_toCQ_empty$D_IN, cache_toCQ_empty$EN;
// register cache_toCQ_enqP
reg cache_toCQ_enqP;
wire cache_toCQ_enqP$D_IN, cache_toCQ_enqP$EN;
// register cache_toCQ_enqReq_rl
reg [585 : 0] cache_toCQ_enqReq_rl;
wire [585 : 0] cache_toCQ_enqReq_rl$D_IN;
wire cache_toCQ_enqReq_rl$EN;
// register cache_toCQ_full
reg cache_toCQ_full;
wire cache_toCQ_full$D_IN, cache_toCQ_full$EN;
// register cache_toMQ_clearReq_rl
reg cache_toMQ_clearReq_rl;
wire cache_toMQ_clearReq_rl$D_IN, cache_toMQ_clearReq_rl$EN;
// register cache_toMQ_data_0
reg [640 : 0] cache_toMQ_data_0;
wire [640 : 0] cache_toMQ_data_0$D_IN;
wire cache_toMQ_data_0$EN;
// register cache_toMQ_data_1
reg [640 : 0] cache_toMQ_data_1;
wire [640 : 0] cache_toMQ_data_1$D_IN;
wire cache_toMQ_data_1$EN;
// register cache_toMQ_deqP
reg cache_toMQ_deqP;
wire cache_toMQ_deqP$D_IN, cache_toMQ_deqP$EN;
// register cache_toMQ_deqReq_rl
reg cache_toMQ_deqReq_rl;
wire cache_toMQ_deqReq_rl$D_IN, cache_toMQ_deqReq_rl$EN;
// register cache_toMQ_empty
reg cache_toMQ_empty;
wire cache_toMQ_empty$D_IN, cache_toMQ_empty$EN;
// register cache_toMQ_enqP
reg cache_toMQ_enqP;
wire cache_toMQ_enqP$D_IN, cache_toMQ_enqP$EN;
// register cache_toMQ_enqReq_rl
reg [641 : 0] cache_toMQ_enqReq_rl;
wire [641 : 0] cache_toMQ_enqReq_rl$D_IN;
wire cache_toMQ_enqReq_rl$EN;
// register cache_toMQ_full
reg cache_toMQ_full;
wire cache_toMQ_full$D_IN, cache_toMQ_full$EN;
// register cache_whichCRq
reg [3 : 0] cache_whichCRq;
wire [3 : 0] cache_whichCRq$D_IN;
wire cache_whichCRq$EN;
// register perfReqQ_clearReq_rl
reg perfReqQ_clearReq_rl;
wire perfReqQ_clearReq_rl$D_IN, perfReqQ_clearReq_rl$EN;
// register perfReqQ_data_0
reg [3 : 0] perfReqQ_data_0;
wire [3 : 0] perfReqQ_data_0$D_IN;
wire perfReqQ_data_0$EN;
// register perfReqQ_deqReq_rl
reg perfReqQ_deqReq_rl;
wire perfReqQ_deqReq_rl$D_IN, perfReqQ_deqReq_rl$EN;
// register perfReqQ_empty
reg perfReqQ_empty;
wire perfReqQ_empty$D_IN, perfReqQ_empty$EN;
// register perfReqQ_enqReq_rl
reg [4 : 0] perfReqQ_enqReq_rl;
wire [4 : 0] perfReqQ_enqReq_rl$D_IN;
wire perfReqQ_enqReq_rl$EN;
// register perfReqQ_full
reg perfReqQ_full;
wire perfReqQ_full$D_IN, perfReqQ_full$EN;
// ports of submodule cache_cRqMshr
reg [512 : 0] cache_cRqMshr$pipelineResp_setData_d;
reg [64 : 0] cache_cRqMshr$pipelineResp_setStateSlot_slot;
reg [3 : 0] cache_cRqMshr$sendRsToDmaC_getRq_n,
cache_cRqMshr$sendRsToDmaC_releaseEntry_n;
reg [2 : 0] cache_cRqMshr$pipelineResp_setStateSlot_state;
wire [512 : 0] cache_cRqMshr$mRsDeq_setData_d,
cache_cRqMshr$pipelineResp_getData,
cache_cRqMshr$sendRsToDmaC_getData,
cache_cRqMshr$sendToM_getData,
cache_cRqMshr$transfer_getEmptyEntryInit_d;
wire [167 : 0] cache_cRqMshr$stuck_get;
wire [151 : 0] cache_cRqMshr$pipelineResp_getRq,
cache_cRqMshr$sendRqToC_getRq,
cache_cRqMshr$sendRsToDmaC_getRq,
cache_cRqMshr$sendToM_getRq,
cache_cRqMshr$transfer_getEmptyEntryInit_r,
cache_cRqMshr$transfer_getRq,
cache_cRqMshr$transfer_hasEmptyEntry_r;
wire [64 : 0] cache_cRqMshr$pipelineResp_getSlot,
cache_cRqMshr$sendRqToC_getSlot,
cache_cRqMshr$sendRqToC_setSlot_s,
cache_cRqMshr$sendToM_getSlot,
cache_cRqMshr$transfer_getSlot;
wire [63 : 0] cache_cRqMshr$pipelineResp_searchEndOfChain_addr;
wire [4 : 0] cache_cRqMshr$pipelineResp_getAddrSucc,
cache_cRqMshr$pipelineResp_getRepSucc,
cache_cRqMshr$pipelineResp_searchEndOfChain,
cache_cRqMshr$pipelineResp_setAddrSucc_succ,
cache_cRqMshr$pipelineResp_setRepSucc_succ,
cache_cRqMshr$sendRqToC_searchNeedRqChild,
cache_cRqMshr$sendRqToC_searchNeedRqChild_suggestIdx;
wire [3 : 0] cache_cRqMshr$mRsDeq_setData_n,
cache_cRqMshr$pipelineResp_getAddrSucc_n,
cache_cRqMshr$pipelineResp_getData_n,
cache_cRqMshr$pipelineResp_getRepSucc_n,
cache_cRqMshr$pipelineResp_getRq_n,
cache_cRqMshr$pipelineResp_getSlot_n,
cache_cRqMshr$pipelineResp_getState_n,
cache_cRqMshr$pipelineResp_setAddrSucc_n,
cache_cRqMshr$pipelineResp_setData_n,
cache_cRqMshr$pipelineResp_setRepSucc_n,
cache_cRqMshr$pipelineResp_setStateSlot_n,
cache_cRqMshr$sendRqToC_getRq_n,
cache_cRqMshr$sendRqToC_getSlot_n,
cache_cRqMshr$sendRqToC_getState_n,
cache_cRqMshr$sendRqToC_setSlot_n,
cache_cRqMshr$sendRsToDmaC_getData_n,
cache_cRqMshr$sendToM_getData_n,
cache_cRqMshr$sendToM_getRq_n,
cache_cRqMshr$sendToM_getSlot_n,
cache_cRqMshr$transfer_getEmptyEntryInit,
cache_cRqMshr$transfer_getRq_n,
cache_cRqMshr$transfer_getSlot_n;
wire [2 : 0] cache_cRqMshr$pipelineResp_getState,
cache_cRqMshr$sendRqToC_getState;
wire cache_cRqMshr$EN_mRsDeq_setData,
cache_cRqMshr$EN_pipelineResp_setAddrSucc,
cache_cRqMshr$EN_pipelineResp_setData,
cache_cRqMshr$EN_pipelineResp_setRepSucc,
cache_cRqMshr$EN_pipelineResp_setStateSlot,
cache_cRqMshr$EN_sendRqToC_setSlot,
cache_cRqMshr$EN_sendRsToDmaC_releaseEntry,
cache_cRqMshr$EN_stuck_get,
cache_cRqMshr$EN_transfer_getEmptyEntryInit,
cache_cRqMshr$RDY_sendRsToDmaC_releaseEntry,
cache_cRqMshr$RDY_stuck_get,
cache_cRqMshr$RDY_transfer_getEmptyEntryInit;
// ports of submodule cache_cRqRetryIndexQ_clearReq_dummy2_0
wire cache_cRqRetryIndexQ_clearReq_dummy2_0$D_IN,
cache_cRqRetryIndexQ_clearReq_dummy2_0$EN;
// ports of submodule cache_cRqRetryIndexQ_clearReq_dummy2_1
wire cache_cRqRetryIndexQ_clearReq_dummy2_1$D_IN,
cache_cRqRetryIndexQ_clearReq_dummy2_1$EN,
cache_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_cRqRetryIndexQ_deqReq_dummy2_0
wire cache_cRqRetryIndexQ_deqReq_dummy2_0$D_IN,
cache_cRqRetryIndexQ_deqReq_dummy2_0$EN;
// ports of submodule cache_cRqRetryIndexQ_deqReq_dummy2_1
wire cache_cRqRetryIndexQ_deqReq_dummy2_1$D_IN,
cache_cRqRetryIndexQ_deqReq_dummy2_1$EN;
// ports of submodule cache_cRqRetryIndexQ_deqReq_dummy2_2
wire cache_cRqRetryIndexQ_deqReq_dummy2_2$D_IN,
cache_cRqRetryIndexQ_deqReq_dummy2_2$EN,
cache_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_cRqRetryIndexQ_enqReq_dummy2_0
wire cache_cRqRetryIndexQ_enqReq_dummy2_0$D_IN,
cache_cRqRetryIndexQ_enqReq_dummy2_0$EN;
// ports of submodule cache_cRqRetryIndexQ_enqReq_dummy2_1
wire cache_cRqRetryIndexQ_enqReq_dummy2_1$D_IN,
cache_cRqRetryIndexQ_enqReq_dummy2_1$EN;
// ports of submodule cache_cRqRetryIndexQ_enqReq_dummy2_2
wire cache_cRqRetryIndexQ_enqReq_dummy2_2$D_IN,
cache_cRqRetryIndexQ_enqReq_dummy2_2$EN,
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_pipeline
reg [583 : 0] cache_pipeline$send_r;
reg [573 : 0] cache_pipeline$deqWrite_wrRam;
reg [4 : 0] cache_pipeline$deqWrite_swapRq;
reg cache_pipeline$deqWrite_updateRep;
wire [584 : 0] cache_pipeline$first, cache_pipeline$unguard_first;
wire cache_pipeline$EN_deqWrite,
cache_pipeline$EN_send,
cache_pipeline$RDY_deqWrite,
cache_pipeline$RDY_first,
cache_pipeline$RDY_send,
cache_pipeline$RDY_unguard_first,
cache_pipeline$notEmpty;
// ports of submodule cache_rqFromCQ_clearReq_dummy2_0
wire cache_rqFromCQ_clearReq_dummy2_0$D_IN,
cache_rqFromCQ_clearReq_dummy2_0$EN;
// ports of submodule cache_rqFromCQ_clearReq_dummy2_1
wire cache_rqFromCQ_clearReq_dummy2_1$D_IN,
cache_rqFromCQ_clearReq_dummy2_1$EN,
cache_rqFromCQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_rqFromCQ_deqReq_dummy2_0
wire cache_rqFromCQ_deqReq_dummy2_0$D_IN, cache_rqFromCQ_deqReq_dummy2_0$EN;
// ports of submodule cache_rqFromCQ_deqReq_dummy2_1
wire cache_rqFromCQ_deqReq_dummy2_1$D_IN, cache_rqFromCQ_deqReq_dummy2_1$EN;
// ports of submodule cache_rqFromCQ_deqReq_dummy2_2
wire cache_rqFromCQ_deqReq_dummy2_2$D_IN,
cache_rqFromCQ_deqReq_dummy2_2$EN,
cache_rqFromCQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rqFromCQ_enqReq_dummy2_0
wire cache_rqFromCQ_enqReq_dummy2_0$D_IN, cache_rqFromCQ_enqReq_dummy2_0$EN;
// ports of submodule cache_rqFromCQ_enqReq_dummy2_1
wire cache_rqFromCQ_enqReq_dummy2_1$D_IN, cache_rqFromCQ_enqReq_dummy2_1$EN;
// ports of submodule cache_rqFromCQ_enqReq_dummy2_2
wire cache_rqFromCQ_enqReq_dummy2_2$D_IN,
cache_rqFromCQ_enqReq_dummy2_2$EN,
cache_rqFromCQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rqFromDmaQ_clearReq_dummy2_0
wire cache_rqFromDmaQ_clearReq_dummy2_0$D_IN,
cache_rqFromDmaQ_clearReq_dummy2_0$EN;
// ports of submodule cache_rqFromDmaQ_clearReq_dummy2_1
wire cache_rqFromDmaQ_clearReq_dummy2_1$D_IN,
cache_rqFromDmaQ_clearReq_dummy2_1$EN,
cache_rqFromDmaQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_rqFromDmaQ_deqReq_dummy2_0
wire cache_rqFromDmaQ_deqReq_dummy2_0$D_IN,
cache_rqFromDmaQ_deqReq_dummy2_0$EN;
// ports of submodule cache_rqFromDmaQ_deqReq_dummy2_1
wire cache_rqFromDmaQ_deqReq_dummy2_1$D_IN,
cache_rqFromDmaQ_deqReq_dummy2_1$EN;
// ports of submodule cache_rqFromDmaQ_deqReq_dummy2_2
wire cache_rqFromDmaQ_deqReq_dummy2_2$D_IN,
cache_rqFromDmaQ_deqReq_dummy2_2$EN,
cache_rqFromDmaQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rqFromDmaQ_enqReq_dummy2_0
wire cache_rqFromDmaQ_enqReq_dummy2_0$D_IN,
cache_rqFromDmaQ_enqReq_dummy2_0$EN;
// ports of submodule cache_rqFromDmaQ_enqReq_dummy2_1
wire cache_rqFromDmaQ_enqReq_dummy2_1$D_IN,
cache_rqFromDmaQ_enqReq_dummy2_1$EN;
// ports of submodule cache_rqFromDmaQ_enqReq_dummy2_2
wire cache_rqFromDmaQ_enqReq_dummy2_2$D_IN,
cache_rqFromDmaQ_enqReq_dummy2_2$EN,
cache_rqFromDmaQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsFromCQ_clearReq_dummy2_0
wire cache_rsFromCQ_clearReq_dummy2_0$D_IN,
cache_rsFromCQ_clearReq_dummy2_0$EN;
// ports of submodule cache_rsFromCQ_clearReq_dummy2_1
wire cache_rsFromCQ_clearReq_dummy2_1$D_IN,
cache_rsFromCQ_clearReq_dummy2_1$EN,
cache_rsFromCQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_rsFromCQ_deqReq_dummy2_0
wire cache_rsFromCQ_deqReq_dummy2_0$D_IN, cache_rsFromCQ_deqReq_dummy2_0$EN;
// ports of submodule cache_rsFromCQ_deqReq_dummy2_1
wire cache_rsFromCQ_deqReq_dummy2_1$D_IN, cache_rsFromCQ_deqReq_dummy2_1$EN;
// ports of submodule cache_rsFromCQ_deqReq_dummy2_2
wire cache_rsFromCQ_deqReq_dummy2_2$D_IN,
cache_rsFromCQ_deqReq_dummy2_2$EN,
cache_rsFromCQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsFromCQ_enqReq_dummy2_0
wire cache_rsFromCQ_enqReq_dummy2_0$D_IN, cache_rsFromCQ_enqReq_dummy2_0$EN;
// ports of submodule cache_rsFromCQ_enqReq_dummy2_1
wire cache_rsFromCQ_enqReq_dummy2_1$D_IN, cache_rsFromCQ_enqReq_dummy2_1$EN;
// ports of submodule cache_rsFromCQ_enqReq_dummy2_2
wire cache_rsFromCQ_enqReq_dummy2_2$D_IN,
cache_rsFromCQ_enqReq_dummy2_2$EN,
cache_rsFromCQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsFromMQ_clearReq_dummy2_0
wire cache_rsFromMQ_clearReq_dummy2_0$D_IN,
cache_rsFromMQ_clearReq_dummy2_0$EN;
// ports of submodule cache_rsFromMQ_clearReq_dummy2_1
wire cache_rsFromMQ_clearReq_dummy2_1$D_IN,
cache_rsFromMQ_clearReq_dummy2_1$EN,
cache_rsFromMQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_rsFromMQ_deqReq_dummy2_0
wire cache_rsFromMQ_deqReq_dummy2_0$D_IN, cache_rsFromMQ_deqReq_dummy2_0$EN;
// ports of submodule cache_rsFromMQ_deqReq_dummy2_1
wire cache_rsFromMQ_deqReq_dummy2_1$D_IN, cache_rsFromMQ_deqReq_dummy2_1$EN;
// ports of submodule cache_rsFromMQ_deqReq_dummy2_2
wire cache_rsFromMQ_deqReq_dummy2_2$D_IN,
cache_rsFromMQ_deqReq_dummy2_2$EN,
cache_rsFromMQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsFromMQ_enqReq_dummy2_0
wire cache_rsFromMQ_enqReq_dummy2_0$D_IN, cache_rsFromMQ_enqReq_dummy2_0$EN;
// ports of submodule cache_rsFromMQ_enqReq_dummy2_1
wire cache_rsFromMQ_enqReq_dummy2_1$D_IN, cache_rsFromMQ_enqReq_dummy2_1$EN;
// ports of submodule cache_rsFromMQ_enqReq_dummy2_2
wire cache_rsFromMQ_enqReq_dummy2_2$D_IN,
cache_rsFromMQ_enqReq_dummy2_2$EN,
cache_rsFromMQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsLdToDmaIndexQ
wire [3 : 0] cache_rsLdToDmaIndexQ$D_IN, cache_rsLdToDmaIndexQ$D_OUT;
wire cache_rsLdToDmaIndexQ$CLR,
cache_rsLdToDmaIndexQ$DEQ,
cache_rsLdToDmaIndexQ$EMPTY_N,
cache_rsLdToDmaIndexQ$ENQ,
cache_rsLdToDmaIndexQ$FULL_N;
// ports of submodule cache_rsLdToDmaIndexQ_mRsDeq
wire [3 : 0] cache_rsLdToDmaIndexQ_mRsDeq$D_IN,
cache_rsLdToDmaIndexQ_mRsDeq$D_OUT;
wire cache_rsLdToDmaIndexQ_mRsDeq$CLR,
cache_rsLdToDmaIndexQ_mRsDeq$DEQ,
cache_rsLdToDmaIndexQ_mRsDeq$EMPTY_N,
cache_rsLdToDmaIndexQ_mRsDeq$ENQ,
cache_rsLdToDmaIndexQ_mRsDeq$FULL_N;
// ports of submodule cache_rsLdToDmaIndexQ_pipelineResp
wire [3 : 0] cache_rsLdToDmaIndexQ_pipelineResp$D_IN,
cache_rsLdToDmaIndexQ_pipelineResp$D_OUT;
wire cache_rsLdToDmaIndexQ_pipelineResp$CLR,
cache_rsLdToDmaIndexQ_pipelineResp$DEQ,
cache_rsLdToDmaIndexQ_pipelineResp$EMPTY_N,
cache_rsLdToDmaIndexQ_pipelineResp$ENQ,
cache_rsLdToDmaIndexQ_pipelineResp$FULL_N;
// ports of submodule cache_rsLdToDmaQ_clearReq_dummy2_0
wire cache_rsLdToDmaQ_clearReq_dummy2_0$D_IN,
cache_rsLdToDmaQ_clearReq_dummy2_0$EN;
// ports of submodule cache_rsLdToDmaQ_clearReq_dummy2_1
wire cache_rsLdToDmaQ_clearReq_dummy2_1$D_IN,
cache_rsLdToDmaQ_clearReq_dummy2_1$EN,
cache_rsLdToDmaQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_rsLdToDmaQ_deqReq_dummy2_0
wire cache_rsLdToDmaQ_deqReq_dummy2_0$D_IN,
cache_rsLdToDmaQ_deqReq_dummy2_0$EN;
// ports of submodule cache_rsLdToDmaQ_deqReq_dummy2_1
wire cache_rsLdToDmaQ_deqReq_dummy2_1$D_IN,
cache_rsLdToDmaQ_deqReq_dummy2_1$EN;
// ports of submodule cache_rsLdToDmaQ_deqReq_dummy2_2
wire cache_rsLdToDmaQ_deqReq_dummy2_2$D_IN,
cache_rsLdToDmaQ_deqReq_dummy2_2$EN,
cache_rsLdToDmaQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsLdToDmaQ_enqReq_dummy2_0
wire cache_rsLdToDmaQ_enqReq_dummy2_0$D_IN,
cache_rsLdToDmaQ_enqReq_dummy2_0$EN;
// ports of submodule cache_rsLdToDmaQ_enqReq_dummy2_1
wire cache_rsLdToDmaQ_enqReq_dummy2_1$D_IN,
cache_rsLdToDmaQ_enqReq_dummy2_1$EN;
// ports of submodule cache_rsLdToDmaQ_enqReq_dummy2_2
wire cache_rsLdToDmaQ_enqReq_dummy2_2$D_IN,
cache_rsLdToDmaQ_enqReq_dummy2_2$EN,
cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsStToDmaIndexQ
wire [3 : 0] cache_rsStToDmaIndexQ$D_IN, cache_rsStToDmaIndexQ$D_OUT;
wire cache_rsStToDmaIndexQ$CLR,
cache_rsStToDmaIndexQ$DEQ,
cache_rsStToDmaIndexQ$EMPTY_N,
cache_rsStToDmaIndexQ$ENQ,
cache_rsStToDmaIndexQ$FULL_N;
// ports of submodule cache_rsStToDmaIndexQ_pipelineResp
wire [3 : 0] cache_rsStToDmaIndexQ_pipelineResp$D_IN,
cache_rsStToDmaIndexQ_pipelineResp$D_OUT;
wire cache_rsStToDmaIndexQ_pipelineResp$CLR,
cache_rsStToDmaIndexQ_pipelineResp$DEQ,
cache_rsStToDmaIndexQ_pipelineResp$EMPTY_N,
cache_rsStToDmaIndexQ_pipelineResp$ENQ,
cache_rsStToDmaIndexQ_pipelineResp$FULL_N;
// ports of submodule cache_rsStToDmaIndexQ_sendToM
wire [3 : 0] cache_rsStToDmaIndexQ_sendToM$D_IN,
cache_rsStToDmaIndexQ_sendToM$D_OUT;
wire cache_rsStToDmaIndexQ_sendToM$CLR,
cache_rsStToDmaIndexQ_sendToM$DEQ,
cache_rsStToDmaIndexQ_sendToM$EMPTY_N,
cache_rsStToDmaIndexQ_sendToM$ENQ,
cache_rsStToDmaIndexQ_sendToM$FULL_N;
// ports of submodule cache_rsStToDmaQ_clearReq_dummy2_0
wire cache_rsStToDmaQ_clearReq_dummy2_0$D_IN,
cache_rsStToDmaQ_clearReq_dummy2_0$EN;
// ports of submodule cache_rsStToDmaQ_clearReq_dummy2_1
wire cache_rsStToDmaQ_clearReq_dummy2_1$D_IN,
cache_rsStToDmaQ_clearReq_dummy2_1$EN,
cache_rsStToDmaQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_rsStToDmaQ_deqReq_dummy2_0
wire cache_rsStToDmaQ_deqReq_dummy2_0$D_IN,
cache_rsStToDmaQ_deqReq_dummy2_0$EN;
// ports of submodule cache_rsStToDmaQ_deqReq_dummy2_1
wire cache_rsStToDmaQ_deqReq_dummy2_1$D_IN,
cache_rsStToDmaQ_deqReq_dummy2_1$EN;
// ports of submodule cache_rsStToDmaQ_deqReq_dummy2_2
wire cache_rsStToDmaQ_deqReq_dummy2_2$D_IN,
cache_rsStToDmaQ_deqReq_dummy2_2$EN,
cache_rsStToDmaQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsStToDmaQ_enqReq_dummy2_0
wire cache_rsStToDmaQ_enqReq_dummy2_0$D_IN,
cache_rsStToDmaQ_enqReq_dummy2_0$EN;
// ports of submodule cache_rsStToDmaQ_enqReq_dummy2_1
wire cache_rsStToDmaQ_enqReq_dummy2_1$D_IN,
cache_rsStToDmaQ_enqReq_dummy2_1$EN;
// ports of submodule cache_rsStToDmaQ_enqReq_dummy2_2
wire cache_rsStToDmaQ_enqReq_dummy2_2$D_IN,
cache_rsStToDmaQ_enqReq_dummy2_2$EN,
cache_rsStToDmaQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsToCIndexQ_clearReq_dummy2_0
wire cache_rsToCIndexQ_clearReq_dummy2_0$D_IN,
cache_rsToCIndexQ_clearReq_dummy2_0$EN;
// ports of submodule cache_rsToCIndexQ_clearReq_dummy2_1
wire cache_rsToCIndexQ_clearReq_dummy2_1$D_IN,
cache_rsToCIndexQ_clearReq_dummy2_1$EN,
cache_rsToCIndexQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_rsToCIndexQ_deqReq_dummy2_0
wire cache_rsToCIndexQ_deqReq_dummy2_0$D_IN,
cache_rsToCIndexQ_deqReq_dummy2_0$EN;
// ports of submodule cache_rsToCIndexQ_deqReq_dummy2_1
wire cache_rsToCIndexQ_deqReq_dummy2_1$D_IN,
cache_rsToCIndexQ_deqReq_dummy2_1$EN;
// ports of submodule cache_rsToCIndexQ_deqReq_dummy2_2
wire cache_rsToCIndexQ_deqReq_dummy2_2$D_IN,
cache_rsToCIndexQ_deqReq_dummy2_2$EN,
cache_rsToCIndexQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_rsToCIndexQ_enqReq_dummy2_0
wire cache_rsToCIndexQ_enqReq_dummy2_0$D_IN,
cache_rsToCIndexQ_enqReq_dummy2_0$EN;
// ports of submodule cache_rsToCIndexQ_enqReq_dummy2_1
wire cache_rsToCIndexQ_enqReq_dummy2_1$D_IN,
cache_rsToCIndexQ_enqReq_dummy2_1$EN;
// ports of submodule cache_rsToCIndexQ_enqReq_dummy2_2
wire cache_rsToCIndexQ_enqReq_dummy2_2$D_IN,
cache_rsToCIndexQ_enqReq_dummy2_2$EN,
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_toCQ_clearReq_dummy2_0
wire cache_toCQ_clearReq_dummy2_0$D_IN, cache_toCQ_clearReq_dummy2_0$EN;
// ports of submodule cache_toCQ_clearReq_dummy2_1
wire cache_toCQ_clearReq_dummy2_1$D_IN,
cache_toCQ_clearReq_dummy2_1$EN,
cache_toCQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_toCQ_deqReq_dummy2_0
wire cache_toCQ_deqReq_dummy2_0$D_IN, cache_toCQ_deqReq_dummy2_0$EN;
// ports of submodule cache_toCQ_deqReq_dummy2_1
wire cache_toCQ_deqReq_dummy2_1$D_IN, cache_toCQ_deqReq_dummy2_1$EN;
// ports of submodule cache_toCQ_deqReq_dummy2_2
wire cache_toCQ_deqReq_dummy2_2$D_IN,
cache_toCQ_deqReq_dummy2_2$EN,
cache_toCQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_toCQ_enqReq_dummy2_0
wire cache_toCQ_enqReq_dummy2_0$D_IN, cache_toCQ_enqReq_dummy2_0$EN;
// ports of submodule cache_toCQ_enqReq_dummy2_1
wire cache_toCQ_enqReq_dummy2_1$D_IN, cache_toCQ_enqReq_dummy2_1$EN;
// ports of submodule cache_toCQ_enqReq_dummy2_2
wire cache_toCQ_enqReq_dummy2_2$D_IN,
cache_toCQ_enqReq_dummy2_2$EN,
cache_toCQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule cache_toMInfoQ
wire [5 : 0] cache_toMInfoQ$D_IN, cache_toMInfoQ$D_OUT;
wire cache_toMInfoQ$CLR,
cache_toMInfoQ$DEQ,
cache_toMInfoQ$EMPTY_N,
cache_toMInfoQ$ENQ,
cache_toMInfoQ$FULL_N;
// ports of submodule cache_toMQ_clearReq_dummy2_0
wire cache_toMQ_clearReq_dummy2_0$D_IN, cache_toMQ_clearReq_dummy2_0$EN;
// ports of submodule cache_toMQ_clearReq_dummy2_1
wire cache_toMQ_clearReq_dummy2_1$D_IN,
cache_toMQ_clearReq_dummy2_1$EN,
cache_toMQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule cache_toMQ_deqReq_dummy2_0
wire cache_toMQ_deqReq_dummy2_0$D_IN, cache_toMQ_deqReq_dummy2_0$EN;
// ports of submodule cache_toMQ_deqReq_dummy2_1
wire cache_toMQ_deqReq_dummy2_1$D_IN, cache_toMQ_deqReq_dummy2_1$EN;
// ports of submodule cache_toMQ_deqReq_dummy2_2
wire cache_toMQ_deqReq_dummy2_2$D_IN,
cache_toMQ_deqReq_dummy2_2$EN,
cache_toMQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule cache_toMQ_enqReq_dummy2_0
wire cache_toMQ_enqReq_dummy2_0$D_IN, cache_toMQ_enqReq_dummy2_0$EN;
// ports of submodule cache_toMQ_enqReq_dummy2_1
wire cache_toMQ_enqReq_dummy2_1$D_IN, cache_toMQ_enqReq_dummy2_1$EN;
// ports of submodule cache_toMQ_enqReq_dummy2_2
wire cache_toMQ_enqReq_dummy2_2$D_IN,
cache_toMQ_enqReq_dummy2_2$EN,
cache_toMQ_enqReq_dummy2_2$Q_OUT;
// ports of submodule perfReqQ_clearReq_dummy2_0
wire perfReqQ_clearReq_dummy2_0$D_IN, perfReqQ_clearReq_dummy2_0$EN;
// ports of submodule perfReqQ_clearReq_dummy2_1
wire perfReqQ_clearReq_dummy2_1$D_IN,
perfReqQ_clearReq_dummy2_1$EN,
perfReqQ_clearReq_dummy2_1$Q_OUT;
// ports of submodule perfReqQ_deqReq_dummy2_0
wire perfReqQ_deqReq_dummy2_0$D_IN, perfReqQ_deqReq_dummy2_0$EN;
// ports of submodule perfReqQ_deqReq_dummy2_1
wire perfReqQ_deqReq_dummy2_1$D_IN, perfReqQ_deqReq_dummy2_1$EN;
// ports of submodule perfReqQ_deqReq_dummy2_2
wire perfReqQ_deqReq_dummy2_2$D_IN,
perfReqQ_deqReq_dummy2_2$EN,
perfReqQ_deqReq_dummy2_2$Q_OUT;
// ports of submodule perfReqQ_enqReq_dummy2_0
wire perfReqQ_enqReq_dummy2_0$D_IN, perfReqQ_enqReq_dummy2_0$EN;
// ports of submodule perfReqQ_enqReq_dummy2_1
wire perfReqQ_enqReq_dummy2_1$D_IN, perfReqQ_enqReq_dummy2_1$EN;
// ports of submodule perfReqQ_enqReq_dummy2_2
wire perfReqQ_enqReq_dummy2_2$D_IN,
perfReqQ_enqReq_dummy2_2$EN,
perfReqQ_enqReq_dummy2_2$Q_OUT;
// rule scheduling signals
wire CAN_FIRE_RL_cache_cRqRetryIndexQ_canonicalize,
CAN_FIRE_RL_cache_cRqRetryIndexQ_clearReq_canon,
CAN_FIRE_RL_cache_cRqRetryIndexQ_deqReq_canon,
CAN_FIRE_RL_cache_cRqRetryIndexQ_enqReq_canon,
CAN_FIRE_RL_cache_cRqTransfer_new_child,
CAN_FIRE_RL_cache_cRqTransfer_new_dma,
CAN_FIRE_RL_cache_cRqTransfer_retry,
CAN_FIRE_RL_cache_cRsTransfer,
CAN_FIRE_RL_cache_mRsDeq_nonRefill,
CAN_FIRE_RL_cache_mRsTransfer,
CAN_FIRE_RL_cache_mergeRsLdToDmaIndexQ_mRsDeq,
CAN_FIRE_RL_cache_mergeRsLdToDmaIndexQ_pipelineResp,
CAN_FIRE_RL_cache_mergeRsStToDmaIndexQ_pipelineResp,
CAN_FIRE_RL_cache_mergeRsStToDmaIndexQ_sendToM,
CAN_FIRE_RL_cache_pipelineResp_cRq,
CAN_FIRE_RL_cache_pipelineResp_cRs,
CAN_FIRE_RL_cache_pipelineResp_mRs,
CAN_FIRE_RL_cache_rqFromCQ_canonicalize,
CAN_FIRE_RL_cache_rqFromCQ_clearReq_canon,
CAN_FIRE_RL_cache_rqFromCQ_deqReq_canon,
CAN_FIRE_RL_cache_rqFromCQ_enqReq_canon,
CAN_FIRE_RL_cache_rqFromDmaQ_canonicalize,
CAN_FIRE_RL_cache_rqFromDmaQ_clearReq_canon,
CAN_FIRE_RL_cache_rqFromDmaQ_deqReq_canon,
CAN_FIRE_RL_cache_rqFromDmaQ_enqReq_canon,
CAN_FIRE_RL_cache_rsFromCQ_canonicalize,
CAN_FIRE_RL_cache_rsFromCQ_clearReq_canon,
CAN_FIRE_RL_cache_rsFromCQ_deqReq_canon,
CAN_FIRE_RL_cache_rsFromCQ_enqReq_canon,
CAN_FIRE_RL_cache_rsFromMQ_canonicalize,
CAN_FIRE_RL_cache_rsFromMQ_clearReq_canon,
CAN_FIRE_RL_cache_rsFromMQ_deqReq_canon,
CAN_FIRE_RL_cache_rsFromMQ_enqReq_canon,
CAN_FIRE_RL_cache_rsLdToDmaQ_canonicalize,
CAN_FIRE_RL_cache_rsLdToDmaQ_clearReq_canon,
CAN_FIRE_RL_cache_rsLdToDmaQ_deqReq_canon,
CAN_FIRE_RL_cache_rsLdToDmaQ_enqReq_canon,
CAN_FIRE_RL_cache_rsStToDmaQ_canonicalize,
CAN_FIRE_RL_cache_rsStToDmaQ_clearReq_canon,
CAN_FIRE_RL_cache_rsStToDmaQ_deqReq_canon,
CAN_FIRE_RL_cache_rsStToDmaQ_enqReq_canon,
CAN_FIRE_RL_cache_rsToCIndexQ_canonicalize,
CAN_FIRE_RL_cache_rsToCIndexQ_clearReq_canon,
CAN_FIRE_RL_cache_rsToCIndexQ_deqReq_canon,
CAN_FIRE_RL_cache_rsToCIndexQ_enqReq_canon,
CAN_FIRE_RL_cache_sendRqToC,
CAN_FIRE_RL_cache_sendRsLdToDma,
CAN_FIRE_RL_cache_sendRsStToDma,
CAN_FIRE_RL_cache_sendRsToC,
CAN_FIRE_RL_cache_sendToM,
CAN_FIRE_RL_cache_toCQ_canonicalize,
CAN_FIRE_RL_cache_toCQ_clearReq_canon,
CAN_FIRE_RL_cache_toCQ_deqReq_canon,
CAN_FIRE_RL_cache_toCQ_enqReq_canon,
CAN_FIRE_RL_cache_toMQ_canonicalize,
CAN_FIRE_RL_cache_toMQ_clearReq_canon,
CAN_FIRE_RL_cache_toMQ_deqReq_canon,
CAN_FIRE_RL_cache_toMQ_enqReq_canon,
CAN_FIRE_RL_perfReqQ_canonicalize,
CAN_FIRE_RL_perfReqQ_clearReq_canon,
CAN_FIRE_RL_perfReqQ_deqReq_canon,
CAN_FIRE_RL_perfReqQ_enqReq_canon,
CAN_FIRE_cRqStuck_get,
CAN_FIRE_dma_memReq_enq,
CAN_FIRE_dma_respLd_deq,
CAN_FIRE_dma_respSt_deq,
CAN_FIRE_perf_req,
CAN_FIRE_perf_resp,
CAN_FIRE_perf_setStatus,
CAN_FIRE_to_child_rqFromC_enq,
CAN_FIRE_to_child_rsFromC_enq,
CAN_FIRE_to_child_toC_deq,
CAN_FIRE_to_mem_rsFromM_enq,
CAN_FIRE_to_mem_toM_deq,
WILL_FIRE_RL_cache_cRqRetryIndexQ_canonicalize,
WILL_FIRE_RL_cache_cRqRetryIndexQ_clearReq_canon,
WILL_FIRE_RL_cache_cRqRetryIndexQ_deqReq_canon,
WILL_FIRE_RL_cache_cRqRetryIndexQ_enqReq_canon,
WILL_FIRE_RL_cache_cRqTransfer_new_child,
WILL_FIRE_RL_cache_cRqTransfer_new_dma,
WILL_FIRE_RL_cache_cRqTransfer_retry,
WILL_FIRE_RL_cache_cRsTransfer,
WILL_FIRE_RL_cache_mRsDeq_nonRefill,
WILL_FIRE_RL_cache_mRsTransfer,
WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_mRsDeq,
WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_pipelineResp,
WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_pipelineResp,
WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_sendToM,
WILL_FIRE_RL_cache_pipelineResp_cRq,
WILL_FIRE_RL_cache_pipelineResp_cRs,
WILL_FIRE_RL_cache_pipelineResp_mRs,
WILL_FIRE_RL_cache_rqFromCQ_canonicalize,
WILL_FIRE_RL_cache_rqFromCQ_clearReq_canon,
WILL_FIRE_RL_cache_rqFromCQ_deqReq_canon,
WILL_FIRE_RL_cache_rqFromCQ_enqReq_canon,
WILL_FIRE_RL_cache_rqFromDmaQ_canonicalize,
WILL_FIRE_RL_cache_rqFromDmaQ_clearReq_canon,
WILL_FIRE_RL_cache_rqFromDmaQ_deqReq_canon,
WILL_FIRE_RL_cache_rqFromDmaQ_enqReq_canon,
WILL_FIRE_RL_cache_rsFromCQ_canonicalize,
WILL_FIRE_RL_cache_rsFromCQ_clearReq_canon,
WILL_FIRE_RL_cache_rsFromCQ_deqReq_canon,
WILL_FIRE_RL_cache_rsFromCQ_enqReq_canon,
WILL_FIRE_RL_cache_rsFromMQ_canonicalize,
WILL_FIRE_RL_cache_rsFromMQ_clearReq_canon,
WILL_FIRE_RL_cache_rsFromMQ_deqReq_canon,
WILL_FIRE_RL_cache_rsFromMQ_enqReq_canon,
WILL_FIRE_RL_cache_rsLdToDmaQ_canonicalize,
WILL_FIRE_RL_cache_rsLdToDmaQ_clearReq_canon,
WILL_FIRE_RL_cache_rsLdToDmaQ_deqReq_canon,
WILL_FIRE_RL_cache_rsLdToDmaQ_enqReq_canon,
WILL_FIRE_RL_cache_rsStToDmaQ_canonicalize,
WILL_FIRE_RL_cache_rsStToDmaQ_clearReq_canon,
WILL_FIRE_RL_cache_rsStToDmaQ_deqReq_canon,
WILL_FIRE_RL_cache_rsStToDmaQ_enqReq_canon,
WILL_FIRE_RL_cache_rsToCIndexQ_canonicalize,
WILL_FIRE_RL_cache_rsToCIndexQ_clearReq_canon,
WILL_FIRE_RL_cache_rsToCIndexQ_deqReq_canon,
WILL_FIRE_RL_cache_rsToCIndexQ_enqReq_canon,
WILL_FIRE_RL_cache_sendRqToC,
WILL_FIRE_RL_cache_sendRsLdToDma,
WILL_FIRE_RL_cache_sendRsStToDma,
WILL_FIRE_RL_cache_sendRsToC,
WILL_FIRE_RL_cache_sendToM,
WILL_FIRE_RL_cache_toCQ_canonicalize,
WILL_FIRE_RL_cache_toCQ_clearReq_canon,
WILL_FIRE_RL_cache_toCQ_deqReq_canon,
WILL_FIRE_RL_cache_toCQ_enqReq_canon,
WILL_FIRE_RL_cache_toMQ_canonicalize,
WILL_FIRE_RL_cache_toMQ_clearReq_canon,
WILL_FIRE_RL_cache_toMQ_deqReq_canon,
WILL_FIRE_RL_cache_toMQ_enqReq_canon,
WILL_FIRE_RL_perfReqQ_canonicalize,
WILL_FIRE_RL_perfReqQ_clearReq_canon,
WILL_FIRE_RL_perfReqQ_deqReq_canon,
WILL_FIRE_RL_perfReqQ_enqReq_canon,
WILL_FIRE_cRqStuck_get,
WILL_FIRE_dma_memReq_enq,
WILL_FIRE_dma_respLd_deq,
WILL_FIRE_dma_respSt_deq,
WILL_FIRE_perf_req,
WILL_FIRE_perf_resp,
WILL_FIRE_perf_setStatus,
WILL_FIRE_to_child_rqFromC_enq,
WILL_FIRE_to_child_rsFromC_enq,
WILL_FIRE_to_child_toC_deq,
WILL_FIRE_to_mem_rsFromM_enq,
WILL_FIRE_to_mem_toM_deq;
// inputs to muxes for submodule ports
reg [3 : 0] MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2,
MUX_cache_cRqMshr$transfer_getRq_1__VAL_2;
wire [585 : 0] MUX_cache_toCQ_enqReq_lat_0$wset_1__VAL_1,
MUX_cache_toCQ_enqReq_lat_0$wset_1__VAL_2;
wire [583 : 0] MUX_cache_pipeline$send_1__VAL_1,
MUX_cache_pipeline$send_1__VAL_2,
MUX_cache_pipeline$send_1__VAL_3,
MUX_cache_pipeline$send_1__VAL_4,
MUX_cache_pipeline$send_1__VAL_5;
wire [573 : 0] MUX_cache_pipeline$deqWrite_2__VAL_1,
MUX_cache_pipeline$deqWrite_2__VAL_2,
MUX_cache_pipeline$deqWrite_2__VAL_3;
wire [512 : 0] MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_1,
MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_2,
MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_3,
MUX_cache_cRqMshr$transfer_getEmptyEntryInit_2__VAL_2;
wire [151 : 0] MUX_cache_cRqMshr$transfer_getEmptyEntryInit_1__VAL_1,
MUX_cache_cRqMshr$transfer_getEmptyEntryInit_1__VAL_2;
wire [64 : 0] MUX_cache_cRqMshr$pipelineResp_setStateSlot_3__VAL_1,
MUX_cache_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
wire [6 : 0] MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_1,
MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_2,
MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_3;
wire [5 : 0] MUX_cache_toMInfoQ$enq_1__VAL_1,
MUX_cache_toMInfoQ$enq_1__VAL_2;
wire [4 : 0] MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_1,
MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_2,
MUX_cache_pipeline$deqWrite_1__VAL_2,
MUX_cache_pipeline$deqWrite_1__VAL_3;
wire [2 : 0] MUX_cache_cRqMshr$pipelineResp_setStateSlot_2__VAL_1,
MUX_cache_cRqMshr$pipelineResp_setStateSlot_2__VAL_2;
wire MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_1,
MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_2,
MUX_cache_cRqMshr$pipelineResp_setStateSlot_1__SEL_1,
MUX_cache_cRqRetryIndexQ_enqReq_dummy2_0$write_1__SEL_1,
MUX_cache_cRqRetryIndexQ_enqReq_dummy2_0$write_1__SEL_2,
MUX_cache_pipeline$deqWrite_3__VAL_2,
MUX_cache_pipeline$deqWrite_3__VAL_3,
MUX_cache_rsLdToDmaIndexQ_pipelineResp$enq_1__SEL_1,
MUX_cache_rsStToDmaIndexQ_pipelineResp$enq_1__SEL_1,
MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_1,
MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_2,
MUX_cache_toMInfoQ$enq_1__SEL_1;
// remaining internal signals
reg [63 : 0] CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q232,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q233,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q267,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q91,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q92,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q93,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q98,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q99,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q236,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q237,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q243,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q69,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q75,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q76,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q1,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q2,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q226,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q227,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q3,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q4,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q73,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q74,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q257,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q258,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q259,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q85,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q86,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q87,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q96,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q97,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q234,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q235,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q239,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q247,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q249,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q88,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q89,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q90,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q94,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q95,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q220,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q221,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q222,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q223,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q224,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q225,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q245,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q246,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q251,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q252,
addr__h257616,
addr__h273361;
reg [15 : 0] CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q266,
x__h456399;
reg [3 : 0] x__h248737, x__h456804;
reg [2 : 0] x__h257564, x__h445950;
reg [1 : 0] CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79,
CASE_cache_pipelinefirst_BITS_580_TO_579_0_ca_ETC__q84,
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q230,
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q265,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q244,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q250,
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522,
SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403,
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445,
x__h249082,
x__h275130,
x__h444361,
x__h444405;
reg CASE_cache_pipelineunguard_first_BITS_584_TO__ETC__q77,
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q231,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q5,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8,
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q106,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q107,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q110,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q111,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q114,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q115,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q118,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q119,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q122,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q123,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q126,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q127,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q130,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q131,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q134,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q135,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q138,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q139,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q142,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q143,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q146,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q147,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q150,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q151,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q154,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q155,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q158,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q159,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q162,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q163,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q166,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q167,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q170,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q171,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q174,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q175,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q178,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q179,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q182,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q183,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q186,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q187,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q190,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q191,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q194,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q195,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q198,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q199,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q202,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q203,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q206,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q207,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q210,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q211,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q214,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q215,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q218,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q219,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q228,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q229,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q80,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q81,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q82,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q83,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q242,
CASE_cache_rsFromMQ_deqP_0_NOT_cache_rsFromMQ__ETC__q263,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q262,
CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q255,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BIT_5_ETC__q238,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BIT_5_ETC__q256,
CASE_cache_toMInfoQD_OUT_BITS_1_TO_0_0_NOT_ca_ETC__q264,
CASE_cache_toMQ_deqP_0_NOT_cache_toMQ_data_0_B_ETC__q260,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_4_ETC__q253,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q100,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q101,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q102,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q103,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q104,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q105,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q108,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q109,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q112,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q113,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q116,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q117,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q120,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q121,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q124,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q125,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q128,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q129,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q132,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q133,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q136,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q137,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q140,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q141,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q144,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q145,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q148,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q149,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q152,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q153,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q156,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q157,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q160,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q161,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q164,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q165,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q168,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q169,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q172,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q173,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q176,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q177,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q180,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q181,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q184,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q185,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q188,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q189,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q192,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q193,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q196,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q197,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q200,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q201,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q204,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q205,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q208,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q209,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q212,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q213,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q216,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q217,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q240,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q241,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_6_ETC__q261,
CASE_child13067_0_cache_cRqMshrsendRqToC_getS_ETC__q254,
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431,
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446;
wire [641 : 0] IF_cache_doLdAfterReplace_007_THEN_2_CONCAT_DO_ETC___d2016;
wire [639 : 0] DONTCARE_CONCAT_SEL_ARR_cache_toMQ_data_0_050__ETC___d4073,
IF_SEL_ARR_NOT_cache_toMQ_data_0_050_BIT_640_0_ETC___d4404,
IF_cache_toMQ_enqReq_dummy2_2_read__54_AND_IF__ETC___d703,
SEL_ARR_cache_toMQ_data_0_050_BITS_639_TO_576__ETC___d4402;
wire [583 : 0] DONTCARE_CONCAT_SEL_ARR_cache_toCQ_data_0_917__ETC___d3940,
IF_SEL_ARR_NOT_cache_toCQ_data_0_917_BIT_584_9_ETC___d4000,
IF_cache_toCQ_enqReq_dummy2_2_read__53_AND_IF__ETC___d302,
SEL_ARR_cache_toCQ_data_0_917_BITS_583_TO_520__ETC___d3998;
wire [580 : 0] SEL_ARR_cache_rsFromCQ_data_0_855_BITS_580_TO__ETC___d1910;
wire [573 : 0] IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2999,
IF_cache_cRqMshr_pipelineResp_searchEndOfChain_ETC___d3012,
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3010,
IF_cache_pipeline_first__581_BIT_512_308_THEN__ETC___d3660,
cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d2995,
cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3658;
wire [514 : 0] SEL_ARR_cache_rsFromCQ_data_0_855_BIT_514_865__ETC___d1909;
wire [512 : 0] SEL_ARR_cache_toCQ_data_0_917_BIT_515_953_cach_ETC___d3992;
wire [511 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2991,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3656,
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2993,
SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1904,
SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1966,
SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4401;
wire [447 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1845,
SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4036,
SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3987;
wire [383 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2916,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3613,
SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1895,
SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1957,
SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4392;
wire [319 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1836,
SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4027,
SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3978;
wire [255 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2844,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3573,
SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1886,
SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1948,
SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4383;
wire [191 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1827,
SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4018,
SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3969;
wire [127 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2772,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3533;
wire [85 : 0] SEL_ARR_cache_rqFromCQ_data_0_090_BITS_7_TO_6__ETC___d1118;
wire [64 : 0] IF_IF_SEL_ARR_cache_pipeline_first__581_BITS_5_ETC___d3709,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3078,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3096,
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3095,
cache_cRqMshr_pipelineResp_getSlot_IF_cache_pi_ETC___d3754;
wire [63 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2808,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2880,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2952,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3553,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3593,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3633,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1806,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4365,
addr__h288271,
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78,
rqAddr__h313360;
wire [61 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1801,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4356;
wire [59 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1796,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4347;
wire [57 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1791,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4338;
wire [55 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2732,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2767,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2839,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2911,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2986,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3511,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3530,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3570,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3610,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3653,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1786,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4329;
wire [53 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1781,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4320;
wire [51 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1776,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4311;
wire [49 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1771,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4302;
wire [47 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2799,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2871,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2943,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3548,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3588,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3628,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1766,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4293;
wire [45 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1761,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4284;
wire [43 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1756,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4275;
wire [41 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1751,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4266;
wire [39 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2723,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2758,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2830,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2902,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2977,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3506,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3525,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3565,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3605,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3648,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1746,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4257;
wire [37 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1741,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4248;
wire [35 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1736,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4239;
wire [33 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1731,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4230;
wire [31 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2790,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2862,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2934,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1726,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4221;
wire [29 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1721,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4212;
wire [27 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1716,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4203;
wire [25 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1711,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4194;
wire [23 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2714,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2749,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2821,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2893,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2968,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1706,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4185;
wire [21 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1701,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4176;
wire [19 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1696,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4167;
wire [17 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1691,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4158;
wire [15 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1686,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4149;
wire [13 : 0] IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d2699,
IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d3397,
IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d3000,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3493,
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2693,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1681,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4140;
wire [12 : 0] _0_CONCAT_IF_cache_pipeline_first__581_BITS_523_ETC___d3043;
wire [11 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1676,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4131;
wire [9 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1671,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4122;
wire [7 : 0] IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3694,
IF_cache_pipeline_first__581_BITS_523_TO_522_6_ETC___d3041,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1666,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4113;
wire [5 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2697,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3396,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1661,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4104;
wire [4 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2678,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2683,
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2676,
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d2682,
IF_cache_pipeline_first__581_BIT_512_308_THEN__ETC___d3486;
wire [3 : 0] SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1656,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4095,
_theResult_____2__h234513,
_theResult_____2__h245988,
next_deqP___1__h234850,
next_deqP___1__h246325,
pipeOutCRqIdx__h314276,
v__h232953,
v__h233236,
v__h242396,
v__h242679;
wire [2 : 0] IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3027,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3033,
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d3025,
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3032;
wire [1 : 0] IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3672,
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3684,
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3697,
IF_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_ETC___d1646,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3054,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3063,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3073,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3712,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3713,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3726,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3727,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3741,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3742,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2686,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3048,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3057,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3067,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3173,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3388,
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3171,
child__h313067;
wire IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d2635,
IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2654,
IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2657,
IF_SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSl_ETC___d3481,
IF_SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSl_ETC___d3482,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3454,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3455,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3458,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3459,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3462,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3463,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3804,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3814,
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3830,
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3417,
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3418,
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2626,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3014,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3022,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3155,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3156,
IF_cache_cRqRetryIndexQ_deqReq_dummy2_2_read___ETC___d854,
IF_cache_cRqRetryIndexQ_deqReq_lat_1_whas__11__ETC___d817,
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833,
IF_cache_pipeline_RDY_first__579_AND_cache_cRq_ETC___d2613,
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d2667,
IF_cache_pipeline_first__581_BIT_517_582_THEN__ETC___d3124,
IF_cache_rqFromCQ_deqReq_dummy2_2_read__7_AND__ETC___d55,
IF_cache_rqFromCQ_deqReq_lat_1_whas__3_THEN_ca_ETC___d19,
IF_cache_rqFromCQ_enqReq_lat_1_whas_THEN_cache_ETC___d39,
IF_cache_rqFromDmaQ_deqReq_dummy2_2_read__53_A_ETC___d361,
IF_cache_rqFromDmaQ_deqReq_lat_1_whas__19_THEN_ETC___d325,
IF_cache_rqFromDmaQ_enqReq_lat_1_whas__09_THEN_ETC___d345,
IF_cache_rsFromCQ_deqReq_dummy2_2_read__39_AND_ETC___d147,
IF_cache_rsFromCQ_deqReq_lat_1_whas__05_THEN_c_ETC___d111,
IF_cache_rsFromCQ_enqReq_lat_1_whas__5_THEN_ca_ETC___d131,
IF_cache_rsFromMQ_deqReq_dummy2_2_read__54_AND_ETC___d762,
IF_cache_rsFromMQ_deqReq_lat_1_whas__20_THEN_c_ETC___d726,
IF_cache_rsFromMQ_enqReq_lat_1_whas__10_THEN_c_ETC___d746,
IF_cache_rsLdToDmaQ_deqReq_dummy2_2_read__44_A_ETC___d452,
IF_cache_rsLdToDmaQ_deqReq_lat_1_whas__10_THEN_ETC___d416,
IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__00_THEN_ETC___d436,
IF_cache_rsStToDmaQ_deqReq_dummy2_2_read__35_A_ETC___d543,
IF_cache_rsStToDmaQ_deqReq_lat_1_whas__01_THEN_ETC___d507,
IF_cache_rsStToDmaQ_enqReq_lat_1_whas__91_THEN_ETC___d527,
IF_cache_rsToCIndexQ_deqReq_dummy2_2_read__64__ETC___d977,
IF_cache_rsToCIndexQ_deqReq_lat_1_whas__34_THE_ETC___d940,
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956,
IF_cache_toCQ_deqReq_dummy2_2_read__61_AND_IF__ETC___d269,
IF_cache_toCQ_deqReq_lat_1_whas__32_THEN_cache_ETC___d238,
IF_cache_toCQ_enqReq_lat_1_whas__87_THEN_cache_ETC___d196,
IF_cache_toMQ_deqReq_dummy2_2_read__62_AND_IF__ETC___d670,
IF_cache_toMQ_deqReq_lat_1_whas__33_THEN_cache_ETC___d639,
IF_cache_toMQ_enqReq_lat_1_whas__88_THEN_cache_ETC___d597,
IF_perfReqQ_enqReq_lat_1_whas__839_THEN_perfRe_ETC___d3875,
NOT_IF_cache_pipeline_first__581_BITS_584_TO_5_ETC___d3191,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1584,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1586,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1588,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1590,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1592,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1594,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1596,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1598,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1600,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1602,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1604,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1606,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1608,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1610,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1612,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1614,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1616,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1618,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1620,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1622,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1624,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1626,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1628,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1630,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1632,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1634,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1636,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1638,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1640,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1642,
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1644,
NOT_SEL_ARR_cache_cRqMshr_sendRqToC_getSlot_IF_ETC___d2508,
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3264,
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3290,
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3299,
NOT_cache_cRqMshr_pipelineResp_getSlot_IF_cach_ETC___d3369,
NOT_cache_cRqMshr_pipelineResp_searchEndOfChai_ETC___d3114,
NOT_cache_cRqMshr_pipelineResp_searchEndOfChai_ETC___d3353,
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853,
NOT_cache_cRqRetryIndexQ_enqReq_dummy2_2_read__ETC___d876,
NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d2637,
NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d3798,
NOT_cache_pipeline_first__581_BITS_519_TO_518__ETC___d3275,
NOT_cache_pipeline_first__581_BITS_519_TO_518__ETC___d3281,
NOT_cache_pipeline_first__581_BITS_525_TO_524__ETC___d3019,
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3801,
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3809,
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3827,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3133,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3143,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3149,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3316,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3320,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3324,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3328,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3332,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3340,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3345,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3351,
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3359,
NOT_cache_rqFromCQ_clearReq_dummy2_1_read__8_9_ETC___d33,
NOT_cache_rqFromCQ_enqReq_dummy2_2_read__4_9_O_ETC___d78,
NOT_cache_rqFromDmaQ_clearReq_dummy2_1_read__3_ETC___d339,
NOT_cache_rqFromDmaQ_enqReq_dummy2_2_read__40__ETC___d384,
NOT_cache_rsFromCQ_clearReq_dummy2_1_read__20__ETC___d125,
NOT_cache_rsFromCQ_enqReq_dummy2_2_read__26_61_ETC___d170,
NOT_cache_rsFromMQ_clearReq_dummy2_1_read__35__ETC___d740,
NOT_cache_rsFromMQ_enqReq_dummy2_2_read__41_76_ETC___d785,
NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__2_ETC___d430,
NOT_cache_rsLdToDmaQ_enqReq_dummy2_2_read__31__ETC___d475,
NOT_cache_rsStToDmaQ_clearReq_dummy2_1_read__1_ETC___d521,
NOT_cache_rsStToDmaQ_enqReq_dummy2_2_read__22__ETC___d566,
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976,
NOT_cache_rsToCIndexQ_enqReq_dummy2_2_read__51_ETC___d999,
NOT_cache_toCQ_clearReq_dummy2_1_read__47_48_O_ETC___d252,
NOT_cache_toCQ_enqReq_dummy2_2_read__53_83_OR__ETC___d292,
NOT_cache_toMQ_clearReq_dummy2_1_read__48_49_O_ETC___d653,
NOT_cache_toMQ_enqReq_dummy2_2_read__54_84_OR__ETC___d693,
NOT_perfReqQ_clearReq_dummy2_1_read__864_865_O_ETC___d3869,
NOT_perfReqQ_enqReq_dummy2_2_read__870_890_OR__ETC___d3900,
SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440,
_0_OR_IF_SEL_ARR_cache_pipeline_first__581_BITS_ETC___d3423,
_0_OR_NOT_CASE_IF_cache_pipeline_first__581_BIT_ETC___d3468,
_0_OR_NOT_cache_pipeline_first__581_BITS_519_TO_ETC___d2614,
_theResult_____2__h119142,
_theResult_____2__h135235,
_theResult_____2__h142737,
_theResult_____2__h208521,
_theResult_____2__h22297,
_theResult_____2__h225016,
_theResult_____2__h37990,
_theResult_____2__h7215,
cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3123,
cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3166,
cache_cRqMshr_pipelineResp_searchEndOfChain_ca_ETC___d2669,
cache_cRqMshr_sendRqToC_searchNeedRqChild_1_CO_ETC___d2482,
cache_cRqRetryIndexQ_enqReq_dummy2_2_read__28__ETC___d864,
cache_pipeline_RDY_deqWrite__580_AND_IF_cache__ETC___d2671,
cache_pipeline_RDY_deqWrite__580_AND_NOT_cache_ETC___d3471,
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588,
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3103,
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3287,
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3295,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2618,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3126,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3136,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3192,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3196,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3265,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3271,
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601,
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2621,
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604,
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2624,
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646,
cache_pipeline_first__581_BIT_517_582_AND_NOT__ETC___d3820,
cache_pipeline_first__581_BIT_517_582_AND_NOT__ETC___d3824,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3129,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3139,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3146,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3195,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3199,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3268,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3274,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3278,
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3284,
cache_rqFromCQ_enqReq_dummy2_2_read__4_AND_IF__ETC___d65,
cache_rqFromDmaQ_enqReq_dummy2_2_read__40_AND__ETC___d371,
cache_rsFromCQ_enqReq_dummy2_2_read__26_AND_IF_ETC___d157,
cache_rsFromMQ_enqReq_dummy2_2_read__41_AND_IF_ETC___d772,
cache_rsLdToDmaQ_enqReq_dummy2_2_read__31_AND__ETC___d462,
cache_rsStToDmaQ_enqReq_dummy2_2_read__22_AND__ETC___d553,
cache_rsToCIndexQ_enqReq_dummy2_2_read__51_AND_ETC___d987,
cache_toCQ_enqReq_dummy2_2_read__53_AND_IF_cac_ETC___d279,
cache_toMQ_enqReq_dummy2_2_read__54_AND_IF_cac_ETC___d680,
next_deqP___1__h119479,
next_deqP___1__h135572,
next_deqP___1__h143074,
next_deqP___1__h208858,
next_deqP___1__h225353,
next_deqP___1__h22634,
next_deqP___1__h38327,
next_deqP___1__h7552,
perfReqQ_enqReq_dummy2_2_read__870_AND_IF_perf_ETC___d3887,
v__h129259,
v__h129542,
v__h142239,
v__h142522,
v__h16641,
v__h168573,
v__h168856,
v__h16924,
v__h218716,
v__h218999,
v__h31944,
v__h32227,
v__h6037,
v__h6320,
v__h72082,
v__h72365;
// value method to_child_rsFromC_notFull
assign to_child_rsFromC_notFull = !cache_rsFromCQ_full ;
assign RDY_to_child_rsFromC_notFull = 1'd1 ;
// action method to_child_rsFromC_enq
assign RDY_to_child_rsFromC_enq = !cache_rsFromCQ_full ;
assign CAN_FIRE_to_child_rsFromC_enq = !cache_rsFromCQ_full ;
assign WILL_FIRE_to_child_rsFromC_enq = EN_to_child_rsFromC_enq ;
// value method to_child_rqFromC_notFull
assign to_child_rqFromC_notFull = !cache_rqFromCQ_full ;
assign RDY_to_child_rqFromC_notFull = 1'd1 ;
// action method to_child_rqFromC_enq
assign RDY_to_child_rqFromC_enq = !cache_rqFromCQ_full ;
assign CAN_FIRE_to_child_rqFromC_enq = !cache_rqFromCQ_full ;
assign WILL_FIRE_to_child_rqFromC_enq = EN_to_child_rqFromC_enq ;
// value method to_child_toC_notEmpty
assign to_child_toC_notEmpty = !cache_toCQ_empty ;
assign RDY_to_child_toC_notEmpty = 1'd1 ;
// action method to_child_toC_deq
assign RDY_to_child_toC_deq = !cache_toCQ_empty ;
assign CAN_FIRE_to_child_toC_deq = !cache_toCQ_empty ;
assign WILL_FIRE_to_child_toC_deq = EN_to_child_toC_deq ;
// value method to_child_toC_first
assign to_child_toC_first =
{ CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BIT_5_ETC__q256,
IF_SEL_ARR_NOT_cache_toCQ_data_0_917_BIT_584_9_ETC___d4000 } ;
assign RDY_to_child_toC_first = !cache_toCQ_empty ;
// value method dma_memReq_notFull
assign dma_memReq_notFull = !cache_rqFromDmaQ_full ;
assign RDY_dma_memReq_notFull = 1'd1 ;
// action method dma_memReq_enq
assign RDY_dma_memReq_enq = !cache_rqFromDmaQ_full ;
assign CAN_FIRE_dma_memReq_enq = !cache_rqFromDmaQ_full ;
assign WILL_FIRE_dma_memReq_enq = EN_dma_memReq_enq ;
// value method dma_respLd_notEmpty
assign dma_respLd_notEmpty = !cache_rsLdToDmaQ_empty ;
assign RDY_dma_respLd_notEmpty = 1'd1 ;
// action method dma_respLd_deq
assign RDY_dma_respLd_deq = !cache_rsLdToDmaQ_empty ;
assign CAN_FIRE_dma_respLd_deq = !cache_rsLdToDmaQ_empty ;
assign WILL_FIRE_dma_respLd_deq = EN_dma_respLd_deq ;
// value method dma_respLd_first
assign dma_respLd_first =
{ SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4036,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q259,
x__h456399 } ;
assign RDY_dma_respLd_first = !cache_rsLdToDmaQ_empty ;
// value method dma_respSt_notEmpty
assign dma_respSt_notEmpty = !cache_rsStToDmaQ_empty ;
assign RDY_dma_respSt_notEmpty = 1'd1 ;
// action method dma_respSt_deq
assign RDY_dma_respSt_deq = !cache_rsStToDmaQ_empty ;
assign CAN_FIRE_dma_respSt_deq = !cache_rsStToDmaQ_empty ;
assign WILL_FIRE_dma_respSt_deq = EN_dma_respSt_deq ;
// value method dma_respSt_first
always@(cache_rsStToDmaQ_deqP or
cache_rsStToDmaQ_data_0 or cache_rsStToDmaQ_data_1)
begin
case (cache_rsStToDmaQ_deqP)
1'd0: dma_respSt_first = cache_rsStToDmaQ_data_0;
1'd1: dma_respSt_first = cache_rsStToDmaQ_data_1;
endcase
end
assign RDY_dma_respSt_first = !cache_rsStToDmaQ_empty ;
// value method to_mem_toM_notEmpty
assign to_mem_toM_notEmpty = !cache_toMQ_empty ;
assign RDY_to_mem_toM_notEmpty = 1'd1 ;
// action method to_mem_toM_deq
assign RDY_to_mem_toM_deq = !cache_toMQ_empty ;
assign CAN_FIRE_to_mem_toM_deq = !cache_toMQ_empty ;
assign WILL_FIRE_to_mem_toM_deq = EN_to_mem_toM_deq ;
// value method to_mem_toM_first
assign to_mem_toM_first =
{ CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_6_ETC__q261,
IF_SEL_ARR_NOT_cache_toMQ_data_0_050_BIT_640_0_ETC___d4404 } ;
assign RDY_to_mem_toM_first = !cache_toMQ_empty ;
// value method to_mem_rsFromM_notFull
assign to_mem_rsFromM_notFull = !cache_rsFromMQ_full ;
assign RDY_to_mem_rsFromM_notFull = 1'd1 ;
// action method to_mem_rsFromM_enq
assign RDY_to_mem_rsFromM_enq = !cache_rsFromMQ_full ;
assign CAN_FIRE_to_mem_rsFromM_enq = !cache_rsFromMQ_full ;
assign WILL_FIRE_to_mem_rsFromM_enq = EN_to_mem_rsFromM_enq ;
// actionvalue method cRqStuck_get
assign cRqStuck_get =
{ cache_cRqMshr$stuck_get[32:16],
cache_cRqMshr$stuck_get[167:100],
cache_cRqMshr$stuck_get[98:97],
cache_cRqMshr$stuck_get[15:0] } ;
assign RDY_cRqStuck_get = cache_cRqMshr$RDY_stuck_get ;
assign CAN_FIRE_cRqStuck_get = cache_cRqMshr$RDY_stuck_get ;
assign WILL_FIRE_cRqStuck_get = EN_cRqStuck_get ;
// action method perf_setStatus
assign RDY_perf_setStatus = 1'd1 ;
assign CAN_FIRE_perf_setStatus = 1'd1 ;
assign WILL_FIRE_perf_setStatus = EN_perf_setStatus ;
// action method perf_req
assign RDY_perf_req = !perfReqQ_full ;
assign CAN_FIRE_perf_req = !perfReqQ_full ;
assign WILL_FIRE_perf_req = EN_perf_req ;
// actionvalue method perf_resp
assign perf_resp = { perfReqQ_data_0, 64'd0 } ;
assign RDY_perf_resp = !perfReqQ_empty ;
assign CAN_FIRE_perf_resp = !perfReqQ_empty ;
assign WILL_FIRE_perf_resp = EN_perf_resp ;
// value method perf_respValid
assign perf_respValid = !perfReqQ_empty ;
assign RDY_perf_respValid = 1'd1 ;
// submodule cache_cRqMshr
mkLastLvCRqMshr cache_cRqMshr(.CLK(CLK),
.RST_N(RST_N),
.mRsDeq_setData_d(cache_cRqMshr$mRsDeq_setData_d),
.mRsDeq_setData_n(cache_cRqMshr$mRsDeq_setData_n),
.pipelineResp_getAddrSucc_n(cache_cRqMshr$pipelineResp_getAddrSucc_n),
.pipelineResp_getData_n(cache_cRqMshr$pipelineResp_getData_n),
.pipelineResp_getRepSucc_n(cache_cRqMshr$pipelineResp_getRepSucc_n),
.pipelineResp_getRq_n(cache_cRqMshr$pipelineResp_getRq_n),
.pipelineResp_getSlot_n(cache_cRqMshr$pipelineResp_getSlot_n),
.pipelineResp_getState_n(cache_cRqMshr$pipelineResp_getState_n),
.pipelineResp_searchEndOfChain_addr(cache_cRqMshr$pipelineResp_searchEndOfChain_addr),
.pipelineResp_setAddrSucc_n(cache_cRqMshr$pipelineResp_setAddrSucc_n),
.pipelineResp_setAddrSucc_succ(cache_cRqMshr$pipelineResp_setAddrSucc_succ),
.pipelineResp_setData_d(cache_cRqMshr$pipelineResp_setData_d),
.pipelineResp_setData_n(cache_cRqMshr$pipelineResp_setData_n),
.pipelineResp_setRepSucc_n(cache_cRqMshr$pipelineResp_setRepSucc_n),
.pipelineResp_setRepSucc_succ(cache_cRqMshr$pipelineResp_setRepSucc_succ),
.pipelineResp_setStateSlot_n(cache_cRqMshr$pipelineResp_setStateSlot_n),
.pipelineResp_setStateSlot_slot(cache_cRqMshr$pipelineResp_setStateSlot_slot),
.pipelineResp_setStateSlot_state(cache_cRqMshr$pipelineResp_setStateSlot_state),
.sendRqToC_getRq_n(cache_cRqMshr$sendRqToC_getRq_n),
.sendRqToC_getSlot_n(cache_cRqMshr$sendRqToC_getSlot_n),
.sendRqToC_getState_n(cache_cRqMshr$sendRqToC_getState_n),
.sendRqToC_searchNeedRqChild_suggestIdx(cache_cRqMshr$sendRqToC_searchNeedRqChild_suggestIdx),
.sendRqToC_setSlot_n(cache_cRqMshr$sendRqToC_setSlot_n),
.sendRqToC_setSlot_s(cache_cRqMshr$sendRqToC_setSlot_s),
.sendRsToDmaC_getData_n(cache_cRqMshr$sendRsToDmaC_getData_n),
.sendRsToDmaC_getRq_n(cache_cRqMshr$sendRsToDmaC_getRq_n),
.sendRsToDmaC_releaseEntry_n(cache_cRqMshr$sendRsToDmaC_releaseEntry_n),
.sendToM_getData_n(cache_cRqMshr$sendToM_getData_n),
.sendToM_getRq_n(cache_cRqMshr$sendToM_getRq_n),
.sendToM_getSlot_n(cache_cRqMshr$sendToM_getSlot_n),
.transfer_getEmptyEntryInit_d(cache_cRqMshr$transfer_getEmptyEntryInit_d),
.transfer_getEmptyEntryInit_r(cache_cRqMshr$transfer_getEmptyEntryInit_r),
.transfer_getRq_n(cache_cRqMshr$transfer_getRq_n),
.transfer_getSlot_n(cache_cRqMshr$transfer_getSlot_n),
.transfer_hasEmptyEntry_r(cache_cRqMshr$transfer_hasEmptyEntry_r),
.EN_transfer_getEmptyEntryInit(cache_cRqMshr$EN_transfer_getEmptyEntryInit),
.EN_mRsDeq_setData(cache_cRqMshr$EN_mRsDeq_setData),
.EN_sendRsToDmaC_releaseEntry(cache_cRqMshr$EN_sendRsToDmaC_releaseEntry),
.EN_sendRqToC_setSlot(cache_cRqMshr$EN_sendRqToC_setSlot),
.EN_pipelineResp_setData(cache_cRqMshr$EN_pipelineResp_setData),
.EN_pipelineResp_setStateSlot(cache_cRqMshr$EN_pipelineResp_setStateSlot),
.EN_pipelineResp_setAddrSucc(cache_cRqMshr$EN_pipelineResp_setAddrSucc),
.EN_pipelineResp_setRepSucc(cache_cRqMshr$EN_pipelineResp_setRepSucc),
.EN_stuck_get(cache_cRqMshr$EN_stuck_get),
.transfer_getRq(cache_cRqMshr$transfer_getRq),
.RDY_transfer_getRq(),
.transfer_getSlot(cache_cRqMshr$transfer_getSlot),
.RDY_transfer_getSlot(),
.transfer_getEmptyEntryInit(cache_cRqMshr$transfer_getEmptyEntryInit),
.RDY_transfer_getEmptyEntryInit(cache_cRqMshr$RDY_transfer_getEmptyEntryInit),
.transfer_hasEmptyEntry(),
.RDY_transfer_hasEmptyEntry(),
.RDY_mRsDeq_setData(),
.sendToM_getRq(cache_cRqMshr$sendToM_getRq),
.RDY_sendToM_getRq(),
.sendToM_getSlot(cache_cRqMshr$sendToM_getSlot),
.RDY_sendToM_getSlot(),
.sendToM_getData(cache_cRqMshr$sendToM_getData),
.RDY_sendToM_getData(),
.sendRsToDmaC_getRq(cache_cRqMshr$sendRsToDmaC_getRq),
.RDY_sendRsToDmaC_getRq(),
.sendRsToDmaC_getData(cache_cRqMshr$sendRsToDmaC_getData),
.RDY_sendRsToDmaC_getData(),
.RDY_sendRsToDmaC_releaseEntry(cache_cRqMshr$RDY_sendRsToDmaC_releaseEntry),
.sendRqToC_getRq(cache_cRqMshr$sendRqToC_getRq),
.RDY_sendRqToC_getRq(),
.sendRqToC_getState(cache_cRqMshr$sendRqToC_getState),
.RDY_sendRqToC_getState(),
.sendRqToC_getSlot(cache_cRqMshr$sendRqToC_getSlot),
.RDY_sendRqToC_getSlot(),
.RDY_sendRqToC_setSlot(),
.sendRqToC_searchNeedRqChild(cache_cRqMshr$sendRqToC_searchNeedRqChild),
.RDY_sendRqToC_searchNeedRqChild(),
.pipelineResp_getRq(cache_cRqMshr$pipelineResp_getRq),
.RDY_pipelineResp_getRq(),
.pipelineResp_getState(cache_cRqMshr$pipelineResp_getState),
.RDY_pipelineResp_getState(),
.pipelineResp_getSlot(cache_cRqMshr$pipelineResp_getSlot),
.RDY_pipelineResp_getSlot(),
.pipelineResp_getData(cache_cRqMshr$pipelineResp_getData),
.RDY_pipelineResp_getData(),
.pipelineResp_getAddrSucc(cache_cRqMshr$pipelineResp_getAddrSucc),
.RDY_pipelineResp_getAddrSucc(),
.pipelineResp_getRepSucc(cache_cRqMshr$pipelineResp_getRepSucc),
.RDY_pipelineResp_getRepSucc(),
.RDY_pipelineResp_setData(),
.RDY_pipelineResp_setStateSlot(),
.RDY_pipelineResp_setAddrSucc(),
.RDY_pipelineResp_setRepSucc(),
.pipelineResp_searchEndOfChain(cache_cRqMshr$pipelineResp_searchEndOfChain),
.RDY_pipelineResp_searchEndOfChain(),
.stuck_get(cache_cRqMshr$stuck_get),
.RDY_stuck_get(cache_cRqMshr$RDY_stuck_get));
// submodule cache_cRqRetryIndexQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_cRqRetryIndexQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_cRqRetryIndexQ_clearReq_dummy2_0$D_IN),
.EN(cache_cRqRetryIndexQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_cRqRetryIndexQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_cRqRetryIndexQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_cRqRetryIndexQ_clearReq_dummy2_1$D_IN),
.EN(cache_cRqRetryIndexQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_cRqRetryIndexQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_cRqRetryIndexQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_cRqRetryIndexQ_deqReq_dummy2_0$D_IN),
.EN(cache_cRqRetryIndexQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_cRqRetryIndexQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_cRqRetryIndexQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_cRqRetryIndexQ_deqReq_dummy2_1$D_IN),
.EN(cache_cRqRetryIndexQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_cRqRetryIndexQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_cRqRetryIndexQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_cRqRetryIndexQ_deqReq_dummy2_2$D_IN),
.EN(cache_cRqRetryIndexQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_cRqRetryIndexQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_cRqRetryIndexQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_cRqRetryIndexQ_enqReq_dummy2_0$D_IN),
.EN(cache_cRqRetryIndexQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_cRqRetryIndexQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_cRqRetryIndexQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_cRqRetryIndexQ_enqReq_dummy2_1$D_IN),
.EN(cache_cRqRetryIndexQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_cRqRetryIndexQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_cRqRetryIndexQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_cRqRetryIndexQ_enqReq_dummy2_2$D_IN),
.EN(cache_cRqRetryIndexQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_pipeline
mkLLPipeline cache_pipeline(.CLK(CLK),
.RST_N(RST_N),
.deqWrite_swapRq(cache_pipeline$deqWrite_swapRq),
.deqWrite_updateRep(cache_pipeline$deqWrite_updateRep),
.deqWrite_wrRam(cache_pipeline$deqWrite_wrRam),
.send_r(cache_pipeline$send_r),
.EN_send(cache_pipeline$EN_send),
.EN_deqWrite(cache_pipeline$EN_deqWrite),
.RDY_send(cache_pipeline$RDY_send),
.notEmpty(cache_pipeline$notEmpty),
.RDY_notEmpty(),
.first(cache_pipeline$first),
.RDY_first(cache_pipeline$RDY_first),
.unguard_first(cache_pipeline$unguard_first),
.RDY_unguard_first(cache_pipeline$RDY_unguard_first),
.RDY_deqWrite(cache_pipeline$RDY_deqWrite));
// submodule cache_rqFromCQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromCQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rqFromCQ_clearReq_dummy2_0$D_IN),
.EN(cache_rqFromCQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rqFromCQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromCQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rqFromCQ_clearReq_dummy2_1$D_IN),
.EN(cache_rqFromCQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_rqFromCQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_rqFromCQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromCQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rqFromCQ_deqReq_dummy2_0$D_IN),
.EN(cache_rqFromCQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rqFromCQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromCQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rqFromCQ_deqReq_dummy2_1$D_IN),
.EN(cache_rqFromCQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rqFromCQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromCQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rqFromCQ_deqReq_dummy2_2$D_IN),
.EN(cache_rqFromCQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_rqFromCQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_rqFromCQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromCQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rqFromCQ_enqReq_dummy2_0$D_IN),
.EN(cache_rqFromCQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rqFromCQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromCQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rqFromCQ_enqReq_dummy2_1$D_IN),
.EN(cache_rqFromCQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rqFromCQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromCQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rqFromCQ_enqReq_dummy2_2$D_IN),
.EN(cache_rqFromCQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_rqFromCQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_rqFromDmaQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromDmaQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rqFromDmaQ_clearReq_dummy2_0$D_IN),
.EN(cache_rqFromDmaQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rqFromDmaQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromDmaQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rqFromDmaQ_clearReq_dummy2_1$D_IN),
.EN(cache_rqFromDmaQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_rqFromDmaQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_rqFromDmaQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromDmaQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rqFromDmaQ_deqReq_dummy2_0$D_IN),
.EN(cache_rqFromDmaQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rqFromDmaQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromDmaQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rqFromDmaQ_deqReq_dummy2_1$D_IN),
.EN(cache_rqFromDmaQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rqFromDmaQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromDmaQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rqFromDmaQ_deqReq_dummy2_2$D_IN),
.EN(cache_rqFromDmaQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_rqFromDmaQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_rqFromDmaQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromDmaQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rqFromDmaQ_enqReq_dummy2_0$D_IN),
.EN(cache_rqFromDmaQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rqFromDmaQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromDmaQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rqFromDmaQ_enqReq_dummy2_1$D_IN),
.EN(cache_rqFromDmaQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rqFromDmaQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rqFromDmaQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rqFromDmaQ_enqReq_dummy2_2$D_IN),
.EN(cache_rqFromDmaQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_rqFromDmaQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_rsFromCQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromCQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsFromCQ_clearReq_dummy2_0$D_IN),
.EN(cache_rsFromCQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsFromCQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromCQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsFromCQ_clearReq_dummy2_1$D_IN),
.EN(cache_rsFromCQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_rsFromCQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_rsFromCQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromCQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsFromCQ_deqReq_dummy2_0$D_IN),
.EN(cache_rsFromCQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsFromCQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromCQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsFromCQ_deqReq_dummy2_1$D_IN),
.EN(cache_rsFromCQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsFromCQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromCQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsFromCQ_deqReq_dummy2_2$D_IN),
.EN(cache_rsFromCQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_rsFromCQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_rsFromCQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromCQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsFromCQ_enqReq_dummy2_0$D_IN),
.EN(cache_rsFromCQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsFromCQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromCQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsFromCQ_enqReq_dummy2_1$D_IN),
.EN(cache_rsFromCQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsFromCQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromCQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsFromCQ_enqReq_dummy2_2$D_IN),
.EN(cache_rsFromCQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_rsFromCQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_rsFromMQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromMQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsFromMQ_clearReq_dummy2_0$D_IN),
.EN(cache_rsFromMQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsFromMQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromMQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsFromMQ_clearReq_dummy2_1$D_IN),
.EN(cache_rsFromMQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_rsFromMQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_rsFromMQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromMQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsFromMQ_deqReq_dummy2_0$D_IN),
.EN(cache_rsFromMQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsFromMQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromMQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsFromMQ_deqReq_dummy2_1$D_IN),
.EN(cache_rsFromMQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsFromMQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromMQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsFromMQ_deqReq_dummy2_2$D_IN),
.EN(cache_rsFromMQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_rsFromMQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_rsFromMQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromMQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsFromMQ_enqReq_dummy2_0$D_IN),
.EN(cache_rsFromMQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsFromMQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromMQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsFromMQ_enqReq_dummy2_1$D_IN),
.EN(cache_rsFromMQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsFromMQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsFromMQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsFromMQ_enqReq_dummy2_2$D_IN),
.EN(cache_rsFromMQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_rsFromMQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_rsLdToDmaIndexQ
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd16),
.p3cntr_width(32'd4),
.guarded(1'd1)) cache_rsLdToDmaIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(cache_rsLdToDmaIndexQ$D_IN),
.ENQ(cache_rsLdToDmaIndexQ$ENQ),
.DEQ(cache_rsLdToDmaIndexQ$DEQ),
.CLR(cache_rsLdToDmaIndexQ$CLR),
.D_OUT(cache_rsLdToDmaIndexQ$D_OUT),
.FULL_N(cache_rsLdToDmaIndexQ$FULL_N),
.EMPTY_N(cache_rsLdToDmaIndexQ$EMPTY_N));
// submodule cache_rsLdToDmaIndexQ_mRsDeq
FIFO2 #(.width(32'd4),
.guarded(1'd1)) cache_rsLdToDmaIndexQ_mRsDeq(.RST(RST_N),
.CLK(CLK),
.D_IN(cache_rsLdToDmaIndexQ_mRsDeq$D_IN),
.ENQ(cache_rsLdToDmaIndexQ_mRsDeq$ENQ),
.DEQ(cache_rsLdToDmaIndexQ_mRsDeq$DEQ),
.CLR(cache_rsLdToDmaIndexQ_mRsDeq$CLR),
.D_OUT(cache_rsLdToDmaIndexQ_mRsDeq$D_OUT),
.FULL_N(cache_rsLdToDmaIndexQ_mRsDeq$FULL_N),
.EMPTY_N(cache_rsLdToDmaIndexQ_mRsDeq$EMPTY_N));
// submodule cache_rsLdToDmaIndexQ_pipelineResp
FIFO2 #(.width(32'd4),
.guarded(1'd1)) cache_rsLdToDmaIndexQ_pipelineResp(.RST(RST_N),
.CLK(CLK),
.D_IN(cache_rsLdToDmaIndexQ_pipelineResp$D_IN),
.ENQ(cache_rsLdToDmaIndexQ_pipelineResp$ENQ),
.DEQ(cache_rsLdToDmaIndexQ_pipelineResp$DEQ),
.CLR(cache_rsLdToDmaIndexQ_pipelineResp$CLR),
.D_OUT(cache_rsLdToDmaIndexQ_pipelineResp$D_OUT),
.FULL_N(cache_rsLdToDmaIndexQ_pipelineResp$FULL_N),
.EMPTY_N(cache_rsLdToDmaIndexQ_pipelineResp$EMPTY_N));
// submodule cache_rsLdToDmaQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsLdToDmaQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsLdToDmaQ_clearReq_dummy2_0$D_IN),
.EN(cache_rsLdToDmaQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsLdToDmaQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsLdToDmaQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsLdToDmaQ_clearReq_dummy2_1$D_IN),
.EN(cache_rsLdToDmaQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_rsLdToDmaQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_rsLdToDmaQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsLdToDmaQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsLdToDmaQ_deqReq_dummy2_0$D_IN),
.EN(cache_rsLdToDmaQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsLdToDmaQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsLdToDmaQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsLdToDmaQ_deqReq_dummy2_1$D_IN),
.EN(cache_rsLdToDmaQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsLdToDmaQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsLdToDmaQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsLdToDmaQ_deqReq_dummy2_2$D_IN),
.EN(cache_rsLdToDmaQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_rsLdToDmaQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_rsLdToDmaQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsLdToDmaQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsLdToDmaQ_enqReq_dummy2_0$D_IN),
.EN(cache_rsLdToDmaQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsLdToDmaQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsLdToDmaQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsLdToDmaQ_enqReq_dummy2_1$D_IN),
.EN(cache_rsLdToDmaQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsLdToDmaQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsLdToDmaQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsLdToDmaQ_enqReq_dummy2_2$D_IN),
.EN(cache_rsLdToDmaQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_rsStToDmaIndexQ
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd16),
.p3cntr_width(32'd4),
.guarded(1'd1)) cache_rsStToDmaIndexQ(.RST(RST_N),
.CLK(CLK),
.D_IN(cache_rsStToDmaIndexQ$D_IN),
.ENQ(cache_rsStToDmaIndexQ$ENQ),
.DEQ(cache_rsStToDmaIndexQ$DEQ),
.CLR(cache_rsStToDmaIndexQ$CLR),
.D_OUT(cache_rsStToDmaIndexQ$D_OUT),
.FULL_N(cache_rsStToDmaIndexQ$FULL_N),
.EMPTY_N(cache_rsStToDmaIndexQ$EMPTY_N));
// submodule cache_rsStToDmaIndexQ_pipelineResp
FIFO2 #(.width(32'd4),
.guarded(1'd1)) cache_rsStToDmaIndexQ_pipelineResp(.RST(RST_N),
.CLK(CLK),
.D_IN(cache_rsStToDmaIndexQ_pipelineResp$D_IN),
.ENQ(cache_rsStToDmaIndexQ_pipelineResp$ENQ),
.DEQ(cache_rsStToDmaIndexQ_pipelineResp$DEQ),
.CLR(cache_rsStToDmaIndexQ_pipelineResp$CLR),
.D_OUT(cache_rsStToDmaIndexQ_pipelineResp$D_OUT),
.FULL_N(cache_rsStToDmaIndexQ_pipelineResp$FULL_N),
.EMPTY_N(cache_rsStToDmaIndexQ_pipelineResp$EMPTY_N));
// submodule cache_rsStToDmaIndexQ_sendToM
FIFO2 #(.width(32'd4),
.guarded(1'd1)) cache_rsStToDmaIndexQ_sendToM(.RST(RST_N),
.CLK(CLK),
.D_IN(cache_rsStToDmaIndexQ_sendToM$D_IN),
.ENQ(cache_rsStToDmaIndexQ_sendToM$ENQ),
.DEQ(cache_rsStToDmaIndexQ_sendToM$DEQ),
.CLR(cache_rsStToDmaIndexQ_sendToM$CLR),
.D_OUT(cache_rsStToDmaIndexQ_sendToM$D_OUT),
.FULL_N(cache_rsStToDmaIndexQ_sendToM$FULL_N),
.EMPTY_N(cache_rsStToDmaIndexQ_sendToM$EMPTY_N));
// submodule cache_rsStToDmaQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsStToDmaQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsStToDmaQ_clearReq_dummy2_0$D_IN),
.EN(cache_rsStToDmaQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsStToDmaQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsStToDmaQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsStToDmaQ_clearReq_dummy2_1$D_IN),
.EN(cache_rsStToDmaQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_rsStToDmaQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_rsStToDmaQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsStToDmaQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsStToDmaQ_deqReq_dummy2_0$D_IN),
.EN(cache_rsStToDmaQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsStToDmaQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsStToDmaQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsStToDmaQ_deqReq_dummy2_1$D_IN),
.EN(cache_rsStToDmaQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsStToDmaQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsStToDmaQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsStToDmaQ_deqReq_dummy2_2$D_IN),
.EN(cache_rsStToDmaQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_rsStToDmaQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_rsStToDmaQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsStToDmaQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsStToDmaQ_enqReq_dummy2_0$D_IN),
.EN(cache_rsStToDmaQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsStToDmaQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsStToDmaQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsStToDmaQ_enqReq_dummy2_1$D_IN),
.EN(cache_rsStToDmaQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsStToDmaQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsStToDmaQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsStToDmaQ_enqReq_dummy2_2$D_IN),
.EN(cache_rsStToDmaQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_rsStToDmaQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_rsToCIndexQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsToCIndexQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsToCIndexQ_clearReq_dummy2_0$D_IN),
.EN(cache_rsToCIndexQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsToCIndexQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsToCIndexQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsToCIndexQ_clearReq_dummy2_1$D_IN),
.EN(cache_rsToCIndexQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_rsToCIndexQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_rsToCIndexQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsToCIndexQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsToCIndexQ_deqReq_dummy2_0$D_IN),
.EN(cache_rsToCIndexQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsToCIndexQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsToCIndexQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsToCIndexQ_deqReq_dummy2_1$D_IN),
.EN(cache_rsToCIndexQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsToCIndexQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsToCIndexQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsToCIndexQ_deqReq_dummy2_2$D_IN),
.EN(cache_rsToCIndexQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_rsToCIndexQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_rsToCIndexQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsToCIndexQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_rsToCIndexQ_enqReq_dummy2_0$D_IN),
.EN(cache_rsToCIndexQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_rsToCIndexQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsToCIndexQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_rsToCIndexQ_enqReq_dummy2_1$D_IN),
.EN(cache_rsToCIndexQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_rsToCIndexQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_rsToCIndexQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_rsToCIndexQ_enqReq_dummy2_2$D_IN),
.EN(cache_rsToCIndexQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_toCQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toCQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_toCQ_clearReq_dummy2_0$D_IN),
.EN(cache_toCQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_toCQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toCQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_toCQ_clearReq_dummy2_1$D_IN),
.EN(cache_toCQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_toCQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_toCQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toCQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_toCQ_deqReq_dummy2_0$D_IN),
.EN(cache_toCQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_toCQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toCQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_toCQ_deqReq_dummy2_1$D_IN),
.EN(cache_toCQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_toCQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toCQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_toCQ_deqReq_dummy2_2$D_IN),
.EN(cache_toCQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_toCQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_toCQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toCQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_toCQ_enqReq_dummy2_0$D_IN),
.EN(cache_toCQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_toCQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toCQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_toCQ_enqReq_dummy2_1$D_IN),
.EN(cache_toCQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_toCQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toCQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_toCQ_enqReq_dummy2_2$D_IN),
.EN(cache_toCQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_toCQ_enqReq_dummy2_2$Q_OUT));
// submodule cache_toMInfoQ
SizedFIFO #(.p1width(32'd6),
.p2depth(32'd16),
.p3cntr_width(32'd4),
.guarded(1'd1)) cache_toMInfoQ(.RST(RST_N),
.CLK(CLK),
.D_IN(cache_toMInfoQ$D_IN),
.ENQ(cache_toMInfoQ$ENQ),
.DEQ(cache_toMInfoQ$DEQ),
.CLR(cache_toMInfoQ$CLR),
.D_OUT(cache_toMInfoQ$D_OUT),
.FULL_N(cache_toMInfoQ$FULL_N),
.EMPTY_N(cache_toMInfoQ$EMPTY_N));
// submodule cache_toMQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toMQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(cache_toMQ_clearReq_dummy2_0$D_IN),
.EN(cache_toMQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_toMQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toMQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(cache_toMQ_clearReq_dummy2_1$D_IN),
.EN(cache_toMQ_clearReq_dummy2_1$EN),
.Q_OUT(cache_toMQ_clearReq_dummy2_1$Q_OUT));
// submodule cache_toMQ_deqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toMQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_toMQ_deqReq_dummy2_0$D_IN),
.EN(cache_toMQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_toMQ_deqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toMQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_toMQ_deqReq_dummy2_1$D_IN),
.EN(cache_toMQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_toMQ_deqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toMQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_toMQ_deqReq_dummy2_2$D_IN),
.EN(cache_toMQ_deqReq_dummy2_2$EN),
.Q_OUT(cache_toMQ_deqReq_dummy2_2$Q_OUT));
// submodule cache_toMQ_enqReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toMQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(cache_toMQ_enqReq_dummy2_0$D_IN),
.EN(cache_toMQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule cache_toMQ_enqReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toMQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(cache_toMQ_enqReq_dummy2_1$D_IN),
.EN(cache_toMQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule cache_toMQ_enqReq_dummy2_2
RevertReg #(.width(32'd1),
.init(1'd1)) cache_toMQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(cache_toMQ_enqReq_dummy2_2$D_IN),
.EN(cache_toMQ_enqReq_dummy2_2$EN),
.Q_OUT(cache_toMQ_enqReq_dummy2_2$Q_OUT));
// submodule perfReqQ_clearReq_dummy2_0
RevertReg #(.width(32'd1),
.init(1'd1)) perfReqQ_clearReq_dummy2_0(.CLK(CLK),
.D_IN(perfReqQ_clearReq_dummy2_0$D_IN),
.EN(perfReqQ_clearReq_dummy2_0$EN),
.Q_OUT());
// submodule perfReqQ_clearReq_dummy2_1
RevertReg #(.width(32'd1),
.init(1'd1)) perfReqQ_clearReq_dummy2_1(.CLK(CLK),
.D_IN(perfReqQ_clearReq_dummy2_1$D_IN),
.EN(perfReqQ_clearReq_dummy2_1$EN),
.Q_OUT(perfReqQ_clearReq_dummy2_1$Q_OUT));
// submodule perfReqQ_deqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_0(.CLK(CLK),
.D_IN(perfReqQ_deqReq_dummy2_0$D_IN),
.EN(perfReqQ_deqReq_dummy2_0$EN),
.Q_OUT());
// submodule perfReqQ_deqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_1(.CLK(CLK),
.D_IN(perfReqQ_deqReq_dummy2_1$D_IN),
.EN(perfReqQ_deqReq_dummy2_1$EN),
.Q_OUT());
// submodule perfReqQ_deqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_deqReq_dummy2_2(.CLK(CLK),
.D_IN(perfReqQ_deqReq_dummy2_2$D_IN),
.EN(perfReqQ_deqReq_dummy2_2$EN),
.Q_OUT(perfReqQ_deqReq_dummy2_2$Q_OUT));
// submodule perfReqQ_enqReq_dummy2_0
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_0(.CLK(CLK),
.D_IN(perfReqQ_enqReq_dummy2_0$D_IN),
.EN(perfReqQ_enqReq_dummy2_0$EN),
.Q_OUT());
// submodule perfReqQ_enqReq_dummy2_1
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_1(.CLK(CLK),
.D_IN(perfReqQ_enqReq_dummy2_1$D_IN),
.EN(perfReqQ_enqReq_dummy2_1$EN),
.Q_OUT());
// submodule perfReqQ_enqReq_dummy2_2
RevertReg #(.width(32'd1), .init(1'd1)) perfReqQ_enqReq_dummy2_2(.CLK(CLK),
.D_IN(perfReqQ_enqReq_dummy2_2$D_IN),
.EN(perfReqQ_enqReq_dummy2_2$EN),
.Q_OUT(perfReqQ_enqReq_dummy2_2$Q_OUT));
// rule RL_cache_mergeRsLdToDmaIndexQ_mRsDeq
assign CAN_FIRE_RL_cache_mergeRsLdToDmaIndexQ_mRsDeq =
cache_rsLdToDmaIndexQ_mRsDeq$EMPTY_N &&
cache_rsLdToDmaIndexQ$FULL_N ;
assign WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_mRsDeq =
CAN_FIRE_RL_cache_mergeRsLdToDmaIndexQ_mRsDeq &&
!WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_pipelineResp ;
// rule RL_cache_mergeRsLdToDmaIndexQ_pipelineResp
assign CAN_FIRE_RL_cache_mergeRsLdToDmaIndexQ_pipelineResp =
cache_rsLdToDmaIndexQ$FULL_N &&
cache_rsLdToDmaIndexQ_pipelineResp$EMPTY_N ;
assign WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_pipelineResp =
CAN_FIRE_RL_cache_mergeRsLdToDmaIndexQ_pipelineResp ;
// rule RL_cache_mergeRsStToDmaIndexQ_sendToM
assign CAN_FIRE_RL_cache_mergeRsStToDmaIndexQ_sendToM =
cache_rsStToDmaIndexQ_sendToM$EMPTY_N &&
cache_rsStToDmaIndexQ$FULL_N ;
assign WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_sendToM =
CAN_FIRE_RL_cache_mergeRsStToDmaIndexQ_sendToM &&
!WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_pipelineResp ;
// rule RL_cache_mergeRsStToDmaIndexQ_pipelineResp
assign CAN_FIRE_RL_cache_mergeRsStToDmaIndexQ_pipelineResp =
cache_rsStToDmaIndexQ$FULL_N &&
cache_rsStToDmaIndexQ_pipelineResp$EMPTY_N ;
assign WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_pipelineResp =
CAN_FIRE_RL_cache_mergeRsStToDmaIndexQ_pipelineResp ;
// rule RL_cache_sendToM
assign CAN_FIRE_RL_cache_sendToM =
cache_toMInfoQ$EMPTY_N &&
CASE_cache_toMInfoQD_OUT_BITS_1_TO_0_0_NOT_ca_ETC__q264 ;
assign WILL_FIRE_RL_cache_sendToM = CAN_FIRE_RL_cache_sendToM ;
// rule RL_cache_sendRsToC
assign CAN_FIRE_RL_cache_sendRsToC =
!cache_toCQ_full && !cache_rsToCIndexQ_empty &&
cache_cRqMshr$RDY_sendRsToDmaC_releaseEntry ;
assign WILL_FIRE_RL_cache_sendRsToC =
CAN_FIRE_RL_cache_sendRsToC &&
!WILL_FIRE_RL_cache_sendRsStToDma &&
!WILL_FIRE_RL_cache_sendRsLdToDma ;
// rule RL_cache_sendRqToC
assign CAN_FIRE_RL_cache_sendRqToC =
!cache_toCQ_full &&
cache_cRqMshr_sendRqToC_searchNeedRqChild_1_CO_ETC___d2482 &&
cache_rsToCIndexQ_empty ;
assign WILL_FIRE_RL_cache_sendRqToC = CAN_FIRE_RL_cache_sendRqToC ;
// rule RL_cache_sendRsLdToDma
assign CAN_FIRE_RL_cache_sendRsLdToDma =
!cache_rsLdToDmaQ_full &&
cache_cRqMshr$RDY_sendRsToDmaC_releaseEntry &&
cache_rsLdToDmaIndexQ$EMPTY_N ;
assign WILL_FIRE_RL_cache_sendRsLdToDma = CAN_FIRE_RL_cache_sendRsLdToDma ;
// rule RL_cache_mRsDeq_nonRefill
assign CAN_FIRE_RL_cache_mRsDeq_nonRefill =
!cache_rsFromMQ_empty && cache_rsLdToDmaIndexQ_mRsDeq$FULL_N &&
CASE_cache_rsFromMQ_deqP_0_NOT_cache_rsFromMQ__ETC__q263 ;
assign WILL_FIRE_RL_cache_mRsDeq_nonRefill =
CAN_FIRE_RL_cache_mRsDeq_nonRefill ;
// rule RL_cache_sendRsStToDma
assign CAN_FIRE_RL_cache_sendRsStToDma =
!cache_rsStToDmaQ_full &&
cache_cRqMshr$RDY_sendRsToDmaC_releaseEntry &&
cache_rsStToDmaIndexQ$EMPTY_N ;
assign WILL_FIRE_RL_cache_sendRsStToDma =
CAN_FIRE_RL_cache_sendRsStToDma &&
!WILL_FIRE_RL_cache_sendRsLdToDma ;
// rule RL_cache_pipelineResp_cRq
assign CAN_FIRE_RL_cache_pipelineResp_cRq =
cache_pipeline$RDY_first &&
cache_pipeline_RDY_deqWrite__580_AND_IF_cache__ETC___d2671 &&
cache_pipeline$first[584:583] == 2'd0 ;
assign WILL_FIRE_RL_cache_pipelineResp_cRq =
CAN_FIRE_RL_cache_pipelineResp_cRq ;
// rule RL_cache_pipelineResp_mRs
assign CAN_FIRE_RL_cache_pipelineResp_mRs =
!cache_rsToCIndexQ_full && cache_pipeline$RDY_first &&
cache_pipeline$RDY_deqWrite &&
cache_pipeline$first[584:583] == 2'd2 ;
assign WILL_FIRE_RL_cache_pipelineResp_mRs =
CAN_FIRE_RL_cache_pipelineResp_mRs ;
// rule RL_cache_pipelineResp_cRs
assign CAN_FIRE_RL_cache_pipelineResp_cRs =
cache_pipeline$RDY_first &&
cache_pipeline_RDY_deqWrite__580_AND_NOT_cache_ETC___d3471 &&
cache_pipeline$first[584:583] == 2'd1 ;
assign WILL_FIRE_RL_cache_pipelineResp_cRs =
CAN_FIRE_RL_cache_pipelineResp_cRs ;
// rule RL_cache_cRqTransfer_retry
assign CAN_FIRE_RL_cache_cRqTransfer_retry =
!cache_cRqRetryIndexQ_empty && cache_pipeline$RDY_send ;
assign WILL_FIRE_RL_cache_cRqTransfer_retry =
CAN_FIRE_RL_cache_cRqTransfer_retry &&
!WILL_FIRE_RL_cache_cRsTransfer &&
!WILL_FIRE_RL_cache_mRsTransfer ;
// rule RL_cache_cRqTransfer_new_child
assign CAN_FIRE_RL_cache_cRqTransfer_new_child =
!cache_rqFromCQ_empty && cache_pipeline$RDY_send &&
cache_cRqMshr$RDY_transfer_getEmptyEntryInit &&
cache_cRqRetryIndexQ_empty &&
(!cache_priorNewCRqSrc || cache_rqFromDmaQ_empty) ;
assign WILL_FIRE_RL_cache_cRqTransfer_new_child =
CAN_FIRE_RL_cache_cRqTransfer_new_child &&
!WILL_FIRE_RL_cache_cRsTransfer &&
!WILL_FIRE_RL_cache_mRsTransfer ;
// rule RL_cache_cRqTransfer_new_dma
assign CAN_FIRE_RL_cache_cRqTransfer_new_dma =
!cache_rqFromDmaQ_empty && cache_pipeline$RDY_send &&
cache_cRqMshr$RDY_transfer_getEmptyEntryInit &&
cache_cRqRetryIndexQ_empty &&
(cache_priorNewCRqSrc || cache_rqFromCQ_empty) ;
assign WILL_FIRE_RL_cache_cRqTransfer_new_dma =
CAN_FIRE_RL_cache_cRqTransfer_new_dma &&
!WILL_FIRE_RL_cache_cRsTransfer &&
!WILL_FIRE_RL_cache_mRsTransfer ;
// rule RL_cache_cRsTransfer
assign CAN_FIRE_RL_cache_cRsTransfer =
!cache_rsFromCQ_empty && cache_pipeline$RDY_send ;
assign WILL_FIRE_RL_cache_cRsTransfer =
CAN_FIRE_RL_cache_cRsTransfer &&
!WILL_FIRE_RL_cache_mRsTransfer ;
// rule RL_cache_mRsTransfer
assign CAN_FIRE_RL_cache_mRsTransfer =
!cache_rsFromMQ_empty && cache_pipeline$RDY_send &&
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q262 ;
assign WILL_FIRE_RL_cache_mRsTransfer = CAN_FIRE_RL_cache_mRsTransfer ;
// rule RL_cache_rqFromCQ_canonicalize
assign CAN_FIRE_RL_cache_rqFromCQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_rqFromCQ_canonicalize = 1'd1 ;
// rule RL_cache_rqFromCQ_enqReq_canon
assign CAN_FIRE_RL_cache_rqFromCQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rqFromCQ_enqReq_canon = 1'd1 ;
// rule RL_cache_rqFromCQ_deqReq_canon
assign CAN_FIRE_RL_cache_rqFromCQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rqFromCQ_deqReq_canon = 1'd1 ;
// rule RL_cache_rqFromCQ_clearReq_canon
assign CAN_FIRE_RL_cache_rqFromCQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rqFromCQ_clearReq_canon = 1'd1 ;
// rule RL_cache_rsFromCQ_canonicalize
assign CAN_FIRE_RL_cache_rsFromCQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_rsFromCQ_canonicalize = 1'd1 ;
// rule RL_cache_rsFromCQ_enqReq_canon
assign CAN_FIRE_RL_cache_rsFromCQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsFromCQ_enqReq_canon = 1'd1 ;
// rule RL_cache_rsFromCQ_deqReq_canon
assign CAN_FIRE_RL_cache_rsFromCQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsFromCQ_deqReq_canon = 1'd1 ;
// rule RL_cache_rsFromCQ_clearReq_canon
assign CAN_FIRE_RL_cache_rsFromCQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsFromCQ_clearReq_canon = 1'd1 ;
// rule RL_cache_toCQ_canonicalize
assign CAN_FIRE_RL_cache_toCQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_toCQ_canonicalize = 1'd1 ;
// rule RL_cache_toCQ_enqReq_canon
assign CAN_FIRE_RL_cache_toCQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_toCQ_enqReq_canon = 1'd1 ;
// rule RL_cache_toCQ_deqReq_canon
assign CAN_FIRE_RL_cache_toCQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_toCQ_deqReq_canon = 1'd1 ;
// rule RL_cache_toCQ_clearReq_canon
assign CAN_FIRE_RL_cache_toCQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_toCQ_clearReq_canon = 1'd1 ;
// rule RL_cache_rqFromDmaQ_canonicalize
assign CAN_FIRE_RL_cache_rqFromDmaQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_rqFromDmaQ_canonicalize = 1'd1 ;
// rule RL_cache_rqFromDmaQ_enqReq_canon
assign CAN_FIRE_RL_cache_rqFromDmaQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rqFromDmaQ_enqReq_canon = 1'd1 ;
// rule RL_cache_rqFromDmaQ_deqReq_canon
assign CAN_FIRE_RL_cache_rqFromDmaQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rqFromDmaQ_deqReq_canon = 1'd1 ;
// rule RL_cache_rqFromDmaQ_clearReq_canon
assign CAN_FIRE_RL_cache_rqFromDmaQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rqFromDmaQ_clearReq_canon = 1'd1 ;
// rule RL_cache_rsLdToDmaQ_canonicalize
assign CAN_FIRE_RL_cache_rsLdToDmaQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_rsLdToDmaQ_canonicalize = 1'd1 ;
// rule RL_cache_rsLdToDmaQ_enqReq_canon
assign CAN_FIRE_RL_cache_rsLdToDmaQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsLdToDmaQ_enqReq_canon = 1'd1 ;
// rule RL_cache_rsLdToDmaQ_deqReq_canon
assign CAN_FIRE_RL_cache_rsLdToDmaQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsLdToDmaQ_deqReq_canon = 1'd1 ;
// rule RL_cache_rsLdToDmaQ_clearReq_canon
assign CAN_FIRE_RL_cache_rsLdToDmaQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsLdToDmaQ_clearReq_canon = 1'd1 ;
// rule RL_cache_rsStToDmaQ_canonicalize
assign CAN_FIRE_RL_cache_rsStToDmaQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_rsStToDmaQ_canonicalize = 1'd1 ;
// rule RL_cache_rsStToDmaQ_enqReq_canon
assign CAN_FIRE_RL_cache_rsStToDmaQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsStToDmaQ_enqReq_canon = 1'd1 ;
// rule RL_cache_rsStToDmaQ_deqReq_canon
assign CAN_FIRE_RL_cache_rsStToDmaQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsStToDmaQ_deqReq_canon = 1'd1 ;
// rule RL_cache_rsStToDmaQ_clearReq_canon
assign CAN_FIRE_RL_cache_rsStToDmaQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsStToDmaQ_clearReq_canon = 1'd1 ;
// rule RL_cache_toMQ_canonicalize
assign CAN_FIRE_RL_cache_toMQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_toMQ_canonicalize = 1'd1 ;
// rule RL_cache_toMQ_enqReq_canon
assign CAN_FIRE_RL_cache_toMQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_toMQ_enqReq_canon = 1'd1 ;
// rule RL_cache_toMQ_deqReq_canon
assign CAN_FIRE_RL_cache_toMQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_toMQ_deqReq_canon = 1'd1 ;
// rule RL_cache_toMQ_clearReq_canon
assign CAN_FIRE_RL_cache_toMQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_toMQ_clearReq_canon = 1'd1 ;
// rule RL_cache_rsFromMQ_canonicalize
assign CAN_FIRE_RL_cache_rsFromMQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_rsFromMQ_canonicalize = 1'd1 ;
// rule RL_cache_rsFromMQ_enqReq_canon
assign CAN_FIRE_RL_cache_rsFromMQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsFromMQ_enqReq_canon = 1'd1 ;
// rule RL_cache_rsFromMQ_deqReq_canon
assign CAN_FIRE_RL_cache_rsFromMQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsFromMQ_deqReq_canon = 1'd1 ;
// rule RL_cache_rsFromMQ_clearReq_canon
assign CAN_FIRE_RL_cache_rsFromMQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsFromMQ_clearReq_canon = 1'd1 ;
// rule RL_cache_cRqRetryIndexQ_canonicalize
assign CAN_FIRE_RL_cache_cRqRetryIndexQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_cRqRetryIndexQ_canonicalize = 1'd1 ;
// rule RL_cache_cRqRetryIndexQ_enqReq_canon
assign CAN_FIRE_RL_cache_cRqRetryIndexQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_cRqRetryIndexQ_enqReq_canon = 1'd1 ;
// rule RL_cache_cRqRetryIndexQ_deqReq_canon
assign CAN_FIRE_RL_cache_cRqRetryIndexQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_cRqRetryIndexQ_deqReq_canon = 1'd1 ;
// rule RL_cache_cRqRetryIndexQ_clearReq_canon
assign CAN_FIRE_RL_cache_cRqRetryIndexQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_cRqRetryIndexQ_clearReq_canon = 1'd1 ;
// rule RL_cache_rsToCIndexQ_canonicalize
assign CAN_FIRE_RL_cache_rsToCIndexQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_cache_rsToCIndexQ_canonicalize = 1'd1 ;
// rule RL_cache_rsToCIndexQ_enqReq_canon
assign CAN_FIRE_RL_cache_rsToCIndexQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsToCIndexQ_enqReq_canon = 1'd1 ;
// rule RL_cache_rsToCIndexQ_deqReq_canon
assign CAN_FIRE_RL_cache_rsToCIndexQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsToCIndexQ_deqReq_canon = 1'd1 ;
// rule RL_cache_rsToCIndexQ_clearReq_canon
assign CAN_FIRE_RL_cache_rsToCIndexQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_cache_rsToCIndexQ_clearReq_canon = 1'd1 ;
// rule RL_perfReqQ_canonicalize
assign CAN_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
assign WILL_FIRE_RL_perfReqQ_canonicalize = 1'd1 ;
// rule RL_perfReqQ_enqReq_canon
assign CAN_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_perfReqQ_enqReq_canon = 1'd1 ;
// rule RL_perfReqQ_deqReq_canon
assign CAN_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
assign WILL_FIRE_RL_perfReqQ_deqReq_canon = 1'd1 ;
// rule RL_perfReqQ_clearReq_canon
assign CAN_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
assign WILL_FIRE_RL_perfReqQ_clearReq_canon = 1'd1 ;
// inputs to muxes for submodule ports
assign MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_1 =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3103 ||
!cache_pipeline$first[517] &&
NOT_cache_cRqMshr_pipelineResp_searchEndOfChai_ETC___d3114) ;
assign MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_2 =
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[517] &&
(cache_pipeline$first[512] &&
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 ||
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484) ;
assign MUX_cache_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 =
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[517] ;
assign MUX_cache_cRqRetryIndexQ_enqReq_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3332 ;
assign MUX_cache_cRqRetryIndexQ_enqReq_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 &&
cache_cRqMshr$pipelineResp_getRepSucc[4] ;
assign MUX_cache_rsLdToDmaIndexQ_pipelineResp$enq_1__SEL_1 =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3139 ||
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3143) ;
assign MUX_cache_rsStToDmaIndexQ_pipelineResp$enq_1__SEL_1 =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3129 ||
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3133) ;
assign MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_1 =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3146 ||
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3149) ;
assign MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_2 =
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
!cache_cRqMshr$pipelineResp_getRq[16] ;
assign MUX_cache_toMInfoQ$enq_1__SEL_1 =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3156 &&
cache_pipeline$first[525:524] == 2'd0 ||
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3166) ;
always@(cache_rsToCIndexQ_deqP or
cache_rsToCIndexQ_data_0 or
cache_rsToCIndexQ_data_1 or
cache_rsToCIndexQ_data_2 or
cache_rsToCIndexQ_data_3 or
cache_rsToCIndexQ_data_4 or
cache_rsToCIndexQ_data_5 or
cache_rsToCIndexQ_data_6 or
cache_rsToCIndexQ_data_7 or
cache_rsToCIndexQ_data_8 or
cache_rsToCIndexQ_data_9 or
cache_rsToCIndexQ_data_10 or
cache_rsToCIndexQ_data_11 or
cache_rsToCIndexQ_data_12 or
cache_rsToCIndexQ_data_13 or
cache_rsToCIndexQ_data_14 or cache_rsToCIndexQ_data_15)
begin
case (cache_rsToCIndexQ_deqP)
4'd0:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_0[5:2];
4'd1:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_1[5:2];
4'd2:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_2[5:2];
4'd3:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_3[5:2];
4'd4:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_4[5:2];
4'd5:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_5[5:2];
4'd6:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_6[5:2];
4'd7:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_7[5:2];
4'd8:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_8[5:2];
4'd9:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_9[5:2];
4'd10:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_10[5:2];
4'd11:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_11[5:2];
4'd12:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_12[5:2];
4'd13:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_13[5:2];
4'd14:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_14[5:2];
4'd15:
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 =
cache_rsToCIndexQ_data_15[5:2];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
MUX_cache_cRqMshr$transfer_getRq_1__VAL_2 =
cache_rsFromMQ_data_0[3:0];
1'd1:
MUX_cache_cRqMshr$transfer_getRq_1__VAL_2 =
cache_rsFromMQ_data_1[3:0];
endcase
end
assign MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_1 =
{ IF_cache_pipeline_first__581_BIT_517_582_THEN__ETC___d3124,
cache_pipeline$first[511:0] } ;
assign MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_2 =
{ cache_pipeline$first[512] ?
cache_pipeline$first[525:524] == 2'd3 :
cache_cRqMshr$pipelineResp_getRq[16] ||
CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79 ==
2'd0,
cache_pipeline$first[511:0] } ;
assign MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_3 =
{ CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79 == 2'd0,
cache_pipeline$first[511:0] } ;
assign MUX_cache_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 =
cache_pipeline$first[512] ?
(IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 ?
3'd3 :
3'd2) :
(IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 ?
3'd4 :
3'd3) ;
assign MUX_cache_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 =
cache_pipeline$first[517] ?
(cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3027 :
3'd5) :
((cache_cRqMshr$pipelineResp_searchEndOfChain[4] &&
cache_cRqMshr$pipelineResp_getState == 3'd1) ?
3'd5 :
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3033) ;
assign MUX_cache_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 =
cache_pipeline$first[512] ?
IF_IF_SEL_ARR_cache_pipeline_first__581_BITS_5_ETC___d3709 :
cache_cRqMshr_pipelineResp_getSlot_IF_cache_pi_ETC___d3754 ;
assign MUX_cache_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 =
cache_pipeline$first[517] ?
(cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3078 :
65'h15555555555554222) :
((cache_cRqMshr$pipelineResp_searchEndOfChain[4] &&
cache_cRqMshr$pipelineResp_getState == 3'd1) ?
65'h15555555555554222 :
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3096) ;
assign MUX_cache_cRqMshr$transfer_getEmptyEntryInit_1__VAL_1 =
{ addr__h257616,
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q265,
SEL_ARR_cache_rqFromCQ_data_0_090_BITS_7_TO_6__ETC___d1118 } ;
assign MUX_cache_cRqMshr$transfer_getEmptyEntryInit_1__VAL_2 =
{ addr__h273361,
2'd0,
IF_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_ETC___d1646,
3'd2,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1806,
1'd1,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q266 } ;
assign MUX_cache_cRqMshr$transfer_getEmptyEntryInit_2__VAL_2 =
{ !CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1644,
SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1845,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q267 } ;
assign MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1, cache_cRqMshr$pipelineResp_getAddrSucc[3:0] } ;
assign MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1, cache_cRqMshr$pipelineResp_getRepSucc[3:0] } ;
assign MUX_cache_pipeline$deqWrite_1__VAL_2 =
cache_pipeline$first[517] ?
(cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2678 :
5'd10) :
((cache_cRqMshr$pipelineResp_searchEndOfChain[4] &&
cache_cRqMshr$pipelineResp_getState == 3'd1) ?
5'd10 :
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2683) ;
assign MUX_cache_pipeline$deqWrite_1__VAL_3 =
cache_pipeline$first[517] ?
IF_cache_pipeline_first__581_BIT_512_308_THEN__ETC___d3486 :
5'd10 ;
assign MUX_cache_pipeline$deqWrite_2__VAL_1 =
{ cache_cRqMshr$pipelineResp_getRq[151:104],
IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d3397,
cache_pipeline$first[511:0] } ;
assign MUX_cache_pipeline$deqWrite_2__VAL_2 =
cache_pipeline$first[517] ?
(cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 ?
cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d2995 :
cache_pipeline$first[573:0]) :
IF_cache_cRqMshr_pipelineResp_searchEndOfChain_ETC___d3012 ;
assign MUX_cache_pipeline$deqWrite_2__VAL_3 =
cache_pipeline$first[517] ?
IF_cache_pipeline_first__581_BIT_512_308_THEN__ETC___d3660 :
cache_pipeline$first[573:0] ;
assign MUX_cache_pipeline$deqWrite_3__VAL_2 =
cache_pipeline$first[517] ?
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3014 :
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3022 ;
assign MUX_cache_pipeline$deqWrite_3__VAL_3 =
cache_pipeline$first[517] && !cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 ;
assign MUX_cache_pipeline$send_1__VAL_1 =
{ 516'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
cache_cRqMshr$transfer_getRq[151:88],
x__h248737 } ;
assign MUX_cache_pipeline$send_1__VAL_2 =
{ 516'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
addr__h257616,
cache_cRqMshr$transfer_getEmptyEntryInit } ;
assign MUX_cache_pipeline$send_1__VAL_3 =
{ 516'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
addr__h273361,
cache_cRqMshr$transfer_getEmptyEntryInit } ;
assign MUX_cache_pipeline$send_1__VAL_4 =
{ 3'd2,
SEL_ARR_cache_rsFromCQ_data_0_855_BITS_580_TO__ETC___d1910 } ;
assign MUX_cache_pipeline$send_1__VAL_5 =
{ 2'd2,
cache_cRqMshr$transfer_getRq[151:88],
(cache_cRqMshr$transfer_getRq[85:84] == 2'd3) ?
cache_cRqMshr$transfer_getRq[85:84] :
2'd2,
SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1966,
cache_cRqMshr$transfer_getSlot[64:61] } ;
assign MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_1 =
{ 1'd1,
cache_pipeline$first[582:579],
cache_cRqMshr$pipelineResp_getRq[85:84] } ;
assign MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_2 =
{ 1'd1,
cache_pipeline$first[516:513],
cache_cRqMshr$pipelineResp_getRq[85:84] } ;
assign MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_3 =
{ 1'd1,
cache_pipeline$first[516:513],
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3388 } ;
assign MUX_cache_toCQ_enqReq_lat_0$wset_1__VAL_1 =
{ 2'd3,
cache_cRqMshr$sendRsToDmaC_getRq[151:88],
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445,
cache_cRqMshr$sendRsToDmaC_getRq[82:81],
cache_cRqMshr$sendRsToDmaC_getData,
cache_cRqMshr$sendRsToDmaC_getRq[2:0] } ;
assign MUX_cache_toCQ_enqReq_lat_0$wset_1__VAL_2 =
{ 518'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
rqAddr__h313360,
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522,
(cache_cRqMshr$sendRqToC_getSlot[3:2] != 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[7:6] != 2'd1) ?
2'd2 :
((cache_cRqMshr$sendRqToC_getSlot[3:2] == 2'd1) ?
2'd0 :
2'd1) } ;
assign MUX_cache_toMInfoQ$enq_1__VAL_1 =
{ cache_pipeline$first[582:579],
cache_pipeline$first[517] ?
2'd0 :
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3173 } ;
assign MUX_cache_toMInfoQ$enq_1__VAL_2 =
{ cache_pipeline$first[516:513],
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3171 } ;
// inlined wires
assign cache_rqFromCQ_enqReq_lat_0$wget = { 1'd1, to_child_rqFromC_enq_x } ;
assign cache_rsFromCQ_enqReq_lat_0$wget = { 1'd1, to_child_rsFromC_enq_x } ;
assign cache_toCQ_enqReq_lat_0$wget =
WILL_FIRE_RL_cache_sendRsToC ?
MUX_cache_toCQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_cache_toCQ_enqReq_lat_0$wset_1__VAL_2 ;
assign cache_toCQ_enqReq_lat_0$whas =
WILL_FIRE_RL_cache_sendRsToC || WILL_FIRE_RL_cache_sendRqToC ;
assign cache_rqFromDmaQ_enqReq_lat_0$wget = { 1'd1, dma_memReq_enq_x } ;
assign cache_rsLdToDmaQ_enqReq_lat_0$wget =
{ 1'd1,
cache_cRqMshr$sendRsToDmaC_getData[511:0],
cache_cRqMshr$sendRsToDmaC_getRq[15:0] } ;
assign cache_rsStToDmaQ_enqReq_lat_0$wget =
{ 1'd1, cache_cRqMshr$sendRsToDmaC_getRq[15:0] } ;
always@(cache_toMInfoQ$D_OUT or
IF_cache_doLdAfterReplace_007_THEN_2_CONCAT_DO_ETC___d2016 or
cache_cRqMshr$sendToM_getRq or cache_cRqMshr$sendToM_getData)
begin
case (cache_toMInfoQ$D_OUT[1:0])
2'd0:
cache_toMQ_enqReq_lat_0$wget =
{ 573'h12AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
cache_cRqMshr$sendToM_getRq[151:88],
!cache_cRqMshr$sendToM_getRq[16],
cache_toMInfoQ$D_OUT[5:2] };
2'd1:
cache_toMQ_enqReq_lat_0$wget =
{ 2'd3,
cache_cRqMshr$sendToM_getRq[151:88],
cache_cRqMshr$sendToM_getRq[80:17],
cache_cRqMshr$sendToM_getData[511:0] };
default: cache_toMQ_enqReq_lat_0$wget =
IF_cache_doLdAfterReplace_007_THEN_2_CONCAT_DO_ETC___d2016;
endcase
end
assign cache_toMQ_enqReq_lat_0$whas =
WILL_FIRE_RL_cache_sendToM &&
(cache_toMInfoQ$D_OUT[1:0] == 2'd0 ||
cache_toMInfoQ$D_OUT[1:0] == 2'd1 ||
cache_toMInfoQ$D_OUT[1:0] == 2'd2) ;
assign cache_rsFromMQ_enqReq_lat_0$wget = { 1'd1, to_mem_rsFromM_enq_x } ;
assign cache_rsFromMQ_deqReq_lat_0$whas =
WILL_FIRE_RL_cache_mRsDeq_nonRefill ||
WILL_FIRE_RL_cache_mRsTransfer ;
assign cache_cRqRetryIndexQ_enqReq_lat_0$wget =
MUX_cache_cRqRetryIndexQ_enqReq_dummy2_0$write_1__SEL_1 ?
MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_1 :
MUX_cache_cRqRetryIndexQ_enqReq_lat_0$wset_1__VAL_2 ;
assign cache_cRqRetryIndexQ_enqReq_lat_0$whas =
MUX_cache_cRqRetryIndexQ_enqReq_dummy2_0$write_1__SEL_1 ||
MUX_cache_cRqRetryIndexQ_enqReq_dummy2_0$write_1__SEL_2 ;
always@(MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_1 or
MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_1 or
MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_2 or
MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_2 or
WILL_FIRE_RL_cache_pipelineResp_mRs or
MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_1:
cache_rsToCIndexQ_enqReq_lat_0$wget =
MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_1;
MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_2:
cache_rsToCIndexQ_enqReq_lat_0$wget =
MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_2;
WILL_FIRE_RL_cache_pipelineResp_mRs:
cache_rsToCIndexQ_enqReq_lat_0$wget =
MUX_cache_rsToCIndexQ_enqReq_lat_0$wset_1__VAL_3;
default: cache_rsToCIndexQ_enqReq_lat_0$wget =
7'b0101010 /* unspecified value */ ;
endcase
end
assign cache_rsToCIndexQ_enqReq_lat_0$whas =
MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_1 ||
MUX_cache_rsToCIndexQ_enqReq_dummy2_0$write_1__SEL_2 ||
WILL_FIRE_RL_cache_pipelineResp_mRs ;
assign perfReqQ_enqReq_lat_0$wget = { 1'd1, perf_req_r } ;
// register cache_cRqRetryIndexQ_clearReq_rl
assign cache_cRqRetryIndexQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_cRqRetryIndexQ_clearReq_rl$EN = 1'd1 ;
// register cache_cRqRetryIndexQ_data_0
assign cache_cRqRetryIndexQ_data_0$D_IN =
cache_cRqRetryIndexQ_enqReq_lat_0$whas ?
cache_cRqRetryIndexQ_enqReq_lat_0$wget[3:0] :
cache_cRqRetryIndexQ_enqReq_rl[3:0] ;
assign cache_cRqRetryIndexQ_data_0$EN =
cache_cRqRetryIndexQ_enqP == 4'd0 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_1
assign cache_cRqRetryIndexQ_data_1$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_1$EN =
cache_cRqRetryIndexQ_enqP == 4'd1 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_10
assign cache_cRqRetryIndexQ_data_10$D_IN =
cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_10$EN =
cache_cRqRetryIndexQ_enqP == 4'd10 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_11
assign cache_cRqRetryIndexQ_data_11$D_IN =
cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_11$EN =
cache_cRqRetryIndexQ_enqP == 4'd11 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_12
assign cache_cRqRetryIndexQ_data_12$D_IN =
cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_12$EN =
cache_cRqRetryIndexQ_enqP == 4'd12 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_13
assign cache_cRqRetryIndexQ_data_13$D_IN =
cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_13$EN =
cache_cRqRetryIndexQ_enqP == 4'd13 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_14
assign cache_cRqRetryIndexQ_data_14$D_IN =
cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_14$EN =
cache_cRqRetryIndexQ_enqP == 4'd14 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_15
assign cache_cRqRetryIndexQ_data_15$D_IN =
cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_15$EN =
cache_cRqRetryIndexQ_enqP == 4'd15 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_2
assign cache_cRqRetryIndexQ_data_2$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_2$EN =
cache_cRqRetryIndexQ_enqP == 4'd2 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_3
assign cache_cRqRetryIndexQ_data_3$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_3$EN =
cache_cRqRetryIndexQ_enqP == 4'd3 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_4
assign cache_cRqRetryIndexQ_data_4$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_4$EN =
cache_cRqRetryIndexQ_enqP == 4'd4 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_5
assign cache_cRqRetryIndexQ_data_5$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_5$EN =
cache_cRqRetryIndexQ_enqP == 4'd5 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_6
assign cache_cRqRetryIndexQ_data_6$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_6$EN =
cache_cRqRetryIndexQ_enqP == 4'd6 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_7
assign cache_cRqRetryIndexQ_data_7$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_7$EN =
cache_cRqRetryIndexQ_enqP == 4'd7 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_8
assign cache_cRqRetryIndexQ_data_8$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_8$EN =
cache_cRqRetryIndexQ_enqP == 4'd8 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_data_9
assign cache_cRqRetryIndexQ_data_9$D_IN = cache_cRqRetryIndexQ_data_0$D_IN ;
assign cache_cRqRetryIndexQ_data_9$EN =
cache_cRqRetryIndexQ_enqP == 4'd9 &&
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ;
// register cache_cRqRetryIndexQ_deqP
assign cache_cRqRetryIndexQ_deqP$D_IN =
(cache_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
cache_cRqRetryIndexQ_clearReq_rl) ?
4'd0 :
_theResult_____2__h234513 ;
assign cache_cRqRetryIndexQ_deqP$EN = 1'd1 ;
// register cache_cRqRetryIndexQ_deqReq_rl
assign cache_cRqRetryIndexQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_cRqRetryIndexQ_deqReq_rl$EN = 1'd1 ;
// register cache_cRqRetryIndexQ_empty
assign cache_cRqRetryIndexQ_empty$D_IN =
cache_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
cache_cRqRetryIndexQ_clearReq_rl ||
IF_cache_cRqRetryIndexQ_deqReq_dummy2_2_read___ETC___d854 &&
NOT_cache_cRqRetryIndexQ_enqReq_dummy2_2_read__ETC___d876 ;
assign cache_cRqRetryIndexQ_empty$EN = 1'd1 ;
// register cache_cRqRetryIndexQ_enqP
assign cache_cRqRetryIndexQ_enqP$D_IN =
(cache_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT &&
cache_cRqRetryIndexQ_clearReq_rl) ?
4'd0 :
v__h232953 ;
assign cache_cRqRetryIndexQ_enqP$EN = 1'd1 ;
// register cache_cRqRetryIndexQ_enqReq_rl
assign cache_cRqRetryIndexQ_enqReq_rl$D_IN = 5'd10 ;
assign cache_cRqRetryIndexQ_enqReq_rl$EN = 1'd1 ;
// register cache_cRqRetryIndexQ_full
assign cache_cRqRetryIndexQ_full$D_IN =
NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 &&
IF_cache_cRqRetryIndexQ_deqReq_dummy2_2_read___ETC___d854 &&
cache_cRqRetryIndexQ_enqReq_dummy2_2_read__28__ETC___d864 ;
assign cache_cRqRetryIndexQ_full$EN = 1'd1 ;
// register cache_doLdAfterReplace
assign cache_doLdAfterReplace$D_IN = !cache_doLdAfterReplace ;
assign cache_doLdAfterReplace$EN =
WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd2 ;
// register cache_priorNewCRqSrc
assign cache_priorNewCRqSrc$D_IN = !cache_priorNewCRqSrc ;
assign cache_priorNewCRqSrc$EN =
WILL_FIRE_RL_cache_cRqTransfer_new_dma ||
WILL_FIRE_RL_cache_cRqTransfer_new_child ;
// register cache_rqFromCQ_clearReq_rl
assign cache_rqFromCQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_rqFromCQ_clearReq_rl$EN = 1'd1 ;
// register cache_rqFromCQ_data_0
assign cache_rqFromCQ_data_0$D_IN =
EN_to_child_rqFromC_enq ?
cache_rqFromCQ_enqReq_lat_0$wget[73:0] :
cache_rqFromCQ_enqReq_rl[73:0] ;
assign cache_rqFromCQ_data_0$EN =
cache_rqFromCQ_enqP == 1'd0 &&
NOT_cache_rqFromCQ_clearReq_dummy2_1_read__8_9_ETC___d33 &&
cache_rqFromCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromCQ_enqReq_lat_1_whas_THEN_cache_ETC___d39 ;
// register cache_rqFromCQ_data_1
assign cache_rqFromCQ_data_1$D_IN =
EN_to_child_rqFromC_enq ?
cache_rqFromCQ_enqReq_lat_0$wget[73:0] :
cache_rqFromCQ_enqReq_rl[73:0] ;
assign cache_rqFromCQ_data_1$EN =
cache_rqFromCQ_enqP == 1'd1 &&
NOT_cache_rqFromCQ_clearReq_dummy2_1_read__8_9_ETC___d33 &&
cache_rqFromCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromCQ_enqReq_lat_1_whas_THEN_cache_ETC___d39 ;
// register cache_rqFromCQ_deqP
assign cache_rqFromCQ_deqP$D_IN =
NOT_cache_rqFromCQ_clearReq_dummy2_1_read__8_9_ETC___d33 &&
_theResult_____2__h7215 ;
assign cache_rqFromCQ_deqP$EN = 1'd1 ;
// register cache_rqFromCQ_deqReq_rl
assign cache_rqFromCQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_rqFromCQ_deqReq_rl$EN = 1'd1 ;
// register cache_rqFromCQ_empty
assign cache_rqFromCQ_empty$D_IN =
cache_rqFromCQ_clearReq_dummy2_1$Q_OUT &&
cache_rqFromCQ_clearReq_rl ||
IF_cache_rqFromCQ_deqReq_dummy2_2_read__7_AND__ETC___d55 &&
NOT_cache_rqFromCQ_enqReq_dummy2_2_read__4_9_O_ETC___d78 ;
assign cache_rqFromCQ_empty$EN = 1'd1 ;
// register cache_rqFromCQ_enqP
assign cache_rqFromCQ_enqP$D_IN =
NOT_cache_rqFromCQ_clearReq_dummy2_1_read__8_9_ETC___d33 &&
v__h6037 ;
assign cache_rqFromCQ_enqP$EN = 1'd1 ;
// register cache_rqFromCQ_enqReq_rl
assign cache_rqFromCQ_enqReq_rl$D_IN = 75'h2AAAAAAAAAAAAAAAAAA ;
assign cache_rqFromCQ_enqReq_rl$EN = 1'd1 ;
// register cache_rqFromCQ_full
assign cache_rqFromCQ_full$D_IN =
NOT_cache_rqFromCQ_clearReq_dummy2_1_read__8_9_ETC___d33 &&
IF_cache_rqFromCQ_deqReq_dummy2_2_read__7_AND__ETC___d55 &&
cache_rqFromCQ_enqReq_dummy2_2_read__4_AND_IF__ETC___d65 ;
assign cache_rqFromCQ_full$EN = 1'd1 ;
// register cache_rqFromDmaQ_clearReq_rl
assign cache_rqFromDmaQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_rqFromDmaQ_clearReq_rl$EN = 1'd1 ;
// register cache_rqFromDmaQ_data_0
assign cache_rqFromDmaQ_data_0$D_IN =
EN_dma_memReq_enq ?
cache_rqFromDmaQ_enqReq_lat_0$wget[655:0] :
cache_rqFromDmaQ_enqReq_rl[655:0] ;
assign cache_rqFromDmaQ_data_0$EN =
cache_rqFromDmaQ_enqP == 1'd0 &&
NOT_cache_rqFromDmaQ_clearReq_dummy2_1_read__3_ETC___d339 &&
cache_rqFromDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromDmaQ_enqReq_lat_1_whas__09_THEN_ETC___d345 ;
// register cache_rqFromDmaQ_data_1
assign cache_rqFromDmaQ_data_1$D_IN =
EN_dma_memReq_enq ?
cache_rqFromDmaQ_enqReq_lat_0$wget[655:0] :
cache_rqFromDmaQ_enqReq_rl[655:0] ;
assign cache_rqFromDmaQ_data_1$EN =
cache_rqFromDmaQ_enqP == 1'd1 &&
NOT_cache_rqFromDmaQ_clearReq_dummy2_1_read__3_ETC___d339 &&
cache_rqFromDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromDmaQ_enqReq_lat_1_whas__09_THEN_ETC___d345 ;
// register cache_rqFromDmaQ_deqP
assign cache_rqFromDmaQ_deqP$D_IN =
NOT_cache_rqFromDmaQ_clearReq_dummy2_1_read__3_ETC___d339 &&
_theResult_____2__h119142 ;
assign cache_rqFromDmaQ_deqP$EN = 1'd1 ;
// register cache_rqFromDmaQ_deqReq_rl
assign cache_rqFromDmaQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_rqFromDmaQ_deqReq_rl$EN = 1'd1 ;
// register cache_rqFromDmaQ_empty
assign cache_rqFromDmaQ_empty$D_IN =
cache_rqFromDmaQ_clearReq_dummy2_1$Q_OUT &&
cache_rqFromDmaQ_clearReq_rl ||
IF_cache_rqFromDmaQ_deqReq_dummy2_2_read__53_A_ETC___d361 &&
NOT_cache_rqFromDmaQ_enqReq_dummy2_2_read__40__ETC___d384 ;
assign cache_rqFromDmaQ_empty$EN = 1'd1 ;
// register cache_rqFromDmaQ_enqP
assign cache_rqFromDmaQ_enqP$D_IN =
NOT_cache_rqFromDmaQ_clearReq_dummy2_1_read__3_ETC___d339 &&
v__h72082 ;
assign cache_rqFromDmaQ_enqP$EN = 1'd1 ;
// register cache_rqFromDmaQ_enqReq_rl
assign cache_rqFromDmaQ_enqReq_rl$D_IN =
657'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign cache_rqFromDmaQ_enqReq_rl$EN = 1'd1 ;
// register cache_rqFromDmaQ_full
assign cache_rqFromDmaQ_full$D_IN =
NOT_cache_rqFromDmaQ_clearReq_dummy2_1_read__3_ETC___d339 &&
IF_cache_rqFromDmaQ_deqReq_dummy2_2_read__53_A_ETC___d361 &&
cache_rqFromDmaQ_enqReq_dummy2_2_read__40_AND__ETC___d371 ;
assign cache_rqFromDmaQ_full$EN = 1'd1 ;
// register cache_rsFromCQ_clearReq_rl
assign cache_rsFromCQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_rsFromCQ_clearReq_rl$EN = 1'd1 ;
// register cache_rsFromCQ_data_0
assign cache_rsFromCQ_data_0$D_IN =
EN_to_child_rsFromC_enq ?
cache_rsFromCQ_enqReq_lat_0$wget[580:0] :
cache_rsFromCQ_enqReq_rl[580:0] ;
assign cache_rsFromCQ_data_0$EN =
cache_rsFromCQ_enqP == 1'd0 &&
NOT_cache_rsFromCQ_clearReq_dummy2_1_read__20__ETC___d125 &&
cache_rsFromCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromCQ_enqReq_lat_1_whas__5_THEN_ca_ETC___d131 ;
// register cache_rsFromCQ_data_1
assign cache_rsFromCQ_data_1$D_IN =
EN_to_child_rsFromC_enq ?
cache_rsFromCQ_enqReq_lat_0$wget[580:0] :
cache_rsFromCQ_enqReq_rl[580:0] ;
assign cache_rsFromCQ_data_1$EN =
cache_rsFromCQ_enqP == 1'd1 &&
NOT_cache_rsFromCQ_clearReq_dummy2_1_read__20__ETC___d125 &&
cache_rsFromCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromCQ_enqReq_lat_1_whas__5_THEN_ca_ETC___d131 ;
// register cache_rsFromCQ_deqP
assign cache_rsFromCQ_deqP$D_IN =
NOT_cache_rsFromCQ_clearReq_dummy2_1_read__20__ETC___d125 &&
_theResult_____2__h22297 ;
assign cache_rsFromCQ_deqP$EN = 1'd1 ;
// register cache_rsFromCQ_deqReq_rl
assign cache_rsFromCQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_rsFromCQ_deqReq_rl$EN = 1'd1 ;
// register cache_rsFromCQ_empty
assign cache_rsFromCQ_empty$D_IN =
cache_rsFromCQ_clearReq_dummy2_1$Q_OUT &&
cache_rsFromCQ_clearReq_rl ||
IF_cache_rsFromCQ_deqReq_dummy2_2_read__39_AND_ETC___d147 &&
NOT_cache_rsFromCQ_enqReq_dummy2_2_read__26_61_ETC___d170 ;
assign cache_rsFromCQ_empty$EN = 1'd1 ;
// register cache_rsFromCQ_enqP
assign cache_rsFromCQ_enqP$D_IN =
NOT_cache_rsFromCQ_clearReq_dummy2_1_read__20__ETC___d125 &&
v__h16641 ;
assign cache_rsFromCQ_enqP$EN = 1'd1 ;
// register cache_rsFromCQ_enqReq_rl
assign cache_rsFromCQ_enqReq_rl$D_IN =
582'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign cache_rsFromCQ_enqReq_rl$EN = 1'd1 ;
// register cache_rsFromCQ_full
assign cache_rsFromCQ_full$D_IN =
NOT_cache_rsFromCQ_clearReq_dummy2_1_read__20__ETC___d125 &&
IF_cache_rsFromCQ_deqReq_dummy2_2_read__39_AND_ETC___d147 &&
cache_rsFromCQ_enqReq_dummy2_2_read__26_AND_IF_ETC___d157 ;
assign cache_rsFromCQ_full$EN = 1'd1 ;
// register cache_rsFromMQ_clearReq_rl
assign cache_rsFromMQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_rsFromMQ_clearReq_rl$EN = 1'd1 ;
// register cache_rsFromMQ_data_0
assign cache_rsFromMQ_data_0$D_IN =
EN_to_mem_rsFromM_enq ?
cache_rsFromMQ_enqReq_lat_0$wget[516:0] :
cache_rsFromMQ_enqReq_rl[516:0] ;
assign cache_rsFromMQ_data_0$EN =
cache_rsFromMQ_enqP == 1'd0 &&
NOT_cache_rsFromMQ_clearReq_dummy2_1_read__35__ETC___d740 &&
cache_rsFromMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromMQ_enqReq_lat_1_whas__10_THEN_c_ETC___d746 ;
// register cache_rsFromMQ_data_1
assign cache_rsFromMQ_data_1$D_IN =
EN_to_mem_rsFromM_enq ?
cache_rsFromMQ_enqReq_lat_0$wget[516:0] :
cache_rsFromMQ_enqReq_rl[516:0] ;
assign cache_rsFromMQ_data_1$EN =
cache_rsFromMQ_enqP == 1'd1 &&
NOT_cache_rsFromMQ_clearReq_dummy2_1_read__35__ETC___d740 &&
cache_rsFromMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromMQ_enqReq_lat_1_whas__10_THEN_c_ETC___d746 ;
// register cache_rsFromMQ_deqP
assign cache_rsFromMQ_deqP$D_IN =
NOT_cache_rsFromMQ_clearReq_dummy2_1_read__35__ETC___d740 &&
_theResult_____2__h225016 ;
assign cache_rsFromMQ_deqP$EN = 1'd1 ;
// register cache_rsFromMQ_deqReq_rl
assign cache_rsFromMQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_rsFromMQ_deqReq_rl$EN = 1'd1 ;
// register cache_rsFromMQ_empty
assign cache_rsFromMQ_empty$D_IN =
cache_rsFromMQ_clearReq_dummy2_1$Q_OUT &&
cache_rsFromMQ_clearReq_rl ||
IF_cache_rsFromMQ_deqReq_dummy2_2_read__54_AND_ETC___d762 &&
NOT_cache_rsFromMQ_enqReq_dummy2_2_read__41_76_ETC___d785 ;
assign cache_rsFromMQ_empty$EN = 1'd1 ;
// register cache_rsFromMQ_enqP
assign cache_rsFromMQ_enqP$D_IN =
NOT_cache_rsFromMQ_clearReq_dummy2_1_read__35__ETC___d740 &&
v__h218716 ;
assign cache_rsFromMQ_enqP$EN = 1'd1 ;
// register cache_rsFromMQ_enqReq_rl
assign cache_rsFromMQ_enqReq_rl$D_IN =
518'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign cache_rsFromMQ_enqReq_rl$EN = 1'd1 ;
// register cache_rsFromMQ_full
assign cache_rsFromMQ_full$D_IN =
NOT_cache_rsFromMQ_clearReq_dummy2_1_read__35__ETC___d740 &&
IF_cache_rsFromMQ_deqReq_dummy2_2_read__54_AND_ETC___d762 &&
cache_rsFromMQ_enqReq_dummy2_2_read__41_AND_IF_ETC___d772 ;
assign cache_rsFromMQ_full$EN = 1'd1 ;
// register cache_rsLdToDmaQ_clearReq_rl
assign cache_rsLdToDmaQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_rsLdToDmaQ_clearReq_rl$EN = 1'd1 ;
// register cache_rsLdToDmaQ_data_0
assign cache_rsLdToDmaQ_data_0$D_IN =
CAN_FIRE_RL_cache_sendRsLdToDma ?
cache_rsLdToDmaQ_enqReq_lat_0$wget[527:0] :
cache_rsLdToDmaQ_enqReq_rl[527:0] ;
assign cache_rsLdToDmaQ_data_0$EN =
cache_rsLdToDmaQ_enqP == 1'd0 &&
NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__2_ETC___d430 &&
cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__00_THEN_ETC___d436 ;
// register cache_rsLdToDmaQ_data_1
assign cache_rsLdToDmaQ_data_1$D_IN =
CAN_FIRE_RL_cache_sendRsLdToDma ?
cache_rsLdToDmaQ_enqReq_lat_0$wget[527:0] :
cache_rsLdToDmaQ_enqReq_rl[527:0] ;
assign cache_rsLdToDmaQ_data_1$EN =
cache_rsLdToDmaQ_enqP == 1'd1 &&
NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__2_ETC___d430 &&
cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__00_THEN_ETC___d436 ;
// register cache_rsLdToDmaQ_deqP
assign cache_rsLdToDmaQ_deqP$D_IN =
NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__2_ETC___d430 &&
_theResult_____2__h135235 ;
assign cache_rsLdToDmaQ_deqP$EN = 1'd1 ;
// register cache_rsLdToDmaQ_deqReq_rl
assign cache_rsLdToDmaQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_rsLdToDmaQ_deqReq_rl$EN = 1'd1 ;
// register cache_rsLdToDmaQ_empty
assign cache_rsLdToDmaQ_empty$D_IN =
cache_rsLdToDmaQ_clearReq_dummy2_1$Q_OUT &&
cache_rsLdToDmaQ_clearReq_rl ||
IF_cache_rsLdToDmaQ_deqReq_dummy2_2_read__44_A_ETC___d452 &&
NOT_cache_rsLdToDmaQ_enqReq_dummy2_2_read__31__ETC___d475 ;
assign cache_rsLdToDmaQ_empty$EN = 1'd1 ;
// register cache_rsLdToDmaQ_enqP
assign cache_rsLdToDmaQ_enqP$D_IN =
NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__2_ETC___d430 &&
v__h129259 ;
assign cache_rsLdToDmaQ_enqP$EN = 1'd1 ;
// register cache_rsLdToDmaQ_enqReq_rl
assign cache_rsLdToDmaQ_enqReq_rl$D_IN =
529'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign cache_rsLdToDmaQ_enqReq_rl$EN = 1'd1 ;
// register cache_rsLdToDmaQ_full
assign cache_rsLdToDmaQ_full$D_IN =
NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__2_ETC___d430 &&
IF_cache_rsLdToDmaQ_deqReq_dummy2_2_read__44_A_ETC___d452 &&
cache_rsLdToDmaQ_enqReq_dummy2_2_read__31_AND__ETC___d462 ;
assign cache_rsLdToDmaQ_full$EN = 1'd1 ;
// register cache_rsStToDmaQ_clearReq_rl
assign cache_rsStToDmaQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_rsStToDmaQ_clearReq_rl$EN = 1'd1 ;
// register cache_rsStToDmaQ_data_0
assign cache_rsStToDmaQ_data_0$D_IN =
WILL_FIRE_RL_cache_sendRsStToDma ?
cache_rsStToDmaQ_enqReq_lat_0$wget[15:0] :
cache_rsStToDmaQ_enqReq_rl[15:0] ;
assign cache_rsStToDmaQ_data_0$EN =
cache_rsStToDmaQ_enqP == 1'd0 &&
NOT_cache_rsStToDmaQ_clearReq_dummy2_1_read__1_ETC___d521 &&
cache_rsStToDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsStToDmaQ_enqReq_lat_1_whas__91_THEN_ETC___d527 ;
// register cache_rsStToDmaQ_data_1
assign cache_rsStToDmaQ_data_1$D_IN =
WILL_FIRE_RL_cache_sendRsStToDma ?
cache_rsStToDmaQ_enqReq_lat_0$wget[15:0] :
cache_rsStToDmaQ_enqReq_rl[15:0] ;
assign cache_rsStToDmaQ_data_1$EN =
cache_rsStToDmaQ_enqP == 1'd1 &&
NOT_cache_rsStToDmaQ_clearReq_dummy2_1_read__1_ETC___d521 &&
cache_rsStToDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsStToDmaQ_enqReq_lat_1_whas__91_THEN_ETC___d527 ;
// register cache_rsStToDmaQ_deqP
assign cache_rsStToDmaQ_deqP$D_IN =
NOT_cache_rsStToDmaQ_clearReq_dummy2_1_read__1_ETC___d521 &&
_theResult_____2__h142737 ;
assign cache_rsStToDmaQ_deqP$EN = 1'd1 ;
// register cache_rsStToDmaQ_deqReq_rl
assign cache_rsStToDmaQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_rsStToDmaQ_deqReq_rl$EN = 1'd1 ;
// register cache_rsStToDmaQ_empty
assign cache_rsStToDmaQ_empty$D_IN =
cache_rsStToDmaQ_clearReq_dummy2_1$Q_OUT &&
cache_rsStToDmaQ_clearReq_rl ||
IF_cache_rsStToDmaQ_deqReq_dummy2_2_read__35_A_ETC___d543 &&
NOT_cache_rsStToDmaQ_enqReq_dummy2_2_read__22__ETC___d566 ;
assign cache_rsStToDmaQ_empty$EN = 1'd1 ;
// register cache_rsStToDmaQ_enqP
assign cache_rsStToDmaQ_enqP$D_IN =
NOT_cache_rsStToDmaQ_clearReq_dummy2_1_read__1_ETC___d521 &&
v__h142239 ;
assign cache_rsStToDmaQ_enqP$EN = 1'd1 ;
// register cache_rsStToDmaQ_enqReq_rl
assign cache_rsStToDmaQ_enqReq_rl$D_IN = 17'd43690 ;
assign cache_rsStToDmaQ_enqReq_rl$EN = 1'd1 ;
// register cache_rsStToDmaQ_full
assign cache_rsStToDmaQ_full$D_IN =
NOT_cache_rsStToDmaQ_clearReq_dummy2_1_read__1_ETC___d521 &&
IF_cache_rsStToDmaQ_deqReq_dummy2_2_read__35_A_ETC___d543 &&
cache_rsStToDmaQ_enqReq_dummy2_2_read__22_AND__ETC___d553 ;
assign cache_rsStToDmaQ_full$EN = 1'd1 ;
// register cache_rsToCIndexQ_clearReq_rl
assign cache_rsToCIndexQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_rsToCIndexQ_clearReq_rl$EN = 1'd1 ;
// register cache_rsToCIndexQ_data_0
assign cache_rsToCIndexQ_data_0$D_IN =
cache_rsToCIndexQ_enqReq_lat_0$whas ?
cache_rsToCIndexQ_enqReq_lat_0$wget[5:0] :
cache_rsToCIndexQ_enqReq_rl[5:0] ;
assign cache_rsToCIndexQ_data_0$EN =
cache_rsToCIndexQ_enqP == 4'd0 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_1
assign cache_rsToCIndexQ_data_1$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_1$EN =
cache_rsToCIndexQ_enqP == 4'd1 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_10
assign cache_rsToCIndexQ_data_10$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_10$EN =
cache_rsToCIndexQ_enqP == 4'd10 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_11
assign cache_rsToCIndexQ_data_11$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_11$EN =
cache_rsToCIndexQ_enqP == 4'd11 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_12
assign cache_rsToCIndexQ_data_12$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_12$EN =
cache_rsToCIndexQ_enqP == 4'd12 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_13
assign cache_rsToCIndexQ_data_13$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_13$EN =
cache_rsToCIndexQ_enqP == 4'd13 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_14
assign cache_rsToCIndexQ_data_14$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_14$EN =
cache_rsToCIndexQ_enqP == 4'd14 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_15
assign cache_rsToCIndexQ_data_15$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_15$EN =
cache_rsToCIndexQ_enqP == 4'd15 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_2
assign cache_rsToCIndexQ_data_2$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_2$EN =
cache_rsToCIndexQ_enqP == 4'd2 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_3
assign cache_rsToCIndexQ_data_3$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_3$EN =
cache_rsToCIndexQ_enqP == 4'd3 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_4
assign cache_rsToCIndexQ_data_4$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_4$EN =
cache_rsToCIndexQ_enqP == 4'd4 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_5
assign cache_rsToCIndexQ_data_5$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_5$EN =
cache_rsToCIndexQ_enqP == 4'd5 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_6
assign cache_rsToCIndexQ_data_6$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_6$EN =
cache_rsToCIndexQ_enqP == 4'd6 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_7
assign cache_rsToCIndexQ_data_7$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_7$EN =
cache_rsToCIndexQ_enqP == 4'd7 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_8
assign cache_rsToCIndexQ_data_8$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_8$EN =
cache_rsToCIndexQ_enqP == 4'd8 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_data_9
assign cache_rsToCIndexQ_data_9$D_IN = cache_rsToCIndexQ_data_0$D_IN ;
assign cache_rsToCIndexQ_data_9$EN =
cache_rsToCIndexQ_enqP == 4'd9 &&
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ;
// register cache_rsToCIndexQ_deqP
assign cache_rsToCIndexQ_deqP$D_IN =
(cache_rsToCIndexQ_clearReq_dummy2_1$Q_OUT &&
cache_rsToCIndexQ_clearReq_rl) ?
4'd0 :
_theResult_____2__h245988 ;
assign cache_rsToCIndexQ_deqP$EN = 1'd1 ;
// register cache_rsToCIndexQ_deqReq_rl
assign cache_rsToCIndexQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_rsToCIndexQ_deqReq_rl$EN = 1'd1 ;
// register cache_rsToCIndexQ_empty
assign cache_rsToCIndexQ_empty$D_IN =
cache_rsToCIndexQ_clearReq_dummy2_1$Q_OUT &&
cache_rsToCIndexQ_clearReq_rl ||
IF_cache_rsToCIndexQ_deqReq_dummy2_2_read__64__ETC___d977 &&
NOT_cache_rsToCIndexQ_enqReq_dummy2_2_read__51_ETC___d999 ;
assign cache_rsToCIndexQ_empty$EN = 1'd1 ;
// register cache_rsToCIndexQ_enqP
assign cache_rsToCIndexQ_enqP$D_IN =
(cache_rsToCIndexQ_clearReq_dummy2_1$Q_OUT &&
cache_rsToCIndexQ_clearReq_rl) ?
4'd0 :
v__h242396 ;
assign cache_rsToCIndexQ_enqP$EN = 1'd1 ;
// register cache_rsToCIndexQ_enqReq_rl
assign cache_rsToCIndexQ_enqReq_rl$D_IN = 7'd42 ;
assign cache_rsToCIndexQ_enqReq_rl$EN = 1'd1 ;
// register cache_rsToCIndexQ_full
assign cache_rsToCIndexQ_full$D_IN =
NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 &&
IF_cache_rsToCIndexQ_deqReq_dummy2_2_read__64__ETC___d977 &&
cache_rsToCIndexQ_enqReq_dummy2_2_read__51_AND_ETC___d987 ;
assign cache_rsToCIndexQ_full$EN = 1'd1 ;
// register cache_toCQ_clearReq_rl
assign cache_toCQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_toCQ_clearReq_rl$EN = 1'd1 ;
// register cache_toCQ_data_0
assign cache_toCQ_data_0$D_IN =
{ cache_toCQ_enqReq_lat_0$whas ?
cache_toCQ_enqReq_lat_0$wget[584] :
cache_toCQ_enqReq_rl[584],
IF_cache_toCQ_enqReq_dummy2_2_read__53_AND_IF__ETC___d302 } ;
assign cache_toCQ_data_0$EN =
cache_toCQ_enqP == 1'd0 &&
NOT_cache_toCQ_clearReq_dummy2_1_read__47_48_O_ETC___d252 &&
cache_toCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toCQ_enqReq_lat_1_whas__87_THEN_cache_ETC___d196 ;
// register cache_toCQ_data_1
assign cache_toCQ_data_1$D_IN = cache_toCQ_data_0$D_IN ;
assign cache_toCQ_data_1$EN =
cache_toCQ_enqP == 1'd1 &&
NOT_cache_toCQ_clearReq_dummy2_1_read__47_48_O_ETC___d252 &&
cache_toCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toCQ_enqReq_lat_1_whas__87_THEN_cache_ETC___d196 ;
// register cache_toCQ_deqP
assign cache_toCQ_deqP$D_IN =
NOT_cache_toCQ_clearReq_dummy2_1_read__47_48_O_ETC___d252 &&
_theResult_____2__h37990 ;
assign cache_toCQ_deqP$EN = 1'd1 ;
// register cache_toCQ_deqReq_rl
assign cache_toCQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_toCQ_deqReq_rl$EN = 1'd1 ;
// register cache_toCQ_empty
assign cache_toCQ_empty$D_IN =
cache_toCQ_clearReq_dummy2_1$Q_OUT && cache_toCQ_clearReq_rl ||
IF_cache_toCQ_deqReq_dummy2_2_read__61_AND_IF__ETC___d269 &&
NOT_cache_toCQ_enqReq_dummy2_2_read__53_83_OR__ETC___d292 ;
assign cache_toCQ_empty$EN = 1'd1 ;
// register cache_toCQ_enqP
assign cache_toCQ_enqP$D_IN =
NOT_cache_toCQ_clearReq_dummy2_1_read__47_48_O_ETC___d252 &&
v__h31944 ;
assign cache_toCQ_enqP$EN = 1'd1 ;
// register cache_toCQ_enqReq_rl
assign cache_toCQ_enqReq_rl$D_IN =
586'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign cache_toCQ_enqReq_rl$EN = 1'd1 ;
// register cache_toCQ_full
assign cache_toCQ_full$D_IN =
NOT_cache_toCQ_clearReq_dummy2_1_read__47_48_O_ETC___d252 &&
IF_cache_toCQ_deqReq_dummy2_2_read__61_AND_IF__ETC___d269 &&
cache_toCQ_enqReq_dummy2_2_read__53_AND_IF_cac_ETC___d279 ;
assign cache_toCQ_full$EN = 1'd1 ;
// register cache_toMQ_clearReq_rl
assign cache_toMQ_clearReq_rl$D_IN = 1'd0 ;
assign cache_toMQ_clearReq_rl$EN = 1'd1 ;
// register cache_toMQ_data_0
assign cache_toMQ_data_0$D_IN =
{ cache_toMQ_enqReq_lat_0$whas ?
cache_toMQ_enqReq_lat_0$wget[640] :
cache_toMQ_enqReq_rl[640],
IF_cache_toMQ_enqReq_dummy2_2_read__54_AND_IF__ETC___d703 } ;
assign cache_toMQ_data_0$EN =
cache_toMQ_enqP == 1'd0 &&
NOT_cache_toMQ_clearReq_dummy2_1_read__48_49_O_ETC___d653 &&
cache_toMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toMQ_enqReq_lat_1_whas__88_THEN_cache_ETC___d597 ;
// register cache_toMQ_data_1
assign cache_toMQ_data_1$D_IN = cache_toMQ_data_0$D_IN ;
assign cache_toMQ_data_1$EN =
cache_toMQ_enqP == 1'd1 &&
NOT_cache_toMQ_clearReq_dummy2_1_read__48_49_O_ETC___d653 &&
cache_toMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toMQ_enqReq_lat_1_whas__88_THEN_cache_ETC___d597 ;
// register cache_toMQ_deqP
assign cache_toMQ_deqP$D_IN =
NOT_cache_toMQ_clearReq_dummy2_1_read__48_49_O_ETC___d653 &&
_theResult_____2__h208521 ;
assign cache_toMQ_deqP$EN = 1'd1 ;
// register cache_toMQ_deqReq_rl
assign cache_toMQ_deqReq_rl$D_IN = 1'd0 ;
assign cache_toMQ_deqReq_rl$EN = 1'd1 ;
// register cache_toMQ_empty
assign cache_toMQ_empty$D_IN =
cache_toMQ_clearReq_dummy2_1$Q_OUT && cache_toMQ_clearReq_rl ||
IF_cache_toMQ_deqReq_dummy2_2_read__62_AND_IF__ETC___d670 &&
NOT_cache_toMQ_enqReq_dummy2_2_read__54_84_OR__ETC___d693 ;
assign cache_toMQ_empty$EN = 1'd1 ;
// register cache_toMQ_enqP
assign cache_toMQ_enqP$D_IN =
NOT_cache_toMQ_clearReq_dummy2_1_read__48_49_O_ETC___d653 &&
v__h168573 ;
assign cache_toMQ_enqP$EN = 1'd1 ;
// register cache_toMQ_enqReq_rl
assign cache_toMQ_enqReq_rl$D_IN =
642'h055555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555554AAAAAAAAAAAAAAAAA ;
assign cache_toMQ_enqReq_rl$EN = 1'd1 ;
// register cache_toMQ_full
assign cache_toMQ_full$D_IN =
NOT_cache_toMQ_clearReq_dummy2_1_read__48_49_O_ETC___d653 &&
IF_cache_toMQ_deqReq_dummy2_2_read__62_AND_IF__ETC___d670 &&
cache_toMQ_enqReq_dummy2_2_read__54_AND_IF_cac_ETC___d680 ;
assign cache_toMQ_full$EN = 1'd1 ;
// register cache_whichCRq
assign cache_whichCRq$D_IN =
(cache_whichCRq == 4'd15) ? 4'd0 : cache_whichCRq + 4'd1 ;
assign cache_whichCRq$EN = CAN_FIRE_RL_cache_sendRqToC ;
// register perfReqQ_clearReq_rl
assign perfReqQ_clearReq_rl$D_IN = 1'd0 ;
assign perfReqQ_clearReq_rl$EN = 1'd1 ;
// register perfReqQ_data_0
assign perfReqQ_data_0$D_IN =
EN_perf_req ?
perfReqQ_enqReq_lat_0$wget[3:0] :
perfReqQ_enqReq_rl[3:0] ;
assign perfReqQ_data_0$EN =
NOT_perfReqQ_clearReq_dummy2_1_read__864_865_O_ETC___d3869 &&
perfReqQ_enqReq_dummy2_2$Q_OUT &&
IF_perfReqQ_enqReq_lat_1_whas__839_THEN_perfRe_ETC___d3875 ;
// register perfReqQ_deqReq_rl
assign perfReqQ_deqReq_rl$D_IN = 1'd0 ;
assign perfReqQ_deqReq_rl$EN = 1'd1 ;
// register perfReqQ_empty
assign perfReqQ_empty$D_IN =
perfReqQ_clearReq_dummy2_1$Q_OUT && perfReqQ_clearReq_rl ||
NOT_perfReqQ_enqReq_dummy2_2_read__870_890_OR__ETC___d3900 ;
assign perfReqQ_empty$EN = 1'd1 ;
// register perfReqQ_enqReq_rl
assign perfReqQ_enqReq_rl$D_IN = 5'd10 ;
assign perfReqQ_enqReq_rl$EN = 1'd1 ;
// register perfReqQ_full
assign perfReqQ_full$D_IN =
NOT_perfReqQ_clearReq_dummy2_1_read__864_865_O_ETC___d3869 &&
perfReqQ_enqReq_dummy2_2_read__870_AND_IF_perf_ETC___d3887 ;
assign perfReqQ_full$EN = 1'd1 ;
// submodule cache_cRqMshr
assign cache_cRqMshr$mRsDeq_setData_d =
{ 1'd1,
SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1966 } ;
assign cache_cRqMshr$mRsDeq_setData_n =
MUX_cache_cRqMshr$transfer_getRq_1__VAL_2 ;
assign cache_cRqMshr$pipelineResp_getAddrSucc_n = pipeOutCRqIdx__h314276 ;
assign cache_cRqMshr$pipelineResp_getData_n =
WILL_FIRE_RL_cache_pipelineResp_cRq ?
cache_pipeline$first[582:579] :
cache_pipeline$first[516:513] ;
assign cache_cRqMshr$pipelineResp_getRepSucc_n = pipeOutCRqIdx__h314276 ;
assign cache_cRqMshr$pipelineResp_getRq_n = pipeOutCRqIdx__h314276 ;
assign cache_cRqMshr$pipelineResp_getSlot_n = pipeOutCRqIdx__h314276 ;
assign cache_cRqMshr$pipelineResp_getState_n = pipeOutCRqIdx__h314276 ;
assign cache_cRqMshr$pipelineResp_searchEndOfChain_addr =
cache_cRqMshr$pipelineResp_getRq[151:88] ;
assign cache_cRqMshr$pipelineResp_setAddrSucc_n =
cache_cRqMshr$pipelineResp_searchEndOfChain[3:0] ;
assign cache_cRqMshr$pipelineResp_setAddrSucc_succ =
{ 1'd1, cache_pipeline$first[582:579] } ;
always@(MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_1 or
MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_1 or
MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_2 or
MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_2 or
WILL_FIRE_RL_cache_pipelineResp_mRs or
MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_1:
cache_cRqMshr$pipelineResp_setData_d =
MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_1;
MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_2:
cache_cRqMshr$pipelineResp_setData_d =
MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_2;
WILL_FIRE_RL_cache_pipelineResp_mRs:
cache_cRqMshr$pipelineResp_setData_d =
MUX_cache_cRqMshr$pipelineResp_setData_2__VAL_3;
default: cache_cRqMshr$pipelineResp_setData_d =
513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign cache_cRqMshr$pipelineResp_setData_n =
(MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_2 ||
WILL_FIRE_RL_cache_pipelineResp_mRs) ?
cache_pipeline$first[516:513] :
cache_pipeline$first[582:579] ;
assign cache_cRqMshr$pipelineResp_setRepSucc_n =
cache_pipeline$first[516:513] ;
assign cache_cRqMshr$pipelineResp_setRepSucc_succ =
{ 1'd1, cache_pipeline$first[582:579] } ;
assign cache_cRqMshr$pipelineResp_setStateSlot_n =
(MUX_cache_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 ||
WILL_FIRE_RL_cache_pipelineResp_mRs) ?
cache_pipeline$first[516:513] :
cache_pipeline$first[582:579] ;
always@(MUX_cache_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 or
MUX_cache_cRqMshr$pipelineResp_setStateSlot_3__VAL_1 or
WILL_FIRE_RL_cache_pipelineResp_cRq or
MUX_cache_cRqMshr$pipelineResp_setStateSlot_3__VAL_2 or
WILL_FIRE_RL_cache_pipelineResp_mRs)
begin
case (1'b1) // synopsys parallel_case
MUX_cache_cRqMshr$pipelineResp_setStateSlot_1__SEL_1:
cache_cRqMshr$pipelineResp_setStateSlot_slot =
MUX_cache_cRqMshr$pipelineResp_setStateSlot_3__VAL_1;
WILL_FIRE_RL_cache_pipelineResp_cRq:
cache_cRqMshr$pipelineResp_setStateSlot_slot =
MUX_cache_cRqMshr$pipelineResp_setStateSlot_3__VAL_2;
WILL_FIRE_RL_cache_pipelineResp_mRs:
cache_cRqMshr$pipelineResp_setStateSlot_slot =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
default: cache_cRqMshr$pipelineResp_setStateSlot_slot =
65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(MUX_cache_cRqMshr$pipelineResp_setStateSlot_1__SEL_1 or
MUX_cache_cRqMshr$pipelineResp_setStateSlot_2__VAL_1 or
WILL_FIRE_RL_cache_pipelineResp_cRq or
MUX_cache_cRqMshr$pipelineResp_setStateSlot_2__VAL_2 or
WILL_FIRE_RL_cache_pipelineResp_mRs)
begin
case (1'b1) // synopsys parallel_case
MUX_cache_cRqMshr$pipelineResp_setStateSlot_1__SEL_1:
cache_cRqMshr$pipelineResp_setStateSlot_state =
MUX_cache_cRqMshr$pipelineResp_setStateSlot_2__VAL_1;
WILL_FIRE_RL_cache_pipelineResp_cRq:
cache_cRqMshr$pipelineResp_setStateSlot_state =
MUX_cache_cRqMshr$pipelineResp_setStateSlot_2__VAL_2;
WILL_FIRE_RL_cache_pipelineResp_mRs:
cache_cRqMshr$pipelineResp_setStateSlot_state = 3'd4;
default: cache_cRqMshr$pipelineResp_setStateSlot_state =
3'b010 /* unspecified value */ ;
endcase
end
assign cache_cRqMshr$sendRqToC_getRq_n =
cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0] ;
assign cache_cRqMshr$sendRqToC_getSlot_n =
cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0] ;
assign cache_cRqMshr$sendRqToC_getState_n =
cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0] ;
assign cache_cRqMshr$sendRqToC_searchNeedRqChild_suggestIdx =
{ 1'd1, cache_whichCRq } ;
assign cache_cRqMshr$sendRqToC_setSlot_n =
cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0] ;
assign cache_cRqMshr$sendRqToC_setSlot_s =
{ cache_cRqMshr$sendRqToC_getSlot[64:12],
(cache_cRqMshr$sendRqToC_getSlot[3:2] != 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[7:6] != 2'd1) ?
2'd2 :
cache_cRqMshr$sendRqToC_getSlot[11:10],
((cache_cRqMshr$sendRqToC_getSlot[3:2] == 2'd1 ||
cache_cRqMshr$sendRqToC_getSlot[7:6] == 2'd1) &&
cache_cRqMshr$sendRqToC_getSlot[11:10] == 2'd1) ?
cache_cRqMshr$sendRqToC_getSlot[9:8] :
((cache_cRqMshr$sendRqToC_getSlot[3:2] != 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[7:6] != 2'd1) ?
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522 :
cache_cRqMshr$sendRqToC_getSlot[9:8]),
(cache_cRqMshr$sendRqToC_getSlot[7:6] == 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[3:2] != 2'd1) ?
2'd2 :
cache_cRqMshr$sendRqToC_getSlot[7:6],
(cache_cRqMshr$sendRqToC_getSlot[3:2] == 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[7:6] == 2'd1) ?
cache_cRqMshr$sendRqToC_getSlot[5:4] :
((cache_cRqMshr$sendRqToC_getSlot[7:6] == 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[3:2] != 2'd1) ?
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522 :
cache_cRqMshr$sendRqToC_getSlot[5:4]),
(cache_cRqMshr$sendRqToC_getSlot[3:2] == 2'd1) ?
2'd2 :
cache_cRqMshr$sendRqToC_getSlot[3:2],
(cache_cRqMshr$sendRqToC_getSlot[3:2] == 2'd1) ?
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522 :
cache_cRqMshr$sendRqToC_getSlot[1:0] } ;
assign cache_cRqMshr$sendRsToDmaC_getData_n =
WILL_FIRE_RL_cache_sendRsLdToDma ?
cache_rsLdToDmaIndexQ$D_OUT :
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 ;
always@(WILL_FIRE_RL_cache_sendRsLdToDma or
cache_rsLdToDmaIndexQ$D_OUT or
WILL_FIRE_RL_cache_sendRsToC or
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 or
WILL_FIRE_RL_cache_sendRsStToDma or cache_rsStToDmaIndexQ$D_OUT)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_cache_sendRsLdToDma:
cache_cRqMshr$sendRsToDmaC_getRq_n = cache_rsLdToDmaIndexQ$D_OUT;
WILL_FIRE_RL_cache_sendRsToC:
cache_cRqMshr$sendRsToDmaC_getRq_n =
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2;
WILL_FIRE_RL_cache_sendRsStToDma:
cache_cRqMshr$sendRsToDmaC_getRq_n = cache_rsStToDmaIndexQ$D_OUT;
default: cache_cRqMshr$sendRsToDmaC_getRq_n =
4'b1010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_cache_sendRsLdToDma or
cache_rsLdToDmaIndexQ$D_OUT or
WILL_FIRE_RL_cache_sendRsToC or
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2 or
WILL_FIRE_RL_cache_sendRsStToDma or cache_rsStToDmaIndexQ$D_OUT)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_cache_sendRsLdToDma:
cache_cRqMshr$sendRsToDmaC_releaseEntry_n =
cache_rsLdToDmaIndexQ$D_OUT;
WILL_FIRE_RL_cache_sendRsToC:
cache_cRqMshr$sendRsToDmaC_releaseEntry_n =
MUX_cache_cRqMshr$sendRsToDmaC_getData_1__VAL_2;
WILL_FIRE_RL_cache_sendRsStToDma:
cache_cRqMshr$sendRsToDmaC_releaseEntry_n =
cache_rsStToDmaIndexQ$D_OUT;
default: cache_cRqMshr$sendRsToDmaC_releaseEntry_n =
4'b1010 /* unspecified value */ ;
endcase
end
assign cache_cRqMshr$sendToM_getData_n = cache_toMInfoQ$D_OUT[5:2] ;
assign cache_cRqMshr$sendToM_getRq_n = cache_toMInfoQ$D_OUT[5:2] ;
assign cache_cRqMshr$sendToM_getSlot_n = cache_toMInfoQ$D_OUT[5:2] ;
assign cache_cRqMshr$transfer_getEmptyEntryInit_d =
WILL_FIRE_RL_cache_cRqTransfer_new_child ?
513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_cache_cRqMshr$transfer_getEmptyEntryInit_2__VAL_2 ;
assign cache_cRqMshr$transfer_getEmptyEntryInit_r =
WILL_FIRE_RL_cache_cRqTransfer_new_child ?
MUX_cache_cRqMshr$transfer_getEmptyEntryInit_1__VAL_1 :
MUX_cache_cRqMshr$transfer_getEmptyEntryInit_1__VAL_2 ;
assign cache_cRqMshr$transfer_getRq_n =
WILL_FIRE_RL_cache_cRqTransfer_retry ?
x__h248737 :
MUX_cache_cRqMshr$transfer_getRq_1__VAL_2 ;
assign cache_cRqMshr$transfer_getSlot_n =
MUX_cache_cRqMshr$transfer_getRq_1__VAL_2 ;
assign cache_cRqMshr$transfer_hasEmptyEntry_r = 152'h0 ;
assign cache_cRqMshr$EN_transfer_getEmptyEntryInit =
WILL_FIRE_RL_cache_cRqTransfer_new_child ||
WILL_FIRE_RL_cache_cRqTransfer_new_dma ;
assign cache_cRqMshr$EN_mRsDeq_setData =
CAN_FIRE_RL_cache_mRsDeq_nonRefill ;
assign cache_cRqMshr$EN_sendRsToDmaC_releaseEntry =
WILL_FIRE_RL_cache_sendRsLdToDma ||
WILL_FIRE_RL_cache_sendRsToC ||
WILL_FIRE_RL_cache_sendRsStToDma ;
assign cache_cRqMshr$EN_sendRqToC_setSlot = CAN_FIRE_RL_cache_sendRqToC ;
assign cache_cRqMshr$EN_pipelineResp_setData =
MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_1 ||
MUX_cache_cRqMshr$pipelineResp_setData_1__SEL_2 ||
WILL_FIRE_RL_cache_pipelineResp_mRs ;
assign cache_cRqMshr$EN_pipelineResp_setStateSlot =
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[517] ||
WILL_FIRE_RL_cache_pipelineResp_cRq ||
WILL_FIRE_RL_cache_pipelineResp_mRs ;
assign cache_cRqMshr$EN_pipelineResp_setAddrSucc =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline$first[517] &&
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
!cache_pipeline$first[517] &&
cache_cRqMshr$pipelineResp_searchEndOfChain[4] &&
cache_cRqMshr$pipelineResp_getState == 3'd1) ;
assign cache_cRqMshr$EN_pipelineResp_setRepSucc =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline$first[517] &&
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ;
assign cache_cRqMshr$EN_stuck_get = EN_cRqStuck_get ;
// submodule cache_cRqRetryIndexQ_clearReq_dummy2_0
assign cache_cRqRetryIndexQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_cRqRetryIndexQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_cRqRetryIndexQ_clearReq_dummy2_1
assign cache_cRqRetryIndexQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_cRqRetryIndexQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_cRqRetryIndexQ_deqReq_dummy2_0
assign cache_cRqRetryIndexQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_cRqRetryIndexQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_cache_cRqTransfer_retry ;
// submodule cache_cRqRetryIndexQ_deqReq_dummy2_1
assign cache_cRqRetryIndexQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_cRqRetryIndexQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_cRqRetryIndexQ_deqReq_dummy2_2
assign cache_cRqRetryIndexQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_cRqRetryIndexQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_cRqRetryIndexQ_enqReq_dummy2_0
assign cache_cRqRetryIndexQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_cRqRetryIndexQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3332 ||
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 &&
cache_cRqMshr$pipelineResp_getRepSucc[4] ;
// submodule cache_cRqRetryIndexQ_enqReq_dummy2_1
assign cache_cRqRetryIndexQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_cRqRetryIndexQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_cRqRetryIndexQ_enqReq_dummy2_2
assign cache_cRqRetryIndexQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_cRqRetryIndexQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_pipeline
always@(WILL_FIRE_RL_cache_pipelineResp_mRs or
cache_cRqMshr$pipelineResp_getAddrSucc or
WILL_FIRE_RL_cache_pipelineResp_cRq or
MUX_cache_pipeline$deqWrite_1__VAL_2 or
WILL_FIRE_RL_cache_pipelineResp_cRs or
MUX_cache_pipeline$deqWrite_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_cache_pipelineResp_mRs:
cache_pipeline$deqWrite_swapRq =
cache_cRqMshr$pipelineResp_getAddrSucc;
WILL_FIRE_RL_cache_pipelineResp_cRq:
cache_pipeline$deqWrite_swapRq =
MUX_cache_pipeline$deqWrite_1__VAL_2;
WILL_FIRE_RL_cache_pipelineResp_cRs:
cache_pipeline$deqWrite_swapRq =
MUX_cache_pipeline$deqWrite_1__VAL_3;
default: cache_pipeline$deqWrite_swapRq =
5'b01010 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_cache_pipelineResp_mRs or
WILL_FIRE_RL_cache_pipelineResp_cRq or
MUX_cache_pipeline$deqWrite_3__VAL_2 or
WILL_FIRE_RL_cache_pipelineResp_cRs or
MUX_cache_pipeline$deqWrite_3__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_cache_pipelineResp_mRs:
cache_pipeline$deqWrite_updateRep = 1'd1;
WILL_FIRE_RL_cache_pipelineResp_cRq:
cache_pipeline$deqWrite_updateRep =
MUX_cache_pipeline$deqWrite_3__VAL_2;
WILL_FIRE_RL_cache_pipelineResp_cRs:
cache_pipeline$deqWrite_updateRep =
MUX_cache_pipeline$deqWrite_3__VAL_3;
default: cache_pipeline$deqWrite_updateRep =
1'b0 /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_cache_pipelineResp_mRs or
MUX_cache_pipeline$deqWrite_2__VAL_1 or
WILL_FIRE_RL_cache_pipelineResp_cRq or
MUX_cache_pipeline$deqWrite_2__VAL_2 or
WILL_FIRE_RL_cache_pipelineResp_cRs or
MUX_cache_pipeline$deqWrite_2__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_cache_pipelineResp_mRs:
cache_pipeline$deqWrite_wrRam =
MUX_cache_pipeline$deqWrite_2__VAL_1;
WILL_FIRE_RL_cache_pipelineResp_cRq:
cache_pipeline$deqWrite_wrRam =
MUX_cache_pipeline$deqWrite_2__VAL_2;
WILL_FIRE_RL_cache_pipelineResp_cRs:
cache_pipeline$deqWrite_wrRam =
MUX_cache_pipeline$deqWrite_2__VAL_3;
default: cache_pipeline$deqWrite_wrRam =
574'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
always@(WILL_FIRE_RL_cache_cRqTransfer_retry or
MUX_cache_pipeline$send_1__VAL_1 or
WILL_FIRE_RL_cache_cRqTransfer_new_child or
MUX_cache_pipeline$send_1__VAL_2 or
WILL_FIRE_RL_cache_cRqTransfer_new_dma or
MUX_cache_pipeline$send_1__VAL_3 or
WILL_FIRE_RL_cache_cRsTransfer or
MUX_cache_pipeline$send_1__VAL_4 or
WILL_FIRE_RL_cache_mRsTransfer or MUX_cache_pipeline$send_1__VAL_5)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_cache_cRqTransfer_retry:
cache_pipeline$send_r = MUX_cache_pipeline$send_1__VAL_1;
WILL_FIRE_RL_cache_cRqTransfer_new_child:
cache_pipeline$send_r = MUX_cache_pipeline$send_1__VAL_2;
WILL_FIRE_RL_cache_cRqTransfer_new_dma:
cache_pipeline$send_r = MUX_cache_pipeline$send_1__VAL_3;
WILL_FIRE_RL_cache_cRsTransfer:
cache_pipeline$send_r = MUX_cache_pipeline$send_1__VAL_4;
WILL_FIRE_RL_cache_mRsTransfer:
cache_pipeline$send_r = MUX_cache_pipeline$send_1__VAL_5;
default: cache_pipeline$send_r =
584'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign cache_pipeline$EN_send =
WILL_FIRE_RL_cache_cRqTransfer_retry ||
WILL_FIRE_RL_cache_cRqTransfer_new_child ||
WILL_FIRE_RL_cache_cRqTransfer_new_dma ||
WILL_FIRE_RL_cache_cRsTransfer ||
WILL_FIRE_RL_cache_mRsTransfer ;
assign cache_pipeline$EN_deqWrite =
WILL_FIRE_RL_cache_pipelineResp_mRs ||
WILL_FIRE_RL_cache_pipelineResp_cRq ||
WILL_FIRE_RL_cache_pipelineResp_cRs ;
// submodule cache_rqFromCQ_clearReq_dummy2_0
assign cache_rqFromCQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_rqFromCQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_rqFromCQ_clearReq_dummy2_1
assign cache_rqFromCQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_rqFromCQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_rqFromCQ_deqReq_dummy2_0
assign cache_rqFromCQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rqFromCQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_cache_cRqTransfer_new_child ;
// submodule cache_rqFromCQ_deqReq_dummy2_1
assign cache_rqFromCQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rqFromCQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rqFromCQ_deqReq_dummy2_2
assign cache_rqFromCQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rqFromCQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rqFromCQ_enqReq_dummy2_0
assign cache_rqFromCQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rqFromCQ_enqReq_dummy2_0$EN = EN_to_child_rqFromC_enq ;
// submodule cache_rqFromCQ_enqReq_dummy2_1
assign cache_rqFromCQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rqFromCQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rqFromCQ_enqReq_dummy2_2
assign cache_rqFromCQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rqFromCQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rqFromDmaQ_clearReq_dummy2_0
assign cache_rqFromDmaQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_rqFromDmaQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_rqFromDmaQ_clearReq_dummy2_1
assign cache_rqFromDmaQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_rqFromDmaQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_rqFromDmaQ_deqReq_dummy2_0
assign cache_rqFromDmaQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rqFromDmaQ_deqReq_dummy2_0$EN =
WILL_FIRE_RL_cache_cRqTransfer_new_dma ;
// submodule cache_rqFromDmaQ_deqReq_dummy2_1
assign cache_rqFromDmaQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rqFromDmaQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rqFromDmaQ_deqReq_dummy2_2
assign cache_rqFromDmaQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rqFromDmaQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rqFromDmaQ_enqReq_dummy2_0
assign cache_rqFromDmaQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rqFromDmaQ_enqReq_dummy2_0$EN = EN_dma_memReq_enq ;
// submodule cache_rqFromDmaQ_enqReq_dummy2_1
assign cache_rqFromDmaQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rqFromDmaQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rqFromDmaQ_enqReq_dummy2_2
assign cache_rqFromDmaQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rqFromDmaQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsFromCQ_clearReq_dummy2_0
assign cache_rsFromCQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_rsFromCQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_rsFromCQ_clearReq_dummy2_1
assign cache_rsFromCQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_rsFromCQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_rsFromCQ_deqReq_dummy2_0
assign cache_rsFromCQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsFromCQ_deqReq_dummy2_0$EN = WILL_FIRE_RL_cache_cRsTransfer ;
// submodule cache_rsFromCQ_deqReq_dummy2_1
assign cache_rsFromCQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsFromCQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsFromCQ_deqReq_dummy2_2
assign cache_rsFromCQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsFromCQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsFromCQ_enqReq_dummy2_0
assign cache_rsFromCQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsFromCQ_enqReq_dummy2_0$EN = EN_to_child_rsFromC_enq ;
// submodule cache_rsFromCQ_enqReq_dummy2_1
assign cache_rsFromCQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsFromCQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsFromCQ_enqReq_dummy2_2
assign cache_rsFromCQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsFromCQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsFromMQ_clearReq_dummy2_0
assign cache_rsFromMQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_rsFromMQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_rsFromMQ_clearReq_dummy2_1
assign cache_rsFromMQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_rsFromMQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_rsFromMQ_deqReq_dummy2_0
assign cache_rsFromMQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsFromMQ_deqReq_dummy2_0$EN =
cache_rsFromMQ_deqReq_lat_0$whas ;
// submodule cache_rsFromMQ_deqReq_dummy2_1
assign cache_rsFromMQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsFromMQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsFromMQ_deqReq_dummy2_2
assign cache_rsFromMQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsFromMQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsFromMQ_enqReq_dummy2_0
assign cache_rsFromMQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsFromMQ_enqReq_dummy2_0$EN = EN_to_mem_rsFromM_enq ;
// submodule cache_rsFromMQ_enqReq_dummy2_1
assign cache_rsFromMQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsFromMQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsFromMQ_enqReq_dummy2_2
assign cache_rsFromMQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsFromMQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsLdToDmaIndexQ
assign cache_rsLdToDmaIndexQ$D_IN =
WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_mRsDeq ?
cache_rsLdToDmaIndexQ_mRsDeq$D_OUT :
cache_rsLdToDmaIndexQ_pipelineResp$D_OUT ;
assign cache_rsLdToDmaIndexQ$ENQ =
WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_mRsDeq ||
WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_pipelineResp ;
assign cache_rsLdToDmaIndexQ$DEQ = CAN_FIRE_RL_cache_sendRsLdToDma ;
assign cache_rsLdToDmaIndexQ$CLR = 1'b0 ;
// submodule cache_rsLdToDmaIndexQ_mRsDeq
assign cache_rsLdToDmaIndexQ_mRsDeq$D_IN =
MUX_cache_cRqMshr$transfer_getRq_1__VAL_2 ;
assign cache_rsLdToDmaIndexQ_mRsDeq$ENQ =
CAN_FIRE_RL_cache_mRsDeq_nonRefill ;
assign cache_rsLdToDmaIndexQ_mRsDeq$DEQ =
WILL_FIRE_RL_cache_mergeRsLdToDmaIndexQ_mRsDeq ;
assign cache_rsLdToDmaIndexQ_mRsDeq$CLR = 1'b0 ;
// submodule cache_rsLdToDmaIndexQ_pipelineResp
assign cache_rsLdToDmaIndexQ_pipelineResp$D_IN =
MUX_cache_rsLdToDmaIndexQ_pipelineResp$enq_1__SEL_1 ?
cache_pipeline$first[582:579] :
cache_pipeline$first[516:513] ;
assign cache_rsLdToDmaIndexQ_pipelineResp$ENQ =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3139 ||
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3143) ||
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline_first__581_BIT_517_582_AND_NOT__ETC___d3824 ;
assign cache_rsLdToDmaIndexQ_pipelineResp$DEQ =
CAN_FIRE_RL_cache_mergeRsLdToDmaIndexQ_pipelineResp ;
assign cache_rsLdToDmaIndexQ_pipelineResp$CLR = 1'b0 ;
// submodule cache_rsLdToDmaQ_clearReq_dummy2_0
assign cache_rsLdToDmaQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_rsLdToDmaQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_rsLdToDmaQ_clearReq_dummy2_1
assign cache_rsLdToDmaQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_rsLdToDmaQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_rsLdToDmaQ_deqReq_dummy2_0
assign cache_rsLdToDmaQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsLdToDmaQ_deqReq_dummy2_0$EN = EN_dma_respLd_deq ;
// submodule cache_rsLdToDmaQ_deqReq_dummy2_1
assign cache_rsLdToDmaQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsLdToDmaQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsLdToDmaQ_deqReq_dummy2_2
assign cache_rsLdToDmaQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsLdToDmaQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsLdToDmaQ_enqReq_dummy2_0
assign cache_rsLdToDmaQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsLdToDmaQ_enqReq_dummy2_0$EN =
CAN_FIRE_RL_cache_sendRsLdToDma ;
// submodule cache_rsLdToDmaQ_enqReq_dummy2_1
assign cache_rsLdToDmaQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsLdToDmaQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsLdToDmaQ_enqReq_dummy2_2
assign cache_rsLdToDmaQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsLdToDmaQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsStToDmaIndexQ
assign cache_rsStToDmaIndexQ$D_IN =
WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_sendToM ?
cache_rsStToDmaIndexQ_sendToM$D_OUT :
cache_rsStToDmaIndexQ_pipelineResp$D_OUT ;
assign cache_rsStToDmaIndexQ$ENQ =
WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_sendToM ||
WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_pipelineResp ;
assign cache_rsStToDmaIndexQ$DEQ = WILL_FIRE_RL_cache_sendRsStToDma ;
assign cache_rsStToDmaIndexQ$CLR = 1'b0 ;
// submodule cache_rsStToDmaIndexQ_pipelineResp
assign cache_rsStToDmaIndexQ_pipelineResp$D_IN =
MUX_cache_rsStToDmaIndexQ_pipelineResp$enq_1__SEL_1 ?
cache_pipeline$first[582:579] :
cache_pipeline$first[516:513] ;
assign cache_rsStToDmaIndexQ_pipelineResp$ENQ =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3129 ||
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3133) ||
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline_first__581_BIT_517_582_AND_NOT__ETC___d3820 ;
assign cache_rsStToDmaIndexQ_pipelineResp$DEQ =
CAN_FIRE_RL_cache_mergeRsStToDmaIndexQ_pipelineResp ;
assign cache_rsStToDmaIndexQ_pipelineResp$CLR = 1'b0 ;
// submodule cache_rsStToDmaIndexQ_sendToM
assign cache_rsStToDmaIndexQ_sendToM$D_IN = cache_toMInfoQ$D_OUT[5:2] ;
assign cache_rsStToDmaIndexQ_sendToM$ENQ =
WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd1 ;
assign cache_rsStToDmaIndexQ_sendToM$DEQ =
WILL_FIRE_RL_cache_mergeRsStToDmaIndexQ_sendToM ;
assign cache_rsStToDmaIndexQ_sendToM$CLR = 1'b0 ;
// submodule cache_rsStToDmaQ_clearReq_dummy2_0
assign cache_rsStToDmaQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_rsStToDmaQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_rsStToDmaQ_clearReq_dummy2_1
assign cache_rsStToDmaQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_rsStToDmaQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_rsStToDmaQ_deqReq_dummy2_0
assign cache_rsStToDmaQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsStToDmaQ_deqReq_dummy2_0$EN = EN_dma_respSt_deq ;
// submodule cache_rsStToDmaQ_deqReq_dummy2_1
assign cache_rsStToDmaQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsStToDmaQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsStToDmaQ_deqReq_dummy2_2
assign cache_rsStToDmaQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsStToDmaQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsStToDmaQ_enqReq_dummy2_0
assign cache_rsStToDmaQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsStToDmaQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_cache_sendRsStToDma ;
// submodule cache_rsStToDmaQ_enqReq_dummy2_1
assign cache_rsStToDmaQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsStToDmaQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsStToDmaQ_enqReq_dummy2_2
assign cache_rsStToDmaQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsStToDmaQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsToCIndexQ_clearReq_dummy2_0
assign cache_rsToCIndexQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_rsToCIndexQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_rsToCIndexQ_clearReq_dummy2_1
assign cache_rsToCIndexQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_rsToCIndexQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_rsToCIndexQ_deqReq_dummy2_0
assign cache_rsToCIndexQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsToCIndexQ_deqReq_dummy2_0$EN = WILL_FIRE_RL_cache_sendRsToC ;
// submodule cache_rsToCIndexQ_deqReq_dummy2_1
assign cache_rsToCIndexQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsToCIndexQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsToCIndexQ_deqReq_dummy2_2
assign cache_rsToCIndexQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsToCIndexQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_rsToCIndexQ_enqReq_dummy2_0
assign cache_rsToCIndexQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_rsToCIndexQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_cache_pipelineResp_cRq &&
(cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3146 ||
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3149) ||
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
!cache_cRqMshr$pipelineResp_getRq[16] ||
WILL_FIRE_RL_cache_pipelineResp_mRs ;
// submodule cache_rsToCIndexQ_enqReq_dummy2_1
assign cache_rsToCIndexQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_rsToCIndexQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_rsToCIndexQ_enqReq_dummy2_2
assign cache_rsToCIndexQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_rsToCIndexQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_toCQ_clearReq_dummy2_0
assign cache_toCQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_toCQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_toCQ_clearReq_dummy2_1
assign cache_toCQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_toCQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_toCQ_deqReq_dummy2_0
assign cache_toCQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_toCQ_deqReq_dummy2_0$EN = EN_to_child_toC_deq ;
// submodule cache_toCQ_deqReq_dummy2_1
assign cache_toCQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_toCQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_toCQ_deqReq_dummy2_2
assign cache_toCQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_toCQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_toCQ_enqReq_dummy2_0
assign cache_toCQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_toCQ_enqReq_dummy2_0$EN =
WILL_FIRE_RL_cache_sendRqToC || WILL_FIRE_RL_cache_sendRsToC ;
// submodule cache_toCQ_enqReq_dummy2_1
assign cache_toCQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_toCQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_toCQ_enqReq_dummy2_2
assign cache_toCQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_toCQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_toMInfoQ
assign cache_toMInfoQ$D_IN =
MUX_cache_toMInfoQ$enq_1__SEL_1 ?
MUX_cache_toMInfoQ$enq_1__VAL_1 :
MUX_cache_toMInfoQ$enq_1__VAL_2 ;
assign cache_toMInfoQ$ENQ =
MUX_cache_toMInfoQ$enq_1__SEL_1 ||
WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 ;
assign cache_toMInfoQ$DEQ =
WILL_FIRE_RL_cache_sendToM &&
(cache_toMInfoQ$D_OUT[1:0] == 2'd0 ||
cache_toMInfoQ$D_OUT[1:0] == 2'd1 ||
cache_toMInfoQ$D_OUT[1:0] == 2'd2 && cache_doLdAfterReplace) ;
assign cache_toMInfoQ$CLR = 1'b0 ;
// submodule cache_toMQ_clearReq_dummy2_0
assign cache_toMQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign cache_toMQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule cache_toMQ_clearReq_dummy2_1
assign cache_toMQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign cache_toMQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule cache_toMQ_deqReq_dummy2_0
assign cache_toMQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_toMQ_deqReq_dummy2_0$EN = EN_to_mem_toM_deq ;
// submodule cache_toMQ_deqReq_dummy2_1
assign cache_toMQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_toMQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_toMQ_deqReq_dummy2_2
assign cache_toMQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_toMQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule cache_toMQ_enqReq_dummy2_0
assign cache_toMQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign cache_toMQ_enqReq_dummy2_0$EN = cache_toMQ_enqReq_lat_0$whas ;
// submodule cache_toMQ_enqReq_dummy2_1
assign cache_toMQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign cache_toMQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule cache_toMQ_enqReq_dummy2_2
assign cache_toMQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign cache_toMQ_enqReq_dummy2_2$EN = 1'd1 ;
// submodule perfReqQ_clearReq_dummy2_0
assign perfReqQ_clearReq_dummy2_0$D_IN = 1'b0 ;
assign perfReqQ_clearReq_dummy2_0$EN = 1'b0 ;
// submodule perfReqQ_clearReq_dummy2_1
assign perfReqQ_clearReq_dummy2_1$D_IN = 1'd1 ;
assign perfReqQ_clearReq_dummy2_1$EN = 1'd1 ;
// submodule perfReqQ_deqReq_dummy2_0
assign perfReqQ_deqReq_dummy2_0$D_IN = 1'd1 ;
assign perfReqQ_deqReq_dummy2_0$EN = EN_perf_resp ;
// submodule perfReqQ_deqReq_dummy2_1
assign perfReqQ_deqReq_dummy2_1$D_IN = 1'b0 ;
assign perfReqQ_deqReq_dummy2_1$EN = 1'b0 ;
// submodule perfReqQ_deqReq_dummy2_2
assign perfReqQ_deqReq_dummy2_2$D_IN = 1'd1 ;
assign perfReqQ_deqReq_dummy2_2$EN = 1'd1 ;
// submodule perfReqQ_enqReq_dummy2_0
assign perfReqQ_enqReq_dummy2_0$D_IN = 1'd1 ;
assign perfReqQ_enqReq_dummy2_0$EN = EN_perf_req ;
// submodule perfReqQ_enqReq_dummy2_1
assign perfReqQ_enqReq_dummy2_1$D_IN = 1'b0 ;
assign perfReqQ_enqReq_dummy2_1$EN = 1'b0 ;
// submodule perfReqQ_enqReq_dummy2_2
assign perfReqQ_enqReq_dummy2_2$D_IN = 1'd1 ;
assign perfReqQ_enqReq_dummy2_2$EN = 1'd1 ;
// remaining internal signals
assign DONTCARE_CONCAT_SEL_ARR_cache_toCQ_data_0_917__ETC___d3940 =
{ 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q249,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q250,
x__h444361 } ;
assign DONTCARE_CONCAT_SEL_ARR_cache_toMQ_data_0_050__ETC___d4073 =
{ 571'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q252,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_4_ETC__q253,
x__h456804 } ;
assign IF_IF_SEL_ARR_cache_pipeline_first__581_BITS_5_ETC___d3709 =
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 ?
{ cache_pipeline$first[578:575],
cache_pipeline$first[573:526],
13'd4642 } :
{ cache_cRqMshr$pipelineResp_getSlot[64:12],
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3694,
(SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 ==
2'd0) ?
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3697 :
cache_cRqMshr$pipelineResp_getSlot[3:2],
cache_cRqMshr$pipelineResp_getSlot[1:0] } ;
assign IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d2635 =
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ?
!cache_rsToCIndexQ_full :
cache_pipeline$first[525:524] != 2'd0 ||
cache_toMInfoQ$FULL_N ;
assign IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d2699 =
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ?
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2686,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2697,
cache_cRqMshr$pipelineResp_getAddrSucc,
1'd0 } :
{ cache_pipeline$first[525:518],
1'd1,
cache_pipeline$first[582:579],
1'd0 } ;
assign IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d3397 =
{ (IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3388 ==
2'd3) ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3388 :
cache_pipeline$first[525:524],
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3396,
cache_cRqMshr$pipelineResp_getAddrSucc,
1'd0 } ;
assign IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3672 =
(cache_pipeline$first[580:579] == 2'd2 ||
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd0) ?
2'd0 :
cache_cRqMshr$pipelineResp_getSlot[11:10] ;
assign IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3684 =
(cache_pipeline$first[580:579] == 2'd1 ||
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd0) ?
2'd0 :
cache_cRqMshr$pipelineResp_getSlot[7:6] ;
assign IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3697 =
(cache_pipeline$first[580:579] == 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd0) ?
2'd0 :
cache_cRqMshr$pipelineResp_getSlot[3:2] ;
assign IF_NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_ETC___d1646 =
(!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1644) ?
2'd3 :
2'd1 ;
assign IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3054 =
(cache_cRqMshr$pipelineResp_getRq[82:81] != 2'd2 &&
!cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 :
cache_cRqMshr$pipelineResp_getRq[87:86] ;
assign IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3063 =
(cache_cRqMshr$pipelineResp_getRq[82:81] != 2'd1 &&
!cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601) ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 :
cache_cRqMshr$pipelineResp_getRq[87:86] ;
assign IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3073 =
(cache_cRqMshr$pipelineResp_getRq[82:81] != 2'd0 &&
!cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598) ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 :
cache_cRqMshr$pipelineResp_getRq[87:86] ;
assign IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2654 =
(cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
_0_OR_NOT_cache_pipeline_first__581_BITS_519_TO_ETC___d2614 :
cache_toMInfoQ$FULL_N &&
(!cache_cRqMshr$pipelineResp_getAddrSucc[4] ||
!cache_cRqRetryIndexQ_full) ;
assign IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2657 =
(cache_pipeline$first[525:524] != 2'd0 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627) ?
!cache_rsToCIndexQ_full :
cache_pipeline$first[525:524] != 2'd0 ||
cache_toMInfoQ$FULL_N ;
assign IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2999 =
(cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
{ cache_cRqMshr$pipelineResp_getRq[151:104],
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2693,
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2993 } :
cache_pipeline$first[573:0] ;
assign IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d3000 =
(cache_pipeline$first[525:524] != 2'd0 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627) ?
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2686,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2697,
cache_cRqMshr$pipelineResp_getAddrSucc,
1'd0 } :
{ cache_pipeline$first[525:518],
1'd1,
cache_pipeline$first[582:579],
1'd0 } ;
assign IF_SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSl_ETC___d3481 =
SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd0 :
(cache_pipeline$first[580:579] == 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd0) &&
(cache_pipeline$first[580:579] == 2'd1 ||
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd0) &&
(cache_pipeline$first[580:579] == 2'd2 ||
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd0) ;
assign IF_SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSl_ETC___d3482 =
SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd0 :
(cache_pipeline$first[580:579] == 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd0) &&
(cache_pipeline$first[580:579] == 2'd1 ||
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd0) &&
(cache_pipeline$first[580:579] == 2'd2 ||
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd0) ;
assign IF_SEL_ARR_NOT_cache_toCQ_data_0_917_BIT_584_9_ETC___d4000 =
CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q255 ?
DONTCARE_CONCAT_SEL_ARR_cache_toCQ_data_0_917__ETC___d3940 :
SEL_ARR_cache_toCQ_data_0_917_BITS_583_TO_520__ETC___d3998 ;
assign IF_SEL_ARR_NOT_cache_toMQ_data_0_050_BIT_640_0_ETC___d4404 =
CASE_cache_toMQ_deqP_0_NOT_cache_toMQ_data_0_B_ETC__q260 ?
DONTCARE_CONCAT_SEL_ARR_cache_toMQ_data_0_050__ETC___d4073 :
SEL_ARR_cache_toMQ_data_0_050_BITS_639_TO_576__ETC___d4402 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3454 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0 :
cache_pipeline$first[580:579] != 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0) :
cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3455 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0 :
cache_pipeline$first[580:579] != 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0) :
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3454 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3458 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0 :
cache_pipeline$first[580:579] != 2'd1 &&
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0) :
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3459 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0 :
cache_pipeline$first[580:579] != 2'd1 &&
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0) :
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3458 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3462 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0 :
cache_pipeline$first[580:579] != 2'd2 &&
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0) :
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3463 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0 :
cache_pipeline$first[580:579] != 2'd2 &&
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0) :
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3462 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 ?
IF_SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSl_ETC___d3481 :
(SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 ?
IF_SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSl_ETC___d3482 :
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd0) ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3712 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[11:10] :
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3672) :
cache_cRqMshr$pipelineResp_getSlot[11:10] ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3713 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[11:10] :
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3672) :
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3712 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3726 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[7:6] :
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3684) :
cache_cRqMshr$pipelineResp_getSlot[7:6] ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3727 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[7:6] :
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3684) :
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3726 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3741 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[3:2] :
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3697) :
cache_cRqMshr$pipelineResp_getSlot[3:2] ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3742 =
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 ?
(SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 ?
cache_cRqMshr$pipelineResp_getSlot[3:2] :
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3697) :
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3741 ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3804 =
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0) ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3814 =
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_cRqMshr$pipelineResp_getData[512] !=
(cache_cRqMshr$pipelineResp_getRq[17] ||
cache_cRqMshr$pipelineResp_getRq[18] ||
cache_cRqMshr$pipelineResp_getRq[19] ||
cache_cRqMshr$pipelineResp_getRq[20] ||
cache_cRqMshr$pipelineResp_getRq[21] ||
cache_cRqMshr$pipelineResp_getRq[22] ||
cache_cRqMshr$pipelineResp_getRq[23] ||
cache_cRqMshr$pipelineResp_getRq[24] ||
cache_cRqMshr$pipelineResp_getRq[25] ||
cache_cRqMshr$pipelineResp_getRq[26] ||
cache_cRqMshr$pipelineResp_getRq[27] ||
cache_cRqMshr$pipelineResp_getRq[28] ||
cache_cRqMshr$pipelineResp_getRq[29] ||
cache_cRqMshr$pipelineResp_getRq[30] ||
cache_cRqMshr$pipelineResp_getRq[31] ||
cache_cRqMshr$pipelineResp_getRq[32] ||
cache_cRqMshr$pipelineResp_getRq[33] ||
cache_cRqMshr$pipelineResp_getRq[34] ||
cache_cRqMshr$pipelineResp_getRq[35] ||
cache_cRqMshr$pipelineResp_getRq[36] ||
cache_cRqMshr$pipelineResp_getRq[37] ||
cache_cRqMshr$pipelineResp_getRq[38] ||
cache_cRqMshr$pipelineResp_getRq[39] ||
cache_cRqMshr$pipelineResp_getRq[40] ||
cache_cRqMshr$pipelineResp_getRq[41] ||
cache_cRqMshr$pipelineResp_getRq[42] ||
cache_cRqMshr$pipelineResp_getRq[43] ||
cache_cRqMshr$pipelineResp_getRq[44] ||
cache_cRqMshr$pipelineResp_getRq[45] ||
cache_cRqMshr$pipelineResp_getRq[46] ||
cache_cRqMshr$pipelineResp_getRq[47] ||
cache_cRqMshr$pipelineResp_getRq[48] ||
cache_cRqMshr$pipelineResp_getRq[49] ||
cache_cRqMshr$pipelineResp_getRq[50] ||
cache_cRqMshr$pipelineResp_getRq[51] ||
cache_cRqMshr$pipelineResp_getRq[52] ||
cache_cRqMshr$pipelineResp_getRq[53] ||
cache_cRqMshr$pipelineResp_getRq[54] ||
cache_cRqMshr$pipelineResp_getRq[55] ||
cache_cRqMshr$pipelineResp_getRq[56] ||
cache_cRqMshr$pipelineResp_getRq[57] ||
cache_cRqMshr$pipelineResp_getRq[58] ||
cache_cRqMshr$pipelineResp_getRq[59] ||
cache_cRqMshr$pipelineResp_getRq[60] ||
cache_cRqMshr$pipelineResp_getRq[61] ||
cache_cRqMshr$pipelineResp_getRq[62] ||
cache_cRqMshr$pipelineResp_getRq[63] ||
cache_cRqMshr$pipelineResp_getRq[64] ||
cache_cRqMshr$pipelineResp_getRq[65] ||
cache_cRqMshr$pipelineResp_getRq[66] ||
cache_cRqMshr$pipelineResp_getRq[67] ||
cache_cRqMshr$pipelineResp_getRq[68] ||
cache_cRqMshr$pipelineResp_getRq[69] ||
cache_cRqMshr$pipelineResp_getRq[70] ||
cache_cRqMshr$pipelineResp_getRq[71] ||
cache_cRqMshr$pipelineResp_getRq[72] ||
cache_cRqMshr$pipelineResp_getRq[73] ||
cache_cRqMshr$pipelineResp_getRq[74] ||
cache_cRqMshr$pipelineResp_getRq[75] ||
cache_cRqMshr$pipelineResp_getRq[76] ||
cache_cRqMshr$pipelineResp_getRq[77] ||
cache_cRqMshr$pipelineResp_getRq[78] ||
cache_cRqMshr$pipelineResp_getRq[79] ||
cache_cRqMshr$pipelineResp_getRq[80]) ;
assign IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3830 =
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0) ;
assign IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3417 =
(SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 ==
2'd0) ?
cache_pipeline$first[580:579] != 2'd1 &&
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0 ||
cache_pipeline$first[580:579] != 2'd2 &&
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0 :
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0 ;
assign IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3418 =
((SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 ==
2'd0) ?
cache_pipeline$first[580:579] != 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0 :
cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0) ||
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3417 ;
assign IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 =
(SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 ==
2'd0) ?
(cache_pipeline$first[580:579] == 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd0) &&
(cache_pipeline$first[580:579] == 2'd1 ||
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd0) &&
(cache_pipeline$first[580:579] == 2'd2 ||
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd0) :
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd0 &&
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd0 ;
assign IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3694 =
{ (SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 ==
2'd0) ?
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3672 :
cache_cRqMshr$pipelineResp_getSlot[11:10],
cache_cRqMshr$pipelineResp_getSlot[9:8],
(SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 ==
2'd0) ?
IF_IF_cache_pipeline_first__581_BITS_584_TO_58_ETC___d3684 :
cache_cRqMshr$pipelineResp_getSlot[7:6],
cache_cRqMshr$pipelineResp_getSlot[5:4] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 =
(cache_cRqMshr$pipelineResp_getRq[85:84] == 2'd1) ?
cache_cRqMshr$pipelineResp_getRq[85:84] :
2'd0 ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2626 =
((cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd1) ?
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2621 :
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601) &&
((cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd2) ?
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2624 :
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 =
((cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd0) ?
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2618 :
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598) &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2626 ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2678 =
cache_cRqMshr$pipelineResp_getRq[16] ?
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2676 :
(IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ?
cache_cRqMshr$pipelineResp_getAddrSucc :
5'd10) ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2683 =
cache_cRqMshr$pipelineResp_getRq[16] ?
((cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2676 :
5'd10) :
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d2682 ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2686 =
(cache_cRqMshr$pipelineResp_getRq[85:84] == 2'd3) ?
cache_cRqMshr$pipelineResp_getRq[85:84] :
cache_pipeline$first[525:524] ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2697 =
{ (cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd2) ?
cache_cRqMshr$pipelineResp_getRq[85:84] :
cache_pipeline$first[523:522],
(cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd1) ?
cache_cRqMshr$pipelineResp_getRq[85:84] :
cache_pipeline$first[521:520],
(cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd0) ?
cache_cRqMshr$pipelineResp_getRq[85:84] :
cache_pipeline$first[519:518] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2714 =
{ cache_cRqMshr$pipelineResp_getRq[80] ?
cache_cRqMshr$pipelineResp_getData[511:504] :
cache_pipeline$first[511:504],
cache_cRqMshr$pipelineResp_getRq[79] ?
cache_cRqMshr$pipelineResp_getData[503:496] :
cache_pipeline$first[503:496],
cache_cRqMshr$pipelineResp_getRq[78] ?
cache_cRqMshr$pipelineResp_getData[495:488] :
cache_pipeline$first[495:488] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2723 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2714,
cache_cRqMshr$pipelineResp_getRq[77] ?
cache_cRqMshr$pipelineResp_getData[487:480] :
cache_pipeline$first[487:480],
cache_cRqMshr$pipelineResp_getRq[76] ?
cache_cRqMshr$pipelineResp_getData[479:472] :
cache_pipeline$first[479:472] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2732 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2723,
cache_cRqMshr$pipelineResp_getRq[75] ?
cache_cRqMshr$pipelineResp_getData[471:464] :
cache_pipeline$first[471:464],
cache_cRqMshr$pipelineResp_getRq[74] ?
cache_cRqMshr$pipelineResp_getData[463:456] :
cache_pipeline$first[463:456] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2749 =
{ cache_cRqMshr$pipelineResp_getRq[72] ?
cache_cRqMshr$pipelineResp_getData[447:440] :
cache_pipeline$first[447:440],
cache_cRqMshr$pipelineResp_getRq[71] ?
cache_cRqMshr$pipelineResp_getData[439:432] :
cache_pipeline$first[439:432],
cache_cRqMshr$pipelineResp_getRq[70] ?
cache_cRqMshr$pipelineResp_getData[431:424] :
cache_pipeline$first[431:424] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2758 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2749,
cache_cRqMshr$pipelineResp_getRq[69] ?
cache_cRqMshr$pipelineResp_getData[423:416] :
cache_pipeline$first[423:416],
cache_cRqMshr$pipelineResp_getRq[68] ?
cache_cRqMshr$pipelineResp_getData[415:408] :
cache_pipeline$first[415:408] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2767 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2758,
cache_cRqMshr$pipelineResp_getRq[67] ?
cache_cRqMshr$pipelineResp_getData[407:400] :
cache_pipeline$first[407:400],
cache_cRqMshr$pipelineResp_getRq[66] ?
cache_cRqMshr$pipelineResp_getData[399:392] :
cache_pipeline$first[399:392] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2772 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2732,
cache_cRqMshr$pipelineResp_getRq[73] ?
cache_cRqMshr$pipelineResp_getData[455:448] :
cache_pipeline$first[455:448],
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2767,
cache_cRqMshr$pipelineResp_getRq[65] ?
cache_cRqMshr$pipelineResp_getData[391:384] :
cache_pipeline$first[391:384] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2790 =
{ cache_cRqMshr$pipelineResp_getRq[64] ?
cache_cRqMshr$pipelineResp_getData[383:376] :
cache_pipeline$first[383:376],
cache_cRqMshr$pipelineResp_getRq[63] ?
cache_cRqMshr$pipelineResp_getData[375:368] :
cache_pipeline$first[375:368],
cache_cRqMshr$pipelineResp_getRq[62] ?
cache_cRqMshr$pipelineResp_getData[367:360] :
cache_pipeline$first[367:360],
cache_cRqMshr$pipelineResp_getRq[61] ?
cache_cRqMshr$pipelineResp_getData[359:352] :
cache_pipeline$first[359:352] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2799 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2790,
cache_cRqMshr$pipelineResp_getRq[60] ?
cache_cRqMshr$pipelineResp_getData[351:344] :
cache_pipeline$first[351:344],
cache_cRqMshr$pipelineResp_getRq[59] ?
cache_cRqMshr$pipelineResp_getData[343:336] :
cache_pipeline$first[343:336] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2808 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2799,
cache_cRqMshr$pipelineResp_getRq[58] ?
cache_cRqMshr$pipelineResp_getData[335:328] :
cache_pipeline$first[335:328],
cache_cRqMshr$pipelineResp_getRq[57] ?
cache_cRqMshr$pipelineResp_getData[327:320] :
cache_pipeline$first[327:320] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2821 =
{ cache_cRqMshr$pipelineResp_getRq[56] ?
cache_cRqMshr$pipelineResp_getData[319:312] :
cache_pipeline$first[319:312],
cache_cRqMshr$pipelineResp_getRq[55] ?
cache_cRqMshr$pipelineResp_getData[311:304] :
cache_pipeline$first[311:304],
cache_cRqMshr$pipelineResp_getRq[54] ?
cache_cRqMshr$pipelineResp_getData[303:296] :
cache_pipeline$first[303:296] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2830 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2821,
cache_cRqMshr$pipelineResp_getRq[53] ?
cache_cRqMshr$pipelineResp_getData[295:288] :
cache_pipeline$first[295:288],
cache_cRqMshr$pipelineResp_getRq[52] ?
cache_cRqMshr$pipelineResp_getData[287:280] :
cache_pipeline$first[287:280] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2839 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2830,
cache_cRqMshr$pipelineResp_getRq[51] ?
cache_cRqMshr$pipelineResp_getData[279:272] :
cache_pipeline$first[279:272],
cache_cRqMshr$pipelineResp_getRq[50] ?
cache_cRqMshr$pipelineResp_getData[271:264] :
cache_pipeline$first[271:264] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2844 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2772,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2808,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2839,
cache_cRqMshr$pipelineResp_getRq[49] ?
cache_cRqMshr$pipelineResp_getData[263:256] :
cache_pipeline$first[263:256] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2862 =
{ cache_cRqMshr$pipelineResp_getRq[48] ?
cache_cRqMshr$pipelineResp_getData[255:248] :
cache_pipeline$first[255:248],
cache_cRqMshr$pipelineResp_getRq[47] ?
cache_cRqMshr$pipelineResp_getData[247:240] :
cache_pipeline$first[247:240],
cache_cRqMshr$pipelineResp_getRq[46] ?
cache_cRqMshr$pipelineResp_getData[239:232] :
cache_pipeline$first[239:232],
cache_cRqMshr$pipelineResp_getRq[45] ?
cache_cRqMshr$pipelineResp_getData[231:224] :
cache_pipeline$first[231:224] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2871 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2862,
cache_cRqMshr$pipelineResp_getRq[44] ?
cache_cRqMshr$pipelineResp_getData[223:216] :
cache_pipeline$first[223:216],
cache_cRqMshr$pipelineResp_getRq[43] ?
cache_cRqMshr$pipelineResp_getData[215:208] :
cache_pipeline$first[215:208] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2880 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2871,
cache_cRqMshr$pipelineResp_getRq[42] ?
cache_cRqMshr$pipelineResp_getData[207:200] :
cache_pipeline$first[207:200],
cache_cRqMshr$pipelineResp_getRq[41] ?
cache_cRqMshr$pipelineResp_getData[199:192] :
cache_pipeline$first[199:192] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2893 =
{ cache_cRqMshr$pipelineResp_getRq[40] ?
cache_cRqMshr$pipelineResp_getData[191:184] :
cache_pipeline$first[191:184],
cache_cRqMshr$pipelineResp_getRq[39] ?
cache_cRqMshr$pipelineResp_getData[183:176] :
cache_pipeline$first[183:176],
cache_cRqMshr$pipelineResp_getRq[38] ?
cache_cRqMshr$pipelineResp_getData[175:168] :
cache_pipeline$first[175:168] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2902 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2893,
cache_cRqMshr$pipelineResp_getRq[37] ?
cache_cRqMshr$pipelineResp_getData[167:160] :
cache_pipeline$first[167:160],
cache_cRqMshr$pipelineResp_getRq[36] ?
cache_cRqMshr$pipelineResp_getData[159:152] :
cache_pipeline$first[159:152] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2911 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2902,
cache_cRqMshr$pipelineResp_getRq[35] ?
cache_cRqMshr$pipelineResp_getData[151:144] :
cache_pipeline$first[151:144],
cache_cRqMshr$pipelineResp_getRq[34] ?
cache_cRqMshr$pipelineResp_getData[143:136] :
cache_pipeline$first[143:136] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2916 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2844,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2880,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2911,
cache_cRqMshr$pipelineResp_getRq[33] ?
cache_cRqMshr$pipelineResp_getData[135:128] :
cache_pipeline$first[135:128] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2934 =
{ cache_cRqMshr$pipelineResp_getRq[32] ?
cache_cRqMshr$pipelineResp_getData[127:120] :
cache_pipeline$first[127:120],
cache_cRqMshr$pipelineResp_getRq[31] ?
cache_cRqMshr$pipelineResp_getData[119:112] :
cache_pipeline$first[119:112],
cache_cRqMshr$pipelineResp_getRq[30] ?
cache_cRqMshr$pipelineResp_getData[111:104] :
cache_pipeline$first[111:104],
cache_cRqMshr$pipelineResp_getRq[29] ?
cache_cRqMshr$pipelineResp_getData[103:96] :
cache_pipeline$first[103:96] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2943 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2934,
cache_cRqMshr$pipelineResp_getRq[28] ?
cache_cRqMshr$pipelineResp_getData[95:88] :
cache_pipeline$first[95:88],
cache_cRqMshr$pipelineResp_getRq[27] ?
cache_cRqMshr$pipelineResp_getData[87:80] :
cache_pipeline$first[87:80] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2952 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2943,
cache_cRqMshr$pipelineResp_getRq[26] ?
cache_cRqMshr$pipelineResp_getData[79:72] :
cache_pipeline$first[79:72],
cache_cRqMshr$pipelineResp_getRq[25] ?
cache_cRqMshr$pipelineResp_getData[71:64] :
cache_pipeline$first[71:64] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2968 =
{ cache_cRqMshr$pipelineResp_getRq[24] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[63:56] :
cache_pipeline$first[63:56],
cache_cRqMshr$pipelineResp_getRq[23] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[55:48] :
cache_pipeline$first[55:48],
cache_cRqMshr$pipelineResp_getRq[22] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[47:40] :
cache_pipeline$first[47:40] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2977 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2968,
cache_cRqMshr$pipelineResp_getRq[21] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[39:32] :
cache_pipeline$first[39:32],
cache_cRqMshr$pipelineResp_getRq[20] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[31:24] :
cache_pipeline$first[31:24] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2986 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2977,
cache_cRqMshr$pipelineResp_getRq[19] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[23:16] :
cache_pipeline$first[23:16],
cache_cRqMshr$pipelineResp_getRq[18] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[15:8] :
cache_pipeline$first[15:8] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2991 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2916,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2952,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2986,
cache_cRqMshr$pipelineResp_getRq[17] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[7:0] :
cache_pipeline$first[7:0] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3014 =
cache_cRqMshr$pipelineResp_getRq[16] ?
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 :
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3022 =
cache_cRqMshr$pipelineResp_getRq[16] ?
NOT_cache_pipeline_first__581_BITS_525_TO_524__ETC___d3019 :
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline$first[525:524] != 2'd0 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3027 =
cache_cRqMshr$pipelineResp_getRq[16] ?
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d3025 :
(IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ?
3'd4 :
3'd3) ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3033 =
cache_cRqMshr$pipelineResp_getRq[16] ?
((cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d3025 :
3'd4) :
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3032 ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3048 =
(cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd2) ?
(cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2624 ?
2'd0 :
2'd2) :
(cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 ?
2'd0 :
2'd1) ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3057 =
(cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd1) ?
(cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2621 ?
2'd0 :
2'd2) :
(cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 ?
2'd0 :
2'd1) ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3067 =
(cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd0) ?
(cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2618 ?
2'd0 :
2'd2) :
(cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 ?
2'd0 :
2'd1) ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3078 =
cache_cRqMshr$pipelineResp_getRq[16] ?
{ cache_pipeline$first[578:575],
48'hAAAAAAAAAAAA,
_0_CONCAT_IF_cache_pipeline_first__581_BITS_523_ETC___d3043 } :
{ cache_pipeline$first[578:575],
48'hAAAAAAAAAAAA,
cache_pipeline$first[525:524] == 2'd0,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3048,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3054,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3057,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3063,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3067,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3073 } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3096 =
cache_cRqMshr$pipelineResp_getRq[16] ?
{ cache_pipeline$first[578:575],
48'hAAAAAAAAAAAA,
_0_CONCAT_IF_cache_pipeline_first__581_BITS_523_ETC___d3043 } :
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3095 ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3155 =
((cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd1) ?
!cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2621 :
!cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601) ||
((cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd2) ?
!cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2624 :
!cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3156 =
((cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd0) ?
!cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2618 :
!cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598) ||
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3155 ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3173 =
cache_cRqMshr$pipelineResp_getRq[16] ?
((cache_cRqMshr$pipelineResp_getRq[85:84] == 2'd3) ?
2'd1 :
2'd0) :
((cache_pipeline$first[525:524] == 2'd0 ||
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
2'd0 :
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3171) ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3388 =
(cache_cRqMshr$pipelineResp_getRq[85:84] == 2'd1 &&
cache_cRqMshr$pipelineResp_getRq[83] &&
cache_pipeline$first[519:518] == 2'd0 &&
cache_pipeline$first[521:520] == 2'd0 &&
cache_pipeline$first[523:522] == 2'd0) ?
2'd2 :
cache_cRqMshr$pipelineResp_getRq[85:84] ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3396 =
{ (cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd2) ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3388 :
cache_pipeline$first[523:522],
(cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd1) ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3388 :
cache_pipeline$first[521:520],
(cache_cRqMshr$pipelineResp_getRq[82:81] == 2'd0) ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3388 :
cache_pipeline$first[519:518] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3493 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2686,
cache_cRqMshr$pipelineResp_getRq[16] ?
cache_pipeline$first[523:518] :
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2697,
cache_cRqMshr$pipelineResp_getAddrSucc,
1'd0 } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3506 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2714,
cache_cRqMshr$pipelineResp_getRq[77] ?
cache_cRqMshr$pipelineResp_getData[487:480] :
cache_pipeline$first[487:480],
cache_cRqMshr$pipelineResp_getRq[76] ?
cache_cRqMshr$pipelineResp_getData[479:472] :
cache_pipeline$first[479:472] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3511 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3506,
cache_cRqMshr$pipelineResp_getRq[75] ?
cache_cRqMshr$pipelineResp_getData[471:464] :
cache_pipeline$first[471:464],
cache_cRqMshr$pipelineResp_getRq[74] ?
cache_cRqMshr$pipelineResp_getData[463:456] :
cache_pipeline$first[463:456] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3525 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2749,
cache_cRqMshr$pipelineResp_getRq[69] ?
cache_cRqMshr$pipelineResp_getData[423:416] :
cache_pipeline$first[423:416],
cache_cRqMshr$pipelineResp_getRq[68] ?
cache_cRqMshr$pipelineResp_getData[415:408] :
cache_pipeline$first[415:408] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3530 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3525,
cache_cRqMshr$pipelineResp_getRq[67] ?
cache_cRqMshr$pipelineResp_getData[407:400] :
cache_pipeline$first[407:400],
cache_cRqMshr$pipelineResp_getRq[66] ?
cache_cRqMshr$pipelineResp_getData[399:392] :
cache_pipeline$first[399:392] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3533 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3511,
cache_cRqMshr$pipelineResp_getRq[73] ?
cache_cRqMshr$pipelineResp_getData[455:448] :
cache_pipeline$first[455:448],
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3530,
cache_cRqMshr$pipelineResp_getRq[65] ?
cache_cRqMshr$pipelineResp_getData[391:384] :
cache_pipeline$first[391:384] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3548 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2790,
cache_cRqMshr$pipelineResp_getRq[60] ?
cache_cRqMshr$pipelineResp_getData[351:344] :
cache_pipeline$first[351:344],
cache_cRqMshr$pipelineResp_getRq[59] ?
cache_cRqMshr$pipelineResp_getData[343:336] :
cache_pipeline$first[343:336] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3553 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3548,
cache_cRqMshr$pipelineResp_getRq[58] ?
cache_cRqMshr$pipelineResp_getData[335:328] :
cache_pipeline$first[335:328],
cache_cRqMshr$pipelineResp_getRq[57] ?
cache_cRqMshr$pipelineResp_getData[327:320] :
cache_pipeline$first[327:320] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3565 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2821,
cache_cRqMshr$pipelineResp_getRq[53] ?
cache_cRqMshr$pipelineResp_getData[295:288] :
cache_pipeline$first[295:288],
cache_cRqMshr$pipelineResp_getRq[52] ?
cache_cRqMshr$pipelineResp_getData[287:280] :
cache_pipeline$first[287:280] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3570 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3565,
cache_cRqMshr$pipelineResp_getRq[51] ?
cache_cRqMshr$pipelineResp_getData[279:272] :
cache_pipeline$first[279:272],
cache_cRqMshr$pipelineResp_getRq[50] ?
cache_cRqMshr$pipelineResp_getData[271:264] :
cache_pipeline$first[271:264] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3573 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3533,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3553,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3570,
cache_cRqMshr$pipelineResp_getRq[49] ?
cache_cRqMshr$pipelineResp_getData[263:256] :
cache_pipeline$first[263:256] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3588 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2862,
cache_cRqMshr$pipelineResp_getRq[44] ?
cache_cRqMshr$pipelineResp_getData[223:216] :
cache_pipeline$first[223:216],
cache_cRqMshr$pipelineResp_getRq[43] ?
cache_cRqMshr$pipelineResp_getData[215:208] :
cache_pipeline$first[215:208] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3593 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3588,
cache_cRqMshr$pipelineResp_getRq[42] ?
cache_cRqMshr$pipelineResp_getData[207:200] :
cache_pipeline$first[207:200],
cache_cRqMshr$pipelineResp_getRq[41] ?
cache_cRqMshr$pipelineResp_getData[199:192] :
cache_pipeline$first[199:192] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3605 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2893,
cache_cRqMshr$pipelineResp_getRq[37] ?
cache_cRqMshr$pipelineResp_getData[167:160] :
cache_pipeline$first[167:160],
cache_cRqMshr$pipelineResp_getRq[36] ?
cache_cRqMshr$pipelineResp_getData[159:152] :
cache_pipeline$first[159:152] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3610 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3605,
cache_cRqMshr$pipelineResp_getRq[35] ?
cache_cRqMshr$pipelineResp_getData[151:144] :
cache_pipeline$first[151:144],
cache_cRqMshr$pipelineResp_getRq[34] ?
cache_cRqMshr$pipelineResp_getData[143:136] :
cache_pipeline$first[143:136] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3613 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3573,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3593,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3610,
cache_cRqMshr$pipelineResp_getRq[33] ?
cache_cRqMshr$pipelineResp_getData[135:128] :
cache_pipeline$first[135:128] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3628 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2934,
cache_cRqMshr$pipelineResp_getRq[28] ?
cache_cRqMshr$pipelineResp_getData[95:88] :
cache_pipeline$first[95:88],
cache_cRqMshr$pipelineResp_getRq[27] ?
cache_cRqMshr$pipelineResp_getData[87:80] :
cache_pipeline$first[87:80] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3633 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3628,
cache_cRqMshr$pipelineResp_getRq[26] ?
cache_cRqMshr$pipelineResp_getData[79:72] :
cache_pipeline$first[79:72],
cache_cRqMshr$pipelineResp_getRq[25] ?
cache_cRqMshr$pipelineResp_getData[71:64] :
cache_pipeline$first[71:64] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3648 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2968,
cache_cRqMshr$pipelineResp_getRq[21] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[39:32] :
cache_pipeline$first[39:32],
cache_cRqMshr$pipelineResp_getRq[20] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[31:24] :
cache_pipeline$first[31:24] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3653 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3648,
cache_cRqMshr$pipelineResp_getRq[19] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[23:16] :
cache_pipeline$first[23:16],
cache_cRqMshr$pipelineResp_getRq[18] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[15:8] :
cache_pipeline$first[15:8] } ;
assign IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3656 =
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3613,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3633,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3653,
cache_cRqMshr$pipelineResp_getRq[17] ?
cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78[7:0] :
cache_pipeline$first[7:0] } ;
assign IF_cache_cRqMshr_pipelineResp_searchEndOfChain_ETC___d3012 =
(cache_cRqMshr$pipelineResp_searchEndOfChain[4] &&
cache_cRqMshr$pipelineResp_getState == 3'd1) ?
cache_pipeline$first[573:0] :
(cache_cRqMshr$pipelineResp_getRq[16] ?
IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2999 :
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3010) ;
assign IF_cache_cRqRetryIndexQ_deqReq_dummy2_2_read___ETC___d854 =
_theResult_____2__h234513 == v__h232953 ;
assign IF_cache_cRqRetryIndexQ_deqReq_lat_1_whas__11__ETC___d817 =
WILL_FIRE_RL_cache_cRqTransfer_retry ||
cache_cRqRetryIndexQ_deqReq_rl ;
assign IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 =
cache_cRqRetryIndexQ_enqReq_lat_0$whas ?
cache_cRqRetryIndexQ_enqReq_lat_0$wget[4] :
cache_cRqRetryIndexQ_enqReq_rl[4] ;
assign IF_cache_doLdAfterReplace_007_THEN_2_CONCAT_DO_ETC___d2016 =
cache_doLdAfterReplace ?
{ 573'h12AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
cache_cRqMshr$sendToM_getRq[151:88],
1'd1,
cache_toMInfoQ$D_OUT[5:2] } :
{ 2'd3,
addr__h288271,
64'hFFFFFFFFFFFFFFFF,
cache_cRqMshr$sendToM_getData[511:0] } ;
assign IF_cache_pipeline_RDY_first__579_AND_cache_cRq_ETC___d2613 =
(cache_pipeline$RDY_first &&
cache_cRqMshr$pipelineResp_getRq[85:84] == 2'd3) ?
cache_rsStToDmaIndexQ_pipelineResp$FULL_N :
cache_rsLdToDmaIndexQ_pipelineResp$FULL_N ;
assign IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2676 =
(cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) ?
cache_cRqMshr$pipelineResp_getAddrSucc :
5'd10 ;
assign IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2693 =
(cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) ?
{ IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2686,
cache_pipeline$first[523:518],
cache_cRqMshr$pipelineResp_getAddrSucc,
1'd0 } :
{ cache_pipeline$first[525:518],
1'd1,
cache_pipeline$first[582:579],
1'd0 } ;
assign IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2993 =
(cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2991 :
cache_pipeline$first[511:0] ;
assign IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d3025 =
(cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) ?
3'd4 :
3'd3 ;
assign IF_cache_pipeline_first__581_BITS_523_TO_522_6_ETC___d3041 =
{ cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 ?
4'd2 :
{ 2'd1,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 },
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 ?
4'd2 :
{ 2'd1,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 } } ;
assign IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d2667 =
(cache_pipeline$first[525:524] == 2'd0 ||
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2657 :
cache_pipeline$first[519:518] != 2'd0 ||
cache_pipeline$first[521:520] != 2'd0 ||
cache_pipeline$first[523:522] != 2'd0 ||
cache_toMInfoQ$FULL_N ;
assign IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d2682 =
(cache_pipeline$first[525:524] == 2'd0 ||
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
((cache_pipeline$first[525:524] != 2'd0 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627) ?
cache_cRqMshr$pipelineResp_getAddrSucc :
5'd10) :
5'd10 ;
assign IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3010 =
(cache_pipeline$first[525:524] == 2'd0 ||
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
{ cache_cRqMshr$pipelineResp_getRq[151:104],
IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d3000,
cache_pipeline$first[511:0] } :
((cache_pipeline$first[519:518] == 2'd0 &&
cache_pipeline$first[521:520] == 2'd0 &&
cache_pipeline$first[523:522] == 2'd0) ?
{ cache_cRqMshr$pipelineResp_getRq[151:104],
9'd1,
cache_pipeline$first[582:579],
513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } :
{ cache_pipeline$first[573:518],
1'd1,
cache_pipeline$first[582:579],
1'd1,
cache_pipeline$first[511:0] }) ;
assign IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3032 =
(cache_pipeline$first[525:524] == 2'd0 ||
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
((cache_pipeline$first[525:524] != 2'd0 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627) ?
3'd4 :
3'd3) :
((cache_pipeline$first[519:518] == 2'd0 &&
cache_pipeline$first[521:520] == 2'd0 &&
cache_pipeline$first[523:522] == 2'd0) ?
3'd3 :
3'd2) ;
assign IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3095 =
(cache_pipeline$first[525:524] == 2'd0 ||
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
{ cache_pipeline$first[578:575],
48'hAAAAAAAAAAAA,
cache_pipeline$first[525:524] == 2'd0,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3048,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3054,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3057,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3063,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3067,
IF_NOT_cache_cRqMshr_pipelineResp_getRq_IF_cac_ETC___d3073 } :
{ cache_pipeline$first[578:575],
cache_pipeline$first[573:526],
cache_pipeline$first[519:518] == 2'd0 &&
cache_pipeline$first[521:520] == 2'd0 &&
cache_pipeline$first[523:522] == 2'd0,
(cache_pipeline$first[519:518] == 2'd0 &&
cache_pipeline$first[521:520] == 2'd0 &&
cache_pipeline$first[523:522] == 2'd0) ?
12'd546 :
{ (cache_pipeline$first[523:522] == 2'd0) ?
cache_pipeline$first[523:520] :
4'd4,
(cache_pipeline$first[521:520] == 2'd0) ?
cache_pipeline$first[521:518] :
4'd4,
(cache_pipeline$first[519:518] == 2'd0) ?
cache_pipeline$first[519:516] :
4'd4 } } ;
assign IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d3171 =
(cache_pipeline$first[525:524] == 2'd3) ? 2'd2 : 2'd0 ;
assign IF_cache_pipeline_first__581_BIT_512_308_THEN__ETC___d3486 =
cache_pipeline$first[512] ?
5'd10 :
(IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 ?
cache_cRqMshr$pipelineResp_getAddrSucc :
5'd10) ;
assign IF_cache_pipeline_first__581_BIT_512_308_THEN__ETC___d3660 =
cache_pipeline$first[512] ?
(IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 ?
{ cache_cRqMshr$pipelineResp_getRq[151:104],
9'd1,
cache_pipeline$first[516:513],
513'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } :
cache_pipeline$first[573:0]) :
(IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 ?
cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3658 :
cache_pipeline$first[573:0]) ;
assign IF_cache_pipeline_first__581_BIT_517_582_THEN__ETC___d3124 =
cache_pipeline$first[517] ?
cache_cRqMshr$pipelineResp_getRq[16] ||
CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79 ==
2'd0 :
cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3123 ;
assign IF_cache_rqFromCQ_deqReq_dummy2_2_read__7_AND__ETC___d55 =
_theResult_____2__h7215 == v__h6037 ;
assign IF_cache_rqFromCQ_deqReq_lat_1_whas__3_THEN_ca_ETC___d19 =
WILL_FIRE_RL_cache_cRqTransfer_new_child ||
cache_rqFromCQ_deqReq_rl ;
assign IF_cache_rqFromCQ_enqReq_lat_1_whas_THEN_cache_ETC___d39 =
EN_to_child_rqFromC_enq ?
cache_rqFromCQ_enqReq_lat_0$wget[74] :
cache_rqFromCQ_enqReq_rl[74] ;
assign IF_cache_rqFromDmaQ_deqReq_dummy2_2_read__53_A_ETC___d361 =
_theResult_____2__h119142 == v__h72082 ;
assign IF_cache_rqFromDmaQ_deqReq_lat_1_whas__19_THEN_ETC___d325 =
WILL_FIRE_RL_cache_cRqTransfer_new_dma ||
cache_rqFromDmaQ_deqReq_rl ;
assign IF_cache_rqFromDmaQ_enqReq_lat_1_whas__09_THEN_ETC___d345 =
EN_dma_memReq_enq ?
cache_rqFromDmaQ_enqReq_lat_0$wget[656] :
cache_rqFromDmaQ_enqReq_rl[656] ;
assign IF_cache_rsFromCQ_deqReq_dummy2_2_read__39_AND_ETC___d147 =
_theResult_____2__h22297 == v__h16641 ;
assign IF_cache_rsFromCQ_deqReq_lat_1_whas__05_THEN_c_ETC___d111 =
WILL_FIRE_RL_cache_cRsTransfer || cache_rsFromCQ_deqReq_rl ;
assign IF_cache_rsFromCQ_enqReq_lat_1_whas__5_THEN_ca_ETC___d131 =
EN_to_child_rsFromC_enq ?
cache_rsFromCQ_enqReq_lat_0$wget[581] :
cache_rsFromCQ_enqReq_rl[581] ;
assign IF_cache_rsFromMQ_deqReq_dummy2_2_read__54_AND_ETC___d762 =
_theResult_____2__h225016 == v__h218716 ;
assign IF_cache_rsFromMQ_deqReq_lat_1_whas__20_THEN_c_ETC___d726 =
cache_rsFromMQ_deqReq_lat_0$whas || cache_rsFromMQ_deqReq_rl ;
assign IF_cache_rsFromMQ_enqReq_lat_1_whas__10_THEN_c_ETC___d746 =
EN_to_mem_rsFromM_enq ?
cache_rsFromMQ_enqReq_lat_0$wget[517] :
cache_rsFromMQ_enqReq_rl[517] ;
assign IF_cache_rsLdToDmaQ_deqReq_dummy2_2_read__44_A_ETC___d452 =
_theResult_____2__h135235 == v__h129259 ;
assign IF_cache_rsLdToDmaQ_deqReq_lat_1_whas__10_THEN_ETC___d416 =
EN_dma_respLd_deq || cache_rsLdToDmaQ_deqReq_rl ;
assign IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__00_THEN_ETC___d436 =
CAN_FIRE_RL_cache_sendRsLdToDma ?
cache_rsLdToDmaQ_enqReq_lat_0$wget[528] :
cache_rsLdToDmaQ_enqReq_rl[528] ;
assign IF_cache_rsStToDmaQ_deqReq_dummy2_2_read__35_A_ETC___d543 =
_theResult_____2__h142737 == v__h142239 ;
assign IF_cache_rsStToDmaQ_deqReq_lat_1_whas__01_THEN_ETC___d507 =
EN_dma_respSt_deq || cache_rsStToDmaQ_deqReq_rl ;
assign IF_cache_rsStToDmaQ_enqReq_lat_1_whas__91_THEN_ETC___d527 =
WILL_FIRE_RL_cache_sendRsStToDma ?
cache_rsStToDmaQ_enqReq_lat_0$wget[16] :
cache_rsStToDmaQ_enqReq_rl[16] ;
assign IF_cache_rsToCIndexQ_deqReq_dummy2_2_read__64__ETC___d977 =
_theResult_____2__h245988 == v__h242396 ;
assign IF_cache_rsToCIndexQ_deqReq_lat_1_whas__34_THE_ETC___d940 =
WILL_FIRE_RL_cache_sendRsToC || cache_rsToCIndexQ_deqReq_rl ;
assign IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 =
cache_rsToCIndexQ_enqReq_lat_0$whas ?
cache_rsToCIndexQ_enqReq_lat_0$wget[6] :
cache_rsToCIndexQ_enqReq_rl[6] ;
assign IF_cache_toCQ_deqReq_dummy2_2_read__61_AND_IF__ETC___d269 =
_theResult_____2__h37990 == v__h31944 ;
assign IF_cache_toCQ_deqReq_lat_1_whas__32_THEN_cache_ETC___d238 =
EN_to_child_toC_deq || cache_toCQ_deqReq_rl ;
assign IF_cache_toCQ_enqReq_dummy2_2_read__53_AND_IF__ETC___d302 =
(cache_toCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toCQ_enqReq_lat_1_whas__87_THEN_cache_ETC___d196 &&
(cache_toCQ_enqReq_lat_0$whas ?
!cache_toCQ_enqReq_lat_0$wget[584] :
!cache_toCQ_enqReq_rl[584])) ?
{ 516'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
cache_toCQ_enqReq_lat_0$whas ?
cache_toCQ_enqReq_lat_0$wget[67:0] :
cache_toCQ_enqReq_rl[67:0] } :
(cache_toCQ_enqReq_lat_0$whas ?
cache_toCQ_enqReq_lat_0$wget[583:0] :
cache_toCQ_enqReq_rl[583:0]) ;
assign IF_cache_toCQ_enqReq_lat_1_whas__87_THEN_cache_ETC___d196 =
cache_toCQ_enqReq_lat_0$whas ?
cache_toCQ_enqReq_lat_0$wget[585] :
cache_toCQ_enqReq_rl[585] ;
assign IF_cache_toMQ_deqReq_dummy2_2_read__62_AND_IF__ETC___d670 =
_theResult_____2__h208521 == v__h168573 ;
assign IF_cache_toMQ_deqReq_lat_1_whas__33_THEN_cache_ETC___d639 =
EN_to_mem_toM_deq || cache_toMQ_deqReq_rl ;
assign IF_cache_toMQ_enqReq_dummy2_2_read__54_AND_IF__ETC___d703 =
(cache_toMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toMQ_enqReq_lat_1_whas__88_THEN_cache_ETC___d597 &&
(cache_toMQ_enqReq_lat_0$whas ?
!cache_toMQ_enqReq_lat_0$wget[640] :
!cache_toMQ_enqReq_rl[640])) ?
{ 571'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA,
cache_toMQ_enqReq_lat_0$whas ?
cache_toMQ_enqReq_lat_0$wget[68:0] :
cache_toMQ_enqReq_rl[68:0] } :
(cache_toMQ_enqReq_lat_0$whas ?
cache_toMQ_enqReq_lat_0$wget[639:0] :
cache_toMQ_enqReq_rl[639:0]) ;
assign IF_cache_toMQ_enqReq_lat_1_whas__88_THEN_cache_ETC___d597 =
cache_toMQ_enqReq_lat_0$whas ?
cache_toMQ_enqReq_lat_0$wget[641] :
cache_toMQ_enqReq_rl[641] ;
assign IF_perfReqQ_enqReq_lat_1_whas__839_THEN_perfRe_ETC___d3875 =
EN_perf_req ?
perfReqQ_enqReq_lat_0$wget[4] :
perfReqQ_enqReq_rl[4] ;
assign NOT_IF_cache_pipeline_first__581_BITS_584_TO_5_ETC___d3191 =
cache_pipeline$first[582:579] != pipeOutCRqIdx__h314276 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1584 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q5 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1586 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1584 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1588 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1586 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1590 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1588 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1592 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1590 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1594 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1592 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1596 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1594 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1598 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1596 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1600 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1598 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1602 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1600 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1604 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1602 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1606 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1604 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1608 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1606 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1610 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1608 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1612 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1610 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1614 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1612 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1616 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1614 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1618 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1616 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1620 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1618 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1622 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1620 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1624 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1622 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1626 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1624 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1628 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1626 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1630 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1628 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1632 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1630 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1634 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1632 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1636 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1634 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1638 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1636 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1640 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1638 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1642 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1640 ;
assign NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1644 =
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 ||
!CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 ||
NOT_SEL_ARR_NOT_cache_rqFromDmaQ_data_0_129_BI_ETC___d1642 ;
assign NOT_SEL_ARR_cache_cRqMshr_sendRqToC_getSlot_IF_ETC___d2508 =
!CASE_child13067_0_cache_cRqMshrsendRqToC_getS_ETC__q254 ;
assign NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3264 =
(cache_cRqMshr$pipelineResp_getRq[17] ||
cache_cRqMshr$pipelineResp_getRq[18] ||
cache_cRqMshr$pipelineResp_getRq[19] ||
cache_cRqMshr$pipelineResp_getRq[20] ||
cache_cRqMshr$pipelineResp_getRq[21] ||
cache_cRqMshr$pipelineResp_getRq[22] ||
cache_cRqMshr$pipelineResp_getRq[23] ||
cache_cRqMshr$pipelineResp_getRq[24] ||
cache_cRqMshr$pipelineResp_getRq[25] ||
cache_cRqMshr$pipelineResp_getRq[26] ||
cache_cRqMshr$pipelineResp_getRq[27] ||
cache_cRqMshr$pipelineResp_getRq[28] ||
cache_cRqMshr$pipelineResp_getRq[29] ||
cache_cRqMshr$pipelineResp_getRq[30] ||
cache_cRqMshr$pipelineResp_getRq[31] ||
cache_cRqMshr$pipelineResp_getRq[32] ||
cache_cRqMshr$pipelineResp_getRq[33] ||
cache_cRqMshr$pipelineResp_getRq[34] ||
cache_cRqMshr$pipelineResp_getRq[35] ||
cache_cRqMshr$pipelineResp_getRq[36] ||
cache_cRqMshr$pipelineResp_getRq[37] ||
cache_cRqMshr$pipelineResp_getRq[38] ||
cache_cRqMshr$pipelineResp_getRq[39] ||
cache_cRqMshr$pipelineResp_getRq[40] ||
cache_cRqMshr$pipelineResp_getRq[41] ||
cache_cRqMshr$pipelineResp_getRq[42] ||
cache_cRqMshr$pipelineResp_getRq[43] ||
cache_cRqMshr$pipelineResp_getRq[44] ||
cache_cRqMshr$pipelineResp_getRq[45] ||
cache_cRqMshr$pipelineResp_getRq[46] ||
cache_cRqMshr$pipelineResp_getRq[47] ||
cache_cRqMshr$pipelineResp_getRq[48] ||
cache_cRqMshr$pipelineResp_getRq[49] ||
cache_cRqMshr$pipelineResp_getRq[50] ||
cache_cRqMshr$pipelineResp_getRq[51] ||
cache_cRqMshr$pipelineResp_getRq[52] ||
cache_cRqMshr$pipelineResp_getRq[53] ||
cache_cRqMshr$pipelineResp_getRq[54] ||
cache_cRqMshr$pipelineResp_getRq[55] ||
cache_cRqMshr$pipelineResp_getRq[56] ||
cache_cRqMshr$pipelineResp_getRq[57] ||
cache_cRqMshr$pipelineResp_getRq[58] ||
cache_cRqMshr$pipelineResp_getRq[59] ||
cache_cRqMshr$pipelineResp_getRq[60] ||
cache_cRqMshr$pipelineResp_getRq[61] ||
cache_cRqMshr$pipelineResp_getRq[62] ||
cache_cRqMshr$pipelineResp_getRq[63] ||
cache_cRqMshr$pipelineResp_getRq[64] ||
cache_cRqMshr$pipelineResp_getRq[65] ||
cache_cRqMshr$pipelineResp_getRq[66] ||
cache_cRqMshr$pipelineResp_getRq[67] ||
cache_cRqMshr$pipelineResp_getRq[68] ||
cache_cRqMshr$pipelineResp_getRq[69] ||
cache_cRqMshr$pipelineResp_getRq[70] ||
cache_cRqMshr$pipelineResp_getRq[71] ||
cache_cRqMshr$pipelineResp_getRq[72] ||
cache_cRqMshr$pipelineResp_getRq[73] ||
cache_cRqMshr$pipelineResp_getRq[74] ||
cache_cRqMshr$pipelineResp_getRq[75] ||
cache_cRqMshr$pipelineResp_getRq[76] ||
cache_cRqMshr$pipelineResp_getRq[77] ||
cache_cRqMshr$pipelineResp_getRq[78] ||
cache_cRqMshr$pipelineResp_getRq[79] ||
cache_cRqMshr$pipelineResp_getRq[80]) !=
(cache_cRqMshr$pipelineResp_getRq[85:84] == 2'd3) ;
assign NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3290 =
!cache_cRqMshr$pipelineResp_getRq[16] &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0) ;
assign NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3299 =
!cache_cRqMshr$pipelineResp_getRq[16] &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3156 &&
cache_pipeline$first[525:524] == 2'd0 &&
(cache_pipeline$first[519:518] != 2'd0 ||
cache_pipeline$first[521:520] != 2'd0 ||
cache_pipeline$first[523:522] != 2'd0) ;
assign NOT_cache_cRqMshr_pipelineResp_getSlot_IF_cach_ETC___d3369 =
cache_cRqMshr$pipelineResp_getSlot[64:61] !=
cache_pipeline$first[578:575] ;
assign NOT_cache_cRqMshr_pipelineResp_searchEndOfChai_ETC___d3114 =
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
(cache_cRqMshr$pipelineResp_getRq[16] &&
NOT_cache_pipeline_first__581_BITS_525_TO_524__ETC___d3019 ||
!cache_cRqMshr$pipelineResp_getRq[16] &&
(cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline$first[525:524] != 2'd0 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ||
cache_pipeline$first[525:524] != 2'd0 &&
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline$first[519:518] == 2'd0 &&
cache_pipeline$first[521:520] == 2'd0 &&
cache_pipeline$first[523:522] == 2'd0)) ;
assign NOT_cache_cRqMshr_pipelineResp_searchEndOfChai_ETC___d3353 =
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline$first[525:524] == 2'd0 &&
(cache_pipeline$first[519:518] != 2'd0 ||
cache_pipeline$first[521:520] != 2'd0 ||
cache_pipeline$first[523:522] != 2'd0) ;
assign NOT_cache_cRqRetryIndexQ_clearReq_dummy2_1_rea_ETC___d853 =
!cache_cRqRetryIndexQ_clearReq_dummy2_1$Q_OUT ||
!cache_cRqRetryIndexQ_clearReq_rl ;
assign NOT_cache_cRqRetryIndexQ_enqReq_dummy2_2_read__ETC___d876 =
(!cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT ||
(cache_cRqRetryIndexQ_enqReq_lat_0$whas ?
!cache_cRqRetryIndexQ_enqReq_lat_0$wget[4] :
!cache_cRqRetryIndexQ_enqReq_rl[4])) &&
(cache_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_deqReq_lat_1_whas__11__ETC___d817 ||
cache_cRqRetryIndexQ_empty) ;
assign NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d2637 =
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 ||
(cache_cRqMshr$pipelineResp_getRq[16] ?
_0_OR_NOT_cache_pipeline_first__581_BITS_519_TO_ETC___d2614 :
IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d2635) ;
assign NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d3798 =
cache_pipeline$first[516:513] != pipeOutCRqIdx__h314276 ;
assign NOT_cache_pipeline_first__581_BITS_519_TO_518__ETC___d3275 =
(!cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 ||
!cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 ||
!cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0) ;
assign NOT_cache_pipeline_first__581_BITS_519_TO_518__ETC___d3281 =
(!cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 ||
!cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 ||
!cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604) &&
cache_cRqMshr$pipelineResp_getSlot[12] ;
assign NOT_cache_pipeline_first__581_BITS_525_TO_524__ETC___d3019 =
cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 ;
assign NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3801 =
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d3798 ;
assign NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3809 =
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3264 ;
assign NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3827 =
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d3798 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3133 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3126 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3143 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3136 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3149 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline$first[525:524] != 2'd0 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3316 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3192 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3320 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3265 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3324 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3271 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3328 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline$first[525:524] != 2'd0 &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
NOT_cache_pipeline_first__581_BITS_519_TO_518__ETC___d3281 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3332 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr$pipelineResp_getRq[16] &&
(cache_pipeline$first[525:524] == 2'd0 ||
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) &&
cache_cRqMshr$pipelineResp_getAddrSucc[4] ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3340 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
cache_cRqMshr$pipelineResp_getRq[16] &&
(cache_pipeline$first[525:524] == 2'd0 ||
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) &&
cache_cRqMshr$pipelineResp_getRepSucc[4] ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3345 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline$first[525:524] != 2'd0 &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 &&
NOT_IF_cache_pipeline_first__581_BITS_584_TO_5_ETC___d3191 ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3351 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
(cache_pipeline$first[525:524] == 2'd0 ||
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) &&
(cache_pipeline$first[525:524] == 2'd0 ||
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3156) &&
cache_cRqMshr$pipelineResp_getSlot[12] ;
assign NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3359 =
!cache_pipeline$first[517] &&
(!cache_cRqMshr$pipelineResp_searchEndOfChain[4] ||
cache_cRqMshr$pipelineResp_getState != 3'd1) &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline$first[525:524] != 2'd0 &&
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline$first[519:518] == 2'd0 &&
cache_pipeline$first[521:520] == 2'd0 &&
cache_pipeline$first[523:522] == 2'd0 &&
cache_cRqMshr$pipelineResp_getRepSucc[4] ;
assign NOT_cache_rqFromCQ_clearReq_dummy2_1_read__8_9_ETC___d33 =
!cache_rqFromCQ_clearReq_dummy2_1$Q_OUT ||
!cache_rqFromCQ_clearReq_rl ;
assign NOT_cache_rqFromCQ_enqReq_dummy2_2_read__4_9_O_ETC___d78 =
(!cache_rqFromCQ_enqReq_dummy2_2$Q_OUT ||
(EN_to_child_rqFromC_enq ?
!cache_rqFromCQ_enqReq_lat_0$wget[74] :
!cache_rqFromCQ_enqReq_rl[74])) &&
(cache_rqFromCQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromCQ_deqReq_lat_1_whas__3_THEN_ca_ETC___d19 ||
cache_rqFromCQ_empty) ;
assign NOT_cache_rqFromDmaQ_clearReq_dummy2_1_read__3_ETC___d339 =
!cache_rqFromDmaQ_clearReq_dummy2_1$Q_OUT ||
!cache_rqFromDmaQ_clearReq_rl ;
assign NOT_cache_rqFromDmaQ_enqReq_dummy2_2_read__40__ETC___d384 =
(!cache_rqFromDmaQ_enqReq_dummy2_2$Q_OUT ||
(EN_dma_memReq_enq ?
!cache_rqFromDmaQ_enqReq_lat_0$wget[656] :
!cache_rqFromDmaQ_enqReq_rl[656])) &&
(cache_rqFromDmaQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromDmaQ_deqReq_lat_1_whas__19_THEN_ETC___d325 ||
cache_rqFromDmaQ_empty) ;
assign NOT_cache_rsFromCQ_clearReq_dummy2_1_read__20__ETC___d125 =
!cache_rsFromCQ_clearReq_dummy2_1$Q_OUT ||
!cache_rsFromCQ_clearReq_rl ;
assign NOT_cache_rsFromCQ_enqReq_dummy2_2_read__26_61_ETC___d170 =
(!cache_rsFromCQ_enqReq_dummy2_2$Q_OUT ||
(EN_to_child_rsFromC_enq ?
!cache_rsFromCQ_enqReq_lat_0$wget[581] :
!cache_rsFromCQ_enqReq_rl[581])) &&
(cache_rsFromCQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromCQ_deqReq_lat_1_whas__05_THEN_c_ETC___d111 ||
cache_rsFromCQ_empty) ;
assign NOT_cache_rsFromMQ_clearReq_dummy2_1_read__35__ETC___d740 =
!cache_rsFromMQ_clearReq_dummy2_1$Q_OUT ||
!cache_rsFromMQ_clearReq_rl ;
assign NOT_cache_rsFromMQ_enqReq_dummy2_2_read__41_76_ETC___d785 =
(!cache_rsFromMQ_enqReq_dummy2_2$Q_OUT ||
(EN_to_mem_rsFromM_enq ?
!cache_rsFromMQ_enqReq_lat_0$wget[517] :
!cache_rsFromMQ_enqReq_rl[517])) &&
(cache_rsFromMQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromMQ_deqReq_lat_1_whas__20_THEN_c_ETC___d726 ||
cache_rsFromMQ_empty) ;
assign NOT_cache_rsLdToDmaQ_clearReq_dummy2_1_read__2_ETC___d430 =
!cache_rsLdToDmaQ_clearReq_dummy2_1$Q_OUT ||
!cache_rsLdToDmaQ_clearReq_rl ;
assign NOT_cache_rsLdToDmaQ_enqReq_dummy2_2_read__31__ETC___d475 =
(!cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT ||
(CAN_FIRE_RL_cache_sendRsLdToDma ?
!cache_rsLdToDmaQ_enqReq_lat_0$wget[528] :
!cache_rsLdToDmaQ_enqReq_rl[528])) &&
(cache_rsLdToDmaQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsLdToDmaQ_deqReq_lat_1_whas__10_THEN_ETC___d416 ||
cache_rsLdToDmaQ_empty) ;
assign NOT_cache_rsStToDmaQ_clearReq_dummy2_1_read__1_ETC___d521 =
!cache_rsStToDmaQ_clearReq_dummy2_1$Q_OUT ||
!cache_rsStToDmaQ_clearReq_rl ;
assign NOT_cache_rsStToDmaQ_enqReq_dummy2_2_read__22__ETC___d566 =
(!cache_rsStToDmaQ_enqReq_dummy2_2$Q_OUT ||
(WILL_FIRE_RL_cache_sendRsStToDma ?
!cache_rsStToDmaQ_enqReq_lat_0$wget[16] :
!cache_rsStToDmaQ_enqReq_rl[16])) &&
(cache_rsStToDmaQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsStToDmaQ_deqReq_lat_1_whas__01_THEN_ETC___d507 ||
cache_rsStToDmaQ_empty) ;
assign NOT_cache_rsToCIndexQ_clearReq_dummy2_1_read___ETC___d976 =
!cache_rsToCIndexQ_clearReq_dummy2_1$Q_OUT ||
!cache_rsToCIndexQ_clearReq_rl ;
assign NOT_cache_rsToCIndexQ_enqReq_dummy2_2_read__51_ETC___d999 =
(!cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT ||
(cache_rsToCIndexQ_enqReq_lat_0$whas ?
!cache_rsToCIndexQ_enqReq_lat_0$wget[6] :
!cache_rsToCIndexQ_enqReq_rl[6])) &&
(cache_rsToCIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_deqReq_lat_1_whas__34_THE_ETC___d940 ||
cache_rsToCIndexQ_empty) ;
assign NOT_cache_toCQ_clearReq_dummy2_1_read__47_48_O_ETC___d252 =
!cache_toCQ_clearReq_dummy2_1$Q_OUT || !cache_toCQ_clearReq_rl ;
assign NOT_cache_toCQ_enqReq_dummy2_2_read__53_83_OR__ETC___d292 =
(!cache_toCQ_enqReq_dummy2_2$Q_OUT ||
(cache_toCQ_enqReq_lat_0$whas ?
!cache_toCQ_enqReq_lat_0$wget[585] :
!cache_toCQ_enqReq_rl[585])) &&
(cache_toCQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_toCQ_deqReq_lat_1_whas__32_THEN_cache_ETC___d238 ||
cache_toCQ_empty) ;
assign NOT_cache_toMQ_clearReq_dummy2_1_read__48_49_O_ETC___d653 =
!cache_toMQ_clearReq_dummy2_1$Q_OUT || !cache_toMQ_clearReq_rl ;
assign NOT_cache_toMQ_enqReq_dummy2_2_read__54_84_OR__ETC___d693 =
(!cache_toMQ_enqReq_dummy2_2$Q_OUT ||
(cache_toMQ_enqReq_lat_0$whas ?
!cache_toMQ_enqReq_lat_0$wget[641] :
!cache_toMQ_enqReq_rl[641])) &&
(cache_toMQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_toMQ_deqReq_lat_1_whas__33_THEN_cache_ETC___d639 ||
cache_toMQ_empty) ;
assign NOT_perfReqQ_clearReq_dummy2_1_read__864_865_O_ETC___d3869 =
!perfReqQ_clearReq_dummy2_1$Q_OUT || !perfReqQ_clearReq_rl ;
assign NOT_perfReqQ_enqReq_dummy2_2_read__870_890_OR__ETC___d3900 =
(!perfReqQ_enqReq_dummy2_2$Q_OUT ||
(EN_perf_req ?
!perfReqQ_enqReq_lat_0$wget[4] :
!perfReqQ_enqReq_rl[4])) &&
(perfReqQ_deqReq_dummy2_2$Q_OUT &&
(EN_perf_resp || perfReqQ_deqReq_rl) ||
perfReqQ_empty) ;
assign SEL_ARR_IF_cache_cRqMshr_pipelineResp_getSlot__ETC___d3440 =
CASE_cache_pipelinefirst_BITS_580_TO_579_0_ca_ETC__q84 <
SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 ;
assign SEL_ARR_cache_rqFromCQ_data_0_090_BITS_7_TO_6__ETC___d1118 =
{ CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q230,
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q231,
x__h249082,
78'h2AAAAAAAAAAAAAAA8AAA,
x__h257564 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1827 =
{ CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q91,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q92,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q93 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1836 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1827,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q98,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q99 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1845 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BITS_527_T_ETC___d1836,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q232,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q233 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1656 =
{ CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q80,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q81,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q82,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q83 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1661 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1656,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q106,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q107 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1666 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1661,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q110,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q111 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1671 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1666,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q114,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q115 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1676 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1671,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q118,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q119 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1681 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1676,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q122,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q123 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1686 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1681,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q126,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q127 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1691 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1686,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q130,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q131 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1696 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1691,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q134,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q135 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1701 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1696,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q138,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q139 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1706 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1701,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q142,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q143 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1711 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1706,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q146,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q147 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1716 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1711,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q150,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q151 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1721 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1716,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q154,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q155 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1726 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1721,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q158,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q159 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1731 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1726,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q162,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q163 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1736 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1731,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q166,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q167 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1741 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1736,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q170,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q171 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1746 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1741,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q174,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q175 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1751 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1746,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q178,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q179 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1756 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1751,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q182,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q183 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1761 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1756,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q186,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q187 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1766 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1761,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q190,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q191 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1771 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1766,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q194,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q195 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1776 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1771,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q198,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q199 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1781 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1776,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q202,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q203 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1786 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1781,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q206,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q207 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1791 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1786,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q210,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q211 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1796 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1791,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q214,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q215 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1801 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1796,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q218,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q219 } ;
assign SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1806 =
{ SEL_ARR_cache_rqFromDmaQ_data_0_129_BIT_591_57_ETC___d1801,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q228,
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q229 } ;
assign SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1886 =
{ CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q69,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 } ;
assign SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1895 =
{ SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1886,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q75,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q76 } ;
assign SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1904 =
{ SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1895,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q236,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q237 } ;
assign SEL_ARR_cache_rsFromCQ_data_0_855_BITS_580_TO__ETC___d1910 =
{ CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q243,
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q244,
SEL_ARR_cache_rsFromCQ_data_0_855_BIT_514_865__ETC___d1909 } ;
assign SEL_ARR_cache_rsFromCQ_data_0_855_BIT_514_865__ETC___d1909 =
{ CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q242,
SEL_ARR_cache_rsFromCQ_data_0_855_BITS_513_TO__ETC___d1904,
x__h275130 } ;
assign SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1948 =
{ CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q1,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q2,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q3,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q4 } ;
assign SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1957 =
{ SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1948,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q73,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q74 } ;
assign SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1966 =
{ SEL_ARR_cache_rsFromMQ_data_0_914_BITS_516_TO__ETC___d1957,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q226,
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q227 } ;
assign SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4018 =
{ CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q85,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q86,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q87 } ;
assign SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4027 =
{ SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4018,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q96,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q97 } ;
assign SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4036 =
{ SEL_ARR_cache_rsLdToDmaQ_data_0_004_BITS_527_T_ETC___d4027,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q257,
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q258 } ;
assign SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3969 =
{ CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q88,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q89,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q90 } ;
assign SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3978 =
{ SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3969,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q94,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q95 } ;
assign SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3987 =
{ SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3978,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q234,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q235 } ;
assign SEL_ARR_cache_toCQ_data_0_917_BITS_583_TO_520__ETC___d3998 =
{ CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q247,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248,
x__h444405,
SEL_ARR_cache_toCQ_data_0_917_BIT_515_953_cach_ETC___d3992,
x__h445950 } ;
assign SEL_ARR_cache_toCQ_data_0_917_BIT_515_953_cach_ETC___d3992 =
{ CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BIT_5_ETC__q238,
SEL_ARR_cache_toCQ_data_0_917_BITS_514_TO_451__ETC___d3987,
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q239 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4383 =
{ CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q220,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q221,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q222,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q223 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4392 =
{ SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4383,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q224,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q225 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4401 =
{ SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4392,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q245,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q246 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BITS_639_TO_576__ETC___d4402 =
{ CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q251,
SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4365,
SEL_ARR_cache_toMQ_data_0_050_BITS_511_TO_448__ETC___d4401 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4095 =
{ CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q100,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q101,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q102,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q103 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4104 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4095,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q104,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q105 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4113 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4104,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q108,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q109 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4122 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4113,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q112,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q113 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4131 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4122,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q116,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q117 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4140 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4131,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q120,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q121 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4149 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4140,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q124,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q125 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4158 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4149,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q128,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q129 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4167 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4158,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q132,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q133 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4176 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4167,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q136,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q137 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4185 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4176,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q140,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q141 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4194 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4185,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q144,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q145 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4203 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4194,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q148,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q149 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4212 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4203,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q152,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q153 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4221 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4212,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q156,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q157 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4230 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4221,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q160,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q161 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4239 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4230,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q164,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q165 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4248 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4239,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q168,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q169 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4257 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4248,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q172,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q173 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4266 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4257,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q176,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q177 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4275 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4266,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q180,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q181 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4284 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4275,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q184,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q185 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4293 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4284,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q188,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q189 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4302 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4293,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q192,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q193 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4311 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4302,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q196,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q197 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4320 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4311,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q200,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q201 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4329 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4320,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q204,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q205 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4338 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4329,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q208,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q209 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4347 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4338,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q212,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q213 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4356 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4347,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q216,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q217 } ;
assign SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4365 =
{ SEL_ARR_cache_toMQ_data_0_050_BIT_575_078_cach_ETC___d4356,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q240,
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q241 } ;
assign _0_CONCAT_IF_cache_pipeline_first__581_BITS_523_ETC___d3043 =
{ 1'd0,
IF_cache_pipeline_first__581_BITS_523_TO_522_6_ETC___d3041,
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 ?
4'd2 :
{ 2'd1,
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 } } ;
assign _0_OR_IF_SEL_ARR_cache_pipeline_first__581_BITS_ETC___d3423 =
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3418 ||
cache_toMInfoQ$FULL_N &&
(!cache_cRqMshr$pipelineResp_getRepSucc[4] ||
!cache_cRqRetryIndexQ_full) ;
assign _0_OR_NOT_CASE_IF_cache_pipeline_first__581_BIT_ETC___d3468 =
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3455 ||
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3459 ||
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3463 ||
(cache_cRqMshr$pipelineResp_getRq[16] ?
IF_cache_pipeline_RDY_first__579_AND_cache_cRq_ETC___d2613 :
!cache_rsToCIndexQ_full) ;
assign _0_OR_NOT_cache_pipeline_first__581_BITS_519_TO_ETC___d2614 =
!cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 ||
!cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 ||
!cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 ||
IF_cache_pipeline_RDY_first__579_AND_cache_cRq_ETC___d2613 ;
assign _theResult_____2__h119142 =
(cache_rqFromDmaQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromDmaQ_deqReq_lat_1_whas__19_THEN_ETC___d325) ?
next_deqP___1__h119479 :
cache_rqFromDmaQ_deqP ;
assign _theResult_____2__h135235 =
(cache_rsLdToDmaQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsLdToDmaQ_deqReq_lat_1_whas__10_THEN_ETC___d416) ?
next_deqP___1__h135572 :
cache_rsLdToDmaQ_deqP ;
assign _theResult_____2__h142737 =
(cache_rsStToDmaQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsStToDmaQ_deqReq_lat_1_whas__01_THEN_ETC___d507) ?
next_deqP___1__h143074 :
cache_rsStToDmaQ_deqP ;
assign _theResult_____2__h208521 =
(cache_toMQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_toMQ_deqReq_lat_1_whas__33_THEN_cache_ETC___d639) ?
next_deqP___1__h208858 :
cache_toMQ_deqP ;
assign _theResult_____2__h22297 =
(cache_rsFromCQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromCQ_deqReq_lat_1_whas__05_THEN_c_ETC___d111) ?
next_deqP___1__h22634 :
cache_rsFromCQ_deqP ;
assign _theResult_____2__h225016 =
(cache_rsFromMQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromMQ_deqReq_lat_1_whas__20_THEN_c_ETC___d726) ?
next_deqP___1__h225353 :
cache_rsFromMQ_deqP ;
assign _theResult_____2__h234513 =
(cache_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_deqReq_lat_1_whas__11__ETC___d817) ?
next_deqP___1__h234850 :
cache_cRqRetryIndexQ_deqP ;
assign _theResult_____2__h245988 =
(cache_rsToCIndexQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_deqReq_lat_1_whas__34_THE_ETC___d940) ?
next_deqP___1__h246325 :
cache_rsToCIndexQ_deqP ;
assign _theResult_____2__h37990 =
(cache_toCQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_toCQ_deqReq_lat_1_whas__32_THEN_cache_ETC___d238) ?
next_deqP___1__h38327 :
cache_toCQ_deqP ;
assign _theResult_____2__h7215 =
(cache_rqFromCQ_deqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromCQ_deqReq_lat_1_whas__3_THEN_ca_ETC___d19) ?
next_deqP___1__h7552 :
cache_rqFromCQ_deqP ;
assign addr__h288271 =
{ cache_cRqMshr$sendToM_getSlot[60:13],
cache_cRqMshr$sendToM_getRq[103:88] } ;
assign cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d2995 =
{ cache_cRqMshr$pipelineResp_getRq[151:104],
cache_cRqMshr$pipelineResp_getRq[16] ?
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2693 :
IF_IF_cache_cRqMshr_pipelineResp_getRq_IF_cach_ETC___d2699,
cache_cRqMshr$pipelineResp_getRq[16] ?
IF_cache_pipeline_first__581_BITS_519_TO_518_5_ETC___d2993 :
cache_pipeline$first[511:0] } ;
assign cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3123 =
cache_cRqMshr$pipelineResp_getRq[16] ||
((cache_pipeline$first[525:524] == 2'd0 ||
cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ?
CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79 ==
2'd0 :
cache_pipeline$first[525:524] == 2'd3) ;
assign cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3166 =
cache_cRqMshr$pipelineResp_getRq[16] &&
(cache_pipeline$first[525:524] == 2'd0 ||
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646) ||
!cache_cRqMshr$pipelineResp_getRq[16] &&
(cache_pipeline$first[525:524] == 2'd0 ||
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 &&
cache_pipeline$first[519:518] == 2'd0 &&
cache_pipeline$first[521:520] == 2'd0 &&
cache_pipeline$first[523:522] == 2'd0) ;
assign cache_cRqMshr_pipelineResp_getRq_IF_cache_pipe_ETC___d3658 =
{ cache_cRqMshr$pipelineResp_getRq[151:104],
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3493,
cache_cRqMshr$pipelineResp_getRq[16] ?
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3656 :
cache_pipeline$first[511:0] } ;
assign cache_cRqMshr_pipelineResp_getSlot_IF_cache_pi_ETC___d3754 =
{ cache_cRqMshr$pipelineResp_getSlot[64:12],
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3713,
cache_cRqMshr$pipelineResp_getSlot[9:8],
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3727,
cache_cRqMshr$pipelineResp_getSlot[5:4],
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3742,
cache_cRqMshr$pipelineResp_getSlot[1:0] } ;
assign cache_cRqMshr_pipelineResp_searchEndOfChain_ca_ETC___d2669 =
cache_cRqMshr$pipelineResp_searchEndOfChain[4] &&
cache_cRqMshr$pipelineResp_getState == 3'd1 ||
(cache_cRqMshr$pipelineResp_getRq[16] ?
IF_NOT_cache_pipeline_first__581_BITS_525_TO_5_ETC___d2654 :
IF_cache_pipeline_first__581_BITS_525_TO_524_6_ETC___d2667) ;
assign cache_cRqMshr_sendRqToC_searchNeedRqChild_1_CO_ETC___d2482 =
cache_cRqMshr$sendRqToC_searchNeedRqChild[4] &&
(!cache_pipeline$notEmpty || cache_pipeline$RDY_unguard_first) &&
(!cache_pipeline$notEmpty ||
CASE_cache_pipelineunguard_first_BITS_584_TO__ETC__q77) ;
assign cache_cRqMshrpipelineResp_getData_BITS_63_TO_0__q78 =
cache_cRqMshr$pipelineResp_getData[63:0] ;
assign cache_cRqRetryIndexQ_enqReq_dummy2_2_read__28__ETC___d864 =
cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833 ||
(!cache_cRqRetryIndexQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_cache_cRqTransfer_retry &&
!cache_cRqRetryIndexQ_deqReq_rl) &&
cache_cRqRetryIndexQ_full ;
assign cache_pipeline_RDY_deqWrite__580_AND_IF_cache__ETC___d2671 =
cache_pipeline$RDY_deqWrite &&
(cache_pipeline$first[517] ?
NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d2637 :
cache_cRqMshr_pipelineResp_searchEndOfChain_ca_ETC___d2669) ;
assign cache_pipeline_RDY_deqWrite__580_AND_NOT_cache_ETC___d3471 =
cache_pipeline$RDY_deqWrite &&
(!cache_pipeline$first[517] ||
(cache_pipeline$first[512] ?
_0_OR_IF_SEL_ARR_cache_pipeline_first__581_BITS_ETC___d3423 :
_0_OR_NOT_CASE_IF_cache_pipeline_first__581_BIT_ETC___d3468)) ;
assign cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 =
cache_pipeline$first[516:513] == cache_pipeline$first[582:579] ;
assign cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3103 =
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
(cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 ||
!cache_cRqMshr$pipelineResp_getRq[16] &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627) ;
assign cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3287 =
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 &&
NOT_IF_cache_pipeline_first__581_BITS_584_TO_5_ETC___d3191 ;
assign cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3295 =
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d3156 &&
cache_cRqMshr$pipelineResp_getSlot[12] ;
assign cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 =
cache_pipeline$first[519:518] <=
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 ;
assign cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2618 =
cache_pipeline$first[519:518] <=
cache_cRqMshr$pipelineResp_getRq[87:86] ;
assign cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3126 =
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 &&
cache_cRqMshr$pipelineResp_getRq[85:84] == 2'd3 ;
assign cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3136 =
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 &&
cache_cRqMshr$pipelineResp_getRq[85:84] != 2'd3 ;
assign cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3192 =
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 &&
NOT_IF_cache_pipeline_first__581_BITS_584_TO_5_ETC___d3191 ;
assign cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3196 =
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0) ;
assign cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3265 =
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 &&
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3264 ;
assign cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3271 =
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d2598 &&
cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 &&
cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 &&
cache_cRqMshr$pipelineResp_getData[512] !=
(cache_cRqMshr$pipelineResp_getRq[17] ||
cache_cRqMshr$pipelineResp_getRq[18] ||
cache_cRqMshr$pipelineResp_getRq[19] ||
cache_cRqMshr$pipelineResp_getRq[20] ||
cache_cRqMshr$pipelineResp_getRq[21] ||
cache_cRqMshr$pipelineResp_getRq[22] ||
cache_cRqMshr$pipelineResp_getRq[23] ||
cache_cRqMshr$pipelineResp_getRq[24] ||
cache_cRqMshr$pipelineResp_getRq[25] ||
cache_cRqMshr$pipelineResp_getRq[26] ||
cache_cRqMshr$pipelineResp_getRq[27] ||
cache_cRqMshr$pipelineResp_getRq[28] ||
cache_cRqMshr$pipelineResp_getRq[29] ||
cache_cRqMshr$pipelineResp_getRq[30] ||
cache_cRqMshr$pipelineResp_getRq[31] ||
cache_cRqMshr$pipelineResp_getRq[32] ||
cache_cRqMshr$pipelineResp_getRq[33] ||
cache_cRqMshr$pipelineResp_getRq[34] ||
cache_cRqMshr$pipelineResp_getRq[35] ||
cache_cRqMshr$pipelineResp_getRq[36] ||
cache_cRqMshr$pipelineResp_getRq[37] ||
cache_cRqMshr$pipelineResp_getRq[38] ||
cache_cRqMshr$pipelineResp_getRq[39] ||
cache_cRqMshr$pipelineResp_getRq[40] ||
cache_cRqMshr$pipelineResp_getRq[41] ||
cache_cRqMshr$pipelineResp_getRq[42] ||
cache_cRqMshr$pipelineResp_getRq[43] ||
cache_cRqMshr$pipelineResp_getRq[44] ||
cache_cRqMshr$pipelineResp_getRq[45] ||
cache_cRqMshr$pipelineResp_getRq[46] ||
cache_cRqMshr$pipelineResp_getRq[47] ||
cache_cRqMshr$pipelineResp_getRq[48] ||
cache_cRqMshr$pipelineResp_getRq[49] ||
cache_cRqMshr$pipelineResp_getRq[50] ||
cache_cRqMshr$pipelineResp_getRq[51] ||
cache_cRqMshr$pipelineResp_getRq[52] ||
cache_cRqMshr$pipelineResp_getRq[53] ||
cache_cRqMshr$pipelineResp_getRq[54] ||
cache_cRqMshr$pipelineResp_getRq[55] ||
cache_cRqMshr$pipelineResp_getRq[56] ||
cache_cRqMshr$pipelineResp_getRq[57] ||
cache_cRqMshr$pipelineResp_getRq[58] ||
cache_cRqMshr$pipelineResp_getRq[59] ||
cache_cRqMshr$pipelineResp_getRq[60] ||
cache_cRqMshr$pipelineResp_getRq[61] ||
cache_cRqMshr$pipelineResp_getRq[62] ||
cache_cRqMshr$pipelineResp_getRq[63] ||
cache_cRqMshr$pipelineResp_getRq[64] ||
cache_cRqMshr$pipelineResp_getRq[65] ||
cache_cRqMshr$pipelineResp_getRq[66] ||
cache_cRqMshr$pipelineResp_getRq[67] ||
cache_cRqMshr$pipelineResp_getRq[68] ||
cache_cRqMshr$pipelineResp_getRq[69] ||
cache_cRqMshr$pipelineResp_getRq[70] ||
cache_cRqMshr$pipelineResp_getRq[71] ||
cache_cRqMshr$pipelineResp_getRq[72] ||
cache_cRqMshr$pipelineResp_getRq[73] ||
cache_cRqMshr$pipelineResp_getRq[74] ||
cache_cRqMshr$pipelineResp_getRq[75] ||
cache_cRqMshr$pipelineResp_getRq[76] ||
cache_cRqMshr$pipelineResp_getRq[77] ||
cache_cRqMshr$pipelineResp_getRq[78] ||
cache_cRqMshr$pipelineResp_getRq[79] ||
cache_cRqMshr$pipelineResp_getRq[80]) ;
assign cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2601 =
cache_pipeline$first[521:520] <=
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 ;
assign cache_pipeline_first__581_BITS_521_TO_520_600__ETC___d2621 =
cache_pipeline$first[521:520] <=
cache_cRqMshr$pipelineResp_getRq[87:86] ;
assign cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2604 =
cache_pipeline$first[523:522] <=
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2597 ;
assign cache_pipeline_first__581_BITS_523_TO_522_603__ETC___d2624 =
cache_pipeline$first[523:522] <=
cache_cRqMshr$pipelineResp_getRq[87:86] ;
assign cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 =
cache_pipeline$first[573:526] ==
cache_cRqMshr$pipelineResp_getRq[151:104] ;
assign cache_pipeline_first__581_BIT_517_582_AND_NOT__ETC___d3820 =
cache_pipeline$first[517] && !cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_cRqMshr$pipelineResp_getRq[85:84] == 2'd3 ;
assign cache_pipeline_first__581_BIT_517_582_AND_NOT__ETC___d3824 =
cache_pipeline$first[517] && !cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3484 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_cRqMshr$pipelineResp_getRq[85:84] != 2'd3 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3129 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3126 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3139 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3136 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3146 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
!cache_cRqMshr$pipelineResp_getRq[16] &&
IF_cache_cRqMshr_pipelineResp_getRq_IF_cache_p_ETC___d2627 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3195 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3192 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3199 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3196 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3268 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3265 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3274 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
cache_pipeline_first__581_BITS_519_TO_518_594__ETC___d3271 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3278 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
NOT_cache_pipeline_first__581_BITS_519_TO_518__ETC___d3275 ;
assign cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3284 =
cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getRq[16] &&
NOT_cache_pipeline_first__581_BITS_519_TO_518__ETC___d3281 ;
assign cache_rqFromCQ_enqReq_dummy2_2_read__4_AND_IF__ETC___d65 =
cache_rqFromCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromCQ_enqReq_lat_1_whas_THEN_cache_ETC___d39 ||
(!cache_rqFromCQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_cache_cRqTransfer_new_child &&
!cache_rqFromCQ_deqReq_rl) &&
cache_rqFromCQ_full ;
assign cache_rqFromDmaQ_enqReq_dummy2_2_read__40_AND__ETC___d371 =
cache_rqFromDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromDmaQ_enqReq_lat_1_whas__09_THEN_ETC___d345 ||
(!cache_rqFromDmaQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_cache_cRqTransfer_new_dma &&
!cache_rqFromDmaQ_deqReq_rl) &&
cache_rqFromDmaQ_full ;
assign cache_rsFromCQ_enqReq_dummy2_2_read__26_AND_IF_ETC___d157 =
cache_rsFromCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromCQ_enqReq_lat_1_whas__5_THEN_ca_ETC___d131 ||
(!cache_rsFromCQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_cache_cRsTransfer && !cache_rsFromCQ_deqReq_rl) &&
cache_rsFromCQ_full ;
assign cache_rsFromMQ_enqReq_dummy2_2_read__41_AND_IF_ETC___d772 =
cache_rsFromMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromMQ_enqReq_lat_1_whas__10_THEN_c_ETC___d746 ||
(!cache_rsFromMQ_deqReq_dummy2_2$Q_OUT ||
!cache_rsFromMQ_deqReq_lat_0$whas &&
!cache_rsFromMQ_deqReq_rl) &&
cache_rsFromMQ_full ;
assign cache_rsLdToDmaQ_enqReq_dummy2_2_read__31_AND__ETC___d462 =
cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__00_THEN_ETC___d436 ||
(!cache_rsLdToDmaQ_deqReq_dummy2_2$Q_OUT ||
!EN_dma_respLd_deq && !cache_rsLdToDmaQ_deqReq_rl) &&
cache_rsLdToDmaQ_full ;
assign cache_rsStToDmaQ_enqReq_dummy2_2_read__22_AND__ETC___d553 =
cache_rsStToDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsStToDmaQ_enqReq_lat_1_whas__91_THEN_ETC___d527 ||
(!cache_rsStToDmaQ_deqReq_dummy2_2$Q_OUT ||
!EN_dma_respSt_deq && !cache_rsStToDmaQ_deqReq_rl) &&
cache_rsStToDmaQ_full ;
assign cache_rsToCIndexQ_enqReq_dummy2_2_read__51_AND_ETC___d987 =
cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956 ||
(!cache_rsToCIndexQ_deqReq_dummy2_2$Q_OUT ||
!WILL_FIRE_RL_cache_sendRsToC &&
!cache_rsToCIndexQ_deqReq_rl) &&
cache_rsToCIndexQ_full ;
assign cache_toCQ_enqReq_dummy2_2_read__53_AND_IF_cac_ETC___d279 =
cache_toCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toCQ_enqReq_lat_1_whas__87_THEN_cache_ETC___d196 ||
(!cache_toCQ_deqReq_dummy2_2$Q_OUT ||
!EN_to_child_toC_deq && !cache_toCQ_deqReq_rl) &&
cache_toCQ_full ;
assign cache_toMQ_enqReq_dummy2_2_read__54_AND_IF_cac_ETC___d680 =
cache_toMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toMQ_enqReq_lat_1_whas__88_THEN_cache_ETC___d597 ||
(!cache_toMQ_deqReq_dummy2_2$Q_OUT ||
!EN_to_mem_toM_deq && !cache_toMQ_deqReq_rl) &&
cache_toMQ_full ;
assign child__h313067 =
(cache_cRqMshr$sendRqToC_getSlot[3:2] != 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[7:6] != 2'd1) ?
2'd2 :
((cache_cRqMshr$sendRqToC_getSlot[3:2] == 2'd1) ?
2'd0 :
2'd1) ;
assign next_deqP___1__h119479 = cache_rqFromDmaQ_deqP + 1'd1 ;
assign next_deqP___1__h135572 = cache_rsLdToDmaQ_deqP + 1'd1 ;
assign next_deqP___1__h143074 = cache_rsStToDmaQ_deqP + 1'd1 ;
assign next_deqP___1__h208858 = cache_toMQ_deqP + 1'd1 ;
assign next_deqP___1__h225353 = cache_rsFromMQ_deqP + 1'd1 ;
assign next_deqP___1__h22634 = cache_rsFromCQ_deqP + 1'd1 ;
assign next_deqP___1__h234850 =
(cache_cRqRetryIndexQ_deqP == 4'd15) ?
4'd0 :
cache_cRqRetryIndexQ_deqP + 4'd1 ;
assign next_deqP___1__h246325 =
(cache_rsToCIndexQ_deqP == 4'd15) ?
4'd0 :
cache_rsToCIndexQ_deqP + 4'd1 ;
assign next_deqP___1__h38327 = cache_toCQ_deqP + 1'd1 ;
assign next_deqP___1__h7552 = cache_rqFromCQ_deqP + 1'd1 ;
assign perfReqQ_enqReq_dummy2_2_read__870_AND_IF_perf_ETC___d3887 =
perfReqQ_enqReq_dummy2_2$Q_OUT &&
IF_perfReqQ_enqReq_lat_1_whas__839_THEN_perfRe_ETC___d3875 ||
(!perfReqQ_deqReq_dummy2_2$Q_OUT ||
!EN_perf_resp && !perfReqQ_deqReq_rl) &&
perfReqQ_full ;
assign pipeOutCRqIdx__h314276 =
(cache_pipeline$first[584:583] == 2'd0) ?
cache_pipeline$first[582:579] :
(cache_pipeline$first[517] ?
cache_pipeline$first[516:513] :
4'd0) ;
assign rqAddr__h313360 =
(cache_cRqMshr$sendRqToC_getState == 3'd3) ?
cache_cRqMshr$sendRqToC_getRq[151:88] :
{ cache_cRqMshr$sendRqToC_getSlot[60:13],
cache_cRqMshr$sendRqToC_getRq[103:88] } ;
assign v__h129259 =
(cache_rsLdToDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsLdToDmaQ_enqReq_lat_1_whas__00_THEN_ETC___d436) ?
v__h129542 :
cache_rsLdToDmaQ_enqP ;
assign v__h129542 = cache_rsLdToDmaQ_enqP + 1'd1 ;
assign v__h142239 =
(cache_rsStToDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsStToDmaQ_enqReq_lat_1_whas__91_THEN_ETC___d527) ?
v__h142522 :
cache_rsStToDmaQ_enqP ;
assign v__h142522 = cache_rsStToDmaQ_enqP + 1'd1 ;
assign v__h16641 =
(cache_rsFromCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromCQ_enqReq_lat_1_whas__5_THEN_ca_ETC___d131) ?
v__h16924 :
cache_rsFromCQ_enqP ;
assign v__h168573 =
(cache_toMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toMQ_enqReq_lat_1_whas__88_THEN_cache_ETC___d597) ?
v__h168856 :
cache_toMQ_enqP ;
assign v__h168856 = cache_toMQ_enqP + 1'd1 ;
assign v__h16924 = cache_rsFromCQ_enqP + 1'd1 ;
assign v__h218716 =
(cache_rsFromMQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsFromMQ_enqReq_lat_1_whas__10_THEN_c_ETC___d746) ?
v__h218999 :
cache_rsFromMQ_enqP ;
assign v__h218999 = cache_rsFromMQ_enqP + 1'd1 ;
assign v__h232953 =
(cache_cRqRetryIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_cRqRetryIndexQ_enqReq_lat_1_whas__01__ETC___d833) ?
v__h233236 :
cache_cRqRetryIndexQ_enqP ;
assign v__h233236 =
(cache_cRqRetryIndexQ_enqP == 4'd15) ?
4'd0 :
cache_cRqRetryIndexQ_enqP + 4'd1 ;
assign v__h242396 =
(cache_rsToCIndexQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rsToCIndexQ_enqReq_lat_1_whas__24_THE_ETC___d956) ?
v__h242679 :
cache_rsToCIndexQ_enqP ;
assign v__h242679 =
(cache_rsToCIndexQ_enqP == 4'd15) ?
4'd0 :
cache_rsToCIndexQ_enqP + 4'd1 ;
assign v__h31944 =
(cache_toCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_toCQ_enqReq_lat_1_whas__87_THEN_cache_ETC___d196) ?
v__h32227 :
cache_toCQ_enqP ;
assign v__h32227 = cache_toCQ_enqP + 1'd1 ;
assign v__h6037 =
(cache_rqFromCQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromCQ_enqReq_lat_1_whas_THEN_cache_ETC___d39) ?
v__h6320 :
cache_rqFromCQ_enqP ;
assign v__h6320 = cache_rqFromCQ_enqP + 1'd1 ;
assign v__h72082 =
(cache_rqFromDmaQ_enqReq_dummy2_2$Q_OUT &&
IF_cache_rqFromDmaQ_enqReq_lat_1_whas__09_THEN_ETC___d345) ?
v__h72365 :
cache_rqFromDmaQ_enqP ;
assign v__h72365 = cache_rqFromDmaQ_enqP + 1'd1 ;
always@(cache_rqFromCQ_deqP or
cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1)
begin
case (cache_rqFromCQ_deqP)
1'd0: x__h257564 = cache_rqFromCQ_data_0[4:2];
1'd1: x__h257564 = cache_rqFromCQ_data_1[4:2];
endcase
end
always@(cache_rqFromCQ_deqP or
cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1)
begin
case (cache_rqFromCQ_deqP)
1'd0: addr__h257616 = cache_rqFromCQ_data_0[73:10];
1'd1: addr__h257616 = cache_rqFromCQ_data_1[73:10];
endcase
end
always@(cache_cRqRetryIndexQ_deqP or
cache_cRqRetryIndexQ_data_0 or
cache_cRqRetryIndexQ_data_1 or
cache_cRqRetryIndexQ_data_2 or
cache_cRqRetryIndexQ_data_3 or
cache_cRqRetryIndexQ_data_4 or
cache_cRqRetryIndexQ_data_5 or
cache_cRqRetryIndexQ_data_6 or
cache_cRqRetryIndexQ_data_7 or
cache_cRqRetryIndexQ_data_8 or
cache_cRqRetryIndexQ_data_9 or
cache_cRqRetryIndexQ_data_10 or
cache_cRqRetryIndexQ_data_11 or
cache_cRqRetryIndexQ_data_12 or
cache_cRqRetryIndexQ_data_13 or
cache_cRqRetryIndexQ_data_14 or cache_cRqRetryIndexQ_data_15)
begin
case (cache_cRqRetryIndexQ_deqP)
4'd0: x__h248737 = cache_cRqRetryIndexQ_data_0;
4'd1: x__h248737 = cache_cRqRetryIndexQ_data_1;
4'd2: x__h248737 = cache_cRqRetryIndexQ_data_2;
4'd3: x__h248737 = cache_cRqRetryIndexQ_data_3;
4'd4: x__h248737 = cache_cRqRetryIndexQ_data_4;
4'd5: x__h248737 = cache_cRqRetryIndexQ_data_5;
4'd6: x__h248737 = cache_cRqRetryIndexQ_data_6;
4'd7: x__h248737 = cache_cRqRetryIndexQ_data_7;
4'd8: x__h248737 = cache_cRqRetryIndexQ_data_8;
4'd9: x__h248737 = cache_cRqRetryIndexQ_data_9;
4'd10: x__h248737 = cache_cRqRetryIndexQ_data_10;
4'd11: x__h248737 = cache_cRqRetryIndexQ_data_11;
4'd12: x__h248737 = cache_cRqRetryIndexQ_data_12;
4'd13: x__h248737 = cache_cRqRetryIndexQ_data_13;
4'd14: x__h248737 = cache_cRqRetryIndexQ_data_14;
4'd15: x__h248737 = cache_cRqRetryIndexQ_data_15;
endcase
end
always@(cache_rqFromCQ_deqP or
cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1)
begin
case (cache_rqFromCQ_deqP)
1'd0: x__h249082 = cache_rqFromCQ_data_0[1:0];
1'd1: x__h249082 = cache_rqFromCQ_data_1[1:0];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0: addr__h273361 = cache_rqFromDmaQ_data_0[655:592];
1'd1: addr__h273361 = cache_rqFromDmaQ_data_1[655:592];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0: x__h444361 = cache_toCQ_data_0[1:0];
1'd1: x__h444361 = cache_toCQ_data_1[1:0];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0: x__h444405 = cache_toCQ_data_0[517:516];
1'd1: x__h444405 = cache_toCQ_data_1[517:516];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0: x__h445950 = cache_toCQ_data_0[2:0];
1'd1: x__h445950 = cache_toCQ_data_1[2:0];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0: x__h456804 = cache_toMQ_data_0[3:0];
1'd1: x__h456804 = cache_toMQ_data_1[3:0];
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0: x__h456399 = cache_rsLdToDmaQ_data_0[15:0];
1'd1: x__h456399 = cache_rsLdToDmaQ_data_1[15:0];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0: x__h275130 = cache_rsFromCQ_data_0[1:0];
1'd1: x__h275130 = cache_rsFromCQ_data_1[1:0];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q1 =
cache_rsFromMQ_data_0[516:453];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q1 =
cache_rsFromMQ_data_1[516:453];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q2 =
cache_rsFromMQ_data_0[452:389];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q2 =
cache_rsFromMQ_data_1[452:389];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q3 =
cache_rsFromMQ_data_0[388:325];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q3 =
cache_rsFromMQ_data_1[388:325];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q4 =
cache_rsFromMQ_data_0[324:261];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q4 =
cache_rsFromMQ_data_1[324:261];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q5 =
!cache_rqFromDmaQ_data_0[589];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q5 =
!cache_rqFromDmaQ_data_1[589];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 =
!cache_rqFromDmaQ_data_0[590];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q6 =
!cache_rqFromDmaQ_data_1[590];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 =
!cache_rqFromDmaQ_data_0[591];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q7 =
!cache_rqFromDmaQ_data_1[591];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 =
!cache_rqFromDmaQ_data_0[587];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q8 =
!cache_rqFromDmaQ_data_1[587];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 =
!cache_rqFromDmaQ_data_0[588];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q9 =
!cache_rqFromDmaQ_data_1[588];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 =
!cache_rqFromDmaQ_data_0[585];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q10 =
!cache_rqFromDmaQ_data_1[585];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 =
!cache_rqFromDmaQ_data_0[586];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q11 =
!cache_rqFromDmaQ_data_1[586];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 =
!cache_rqFromDmaQ_data_0[583];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q12 =
!cache_rqFromDmaQ_data_1[583];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 =
!cache_rqFromDmaQ_data_0[584];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q13 =
!cache_rqFromDmaQ_data_1[584];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 =
!cache_rqFromDmaQ_data_0[581];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q14 =
!cache_rqFromDmaQ_data_1[581];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 =
!cache_rqFromDmaQ_data_0[582];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q15 =
!cache_rqFromDmaQ_data_1[582];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 =
!cache_rqFromDmaQ_data_0[579];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q16 =
!cache_rqFromDmaQ_data_1[579];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 =
!cache_rqFromDmaQ_data_0[580];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q17 =
!cache_rqFromDmaQ_data_1[580];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 =
!cache_rqFromDmaQ_data_0[577];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q18 =
!cache_rqFromDmaQ_data_1[577];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 =
!cache_rqFromDmaQ_data_0[578];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q19 =
!cache_rqFromDmaQ_data_1[578];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 =
!cache_rqFromDmaQ_data_0[575];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q20 =
!cache_rqFromDmaQ_data_1[575];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 =
!cache_rqFromDmaQ_data_0[576];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q21 =
!cache_rqFromDmaQ_data_1[576];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 =
!cache_rqFromDmaQ_data_0[573];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q22 =
!cache_rqFromDmaQ_data_1[573];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 =
!cache_rqFromDmaQ_data_0[574];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q23 =
!cache_rqFromDmaQ_data_1[574];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 =
!cache_rqFromDmaQ_data_0[571];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q24 =
!cache_rqFromDmaQ_data_1[571];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 =
!cache_rqFromDmaQ_data_0[572];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q25 =
!cache_rqFromDmaQ_data_1[572];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 =
!cache_rqFromDmaQ_data_0[569];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q26 =
!cache_rqFromDmaQ_data_1[569];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 =
!cache_rqFromDmaQ_data_0[570];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q27 =
!cache_rqFromDmaQ_data_1[570];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 =
!cache_rqFromDmaQ_data_0[567];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q28 =
!cache_rqFromDmaQ_data_1[567];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 =
!cache_rqFromDmaQ_data_0[568];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q29 =
!cache_rqFromDmaQ_data_1[568];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 =
!cache_rqFromDmaQ_data_0[565];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q30 =
!cache_rqFromDmaQ_data_1[565];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 =
!cache_rqFromDmaQ_data_0[566];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q31 =
!cache_rqFromDmaQ_data_1[566];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 =
!cache_rqFromDmaQ_data_0[563];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q32 =
!cache_rqFromDmaQ_data_1[563];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 =
!cache_rqFromDmaQ_data_0[564];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q33 =
!cache_rqFromDmaQ_data_1[564];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 =
!cache_rqFromDmaQ_data_0[561];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q34 =
!cache_rqFromDmaQ_data_1[561];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 =
!cache_rqFromDmaQ_data_0[562];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q35 =
!cache_rqFromDmaQ_data_1[562];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 =
!cache_rqFromDmaQ_data_0[559];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q36 =
!cache_rqFromDmaQ_data_1[559];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 =
!cache_rqFromDmaQ_data_0[560];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q37 =
!cache_rqFromDmaQ_data_1[560];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 =
!cache_rqFromDmaQ_data_0[557];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q38 =
!cache_rqFromDmaQ_data_1[557];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 =
!cache_rqFromDmaQ_data_0[558];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q39 =
!cache_rqFromDmaQ_data_1[558];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 =
!cache_rqFromDmaQ_data_0[555];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q40 =
!cache_rqFromDmaQ_data_1[555];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 =
!cache_rqFromDmaQ_data_0[556];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q41 =
!cache_rqFromDmaQ_data_1[556];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 =
!cache_rqFromDmaQ_data_0[553];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q42 =
!cache_rqFromDmaQ_data_1[553];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 =
!cache_rqFromDmaQ_data_0[554];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q43 =
!cache_rqFromDmaQ_data_1[554];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 =
!cache_rqFromDmaQ_data_0[551];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q44 =
!cache_rqFromDmaQ_data_1[551];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 =
!cache_rqFromDmaQ_data_0[552];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q45 =
!cache_rqFromDmaQ_data_1[552];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 =
!cache_rqFromDmaQ_data_0[549];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q46 =
!cache_rqFromDmaQ_data_1[549];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 =
!cache_rqFromDmaQ_data_0[550];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q47 =
!cache_rqFromDmaQ_data_1[550];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 =
!cache_rqFromDmaQ_data_0[547];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q48 =
!cache_rqFromDmaQ_data_1[547];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 =
!cache_rqFromDmaQ_data_0[548];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q49 =
!cache_rqFromDmaQ_data_1[548];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 =
!cache_rqFromDmaQ_data_0[545];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q50 =
!cache_rqFromDmaQ_data_1[545];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 =
!cache_rqFromDmaQ_data_0[546];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q51 =
!cache_rqFromDmaQ_data_1[546];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 =
!cache_rqFromDmaQ_data_0[543];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q52 =
!cache_rqFromDmaQ_data_1[543];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 =
!cache_rqFromDmaQ_data_0[544];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q53 =
!cache_rqFromDmaQ_data_1[544];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 =
!cache_rqFromDmaQ_data_0[541];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q54 =
!cache_rqFromDmaQ_data_1[541];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 =
!cache_rqFromDmaQ_data_0[542];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q55 =
!cache_rqFromDmaQ_data_1[542];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 =
!cache_rqFromDmaQ_data_0[539];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q56 =
!cache_rqFromDmaQ_data_1[539];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 =
!cache_rqFromDmaQ_data_0[540];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q57 =
!cache_rqFromDmaQ_data_1[540];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 =
!cache_rqFromDmaQ_data_0[537];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q58 =
!cache_rqFromDmaQ_data_1[537];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 =
!cache_rqFromDmaQ_data_0[538];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q59 =
!cache_rqFromDmaQ_data_1[538];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 =
!cache_rqFromDmaQ_data_0[535];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q60 =
!cache_rqFromDmaQ_data_1[535];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 =
!cache_rqFromDmaQ_data_0[536];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q61 =
!cache_rqFromDmaQ_data_1[536];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 =
!cache_rqFromDmaQ_data_0[533];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q62 =
!cache_rqFromDmaQ_data_1[533];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 =
!cache_rqFromDmaQ_data_0[534];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q63 =
!cache_rqFromDmaQ_data_1[534];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 =
!cache_rqFromDmaQ_data_0[531];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q64 =
!cache_rqFromDmaQ_data_1[531];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 =
!cache_rqFromDmaQ_data_0[532];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q65 =
!cache_rqFromDmaQ_data_1[532];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 =
!cache_rqFromDmaQ_data_0[529];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q66 =
!cache_rqFromDmaQ_data_1[529];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 =
!cache_rqFromDmaQ_data_0[530];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q67 =
!cache_rqFromDmaQ_data_1[530];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 =
!cache_rqFromDmaQ_data_0[528];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_NOT_cache_rqFromD_ETC__q68 =
!cache_rqFromDmaQ_data_1[528];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q69 =
cache_rsFromCQ_data_0[513:450];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q69 =
cache_rsFromCQ_data_1[513:450];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70 =
cache_rsFromCQ_data_0[449:386];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q70 =
cache_rsFromCQ_data_1[449:386];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71 =
cache_rsFromCQ_data_0[385:322];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q71 =
cache_rsFromCQ_data_1[385:322];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 =
cache_rsFromCQ_data_0[321:258];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q72 =
cache_rsFromCQ_data_1[321:258];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q73 =
cache_rsFromMQ_data_0[260:197];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q73 =
cache_rsFromMQ_data_1[260:197];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q74 =
cache_rsFromMQ_data_0[196:133];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q74 =
cache_rsFromMQ_data_1[196:133];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q75 =
cache_rsFromCQ_data_0[257:194];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q75 =
cache_rsFromCQ_data_1[257:194];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q76 =
cache_rsFromCQ_data_0[193:130];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q76 =
cache_rsFromCQ_data_1[193:130];
endcase
end
always@(cache_pipeline$unguard_first or
cache_cRqMshr$sendRqToC_searchNeedRqChild)
begin
case (cache_pipeline$unguard_first[584:583])
2'd0:
CASE_cache_pipelineunguard_first_BITS_584_TO__ETC__q77 =
cache_pipeline$unguard_first[582:579] !=
cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0];
2'd2:
CASE_cache_pipelineunguard_first_BITS_584_TO__ETC__q77 =
!cache_pipeline$unguard_first[517] ||
cache_pipeline$unguard_first[516:513] !=
cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0];
default: CASE_cache_pipelineunguard_first_BITS_584_TO__ETC__q77 =
cache_pipeline$unguard_first[584:583] != 2'd1 ||
!cache_pipeline$unguard_first[517] ||
cache_pipeline$unguard_first[516:513] !=
cache_cRqMshr$sendRqToC_searchNeedRqChild[3:0];
endcase
end
always@(cache_cRqMshr$pipelineResp_getRq or cache_pipeline$first)
begin
case (cache_cRqMshr$pipelineResp_getRq[82:81])
2'd0:
CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79 =
cache_pipeline$first[519:518];
2'd1:
CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79 =
cache_pipeline$first[521:520];
2'd2:
CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79 =
cache_pipeline$first[523:522];
2'd3:
CASE_cache_cRqMshrpipelineResp_getRq_BITS_82__ETC__q79 =
2'b10 /* unspecified value */ ;
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q80 =
cache_rqFromDmaQ_data_0[591];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q80 =
cache_rqFromDmaQ_data_1[591];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q81 =
cache_rqFromDmaQ_data_0[590];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q81 =
cache_rqFromDmaQ_data_1[590];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q82 =
cache_rqFromDmaQ_data_0[589];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q82 =
cache_rqFromDmaQ_data_1[589];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q83 =
cache_rqFromDmaQ_data_0[588];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q83 =
cache_rqFromDmaQ_data_1[588];
endcase
end
always@(cache_pipeline$first)
begin
case (cache_pipeline$first[580:579])
2'd0:
SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 =
cache_pipeline$first[519:518];
2'd1:
SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 =
cache_pipeline$first[521:520];
2'd2:
SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 =
cache_pipeline$first[523:522];
2'd3:
SEL_ARR_cache_pipeline_first__581_BITS_519_TO__ETC___d3403 =
2'b10 /* unspecified value */ ;
endcase
end
always@(cache_pipeline$first or cache_cRqMshr$pipelineResp_getSlot)
begin
case (cache_pipeline$first[580:579])
2'd0:
CASE_cache_pipelinefirst_BITS_580_TO_579_0_ca_ETC__q84 =
cache_cRqMshr$pipelineResp_getSlot[1:0];
2'd1:
CASE_cache_pipelinefirst_BITS_580_TO_579_0_ca_ETC__q84 =
cache_cRqMshr$pipelineResp_getSlot[5:4];
2'd2:
CASE_cache_pipelinefirst_BITS_580_TO_579_0_ca_ETC__q84 =
cache_cRqMshr$pipelineResp_getSlot[9:8];
2'd3:
CASE_cache_pipelinefirst_BITS_580_TO_579_0_ca_ETC__q84 =
2'b10 /* unspecified value */ ;
endcase
end
always@(cache_pipeline$first or cache_cRqMshr$pipelineResp_getSlot)
begin
case (cache_pipeline$first[580:579])
2'd0:
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 =
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd2;
2'd1:
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 =
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd2;
2'd2:
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 =
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd2;
2'd3:
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3446 =
1'b0 /* unspecified value */ ;
endcase
end
always@(cache_pipeline$first or cache_cRqMshr$pipelineResp_getSlot)
begin
case (cache_pipeline$first[580:579])
2'd0:
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 =
cache_cRqMshr$pipelineResp_getSlot[3:2] == 2'd1;
2'd1:
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 =
cache_cRqMshr$pipelineResp_getSlot[7:6] == 2'd1;
2'd2:
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 =
cache_cRqMshr$pipelineResp_getSlot[11:10] == 2'd1;
2'd3:
SEL_ARR_cache_cRqMshr_pipelineResp_getSlot_IF__ETC___d3431 =
1'b0 /* unspecified value */ ;
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q85 =
cache_rsLdToDmaQ_data_0[527:464];
1'd1:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q85 =
cache_rsLdToDmaQ_data_1[527:464];
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q86 =
cache_rsLdToDmaQ_data_0[463:400];
1'd1:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q86 =
cache_rsLdToDmaQ_data_1[463:400];
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q87 =
cache_rsLdToDmaQ_data_0[399:336];
1'd1:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q87 =
cache_rsLdToDmaQ_data_1[399:336];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q88 =
cache_toCQ_data_0[514:451];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q88 =
cache_toCQ_data_1[514:451];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q89 =
cache_toCQ_data_0[450:387];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q89 =
cache_toCQ_data_1[450:387];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q90 =
cache_toCQ_data_0[386:323];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q90 =
cache_toCQ_data_1[386:323];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q91 =
cache_rqFromDmaQ_data_0[527:464];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q91 =
cache_rqFromDmaQ_data_1[527:464];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q92 =
cache_rqFromDmaQ_data_0[463:400];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q92 =
cache_rqFromDmaQ_data_1[463:400];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q93 =
cache_rqFromDmaQ_data_0[399:336];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q93 =
cache_rqFromDmaQ_data_1[399:336];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q94 =
cache_toCQ_data_0[322:259];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q94 =
cache_toCQ_data_1[322:259];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q95 =
cache_toCQ_data_0[258:195];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q95 =
cache_toCQ_data_1[258:195];
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q96 =
cache_rsLdToDmaQ_data_0[335:272];
1'd1:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q96 =
cache_rsLdToDmaQ_data_1[335:272];
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q97 =
cache_rsLdToDmaQ_data_0[271:208];
1'd1:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q97 =
cache_rsLdToDmaQ_data_1[271:208];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q98 =
cache_rqFromDmaQ_data_0[335:272];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q98 =
cache_rqFromDmaQ_data_1[335:272];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q99 =
cache_rqFromDmaQ_data_0[271:208];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q99 =
cache_rqFromDmaQ_data_1[271:208];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q100 =
cache_toMQ_data_0[575];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q100 =
cache_toMQ_data_1[575];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q101 =
cache_toMQ_data_0[574];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q101 =
cache_toMQ_data_1[574];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q102 =
cache_toMQ_data_0[573];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q102 =
cache_toMQ_data_1[573];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q103 =
cache_toMQ_data_0[572];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q103 =
cache_toMQ_data_1[572];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q104 =
cache_toMQ_data_0[571];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q104 =
cache_toMQ_data_1[571];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q105 =
cache_toMQ_data_0[570];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q105 =
cache_toMQ_data_1[570];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q106 =
cache_rqFromDmaQ_data_0[587];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q106 =
cache_rqFromDmaQ_data_1[587];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q107 =
cache_rqFromDmaQ_data_0[586];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q107 =
cache_rqFromDmaQ_data_1[586];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q108 =
cache_toMQ_data_0[569];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q108 =
cache_toMQ_data_1[569];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q109 =
cache_toMQ_data_0[568];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q109 =
cache_toMQ_data_1[568];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q110 =
cache_rqFromDmaQ_data_0[585];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q110 =
cache_rqFromDmaQ_data_1[585];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q111 =
cache_rqFromDmaQ_data_0[584];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q111 =
cache_rqFromDmaQ_data_1[584];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q112 =
cache_toMQ_data_0[567];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q112 =
cache_toMQ_data_1[567];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q113 =
cache_toMQ_data_0[566];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q113 =
cache_toMQ_data_1[566];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q114 =
cache_rqFromDmaQ_data_0[583];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q114 =
cache_rqFromDmaQ_data_1[583];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q115 =
cache_rqFromDmaQ_data_0[582];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q115 =
cache_rqFromDmaQ_data_1[582];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q116 =
cache_toMQ_data_0[565];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q116 =
cache_toMQ_data_1[565];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q117 =
cache_toMQ_data_0[564];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q117 =
cache_toMQ_data_1[564];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q118 =
cache_rqFromDmaQ_data_0[581];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q118 =
cache_rqFromDmaQ_data_1[581];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q119 =
cache_rqFromDmaQ_data_0[580];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q119 =
cache_rqFromDmaQ_data_1[580];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q120 =
cache_toMQ_data_0[563];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q120 =
cache_toMQ_data_1[563];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q121 =
cache_toMQ_data_0[562];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q121 =
cache_toMQ_data_1[562];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q122 =
cache_rqFromDmaQ_data_0[579];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q122 =
cache_rqFromDmaQ_data_1[579];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q123 =
cache_rqFromDmaQ_data_0[578];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q123 =
cache_rqFromDmaQ_data_1[578];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q124 =
cache_toMQ_data_0[561];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q124 =
cache_toMQ_data_1[561];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q125 =
cache_toMQ_data_0[560];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q125 =
cache_toMQ_data_1[560];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q126 =
cache_rqFromDmaQ_data_0[577];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q126 =
cache_rqFromDmaQ_data_1[577];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q127 =
cache_rqFromDmaQ_data_0[576];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q127 =
cache_rqFromDmaQ_data_1[576];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q128 =
cache_toMQ_data_0[559];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q128 =
cache_toMQ_data_1[559];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q129 =
cache_toMQ_data_0[558];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q129 =
cache_toMQ_data_1[558];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q130 =
cache_rqFromDmaQ_data_0[575];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q130 =
cache_rqFromDmaQ_data_1[575];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q131 =
cache_rqFromDmaQ_data_0[574];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q131 =
cache_rqFromDmaQ_data_1[574];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q132 =
cache_toMQ_data_0[557];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q132 =
cache_toMQ_data_1[557];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q133 =
cache_toMQ_data_0[556];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q133 =
cache_toMQ_data_1[556];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q134 =
cache_rqFromDmaQ_data_0[573];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q134 =
cache_rqFromDmaQ_data_1[573];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q135 =
cache_rqFromDmaQ_data_0[572];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q135 =
cache_rqFromDmaQ_data_1[572];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q136 =
cache_toMQ_data_0[555];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q136 =
cache_toMQ_data_1[555];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q137 =
cache_toMQ_data_0[554];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q137 =
cache_toMQ_data_1[554];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q138 =
cache_rqFromDmaQ_data_0[571];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q138 =
cache_rqFromDmaQ_data_1[571];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q139 =
cache_rqFromDmaQ_data_0[570];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q139 =
cache_rqFromDmaQ_data_1[570];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q140 =
cache_toMQ_data_0[553];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q140 =
cache_toMQ_data_1[553];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q141 =
cache_toMQ_data_0[552];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q141 =
cache_toMQ_data_1[552];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q142 =
cache_rqFromDmaQ_data_0[569];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q142 =
cache_rqFromDmaQ_data_1[569];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q143 =
cache_rqFromDmaQ_data_0[568];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q143 =
cache_rqFromDmaQ_data_1[568];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q144 =
cache_toMQ_data_0[551];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q144 =
cache_toMQ_data_1[551];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q145 =
cache_toMQ_data_0[550];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q145 =
cache_toMQ_data_1[550];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q146 =
cache_rqFromDmaQ_data_0[567];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q146 =
cache_rqFromDmaQ_data_1[567];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q147 =
cache_rqFromDmaQ_data_0[566];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q147 =
cache_rqFromDmaQ_data_1[566];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q148 =
cache_toMQ_data_0[549];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q148 =
cache_toMQ_data_1[549];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q149 =
cache_toMQ_data_0[548];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q149 =
cache_toMQ_data_1[548];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q150 =
cache_rqFromDmaQ_data_0[565];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q150 =
cache_rqFromDmaQ_data_1[565];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q151 =
cache_rqFromDmaQ_data_0[564];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q151 =
cache_rqFromDmaQ_data_1[564];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q152 =
cache_toMQ_data_0[547];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q152 =
cache_toMQ_data_1[547];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q153 =
cache_toMQ_data_0[546];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q153 =
cache_toMQ_data_1[546];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q154 =
cache_rqFromDmaQ_data_0[563];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q154 =
cache_rqFromDmaQ_data_1[563];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q155 =
cache_rqFromDmaQ_data_0[562];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q155 =
cache_rqFromDmaQ_data_1[562];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q156 =
cache_toMQ_data_0[545];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q156 =
cache_toMQ_data_1[545];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q157 =
cache_toMQ_data_0[544];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q157 =
cache_toMQ_data_1[544];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q158 =
cache_rqFromDmaQ_data_0[561];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q158 =
cache_rqFromDmaQ_data_1[561];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q159 =
cache_rqFromDmaQ_data_0[560];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q159 =
cache_rqFromDmaQ_data_1[560];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q160 =
cache_toMQ_data_0[543];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q160 =
cache_toMQ_data_1[543];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q161 =
cache_toMQ_data_0[542];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q161 =
cache_toMQ_data_1[542];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q162 =
cache_rqFromDmaQ_data_0[559];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q162 =
cache_rqFromDmaQ_data_1[559];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q163 =
cache_rqFromDmaQ_data_0[558];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q163 =
cache_rqFromDmaQ_data_1[558];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q164 =
cache_toMQ_data_0[541];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q164 =
cache_toMQ_data_1[541];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q165 =
cache_toMQ_data_0[540];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q165 =
cache_toMQ_data_1[540];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q166 =
cache_rqFromDmaQ_data_0[557];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q166 =
cache_rqFromDmaQ_data_1[557];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q167 =
cache_rqFromDmaQ_data_0[556];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q167 =
cache_rqFromDmaQ_data_1[556];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q168 =
cache_toMQ_data_0[539];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q168 =
cache_toMQ_data_1[539];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q169 =
cache_toMQ_data_0[538];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q169 =
cache_toMQ_data_1[538];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q170 =
cache_rqFromDmaQ_data_0[555];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q170 =
cache_rqFromDmaQ_data_1[555];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q171 =
cache_rqFromDmaQ_data_0[554];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q171 =
cache_rqFromDmaQ_data_1[554];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q172 =
cache_toMQ_data_0[537];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q172 =
cache_toMQ_data_1[537];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q173 =
cache_toMQ_data_0[536];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q173 =
cache_toMQ_data_1[536];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q174 =
cache_rqFromDmaQ_data_0[553];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q174 =
cache_rqFromDmaQ_data_1[553];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q175 =
cache_rqFromDmaQ_data_0[552];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q175 =
cache_rqFromDmaQ_data_1[552];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q176 =
cache_toMQ_data_0[535];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q176 =
cache_toMQ_data_1[535];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q177 =
cache_toMQ_data_0[534];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q177 =
cache_toMQ_data_1[534];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q178 =
cache_rqFromDmaQ_data_0[551];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q178 =
cache_rqFromDmaQ_data_1[551];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q179 =
cache_rqFromDmaQ_data_0[550];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q179 =
cache_rqFromDmaQ_data_1[550];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q180 =
cache_toMQ_data_0[533];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q180 =
cache_toMQ_data_1[533];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q181 =
cache_toMQ_data_0[532];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q181 =
cache_toMQ_data_1[532];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q182 =
cache_rqFromDmaQ_data_0[549];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q182 =
cache_rqFromDmaQ_data_1[549];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q183 =
cache_rqFromDmaQ_data_0[548];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q183 =
cache_rqFromDmaQ_data_1[548];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q184 =
cache_toMQ_data_0[531];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q184 =
cache_toMQ_data_1[531];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q185 =
cache_toMQ_data_0[530];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q185 =
cache_toMQ_data_1[530];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q186 =
cache_rqFromDmaQ_data_0[547];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q186 =
cache_rqFromDmaQ_data_1[547];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q187 =
cache_rqFromDmaQ_data_0[546];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q187 =
cache_rqFromDmaQ_data_1[546];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q188 =
cache_toMQ_data_0[529];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q188 =
cache_toMQ_data_1[529];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q189 =
cache_toMQ_data_0[528];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q189 =
cache_toMQ_data_1[528];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q190 =
cache_rqFromDmaQ_data_0[545];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q190 =
cache_rqFromDmaQ_data_1[545];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q191 =
cache_rqFromDmaQ_data_0[544];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q191 =
cache_rqFromDmaQ_data_1[544];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q192 =
cache_toMQ_data_0[527];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q192 =
cache_toMQ_data_1[527];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q193 =
cache_toMQ_data_0[526];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q193 =
cache_toMQ_data_1[526];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q194 =
cache_rqFromDmaQ_data_0[543];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q194 =
cache_rqFromDmaQ_data_1[543];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q195 =
cache_rqFromDmaQ_data_0[542];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q195 =
cache_rqFromDmaQ_data_1[542];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q196 =
cache_toMQ_data_0[525];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q196 =
cache_toMQ_data_1[525];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q197 =
cache_toMQ_data_0[524];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q197 =
cache_toMQ_data_1[524];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q198 =
cache_rqFromDmaQ_data_0[541];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q198 =
cache_rqFromDmaQ_data_1[541];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q199 =
cache_rqFromDmaQ_data_0[540];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q199 =
cache_rqFromDmaQ_data_1[540];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q200 =
cache_toMQ_data_0[523];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q200 =
cache_toMQ_data_1[523];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q201 =
cache_toMQ_data_0[522];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q201 =
cache_toMQ_data_1[522];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q202 =
cache_rqFromDmaQ_data_0[539];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q202 =
cache_rqFromDmaQ_data_1[539];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q203 =
cache_rqFromDmaQ_data_0[538];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q203 =
cache_rqFromDmaQ_data_1[538];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q204 =
cache_toMQ_data_0[521];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q204 =
cache_toMQ_data_1[521];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q205 =
cache_toMQ_data_0[520];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q205 =
cache_toMQ_data_1[520];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q206 =
cache_rqFromDmaQ_data_0[537];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q206 =
cache_rqFromDmaQ_data_1[537];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q207 =
cache_rqFromDmaQ_data_0[536];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q207 =
cache_rqFromDmaQ_data_1[536];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q208 =
cache_toMQ_data_0[519];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q208 =
cache_toMQ_data_1[519];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q209 =
cache_toMQ_data_0[518];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q209 =
cache_toMQ_data_1[518];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q210 =
cache_rqFromDmaQ_data_0[535];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q210 =
cache_rqFromDmaQ_data_1[535];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q211 =
cache_rqFromDmaQ_data_0[534];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q211 =
cache_rqFromDmaQ_data_1[534];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q212 =
cache_toMQ_data_0[517];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q212 =
cache_toMQ_data_1[517];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q213 =
cache_toMQ_data_0[516];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q213 =
cache_toMQ_data_1[516];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q214 =
cache_rqFromDmaQ_data_0[533];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q214 =
cache_rqFromDmaQ_data_1[533];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q215 =
cache_rqFromDmaQ_data_0[532];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q215 =
cache_rqFromDmaQ_data_1[532];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q216 =
cache_toMQ_data_0[515];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q216 =
cache_toMQ_data_1[515];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q217 =
cache_toMQ_data_0[514];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q217 =
cache_toMQ_data_1[514];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q218 =
cache_rqFromDmaQ_data_0[531];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q218 =
cache_rqFromDmaQ_data_1[531];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q219 =
cache_rqFromDmaQ_data_0[530];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q219 =
cache_rqFromDmaQ_data_1[530];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q220 =
cache_toMQ_data_0[511:448];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q220 =
cache_toMQ_data_1[511:448];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q221 =
cache_toMQ_data_0[447:384];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q221 =
cache_toMQ_data_1[447:384];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q222 =
cache_toMQ_data_0[383:320];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q222 =
cache_toMQ_data_1[383:320];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q223 =
cache_toMQ_data_0[319:256];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q223 =
cache_toMQ_data_1[319:256];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q224 =
cache_toMQ_data_0[255:192];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q224 =
cache_toMQ_data_1[255:192];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q225 =
cache_toMQ_data_0[191:128];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q225 =
cache_toMQ_data_1[191:128];
endcase
end
always@(child__h313067 or cache_cRqMshr$sendRqToC_getSlot)
begin
case (child__h313067)
2'd0:
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522 =
cache_cRqMshr$sendRqToC_getSlot[1:0];
2'd1:
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522 =
cache_cRqMshr$sendRqToC_getSlot[5:4];
2'd2:
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522 =
cache_cRqMshr$sendRqToC_getSlot[9:8];
2'd3:
SEL_ARR_IF_cache_cRqMshr_sendRqToC_getSlot_IF__ETC___d2522 =
2'b10 /* unspecified value */ ;
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q226 =
cache_rsFromMQ_data_0[132:69];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q226 =
cache_rsFromMQ_data_1[132:69];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q227 =
cache_rsFromMQ_data_0[68:5];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q227 =
cache_rsFromMQ_data_1[68:5];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q228 =
cache_rqFromDmaQ_data_0[529];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q228 =
cache_rqFromDmaQ_data_1[529];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q229 =
cache_rqFromDmaQ_data_0[528];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q229 =
cache_rqFromDmaQ_data_1[528];
endcase
end
always@(cache_rqFromCQ_deqP or
cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1)
begin
case (cache_rqFromCQ_deqP)
1'd0:
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q230 =
cache_rqFromCQ_data_0[7:6];
1'd1:
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q230 =
cache_rqFromCQ_data_1[7:6];
endcase
end
always@(cache_rqFromCQ_deqP or
cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1)
begin
case (cache_rqFromCQ_deqP)
1'd0:
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q231 =
cache_rqFromCQ_data_0[5];
1'd1:
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q231 =
cache_rqFromCQ_data_1[5];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q232 =
cache_rqFromDmaQ_data_0[207:144];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q232 =
cache_rqFromDmaQ_data_1[207:144];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q233 =
cache_rqFromDmaQ_data_0[143:80];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q233 =
cache_rqFromDmaQ_data_1[143:80];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q234 =
cache_toCQ_data_0[194:131];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q234 =
cache_toCQ_data_1[194:131];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q235 =
cache_toCQ_data_0[130:67];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q235 =
cache_toCQ_data_1[130:67];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q236 =
cache_rsFromCQ_data_0[129:66];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q236 =
cache_rsFromCQ_data_1[129:66];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q237 =
cache_rsFromCQ_data_0[65:2];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q237 =
cache_rsFromCQ_data_1[65:2];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BIT_5_ETC__q238 =
cache_toCQ_data_0[515];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BIT_5_ETC__q238 =
cache_toCQ_data_1[515];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q239 =
cache_toCQ_data_0[66:3];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q239 =
cache_toCQ_data_1[66:3];
endcase
end
always@(cache_rsToCIndexQ_deqP or
cache_rsToCIndexQ_data_0 or
cache_rsToCIndexQ_data_1 or
cache_rsToCIndexQ_data_2 or
cache_rsToCIndexQ_data_3 or
cache_rsToCIndexQ_data_4 or
cache_rsToCIndexQ_data_5 or
cache_rsToCIndexQ_data_6 or
cache_rsToCIndexQ_data_7 or
cache_rsToCIndexQ_data_8 or
cache_rsToCIndexQ_data_9 or
cache_rsToCIndexQ_data_10 or
cache_rsToCIndexQ_data_11 or
cache_rsToCIndexQ_data_12 or
cache_rsToCIndexQ_data_13 or
cache_rsToCIndexQ_data_14 or cache_rsToCIndexQ_data_15)
begin
case (cache_rsToCIndexQ_deqP)
4'd0:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_0[1:0];
4'd1:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_1[1:0];
4'd2:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_2[1:0];
4'd3:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_3[1:0];
4'd4:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_4[1:0];
4'd5:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_5[1:0];
4'd6:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_6[1:0];
4'd7:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_7[1:0];
4'd8:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_8[1:0];
4'd9:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_9[1:0];
4'd10:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_10[1:0];
4'd11:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_11[1:0];
4'd12:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_12[1:0];
4'd13:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_13[1:0];
4'd14:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_14[1:0];
4'd15:
SEL_ARR_cache_rsToCIndexQ_data_0_391_BITS_1_TO_ETC___d2445 =
cache_rsToCIndexQ_data_15[1:0];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q240 =
cache_toMQ_data_0[513];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q240 =
cache_toMQ_data_1[513];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q241 =
cache_toMQ_data_0[512];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_5_ETC__q241 =
cache_toMQ_data_1[512];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q242 =
cache_rsFromCQ_data_0[514];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q242 =
cache_rsFromCQ_data_1[514];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q243 =
cache_rsFromCQ_data_0[580:517];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q243 =
cache_rsFromCQ_data_1[580:517];
endcase
end
always@(cache_rsFromCQ_deqP or
cache_rsFromCQ_data_0 or cache_rsFromCQ_data_1)
begin
case (cache_rsFromCQ_deqP)
1'd0:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q244 =
cache_rsFromCQ_data_0[516:515];
1'd1:
CASE_cache_rsFromCQ_deqP_0_cache_rsFromCQ_data_ETC__q244 =
cache_rsFromCQ_data_1[516:515];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q245 =
cache_toMQ_data_0[127:64];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q245 =
cache_toMQ_data_1[127:64];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q246 =
cache_toMQ_data_0[63:0];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q246 =
cache_toMQ_data_1[63:0];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q247 =
cache_toCQ_data_0[583:520];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q247 =
cache_toCQ_data_1[583:520];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248 =
cache_toCQ_data_0[519:518];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q248 =
cache_toCQ_data_1[519:518];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q249 =
cache_toCQ_data_0[67:4];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q249 =
cache_toCQ_data_1[67:4];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q250 =
cache_toCQ_data_0[3:2];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BITS__ETC__q250 =
cache_toCQ_data_1[3:2];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q251 =
cache_toMQ_data_0[639:576];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q251 =
cache_toMQ_data_1[639:576];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q252 =
cache_toMQ_data_0[68:5];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BITS__ETC__q252 =
cache_toMQ_data_1[68:5];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_4_ETC__q253 =
cache_toMQ_data_0[4];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_4_ETC__q253 =
cache_toMQ_data_1[4];
endcase
end
always@(child__h313067 or cache_cRqMshr$sendRqToC_getSlot)
begin
case (child__h313067)
2'd0:
CASE_child13067_0_cache_cRqMshrsendRqToC_getS_ETC__q254 =
cache_cRqMshr$sendRqToC_getSlot[3:2] == 2'd1;
2'd1:
CASE_child13067_0_cache_cRqMshrsendRqToC_getS_ETC__q254 =
cache_cRqMshr$sendRqToC_getSlot[7:6] == 2'd1;
2'd2:
CASE_child13067_0_cache_cRqMshrsendRqToC_getS_ETC__q254 =
cache_cRqMshr$sendRqToC_getSlot[11:10] == 2'd1;
2'd3:
CASE_child13067_0_cache_cRqMshrsendRqToC_getS_ETC__q254 =
1'b0 /* unspecified value */ ;
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q255 =
!cache_toCQ_data_0[584];
1'd1:
CASE_cache_toCQ_deqP_0_NOT_cache_toCQ_data_0_B_ETC__q255 =
!cache_toCQ_data_1[584];
endcase
end
always@(cache_toCQ_deqP or cache_toCQ_data_0 or cache_toCQ_data_1)
begin
case (cache_toCQ_deqP)
1'd0:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BIT_5_ETC__q256 =
cache_toCQ_data_0[584];
1'd1:
CASE_cache_toCQ_deqP_0_cache_toCQ_data_0_BIT_5_ETC__q256 =
cache_toCQ_data_1[584];
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q257 =
cache_rsLdToDmaQ_data_0[207:144];
1'd1:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q257 =
cache_rsLdToDmaQ_data_1[207:144];
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q258 =
cache_rsLdToDmaQ_data_0[143:80];
1'd1:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q258 =
cache_rsLdToDmaQ_data_1[143:80];
endcase
end
always@(cache_rsLdToDmaQ_deqP or
cache_rsLdToDmaQ_data_0 or cache_rsLdToDmaQ_data_1)
begin
case (cache_rsLdToDmaQ_deqP)
1'd0:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q259 =
cache_rsLdToDmaQ_data_0[79:16];
1'd1:
CASE_cache_rsLdToDmaQ_deqP_0_cache_rsLdToDmaQ__ETC__q259 =
cache_rsLdToDmaQ_data_1[79:16];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_NOT_cache_toMQ_data_0_B_ETC__q260 =
!cache_toMQ_data_0[640];
1'd1:
CASE_cache_toMQ_deqP_0_NOT_cache_toMQ_data_0_B_ETC__q260 =
!cache_toMQ_data_1[640];
endcase
end
always@(cache_toMQ_deqP or cache_toMQ_data_0 or cache_toMQ_data_1)
begin
case (cache_toMQ_deqP)
1'd0:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_6_ETC__q261 =
cache_toMQ_data_0[640];
1'd1:
CASE_cache_toMQ_deqP_0_cache_toMQ_data_0_BIT_6_ETC__q261 =
cache_toMQ_data_1[640];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q262 =
cache_rsFromMQ_data_0[4];
1'd1:
CASE_cache_rsFromMQ_deqP_0_cache_rsFromMQ_data_ETC__q262 =
cache_rsFromMQ_data_1[4];
endcase
end
always@(cache_rsFromMQ_deqP or
cache_rsFromMQ_data_0 or cache_rsFromMQ_data_1)
begin
case (cache_rsFromMQ_deqP)
1'd0:
CASE_cache_rsFromMQ_deqP_0_NOT_cache_rsFromMQ__ETC__q263 =
!cache_rsFromMQ_data_0[4];
1'd1:
CASE_cache_rsFromMQ_deqP_0_NOT_cache_rsFromMQ__ETC__q263 =
!cache_rsFromMQ_data_1[4];
endcase
end
always@(cache_toMInfoQ$D_OUT or
cache_toMQ_full or cache_rsStToDmaIndexQ_sendToM$FULL_N)
begin
case (cache_toMInfoQ$D_OUT[1:0])
2'd0:
CASE_cache_toMInfoQD_OUT_BITS_1_TO_0_0_NOT_ca_ETC__q264 =
!cache_toMQ_full;
2'd1:
CASE_cache_toMInfoQD_OUT_BITS_1_TO_0_0_NOT_ca_ETC__q264 =
!cache_toMQ_full && cache_rsStToDmaIndexQ_sendToM$FULL_N;
default: CASE_cache_toMInfoQD_OUT_BITS_1_TO_0_0_NOT_ca_ETC__q264 =
cache_toMInfoQ$D_OUT[1:0] != 2'd2 || !cache_toMQ_full;
endcase
end
always@(cache_rqFromCQ_deqP or
cache_rqFromCQ_data_0 or cache_rqFromCQ_data_1)
begin
case (cache_rqFromCQ_deqP)
1'd0:
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q265 =
cache_rqFromCQ_data_0[9:8];
1'd1:
CASE_cache_rqFromCQ_deqP_0_cache_rqFromCQ_data_ETC__q265 =
cache_rqFromCQ_data_1[9:8];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q266 =
cache_rqFromDmaQ_data_0[15:0];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q266 =
cache_rqFromDmaQ_data_1[15:0];
endcase
end
always@(cache_rqFromDmaQ_deqP or
cache_rqFromDmaQ_data_0 or cache_rqFromDmaQ_data_1)
begin
case (cache_rqFromDmaQ_deqP)
1'd0:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q267 =
cache_rqFromDmaQ_data_0[79:16];
1'd1:
CASE_cache_rqFromDmaQ_deqP_0_cache_rqFromDmaQ__ETC__q267 =
cache_rqFromDmaQ_data_1[79:16];
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cache_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_10 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_11 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_12 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_13 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_14 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_15 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_8 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_data_9 <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
cache_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_doLdAfterReplace <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_priorNewCRqSrc <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromCQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromCQ_data_0 <= `BSV_ASSIGNMENT_DELAY 74'd0;
cache_rqFromCQ_data_1 <= `BSV_ASSIGNMENT_DELAY 74'd0;
cache_rqFromCQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromCQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromCQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_rqFromCQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromCQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
75'h2AAAAAAAAAAAAAAAAAA;
cache_rqFromCQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromDmaQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromDmaQ_data_0 <= `BSV_ASSIGNMENT_DELAY 656'd0;
cache_rqFromDmaQ_data_1 <= `BSV_ASSIGNMENT_DELAY 656'd0;
cache_rqFromDmaQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromDmaQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromDmaQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_rqFromDmaQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rqFromDmaQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
657'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rqFromDmaQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromCQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromCQ_data_0 <= `BSV_ASSIGNMENT_DELAY
581'h000000000000000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA8;
cache_rsFromCQ_data_1 <= `BSV_ASSIGNMENT_DELAY
581'h000000000000000002AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA8;
cache_rsFromCQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromCQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromCQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_rsFromCQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromCQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
582'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsFromCQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromMQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromMQ_data_0 <= `BSV_ASSIGNMENT_DELAY 517'd0;
cache_rsFromMQ_data_1 <= `BSV_ASSIGNMENT_DELAY 517'd0;
cache_rsFromMQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromMQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromMQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_rsFromMQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsFromMQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
518'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsFromMQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsLdToDmaQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsLdToDmaQ_data_0 <= `BSV_ASSIGNMENT_DELAY 528'd0;
cache_rsLdToDmaQ_data_1 <= `BSV_ASSIGNMENT_DELAY 528'd0;
cache_rsLdToDmaQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsLdToDmaQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsLdToDmaQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_rsLdToDmaQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsLdToDmaQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
529'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsLdToDmaQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsStToDmaQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsStToDmaQ_data_0 <= `BSV_ASSIGNMENT_DELAY 16'd0;
cache_rsStToDmaQ_data_1 <= `BSV_ASSIGNMENT_DELAY 16'd0;
cache_rsStToDmaQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsStToDmaQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsStToDmaQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_rsStToDmaQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsStToDmaQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 17'd43690;
cache_rsStToDmaQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsToCIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsToCIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_10 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_11 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_12 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_13 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_14 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_15 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_8 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_data_9 <= `BSV_ASSIGNMENT_DELAY 6'd0;
cache_rsToCIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_rsToCIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_rsToCIndexQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_rsToCIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY 4'd0;
cache_rsToCIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 7'd42;
cache_rsToCIndexQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toCQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toCQ_data_0 <= `BSV_ASSIGNMENT_DELAY
585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00000000000000000;
cache_toCQ_data_1 <= `BSV_ASSIGNMENT_DELAY
585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00000000000000000;
cache_toCQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toCQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toCQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_toCQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toCQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
586'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_toCQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toMQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toMQ_data_0 <= `BSV_ASSIGNMENT_DELAY
641'h05555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555400000000000000000;
cache_toMQ_data_1 <= `BSV_ASSIGNMENT_DELAY
641'h05555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555400000000000000000;
cache_toMQ_deqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toMQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toMQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
cache_toMQ_enqP <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_toMQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
642'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_toMQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
cache_whichCRq <= `BSV_ASSIGNMENT_DELAY 4'd0;
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY 4'd0;
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY 1'd0;
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY 1'd1;
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY 5'd10;
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cache_cRqRetryIndexQ_clearReq_rl$EN)
cache_cRqRetryIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_clearReq_rl$D_IN;
if (cache_cRqRetryIndexQ_data_0$EN)
cache_cRqRetryIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_0$D_IN;
if (cache_cRqRetryIndexQ_data_1$EN)
cache_cRqRetryIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_1$D_IN;
if (cache_cRqRetryIndexQ_data_10$EN)
cache_cRqRetryIndexQ_data_10 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_10$D_IN;
if (cache_cRqRetryIndexQ_data_11$EN)
cache_cRqRetryIndexQ_data_11 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_11$D_IN;
if (cache_cRqRetryIndexQ_data_12$EN)
cache_cRqRetryIndexQ_data_12 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_12$D_IN;
if (cache_cRqRetryIndexQ_data_13$EN)
cache_cRqRetryIndexQ_data_13 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_13$D_IN;
if (cache_cRqRetryIndexQ_data_14$EN)
cache_cRqRetryIndexQ_data_14 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_14$D_IN;
if (cache_cRqRetryIndexQ_data_15$EN)
cache_cRqRetryIndexQ_data_15 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_15$D_IN;
if (cache_cRqRetryIndexQ_data_2$EN)
cache_cRqRetryIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_2$D_IN;
if (cache_cRqRetryIndexQ_data_3$EN)
cache_cRqRetryIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_3$D_IN;
if (cache_cRqRetryIndexQ_data_4$EN)
cache_cRqRetryIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_4$D_IN;
if (cache_cRqRetryIndexQ_data_5$EN)
cache_cRqRetryIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_5$D_IN;
if (cache_cRqRetryIndexQ_data_6$EN)
cache_cRqRetryIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_6$D_IN;
if (cache_cRqRetryIndexQ_data_7$EN)
cache_cRqRetryIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_7$D_IN;
if (cache_cRqRetryIndexQ_data_8$EN)
cache_cRqRetryIndexQ_data_8 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_8$D_IN;
if (cache_cRqRetryIndexQ_data_9$EN)
cache_cRqRetryIndexQ_data_9 <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_data_9$D_IN;
if (cache_cRqRetryIndexQ_deqP$EN)
cache_cRqRetryIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_deqP$D_IN;
if (cache_cRqRetryIndexQ_deqReq_rl$EN)
cache_cRqRetryIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_deqReq_rl$D_IN;
if (cache_cRqRetryIndexQ_empty$EN)
cache_cRqRetryIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_empty$D_IN;
if (cache_cRqRetryIndexQ_enqP$EN)
cache_cRqRetryIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_enqP$D_IN;
if (cache_cRqRetryIndexQ_enqReq_rl$EN)
cache_cRqRetryIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_enqReq_rl$D_IN;
if (cache_cRqRetryIndexQ_full$EN)
cache_cRqRetryIndexQ_full <= `BSV_ASSIGNMENT_DELAY
cache_cRqRetryIndexQ_full$D_IN;
if (cache_doLdAfterReplace$EN)
cache_doLdAfterReplace <= `BSV_ASSIGNMENT_DELAY
cache_doLdAfterReplace$D_IN;
if (cache_priorNewCRqSrc$EN)
cache_priorNewCRqSrc <= `BSV_ASSIGNMENT_DELAY
cache_priorNewCRqSrc$D_IN;
if (cache_rqFromCQ_clearReq_rl$EN)
cache_rqFromCQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_clearReq_rl$D_IN;
if (cache_rqFromCQ_data_0$EN)
cache_rqFromCQ_data_0 <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_data_0$D_IN;
if (cache_rqFromCQ_data_1$EN)
cache_rqFromCQ_data_1 <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_data_1$D_IN;
if (cache_rqFromCQ_deqP$EN)
cache_rqFromCQ_deqP <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_deqP$D_IN;
if (cache_rqFromCQ_deqReq_rl$EN)
cache_rqFromCQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_deqReq_rl$D_IN;
if (cache_rqFromCQ_empty$EN)
cache_rqFromCQ_empty <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_empty$D_IN;
if (cache_rqFromCQ_enqP$EN)
cache_rqFromCQ_enqP <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_enqP$D_IN;
if (cache_rqFromCQ_enqReq_rl$EN)
cache_rqFromCQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_enqReq_rl$D_IN;
if (cache_rqFromCQ_full$EN)
cache_rqFromCQ_full <= `BSV_ASSIGNMENT_DELAY
cache_rqFromCQ_full$D_IN;
if (cache_rqFromDmaQ_clearReq_rl$EN)
cache_rqFromDmaQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_clearReq_rl$D_IN;
if (cache_rqFromDmaQ_data_0$EN)
cache_rqFromDmaQ_data_0 <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_data_0$D_IN;
if (cache_rqFromDmaQ_data_1$EN)
cache_rqFromDmaQ_data_1 <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_data_1$D_IN;
if (cache_rqFromDmaQ_deqP$EN)
cache_rqFromDmaQ_deqP <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_deqP$D_IN;
if (cache_rqFromDmaQ_deqReq_rl$EN)
cache_rqFromDmaQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_deqReq_rl$D_IN;
if (cache_rqFromDmaQ_empty$EN)
cache_rqFromDmaQ_empty <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_empty$D_IN;
if (cache_rqFromDmaQ_enqP$EN)
cache_rqFromDmaQ_enqP <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_enqP$D_IN;
if (cache_rqFromDmaQ_enqReq_rl$EN)
cache_rqFromDmaQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_enqReq_rl$D_IN;
if (cache_rqFromDmaQ_full$EN)
cache_rqFromDmaQ_full <= `BSV_ASSIGNMENT_DELAY
cache_rqFromDmaQ_full$D_IN;
if (cache_rsFromCQ_clearReq_rl$EN)
cache_rsFromCQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_clearReq_rl$D_IN;
if (cache_rsFromCQ_data_0$EN)
cache_rsFromCQ_data_0 <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_data_0$D_IN;
if (cache_rsFromCQ_data_1$EN)
cache_rsFromCQ_data_1 <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_data_1$D_IN;
if (cache_rsFromCQ_deqP$EN)
cache_rsFromCQ_deqP <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_deqP$D_IN;
if (cache_rsFromCQ_deqReq_rl$EN)
cache_rsFromCQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_deqReq_rl$D_IN;
if (cache_rsFromCQ_empty$EN)
cache_rsFromCQ_empty <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_empty$D_IN;
if (cache_rsFromCQ_enqP$EN)
cache_rsFromCQ_enqP <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_enqP$D_IN;
if (cache_rsFromCQ_enqReq_rl$EN)
cache_rsFromCQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_enqReq_rl$D_IN;
if (cache_rsFromCQ_full$EN)
cache_rsFromCQ_full <= `BSV_ASSIGNMENT_DELAY
cache_rsFromCQ_full$D_IN;
if (cache_rsFromMQ_clearReq_rl$EN)
cache_rsFromMQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_clearReq_rl$D_IN;
if (cache_rsFromMQ_data_0$EN)
cache_rsFromMQ_data_0 <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_data_0$D_IN;
if (cache_rsFromMQ_data_1$EN)
cache_rsFromMQ_data_1 <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_data_1$D_IN;
if (cache_rsFromMQ_deqP$EN)
cache_rsFromMQ_deqP <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_deqP$D_IN;
if (cache_rsFromMQ_deqReq_rl$EN)
cache_rsFromMQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_deqReq_rl$D_IN;
if (cache_rsFromMQ_empty$EN)
cache_rsFromMQ_empty <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_empty$D_IN;
if (cache_rsFromMQ_enqP$EN)
cache_rsFromMQ_enqP <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_enqP$D_IN;
if (cache_rsFromMQ_enqReq_rl$EN)
cache_rsFromMQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_enqReq_rl$D_IN;
if (cache_rsFromMQ_full$EN)
cache_rsFromMQ_full <= `BSV_ASSIGNMENT_DELAY
cache_rsFromMQ_full$D_IN;
if (cache_rsLdToDmaQ_clearReq_rl$EN)
cache_rsLdToDmaQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_clearReq_rl$D_IN;
if (cache_rsLdToDmaQ_data_0$EN)
cache_rsLdToDmaQ_data_0 <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_data_0$D_IN;
if (cache_rsLdToDmaQ_data_1$EN)
cache_rsLdToDmaQ_data_1 <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_data_1$D_IN;
if (cache_rsLdToDmaQ_deqP$EN)
cache_rsLdToDmaQ_deqP <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_deqP$D_IN;
if (cache_rsLdToDmaQ_deqReq_rl$EN)
cache_rsLdToDmaQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_deqReq_rl$D_IN;
if (cache_rsLdToDmaQ_empty$EN)
cache_rsLdToDmaQ_empty <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_empty$D_IN;
if (cache_rsLdToDmaQ_enqP$EN)
cache_rsLdToDmaQ_enqP <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_enqP$D_IN;
if (cache_rsLdToDmaQ_enqReq_rl$EN)
cache_rsLdToDmaQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_enqReq_rl$D_IN;
if (cache_rsLdToDmaQ_full$EN)
cache_rsLdToDmaQ_full <= `BSV_ASSIGNMENT_DELAY
cache_rsLdToDmaQ_full$D_IN;
if (cache_rsStToDmaQ_clearReq_rl$EN)
cache_rsStToDmaQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_clearReq_rl$D_IN;
if (cache_rsStToDmaQ_data_0$EN)
cache_rsStToDmaQ_data_0 <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_data_0$D_IN;
if (cache_rsStToDmaQ_data_1$EN)
cache_rsStToDmaQ_data_1 <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_data_1$D_IN;
if (cache_rsStToDmaQ_deqP$EN)
cache_rsStToDmaQ_deqP <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_deqP$D_IN;
if (cache_rsStToDmaQ_deqReq_rl$EN)
cache_rsStToDmaQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_deqReq_rl$D_IN;
if (cache_rsStToDmaQ_empty$EN)
cache_rsStToDmaQ_empty <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_empty$D_IN;
if (cache_rsStToDmaQ_enqP$EN)
cache_rsStToDmaQ_enqP <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_enqP$D_IN;
if (cache_rsStToDmaQ_enqReq_rl$EN)
cache_rsStToDmaQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_enqReq_rl$D_IN;
if (cache_rsStToDmaQ_full$EN)
cache_rsStToDmaQ_full <= `BSV_ASSIGNMENT_DELAY
cache_rsStToDmaQ_full$D_IN;
if (cache_rsToCIndexQ_clearReq_rl$EN)
cache_rsToCIndexQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_clearReq_rl$D_IN;
if (cache_rsToCIndexQ_data_0$EN)
cache_rsToCIndexQ_data_0 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_0$D_IN;
if (cache_rsToCIndexQ_data_1$EN)
cache_rsToCIndexQ_data_1 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_1$D_IN;
if (cache_rsToCIndexQ_data_10$EN)
cache_rsToCIndexQ_data_10 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_10$D_IN;
if (cache_rsToCIndexQ_data_11$EN)
cache_rsToCIndexQ_data_11 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_11$D_IN;
if (cache_rsToCIndexQ_data_12$EN)
cache_rsToCIndexQ_data_12 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_12$D_IN;
if (cache_rsToCIndexQ_data_13$EN)
cache_rsToCIndexQ_data_13 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_13$D_IN;
if (cache_rsToCIndexQ_data_14$EN)
cache_rsToCIndexQ_data_14 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_14$D_IN;
if (cache_rsToCIndexQ_data_15$EN)
cache_rsToCIndexQ_data_15 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_15$D_IN;
if (cache_rsToCIndexQ_data_2$EN)
cache_rsToCIndexQ_data_2 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_2$D_IN;
if (cache_rsToCIndexQ_data_3$EN)
cache_rsToCIndexQ_data_3 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_3$D_IN;
if (cache_rsToCIndexQ_data_4$EN)
cache_rsToCIndexQ_data_4 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_4$D_IN;
if (cache_rsToCIndexQ_data_5$EN)
cache_rsToCIndexQ_data_5 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_5$D_IN;
if (cache_rsToCIndexQ_data_6$EN)
cache_rsToCIndexQ_data_6 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_6$D_IN;
if (cache_rsToCIndexQ_data_7$EN)
cache_rsToCIndexQ_data_7 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_7$D_IN;
if (cache_rsToCIndexQ_data_8$EN)
cache_rsToCIndexQ_data_8 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_8$D_IN;
if (cache_rsToCIndexQ_data_9$EN)
cache_rsToCIndexQ_data_9 <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_data_9$D_IN;
if (cache_rsToCIndexQ_deqP$EN)
cache_rsToCIndexQ_deqP <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_deqP$D_IN;
if (cache_rsToCIndexQ_deqReq_rl$EN)
cache_rsToCIndexQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_deqReq_rl$D_IN;
if (cache_rsToCIndexQ_empty$EN)
cache_rsToCIndexQ_empty <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_empty$D_IN;
if (cache_rsToCIndexQ_enqP$EN)
cache_rsToCIndexQ_enqP <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_enqP$D_IN;
if (cache_rsToCIndexQ_enqReq_rl$EN)
cache_rsToCIndexQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_enqReq_rl$D_IN;
if (cache_rsToCIndexQ_full$EN)
cache_rsToCIndexQ_full <= `BSV_ASSIGNMENT_DELAY
cache_rsToCIndexQ_full$D_IN;
if (cache_toCQ_clearReq_rl$EN)
cache_toCQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_toCQ_clearReq_rl$D_IN;
if (cache_toCQ_data_0$EN)
cache_toCQ_data_0 <= `BSV_ASSIGNMENT_DELAY cache_toCQ_data_0$D_IN;
if (cache_toCQ_data_1$EN)
cache_toCQ_data_1 <= `BSV_ASSIGNMENT_DELAY cache_toCQ_data_1$D_IN;
if (cache_toCQ_deqP$EN)
cache_toCQ_deqP <= `BSV_ASSIGNMENT_DELAY cache_toCQ_deqP$D_IN;
if (cache_toCQ_deqReq_rl$EN)
cache_toCQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_toCQ_deqReq_rl$D_IN;
if (cache_toCQ_empty$EN)
cache_toCQ_empty <= `BSV_ASSIGNMENT_DELAY cache_toCQ_empty$D_IN;
if (cache_toCQ_enqP$EN)
cache_toCQ_enqP <= `BSV_ASSIGNMENT_DELAY cache_toCQ_enqP$D_IN;
if (cache_toCQ_enqReq_rl$EN)
cache_toCQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_toCQ_enqReq_rl$D_IN;
if (cache_toCQ_full$EN)
cache_toCQ_full <= `BSV_ASSIGNMENT_DELAY cache_toCQ_full$D_IN;
if (cache_toMQ_clearReq_rl$EN)
cache_toMQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_toMQ_clearReq_rl$D_IN;
if (cache_toMQ_data_0$EN)
cache_toMQ_data_0 <= `BSV_ASSIGNMENT_DELAY cache_toMQ_data_0$D_IN;
if (cache_toMQ_data_1$EN)
cache_toMQ_data_1 <= `BSV_ASSIGNMENT_DELAY cache_toMQ_data_1$D_IN;
if (cache_toMQ_deqP$EN)
cache_toMQ_deqP <= `BSV_ASSIGNMENT_DELAY cache_toMQ_deqP$D_IN;
if (cache_toMQ_deqReq_rl$EN)
cache_toMQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_toMQ_deqReq_rl$D_IN;
if (cache_toMQ_empty$EN)
cache_toMQ_empty <= `BSV_ASSIGNMENT_DELAY cache_toMQ_empty$D_IN;
if (cache_toMQ_enqP$EN)
cache_toMQ_enqP <= `BSV_ASSIGNMENT_DELAY cache_toMQ_enqP$D_IN;
if (cache_toMQ_enqReq_rl$EN)
cache_toMQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY
cache_toMQ_enqReq_rl$D_IN;
if (cache_toMQ_full$EN)
cache_toMQ_full <= `BSV_ASSIGNMENT_DELAY cache_toMQ_full$D_IN;
if (cache_whichCRq$EN)
cache_whichCRq <= `BSV_ASSIGNMENT_DELAY cache_whichCRq$D_IN;
if (perfReqQ_clearReq_rl$EN)
perfReqQ_clearReq_rl <= `BSV_ASSIGNMENT_DELAY
perfReqQ_clearReq_rl$D_IN;
if (perfReqQ_data_0$EN)
perfReqQ_data_0 <= `BSV_ASSIGNMENT_DELAY perfReqQ_data_0$D_IN;
if (perfReqQ_deqReq_rl$EN)
perfReqQ_deqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_deqReq_rl$D_IN;
if (perfReqQ_empty$EN)
perfReqQ_empty <= `BSV_ASSIGNMENT_DELAY perfReqQ_empty$D_IN;
if (perfReqQ_enqReq_rl$EN)
perfReqQ_enqReq_rl <= `BSV_ASSIGNMENT_DELAY perfReqQ_enqReq_rl$D_IN;
if (perfReqQ_full$EN)
perfReqQ_full <= `BSV_ASSIGNMENT_DELAY perfReqQ_full$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cache_cRqRetryIndexQ_clearReq_rl = 1'h0;
cache_cRqRetryIndexQ_data_0 = 4'hA;
cache_cRqRetryIndexQ_data_1 = 4'hA;
cache_cRqRetryIndexQ_data_10 = 4'hA;
cache_cRqRetryIndexQ_data_11 = 4'hA;
cache_cRqRetryIndexQ_data_12 = 4'hA;
cache_cRqRetryIndexQ_data_13 = 4'hA;
cache_cRqRetryIndexQ_data_14 = 4'hA;
cache_cRqRetryIndexQ_data_15 = 4'hA;
cache_cRqRetryIndexQ_data_2 = 4'hA;
cache_cRqRetryIndexQ_data_3 = 4'hA;
cache_cRqRetryIndexQ_data_4 = 4'hA;
cache_cRqRetryIndexQ_data_5 = 4'hA;
cache_cRqRetryIndexQ_data_6 = 4'hA;
cache_cRqRetryIndexQ_data_7 = 4'hA;
cache_cRqRetryIndexQ_data_8 = 4'hA;
cache_cRqRetryIndexQ_data_9 = 4'hA;
cache_cRqRetryIndexQ_deqP = 4'hA;
cache_cRqRetryIndexQ_deqReq_rl = 1'h0;
cache_cRqRetryIndexQ_empty = 1'h0;
cache_cRqRetryIndexQ_enqP = 4'hA;
cache_cRqRetryIndexQ_enqReq_rl = 5'h0A;
cache_cRqRetryIndexQ_full = 1'h0;
cache_doLdAfterReplace = 1'h0;
cache_priorNewCRqSrc = 1'h0;
cache_rqFromCQ_clearReq_rl = 1'h0;
cache_rqFromCQ_data_0 = 74'h2AAAAAAAAAAAAAAAAAA;
cache_rqFromCQ_data_1 = 74'h2AAAAAAAAAAAAAAAAAA;
cache_rqFromCQ_deqP = 1'h0;
cache_rqFromCQ_deqReq_rl = 1'h0;
cache_rqFromCQ_empty = 1'h0;
cache_rqFromCQ_enqP = 1'h0;
cache_rqFromCQ_enqReq_rl = 75'h2AAAAAAAAAAAAAAAAAA;
cache_rqFromCQ_full = 1'h0;
cache_rqFromDmaQ_clearReq_rl = 1'h0;
cache_rqFromDmaQ_data_0 =
656'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rqFromDmaQ_data_1 =
656'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rqFromDmaQ_deqP = 1'h0;
cache_rqFromDmaQ_deqReq_rl = 1'h0;
cache_rqFromDmaQ_empty = 1'h0;
cache_rqFromDmaQ_enqP = 1'h0;
cache_rqFromDmaQ_enqReq_rl =
657'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rqFromDmaQ_full = 1'h0;
cache_rsFromCQ_clearReq_rl = 1'h0;
cache_rsFromCQ_data_0 =
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsFromCQ_data_1 =
581'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsFromCQ_deqP = 1'h0;
cache_rsFromCQ_deqReq_rl = 1'h0;
cache_rsFromCQ_empty = 1'h0;
cache_rsFromCQ_enqP = 1'h0;
cache_rsFromCQ_enqReq_rl =
582'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsFromCQ_full = 1'h0;
cache_rsFromMQ_clearReq_rl = 1'h0;
cache_rsFromMQ_data_0 =
517'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsFromMQ_data_1 =
517'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsFromMQ_deqP = 1'h0;
cache_rsFromMQ_deqReq_rl = 1'h0;
cache_rsFromMQ_empty = 1'h0;
cache_rsFromMQ_enqP = 1'h0;
cache_rsFromMQ_enqReq_rl =
518'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsFromMQ_full = 1'h0;
cache_rsLdToDmaQ_clearReq_rl = 1'h0;
cache_rsLdToDmaQ_data_0 =
528'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsLdToDmaQ_data_1 =
528'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsLdToDmaQ_deqP = 1'h0;
cache_rsLdToDmaQ_deqReq_rl = 1'h0;
cache_rsLdToDmaQ_empty = 1'h0;
cache_rsLdToDmaQ_enqP = 1'h0;
cache_rsLdToDmaQ_enqReq_rl =
529'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_rsLdToDmaQ_full = 1'h0;
cache_rsStToDmaQ_clearReq_rl = 1'h0;
cache_rsStToDmaQ_data_0 = 16'hAAAA;
cache_rsStToDmaQ_data_1 = 16'hAAAA;
cache_rsStToDmaQ_deqP = 1'h0;
cache_rsStToDmaQ_deqReq_rl = 1'h0;
cache_rsStToDmaQ_empty = 1'h0;
cache_rsStToDmaQ_enqP = 1'h0;
cache_rsStToDmaQ_enqReq_rl = 17'h0AAAA;
cache_rsStToDmaQ_full = 1'h0;
cache_rsToCIndexQ_clearReq_rl = 1'h0;
cache_rsToCIndexQ_data_0 = 6'h2A;
cache_rsToCIndexQ_data_1 = 6'h2A;
cache_rsToCIndexQ_data_10 = 6'h2A;
cache_rsToCIndexQ_data_11 = 6'h2A;
cache_rsToCIndexQ_data_12 = 6'h2A;
cache_rsToCIndexQ_data_13 = 6'h2A;
cache_rsToCIndexQ_data_14 = 6'h2A;
cache_rsToCIndexQ_data_15 = 6'h2A;
cache_rsToCIndexQ_data_2 = 6'h2A;
cache_rsToCIndexQ_data_3 = 6'h2A;
cache_rsToCIndexQ_data_4 = 6'h2A;
cache_rsToCIndexQ_data_5 = 6'h2A;
cache_rsToCIndexQ_data_6 = 6'h2A;
cache_rsToCIndexQ_data_7 = 6'h2A;
cache_rsToCIndexQ_data_8 = 6'h2A;
cache_rsToCIndexQ_data_9 = 6'h2A;
cache_rsToCIndexQ_deqP = 4'hA;
cache_rsToCIndexQ_deqReq_rl = 1'h0;
cache_rsToCIndexQ_empty = 1'h0;
cache_rsToCIndexQ_enqP = 4'hA;
cache_rsToCIndexQ_enqReq_rl = 7'h2A;
cache_rsToCIndexQ_full = 1'h0;
cache_toCQ_clearReq_rl = 1'h0;
cache_toCQ_data_0 =
585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_toCQ_data_1 =
585'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_toCQ_deqP = 1'h0;
cache_toCQ_deqReq_rl = 1'h0;
cache_toCQ_empty = 1'h0;
cache_toCQ_enqP = 1'h0;
cache_toCQ_enqReq_rl =
586'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_toCQ_full = 1'h0;
cache_toMQ_clearReq_rl = 1'h0;
cache_toMQ_data_0 =
641'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_toMQ_data_1 =
641'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_toMQ_deqP = 1'h0;
cache_toMQ_deqReq_rl = 1'h0;
cache_toMQ_empty = 1'h0;
cache_toMQ_enqP = 1'h0;
cache_toMQ_enqReq_rl =
642'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
cache_toMQ_full = 1'h0;
cache_whichCRq = 4'hA;
perfReqQ_clearReq_rl = 1'h0;
perfReqQ_data_0 = 4'hA;
perfReqQ_deqReq_rl = 1'h0;
perfReqQ_empty = 1'h0;
perfReqQ_enqReq_rl = 5'h0A;
perfReqQ_full = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd0 &&
cache_cRqMshr$sendToM_getData[512])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 560, column 38\ncannot have data");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd0 &&
cache_cRqMshr$sendToM_getData[512])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd0 &&
cache_doLdAfterReplace)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 561, column 41\ndoLdAfterReplace should be false");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd0 &&
cache_doLdAfterReplace)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd1 &&
!cache_cRqMshr$sendToM_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 585, column 43\nmust be dma write");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd1 &&
!cache_cRqMshr$sendToM_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd1 &&
!cache_cRqMshr$sendToM_getData[512])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 586, column 37\ndma write must have data");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd1 &&
!cache_cRqMshr$sendToM_getData[512])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd1 &&
cache_doLdAfterReplace)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 587, column 41\ndoLdAfterReplace should be false");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd1 &&
cache_doLdAfterReplace)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd2 &&
cache_cRqMshr$sendToM_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 626, column 41\nmust be child req");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd2 &&
cache_cRqMshr$sendToM_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd2 &&
!cache_cRqMshr$sendToM_getData[512])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 627, column 37\nreplace must have data");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] == 2'd2 &&
!cache_cRqMshr$sendToM_getData[512])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] != 2'd0 &&
cache_toMInfoQ$D_OUT[1:0] != 2'd1 &&
cache_toMInfoQ$D_OUT[1:0] != 2'd2)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 630, column 29\nunknown to mem type");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendToM && cache_toMInfoQ$D_OUT[1:0] != 2'd0 &&
cache_toMInfoQ$D_OUT[1:0] != 2'd1 &&
cache_toMInfoQ$D_OUT[1:0] != 2'd2)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsToC &&
cache_cRqMshr$sendRsToDmaC_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 697, column 37\ncRq should be child req");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsToC &&
cache_cRqMshr$sendRsToDmaC_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRqToC &&
cache_cRqMshr$sendRqToC_getState != 3'd3 &&
cache_cRqMshr$sendRqToC_getState != 3'd2)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 761, column 13\nonly WaitSt and WaitOldTag needs req child");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRqToC &&
cache_cRqMshr$sendRqToC_getState != 3'd3 &&
cache_cRqMshr$sendRqToC_getState != 3'd2)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRqToC &&
cache_cRqMshr$sendRqToC_getSlot[3:2] != 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[7:6] != 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[11:10] != 2'd1)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 768, column 41\nshould have a child to downgrade");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRqToC &&
cache_cRqMshr$sendRqToC_getSlot[3:2] != 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[7:6] != 2'd1 &&
cache_cRqMshr$sendRqToC_getSlot[11:10] != 2'd1)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRqToC &&
NOT_SEL_ARR_cache_cRqMshr_sendRqToC_getSlot_IF_ETC___d2508)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 776, column 30\ndirPend should be ToSend");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRqToC &&
NOT_SEL_ARR_cache_cRqMshr_sendRqToC_getSlot_IF_ETC___d2508)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsLdToDma &&
!cache_cRqMshr$sendRsToDmaC_getData[512])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 646, column 33\ndma read req always has valid data");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsLdToDma &&
!cache_cRqMshr$sendRsToDmaC_getData[512])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsLdToDma &&
!cache_cRqMshr$sendRsToDmaC_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 648, column 39\ncRq should be DMA req");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsLdToDma &&
!cache_cRqMshr$sendRsToDmaC_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsLdToDma &&
(cache_cRqMshr$sendRsToDmaC_getRq[17] ||
cache_cRqMshr$sendRsToDmaC_getRq[18] ||
cache_cRqMshr$sendRsToDmaC_getRq[19] ||
cache_cRqMshr$sendRsToDmaC_getRq[20] ||
cache_cRqMshr$sendRsToDmaC_getRq[21] ||
cache_cRqMshr$sendRsToDmaC_getRq[22] ||
cache_cRqMshr$sendRsToDmaC_getRq[23] ||
cache_cRqMshr$sendRsToDmaC_getRq[24] ||
cache_cRqMshr$sendRsToDmaC_getRq[25] ||
cache_cRqMshr$sendRsToDmaC_getRq[26] ||
cache_cRqMshr$sendRsToDmaC_getRq[27] ||
cache_cRqMshr$sendRsToDmaC_getRq[28] ||
cache_cRqMshr$sendRsToDmaC_getRq[29] ||
cache_cRqMshr$sendRsToDmaC_getRq[30] ||
cache_cRqMshr$sendRsToDmaC_getRq[31] ||
cache_cRqMshr$sendRsToDmaC_getRq[32] ||
cache_cRqMshr$sendRsToDmaC_getRq[33] ||
cache_cRqMshr$sendRsToDmaC_getRq[34] ||
cache_cRqMshr$sendRsToDmaC_getRq[35] ||
cache_cRqMshr$sendRsToDmaC_getRq[36] ||
cache_cRqMshr$sendRsToDmaC_getRq[37] ||
cache_cRqMshr$sendRsToDmaC_getRq[38] ||
cache_cRqMshr$sendRsToDmaC_getRq[39] ||
cache_cRqMshr$sendRsToDmaC_getRq[40] ||
cache_cRqMshr$sendRsToDmaC_getRq[41] ||
cache_cRqMshr$sendRsToDmaC_getRq[42] ||
cache_cRqMshr$sendRsToDmaC_getRq[43] ||
cache_cRqMshr$sendRsToDmaC_getRq[44] ||
cache_cRqMshr$sendRsToDmaC_getRq[45] ||
cache_cRqMshr$sendRsToDmaC_getRq[46] ||
cache_cRqMshr$sendRsToDmaC_getRq[47] ||
cache_cRqMshr$sendRsToDmaC_getRq[48] ||
cache_cRqMshr$sendRsToDmaC_getRq[49] ||
cache_cRqMshr$sendRsToDmaC_getRq[50] ||
cache_cRqMshr$sendRsToDmaC_getRq[51] ||
cache_cRqMshr$sendRsToDmaC_getRq[52] ||
cache_cRqMshr$sendRsToDmaC_getRq[53] ||
cache_cRqMshr$sendRsToDmaC_getRq[54] ||
cache_cRqMshr$sendRsToDmaC_getRq[55] ||
cache_cRqMshr$sendRsToDmaC_getRq[56] ||
cache_cRqMshr$sendRsToDmaC_getRq[57] ||
cache_cRqMshr$sendRsToDmaC_getRq[58] ||
cache_cRqMshr$sendRsToDmaC_getRq[59] ||
cache_cRqMshr$sendRsToDmaC_getRq[60] ||
cache_cRqMshr$sendRsToDmaC_getRq[61] ||
cache_cRqMshr$sendRsToDmaC_getRq[62] ||
cache_cRqMshr$sendRsToDmaC_getRq[63] ||
cache_cRqMshr$sendRsToDmaC_getRq[64] ||
cache_cRqMshr$sendRsToDmaC_getRq[65] ||
cache_cRqMshr$sendRsToDmaC_getRq[66] ||
cache_cRqMshr$sendRsToDmaC_getRq[67] ||
cache_cRqMshr$sendRsToDmaC_getRq[68] ||
cache_cRqMshr$sendRsToDmaC_getRq[69] ||
cache_cRqMshr$sendRsToDmaC_getRq[70] ||
cache_cRqMshr$sendRsToDmaC_getRq[71] ||
cache_cRqMshr$sendRsToDmaC_getRq[72] ||
cache_cRqMshr$sendRsToDmaC_getRq[73] ||
cache_cRqMshr$sendRsToDmaC_getRq[74] ||
cache_cRqMshr$sendRsToDmaC_getRq[75] ||
cache_cRqMshr$sendRsToDmaC_getRq[76] ||
cache_cRqMshr$sendRsToDmaC_getRq[77] ||
cache_cRqMshr$sendRsToDmaC_getRq[78] ||
cache_cRqMshr$sendRsToDmaC_getRq[79] ||
cache_cRqMshr$sendRsToDmaC_getRq[80] ||
cache_cRqMshr$sendRsToDmaC_getRq[85:84] != 2'd1))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 650, column 13\ncRq should be DMA read");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsLdToDma &&
(cache_cRqMshr$sendRsToDmaC_getRq[17] ||
cache_cRqMshr$sendRsToDmaC_getRq[18] ||
cache_cRqMshr$sendRsToDmaC_getRq[19] ||
cache_cRqMshr$sendRsToDmaC_getRq[20] ||
cache_cRqMshr$sendRsToDmaC_getRq[21] ||
cache_cRqMshr$sendRsToDmaC_getRq[22] ||
cache_cRqMshr$sendRsToDmaC_getRq[23] ||
cache_cRqMshr$sendRsToDmaC_getRq[24] ||
cache_cRqMshr$sendRsToDmaC_getRq[25] ||
cache_cRqMshr$sendRsToDmaC_getRq[26] ||
cache_cRqMshr$sendRsToDmaC_getRq[27] ||
cache_cRqMshr$sendRsToDmaC_getRq[28] ||
cache_cRqMshr$sendRsToDmaC_getRq[29] ||
cache_cRqMshr$sendRsToDmaC_getRq[30] ||
cache_cRqMshr$sendRsToDmaC_getRq[31] ||
cache_cRqMshr$sendRsToDmaC_getRq[32] ||
cache_cRqMshr$sendRsToDmaC_getRq[33] ||
cache_cRqMshr$sendRsToDmaC_getRq[34] ||
cache_cRqMshr$sendRsToDmaC_getRq[35] ||
cache_cRqMshr$sendRsToDmaC_getRq[36] ||
cache_cRqMshr$sendRsToDmaC_getRq[37] ||
cache_cRqMshr$sendRsToDmaC_getRq[38] ||
cache_cRqMshr$sendRsToDmaC_getRq[39] ||
cache_cRqMshr$sendRsToDmaC_getRq[40] ||
cache_cRqMshr$sendRsToDmaC_getRq[41] ||
cache_cRqMshr$sendRsToDmaC_getRq[42] ||
cache_cRqMshr$sendRsToDmaC_getRq[43] ||
cache_cRqMshr$sendRsToDmaC_getRq[44] ||
cache_cRqMshr$sendRsToDmaC_getRq[45] ||
cache_cRqMshr$sendRsToDmaC_getRq[46] ||
cache_cRqMshr$sendRsToDmaC_getRq[47] ||
cache_cRqMshr$sendRsToDmaC_getRq[48] ||
cache_cRqMshr$sendRsToDmaC_getRq[49] ||
cache_cRqMshr$sendRsToDmaC_getRq[50] ||
cache_cRqMshr$sendRsToDmaC_getRq[51] ||
cache_cRqMshr$sendRsToDmaC_getRq[52] ||
cache_cRqMshr$sendRsToDmaC_getRq[53] ||
cache_cRqMshr$sendRsToDmaC_getRq[54] ||
cache_cRqMshr$sendRsToDmaC_getRq[55] ||
cache_cRqMshr$sendRsToDmaC_getRq[56] ||
cache_cRqMshr$sendRsToDmaC_getRq[57] ||
cache_cRqMshr$sendRsToDmaC_getRq[58] ||
cache_cRqMshr$sendRsToDmaC_getRq[59] ||
cache_cRqMshr$sendRsToDmaC_getRq[60] ||
cache_cRqMshr$sendRsToDmaC_getRq[61] ||
cache_cRqMshr$sendRsToDmaC_getRq[62] ||
cache_cRqMshr$sendRsToDmaC_getRq[63] ||
cache_cRqMshr$sendRsToDmaC_getRq[64] ||
cache_cRqMshr$sendRsToDmaC_getRq[65] ||
cache_cRqMshr$sendRsToDmaC_getRq[66] ||
cache_cRqMshr$sendRsToDmaC_getRq[67] ||
cache_cRqMshr$sendRsToDmaC_getRq[68] ||
cache_cRqMshr$sendRsToDmaC_getRq[69] ||
cache_cRqMshr$sendRsToDmaC_getRq[70] ||
cache_cRqMshr$sendRsToDmaC_getRq[71] ||
cache_cRqMshr$sendRsToDmaC_getRq[72] ||
cache_cRqMshr$sendRsToDmaC_getRq[73] ||
cache_cRqMshr$sendRsToDmaC_getRq[74] ||
cache_cRqMshr$sendRsToDmaC_getRq[75] ||
cache_cRqMshr$sendRsToDmaC_getRq[76] ||
cache_cRqMshr$sendRsToDmaC_getRq[77] ||
cache_cRqMshr$sendRsToDmaC_getRq[78] ||
cache_cRqMshr$sendRsToDmaC_getRq[79] ||
cache_cRqMshr$sendRsToDmaC_getRq[80] ||
cache_cRqMshr$sendRsToDmaC_getRq[85:84] != 2'd1))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsStToDma &&
!cache_cRqMshr$sendRsToDmaC_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 671, column 39\ncRq should be DMA req");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsStToDma &&
!cache_cRqMshr$sendRsToDmaC_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsStToDma &&
(!cache_cRqMshr$sendRsToDmaC_getRq[17] &&
!cache_cRqMshr$sendRsToDmaC_getRq[18] &&
!cache_cRqMshr$sendRsToDmaC_getRq[19] &&
!cache_cRqMshr$sendRsToDmaC_getRq[20] &&
!cache_cRqMshr$sendRsToDmaC_getRq[21] &&
!cache_cRqMshr$sendRsToDmaC_getRq[22] &&
!cache_cRqMshr$sendRsToDmaC_getRq[23] &&
!cache_cRqMshr$sendRsToDmaC_getRq[24] &&
!cache_cRqMshr$sendRsToDmaC_getRq[25] &&
!cache_cRqMshr$sendRsToDmaC_getRq[26] &&
!cache_cRqMshr$sendRsToDmaC_getRq[27] &&
!cache_cRqMshr$sendRsToDmaC_getRq[28] &&
!cache_cRqMshr$sendRsToDmaC_getRq[29] &&
!cache_cRqMshr$sendRsToDmaC_getRq[30] &&
!cache_cRqMshr$sendRsToDmaC_getRq[31] &&
!cache_cRqMshr$sendRsToDmaC_getRq[32] &&
!cache_cRqMshr$sendRsToDmaC_getRq[33] &&
!cache_cRqMshr$sendRsToDmaC_getRq[34] &&
!cache_cRqMshr$sendRsToDmaC_getRq[35] &&
!cache_cRqMshr$sendRsToDmaC_getRq[36] &&
!cache_cRqMshr$sendRsToDmaC_getRq[37] &&
!cache_cRqMshr$sendRsToDmaC_getRq[38] &&
!cache_cRqMshr$sendRsToDmaC_getRq[39] &&
!cache_cRqMshr$sendRsToDmaC_getRq[40] &&
!cache_cRqMshr$sendRsToDmaC_getRq[41] &&
!cache_cRqMshr$sendRsToDmaC_getRq[42] &&
!cache_cRqMshr$sendRsToDmaC_getRq[43] &&
!cache_cRqMshr$sendRsToDmaC_getRq[44] &&
!cache_cRqMshr$sendRsToDmaC_getRq[45] &&
!cache_cRqMshr$sendRsToDmaC_getRq[46] &&
!cache_cRqMshr$sendRsToDmaC_getRq[47] &&
!cache_cRqMshr$sendRsToDmaC_getRq[48] &&
!cache_cRqMshr$sendRsToDmaC_getRq[49] &&
!cache_cRqMshr$sendRsToDmaC_getRq[50] &&
!cache_cRqMshr$sendRsToDmaC_getRq[51] &&
!cache_cRqMshr$sendRsToDmaC_getRq[52] &&
!cache_cRqMshr$sendRsToDmaC_getRq[53] &&
!cache_cRqMshr$sendRsToDmaC_getRq[54] &&
!cache_cRqMshr$sendRsToDmaC_getRq[55] &&
!cache_cRqMshr$sendRsToDmaC_getRq[56] &&
!cache_cRqMshr$sendRsToDmaC_getRq[57] &&
!cache_cRqMshr$sendRsToDmaC_getRq[58] &&
!cache_cRqMshr$sendRsToDmaC_getRq[59] &&
!cache_cRqMshr$sendRsToDmaC_getRq[60] &&
!cache_cRqMshr$sendRsToDmaC_getRq[61] &&
!cache_cRqMshr$sendRsToDmaC_getRq[62] &&
!cache_cRqMshr$sendRsToDmaC_getRq[63] &&
!cache_cRqMshr$sendRsToDmaC_getRq[64] &&
!cache_cRqMshr$sendRsToDmaC_getRq[65] &&
!cache_cRqMshr$sendRsToDmaC_getRq[66] &&
!cache_cRqMshr$sendRsToDmaC_getRq[67] &&
!cache_cRqMshr$sendRsToDmaC_getRq[68] &&
!cache_cRqMshr$sendRsToDmaC_getRq[69] &&
!cache_cRqMshr$sendRsToDmaC_getRq[70] &&
!cache_cRqMshr$sendRsToDmaC_getRq[71] &&
!cache_cRqMshr$sendRsToDmaC_getRq[72] &&
!cache_cRqMshr$sendRsToDmaC_getRq[73] &&
!cache_cRqMshr$sendRsToDmaC_getRq[74] &&
!cache_cRqMshr$sendRsToDmaC_getRq[75] &&
!cache_cRqMshr$sendRsToDmaC_getRq[76] &&
!cache_cRqMshr$sendRsToDmaC_getRq[77] &&
!cache_cRqMshr$sendRsToDmaC_getRq[78] &&
!cache_cRqMshr$sendRsToDmaC_getRq[79] &&
!cache_cRqMshr$sendRsToDmaC_getRq[80] ||
cache_cRqMshr$sendRsToDmaC_getRq[85:84] != 2'd3))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 673, column 13\ncRq should be DMA write");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_sendRsStToDma &&
(!cache_cRqMshr$sendRsToDmaC_getRq[17] &&
!cache_cRqMshr$sendRsToDmaC_getRq[18] &&
!cache_cRqMshr$sendRsToDmaC_getRq[19] &&
!cache_cRqMshr$sendRsToDmaC_getRq[20] &&
!cache_cRqMshr$sendRsToDmaC_getRq[21] &&
!cache_cRqMshr$sendRsToDmaC_getRq[22] &&
!cache_cRqMshr$sendRsToDmaC_getRq[23] &&
!cache_cRqMshr$sendRsToDmaC_getRq[24] &&
!cache_cRqMshr$sendRsToDmaC_getRq[25] &&
!cache_cRqMshr$sendRsToDmaC_getRq[26] &&
!cache_cRqMshr$sendRsToDmaC_getRq[27] &&
!cache_cRqMshr$sendRsToDmaC_getRq[28] &&
!cache_cRqMshr$sendRsToDmaC_getRq[29] &&
!cache_cRqMshr$sendRsToDmaC_getRq[30] &&
!cache_cRqMshr$sendRsToDmaC_getRq[31] &&
!cache_cRqMshr$sendRsToDmaC_getRq[32] &&
!cache_cRqMshr$sendRsToDmaC_getRq[33] &&
!cache_cRqMshr$sendRsToDmaC_getRq[34] &&
!cache_cRqMshr$sendRsToDmaC_getRq[35] &&
!cache_cRqMshr$sendRsToDmaC_getRq[36] &&
!cache_cRqMshr$sendRsToDmaC_getRq[37] &&
!cache_cRqMshr$sendRsToDmaC_getRq[38] &&
!cache_cRqMshr$sendRsToDmaC_getRq[39] &&
!cache_cRqMshr$sendRsToDmaC_getRq[40] &&
!cache_cRqMshr$sendRsToDmaC_getRq[41] &&
!cache_cRqMshr$sendRsToDmaC_getRq[42] &&
!cache_cRqMshr$sendRsToDmaC_getRq[43] &&
!cache_cRqMshr$sendRsToDmaC_getRq[44] &&
!cache_cRqMshr$sendRsToDmaC_getRq[45] &&
!cache_cRqMshr$sendRsToDmaC_getRq[46] &&
!cache_cRqMshr$sendRsToDmaC_getRq[47] &&
!cache_cRqMshr$sendRsToDmaC_getRq[48] &&
!cache_cRqMshr$sendRsToDmaC_getRq[49] &&
!cache_cRqMshr$sendRsToDmaC_getRq[50] &&
!cache_cRqMshr$sendRsToDmaC_getRq[51] &&
!cache_cRqMshr$sendRsToDmaC_getRq[52] &&
!cache_cRqMshr$sendRsToDmaC_getRq[53] &&
!cache_cRqMshr$sendRsToDmaC_getRq[54] &&
!cache_cRqMshr$sendRsToDmaC_getRq[55] &&
!cache_cRqMshr$sendRsToDmaC_getRq[56] &&
!cache_cRqMshr$sendRsToDmaC_getRq[57] &&
!cache_cRqMshr$sendRsToDmaC_getRq[58] &&
!cache_cRqMshr$sendRsToDmaC_getRq[59] &&
!cache_cRqMshr$sendRsToDmaC_getRq[60] &&
!cache_cRqMshr$sendRsToDmaC_getRq[61] &&
!cache_cRqMshr$sendRsToDmaC_getRq[62] &&
!cache_cRqMshr$sendRsToDmaC_getRq[63] &&
!cache_cRqMshr$sendRsToDmaC_getRq[64] &&
!cache_cRqMshr$sendRsToDmaC_getRq[65] &&
!cache_cRqMshr$sendRsToDmaC_getRq[66] &&
!cache_cRqMshr$sendRsToDmaC_getRq[67] &&
!cache_cRqMshr$sendRsToDmaC_getRq[68] &&
!cache_cRqMshr$sendRsToDmaC_getRq[69] &&
!cache_cRqMshr$sendRsToDmaC_getRq[70] &&
!cache_cRqMshr$sendRsToDmaC_getRq[71] &&
!cache_cRqMshr$sendRsToDmaC_getRq[72] &&
!cache_cRqMshr$sendRsToDmaC_getRq[73] &&
!cache_cRqMshr$sendRsToDmaC_getRq[74] &&
!cache_cRqMshr$sendRsToDmaC_getRq[75] &&
!cache_cRqMshr$sendRsToDmaC_getRq[76] &&
!cache_cRqMshr$sendRsToDmaC_getRq[77] &&
!cache_cRqMshr$sendRsToDmaC_getRq[78] &&
!cache_cRqMshr$sendRsToDmaC_getRq[79] &&
!cache_cRqMshr$sendRsToDmaC_getRq[80] ||
cache_cRqMshr$sendRsToDmaC_getRq[85:84] != 2'd3))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getState != 3'd5)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1191, column 44\nowner is myself, must be swapped in");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getState != 3'd5)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1195, column 21\ncRq swapped in, tag must match, cs > I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3195)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 893, column 38\nmust match pipe out cRq idx");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3195)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3199)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 896, column 13\ncRqHit but tag or cs incorrect");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3199)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3268)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 898, column 74\ntoState should match byteEn");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3268)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3274)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 907, column 13\ndma write should carry valid data");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3274)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3278)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1082, column 17\ntag match and cs > I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3278)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3284)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1087, column 36\nwaitP must be false");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
cache_pipeline_first__581_BIT_517_582_AND_cach_ETC___d3284)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3287)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 835, column 38\nmust match pipe out cRq idx");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3287)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3290)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 841, column 14\ncRqHit but tag or cs incorrect");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3290)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3295)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1047, column 36\nwaitP must be false");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d3295)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3299)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1054, column 56\ndir should be all I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
NOT_cache_cRqMshr_pipelineResp_getRq_IF_cache__ETC___d3299)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getState != 3'd1)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1157, column 42\nowner is other, must first time go through tag match");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
cache_cRqMshr$pipelineResp_getState != 3'd1)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
(cache_pipeline$first[525:524] == 2'd0 ||
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1160, column 22\ncRq should hit in tag match");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
(cache_pipeline$first[525:524] == 2'd0 ||
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
!cache_cRqMshr$pipelineResp_searchEndOfChain[4] &&
!cache_pipeline$first[512])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1185, column 48\nline must be replacing");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && cache_pipeline$first[517] &&
!cache_pipeline_first__581_BITS_516_TO_513_583__ETC___d2588 &&
!cache_cRqMshr$pipelineResp_searchEndOfChain[4] &&
!cache_pipeline$first[512])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3316)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 893, column 38\nmust match pipe out cRq idx");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3316)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3320)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 898, column 74\ntoState should match byteEn");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3320)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3324)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 907, column 13\ndma write should carry valid data");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3324)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3328)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1087, column 36\nwaitP must be false");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3328)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3340)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1308, column 53\nshould not have any rep succ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3340)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3345)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 835, column 38\nmust match pipe out cRq idx");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3345)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3351)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1047, column 36\nwaitP must be false");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3351)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && !cache_pipeline$first[517] &&
NOT_cache_cRqMshr_pipelineResp_searchEndOfChai_ETC___d3353)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1054, column 56\ndir should be all I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq && !cache_pipeline$first[517] &&
NOT_cache_cRqMshr_pipelineResp_searchEndOfChai_ETC___d3353)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3359)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1117, column 45\ncannot have rep succ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRq &&
NOT_cache_pipeline_first__581_BIT_517_582_105__ETC___d3359)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs && !cache_pipeline$first[517])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1318, column 43\nmRs owner must match some cRq");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs && !cache_pipeline$first[517])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
cache_cRqMshr$pipelineResp_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1329, column 37\nonly child req gets mem resp that refills the cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
cache_cRqMshr$pipelineResp_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
(cache_pipeline$first[525:524] <
cache_cRqMshr$pipelineResp_getRq[85:84] ||
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1331, column 13\nmRs must be tag match & have enough cs");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
(cache_pipeline$first[525:524] <
cache_cRqMshr$pipelineResp_getRq[85:84] ||
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
(cache_pipeline$first[519:518] != 2'd0 ||
cache_pipeline$first[521:520] != 2'd0 ||
cache_pipeline$first[523:522] != 2'd0))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1333, column 48\nall children must be I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
(cache_pipeline$first[519:518] != 2'd0 ||
cache_pipeline$first[521:520] != 2'd0 ||
cache_pipeline$first[523:522] != 2'd0))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs && cache_pipeline$first[512])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1334, column 37\nmRs cannot hit on replacing line");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs && cache_pipeline$first[512])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
NOT_cache_cRqMshr_pipelineResp_getSlot_IF_cach_ETC___d3369)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1335, column 44\nmRs should hit on way in MSHR slot");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
NOT_cache_cRqMshr_pipelineResp_getSlot_IF_cach_ETC___d3369)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
!cache_cRqMshr$pipelineResp_getSlot[12])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1336, column 31\nmRs should match cRq which is waiting for it");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
!cache_cRqMshr$pipelineResp_getSlot[12])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
(cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1338, column 13\ncRq that needs mRs should not have children to wait for");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
(cache_cRqMshr$pipelineResp_getSlot[3:2] != 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[7:6] != 2'd0 ||
cache_cRqMshr$pipelineResp_getSlot[11:10] != 2'd0))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d3798)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 835, column 38\nmust match pipe out cRq idx");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
NOT_cache_pipeline_first__581_BITS_516_TO_513__ETC___d3798)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
cache_cRqMshr$pipelineResp_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 836, column 37\nshould be cRq from child");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
cache_cRqMshr$pipelineResp_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 841, column 14\ncRqHit but tag or cs incorrect");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_mRs &&
(!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646 ||
cache_pipeline$first[525:524] == 2'd0))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[525:524] == 2'd0)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1352, column 35\ncRs should hit on a line");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs &&
cache_pipeline$first[525:524] == 2'd0)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
NOT_cache_cRqMshr_pipelineResp_getSlot_IF_cach_ETC___d3369)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1365, column 48\ncRs way should match MSHR slot");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
NOT_cache_cRqMshr_pipelineResp_getSlot_IF_cach_ETC___d3369)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1369, column 45\nonly child req do replace");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getState != 3'd2)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1370, column 48\nmust be waiting for old tag");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getState != 3'd2)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getSlot[12])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1371, column 40\ncannot wait for parent while replacing");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getSlot[12])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getSlot[60:13] !=
cache_pipeline$first[573:526])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1372, column 56\nshould match replacing tag");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getSlot[60:13] !=
cache_pipeline$first[573:526])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 &&
cache_cRqMshr$pipelineResp_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 953, column 37\nonly cRq from child can evict a line");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 &&
cache_cRqMshr$pipelineResp_getRq[16])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 &&
(cache_pipeline$first[519:518] != 2'd0 ||
cache_pipeline$first[521:520] != 2'd0 ||
cache_pipeline$first[523:522] != 2'd0 ||
cache_pipeline$first[525:524] == 2'd0))
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 955, column 13\nonly evict valid line which has no children");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
cache_pipeline$first[512] &&
IF_SEL_ARR_cache_pipeline_first__581_BITS_519__ETC___d3488 &&
(cache_pipeline$first[519:518] != 2'd0 ||
cache_pipeline$first[521:520] != 2'd0 ||
cache_pipeline$first[523:522] != 2'd0 ||
cache_pipeline$first[525:524] == 2'd0))
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getState != 3'd3)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1405, column 44\nmust be waiting for child/parent state");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getState != 3'd3)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1406, column 60\ncRq tag should match cRs hit line");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
!cache_pipeline_first__581_BITS_573_TO_526_644__ETC___d2646)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getSlot[12])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 1407, column 40\ncs > I, so cannot wait for memory");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
cache_cRqMshr$pipelineResp_getSlot[12])
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3801)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 893, column 38\nmust match pipe out cRq idx");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3801)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3804)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 896, column 13\ncRqHit but tag or cs incorrect");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3804)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3809)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 898, column 74\ntoState should match byteEn");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3809)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3814)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 907, column 13\ndma write should carry valid data");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3814)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3827)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 835, column 38\nmust match pipe out cRq idx");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
NOT_cache_pipeline_first__581_BIT_512_308_309__ETC___d3827)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3830)
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 841, column 14\ncRqHit but tag or cs incorrect");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_pipelineResp_cRs && cache_pipeline$first[517] &&
!cache_pipeline$first[512] &&
IF_SEL_ARR_cache_cRqMshr_pipelineResp_getSlot__ETC___d3830)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_mRsTransfer && cache_cRqMshr$transfer_getRq[16])
$display("Dynamic assertion failed: \"../../src_Core/Near_Mem_VM_WB_L1_L2/src_LLCache/coherence/src/LLBank.bsv\", line 491, column 37\nrefill mem resp must be for child req");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_cache_mRsTransfer && cache_cRqMshr$transfer_getRq[16])
$finish(32'd0);
end
// synopsys translate_on
endmodule // mkLLCache
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S18KAPWR_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S18KAPWR_BLACKBOX_V
/**
* dlybuf4s18kapwr: Delay Buffer 4-stage 0.18um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s18kapwr (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S18KAPWR_BLACKBOX_V
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_phy_dm_iob.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module places the data mask signals into the IOBs.
//Reference:
//Revision History:
// Rev 1.1 - To fix timing issues with Synplicity 9.6.1, syn_preserve
// attribute added for the instance u_dm_ce. PK. 11/11/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_dm_iob
(
input clk90,
input dm_ce,
input mask_data_rise,
input mask_data_fall,
output ddr_dm
);
wire dm_out;
wire dm_ce_r;
FDRSE_1 u_dm_ce
(
.Q (dm_ce_r),
.C (clk90),
.CE (1'b1),
.D (dm_ce),
.R (1'b0),
.S (1'b0)
) /* synthesis syn_preserve=1 */;
ODDR #
(
.SRTYPE("SYNC"),
.DDR_CLK_EDGE("SAME_EDGE")
)
u_oddr_dm
(
.Q (dm_out),
.C (clk90),
.CE (dm_ce_r),
.D1 (mask_data_rise),
.D2 (mask_data_fall),
.R (1'b0),
.S (1'b0)
);
OBUF u_obuf_dm
(
.I (dm_out),
.O (ddr_dm)
);
endmodule
|
`timescale 1ns / 1ns
module gui(clock,
reset,
keys,
mode,
//playback_keys
colour,
x,
y,
plot);
input clock;
input reset;
input [3:0] keys;
// input [3:0] playback_keys;
// input [1:0] mode;
output [2:0] colour;
output [7:0] x;
output [6:0] y;
output plot;
wire redraw;
wire [3:0] keys_pressed;
wire [14:0] clock_count;
controlgui g(
.clock(clock),
.reset(reset),
.plot(plot),
.keys(keys),
.redraw(redraw),
.clock_count(clock_count),
.keys_pressed(keys_pressed)
);
datapathgui d(
.clock(clock),
.reset(reset),
.redraw(redraw),
.keys_pressed(keys_pressed),
.playback_keys(playback_keys),
.clock_count(clock_count),
// .mode(mode),
.colour(colour),
.x(x),
.y(y)
);
endmodule
module controlgui(clock, reset, keys, plot, redraw, clock_count, keys_pressed);
input clock, reset;
input [3:0] keys;
//Remove unnecessary regs
output reg [3:0] keys_pressed;
output reg plot, redraw;
output reg [14:0] clock_count;
reg [2:0] current_state, next_state;
localparam REDRAW = 3'b000,
STATIONARY = 3'b001,
KEY_ONE_PRESSED = 3'b010,
KEY_TWO_PRESSED = 3'b011,
KEY_THREE_PRESSED = 3'b100,
KEY_FOUR_PRESSED = 3'b101;
/*
* Can be reset for testing purposes
*/
parameter PIXEL_COUNT = 15'b111100010100001;
always @(posedge clock) begin
if (!reset) begin
current_state <= REDRAW;
end
else begin
current_state <= next_state;
if (current_state != STATIONARY) begin
clock_count <= clock_count + 1'b1;
end
else begin
clock_count <= 15'b0;
end
end
end
always @(*)
begin: state_table
case (current_state)
REDRAW: next_state = clock_count == PIXEL_COUNT ? STATIONARY : REDRAW;
STATIONARY: begin
if (keys[0] == 1'b1) begin
next_state = KEY_ONE_PRESSED;
end
else if (keys[1] == 1'b1) begin
next_state = KEY_TWO_PRESSED;
end
else if (keys[2] == 1'b1) begin
next_state = KEY_THREE_PRESSED;
end
else if (keys[3] == 1'b1) begin
next_state = KEY_FOUR_PRESSED;
end
else begin
next_state = REDRAW;
end
end
KEY_ONE_PRESSED: next_state = clock_count == PIXEL_COUNT ? STATIONARY : KEY_ONE_PRESSED;
KEY_TWO_PRESSED:
default: next_state = REDRAW;
endcase
end
//datapath control signals
always @(*)
begin: signals
plot = 1'b0;
keys_pressed = 4'b0;
case (current_state)
REDRAW: begin
plot = 1'b1;
redraw = 1'b1;
end
KEY_ONE_PRESSED: begin
plot = 1'b1;
redraw = 1'b1;
keys_pressed = 4'b0001;
end
KEY_TWO_PRESSED: begin
plot = 1'b1;
redraw = 1'b1;
keys_pressed = 4'b0010;
end
KEY_THREE_PRESSED: begin
plot = 1'b1;
redraw = 1'b1;
keys_pressed = 4'b0100;
end
KEY_FOUR_PRESSED: begin
plot = 1'b1;
redraw = 1'b1;
keys_pressed = 4'b1000;
end
endcase
end
endmodule
module datapathgui(clock,
reset,
redraw,
colour,
// mode,
x,
y,
clock_count);
input clock, reset, redraw;
// input [1:0] mode;
input [14:0] clock_count;
input [3:0] keys_pressed;
//Remove unnecessary regs
output reg [2:0] colour;
output reg [7:0] x;
output reg [6:0] y;
/*
* Don't need these
*/
reg [7:0] temp_x;
reg [6:0] temp_y;
localparam WHITE = 3'b111,
BLACK = 3'b000,
BLUE = 3'b001,
RED = 3'b100;
parameter FIRST_DIVIDER = 8'b00100111;
parameter SECOND_DIVIDER = 8'b01001111;
parameter THIRD_DIVIDER = 8'b01110111;
parameter MAX_X = 8'b10100000;
parameter MAX_Y = 7'b1111000;
always @(posedge clock) begin
if (!reset) begin
x <= 8'b0;
y <= 8'b0;
colour <= 3'b0;
temp_x <= 8'b0;
temp_y <= 7'b0;
end
else if (redraw) begin
// if (clock_count[1:0] < 3'b100 & clock_count[9:8] < 3'b100 & mode[1:0] > 1'b0) begin
// if (mode[1:0] == 2'b01) begin
// colour <= RED; //RECORDING
// end
// else begin
// colour <= GREEN; //PLAYBACK
// end
// end
if (clock_count[7:0] == FIRST_DIVIDER || clock_count[7:0] == SECOND_DIVIDER || clock_count[7:0] == THIRD_DIVIDER) begin
colour <= BLACK;
end
else begin
if (keys_pressed == 4'b0001 & clock_count[7:0] < FIRST_DIVIDER) begin // First key
colour <= BLUE;
end
else if (keys_pressed == 4'b0010 & clock_count[7:0] > FIRST_DIVIDER & clock_count[7:0] < SECOND_DIVIDER) begin // Second key
colour <= BLUE;
end
else if (keys_pressed == 4'b0100 & clock_count[7:0] > SECOND_DIVIDER & clock_count[7:0] < THIRD_DIVIDER) begin // Third key
colour <= BLUE;
end
else if (keys_pressed == 4'b1000 & clock_count[7:0] > THIRD_DIVIDER ) begin // Fourth key
colour <= BLUE;
end
else begin
colour <= WHITE;
end
end
if (!(clock_count[7:0] > MAX_X)) begin
x <= temp_x + clock_count[7:0];
end
if (!(clock_count[14:8] > MAX_Y)) begin
y <= temp_y + clock_count[14:8];
end
end
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : cpu.v
-- DESCRIPTION : CPUgbvW
[
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
`include "isa.h"
`include "cpu.h"
`include "bus.h"
`include "spm.h"
module cpu (
input wire clk,
input wire clk_,
input wire reset,
input wire [`WordDataBus] if_bus_rd_data,
input wire if_bus_rdy_,
input wire if_bus_grnt_,
output wire if_bus_req_,
output wire [`WordAddrBus] if_bus_addr,
output wire if_bus_as_,
output wire if_bus_rw,
output wire [`WordDataBus] if_bus_wr_data,
input wire [`WordDataBus] mem_bus_rd_data,
input wire mem_bus_rdy_,
input wire mem_bus_grnt_,
output wire mem_bus_req_,
output wire [`WordAddrBus] mem_bus_addr,
output wire mem_bus_as_,
output wire mem_bus_rw,
output wire [`WordDataBus] mem_bus_wr_data,
input wire [`CPU_IRQ_CH-1:0] cpu_irq
);
wire [`WordAddrBus] if_pc;
wire [`WordDataBus] if_insn;
wire if_en;
wire [`WordAddrBus] id_pc;
wire id_en;
wire [`AluOpBus] id_alu_op;
wire [`WordDataBus] id_alu_in_0;
wire [`WordDataBus] id_alu_in_1;
wire id_br_flag;
wire [`MemOpBus] id_mem_op;
wire [`WordDataBus] id_mem_wr_data;
wire [`CtrlOpBus] id_ctrl_op;
wire [`RegAddrBus] id_dst_addr;
wire id_gpr_we_;
wire [`IsaExpBus] id_exp_code;
wire [`WordAddrBus] ex_pc;
wire ex_en;
wire ex_br_flag;
wire [`MemOpBus] ex_mem_op;
wire [`WordDataBus] ex_mem_wr_data;
wire [`CtrlOpBus] ex_ctrl_op;
wire [`RegAddrBus] ex_dst_addr;
wire ex_gpr_we_;
wire [`IsaExpBus] ex_exp_code;
wire [`WordDataBus] ex_out;
wire [`WordAddrBus] mem_pc;
wire mem_en;
wire mem_br_flag;
wire [`CtrlOpBus] mem_ctrl_op;
wire [`RegAddrBus] mem_dst_addr;
wire mem_gpr_we_;
wire [`IsaExpBus] mem_exp_code;
wire [`WordDataBus] mem_out;
wire if_stall;
wire id_stall;
wire ex_stall;
wire mem_stall;
wire if_flush;
wire id_flush;
wire ex_flush;
wire mem_flush;
wire if_busy;
wire mem_busy;
wire [`WordAddrBus] new_pc;
wire [`WordAddrBus] br_addr;
wire br_taken;
wire ld_hazard;
wire [`WordDataBus] gpr_rd_data_0;
wire [`WordDataBus] gpr_rd_data_1;
wire [`RegAddrBus] gpr_rd_addr_0;
wire [`RegAddrBus] gpr_rd_addr_1;
wire [`CpuExeModeBus] exe_mode;
wire [`WordDataBus] creg_rd_data;
wire [`RegAddrBus] creg_rd_addr;
wire int_detect;
wire [`WordDataBus] if_spm_rd_data;
wire [`WordAddrBus] if_spm_addr;
wire if_spm_as_;
wire if_spm_rw;
wire [`WordDataBus] if_spm_wr_data;
wire [`WordDataBus] mem_spm_rd_data;
wire [`WordAddrBus] mem_spm_addr;
wire mem_spm_as_;
wire mem_spm_rw;
wire [`WordDataBus] mem_spm_wr_data;
wire [`WordDataBus] ex_fwd_data;
wire [`WordDataBus] mem_fwd_data;
if_stage if_stage (
.clk (clk),
.reset (reset),
.spm_rd_data (if_spm_rd_data),
.spm_addr (if_spm_addr),
.spm_as_ (if_spm_as_),
.spm_rw (if_spm_rw),
.spm_wr_data (if_spm_wr_data),
.bus_rd_data (if_bus_rd_data),
.bus_rdy_ (if_bus_rdy_),
.bus_grnt_ (if_bus_grnt_),
.bus_req_ (if_bus_req_),
.bus_addr (if_bus_addr),
.bus_as_ (if_bus_as_),
.bus_rw (if_bus_rw),
.bus_wr_data (if_bus_wr_data),
.stall (if_stall),
.flush (if_flush),
.new_pc (new_pc),
.br_taken (br_taken),
.br_addr (br_addr),
.busy (if_busy),
.if_pc (if_pc),
.if_insn (if_insn),
.if_en (if_en)
);
id_stage id_stage (
.clk (clk),
.reset (reset),
.gpr_rd_data_0 (gpr_rd_data_0),
.gpr_rd_data_1 (gpr_rd_data_1),
.gpr_rd_addr_0 (gpr_rd_addr_0),
.gpr_rd_addr_1 (gpr_rd_addr_1),
.ex_en (ex_en),
.ex_fwd_data (ex_fwd_data),
.ex_dst_addr (ex_dst_addr),
.ex_gpr_we_ (ex_gpr_we_),
.mem_fwd_data (mem_fwd_data),
.exe_mode (exe_mode),
.creg_rd_data (creg_rd_data),
.creg_rd_addr (creg_rd_addr),
.stall (id_stall),
.flush (id_flush),
.br_addr (br_addr),
.br_taken (br_taken),
.ld_hazard (ld_hazard),
.if_pc (if_pc),
.if_insn (if_insn),
.if_en (if_en),
.id_pc (id_pc),
.id_en (id_en),
.id_alu_op (id_alu_op),
.id_alu_in_0 (id_alu_in_0),
.id_alu_in_1 (id_alu_in_1),
.id_br_flag (id_br_flag),
.id_mem_op (id_mem_op),
.id_mem_wr_data (id_mem_wr_data),
.id_ctrl_op (id_ctrl_op),
.id_dst_addr (id_dst_addr),
.id_gpr_we_ (id_gpr_we_),
.id_exp_code (id_exp_code)
);
ex_stage ex_stage (
.clk (clk),
.reset (reset),
.stall (ex_stall),
.flush (ex_flush),
.int_detect (int_detect),
.fwd_data (ex_fwd_data),
.id_pc (id_pc),
.id_en (id_en),
.id_alu_op (id_alu_op),
.id_alu_in_0 (id_alu_in_0),
.id_alu_in_1 (id_alu_in_1),
.id_br_flag (id_br_flag),
.id_mem_op (id_mem_op),
.id_mem_wr_data (id_mem_wr_data),
.id_ctrl_op (id_ctrl_op),
.id_dst_addr (id_dst_addr),
.id_gpr_we_ (id_gpr_we_),
.id_exp_code (id_exp_code),
.ex_pc (ex_pc),
.ex_en (ex_en),
.ex_br_flag (ex_br_flag),
.ex_mem_op (ex_mem_op),
.ex_mem_wr_data (ex_mem_wr_data),
.ex_ctrl_op (ex_ctrl_op),
.ex_dst_addr (ex_dst_addr),
.ex_gpr_we_ (ex_gpr_we_),
.ex_exp_code (ex_exp_code),
.ex_out (ex_out)
);
mem_stage mem_stage (
.clk (clk),
.reset (reset),
.stall (mem_stall),
.flush (mem_flush),
.busy (mem_busy),
.fwd_data (mem_fwd_data),
.spm_rd_data (mem_spm_rd_data),
.spm_addr (mem_spm_addr),
.spm_as_ (mem_spm_as_),
.spm_rw (mem_spm_rw),
.spm_wr_data (mem_spm_wr_data),
.bus_rd_data (mem_bus_rd_data),
.bus_rdy_ (mem_bus_rdy_),
.bus_grnt_ (mem_bus_grnt_),
.bus_req_ (mem_bus_req_),
.bus_addr (mem_bus_addr),
.bus_as_ (mem_bus_as_),
.bus_rw (mem_bus_rw),
.bus_wr_data (mem_bus_wr_data),
.ex_pc (ex_pc),
.ex_en (ex_en),
.ex_br_flag (ex_br_flag),
.ex_mem_op (ex_mem_op),
.ex_mem_wr_data (ex_mem_wr_data),
.ex_ctrl_op (ex_ctrl_op),
.ex_dst_addr (ex_dst_addr),
.ex_gpr_we_ (ex_gpr_we_),
.ex_exp_code (ex_exp_code),
.ex_out (ex_out),
.mem_pc (mem_pc),
.mem_en (mem_en),
.mem_br_flag (mem_br_flag),
.mem_ctrl_op (mem_ctrl_op),
.mem_dst_addr (mem_dst_addr),
.mem_gpr_we_ (mem_gpr_we_),
.mem_exp_code (mem_exp_code),
.mem_out (mem_out)
);
ctrl ctrl (
.clk (clk),
.reset (reset),
.creg_rd_addr (creg_rd_addr),
.creg_rd_data (creg_rd_data),
.exe_mode (exe_mode),
.irq (cpu_irq),
.int_detect (int_detect),
.id_pc (id_pc),
.mem_pc (mem_pc),
.mem_en (mem_en),
.mem_br_flag (mem_br_flag),
.mem_ctrl_op (mem_ctrl_op),
.mem_dst_addr (mem_dst_addr),
.mem_exp_code (mem_exp_code),
.mem_out (mem_out),
.if_busy (if_busy),
.ld_hazard (ld_hazard),
.mem_busy (mem_busy),
.if_stall (if_stall),
.id_stall (id_stall),
.ex_stall (ex_stall),
.mem_stall (mem_stall),
.if_flush (if_flush),
.id_flush (id_flush),
.ex_flush (ex_flush),
.mem_flush (mem_flush),
.new_pc (new_pc)
);
gpr gpr (
.clk (clk),
.reset (reset),
.rd_addr_0 (gpr_rd_addr_0),
.rd_data_0 (gpr_rd_data_0),
.rd_addr_1 (gpr_rd_addr_1),
.rd_data_1 (gpr_rd_data_1),
.we_ (mem_gpr_we_),
.wr_addr (mem_dst_addr),
.wr_data (mem_out)
);
spm spm (
.clk (clk_),
.if_spm_addr (if_spm_addr[`SpmAddrLoc]),
.if_spm_as_ (if_spm_as_),
.if_spm_rw (if_spm_rw),
.if_spm_wr_data (if_spm_wr_data),
.if_spm_rd_data (if_spm_rd_data),
.mem_spm_addr (mem_spm_addr[`SpmAddrLoc]),
.mem_spm_as_ (mem_spm_as_),
.mem_spm_rw (mem_spm_rw),
.mem_spm_wr_data (mem_spm_wr_data),
.mem_spm_rd_data (mem_spm_rd_data)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_pipe_rate.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Rate Module --------------------------------------------------
module pcieCore_pipe_rate #
(
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
)
(
//---------- Input -------------------------------------
input RATE_CLK,
input RATE_RST_N,
input RATE_RST_IDLE,
input RATE_ACTIVE_LANE,
input [ 1:0] RATE_RATE_IN,
input RATE_CPLLLOCK,
input RATE_QPLLLOCK,
input RATE_MMCM_LOCK,
input RATE_DRP_DONE,
input RATE_RXPMARESETDONE,
input RATE_TXRESETDONE,
input RATE_RXRESETDONE,
input RATE_TXRATEDONE,
input RATE_RXRATEDONE,
input RATE_PHYSTATUS,
input RATE_RESETOVRD_DONE,
input RATE_TXSYNC_DONE,
input RATE_RXSYNC_DONE,
//---------- Output ------------------------------------
output RATE_CPLLPD,
output RATE_QPLLPD,
output RATE_CPLLRESET,
output RATE_QPLLRESET,
output RATE_TXPMARESET,
output RATE_RXPMARESET,
output RATE_DRP_START,
output [ 1:0] RATE_SYSCLKSEL,
output RATE_PCLK_SEL,
output RATE_GEN3,
output RATE_DRP_X16X20_MODE,
output RATE_DRP_X16,
output [ 2:0] RATE_RATE_OUT,
output RATE_RESETOVRD_START,
output RATE_TXSYNC_START,
output RATE_DONE,
output RATE_RXSYNC_START,
output RATE_RXSYNC,
output RATE_IDLE,
output [ 4:0] RATE_FSM
);
//---------- Input FF or Buffer ------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2;
//---------- Internal Signals --------------------------
wire pll_lock;
wire [ 2:0] rate;
reg [ 3:0] txdata_wait_cnt = 4'd0;
reg txratedone = 1'd0;
reg rxratedone = 1'd0;
reg phystatus = 1'd0;
reg ratedone = 1'd0;
reg gen3_exit = 1'd0;
//---------- Output FF or Buffer -----------------------
reg cpllpd = 1'd0;
reg qpllpd = 1'd0;
reg cpllreset = 1'd0;
reg qpllreset = 1'd0;
reg txpmareset = 1'd0;
reg rxpmareset = 1'd0;
reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
reg gen3 = 1'd0;
reg pclk_sel = 1'd0;
reg [ 2:0] rate_out = 3'd0;
reg drp_start = 1'd0;
reg drp_x16x20_mode = 1'd0;
reg drp_x16 = 1'd0;
reg [ 4:0] fsm = 0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_PLL_PU = 1; // Gen 3 only
localparam FSM_PLL_PURESET = 2; // Gen 3 only
localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only
localparam FSM_DRP_X16_GEN3_START = 4;
localparam FSM_DRP_X16_GEN3_DONE = 5;
localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only
localparam FSM_PLL_SEL = 7; // Gen 3 or reset only
localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only
localparam FSM_DRP_START = 9; // Gen 3 or reset only
localparam FSM_DRP_DONE = 10; // Gen 3 or reset only
localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only
localparam FSM_PMARESET_DONE = 12; // Gen 3 only
localparam FSM_TXDATA_WAIT = 13;
localparam FSM_PCLK_SEL = 14;
localparam FSM_DRP_X16_START = 15;
localparam FSM_DRP_X16_DONE = 16;
localparam FSM_RATE_SEL = 17;
localparam FSM_RXPMARESETDONE = 18;
localparam FSM_DRP_X20_START = 19;
localparam FSM_DRP_X20_DONE = 20;
localparam FSM_RATE_DONE = 21;
localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only
localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only
localparam FSM_PLL_PDRESET = 24;
localparam FSM_PLL_PD = 25;
localparam FSM_TXSYNC_START = 26;
localparam FSM_TXSYNC_DONE = 27;
localparam FSM_DONE = 28; // Must sync value to pipe_user.v
localparam FSM_RXSYNC_START = 29; // Gen 3 only
localparam FSM_RXSYNC_DONE = 30; // Gen 3 only
//---------- Input FF ----------------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= 1'd0;
rate_in_reg1 <= 2'd0;
cplllock_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
drp_done_reg1 <= 1'd0;
rxpmaresetdone_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txratedone_reg1 <= 1'd0;
rxratedone_reg1 <= 1'd0;
phystatus_reg1 <= 1'd0;
resetovrd_done_reg1 <= 1'd0;
txsync_done_reg1 <= 1'd0;
rxsync_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= 1'd0;
rate_in_reg2 <= 2'd0;
cplllock_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
drp_done_reg2 <= 1'd0;
rxpmaresetdone_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txratedone_reg2 <= 1'd0;
rxratedone_reg2 <= 1'd0;
phystatus_reg2 <= 1'd0;
resetovrd_done_reg2 <= 1'd0;
txsync_done_reg2 <= 1'd0;
rxsync_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= RATE_RST_IDLE;
rate_in_reg1 <= RATE_RATE_IN;
cplllock_reg1 <= RATE_CPLLLOCK;
qplllock_reg1 <= RATE_QPLLLOCK;
mmcm_lock_reg1 <= RATE_MMCM_LOCK;
drp_done_reg1 <= RATE_DRP_DONE;
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
txresetdone_reg1 <= RATE_TXRESETDONE;
rxresetdone_reg1 <= RATE_RXRESETDONE;
txratedone_reg1 <= RATE_TXRATEDONE;
rxratedone_reg1 <= RATE_RXRATEDONE;
phystatus_reg1 <= RATE_PHYSTATUS;
resetovrd_done_reg1 <= RATE_RESETOVRD_DONE;
txsync_done_reg1 <= RATE_TXSYNC_DONE;
rxsync_done_reg1 <= RATE_RXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= rst_idle_reg1;
rate_in_reg2 <= rate_in_reg1;
cplllock_reg2 <= cplllock_reg1;
qplllock_reg2 <= qplllock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txratedone_reg2 <= txratedone_reg1;
rxratedone_reg2 <= rxratedone_reg1;
phystatus_reg2 <= phystatus_reg1;
resetovrd_done_reg2 <= resetovrd_done_reg1;
txsync_done_reg2 <= txsync_done_reg1;
rxsync_done_reg2 <= rxsync_done_reg1;
end
end
//---------- Select CPLL or QPLL Lock ------------------------------------------
// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen3 : Wait for QPLL lock
//------------------------------------------------------------------------------
assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2;
//---------- Select Rate -------------------------------------------------------
// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2
// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1
// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1
//------------------------------------------------------------------------------
assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 :
(rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0;
//---------- TXDATA Wait Counter -----------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
txdata_wait_cnt <= 4'd0;
else
//---------- Increment Wait Counter ----------------
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
//---------- Hold Wait Counter ---------------------
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt;
//---------- Reset Wait Counter --------------------
else
txdata_wait_cnt <= 4'd0;
end
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
else
begin
if (fsm == FSM_RATE_DONE)
begin
//---------- Latch TXRATEDONE ------------------
if (txratedone_reg2)
txratedone <= 1'd1;
else
txratedone <= txratedone;
//---------- Latch RXRATEDONE ------------------
if (rxratedone_reg2)
rxratedone <= 1'd1;
else
rxratedone <= rxratedone;
//---------- Latch PHYSTATUS -------------------
if (phystatus_reg2)
phystatus <= 1'd1;
else
phystatus <= phystatus;
//---------- Latch Rate Done -------------------
if (rxratedone && txratedone && phystatus)
ratedone <= 1'd1;
else
ratedone <= ratedone;
end
else
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
end
end
//---------- PIPE Rate FSM -----------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Detect Rate Change ----------------
if (rate_in_reg2 != rate_in_reg1)
begin
fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT;
gen3_exit <= (rate_in_reg2 == 2'd2);
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
end
//---------- Power-up PLL --------------------------
FSM_PLL_PU :
begin
fsm <= FSM_PLL_PURESET;
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= 1'd0;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PLL Resets --------------------
FSM_PLL_PURESET :
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllreset <= 1'd0;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for PLL Lock ---------------------
FSM_PLL_LOCK :
begin
fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_GEN3_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_GEN3_DONE :
begin
fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Hold both PMA in Reset ----------------
// Gen1 : Release PMA Reset
// Gen2 : Release PMA Reset
// Gen3 : Hold PMA Reset
//--------------------------------------------------
FSM_PMARESET_HOLD :
begin
fsm <= FSM_PLL_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PLL ----------------------------
// Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen3 : QPLL
//--------------------------------------------------
FSM_PLL_SEL :
begin
fsm <= FSM_MMCM_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Check for MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP -----------------------------
FSM_DRP_START:
begin
fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= (rate_in_reg2 == 2'd2);
rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out);
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP Done ---------------------
FSM_DRP_DONE :
begin
fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PMA Resets --------------------
FSM_PMARESET_RELEASE :
begin
fsm <= FSM_PMARESET_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion
FSM_PMARESET_DONE :
begin
fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TXDATA to TX[P/N] Latency ----
FSM_TXDATA_WAIT :
begin
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PCLK Frequency -----------------
// Gen1 : PCLK = 125 MHz
// Gen2 : PCLK = 250 MHz
// Gen3 : PCLK = 250 MHz
//--------------------------------------------------
FSM_PCLK_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Select Rate ---------------------------
FSM_RATE_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate; // Update [TX/RX]RATE
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE :
begin
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for Rate Change Done -------------
FSM_RATE_DONE :
begin
if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE)
if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit))
fsm <= FSM_RESETOVRD_START;
else
fsm <= FSM_PLL_PDRESET;
else
fsm <= FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Start ------------------
FSM_RESETOVRD_START:
begin
fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Done -------------------
FSM_RESETOVRD_DONE :
begin
fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Hold PLL Not Used in Reset ------------
FSM_PLL_PDRESET :
begin
fsm <= FSM_PLL_PD;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Power-Down PLL Not Used ---------------
FSM_PLL_PD :
begin
fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE);
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START:
begin
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE:
begin
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Rate Change Done ----------------------
FSM_DONE :
begin
fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start RX Sync -------------------------
FSM_RXSYNC_START:
begin
fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RX Sync Done -----------------
FSM_RXSYNC_DONE:
begin
fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
endcase
end
end
//---------- PIPE Rate Output --------------------------------------------------
assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset);
assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset);
assign RATE_TXPMARESET = txpmareset;
assign RATE_RXPMARESET = rxpmareset;
assign RATE_SYSCLKSEL = sysclksel;
//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
assign RATE_DRP_START = drp_start;
//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) ||
// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
assign RATE_DRP_X16X20_MODE = drp_x16x20_mode;
//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
assign RATE_DRP_X16 = drp_x16;
assign RATE_PCLK_SEL = pclk_sel;
assign RATE_GEN3 = gen3;
assign RATE_RATE_OUT = rate_out;
assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START);
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RATE_DONE = (fsm == FSM_DONE);
assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START);
assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE));
assign RATE_IDLE = (fsm == FSM_IDLE);
assign RATE_FSM = fsm;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:13:00 04/24/2015
// Design Name: ALU_16
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_alu.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ALU_16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_alu;
reg clock;
// Inputs
reg [15:0] ALU_data_in1;
reg [15:0] ALU_data_in2;
reg [7:0] ALU_control;
// Outputs
wire [15:0] ALU_data_out;
wire N;
wire Z;
wire C;
wire V;
// Instantiate the Unit Under Test (UUT)
ALU_16 uut (
.clock(clock),
.ALU_data_in1(ALU_data_in1),
.ALU_data_in2(ALU_data_in2),
.ALU_control(ALU_control),
.ALU_data_out(ALU_data_out),
.N(N),
.Z(Z),
.C(C),
.V(V)
);
initial begin
// Initialize Inputs
clock = 0;
ALU_data_in1 = 0;
ALU_data_in2 = 0;
ALU_control = 0;
// Wait 100 ns for global reset to finish
//#100;
check_alu(16'h8007, 16'hc005, 8'h00, 16'h8005, 0, 0, 0, 0);
check_alu(16'h000a, 16'h000c, 8'he6, 16'h8005, 1, 0, 0, 0);
end
task check_alu;
input [15:0] i_a;
input [15:0] i_b;
input [7:0] i_c;
input [15:0] exp_o;
input exp_n;
input exp_z;
input exp_c;
input exp_v;
begin
ALU_data_in1 = i_a;
ALU_data_in2 = i_b;
ALU_control = i_c;
#1;
if ((ALU_data_out !== exp_o) || (N !== exp_n) || (Z !== exp_z) || (C !== exp_c) || (V !== exp_v)) begin
$display("Error @%dns O=%b, eO=%b | N=%b, eN=%b | Z=%b, eZ=%b | C=%b, eC=%b | V=%b, eV=%b", $time, ALU_data_out, exp_o, N, exp_n, Z, exp_z, C, exp_c, V, exp_v);
end
$display ("======================");
end
endtask
always #1 clock = !clock;
endmodule
|
// board has 8 LED segment for display numbers
// print out the current tick which increments
// every number of second based on the clock
// use 4 button switch for reset and toggle of the
// step value. 18 LEDR is used for displaying the
// current step
`define NSEG 8
`define NLEDR 18
module ledhex
(
input wire [3:0] key,
input wire clk,
output reg [`NLEDR-1:0] ledr,
output reg [`NSEG*7-1:0] hex
);
task clear();
integer i;
for (i = 0; i < `NSEG*7; i = i + 1) begin
hex[i] = 1;
end
endtask
task digit(input integer hp, input integer n);
reg [7:0] v;
integer i;
begin
case (n)
0: v = 7'b1000000;
1: v = 7'b1111001;
2: v = 7'b0100100;
3: v = 7'b0110000;
4: v = 7'b0011001;
5: v = 7'b0010010;
6: v = 7'b0000010;
7: v = 7'b1111000;
8: v = 7'b0000000;
9: v = 7'b0010000;
default: v = 7'b1111111;
endcase
hp = hp*7;
for (i = 0; i < 7; i = i + 1) begin
hex[hp+i] = v[i];
end
end
endtask
task print(input integer n);
integer i;
begin
clear();
for (i = 0; i < `NSEG; i = i + 1) begin
digit(i, n % 10);
n = n / 10;
end
end
endtask
parameter CLK_FREQ = 50_000_000;
parameter EV_MAX = CLK_FREQ / 25;
parameter CNT_MAX = CLK_FREQ;
parameter MAX_NUM = 100_000_000;
reg [31:0] cnt, ev, val, step;
integer i;
initial begin
cnt = 0;
ev = 0;
val = 0;
step = 1;
end
always @ (posedge clk) begin
if (cnt >= CNT_MAX) begin
cnt = 0;
val = (val + step) % MAX_NUM;
end
else
cnt = cnt + 1;
if (ev >= EV_MAX) begin
ev = 0;
if (key[0] == 1'b0)
val = 0;
if (key[1] == 1'b0)
step = 1;
if (key[2] == 1'b0)
step = (step + 1) % MAX_NUM;
if (key[3] == 1'b0 && step > 0)
step = step - 1;
end
else
ev = ev + 1;
for (i = 0; i < `NLEDR; i = i + 1)
ledr[i] = (step >> i) & 1;
print(val);
end
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** Reset logic for HIP +
//*/
module pcie_4243_hip_s4gx_gen2_x8_128_rs_hip (
// inputs:
dlup_exit,
hotrst_exit,
l2_exit,
ltssm,
npor,
pld_clk,
test_sim,
// outputs:
app_rstn,
crst,
srst
)
;
output app_rstn;
output crst;
output srst;
input dlup_exit;
input hotrst_exit;
input l2_exit;
input [ 4: 0] ltssm;
input npor;
input pld_clk;
input test_sim;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg app_rstn;
reg app_rstn0;
reg crst;
reg crst0;
reg [ 4: 0] dl_ltssm_r;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
wire otb0;
wire otb1;
reg [ 10: 0] rsnt_cntn;
reg srst;
reg srst0;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
//pipe line exit conditions
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
dlup_exit_r <= otb1;
hotrst_exit_r <= otb1;
l2_exit_r <= otb1;
exits_r <= otb0;
end
else
begin
dlup_exit_r <= dlup_exit;
hotrst_exit_r <= hotrst_exit;
l2_exit_r <= l2_exit;
exits_r <= (l2_exit_r == 1'b0) | (hotrst_exit_r == 1'b0) | (dlup_exit_r == 1'b0) | (dl_ltssm_r == 5'h10);
end
end
//LTSSM pipeline
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
dl_ltssm_r <= 0;
else
dl_ltssm_r <= ltssm;
end
//reset Synchronizer
always @(posedge pld_clk or negedge npor)
begin
if (npor == 0)
begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end
else
begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
end
end
//reset counter
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
rsnt_cntn <= 0;
else if (exits_r == 1'b1)
rsnt_cntn <= 11'h3f0;
else if (rsnt_cntn != 11'd1024)
rsnt_cntn <= rsnt_cntn + 1;
end
//sync and config reset
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
app_rstn0 <= 0;
srst0 <= 1;
crst0 <= 1;
end
else if (exits_r == 1'b1)
begin
srst0 <= 1;
crst0 <= 1;
app_rstn0 <= 0;
end
else // synthesis translate_off
if ((test_sim == 1'b1) & (rsnt_cntn >= 11'd32))
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
else // synthesis translate_on
if (rsnt_cntn == 11'd1024)
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
end
//sync and config reset pipeline
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
app_rstn <= 0;
srst <= 1;
crst <= 1;
end
else
begin
app_rstn <= app_rstn0;
srst <= srst0;
crst <= crst0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_no_pg/sky130_fd_sc_hs__u_df_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfxtp (
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR,
VGND
);
// Module ports
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_BEHAVIORAL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Avalon memory interface functional model
// File : borealis_stim.v
// Author : Frank Bruno
// Created : 10-19-2010
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description : This models a memory based on the avalon interface to
// speed up simulations.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
module fast_mem_tasks;
// These tasks are for 128 bit version of the memory, 16 BYTES only
/**************************************************************************/
/* Behavioral tasks to move data to or from the RAMs */
task ram_fill32;
// This tasks initialize display buffer memory by writing requested number
// of 32 bit words of data with a initial location at start_addr.
// Start address is specifed for a 32bit word. (IT is not page_address as
// for EDO, and it is NOT byte address). The task can fill 8MB display
// buffer switching automaticaly to the proper 4MB bank.
// Data is placed in memories assuming an upgradable 2MB@64 ->4MB@128 board
// The amount of data written to the buffer is the same for 64 bit bus and
// 128 bit bus if the number of words passed to the task stays the same.
input [31:0] start_adr; // address in 32bit words
input [31:0] words;
input [31:0] data;
reg [31:0] i;
begin
// for (i = start_adr; i < (start_adr+words)<<2; i = i + 1) begin
for (i = start_adr; i < (start_adr+words); i = i + 1) begin
// U0.U_DDR3.mem[i] = data[i[1:0]*8+:8];
U0.U_DDR3.mem[{i, 2'b00}] = data[7:0];
U0.U_DDR3.mem[{i, 2'b01}] = data[15:8];
U0.U_DDR3.mem[{i, 2'b10}] = data[23:16];
U0.U_DDR3.mem[{i, 2'b11}] = data[31:24];
end
end
endtask // ram_fill32
/**************************************************************************/
task ram_loadh;
input [22:0] start_adr;
input [127:0] datar;
input [15:0] ben;
reg [31:0] indxw; // pointer to SGRAM buffer
begin
indxw = start_adr<<4;
for (int i = 0; i < 16; i++) begin
// $display("Writing %h: %h", indxw, datar[i[3:0]*8+:8]);
U0.U_DDR3.mem[indxw] = datar[i[3:0]*8+:8];
indxw++;
// #100 $stop;
end
// Read next line
//status_in = $fscanf(file_in, "%h\n", datar);
end
endtask // ram_loadh
/**************************************************************************/
task ram_floadh;
// This task loads a requested number of 128bit words of data from
// a file and places it in the display SGRAM buffer starting at start_addr.
// The start addr is in 32bit words.
// Written by Jack and _copied_ by hk for sgram
input [8*64:1] image_file;
input [21:0] start_adr; //start address in memory [32bit words]
input [16:0] lines; /* number of 128bit words to be read from temp
* buffer/into SGRAM models.
* In most cases this will be
* number of lines in a file ,
* But it can be smaller */
reg [127:0] datar; // data read from temp buffer
reg [31:0] indxw; // pointer to SGRAM buffer
integer file_in; // File pointer
integer status_in; // Status of file
begin
$display ("reading file %s", image_file);
file_in = $fopen(image_file, "r");
$display ("loading image into SGRAM RAM DISPLAY BUFFER ");
// indxw = start_adr<<4;
indxw = start_adr<<2;
while (!$feof(file_in)) begin
status_in = $fscanf(file_in, "%h\n", datar);
for (int i = 0; i < 16; i++) begin
// $display("Writing %h: %h", indxw, datar[i[3:0]*8+:8]);
U0.U_DDR3.mem[indxw] = datar[i[3:0]*8+:8];
indxw++;
// #100 $stop;
end
// Read next line
//status_in = $fscanf(file_in, "%h\n", datar);
end
end
endtask // ram_floadh
/**************************************************************************/
task ram_floadh2;
// This task loads a requested number of 128bit words of data from
// a file and places it in the display SGRAM buffer starting at start_addr.
// The start addr is in 32bit words.
input [8*64:1] image_file;
reg [127:0] datar; // data read from temp buffer
reg [22:0] adr; //start address in memory [32bit words]
reg [31:0] indxw; // pointer to SGRAM buffer
reg [15:0] mask;
integer file_in; // File pointer
integer status_in; // Status of file
begin
$display ("reading file %s", image_file);
file_in = $fopen(image_file, "r");
$display ("loading data into RAM\n");
while (!$feof(file_in)) begin
status_in = $fscanf(file_in, "%h %h %h\n", adr, datar, mask);
indxw = adr<<4;
for (int i = 0; i < 16; i++) begin
// $display("Writing %h: %h", indxw, datar[i[3:0]*8+:8]);
if (~mask[i]) U0.U_DDR3.mem[indxw] = datar[i[3:0]*8+:8];
indxw++;
// #100 $stop;
end
// Read next line
//status_in = $fscanf(file_in, "%h\n", datar);
end
end
endtask // ram_floadh
/**************************************************************************/
task ram_floadh_32_to_565;
// This task loads a requested number of 128bit words of data from
// a file and places it in the display SGRAM buffer starting at start_addr.
// The start addr is in 32bit words.
// Written by Jack and _copied_ by hk for sgram
input [8*64:1] image_file;
input [21:0] start_adr; //start address in memory [32bit words]
input [16:0] lines; /* number of 128bit words to be read from temp
* buffer/into SGRAM models.
* In most cases this will be
* number of lines in a file ,
* But it can be smaller */
reg [255:0] datar; // data read from temp buffer
reg [127:0] datar1; // data read from temp buffer
reg [31:0] indxw; // pointer to SGRAM buffer
integer file_in; // File pointer
integer status_in; // Status of file
begin
$display ("reading file %s", image_file);
file_in = $fopen(image_file, "r");
status_in = $fscanf(file_in, "%h\n", datar[127:0]);
status_in = $fscanf(file_in, "%h\n", datar[255:128]);
datar1[15:0] = {datar[(0*32)+23:(0*32)+19], datar[(0*32)+15:(0*32)+10], datar[(0*32)+7:(0*32)+3]};
datar1[31:16] = {datar[(1*32)+23:(1*32)+19], datar[(1*32)+15:(1*32)+10], datar[(1*32)+7:(1*32)+3]};
datar1[47:32] = {datar[(2*32)+23:(2*32)+19], datar[(2*32)+15:(2*32)+10], datar[(2*32)+7:(2*32)+3]};
datar1[63:48] = {datar[(3*32)+23:(3*32)+19], datar[(3*32)+15:(3*32)+10], datar[(3*32)+7:(3*32)+3]};
datar1[79:64] = {datar[(4*32)+23:(4*32)+19], datar[(4*32)+15:(4*32)+10], datar[(4*32)+7:(4*32)+3]};
datar1[95:80] = {datar[(5*32)+23:(5*32)+19], datar[(5*32)+15:(5*32)+10], datar[(5*32)+7:(5*32)+3]};
datar1[111:96] = {datar[(6*32)+23:(6*32)+19], datar[(6*32)+15:(6*32)+10], datar[(6*32)+7:(6*32)+3]};
datar1[127:112] = {datar[(7*32)+23:(7*32)+19], datar[(7*32)+15:(7*32)+10], datar[(7*32)+7:(7*32)+3]};
$display ("loading image into SGRAM RAM DISPLAY BUFFER ");
// indxw = start_adr<<4;
indxw = start_adr<<2;
while (!$feof(file_in)) begin
for (int i = 0; i < 16; i++) begin
// $display("Writing %h: %h", indxw, datar[i[3:0]*8+:8]);
U0.U_DDR3.mem[indxw] = datar1[i[3:0]*8+:8];
indxw++;
// #100 $stop;
end
// Read next line
status_in = $fscanf(file_in, "%h\n", datar[127:0]);
status_in = $fscanf(file_in, "%h\n", datar[255:128]);
datar1[15:0] = {datar[(0*32)+23:(0*32)+19], datar[(0*32)+15:(0*32)+10], datar[(0*32)+7:(0*32)+3]};
datar1[31:16] = {datar[(1*32)+23:(1*32)+19], datar[(1*32)+15:(1*32)+10], datar[(1*32)+7:(1*32)+3]};
datar1[47:32] = {datar[(2*32)+23:(2*32)+19], datar[(2*32)+15:(2*32)+10], datar[(2*32)+7:(2*32)+3]};
datar1[63:48] = {datar[(3*32)+23:(3*32)+19], datar[(3*32)+15:(3*32)+10], datar[(3*32)+7:(3*32)+3]};
datar1[79:64] = {datar[(4*32)+23:(4*32)+19], datar[(4*32)+15:(4*32)+10], datar[(4*32)+7:(4*32)+3]};
datar1[95:80] = {datar[(5*32)+23:(5*32)+19], datar[(5*32)+15:(5*32)+10], datar[(5*32)+7:(5*32)+3]};
datar1[111:96] = {datar[(6*32)+23:(6*32)+19], datar[(6*32)+15:(6*32)+10], datar[(6*32)+7:(6*32)+3]};
datar1[127:112] = {datar[(7*32)+23:(7*32)+19], datar[(7*32)+15:(7*32)+10], datar[(7*32)+7:(7*32)+3]};
end
end
endtask // ram_floadh
task vga_floadh;
// This task loads a VGA memory image into the I128 Memory system
input [8*64:1] image_file;
input [21:0] start_adr; // start address in memory [32bit words]
input [15:0] lines; /* number of 128bit words to be read from temp
* buffer/into SGRAM models.
* In most cases this will be number of lines
* in a file , But it can be smaller */
reg [32:0] tempbuff[0:131071]; // TWO meg !!, always loaded from addr=0
reg [127:0] datar; // data read from temp buffer
reg [16:0] indxr; // pointer to temp buffer
reg [1:0] indxwr;// Index write
reg [31:0] dataw; // data writen into SGRAM
reg [21:0] indxw; // pointer to SGRAM buffer
begin
$display ("reading file %s", image_file);
$readmemh(image_file, tempbuff); //load temp. buffer from a file
$display ("loading image into SGRAM RAM DISPLAY BUFFER ");
indxw = start_adr;
for (indxr = 0; indxr < lines; indxr = indxr + 1) begin
datar = tempbuff[indxr];
for (indxwr = 0; indxwr < 2; indxwr = indxwr + 1) begin
VR.ram_fill32(indxw, 1, datar);
indxw = indxw + 1;
end
end
end
endtask // ram_floadh
/**************************************************************************/
task save_fbmp;
//This task saves a bitmap in DISPLAY buffer to a file.
input [31:0] bitmap_address; // Byte address in DISPLAY buffer
input [15:0] x_size; /* X size (in pixels) of the image
* in the output file */
input [15:0] y_size; /* Y size (in pixels) of the image
* in the output file */
input [240:1] file_name; // name of the output file
input [31:0] i_pitch; /* Image pitch (in bytes) in the display
* buffer
* This may be set in local tasks
* arbitrarily or passed to this task
* as the result of testing of e.g.
* xx_DPTCH register, or other internal
* registers. */
input [1:0] i_psize; /* Image bpp in the display buffer
* This may be set in local tasks
* arbitrarily or passed to this task
* as the result of testing of e.g.
* xx_PSIZE register or other internal
* registers */
integer index;
integer x;
integer y;
integer pageindex;
integer dump_file;
integer data_file;
integer pitch;
integer bpp;
reg [15:0] temp_mem;
reg [32:0] data;
reg [7:0] c8;
reg [15:0] c16;
reg [31:0] c32;
integer i;
reg [127:0] data_0, data_1, data_2, data_3, data_4, data_5, data_6,
data_7;
begin
$display("Saving file '%s' ...", file_name);
dump_file = $fopen(file_name);
data_file = $fopen("data.bmp");
pitch = i_pitch ;
$display("pitch = %h ", pitch);
bpp = 8;
if (i_psize==2'b10)
bpp = 32;
else if (i_psize==2'b01 | i_psize==2'b11)
bpp = 16;
if (bpp == 8) index = bitmap_address;
else if (bpp == 16) index = bitmap_address >> 1;
else if (bpp == 32) index = bitmap_address >> 2;
// Write Bitmap Header information to file.
$fwrite(dump_file,"\nVerilog Simulation Data\n\n");
$fwrite(dump_file,"BitmapDX\t%d\n", x_size);
$fwrite(dump_file,"BitmapDY\t%d\n", y_size);
$fwrite(dump_file,"BitsPerPixel\t%d\n", bpp);
$fwrite(dump_file,"WidthBytes\t%d\n\n", x_size * bpp/8);
$fwrite(dump_file,"X\tY\tPixelValue\n");
for (y = 0; y < y_size; y = y + 1) begin
for (x = 0; x < x_size; x = x + 1) begin
pageindex = (index + x);
//if (bpp == 8) pageindex = (index + x);
//else if (bpp == 16) pageindex = (index + (x * 2));
//else if (bpp == 32) pageindex = (index + (x * 4));
// $display ("Direct Read %h", pageindex[20:0]);
if (bpp == 8) begin
c8 = U0.U_DDR3.mem[pageindex];
$display("Saving from %h", pageindex);
$fwrite(dump_file,"%d\t%d\t0x%0h\n", x, y, c8);
$fwrite(data_file,"%c", c8);
end else if (bpp == 16) begin
c16 = {U0.U_DDR3.mem[{pageindex,1'b1}],
U0.U_DDR3.mem[{pageindex,1'b0}]};
$fwrite(dump_file,"%d\t%d\t0x%0h\n", x, y, c16);
$fwrite(data_file,"%c", c16[7:0]);
$fwrite(data_file,"%c", c16[15:8]);
end else if (bpp == 32) begin
data = {U0.U_DDR3.mem[{pageindex,2'b11}],
U0.U_DDR3.mem[{pageindex,2'b10}],
U0.U_DDR3.mem[{pageindex,2'b01}],
U0.U_DDR3.mem[{pageindex,2'b00}]};
$fwrite(dump_file,"%d\t%d\t0x%0h\n", x, y, data);
$fwrite(data_file,"%c", data[7:0]);
$fwrite(data_file,"%c", data[15:8]);
$fwrite(data_file,"%c", data[23:16]);
$fwrite(data_file,"%c", data[31:24]);
$display("Saving %h from %h", U0.U_DDR3.mem[pageindex], pageindex>>2);
end
//$display("saving address %h,: %h", pageindex[20:2], c8);
end // for (x = 0; x < x_size; x = x + 1)
//index = index + pitch;
if (bpp == 8) index = index + pitch;
else if (bpp == 16)index = index + (pitch >> 1);
else index = index + (pitch >> 2);
end // for (y = 0; y < y_size; y = y + 1)
$fclose(dump_file);
$fclose(data_file);
$display("Done saving file '%s' ...", file_name);
end
endtask // save_fbmp
/****************************************************************/
/* For future reference, these are the commands availible */
/* for dynamic memory allocation. */
// $damem_read("MEM",adr,data_reg);
// $damem_write("MEM",adr,data_val);
// $damem_initb("MEM","file_name",addr_from,addr_to); //formatted for the readmemb system task.
// $damem_inith("MEM","file_name",addr_from,addr_to); //formatted for the readmemh system task.
/****************************************************************/
task rr;
input [19:0] start_adr;
input [19:0] words;
reg [31:0] i;
reg [127:0] ram_reg;
begin
$display("start addr= %h quan words= %h",start_adr,i);
for(i=start_adr;i<(start_adr+words*4);i=i+4) begin
ram_reg = {U0.U_DDR3.mem[{start_adr[19:0]+3, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0]+2, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0]+1, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0], 2'b0}]};
$display("addr= %h data= %h",i,ram_reg);
end
end
endtask
/****************************************************************/
task ram_dump; // modif
input [19:0] start_adr;
input [19:0] words;
input [80:1] file_name;
reg [31:0] i;
reg [127:0] ram_reg;
integer dump_file;
begin
dump_file = $fopen(file_name);
for(i=start_adr;i<(start_adr+words*4);i=i+4) begin
ram_reg = {U0.U_DDR3.mem[{start_adr[19:0]+3, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0]+2, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0]+1, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0], 2'b0}]};
$fdisplay(dump_file,"addr= %h data= %h",i,ram_reg);
end
$fclose(dump_file);
end
endtask
/****************************************************************/
task ram_fill; // modif
input [19:0] start_adr;
input [19:0] words;
input [31:0] data;
reg [31:0] i;
begin
for(i=start_adr;i<(start_adr+words*4);i=i+1) begin
U0.U_DDR3.mem[{start_adr[19:0], 2'b0}] = data;
end
end
endtask
/****************************************************************/
task wide_fill; // modif
input [17:0] start_adr;
input [17:0] words;
input [128:0] data;
reg [31:0] i, j;
reg [127:0] temp_0, temp_1, temp_2, temp_3;
begin
for (i=start_adr;i<(start_adr+words);i=i+4) begin
for (j = 0; j < 4; j = j + 1) begin
U0.U_DDR3.mem[{start_adr[17:0], 2'b0}] = data[31:0];
U0.U_DDR3.mem[{start_adr[17:0]+1, 2'b0}] = data[63:32];
U0.U_DDR3.mem[{start_adr[17:0]+2, 2'b0}] = data[95:64];
U0.U_DDR3.mem[{start_adr[17:0]+3, 2'b0}] = data[127:96];
end
end // for (i=start_adr;i<(start_adr+words);i=i+1)
end
endtask
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
module jt12_dout(
// input rst_n,
input clk, // CPU clock
input flag_A,
input flag_B,
input busy,
input [5:0] adpcma_flags,
input adpcmb_flag,
input [7:0] psg_dout,
input [1:0] addr,
output reg [7:0] dout
);
parameter use_ssg=0, use_adpcm=0;
always @(posedge clk) begin
casez( addr )
2'b00: dout <= {busy, 5'd0, flag_B, flag_A }; // YM2203
2'b01: dout <= (use_ssg ==1) ? psg_dout : {busy, 5'd0, flag_B, flag_A };
2'b1?: dout <= (use_adpcm==1) ?
{ adpcmb_flag, 1'b0, adpcma_flags } :
{ busy, 5'd0, flag_B, flag_A };
endcase
end
endmodule // jt12_dout
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 14:49:03 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_vga_transform_0_1 -prefix
// system_vga_transform_0_1_ system_vga_transform_0_1_sim_netlist.v
// Design : system_vga_transform_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_transform_0_1,vga_transform,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_transform,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_transform_0_1
(clk,
enable,
x_addr_in,
y_addr_in,
rot_m00,
rot_m01,
rot_m10,
rot_m11,
t_x,
t_y,
x_addr_out,
y_addr_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input enable;
input [9:0]x_addr_in;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [15:0]rot_m01;
input [15:0]rot_m10;
input [15:0]rot_m11;
input [9:0]t_x;
input [9:0]t_y;
output [9:0]x_addr_out;
output [9:0]y_addr_out;
wire clk;
wire enable;
wire [15:0]rot_m00;
wire [15:0]rot_m01;
wire [15:0]rot_m10;
wire [15:0]rot_m11;
wire [9:0]t_x;
wire [9:0]t_y;
wire [9:0]x_addr_in;
wire [9:0]x_addr_out;
wire [9:0]y_addr_in;
wire [9:0]y_addr_out;
system_vga_transform_0_1_vga_transform U0
(.clk(clk),
.enable(enable),
.rot_m00(rot_m00),
.rot_m01(rot_m01),
.rot_m10(rot_m10),
.rot_m11(rot_m11),
.t_x(t_x),
.t_y(t_y),
.x_addr_in(x_addr_in),
.x_addr_out(x_addr_out),
.y_addr_in(y_addr_in),
.y_addr_out(y_addr_out));
endmodule
module system_vga_transform_0_1_vga_transform
(x_addr_out,
y_addr_out,
rot_m01,
y_addr_in,
rot_m00,
x_addr_in,
clk,
rot_m11,
rot_m10,
enable,
t_x,
t_y);
output [9:0]x_addr_out;
output [9:0]y_addr_out;
input [15:0]rot_m01;
input [9:0]y_addr_in;
input [15:0]rot_m00;
input [9:0]x_addr_in;
input clk;
input [15:0]rot_m11;
input [15:0]rot_m10;
input enable;
input [9:0]t_x;
input [9:0]t_y;
wire clk;
wire enable;
wire [9:0]p_0_in;
wire [23:14]p_1_in;
wire [15:0]rot_m00;
wire [15:0]rot_m01;
wire [15:0]rot_m10;
wire [15:0]rot_m11;
wire [9:0]t_x;
wire [9:0]t_y;
wire [9:0]x_addr_in;
wire [9:0]x_addr_out;
wire [23:14]x_addr_out0;
wire x_addr_out0_carry__0_i_1_n_0;
wire x_addr_out0_carry__0_i_2_n_0;
wire x_addr_out0_carry__0_i_3_n_0;
wire x_addr_out0_carry__0_i_4_n_0;
wire x_addr_out0_carry__0_n_0;
wire x_addr_out0_carry__0_n_1;
wire x_addr_out0_carry__0_n_2;
wire x_addr_out0_carry__0_n_3;
wire x_addr_out0_carry__1_i_1_n_0;
wire x_addr_out0_carry__1_i_2_n_0;
wire x_addr_out0_carry__1_n_3;
wire x_addr_out0_carry_i_1_n_0;
wire x_addr_out0_carry_i_2_n_0;
wire x_addr_out0_carry_i_3_n_0;
wire x_addr_out0_carry_n_0;
wire x_addr_out0_carry_n_1;
wire x_addr_out0_carry_n_2;
wire x_addr_out0_carry_n_3;
wire x_addr_out2_carry__0_i_1_n_0;
wire x_addr_out2_carry__0_i_2_n_0;
wire x_addr_out2_carry__0_i_3_n_0;
wire x_addr_out2_carry__0_i_4_n_0;
wire x_addr_out2_carry__0_n_0;
wire x_addr_out2_carry__0_n_1;
wire x_addr_out2_carry__0_n_2;
wire x_addr_out2_carry__0_n_3;
wire x_addr_out2_carry__1_i_1_n_0;
wire x_addr_out2_carry__1_i_2_n_0;
wire x_addr_out2_carry__1_i_3_n_0;
wire x_addr_out2_carry__1_i_4_n_0;
wire x_addr_out2_carry__1_n_0;
wire x_addr_out2_carry__1_n_1;
wire x_addr_out2_carry__1_n_2;
wire x_addr_out2_carry__1_n_3;
wire x_addr_out2_carry__2_i_1_n_0;
wire x_addr_out2_carry__2_i_2_n_0;
wire x_addr_out2_carry__2_i_3_n_0;
wire x_addr_out2_carry__2_i_4_n_0;
wire x_addr_out2_carry__2_n_0;
wire x_addr_out2_carry__2_n_1;
wire x_addr_out2_carry__2_n_2;
wire x_addr_out2_carry__2_n_3;
wire x_addr_out2_carry__3_i_1_n_0;
wire x_addr_out2_carry__3_i_2_n_0;
wire x_addr_out2_carry__3_i_3_n_0;
wire x_addr_out2_carry__3_i_4_n_0;
wire x_addr_out2_carry__3_n_0;
wire x_addr_out2_carry__3_n_1;
wire x_addr_out2_carry__3_n_2;
wire x_addr_out2_carry__3_n_3;
wire x_addr_out2_carry__4_i_1_n_0;
wire x_addr_out2_carry__4_i_2_n_0;
wire x_addr_out2_carry__4_i_3_n_0;
wire x_addr_out2_carry__4_i_4_n_0;
wire x_addr_out2_carry__4_n_0;
wire x_addr_out2_carry__4_n_1;
wire x_addr_out2_carry__4_n_2;
wire x_addr_out2_carry__4_n_3;
wire x_addr_out2_carry__5_i_1_n_0;
wire x_addr_out2_carry__5_i_2_n_0;
wire x_addr_out2_carry__5_i_3_n_0;
wire x_addr_out2_carry__5_i_4_n_0;
wire x_addr_out2_carry__5_n_0;
wire x_addr_out2_carry__5_n_1;
wire x_addr_out2_carry__5_n_2;
wire x_addr_out2_carry__5_n_3;
wire x_addr_out2_carry__6_i_1_n_0;
wire x_addr_out2_carry__6_i_2_n_0;
wire x_addr_out2_carry__6_i_3_n_0;
wire x_addr_out2_carry__6_i_4_n_0;
wire x_addr_out2_carry__6_n_0;
wire x_addr_out2_carry__6_n_1;
wire x_addr_out2_carry__6_n_2;
wire x_addr_out2_carry__6_n_3;
wire x_addr_out2_carry__7_i_1_n_0;
wire x_addr_out2_carry__7_i_2_n_0;
wire x_addr_out2_carry__7_i_3_n_0;
wire x_addr_out2_carry__7_i_4_n_0;
wire x_addr_out2_carry__7_n_0;
wire x_addr_out2_carry__7_n_1;
wire x_addr_out2_carry__7_n_2;
wire x_addr_out2_carry__7_n_3;
wire x_addr_out2_carry__8_i_1_n_0;
wire x_addr_out2_carry__8_i_2_n_0;
wire x_addr_out2_carry__8_n_3;
wire x_addr_out2_carry_i_1_n_0;
wire x_addr_out2_carry_i_2_n_0;
wire x_addr_out2_carry_i_3_n_0;
wire x_addr_out2_carry_i_4_n_0;
wire x_addr_out2_carry_n_0;
wire x_addr_out2_carry_n_1;
wire x_addr_out2_carry_n_2;
wire x_addr_out2_carry_n_3;
wire x_addr_out3__0_n_100;
wire x_addr_out3__0_n_101;
wire x_addr_out3__0_n_102;
wire x_addr_out3__0_n_103;
wire x_addr_out3__0_n_104;
wire x_addr_out3__0_n_105;
wire x_addr_out3__0_n_58;
wire x_addr_out3__0_n_59;
wire x_addr_out3__0_n_60;
wire x_addr_out3__0_n_61;
wire x_addr_out3__0_n_62;
wire x_addr_out3__0_n_63;
wire x_addr_out3__0_n_64;
wire x_addr_out3__0_n_65;
wire x_addr_out3__0_n_66;
wire x_addr_out3__0_n_67;
wire x_addr_out3__0_n_68;
wire x_addr_out3__0_n_69;
wire x_addr_out3__0_n_70;
wire x_addr_out3__0_n_71;
wire x_addr_out3__0_n_72;
wire x_addr_out3__0_n_73;
wire x_addr_out3__0_n_74;
wire x_addr_out3__0_n_75;
wire x_addr_out3__0_n_76;
wire x_addr_out3__0_n_77;
wire x_addr_out3__0_n_78;
wire x_addr_out3__0_n_79;
wire x_addr_out3__0_n_80;
wire x_addr_out3__0_n_81;
wire x_addr_out3__0_n_82;
wire x_addr_out3__0_n_83;
wire x_addr_out3__0_n_84;
wire x_addr_out3__0_n_85;
wire x_addr_out3__0_n_86;
wire x_addr_out3__0_n_87;
wire x_addr_out3__0_n_88;
wire x_addr_out3__0_n_89;
wire x_addr_out3__0_n_90;
wire x_addr_out3__0_n_91;
wire x_addr_out3__0_n_92;
wire x_addr_out3__0_n_93;
wire x_addr_out3__0_n_94;
wire x_addr_out3__0_n_95;
wire x_addr_out3__0_n_96;
wire x_addr_out3__0_n_97;
wire x_addr_out3__0_n_98;
wire x_addr_out3__0_n_99;
wire x_addr_out3__1_n_100;
wire x_addr_out3__1_n_101;
wire x_addr_out3__1_n_102;
wire x_addr_out3__1_n_103;
wire x_addr_out3__1_n_104;
wire x_addr_out3__1_n_105;
wire x_addr_out3__1_n_106;
wire x_addr_out3__1_n_107;
wire x_addr_out3__1_n_108;
wire x_addr_out3__1_n_109;
wire x_addr_out3__1_n_110;
wire x_addr_out3__1_n_111;
wire x_addr_out3__1_n_112;
wire x_addr_out3__1_n_113;
wire x_addr_out3__1_n_114;
wire x_addr_out3__1_n_115;
wire x_addr_out3__1_n_116;
wire x_addr_out3__1_n_117;
wire x_addr_out3__1_n_118;
wire x_addr_out3__1_n_119;
wire x_addr_out3__1_n_120;
wire x_addr_out3__1_n_121;
wire x_addr_out3__1_n_122;
wire x_addr_out3__1_n_123;
wire x_addr_out3__1_n_124;
wire x_addr_out3__1_n_125;
wire x_addr_out3__1_n_126;
wire x_addr_out3__1_n_127;
wire x_addr_out3__1_n_128;
wire x_addr_out3__1_n_129;
wire x_addr_out3__1_n_130;
wire x_addr_out3__1_n_131;
wire x_addr_out3__1_n_132;
wire x_addr_out3__1_n_133;
wire x_addr_out3__1_n_134;
wire x_addr_out3__1_n_135;
wire x_addr_out3__1_n_136;
wire x_addr_out3__1_n_137;
wire x_addr_out3__1_n_138;
wire x_addr_out3__1_n_139;
wire x_addr_out3__1_n_140;
wire x_addr_out3__1_n_141;
wire x_addr_out3__1_n_142;
wire x_addr_out3__1_n_143;
wire x_addr_out3__1_n_144;
wire x_addr_out3__1_n_145;
wire x_addr_out3__1_n_146;
wire x_addr_out3__1_n_147;
wire x_addr_out3__1_n_148;
wire x_addr_out3__1_n_149;
wire x_addr_out3__1_n_150;
wire x_addr_out3__1_n_151;
wire x_addr_out3__1_n_152;
wire x_addr_out3__1_n_153;
wire x_addr_out3__1_n_58;
wire x_addr_out3__1_n_59;
wire x_addr_out3__1_n_60;
wire x_addr_out3__1_n_61;
wire x_addr_out3__1_n_62;
wire x_addr_out3__1_n_63;
wire x_addr_out3__1_n_64;
wire x_addr_out3__1_n_65;
wire x_addr_out3__1_n_66;
wire x_addr_out3__1_n_67;
wire x_addr_out3__1_n_68;
wire x_addr_out3__1_n_69;
wire x_addr_out3__1_n_70;
wire x_addr_out3__1_n_71;
wire x_addr_out3__1_n_72;
wire x_addr_out3__1_n_73;
wire x_addr_out3__1_n_74;
wire x_addr_out3__1_n_75;
wire x_addr_out3__1_n_76;
wire x_addr_out3__1_n_77;
wire x_addr_out3__1_n_78;
wire x_addr_out3__1_n_79;
wire x_addr_out3__1_n_80;
wire x_addr_out3__1_n_81;
wire x_addr_out3__1_n_82;
wire x_addr_out3__1_n_83;
wire x_addr_out3__1_n_84;
wire x_addr_out3__1_n_85;
wire x_addr_out3__1_n_86;
wire x_addr_out3__1_n_87;
wire x_addr_out3__1_n_88;
wire x_addr_out3__1_n_89;
wire x_addr_out3__1_n_90;
wire x_addr_out3__1_n_91;
wire x_addr_out3__1_n_92;
wire x_addr_out3__1_n_93;
wire x_addr_out3__1_n_94;
wire x_addr_out3__1_n_95;
wire x_addr_out3__1_n_96;
wire x_addr_out3__1_n_97;
wire x_addr_out3__1_n_98;
wire x_addr_out3__1_n_99;
wire x_addr_out3__2_n_100;
wire x_addr_out3__2_n_101;
wire x_addr_out3__2_n_102;
wire x_addr_out3__2_n_103;
wire x_addr_out3__2_n_104;
wire x_addr_out3__2_n_105;
wire x_addr_out3__2_n_58;
wire x_addr_out3__2_n_59;
wire x_addr_out3__2_n_60;
wire x_addr_out3__2_n_61;
wire x_addr_out3__2_n_62;
wire x_addr_out3__2_n_63;
wire x_addr_out3__2_n_64;
wire x_addr_out3__2_n_65;
wire x_addr_out3__2_n_66;
wire x_addr_out3__2_n_67;
wire x_addr_out3__2_n_68;
wire x_addr_out3__2_n_69;
wire x_addr_out3__2_n_70;
wire x_addr_out3__2_n_71;
wire x_addr_out3__2_n_72;
wire x_addr_out3__2_n_73;
wire x_addr_out3__2_n_74;
wire x_addr_out3__2_n_75;
wire x_addr_out3__2_n_76;
wire x_addr_out3__2_n_77;
wire x_addr_out3__2_n_78;
wire x_addr_out3__2_n_79;
wire x_addr_out3__2_n_80;
wire x_addr_out3__2_n_81;
wire x_addr_out3__2_n_82;
wire x_addr_out3__2_n_83;
wire x_addr_out3__2_n_84;
wire x_addr_out3__2_n_85;
wire x_addr_out3__2_n_86;
wire x_addr_out3__2_n_87;
wire x_addr_out3__2_n_88;
wire x_addr_out3__2_n_89;
wire x_addr_out3__2_n_90;
wire x_addr_out3__2_n_91;
wire x_addr_out3__2_n_92;
wire x_addr_out3__2_n_93;
wire x_addr_out3__2_n_94;
wire x_addr_out3__2_n_95;
wire x_addr_out3__2_n_96;
wire x_addr_out3__2_n_97;
wire x_addr_out3__2_n_98;
wire x_addr_out3__2_n_99;
wire x_addr_out3_n_100;
wire x_addr_out3_n_101;
wire x_addr_out3_n_102;
wire x_addr_out3_n_103;
wire x_addr_out3_n_104;
wire x_addr_out3_n_105;
wire x_addr_out3_n_106;
wire x_addr_out3_n_107;
wire x_addr_out3_n_108;
wire x_addr_out3_n_109;
wire x_addr_out3_n_110;
wire x_addr_out3_n_111;
wire x_addr_out3_n_112;
wire x_addr_out3_n_113;
wire x_addr_out3_n_114;
wire x_addr_out3_n_115;
wire x_addr_out3_n_116;
wire x_addr_out3_n_117;
wire x_addr_out3_n_118;
wire x_addr_out3_n_119;
wire x_addr_out3_n_120;
wire x_addr_out3_n_121;
wire x_addr_out3_n_122;
wire x_addr_out3_n_123;
wire x_addr_out3_n_124;
wire x_addr_out3_n_125;
wire x_addr_out3_n_126;
wire x_addr_out3_n_127;
wire x_addr_out3_n_128;
wire x_addr_out3_n_129;
wire x_addr_out3_n_130;
wire x_addr_out3_n_131;
wire x_addr_out3_n_132;
wire x_addr_out3_n_133;
wire x_addr_out3_n_134;
wire x_addr_out3_n_135;
wire x_addr_out3_n_136;
wire x_addr_out3_n_137;
wire x_addr_out3_n_138;
wire x_addr_out3_n_139;
wire x_addr_out3_n_140;
wire x_addr_out3_n_141;
wire x_addr_out3_n_142;
wire x_addr_out3_n_143;
wire x_addr_out3_n_144;
wire x_addr_out3_n_145;
wire x_addr_out3_n_146;
wire x_addr_out3_n_147;
wire x_addr_out3_n_148;
wire x_addr_out3_n_149;
wire x_addr_out3_n_150;
wire x_addr_out3_n_151;
wire x_addr_out3_n_152;
wire x_addr_out3_n_153;
wire x_addr_out3_n_58;
wire x_addr_out3_n_59;
wire x_addr_out3_n_60;
wire x_addr_out3_n_61;
wire x_addr_out3_n_62;
wire x_addr_out3_n_63;
wire x_addr_out3_n_64;
wire x_addr_out3_n_65;
wire x_addr_out3_n_66;
wire x_addr_out3_n_67;
wire x_addr_out3_n_68;
wire x_addr_out3_n_69;
wire x_addr_out3_n_70;
wire x_addr_out3_n_71;
wire x_addr_out3_n_72;
wire x_addr_out3_n_73;
wire x_addr_out3_n_74;
wire x_addr_out3_n_75;
wire x_addr_out3_n_76;
wire x_addr_out3_n_77;
wire x_addr_out3_n_78;
wire x_addr_out3_n_79;
wire x_addr_out3_n_80;
wire x_addr_out3_n_81;
wire x_addr_out3_n_82;
wire x_addr_out3_n_83;
wire x_addr_out3_n_84;
wire x_addr_out3_n_85;
wire x_addr_out3_n_86;
wire x_addr_out3_n_87;
wire x_addr_out3_n_88;
wire x_addr_out3_n_89;
wire x_addr_out3_n_90;
wire x_addr_out3_n_91;
wire x_addr_out3_n_92;
wire x_addr_out3_n_93;
wire x_addr_out3_n_94;
wire x_addr_out3_n_95;
wire x_addr_out3_n_96;
wire x_addr_out3_n_97;
wire x_addr_out3_n_98;
wire x_addr_out3_n_99;
wire \x_addr_out[0]_i_1_n_0 ;
wire \x_addr_out[1]_i_1_n_0 ;
wire \x_addr_out[2]_i_1_n_0 ;
wire \x_addr_out[3]_i_1_n_0 ;
wire \x_addr_out[4]_i_1_n_0 ;
wire \x_addr_out[5]_i_1_n_0 ;
wire \x_addr_out[6]_i_1_n_0 ;
wire \x_addr_out[7]_i_1_n_0 ;
wire \x_addr_out[8]_i_1_n_0 ;
wire \x_addr_out[9]_i_1_n_0 ;
wire [9:0]y_addr_in;
wire [9:0]y_addr_out;
wire y_addr_out0_carry__0_i_1_n_0;
wire y_addr_out0_carry__0_i_2_n_0;
wire y_addr_out0_carry__0_i_3_n_0;
wire y_addr_out0_carry__0_i_4_n_0;
wire y_addr_out0_carry__0_n_0;
wire y_addr_out0_carry__0_n_1;
wire y_addr_out0_carry__0_n_2;
wire y_addr_out0_carry__0_n_3;
wire y_addr_out0_carry__1_i_1_n_0;
wire y_addr_out0_carry__1_i_2_n_0;
wire y_addr_out0_carry__1_n_3;
wire y_addr_out0_carry_i_1_n_0;
wire y_addr_out0_carry_i_2_n_0;
wire y_addr_out0_carry_i_3_n_0;
wire y_addr_out0_carry_i_4_n_0;
wire y_addr_out0_carry_n_0;
wire y_addr_out0_carry_n_1;
wire y_addr_out0_carry_n_2;
wire y_addr_out0_carry_n_3;
wire [37:28]y_addr_out2;
wire y_addr_out2_carry__0_i_1_n_0;
wire y_addr_out2_carry__0_i_2_n_0;
wire y_addr_out2_carry__0_i_3_n_0;
wire y_addr_out2_carry__0_i_4_n_0;
wire y_addr_out2_carry__0_n_0;
wire y_addr_out2_carry__0_n_1;
wire y_addr_out2_carry__0_n_2;
wire y_addr_out2_carry__0_n_3;
wire y_addr_out2_carry__1_i_1_n_0;
wire y_addr_out2_carry__1_i_2_n_0;
wire y_addr_out2_carry__1_i_3_n_0;
wire y_addr_out2_carry__1_i_4_n_0;
wire y_addr_out2_carry__1_n_0;
wire y_addr_out2_carry__1_n_1;
wire y_addr_out2_carry__1_n_2;
wire y_addr_out2_carry__1_n_3;
wire y_addr_out2_carry__2_i_1_n_0;
wire y_addr_out2_carry__2_i_2_n_0;
wire y_addr_out2_carry__2_i_3_n_0;
wire y_addr_out2_carry__2_i_4_n_0;
wire y_addr_out2_carry__2_n_0;
wire y_addr_out2_carry__2_n_1;
wire y_addr_out2_carry__2_n_2;
wire y_addr_out2_carry__2_n_3;
wire y_addr_out2_carry__3_i_1_n_0;
wire y_addr_out2_carry__3_i_2_n_0;
wire y_addr_out2_carry__3_i_3_n_0;
wire y_addr_out2_carry__3_i_4_n_0;
wire y_addr_out2_carry__3_n_0;
wire y_addr_out2_carry__3_n_1;
wire y_addr_out2_carry__3_n_2;
wire y_addr_out2_carry__3_n_3;
wire y_addr_out2_carry__4_i_1_n_0;
wire y_addr_out2_carry__4_i_2_n_0;
wire y_addr_out2_carry__4_i_3_n_0;
wire y_addr_out2_carry__4_i_4_n_0;
wire y_addr_out2_carry__4_n_0;
wire y_addr_out2_carry__4_n_1;
wire y_addr_out2_carry__4_n_2;
wire y_addr_out2_carry__4_n_3;
wire y_addr_out2_carry__5_i_1_n_0;
wire y_addr_out2_carry__5_i_2_n_0;
wire y_addr_out2_carry__5_i_3_n_0;
wire y_addr_out2_carry__5_i_4_n_0;
wire y_addr_out2_carry__5_n_0;
wire y_addr_out2_carry__5_n_1;
wire y_addr_out2_carry__5_n_2;
wire y_addr_out2_carry__5_n_3;
wire y_addr_out2_carry__6_i_1_n_0;
wire y_addr_out2_carry__6_i_2_n_0;
wire y_addr_out2_carry__6_i_3_n_0;
wire y_addr_out2_carry__6_i_4_n_0;
wire y_addr_out2_carry__6_n_0;
wire y_addr_out2_carry__6_n_1;
wire y_addr_out2_carry__6_n_2;
wire y_addr_out2_carry__6_n_3;
wire y_addr_out2_carry__7_i_1_n_0;
wire y_addr_out2_carry__7_i_2_n_0;
wire y_addr_out2_carry__7_i_3_n_0;
wire y_addr_out2_carry__7_i_4_n_0;
wire y_addr_out2_carry__7_n_0;
wire y_addr_out2_carry__7_n_1;
wire y_addr_out2_carry__7_n_2;
wire y_addr_out2_carry__7_n_3;
wire y_addr_out2_carry__8_i_1_n_0;
wire y_addr_out2_carry__8_i_2_n_0;
wire y_addr_out2_carry__8_n_3;
wire y_addr_out2_carry_i_1_n_0;
wire y_addr_out2_carry_i_2_n_0;
wire y_addr_out2_carry_i_3_n_0;
wire y_addr_out2_carry_i_4_n_0;
wire y_addr_out2_carry_n_0;
wire y_addr_out2_carry_n_1;
wire y_addr_out2_carry_n_2;
wire y_addr_out2_carry_n_3;
wire y_addr_out3__0_n_100;
wire y_addr_out3__0_n_101;
wire y_addr_out3__0_n_102;
wire y_addr_out3__0_n_103;
wire y_addr_out3__0_n_104;
wire y_addr_out3__0_n_105;
wire y_addr_out3__0_n_58;
wire y_addr_out3__0_n_59;
wire y_addr_out3__0_n_60;
wire y_addr_out3__0_n_61;
wire y_addr_out3__0_n_62;
wire y_addr_out3__0_n_63;
wire y_addr_out3__0_n_64;
wire y_addr_out3__0_n_65;
wire y_addr_out3__0_n_66;
wire y_addr_out3__0_n_67;
wire y_addr_out3__0_n_68;
wire y_addr_out3__0_n_69;
wire y_addr_out3__0_n_70;
wire y_addr_out3__0_n_71;
wire y_addr_out3__0_n_72;
wire y_addr_out3__0_n_73;
wire y_addr_out3__0_n_74;
wire y_addr_out3__0_n_75;
wire y_addr_out3__0_n_76;
wire y_addr_out3__0_n_77;
wire y_addr_out3__0_n_78;
wire y_addr_out3__0_n_79;
wire y_addr_out3__0_n_80;
wire y_addr_out3__0_n_81;
wire y_addr_out3__0_n_82;
wire y_addr_out3__0_n_83;
wire y_addr_out3__0_n_84;
wire y_addr_out3__0_n_85;
wire y_addr_out3__0_n_86;
wire y_addr_out3__0_n_87;
wire y_addr_out3__0_n_88;
wire y_addr_out3__0_n_89;
wire y_addr_out3__0_n_90;
wire y_addr_out3__0_n_91;
wire y_addr_out3__0_n_92;
wire y_addr_out3__0_n_93;
wire y_addr_out3__0_n_94;
wire y_addr_out3__0_n_95;
wire y_addr_out3__0_n_96;
wire y_addr_out3__0_n_97;
wire y_addr_out3__0_n_98;
wire y_addr_out3__0_n_99;
wire y_addr_out3__1_n_100;
wire y_addr_out3__1_n_101;
wire y_addr_out3__1_n_102;
wire y_addr_out3__1_n_103;
wire y_addr_out3__1_n_104;
wire y_addr_out3__1_n_105;
wire y_addr_out3__1_n_106;
wire y_addr_out3__1_n_107;
wire y_addr_out3__1_n_108;
wire y_addr_out3__1_n_109;
wire y_addr_out3__1_n_110;
wire y_addr_out3__1_n_111;
wire y_addr_out3__1_n_112;
wire y_addr_out3__1_n_113;
wire y_addr_out3__1_n_114;
wire y_addr_out3__1_n_115;
wire y_addr_out3__1_n_116;
wire y_addr_out3__1_n_117;
wire y_addr_out3__1_n_118;
wire y_addr_out3__1_n_119;
wire y_addr_out3__1_n_120;
wire y_addr_out3__1_n_121;
wire y_addr_out3__1_n_122;
wire y_addr_out3__1_n_123;
wire y_addr_out3__1_n_124;
wire y_addr_out3__1_n_125;
wire y_addr_out3__1_n_126;
wire y_addr_out3__1_n_127;
wire y_addr_out3__1_n_128;
wire y_addr_out3__1_n_129;
wire y_addr_out3__1_n_130;
wire y_addr_out3__1_n_131;
wire y_addr_out3__1_n_132;
wire y_addr_out3__1_n_133;
wire y_addr_out3__1_n_134;
wire y_addr_out3__1_n_135;
wire y_addr_out3__1_n_136;
wire y_addr_out3__1_n_137;
wire y_addr_out3__1_n_138;
wire y_addr_out3__1_n_139;
wire y_addr_out3__1_n_140;
wire y_addr_out3__1_n_141;
wire y_addr_out3__1_n_142;
wire y_addr_out3__1_n_143;
wire y_addr_out3__1_n_144;
wire y_addr_out3__1_n_145;
wire y_addr_out3__1_n_146;
wire y_addr_out3__1_n_147;
wire y_addr_out3__1_n_148;
wire y_addr_out3__1_n_149;
wire y_addr_out3__1_n_150;
wire y_addr_out3__1_n_151;
wire y_addr_out3__1_n_152;
wire y_addr_out3__1_n_153;
wire y_addr_out3__1_n_58;
wire y_addr_out3__1_n_59;
wire y_addr_out3__1_n_60;
wire y_addr_out3__1_n_61;
wire y_addr_out3__1_n_62;
wire y_addr_out3__1_n_63;
wire y_addr_out3__1_n_64;
wire y_addr_out3__1_n_65;
wire y_addr_out3__1_n_66;
wire y_addr_out3__1_n_67;
wire y_addr_out3__1_n_68;
wire y_addr_out3__1_n_69;
wire y_addr_out3__1_n_70;
wire y_addr_out3__1_n_71;
wire y_addr_out3__1_n_72;
wire y_addr_out3__1_n_73;
wire y_addr_out3__1_n_74;
wire y_addr_out3__1_n_75;
wire y_addr_out3__1_n_76;
wire y_addr_out3__1_n_77;
wire y_addr_out3__1_n_78;
wire y_addr_out3__1_n_79;
wire y_addr_out3__1_n_80;
wire y_addr_out3__1_n_81;
wire y_addr_out3__1_n_82;
wire y_addr_out3__1_n_83;
wire y_addr_out3__1_n_84;
wire y_addr_out3__1_n_85;
wire y_addr_out3__1_n_86;
wire y_addr_out3__1_n_87;
wire y_addr_out3__1_n_88;
wire y_addr_out3__1_n_89;
wire y_addr_out3__1_n_90;
wire y_addr_out3__1_n_91;
wire y_addr_out3__1_n_92;
wire y_addr_out3__1_n_93;
wire y_addr_out3__1_n_94;
wire y_addr_out3__1_n_95;
wire y_addr_out3__1_n_96;
wire y_addr_out3__1_n_97;
wire y_addr_out3__1_n_98;
wire y_addr_out3__1_n_99;
wire y_addr_out3__2_n_100;
wire y_addr_out3__2_n_101;
wire y_addr_out3__2_n_102;
wire y_addr_out3__2_n_103;
wire y_addr_out3__2_n_104;
wire y_addr_out3__2_n_105;
wire y_addr_out3__2_n_58;
wire y_addr_out3__2_n_59;
wire y_addr_out3__2_n_60;
wire y_addr_out3__2_n_61;
wire y_addr_out3__2_n_62;
wire y_addr_out3__2_n_63;
wire y_addr_out3__2_n_64;
wire y_addr_out3__2_n_65;
wire y_addr_out3__2_n_66;
wire y_addr_out3__2_n_67;
wire y_addr_out3__2_n_68;
wire y_addr_out3__2_n_69;
wire y_addr_out3__2_n_70;
wire y_addr_out3__2_n_71;
wire y_addr_out3__2_n_72;
wire y_addr_out3__2_n_73;
wire y_addr_out3__2_n_74;
wire y_addr_out3__2_n_75;
wire y_addr_out3__2_n_76;
wire y_addr_out3__2_n_77;
wire y_addr_out3__2_n_78;
wire y_addr_out3__2_n_79;
wire y_addr_out3__2_n_80;
wire y_addr_out3__2_n_81;
wire y_addr_out3__2_n_82;
wire y_addr_out3__2_n_83;
wire y_addr_out3__2_n_84;
wire y_addr_out3__2_n_85;
wire y_addr_out3__2_n_86;
wire y_addr_out3__2_n_87;
wire y_addr_out3__2_n_88;
wire y_addr_out3__2_n_89;
wire y_addr_out3__2_n_90;
wire y_addr_out3__2_n_91;
wire y_addr_out3__2_n_92;
wire y_addr_out3__2_n_93;
wire y_addr_out3__2_n_94;
wire y_addr_out3__2_n_95;
wire y_addr_out3__2_n_96;
wire y_addr_out3__2_n_97;
wire y_addr_out3__2_n_98;
wire y_addr_out3__2_n_99;
wire y_addr_out3_n_100;
wire y_addr_out3_n_101;
wire y_addr_out3_n_102;
wire y_addr_out3_n_103;
wire y_addr_out3_n_104;
wire y_addr_out3_n_105;
wire y_addr_out3_n_106;
wire y_addr_out3_n_107;
wire y_addr_out3_n_108;
wire y_addr_out3_n_109;
wire y_addr_out3_n_110;
wire y_addr_out3_n_111;
wire y_addr_out3_n_112;
wire y_addr_out3_n_113;
wire y_addr_out3_n_114;
wire y_addr_out3_n_115;
wire y_addr_out3_n_116;
wire y_addr_out3_n_117;
wire y_addr_out3_n_118;
wire y_addr_out3_n_119;
wire y_addr_out3_n_120;
wire y_addr_out3_n_121;
wire y_addr_out3_n_122;
wire y_addr_out3_n_123;
wire y_addr_out3_n_124;
wire y_addr_out3_n_125;
wire y_addr_out3_n_126;
wire y_addr_out3_n_127;
wire y_addr_out3_n_128;
wire y_addr_out3_n_129;
wire y_addr_out3_n_130;
wire y_addr_out3_n_131;
wire y_addr_out3_n_132;
wire y_addr_out3_n_133;
wire y_addr_out3_n_134;
wire y_addr_out3_n_135;
wire y_addr_out3_n_136;
wire y_addr_out3_n_137;
wire y_addr_out3_n_138;
wire y_addr_out3_n_139;
wire y_addr_out3_n_140;
wire y_addr_out3_n_141;
wire y_addr_out3_n_142;
wire y_addr_out3_n_143;
wire y_addr_out3_n_144;
wire y_addr_out3_n_145;
wire y_addr_out3_n_146;
wire y_addr_out3_n_147;
wire y_addr_out3_n_148;
wire y_addr_out3_n_149;
wire y_addr_out3_n_150;
wire y_addr_out3_n_151;
wire y_addr_out3_n_152;
wire y_addr_out3_n_153;
wire y_addr_out3_n_58;
wire y_addr_out3_n_59;
wire y_addr_out3_n_60;
wire y_addr_out3_n_61;
wire y_addr_out3_n_62;
wire y_addr_out3_n_63;
wire y_addr_out3_n_64;
wire y_addr_out3_n_65;
wire y_addr_out3_n_66;
wire y_addr_out3_n_67;
wire y_addr_out3_n_68;
wire y_addr_out3_n_69;
wire y_addr_out3_n_70;
wire y_addr_out3_n_71;
wire y_addr_out3_n_72;
wire y_addr_out3_n_73;
wire y_addr_out3_n_74;
wire y_addr_out3_n_75;
wire y_addr_out3_n_76;
wire y_addr_out3_n_77;
wire y_addr_out3_n_78;
wire y_addr_out3_n_79;
wire y_addr_out3_n_80;
wire y_addr_out3_n_81;
wire y_addr_out3_n_82;
wire y_addr_out3_n_83;
wire y_addr_out3_n_84;
wire y_addr_out3_n_85;
wire y_addr_out3_n_86;
wire y_addr_out3_n_87;
wire y_addr_out3_n_88;
wire y_addr_out3_n_89;
wire y_addr_out3_n_90;
wire y_addr_out3_n_91;
wire y_addr_out3_n_92;
wire y_addr_out3_n_93;
wire y_addr_out3_n_94;
wire y_addr_out3_n_95;
wire y_addr_out3_n_96;
wire y_addr_out3_n_97;
wire y_addr_out3_n_98;
wire y_addr_out3_n_99;
wire [0:0]NLW_x_addr_out0_carry_O_UNCONNECTED;
wire [3:1]NLW_x_addr_out0_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_x_addr_out0_carry__1_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__0_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__1_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__2_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__3_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__4_O_UNCONNECTED;
wire [3:0]NLW_x_addr_out2_carry__5_O_UNCONNECTED;
wire [3:1]NLW_x_addr_out2_carry__8_CO_UNCONNECTED;
wire [3:2]NLW_x_addr_out2_carry__8_O_UNCONNECTED;
wire NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3_CARRYOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_x_addr_out3__0_PCOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__1_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__1_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED;
wire NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED;
wire NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED;
wire NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED;
wire NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_x_addr_out3__2_ACOUT_UNCONNECTED;
wire [17:0]NLW_x_addr_out3__2_BCOUT_UNCONNECTED;
wire [3:0]NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_x_addr_out3__2_PCOUT_UNCONNECTED;
wire [0:0]NLW_y_addr_out0_carry_O_UNCONNECTED;
wire [3:1]NLW_y_addr_out0_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_y_addr_out0_carry__1_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__0_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__1_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__2_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__3_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__4_O_UNCONNECTED;
wire [3:0]NLW_y_addr_out2_carry__5_O_UNCONNECTED;
wire [3:1]NLW_y_addr_out2_carry__8_CO_UNCONNECTED;
wire [3:2]NLW_y_addr_out2_carry__8_O_UNCONNECTED;
wire NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3_CARRYOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__0_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__0_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_y_addr_out3__0_PCOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__1_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__1_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED;
wire NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED;
wire NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED;
wire NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED;
wire NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED;
wire [29:0]NLW_y_addr_out3__2_ACOUT_UNCONNECTED;
wire [17:0]NLW_y_addr_out3__2_BCOUT_UNCONNECTED;
wire [3:0]NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED;
wire [47:0]NLW_y_addr_out3__2_PCOUT_UNCONNECTED;
CARRY4 x_addr_out0_carry
(.CI(1'b0),
.CO({x_addr_out0_carry_n_0,x_addr_out0_carry_n_1,x_addr_out0_carry_n_2,x_addr_out0_carry_n_3}),
.CYINIT(1'b0),
.DI(p_1_in[17:14]),
.O({x_addr_out0[17:15],NLW_x_addr_out0_carry_O_UNCONNECTED[0]}),
.S({x_addr_out0_carry_i_1_n_0,x_addr_out0_carry_i_2_n_0,x_addr_out0_carry_i_3_n_0,x_addr_out0[14]}));
CARRY4 x_addr_out0_carry__0
(.CI(x_addr_out0_carry_n_0),
.CO({x_addr_out0_carry__0_n_0,x_addr_out0_carry__0_n_1,x_addr_out0_carry__0_n_2,x_addr_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(p_1_in[21:18]),
.O(x_addr_out0[21:18]),
.S({x_addr_out0_carry__0_i_1_n_0,x_addr_out0_carry__0_i_2_n_0,x_addr_out0_carry__0_i_3_n_0,x_addr_out0_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_1
(.I0(p_1_in[21]),
.I1(t_x[7]),
.O(x_addr_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_2
(.I0(p_1_in[20]),
.I1(t_x[6]),
.O(x_addr_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_3
(.I0(p_1_in[19]),
.I1(t_x[5]),
.O(x_addr_out0_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__0_i_4
(.I0(p_1_in[18]),
.I1(t_x[4]),
.O(x_addr_out0_carry__0_i_4_n_0));
CARRY4 x_addr_out0_carry__1
(.CI(x_addr_out0_carry__0_n_0),
.CO({NLW_x_addr_out0_carry__1_CO_UNCONNECTED[3:1],x_addr_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_1_in[22]}),
.O({NLW_x_addr_out0_carry__1_O_UNCONNECTED[3:2],x_addr_out0[23:22]}),
.S({1'b0,1'b0,x_addr_out0_carry__1_i_1_n_0,x_addr_out0_carry__1_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__1_i_1
(.I0(p_1_in[23]),
.I1(t_x[9]),
.O(x_addr_out0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry__1_i_2
(.I0(p_1_in[22]),
.I1(t_x[8]),
.O(x_addr_out0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_1
(.I0(p_1_in[17]),
.I1(t_x[3]),
.O(x_addr_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_2
(.I0(p_1_in[16]),
.I1(t_x[2]),
.O(x_addr_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_3
(.I0(p_1_in[15]),
.I1(t_x[1]),
.O(x_addr_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out0_carry_i_4
(.I0(p_1_in[14]),
.I1(t_x[0]),
.O(x_addr_out0[14]));
CARRY4 x_addr_out2_carry
(.CI(1'b0),
.CO({x_addr_out2_carry_n_0,x_addr_out2_carry_n_1,x_addr_out2_carry_n_2,x_addr_out2_carry_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_102,x_addr_out3__1_n_103,x_addr_out3__1_n_104,x_addr_out3__1_n_105}),
.O(NLW_x_addr_out2_carry_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry_i_1_n_0,x_addr_out2_carry_i_2_n_0,x_addr_out2_carry_i_3_n_0,x_addr_out2_carry_i_4_n_0}));
CARRY4 x_addr_out2_carry__0
(.CI(x_addr_out2_carry_n_0),
.CO({x_addr_out2_carry__0_n_0,x_addr_out2_carry__0_n_1,x_addr_out2_carry__0_n_2,x_addr_out2_carry__0_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_98,x_addr_out3__1_n_99,x_addr_out3__1_n_100,x_addr_out3__1_n_101}),
.O(NLW_x_addr_out2_carry__0_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__0_i_1_n_0,x_addr_out2_carry__0_i_2_n_0,x_addr_out2_carry__0_i_3_n_0,x_addr_out2_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_1
(.I0(x_addr_out3__1_n_98),
.I1(x_addr_out3_n_98),
.O(x_addr_out2_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_2
(.I0(x_addr_out3__1_n_99),
.I1(x_addr_out3_n_99),
.O(x_addr_out2_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_3
(.I0(x_addr_out3__1_n_100),
.I1(x_addr_out3_n_100),
.O(x_addr_out2_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__0_i_4
(.I0(x_addr_out3__1_n_101),
.I1(x_addr_out3_n_101),
.O(x_addr_out2_carry__0_i_4_n_0));
CARRY4 x_addr_out2_carry__1
(.CI(x_addr_out2_carry__0_n_0),
.CO({x_addr_out2_carry__1_n_0,x_addr_out2_carry__1_n_1,x_addr_out2_carry__1_n_2,x_addr_out2_carry__1_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_94,x_addr_out3__1_n_95,x_addr_out3__1_n_96,x_addr_out3__1_n_97}),
.O(NLW_x_addr_out2_carry__1_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__1_i_1_n_0,x_addr_out2_carry__1_i_2_n_0,x_addr_out2_carry__1_i_3_n_0,x_addr_out2_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_1
(.I0(x_addr_out3__1_n_94),
.I1(x_addr_out3_n_94),
.O(x_addr_out2_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_2
(.I0(x_addr_out3__1_n_95),
.I1(x_addr_out3_n_95),
.O(x_addr_out2_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_3
(.I0(x_addr_out3__1_n_96),
.I1(x_addr_out3_n_96),
.O(x_addr_out2_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__1_i_4
(.I0(x_addr_out3__1_n_97),
.I1(x_addr_out3_n_97),
.O(x_addr_out2_carry__1_i_4_n_0));
CARRY4 x_addr_out2_carry__2
(.CI(x_addr_out2_carry__1_n_0),
.CO({x_addr_out2_carry__2_n_0,x_addr_out2_carry__2_n_1,x_addr_out2_carry__2_n_2,x_addr_out2_carry__2_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__1_n_90,x_addr_out3__1_n_91,x_addr_out3__1_n_92,x_addr_out3__1_n_93}),
.O(NLW_x_addr_out2_carry__2_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__2_i_1_n_0,x_addr_out2_carry__2_i_2_n_0,x_addr_out2_carry__2_i_3_n_0,x_addr_out2_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_1
(.I0(x_addr_out3__1_n_90),
.I1(x_addr_out3_n_90),
.O(x_addr_out2_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_2
(.I0(x_addr_out3__1_n_91),
.I1(x_addr_out3_n_91),
.O(x_addr_out2_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_3
(.I0(x_addr_out3__1_n_92),
.I1(x_addr_out3_n_92),
.O(x_addr_out2_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__2_i_4
(.I0(x_addr_out3__1_n_93),
.I1(x_addr_out3_n_93),
.O(x_addr_out2_carry__2_i_4_n_0));
CARRY4 x_addr_out2_carry__3
(.CI(x_addr_out2_carry__2_n_0),
.CO({x_addr_out2_carry__3_n_0,x_addr_out2_carry__3_n_1,x_addr_out2_carry__3_n_2,x_addr_out2_carry__3_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_103,x_addr_out3__2_n_104,x_addr_out3__2_n_105,x_addr_out3__1_n_89}),
.O(NLW_x_addr_out2_carry__3_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__3_i_1_n_0,x_addr_out2_carry__3_i_2_n_0,x_addr_out2_carry__3_i_3_n_0,x_addr_out2_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_1
(.I0(x_addr_out3__2_n_103),
.I1(x_addr_out3__0_n_103),
.O(x_addr_out2_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_2
(.I0(x_addr_out3__2_n_104),
.I1(x_addr_out3__0_n_104),
.O(x_addr_out2_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_3
(.I0(x_addr_out3__2_n_105),
.I1(x_addr_out3__0_n_105),
.O(x_addr_out2_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__3_i_4
(.I0(x_addr_out3__1_n_89),
.I1(x_addr_out3_n_89),
.O(x_addr_out2_carry__3_i_4_n_0));
CARRY4 x_addr_out2_carry__4
(.CI(x_addr_out2_carry__3_n_0),
.CO({x_addr_out2_carry__4_n_0,x_addr_out2_carry__4_n_1,x_addr_out2_carry__4_n_2,x_addr_out2_carry__4_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_99,x_addr_out3__2_n_100,x_addr_out3__2_n_101,x_addr_out3__2_n_102}),
.O(NLW_x_addr_out2_carry__4_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__4_i_1_n_0,x_addr_out2_carry__4_i_2_n_0,x_addr_out2_carry__4_i_3_n_0,x_addr_out2_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_1
(.I0(x_addr_out3__2_n_99),
.I1(x_addr_out3__0_n_99),
.O(x_addr_out2_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_2
(.I0(x_addr_out3__2_n_100),
.I1(x_addr_out3__0_n_100),
.O(x_addr_out2_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_3
(.I0(x_addr_out3__2_n_101),
.I1(x_addr_out3__0_n_101),
.O(x_addr_out2_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__4_i_4
(.I0(x_addr_out3__2_n_102),
.I1(x_addr_out3__0_n_102),
.O(x_addr_out2_carry__4_i_4_n_0));
CARRY4 x_addr_out2_carry__5
(.CI(x_addr_out2_carry__4_n_0),
.CO({x_addr_out2_carry__5_n_0,x_addr_out2_carry__5_n_1,x_addr_out2_carry__5_n_2,x_addr_out2_carry__5_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_95,x_addr_out3__2_n_96,x_addr_out3__2_n_97,x_addr_out3__2_n_98}),
.O(NLW_x_addr_out2_carry__5_O_UNCONNECTED[3:0]),
.S({x_addr_out2_carry__5_i_1_n_0,x_addr_out2_carry__5_i_2_n_0,x_addr_out2_carry__5_i_3_n_0,x_addr_out2_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_1
(.I0(x_addr_out3__2_n_95),
.I1(x_addr_out3__0_n_95),
.O(x_addr_out2_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_2
(.I0(x_addr_out3__2_n_96),
.I1(x_addr_out3__0_n_96),
.O(x_addr_out2_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_3
(.I0(x_addr_out3__2_n_97),
.I1(x_addr_out3__0_n_97),
.O(x_addr_out2_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__5_i_4
(.I0(x_addr_out3__2_n_98),
.I1(x_addr_out3__0_n_98),
.O(x_addr_out2_carry__5_i_4_n_0));
CARRY4 x_addr_out2_carry__6
(.CI(x_addr_out2_carry__5_n_0),
.CO({x_addr_out2_carry__6_n_0,x_addr_out2_carry__6_n_1,x_addr_out2_carry__6_n_2,x_addr_out2_carry__6_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_91,x_addr_out3__2_n_92,x_addr_out3__2_n_93,x_addr_out3__2_n_94}),
.O(p_1_in[17:14]),
.S({x_addr_out2_carry__6_i_1_n_0,x_addr_out2_carry__6_i_2_n_0,x_addr_out2_carry__6_i_3_n_0,x_addr_out2_carry__6_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_1
(.I0(x_addr_out3__2_n_91),
.I1(x_addr_out3__0_n_91),
.O(x_addr_out2_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_2
(.I0(x_addr_out3__2_n_92),
.I1(x_addr_out3__0_n_92),
.O(x_addr_out2_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_3
(.I0(x_addr_out3__2_n_93),
.I1(x_addr_out3__0_n_93),
.O(x_addr_out2_carry__6_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__6_i_4
(.I0(x_addr_out3__2_n_94),
.I1(x_addr_out3__0_n_94),
.O(x_addr_out2_carry__6_i_4_n_0));
CARRY4 x_addr_out2_carry__7
(.CI(x_addr_out2_carry__6_n_0),
.CO({x_addr_out2_carry__7_n_0,x_addr_out2_carry__7_n_1,x_addr_out2_carry__7_n_2,x_addr_out2_carry__7_n_3}),
.CYINIT(1'b0),
.DI({x_addr_out3__2_n_87,x_addr_out3__2_n_88,x_addr_out3__2_n_89,x_addr_out3__2_n_90}),
.O(p_1_in[21:18]),
.S({x_addr_out2_carry__7_i_1_n_0,x_addr_out2_carry__7_i_2_n_0,x_addr_out2_carry__7_i_3_n_0,x_addr_out2_carry__7_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_1
(.I0(x_addr_out3__2_n_87),
.I1(x_addr_out3__0_n_87),
.O(x_addr_out2_carry__7_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_2
(.I0(x_addr_out3__2_n_88),
.I1(x_addr_out3__0_n_88),
.O(x_addr_out2_carry__7_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_3
(.I0(x_addr_out3__2_n_89),
.I1(x_addr_out3__0_n_89),
.O(x_addr_out2_carry__7_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__7_i_4
(.I0(x_addr_out3__2_n_90),
.I1(x_addr_out3__0_n_90),
.O(x_addr_out2_carry__7_i_4_n_0));
CARRY4 x_addr_out2_carry__8
(.CI(x_addr_out2_carry__7_n_0),
.CO({NLW_x_addr_out2_carry__8_CO_UNCONNECTED[3:1],x_addr_out2_carry__8_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,x_addr_out3__2_n_86}),
.O({NLW_x_addr_out2_carry__8_O_UNCONNECTED[3:2],p_1_in[23:22]}),
.S({1'b0,1'b0,x_addr_out2_carry__8_i_1_n_0,x_addr_out2_carry__8_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__8_i_1
(.I0(x_addr_out3__2_n_85),
.I1(x_addr_out3__0_n_85),
.O(x_addr_out2_carry__8_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry__8_i_2
(.I0(x_addr_out3__2_n_86),
.I1(x_addr_out3__0_n_86),
.O(x_addr_out2_carry__8_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_1
(.I0(x_addr_out3__1_n_102),
.I1(x_addr_out3_n_102),
.O(x_addr_out2_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_2
(.I0(x_addr_out3__1_n_103),
.I1(x_addr_out3_n_103),
.O(x_addr_out2_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_3
(.I0(x_addr_out3__1_n_104),
.I1(x_addr_out3_n_104),
.O(x_addr_out2_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
x_addr_out2_carry_i_4
(.I0(x_addr_out3__1_n_105),
.I1(x_addr_out3_n_105),
.O(x_addr_out2_carry_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m01[15],rot_m01[15],rot_m01}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3_OVERFLOW_UNCONNECTED),
.P({x_addr_out3_n_58,x_addr_out3_n_59,x_addr_out3_n_60,x_addr_out3_n_61,x_addr_out3_n_62,x_addr_out3_n_63,x_addr_out3_n_64,x_addr_out3_n_65,x_addr_out3_n_66,x_addr_out3_n_67,x_addr_out3_n_68,x_addr_out3_n_69,x_addr_out3_n_70,x_addr_out3_n_71,x_addr_out3_n_72,x_addr_out3_n_73,x_addr_out3_n_74,x_addr_out3_n_75,x_addr_out3_n_76,x_addr_out3_n_77,x_addr_out3_n_78,x_addr_out3_n_79,x_addr_out3_n_80,x_addr_out3_n_81,x_addr_out3_n_82,x_addr_out3_n_83,x_addr_out3_n_84,x_addr_out3_n_85,x_addr_out3_n_86,x_addr_out3_n_87,x_addr_out3_n_88,x_addr_out3_n_89,x_addr_out3_n_90,x_addr_out3_n_91,x_addr_out3_n_92,x_addr_out3_n_93,x_addr_out3_n_94,x_addr_out3_n_95,x_addr_out3_n_96,x_addr_out3_n_97,x_addr_out3_n_98,x_addr_out3_n_99,x_addr_out3_n_100,x_addr_out3_n_101,x_addr_out3_n_102,x_addr_out3_n_103,x_addr_out3_n_104,x_addr_out3_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({x_addr_out3_n_106,x_addr_out3_n_107,x_addr_out3_n_108,x_addr_out3_n_109,x_addr_out3_n_110,x_addr_out3_n_111,x_addr_out3_n_112,x_addr_out3_n_113,x_addr_out3_n_114,x_addr_out3_n_115,x_addr_out3_n_116,x_addr_out3_n_117,x_addr_out3_n_118,x_addr_out3_n_119,x_addr_out3_n_120,x_addr_out3_n_121,x_addr_out3_n_122,x_addr_out3_n_123,x_addr_out3_n_124,x_addr_out3_n_125,x_addr_out3_n_126,x_addr_out3_n_127,x_addr_out3_n_128,x_addr_out3_n_129,x_addr_out3_n_130,x_addr_out3_n_131,x_addr_out3_n_132,x_addr_out3_n_133,x_addr_out3_n_134,x_addr_out3_n_135,x_addr_out3_n_136,x_addr_out3_n_137,x_addr_out3_n_138,x_addr_out3_n_139,x_addr_out3_n_140,x_addr_out3_n_141,x_addr_out3_n_142,x_addr_out3_n_143,x_addr_out3_n_144,x_addr_out3_n_145,x_addr_out3_n_146,x_addr_out3_n_147,x_addr_out3_n_148,x_addr_out3_n_149,x_addr_out3_n_150,x_addr_out3_n_151,x_addr_out3_n_152,x_addr_out3_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__0
(.A({rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01[15],rot_m01}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__0_n_58,x_addr_out3__0_n_59,x_addr_out3__0_n_60,x_addr_out3__0_n_61,x_addr_out3__0_n_62,x_addr_out3__0_n_63,x_addr_out3__0_n_64,x_addr_out3__0_n_65,x_addr_out3__0_n_66,x_addr_out3__0_n_67,x_addr_out3__0_n_68,x_addr_out3__0_n_69,x_addr_out3__0_n_70,x_addr_out3__0_n_71,x_addr_out3__0_n_72,x_addr_out3__0_n_73,x_addr_out3__0_n_74,x_addr_out3__0_n_75,x_addr_out3__0_n_76,x_addr_out3__0_n_77,x_addr_out3__0_n_78,x_addr_out3__0_n_79,x_addr_out3__0_n_80,x_addr_out3__0_n_81,x_addr_out3__0_n_82,x_addr_out3__0_n_83,x_addr_out3__0_n_84,x_addr_out3__0_n_85,x_addr_out3__0_n_86,x_addr_out3__0_n_87,x_addr_out3__0_n_88,x_addr_out3__0_n_89,x_addr_out3__0_n_90,x_addr_out3__0_n_91,x_addr_out3__0_n_92,x_addr_out3__0_n_93,x_addr_out3__0_n_94,x_addr_out3__0_n_95,x_addr_out3__0_n_96,x_addr_out3__0_n_97,x_addr_out3__0_n_98,x_addr_out3__0_n_99,x_addr_out3__0_n_100,x_addr_out3__0_n_101,x_addr_out3__0_n_102,x_addr_out3__0_n_103,x_addr_out3__0_n_104,x_addr_out3__0_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED),
.PCIN({x_addr_out3_n_106,x_addr_out3_n_107,x_addr_out3_n_108,x_addr_out3_n_109,x_addr_out3_n_110,x_addr_out3_n_111,x_addr_out3_n_112,x_addr_out3_n_113,x_addr_out3_n_114,x_addr_out3_n_115,x_addr_out3_n_116,x_addr_out3_n_117,x_addr_out3_n_118,x_addr_out3_n_119,x_addr_out3_n_120,x_addr_out3_n_121,x_addr_out3_n_122,x_addr_out3_n_123,x_addr_out3_n_124,x_addr_out3_n_125,x_addr_out3_n_126,x_addr_out3_n_127,x_addr_out3_n_128,x_addr_out3_n_129,x_addr_out3_n_130,x_addr_out3_n_131,x_addr_out3_n_132,x_addr_out3_n_133,x_addr_out3_n_134,x_addr_out3_n_135,x_addr_out3_n_136,x_addr_out3_n_137,x_addr_out3_n_138,x_addr_out3_n_139,x_addr_out3_n_140,x_addr_out3_n_141,x_addr_out3_n_142,x_addr_out3_n_143,x_addr_out3_n_144,x_addr_out3_n_145,x_addr_out3_n_146,x_addr_out3_n_147,x_addr_out3_n_148,x_addr_out3_n_149,x_addr_out3_n_150,x_addr_out3_n_151,x_addr_out3_n_152,x_addr_out3_n_153}),
.PCOUT(NLW_x_addr_out3__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__1
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m00[15],rot_m00[15],rot_m00}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__1_n_58,x_addr_out3__1_n_59,x_addr_out3__1_n_60,x_addr_out3__1_n_61,x_addr_out3__1_n_62,x_addr_out3__1_n_63,x_addr_out3__1_n_64,x_addr_out3__1_n_65,x_addr_out3__1_n_66,x_addr_out3__1_n_67,x_addr_out3__1_n_68,x_addr_out3__1_n_69,x_addr_out3__1_n_70,x_addr_out3__1_n_71,x_addr_out3__1_n_72,x_addr_out3__1_n_73,x_addr_out3__1_n_74,x_addr_out3__1_n_75,x_addr_out3__1_n_76,x_addr_out3__1_n_77,x_addr_out3__1_n_78,x_addr_out3__1_n_79,x_addr_out3__1_n_80,x_addr_out3__1_n_81,x_addr_out3__1_n_82,x_addr_out3__1_n_83,x_addr_out3__1_n_84,x_addr_out3__1_n_85,x_addr_out3__1_n_86,x_addr_out3__1_n_87,x_addr_out3__1_n_88,x_addr_out3__1_n_89,x_addr_out3__1_n_90,x_addr_out3__1_n_91,x_addr_out3__1_n_92,x_addr_out3__1_n_93,x_addr_out3__1_n_94,x_addr_out3__1_n_95,x_addr_out3__1_n_96,x_addr_out3__1_n_97,x_addr_out3__1_n_98,x_addr_out3__1_n_99,x_addr_out3__1_n_100,x_addr_out3__1_n_101,x_addr_out3__1_n_102,x_addr_out3__1_n_103,x_addr_out3__1_n_104,x_addr_out3__1_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({x_addr_out3__1_n_106,x_addr_out3__1_n_107,x_addr_out3__1_n_108,x_addr_out3__1_n_109,x_addr_out3__1_n_110,x_addr_out3__1_n_111,x_addr_out3__1_n_112,x_addr_out3__1_n_113,x_addr_out3__1_n_114,x_addr_out3__1_n_115,x_addr_out3__1_n_116,x_addr_out3__1_n_117,x_addr_out3__1_n_118,x_addr_out3__1_n_119,x_addr_out3__1_n_120,x_addr_out3__1_n_121,x_addr_out3__1_n_122,x_addr_out3__1_n_123,x_addr_out3__1_n_124,x_addr_out3__1_n_125,x_addr_out3__1_n_126,x_addr_out3__1_n_127,x_addr_out3__1_n_128,x_addr_out3__1_n_129,x_addr_out3__1_n_130,x_addr_out3__1_n_131,x_addr_out3__1_n_132,x_addr_out3__1_n_133,x_addr_out3__1_n_134,x_addr_out3__1_n_135,x_addr_out3__1_n_136,x_addr_out3__1_n_137,x_addr_out3__1_n_138,x_addr_out3__1_n_139,x_addr_out3__1_n_140,x_addr_out3__1_n_141,x_addr_out3__1_n_142,x_addr_out3__1_n_143,x_addr_out3__1_n_144,x_addr_out3__1_n_145,x_addr_out3__1_n_146,x_addr_out3__1_n_147,x_addr_out3__1_n_148,x_addr_out3__1_n_149,x_addr_out3__1_n_150,x_addr_out3__1_n_151,x_addr_out3__1_n_152,x_addr_out3__1_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
x_addr_out3__2
(.A({rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00[15],rot_m00}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_x_addr_out3__2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_x_addr_out3__2_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED),
.P({x_addr_out3__2_n_58,x_addr_out3__2_n_59,x_addr_out3__2_n_60,x_addr_out3__2_n_61,x_addr_out3__2_n_62,x_addr_out3__2_n_63,x_addr_out3__2_n_64,x_addr_out3__2_n_65,x_addr_out3__2_n_66,x_addr_out3__2_n_67,x_addr_out3__2_n_68,x_addr_out3__2_n_69,x_addr_out3__2_n_70,x_addr_out3__2_n_71,x_addr_out3__2_n_72,x_addr_out3__2_n_73,x_addr_out3__2_n_74,x_addr_out3__2_n_75,x_addr_out3__2_n_76,x_addr_out3__2_n_77,x_addr_out3__2_n_78,x_addr_out3__2_n_79,x_addr_out3__2_n_80,x_addr_out3__2_n_81,x_addr_out3__2_n_82,x_addr_out3__2_n_83,x_addr_out3__2_n_84,x_addr_out3__2_n_85,x_addr_out3__2_n_86,x_addr_out3__2_n_87,x_addr_out3__2_n_88,x_addr_out3__2_n_89,x_addr_out3__2_n_90,x_addr_out3__2_n_91,x_addr_out3__2_n_92,x_addr_out3__2_n_93,x_addr_out3__2_n_94,x_addr_out3__2_n_95,x_addr_out3__2_n_96,x_addr_out3__2_n_97,x_addr_out3__2_n_98,x_addr_out3__2_n_99,x_addr_out3__2_n_100,x_addr_out3__2_n_101,x_addr_out3__2_n_102,x_addr_out3__2_n_103,x_addr_out3__2_n_104,x_addr_out3__2_n_105}),
.PATTERNBDETECT(NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED),
.PCIN({x_addr_out3__1_n_106,x_addr_out3__1_n_107,x_addr_out3__1_n_108,x_addr_out3__1_n_109,x_addr_out3__1_n_110,x_addr_out3__1_n_111,x_addr_out3__1_n_112,x_addr_out3__1_n_113,x_addr_out3__1_n_114,x_addr_out3__1_n_115,x_addr_out3__1_n_116,x_addr_out3__1_n_117,x_addr_out3__1_n_118,x_addr_out3__1_n_119,x_addr_out3__1_n_120,x_addr_out3__1_n_121,x_addr_out3__1_n_122,x_addr_out3__1_n_123,x_addr_out3__1_n_124,x_addr_out3__1_n_125,x_addr_out3__1_n_126,x_addr_out3__1_n_127,x_addr_out3__1_n_128,x_addr_out3__1_n_129,x_addr_out3__1_n_130,x_addr_out3__1_n_131,x_addr_out3__1_n_132,x_addr_out3__1_n_133,x_addr_out3__1_n_134,x_addr_out3__1_n_135,x_addr_out3__1_n_136,x_addr_out3__1_n_137,x_addr_out3__1_n_138,x_addr_out3__1_n_139,x_addr_out3__1_n_140,x_addr_out3__1_n_141,x_addr_out3__1_n_142,x_addr_out3__1_n_143,x_addr_out3__1_n_144,x_addr_out3__1_n_145,x_addr_out3__1_n_146,x_addr_out3__1_n_147,x_addr_out3__1_n_148,x_addr_out3__1_n_149,x_addr_out3__1_n_150,x_addr_out3__1_n_151,x_addr_out3__1_n_152,x_addr_out3__1_n_153}),
.PCOUT(NLW_x_addr_out3__2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED));
LUT4 #(
.INIT(16'h66F0))
\x_addr_out[0]_i_1
(.I0(p_1_in[14]),
.I1(t_x[0]),
.I2(x_addr_in[0]),
.I3(enable),
.O(\x_addr_out[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[1]_i_1
(.I0(x_addr_out0[15]),
.I1(x_addr_in[1]),
.I2(enable),
.O(\x_addr_out[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[2]_i_1
(.I0(x_addr_out0[16]),
.I1(x_addr_in[2]),
.I2(enable),
.O(\x_addr_out[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[3]_i_1
(.I0(x_addr_out0[17]),
.I1(x_addr_in[3]),
.I2(enable),
.O(\x_addr_out[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[4]_i_1
(.I0(x_addr_out0[18]),
.I1(x_addr_in[4]),
.I2(enable),
.O(\x_addr_out[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[5]_i_1
(.I0(x_addr_out0[19]),
.I1(x_addr_in[5]),
.I2(enable),
.O(\x_addr_out[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[6]_i_1
(.I0(x_addr_out0[20]),
.I1(x_addr_in[6]),
.I2(enable),
.O(\x_addr_out[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[7]_i_1
(.I0(x_addr_out0[21]),
.I1(x_addr_in[7]),
.I2(enable),
.O(\x_addr_out[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\x_addr_out[8]_i_1
(.I0(x_addr_out0[22]),
.I1(x_addr_in[8]),
.I2(enable),
.O(\x_addr_out[8]_i_1_n_0 ));
LUT3 #(
.INIT(8'hAC))
\x_addr_out[9]_i_1
(.I0(x_addr_out0[23]),
.I1(x_addr_in[9]),
.I2(enable),
.O(\x_addr_out[9]_i_1_n_0 ));
FDRE \x_addr_out_reg[0]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[0]_i_1_n_0 ),
.Q(x_addr_out[0]),
.R(1'b0));
FDRE \x_addr_out_reg[1]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[1]_i_1_n_0 ),
.Q(x_addr_out[1]),
.R(1'b0));
FDRE \x_addr_out_reg[2]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[2]_i_1_n_0 ),
.Q(x_addr_out[2]),
.R(1'b0));
FDRE \x_addr_out_reg[3]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[3]_i_1_n_0 ),
.Q(x_addr_out[3]),
.R(1'b0));
FDRE \x_addr_out_reg[4]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[4]_i_1_n_0 ),
.Q(x_addr_out[4]),
.R(1'b0));
FDRE \x_addr_out_reg[5]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[5]_i_1_n_0 ),
.Q(x_addr_out[5]),
.R(1'b0));
FDRE \x_addr_out_reg[6]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[6]_i_1_n_0 ),
.Q(x_addr_out[6]),
.R(1'b0));
FDRE \x_addr_out_reg[7]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[7]_i_1_n_0 ),
.Q(x_addr_out[7]),
.R(1'b0));
FDRE \x_addr_out_reg[8]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[8]_i_1_n_0 ),
.Q(x_addr_out[8]),
.R(1'b0));
FDRE \x_addr_out_reg[9]
(.C(clk),
.CE(1'b1),
.D(\x_addr_out[9]_i_1_n_0 ),
.Q(x_addr_out[9]),
.R(1'b0));
CARRY4 y_addr_out0_carry
(.CI(1'b0),
.CO({y_addr_out0_carry_n_0,y_addr_out0_carry_n_1,y_addr_out0_carry_n_2,y_addr_out0_carry_n_3}),
.CYINIT(1'b0),
.DI(y_addr_out2[31:28]),
.O({p_0_in[3:1],NLW_y_addr_out0_carry_O_UNCONNECTED[0]}),
.S({y_addr_out0_carry_i_1_n_0,y_addr_out0_carry_i_2_n_0,y_addr_out0_carry_i_3_n_0,y_addr_out0_carry_i_4_n_0}));
CARRY4 y_addr_out0_carry__0
(.CI(y_addr_out0_carry_n_0),
.CO({y_addr_out0_carry__0_n_0,y_addr_out0_carry__0_n_1,y_addr_out0_carry__0_n_2,y_addr_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(y_addr_out2[35:32]),
.O(p_0_in[7:4]),
.S({y_addr_out0_carry__0_i_1_n_0,y_addr_out0_carry__0_i_2_n_0,y_addr_out0_carry__0_i_3_n_0,y_addr_out0_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_1
(.I0(y_addr_out2[35]),
.I1(t_y[7]),
.O(y_addr_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_2
(.I0(y_addr_out2[34]),
.I1(t_y[6]),
.O(y_addr_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_3
(.I0(y_addr_out2[33]),
.I1(t_y[5]),
.O(y_addr_out0_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__0_i_4
(.I0(y_addr_out2[32]),
.I1(t_y[4]),
.O(y_addr_out0_carry__0_i_4_n_0));
CARRY4 y_addr_out0_carry__1
(.CI(y_addr_out0_carry__0_n_0),
.CO({NLW_y_addr_out0_carry__1_CO_UNCONNECTED[3:1],y_addr_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,y_addr_out2[36]}),
.O({NLW_y_addr_out0_carry__1_O_UNCONNECTED[3:2],p_0_in[9:8]}),
.S({1'b0,1'b0,y_addr_out0_carry__1_i_1_n_0,y_addr_out0_carry__1_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__1_i_1
(.I0(y_addr_out2[37]),
.I1(t_y[9]),
.O(y_addr_out0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry__1_i_2
(.I0(y_addr_out2[36]),
.I1(t_y[8]),
.O(y_addr_out0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_1
(.I0(y_addr_out2[31]),
.I1(t_y[3]),
.O(y_addr_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_2
(.I0(y_addr_out2[30]),
.I1(t_y[2]),
.O(y_addr_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_3
(.I0(y_addr_out2[29]),
.I1(t_y[1]),
.O(y_addr_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out0_carry_i_4
(.I0(y_addr_out2[28]),
.I1(t_y[0]),
.O(y_addr_out0_carry_i_4_n_0));
CARRY4 y_addr_out2_carry
(.CI(1'b0),
.CO({y_addr_out2_carry_n_0,y_addr_out2_carry_n_1,y_addr_out2_carry_n_2,y_addr_out2_carry_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_102,y_addr_out3__1_n_103,y_addr_out3__1_n_104,y_addr_out3__1_n_105}),
.O(NLW_y_addr_out2_carry_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry_i_1_n_0,y_addr_out2_carry_i_2_n_0,y_addr_out2_carry_i_3_n_0,y_addr_out2_carry_i_4_n_0}));
CARRY4 y_addr_out2_carry__0
(.CI(y_addr_out2_carry_n_0),
.CO({y_addr_out2_carry__0_n_0,y_addr_out2_carry__0_n_1,y_addr_out2_carry__0_n_2,y_addr_out2_carry__0_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_98,y_addr_out3__1_n_99,y_addr_out3__1_n_100,y_addr_out3__1_n_101}),
.O(NLW_y_addr_out2_carry__0_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__0_i_1_n_0,y_addr_out2_carry__0_i_2_n_0,y_addr_out2_carry__0_i_3_n_0,y_addr_out2_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_1
(.I0(y_addr_out3__1_n_98),
.I1(y_addr_out3_n_98),
.O(y_addr_out2_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_2
(.I0(y_addr_out3__1_n_99),
.I1(y_addr_out3_n_99),
.O(y_addr_out2_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_3
(.I0(y_addr_out3__1_n_100),
.I1(y_addr_out3_n_100),
.O(y_addr_out2_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__0_i_4
(.I0(y_addr_out3__1_n_101),
.I1(y_addr_out3_n_101),
.O(y_addr_out2_carry__0_i_4_n_0));
CARRY4 y_addr_out2_carry__1
(.CI(y_addr_out2_carry__0_n_0),
.CO({y_addr_out2_carry__1_n_0,y_addr_out2_carry__1_n_1,y_addr_out2_carry__1_n_2,y_addr_out2_carry__1_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_94,y_addr_out3__1_n_95,y_addr_out3__1_n_96,y_addr_out3__1_n_97}),
.O(NLW_y_addr_out2_carry__1_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__1_i_1_n_0,y_addr_out2_carry__1_i_2_n_0,y_addr_out2_carry__1_i_3_n_0,y_addr_out2_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_1
(.I0(y_addr_out3__1_n_94),
.I1(y_addr_out3_n_94),
.O(y_addr_out2_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_2
(.I0(y_addr_out3__1_n_95),
.I1(y_addr_out3_n_95),
.O(y_addr_out2_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_3
(.I0(y_addr_out3__1_n_96),
.I1(y_addr_out3_n_96),
.O(y_addr_out2_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__1_i_4
(.I0(y_addr_out3__1_n_97),
.I1(y_addr_out3_n_97),
.O(y_addr_out2_carry__1_i_4_n_0));
CARRY4 y_addr_out2_carry__2
(.CI(y_addr_out2_carry__1_n_0),
.CO({y_addr_out2_carry__2_n_0,y_addr_out2_carry__2_n_1,y_addr_out2_carry__2_n_2,y_addr_out2_carry__2_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__1_n_90,y_addr_out3__1_n_91,y_addr_out3__1_n_92,y_addr_out3__1_n_93}),
.O(NLW_y_addr_out2_carry__2_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__2_i_1_n_0,y_addr_out2_carry__2_i_2_n_0,y_addr_out2_carry__2_i_3_n_0,y_addr_out2_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_1
(.I0(y_addr_out3__1_n_90),
.I1(y_addr_out3_n_90),
.O(y_addr_out2_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_2
(.I0(y_addr_out3__1_n_91),
.I1(y_addr_out3_n_91),
.O(y_addr_out2_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_3
(.I0(y_addr_out3__1_n_92),
.I1(y_addr_out3_n_92),
.O(y_addr_out2_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__2_i_4
(.I0(y_addr_out3__1_n_93),
.I1(y_addr_out3_n_93),
.O(y_addr_out2_carry__2_i_4_n_0));
CARRY4 y_addr_out2_carry__3
(.CI(y_addr_out2_carry__2_n_0),
.CO({y_addr_out2_carry__3_n_0,y_addr_out2_carry__3_n_1,y_addr_out2_carry__3_n_2,y_addr_out2_carry__3_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_103,y_addr_out3__2_n_104,y_addr_out3__2_n_105,y_addr_out3__1_n_89}),
.O(NLW_y_addr_out2_carry__3_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__3_i_1_n_0,y_addr_out2_carry__3_i_2_n_0,y_addr_out2_carry__3_i_3_n_0,y_addr_out2_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_1
(.I0(y_addr_out3__2_n_103),
.I1(y_addr_out3__0_n_103),
.O(y_addr_out2_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_2
(.I0(y_addr_out3__2_n_104),
.I1(y_addr_out3__0_n_104),
.O(y_addr_out2_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_3
(.I0(y_addr_out3__2_n_105),
.I1(y_addr_out3__0_n_105),
.O(y_addr_out2_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__3_i_4
(.I0(y_addr_out3__1_n_89),
.I1(y_addr_out3_n_89),
.O(y_addr_out2_carry__3_i_4_n_0));
CARRY4 y_addr_out2_carry__4
(.CI(y_addr_out2_carry__3_n_0),
.CO({y_addr_out2_carry__4_n_0,y_addr_out2_carry__4_n_1,y_addr_out2_carry__4_n_2,y_addr_out2_carry__4_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_99,y_addr_out3__2_n_100,y_addr_out3__2_n_101,y_addr_out3__2_n_102}),
.O(NLW_y_addr_out2_carry__4_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__4_i_1_n_0,y_addr_out2_carry__4_i_2_n_0,y_addr_out2_carry__4_i_3_n_0,y_addr_out2_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_1
(.I0(y_addr_out3__2_n_99),
.I1(y_addr_out3__0_n_99),
.O(y_addr_out2_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_2
(.I0(y_addr_out3__2_n_100),
.I1(y_addr_out3__0_n_100),
.O(y_addr_out2_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_3
(.I0(y_addr_out3__2_n_101),
.I1(y_addr_out3__0_n_101),
.O(y_addr_out2_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__4_i_4
(.I0(y_addr_out3__2_n_102),
.I1(y_addr_out3__0_n_102),
.O(y_addr_out2_carry__4_i_4_n_0));
CARRY4 y_addr_out2_carry__5
(.CI(y_addr_out2_carry__4_n_0),
.CO({y_addr_out2_carry__5_n_0,y_addr_out2_carry__5_n_1,y_addr_out2_carry__5_n_2,y_addr_out2_carry__5_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_95,y_addr_out3__2_n_96,y_addr_out3__2_n_97,y_addr_out3__2_n_98}),
.O(NLW_y_addr_out2_carry__5_O_UNCONNECTED[3:0]),
.S({y_addr_out2_carry__5_i_1_n_0,y_addr_out2_carry__5_i_2_n_0,y_addr_out2_carry__5_i_3_n_0,y_addr_out2_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_1
(.I0(y_addr_out3__2_n_95),
.I1(y_addr_out3__0_n_95),
.O(y_addr_out2_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_2
(.I0(y_addr_out3__2_n_96),
.I1(y_addr_out3__0_n_96),
.O(y_addr_out2_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_3
(.I0(y_addr_out3__2_n_97),
.I1(y_addr_out3__0_n_97),
.O(y_addr_out2_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__5_i_4
(.I0(y_addr_out3__2_n_98),
.I1(y_addr_out3__0_n_98),
.O(y_addr_out2_carry__5_i_4_n_0));
CARRY4 y_addr_out2_carry__6
(.CI(y_addr_out2_carry__5_n_0),
.CO({y_addr_out2_carry__6_n_0,y_addr_out2_carry__6_n_1,y_addr_out2_carry__6_n_2,y_addr_out2_carry__6_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_91,y_addr_out3__2_n_92,y_addr_out3__2_n_93,y_addr_out3__2_n_94}),
.O(y_addr_out2[31:28]),
.S({y_addr_out2_carry__6_i_1_n_0,y_addr_out2_carry__6_i_2_n_0,y_addr_out2_carry__6_i_3_n_0,y_addr_out2_carry__6_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_1
(.I0(y_addr_out3__2_n_91),
.I1(y_addr_out3__0_n_91),
.O(y_addr_out2_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_2
(.I0(y_addr_out3__2_n_92),
.I1(y_addr_out3__0_n_92),
.O(y_addr_out2_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_3
(.I0(y_addr_out3__2_n_93),
.I1(y_addr_out3__0_n_93),
.O(y_addr_out2_carry__6_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__6_i_4
(.I0(y_addr_out3__2_n_94),
.I1(y_addr_out3__0_n_94),
.O(y_addr_out2_carry__6_i_4_n_0));
CARRY4 y_addr_out2_carry__7
(.CI(y_addr_out2_carry__6_n_0),
.CO({y_addr_out2_carry__7_n_0,y_addr_out2_carry__7_n_1,y_addr_out2_carry__7_n_2,y_addr_out2_carry__7_n_3}),
.CYINIT(1'b0),
.DI({y_addr_out3__2_n_87,y_addr_out3__2_n_88,y_addr_out3__2_n_89,y_addr_out3__2_n_90}),
.O(y_addr_out2[35:32]),
.S({y_addr_out2_carry__7_i_1_n_0,y_addr_out2_carry__7_i_2_n_0,y_addr_out2_carry__7_i_3_n_0,y_addr_out2_carry__7_i_4_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_1
(.I0(y_addr_out3__2_n_87),
.I1(y_addr_out3__0_n_87),
.O(y_addr_out2_carry__7_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_2
(.I0(y_addr_out3__2_n_88),
.I1(y_addr_out3__0_n_88),
.O(y_addr_out2_carry__7_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_3
(.I0(y_addr_out3__2_n_89),
.I1(y_addr_out3__0_n_89),
.O(y_addr_out2_carry__7_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__7_i_4
(.I0(y_addr_out3__2_n_90),
.I1(y_addr_out3__0_n_90),
.O(y_addr_out2_carry__7_i_4_n_0));
CARRY4 y_addr_out2_carry__8
(.CI(y_addr_out2_carry__7_n_0),
.CO({NLW_y_addr_out2_carry__8_CO_UNCONNECTED[3:1],y_addr_out2_carry__8_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,y_addr_out3__2_n_86}),
.O({NLW_y_addr_out2_carry__8_O_UNCONNECTED[3:2],y_addr_out2[37:36]}),
.S({1'b0,1'b0,y_addr_out2_carry__8_i_1_n_0,y_addr_out2_carry__8_i_2_n_0}));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__8_i_1
(.I0(y_addr_out3__2_n_85),
.I1(y_addr_out3__0_n_85),
.O(y_addr_out2_carry__8_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry__8_i_2
(.I0(y_addr_out3__2_n_86),
.I1(y_addr_out3__0_n_86),
.O(y_addr_out2_carry__8_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_1
(.I0(y_addr_out3__1_n_102),
.I1(y_addr_out3_n_102),
.O(y_addr_out2_carry_i_1_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_2
(.I0(y_addr_out3__1_n_103),
.I1(y_addr_out3_n_103),
.O(y_addr_out2_carry_i_2_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_3
(.I0(y_addr_out3__1_n_104),
.I1(y_addr_out3_n_104),
.O(y_addr_out2_carry_i_3_n_0));
LUT2 #(
.INIT(4'h6))
y_addr_out2_carry_i_4
(.I0(y_addr_out3__1_n_105),
.I1(y_addr_out3_n_105),
.O(y_addr_out2_carry_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m11[15],rot_m11[15],rot_m11}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3_OVERFLOW_UNCONNECTED),
.P({y_addr_out3_n_58,y_addr_out3_n_59,y_addr_out3_n_60,y_addr_out3_n_61,y_addr_out3_n_62,y_addr_out3_n_63,y_addr_out3_n_64,y_addr_out3_n_65,y_addr_out3_n_66,y_addr_out3_n_67,y_addr_out3_n_68,y_addr_out3_n_69,y_addr_out3_n_70,y_addr_out3_n_71,y_addr_out3_n_72,y_addr_out3_n_73,y_addr_out3_n_74,y_addr_out3_n_75,y_addr_out3_n_76,y_addr_out3_n_77,y_addr_out3_n_78,y_addr_out3_n_79,y_addr_out3_n_80,y_addr_out3_n_81,y_addr_out3_n_82,y_addr_out3_n_83,y_addr_out3_n_84,y_addr_out3_n_85,y_addr_out3_n_86,y_addr_out3_n_87,y_addr_out3_n_88,y_addr_out3_n_89,y_addr_out3_n_90,y_addr_out3_n_91,y_addr_out3_n_92,y_addr_out3_n_93,y_addr_out3_n_94,y_addr_out3_n_95,y_addr_out3_n_96,y_addr_out3_n_97,y_addr_out3_n_98,y_addr_out3_n_99,y_addr_out3_n_100,y_addr_out3_n_101,y_addr_out3_n_102,y_addr_out3_n_103,y_addr_out3_n_104,y_addr_out3_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({y_addr_out3_n_106,y_addr_out3_n_107,y_addr_out3_n_108,y_addr_out3_n_109,y_addr_out3_n_110,y_addr_out3_n_111,y_addr_out3_n_112,y_addr_out3_n_113,y_addr_out3_n_114,y_addr_out3_n_115,y_addr_out3_n_116,y_addr_out3_n_117,y_addr_out3_n_118,y_addr_out3_n_119,y_addr_out3_n_120,y_addr_out3_n_121,y_addr_out3_n_122,y_addr_out3_n_123,y_addr_out3_n_124,y_addr_out3_n_125,y_addr_out3_n_126,y_addr_out3_n_127,y_addr_out3_n_128,y_addr_out3_n_129,y_addr_out3_n_130,y_addr_out3_n_131,y_addr_out3_n_132,y_addr_out3_n_133,y_addr_out3_n_134,y_addr_out3_n_135,y_addr_out3_n_136,y_addr_out3_n_137,y_addr_out3_n_138,y_addr_out3_n_139,y_addr_out3_n_140,y_addr_out3_n_141,y_addr_out3_n_142,y_addr_out3_n_143,y_addr_out3_n_144,y_addr_out3_n_145,y_addr_out3_n_146,y_addr_out3_n_147,y_addr_out3_n_148,y_addr_out3_n_149,y_addr_out3_n_150,y_addr_out3_n_151,y_addr_out3_n_152,y_addr_out3_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__0
(.A({rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11[15],rot_m11}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__0_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,y_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__0_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__0_n_58,y_addr_out3__0_n_59,y_addr_out3__0_n_60,y_addr_out3__0_n_61,y_addr_out3__0_n_62,y_addr_out3__0_n_63,y_addr_out3__0_n_64,y_addr_out3__0_n_65,y_addr_out3__0_n_66,y_addr_out3__0_n_67,y_addr_out3__0_n_68,y_addr_out3__0_n_69,y_addr_out3__0_n_70,y_addr_out3__0_n_71,y_addr_out3__0_n_72,y_addr_out3__0_n_73,y_addr_out3__0_n_74,y_addr_out3__0_n_75,y_addr_out3__0_n_76,y_addr_out3__0_n_77,y_addr_out3__0_n_78,y_addr_out3__0_n_79,y_addr_out3__0_n_80,y_addr_out3__0_n_81,y_addr_out3__0_n_82,y_addr_out3__0_n_83,y_addr_out3__0_n_84,y_addr_out3__0_n_85,y_addr_out3__0_n_86,y_addr_out3__0_n_87,y_addr_out3__0_n_88,y_addr_out3__0_n_89,y_addr_out3__0_n_90,y_addr_out3__0_n_91,y_addr_out3__0_n_92,y_addr_out3__0_n_93,y_addr_out3__0_n_94,y_addr_out3__0_n_95,y_addr_out3__0_n_96,y_addr_out3__0_n_97,y_addr_out3__0_n_98,y_addr_out3__0_n_99,y_addr_out3__0_n_100,y_addr_out3__0_n_101,y_addr_out3__0_n_102,y_addr_out3__0_n_103,y_addr_out3__0_n_104,y_addr_out3__0_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED),
.PCIN({y_addr_out3_n_106,y_addr_out3_n_107,y_addr_out3_n_108,y_addr_out3_n_109,y_addr_out3_n_110,y_addr_out3_n_111,y_addr_out3_n_112,y_addr_out3_n_113,y_addr_out3_n_114,y_addr_out3_n_115,y_addr_out3_n_116,y_addr_out3_n_117,y_addr_out3_n_118,y_addr_out3_n_119,y_addr_out3_n_120,y_addr_out3_n_121,y_addr_out3_n_122,y_addr_out3_n_123,y_addr_out3_n_124,y_addr_out3_n_125,y_addr_out3_n_126,y_addr_out3_n_127,y_addr_out3_n_128,y_addr_out3_n_129,y_addr_out3_n_130,y_addr_out3_n_131,y_addr_out3_n_132,y_addr_out3_n_133,y_addr_out3_n_134,y_addr_out3_n_135,y_addr_out3_n_136,y_addr_out3_n_137,y_addr_out3_n_138,y_addr_out3_n_139,y_addr_out3_n_140,y_addr_out3_n_141,y_addr_out3_n_142,y_addr_out3_n_143,y_addr_out3_n_144,y_addr_out3_n_145,y_addr_out3_n_146,y_addr_out3_n_147,y_addr_out3_n_148,y_addr_out3_n_149,y_addr_out3_n_150,y_addr_out3_n_151,y_addr_out3_n_152,y_addr_out3_n_153}),
.PCOUT(NLW_y_addr_out3__0_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__1
(.A({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[2:0],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__1_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({rot_m10[15],rot_m10[15],rot_m10}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__1_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b0,1'b0,1'b0,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__1_n_58,y_addr_out3__1_n_59,y_addr_out3__1_n_60,y_addr_out3__1_n_61,y_addr_out3__1_n_62,y_addr_out3__1_n_63,y_addr_out3__1_n_64,y_addr_out3__1_n_65,y_addr_out3__1_n_66,y_addr_out3__1_n_67,y_addr_out3__1_n_68,y_addr_out3__1_n_69,y_addr_out3__1_n_70,y_addr_out3__1_n_71,y_addr_out3__1_n_72,y_addr_out3__1_n_73,y_addr_out3__1_n_74,y_addr_out3__1_n_75,y_addr_out3__1_n_76,y_addr_out3__1_n_77,y_addr_out3__1_n_78,y_addr_out3__1_n_79,y_addr_out3__1_n_80,y_addr_out3__1_n_81,y_addr_out3__1_n_82,y_addr_out3__1_n_83,y_addr_out3__1_n_84,y_addr_out3__1_n_85,y_addr_out3__1_n_86,y_addr_out3__1_n_87,y_addr_out3__1_n_88,y_addr_out3__1_n_89,y_addr_out3__1_n_90,y_addr_out3__1_n_91,y_addr_out3__1_n_92,y_addr_out3__1_n_93,y_addr_out3__1_n_94,y_addr_out3__1_n_95,y_addr_out3__1_n_96,y_addr_out3__1_n_97,y_addr_out3__1_n_98,y_addr_out3__1_n_99,y_addr_out3__1_n_100,y_addr_out3__1_n_101,y_addr_out3__1_n_102,y_addr_out3__1_n_103,y_addr_out3__1_n_104,y_addr_out3__1_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED),
.PCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.PCOUT({y_addr_out3__1_n_106,y_addr_out3__1_n_107,y_addr_out3__1_n_108,y_addr_out3__1_n_109,y_addr_out3__1_n_110,y_addr_out3__1_n_111,y_addr_out3__1_n_112,y_addr_out3__1_n_113,y_addr_out3__1_n_114,y_addr_out3__1_n_115,y_addr_out3__1_n_116,y_addr_out3__1_n_117,y_addr_out3__1_n_118,y_addr_out3__1_n_119,y_addr_out3__1_n_120,y_addr_out3__1_n_121,y_addr_out3__1_n_122,y_addr_out3__1_n_123,y_addr_out3__1_n_124,y_addr_out3__1_n_125,y_addr_out3__1_n_126,y_addr_out3__1_n_127,y_addr_out3__1_n_128,y_addr_out3__1_n_129,y_addr_out3__1_n_130,y_addr_out3__1_n_131,y_addr_out3__1_n_132,y_addr_out3__1_n_133,y_addr_out3__1_n_134,y_addr_out3__1_n_135,y_addr_out3__1_n_136,y_addr_out3__1_n_137,y_addr_out3__1_n_138,y_addr_out3__1_n_139,y_addr_out3__1_n_140,y_addr_out3__1_n_141,y_addr_out3__1_n_142,y_addr_out3__1_n_143,y_addr_out3__1_n_144,y_addr_out3__1_n_145,y_addr_out3__1_n_146,y_addr_out3__1_n_147,y_addr_out3__1_n_148,y_addr_out3__1_n_149,y_addr_out3__1_n_150,y_addr_out3__1_n_151,y_addr_out3__1_n_152,y_addr_out3__1_n_153}),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-13 {cell *THIS*}}" *)
DSP48E1 #(
.ACASCREG(0),
.ADREG(1),
.ALUMODEREG(0),
.AREG(0),
.AUTORESET_PATDET("NO_RESET"),
.A_INPUT("DIRECT"),
.BCASCREG(0),
.BREG(0),
.B_INPUT("DIRECT"),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(1),
.DREG(1),
.INMODEREG(0),
.MASK(48'h3FFFFFFFFFFF),
.MREG(0),
.OPMODEREG(0),
.PATTERN(48'h000000000000),
.PREG(0),
.SEL_MASK("MASK"),
.SEL_PATTERN("PATTERN"),
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_PATTERN_DETECT("NO_PATDET"),
.USE_SIMD("ONE48"))
y_addr_out3__2
(.A({rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10[15],rot_m10}),
.ACIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ACOUT(NLW_y_addr_out3__2_ACOUT_UNCONNECTED[29:0]),
.ALUMODE({1'b0,1'b0,1'b0,1'b0}),
.B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,x_addr_in[9:3]}),
.BCIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.BCOUT(NLW_y_addr_out3__2_BCOUT_UNCONNECTED[17:0]),
.C({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CARRYCASCIN(1'b0),
.CARRYCASCOUT(NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED),
.CARRYIN(1'b0),
.CARRYINSEL({1'b0,1'b0,1'b0}),
.CARRYOUT(NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED[3:0]),
.CEA1(1'b0),
.CEA2(1'b0),
.CEAD(1'b0),
.CEALUMODE(1'b0),
.CEB1(1'b0),
.CEB2(1'b0),
.CEC(1'b0),
.CECARRYIN(1'b0),
.CECTRL(1'b0),
.CED(1'b0),
.CEINMODE(1'b0),
.CEM(1'b0),
.CEP(1'b0),
.CLK(1'b0),
.D({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.INMODE({1'b0,1'b0,1'b0,1'b0,1'b0}),
.MULTSIGNIN(1'b0),
.MULTSIGNOUT(NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED),
.OPMODE({1'b1,1'b0,1'b1,1'b0,1'b1,1'b0,1'b1}),
.OVERFLOW(NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED),
.P({y_addr_out3__2_n_58,y_addr_out3__2_n_59,y_addr_out3__2_n_60,y_addr_out3__2_n_61,y_addr_out3__2_n_62,y_addr_out3__2_n_63,y_addr_out3__2_n_64,y_addr_out3__2_n_65,y_addr_out3__2_n_66,y_addr_out3__2_n_67,y_addr_out3__2_n_68,y_addr_out3__2_n_69,y_addr_out3__2_n_70,y_addr_out3__2_n_71,y_addr_out3__2_n_72,y_addr_out3__2_n_73,y_addr_out3__2_n_74,y_addr_out3__2_n_75,y_addr_out3__2_n_76,y_addr_out3__2_n_77,y_addr_out3__2_n_78,y_addr_out3__2_n_79,y_addr_out3__2_n_80,y_addr_out3__2_n_81,y_addr_out3__2_n_82,y_addr_out3__2_n_83,y_addr_out3__2_n_84,y_addr_out3__2_n_85,y_addr_out3__2_n_86,y_addr_out3__2_n_87,y_addr_out3__2_n_88,y_addr_out3__2_n_89,y_addr_out3__2_n_90,y_addr_out3__2_n_91,y_addr_out3__2_n_92,y_addr_out3__2_n_93,y_addr_out3__2_n_94,y_addr_out3__2_n_95,y_addr_out3__2_n_96,y_addr_out3__2_n_97,y_addr_out3__2_n_98,y_addr_out3__2_n_99,y_addr_out3__2_n_100,y_addr_out3__2_n_101,y_addr_out3__2_n_102,y_addr_out3__2_n_103,y_addr_out3__2_n_104,y_addr_out3__2_n_105}),
.PATTERNBDETECT(NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED),
.PATTERNDETECT(NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED),
.PCIN({y_addr_out3__1_n_106,y_addr_out3__1_n_107,y_addr_out3__1_n_108,y_addr_out3__1_n_109,y_addr_out3__1_n_110,y_addr_out3__1_n_111,y_addr_out3__1_n_112,y_addr_out3__1_n_113,y_addr_out3__1_n_114,y_addr_out3__1_n_115,y_addr_out3__1_n_116,y_addr_out3__1_n_117,y_addr_out3__1_n_118,y_addr_out3__1_n_119,y_addr_out3__1_n_120,y_addr_out3__1_n_121,y_addr_out3__1_n_122,y_addr_out3__1_n_123,y_addr_out3__1_n_124,y_addr_out3__1_n_125,y_addr_out3__1_n_126,y_addr_out3__1_n_127,y_addr_out3__1_n_128,y_addr_out3__1_n_129,y_addr_out3__1_n_130,y_addr_out3__1_n_131,y_addr_out3__1_n_132,y_addr_out3__1_n_133,y_addr_out3__1_n_134,y_addr_out3__1_n_135,y_addr_out3__1_n_136,y_addr_out3__1_n_137,y_addr_out3__1_n_138,y_addr_out3__1_n_139,y_addr_out3__1_n_140,y_addr_out3__1_n_141,y_addr_out3__1_n_142,y_addr_out3__1_n_143,y_addr_out3__1_n_144,y_addr_out3__1_n_145,y_addr_out3__1_n_146,y_addr_out3__1_n_147,y_addr_out3__1_n_148,y_addr_out3__1_n_149,y_addr_out3__1_n_150,y_addr_out3__1_n_151,y_addr_out3__1_n_152,y_addr_out3__1_n_153}),
.PCOUT(NLW_y_addr_out3__2_PCOUT_UNCONNECTED[47:0]),
.RSTA(1'b0),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTCTRL(1'b0),
.RSTD(1'b0),
.RSTINMODE(1'b0),
.RSTM(1'b0),
.RSTP(1'b0),
.UNDERFLOW(NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED));
LUT2 #(
.INIT(4'h6))
\y_addr_out[0]_i_1
(.I0(y_addr_out2[28]),
.I1(t_y[0]),
.O(p_0_in[0]));
FDRE \y_addr_out_reg[0]
(.C(clk),
.CE(enable),
.D(p_0_in[0]),
.Q(y_addr_out[0]),
.R(1'b0));
FDRE \y_addr_out_reg[1]
(.C(clk),
.CE(enable),
.D(p_0_in[1]),
.Q(y_addr_out[1]),
.R(1'b0));
FDRE \y_addr_out_reg[2]
(.C(clk),
.CE(enable),
.D(p_0_in[2]),
.Q(y_addr_out[2]),
.R(1'b0));
FDRE \y_addr_out_reg[3]
(.C(clk),
.CE(enable),
.D(p_0_in[3]),
.Q(y_addr_out[3]),
.R(1'b0));
FDRE \y_addr_out_reg[4]
(.C(clk),
.CE(enable),
.D(p_0_in[4]),
.Q(y_addr_out[4]),
.R(1'b0));
FDRE \y_addr_out_reg[5]
(.C(clk),
.CE(enable),
.D(p_0_in[5]),
.Q(y_addr_out[5]),
.R(1'b0));
FDRE \y_addr_out_reg[6]
(.C(clk),
.CE(enable),
.D(p_0_in[6]),
.Q(y_addr_out[6]),
.R(1'b0));
FDRE \y_addr_out_reg[7]
(.C(clk),
.CE(enable),
.D(p_0_in[7]),
.Q(y_addr_out[7]),
.R(1'b0));
FDRE \y_addr_out_reg[8]
(.C(clk),
.CE(enable),
.D(p_0_in[8]),
.Q(y_addr_out[8]),
.R(1'b0));
FDRE \y_addr_out_reg[9]
(.C(clk),
.CE(enable),
.D(p_0_in[9]),
.Q(y_addr_out[9]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`ifndef _control
`define _control
`define BRANCH_BEQ 0
`define BRANCH_BNE 1
module control(
input wire [5:0] opcode,
output wire regdst, memread, memtoreg,
output wire [1:0] branch,
output wire [1:0] aluop,
output wire memwrite, alusrc, regwrite);
reg oc_lw, oc_addi, oc_beq, oc_sw, oc_bne, oc_add;
always @(*) begin
oc_lw <= 1'b0;
oc_addi <= 1'b0;
oc_beq <= 1'b0;
oc_sw <= 1'b0;
oc_bne <= 1'b0;
oc_add <= 1'b0;
case (opcode)
6'b100011: oc_lw <= 1'b1; /* lw */
6'b001000: oc_addi <= 1'b1; /* addi */
6'b000100: oc_beq <= 1'b1; /* beq */
6'b101011: oc_sw <= 1'b1; /* sw */
6'b000101: oc_bne <= 1'b1; /* bne */
6'b000000: oc_add <= 1'b1; /* add */
endcase
end
assign regdst = ~(oc_lw | oc_addi);
assign branch[`BRANCH_BEQ] = oc_beq;
assign branch[`BRANCH_BNE] = oc_bne;
assign memread = oc_lw;
assign memtoreg = oc_lw;
assign aluop[0] = oc_beq | oc_bne;
assign aluop[1] = ~(oc_lw | oc_addi | oc_beq | oc_sw | oc_bne);
assign memwrite = oc_sw;
assign alusrc = oc_lw | oc_addi | oc_sw;
assign regwrite = ~(oc_beq | oc_sw | oc_bne);
endmodule
`endif
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
`define M 593 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 1187
module test_tiny;
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg [`WIDTH_D0:0] data;
// Outputs
wire [`WIDTH_D0:0] out;
wire done;
// Instantiate the Unit Under Test (UUT)
tiny uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.data(data),
.out(out),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1; // keep FSM silent
// init x, y
write(3, 1186'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
write(5, 1186'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
write(6, 1186'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
write(7, 1186'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
/* read back. uncomment me if error happens */
/* read(3);
$display("xp = %h", out);
read(5);
$display("yp = %h", out);
read(6);
$display("xq = %h", out);
read(7);
$display("yq = %h", out);*/
reset = 0;
sel = 0; w = 0;
@(posedge done);
@(negedge clk);
read(9);
check(1186'h20115a6958895a08585a412698a58250900a651a859448a4848125164545598a426119a09885802424154a08855a0042a168516099228606222540582026aa0a6029a88805a1888628856a2a64504120aa290491925284508921140a24a0a8641548a521512698985a610861a401208644612a4a52625119000006004518844899810191a056aaa680889958996508954685a0920);
read(10);
check(1186'h228a9556506501a0258028a8856851a5466a205a2544849a12a10a018a40aaa461959859a4408245094969a44565a160a98229805169491120568121008a04918050a9022854868440662591221116889a9668a82aa84182a59025424469164015a56698a95989555601618402286696055608a82508125aaa5882000aaa96114998660a684582889a5a5190058a0411426145250);
read(11);
check(1186'h001224a468a9154205488585aaa9a0a9882056194952001a88424522191052a96a21102915181a845a5509844985196696160900a0515956a2a10a100a12566408a14450049a586951896442400a8620148582958a8a51869990a161412406860012a61a66214a4461a86895640a48284528201852615921952aaaaa40802586168a929582128a985929990826a9110186891489a);
read(12);
check(1186'h019618a9624a522a280a06a0654418906998059625a892054996a0560a941a842589189984190884426125114000aa60a0a568285221026662226a626a8600605095054405486561a95059449282969a5a10819101a620902609052a1294182962a020512196945a2aa42598a41842096596551544969262a12a86685214a952494a956166a199682a649249a990088296422051a);
read(13);
check(1186'h1a6999a0105054aaa2145298116480601695482119a0619155a4414a8a82840918a512a5680a8000889a4905016868480211289860a8a5699a250245161a042846096a9866025094a189860a9829465281646040866a26959a61a18621848689101a9a95685016a9581224968461a0a108958a91205a0220a18865105928298299a642a906900289a95095845649aa41591069866);
read(14);
check(1186'h15a4208a19a0405005900212505098a881a49445242619a12a12491844110169529a422046a684668819599891a411954196961160591865590a699a04908a6196928965a1686a664210420908115a5816919169662656a855099464680902514586265602510840a566a94a506961a615420a908aa91959610a1a0899589600902a10962460a664104126056a82551462459169a);
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task write;
input [6:0] adr;
input [`WIDTH_D0:0] dat;
begin
sel = 1;
w = 1;
addr = adr;
data = dat;
#(`P);
end
endtask
task read;
input [6:0] adr;
begin
sel = 1;
w = 0;
addr = adr;
#(`P);
end
endtask
task check;
input [`WIDTH_D0:0] wish;
begin
if (out !== wish)
begin $display("Error! %h %h", out, wish); end
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR2B_PP_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND3B_BEHAVIORAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and3b (
VPWR,
VGND,
X ,
A_N ,
B ,
C
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_BEHAVIORAL_PP_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_SHARED_CODE
integer i = 0;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (start_event == 1'b1) begin
i <= num_cks;
end
else if (i > 1) begin
i <= i - 1;
end
end
else begin
i <= 0;
end
end
`endif // OVL_SHARED_CODE
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_next_assert #(
.num_cks(num_cks),
.check_overlapping(check_overlapping),
.check_missing_start(check_missing_start))
assert_next_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.no_overlapping(i <= 0),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_next_assume #(
.num_cks(num_cks),
.check_overlapping(check_overlapping),
.check_missing_start(check_missing_start))
assert_next_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.no_overlapping(i <= 0),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_next_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON),
.OVL_COVER_CORNER_ON(OVL_COVER_CORNER_ON))
assert_next_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.no_overlapping(i <= 0));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_next.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_next_assert (clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable);
parameter num_cks = 1;
parameter check_overlapping = 1;
parameter check_missing_start = 1;
input clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_next_assume (clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable);
parameter num_cks = 1;
parameter check_overlapping = 1;
parameter check_missing_start = 1;
input clk, reset_n, test_expr, start_event, no_overlapping, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_next_cover (clk, reset_n, test_expr, start_event, no_overlapping);
parameter OVL_COVER_BASIC_ON = 1;
parameter OVL_COVER_CORNER_ON = 1;
input clk, reset_n, test_expr, start_event, no_overlapping;
endmodule
|
// pr_region_default_onchip_memory2_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module pr_region_default_onchip_memory2_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [6:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [31:0] readdata, // .readdata
input wire [31:0] writedata, // .writedata
input wire [3:0] byteenable // .byteenable
);
pr_region_default_onchip_memory2_0_altera_avalon_onchip_memory2_171_z7z2goy onchip_memory2_0 (
.clk (clk), // input, width = 1, clk1.clk
.address (address), // input, width = 7, s1.address
.clken (clken), // input, width = 1, .clken
.chipselect (chipselect), // input, width = 1, .chipselect
.write (write), // input, width = 1, .write
.readdata (readdata), // output, width = 32, .readdata
.writedata (writedata), // input, width = 32, .writedata
.byteenable (byteenable), // input, width = 4, .byteenable
.reset (reset), // input, width = 1, reset1.reset
.reset_req (reset_req), // input, width = 1, .reset_req
.freeze (1'b0) // (terminated),
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpll1.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpll1 (
areset,
clkswitch,
inclk0,
inclk1,
activeclock,
c0,
c1,
c2,
c3,
locked);
input areset;
input clkswitch;
input inclk0;
input inclk1;
output activeclock;
output c0;
output c1;
output c2;
output c3;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 clkswitch;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [4:0] sub_wire1;
wire sub_wire6;
wire sub_wire9 = inclk1;
wire activeclock = sub_wire0;
wire [3:3] sub_wire5 = sub_wire1[3:3];
wire [2:2] sub_wire4 = sub_wire1[2:2];
wire [0:0] sub_wire3 = sub_wire1[0:0];
wire [1:1] sub_wire2 = sub_wire1[1:1];
wire c1 = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire c3 = sub_wire5;
wire locked = sub_wire6;
wire sub_wire7 = inclk0;
wire [1:0] sub_wire8 = {sub_wire9, sub_wire7};
altpll altpll_component (
.areset (areset),
.clkswitch (clkswitch),
.inclk (sub_wire8),
.activeclock (sub_wire0),
.clk (sub_wire1),
.locked (sub_wire6),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "HIGH",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "12500",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 10,
altpll_component.clk1_phase_shift = "313",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 10,
altpll_component.clk2_phase_shift = "625",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 10,
altpll_component.clk3_phase_shift = "938",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 25000,
altpll_component.inclk1_input_frequency = 25000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=altpll1",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_USED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_USED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_USED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.primary_clock = "inclk0",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.switch_over_type = "MANUAL",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "1"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "400.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "400.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "400.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "40.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "40.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "10"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "10"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "10"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "400.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "400.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "400.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "400.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "12.50000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "45.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "135.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "12500"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "313"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "625"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "938"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "25000"
// Retrieval info: CONSTANT: INCLK1_INPUT_FREQUENCY NUMERIC "25000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PRIMARY_CLOCK STRING "inclk0"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: SWITCH_OVER_TYPE STRING "MANUAL"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: activeclock 0 0 0 0 OUTPUT GND "activeclock"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: clkswitch 0 0 0 0 INPUT GND "clkswitch"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: inclk1 0 0 0 0 INPUT_CLK_EXT GND "inclk1"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @clkswitch 0 0 0 0 clkswitch 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 inclk1 0 0 0 0
// Retrieval info: CONNECT: activeclock 0 0 0 0 @activeclock 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`ifndef _inc_fifo_
`define _inc_fifo_
module fifo2 (clk, reset, full, empty, item_in, item_out, write, read);
parameter SIZE = 2;
parameter DEPTH_LOG2 = 1;
localparam DEPTH = 2 ** DEPTH_LOG2;
input clk, reset, write, read;
input [SIZE-1:0] item_in;
output [SIZE-1:0] item_out;
output full, empty;
reg full, empty;
reg [SIZE-1:0] memory [DEPTH-1:0];
reg [DEPTH_LOG2-1:0] read_ptr;
reg [DEPTH_LOG2-1:0] write_ptr;
wire [DEPTH_LOG2-1:0] read_ptr_p1 = read_ptr + 1;
wire [DEPTH_LOG2-1:0] write_ptr_p1 = write_ptr + 1;
assign item_out = memory[read_ptr];
integer i;
wire do_read = read & !empty;
wire do_write = write & !full;
always @(posedge clk or posedge reset) begin
if (reset) begin
read_ptr <= 0;
write_ptr <= 0;
empty <= 1;
full <= 0;
for (i=0; i<DEPTH; i=i+1) memory[i] <= 0;
end else begin
if (do_read & do_write) begin
read_ptr <= read_ptr_p1;
write_ptr <= write_ptr_p1;
memory[write_ptr] <= item_in;
end else if (do_read) begin
full <= 0;
read_ptr <= read_ptr_p1;
empty <= (read_ptr_p1 == write_ptr);
end else if (do_write) begin
memory[write_ptr] <= item_in;
empty <= 0;
write_ptr <= write_ptr_p1;
full <= (read_ptr == write_ptr_p1);
end
end
end
endmodule
`endif
|
module membus_2_connect(
// unused
input wire clk,
input wire reset,
// Master
input wire m_wr_rs,
input wire m_rq_cyc,
input wire m_rd_rq,
input wire m_wr_rq,
input wire [21:35] m_ma,
input wire [18:21] m_sel,
input wire m_fmc_select,
input wire [0:35] m_mb_write,
output wire m_addr_ack,
output wire m_rd_rs,
output wire [0:35] m_mb_read,
// Slave 0
output wire s0_wr_rs,
output wire s0_rq_cyc,
output wire s0_rd_rq,
output wire s0_wr_rq,
output wire [21:35] s0_ma,
output wire [18:21] s0_sel,
output wire s0_fmc_select,
output wire [0:35] s0_mb_write,
input wire s0_addr_ack,
input wire s0_rd_rs,
input wire [0:35] s0_mb_read,
// Slave 1
output wire s1_wr_rs,
output wire s1_rq_cyc,
output wire s1_rd_rq,
output wire s1_wr_rq,
output wire [21:35] s1_ma,
output wire [18:21] s1_sel,
output wire s1_fmc_select,
output wire [0:35] s1_mb_write,
input wire s1_addr_ack,
input wire s1_rd_rs,
input wire [0:35] s1_mb_read
);
wire [0:35] mb_out = m_mb_write | s0_mb_read | s1_mb_read;
assign m_addr_ack = s0_addr_ack | s1_addr_ack;
assign m_rd_rs = s0_rd_rs | s1_rd_rs;
assign m_mb_read = mb_out;
assign s0_wr_rs = m_wr_rs;
assign s0_rq_cyc = m_rq_cyc;
assign s0_rd_rq = m_rd_rq;
assign s0_wr_rq = m_wr_rq;
assign s0_ma = m_ma;
assign s0_sel = m_sel;
assign s0_fmc_select = m_fmc_select;
assign s0_mb_write = mb_out;
assign s1_wr_rs = m_wr_rs;
assign s1_rq_cyc = m_rq_cyc;
assign s1_rd_rq = m_rd_rq;
assign s1_wr_rq = m_wr_rq;
assign s1_ma = m_ma;
assign s1_sel = m_sel;
assign s1_fmc_select = m_fmc_select;
assign s1_mb_write = mb_out;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/06/2017 08:43:21 AM
// Design Name:
// Module Name: MULTIPLEXER_2_TO_1
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MULTIPLEXER_2_TO_1 #(
parameter BUS_WIDTH = 32
) (
input [BUS_WIDTH - 1 : 0] IN1 ,
input [BUS_WIDTH - 1 : 0] IN2 ,
input SELECT ,
output [BUS_WIDTH - 1 : 0] OUT
);
reg [BUS_WIDTH - 1 : 0] out_reg;
always@(*)
begin
case(SELECT)
1'b0:
begin
out_reg = IN1;
end
1'b1:
begin
out_reg = IN2;
end
endcase
end
assign OUT = out_reg;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A22O_FUNCTIONAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a22o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_FUNCTIONAL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0.v
// Version : 1.11
//
// Description: 7-series solution wrapper : Endpoint for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_11_0 # (
parameter CFG_VEND_ID = 16'h10EE,
parameter CFG_DEV_ID = 16'h7011,
parameter CFG_REV_ID = 8'h00,
parameter CFG_SUBSYS_VEND_ID = 16'h10EE,
parameter CFG_SUBSYS_ID = 16'h0007,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter PIPE_PIPELINE_STAGES = 0,
parameter [11:0] AER_BASE_PTR = 12'h000,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h000,
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_ON = "FALSE",
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "FALSE",
parameter [31:0] BAR0 = 32'hFFFE0000,
parameter [31:0] BAR1 = 32'h00000000,
parameter [31:0] BAR2 = 32'h00000000,
parameter [31:0] BAR3 = 32'h00000000,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 64,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h058000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'b00,
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_LANE_REVERSAL = "TRUE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h000,
parameter DSN_CAP_ON = "TRUE",
parameter [10:0] ENABLE_MSG_ROUTE = 11'b00000000000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter [31:0] EXPANSION_ROM = 32'h00000000,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [7:0] INTERRUPT_PIN = 8'h1,
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h01,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 1,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01,
parameter MSI_CAP_MULTIMSGCAP = 0,
parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter MSI_CAP_ON = "TRUE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter MSIX_CAP_ON = "FALSE",
parameter MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h0,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h0,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00,
parameter PM_CAP_DSI = "FALSE",
parameter PM_CAP_D1SUPPORT = "FALSE",
parameter PM_CAP_D2SUPPORT = "FALSE",
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [1:0] PM_DATA_SCALE0 = 2'h0,
parameter [1:0] PM_DATA_SCALE1 = 2'h0,
parameter [1:0] PM_DATA_SCALE2 = 2'h0,
parameter [1:0] PM_DATA_SCALE3 = 2'h0,
parameter [1:0] PM_DATA_SCALE4 = 2'h0,
parameter [1:0] PM_DATA_SCALE5 = 2'h0,
parameter [1:0] PM_DATA_SCALE6 = 2'h0,
parameter [1:0] PM_DATA_SCALE7 = 2'h0,
parameter [7:0] PM_DATA0 = 8'h00,
parameter [7:0] PM_DATA1 = 8'h00,
parameter [7:0] PM_DATA2 = 8'h00,
parameter [7:0] PM_DATA3 = 8'h00,
parameter [7:0] PM_DATA4 = 8'h00,
parameter [7:0] PM_DATA5 = 8'h00,
parameter [7:0] PM_DATA6 = 8'h00,
parameter [7:0] PM_DATA7 = 8'h00,
parameter [11:0] RBAR_BASE_PTR = 12'h000,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00001,
parameter [2:0] RBAR_NUM = 3'h0,
parameter RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter TL_RX_RAM_RADDR_LATENCY = 0,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TX_RAM_RADDR_LATENCY = 0,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_NP_FC = "TRUE",
parameter TRN_DW = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "FALSE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK_FREQ = 1,
parameter USER_CLK2_DIV2 = "FALSE",
parameter [11:0] VC_BASE_PTR = 12'h000,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h7FF,
parameter VC0_TOTAL_CREDITS_CD = 850,
parameter VC0_TOTAL_CREDITS_CH = 72,
parameter VC0_TOTAL_CREDITS_NPH = 4,
parameter VC0_TOTAL_CREDITS_NPD = 8,
parameter VC0_TOTAL_CREDITS_PD = 64,
parameter VC0_TOTAL_CREDITS_PH = 4,
parameter VC0_TX_LASTPACKET = 29,
parameter [11:0] VSEC_BASE_PTR = 12'h000,
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter [4:0] INFER_EI = 5'h00,
parameter IS_SWITCH = "FALSE",
parameter LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_RSVD_23 = 0,
parameter LINK_CONTROL_RCB = 0,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR =8'h00,
parameter N_FTS_COMCLK_GEN1 = 255,
parameter N_FTS_COMCLK_GEN2 = 255,
parameter N_FTS_GEN1 = 255,
parameter N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter PCIE_CAP_ON = "TRUE",
parameter PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter PCIE_REVISION = 2,
parameter PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter PCIE_EXT_CLK = "TRUE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter PM_CAP_AUXCURRENT = 0,
parameter [7:0] PM_CAP_ID = 8'h01,
parameter PM_CAP_ON = "TRUE",
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_RSVD_04 = 0,
parameter PM_CAP_VERSION = 3,
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_B2B3 = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter SELECT_DLL_IF = "FALSE",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter TL_RBYPASS = "FALSE",
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter DEV_CAP_RSVD_14_12 = 0,
parameter DEV_CAP_RSVD_17_16 = 0,
parameter DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1,
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter MPS_FORCE = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter PM_MF = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SIM_VERSION = "1.0",
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter UR_CFG1 = "TRUE",
parameter USE_RID_PINS = "FALSE",
// New Parameters
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter PCIE_USE_MODE = "3.0",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_CHAN_BOND = 1,
parameter PCIE_PLL_SEL = "CPLL",
parameter PCIE_ASYNC_EN = "FALSE",
parameter PCIE_TXBUF_EN = "FALSE"
)
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock Inputs //
//----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input PIPE_RXUSRCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output reg user_reset_out,
output user_lnk_up,
// Tx
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
output s_axis_tx_tready,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
input tx_cfg_gnt,
// Rx
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output wire cfg_pmcsr_pme_en,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_status,
output wire cfg_received_func_lvl_rst,
// Management Interface
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_en,
input wire cfg_mgmt_rd_en,
input wire cfg_mgmt_wr_readonly,
// Error Reporting Interface
input wire cfg_err_ecrc,
input wire cfg_err_ur,
input wire cfg_err_cpl_timeout,
input wire cfg_err_cpl_unexpect,
input wire cfg_err_cpl_abort,
input wire cfg_err_posted,
input wire cfg_err_cor,
input wire cfg_err_atomic_egress_blocked,
input wire cfg_err_internal_cor,
input wire cfg_err_malformed,
input wire cfg_err_mc_blocked,
input wire cfg_err_poisoned,
input wire cfg_err_norecovery,
input wire [47:0] cfg_err_tlp_cpl_header,
output wire cfg_err_cpl_rdy,
input wire cfg_err_locked,
input wire cfg_err_acs,
input wire cfg_err_internal_uncor,
input wire cfg_trn_pending,
input wire cfg_pm_halt_aspm_l0s,
input wire cfg_pm_halt_aspm_l1,
input wire cfg_pm_force_state_en,
input wire [1:0] cfg_pm_force_state,
input wire [63:0] cfg_dsn,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
// Interrupt Interface Signals
input wire cfg_interrupt,
output wire cfg_interrupt_rdy,
input wire cfg_interrupt_assert,
input wire [7:0] cfg_interrupt_di,
output wire [7:0] cfg_interrupt_do,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
input wire cfg_interrupt_stat,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input wire cfg_turnoff_ok,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
input wire cfg_pm_wake,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire cfg_pm_send_pme_to,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire cfg_mgmt_wr_rw1c_as_rw,
output cfg_msg_received,
output [15:0] cfg_msg_data,
output wire cfg_bridge_serr_en,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_setslotpowerlimit,
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output wire pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire pl_transmit_hot_rst,
input wire pl_downstream_deemph_source,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input wire [127:0] cfg_err_aer_headerlog,
input wire [4:0] cfg_aer_interrupt_msgnum,
output wire cfg_err_aer_headerlog_set,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output wire [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// 8. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
output wire [2:0] pipe_rx0_status_gt,
output wire pipe_rx0_phy_status_gt,
input [3:0] i_tx_diff_ctr,
output [15:0] o_rx_data,
output [1:0] o_rx_data_k,
output [1:0] o_rx_byte_is_comma,
output o_rx_byte_is_aligned,
input wire PIPE_MMCM_RST_N,
input wire sys_clk,
input wire sys_rst_n
);
localparam TCQ = 100;
wire user_clk;
wire user_clk2;
wire [15:0] cfg_vend_id = CFG_VEND_ID;
wire [15:0] cfg_dev_id = CFG_DEV_ID;
wire [7:0] cfg_rev_id = CFG_REV_ID;
wire [15:0] cfg_subsys_vend_id = CFG_SUBSYS_VEND_ID;
wire [15:0] cfg_subsys_id = CFG_SUBSYS_ID;
// PIPE Interface Wires
wire phy_rdy_n;
wire pipe_rx0_polarity_gt;
wire pipe_rx1_polarity_gt;
wire pipe_rx2_polarity_gt;
wire pipe_rx3_polarity_gt;
wire pipe_rx4_polarity_gt;
wire pipe_rx5_polarity_gt;
wire pipe_rx6_polarity_gt;
wire pipe_rx7_polarity_gt;
wire pipe_tx_deemph_gt;
wire [2:0] pipe_tx_margin_gt;
wire pipe_tx_rate_gt;
wire pipe_tx_rcvr_det_gt;
wire [1:0] pipe_tx0_char_is_k_gt;
wire pipe_tx0_compliance_gt;
wire [15:0] pipe_tx0_data_gt;
wire pipe_tx0_elec_idle_gt;
wire [1:0] pipe_tx0_powerdown_gt;
wire [1:0] pipe_tx1_char_is_k_gt;
wire pipe_tx1_compliance_gt;
wire [15:0] pipe_tx1_data_gt;
wire pipe_tx1_elec_idle_gt;
wire [1:0] pipe_tx1_powerdown_gt;
wire [1:0] pipe_tx2_char_is_k_gt;
wire pipe_tx2_compliance_gt;
wire [15:0] pipe_tx2_data_gt;
wire pipe_tx2_elec_idle_gt;
wire [1:0] pipe_tx2_powerdown_gt;
wire [1:0] pipe_tx3_char_is_k_gt;
wire pipe_tx3_compliance_gt;
wire [15:0] pipe_tx3_data_gt;
wire pipe_tx3_elec_idle_gt;
wire [1:0] pipe_tx3_powerdown_gt;
wire [1:0] pipe_tx4_char_is_k_gt;
wire pipe_tx4_compliance_gt;
wire [15:0] pipe_tx4_data_gt;
wire pipe_tx4_elec_idle_gt;
wire [1:0] pipe_tx4_powerdown_gt;
wire [1:0] pipe_tx5_char_is_k_gt;
wire pipe_tx5_compliance_gt;
wire [15:0] pipe_tx5_data_gt;
wire pipe_tx5_elec_idle_gt;
wire [1:0] pipe_tx5_powerdown_gt;
wire [1:0] pipe_tx6_char_is_k_gt;
wire pipe_tx6_compliance_gt;
wire [15:0] pipe_tx6_data_gt;
wire pipe_tx6_elec_idle_gt;
wire [1:0] pipe_tx6_powerdown_gt;
wire [1:0] pipe_tx7_char_is_k_gt;
wire pipe_tx7_compliance_gt;
wire [15:0] pipe_tx7_data_gt;
wire pipe_tx7_elec_idle_gt;
wire [1:0] pipe_tx7_powerdown_gt;
wire pipe_rx0_chanisaligned_gt;
wire [1:0] pipe_rx0_char_is_k_gt;
wire [15:0] pipe_rx0_data_gt;
wire pipe_rx0_elec_idle_gt;
// wire pipe_rx0_phy_status_gt;
// wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_valid_gt;
wire pipe_rx1_chanisaligned_gt;
wire [1:0] pipe_rx1_char_is_k_gt;
wire [15:0] pipe_rx1_data_gt;
wire pipe_rx1_elec_idle_gt;
wire pipe_rx1_phy_status_gt;
wire [2:0] pipe_rx1_status_gt;
wire pipe_rx1_valid_gt;
wire pipe_rx2_chanisaligned_gt;
wire [1:0] pipe_rx2_char_is_k_gt;
wire [15:0] pipe_rx2_data_gt;
wire pipe_rx2_elec_idle_gt;
wire pipe_rx2_phy_status_gt;
wire [2:0] pipe_rx2_status_gt;
wire pipe_rx2_valid_gt;
wire pipe_rx3_chanisaligned_gt;
wire [1:0] pipe_rx3_char_is_k_gt;
wire [15:0] pipe_rx3_data_gt;
wire pipe_rx3_elec_idle_gt;
wire pipe_rx3_phy_status_gt;
wire [2:0] pipe_rx3_status_gt;
wire pipe_rx3_valid_gt;
wire pipe_rx4_chanisaligned_gt;
wire [1:0] pipe_rx4_char_is_k_gt;
wire [15:0] pipe_rx4_data_gt;
wire pipe_rx4_elec_idle_gt;
wire pipe_rx4_phy_status_gt;
wire [2:0] pipe_rx4_status_gt;
wire pipe_rx4_valid_gt;
wire pipe_rx5_chanisaligned_gt;
wire [1:0] pipe_rx5_char_is_k_gt;
wire [15:0] pipe_rx5_data_gt;
wire pipe_rx5_elec_idle_gt;
wire pipe_rx5_phy_status_gt;
wire [2:0] pipe_rx5_status_gt;
wire pipe_rx5_valid_gt;
wire pipe_rx6_chanisaligned_gt;
wire [1:0] pipe_rx6_char_is_k_gt;
wire [15:0] pipe_rx6_data_gt;
wire pipe_rx6_elec_idle_gt;
wire pipe_rx6_phy_status_gt;
wire [2:0] pipe_rx6_status_gt;
wire pipe_rx6_valid_gt;
wire pipe_rx7_chanisaligned_gt;
wire [1:0] pipe_rx7_char_is_k_gt;
wire [15:0] pipe_rx7_data_gt;
wire pipe_rx7_elec_idle_gt;
wire pipe_rx7_phy_status_gt;
wire [2:0] pipe_rx7_status_gt;
wire pipe_rx7_valid_gt;
reg user_lnk_up_int;
reg user_reset_int;
reg bridge_reset_int;
reg bridge_reset_d;
wire user_rst_n;
reg pl_received_hot_rst_q;
wire pl_received_hot_rst_wire;
reg pl_phy_lnk_up_q;
wire pl_phy_lnk_up_wire;
wire sys_or_hot_rst;
wire trn_lnk_up;
wire [5:0] pl_ltssm_state_int;
wire user_app_rdy;
reg user_app_rdy_req = 1'b0;
reg sys_rst_n_int = 1'b1;
reg user_lnk_up_mux;
reg mmcm_lock_int;
assign user_lnk_up = user_lnk_up_mux;
assign pl_ltssm_state = pl_ltssm_state_int;
assign pl_phy_lnk_up = pl_phy_lnk_up_q;
assign pl_received_hot_rst = pl_received_hot_rst_q;
//--------------------------------------------------------------------------//
// Register stages to separate interface nets from the rest of the design, //
// as required for the Tandem flow. //
//--------------------------------------------------------------------------//
always @(posedge user_clk_out) begin
sys_rst_n_int <= #TCQ sys_rst_n;
end
always @ (posedge user_clk_out) begin
if (!sys_rst_n_int) begin
mmcm_lock_int <= #TCQ 1'd0;
end else begin
mmcm_lock_int <= #TCQ PIPE_MMCM_LOCK_IN;
end
end
// Register block outputs pl_received_hot_rst and phy_lnk_up to ease timing on block output
assign sys_or_hot_rst = !sys_rst_n_int || pl_received_hot_rst_q;
always @(posedge user_clk_out)
begin
if (!sys_rst_n_int) begin
pl_received_hot_rst_q <= #TCQ 1'b0;
pl_phy_lnk_up_q <= #TCQ 1'b0;
end else begin
pl_received_hot_rst_q <= #TCQ pl_received_hot_rst_wire;
pl_phy_lnk_up_q <= #TCQ pl_phy_lnk_up_wire;
end
end
// Generate user_lnk_up_mux
always @(posedge user_clk_out)
begin
if (!sys_rst_n_int) begin
user_lnk_up_mux <= #TCQ 1'b0;
end else begin
user_lnk_up_mux <= #TCQ user_lnk_up_int;
end
end
always @(posedge user_clk_out)
begin
if (!sys_rst_n_int) begin
user_lnk_up_int <= #TCQ 1'b0;
end else begin
user_lnk_up_int <= #TCQ trn_lnk_up;
end
end
//------------------------------------------------------------------------------------------------------------------//
// Generate user_reset_out //
// Once user reset output of PCIE and Phy Layer is active, de-assert reset //
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise //
//------------------------------------------------------------------------------------------------------------------//
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_out <= #TCQ 1'b1;
end else begin
user_reset_out <= #TCQ user_reset_int;
end
end
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
bridge_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
bridge_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
bridge_reset_d <= #TCQ 1'b1;
end else begin
bridge_reset_d <= #TCQ bridge_reset_int;
end
end
//------------------------------------------------------------------------------------------------------------------//
// **** PCI Express Core Wrapper **** //
// The PCI Express Core Wrapper includes the following: //
// 1) AXI Streaming Bridge //
// 2) PCIE 2_1 Hard Block //
// 3) PCIE PIPE Interface Pipeline //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_11_0_pcie_top # (
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS ( USE_RID_PINS ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
// I/O
) pcie_top_i (
// AXI Interface
.user_clk_out ( user_clk_out ),
.user_reset ( bridge_reset_d ),
.user_lnk_up ( user_lnk_up ),
.user_rst_n ( user_rst_n ),
.trn_lnk_up ( trn_lnk_up ),
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cm_rst_n ( 1'b1 ),
.func_lvl_rst_n ( 1'b1 ),
.lnk_clk_en ( ),
.cfg_dev_id ( cfg_dev_id ),
.cfg_vend_id ( cfg_vend_id ),
.cfg_rev_id ( cfg_rev_id ),
.cfg_subsys_id ( cfg_subsys_id ),
.cfg_subsys_vend_id ( cfg_subsys_vend_id ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_bridge_serr_en ( cfg_bridge_serr_en ),
.cfg_command_bus_master_enable ( ),
.cfg_command_interrupt_disable ( ),
.cfg_command_io_enable ( ),
.cfg_command_mem_enable ( ),
.cfg_command_serr_en ( ),
.cfg_dev_control_aux_power_en ( ),
.cfg_dev_control_corr_err_reporting_en ( ),
.cfg_dev_control_enable_ro ( ),
.cfg_dev_control_ext_tag_en ( ),
.cfg_dev_control_fatal_err_reporting_en ( ),
.cfg_dev_control_max_payload ( ),
.cfg_dev_control_max_read_req ( ),
.cfg_dev_control_non_fatal_reporting_en ( ),
.cfg_dev_control_no_snoop_en ( ),
.cfg_dev_control_phantom_en ( ),
.cfg_dev_control_ur_err_reporting_en ( ),
.cfg_dev_control2_cpl_timeout_dis ( ),
.cfg_dev_control2_cpl_timeout_val ( ),
.cfg_dev_control2_ari_forward_en ( ),
.cfg_dev_control2_atomic_requester_en ( ),
.cfg_dev_control2_atomic_egress_block ( ),
.cfg_dev_control2_ido_req_en ( ),
.cfg_dev_control2_ido_cpl_en ( ),
.cfg_dev_control2_ltr_en ( ),
.cfg_dev_control2_tlp_prefix_block ( ),
.cfg_dev_status_corr_err_detected ( ),
.cfg_dev_status_fatal_err_detected ( ),
.cfg_dev_status_non_fatal_err_detected ( ),
.cfg_dev_status_ur_detected ( ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_link_control_rcb ( ),
.cfg_link_control_aspm_control ( ),
.cfg_link_control_auto_bandwidth_int_en ( ),
.cfg_link_control_bandwidth_int_en ( ),
.cfg_link_control_clock_pm_en ( ),
.cfg_link_control_common_clock ( ),
.cfg_link_control_extended_sync ( ),
.cfg_link_control_hw_auto_width_dis ( ),
.cfg_link_control_link_disable ( ),
.cfg_link_control_retrain_link ( ),
.cfg_link_status_auto_bandwidth_status ( ),
.cfg_link_status_bandwidth_status ( ),
.cfg_link_status_current_speed ( ),
.cfg_link_status_dll_active ( ),
.cfg_link_status_link_training ( ),
.cfg_link_status_negotiated_width ( ),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a ),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b ),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c ),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d ),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a ),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b ),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c ),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d ),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor ),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal ),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal ),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak ),
.cfg_msg_received_pme_to ( ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack ),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme ),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit ),
.cfg_msg_received_unlock ( ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_pm_rcv_as_req_l1_n ( ),
.cfg_pm_rcv_enter_l1_n ( ),
.cfg_pm_rcv_enter_l23_n ( ),
.cfg_pm_rcv_req_ack_n ( ),
.cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ),
.cfg_slot_control_electromech_il_ctl_pulse ( cfg_slot_control_electromech_il_ctl_pulse ),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en ),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en ),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en ),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( cfg_aer_rooterr_non_fatal_err_reporting_en ),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en ),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received ),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received ),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( ),
.cfg_transaction_addr ( ),
.cfg_transaction_type ( ),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map ),
.cfg_mgmt_byte_en_n ( ~cfg_mgmt_byte_en ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( ~cfg_err_cor ),
.cfg_err_cpl_abort_n ( ~cfg_err_cpl_abort ),
.cfg_err_cpl_timeout_n ( ~cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect_n ( ~cfg_err_cpl_unexpect ),
.cfg_err_ecrc_n ( ~cfg_err_ecrc ),
.cfg_err_locked_n ( ~cfg_err_locked ),
.cfg_err_posted_n ( ~cfg_err_posted ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( ~cfg_err_ur ),
.cfg_err_malformed_n ( ~cfg_err_malformed ),
.cfg_err_poisoned_n ( ~cfg_err_poisoned ),
.cfg_err_atomic_egress_blocked_n ( ~cfg_err_atomic_egress_blocked ),
.cfg_err_mc_blocked_n ( ~cfg_err_mc_blocked ),
.cfg_err_internal_uncor_n ( ~cfg_err_internal_uncor ),
.cfg_err_internal_cor_n ( ~cfg_err_internal_cor ),
.cfg_err_norecovery_n ( ~cfg_err_norecovery ),
.cfg_interrupt_assert_n ( ~cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( ~cfg_interrupt ),
.cfg_interrupt_stat_n ( ~cfg_interrupt_stat ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_pm_send_pme_to_n ( 1'b1 ),
.cfg_pm_wake_n ( ~cfg_pm_wake ),
.cfg_pm_halt_aspm_l0s_n ( ~cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1_n ( ~cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en_n ( ~cfg_pm_force_state_en),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( 3'b0 ),
.cfg_force_common_clock_off ( 1'b0 ),
.cfg_force_extended_sync_on ( 1'b0 ),
.cfg_port_number ( 8'b0 ),
.cfg_mgmt_rd_en_n ( ~cfg_mgmt_rd_en ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( ~cfg_mgmt_wr_en ),
.cfg_mgmt_wr_readonly_n ( ~cfg_mgmt_wr_readonly ),
.cfg_mgmt_wr_rw1c_as_rw_n ( ~cfg_mgmt_wr_rw1c_as_rw ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state_int ),
.pl_phy_lnk_up ( pl_phy_lnk_up_wire ),
.pl_received_hot_rst ( pl_received_hot_rst_wire ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( 1'b0 ),
.pl_directed_ltssm_new ( 6'b0 ),
.pl_directed_ltssm_stall ( 1'b0 ),
.pl_directed_change_done ( pl_directed_change_done ),
.phy_rdy_n ( phy_rdy_n ),
.dbg_sclr_a ( ),
.dbg_sclr_b ( ),
.dbg_sclr_c ( ),
.dbg_sclr_d ( ),
.dbg_sclr_e ( ),
.dbg_sclr_f ( ),
.dbg_sclr_g ( ),
.dbg_sclr_h ( ),
.dbg_sclr_i ( ),
.dbg_sclr_j ( ),
.dbg_sclr_k ( ),
.dbg_vec_a ( ),
.dbg_vec_b ( ),
.dbg_vec_c ( ),
.pl_dbg_vec ( ),
.trn_rdllp_data ( ),
.trn_rdllp_src_rdy ( ),
.dbg_mode ( 2'b0 ),
.dbg_sub_mode ( 1'b0 ),
.pl_dbg_mode ( 3'b0 ),
.drp_clk ( 1'b0 ),
.drp_do ( ),
.drp_rdy ( ),
.drp_addr ( 9'b0 ),
.drp_en ( 1'b0 ),
.drp_di ( 16'b0 ),
.drp_we ( 1'b0 ),
// Pipe Interface
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity_gt ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity_gt ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity_gt ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity_gt ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity_gt ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity_gt ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity_gt ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity_gt ),
.pipe_tx_deemph_gt ( pipe_tx_deemph_gt ),
.pipe_tx_margin_gt ( pipe_tx_margin_gt ),
.pipe_tx_rate_gt ( pipe_tx_rate_gt ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det_gt ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance_gt ),
.pipe_tx0_data_gt ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown_gt ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance_gt ),
.pipe_tx1_data_gt ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown_gt ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance_gt ),
.pipe_tx2_data_gt ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown_gt ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance_gt ),
.pipe_tx3_data_gt ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown_gt ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance_gt ),
.pipe_tx4_data_gt ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown_gt ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance_gt ),
.pipe_tx5_data_gt ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown_gt ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance_gt ),
.pipe_tx6_data_gt ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown_gt ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance_gt ),
.pipe_tx7_data_gt ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown_gt ),
.pipe_rx0_chanisaligned_gt ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_gt ( pipe_rx0_data_gt ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status_gt ),
.pipe_rx0_status_gt ( pipe_rx0_status_gt ),
.pipe_rx0_valid_gt ( pipe_rx0_valid_gt ),
.pipe_rx1_chanisaligned_gt ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_gt ( pipe_rx1_data_gt ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status_gt ),
.pipe_rx1_status_gt ( pipe_rx1_status_gt ),
.pipe_rx1_valid_gt ( pipe_rx1_valid_gt ),
.pipe_rx2_chanisaligned_gt ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_gt ( pipe_rx2_data_gt ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status_gt ),
.pipe_rx2_status_gt ( pipe_rx2_status_gt ),
.pipe_rx2_valid_gt ( pipe_rx2_valid_gt ),
.pipe_rx3_chanisaligned_gt ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_gt ( pipe_rx3_data_gt ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status_gt ),
.pipe_rx3_status_gt ( pipe_rx3_status_gt ),
.pipe_rx3_valid_gt ( pipe_rx3_valid_gt ),
.pipe_rx4_chanisaligned_gt ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_gt ( pipe_rx4_data_gt ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status_gt ),
.pipe_rx4_status_gt ( pipe_rx4_status_gt ),
.pipe_rx4_valid_gt ( pipe_rx4_valid_gt ),
.pipe_rx5_chanisaligned_gt ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_gt ( pipe_rx5_data_gt ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status_gt ),
.pipe_rx5_status_gt ( pipe_rx5_status_gt ),
.pipe_rx5_valid_gt ( pipe_rx5_valid_gt ),
.pipe_rx6_chanisaligned_gt ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_gt ( pipe_rx6_data_gt ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status_gt ),
.pipe_rx6_status_gt ( pipe_rx6_status_gt ),
.pipe_rx6_valid_gt ( pipe_rx6_valid_gt ),
.pipe_rx7_chanisaligned_gt ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_gt ( pipe_rx7_data_gt ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status_gt ),
.pipe_rx7_status_gt ( pipe_rx7_status_gt ),
.pipe_rx7_valid_gt ( pipe_rx7_valid_gt )
);
//------------------------------------------------------------------------------------------------------------------//
// **** V7/K7/A7 GTX Wrapper **** //
// The 7-Series GTX Wrapper includes the following: //
// 1) Virtex-7 GTX //
// 2) Kintex-7 GTX //
// 3) Artix-7 GTP //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_11_0_gt_top #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE ),
.PCIE_GT_DEVICE ( PCIE_GT_DEVICE ),
.PCIE_PLL_SEL ( PCIE_PLL_SEL ),
.PCIE_ASYNC_EN ( PCIE_ASYNC_EN ),
.PCIE_TXBUF_EN ( PCIE_TXBUF_EN ),
.PCIE_CHAN_BOND ( PCIE_CHAN_BOND )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n_int ),
.PIPE_MMCM_RST_N ( PIPE_MMCM_RST_N ), // Async | Async
.pipe_clk ( pipe_clk ),
.i_tx_diff_ctr ( i_tx_diff_ctr ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
.o_rx_data ( o_rx_data ),
.o_rx_data_k ( o_rx_data_k ),
.o_rx_byte_is_comma ( o_rx_byte_is_comma ),
.o_rx_byte_is_aligned ( o_rx_byte_is_aligned ),
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( mmcm_lock_int ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT )
);
endmodule
|
/*
* Copyright 2013-2016 Colin Weltin-Wu ([email protected])
* UC San Diego Integrated Signal Processing Group
*
* Licensed under GNU General Public License 3.0 or later.
* Some rights reserved. See LICENSE.
*
* spi_regs.v
* State machine which handles reading and writing from the test registers.
* Currently, the test bus width is hardcoded as 37 bits wide, generalize
* later.
* Autogenerated code from the register .csv definition file.
*/
module spi_reg(
// Register read signals
// INSERT_RD
// Register write signals
// INSERT_WR
// Inouts
vio_data_regs, io_success, vio_tbus,
// Inputs
i_rstb, i_clk_ext_osc, i_spi_active, vi_data_rx, i_rx_valid,
vi_byte_num);
// This global variable defines the number of registers
// INSERT_NUM_REG
// Global reset
input i_rstb;
// State machine clock
input i_clk_ext_osc;
// SPI interface
input i_spi_active;
input [7:0] vi_data_rx;
input i_rx_valid;
input [2:0] vi_byte_num;
inout [7:0] vio_data_regs;
// Test bus
inout io_success;
inout [36:0] vio_tbus;
// Register read and write controls
// INSERT_RD_DECLARATION
// INSERT_WR_DECLARATION
/*
* These vectors define the data mask for the test bus reads
*/
reg [7:0] rv_addr;
reg [36:0] rv_rd_mask;
always @( * ) begin
case ( rv_addr )
// INSERT_MASK
default : rv_rd_mask = {NUM_REGS{1'b0}};
endcase // case ( rv_addr )
end
/*
* These vectors define the number of bytes transmitted for the
* corresponding register. In the MSB register, unused bits are 0
* due to the data coming in the test bus being masked off.
*/
reg [NUM_REGS-1:0] rv_num_rd_bytes;
always @( * ) begin
case ( rv_addr )
// INSERT_NUM_BYTES
default : rv_num_rd_bytes = 0;
endcase // case ( rv_addr )
end
/*
* This register groups all the _rd wires into a single bus, such that
* rv_rd_bus[n] corresponds to the _rd wire associated with the register
* at address n.
*/
reg [NUM_REGS-1:0] rv_rd_tbus;
// INSERT_RD_BUS
/*
* This does the same for the _wr wires
*/
reg [NUM_REGS-1:0] rv_wr_tbus;
// INSERT_WR_BUS
/*
* Local reset
*/
wire active = i_rstb && i_spi_active;
/*
* This state machine simply captures the opcode on the arrival
* of the first (0th) byte, and enables the oscillator
*/
reg r_read_tbus;
reg r_write_tbus;
reg r_clamp_success;
always @( posedge i_rx_valid or negedge active ) begin : opcode_fsm
if ( !active ) begin
r_read_tbus <= 0;
r_write_tbus <= 0;
r_clamp_success <= 1;
end else begin
if ( 0 == vi_byte_num ) begin
if ( 128 == vi_data_rx ) begin
r_write_tbus <= 1;
r_clamp_success <= 0;
end
if ( 192 == vi_data_rx ) begin
r_read_tbus <= 1;
r_clamp_success <= 0;
end
end
end
end // block: opcode_fsm
assign io_success = r_clamp_success ? 1'b0 : 1'bz;
/*
* This state machine captures the address arriving on byte 1 regardless
* of whether the register interface is active or not.
*/
always @( posedge i_rx_valid or negedge active ) begin : address_fsm
if ( !active ) begin
rv_addr <= 0;
end else begin
if ( 1 == vi_byte_num )
rv_addr <= vi_data_rx;
end
end
/*
* This state machine handles register reads. When the address is loaded,
* ena_reg_read triggers the state machine clocked by the internal oscillator
* The data which is read from the test bus is then serialized out one
* byte at a time, from the LSB chunk to the MSB chunk.
* The shadow byte is initialized to an invalid value (7) which makes
* the output mux drive a 0.
*/
reg [2:0] rv_shadow_byte;
reg [7:0] rv_reg2spi;
reg r_ena_reg_read;
always @( posedge i_rx_valid or negedge active ) begin : read_fsm
if ( !active ) begin
rv_shadow_byte <= 7;
r_ena_reg_read <= 0;
end else begin
if (( 1 == vi_byte_num ) && r_read_tbus )
r_ena_reg_read <= 1;
if ( rv_num_rd_bytes >= vi_byte_num )
rv_shadow_byte <= vi_byte_num - 1;
else
rv_shadow_byte <= 7;
end
end
// The byte of the shadow register is addressed by the byte number
reg [36:0] rv_read_shadow;
always @( * ) begin
case ( rv_shadow_byte )
0 : rv_reg2spi = rv_read_shadow[7:0];
1 : rv_reg2spi = rv_read_shadow[15:8];
2 : rv_reg2spi = rv_read_shadow[23:16];
3 : rv_reg2spi = rv_read_shadow[31:24];
4 : rv_reg2spi = {3'b000,rv_read_shadow[36:32]};
default : rv_reg2spi = 0;
endcase // case ( rv_shadow_byte )
end
/*
* This state machine handles parallelizing the byte-widge chunks coming
* from the SPI into the full 37 bit test bus vector. When the parallel
* shadow bus is loaded, ena_reg_write is raised which initiates the state
* machine clocked by the internal oscillator.
*/
reg [36:0] rv_write_shadow;
reg r_ena_reg_write;
reg r_ser2par_done;
always @( posedge i_rx_valid or negedge active ) begin : write_fsm
if ( ! active ) begin
r_ena_reg_write <= 0;
r_ser2par_done <= 0;
rv_write_shadow <= 0;
end else begin
if ( !r_ser2par_done ) begin
// Serialize the data while the byte number is within the register size
if ( 2 == vi_byte_num )
rv_write_shadow[7:0] <= vi_data_rx;
if ( 3 == vi_byte_num )
rv_write_shadow[15:8] <= vi_data_rx;
if ( 4 == vi_byte_num )
rv_write_shadow[23:16] <= vi_data_rx;
if ( 5 == vi_byte_num )
rv_write_shadow[31:24] <= vi_data_rx;
if ( 6 == vi_byte_num )
rv_write_shadow[36:32] <= vi_data_rx[4:0];
if ( rv_num_rd_bytes < vi_byte_num ) begin
// When enough bytes are loaded, stop loading data
r_ser2par_done <= 1;
r_ena_reg_write <= r_write_tbus;
end
end
end
end
/*
* This state machine is clocked on the external oscillator. It
* sends the appropriate _rd signal, waits for the success line to go
* high, then latches the data on the test bus to the shadow register
*/
reg [1:0] rv_rd_state;
localparam READ_IDLE = 0;
localparam READ_WAIT = 1;
localparam READ_DONE = 2;
always @( posedge i_clk_ext_osc or negedge active ) begin
if ( !active ) begin
rv_read_shadow <= 0;
rv_rd_tbus <= 0;
rv_rd_state <= READ_IDLE;
end else begin
if (( READ_IDLE == rv_rd_state ) && r_ena_reg_read ) begin
// A read was just initiated, and we need to send the right _rd
rv_rd_tbus[rv_addr] <= 1;
rv_rd_state <= READ_WAIT;
end
if (( READ_WAIT == rv_rd_state ) && io_success ) begin
// The read had been initiated, and now data has appeared on the bus
rv_read_shadow <= vio_tbus & rv_rd_mask;
rv_rd_tbus <= 0;
rv_rd_state <= READ_DONE;
end
if ( READ_DONE == rv_rd_state ) begin
// Wait here forever until SPI goes inactive again
rv_rd_tbus <= 0;
rv_rd_state <= READ_DONE;
end
end
end
/*
* This state machine handles writing data to the register interface
*/
reg [1:0] rv_wr_state;
localparam WRITE_IDLE = 0;
localparam WRITE_WAIT = 1;
localparam WRITE_DONE = 2;
always @( posedge i_clk_ext_osc or negedge active ) begin
if ( !active ) begin
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_IDLE;
end else begin
if (( WRITE_IDLE == rv_wr_state ) && r_ena_reg_write ) begin
// A write was just initiated, now send the right _wr and wait
rv_wr_tbus[rv_addr] <= 1;
rv_wr_state <= WRITE_WAIT;
end
if (( WRITE_WAIT == rv_wr_state ) && io_success ) begin
// The success signal indicates the data on vio_tbus was latched in
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_DONE;
end
if ( WRITE_DONE == rv_wr_state ) begin
// Stay here until bus resets
rv_wr_tbus <= 0;
rv_wr_state <= WRITE_DONE;
end
end
end
/*
* Tristate bus driver: drive the test bus when in register write mode,
* otherwise leave it floating.
*/
assign vio_tbus = r_write_tbus ? rv_write_shadow : 37'bz;
/*
* Tristate bus driver: only drive data back to SPI when we are in
* register read mode, otherwise float bus.
*/
assign vio_data_regs = r_read_tbus ? rv_reg2spi : 8'bz;
endmodule // spi_regs
|
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|P%d|%d%d%d|%d", cnt[19:0], u.core.elem, u.core.phase[2:0], u.core.iter_done, u.core.pchange, u.core.irst, u.core.ecnt);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("[%d](%d)", u.core.req, u.core.state);
$write("| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d|",
u.core.im00.imf.cnt, u.core.im01.imf.cnt, u.core.im02.imf.cnt, u.core.im03.imf.cnt,
u.core.im04.imf.cnt, u.core.im05.imf.cnt, u.core.im06.imf.cnt, u.core.im07.imf.cnt,
u.core.im08.imf.cnt, u.core.im09.imf.cnt, u.core.im10.imf.cnt, u.core.im11.imf.cnt,
u.core.im12.imf.cnt, u.core.im13.imf.cnt, u.core.im14.imf.cnt, u.core.im15.imf.cnt);
// $write("| %d %d %d %d %d %d %d %d|",
// u.core.im00.im_deq, u.core.im01.im_deq, u.core.im02.im_deq, u.core.im03.im_deq,
// u.core.im04.im_deq, u.core.im05.im_deq, u.core.im06.im_deq, u.core.im07.im_deq,
// u.core.im08.im_deq, u.core.im09.im_deq, u.core.im10.im_deq, u.core.im11.im_deq,
// u.core.im12.im_deq, u.core.im13.im_deq, u.core.im14.im_deq, u.core.im15.im_deq);
$write(" ");
if (u.core.F01_deq) $write("%08x %08x %08x %08x ", u.core.F01_dot[127:96], u.core.F01_dot[95:64], u.core.F01_dot[63:32], u.core.F01_dot[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Inspired by the post by Ulf Samuelsson
* http://www.velocityreviews.com/forums/t25846-p4-how-to-count-zeros-in-registers.html
*
* The idea is to use a divide-and-conquer approach to process a 2^N bit number.
* We split the number in two equal halves of 2^(N-1) bits :
* MMMMLLLL
* then, we check if MMMM is all 0's.
* If it is,
* then the number of leading zeros is 2^(N-1) + CLZ(LLLL)
* If it is not,
* then the number of leading zeros is CLZ(MMMM)
* Recursion stops with CLZ(0)=1 and CLZ(1)=0.
*
* If the input is not all zeros, we never propagate a carry and
* the additions can be replaced by OR's,
* giving the result bit per bit.
*
* In this implementation, we assume that d[0] = 1, yielding the result 31
* when the input is actually all 0's.
*/
module pfpu_clz32(
input [31:0] d,
output [4:0] clz
);
assign clz[4] = d[31:16] == 16'd0;
wire [15:0] d1 = clz[4] ? d[15:0] : d[31:16];
assign clz[3] = d1[15:8] == 8'd0;
wire [7:0] d2 = clz[3] ? d1[7:0] : d1[15:8];
assign clz[2] = d2[7:4] == 4'd0;
wire [3:0] d3 = clz[2] ? d2[3:0] : d2[7:4];
assign clz[1] = d3[3:2] == 2'd0;
wire [1:0] d4 = clz[1] ? d3[1:0] : d3[3:2];
assign clz[0] = d4[1] == 1'b0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_2_V
`define SKY130_FD_SC_MS__A311O_2_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_aluspr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_aluspr
// Description: This block implements the sum predict for the sparc alu.
// It takes two operands and produces the correct result if the
// sum is zero. If not, the output is undefined, but non-zero.
*/
module sparc_exu_aluspr(/*AUTOARG*/
// Outputs
spr_out,
// Inputs
rs1_data, rs2_data, cin
);
input [63:0] rs1_data;
input [63:0] rs2_data;
input cin;
output [63:0] spr_out;
wire [63:0] rs1_data_xor_rs2_data;
wire [62:0] rs1_data_or_rs2_data;
wire [63:0] shift_or;
assign rs1_data_xor_rs2_data[63:0] = rs1_data[63:0] ^ rs2_data[63:0];
assign rs1_data_or_rs2_data[62:0] = rs1_data[62:0] | rs2_data[62:0];
assign shift_or[63:0] = {rs1_data_or_rs2_data[62:0],cin};
assign spr_out[63:0] = rs1_data_xor_rs2_data[63:0] ^ shift_or[63:0];
endmodule // sparc_exu_aluspr
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_V
|
`timescale 1ns/ 10ps
`default_nettype none
module tb_gci_std_display;
parameter SYS_CYCLE = 20; //50MHz
parameter DISP_CYCLE = 40; //525MHz
reg iCLOCK;
reg inRESET;
//BUS(DATA)-Input
reg iDEV_REQ;
wire oDEV_BUSY;
reg iDEV_RW;
reg [31:0] iDEV_ADDR;
reg [31:0] iDEV_DATA;
//BUS(DATA)-Output
wire oDEV_REQ;
reg iDEV_BUSY;
wire [31:0] oDEV_DATA;
//IRQ
wire oDEV_IRQ_REQ;
reg iDEV_IRQ_BUSY;
wire [23:0] oDEV_IRQ_DATA;
reg iDEV_IRQ_ACK;
//Display Clock
reg iVGA_CLOCK;
`ifdef GCI_STD_DISPLAY_SRAM
//SRAM
wire onSRAM_CE;
wire onSRAM_WE;
wire onSRAM_OE;
wire onSRAM_UB;
wire onSRAM_LB;
wire [19:0] oSRAM_ADDR;
wire [15:0] ioSRAM_DATA;
`elsif GCI_STD_DISPLAY_SSRAM
//SSRAM
wire oSSRAM_CLOCK;
wire onSSRAM_ADSC;
wire onSSRAM_ADSP;
wire onSSRAM_ADC;
wire onSSRAM_GW;
wire onSSRAM_OE;
wire onSSRAM_WE;
wire [3:0] onSSRAM_BE;
wire onSSRAM_CE1;
wire oSSRAM_CE2;
wire onSSRAM_CE3;
wire [18:0] oSSRAM_ADDR;
wire [31:0] ioSSRAM_DATA;
wire [3:0] ioSSRAM_PARITY;
`endif
//Display
wire oDISP_CLOCK;
wire onDISP_RESET;
wire oDISP_ENA;
wire oDISP_BLANK;
wire onDISP_HSYNC;
wire onDISP_VSYNC;
wire [9:0] oDISP_DATA_R;
wire [9:0] oDISP_DATA_G;
wire [9:0] oDISP_DATA_B;
/********************************
Model
********************************/
//VGA
reg display_model_file_dump;
initial display_model_file_dump = 0;
display_model VGA_MODEL(
.iFILE_DUMP(display_model_file_dump),
.inSYNC_H(onDISP_HSYNC),
.inSYNC_V(onDISP_VSYNC),
.iDISP_R(oDISP_DATA_R),
.iDISP_G(oDISP_DATA_G),
.iDISP_B(oDISP_DATA_B)
);
//Memory
`ifdef GCI_STD_DISPLAY_SRAM
//SRAM
is61wv102416bll #(10) SRAM_MODEL(
.A(oSRAM_ADDR),
.IO(ioSRAM_DATA),
.CE_(onSRAM_CE),
.OE_(onSRAM_OE),
.WE_(onSRAM_WE),
.LB_(onSRAM_LB),
.UB_(onSRAM_UB)
);
`elsif GCI_STD_DISPLAY_SSRAM
//SSRAM
CY7C1380_PLSCD SSRAM_MODEL(
.ZZ(1'b0),
.Mode(1'b0), //Lenear Burst
.ADDR(oSSRAM_ADDR),
.GW_N(onSSRAM_GW),
.BWE_N(onSSRAM_WE),
.BWd_N(onSSRAM_BE[3]),
.BWc_N(onSSRAM_BE[2]),
.BWb_N(onSSRAM_BE[1]),
.BWa_N(onSSRAM_BE[0]),
.CE1_N(onSSRAM_CE1),
.CE2(oSSRAM_CE2),
.CE3_N(onSSRAM_CE3),
.ADSP_N(onSSRAM_ADSP),
.ADSC_N(onSSRAM_ADSC),
.ADV_N(onSSRAM_ADC),
.OE_N(onSSRAM_OE),
.DQ({ioSSRAM_PARITY[3], ioSSRAM_DATA[31:24], ioSSRAM_PARITY[2], ioSSRAM_DATA[23:16], ioSSRAM_PARITY[1], ioSSRAM_DATA[15:8], ioSSRAM_PARITY[0], ioSSRAM_DATA[7:0]}),
.CLK(oSSRAM_CLOCK)
);
`endif
integer i = 0;
//Port Initial
initial begin
#(SYS_CYCLE/2)begin
iCLOCK = 1'b1;
inRESET = 1'b0;
iDEV_REQ = 1'b0;
iDEV_RW = 1'b0;
iDEV_ADDR = 32'h0;
iDEV_DATA = 32'h0;
iDEV_BUSY = 1'b0;
iDEV_IRQ_BUSY = 1'b0;
iDEV_IRQ_ACK = 1'b0;
iVGA_CLOCK = 1'b0;
end
#(SYS_CYCLE) begin
inRESET = 1'b1;
#SYS_CYCLE;
inRESET = 1'b0;
#SYS_CYCLE;
inRESET = 1'b1;
end
end
/**************************************
Test Vector
**************************************/
reg [7:0] b_disp_b[0:(640*480)-1];
reg [7:0] b_disp_g[0:(640*480)-1];
reg [7:0] b_disp_r[0:(640*480)-1];
function [7:0] f_test_r;
input [15:0] data;
begin
f_test_r = {data[4:0], {3{data[0]}}};
end
endfunction
function [7:0] f_test_g;
input [15:0] data;
begin
f_test_g = {data[10:5], {2{data[5]}}};
end
endfunction
function [7:0] f_test_b;
input [15:0] data;
begin
f_test_b = {data[15:11], {3{data[11]}}};
end
endfunction
function [7:0] func_mask;
input [8:0] data;
begin
func_mask = data[7:0];
end
endfunction
integer fp;
integer l;
initial begin
#(500);
//File Dump Start
while(!vram_writend_flag)begin
#(200);
end
for(l = 0; l < 640*480; l = l + 1)begin
if(!l[0])begin
b_disp_r[l] = f_test_r({func_mask(SSRAM_MODEL.bank1[l>>1]), func_mask(SSRAM_MODEL.bank0[l>>1])});
b_disp_g[l] = f_test_g({func_mask(SSRAM_MODEL.bank1[l>>1]), func_mask(SSRAM_MODEL.bank0[l>>1])});
b_disp_b[l] = f_test_b({func_mask(SSRAM_MODEL.bank1[l>>1]), func_mask(SSRAM_MODEL.bank0[l>>1])});
end
else begin
b_disp_r[l] = f_test_r({func_mask(SSRAM_MODEL.bank3[l>>1]), func_mask(SSRAM_MODEL.bank2[l>>1])});
b_disp_g[l] = f_test_g({func_mask(SSRAM_MODEL.bank3[l>>1]), func_mask(SSRAM_MODEL.bank2[l>>1])});
b_disp_b[l] = f_test_b({func_mask(SSRAM_MODEL.bank3[l>>1]), func_mask(SSRAM_MODEL.bank2[l>>1])});
end
end
//File Open
fp = $fopen("dump_disp_memory.bmp", "wb");
if(!fp)begin
$display("File open error");
$stop;
end
//File dump
tsk_write_bmp();
$fclose(fp);
$stop;
end
//File Header
reg [15:0] bfType = "BM";
reg [31:0] bfSize = 14+40+(640*480*4); //File Header + Info Header + PixcelData32bit
reg [15:0] bfReserved1 = 0;
reg [15:0] bfReserved2 = 0;
reg [31:0] bfOffBits = 14+40; //File Header + Info Header
//Info Header
reg [31:0] biSize = 40;
reg [31:0] biWidth = 640;
reg [31:0] biHeight = 480;
reg [15:0] biPlanes = 1;
reg [15:0] biBitCount = 32;
reg [31:0] biCopmression = 0;
reg [31:0] biSizeImage = 3780;
reg [31:0] biXPixPerMeter = 3780;
reg [31:0] biYPixPerMeter = 3780;
reg [31:0] biClrUsed = 0;
reg [31:0] biCirImportant = 0;
//ReserveData
reg [7:0] bBitReserved = 0;
task tsk_write_bmp;
begin
//Write File Header
$fwrite(fp, "%s", bfType);
$fwrite(fp, "%c", bfSize[7:0]);
$fwrite(fp, "%c", bfSize[15:8]);
$fwrite(fp, "%c", bfSize[23:16]);
$fwrite(fp, "%c", bfSize[31:24]);
$fwrite(fp, "%c", bfReserved1[7:0]);
$fwrite(fp, "%c", bfReserved1[15:8]);
$fwrite(fp, "%c", bfReserved2[7:0]);
$fwrite(fp, "%c", bfReserved2[15:8]);
$fwrite(fp, "%c", bfOffBits[7:0]);
$fwrite(fp, "%c", bfOffBits[15:8]);
$fwrite(fp, "%c", bfOffBits[23:16]);
$fwrite(fp, "%c", bfOffBits[31:24]);
//Write Info Header
$fwrite(fp, "%c", biSize[7:0]);
$fwrite(fp, "%c", biSize[15:8]);
$fwrite(fp, "%c", biSize[23:16]);
$fwrite(fp, "%c", biSize[31:24]);
$fwrite(fp, "%c", biWidth[7:0]);
$fwrite(fp, "%c", biWidth[15:8]);
$fwrite(fp, "%c", biWidth[23:16]);
$fwrite(fp, "%c", biWidth[31:24]);
$fwrite(fp, "%c", biHeight[7:0]);
$fwrite(fp, "%c", biHeight[15:8]);
$fwrite(fp, "%c", biHeight[23:16]);
$fwrite(fp, "%c", biHeight[31:24]);
$fwrite(fp, "%c", biPlanes[7:0]);
$fwrite(fp, "%c", biPlanes[15:8]);
$fwrite(fp, "%c", biBitCount[7:0]);
$fwrite(fp, "%c", biBitCount[15:8]);
$fwrite(fp, "%c", biCopmression[7:0]);
$fwrite(fp, "%c", biCopmression[15:8]);
$fwrite(fp, "%c", biCopmression[23:16]);
$fwrite(fp, "%c", biCopmression[31:24]);
$fwrite(fp, "%c", biSizeImage[7:0]);
$fwrite(fp, "%c", biSizeImage[15:8]);
$fwrite(fp, "%c", biSizeImage[23:16]);
$fwrite(fp, "%c", biSizeImage[31:24]);
$fwrite(fp, "%c", biXPixPerMeter[7:0]);
$fwrite(fp, "%c", biXPixPerMeter[15:8]);
$fwrite(fp, "%c", biXPixPerMeter[23:16]);
$fwrite(fp, "%c", biXPixPerMeter[31:24]);
$fwrite(fp, "%c", biYPixPerMeter[7:0]);
$fwrite(fp, "%c", biYPixPerMeter[15:8]);
$fwrite(fp, "%c", biYPixPerMeter[23:16]);
$fwrite(fp, "%c", biYPixPerMeter[31:24]);
$fwrite(fp, "%c", biClrUsed[7:0]);
$fwrite(fp, "%c", biClrUsed[15:8]);
$fwrite(fp, "%c", biClrUsed[23:16]);
$fwrite(fp, "%c", biClrUsed[31:24]);
$fwrite(fp, "%c", biCirImportant[7:0]);
$fwrite(fp, "%c", biCirImportant[15:8]);
$fwrite(fp, "%c", biCirImportant[23:16]);
$fwrite(fp, "%c", biCirImportant[31:24]);
//Write Pixcel Data
for(i = (640*480)-1; i >= 0 ; i = i - 1)begin : F_DATA_OUT
$fwrite(fp, "%c%c%c%c", b_disp_b[i], b_disp_g[i], b_disp_r[i], bBitReserved);
end
end
endtask
//VRAM Write
reg vram_writend_flag;
initial begin
#0 begin
vram_writend_flag = 0;
end
#(SYS_CYCLE/2)
//Write VRAM
#(SYS_CYCLE*20)begin
for(i = 0; i < 640*480; i = i+1)begin
tsk_write_data(32'hc400 + i*4, func_patgen(i%640, i/640));
end
vram_writend_flag = 1;
$display("VRAM Write END");
display_model_file_dump = 1;
end
end
task tsk_write_data;
input [31:0] addr;
input [31:0] data;
begin
iDEV_REQ = 1'b1;
iDEV_RW = 1'b1;
iDEV_ADDR = addr;
iDEV_DATA = data;
#(SYS_CYCLE);
while(oDEV_BUSY)begin
#(SYS_CYCLE);
end
iDEV_REQ = 1'b0;
#(SYS_CYCLE);
end
endtask
function [15:0] func_patgen;
input [9:0] func_h_addr;
input [8:0] func_v_addr;
reg [2:0] pri_h_case;
reg [1:0] pri_v_case;
reg [2:0] pri_puttern_case;
begin
//h
if(func_h_addr[9:4] < 6'h5)begin
pri_h_case = 3'H0;
end
else if(func_h_addr[9:4] < 6'ha)begin
pri_h_case = 3'h1;
end
else if(func_h_addr[9:4] < 6'hf)begin
pri_h_case = 3'h2;
end
else if(func_h_addr[9:4] < 6'h14)begin
pri_h_case = 3'h3;
end
else if(func_h_addr[9:4] < 6'h19)begin
pri_h_case = 3'h4;
end
else if(func_h_addr[9:4] < 6'h1e)begin
pri_h_case = 3'h5;
end
else if(func_h_addr[9:4] < 6'h23)begin
pri_h_case = 3'h6;
end
else begin
pri_h_case = 3'h7;
end
//v
if(func_v_addr < 9'h78)begin
pri_v_case = 2'h0;
end
else if(func_v_addr < 9'hf0)begin
pri_v_case = 2'h1;
end
else if(func_v_addr < 9'h168)begin
pri_v_case = 2'h2;
end
else begin
pri_v_case = 2'h3;
end
pri_puttern_case = pri_h_case + pri_v_case;
case(pri_puttern_case)
3'h0 : func_patgen = {5'hFF, 6'h00, 5'h00};
3'h1 : func_patgen = {5'h00, 6'hFF, 5'h00};
3'h2 : func_patgen = {5'h00, 6'h00, 5'hFF};
3'h3 : func_patgen = {5'hFF, 6'h00, 5'hFF};
3'h4 : func_patgen = {5'hFF, 6'hFF, 5'h00};
3'h5 : func_patgen = {5'h00, 6'hFF, 5'hFF};
3'h6 : func_patgen = {5'h00, 6'h00, 5'h00};
default : func_patgen = {5'hFF, 6'hFF, 5'hFF};
endcase
end
endfunction
//System CLock
always#(SYS_CYCLE/2)begin
iCLOCK = !iCLOCK;
end
//Display Clock
always#(DISP_CYCLE/2)begin
iVGA_CLOCK = !iVGA_CLOCK;
end
gci_std_display TARGET(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//BUS(DATA)-Input
.iDEV_REQ(iDEV_REQ),
.oDEV_BUSY(oDEV_BUSY),
.iDEV_RW(iDEV_RW),
.iDEV_ADDR(iDEV_ADDR),
.iDEV_DATA(iDEV_DATA),
//BUS(DATA)-Output
.oDEV_REQ(oDEV_REQ),
.iDEV_BUSY(iDEV_BUSY),
.oDEV_DATA(oDEV_DATA),
//IRQ
.oDEV_IRQ_REQ(oDEV_IRQ_REQ),
.iDEV_IRQ_BUSY(iDEV_IRQ_BUSY),
.oDEV_IRQ_DATA(oDEV_IRQ_DATA),
.iDEV_IRQ_ACK(iDEV_IRQ_ACK),
//Display Clock
.iVGA_CLOCK(iVGA_CLOCK),
//SRAM
`ifdef GCI_STD_DISPLAY_SRAM
.onSRAM_CE(onSRAM_CE),
.onSRAM_WE(onSRAM_WE),
.onSRAM_OE(onSRAM_OE),
.onSRAM_UB(onSRAM_UB),
.onSRAM_LB(onSRAM_LB),
.oSRAM_ADDR(oSRAM_ADDR),
.ioSRAM_DATA(ioSRAM_DATA),
`elsif GCI_STD_DISPLAY_SSRAM
.oSSRAM_CLOCK(oSSRAM_CLOCK),
.onSSRAM_ADSC(onSSRAM_ADSC),
.onSSRAM_ADSP(onSSRAM_ADSP),
.onSSRAM_ADV(onSSRAM_ADC),
.onSSRAM_GW(onSSRAM_GW),
.onSSRAM_OE(onSSRAM_OE),
.onSSRAM_WE(onSSRAM_WE),
.onSSRAM_BE(onSSRAM_BE),
.onSSRAM_CE1(onSSRAM_CE1),
.oSSRAM_CE2(oSSRAM_CE2),
.onSSRAM_CE3(onSSRAM_CE3),
.oSSRAM_ADDR(oSSRAM_ADDR),
.ioSSRAM_DATA(ioSSRAM_DATA),
.ioSSRAM_PARITY(ioSSRAM_PARITY),
`endif
//Display
.oDISP_CLOCK(oDISP_CLOCK),
.onDISP_RESET(onDISP_RESET),
.oDISP_ENA(oDISP_ENA),
.oDISP_BLANK(oDISP_BLANK),
.onDISP_HSYNC(onDISP_HSYNC),
.onDISP_VSYNC(onDISP_VSYNC),
.oDISP_DATA_R(oDISP_DATA_R),
.oDISP_DATA_G(oDISP_DATA_G),
.oDISP_DATA_B(oDISP_DATA_B)
);
endmodule
`default_nettype wire
|
`timescale 1ns/1ps
module sort_cell #(
parameter SORT_WIDTH=32,
parameter SHIFT_INPUT_WIDTH=8,
parameter PRI_POS_START=0,
parameter PRI_POS_END=32
) (
input clk,
input reset,
//Forward shift path
input [SORT_WIDTH-1:0] prev_data,
output [SORT_WIDTH-1:0] data_out,
input [SORT_WIDTH-1:0] datain,
input place_en,
input wren,
input order,
input left_is_lower,
output i_am_lower //if (datain>= data_out), ly is set otherwise reset
);
reg [SORT_WIDTH-1:0] datain_stored;
reg [SORT_WIDTH-1:0] current;
assign data_out = current;
reg is_lower, is_lower_next;
wire aleb;
wire [31:0] current_priority;
wire [31:0] datain_priority;
assign current_priority = current[PRI_POS_END-1:PRI_POS_START];
assign datain_priority = datain[PRI_POS_END-1:PRI_POS_START];
assign i_am_lower = is_lower;
//data in is [key, val, delta, pri, ptr]
//look at pri field for comparison
//assign i_am_bigger = (current[PRI_POS_END-1:PRI_POS_START]>datain[PRI_POS_END-1:PRI_POS_START])?1'b1:1'b0;
/*A comparator for floating point comparisons*/
float_cmp fcomp (
.clk_en (place_en), //when the place_en is high, the floating_cmp compares the data and produces aleb - This result will be used 1 cycle later when wren is asserted
.clock (clk),
.dataa (current_priority),
.datab (datain_priority),
.aleb (aleb)
);
always@(posedge clk)
begin
if(reset) begin
current <= 0;
is_lower <= 0;
datain_stored <= 0;
end
else begin
if(wren) begin
current <= current;
is_lower <= (aleb)?1'b1:1'b0; //(current_priority<=datain_priority)?1'b1:1'b0;
end
else if(order) begin //this logic will make the logic shift right (if the cell's value is lower than the incoming data value)
is_lower <= is_lower;
case({left_is_lower,i_am_lower})
2'b01: current <= datain_stored;
2'b11: current <= prev_data;
default: current <= current;
endcase
end
else begin
current <= current;
is_lower <= is_lower;
end
datain_stored <= datain;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFXBP_FUNCTIONAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXBP_FUNCTIONAL_PP_V
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
// Baudrate generator for asyncronous data transmitters (e.g. UARTs).
module BAUDGEN(
input clk,
input rst,
output reg baud_edge
);
parameter COUNTER = 200;
reg [$clog2(COUNTER)-1:0] counter;
always @(posedge clk) begin
if(rst) begin
counter <= 0;
baud_edge <= 0;
end else begin
if(counter == COUNTER-1) begin
baud_edge <= 1;
counter <= 0;
end else begin
baud_edge <= 0;
counter <= counter + 1;
end
end
end
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_afi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
* from Cadence.
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_afi_slave (
S_RESETN,
S_ARREADY,
S_AWREADY,
S_BVALID,
S_RLAST,
S_RVALID,
S_WREADY,
S_BRESP,
S_RRESP,
S_RDATA,
S_BID,
S_RID,
S_ACLK,
S_ARVALID,
S_AWVALID,
S_BREADY,
S_RREADY,
S_WLAST,
S_WVALID,
S_ARBURST,
S_ARLOCK,
S_ARSIZE,
S_AWBURST,
S_AWLOCK,
S_AWSIZE,
S_ARPROT,
S_AWPROT,
S_ARADDR,
S_AWADDR,
S_WDATA,
S_ARCACHE,
S_ARLEN,
S_AWCACHE,
S_AWLEN,
S_WSTRB,
S_ARID,
S_AWID,
S_WID,
S_AWQOS,
S_ARQOS,
SW_CLK,
WR_DATA_ACK_OCM,
WR_DATA_ACK_DDR,
WR_ADDR,
WR_DATA,
WR_BYTES,
WR_DATA_VALID_OCM,
WR_DATA_VALID_DDR,
WR_QOS,
RD_REQ_DDR,
RD_REQ_OCM,
RD_ADDR,
RD_DATA_OCM,
RD_DATA_DDR,
RD_BYTES,
RD_QOS,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR,
S_RDISSUECAP1_EN,
S_WRISSUECAP1_EN,
S_RCOUNT,
S_WCOUNT,
S_RACOUNT,
S_WACOUNT
);
parameter enable_this_port = 0;
parameter slave_name = "Slave";
parameter data_bus_width = 32;
parameter address_bus_width = 32;
parameter id_bus_width = 6;
parameter slave_base_address = 0;
parameter slave_high_address = 4;
parameter max_outstanding_transactions = 8;
parameter exclusive_access_supported = 0;
`include "processing_system7_bfm_v2_0_local_params.v"
/* Local parameters only for this module */
/* Internal counters that are used as Read/Write pointers to the fifo's that store all the transaction info on all channles.
This parameter is used to define the width of these pointers --> depending on Maximum outstanding transactions supported.
1-bit extra width than the no.of.bits needed to represent the outstanding transactions
Extra bit helps in generating the empty and full flags
*/
parameter int_cntr_width = clogb2(max_outstanding_transactions)+1;
/* RESP data */
parameter rsp_fifo_bits = axi_rsp_width+id_bus_width;
parameter rsp_lsb = 0;
parameter rsp_msb = axi_rsp_width-1;
parameter rsp_id_lsb = rsp_msb + 1;
parameter rsp_id_msb = rsp_id_lsb + id_bus_width-1;
input S_RESETN;
output S_ARREADY;
output S_AWREADY;
output S_BVALID;
output S_RLAST;
output S_RVALID;
output S_WREADY;
output [axi_rsp_width-1:0] S_BRESP;
output [axi_rsp_width-1:0] S_RRESP;
output [data_bus_width-1:0] S_RDATA;
output [id_bus_width-1:0] S_BID;
output [id_bus_width-1:0] S_RID;
input S_ACLK;
input S_ARVALID;
input S_AWVALID;
input S_BREADY;
input S_RREADY;
input S_WLAST;
input S_WVALID;
input [axi_brst_type_width-1:0] S_ARBURST;
input [axi_lock_width-1:0] S_ARLOCK;
input [axi_size_width-1:0] S_ARSIZE;
input [axi_brst_type_width-1:0] S_AWBURST;
input [axi_lock_width-1:0] S_AWLOCK;
input [axi_size_width-1:0] S_AWSIZE;
input [axi_prot_width-1:0] S_ARPROT;
input [axi_prot_width-1:0] S_AWPROT;
input [address_bus_width-1:0] S_ARADDR;
input [address_bus_width-1:0] S_AWADDR;
input [data_bus_width-1:0] S_WDATA;
input [axi_cache_width-1:0] S_ARCACHE;
input [axi_cache_width-1:0] S_ARLEN;
input [axi_qos_width-1:0] S_ARQOS;
input [axi_cache_width-1:0] S_AWCACHE;
input [axi_len_width-1:0] S_AWLEN;
input [axi_qos_width-1:0] S_AWQOS;
input [(data_bus_width/8)-1:0] S_WSTRB;
input [id_bus_width-1:0] S_ARID;
input [id_bus_width-1:0] S_AWID;
input [id_bus_width-1:0] S_WID;
input SW_CLK;
input WR_DATA_ACK_DDR, WR_DATA_ACK_OCM;
output WR_DATA_VALID_DDR, WR_DATA_VALID_OCM;
output [max_burst_bits-1:0] WR_DATA;
output [addr_width-1:0] WR_ADDR;
output [max_transfer_bytes_width:0] WR_BYTES;
output reg RD_REQ_OCM, RD_REQ_DDR;
output reg [addr_width-1:0] RD_ADDR;
input [max_burst_bits-1:0] RD_DATA_DDR,RD_DATA_OCM;
output reg[max_transfer_bytes_width:0] RD_BYTES;
input RD_DATA_VALID_OCM,RD_DATA_VALID_DDR;
output [axi_qos_width-1:0] WR_QOS;
output reg [axi_qos_width-1:0] RD_QOS;
input S_RDISSUECAP1_EN;
input S_WRISSUECAP1_EN;
output [7:0] S_RCOUNT;
output [7:0] S_WCOUNT;
output [2:0] S_RACOUNT;
output [5:0] S_WACOUNT;
wire net_ARVALID;
wire net_AWVALID;
wire net_WVALID;
real s_aclk_period;
cdn_axi3_slave_bfm #(slave_name,
data_bus_width,
address_bus_width,
id_bus_width,
slave_base_address,
(slave_high_address- slave_base_address),
max_outstanding_transactions,
0, ///MEMORY_MODEL_MODE,
exclusive_access_supported)
slave (.ACLK (S_ACLK),
.ARESETn (S_RESETN), /// confirm this
// Write Address Channel
.AWID (S_AWID),
.AWADDR (S_AWADDR),
.AWLEN (S_AWLEN),
.AWSIZE (S_AWSIZE),
.AWBURST (S_AWBURST),
.AWLOCK (S_AWLOCK),
.AWCACHE (S_AWCACHE),
.AWPROT (S_AWPROT),
.AWVALID (net_AWVALID),
.AWREADY (S_AWREADY),
// Write Data Channel Signals.
.WID (S_WID),
.WDATA (S_WDATA),
.WSTRB (S_WSTRB),
.WLAST (S_WLAST),
.WVALID (net_WVALID),
.WREADY (S_WREADY),
// Write Response Channel Signals.
.BID (S_BID),
.BRESP (S_BRESP),
.BVALID (S_BVALID),
.BREADY (S_BREADY),
// Read Address Channel Signals.
.ARID (S_ARID),
.ARADDR (S_ARADDR),
.ARLEN (S_ARLEN),
.ARSIZE (S_ARSIZE),
.ARBURST (S_ARBURST),
.ARLOCK (S_ARLOCK),
.ARCACHE (S_ARCACHE),
.ARPROT (S_ARPROT),
.ARVALID (net_ARVALID),
.ARREADY (S_ARREADY),
// Read Data Channel Signals.
.RID (S_RID),
.RDATA (S_RDATA),
.RRESP (S_RRESP),
.RLAST (S_RLAST),
.RVALID (S_RVALID),
.RREADY (S_RREADY));
wire wr_intr_fifo_full;
reg temp_wr_intr_fifo_full;
/* Interconnect WR_FIFO model instance */
processing_system7_bfm_v2_0_intr_wr_mem wr_intr_fifo(SW_CLK, S_RESETN, wr_intr_fifo_full, WR_DATA_ACK_OCM, WR_DATA_ACK_DDR, WR_ADDR, WR_DATA, WR_BYTES, WR_QOS, WR_DATA_VALID_OCM, WR_DATA_VALID_DDR);
/* Register the async 'full' signal to S_ACLK clock */
always@(posedge S_ACLK) temp_wr_intr_fifo_full = wr_intr_fifo_full;
/* Latency type and Debug/Error Control */
reg[1:0] latency_type = RANDOM_CASE;
reg DEBUG_INFO = 1;
reg STOP_ON_ERROR = 1'b1;
/* Internal nets/regs for calling slave BFM API's*/
reg [wr_afi_fifo_data_bits-1:0] wr_fifo [0:max_outstanding_transactions-1];
reg [int_cntr_width-1:0] wr_fifo_wr_ptr = 0, wr_fifo_rd_ptr = 0;
wire wr_fifo_empty;
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
reg [7:0] aw_time_cnt = 0,bresp_time_cnt = 0;
real awvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new awvalid is received
reg awvalid_flag[0:max_outstanding_transactions]; // store the time when a new awvalid is received
/* Address Write Channel handshake*/
reg[int_cntr_width-1:0] aw_cnt = 0;//
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] awsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] awprot [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] awlock [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] awcache [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] awbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] awlen [0:max_outstanding_transactions-1];
reg aw_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] awaddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] awid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] awqos [0:max_outstanding_transactions-1];
wire aw_fifo_full; // indicates awvalid_fifo is full (max outstanding transactions reached)
/* internal fifos to store burst write data, ID & strobes*/
reg [(data_bus_width*axi_burst_len)-1:0] burst_data [0:max_outstanding_transactions-1];
reg [max_burst_bytes_width:0] burst_valid_bytes [0:max_outstanding_transactions-1]; /// total valid bytes received in a complete burst transfer
reg wlast_flag [0:max_outstanding_transactions-1]; // flag to indicate WLAST received
wire wd_fifo_full;
/* Write Data Channel and Write Response handshake signals*/
reg [int_cntr_width-1:0] wd_cnt = 0;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_wr_data;
reg [addr_width-1:0] aligned_wr_addr;
reg [max_burst_bytes_width:0] valid_data_bytes;
reg [int_cntr_width-1:0] wr_bresp_cnt = 0;
reg [axi_rsp_width-1:0] bresp;
reg [rsp_fifo_bits-1:0] fifo_bresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_bresp;
reg [int_cntr_width-1:0] rd_bresp_cnt = 0;
integer wr_latency_count;
reg wr_delayed;
wire bresp_fifo_empty;
/* keep track of count values */
reg[7:0] wcount;
reg[5:0] wacount;
/* Qos*/
reg [axi_qos_width-1:0] ar_qos, aw_qos;
initial begin
if(DEBUG_INFO) begin
if(enable_this_port)
$display("[%0d] : %0s : %0s : Port is ENABLED.",$time, DISP_INFO, slave_name);
else
$display("[%0d] : %0s : %0s : Port is DISABLED.",$time, DISP_INFO, slave_name);
end
end
/*--------------------------------------------------------------------------------*/
/* Store the Clock cycle time period */
always@(S_RESETN)
begin
if(S_RESETN) begin
@(posedge S_ACLK);
s_aclk_period = $time;
@(posedge S_ACLK);
s_aclk_period = $time - s_aclk_period;
end
end
/*--------------------------------------------------------------------------------*/
initial slave.set_disable_reset_value_checks(1);
initial begin
repeat(2) @(posedge S_ACLK);
if(!enable_this_port) begin
slave.set_channel_level_info(0);
slave.set_function_level_info(0);
end
slave.RESPONSE_TIMEOUT = 0;
end
/*--------------------------------------------------------------------------------*/
/* Set Latency type to be used */
task set_latency_type;
input[1:0] lat;
begin
if(enable_this_port)
latency_type = lat;
else begin
//if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'Latency Profile' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set ARQoS to be used */
task set_arqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
ar_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'ARQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* Set AWQoS to be used */
task set_awqos;
input[axi_qos_width-1:0] qos;
begin
if(enable_this_port)
aw_qos = qos;
else begin
if(DEBUG_INFO)
$display("[%0d] : %0s : %0s : Port is disabled. 'AWQOS' will not be set...",$time, DISP_WARN, slave_name);
end
end
endtask
/*--------------------------------------------------------------------------------*/
/* get the wr latency number */
function [31:0] get_wr_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_wr_lat_number = afi_wr_min;
AVG_CASE : get_wr_lat_number = afi_wr_avg;
WORST_CASE : get_wr_lat_number = afi_wr_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_wr_lat_number = ($random()%10+ afi_wr_min);
2'b01 : get_wr_lat_number = ($random()%40+ afi_wr_avg);
default : get_wr_lat_number = ($random()%60+ afi_wr_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* get the rd latency number */
function [31:0] get_rd_lat_number;
input dummy;
reg[1:0] temp;
begin
case(latency_type)
BEST_CASE : get_rd_lat_number = afi_rd_min;
AVG_CASE : get_rd_lat_number = afi_rd_avg;
WORST_CASE : get_rd_lat_number = afi_rd_max;
default : begin // RANDOM_CASE
temp = $random;
case(temp)
2'b00 : get_rd_lat_number = ($random()%10+ afi_rd_min);
2'b01 : get_rd_lat_number = ($random()%40+ afi_rd_avg);
default : get_rd_lat_number = ($random()%60+ afi_rd_max);
endcase
end
endcase
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Check for any WRITE/READs when this port is disabled */
always@(S_AWVALID or S_WVALID or S_ARVALID)
begin
if((S_AWVALID | S_WVALID | S_ARVALID) && !enable_this_port) begin
$display("[%0d] : %0s : %0s : Port is disabled. AXI transaction is initiated on this port ...\nSimulation will halt ..",$time, DISP_ERR, slave_name);
$stop;
end
end
/*--------------------------------------------------------------------------------*/
assign net_ARVALID = enable_this_port ? S_ARVALID : 1'b0;
assign net_AWVALID = enable_this_port ? S_AWVALID : 1'b0;
assign net_WVALID = enable_this_port ? S_WVALID : 1'b0;
assign wr_fifo_empty = (wr_fifo_wr_ptr === wr_fifo_rd_ptr)?1'b1: 1'b0;
assign bresp_fifo_empty = (wr_bresp_cnt === rd_bresp_cnt)?1'b1:1'b0;
assign bresp_fifo_full = ((wr_bresp_cnt[int_cntr_width-1] !== rd_bresp_cnt[int_cntr_width-1]) && (wr_bresp_cnt[int_cntr_width-2:0] === rd_bresp_cnt[int_cntr_width-2:0]))?1'b1:1'b0;
assign S_WCOUNT = wcount;
assign S_WACOUNT = wacount;
// FIFO_STATUS (only if AFI port) 1- full
function automatic wrfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - wcount;
if(fifo_space_left < fifo_space_exp)
wrfifo_full = 1;
else
wrfifo_full = 0;
end
endfunction
/*--------------------------------------------------------------------------------*/
/* Store the awvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_AWID or S_AWADDR or S_AWVALID )
begin
if(!S_RESETN)
aw_time_cnt = 0;
else begin
if(S_AWVALID) begin
awvalid_receive_time[aw_time_cnt] = $time;
awvalid_flag[aw_time_cnt] = 1'b1;
aw_time_cnt = aw_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_AWVALID && S_AWREADY) begin
if(S_AWQOS === 0) awqos[aw_cnt[int_cntr_width-2:0]] = aw_qos;
else awqos[aw_cnt[int_cntr_width-2:0]] = S_AWQOS;
end
end
/* Address Write Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
aw_cnt = 0;
wacount = 0;
end else begin
if(S_AWVALID && !wrfifo_full(S_AWLEN+1)) begin
slave.RECEIVE_WRITE_ADDRESS(0,
id_invalid,
awaddr[aw_cnt[int_cntr_width-2:0]],
awlen[aw_cnt[int_cntr_width-2:0]],
awsize[aw_cnt[int_cntr_width-2:0]],
awbrst[aw_cnt[int_cntr_width-2:0]],
awlock[aw_cnt[int_cntr_width-2:0]],
awcache[aw_cnt[int_cntr_width-2:0]],
awprot[aw_cnt[int_cntr_width-2:0]],
awid[aw_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
aw_flag[aw_cnt[int_cntr_width-2:0]] = 1'b1;
aw_cnt = aw_cnt + 1;
wacount = wacount + 1;
end // if (!aw_fifo_full)
end /// if else
end /// always
/*--------------------------------------------------------------------------------*/
/* Write Data Channel Handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wd_cnt = 0;
end else begin
if(aw_flag[wd_cnt[int_cntr_width-2:0]]) begin
if(S_WVALID && !wrfifo_full(awlen[wd_cnt[int_cntr_width-2:0]] + 1)) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end else begin
if(!wrfifo_full(axi_burst_len+1) && S_WVALID) begin
slave.RECEIVE_WRITE_BURST_NO_CHECKS(S_WID, burst_data[wd_cnt[int_cntr_width-2:0]], burst_valid_bytes[wd_cnt[int_cntr_width-2:0]]);
wlast_flag[wd_cnt[int_cntr_width-2:0]] = 1'b1;
wd_cnt = wd_cnt + 1;
end
end /// if
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* Align the wrap data for write transaction */
task automatic get_wrap_aligned_wr_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
output [addr_width-1:0] start_addr; /// aligned start address
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
wrp_data = wrp_data << ((data_bus_width*axi_burst_len) - (v_bytes*8));
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data << 8;
temp_data[7:0] = wrp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8];
wrp_data = wrp_data << 8;
wrp_bytes = wrp_bytes - 1;
end
wrp_bytes = addr - start_addr;
wrp_data = b_data << (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
/* Calculate the Response for each read/write transaction */
function [axi_rsp_width-1:0] calculate_resp;
input [addr_width-1:0] awaddr;
input [axi_prot_width-1:0] awprot;
reg [axi_rsp_width-1:0] rsp;
begin
rsp = AXI_OK;
/* Address Decode */
if(decode_address(awaddr) === INVALID_MEM_TYPE) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Invalid location(0x%0h) ",$time, DISP_ERR, slave_name, awaddr);
end
else if(decode_address(awaddr) === REG_MEM) begin
rsp = AXI_SLV_ERR; //slave error
$display("[%0d] : %0s : %0s : AXI Access to Register Map(0x%0h) is not allowed through this port.",$time, DISP_ERR, slave_name, awaddr);
end
if(secure_access_enabled && awprot[1])
rsp = AXI_DEC_ERR; // decode error
calculate_resp = rsp;
end
endfunction
/*--------------------------------------------------------------------------------*/
reg[max_burst_bits-1:0] temp_wr_data;
/* Store the Write response for each write transaction */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_fifo_wr_ptr = 0;
wcount = 0;
end else begin
enable_write_bresp = aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] && wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]];
/* calculate bresp only when AWVALID && WLAST is received */
if(enable_write_bresp) begin
aw_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
wlast_flag[wr_fifo_wr_ptr[int_cntr_width-2:0]] = 0;
bresp = calculate_resp(awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], awprot[wr_fifo_wr_ptr[int_cntr_width-2:0]]);
/* Fill AFI_WR_data FIFO */
if(bresp === AXI_OK ) begin
if(awbrst[wr_fifo_wr_ptr[int_cntr_width-2:0]]=== AXI_WRAP) begin /// wrap type? then align the data
get_wrap_aligned_wr_data(aligned_wr_data, aligned_wr_addr, awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]], burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]],burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]]); /// gives wrapped start address
end else begin
aligned_wr_data = burst_data[wr_fifo_wr_ptr[int_cntr_width-2:0]];
aligned_wr_addr = awaddr[wr_fifo_wr_ptr[int_cntr_width-2:0]] ;
end
valid_data_bytes = burst_valid_bytes[wr_fifo_wr_ptr[int_cntr_width-2:0]];
end else
valid_data_bytes = 0;
temp_wr_data = aligned_wr_data;
wr_fifo[wr_fifo_wr_ptr[int_cntr_width-2:0]] = {awqos[wr_fifo_wr_ptr[int_cntr_width-2:0]], awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]], awid[wr_fifo_wr_ptr[int_cntr_width-2:0]], bresp, temp_wr_data, aligned_wr_addr, valid_data_bytes};
wcount = wcount + awlen[wr_fifo_wr_ptr[int_cntr_width-2:0]]+1;
wr_fifo_wr_ptr = wr_fifo_wr_ptr + 1;
end
end // else
end // always
/*--------------------------------------------------------------------------------*/
/* Send Write Response Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
rd_bresp_cnt = 0;
wr_latency_count = get_wr_lat_number(1);
wr_delayed = 0;
bresp_time_cnt = 0;
end else begin
wr_delayed = 1'b0;
if(awvalid_flag[bresp_time_cnt] && (($time - awvalid_receive_time[bresp_time_cnt])/s_aclk_period >= wr_latency_count))
wr_delayed = 1;
if(!bresp_fifo_empty && wr_delayed) begin
slave.SEND_WRITE_RESPONSE(fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_id_msb : rsp_id_lsb], // ID
fifo_bresp[rd_bresp_cnt[int_cntr_width-2:0]][rsp_msb : rsp_lsb] // Response
);
wr_delayed = 0;
awvalid_flag[bresp_time_cnt] = 1'b0;
bresp_time_cnt = bresp_time_cnt+1;
rd_bresp_cnt = rd_bresp_cnt + 1;
wr_latency_count = get_wr_lat_number(1);
end
end // else
end//always
/*--------------------------------------------------------------------------------*/
/* Write Response Channel handshake */
reg wr_int_state;
/* Reading from the wr_fifo and sending to Interconnect fifo*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
wr_int_state = 1'b0;
wr_bresp_cnt = 0;
wr_fifo_rd_ptr = 0;
end else begin
case(wr_int_state)
1'b0 : begin
wr_int_state = 1'b0;
if(!temp_wr_intr_fifo_full && !bresp_fifo_full && !wr_fifo_empty) begin
wr_intr_fifo.write_mem({wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_qos_msb:wr_afi_qos_lsb], wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_data_msb:wr_afi_bytes_lsb]}); /// qos, data, address and valid_bytes
wr_int_state = 1'b1;
/* start filling the write response fifo at the same time */
fifo_bresp[wr_bresp_cnt[int_cntr_width-2:0]] = wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_id_msb:wr_afi_rsp_lsb]; // ID and Resp
wcount = wcount - (wr_fifo[wr_fifo_rd_ptr[int_cntr_width-2:0]][wr_afi_ln_msb:wr_afi_ln_lsb] + 1); /// burst length
wacount = wacount - 1;
wr_fifo_rd_ptr = wr_fifo_rd_ptr + 1;
wr_bresp_cnt = wr_bresp_cnt+1;
end
end
1'b1 : begin
wr_int_state = 0;
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
/*-------------------------------- WRITE HANDSHAKE END ----------------------------------------*/
/*-------------------------------- READ HANDSHAKE ---------------------------------------------*/
/* READ CHANNELS */
/* Store the arvalid receive time --- necessary for calculating latency in sending the rresp latency */
reg [7:0] ar_time_cnt = 0,rresp_time_cnt = 0;
real arvalid_receive_time[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg arvalid_flag[0:max_outstanding_transactions]; // store the time when a new arvalid is received
reg [int_cntr_width-1:0] ar_cnt = 0;// counter for arvalid info
/* various FIFOs for storing the ADDR channel info */
reg [axi_size_width-1:0] arsize [0:max_outstanding_transactions-1];
reg [axi_prot_width-1:0] arprot [0:max_outstanding_transactions-1];
reg [axi_brst_type_width-1:0] arbrst [0:max_outstanding_transactions-1];
reg [axi_len_width-1:0] arlen [0:max_outstanding_transactions-1];
reg [axi_cache_width-1:0] arcache [0:max_outstanding_transactions-1];
reg [axi_lock_width-1:0] arlock [0:max_outstanding_transactions-1];
reg ar_flag [0:max_outstanding_transactions-1];
reg [addr_width-1:0] araddr [0:max_outstanding_transactions-1];
reg [id_bus_width-1:0] arid [0:max_outstanding_transactions-1];
reg [axi_qos_width-1:0] arqos [0:max_outstanding_transactions-1];
wire ar_fifo_full; // indicates arvalid_fifo is full (max outstanding transactions reached)
reg [int_cntr_width-1:0] wr_rresp_cnt = 0;
reg [axi_rsp_width-1:0] rresp;
reg [rsp_fifo_bits-1:0] fifo_rresp [0:max_outstanding_transactions-1]; // store the ID and its corresponding response
reg enable_write_rresp;
/* Send Read Response & Data Channel handshake */
integer rd_latency_count;
reg rd_delayed;
reg [rd_afi_fifo_bits-1:0] read_fifo[0:max_outstanding_transactions-1]; /// Read Burst Data, addr, size, burst, len, RID, RRESP, valid_bytes
reg [int_cntr_width-1:0] rd_fifo_wr_ptr = 0, rd_fifo_rd_ptr = 0;
wire read_fifo_full;
reg [7:0] rcount;
reg [2:0] racount;
wire rd_intr_fifo_full, rd_intr_fifo_empty;
wire read_fifo_empty;
/* signals to communicate with interconnect RD_FIFO model */
reg rd_req, invalid_rd_req;
/* REad control Info
56:25 : Address (32)
24:22 : Size (3)
21:20 : BRST (2)
19:16 : LEN (4)
15:10 : RID (6)
9:8 : RRSP (2)
7:0 : byte cnt (8)
*/
reg [rd_info_bits-1:0] read_control_info;
reg [(data_bus_width*axi_burst_len)-1:0] aligned_rd_data;
reg temp_rd_intr_fifo_empty;
processing_system7_bfm_v2_0_intr_rd_mem rd_intr_fifo(SW_CLK, S_RESETN, rd_intr_fifo_full, rd_intr_fifo_empty, rd_req, invalid_rd_req, read_control_info , RD_DATA_OCM, RD_DATA_DDR, RD_DATA_VALID_OCM, RD_DATA_VALID_DDR);
assign read_fifo_empty = (rd_fifo_wr_ptr === rd_fifo_rd_ptr)?1'b1: 1'b0;
assign S_RCOUNT = rcount;
assign S_RACOUNT = racount;
/* Register the asynch signal empty coming from Interconnect READ FIFO */
always@(posedge S_ACLK) temp_rd_intr_fifo_empty = rd_intr_fifo_empty;
// FIFO_STATUS (only if AFI port) 1- full
function automatic rdfifo_full ;
input [axi_len_width:0] fifo_space_exp;
integer fifo_space_left;
begin
fifo_space_left = afi_fifo_locations - rcount;
if(fifo_space_left < fifo_space_exp)
rdfifo_full = 1;
else
rdfifo_full = 0;
end
endfunction
/* Store the arvalid receive time --- necessary for calculating the bresp latency */
always@(negedge S_RESETN or S_ARID or S_ARADDR or S_ARVALID )
begin
if(!S_RESETN)
ar_time_cnt = 0;
else begin
if(S_ARVALID) begin
arvalid_receive_time[ar_time_cnt] = $time;
arvalid_flag[ar_time_cnt] = 1'b1;
ar_time_cnt = ar_time_cnt + 1;
end
end // else
end /// always
/*--------------------------------------------------------------------------------*/
always@(posedge S_ACLK)
begin
if(net_ARVALID && S_ARREADY) begin
if(S_ARQOS === 0) arqos[aw_cnt[int_cntr_width-2:0]] = ar_qos;
else arqos[aw_cnt[int_cntr_width-2:0]] = S_ARQOS;
end
end
/* Address Read Channel handshake*/
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN) begin
ar_cnt = 0;
racount = 0;
end else begin
if(S_ARVALID && !rdfifo_full(S_ARLEN+1)) begin /// if AFI read fifo is not full
slave.RECEIVE_READ_ADDRESS(0,
id_invalid,
araddr[ar_cnt[int_cntr_width-2:0]],
arlen[ar_cnt[int_cntr_width-2:0]],
arsize[ar_cnt[int_cntr_width-2:0]],
arbrst[ar_cnt[int_cntr_width-2:0]],
arlock[ar_cnt[int_cntr_width-2:0]],
arcache[ar_cnt[int_cntr_width-2:0]],
arprot[ar_cnt[int_cntr_width-2:0]],
arid[ar_cnt[int_cntr_width-2:0]]); /// sampled valid ID.
ar_flag[ar_cnt[int_cntr_width-2:0]] = 1'b1;
ar_cnt = ar_cnt+1;
racount = racount + 1;
end /// if(!ar_fifo_full)
end /// if else
end /// always*/
/*--------------------------------------------------------------------------------*/
/* Align Wrap data for read transaction*/
task automatic get_wrap_aligned_rd_data;
output [(data_bus_width*axi_burst_len)-1:0] aligned_data;
input [addr_width-1:0] addr;
input [(data_bus_width*axi_burst_len)-1:0] b_data;
input [max_burst_bytes_width:0] v_bytes;
reg [addr_width-1:0] start_addr;
reg [(data_bus_width*axi_burst_len)-1:0] temp_data, wrp_data;
integer wrp_bytes;
integer i;
begin
start_addr = (addr/v_bytes) * v_bytes;
wrp_bytes = addr - start_addr;
wrp_data = b_data;
temp_data = 0;
while(wrp_bytes > 0) begin /// get the data that is wrapped
temp_data = temp_data >> 8;
temp_data[(data_bus_width*axi_burst_len)-1 : (data_bus_width*axi_burst_len)-8] = wrp_data[7:0];
wrp_data = wrp_data >> 8;
wrp_bytes = wrp_bytes - 1;
end
temp_data = temp_data >> ((data_bus_width*axi_burst_len) - (v_bytes*8));
wrp_bytes = addr - start_addr;
wrp_data = b_data >> (wrp_bytes*8);
aligned_data = (temp_data | wrp_data);
end
endtask
/*--------------------------------------------------------------------------------*/
parameter RD_DATA_REQ = 1'b0, WAIT_RD_VALID = 1'b1;
reg rd_fifo_state;
reg [addr_width-1:0] temp_read_address;
reg [max_burst_bytes_width:0] temp_rd_valid_bytes;
/* get the data from memory && also calculate the rresp*/
always@(negedge S_RESETN or posedge SW_CLK)
begin
if(!S_RESETN)begin
wr_rresp_cnt =0;
rd_fifo_state = RD_DATA_REQ;
temp_rd_valid_bytes = 0;
temp_read_address = 0;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
rd_req = 0;
invalid_rd_req= 0;
RD_QOS = 0;
end else begin
case(rd_fifo_state)
RD_DATA_REQ : begin
rd_fifo_state = RD_DATA_REQ;
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
if(ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] && !rd_intr_fifo_full) begin /// check the rd_fifo_bytes, interconnect fifo full condition
ar_flag[wr_rresp_cnt[int_cntr_width-2:0]] = 0;
rresp = calculate_resp(araddr[wr_rresp_cnt[int_cntr_width-2:0]],arprot[wr_rresp_cnt[int_cntr_width-2:0]]);
temp_rd_valid_bytes = (arlen[wr_rresp_cnt[int_cntr_width-2:0]]+1)*(2**arsize[wr_rresp_cnt[int_cntr_width-2:0]]);//data_bus_width/8;
if(arbrst[wr_rresp_cnt[int_cntr_width-2:0]] === AXI_WRAP) /// wrap begin
temp_read_address = (araddr[wr_rresp_cnt[int_cntr_width-2:0]]/temp_rd_valid_bytes) * temp_rd_valid_bytes;
else
temp_read_address = araddr[wr_rresp_cnt[int_cntr_width-2:0]];
if(rresp === AXI_OK) begin
case(decode_address(temp_read_address))//decode_address(araddr[wr_rresp_cnt[int_cntr_width-2:0]]);
OCM_MEM : RD_REQ_OCM = 1;
DDR_MEM : RD_REQ_DDR = 1;
default : invalid_rd_req = 1;
endcase
end else
invalid_rd_req = 1;
RD_ADDR = temp_read_address; ///araddr[wr_rresp_cnt[int_cntr_width-2:0]];
RD_BYTES = temp_rd_valid_bytes;
RD_QOS = arqos[wr_rresp_cnt[int_cntr_width-2:0]];
rd_fifo_state = WAIT_RD_VALID;
rd_req = 1;
racount = racount - 1;
read_control_info = {araddr[wr_rresp_cnt[int_cntr_width-2:0]], arsize[wr_rresp_cnt[int_cntr_width-2:0]], arbrst[wr_rresp_cnt[int_cntr_width-2:0]], arlen[wr_rresp_cnt[int_cntr_width-2:0]], arid[wr_rresp_cnt[int_cntr_width-2:0]], rresp, temp_rd_valid_bytes };
wr_rresp_cnt = wr_rresp_cnt + 1;
end
end
WAIT_RD_VALID : begin
rd_fifo_state = WAIT_RD_VALID;
rd_req = 0;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd_req) begin ///temp_dec == 2'b11) begin
RD_REQ_DDR = 1'b0;
RD_REQ_OCM = 1'b0;
invalid_rd_req = 0;
rd_fifo_state = RD_DATA_REQ;
end
end
endcase
end /// else
end /// always
/*--------------------------------------------------------------------------------*/
/* thread to fill in the AFI RD_FIFO */
reg[rd_afi_fifo_bits-1:0] temp_rd_data;//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
reg tmp_state;
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_wr_ptr = 0;
rcount = 0;
tmp_state = 0;
end else begin
case(tmp_state)
0 : begin
tmp_state = 0;
if(!temp_rd_intr_fifo_empty) begin
rd_intr_fifo.read_mem(temp_rd_data);
tmp_state = 1;
end
end
1 : begin
tmp_state = 1;
if(!rdfifo_full(temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1)) begin
read_fifo[rd_fifo_wr_ptr[int_cntr_width-2:0]] = temp_rd_data;
rd_fifo_wr_ptr = rd_fifo_wr_ptr + 1;
rcount = rcount + temp_rd_data[rd_afi_ln_msb:rd_afi_ln_lsb]+1; /// Burst length
tmp_state = 0;
end
end
endcase
end
end
/*--------------------------------------------------------------------------------*/
reg[max_burst_bytes_width:0] rd_v_b;
reg[rd_afi_fifo_bits-1:0] tmp_fifo_rd; /// Data, addr, size, burst, len, RID, RRESP,valid_bytes
reg[(data_bus_width*axi_burst_len)-1:0] temp_read_data;
reg[(axi_rsp_width*axi_burst_len)-1:0] temp_read_rsp;
/* Read Data Channel handshake */
always@(negedge S_RESETN or posedge S_ACLK)
begin
if(!S_RESETN)begin
rd_fifo_rd_ptr = 0;
rd_latency_count = get_rd_lat_number(1);
rd_delayed = 0;
rresp_time_cnt = 0;
rd_v_b = 0;
end else begin
if(arvalid_flag[rresp_time_cnt] && ((($time - arvalid_receive_time[rresp_time_cnt])/s_aclk_period) >= rd_latency_count)) begin
rd_delayed = 1;
end
if(!read_fifo_empty && rd_delayed)begin
rd_delayed = 0;
arvalid_flag[rresp_time_cnt] = 1'b0;
tmp_fifo_rd = read_fifo[rd_fifo_rd_ptr[int_cntr_width-2:0]];
rd_v_b = (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+1)*(2**tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb]);
temp_read_data = tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb];
if(tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb] === AXI_WRAP) begin
get_wrap_aligned_rd_data(aligned_rd_data, tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb], tmp_fifo_rd[rd_afi_data_msb : rd_afi_data_lsb], rd_v_b);
temp_read_data = aligned_rd_data;
end
temp_read_rsp = 0;
repeat(axi_burst_len) begin
temp_read_rsp = temp_read_rsp >> axi_rsp_width;
temp_read_rsp[(axi_rsp_width*axi_burst_len)-1:(axi_rsp_width*axi_burst_len)-axi_rsp_width] = tmp_fifo_rd[rd_afi_rsp_msb : rd_afi_rsp_lsb];
end
slave.SEND_READ_BURST_RESP_CTRL(tmp_fifo_rd[rd_afi_id_msb : rd_afi_id_lsb],
tmp_fifo_rd[rd_afi_addr_msb : rd_afi_addr_lsb],
tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb],
tmp_fifo_rd[rd_afi_siz_msb : rd_afi_siz_lsb],
tmp_fifo_rd[rd_afi_brst_msb : rd_afi_brst_lsb],
temp_read_data,
temp_read_rsp);
rcount = rcount - (tmp_fifo_rd[rd_afi_ln_msb : rd_afi_ln_lsb]+ 1) ;
rresp_time_cnt = rresp_time_cnt+1;
rd_latency_count = get_rd_lat_number(1);
rd_fifo_rd_ptr = rd_fifo_rd_ptr+1;
end
end /// else
end /// always
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_LP_V
`define SKY130_FD_SC_LP__O21BAI_LP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21bai_lp (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21bai_lp (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_LP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module Eblock(
input [0:31] R,
output [0:47] Rout
//, input CLK
);
assign Rout = {R[31], R[0], R[1], R[2], R[3], R[4], R[3], R[4], R[5], R[6], R[7], R[8], R[7], R[8], R[9], R[10], R[11], R[12], R[11], R[12], R[13], R[14], R[15], R[16], R[15], R[16], R[17], R[18], R[19], R[20], R[19], R[20], R[21], R[22], R[23], R[24], R[23], R[24], R[25], R[26], R[27], R[28], R[27], R[28], R[29], R[30], R[31], R[0]};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4bb (
VPWR,
VGND,
X ,
A_N ,
B_N ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
// Local signals
wire D nor0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_BEHAVIORAL_PP_V
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [7:0] featurebits,
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // want to access RAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output cx4_enable,
output cx4_vect_enable,
output r213f_enable,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4
;
wire [23:0] SRAM_SNES_ADDR;
/* Cx4 mapper:
- LoROM (extended to 00-7d, 80-ff)
- MMIO @ 6000-7fff
- SRAM @ 70-7d/80-ff:0000-7fff
*/
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
|(SNES_ADDR[22]));
assign IS_SAVERAM = |SAVERAM_MASK & (&SNES_ADDR[22:20] & ~SNES_ADDR[15] & (SNES_ADDR[19:16] < 4'b1110));
assign SRAM_SNES_ADDR = IS_SAVERAM
? (24'hE00000 | ({SNES_ADDR[19:16], SNES_ADDR[14:0]}
& SAVERAM_MASK))
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign IS_WRITABLE = IS_SAVERAM;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
wire msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign msu_enable = msu_enable_w;
wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011));
assign cx4_enable = cx4_enable_w;
assign cx4_vect_enable = &SNES_ADDR[15:5];
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 9'h3f);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A5A);
assign branch1_enable = (SNES_ADDR == 24'h002A13);
assign branch2_enable = (SNES_ADDR == 24'h002A4D);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__TAP_FUNCTIONAL_PP_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__ISO0P_PP_BLACKBOX_V
/**
* iso0p: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0p (
X ,
A ,
SLEEP,
KAPWR,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_PP_BLACKBOX_V
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description: Phy layer SD host controller for 1 bit SD mode
* When the i_data_en signal goes high the core will read in the
* i_write_flag.
* Writing:
* If high then it will read in the i_data_h2s data until
* it reads i_data_count bytes from the host, each i_data_stb will tell
* the above phy to present a new byte to on the i_data_h2s register.
*
* Reading:
* read the number of bytes on i_data_count. when a new byte is finished
* the new byte will be on o_data_s2h.
*
* To activate a transaction set i_en along with i_write_flag to 1 for write
* or 0 for read, the core will strobe in/out data on it's own, it's
* up to the above layer to make sure there is enough data or space
* available, the maximum space should be 2048 bytes. when a transaction is
* finished the o_finished flag will go high, the controlling core must
* de-assert i_en in order to reset the core to get ready for new
* transactions. This signal will go high for one clock cycle if the host
* de-asserts i_en before a transaction is finished.
*
* clk: sdio_clk
* rst: reset core
* i_en: Enable a data transaction
* o_finished: transaction is finished (de-assert i_en to reset)
* i_write_flag: 1 = Write, 0 = Read
* i_data_h2s: Data from host to SD card
* o_data_h2s: Data from SD card to host
* i_data_count: Number of bytes to read/write
* o_data_stb: request or strobe in a byte
* o_crc_err: CRC error occured during read
* io_sd_data: raw sdio data bits
*
* Changes:
* 2015.08.24: Initial commit
*/
module sd_sd1_phy (
input clk,
input rst,
input i_en,
output reg o_finished,
input i_write_flag,
output reg o_crc_err, //Detected a CRC error during read
output reg o_data_stb,
input [11:0] i_data_count,
input [7:0] i_data_h2s,
output reg [7:0] o_data_s2h,
inout [7:0] io_sd_data
);
//local parameters
localparam IDLE = 4'h0;
localparam WRITE_START = 4'h1;
localparam WRITE = 4'h2;
localparam WRITE_CRC = 4'h3;
localparam WRITE_FINISHED= 4'h4;
localparam READ_START = 4'h5;
localparam READ = 4'h6;
localparam READ_CRC = 4'h7;
localparam FINISHED = 4'h8;
//registes/wires
reg [3:0] state;
reg [7:0] sd_data;
wire sd_data_bit;
wire [15:0] gen_crc;
reg [15:0] crc;
reg crc_rst;
reg [3:0] bit_count; //Need 4 bits to cound the CRC value
wire sd_bit;
reg r_sd_bit;
//submodules
sd_crc_16 (
.clk (clk ),
.rst (crc_rst ),
.en (crc_en ),
//.bitval (r_sd_bit ), //Shoud this be registered?
.bitval (sd_bit ),
.crc (gen_crc )
);
//asynchronous logic
assign sd_data_bit = (state == WRITE_START) ? 1'b0 :
(state == WRITE_CRC) ? crc[15] :
(state == WRITE_FINISHED) ? 1'b1 :
sd_data[7];
assign io_sd_data = (i_write_flag) ? {7'b0, sd_data_bit}, 8'hZZ;
assign sd_bit = io_sd_data[0];
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
o_data_stb <= 0;
if (rst) begin
sd_data <= 0;
state <= IDLE;
crc_rst <= 1;
crc_en <= 0;
o_finished <= 0;
bit_count <= 0;
data_count <= 0;
o_crc_err <= 0;
end
else begin
case (state)
IDLE: begin
crc_en <= 0;
crc_rst <= 1;
o_finished <= 0;
bit_count <= 0;
data_count <= 0;
o_crc_err <= 0;
if (i_en) begin
crc_rst <= 0;
if(i_write_flag) begin
state <= WRITE_START;
end
else begin
state <= READ_START;
end
end
end
WRITE_START: begin
//Set the data bit low to initiate a transaction
//The assignment statement above will take care of setting data bit to 0
state <= WRITE;
crc_en <= 1;
sd_data <= i_data_h2s;
end
WRITE: begin
sd_data <= {sd_data[6:0], 0};
bit_count <= bit_count + 1;
if (bit_count >= 7) begin
if (data_count < i_data_count) begin
o_data_stb <= 1;
bit_count <= 0;
data_count <= data_count + 1;
sd_data <= i_data_h2s;
end
else begin
state <= WRITE_CRC;
crc_en <= 0;
crc <= gen_crc;
end
end
end
WRITE_CRC: begin
crc <= {crc[14:0], sd_bit};
bit_count <= bit_count + 1;
if (bit_count >= 15) begin
state <= WRITE_FINISHED;
end
end
WRITE_FINISHED: begin
//Pass through, assign statement will set the value to 1
state <= FINISHED;
end
READ_START: begin
//Wait for data bit to go low
if (!sd_bit) begin
crc_en <= 1;
state <= READ;
end
end
READ: begin
//Shift the bits in
o_data_s2h <= {o_data_sh[6:0], sd_bit};
bit_count <= bit_count + bit_count + 8'h1;
if (bit_count >= 7) begin
//Finished reading a byte
o_data_stb <= 1; //Will this give me enough time for the new data to get clocked in?
bit_count <= 0;
if (data_count < i_data_count) begin
data_count <= data_count + 1;
end
else begin
//Finished reading all bytes
state <= READ_CRC;
end
end
end
READ_CRC: begin
crc_en <= 0; //XXX: should this be in the previous state??
crc <= {crc[14:0], sd_bit};
if (bit_count >= 15) begin
state <= FINISHED;
end
end
FINISHED: begin
o_finished <= 1;
if (crc != gen_crc) begin
o_crc_err <= 1;
end
if (!i_en) begin
o_finished <= 0;
state <= IDLE;
end
end
default: begin
end
endcase
r_sd_bt <= sd_bit;
end
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module bram_fifo #(
parameter BASEADDR = 32'h0000,
parameter HIGHADDR = 32'h0000,
parameter ABUSWIDTH = 32,
parameter BASEADDR_DATA = 32'h0000,
parameter HIGHADDR_DATA = 32'h0000,
parameter DEPTH = 32'h8000*8,
parameter FIFO_ALMOST_FULL_THRESHOLD = 95, // in percent
parameter FIFO_ALMOST_EMPTY_THRESHOLD = 5 // in percent
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire FIFO_READ_NEXT_OUT,
input wire FIFO_EMPTY_IN,
input wire [31:0] FIFO_DATA,
output wire FIFO_NOT_EMPTY,
output wire FIFO_FULL,
output wire FIFO_NEAR_FULL,
output wire FIFO_READ_ERROR
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip_control (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
wire IP_RD_DATA, IP_WR_DATA;
wire [31:0] IP_DATA_OUT_DATA, IP_DATA_IN_DATA;
bus_to_ip #(
.BASEADDR(BASEADDR_DATA),
.HIGHADDR(HIGHADDR_DATA) ,
.ABUSWIDTH(ABUSWIDTH),
.DBUSWIDTH(32)
) i_bus_to_ip_data (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD_DATA),
.IP_WR(IP_WR_DATA),
.IP_ADD(),
.IP_DATA_IN(IP_DATA_IN_DATA),
.IP_DATA_OUT(IP_DATA_OUT_DATA)
);
bram_fifo_core #(
.DEPTH(DEPTH),
.FIFO_ALMOST_FULL_THRESHOLD(FIFO_ALMOST_FULL_THRESHOLD),
.FIFO_ALMOST_EMPTY_THRESHOLD(FIFO_ALMOST_EMPTY_THRESHOLD),
.ABUSWIDTH(ABUSWIDTH)
) i_bram_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.BUS_RD_DATA(IP_RD_DATA),
.BUS_WR_DATA(IP_WR_DATA),
.BUS_DATA_IN_DATA(IP_DATA_IN_DATA),
.BUS_DATA_OUT_DATA(IP_DATA_OUT_DATA),
.FIFO_READ_NEXT_OUT(FIFO_READ_NEXT_OUT),
.FIFO_EMPTY_IN(FIFO_EMPTY_IN),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(FIFO_NOT_EMPTY),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
.FIFO_READ_ERROR(FIFO_READ_ERROR)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_SYMBOL_V
`define SKY130_FD_SC_MS__A32O_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_1_V
`define SKY130_FD_SC_MS__DLRBP_1_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlrbp_1 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_1_V
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// Basic reset synchronizer, w/ async assert and sync de-assert.
//
//---- Detailed Description ----------------------------------------------------
//
// See:
//
// C. Cummings, D. Mills, and S. Golson, “Asynchronous & synchronous reset
// design techniques - Part deux,” Synopsys User Group (SNUG), User papers,
// Boston, USA, Sept. 2003.
//
//------------------------------------------------------------------------------
`ifndef _ZL_RESET_SYNC_V_
`define _ZL_RESET_SYNC_V_
module zl_reset_sync
(
input clk,
input in_rst_n,
output out_rst_n
);
reg [1:0] ff;
always @(posedge clk or negedge in_rst_n) begin
if(!in_rst_n) begin
ff[1] <= 1'b0;
ff[0] <= 1'b0;
end
else begin
ff[1] <= 1'b1;
ff[0] <= ff[1];
end
end
assign out_rst_n = ff[0];
endmodule // zl_reset_sync
`endif // _ZL_RESET_SYNC_V_
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(** %\chapter{Some Quick Examples}% *)
(** I will start off by jumping right in to a fully worked set of examples, building certified compilers from increasingly complicated source languages to stack machines. We will meet a few useful tactics and see how they can be used in manual proofs, and we will also see how easily these proofs can be automated instead. This chapter is not meant to give full explanations of the features that are employed. Rather, it is meant more as an advertisement of what is possible. Later chapters will introduce all of the concepts in bottom-up fashion. In other words, it is expected that most readers will not understand what exactly is going on here, but I hope this demo will whet your appetite for the remaining chapters!
As always, you can step through the source file <<StackMachine.v>> for this chapter interactively in Proof General. Alternatively, to get a feel for the whole lifecycle of creating a Coq development, you can enter the pieces of source code in this chapter in a new <<.v>> file in an Emacs buffer. If you do the latter, include these three lines at the start of the file. *)
Require Import Bool Arith List CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* begin hide *)
(* begin thide *)
Definition bleh := app_assoc.
(* end thide *)
(* end hide *)
(** In general, similar commands will be hidden in the book rendering of each chapter's source code, so you will need to insert them in from-scratch replayings of the code that is presented. To be more specific, every chapter begins with the above three lines, with the import list tweaked as appropriate, considering which definitions the chapter uses. The second command above affects the default behavior of definitions regarding type inference, and the third allows for more concise pattern-matching syntax in Coq versions 8.5 and higher (having no effect in earlier versions). *)
(** * Arithmetic Expressions Over Natural Numbers *)
(** We will begin with that staple of compiler textbooks, arithmetic expressions over a single type of numbers. *)
(** ** Source Language *)
(** We begin with the syntax of the source language.%\index{Vernacular commands!Inductive}% *)
Inductive binop : Set := Plus | Times.
(** Our first line of Coq code should be unsurprising to ML and Haskell programmers. We define an %\index{algebraic datatypes}%algebraic datatype [binop] to stand for the binary operators of our source language. There are just two wrinkles compared to ML and Haskell. First, we use the keyword [Inductive], in place of <<data>>, <<datatype>>, or <<type>>. This is not just a trivial surface syntax difference; inductive types in Coq are much more expressive than garden variety algebraic datatypes, essentially enabling us to encode all of mathematics, though we begin humbly in this chapter. Second, there is the %\index{Gallina terms!Set}%[: Set] fragment, which declares that we are defining a datatype that should be thought of as a constituent of programs. Later, we will see other options for defining datatypes in the universe of proofs or in an infinite hierarchy of universes, encompassing both programs and proofs, that is useful in higher-order constructions. *)
Inductive exp : Set :=
| Const : nat -> exp
| Binop : binop -> exp -> exp -> exp.
(** Now we define the type of arithmetic expressions. We write that a constant may be built from one argument, a natural number; and a binary operation may be built from a choice of operator and two operand expressions.
A note for readers following along in the PDF version: %\index{coqdoc}%coqdoc supports pretty-printing of tokens in %\LaTeX{}%#LaTeX# or HTML. Where you see a right arrow character, the source contains the ASCII text <<->>>. Other examples of this substitution appearing in this chapter are a double right arrow for <<=>>>, the inverted %`%#'#A' symbol for <<forall>>, and the Cartesian product %`%#'#X' for <<*>>. When in doubt about the ASCII version of a symbol, you can consult the chapter source code.
%\medskip%
Now we are ready to say what programs in our expression language mean. We will do this by writing an %\index{interpreters}%interpreter that can be thought of as a trivial operational or denotational semantics. (If you are not familiar with these semantic techniques, no need to worry: we will stick to "common sense" constructions.)%\index{Vernacular commands!Definition}% *)
Definition binopDenote (b : binop) : nat -> nat -> nat :=
match b with
| Plus => plus
| Times => mult
end.
(** The meaning of a binary operator is a binary function over naturals, defined with pattern-matching notation analogous to the <<case>> and <<match>> of ML and Haskell, and referring to the functions [plus] and [mult] from the Coq standard library. The keyword [Definition] is Coq's all-purpose notation for binding a term of the programming language to a name, with some associated syntactic sugar, like the notation we see here for defining a function. That sugar could be expanded to yield this definition:
[[
Definition binopDenote : binop -> nat -> nat -> nat := fun (b : binop) =>
match b with
| Plus => plus
| Times => mult
end.
]]
In this example, we could also omit all of the type annotations, arriving at:
[[
Definition binopDenote := fun b =>
match b with
| Plus => plus
| Times => mult
end.
]]
Languages like Haskell and ML have a convenient%\index{principal types}\index{type inference}% _principal types_ property, which gives us strong guarantees about how effective type inference will be. Unfortunately, Coq's type system is so expressive that any kind of "complete" type inference is impossible, and the task even seems to be hard in practice. Nonetheless, Coq includes some very helpful heuristics, many of them copying the workings of Haskell and ML type-checkers for programs that fall in simple fragments of Coq's language.
This is as good a time as any to mention the profusion of different languages associated with Coq. The theoretical foundation of Coq is a formal system called the%\index{Calculus of Inductive Constructions}\index{CIC|see{Calculus of Inductive Constructions}}% _Calculus of Inductive Constructions_ (CIC)%~\cite{CIC}%, which is an extension of the older%\index{Calculus of Constructions}\index{CoC|see{Calculus of Constructions}}% _Calculus of Constructions_ (CoC)%~\cite{CoC}%. CIC is quite a spartan foundation, which is helpful for proving metatheory but not so helpful for real development. Still, it is nice to know that it has been proved that CIC enjoys properties like%\index{strong normalization}% _strong normalization_ %\cite{CIC}%, meaning that every program (and, more importantly, every proof term) terminates; and%\index{relative consistency}% _relative consistency_ %\cite{SetsInTypes}% with systems like versions of %\index{Zermelo-Fraenkel set theory}%Zermelo-Fraenkel set theory, which roughly means that you can believe that Coq proofs mean that the corresponding propositions are "really true," if you believe in set theory.
Coq is actually based on an extension of CIC called %\index{Gallina}%Gallina. The text after the [:=] and before the period in the last code example is a term of Gallina. Gallina includes several useful features that must be considered as extensions to CIC. The important metatheorems about CIC have not been extended to the full breadth of the features that go beyond the formalized language, but most Coq users do not seem to lose much sleep over this omission.
Next, there is %\index{Ltac}%Ltac, Coq's domain-specific language for writing proofs and decision procedures. We will see some basic examples of Ltac later in this chapter, and much of this book is devoted to more involved Ltac examples.
Finally, commands like [Inductive] and [Definition] are part of %\index{Vernacular commands}%the Vernacular, which includes all sorts of useful queries and requests to the Coq system. Every Coq source file is a series of vernacular commands, where many command forms take arguments that are Gallina or Ltac programs. (Actually, Coq source files are more like _trees_ of vernacular commands, thanks to various nested scoping constructs.)
%\medskip%
We can give a simple definition of the meaning of an expression:%\index{Vernacular commands!Fixpoint}% *)
Fixpoint expDenote (e : exp) : nat :=
match e with
| Const n => n
| Binop b e1 e2 => (binopDenote b) (expDenote e1) (expDenote e2)
end.
(** We declare explicitly that this is a recursive definition, using the keyword [Fixpoint]. The rest should be old hat for functional programmers. *)
(** It is convenient to be able to test definitions before starting to prove things about them. We can verify that our semantics is sensible by evaluating some sample uses, using the command %\index{Vernacular commands!Eval}%[Eval]. This command takes an argument expressing a%\index{reduction strategy}% _reduction strategy_, or an "order of evaluation." Unlike with ML, which hardcodes an _eager_ reduction strategy, or Haskell, which hardcodes a _lazy_ strategy, in Coq we are free to choose between these and many other orders of evaluation, because all Coq programs terminate. In fact, Coq silently checked %\index{termination checking}%termination of our [Fixpoint] definition above, using a simple heuristic based on monotonically decreasing size of arguments across recursive calls. Specifically, recursive calls must be made on arguments that were pulled out of the original recursive argument with [match] expressions. (In Chapter 7, we will see some ways of getting around this restriction, though simply removing the restriction would leave Coq useless as a theorem proving tool, for reasons we will start to learn about in the next chapter.)
To return to our test evaluations, we run the [Eval] command using the [simpl] evaluation strategy, whose definition is best postponed until we have learned more about Coq's foundations, but which usually gets the job done. *)
Eval simpl in expDenote (Const 42).
(** [= 42 : nat] *)
Eval simpl in expDenote (Binop Plus (Const 3) (Const 2)).
(** [= 4 : nat] *)
Eval simpl in expDenote (Binop Times (Binop Plus (Const 2) (Const 2)) (Const 7)).
(** [= 28 : nat] *)
(** %\smallskip{}%Nothing too surprising goes on here, so we are ready to move on to the target language of our compiler. *)
(** ** Target Language *)
(** We will compile our source programs onto a simple stack machine, whose syntax is: *)
Inductive instr : Set :=
| iConst : nat -> instr
| iBinop : binop -> instr.
Definition prog := list instr.
Definition stack := list nat.
(** An instruction either pushes a constant onto the stack or pops two arguments, applies a binary operator to them, and pushes the result onto the stack. A program is a list of instructions, and a stack is a list of natural numbers.
We can give instructions meanings as functions from stacks to optional stacks, where running an instruction results in [None] in case of a stack underflow and results in [Some s'] when the result of execution is the new stack [s']. %\index{Gallina operators!::}%The infix operator [::] is "list cons" from the Coq standard library.%\index{Gallina terms!option}% *)
Definition instrDenote (i : instr) (s : stack) : option stack :=
match i with
| iConst n => Some (n :: s)
| iBinop b =>
match s with
| arg1 :: arg2 :: s' => Some ((binopDenote b) arg1 arg2 :: s')
| _ => None
end
end.
(** With [instrDenote] defined, it is easy to define a function [progDenote], which iterates application of [instrDenote] through a whole program. *)
Fixpoint progDenote (p : prog) (s : stack) : option stack :=
match p with
| nil => Some s
| i :: p' =>
match instrDenote i s with
| None => None
| Some s' => progDenote p' s'
end
end.
(** With the two programming languages defined, we can turn to the compiler definition. *)
(** ** Translation *)
(** Our compiler itself is now unsurprising. The list concatenation operator %\index{Gallina operators!++}\coqdocnotation{%#<tt>#++#</tt>#%}% comes from the Coq standard library. *)
Fixpoint compile (e : exp) : prog :=
match e with
| Const n => iConst n :: nil
| Binop b e1 e2 => compile e2 ++ compile e1 ++ iBinop b :: nil
end.
(** Before we set about proving that this compiler is correct, we can try a few test runs, using our sample programs from earlier. *)
Eval simpl in compile (Const 42).
(** [= iConst 42 :: nil : prog] *)
Eval simpl in compile (Binop Plus (Const 2) (Const 2)).
(** [= iConst 2 :: iConst 2 :: iBinop Plus :: nil : prog] *)
Eval simpl in compile (Binop Times (Binop Plus (Const 2) (Const 2)) (Const 7)).
(** [= iConst 7 :: iConst 2 :: iConst 2 :: iBinop Plus :: iBinop Times :: nil : prog] *)
(** %\smallskip{}%We can also run our compiled programs and check that they give the right results. *)
Eval simpl in progDenote (compile (Const 42)) nil.
(** [= Some (42 :: nil) : option stack] *)
Eval simpl in progDenote (compile (Binop Plus (Const 2) (Const 2))) nil.
(** [= Some (4 :: nil) : option stack] *)
Eval simpl in progDenote (compile (Binop Times (Binop Plus (Const 2) (Const 2))
(Const 7))) nil.
(** [= Some (28 :: nil) : option stack] *)
(** %\smallskip{}%So far so good, but how can we be sure the compiler operates correctly for _all_ input programs? *)
(** ** Translation Correctness *)
(** We are ready to prove that our compiler is implemented correctly. We can use a new vernacular command [Theorem] to start a correctness proof, in terms of the semantics we defined earlier:%\index{Vernacular commands!Theorem}% *)
Theorem compile_correct : forall e,
progDenote (compile e) nil = Some (expDenote e :: nil).
(* begin thide *)
(** Though a pencil-and-paper proof might clock out at this point, writing "by a routine induction on [e]," it turns out not to make sense to attack this proof directly. We need to use the standard trick of%\index{strengthening the induction hypothesis}% _strengthening the induction hypothesis_. We do that by proving an auxiliary lemma, using the command [Lemma] that is a synonym for [Theorem], conventionally used for less important theorems that appear in the proofs of primary theorems.%\index{Vernacular commands!Lemma}% *)
Abort.
Lemma compile_correct' : forall e p s,
progDenote (compile e ++ p) s = progDenote p (expDenote e :: s).
(** After the period in the [Lemma] command, we are in%\index{interactive proof-editing mode}% _the interactive proof-editing mode_. We find ourselves staring at this ominous screen of text:
[[
1 subgoal
============================
forall (e : exp) (p : list instr) (s : stack),
progDenote (compile e ++ p) s = progDenote p (expDenote e :: s)
]]
Coq seems to be restating the lemma for us. What we are seeing is a limited case of a more general protocol for describing where we are in a proof. We are told that we have a single subgoal. In general, during a proof, we can have many pending %\index{subgoals}%subgoals, each of which is a logical proposition to prove. Subgoals can be proved in any order, but it usually works best to prove them in the order that Coq chooses.
Next in the output, we see our single subgoal described in full detail. There is a double-dashed line, above which would be our free variables and %\index{hypotheses}%hypotheses, if we had any. Below the line is the %\index{conclusion}%conclusion, which, in general, is to be proved from the hypotheses.
We manipulate the proof state by running commands called%\index{tactics}% _tactics_. Let us start out by running one of the most important tactics:%\index{tactics!induction}%
*)
induction e.
(** We declare that this proof will proceed by induction on the structure of the expression [e]. This swaps out our initial subgoal for two new subgoals, one for each case of the inductive proof:
[[
2 subgoals
n : nat
============================
forall (s : stack) (p : list instr),
progDenote (compile (Const n) ++ p) s =
progDenote p (expDenote (Const n) :: s)
subgoal 2 is
forall (s : stack) (p : list instr),
progDenote (compile (Binop b e1 e2) ++ p) s =
progDenote p (expDenote (Binop b e1 e2) :: s)
]]
The first and current subgoal is displayed with the double-dashed line below free variables and hypotheses, while later subgoals are only summarized with their conclusions. We see an example of a %\index{free variable}%free variable in the first subgoal; [n] is a free variable of type [nat]. The conclusion is the original theorem statement where [e] has been replaced by [Const n]. In a similar manner, the second case has [e] replaced by a generalized invocation of the [Binop] expression constructor. We can see that proving both cases corresponds to a standard proof by %\index{structural induction}%structural induction.
We begin the first case with another very common tactic.%\index{tactics!intros}%
*)
intros.
(** The current subgoal changes to:
[[
n : nat
s : stack
p : list instr
============================
progDenote (compile (Const n) ++ p) s =
progDenote p (expDenote (Const n) :: s)
]]
We see that [intros] changes [forall]-bound variables at the beginning of a goal into free variables.
To progress further, we need to use the definitions of some of the functions appearing in the goal. The [unfold] tactic replaces an identifier with its definition.%\index{tactics!unfold}%
*)
unfold compile.
(** [[
n : nat
s : stack
p : list instr
============================
progDenote ((iConst n :: nil) ++ p) s =
progDenote p (expDenote (Const n) :: s)
]]
*)
unfold expDenote.
(** [[
n : nat
s : stack
p : list instr
============================
progDenote ((iConst n :: nil) ++ p) s = progDenote p (n :: s)
]]
We only need to unfold the first occurrence of [progDenote] to prove the goal. An [at] clause used with [unfold] specifies a particular occurrence of an identifier to unfold, where we count occurrences from left to right.%\index{tactics!unfold}% *)
unfold progDenote at 1.
(** [[
n : nat
s : stack
p : list instr
============================
(fix progDenote (p0 : prog) (s0 : stack) {struct p0} :
option stack :=
match p0 with
| nil => Some s0
| i :: p' =>
match instrDenote i s0 with
| Some s' => progDenote p' s'
| None => None (A:=stack)
end
end) ((iConst n :: nil) ++ p) s =
progDenote p (n :: s)
]]
This last [unfold] has left us with an anonymous recursive definition of [progDenote] (similarly to how [fun] or "lambda" constructs in general allow anonymous non-recursive functions), which will generally happen when unfolding recursive definitions. Note that Coq has automatically renamed the [fix] arguments [p] and [s] to [p0] and [s0], to avoid clashes with our local free variables. There is also a subterm [None (A:=stack)], which has an annotation specifying that the type of the term ought to be [option stack]. This is phrased as an explicit instantiation of a named type parameter [A] from the definition of [option].
Fortunately, in this case, we can eliminate the complications of anonymous recursion right away, since the structure of the argument ([iConst n :: nil) ++ p] is known, allowing us to simplify the internal pattern match with the [simpl] tactic, which applies the same reduction strategy that we used earlier with [Eval] (and whose details we still postpone).%\index{tactics!simpl}%
*)
simpl.
(** [[
n : nat
s : stack
p : list instr
============================
(fix progDenote (p0 : prog) (s0 : stack) {struct p0} :
option stack :=
match p0 with
| nil => Some s0
| i :: p' =>
match instrDenote i s0 with
| Some s' => progDenote p' s'
| None => None (A:=stack)
end
end) p (n :: s) = progDenote p (n :: s)
]]
Now we can unexpand the definition of [progDenote]:%\index{tactics!fold}%
*)
fold progDenote.
(** [[
n : nat
s : stack
p : list instr
============================
progDenote p (n :: s) = progDenote p (n :: s)
]]
It looks like we are at the end of this case, since we have a trivial equality. Indeed, a single tactic finishes us off:%\index{tactics!reflexivity}%
*)
reflexivity.
(** On to the second inductive case:
[[
b : binop
e1 : exp
IHe1 : forall (s : stack) (p : list instr),
progDenote (compile e1 ++ p) s = progDenote p (expDenote e1 :: s)
e2 : exp
IHe2 : forall (s : stack) (p : list instr),
progDenote (compile e2 ++ p) s = progDenote p (expDenote e2 :: s)
============================
forall (s : stack) (p : list instr),
progDenote (compile (Binop b e1 e2) ++ p) s =
progDenote p (expDenote (Binop b e1 e2) :: s)
]]
We see our first example of %\index{hypotheses}%hypotheses above the double-dashed line. They are the inductive hypotheses [IHe1] and [IHe2] corresponding to the subterms [e1] and [e2], respectively.
We start out the same way as before, introducing new free variables and unfolding and folding the appropriate definitions. The seemingly frivolous [unfold]/[fold] pairs are actually accomplishing useful work, because [unfold] will sometimes perform easy simplifications. %\index{tactics!intros}\index{tactics!unfold}\index{tactics!fold}% *)
intros.
unfold compile.
fold compile.
unfold expDenote.
fold expDenote.
(** Now we arrive at a point where the tactics we have seen so far are insufficient. No further definition unfoldings get us anywhere, so we will need to try something different.
[[
b : binop
e1 : exp
IHe1 : forall (s : stack) (p : list instr),
progDenote (compile e1 ++ p) s = progDenote p (expDenote e1 :: s)
e2 : exp
IHe2 : forall (s : stack) (p : list instr),
progDenote (compile e2 ++ p) s = progDenote p (expDenote e2 :: s)
s : stack
p : list instr
============================
progDenote ((compile e2 ++ compile e1 ++ iBinop b :: nil) ++ p) s =
progDenote p (binopDenote b (expDenote e1) (expDenote e2) :: s)
]]
What we need is the associative law of list concatenation, which is available as a theorem [app_assoc_reverse] in the standard library.%\index{Vernacular commands!Check}% (Here and elsewhere, it is possible to tell the difference between inputs and outputs to Coq by periods at the ends of the inputs.) *)
Check app_assoc_reverse.
(** %\vspace{-.15in}%[[
app_assoc_reverse
: forall (A : Type) (l m n : list A), (l ++ m) ++ n = l ++ m ++ n
]]
If we did not already know the name of the theorem, we could use the %\index{Vernacular commands!SearchRewrite}%[SearchRewrite] command to find it, based on a pattern that we would like to rewrite: *)
SearchRewrite ((_ ++ _) ++ _).
(** %\vspace{-.15in}%[[
app_assoc_reverse:
forall (A : Type) (l m n : list A), (l ++ m) ++ n = l ++ m ++ n
]]
%\vspace{-.25in}%
[[
app_assoc: forall (A : Type) (l m n : list A), l ++ m ++ n = (l ++ m) ++ n
]]
We use [app_assoc_reverse] to perform a rewrite: %\index{tactics!rewrite}% *)
rewrite app_assoc_reverse.
(** %\noindent{}%changing the conclusion to:
[[
progDenote (compile e2 ++ (compile e1 ++ iBinop b :: nil) ++ p) s =
progDenote p (binopDenote b (expDenote e1) (expDenote e2) :: s)
]]
Now we can notice that the lefthand side of the equality matches the lefthand side of the second inductive hypothesis, so we can rewrite with that hypothesis, too.%\index{tactics!rewrite}% *)
rewrite IHe2.
(** [[
progDenote ((compile e1 ++ iBinop b :: nil) ++ p) (expDenote e2 :: s) =
progDenote p (binopDenote b (expDenote e1) (expDenote e2) :: s)
]]
The same process lets us apply the remaining hypothesis.%\index{tactics!rewrite}% *)
rewrite app_assoc_reverse.
rewrite IHe1.
(** [[
progDenote ((iBinop b :: nil) ++ p) (expDenote e1 :: expDenote e2 :: s) =
progDenote p (binopDenote b (expDenote e1) (expDenote e2) :: s)
]]
Now we can apply a similar sequence of tactics to the one that ended the proof of the first case.%\index{tactics!unfold}\index{tactics!simpl}\index{tactics!fold}\index{tactics!reflexivity}%
*)
unfold progDenote at 1.
simpl.
fold progDenote.
reflexivity.
(** And the proof is completed, as indicated by the message: *)
(**
<<
Proof completed.
>>
*)
(** And there lies our first proof. Already, even for simple theorems like this, the final proof script is unstructured and not very enlightening to readers. If we extend this approach to more serious theorems, we arrive at the unreadable proof scripts that are the favorite complaints of opponents of tactic-based proving. Fortunately, Coq has rich support for scripted automation, and we can take advantage of such a scripted tactic (defined elsewhere) to make short work of this lemma. We abort the old proof attempt and start again.%\index{Vernacular commands!Abort}%
*)
Abort.
(** %\index{tactics!induction}\index{tactics!crush}% *)
Lemma compile_correct' : forall e s p,
progDenote (compile e ++ p) s = progDenote p (expDenote e :: s).
induction e; crush.
Qed.
(** We need only to state the basic inductive proof scheme and call a tactic that automates the tedious reasoning in between. In contrast to the period tactic terminator from our last proof, the %\index{tactics!semicolon}%semicolon tactic separator supports structured, compositional proofs. The tactic [t1; t2] has the effect of running [t1] and then running [t2] on each remaining subgoal. The semicolon is one of the most fundamental building blocks of effective proof automation. The period terminator is very useful for exploratory proving, where you need to see intermediate proof states, but final proofs of any serious complexity should have just one period, terminating a single compound tactic that probably uses semicolons.
The [crush] tactic comes from the library associated with this book and is not part of the Coq standard library. The book's library contains a number of other tactics that are especially helpful in highly automated proofs.
The %\index{Vernacular commands!Qed}%[Qed] command checks that the proof is finished and, if so, saves it. The tactic commands we have written above are an example of a _proof script_, or a series of Ltac programs; while [Qed] uses the result of the script to generate a _proof term_, a well-typed term of Gallina. To believe that a theorem is true, we only need to trust that the (relatively simple) checker for proof terms is correct; the use of proof scripts is immaterial. Part I of this book will introduce the principles behind encoding all proofs as terms of Gallina.
The proof of our main theorem is now easy. We prove it with four period-terminated tactics, though separating them with semicolons would work as well; the version here is easier to step through.%\index{tactics!intros}% *)
Theorem compile_correct : forall e, progDenote (compile e) nil = Some (expDenote e :: nil).
intros.
(** [[
e : exp
============================
progDenote (compile e) nil = Some (expDenote e :: nil)
]]
At this point, we want to massage the lefthand side to match the statement of [compile_correct']. A theorem from the standard library is useful: *)
Check app_nil_end.
(** [[
app_nil_end
: forall (A : Type) (l : list A), l = l ++ nil
]]
%\index{tactics!rewrite}% *)
rewrite (app_nil_end (compile e)).
(** This time, we explicitly specify the value of the variable [l] from the theorem statement, since multiple expressions of list type appear in the conclusion. The [rewrite] tactic might choose the wrong place to rewrite if we did not specify which we want.
[[
e : exp
============================
progDenote (compile e ++ nil) nil = Some (expDenote e :: nil)
]]
Now we can apply the lemma.%\index{tactics!rewrite}% *)
rewrite compile_correct'.
(** [[
e : exp
============================
progDenote nil (expDenote e :: nil) = Some (expDenote e :: nil)
]]
We are almost done. The lefthand and righthand sides can be seen to match by simple symbolic evaluation. That means we are in luck, because Coq identifies any pair of terms as equal whenever they normalize to the same result by symbolic evaluation. By the definition of [progDenote], that is the case here, but we do not need to worry about such details. A simple invocation of %\index{tactics!reflexivity}%[reflexivity] does the normalization and checks that the two results are syntactically equal.%\index{tactics!reflexivity}% *)
reflexivity.
Qed.
(* end thide *)
(** This proof can be shortened and automated, but we leave that task as an exercise for the reader. *)
(** * Typed Expressions *)
(** In this section, we will build on the initial example by adding additional expression forms that depend on static typing of terms for safety. *)
(** ** Source Language *)
(** We define a trivial language of types to classify our expressions: *)
Inductive type : Set := Nat | Bool.
(** Like most programming languages, Coq uses case-sensitive variable names, so that our user-defined type [type] is distinct from the [Type] keyword that we have already seen appear in the statement of a polymorphic theorem (and that we will meet in more detail later), and our constructor names [Nat] and [Bool] are distinct from the types [nat] and [bool] in the standard library.
Now we define an expanded set of binary operators. *)
Inductive tbinop : type -> type -> type -> Set :=
| TPlus : tbinop Nat Nat Nat
| TTimes : tbinop Nat Nat Nat
| TEq : forall t, tbinop t t Bool
| TLt : tbinop Nat Nat Bool.
(** The definition of [tbinop] is different from [binop] in an important way. Where we declared that [binop] has type [Set], here we declare that [tbinop] has type [type -> type -> type -> Set]. We define [tbinop] as an _indexed type family_. Indexed inductive types are at the heart of Coq's expressive power; almost everything else of interest is defined in terms of them.
The intuitive explanation of [tbinop] is that a [tbinop t1 t2 t] is a binary operator whose operands should have types [t1] and [t2], and whose result has type [t]. For instance, constructor [TLt] (for less-than comparison of numbers) is assigned type [tbinop Nat Nat Bool], meaning the operator's arguments are naturals and its result is Boolean. The type of [TEq] introduces a small bit of additional complication via polymorphism: we want to allow equality comparison of any two values of any type, as long as they have the _same_ type.
ML and Haskell have indexed algebraic datatypes. For instance, their list types are indexed by the type of data that the list carries. However, compared to Coq, ML and Haskell 98 place two important restrictions on datatype definitions.
First, the indices of the range of each data constructor must be type variables bound at the top level of the datatype definition. There is no way to do what we did here, where we, for instance, say that [TPlus] is a constructor building a [tbinop] whose indices are all fixed at [Nat]. %\index{generalized algebraic datatypes}\index{GADTs|see{generalized algebraic datatypes}}% _Generalized algebraic datatypes_ (GADTs)%~\cite{GADT}% are a popular feature in %\index{GHC Haskell}%GHC Haskell, OCaml 4, and other languages that removes this first restriction.
The second restriction is not lifted by GADTs. In ML and Haskell, indices of types must be types and may not be _expressions_. In Coq, types may be indexed by arbitrary Gallina terms. Type indices can live in the same universe as programs, and we can compute with them just like regular programs. Haskell supports a hobbled form of computation in type indices based on %\index{Haskell}%multi-parameter type classes, and recent extensions like type functions bring Haskell programming even closer to "real" functional programming with types, but, without dependent typing, there must always be a gap between how one programs with types and how one programs normally.
*)
(** We can define a similar type family for typed expressions, where a term of type [texp t] can be assigned object language type [t]. (It is conventional in the world of interactive theorem proving to call the language of the proof assistant the%\index{meta language}% _meta language_ and a language being formalized the%\index{object language}% _object language_.) *)
Inductive texp : type -> Set :=
| TNConst : nat -> texp Nat
| TBConst : bool -> texp Bool
| TBinop : forall t1 t2 t, tbinop t1 t2 t -> texp t1 -> texp t2 -> texp t.
(** Thanks to our use of dependent types, every well-typed [texp] represents a well-typed source expression, by construction. This turns out to be very convenient for many things we might want to do with expressions. For instance, it is easy to adapt our interpreter approach to defining semantics. We start by defining a function mapping the types of our object language into Coq types: *)
Definition typeDenote (t : type) : Set :=
match t with
| Nat => nat
| Bool => bool
end.
(** It can take a few moments to come to terms with the fact that [Set], the type of types of programs, is itself a first-class type, and that we can write functions that return [Set]s. Past that wrinkle, the definition of [typeDenote] is trivial, relying on the [nat] and [bool] types from the Coq standard library. We can interpret binary operators by relying on standard-library equality test functions [eqb] and [beq_nat] for Booleans and naturals, respectively, along with a less-than test [leb]: *)
Definition tbinopDenote arg1 arg2 res (b : tbinop arg1 arg2 res)
: typeDenote arg1 -> typeDenote arg2 -> typeDenote res :=
match b with
| TPlus => plus
| TTimes => mult
| TEq Nat => beq_nat
| TEq Bool => eqb
| TLt => leb
end.
(** This function has just a few differences from the denotation functions we saw earlier. First, [tbinop] is an indexed type, so its indices become additional arguments to [tbinopDenote]. Second, we need to perform a genuine%\index{dependent pattern matching}% _dependent pattern match_, where the necessary _type_ of each case body depends on the _value_ that has been matched. At this early stage, we will not go into detail on the many subtle aspects of Gallina that support dependent pattern-matching, but the subject is central to Part II of the book.
The same tricks suffice to define an expression denotation function in an unsurprising way. Note that the [type] arguments to the [TBinop] constructor must be included explicitly in pattern-matching, but here we write underscores because we do not need to refer to those arguments directly. *)
Fixpoint texpDenote t (e : texp t) : typeDenote t :=
match e with
| TNConst n => n
| TBConst b => b
| TBinop _ _ _ b e1 e2 => (tbinopDenote b) (texpDenote e1) (texpDenote e2)
end.
(** We can evaluate a few example programs to convince ourselves that this semantics is correct. *)
Eval simpl in texpDenote (TNConst 42).
(** [= 42 : typeDenote Nat] *)
(* begin hide *)
Eval simpl in texpDenote (TBConst false).
(* end hide *)
Eval simpl in texpDenote (TBConst true).
(** [= true : typeDenote Bool] *)
Eval simpl in texpDenote (TBinop TTimes (TBinop TPlus (TNConst 2) (TNConst 2))
(TNConst 7)).
(** [= 28 : typeDenote Nat] *)
Eval simpl in texpDenote (TBinop (TEq Nat) (TBinop TPlus (TNConst 2) (TNConst 2))
(TNConst 7)).
(** [= false : typeDenote Bool] *)
Eval simpl in texpDenote (TBinop TLt (TBinop TPlus (TNConst 2) (TNConst 2))
(TNConst 7)).
(** [= true : typeDenote Bool] *)
(** %\smallskip{}%Now we are ready to define a suitable stack machine target for compilation. *)
(** ** Target Language *)
(** In the example of the untyped language, stack machine programs could encounter stack underflows and "get stuck." This was unfortunate, since we had to deal with this complication even though we proved that our compiler never produced underflowing programs. We could have used dependent types to force all stack machine programs to be underflow-free.
For our new languages, besides underflow, we also have the problem of stack slots with naturals instead of bools or vice versa. This time, we will use indexed typed families to avoid the need to reason about potential failures.
We start by defining stack types, which classify sets of possible stacks. *)
Definition tstack := list type.
(** Any stack classified by a [tstack] must have exactly as many elements, and each stack element must have the type found in the same position of the stack type.
We can define instructions in terms of stack types, where every instruction's type tells us what initial stack type it expects and what final stack type it will produce. *)
Inductive tinstr : tstack -> tstack -> Set :=
| TiNConst : forall s, nat -> tinstr s (Nat :: s)
| TiBConst : forall s, bool -> tinstr s (Bool :: s)
| TiBinop : forall arg1 arg2 res s,
tbinop arg1 arg2 res
-> tinstr (arg1 :: arg2 :: s) (res :: s).
(** Stack machine programs must be a similar inductive family, since, if we again used the [list] type family, we would not be able to guarantee that intermediate stack types match within a program. *)
Inductive tprog : tstack -> tstack -> Set :=
| TNil : forall s, tprog s s
| TCons : forall s1 s2 s3,
tinstr s1 s2
-> tprog s2 s3
-> tprog s1 s3.
(** Now, to define the semantics of our new target language, we need a representation for stacks at runtime. We will again take advantage of type information to define types of value stacks that, by construction, contain the right number and types of elements. *)
Fixpoint vstack (ts : tstack) : Set :=
match ts with
| nil => unit
| t :: ts' => typeDenote t * vstack ts'
end%type.
(** This is another [Set]-valued function. This time it is recursive, which is perfectly valid, since [Set] is not treated specially in determining which functions may be written. We say that the value stack of an empty stack type is any value of type [unit], which has just a single value, [tt]. A nonempty stack type leads to a value stack that is a pair, whose first element has the proper type and whose second element follows the representation for the remainder of the stack type. We write [%]%\index{notation scopes}\coqdocvar{%#<tt>#type#</tt>#%}% as an instruction to Coq's extensible parser. In particular, this directive applies to the whole [match] expression, which we ask to be parsed as though it were a type, so that the operator [*] is interpreted as Cartesian product instead of, say, multiplication. (Note that this use of %\coqdocvar{%#<tt>#type#</tt>#%}% has no connection to the inductive type [type] that we have defined.)
This idea of programming with types can take a while to internalize, but it enables a very simple definition of instruction denotation. Our definition is like what you might expect from a Lisp-like version of ML that ignored type information. Nonetheless, the fact that [tinstrDenote] passes the type-checker guarantees that our stack machine programs can never go wrong. We use a special form of [let] to destructure a multi-level tuple. *)
Definition tinstrDenote ts ts' (i : tinstr ts ts') : vstack ts -> vstack ts' :=
match i with
| TiNConst _ n => fun s => (n, s)
| TiBConst _ b => fun s => (b, s)
| TiBinop _ _ _ _ b => fun s =>
let '(arg1, (arg2, s')) := s in
((tbinopDenote b) arg1 arg2, s')
end.
(** Why do we choose to use an anonymous function to bind the initial stack in every case of the [match]? Consider this well-intentioned but invalid alternative version:
[[
Definition tinstrDenote ts ts' (i : tinstr ts ts') (s : vstack ts) : vstack ts' :=
match i with
| TiNConst _ n => (n, s)
| TiBConst _ b => (b, s)
| TiBinop _ _ _ _ b =>
let '(arg1, (arg2, s')) := s in
((tbinopDenote b) arg1 arg2, s')
end.
]]
The Coq type checker complains that:
<<
The term "(n, s)" has type "(nat * vstack ts)%type"
while it is expected to have type "vstack ?119".
>>
This and other mysteries of Coq dependent typing we postpone until Part II of the book. The upshot of our later discussion is that it is often useful to push inside of [match] branches those function parameters whose types depend on the type of the value being matched. Our later, more complete treatment of Gallina's typing rules will explain why this helps.
*)
(** We finish the semantics with a straightforward definition of program denotation. *)
Fixpoint tprogDenote ts ts' (p : tprog ts ts') : vstack ts -> vstack ts' :=
match p with
| TNil _ => fun s => s
| TCons _ _ _ i p' => fun s => tprogDenote p' (tinstrDenote i s)
end.
(** The same argument-postponing trick is crucial for this definition. *)
(** ** Translation *)
(** To define our compilation, it is useful to have an auxiliary function for concatenating two stack machine programs. *)
Fixpoint tconcat ts ts' ts'' (p : tprog ts ts') : tprog ts' ts'' -> tprog ts ts'' :=
match p with
| TNil _ => fun p' => p'
| TCons _ _ _ i p1 => fun p' => TCons i (tconcat p1 p')
end.
(** With that function in place, the compilation is defined very similarly to how it was before, modulo the use of dependent typing. *)
Fixpoint tcompile t (e : texp t) (ts : tstack) : tprog ts (t :: ts) :=
match e with
| TNConst n => TCons (TiNConst _ n) (TNil _)
| TBConst b => TCons (TiBConst _ b) (TNil _)
| TBinop _ _ _ b e1 e2 => tconcat (tcompile e2 _)
(tconcat (tcompile e1 _) (TCons (TiBinop _ b) (TNil _)))
end.
(** One interesting feature of the definition is the underscores appearing to the right of [=>] arrows. Haskell and ML programmers are quite familiar with compilers that infer type parameters to polymorphic values. In Coq, it is possible to go even further and ask the system to infer arbitrary terms, by writing underscores in place of specific values. You may have noticed that we have been calling functions without specifying all of their arguments. For instance, the recursive calls here to [tcompile] omit the [t] argument. Coq's _implicit argument_ mechanism automatically inserts underscores for arguments that it will probably be able to infer. Inference of such values is far from complete, though; generally, it only works in cases similar to those encountered with polymorphic type instantiation in Haskell and ML.
The underscores here are being filled in with stack types. That is, the Coq type inferencer is, in a sense, inferring something about the flow of control in the translated programs. We can take a look at exactly which values are filled in: *)
Print tcompile.
(** %\vspace{-.15in}%[[
tcompile =
fix tcompile (t : type) (e : texp t) (ts : tstack) {struct e} :
tprog ts (t :: ts) :=
match e in (texp t0) return (tprog ts (t0 :: ts)) with
| TNConst n => TCons (TiNConst ts n) (TNil (Nat :: ts))
| TBConst b => TCons (TiBConst ts b) (TNil (Bool :: ts))
| TBinop arg1 arg2 res b e1 e2 =>
tconcat (tcompile arg2 e2 ts)
(tconcat (tcompile arg1 e1 (arg2 :: ts))
(TCons (TiBinop ts b) (TNil (res :: ts))))
end
: forall t : type, texp t -> forall ts : tstack, tprog ts (t :: ts)
]]
*)
(** We can check that the compiler generates programs that behave appropriately on our sample programs from above: *)
Eval simpl in tprogDenote (tcompile (TNConst 42) nil) tt.
(** [= (42, tt) : vstack (Nat :: nil)] *)
Eval simpl in tprogDenote (tcompile (TBConst true) nil) tt.
(** [= (true, tt) : vstack (Bool :: nil)] *)
Eval simpl in tprogDenote (tcompile (TBinop TTimes (TBinop TPlus (TNConst 2)
(TNConst 2)) (TNConst 7)) nil) tt.
(** [= (28, tt) : vstack (Nat :: nil)] *)
Eval simpl in tprogDenote (tcompile (TBinop (TEq Nat) (TBinop TPlus (TNConst 2)
(TNConst 2)) (TNConst 7)) nil) tt.
(** [= (false, tt) : vstack (Bool :: nil)] *)
Eval simpl in tprogDenote (tcompile (TBinop TLt (TBinop TPlus (TNConst 2) (TNConst 2))
(TNConst 7)) nil) tt.
(** [= (true, tt) : vstack (Bool :: nil)] *)
(** %\smallskip{}%The compiler seems to be working, so let us turn to proving that it _always_ works. *)
(** ** Translation Correctness *)
(** We can state a correctness theorem similar to the last one. *)
Theorem tcompile_correct : forall t (e : texp t),
tprogDenote (tcompile e nil) tt = (texpDenote e, tt).
(* begin hide *)
Abort.
(* end hide *)
(* begin thide *)
(** Again, we need to strengthen the theorem statement so that the induction will go through. This time, to provide an excuse to demonstrate different tactics, I will develop an alternative approach to this kind of proof, stating the key lemma as: *)
Lemma tcompile_correct' : forall t (e : texp t) ts (s : vstack ts),
tprogDenote (tcompile e ts) s = (texpDenote e, s).
(** While lemma [compile_correct'] quantified over a program that is the "continuation"%~\cite{continuations}% for the expression we are considering, here we avoid drawing in any extra syntactic elements. In addition to the source expression and its type, we also quantify over an initial stack type and a stack compatible with it. Running the compilation of the program starting from that stack, we should arrive at a stack that differs only in having the program's denotation pushed onto it.
Let us try to prove this theorem in the same way that we settled on in the last section. *)
induction e; crush.
(** We are left with this unproved conclusion:
[[
tprogDenote
(tconcat (tcompile e2 ts)
(tconcat (tcompile e1 (arg2 :: ts))
(TCons (TiBinop ts t) (TNil (res :: ts))))) s =
(tbinopDenote t (texpDenote e1) (texpDenote e2), s)
]]
We need an analogue to the [app_assoc_reverse] theorem that we used to rewrite the goal in the last section. We can abort this proof and prove such a lemma about [tconcat].
*)
Abort.
Lemma tconcat_correct : forall ts ts' ts'' (p : tprog ts ts') (p' : tprog ts' ts'')
(s : vstack ts),
tprogDenote (tconcat p p') s
= tprogDenote p' (tprogDenote p s).
induction p; crush.
Qed.
(** This one goes through completely automatically.
Some code behind the scenes registers [app_assoc_reverse] for use by [crush]. We must register [tconcat_correct] similarly to get the same effect:%\index{Vernacular commands!Hint Rewrite}% *)
Hint Rewrite tconcat_correct.
(** Here we meet the pervasive concept of a _hint_. Many proofs can be found through exhaustive enumerations of combinations of possible proof steps; hints provide the set of steps to consider. The tactic [crush] is applying such brute force search for us silently, and it will consider more possibilities as we add more hints. This particular hint asks that the lemma be used for left-to-right rewriting.
Now we are ready to return to [tcompile_correct'], proving it automatically this time. *)
Lemma tcompile_correct' : forall t (e : texp t) ts (s : vstack ts),
tprogDenote (tcompile e ts) s = (texpDenote e, s).
induction e; crush.
Qed.
(** We can register this main lemma as another hint, allowing us to prove the final theorem trivially. *)
Hint Rewrite tcompile_correct'.
Theorem tcompile_correct : forall t (e : texp t),
tprogDenote (tcompile e nil) tt = (texpDenote e, tt).
crush.
Qed.
(* end thide *)
(** It is probably worth emphasizing that we are doing more than building mathematical models. Our compilers are functional programs that can be executed efficiently. One strategy for doing so is based on%\index{program extraction}% _program extraction_, which generates OCaml code from Coq developments. For instance, we run a command to output the OCaml version of [tcompile]:%\index{Vernacular commands!Extraction}% *)
Extraction tcompile.
(** <<
let rec tcompile t e ts =
match e with
| TNConst n ->
TCons (ts, (Cons (Nat, ts)), (Cons (Nat, ts)), (TiNConst (ts, n)), (TNil
(Cons (Nat, ts))))
| TBConst b ->
TCons (ts, (Cons (Bool, ts)), (Cons (Bool, ts)), (TiBConst (ts, b)),
(TNil (Cons (Bool, ts))))
| TBinop (t1, t2, t0, b, e1, e2) ->
tconcat ts (Cons (t2, ts)) (Cons (t0, ts)) (tcompile t2 e2 ts)
(tconcat (Cons (t2, ts)) (Cons (t1, (Cons (t2, ts)))) (Cons (t0, ts))
(tcompile t1 e1 (Cons (t2, ts))) (TCons ((Cons (t1, (Cons (t2,
ts)))), (Cons (t0, ts)), (Cons (t0, ts)), (TiBinop (t1, t2, t0, ts,
b)), (TNil (Cons (t0, ts))))))
>>
We can compile this code with the usual OCaml compiler and obtain an executable program with halfway decent performance.
This chapter has been a whirlwind tour through two examples of the style of Coq development that I advocate. Parts II and III of the book focus on the key elements of that style, namely dependent types and scripted proof automation, respectively. Before we get there, we will spend some time in Part I on more standard foundational material. Part I may still be of interest to seasoned Coq hackers, since I follow the highly automated proof style even at that early stage. *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_SYMBOL_V
`define SKY130_FD_SC_HDLL__A211O_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_TB_V
`define SKY130_FD_SC_HVL__SDFSBP_TB_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfsbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__sdfsbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_TB_V
|
// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
//
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module table_control #( parameter n_words = 40
)
( input clk
, input ctrl_reset_n
, input [26:0] tdatai // dispatch intf to tables
, input [14:0] twraddr
, input [2:0] twren
, output [26:0] tdata_0
, output [26:0] tdata_1
, output [26:0] tdata_2
, input [1:0] command
, output idle
);
localparam wbits = $clog2(n_words);
wire [26:0] tdatao [2:0];
assign tdata_0 = tdatao[0];
assign tdata_1 = tdatao[1];
assign tdata_2 = tdatao[2];
reg [14:0] trdaddr_reg, trdaddr_next;
reg trden_reg, trden_next;
reg [wbits-1:0] count_reg, count_next;
reg state_reg, state_next;
localparam ST_IDLE = 1'b0;
localparam ST_STRM = 1'b1;
wire inST_IDLE = state_reg == ST_IDLE;
wire inST_STRM = state_reg == ST_STRM;
localparam CMD_START = 2'b01;
localparam CMD_RESET = 2'b10;
localparam CMD_ABORT = 2'b11;
wire gotCMD_ABORT = command == CMD_ABORT;
wire [14:0] trdaddr = trdaddr_reg + {{(15-wbits){1'b0}},count_reg};
wire last_count = count_reg == (n_words - 1);
assign idle = inST_IDLE;
always_comb begin
trdaddr_next = trdaddr_reg;
trden_next = trden_reg;
count_next = count_reg;
state_next = state_reg;
case (state_reg)
ST_IDLE: begin
if (~trden_reg) begin
case (command)
CMD_RESET: begin
trdaddr_next = '0;
trden_next = '0;
count_next = '0;
end
CMD_START: begin
trden_next = '1;
count_next = '0;
end
default: state_next = ST_IDLE;
endcase
end else begin
state_next = ST_STRM;
count_next = count_reg + 1'b1;
end
end
ST_STRM: begin
if (last_count | gotCMD_ABORT) begin
trden_next = '0;
count_next = '0;
trdaddr_next = trdaddr_reg + n_words;
state_next = ST_IDLE;
end else begin
count_next = count_reg + 1'b1;
end
end
endcase
end
always_ff @(posedge clk or negedge ctrl_reset_n) begin
if (~ctrl_reset_n) begin
trdaddr_reg <= '0;
trden_reg <= '0;
count_reg <= '0;
state_reg <= '0;
end else begin
trdaddr_reg <= trdaddr_next;
trden_reg <= trden_next;
count_reg <= count_next;
state_reg <= state_next;
end
end
genvar TGen;
generate for(TGen=0; TGen<3; TGen++) begin: TGenInst
t_ram ramins( .aclr (~ctrl_reset_n)
, .clock (clk)
, .data (tdatai)
, .wraddress (twraddr)
, .wren (twren[TGen])
, .rden (trden_reg)
, .rdaddress (trdaddr)
, .q (tdatao[TGen])
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_4_V
`define SKY130_FD_SC_LP__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_4_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : xilinx_pcie_2_1_ep_7x.v
// Version : 1.11
//--
//-- Description: PCI Express Endpoint example FPGA design
//--
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
module xilinx_pcie_2_1_ep_7x # (
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
output [0:0] pci_exp_txp,
output [0:0] pci_exp_txn,
input [0:0] pci_exp_rxp,
input [0:0] pci_exp_rxn,
input sys_clk_p,
input sys_clk_n,
input sys_rst_n
);
localparam TCQ = 1;
wire user_clk;
wire user_reset;
wire user_lnk_up;
// Tx
// wire [5:0] tx_buf_av;
// wire tx_cfg_req;
// wire tx_err_drop;
wire tx_cfg_gnt;
wire s_axis_tx_tready;
wire [3:0] s_axis_tx_tuser;
wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata;
wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
// Rx
wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata;
wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire rx_np_ok;
wire rx_np_req;
// Flow Control
// wire [11:0] fc_cpld;
// wire [7:0] fc_cplh;
// wire [11:0] fc_npd;
// wire [7:0] fc_nph;
// wire [11:0] fc_pd;
// wire [7:0] fc_ph;
wire [2:0] fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
wire cfg_err_cor;
wire cfg_err_ur;
wire cfg_err_ecrc;
wire cfg_err_cpl_timeout;
wire cfg_err_cpl_abort;
wire cfg_err_cpl_unexpect;
wire cfg_err_posted;
wire cfg_err_locked;
wire [47:0] cfg_err_tlp_cpl_header;
// wire cfg_err_cpl_rdy;
wire cfg_interrupt;
// wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_di;
// wire [7:0] cfg_interrupt_do;
// wire [2:0] cfg_interrupt_mmenable;
// wire cfg_interrupt_msienable;
// wire cfg_interrupt_msixenable;
// wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire [4:0] cfg_pciecap_interrupt_msgnum;
wire cfg_turnoff_ok;
wire cfg_to_turnoff;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
// wire [15:0] cfg_status;
// wire [15:0] cfg_command;
// wire [15:0] cfg_dcommand;
// wire [15:0] cfg_lcommand;
// wire [15:0] cfg_dcommand2;
wire [63:0] cfg_dsn;
wire [127:0] cfg_err_aer_headerlog;
wire [4:0] cfg_aer_interrupt_msgnum;
// wire cfg_err_aer_headerlog_set;
// wire cfg_aer_ecrc_check_en;
// wire cfg_aer_ecrc_gen_en;
wire [31:0] cfg_mgmt_di;
wire [3:0] cfg_mgmt_byte_en;
wire [9:0] cfg_mgmt_dwaddr;
wire cfg_mgmt_wr_en;
wire cfg_mgmt_rd_en;
wire cfg_mgmt_wr_readonly;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
// wire [2:0] pl_initial_link_width;
// wire [1:0] pl_lane_reversal_mode;
// wire pl_link_gen2_cap;
// wire pl_link_partner_gen2_supported;
// wire pl_link_upcfg_cap;
// wire pl_received_hot_rst;
// wire pl_sel_lnk_rate;
// wire [1:0] pl_sel_lnk_width;
wire pl_directed_link_auton;
wire [1:0] pl_directed_link_change;
wire pl_directed_link_speed;
wire [1:0] pl_directed_link_width;
wire pl_upstream_prefer_deemph;
wire sys_rst_n_c;
// Wires used for external clocking connectivity
wire PIPE_PCLK_IN;
wire PIPE_RXUSRCLK_IN;
wire [0:0] PIPE_RXOUTCLK_IN;
wire PIPE_DCLK_IN;
wire PIPE_USERCLK1_IN;
wire PIPE_USERCLK2_IN;
wire PIPE_MMCM_LOCK_IN;
wire PIPE_TXOUTCLK_OUT;
wire [0:0] PIPE_RXOUTCLK_OUT;
wire [0:0] PIPE_PCLK_SEL_OUT;
wire PIPE_GEN3_OUT;
wire PIPE_OOBCLK_IN;
localparam USER_CLK_FREQ = 1;
localparam USER_CLK2_DIV2 = "FALSE";
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ?
(USER_CLK_FREQ == 4) ? 3 :
(USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ :
USER_CLK_FREQ;
//-------------------------------------------------------
IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n));
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n));
reg user_reset_q;
reg user_lnk_up_q;
reg PIPE_MMCM_RST_N = 1'b1;
always @(posedge user_clk) begin
user_reset_q <= user_reset;
user_lnk_up_q <= user_lnk_up;
end
// Generate External Clock Module if External Clocking is selected
generate
if (PCIE_EXT_CLK == "TRUE") begin : ext_clk
//---------- PIPE Clock Module -------------------------------------------------
pcie_7x_v1_11_0_pipe_clock #
(
.PCIE_ASYNC_EN ( "FALSE" ), // PCIe async enable
.PCIE_TXBUF_EN ( "FALSE" ), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE ( 6'h01 ), // PCIe number of lanes
// synthesis translate_off
.PCIE_LINK_SPEED ( 2 ),
// synthesis translate_on
.PCIE_REFCLK_FREQ ( 0 ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ), // PCIe user clock 2 frequency
.PCIE_DEBUG_MODE ( 0 )
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK ( sys_clk ),
.CLK_TXOUTCLK ( PIPE_TXOUTCLK_OUT ), // Reference clock from lane 0
.CLK_RXOUTCLK_IN ( PIPE_RXOUTCLK_OUT ),
// .CLK_RST_N ( 1'b1 ),
.CLK_RST_N ( PIPE_MMCM_RST_N ),
.CLK_PCLK_SEL ( PIPE_PCLK_SEL_OUT ),
.CLK_GEN3 ( PIPE_GEN3_OUT ),
//---------- Output ------------------------------------
.CLK_PCLK ( PIPE_PCLK_IN ),
.CLK_RXUSRCLK ( PIPE_RXUSRCLK_IN ),
.CLK_RXOUTCLK_OUT ( PIPE_RXOUTCLK_IN ),
.CLK_DCLK ( PIPE_DCLK_IN ),
.CLK_OOBCLK ( PIPE_OOBCLK_IN ),
.CLK_USERCLK1 ( PIPE_USERCLK1_IN ),
.CLK_USERCLK2 ( PIPE_USERCLK2_IN ),
.CLK_MMCM_LOCK ( PIPE_MMCM_LOCK_IN )
);
end else begin
assign pipe_pclk_in = 1'b0;
assign pipe_rxusrclk_in = 1'b0;
assign pipe_rxoutclk_in = 0;
assign pipe_dclk_in = 1'b0;
assign pipe_userclk1_in = 1'b0;
assign pipe_userclk2_in = 1'b0;
assign pipe_mmcm_lock_in = 1'b0;
assign pipe_oobclk_in = 1'b0;
end
endgenerate
pcie_7x_v1_11_0 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK )
) pcie_7x_v1_11_0_i
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
// Rx
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Clocking Interface //
//----------------------------------------------------------------------------------------------------------------//
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
// TX
.tx_buf_av ( ),
.tx_err_drop ( ),
.tx_cfg_req ( ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
// Flow Control
.fc_cpld ( ),
.fc_cplh ( ),
.fc_npd ( ),
.fc_nph ( ),
.fc_pd ( ),
.fc_ph ( ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
.cfg_mgmt_do ( ),
.cfg_mgmt_rd_wr_done ( ),
.cfg_status ( ),
.cfg_command ( ),
.cfg_dstatus ( ),
.cfg_lstatus ( ),
.cfg_pcie_link_state ( ),
.cfg_dcommand ( ),
.cfg_lcommand ( ),
.cfg_dcommand2 ( ),
.cfg_pmcsr_pme_en ( ),
.cfg_pmcsr_powerstate ( ),
.cfg_pmcsr_pme_status ( ),
.cfg_received_func_lvl_rst ( ),
// Management Interface
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( cfg_mgmt_wr_en ),
.cfg_mgmt_rd_en ( cfg_mgmt_rd_en ),
.cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ),
// Error Reporting Interface
.cfg_err_ecrc ( cfg_err_ecrc ),
.cfg_err_ur ( cfg_err_ur ),
.cfg_err_cpl_timeout ( cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ),
.cfg_err_cpl_abort ( cfg_err_cpl_abort ),
.cfg_err_posted ( cfg_err_posted ),
.cfg_err_cor ( cfg_err_cor ),
.cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ),
.cfg_err_internal_cor ( cfg_err_internal_cor ),
.cfg_err_malformed ( cfg_err_malformed ),
.cfg_err_mc_blocked ( cfg_err_mc_blocked ),
.cfg_err_poisoned ( cfg_err_poisoned ),
.cfg_err_norecovery ( cfg_err_norecovery ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy ( ),
.cfg_err_locked ( cfg_err_locked ),
.cfg_err_acs ( cfg_err_acs ),
.cfg_err_internal_uncor ( cfg_err_internal_uncor ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( ),
.cfg_interrupt_mmenable ( ),
.cfg_interrupt_msienable ( ),
.cfg_interrupt_msixenable ( ),
.cfg_interrupt_msixfm ( ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_pm_wake ( cfg_pm_wake ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
.cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ),
.cfg_msg_received ( ),
.cfg_msg_data ( ),
.cfg_bridge_serr_en ( ),
.cfg_slot_control_electromech_il_ctl_pulse ( ),
.cfg_root_control_syserr_corr_err_en ( ),
.cfg_root_control_syserr_non_fatal_err_en ( ),
.cfg_root_control_syserr_fatal_err_en ( ),
.cfg_root_control_pme_int_en ( ),
.cfg_aer_rooterr_corr_err_reporting_en ( ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_corr_err_received ( ),
.cfg_aer_rooterr_non_fatal_err_received ( ),
.cfg_aer_rooterr_fatal_err_received ( ),
.cfg_msg_received_err_cor ( ),
.cfg_msg_received_err_non_fatal ( ),
.cfg_msg_received_err_fatal ( ),
.cfg_msg_received_pm_as_nak ( ),
.cfg_msg_received_pme_to_ack ( ),
.cfg_msg_received_assert_int_a ( ),
.cfg_msg_received_assert_int_b ( ),
.cfg_msg_received_assert_int_c ( ),
.cfg_msg_received_assert_int_d ( ),
.cfg_msg_received_deassert_int_a ( ),
.cfg_msg_received_deassert_int_b ( ),
.cfg_msg_received_deassert_int_c ( ),
.cfg_msg_received_deassert_int_d ( ),
.cfg_msg_received_pm_pme ( ),
.cfg_msg_received_setslotpowerlimit ( ),
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_sel_lnk_rate ( ),
.pl_sel_lnk_width ( ),
.pl_ltssm_state ( ),
.pl_lane_reversal_mode ( ),
.pl_phy_lnk_up ( ),
.pl_tx_pm_state ( ),
.pl_rx_pm_state ( ),
.pl_link_upcfg_cap ( ),
.pl_link_gen2_cap ( ),
.pl_link_partner_gen2_supported ( ),
.pl_initial_link_width ( ),
.pl_directed_change_done ( ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.pl_received_hot_rst ( ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.pl_transmit_hot_rst ( 1'b0 ),
.pl_downstream_deemph_source ( 1'b0 ),
//----------------------------------------------------------------------------------------------------------------//
// 6. AER Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_err_aer_headerlog_set ( ),
.cfg_aer_ecrc_check_en ( ),
.cfg_aer_ecrc_gen_en ( ),
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_vc_tcvc_map ( ),
//----------------------------------------------------------------------------------------------------------------//
// 8. System (SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
.PIPE_MMCM_RST_N ( PIPE_MMCM_RST_N ), // Async | Async
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n_c )
);
//----------------------------------------------------------------------------------------------------------------//
// User App //
//----------------------------------------------------------------------------------------------------------------//
pcie_app_7x #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ )
) app (
//----------------------------------------------------------------------------------------------------------------//
// 1. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk ( user_clk ),
.user_reset ( user_reset_q ),
.user_lnk_up ( user_lnk_up_q ),
// Tx
// .tx_buf_av ( tx_buf_av ),
// .tx_cfg_req ( tx_cfg_req ),
// .tx_err_drop ( tx_err_drop ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
// Flow Control
// .fc_cpld ( fc_cpld ),
// .fc_cplh ( fc_cplh ),
// .fc_npd ( fc_npd ),
// .fc_nph ( fc_nph ),
// .fc_pd ( fc_pd ),
// .fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_cor ( cfg_err_cor ),
.cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ),
.cfg_err_internal_cor ( cfg_err_internal_cor ),
.cfg_err_malformed ( cfg_err_malformed ),
.cfg_err_mc_blocked ( cfg_err_mc_blocked ),
.cfg_err_poisoned ( cfg_err_poisoned ),
.cfg_err_norecovery ( cfg_err_norecovery ),
.cfg_err_ur ( cfg_err_ur ),
.cfg_err_ecrc ( cfg_err_ecrc ),
.cfg_err_cpl_timeout ( cfg_err_cpl_timeout ),
.cfg_err_cpl_abort ( cfg_err_cpl_abort ),
.cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ),
.cfg_err_posted ( cfg_err_posted ),
.cfg_err_locked ( cfg_err_locked ),
.cfg_err_acs ( cfg_err_acs ), //1'b0 ),
.cfg_err_internal_uncor ( cfg_err_internal_uncor ), //1'b0 ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
// .cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt ( cfg_interrupt ),
// .cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
// .cfg_interrupt_do ( cfg_interrupt_do ),
// .cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
// .cfg_interrupt_msienable ( cfg_interrupt_msienable ),
// .cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
// .cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
// .cfg_status ( cfg_status ),
// .cfg_command ( cfg_command ),
// .cfg_dstatus ( cfg_dstatus ),
// .cfg_dcommand ( cfg_dcommand ),
// .cfg_lstatus ( cfg_lstatus ),
// .cfg_lcommand ( cfg_lcommand ),
// .cfg_dcommand2 ( cfg_dcommand2 ),
// .cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_dsn ( cfg_dsn ),
//----------------------------------------------------------------------------------------------------------------//
// 3. Management (MGMT) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( cfg_mgmt_wr_en ),
.cfg_mgmt_rd_en ( cfg_mgmt_rd_en ),
.cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ),
//----------------------------------------------------------------------------------------------------------------//
// 3. Advanced Error Reporting (AER) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
// .cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
// .cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
// .cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
// .pl_initial_link_width ( pl_initial_link_width ),
// .pl_lane_reversal_mode ( pl_lane_reversal_mode ),
// .pl_link_gen2_cap ( pl_link_gen2_cap ),
// .pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
// .pl_link_upcfg_cap ( pl_link_upcfg_cap ),
// .pl_ltssm_state ( pl_ltssm_state ),
// .pl_received_hot_rst ( pl_received_hot_rst ),
// .pl_sel_lnk_rate ( pl_sel_lnk_rate ),
// .pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph )
);
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_regfile_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 31: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 31: 0] data_out;
wire [ 31: 0] out_port;
wire [ 31: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[31 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_TB_V
`define SKY130_FD_SC_MS__TAPVGND_TB_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tapvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ms__tapvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__XNOR2_BEHAVIORAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xnor2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire xnor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pdr_odd.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pdr_odd(/*AUTOARG*/
// Outputs
arbpc1_pcxdp_grant_pa, arbpc1_pcxdp_q0_hold_pa_l,
arbpc1_pcxdp_qsel0_pa, arbpc1_pcxdp_qsel1_pa_l,
arbpc1_pcxdp_shift_px, arbpc3_pcxdp_grant_pa,
arbpc3_pcxdp_q0_hold_pa_l, arbpc3_pcxdp_qsel0_pa,
arbpc3_pcxdp_qsel1_pa_l, arbpc3_pcxdp_shift_px,
arbpc4_pcxdp_grant_pa, arbpc4_pcxdp_q0_hold_pa_l,
arbpc4_pcxdp_qsel0_pa, arbpc4_pcxdp_qsel1_pa_l,
arbpc4_pcxdp_shift_px,
// Inputs
arbpc1_pcxdp_grant_bufp3_pa_l, arbpc1_pcxdp_q0_hold_bufp3_pa,
arbpc1_pcxdp_qsel0_bufp3_pa_l, arbpc1_pcxdp_qsel1_bufp3_pa,
arbpc1_pcxdp_shift_bufp3_px_l, arbpc3_pcxdp_grant_bufp3_pa_l,
arbpc3_pcxdp_q0_hold_bufp3_pa, arbpc3_pcxdp_qsel0_bufp3_pa_l,
arbpc3_pcxdp_qsel1_bufp3_pa, arbpc3_pcxdp_shift_bufp3_px_l,
arbpc4_pcxdp_grant_bufp3_pa_l, arbpc4_pcxdp_q0_hold_bufp3_pa,
arbpc4_pcxdp_qsel0_bufp3_pa_l, arbpc4_pcxdp_qsel1_bufp3_pa,
arbpc4_pcxdp_shift_bufp3_px_l
);
output arbpc1_pcxdp_grant_pa ;
output arbpc1_pcxdp_q0_hold_pa_l ;
output arbpc1_pcxdp_qsel0_pa ;
output arbpc1_pcxdp_qsel1_pa_l ;
output arbpc1_pcxdp_shift_px ;
output arbpc3_pcxdp_grant_pa ;
output arbpc3_pcxdp_q0_hold_pa_l ;
output arbpc3_pcxdp_qsel0_pa ;
output arbpc3_pcxdp_qsel1_pa_l ;
output arbpc3_pcxdp_shift_px ;
output arbpc4_pcxdp_grant_pa ;
output arbpc4_pcxdp_q0_hold_pa_l ;
output arbpc4_pcxdp_qsel0_pa ;
output arbpc4_pcxdp_qsel1_pa_l ;
output arbpc4_pcxdp_shift_px ;
input arbpc1_pcxdp_grant_bufp3_pa_l;
input arbpc1_pcxdp_q0_hold_bufp3_pa;
input arbpc1_pcxdp_qsel0_bufp3_pa_l;
input arbpc1_pcxdp_qsel1_bufp3_pa;
input arbpc1_pcxdp_shift_bufp3_px_l;
input arbpc3_pcxdp_grant_bufp3_pa_l;
input arbpc3_pcxdp_q0_hold_bufp3_pa;
input arbpc3_pcxdp_qsel0_bufp3_pa_l;
input arbpc3_pcxdp_qsel1_bufp3_pa;
input arbpc3_pcxdp_shift_bufp3_px_l;
input arbpc4_pcxdp_grant_bufp3_pa_l;
input arbpc4_pcxdp_q0_hold_bufp3_pa;
input arbpc4_pcxdp_qsel0_bufp3_pa_l;
input arbpc4_pcxdp_qsel1_bufp3_pa;
input arbpc4_pcxdp_shift_bufp3_px_l;
assign arbpc1_pcxdp_grant_pa = ~arbpc1_pcxdp_grant_bufp3_pa_l;
assign arbpc1_pcxdp_q0_hold_pa_l = ~arbpc1_pcxdp_q0_hold_bufp3_pa;
assign arbpc1_pcxdp_qsel0_pa = ~arbpc1_pcxdp_qsel0_bufp3_pa_l;
assign arbpc1_pcxdp_qsel1_pa_l = ~arbpc1_pcxdp_qsel1_bufp3_pa;
assign arbpc1_pcxdp_shift_px = ~arbpc1_pcxdp_shift_bufp3_px_l;
assign arbpc3_pcxdp_grant_pa = ~arbpc3_pcxdp_grant_bufp3_pa_l;
assign arbpc3_pcxdp_q0_hold_pa_l = ~arbpc3_pcxdp_q0_hold_bufp3_pa;
assign arbpc3_pcxdp_qsel0_pa = ~arbpc3_pcxdp_qsel0_bufp3_pa_l;
assign arbpc3_pcxdp_qsel1_pa_l = ~arbpc3_pcxdp_qsel1_bufp3_pa;
assign arbpc3_pcxdp_shift_px = ~arbpc3_pcxdp_shift_bufp3_px_l;
assign arbpc4_pcxdp_grant_pa = ~arbpc4_pcxdp_grant_bufp3_pa_l;
assign arbpc4_pcxdp_q0_hold_pa_l = ~arbpc4_pcxdp_q0_hold_bufp3_pa;
assign arbpc4_pcxdp_qsel0_pa = ~arbpc4_pcxdp_qsel0_bufp3_pa_l;
assign arbpc4_pcxdp_qsel1_pa_l = ~arbpc4_pcxdp_qsel1_bufp3_pa;
assign arbpc4_pcxdp_shift_px = ~arbpc4_pcxdp_shift_bufp3_px_l;
endmodule
|
module clk_rst_mngr (
input clk_in,
input rst_async_n,
input en_clk_div8,
output rst_sync_n,
output clk_out,
output clk_div2,
output clk_div4,
output clk_div8,
output clk_div8_proc
);
reg [2:0] counter;
reg synch_rst_reg1_n, synch_rst_reg2_n;
reg en_clk_div8_reg;
// clock divider
always@(posedge clk_in)begin
if(!rst_async_n)
counter <= 0;
else
counter <= counter-1;
end
assign clk_out = clk_in;
assign clk_div2 = counter[0];
assign clk_div4 = counter[1];
assign clk_div8 = counter[2];
//change to make one delay to release the processor
always@(posedge clk_div8, negedge rst_async_n)begin
if(!rst_async_n)begin
en_clk_div8_reg <= 0;
end
else begin
en_clk_div8_reg <= en_clk_div8;
end
end
//"clock gate"
assign clk_div8_proc = en_clk_div8_reg?counter[2]:1'b0;
always@(posedge clk_div8, negedge rst_async_n)begin
if(!rst_async_n)begin
synch_rst_reg1_n <= 1'b0;
synch_rst_reg2_n <= 1'b0;
end
else begin
synch_rst_reg1_n <= 1'b1;
synch_rst_reg2_n <= synch_rst_reg1_n;
end
end
assign rst_sync_n = synch_rst_reg2_n;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_jesd_align (
// jesd interface
rx_clk,
rx_ip_sof,
rx_ip_data,
rx_sof,
rx_data);
// jesd interface
input rx_clk;
input [ 3:0] rx_ip_sof;
input [31:0] rx_ip_data;
// aligned data
output rx_sof;
output [31:0] rx_data;
// internal registers
reg [31:0] rx_ip_data_d = 'd0;
reg [ 3:0] rx_ip_sof_hold = 'd0;
reg rx_sof = 'd0;
reg [31:0] rx_data = 'd0;
// dword may contain more than one frame per clock
always @(posedge rx_clk) begin
rx_ip_data_d <= rx_ip_data;
if (rx_ip_sof != 4'd0) begin
rx_ip_sof_hold <= rx_ip_sof;
end
rx_sof <= |rx_ip_sof;
if (rx_ip_sof_hold[3] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[ 7: 0];
rx_data[23:16] <= rx_ip_data[15: 8];
rx_data[15: 8] <= rx_ip_data[23:16];
rx_data[ 7: 0] <= rx_ip_data[31:24];
end else if (rx_ip_sof_hold[2] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[31:24];
rx_data[23:16] <= rx_ip_data_d[ 7: 0];
rx_data[15: 8] <= rx_ip_data_d[15: 8];
rx_data[ 7: 0] <= rx_ip_data_d[23:16];
end else if (rx_ip_sof_hold[1] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[23:16];
rx_data[23:16] <= rx_ip_data[31:24];
rx_data[15: 8] <= rx_ip_data_d[ 7: 0];
rx_data[ 7: 0] <= rx_ip_data_d[15: 8];
end else if (rx_ip_sof_hold[0] == 1'b1) begin
rx_data[31:24] <= rx_ip_data[15: 8];
rx_data[23:16] <= rx_ip_data[23:16];
rx_data[15: 8] <= rx_ip_data[31:24];
rx_data[ 7: 0] <= rx_ip_data_d[ 7: 0];
end else begin
rx_data[31:24] <= 8'd0;
rx_data[23:16] <= 8'd0;
rx_data[15: 8] <= 8'd0;
rx_data[ 7: 0] <= 8'd0;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
(** * MoreInd: More on Induction *)
Require Export "ProofObjects".
(* ##################################################### *)
(** * Induction Principles *)
(** This is a good point to pause and take a deeper look at induction
principles.
Every time we declare a new [Inductive] datatype, Coq
automatically generates and proves an _induction principle_
for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** *** *)
(** The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
Case "O". reflexivity.
Case "S". simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, optional (plus_one_r') *)
(** Complete this proof as we did [mult_0_r'] above, without using
the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. (Although
we don't need induction to prove properties of non-recursive
datatypes, the idea of an induction principle still makes sense
for them: it gives a way to prove that a property holds for all
values of the type.)
These generated principles follow a similar pattern. If we define a
type [t] with constructors [c1] ... [cn], Coq generates a theorem
with this shape:
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(** **** Exercise: 1 star, optional (rgb) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
Check rgb_ind.
(** [] *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little variable renaming for clarity)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(** **** Exercise: 1 star, optional (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(** Now what will the induction principle look like? *)
(** [] *)
(** From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of
type [t]), then [P] holds for [c x1 ... xn]".
*)
(** **** Exercise: 1 star, optional (byntree_ind) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive byntree : Type :=
| bempty : byntree
| bleaf : yesno -> byntree
| nbranch : yesno -> byntree -> byntree -> byntree.
(** [] *)
(** **** Exercise: 1 star, optional (ex_set) *)
(** Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
Inductive ExSet : Type :=
(* FILL IN HERE *)
.
(** [] *)
(** What about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** **** Exercise: 1 star, optional (tree) *)
(** Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(** [] *)
(** **** Exercise: 1 star, optional (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo) *)
(** Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo') *)
(** Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(** What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently... *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** Now when we do the proof it is easier to see where [P_m0r]
appears. *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
Case "n = O". reflexivity.
Case "n = S n'".
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(** This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ##################################################### *)
(** ** More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative...
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
Case "n = O". intros m. rewrite -> plus_0_r. reflexivity.
Case "n = S n'". intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m'].
Case "m = O". simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(* FILL IN HERE *)
(** [] *)
(** ** Generalizing Inductions. *)
(** One potentially confusing feature of the [induction] tactic is
that it happily lets you try to set up an induction over a term
that isn't sufficiently general. The net effect of this will be
to lose information (much as [destruct] can do), and leave
you unable to complete the proof. Here's an example: *)
Lemma one_not_beautiful_FAILED: ~ beautiful 1.
Proof.
intro H.
(* Just doing an [inversion] on [H] won't get us very far in the [b_sum]
case. (Try it!). So we'll need induction. A naive first attempt: *)
induction H.
(* But now, although we get four cases, as we would expect from
the definition of [beautiful], we lose all information about [H] ! *)
Abort.
(** The problem is that [induction] over a Prop only works properly over
completely general instances of the Prop, i.e. one in which all
the arguments are free (unconstrained) variables.
In this respect it behaves more
like [destruct] than like [inversion].
When you're tempted to do use [induction] like this, it is generally
an indication that you need to be proving something more general.
But in some cases, it suffices to pull out any concrete arguments
into separate equations, like this: *)
Lemma one_not_beautiful: forall n, n = 1 -> ~ beautiful n.
Proof.
intros n E H.
induction H as [| | | p q Hp IHp Hq IHq].
Case "b_0".
inversion E.
Case "b_3".
inversion E.
Case "b_5".
inversion E.
Case "b_sum".
(* the rest is a tedious case analysis *)
destruct p as [|p'].
SCase "p = 0".
destruct q as [|q'].
SSCase "q = 0".
inversion E.
SSCase "q = S q'".
apply IHq. apply E.
SCase "p = S p'".
destruct q as [|q'].
SSCase "q = 0".
apply IHp. rewrite plus_0_r in E. apply E.
SSCase "q = S q'".
simpl in E. inversion E. destruct p'. inversion H0. inversion H0.
Qed.
(** There's a handy [remember] tactic that can generate the second
proof state out of the original one. *)
Lemma one_not_beautiful': ~ beautiful 1.
Proof.
intros H.
remember 1 as n eqn:E.
(* now carry on as above *)
induction H.
Admitted.
(* ####################################################### *)
(** * Informal Proofs (Advanced) *)
(** Q: What is the relation between a formal proof of a proposition
[P] and an informal proof of the same proposition [P]?
A: The latter should _teach_ the reader how to produce the
former.
Q: How much detail is needed??
Unfortunately, There is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the informal proof amounts to just
transcribing the formal one into words). This gives the reader
the _ability_ to reproduce the formal one for themselves, but it
doesn't _teach_ them anything.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because
usually writing the proof requires some deep insights into the
thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard part of work
that we went through to find the proof in the first place) and
clear high-level suggestions for the more routine parts to save the
reader from spending too much time reconstructing these
parts (e.g., what the IH says and what must be shown in each case
of an inductive proof), but not so much detail that the main ideas
are obscured.
Another key point: if we're comparing a formal proof of a
proposition [P] and an informal proof of [P], the proposition [P]
doesn't change. That is, formal and informal proofs are _talking
about the same world_ and they _must play by the same rules_. *)
(** ** Informal Proofs by Induction *)
(** Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief
and telegraphic. The ideal is somewhere in between, of course,
but while you are getting used to the style it is better to start
out at the pedantic end. Also, during the learning phase, it is
probably helpful to have a clear standard to compare against.
With this in mind, we offer two templates below -- one for proofs
by induction over _data_ (i.e., where the thing we're doing
induction on lives in [Type]) and one for proofs by induction over
_evidence_ (i.e., where the inductively defined thing lives in
[Prop]). In the rest of this course, please follow one of the two
for _all_ of your inductive proofs. *)
(** *** Induction Over an Inductively Defined Set *)
(** _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if length [[] = n], then [index (S n) [] =
None].
This follows immediately from the definition of index.
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be length [l']. [] *)
(** *** Induction Over an Inductively Defined Proposition *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(* ##################################################### *)
(** * Optional Material *)
(** The remainder of this chapter offers some additional details on
how induction works in Coq, the process of building proof
trees, and the "trusted computing base" that underlies
Coq proofs. It can safely be skimmed on a first reading. (We
recommend skimming rather than skipping over it outright: it
answers some questions that occur to many Coq users at some point,
so it is useful to have a rough idea of what's here.) *)
(* ##################################################### *)
(** ** Induction Principles in [Prop] *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [gorgeous]
are a tiny bit more complicated. As with all induction
principles, we want to use the induction principle on [gorgeous]
to prove things by inductively considering the possible shapes
that something in [gorgeous] can have -- either it is evidence
that [0] is gorgeous, or it is evidence that, for some [n], [3+n]
is gorgeous, or it is evidence that, for some [n], [5+n] is
gorgeous and it includes evidence that [n] itself is. Intuitively
speaking, however, what we want to prove are not statements about
_evidence_ but statements about _numbers_. So we want an
induction principle that lets us prove properties of numbers by
induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [gorgeous]...
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+m)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+m).
...to give rise to an induction principle that looks like this...
gorgeous_ind_max :
forall P : (forall n : nat, gorgeous n -> Prop),
P O g_0 ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (3+m) (g_plus3 m e) ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (5+m) (g_plus5 m e) ->
forall (n : nat) (e : gorgeous n), P n e
... because:
- Since [gorgeous] is indexed by a number [n] (every [gorgeous]
object [e] is a piece of evidence that some particular number
[n] is gorgeous), the proposition [P] is parameterized by both
[n] and [e] -- that is, the induction principle can be used to
prove assertions involving both a gorgeous number and the
evidence that it is gorgeous.
- Since there are three ways of giving evidence of gorgeousness
([gorgeous] has three constructors), applying the induction
principle generates three subgoals:
- We must prove that [P] holds for [O] and [b_0].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [3+m] and [g_plus3 n e].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [5+m] and [g_plus5 n e].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ gorgeous numbers [n] and
evidence [e] of their gorgeousness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
gorgeousness, while all we really care about is proving
properties of _numbers_ that are gorgeous -- we are interested in
assertions about numbers, not about evidence. It would therefore
be more convenient to have an induction principle for proving
propositions [P] that are parameterized just by [n] and whose
conclusion establishes [P] for all gorgeous numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat, gorgeous n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [gorgeous]: *)
Check gorgeous_ind.
(* ===> gorgeous_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, gorgeous n -> P n -> P (3 + n)) ->
(forall n : nat, gorgeous n -> P n -> P (5 + n)) ->
forall n : nat, gorgeous n -> P n *)
(** In particular, Coq has dropped the evidence term [e] as a
parameter of the the proposition [P], and consequently has
rewritten the assumption [forall (n : nat) (e: gorgeous n), ...]
to be [forall (n : nat), gorgeous n -> ...]; i.e., we no longer
require explicit evidence of the provability of [gorgeous n]. *)
(** In English, [gorgeous_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is gorgeous, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [3+n],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [5+n]. *)
(** As expected, we can apply [gorgeous_ind] directly instead of using [induction]. *)
Theorem gorgeous__beautiful' : forall n, gorgeous n -> beautiful n.
Proof.
intros.
apply gorgeous_ind.
Case "g_0".
apply b_0.
Case "g_plus3".
intros.
apply b_sum. apply b_3.
apply H1.
Case "g_plus5".
intros.
apply b_sum. apply b_5.
apply H1.
apply H.
Qed.
(** The precise form of an Inductive definition can affect the
induction principle Coq generates.
For example, in [Logic], we have defined [<=] as: *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(** By contrast, the induction principle that Coq calculates for the
first definition has a lot of extra quantifiers, which makes it
messier to work with when proving things by induction. Here is
the induction principle for the first [le]: *)
(* le_ind :
forall P : nat -> nat -> Prop,
(forall n : nat, P n n) ->
(forall n m : nat, le n m -> P n m -> P n (S m)) ->
forall n n0 : nat, le n n0 -> P n n0 *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** Suppose we make the following inductive definition:
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
Fill in the blanks to complete the induction principle that will be
generated by Coq.
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
*)
(** [] *)
(** **** Exercise: 2 stars, optional (bar_ind_principle) *)
(** Consider the following induction principle:
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
Write out the corresponding inductive set definition.
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** Given the following inductively defined proposition:
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
write the induction principle generated by Coq.
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Principles for other Logical Propositions *)
(** Similarly, in [Logic] we have defined [eq] as: *)
(* Inductive eq (X:Type) : X -> X -> Prop :=
refl_equal : forall x, eq X x x. *)
(** In the Coq standard library, the definition of equality is
slightly different: *)
Inductive eq' (X:Type) (x:X) : X -> Prop :=
refl_equal' : eq' X x x.
(** The advantage of this definition is that the induction
principle that Coq derives for it is precisely the familiar
principle of _Leibniz equality_: what we mean when we say "[x] and
[y] are equal" is that every property on [P] that is true of [x]
is also true of [y]. *)
Check eq'_ind.
(* ===>
forall (X : Type) (x : X) (P : X -> Prop),
P x -> forall y : X, x =' y -> P y
===> (i.e., after a little reorganization)
forall (X : Type) (x : X) forall y : X,
x =' y ->
forall P : X -> Prop, P x -> P y *)
(** The induction principles for conjunction and disjunction are a
good illustration of Coq's way of generating simplified induction
principles for [Inductive]ly defined propositions, which we
discussed above. You try first: *)
(** **** Exercise: 1 star, optional (and_ind_principle) *)
(** See if you can predict the induction principle for conjunction. *)
(* Check and_ind. *)
(** [] *)
(** **** Exercise: 1 star, optional (or_ind_principle) *)
(** See if you can predict the induction principle for disjunction. *)
(* Check or_ind. *)
(** [] *)
Check and_ind.
(** From the inductive definition of the proposition [and P Q]
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
we might expect Coq to generate this induction principle
and_ind_max :
forall (P Q : Prop) (P0 : P /\ Q -> Prop),
(forall (a : P) (b : Q), P0 (conj P Q a b)) ->
forall a : P /\ Q, P0 a
but actually it generates this simpler and more useful one:
and_ind :
forall P Q P0 : Prop,
(P -> Q -> P0) ->
P /\ Q -> P0
In the same way, when given the inductive definition of [or P Q]
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
instead of the "maximal induction principle"
or_ind_max :
forall (P Q : Prop) (P0 : P \/ Q -> Prop),
(forall a : P, P0 (or_introl P Q a)) ->
(forall b : Q, P0 (or_intror P Q b)) ->
forall o : P \/ Q, P0 o
what Coq actually generates is this:
or_ind :
forall P Q P0 : Prop,
(P -> P0) ->
(Q -> P0) ->
P \/ Q -> P0
]]
*)
(** **** Exercise: 1 star, optional (False_ind_principle) *)
(** Can you predict the induction principle for falsehood? *)
(* Check False_ind. *)
(** [] *)
(** Here's the induction principle that Coq generates for existentials: *)
Check ex_ind.
(* ===> forall (X:Type) (P: X->Prop) (Q: Prop),
(forall witness:X, P witness -> Q) ->
ex X P ->
Q *)
(** This induction principle can be understood as follows: If we have
a function [f] that can construct evidence for [Q] given _any_
witness of type [X] together with evidence that this witness has
property [P], then from a proof of [ex X P] we can extract the
witness and evidence that must have been supplied to the
constructor, give these to [f], and thus obtain a proof of [Q]. *)
(* ######################################################### *)
(** ** Explicit Proof Objects for Induction *)
(** Although tactic-based proofs are normally much easier to
work with, the ability to write a proof term directly is sometimes
very handy, particularly when we want Coq to do something slightly
non-standard. *)
(** Recall the induction principle on naturals that Coq generates for
us automatically from the Inductive declation for [nat]. *)
Check nat_ind.
(* ===>
nat_ind : forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** There's nothing magic about this induction lemma: it's just
another Coq lemma that requires a proof. Coq generates the proof
automatically too... *)
Print nat_ind.
Print nat_rect.
(* ===> (after some manual inlining and tidying)
nat_ind =
fun (P : nat -> Prop)
(f : P 0)
(f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n with
| 0 => f
| S n0 => f0 n0 (F n0)
end.
*)
(** We can read this as follows:
Suppose we have evidence [f] that [P] holds on 0, and
evidence [f0] that [forall n:nat, P n -> P (S n)].
Then we can prove that [P] holds of an arbitrary nat [n] via
a recursive function [F] (here defined using the expression
form [Fix] rather than by a top-level [Fixpoint]
declaration). [F] pattern matches on [n]:
- If it finds 0, [F] uses [f] to show that [P n] holds.
- If it finds [S n0], [F] applies itself recursively on [n0]
to obtain evidence that [P n0] holds; then it applies [f0]
on that evidence to show that [P (S n)] holds.
[F] is just an ordinary recursive function that happens to
operate on evidence in [Prop] rather than on terms in [Set].
*)
(** We can adapt this approach to proving [nat_ind] to help prove
_non-standard_ induction principles too. Recall our desire to
prove that
[forall n : nat, even n -> ev n].
Attempts to do this by standard induction on [n] fail, because the
induction principle only lets us proceed when we can prove that
[even n -> even (S n)] -- which is of course never provable. What
we did in [Logic] was a bit of a hack:
[Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n))].
We can make a much better proof by defining and proving a
non-standard induction principle that goes "by twos":
*)
Definition nat_ind2 :
forall (P : nat -> Prop),
P 0 ->
P 1 ->
(forall n : nat, P n -> P (S(S n))) ->
forall n : nat , P n :=
fun P => fun P0 => fun P1 => fun PSS =>
fix f (n:nat) := match n with
0 => P0
| 1 => P1
| S (S n') => PSS n' (f n')
end.
(** Once you get the hang of it, it is entirely straightforward to
give an explicit proof term for induction principles like this.
Proving this as a lemma using tactics is much less intuitive (try
it!).
The [induction ... using] tactic variant gives a convenient way to
specify a non-standard induction principle like this. *)
Lemma even__ev' : forall n, even n -> ev n.
Proof.
intros.
induction n as [ | |n'] using nat_ind2.
Case "even 0".
apply ev_0.
Case "even 1".
inversion H.
Case "even (S(S n'))".
apply ev_SS.
apply IHn'. unfold even. unfold even in H. simpl in H. apply H.
Qed.
(* ######################################################### *)
(** ** The Coq Trusted Computing Base *)
(** One issue that arises with any automated proof assistant is "why
trust it?": what if there is a bug in the implementation that
renders all its reasoning suspect?
While it is impossible to allay such concerns completely, the fact
that Coq is based on the Curry-Howard correspondence gives it a
strong foundation. Because propositions are just types and proofs
are just terms, checking that an alleged proof of a proposition is
valid just amounts to _type-checking_ the term. Type checkers are
relatively small and straightforward programs, so the "trusted
computing base" for Coq -- the part of the code that we have to
believe is operating correctly -- is small too.
What must a typechecker do? Its primary job is to make sure that
in each function application the expected and actual argument
types match, that the arms of a [match] expression are constructor
patterns belonging to the inductive type being matched over and
all arms of the [match] return the same type, and so on.
There are a few additional wrinkles:
- Since Coq types can themselves be expressions, the checker must
normalize these (by using the computation rules) before
comparing them.
- The checker must make sure that [match] expressions are
_exhaustive_. That is, there must be an arm for every possible
constructor. To see why, consider the following alleged proof
object:
Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
All the types here match correctly, but the [match] only
considers one of the possible constructors for [or]. Coq's
exhaustiveness check will reject this definition.
- The checker must make sure that each [fix] expression
terminates. It does this using a syntactic check to make sure
that each recursive call is on a subexpression of the original
argument. To see why this is essential, consider this alleged
proof:
Definition nat_false : forall (n:nat), False :=
fix f (n:nat) : False := f n.
Again, this is perfectly well-typed, but (fortunately) Coq will
reject it. *)
(** Note that the soundness of Coq depends only on the correctness of
this typechecking engine, not on the tactic machinery. If there
is a bug in a tactic implementation (and this certainly does
happen!), that tactic might construct an invalid proof term. But
when you type [Qed], Coq checks the term for validity from
scratch. Only lemmas whose proofs pass the type-checker can be
used in further proof developments. *)
(* $Date: 2014-06-05 07:22:21 -0400 (Thu, 05 Jun 2014) $ *)
|
/*
* Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
* Don't remove this header.
* When you use this source, there is a need to inherit this header.
*
* This software is released under the MIT License.
* http://opensource.org/licenses/mit-license.php
*
* For further information please contact.
* URI: http://www.aquaxis.com/
* E-Mail: info(at)aquaxis.com
*/
`timescale 1ps / 1ps
module aq_fifo
#(
parameter FIFO_DEPTH = 10,
parameter FIFO_WIDTH = 64
)
(
input RST_N,
input FIFO_WR_CLK,
input FIFO_WR_ENA,
input [FIFO_WIDTH -1:0] FIFO_WR_DATA,
input FIFO_WR_LAST,
output FIFO_WR_FULL,
output FIFO_WR_ALM_FULL,
input [FIFO_DEPTH -1:0] FIFO_WR_ALM_COUNT,
input FIFO_RD_CLK,
input FIFO_RD_ENA,
output [FIFO_WIDTH -1:0] FIFO_RD_DATA,
output FIFO_RD_EMPTY,
output FIFO_RD_ALM_EMPTY,
input [FIFO_DEPTH -1:0] FIFO_RD_ALM_COUNT
);
wire wr_ena, wr_full;
reg wr_ena_req_pre, wr_ena_req;
reg wr_rd_ena;
reg [2:0] wr_rd_ena_d;
wire wr_rd_ena_ack;
reg wr_rd_empty;
reg [FIFO_DEPTH -1:0] wr_adrs;
reg [FIFO_DEPTH :0] wr_count, wr_alm_count, wr_count_req_pre, wr_count_req, wr_rd_count;
wire rd_ena, rd_empty;
reg rd_ena_d;
reg rd_ena_req_pre, rd_ena_req;
reg rd_wr_ena;
reg [2:0] rd_wr_ena_d;
wire rd_wr_ena_ack;
reg rd_wr_full;
reg [FIFO_DEPTH -1:0] rd_adrs;
reg [FIFO_DEPTH :0] rd_count, rd_alm_count, rd_count_req_pre, rd_count_req, rd_wr_count;
wire rsv_ena;
reg rsv_empty;
reg [FIFO_WIDTH -1:0] rsv_data;
wire [FIFO_WIDTH -1:0] rd_fifo;
/////////////////////////////////////////////////////////////////////
// Write Block
assign wr_full = wr_count[FIFO_DEPTH];
assign wr_ena = (!wr_full)?(FIFO_WR_ENA):1'b0;
// Write Address
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_adrs <= 0;
end else begin
if(wr_ena) wr_adrs <= wr_adrs + 1;
end
end
// make a full and almost full signal
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_count <= 0;
wr_alm_count <= 0;
end else begin
if(wr_ena) begin
if(wr_rd_ena) begin
wr_count <= wr_count - {1'b0, wr_rd_count} + 1;
end else begin
wr_count <= wr_count + 1;
end
end else if(wr_rd_ena) begin
wr_count <= wr_count - {1'b0, wr_rd_count};
end
wr_alm_count <= wr_count + {1'b0, FIFO_WR_ALM_COUNT};
end
end
// Read Control signal from Read Block
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_rd_count <= {FIFO_DEPTH{1'b0}};
wr_rd_ena_d[2:0] <= 3'd0;
wr_rd_empty <= 1'b0;
wr_rd_ena <= 1'b0;
end else begin
wr_rd_ena_d[2:0] <= {wr_rd_ena_d[1:0], rd_ena_req};
if(wr_rd_ena_d[2:1] == 2'b01) begin
wr_rd_ena <= 1'b1;
wr_rd_count <= rd_count_req;
wr_rd_empty <= rd_empty;
end else begin
wr_rd_ena <= 1'b0;
end
end
end
assign wr_rd_ena_ack = wr_rd_ena_d[2] & wr_rd_ena_d[1];
// Send a write enable signal for Read Block
reg [2:0] wr_rd_ack_d;
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_ena_req_pre <= 1'b0;
wr_ena_req <= 1'b0;
wr_count_req_pre <= 0;
wr_count_req <= 0;
wr_rd_ack_d <= 3'd0;
end else begin
wr_rd_ack_d[2:0] <= {wr_rd_ack_d[1:0], rd_wr_ena_ack};
if(wr_ena & FIFO_WR_LAST) begin
wr_ena_req_pre <= 1'b1;
end else if(~wr_ena_req & (wr_rd_ack_d[2:1] == 2'b00)) begin
wr_ena_req_pre <= 1'b0;
end
if(~wr_ena_req & wr_ena_req_pre & (wr_rd_ack_d[2:1] == 2'b00)) begin
if(wr_ena) begin
wr_count_req_pre <= 1;
end else begin
wr_count_req_pre <= 0;
end
end else if(wr_ena) begin
wr_count_req_pre <= wr_count_req_pre + 1;
end
if(~wr_ena_req & wr_ena_req_pre & (wr_rd_ack_d[2:1] == 2'b00)) begin
wr_ena_req <= 1'b1;
wr_count_req <= wr_count_req_pre;
end else if(wr_rd_ack_d[2:1] == 2'b01) begin
wr_ena_req <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////
// Read Block
assign rd_empty = (rd_count == 0)?1'b1:1'b0;
assign rsv_ena = rsv_empty & ~rd_empty;
assign rd_ena = rsv_ena | (FIFO_RD_ENA & ~rd_empty);
// Read Address
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_adrs <= 0;
end else begin
if(rd_ena) begin
rd_adrs <= rd_adrs + 1;
end
end
end
// make a empty and almost empty signal
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_count <= 0;
rd_alm_count <= 0;
end else begin
if(rd_ena) begin
if(rd_wr_ena) begin
rd_count <= rd_count + {1'b0, rd_wr_count} - 1;
end else begin
rd_count <= rd_count - 1;
end
end else if(rd_wr_ena) begin
rd_count <= rd_count + {1'b0, rd_wr_count};
end
rd_alm_count <= rd_count - {1'b0, FIFO_RD_ALM_COUNT};
end
end
// Write Control signal from Write Block
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_wr_ena_d[2:0] <= 3'd0;
rd_wr_count <= {FIFO_DEPTH{1'b0}};
rd_wr_full <= 1'b0;
rd_wr_ena <= 1'b0;
end else begin
rd_wr_ena_d[2:0] <= {rd_wr_ena_d[1:0], wr_ena_req};
if(rd_wr_ena_d[2:1] == 2'b01) begin
rd_wr_ena <= 1'b1;
rd_wr_count <= wr_count_req;
rd_wr_full <= wr_count[FIFO_DEPTH];
end else begin
rd_wr_ena <= 1'b0;
end
end
end
// Write enable signal from write block
assign rd_wr_ena_ack = rd_wr_ena_d[2] & rd_wr_ena_d[1];
// Send a read enable signal for Write Block
reg [2:0] rd_wr_ack_d;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_ena_req_pre <= 1'b0;
rd_ena_req <= 1'b0;
rd_count_req <= {FIFO_DEPTH{1'b0}};
rd_count_req_pre <= {FIFO_DEPTH{1'b0}};
rd_wr_ack_d[2:0] <= 3'd0;
end else begin
rd_wr_ack_d[2:0] <= {rd_wr_ack_d[1:0], wr_rd_ena_ack};
if(rd_ena) begin
rd_ena_req_pre <= 1'b1;
end else if(~rd_ena_req & (rd_wr_ack_d[2:1] == 2'd00)) begin
rd_ena_req_pre <= 1'b0;
end
if(~rd_ena_req & rd_ena_req_pre & (rd_wr_ack_d[2:1] == 2'd00)) begin
if(rd_ena) begin
rd_count_req_pre <= 1;
end else begin
rd_count_req_pre <= 0;
end
end else if(rd_ena) begin
rd_count_req_pre <= rd_count_req_pre + 1;
end
if(~rd_ena_req & rd_ena_req_pre & (rd_wr_ack_d[2:1] == 2'd00)) begin
rd_ena_req <= 1'b1;
rd_count_req <= rd_count_req_pre;
end else if(rd_wr_ack_d[2:1] == 2'b01) begin
rd_ena_req <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////
// rsv Block
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rsv_data <= {FIFO_WIDTH{1'b0}};
rsv_empty <= 1'b1;
end else begin
rd_ena_d <= FIFO_RD_ENA;
if(rd_ena | rd_ena_d) begin
rsv_data <= rd_fifo;
end
if(FIFO_RD_ENA & rd_empty) begin
rsv_empty <= 1'b1;
end else if(rd_ena) begin
rsv_empty <= 1'b0;
end
end
end
assign rsv_alm_empty = (rd_empty & ~rsv_empty);
/////////////////////////////////////////////////////////////////////
// output signals
assign FIFO_WR_FULL = wr_count[FIFO_DEPTH];
assign FIFO_WR_ALM_FULL = wr_alm_count[FIFO_DEPTH];
assign FIFO_RD_EMPTY = rsv_empty;
assign FIFO_RD_ALM_EMPTY = rd_alm_count[FIFO_DEPTH];
assign FIFO_RD_DATA = (rd_ena_d)?rd_fifo:rsv_data;
/////////////////////////////////////////////////////////////////////
// RAM
fifo_ram #(FIFO_DEPTH,FIFO_WIDTH) u_fifo_ram(
.WR_CLK ( FIFO_WR_CLK ),
.WR_ENA ( wr_ena ),
.WR_ADRS ( wr_adrs ),
.WR_DATA ( FIFO_WR_DATA ),
.RD_CLK ( FIFO_RD_CLK ),
.RD_ADRS ( rd_adrs ),
.RD_DATA ( rd_fifo )
);
endmodule
module fifo_ram
#(
parameter DEPTH = 12,
parameter WIDTH = 32
)
(
input WR_CLK,
input WR_ENA,
input [DEPTH -1:0] WR_ADRS,
input [WIDTH -1:0] WR_DATA,
input RD_CLK,
input [DEPTH -1:0] RD_ADRS,
output [WIDTH -1:0] RD_DATA
);
reg [WIDTH -1:0] ram [0:(2**DEPTH) -1];
reg [WIDTH -1:0] rd_reg;
always @(posedge WR_CLK) begin
if(WR_ENA) ram[WR_ADRS] <= WR_DATA;
end
always @(posedge RD_CLK) begin
rd_reg <= ram[RD_ADRS];
end
assign RD_DATA = rd_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__OR3B_PP_SYMBOL_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVP_TB_V
`define SKY130_FD_SC_MS__EINVP_TB_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvp.v"
module top();
// Inputs are registered
reg A;
reg TE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__einvp dut (.A(A), .TE(TE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVP_TB_V
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_keccak;
// Inputs
reg clk;
reg reset;
reg [31:0] in;
reg in_ready;
reg is_last;
reg [1:0] byte_num;
// Outputs
wire buffer_full;
wire [511:0] out;
wire out_ready;
// Var
integer i;
// Instantiate the Unit Under Test (UUT)
keccak uut (
.clk(clk),
.reset(reset),
.in(in),
.in_ready(in_ready),
.is_last(is_last),
.byte_num(byte_num),
.buffer_full(buffer_full),
.out(out),
.out_ready(out_ready)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
in = 0;
in_ready = 0;
is_last = 0;
byte_num = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// SHA3-512("The quick brown fox jumps over the lazy dog")
reset = 1; #(`P); reset = 0;
in_ready = 1; is_last = 0;
in = "The "; #(`P);
in = "quic"; #(`P);
in = "k br"; #(`P);
in = "own "; #(`P);
in = "fox "; #(`P);
in = "jump"; #(`P);
in = "s ov"; #(`P);
in = "er t"; #(`P);
in = "he l"; #(`P);
in = "azy "; #(`P);
in = "dog "; byte_num = 3; is_last = 1; #(`P); /* !!! not in = "dog" */
in_ready = 0; is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'hd135bb84d0439dbac432247ee573a23ea7d3c9deb2a968eb31d47c4fb45f1ef4422d6c531b5b9bd6f449ebcc449ea94d0a8f05f62130fda612da53c79659f609);
// SHA3-512("The quick brown fox jumps over the lazy dog.")
reset = 1; #(`P); reset = 0;
in_ready = 1; is_last = 0;
in = "The "; #(`P);
in = "quic"; #(`P);
in = "k br"; #(`P);
in = "own "; #(`P);
in = "fox "; #(`P);
in = "jump"; #(`P);
in = "s ov"; #(`P);
in = "er t"; #(`P);
in = "he l"; #(`P);
in = "azy "; #(`P);
in = "dog."; #(`P);
in = 0; byte_num = 0; is_last = 1; #(`P); /* !!! */
in_ready = 0; is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'hab7192d2b11f51c7dd744e7b3441febf397ca07bf812cceae122ca4ded6387889064f8db9230f173f6d1ab6e24b6e50f065b039f799f5592360a6558eb52d760);
// hash an string "\xA1\xA2\xA3\xA4\xA5", len == 5
reset = 1; #(`P); reset = 0;
#(7*`P); // wait some cycles
in_ready = 1; is_last = 0; byte_num = 1;
in = 32'hA1A2A3A4;
#(`P);
is_last = 1; byte_num = 1;
in = 32'hA5000000;
#(`P);
in = 32'h12345678; // next input
in_ready = 1;
is_last = 1;
#(`P/2);
if (buffer_full === 1) error; // should be 0
#(`P/2);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'h12f4a85b68b091e8836219e79dfff7eb9594a42f5566515423b2aa4c67c454de83a62989e44b5303022bfe8c1a9976781b747a596cdab0458e20d8750df6ddfb);
for(i=0; i<5; i=i+1)
begin
#(`P);
if (buffer_full !== 0) error; // should keep 0
end
// hash an empty string, should not eat next input
reset = 1; #(`P); reset = 0;
#(7*`P); // wait some cycles
in = 32'h12345678; // should not be eat
byte_num = 0;
in_ready = 1;
is_last = 1;
#(`P);
in = 32'hddddd; // should not be eat
in_ready = 1; // next input
is_last = 1;
#(`P);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'h0eab42de4c3ceb9235fc91acffe746b29c29a8c366b7c60e4e67c466f36a4304c00fa9caf9d87976ba469bcbe06713b435f091ef2769fb160cdab33d3670680e);
for(i=0; i<5; i=i+1)
begin
#(`P);
if (buffer_full !== 0) error; // should keep 0
end
// hash an (576-8) bit string
reset = 1; #(`P); reset = 0;
#(4*`P); // wait some cycles
in_ready = 1;
byte_num = 3; /* should have no effect */
is_last = 0;
for (i=0; i<8; i=i+1)
begin
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; #(`P);
end
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; is_last = 1; #(`P);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'hf7f6b44069dba8900b6711ffcbe40523d4bb718cc8ed7f0a0bd28a1b18ee9374359f0ca0c9c1e96fcfca29ee2f282b46d5045eff01f7a7549eaa6b652cbf6270);
// pad an (576-64) bit string
reset = 1; #(`P); reset = 0;
// don't wait any cycle
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<8; i=i+1)
begin
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; #(`P);
end
is_last = 1;
byte_num = 0;
#(`P);
in_ready = 0;
is_last = 0;
in = 0;
while (out_ready !== 1)
#(`P);
check(512'hccd91653872c106f6eea1b8b68a4c2901c8d9bed9c180201f8a6144e7e6e6c251afcb6f6da44780b2d9aabff254036664719425469671f7e21fb67e5280a27ed);
// pad an (576*2-16) bit string
reset = 1; #(`P); reset = 0;
in_ready = 1;
byte_num = 1; /* should have no effect */
is_last = 0;
for (i=0; i<9; i=i+1)
begin
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; #(`P);
end
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
in = 32'h999; // should not eat this
in_ready = 0;
#(`P/2);
if (buffer_full !== 0) error; // should not eat, but buffer should not be full
#(`P/2);
#(`P);
// feed next (576-16) bit
in_ready = 1;
for (i=0; i<8; i=i+1)
begin
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; #(`P);
end
in = 32'hEFCDAB90; #(`P);
byte_num = 2;
is_last = 1;
in = 32'h78563412;
#(`P);
is_last = 0;
in_ready = 0;
while (out_ready !== 1)
#(`P);
check(512'h0f385323604e279251e80f928cfd9ce9492ba5df775063ea106eebe2a2c7785a3e33b4397fca66e90f67470334c66ea12016cb1f06170b9b033f158a7c01933e);
$display("Good!");
$finish;
end
always #(`P/2) clk = ~ clk;
task error;
begin
$display("E");
$finish;
end
endtask
task check;
input [511:0] wish;
begin
if (out !== wish)
begin
$display("%h %h", out, wish); error;
end
end
endtask
endmodule
`undef P
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hvl__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hvl__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
wire buf0_out_Q;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out , D, SCD, SCE );
sky130_fd_sc_hvl__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_4_V
`define SKY130_FD_SC_HD__O311A_4_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311a_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_4_V
|
`default_nettype none
module pulse_gen(
input clk, // 12 MHz base clock
input RS232_Rx, // Receive pin for the FTDI chip
// input resetn, // Reset the cycle
output RS232_Tx, // Transmit pin for the FTDI chip
output Pulse, // Output pin for the switch
output Sync, // Output pin for the SYNC pulse
// output FM, // Output pin for the FM pulse
output Block
// output P3,
// output P4,
// output J1_4,
// output J1_5,
// output J1_6,
// output J1_7,
// output J1_8,
// output J1_9,
// output J1_10,
// output J4_3,
// output J4_4,
// output J4_5,
// output J4_6,
// output J4_7,
// output J4_8,
// output J4_9
);
wire [23:0] period;
wire [15:0] p1width;
wire [15:0] delay;
wire [15:0] p2width;
wire block;
wire [7:0] pulse_block;
// wire [15:0] pulse_block_off;
wire cpmg;
wire rx_done;
// wire [6:0] pre_att;
// wire [6:0] post_att;
// NOSIM_START
wire clk_pll;
wire clk_pll_gl;
wire lock;
// Setting the PLL to output a 100.5 MHz clock, based on code from
// https://gist.github.com/thoughtpolice/8ec923e1b3fc4bb12c11aa23b4dc53b5#file-ice40-v
// Note: These values are slightly different from those outputted by icepll
// icepll pll(
// .REFERENCECLK(clk),
// .PLLOUTCORE(clk_pll),
// .PLLOUTGLOBAL(clk_pll_gl),
// .RESET(!resetn),
// .LOCK(lock)
// );
pll icepll(
.clock_in(clk),
.clock_out(clk_pll),
.locked(lock)
);
// NOSIM_END
// Setting up communications with LabView over USB
pulse_control control(
.clk(clk),
.RS232_Rx(RS232_Rx),
.RS232_Tx(RS232_Tx),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
// .p_bl(pulse_block),
// .p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done)
);
// Generating the necessary pulses
pulses pulses(
.clk_pll(clk_pll),
.clk(clk),
// .reset(resetn),
.per(period),
.p1wid(p1width),
.del(delay),
.p2wid(p2width),
// .pr_att(pre_att),
// .po_att(post_att),
.cp(cpmg),
// .p_bl(pulse_block),
// .p_bl_off(pulse_block_off),
.bl(block),
.rxd(rx_done),
.sync_on(Sync),
.pulse_on(Pulse),
// .Att1({J1_4, J1_5, J1_6, J1_7, J1_8, J1_9, J1_10}),
// .Att3({J4_9, J4_8, J4_7, J4_6, J4_5, J4_4, J4_3}),
.inhib(Block)
// .test({FM, P3, P4})
);
endmodule // pulse_gen
|
/*
*******************************************************************************
* File Name : ada_exu.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 1st, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : The Execution unit.
* Performs the following operations:
* - Arithmetic (add, substraction, multiplication and division)
* - Logical (and, nand, or, nor, xor, xnor, not)
* - Shift (logic left, arithmetic right, logic right)
* - Comparison (ce, cne, cg, cge, cgu, cgeu)
* Dependencies: ada_exu_div : divider unit
*******************************************************************************
*/
`include "ada_defines.v"
module ada_exu(
input clk, // clock
input rst, // reset
input [31:0] port_a, // Operand
input [31:0] port_b, // Operand
input [4:0] operation, // Alu operation
input ex_stall, // stall the execution stage
input ex_flush, // flush the execution stage
output reg [31:0] result, //
output exc_div_zero, // Exception for divide by zero.
output haz_ex_stall // Executing a Div instruction
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg [63:0] hilo; // hold the result from the mul and div instructions (signed and unsigned)
reg div_active; // 1 if the divider is currently active.
reg hilo_access;
///-------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [31:0] A;
wire [31:0] B;
wire signed [31:0] As;
wire signed [31:0] Bs;
wire signed [31:0] addsub_result;
wire signed [63:0] mults_result;
wire signed [63:0] multu_result;
wire [31:0] quotient;
wire [31:0] remainder;
wire [31:0] hi;
wire [31:0] lo;
wire op_divs;
wire op_divu;
wire div_stall;
wire enable_ex;
//--------------------------------------------------------------------------
// assigments
//--------------------------------------------------------------------------
assign A = port_a;
assign B = port_b;
assign As = port_a;
assign Bs = port_b;
assign addsub_result = (operation == `ALU_OP_ADD) ? A + B : A - B;
assign multu_result = A * B;
assign mults_result = As * Bs;
assign hi = hilo[63:32];
assign lo = hilo[31:0];
assign enable_ex = ~(ex_stall | ex_flush | haz_ex_stall);
assign op_divs = (B != 32'd0) & (div_active == 1'b0) & (operation == `ALU_OP_DIVS) & enable_ex;
assign op_divu = (B != 32'd0) & (div_active == 1'b0) & (operation == `ALU_OP_DIVU) & enable_ex;
assign exc_div_zero = (B == 32'd0) & ((operation == `ALU_OP_DIVS) | (operation == `ALU_OP_DIVU));
assign haz_ex_stall = (div_active == 1'b1) & (hilo_access == 1'b1);
//--------------------------------------------------------------------------
// instantiate the divider unit
//--------------------------------------------------------------------------
ada_exu_div Divider(
.clk(clk),
.rst(rst),
.op_divs(op_divs),
.op_divu(op_divu),
.dividend(port_a),
.divisor(port_b),
.quotient(quotient),
.remainder(remainder),
.stall(div_stall)
);
//--------------------------------------------------------------------------
// the BIG multiplexer
//--------------------------------------------------------------------------
always @(*) begin
case(operation)
`ALU_OP_ADD : result <= addsub_result;
`ALU_OP_SUB : result <= addsub_result;
`ALU_OP_CE : result <= {32{A == B}};
`ALU_OP_CGE : result <= {32{As >= Bs}};
`ALU_OP_CGEU : result <= {32{A >= B}};
`ALU_OP_CG : result <= {32{As > Bs}};
`ALU_OP_CGU : result <= {32{A > B}};
`ALU_OP_CNE : result <= {32{A != B}};
`ALU_OP_AND : result <= A & B;
`ALU_OP_NAND : result <= ~(A & B);
`ALU_OP_NOR : result <= ~(A | B);
`ALU_OP_OR : result <= A | B;
`ALU_OP_NOT : result <= ~A;
`ALU_OP_XNOR : result <= ~(A ^ B);
`ALU_OP_XOR : result <= A ^ B;
`ALU_OP_RL : result <= (A << B) | (A >> (6'd32 - B));
`ALU_OP_RR : result <= (A >> B) | (A << (6'd32 - B));
`ALU_OP_SLL : result <= A << B;
`ALU_OP_SRA : result <= As >> B;
`ALU_OP_SRL : result <= A >> B;
`ALU_OP_MULS : result <= mults_result[31:0];
`ALU_OP_MULU : result <= multu_result[31:0];
`ALU_OP_MFH : result <= hi;
`ALU_OP_MFL : result <= lo;
default : result <= 32'bx;
endcase
end
//--------------------------------------------------------------------------
// Write to hilo register
// Div has priority over mult
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
hilo <= 64'h00000000_00000000;
end
else if ((div_stall == 1'b0) & (div_active == 1'b1)) begin
hilo <= {remainder, quotient}; // Load when div operations has been finished.
end
else if(enable_ex) begin
case (operation)
`ALU_OP_MULS : hilo <= mults_result;
`ALU_OP_MULU : hilo <= multu_result;
`ALU_OP_MACS : hilo <= hilo + mults_result; // MAC instruction (signed)
`ALU_OP_MACU : hilo <= hilo + multu_result; // MAC instruction (unsigned)
`ALU_OP_MASS : hilo <= hilo - mults_result; // MAS instruction (signed)
`ALU_OP_MASU : hilo <= hilo - multu_result; // MAS instruction (unsigned)
`ALU_OP_MTH : hilo <= {A, lo};
`ALU_OP_MTL : hilo <= {hi, A};
default : hilo <= hilo;
endcase
end
else begin
hilo <= hilo;
end
end
//--------------------------------------------------------------------------
// determinate if the dividers is currently on use.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
div_active <= 1'b0;
end
else begin
case(div_active)
1'd0 : div_active <= (op_divs || op_divu) ? 1'b1 : 1'b0; // Check hilo_enable is redundant
1'd1 : div_active <= (~div_stall) ? 1'b0 : 1'b1;
endcase
end
end
//--------------------------------------------------------------------------
// Detect access to HILO register
//--------------------------------------------------------------------------
always @(*) begin
case (operation)
`ALU_OP_DIVS : hilo_access <= 1'b1;
`ALU_OP_DIVU : hilo_access <= 1'b1;
`ALU_OP_MULS : hilo_access <= 1'b1;
`ALU_OP_MULU : hilo_access <= 1'b1;
`ALU_OP_MACS : hilo_access <= 1'b1;
`ALU_OP_MACU : hilo_access <= 1'b1;
`ALU_OP_MASS : hilo_access <= 1'b1;
`ALU_OP_MASU : hilo_access <= 1'b1;
`ALU_OP_MTH : hilo_access <= 1'b1;
`ALU_OP_MTL : hilo_access <= 1'b1;
`ALU_OP_MFH : hilo_access <= 1'b1;
`ALU_OP_MFL : hilo_access <= 1'b1;
default : hilo_access <= 1'b0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_2_V
`define SKY130_FD_SC_HS__A311O_2_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_2_V
|
/****************************************************************************************
*
* File Name: ddr.v
* Version: 6.00
* Model: BUS Functional
*
* Dependencies: ddr_parameters.v
*
* Description: Micron SDRAM DDR (Double Data Rate)
*
* Limitation: - Doesn't check for 8K-cycle refresh.
* - Doesn't check power-down entry/exit
* - Doesn't check self-refresh entry/exit.
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set DEBUG = 0 to disable $display messages
* - Model assume Clk and Clk# crossing at both edge
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* --- ------ ---------- ---------------------------------------
* 2.1 SPH 03/19/2002 - Second Release
* - Fix tWR and several incompatability
* between different simulators
* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks.
* - Added tDQSH and tDQSL timing checks.
* 3.1 CAH 05/28/2003 - update all models to release version 3.1
* (no changes to this model)
* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3
* 3.3 JMK 09/11/2003 - Added initialization sequence checks.
* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v"
* - Fixed tWTR check
* 4.1 JMK 01/14/2004 - Grouped specify parameters by speed grade
* - Fixed mem_sizes parameter
* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs
* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module
* - Changed Dq_buf size to [15:0]
* 5.0 JMK 06/16/2004 - Added read to write checking.
* - Added read with precharge truncation to write checking.
* - Added associative memory array to reduce memory consumption.
* - Added checking for required DQS edges during write.
* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write.
* - Fixed wdqs_valid window.
* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored.
* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate.
* - Added tRFC checking during Load Mode and Precharge.
* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences.
* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences.
* JMK 02/11/2005 - Changed the display format for numbers to hex.
* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation.
* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error.
* - Renamed parameters file with .vh extension.
* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb
* - Added x32 functionality
* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model
* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION
`timescale 1ns / 1ps
`define sg6T
`define x16
module Ddr (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs);
`include "/home/horia/work/batchelor/v6/prj/xtra/extern/MicronDDRSim/DdrParameters.vh"
// Port Declarations
input Clk;
input Clk_n;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Ba;
input [ADDR_BITS - 1 : 0] Addr;
input [DM_BITS - 1 : 0] Dm;
inout [DQ_BITS - 1 : 0] Dq;
inout [DQS_BITS - 1 : 0] Dqs;
// Internal Wires (fixed width)
wire [31 : 0] Dq_in;
wire [3 : 0] Dqs_in;
wire [3 : 0] Dm_in;
assign Dq_in [DQ_BITS - 1 : 0] = Dq;
assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;
assign Dm_in [DM_BITS - 1 : 0] = Dm;
// Data pair
reg [31 : 0] dq_rise;
reg [3 : 0] dm_rise;
reg [31 : 0] dq_fall;
reg [3 : 0] dm_fall;
reg [7 : 0] dm_pair;
reg [31 : 0] Dq_buf;
// Mode Register
reg [ADDR_BITS - 1 : 0] Mode_reg;
// Internal System Clock
reg CkeZ, Sys_clk;
// Internal Dqs initialize
reg Dqs_int;
// Dqs buffer
reg [DQS_BITS - 1 : 0] Dqs_out;
// Dq buffer
reg [DQ_BITS - 1 : 0] Dq_out;
// Read pipeline variables
reg Read_cmnd [0 : 6];
reg [1 : 0] Read_bank [0 : 6];
reg [COL_BITS - 1 : 0] Read_cols [0 : 6];
// Write pipeline variables
reg Write_cmnd [0 : 3];
reg [1 : 0] Write_bank [0 : 3];
reg [COL_BITS - 1 : 0] Write_cols [0 : 3];
// Auto precharge variables
reg Read_precharge [0 : 3];
reg Write_precharge [0 : 3];
integer Count_precharge [0 : 3];
// Manual precharge variables
reg A10_precharge [0 : 6];
reg [1 : 0] Bank_precharge [0 : 6];
reg Cmnd_precharge [0 : 6];
// Burst terminate variables
reg Cmnd_bst [0 : 6];
// Memory Banks
`ifdef FULL_MEM
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<full_mem_bits)-1];
`else
reg [DQ_BITS - 1 : 0] mem_array [0 : (1<<part_mem_bits)-1];
reg [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];
reg [part_mem_bits : 0] mem_used;
initial mem_used = 0;
`endif
// Dqs edge checking
integer i;
reg [3 :0] expect_pos_dqs;
reg [3 :0] expect_neg_dqs;
// Burst counter
reg [COL_BITS - 1 : 0] Burst_counter;
// Precharge variables
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3;
// Activate variables
reg Act_b0, Act_b1, Act_b2, Act_b3;
// Data IO variables
reg Data_in_enable;
reg Data_out_enable;
// Internal address mux variables
reg [1 : 0] Prev_bank;
reg [1 : 0] Bank_addr;
reg [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;
reg [ADDR_BITS - 1 : 0] Rows_addr;
reg [ADDR_BITS - 1 : 0] B0_row_addr;
reg [ADDR_BITS - 1 : 0] B1_row_addr;
reg [ADDR_BITS - 1 : 0] B2_row_addr;
reg [ADDR_BITS - 1 : 0] B3_row_addr;
// DLL Reset variable
reg DLL_enable;
reg DLL_reset;
reg DLL_done;
integer DLL_count;
integer aref_count;
integer Prech_count;
reg power_up_done;
// Write DQS for tDSS, tDSH, tDQSH, tDQSL checks
wire wdqs_valid = Write_cmnd[2] || Write_cmnd[1] || Data_in_enable;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & Ba[0] & ~Ba[1];
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1];
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire [3:0] burst_length = 1 << (Mode_reg[2:0]);
reg [3:0] read_precharge_truncation;
// CAS Latency Decode
wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4];
// DQS Buffer
assign Dqs = Dqs_out;
// DQ Buffer
assign Dq = Dq_out;
// Timing Check
time MRD_chk;
time RFC_chk;
time RRD_chk;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
time WR_chk0, WR_chk1, WR_chk2, WR_chk3;
initial begin
CkeZ = 1'b0;
Sys_clk = 1'b0;
{Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;
{Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;
Dqs_int = 1'b0;
Dqs_out = {DQS_BITS{1'bz}};
Dq_out = {DQ_BITS{1'bz}};
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
DLL_enable = 1'b0;
DLL_reset = 1'b0;
DLL_done = 1'b0;
DLL_count = 0;
aref_count = 0;
Prech_count = 0;
power_up_done = 0;
MRD_chk = 0;
RFC_chk = 0;
RRD_chk = 0;
{RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;
{RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3} = 0;
{RC_chk0, RC_chk1, RC_chk2, RC_chk3} = 0;
{RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;
{RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;
{WR_chk0, WR_chk1, WR_chk2, WR_chk3} = 0;
$timeformat (-9, 3, " ns", 12);
end
// System Clock
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
// Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high
always @(Cke) begin
if (Cke === 1'b1) begin
if (!((Cs_n) || (~Cs_n & Ras_n & Cas_n & We_n))) begin
$display ("%m: at time %t MEMORY ERROR: You must have a Deselect or NOP command applied", $time);
$display ("%m: when the Clock Enable is brought High.");
end
end
end
// Check the initialization sequence
initial begin
@ (posedge Cke) begin
@ (posedge DLL_enable) begin
aref_count = 0;
@ (posedge DLL_reset) begin
@ (Prech_count) begin
if (aref_count >= 2) begin
if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
power_up_done = 1;
end else begin
aref_count = 0;
@ (aref_count >= 2) begin
if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time);
power_up_done = 1;
end
end
end
end
end
end
end
// Write Memory
task write_mem;
input [full_mem_bits - 1 : 0] addr;
input [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
mem_array[addr] = data;
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i === mem_used) begin
if (i === (1<<part_mem_bits)) begin
$display ("At time %t ERROR: Memory overflow.\n Write to Address %h with Data %h will be lost.\n You must increase the part_mem_bits parameter or define FULL_MEM.", $time, addr, data);
end else begin
mem_used = mem_used + 1;
addr_array[i] = addr;
end
end
mem_array[i] = data;
`endif
end
endtask
// Read Memory
task read_mem;
input [full_mem_bits - 1 : 0] addr;
output [DQ_BITS - 1 : 0] data;
reg [part_mem_bits : 0] i;
begin
`ifdef FULL_MEM
data = mem_array[addr];
`else
begin : loop
for (i = 0; i < mem_used; i = i + 1) begin
if (addr_array[i] === addr) begin
disable loop;
end
end
end
if (i <= mem_used) begin
data = mem_array[i];
end
`endif
end
endtask
// Burst Decode
task Burst_Decode;
begin
// Advance Burst Counter
if (Burst_counter < burst_length) begin
Burst_counter = Burst_counter + 1;
end
// Burst Type
if (Mode_reg[3] === 1'b0) begin // Sequential Burst
Cols_temp = Cols_addr + 1;
end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst
Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2];
Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1];
Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0];
end
// Burst Length
if (burst_length === 2) begin
Cols_addr [0] = Cols_temp [0];
end else if (burst_length === 4) begin
Cols_addr [1 : 0] = Cols_temp [1 : 0];
end else if (burst_length === 8) begin
Cols_addr [2 : 0] = Cols_temp [2 : 0];
end else begin
Cols_addr = Cols_temp;
end
// Data Counter
if (Burst_counter >= burst_length) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
read_precharge_truncation = 4'h0;
end
end
endtask
// Manual Precharge Pipeline
task Manual_Precharge_Pipeline;
begin
// A10 Precharge Pipeline
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = A10_precharge[4];
A10_precharge[4] = A10_precharge[5];
A10_precharge[5] = A10_precharge[6];
A10_precharge[6] = 1'b0;
// Bank Precharge Pipeline
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = Bank_precharge[4];
Bank_precharge[4] = Bank_precharge[5];
Bank_precharge[5] = Bank_precharge[6];
Bank_precharge[6] = 2'b0;
// Command Precharge Pipeline
Cmnd_precharge[0] = Cmnd_precharge[1];
Cmnd_precharge[1] = Cmnd_precharge[2];
Cmnd_precharge[2] = Cmnd_precharge[3];
Cmnd_precharge[3] = Cmnd_precharge[4];
Cmnd_precharge[4] = Cmnd_precharge[5];
Cmnd_precharge[5] = Cmnd_precharge[6];
Cmnd_precharge[6] = 1'b0;
// Terminate a Read if same bank or all banks
if (Cmnd_precharge[0] === 1'b1) begin
if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin
if (Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
read_precharge_truncation = 4'hF;
end
end
end
end
endtask
// Burst Terminate Pipeline
task Burst_Terminate_Pipeline;
begin
// Command Precharge Pipeline
Cmnd_bst[0] = Cmnd_bst[1];
Cmnd_bst[1] = Cmnd_bst[2];
Cmnd_bst[2] = Cmnd_bst[3];
Cmnd_bst[3] = Cmnd_bst[4];
Cmnd_bst[4] = Cmnd_bst[5];
Cmnd_bst[5] = Cmnd_bst[6];
Cmnd_bst[6] = 1'b0;
// Terminate a Read regardless of banks
if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin
Data_out_enable = 1'b0;
end
end
endtask
// Dq and Dqs Drivers
task Dq_Dqs_Drivers;
begin
// read command pipeline
Read_cmnd [0] = Read_cmnd [1];
Read_cmnd [1] = Read_cmnd [2];
Read_cmnd [2] = Read_cmnd [3];
Read_cmnd [3] = Read_cmnd [4];
Read_cmnd [4] = Read_cmnd [5];
Read_cmnd [5] = Read_cmnd [6];
Read_cmnd [6] = 1'b0;
// read bank pipeline
Read_bank [0] = Read_bank [1];
Read_bank [1] = Read_bank [2];
Read_bank [2] = Read_bank [3];
Read_bank [3] = Read_bank [4];
Read_bank [4] = Read_bank [5];
Read_bank [5] = Read_bank [6];
Read_bank [6] = 2'b0;
// read column pipeline
Read_cols [0] = Read_cols [1];
Read_cols [1] = Read_cols [2];
Read_cols [2] = Read_cols [3];
Read_cols [3] = Read_cols [4];
Read_cols [4] = Read_cols [5];
Read_cols [5] = Read_cols [6];
Read_cols [6] = 0;
// Initialize Read command
if (Read_cmnd [0] === 1'b1) begin
Data_out_enable = 1'b1;
Bank_addr = Read_bank [0];
Cols_addr = Read_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row Address Mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("At time %t ERROR: Invalid Bank Address", $time);
endcase
end
// Toggle Dqs during Read command
if (Data_out_enable === 1'b1) begin
Dqs_int = 1'b0;
if (Dqs_out === {DQS_BITS{1'b0}}) begin
Dqs_out = {DQS_BITS{1'b1}};
end else if (Dqs_out === {DQS_BITS{1'b1}}) begin
Dqs_out = {DQS_BITS{1'b0}};
end else begin
Dqs_out = {DQS_BITS{1'b0}};
end
end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin
Dqs_out = {DQS_BITS{1'bz}};
end
// Initialize dqs for Read command
if (Read_cmnd [2] === 1'b1) begin
if (Data_out_enable === 1'b0) begin
Dqs_int = 1'b1;
Dqs_out = {DQS_BITS{1'b0}};
end
end
// Read latch
if (Data_out_enable === 1'b1) begin
// output data
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);
if (DEBUG) begin
$display ("At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);
end
end else begin
Dq_out = {DQ_BITS{1'bz}};
end
end
endtask
// Write FIFO and DM Mask Logic
task Write_FIFO_DM_Mask_Logic;
begin
// Write command pipeline
Write_cmnd [0] = Write_cmnd [1];
Write_cmnd [1] = Write_cmnd [2];
Write_cmnd [2] = Write_cmnd [3];
Write_cmnd [3] = 1'b0;
// Write command pipeline
Write_bank [0] = Write_bank [1];
Write_bank [1] = Write_bank [2];
Write_bank [2] = Write_bank [3];
Write_bank [3] = 2'b0;
// Write column pipeline
Write_cols [0] = Write_cols [1];
Write_cols [1] = Write_cols [2];
Write_cols [2] = Write_cols [3];
Write_cols [3] = {COL_BITS{1'b0}};
// Initialize Write command
if (Write_cmnd [0] === 1'b1) begin
Data_in_enable = 1'b1;
Bank_addr = Write_bank [0];
Cols_addr = Write_cols [0];
Cols_brst = Cols_addr [2 : 0];
Burst_counter = 0;
// Row address mux
case (Bank_addr)
2'd0 : Rows_addr = B0_row_addr;
2'd1 : Rows_addr = B1_row_addr;
2'd2 : Rows_addr = B2_row_addr;
2'd3 : Rows_addr = B3_row_addr;
default : $display ("At time %t ERROR: Invalid Row Address", $time);
endcase
end
// Write data
if (Data_in_enable === 1'b1) begin
// Data Buffer
read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// write negedge Dqs on posedge Sys_clk
if (Sys_clk) begin
if (!dm_fall[0]) begin
Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];
end
if (!dm_fall[1]) begin
Dq_buf [15 : 8] = dq_fall [15 : 8];
end
if (!dm_fall[2]) begin
Dq_buf [23 : 16] = dq_fall [23 : 16];
end
if (!dm_fall[3]) begin
Dq_buf [31 : 24] = dq_fall [31 : 24];
end
if (~&dm_fall) begin
if (DEBUG) begin
$display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
// write posedge Dqs on negedge Sys_clk
end else begin
if (!dm_rise[0]) begin
Dq_buf [ 7 : 0] = dq_rise [ 7 : 0];
end
if (!dm_rise[1]) begin
Dq_buf [15 : 8] = dq_rise [15 : 8];
end
if (!dm_rise[2]) begin
Dq_buf [23 : 16] = dq_rise [23 : 16];
end
if (!dm_rise[3]) begin
Dq_buf [31 : 24] = dq_rise [31 : 24];
end
if (~&dm_rise) begin
if (DEBUG) begin
$display ("At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]);
end
end
end
// Write Data
write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);
// tWR start and tWTR check
if (Sys_clk && &dm_pair === 1'b0) begin
case (Bank_addr)
2'd0 : WR_chk0 = $time;
2'd1 : WR_chk1 = $time;
2'd2 : WR_chk2 = $time;
2'd3 : WR_chk3 = $time;
default : $display ("At time %t ERROR: Invalid Bank Address (tWR)", $time);
endcase
// tWTR check
if (Read_enable === 1'b1) begin
$display ("At time %t ERROR: tWTR violation during Read", $time);
end
end
end
end
endtask
// Auto Precharge Calculation
task Auto_Precharge_Calculation;
begin
// Precharge counter
if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin
Count_precharge [0] = Count_precharge [0] + 1;
end
if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin
Count_precharge [1] = Count_precharge [1] + 1;
end
if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin
Count_precharge [2] = Count_precharge [2] + 1;
end
if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin
Count_precharge [3] = Count_precharge [3] + 1;
end
// Read with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. BL/2 cycles after command
if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
if (Count_precharge[0] >= burst_length/2) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Read_precharge[0] = 1'b0;
end
end
if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
if (Count_precharge[1] >= burst_length/2) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Read_precharge[1] = 1'b0;
end
end
if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
if (Count_precharge[2] >= burst_length/2) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Read_precharge[2] = 1'b0;
end
end
if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
if (Count_precharge[3] >= burst_length/2) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Read_precharge[3] = 1'b0;
end
end
// Write with AutoPrecharge Calculation
// The device start internal precharge when:
// 1. Meet tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command
if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin
if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Write_precharge[0] = 1'b0;
end
end
if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin
if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Write_precharge[1] = 1'b0;
end
end
if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin
if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Write_precharge[2] = 1'b0;
end
end
if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin
if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Write_precharge[3] = 1'b0;
end
end
end
endtask
// DLL Counter
task DLL_Counter;
begin
if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin
DLL_count = DLL_count + 1;
if (DLL_count >= 200) begin
DLL_done = 1'b1;
end
end
end
endtask
// Control Logic
task Control_Logic;
begin
// Auto Refresh
if (Aref_enable === 1'b1) begin
// Display DEBUG Message
if (DEBUG) begin
$display ("At time %t AREF : Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Auto Refresh", $time);
end
// LMR/EMR to Auto Refresh
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Auto Refresh to Auto Refresh
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: All banks must be Precharged before Auto Refresh", $time);
if (!no_halt) $stop (0);
end else begin
aref_count = aref_count + 1;
RFC_chk = $time;
end
end
// Extended Mode Register
if (Ext_mode_enable === 1'b1) begin
if (DEBUG) begin
$display ("At time %t EMR : Extended Mode Register", $time);
end
// Precharge to LMR/EMR
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Extended Mode Register", $time);
end
// LMR/EMR to LMR/EMR
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Extended Mode Register", $time);
end
// Auto Refresh to LMR/EMR
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Extended Mode Register", $time);
end
// Precharge to LMR/EMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time);
if (!no_halt) $stop (0);
end else begin
if (Addr[0] === 1'b0) begin
DLL_enable = 1'b1;
if (DEBUG) begin
$display ("At time %t EMR : Enable DLL", $time);
end
end else begin
DLL_enable = 1'b0;
if (DEBUG) begin
$display ("At time %t EMR : Disable DLL", $time);
end
end
MRD_chk = $time;
end
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
if (DEBUG) begin
$display ("At time %t LMR : Load Mode Register", $time);
end
// Precharge to LMR/EMR
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("At time %t ERROR: tRP violation during Load Mode Register", $time);
end
// LMR/EMR to LMR/EMR
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Auto Refresh to LMR/EMR
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Load Mode Register", $time);
end
// Precharge to LMR/EMR
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("At time %t ERROR: all banks must be Precharged before Load Mode Register", $time);
end else begin
// Register Mode
Mode_reg = Addr;
// DLL Reset
if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin
DLL_reset = 1'b1;
DLL_done = 1'b0;
DLL_count = 0;
end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin
$display ("At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time);
end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin
$display ("At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time);
end
// Burst Length
case (Addr [2 : 0])
3'b001 : $display ("At time %t LMR : Burst Length = 2", $time);
3'b010 : $display ("At time %t LMR : Burst Length = 4", $time);
3'b011 : $display ("At time %t LMR : Burst Length = 8", $time);
default : $display ("At time %t ERROR: Burst Length not supported", $time);
endcase
// CAS Latency
case (Addr [6 : 4])
3'b010 : $display ("At time %t LMR : CAS Latency = 2", $time);
3'b110 : $display ("At time %t LMR : CAS Latency = 2.5", $time);
3'b011 : $display ("At time %t LMR : CAS Latency = 3", $time);
default : $display ("At time %t ERROR: CAS Latency not supported", $time);
endcase
// Record current tMRD time
MRD_chk = $time;
end
end
// Activate Block
if (Active_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time);
end
// Display DEBUG Message
if (DEBUG) begin
$display ("At time %t ACT : Bank = %h, Row = %h", $time, Ba, Addr);
end
// Activate to Activate (different bank)
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba);
end
// LMR/EMR to Activate
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba);
end
// AutoRefresh to Activate
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) ||
(Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin
$display ("At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba);
if (!no_halt) $stop (0);
end else begin
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk0 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk0 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr;
RC_chk0 = $time;
RCD_chk0 = $time;
RAS_chk0 = $time;
RAP_chk0 = $time;
end
// Activate Bank 1
if (Ba === 2'b01 && Pc_b1 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk1 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk1 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr;
RC_chk1 = $time;
RCD_chk1 = $time;
RAS_chk1 = $time;
RAP_chk1 = $time;
end
// Activate Bank 2
if (Ba === 2'b10 && Pc_b2 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk2 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk2 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr;
RC_chk2 = $time;
RCD_chk2 = $time;
RAS_chk2 = $time;
RAP_chk2 = $time;
end
// Activate Bank 3
if (Ba === 2'b11 && Pc_b3 === 1'b1) begin
// Activate to Activate (same bank)
if ($time - RC_chk3 < tRC) begin
$display ("At time %t ERROR: tRC violation during Activate bank %h", $time, Ba);
end
// Precharge to Activate
if ($time - RP_chk3 < tRP) begin
$display ("At time %t ERROR: tRP violation during Activate bank %h", $time, Ba);
end
// Record variables for checking violation
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr;
RC_chk3 = $time;
RCD_chk3 = $time;
RAS_chk3 = $time;
RAP_chk3 = $time;
end
// Record variable for checking violation
RRD_chk = $time;
Prev_bank = Ba;
read_precharge_truncation[Ba] = 1'b0;
end
end
// Precharge Block - consider NOP if bank already precharged or in process of precharging
if (Prech_enable === 1'b1) begin
// Display DEBUG Message
if (DEBUG) begin
$display ("At time %t PRE : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba);
end
// LMR/EMR to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("At time %t ERROR: tMRD violation during Precharge", $time);
end
// AutoRefresh to Precharge
if ($time - RFC_chk < tRFC) begin
$display ("At time %t ERROR: tRFC violation during Precharge", $time);
end
// Precharge bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge Bank
if ($time - RAS_chk0 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk0 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge Bank 1
if ($time - RAS_chk1 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk1 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge Bank 2
if ($time - RAS_chk2 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk2 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Precharge bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge Bank 3
if ($time - RAS_chk3 < tRAS) begin
$display ("At time %t ERROR: tRAS violation during Precharge", $time);
end
// tWR violation check for Write
if ($time - WR_chk3 < tWR) begin
$display ("At time %t ERROR: tWR violation during Precharge", $time);
end
end
// Prech_count is to make sure we have met part of the initialization sequence
Prech_count = Prech_count + 1;
// Pipeline for READ
A10_precharge [cas_latency_x2] = Addr[10];
Bank_precharge[cas_latency_x2] = Ba;
Cmnd_precharge[cas_latency_x2] = 1'b1;
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Display DEBUG Message
if (DEBUG) begin
$display ("At time %t BST : Burst Terminate",$time);
end
if (Data_in_enable === 1'b1) begin
// Illegal to burst terminate a Write
$display ("At time %t ERROR: It's illegal to burst terminate a Write", $time);
if (!no_halt) $stop (0);
end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 ||
// Illegal to burst terminate a Read with Auto Precharge
Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin
$display ("At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time);
if (!no_halt) $stop (0);
end else begin
// Burst Terminate Command Pipeline for Read
Cmnd_bst[cas_latency_x2] = 1'b1;
end
end
// Read Command
if (Read_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time);
end
// Check for DLL reset before Read
if (DLL_reset === 1 && DLL_done === 0) begin
$display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count);
end
// Display DEBUG Message
if (DEBUG) begin
$display ("At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]});
end
// Terminate a Write
if (Data_in_enable === 1'b1) begin
Data_in_enable = 1'b0;
end
// Activate to Read without Auto Precharge
if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
(Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
$display("At time %t ERROR: tRCD violation during Read", $time);
end
// Activate to Read with Auto Precharge
if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) ||
(Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin
$display ("At time %t ERROR: tRAP violation during Read", $time);
end
// Interrupt a Read with Auto Precharge (same bank only)
if (Read_precharge [Ba] === 1'b1) begin
$display ("At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time);
if (!no_halt) $stop (0);
// Cancel Auto Precharge
if (Addr[10] === 1'b0) begin
Read_precharge [Ba]= 1'b0;
end
end
// Activate to Read
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("At time %t ERROR: Bank is not Activated for Read", $time);
if (!no_halt) $stop (0);
end else begin
// CAS Latency pipeline
Read_cmnd[cas_latency_x2] = 1'b1;
Read_bank[cas_latency_x2] = Ba;
Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Auto Precharge
if (Addr[10] === 1'b1) begin
Read_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
end
end
end
// Write Command
if (Write_enable === 1'b1) begin
if (!(power_up_done)) begin
$display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time);
if (!no_halt) $stop (0);
end
// display DEBUG message
if (DEBUG) begin
$display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]});
end
// Activate to Write
if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) ||
(Ba === 2'b01 && $time - RCD_chk1 < tRCD) ||
(Ba === 2'b10 && $time - RCD_chk2 < tRCD) ||
(Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin
$display("At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba);
end
// Read to Write
if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] ||
Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin
if (Data_out_enable || read_precharge_truncation[Ba]) begin
$display("At time %t ERROR: Read to Write violation", $time);
end
end
// Interrupt a Write with Auto Precharge (same bank only)
if (Write_precharge [Ba] === 1'b1) begin
$display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time);
if (!no_halt) $stop (0);
// Cancel Auto Precharge
if (Addr[10] === 1'b0) begin
Write_precharge [Ba]= 1'b0;
end
end
// Activate to Write
if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) ||
(Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin
$display("At time %t ERROR: Bank is not Activated for Write", $time);
if (!no_halt) $stop (0);
end else begin
// Pipeline for Write
Write_cmnd [3] = 1'b1;
Write_bank [3] = Ba;
Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]};
// Auto Precharge
if (Addr[10] === 1'b1) begin
Write_precharge [Ba]= 1'b1;
Count_precharge [Ba]= 0;
end
end
end
end
endtask
task check_neg_dqs;
begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_neg_dqs[i]) begin
$display ("At time %t ERROR: Negative DQS[%1d] transition required.", $time, i);
end
expect_neg_dqs[i] = 1'b1;
end
end else begin
expect_pos_dqs = 0;
expect_neg_dqs = 0;
end
end
endtask
task check_pos_dqs;
begin
if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin
for (i=0; i<DQS_BITS; i=i+1) begin
if (expect_pos_dqs[i]) begin
$display ("At time %t ERROR: Positive DQS[%1d] transition required.", $time, i);
end
expect_pos_dqs[i] = 1'b1;
end
end else begin
expect_pos_dqs = 0;
expect_neg_dqs = 0;
end
end
endtask
// Main Logic
always @ (posedge Sys_clk) begin
Manual_Precharge_Pipeline;
Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
check_neg_dqs;
Auto_Precharge_Calculation;
DLL_Counter;
Control_Logic;
end
always @ (negedge Sys_clk) begin
Manual_Precharge_Pipeline;
Burst_Terminate_Pipeline;
Dq_Dqs_Drivers;
Write_FIFO_DM_Mask_Logic;
Burst_Decode;
check_pos_dqs;
end
// Dqs Receiver
always @ (posedge Dqs_in[0]) begin
// Latch data at posedge Dqs
dq_rise[7 : 0] = Dq_in[7 : 0];
dm_rise[0] = Dm_in[0];
expect_pos_dqs[0] = 0;
end
always @ (posedge Dqs_in[1]) begin
// Latch data at posedge Dqs
dq_rise[15 : 8] = Dq_in[15 : 8];
dm_rise[1] = Dm_in [1];
expect_pos_dqs[1] = 0;
end
always @ (posedge Dqs_in[2]) begin
// Latch data at posedge Dqs
dq_rise[23 : 16] = Dq_in[23 : 16];
dm_rise[2] = Dm_in [2];
expect_pos_dqs[2] = 0;
end
always @ (posedge Dqs_in[3]) begin
// Latch data at posedge Dqs
dq_rise[31 : 24] = Dq_in[31 : 24];
dm_rise[3] = Dm_in [3];
expect_pos_dqs[3] = 0;
end
always @ (negedge Dqs_in[0]) begin
// Latch data at negedge Dqs
dq_fall[7 : 0] = Dq_in[7 : 0];
dm_fall[0] = Dm_in[0];
dm_pair[1:0] = {dm_rise[0], dm_fall[0]};
expect_neg_dqs[0] = 0;
end
always @ (negedge Dqs_in[1]) begin
// Latch data at negedge Dqs
dq_fall[15: 8] = Dq_in[15 : 8];
dm_fall[1] = Dm_in[1];
dm_pair[3:2] = {dm_rise[1], dm_fall[1]};
expect_neg_dqs[1] = 0;
end
always @ (negedge Dqs_in[2]) begin
// Latch data at negedge Dqs
dq_fall[23: 16] = Dq_in[23 : 16];
dm_fall[2] = Dm_in[2];
dm_pair[5:4] = {dm_rise[2], dm_fall[2]};
expect_neg_dqs[2] = 0;
end
always @ (negedge Dqs_in[3]) begin
// Latch data at negedge Dqs
dq_fall[31: 24] = Dq_in[31 : 24];
dm_fall[3] = Dm_in[3];
dm_pair[7:6] = {dm_rise[3], dm_fall[3]};
expect_neg_dqs[3] = 0;
end
specify
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg5B // specparams for -5B (CL = 3)
specparam tDSS = 1.0; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.0; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.750; // tIH ns Input Hold Time
specparam tIS = 0.750; // tIS ns Input Setup Time
specparam tDQSH = 1.75; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 1.75; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`else `ifdef sg6 // specparams for -6 (CL = 2.5)
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.750; // tIH ns Input Hold Time
specparam tIS = 0.750; // tIS ns Input Setup Time
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`else `ifdef sg6T // specparams for -6 (CL = 2.5)
specparam tDSS = 1.2; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.2; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.750; // tIH ns Input Hold Time
specparam tIS = 0.750; // tIS ns Input Setup Time
specparam tDQSH = 2.1; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.1; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`else `ifdef sg75 // specparams for -75E (CL = 2)
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.900; // tIH ns Input Hold Time
specparam tIS = 0.900; // tIS ns Input Setup Time
specparam tDQSH = 2.625; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.625; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`else `ifdef sg75E // specparams for -75E (CL = 2)
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.900; // tIH ns Input Hold Time
specparam tIS = 0.900; // tIS ns Input Setup Time
specparam tDQSH = 2.625; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.625; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`else `define sg75Z // specparams for -75Z (CL = 2)
specparam tDSS = 1.5; // tDSS ns DQS falling edge to CLK rising (setup time) = 0.2*tCK
specparam tDSH = 1.5; // tDSH ns DQS falling edge from CLK rising (hold time) = 0.2*tCK
specparam tIH = 0.900; // tIH ns Input Hold Time
specparam tIS = 0.900; // tIS ns Input Setup Time
specparam tDQSH = 2.625; // tDQSH ns DQS input High Pulse Width = 0.35*tCK
specparam tDQSL = 2.625; // tDQSL ns DQS input Low Pulse Width = 0.35*tCK
`endif `endif `endif `endif `endif
$width (posedge Dqs_in[0] &&& wdqs_valid, tDQSH);
$width (posedge Dqs_in[1] &&& wdqs_valid, tDQSH);
$width (negedge Dqs_in[0] &&& wdqs_valid, tDQSL);
$width (negedge Dqs_in[1] &&& wdqs_valid, tDQSL);
$setuphold(posedge Clk, Cke, tIS, tIH);
$setuphold(posedge Clk, Cs_n, tIS, tIH);
$setuphold(posedge Clk, Cas_n, tIS, tIH);
$setuphold(posedge Clk, Ras_n, tIS, tIH);
$setuphold(posedge Clk, We_n, tIS, tIH);
$setuphold(posedge Clk, Addr, tIS, tIH);
$setuphold(posedge Clk, Ba, tIS, tIH);
$setuphold(posedge Clk, negedge Dqs &&& wdqs_valid, tDSS, tDSH);
endspecify
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 17:57:16 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode funcsim
// /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul8_8/mul8_8_sim_netlist.v
// Design : mul8_8
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "mul8_8,mult_gen_v12_0_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
(* NotValidForBitStream *)
module mul8_8
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [7:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [7:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [15:0]P;
wire [7:0]A;
wire [7:0]B;
wire CLK;
wire [15:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "8" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "8" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "15" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mul8_8_mult_gen_v12_0_12 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* C_A_TYPE = "1" *) (* C_A_WIDTH = "8" *) (* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *) (* C_B_WIDTH = "8" *) (* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_HAS_CE = "0" *) (* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_LATENCY = "3" *) (* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *) (* C_OPTIMIZE_GOAL = "1" *) (* C_OUT_HIGH = "15" *)
(* C_OUT_LOW = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *) (* C_XDEVICEFAMILY = "kintexu" *) (* ORIG_REF_NAME = "mult_gen_v12_0_12" *)
(* downgradeipidentifiedwarnings = "yes" *)
module mul8_8_mult_gen_v12_0_12
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [7:0]A;
input [7:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [15:0]P;
output [47:0]PCASC;
wire \<const0> ;
wire [7:0]A;
wire [7:0]B;
wire CLK;
wire [15:0]P;
wire [47:0]NLW_i_mult_PCASC_UNCONNECTED;
wire [1:0]NLW_i_mult_ZERO_DETECT_UNCONNECTED;
assign PCASC[47] = \<const0> ;
assign PCASC[46] = \<const0> ;
assign PCASC[45] = \<const0> ;
assign PCASC[44] = \<const0> ;
assign PCASC[43] = \<const0> ;
assign PCASC[42] = \<const0> ;
assign PCASC[41] = \<const0> ;
assign PCASC[40] = \<const0> ;
assign PCASC[39] = \<const0> ;
assign PCASC[38] = \<const0> ;
assign PCASC[37] = \<const0> ;
assign PCASC[36] = \<const0> ;
assign PCASC[35] = \<const0> ;
assign PCASC[34] = \<const0> ;
assign PCASC[33] = \<const0> ;
assign PCASC[32] = \<const0> ;
assign PCASC[31] = \<const0> ;
assign PCASC[30] = \<const0> ;
assign PCASC[29] = \<const0> ;
assign PCASC[28] = \<const0> ;
assign PCASC[27] = \<const0> ;
assign PCASC[26] = \<const0> ;
assign PCASC[25] = \<const0> ;
assign PCASC[24] = \<const0> ;
assign PCASC[23] = \<const0> ;
assign PCASC[22] = \<const0> ;
assign PCASC[21] = \<const0> ;
assign PCASC[20] = \<const0> ;
assign PCASC[19] = \<const0> ;
assign PCASC[18] = \<const0> ;
assign PCASC[17] = \<const0> ;
assign PCASC[16] = \<const0> ;
assign PCASC[15] = \<const0> ;
assign PCASC[14] = \<const0> ;
assign PCASC[13] = \<const0> ;
assign PCASC[12] = \<const0> ;
assign PCASC[11] = \<const0> ;
assign PCASC[10] = \<const0> ;
assign PCASC[9] = \<const0> ;
assign PCASC[8] = \<const0> ;
assign PCASC[7] = \<const0> ;
assign PCASC[6] = \<const0> ;
assign PCASC[5] = \<const0> ;
assign PCASC[4] = \<const0> ;
assign PCASC[3] = \<const0> ;
assign PCASC[2] = \<const0> ;
assign PCASC[1] = \<const0> ;
assign PCASC[0] = \<const0> ;
assign ZERO_DETECT[1] = \<const0> ;
assign ZERO_DETECT[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "8" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "8" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "3" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "15" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mul8_8_mult_gen_v12_0_12_viv i_mult
(.A(A),
.B(B),
.CE(1'b0),
.CLK(CLK),
.P(P),
.PCASC(NLW_i_mult_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_i_mult_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
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r9Ud/QoIy9qvtjGpRDpZQ347o5zB218wMHXn8mrJZHsoj9c0HQJPCO10wEM7wHAdP2IEs+BVIYWF
Au4N2s1iPAx3ySMWRcVQscnupm0aQhJ+EOtft5BGbtKxfhfj8i8add2GK7M1ZSxjj2QAg0+E7IWp
AGFtzbNT8st/nE5rxC6iDT12rwkxKxEdhMDS5Nc0Hvks0GR9ej5tk7mLjHgmNDgj25mAmFrOvig8
arVSxZpQxt03Cu4M0yJTrn+SZl2/tkAMi2q8jTtcnoT6nKfb+i2zShMMUQyS35Vdvef/x1FlgMT/
8oHLUkqSEtUn9oXcQDI=
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module platform(
input CLK_EXT,
output BUZZER_,
// control panel
input RXD,
output TXD,
output [7:0] DIG,
output [7:0] SEG,
// RAM
output SRAM_CE_, SRAM_OE_, SRAM_WE_, SRAM_UB_, SRAM_LB_,
output [17:0] SRAM_A,
inout [15:0] SRAM_D,
output F_CS_, F_OE_, F_WE_
);
localparam CLK_EXT_HZ = 50_000_000;
// --- MERA-400f ---------------------------------------------------------
wire sram_ce, sram_oe, sram_we;
wire [0:15] w;
wire [10:0] rotary_bus;
wire [0:9] indicators;
mera400f #(
.CLK_EXT_HZ(CLK_EXT_HZ)
) MERA400F (
.clk_ext(CLK_EXT),
.rxd(RXD),
.txd(TXD),
.ram_ce(sram_ce),
.ram_oe(sram_oe),
.ram_we(sram_we),
.ram_a(SRAM_A),
.ram_d(SRAM_D),
.w(w),
.rotary_bus(rotary_bus),
.indicators(indicators)
);
// --- External devices --------------------------------------------------
// silence the buzzer
assign BUZZER_ = 1'b1;
// disable flash, which uses the same D and A buses as sram
assign F_CS_ = 1'b1;
assign F_OE_ = 1'b1;
assign F_WE_ = 1'b1;
// always use full 16-bit word
assign SRAM_LB_ = 1'b0;
assign SRAM_UB_ = 1'b0;
assign SRAM_CE_ = ~sram_ce;
assign SRAM_OE_ = ~sram_oe;
assign SRAM_WE_ = ~sram_we;
// --- 7-segment display
display DISPLAY(
.clk_sys(CLK_EXT),
.w(w),
.rotary_bus(rotary_bus),
.indicators(indicators),
.seg(SEG),
.dig(DIG)
);
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Oct 19 10:57:11 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0],probe26[3:0],probe27[3:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [8:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [7:0]probe24;
input [0:0]probe25;
input [3:0]probe26;
input [3:0]probe27;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__AND3B_FUNCTIONAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_FUNCTIONAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_misc_jbus.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_misc_jbus (/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From cluster_header of cluster_header.v
output dbginit_l; // From cluster_header of cluster_header.v
output rclk; // From cluster_header of cluster_header.v
output so; // From cluster_header of cluster_header.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To cluster_header of cluster_header.v
input arst_l; // To cluster_header of cluster_header.v
input cluster_cken; // To cluster_header of cluster_header.v
input gclk; // To cluster_header of cluster_header.v
input gdbginit_l; // To cluster_header of cluster_header.v
input grst_l; // To cluster_header of cluster_header.v
input se; // To cluster_header of cluster_header.v
input si; // To cluster_header of cluster_header.v
// End of automatics
cluster_header cluster_header
(/*AUTOINST*/
// Outputs
.dbginit_l (dbginit_l),
.cluster_grst_l (cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken (cluster_cken),
.arst_l (arst_l),
.grst_l (grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l),
.si (si),
.se (se));
endmodule
// Local Variables:
// verilog-library-directories:("../../../common/rtl")
// verilog-auto-sense-defines-constant:t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_no_pg/sky130_fd_sc_hs__u_df_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_21 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_BEHAVIORAL_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 15:35:47 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Pointer/Pointer_funcsim.v
// Design : Pointer
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "Pointer,blk_mem_gen_v8_2,{}" *)
(* core_generation_info = "Pointer,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=Pointer.mif,C_INIT_FILE=Pointer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=28,C_READ_WIDTH_A=28,C_WRITE_DEPTH_A=30,C_READ_DEPTH_A=30,C_ADDRA_WIDTH=5,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=28,C_READ_WIDTH_B=28,C_WRITE_DEPTH_B=30,C_READ_DEPTH_B=30,C_ADDRB_WIDTH=5,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.2088 mW}" *)
(* NotValidForBitStream *)
module Pointer
(clka,
addra,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
input [4:0]addra;
output [27:0]douta;
wire [4:0]addra;
wire clka;
wire [27:0]douta;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [27:0]NLW_U0_doutb_UNCONNECTED;
wire [4:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [4:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [27:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "5" *)
(* C_ADDRB_WIDTH = "5" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.2088 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "Pointer.mem" *)
(* C_INIT_FILE_NAME = "Pointer.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "3" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "30" *)
(* C_READ_DEPTH_B = "30" *)
(* C_READ_WIDTH_A = "28" *)
(* C_READ_WIDTH_B = "28" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "30" *)
(* C_WRITE_DEPTH_B = "30" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "28" *)
(* C_WRITE_WIDTH_B = "28" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
Pointer_blk_mem_gen_v8_2__parameterized0 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[27:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[4:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[4:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[27:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.wea(1'b0),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module Pointer_blk_mem_gen_generic_cstr
(douta,
clka,
addra);
output [27:0]douta;
input clka;
input [4:0]addra;
wire [4:0]addra;
wire clka;
wire [27:0]douta;
Pointer_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module Pointer_blk_mem_gen_prim_width
(douta,
clka,
addra);
output [27:0]douta;
input clka;
input [4:0]addra;
wire [4:0]addra;
wire clka;
wire [27:0]douta;
Pointer_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module Pointer_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra);
output [27:0]douta;
input clka;
input [4:0]addra;
wire [4:0]addra;
wire clka;
wire [27:0]douta;
wire \n_0_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
wire \n_16_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
wire \n_24_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
wire \n_32_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
wire \n_33_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
wire \n_34_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
wire \n_35_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
wire \n_8_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h7F7F00007F7C00007F7000007F4000007E0000007C0000007000000040000000),
.INIT_01(256'h7F7F7F7E7F7F7F7E7F7F7F787F7F7F607F7F7F007F7F7E007F7F78007F7F6000),
.INIT_02(256'h7F7C00007F7F00007F7F60007F7F78007F7F7E007F7F7F407F7F7F607F7F7F78),
.INIT_03(256'h000000000000000040000000700000007C0000007F0000007F4000007F700000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,1'b0,1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\n_0_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,douta[13:7],\n_8_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,douta[6:0]}),
.DOBDO({\n_16_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,douta[27:21],\n_24_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,douta[20:14]}),
.DOPADOP({\n_32_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_33_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram }),
.DOPBDOP({\n_34_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram ,\n_35_DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram }),
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module Pointer_blk_mem_gen_top
(douta,
clka,
addra);
output [27:0]douta;
input clka;
input [4:0]addra;
wire [4:0]addra;
wire clka;
wire [27:0]douta;
Pointer_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* C_FAMILY = "artix7" *) (* C_XDEVICEFAMILY = "artix7" *)
(* C_ELABORATION_DIR = "./" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_SLAVE_TYPE = "0" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *) (* C_HAS_AXI_ID = "0" *) (* C_AXI_ID_WIDTH = "4" *)
(* C_MEM_TYPE = "3" *) (* C_BYTE_SIZE = "9" *) (* C_ALGORITHM = "1" *)
(* C_PRIM_TYPE = "1" *) (* C_LOAD_INIT_FILE = "1" *) (* C_INIT_FILE_NAME = "Pointer.mif" *)
(* C_INIT_FILE = "Pointer.mem" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_DEFAULT_DATA = "0" *)
(* C_HAS_RSTA = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RSTRAM_A = "0" *)
(* C_INITA_VAL = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "28" *) (* C_READ_WIDTH_A = "28" *) (* C_WRITE_DEPTH_A = "30" *)
(* C_READ_DEPTH_A = "30" *) (* C_ADDRA_WIDTH = "5" *) (* C_HAS_RSTB = "0" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_RSTRAM_B = "0" *) (* C_INITB_VAL = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_REGCEB = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_WEB_WIDTH = "1" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_B = "28" *)
(* C_READ_WIDTH_B = "28" *) (* C_WRITE_DEPTH_B = "30" *) (* C_READ_DEPTH_B = "30" *)
(* C_ADDRB_WIDTH = "5" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_ECC = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_HAS_INJECTERR = "0" *)
(* C_SIM_COLLISION_CHECK = "ALL" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_COUNT_36K_BRAM = "0" *)
(* C_COUNT_18K_BRAM = "1" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.2088 mW" *) (* downgradeipidentifiedwarnings = "yes" *)
module Pointer_blk_mem_gen_v8_2__parameterized0
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [4:0]addra;
input [27:0]dina;
output [27:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [4:0]addrb;
input [27:0]dinb;
output [27:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [4:0]rdaddrecc;
input sleep;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [27:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [27:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [4:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [4:0]addra;
wire [4:0]addrb;
wire clka;
wire clkb;
wire [27:0]dina;
wire [27:0]dinb;
wire [27:0]douta;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [27:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign doutb[27] = \<const0> ;
assign doutb[26] = \<const0> ;
assign doutb[25] = \<const0> ;
assign doutb[24] = \<const0> ;
assign doutb[23] = \<const0> ;
assign doutb[22] = \<const0> ;
assign doutb[21] = \<const0> ;
assign doutb[20] = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
Pointer_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module Pointer_blk_mem_gen_v8_2_synth
(douta,
clka,
addra);
output [27:0]douta;
input clka;
input [4:0]addra;
wire [4:0]addra;
wire clka;
wire [27:0]douta;
Pointer_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND2_PP_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_PP_BLACKBOX_V
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
//Date : Tue Sep 19 09:36:37 2017
//Host : DarkCube running 64-bit major release (build 9200)
//Command : generate_target bd_350b_wrapper.bd
//Design : bd_350b_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module bd_350b_wrapper
(SLOT_0_AXI_araddr,
SLOT_0_AXI_arready,
SLOT_0_AXI_arvalid,
SLOT_0_AXI_awaddr,
SLOT_0_AXI_awready,
SLOT_0_AXI_awvalid,
SLOT_0_AXI_bready,
SLOT_0_AXI_bresp,
SLOT_0_AXI_bvalid,
SLOT_0_AXI_rdata,
SLOT_0_AXI_rready,
SLOT_0_AXI_rresp,
SLOT_0_AXI_rvalid,
SLOT_0_AXI_wdata,
SLOT_0_AXI_wready,
SLOT_0_AXI_wstrb,
SLOT_0_AXI_wvalid,
SLOT_1_GPIO_tri_o,
SLOT_2_AXI_araddr,
SLOT_2_AXI_arburst,
SLOT_2_AXI_arcache,
SLOT_2_AXI_arid,
SLOT_2_AXI_arlen,
SLOT_2_AXI_arlock,
SLOT_2_AXI_arprot,
SLOT_2_AXI_arqos,
SLOT_2_AXI_arready,
SLOT_2_AXI_arsize,
SLOT_2_AXI_arvalid,
SLOT_2_AXI_awaddr,
SLOT_2_AXI_awburst,
SLOT_2_AXI_awcache,
SLOT_2_AXI_awid,
SLOT_2_AXI_awlen,
SLOT_2_AXI_awlock,
SLOT_2_AXI_awprot,
SLOT_2_AXI_awqos,
SLOT_2_AXI_awready,
SLOT_2_AXI_awsize,
SLOT_2_AXI_awvalid,
SLOT_2_AXI_bid,
SLOT_2_AXI_bready,
SLOT_2_AXI_bresp,
SLOT_2_AXI_bvalid,
SLOT_2_AXI_rdata,
SLOT_2_AXI_rid,
SLOT_2_AXI_rlast,
SLOT_2_AXI_rready,
SLOT_2_AXI_rresp,
SLOT_2_AXI_rvalid,
SLOT_2_AXI_wdata,
SLOT_2_AXI_wlast,
SLOT_2_AXI_wready,
SLOT_2_AXI_wstrb,
SLOT_2_AXI_wvalid,
TRIG_IN_ack,
TRIG_IN_trig,
TRIG_OUT_ack,
TRIG_OUT_trig,
clk,
resetn);
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arready;
input SLOT_0_AXI_arvalid;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awready;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_bready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input [31:0]SLOT_0_AXI_rdata;
input SLOT_0_AXI_rready;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input [31:0]SLOT_0_AXI_wdata;
input SLOT_0_AXI_wready;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input [7:0]SLOT_1_GPIO_tri_o;
input [15:0]SLOT_2_AXI_araddr;
input [1:0]SLOT_2_AXI_arburst;
input [3:0]SLOT_2_AXI_arcache;
input [11:0]SLOT_2_AXI_arid;
input [7:0]SLOT_2_AXI_arlen;
input [0:0]SLOT_2_AXI_arlock;
input [2:0]SLOT_2_AXI_arprot;
input [3:0]SLOT_2_AXI_arqos;
input SLOT_2_AXI_arready;
input [2:0]SLOT_2_AXI_arsize;
input SLOT_2_AXI_arvalid;
input [15:0]SLOT_2_AXI_awaddr;
input [1:0]SLOT_2_AXI_awburst;
input [3:0]SLOT_2_AXI_awcache;
input [11:0]SLOT_2_AXI_awid;
input [7:0]SLOT_2_AXI_awlen;
input [0:0]SLOT_2_AXI_awlock;
input [2:0]SLOT_2_AXI_awprot;
input [3:0]SLOT_2_AXI_awqos;
input SLOT_2_AXI_awready;
input [2:0]SLOT_2_AXI_awsize;
input SLOT_2_AXI_awvalid;
input [11:0]SLOT_2_AXI_bid;
input SLOT_2_AXI_bready;
input [1:0]SLOT_2_AXI_bresp;
input SLOT_2_AXI_bvalid;
input [31:0]SLOT_2_AXI_rdata;
input [11:0]SLOT_2_AXI_rid;
input SLOT_2_AXI_rlast;
input SLOT_2_AXI_rready;
input [1:0]SLOT_2_AXI_rresp;
input SLOT_2_AXI_rvalid;
input [31:0]SLOT_2_AXI_wdata;
input SLOT_2_AXI_wlast;
input SLOT_2_AXI_wready;
input [3:0]SLOT_2_AXI_wstrb;
input SLOT_2_AXI_wvalid;
output [0:0]TRIG_IN_ack;
input [0:0]TRIG_IN_trig;
input [0:0]TRIG_OUT_ack;
output [0:0]TRIG_OUT_trig;
input clk;
input resetn;
wire [8:0]SLOT_0_AXI_araddr;
wire SLOT_0_AXI_arready;
wire SLOT_0_AXI_arvalid;
wire [8:0]SLOT_0_AXI_awaddr;
wire SLOT_0_AXI_awready;
wire SLOT_0_AXI_awvalid;
wire SLOT_0_AXI_bready;
wire [1:0]SLOT_0_AXI_bresp;
wire SLOT_0_AXI_bvalid;
wire [31:0]SLOT_0_AXI_rdata;
wire SLOT_0_AXI_rready;
wire [1:0]SLOT_0_AXI_rresp;
wire SLOT_0_AXI_rvalid;
wire [31:0]SLOT_0_AXI_wdata;
wire SLOT_0_AXI_wready;
wire [3:0]SLOT_0_AXI_wstrb;
wire SLOT_0_AXI_wvalid;
wire [7:0]SLOT_1_GPIO_tri_o;
wire [15:0]SLOT_2_AXI_araddr;
wire [1:0]SLOT_2_AXI_arburst;
wire [3:0]SLOT_2_AXI_arcache;
wire [11:0]SLOT_2_AXI_arid;
wire [7:0]SLOT_2_AXI_arlen;
wire [0:0]SLOT_2_AXI_arlock;
wire [2:0]SLOT_2_AXI_arprot;
wire [3:0]SLOT_2_AXI_arqos;
wire SLOT_2_AXI_arready;
wire [2:0]SLOT_2_AXI_arsize;
wire SLOT_2_AXI_arvalid;
wire [15:0]SLOT_2_AXI_awaddr;
wire [1:0]SLOT_2_AXI_awburst;
wire [3:0]SLOT_2_AXI_awcache;
wire [11:0]SLOT_2_AXI_awid;
wire [7:0]SLOT_2_AXI_awlen;
wire [0:0]SLOT_2_AXI_awlock;
wire [2:0]SLOT_2_AXI_awprot;
wire [3:0]SLOT_2_AXI_awqos;
wire SLOT_2_AXI_awready;
wire [2:0]SLOT_2_AXI_awsize;
wire SLOT_2_AXI_awvalid;
wire [11:0]SLOT_2_AXI_bid;
wire SLOT_2_AXI_bready;
wire [1:0]SLOT_2_AXI_bresp;
wire SLOT_2_AXI_bvalid;
wire [31:0]SLOT_2_AXI_rdata;
wire [11:0]SLOT_2_AXI_rid;
wire SLOT_2_AXI_rlast;
wire SLOT_2_AXI_rready;
wire [1:0]SLOT_2_AXI_rresp;
wire SLOT_2_AXI_rvalid;
wire [31:0]SLOT_2_AXI_wdata;
wire SLOT_2_AXI_wlast;
wire SLOT_2_AXI_wready;
wire [3:0]SLOT_2_AXI_wstrb;
wire SLOT_2_AXI_wvalid;
wire [0:0]TRIG_IN_ack;
wire [0:0]TRIG_IN_trig;
wire [0:0]TRIG_OUT_ack;
wire [0:0]TRIG_OUT_trig;
wire clk;
wire resetn;
bd_350b bd_350b_i
(.SLOT_0_AXI_araddr(SLOT_0_AXI_araddr),
.SLOT_0_AXI_arready(SLOT_0_AXI_arready),
.SLOT_0_AXI_arvalid(SLOT_0_AXI_arvalid),
.SLOT_0_AXI_awaddr(SLOT_0_AXI_awaddr),
.SLOT_0_AXI_awready(SLOT_0_AXI_awready),
.SLOT_0_AXI_awvalid(SLOT_0_AXI_awvalid),
.SLOT_0_AXI_bready(SLOT_0_AXI_bready),
.SLOT_0_AXI_bresp(SLOT_0_AXI_bresp),
.SLOT_0_AXI_bvalid(SLOT_0_AXI_bvalid),
.SLOT_0_AXI_rdata(SLOT_0_AXI_rdata),
.SLOT_0_AXI_rready(SLOT_0_AXI_rready),
.SLOT_0_AXI_rresp(SLOT_0_AXI_rresp),
.SLOT_0_AXI_rvalid(SLOT_0_AXI_rvalid),
.SLOT_0_AXI_wdata(SLOT_0_AXI_wdata),
.SLOT_0_AXI_wready(SLOT_0_AXI_wready),
.SLOT_0_AXI_wstrb(SLOT_0_AXI_wstrb),
.SLOT_0_AXI_wvalid(SLOT_0_AXI_wvalid),
.SLOT_1_GPIO_tri_o(SLOT_1_GPIO_tri_o),
.SLOT_2_AXI_araddr(SLOT_2_AXI_araddr),
.SLOT_2_AXI_arburst(SLOT_2_AXI_arburst),
.SLOT_2_AXI_arcache(SLOT_2_AXI_arcache),
.SLOT_2_AXI_arid(SLOT_2_AXI_arid),
.SLOT_2_AXI_arlen(SLOT_2_AXI_arlen),
.SLOT_2_AXI_arlock(SLOT_2_AXI_arlock),
.SLOT_2_AXI_arprot(SLOT_2_AXI_arprot),
.SLOT_2_AXI_arqos(SLOT_2_AXI_arqos),
.SLOT_2_AXI_arready(SLOT_2_AXI_arready),
.SLOT_2_AXI_arsize(SLOT_2_AXI_arsize),
.SLOT_2_AXI_arvalid(SLOT_2_AXI_arvalid),
.SLOT_2_AXI_awaddr(SLOT_2_AXI_awaddr),
.SLOT_2_AXI_awburst(SLOT_2_AXI_awburst),
.SLOT_2_AXI_awcache(SLOT_2_AXI_awcache),
.SLOT_2_AXI_awid(SLOT_2_AXI_awid),
.SLOT_2_AXI_awlen(SLOT_2_AXI_awlen),
.SLOT_2_AXI_awlock(SLOT_2_AXI_awlock),
.SLOT_2_AXI_awprot(SLOT_2_AXI_awprot),
.SLOT_2_AXI_awqos(SLOT_2_AXI_awqos),
.SLOT_2_AXI_awready(SLOT_2_AXI_awready),
.SLOT_2_AXI_awsize(SLOT_2_AXI_awsize),
.SLOT_2_AXI_awvalid(SLOT_2_AXI_awvalid),
.SLOT_2_AXI_bid(SLOT_2_AXI_bid),
.SLOT_2_AXI_bready(SLOT_2_AXI_bready),
.SLOT_2_AXI_bresp(SLOT_2_AXI_bresp),
.SLOT_2_AXI_bvalid(SLOT_2_AXI_bvalid),
.SLOT_2_AXI_rdata(SLOT_2_AXI_rdata),
.SLOT_2_AXI_rid(SLOT_2_AXI_rid),
.SLOT_2_AXI_rlast(SLOT_2_AXI_rlast),
.SLOT_2_AXI_rready(SLOT_2_AXI_rready),
.SLOT_2_AXI_rresp(SLOT_2_AXI_rresp),
.SLOT_2_AXI_rvalid(SLOT_2_AXI_rvalid),
.SLOT_2_AXI_wdata(SLOT_2_AXI_wdata),
.SLOT_2_AXI_wlast(SLOT_2_AXI_wlast),
.SLOT_2_AXI_wready(SLOT_2_AXI_wready),
.SLOT_2_AXI_wstrb(SLOT_2_AXI_wstrb),
.SLOT_2_AXI_wvalid(SLOT_2_AXI_wvalid),
.TRIG_IN_ack(TRIG_IN_ack),
.TRIG_IN_trig(TRIG_IN_trig),
.TRIG_OUT_ack(TRIG_OUT_ack),
.TRIG_OUT_trig(TRIG_OUT_trig),
.clk(clk),
.resetn(resetn));
endmodule
|
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