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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream arbitrated multiplexer
*/
module axis_arb_mux #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [S_COUNT-1:0] s_axis_tvalid,
output wire [S_COUNT-1:0] s_axis_tready,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI Stream output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser
);
parameter CL_S_COUNT = $clog2(S_COUNT);
wire [S_COUNT-1:0] request;
wire [S_COUNT-1:0] acknowledge;
wire [S_COUNT-1:0] grant;
wire grant_valid;
wire [CL_S_COUNT-1:0] grant_encoded;
// internal datapath
reg [DATA_WIDTH-1:0] m_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg [ID_WIDTH-1:0] m_axis_tid_int;
reg [DEST_WIDTH-1:0] m_axis_tdest_int;
reg [USER_WIDTH-1:0] m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = (m_axis_tready_int_reg && grant_valid) << grant_encoded;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_axis_tvalid[grant_encoded];
wire current_s_tready = s_axis_tready[grant_encoded];
wire current_s_tlast = s_axis_tlast[grant_encoded];
wire [ID_WIDTH-1:0] current_s_tid = s_axis_tid[grant_encoded*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
// arbiter instance
arbiter #(
.PORTS(S_COUNT),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = s_axis_tvalid & ~grant;
assign acknowledge = grant & s_axis_tvalid & s_axis_tready & s_axis_tlast;
always @* begin
// pass through selected packet data
m_axis_tdata_int = current_s_tdata;
m_axis_tkeep_int = current_s_tkeep;
m_axis_tvalid_int = current_s_tvalid && m_axis_tready_int_reg && grant_valid;
m_axis_tlast_int = current_s_tlast;
m_axis_tid_int = current_s_tid;
m_axis_tdest_int = current_s_tdest;
m_axis_tuser_int = current_s_tuser;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tid_reg <= m_axis_tid_int;
m_axis_tdest_reg <= m_axis_tdest_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tid_reg <= temp_m_axis_tid_reg;
m_axis_tdest_reg <= temp_m_axis_tdest_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tid_reg <= m_axis_tid_int;
temp_m_axis_tdest_reg <= m_axis_tdest_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFXTP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfxtp (
CLK,
D ,
Q
);
input CLK;
input D ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:43:45 02/20/2015
// Design Name:
// Module Name: Fetch
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Fetch_FSL(
input [107:0] InstructionPacket,
input [107:0] InstructionPacket_Processed,
input ProcessInputReady,
input reset,
input clock,
input stall,
output reg [31:0] x_input = 32'h00000000,
output reg [31:0] y_input = 32'h00000000,
output reg [31:0] z_input = 32'h00000000,
output reg [1:0] mode,
output reg operation,
output reg [7:0] InsTagFetchOut,
output reg load = 1'b0,
output reg NatLogFlag = 1'b0
);
wire [3:0] Opcode;
wire [31:0] x_processor;
wire [31:0] y_processor;
wire [31:0] z_processor;
wire [7:0] InstructionTag;
wire [3:0] Opcode_processed;
wire [31:0] x_processor_processed;
wire [31:0] y_processor_processed;
wire [31:0] z_processor_processed;
wire [7:0] InstructionTag_processed;
assign InstructionTag = InstructionPacket[107:100];
assign Opcode = InstructionPacket[99:96];
assign x_processor = InstructionPacket[31:0];
assign y_processor = InstructionPacket[63:32];
assign z_processor = InstructionPacket[95:64];
assign InstructionTag_processed = InstructionPacket_Processed[107:100];
assign Opcode_processed = InstructionPacket_Processed[99:96];
assign x_processor_processed = InstructionPacket_Processed[31:0];
assign y_processor_processed = InstructionPacket_Processed[63:32];
assign z_processor_processed = InstructionPacket_Processed[95:64];
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10;
parameter vectoring = 1'b0,
rotation = 1'b1;
parameter circular = 2'b01,
linear = 2'b00,
hyperbolic = 2'b11;
always @ (posedge clock)
begin
if (reset == 1'b1) begin
x_input <= 32'h00000000;
y_input <= 32'h00000000;
z_input <= 32'h00000000;
load <= 1'b0;
NatLogFlag <= 1'b0;
end
else begin
if (ProcessInputReady == 1'b0) begin
InsTagFetchOut <= InstructionTag;
case(Opcode)
sin_cos:
begin
mode <= circular;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
sinh_cosh:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h00000000;
z_input <= z_processor;
load <= 1'b1;
end
arctan:
begin
mode <= circular;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
arctanh:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= 32'h3F800000;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
exp:
begin
mode <= hyperbolic;
operation <= rotation;
x_input <= 32'h3F800000;
y_input <= 32'h3F800000;
z_input <= z_processor;
load <= 1'b1;
end
division:
begin
mode <= linear;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
hypotenuse:
begin
mode <= circular;
operation <= vectoring;
x_input <= x_processor;
y_input <= y_processor;
z_input <= 32'h00000000;
load <= 1'b1;
end
endcase
end
else begin
InsTagFetchOut <= InstructionTag_processed;
case(Opcode_processed)
sqr_root:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input[31] <= x_processor_processed[31];
x_input[30:23] <= x_processor_processed[30:23] - 8'h01;
x_input[22:0] <= x_processor_processed[22:0];
y_input[31] <= 1'b0;
y_input[30:23] <= y_processor_processed[30:23] - 8'h01;
y_input[22:0] <= y_processor_processed[22:0];
z_input <= 32'h00000000;
load <= 1'b1;
end
nat_log:
begin
mode <= hyperbolic;
operation <= vectoring;
x_input <= x_processor_processed;
y_input[30:0] <= y_processor_processed[30:0];
y_input[31] <= 1'b0;
z_input <= 32'h00000000;
load <= 1'b1;
NatLogFlag <= 1'b1;
end
endcase
end
if (stall == 1'b1) begin
load <= 1'b0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:54:44 10/08/2014
// Design Name: pwm
// Module Name: /home/bjones/src/fpga-led-counter/test/pwm_tb.v
// Project Name: fpga-led-counter
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: pwm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module pwm_tb;
// Inputs
reg clk;
reg rst;
reg [7:0] compare0;
reg [7:0] compare1;
reg [7:0] compare2;
reg [7:0] compare3;
// Outputs
wire [3:0] pwm;
// Instantiate the Unit Under Test (UUT)
pwm uut0 (
.clk(clk),
.rst(rst),
.compare(compare0),
.pwm(pwm[0])
);
pwm uut1 (
.clk(clk),
.rst(rst),
.compare(compare1),
.pwm(pwm[1])
);
pwm uut2 (
.clk(clk),
.rst(rst),
.compare(compare2),
.pwm(pwm[2])
);
pwm uut3 (
.clk(clk),
.rst(rst),
.compare(compare3),
.pwm(pwm[3])
);
// clock and reset block
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
// toggle clock a bit
repeat(4) #10 clk = ~clk;
// bring rst low
rst = 0;
// generate the clock forever
forever #10 clk = ~clk;
end
// set parameters for pwm modules
initial begin
compare0 = 0;
compare1 = 0;
compare2 = 0;
compare3 = 0;
@(negedge rst); // wait for reset to lower
compare0 = 192; // 75%
compare1 = 128; // 50% duty cycle
compare2 = 64; // 25% duty cycle
compare3 = 32; // 12.5% duty cycle
repeat(1000) @(posedge clk);
$finish;
end
endmodule
|
// file: tres_relojes.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
`timescale 1ps/1ps
`default_nettype none
(* CORE_GENERATION_INFO = "tres_relojes,clk_wiz_v1_8,{component_name=tres_relojes,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=3,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module cuatro_relojes
(// Clock in ports
input wire CLK_IN1,
// Clock out ports
output wire CLK_OUT1,
output wire CLK_OUT2,
output wire CLK_OUT3,
output wire CLK_OUT4
);
wire clkin1,clkout0;
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire clkfbout;
wire clkfbout_buf;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (13),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (25),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (20.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (),
.CLKOUT2 (),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.LOCKED (),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
reg [2:0] clkdivider = 3'b000;
always @(posedge clkout0)
clkdivider <= clkdivider + 3'b001;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkdivider[0]));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkdivider[1]));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkdivider[2]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_BLACKBOX_V
`define SKY130_FD_SC_LP__HA_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__ha (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_SYMBOL_V
`define SKY130_FD_SC_LP__INVLP_SYMBOL_V
/**
* invlp: Low Power Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invlp (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple multiplexer
// Author: Dustin Richmond (@darichmond)
// TODO: Remove C_CLOG_NUM_INPUTS
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module mux
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32,
parameter C_MUX_TYPE = "SELECT"
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
`include "functions.vh"
generate
if(C_MUX_TYPE == "SELECT") begin
mux_select
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_select_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end else if (C_MUX_TYPE == "SHIFT") begin
mux_shift
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_shift_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end
endgenerate
endmodule
module mux_select
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH-1:0] wMuxInputs[C_NUM_INPUTS-1:0];
assign MUX_OUTPUT = wMuxInputs[MUX_SELECT];
generate
for (i = 0; i < C_NUM_INPUTS ; i = i + 1) begin : gen_muxInputs_array
assign wMuxInputs[i] = MUX_INPUTS[i*C_WIDTH +: C_WIDTH];
end
endgenerate
endmodule
module mux_shift
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH*C_NUM_INPUTS-1:0] wMuxInputs;
assign wMuxInputs = MUX_INPUTS >> MUX_SELECT;
assign MUX_OUTPUT = wMuxInputs[C_WIDTH-1:0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21O_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A21O_FUNCTIONAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a21o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21O_FUNCTIONAL_V
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: ALIGNER.v
// Version: 1.0
// Date: 30 May 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. WR_ALINGER alignes write data to cache and external devices
// 2. RD_ALINGER alignes read data for the data path
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 1. WR_ALINGER alignes write data to cache and external devices
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module WR_ALIGNER ( PACKET, DP_Q, SIZE, WRDATA, ENBYTE );
input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
input [63:0] DP_Q;
input [1:0] SIZE;
output [31:0] WRDATA;
output [3:0] ENBYTE;
reg [3:0] ENBYTE;
reg [7:0] dbyte0,dbyte1,dbyte2,dbyte3;
wire switch;
// Data packet [ B7 ],[ B6 ],[ B5 ],[ B4 ],[ B3 ],[ B2 ],[ B1 ],[ B0 ]
// Address , i.e. 001 : one DWORD
// gives 2 packets : 1. packet [-B6-----B5-----B4-]
// 2. packet, Address + 4 [-B7-]
// Addresse , i.e. 010 : one QWORD
// gives 3 packets : 1. packet [-B1-----B0-]
// 2. packet, Address + 4 [-B5-----B4-----B3-----B2-]
// 3. packet, Address + 8 [-B7-----B6-]
// SIZE PACKET ADR : Outputbus
// 00 00 00 x x x B4
// 00 00 01 x x B4 x
// 00 00 10 x B4 x x
// 00 00 11 B4 x x x
// 01 00 00 x x B5 B4
// 01 00 01 x B5 B4 x
// 01 00 10 B5 B4 x x
// 01 00 11 B4 x x x
// 01 10 11 x x x B5
// 10 00 00 B7 B6 B5 B4
// 10 00 01 B6 B5 B4 x
// 10 10 01 x x x B7
// 10 00 10 B5 B4 x x
// 10 10 10 x x B7 B6
// 10 00 11 B4 x x x
// 10 10 11 x B7 B6 B5
// 11 00 00 B3 B2 B1 B0
// 11 10 00 B7 B6 B5 B4
// 11 00 01 B2 B1 B0 x
// 11 01 01 B6 B5 B4 B3
// 11 10 01 x x x B7
// 11 00 10 B1 B0 x x
// 11 01 10 B5 B4 B3 B2
// 11 10 10 x x B7 B6
// 11 00 11 B0 x x x
// 11 01 11 B4 B3 B2 B1
// 11 10 11 x B7 B6 B5
assign switch = (SIZE == 2'b11) & (PACKET[3:2] == 2'b00);
always @(DP_Q or switch or PACKET)
case (PACKET[1:0])
2'b00 : dbyte0 = switch ? DP_Q[7:0] : DP_Q[39:32];
2'b01 : dbyte0 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
2'b10 : dbyte0 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
2'b11 : dbyte0 = PACKET[3] ? DP_Q[47:40] : DP_Q[15:8];
endcase
always @(DP_Q or switch or PACKET)
case (PACKET[1:0])
2'b00 : dbyte1 = switch ? DP_Q[15:8] : DP_Q[47:40];
2'b01 : dbyte1 = switch ? DP_Q[7:0] : DP_Q[39:32];
2'b10 : dbyte1 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
2'b11 : dbyte1 = PACKET[3] ? DP_Q[55:48] : DP_Q[23:16];
endcase
always @(DP_Q or switch or PACKET)
case (PACKET[1:0])
2'b00 : dbyte2 = switch ? DP_Q[23:16] : DP_Q[55:48];
2'b01 : dbyte2 = switch ? DP_Q[15:8] : DP_Q[47:40];
2'b10 : dbyte2 = switch ? DP_Q[7:0] : DP_Q[39:32];
2'b11 : dbyte2 = PACKET[3] ? DP_Q[63:56] : DP_Q[31:24];
endcase
always @(DP_Q or switch or PACKET)
case (PACKET[1:0])
2'b00 : dbyte3 = switch ? DP_Q[31:24] : DP_Q[63:56];
2'b01 : dbyte3 = switch ? DP_Q[23:16] : DP_Q[55:48];
2'b10 : dbyte3 = switch ? DP_Q[15:8] : DP_Q[47:40];
2'b11 : dbyte3 = switch ? DP_Q[7:0] : DP_Q[39:32];
endcase
assign WRDATA = {dbyte3,dbyte2,dbyte1,dbyte0};
always @(SIZE or PACKET)
casex ({SIZE,PACKET})
6'b00_xx_00 : ENBYTE = 4'b0001; // BYTE
6'b00_xx_01 : ENBYTE = 4'b0010;
6'b00_xx_10 : ENBYTE = 4'b0100;
6'b00_xx_11 : ENBYTE = 4'b1000;
//
6'b01_xx_00 : ENBYTE = 4'b0011; // WORD
6'b01_xx_01 : ENBYTE = 4'b0110;
6'b01_xx_10 : ENBYTE = 4'b1100;
6'b01_0x_11 : ENBYTE = 4'b1000;
6'b01_1x_11 : ENBYTE = 4'b0001;
//
6'b11_xx_00 : ENBYTE = 4'b1111; // QWORD
6'b11_00_01 : ENBYTE = 4'b1110;
6'b11_01_01 : ENBYTE = 4'b1111;
6'b11_1x_01 : ENBYTE = 4'b0001;
6'b11_00_10 : ENBYTE = 4'b1100;
6'b11_01_10 : ENBYTE = 4'b1111;
6'b11_1x_10 : ENBYTE = 4'b0011;
6'b11_00_11 : ENBYTE = 4'b1000;
6'b11_01_11 : ENBYTE = 4'b1111;
6'b11_1x_11 : ENBYTE = 4'b0111;
//
6'b10_xx_00 : ENBYTE = 4'b1111; // DWORD
6'b10_0x_01 : ENBYTE = 4'b1110;
6'b10_1x_01 : ENBYTE = 4'b0001;
6'b10_0x_10 : ENBYTE = 4'b1100;
6'b10_1x_10 : ENBYTE = 4'b0011;
6'b10_0x_11 : ENBYTE = 4'b1000;
6'b10_1x_11 : ENBYTE = 4'b0111;
endcase
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2. RD_ALINGER alignes read data for the data path
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module RD_ALIGNER ( BCLK, ACC_OK, PACKET, SIZE, REG_OUT, RDDATA, CA_HIT, DP_DI, AUX_QW );
input BCLK;
input ACC_OK;
input [3:0] PACKET; // [3:2] Paketnumber , [1:0] Startaddress
input [1:0] SIZE;
input REG_OUT;
input [31:0] RDDATA;
input CA_HIT;
output [31:0] DP_DI;
output reg AUX_QW;
reg [6:0] enable;
reg [7:0] dreg_0,dreg_1,dreg_2,dreg_3,dreg_4,dreg_5,dreg_6;
reg [7:0] out_0,out_1,out_2,out_3;
// RD_ALIGNER principal working : 10 is last packet , 01 is packet in between
// Not aligned QWORD : ADR[1:0] = 3 i.e.
// Bytes to datapath : . - . - 4 - 4
// Bytes from memory : 1 - 4 - 3 - .
// ACC_DONE : _______/----\__
// + 1 cycle ____/--
// at the end 2 cycles lost. ACC_DONE informs the Op-Dec that data is available and sent one clock cycle later
// the LSD of QWORD access. (ACC_DONE -> REG_OUT is happening in ADDR_UNIT.)
//
// SIZE PACKET ADR : Output data ACC_OK
// 00 -- 00 x x x B0 Byte 1
// 00 -- 01 x x x B1 1
// 00 -- 10 x x x B2 1
// 00 -- 11 x x x B3 1
// 01 00 00 x x B1 B0 Word 1
// 01 00 01 x x B2 B1 1
// 01 00 10 x x B3 B2 1
// 01 00 11 B3 x x x -> Reg : R4 - - - 0
// 01 10 11 x x B0 R4 1
// 10 00 00 B3 B2 B1 B0 DWORD 1
// 10 00 01 B3 B2 B1 x -> Reg : R6 R5 R4 - 0
// 10 10 01 B0 R6 R5 R4 1
// 10 00 10 B3 B2 x x -> Reg : R5 R4 - - 0
// 10 10 10 B1 B0 R5 R4 1
// 10 00 11 B3 x x x -> Reg : R4 - - - 0
// 10 10 11 B2 B1 B0 R4 1
// 11 00 00 B3 B2 B1 B0 QWORD 1 MSD
// 11 01 00 B3 B2 B1 B0 not out of Reg! 0 LSD
// 11 00 01 B3 B2 B1 x -> Reg : R2 R1 R0 - 0
// 11 01 01 B3 B2 B1 B0 -> Reg : R6 R5 R4 R3 0
// 11 10 01 B0 R6 R5 R4 1 MSD
// next cycle: R3 R2 R1 R0 LSD
// 11 00 10 B3 B2 x x -> Reg : R1 R0 - - 0
// 11 01 10 B3 B2 B1 B0 -> Reg : R5 R4 R3 R2 0
// 11 10 10 B1 B0 R5 R4 1 MSD
// next cycle: R3 R2 R1 R0 LSD
// 11 00 11 B3 x x x -> Reg : R0 - - - 0
// 11 01 11 B3 B2 B1 B0 -> Reg : R4 R3 R2 R1 0
// 11 10 11 B2 B1 B0 R4 1 MSD
// next cycle: R3 R2 R1 R0 LSD
// IO_ACCESS QWORD :
// 11 00 00 B3 B2 B1 B0 -> Reg : R3 R2 R1 R0 0
// 11 01 00 R3 R2 R1 R0 -> Reg : R3 R2 R1 R0 1 MSD
// next cycle: R3 R2 R1 R0 LSD
always @(ACC_OK or SIZE or PACKET)
casex ({ACC_OK,SIZE,PACKET})
7'b1_xx_0x_00 : enable = 7'b000_1111;
7'b1_01_0x_11 : enable = 7'b001_0000;
7'b1_10_0x_01 : enable = 7'b111_0000;
7'b1_10_0x_10 : enable = 7'b011_0000;
7'b1_10_0x_11 : enable = 7'b001_0000;
7'b1_11_00_01 : enable = 7'b000_0111; // QWORD
7'b1_11_01_01 : enable = 7'b111_1000;
7'b1_11_00_10 : enable = 7'b000_0011;
7'b1_11_01_10 : enable = 7'b011_1100;
7'b1_11_00_11 : enable = 7'b000_0001;
7'b1_11_01_11 : enable = 7'b001_1110;
default : enable = 7'b000_0000;
endcase
// Register for inbetween data: simple multiplexer
always @(posedge BCLK)
if (enable[0])
case (PACKET[1:0])
2'b01 : dreg_0 <= RDDATA[15:8];
2'b10 : dreg_0 <= RDDATA[23:16];
2'b11 : dreg_0 <= RDDATA[31:24];
default : dreg_0 <= RDDATA[7:0];
endcase
always @(posedge BCLK)
if (enable[1])
case (PACKET[1:0])
2'b01 : dreg_1 <= RDDATA[23:16];
2'b10 : dreg_1 <= RDDATA[31:24];
2'b11 : dreg_1 <= RDDATA[7:0];
default : dreg_1 <= RDDATA[15:8];
endcase
always @(posedge BCLK)
if (enable[2])
case (PACKET[1:0])
2'b01 : dreg_2 <= RDDATA[31:24];
2'b10 : dreg_2 <= RDDATA[7:0];
2'b11 : dreg_2 <= RDDATA[15:8];
default : dreg_2 <= RDDATA[23:16];
endcase
always @(posedge BCLK)
if (enable[3])
case (PACKET[1:0])
2'b01 : dreg_3 <= RDDATA[7:0];
2'b10 : dreg_3 <= RDDATA[15:8];
2'b11 : dreg_3 <= RDDATA[23:16];
default : dreg_3 <= RDDATA[31:24];
endcase
always @(posedge BCLK)
if (enable[4])
case (PACKET[1:0])
2'b01 : dreg_4 <= RDDATA[15:8];
2'b10 : dreg_4 <= RDDATA[23:16];
2'b11 : dreg_4 <= RDDATA[31:24];
default : dreg_4 <= dreg_4;
endcase
always @(posedge BCLK) if (enable[5]) dreg_5 <= PACKET[1] ? RDDATA[31:24] : RDDATA[23:16];
always @(posedge BCLK) if (enable[6]) dreg_6 <= RDDATA[31:24];
// +++++++++++++++++++++++
always @(SIZE or PACKET or RDDATA or dreg_0 or dreg_4)
casex ({SIZE,PACKET[3],PACKET[1:0]})
5'b0x_0_01 : out_0 = RDDATA[15:8];
5'b0x_0_10 : out_0 = RDDATA[23:16];
5'b00_0_11 : out_0 = RDDATA[31:24];
5'b01_1_11 : out_0 = dreg_4;
5'b1x_1_01 : out_0 = dreg_4;
5'b1x_1_1x : out_0 = dreg_4;
default : out_0 = RDDATA[7:0];
endcase
always @(SIZE or PACKET or RDDATA or dreg_1 or dreg_5)
casex ({SIZE,PACKET[3],PACKET[1:0]})
5'b01_0_01 : out_1 = RDDATA[23:16];
5'b01_0_10 : out_1 = RDDATA[31:24];
5'bxx_x_11 : out_1 = RDDATA[7:0];
5'b1x_1_01 : out_1 = dreg_5;
5'b1x_1_10 : out_1 = dreg_5;
default : out_1 = RDDATA[15:8];
endcase
always @(SIZE or PACKET or RDDATA or dreg_2 or dreg_6)
case ({SIZE[1],PACKET[3],PACKET[1:0]})
4'b1_1_01 : out_2 = dreg_6;
4'b1_1_10 : out_2 = RDDATA[7:0];
4'b1_1_11 : out_2 = RDDATA[15:8];
default : out_2 = RDDATA[23:16];
endcase
always @(SIZE or PACKET or RDDATA or dreg_3)
case ({SIZE[1],PACKET[3],PACKET[1:0]})
4'b1_1_01 : out_3 = RDDATA[7:0];
4'b1_1_10 : out_3 = RDDATA[15:8];
4'b1_1_11 : out_3 = RDDATA[23:16];
default : out_3 = RDDATA[31:24];
endcase
assign DP_DI = REG_OUT ? {dreg_3,dreg_2,dreg_1,dreg_0} : {out_3,out_2,out_1,out_0};
// ++++++++++++++++ Special case QWord if cache switched off +++++++++++++++++++
always @(posedge BCLK) AUX_QW <= ACC_OK & ~CA_HIT & (SIZE == 2'b11) & PACKET[3];
endmodule
|
module interstage_buffer_if_id(clock);
register#(4) id_control_signals_buffer(if_control_signals,
clock,
id_control_signals);
register#(4) ex_control_signals_buffer(id_control_signals,
clock,
ex_control_signals);
register#(4) mem_control_signals_buffer(ex_control_signals,
clock,
mem_control_signals);
register#(4) wb_control_signals_buffer(mem_control_signals,
clock,
wb_control_signals);
endmodule
module interstage_buffer_id_ex(clock);
register#(4) ex_control_signals_buffer(id_control_signals,
clock,
ex_control_signals);
register#(4) mem_control_signals_buffer(ex_control_signals,
clock,
mem_control_signals);
register#(4) wb_control_signals_buffer(mem_control_signals,
clock,
wb_control_signals);
endmodule
module interstage_buffer_ex_mem(clock);
register#(4) mem_control_signals_buffer(ex_control_signals,
clock,
mem_control_signals);
register#(4) wb_control_signals_buffer(mem_control_signals,
clock,
wb_control_signals);
endmodule
module interstage_buffer_mem_wb(clock);
register#(4) wb_control_signals_buffer(mem_control_signals,
clock,
wb_control_signals);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NAND2B_BEHAVIORAL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
// Local signals
wire Y not0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_BEHAVIORAL_V
|
// megafunction wizard: %ALTPLL_RECONFIG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll_reconfig
// ============================================================
// File Name: pll_cfg.v
// Megafunction Name(s):
// altpll_reconfig
//
// Simulation Library Files(s):
// altera_mf;cycloneive;lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV E" init_from_rom="NO" scan_init_file="./pll_dyn.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
//VERSION_BEGIN 11.1SP2 cbx_altpll_reconfig 2012:01:25:21:13:53:SJ cbx_altsyncram 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_counter 2012:01:25:21:13:53:SJ cbx_lpm_decode 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_stratixiii 2012:01:25:21:13:53:SJ cbx_stratixv 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"ADV_NETLIST_OPT_ALLOWED=\"NEVER_ALLOW\";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1"} *)
module pll_cfg_pllrcfg_9mu
(
busy,
clock,
counter_param,
counter_type,
data_in,
data_out,
pll_areset,
pll_areset_in,
pll_configupdate,
pll_scanclk,
pll_scanclkena,
pll_scandata,
pll_scandataout,
pll_scandone,
read_param,
reconfig,
reset,
write_param) /* synthesis synthesis_clearbox=2 */;
output busy;
input clock;
input [2:0] counter_param;
input [3:0] counter_type;
input [8:0] data_in;
output [8:0] data_out;
output pll_areset;
input pll_areset_in;
output pll_configupdate;
output pll_scanclk;
output pll_scanclkena;
output pll_scandata;
input pll_scandataout;
input pll_scandone;
input read_param;
input reconfig;
input reset;
input write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [2:0] counter_param;
tri0 [3:0] counter_type;
tri0 [8:0] data_in;
tri0 pll_areset_in;
tri0 pll_scandataout;
tri0 pll_scandone;
tri0 read_param;
tri0 reconfig;
tri0 write_param;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_altsyncram4_q_a;
wire wire_le_comb10_combout;
wire wire_le_comb8_combout;
wire wire_le_comb9_combout;
reg areset_init_state_1;
reg areset_state;
reg C0_data_state;
reg C0_ena_state;
reg C1_data_state;
reg C1_ena_state;
reg C2_data_state;
reg C2_ena_state;
reg C3_data_state;
reg C3_ena_state;
reg C4_data_state;
reg C4_ena_state;
reg configupdate2_state;
reg configupdate3_state;
reg configupdate_state;
reg [2:0] counter_param_latch_reg;
reg [3:0] counter_type_latch_reg;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg idle_state;
reg [0:0] nominal_data0;
reg [0:0] nominal_data1;
reg [0:0] nominal_data2;
reg [0:0] nominal_data3;
reg [0:0] nominal_data4;
reg [0:0] nominal_data5;
reg [0:0] nominal_data6;
reg [0:0] nominal_data7;
reg [0:0] nominal_data8;
reg [0:0] nominal_data9;
reg [0:0] nominal_data10;
reg [0:0] nominal_data11;
reg [0:0] nominal_data12;
reg [0:0] nominal_data13;
reg [0:0] nominal_data14;
reg [0:0] nominal_data15;
reg [0:0] nominal_data16;
reg [0:0] nominal_data17;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_data_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_first_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_first_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_init_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_last_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg read_last_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_counter_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_post_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_seq_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_seq_ena_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg reconfig_wait_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
reg reset_state;
reg [0:0] shift_reg0;
reg [0:0] shift_reg1;
reg [0:0] shift_reg2;
reg [0:0] shift_reg3;
reg [0:0] shift_reg4;
reg [0:0] shift_reg5;
reg [0:0] shift_reg6;
reg [0:0] shift_reg7;
reg [0:0] shift_reg8;
reg [0:0] shift_reg9;
reg [0:0] shift_reg10;
reg [0:0] shift_reg11;
reg [0:0] shift_reg12;
reg [0:0] shift_reg13;
reg [0:0] shift_reg14;
reg [0:0] shift_reg15;
reg [0:0] shift_reg16;
reg [0:0] shift_reg17;
wire [17:0] wire_shift_reg_ena;
reg tmp_nominal_data_out_state;
reg tmp_seq_ena_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_data_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_init_nominal_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_init_state;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg write_nominal_state;
wire [8:0] wire_add_sub5_result;
wire [7:0] wire_add_sub6_result;
wire wire_cmpr7_aeb;
wire [7:0] wire_cntr1_q;
wire [7:0] wire_cntr12_q;
wire [5:0] wire_cntr13_q;
wire [4:0] wire_cntr14_q;
wire [7:0] wire_cntr15_q;
wire [7:0] wire_cntr2_q;
wire [4:0] wire_cntr3_q;
wire [4:0] wire_decode11_eq;
wire addr_counter_enable;
wire [7:0] addr_counter_out;
wire addr_counter_sload;
wire [7:0] addr_counter_sload_value;
wire [7:0] addr_decoder_out;
wire [7:0] c0_wire;
wire [7:0] c1_wire;
wire [7:0] c2_wire;
wire [7:0] c3_wire;
wire [7:0] c4_wire;
wire [2:0] counter_param_latch;
wire [3:0] counter_type_latch;
wire [2:0] cuda_combout_wire;
wire dummy_scandataout;
wire [2:0] encode_out;
wire input_latch_enable;
wire power_up;
wire read_addr_counter_enable;
wire [7:0] read_addr_counter_out;
wire read_addr_counter_sload;
wire [7:0] read_addr_counter_sload_value;
wire [7:0] read_addr_decoder_out;
wire read_nominal_out;
wire reconfig_addr_counter_enable;
wire [7:0] reconfig_addr_counter_out;
wire reconfig_addr_counter_sload;
wire [7:0] reconfig_addr_counter_sload_value;
wire reconfig_done;
wire reconfig_post_done;
wire reconfig_width_counter_done;
wire reconfig_width_counter_enable;
wire reconfig_width_counter_sload;
wire [5:0] reconfig_width_counter_sload_value;
wire rotate_addr_counter_enable;
wire [7:0] rotate_addr_counter_out;
wire rotate_addr_counter_sload;
wire [7:0] rotate_addr_counter_sload_value;
wire [4:0] rotate_decoder_wires;
wire rotate_width_counter_done;
wire rotate_width_counter_enable;
wire rotate_width_counter_sload;
wire [4:0] rotate_width_counter_sload_value;
wire [7:0] scan_cache_address;
wire scan_cache_in;
wire scan_cache_out;
wire scan_cache_write_enable;
wire sel_param_bypass_LF_unused;
wire sel_param_c;
wire sel_param_high_i_postscale;
wire sel_param_low_r;
wire sel_param_nominal_count;
wire sel_param_odd_CP_unused;
wire sel_type_c0;
wire sel_type_c1;
wire sel_type_c2;
wire sel_type_c3;
wire sel_type_c4;
wire sel_type_cplf;
wire sel_type_m;
wire sel_type_n;
wire sel_type_vco;
wire [7:0] seq_addr_wire;
wire [5:0] seq_sload_value;
wire shift_reg_clear;
wire shift_reg_load_enable;
wire shift_reg_load_nominal_enable;
wire shift_reg_serial_in;
wire shift_reg_serial_out;
wire shift_reg_shift_enable;
wire shift_reg_shift_nominal_enable;
wire [7:0] shift_reg_width_select;
wire w1565w;
wire w1592w;
wire w64w;
wire width_counter_done;
wire width_counter_enable;
wire width_counter_sload;
wire [4:0] width_counter_sload_value;
wire [4:0] width_decoder_out;
wire [7:0] width_decoder_select;
wire write_from_rom;
altsyncram altsyncram4
(
.address_a(scan_cache_address),
.clock0(clock),
.data_a({scan_cache_in}),
.eccstatus(),
.q_a(wire_altsyncram4_q_a),
.q_b(),
.wren_a(scan_cache_write_enable)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr0(1'b0),
.aclr1(1'b0),
.address_b({1{1'b1}}),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({1{1'b1}}),
.byteena_b({1{1'b1}}),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_b({1{1'b1}}),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_b(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
altsyncram4.init_file = "./pll_dyn.mif",
altsyncram4.numwords_a = 144,
altsyncram4.operation_mode = "SINGLE_PORT",
altsyncram4.width_a = 1,
altsyncram4.width_byteena_a = 1,
altsyncram4.widthad_a = 8,
altsyncram4.intended_device_family = "Cyclone IV E",
altsyncram4.lpm_type = "altsyncram";
cycloneive_lcell_comb le_comb10
(
.combout(wire_le_comb10_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.cin(1'b0),
.datad(1'b0)
);
defparam
le_comb10.dont_touch = "on",
le_comb10.lut_mask = 16'hF0F0,
le_comb10.sum_lutc_input = "datac",
le_comb10.lpm_type = "cycloneive_lcell_comb";
cycloneive_lcell_comb le_comb8
(
.combout(wire_le_comb8_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.cin(1'b0),
.datad(1'b0)
);
defparam
le_comb8.dont_touch = "on",
le_comb8.lut_mask = 16'hAAAA,
le_comb8.sum_lutc_input = "datac",
le_comb8.lpm_type = "cycloneive_lcell_comb";
cycloneive_lcell_comb le_comb9
(
.combout(wire_le_comb9_combout),
.cout(),
.dataa(encode_out[0]),
.datab(encode_out[1]),
.datac(encode_out[2]),
.cin(1'b0),
.datad(1'b0)
);
defparam
le_comb9.dont_touch = "on",
le_comb9.lut_mask = 16'hCCCC,
le_comb9.sum_lutc_input = "datac",
le_comb9.lpm_type = "cycloneive_lcell_comb";
// synopsys translate_off
initial
areset_init_state_1 = 0;
// synopsys translate_on
always @ ( posedge clock)
areset_init_state_1 <= pll_scandone;
// synopsys translate_off
initial
areset_state = 0;
// synopsys translate_on
always @ ( posedge clock)
areset_state <= (areset_init_state_1 & (~ reset));
// synopsys translate_off
initial
C0_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C0_data_state <= (C0_ena_state | (C0_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C0_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C0_ena_state <= (C1_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C1_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C1_data_state <= (C1_ena_state | (C1_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C1_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C1_ena_state <= (C2_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C2_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C2_data_state <= (C2_ena_state | (C2_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C2_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C2_ena_state <= (C3_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C3_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C3_data_state <= (C3_ena_state | (C3_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C3_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C3_ena_state <= (C4_data_state & rotate_width_counter_done);
// synopsys translate_off
initial
C4_data_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C4_data_state <= (C4_ena_state | (C4_data_state & (~ rotate_width_counter_done)));
// synopsys translate_off
initial
C4_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
C4_ena_state <= reconfig_init_state;
// synopsys translate_off
initial
configupdate2_state = 0;
// synopsys translate_on
always @ ( posedge clock)
configupdate2_state <= configupdate_state;
// synopsys translate_off
initial
configupdate3_state = 0;
// synopsys translate_on
always @ ( negedge clock)
configupdate3_state <= configupdate2_state;
// synopsys translate_off
initial
configupdate_state = 0;
// synopsys translate_on
always @ ( posedge clock)
configupdate_state <= reconfig_post_state;
// synopsys translate_off
initial
counter_param_latch_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) counter_param_latch_reg <= 3'b0;
else if (input_latch_enable == 1'b1) counter_param_latch_reg <= counter_param;
// synopsys translate_off
initial
counter_type_latch_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) counter_type_latch_reg <= 4'b0;
else if (input_latch_enable == 1'b1) counter_type_latch_reg <= counter_type;
// synopsys translate_off
initial
idle_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) idle_state <= 1'b0;
else idle_state <= ((((((((((idle_state & (~ read_param)) & (~ write_param)) & (~ reconfig)) & (~ write_from_rom)) | read_last_state) | (write_data_state & width_counter_done)) | (write_nominal_state & width_counter_done)) | read_last_nominal_state) | (reconfig_wait_state & reconfig_done)) | reset_state);
// synopsys translate_off
initial
nominal_data0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data0 <= 1'b0;
else nominal_data0 <= wire_add_sub6_result[0];
// synopsys translate_off
initial
nominal_data1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data1 <= 1'b0;
else nominal_data1 <= wire_add_sub6_result[1];
// synopsys translate_off
initial
nominal_data2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data2 <= 1'b0;
else nominal_data2 <= wire_add_sub6_result[2];
// synopsys translate_off
initial
nominal_data3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data3 <= 1'b0;
else nominal_data3 <= wire_add_sub6_result[3];
// synopsys translate_off
initial
nominal_data4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data4 <= 1'b0;
else nominal_data4 <= wire_add_sub6_result[4];
// synopsys translate_off
initial
nominal_data5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data5 <= 1'b0;
else nominal_data5 <= wire_add_sub6_result[5];
// synopsys translate_off
initial
nominal_data6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data6 <= 1'b0;
else nominal_data6 <= wire_add_sub6_result[6];
// synopsys translate_off
initial
nominal_data7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data7 <= 1'b0;
else nominal_data7 <= wire_add_sub6_result[7];
// synopsys translate_off
initial
nominal_data8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data8 <= 1'b0;
else nominal_data8 <= data_in[0];
// synopsys translate_off
initial
nominal_data9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data9 <= 1'b0;
else nominal_data9 <= data_in[1];
// synopsys translate_off
initial
nominal_data10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data10 <= 1'b0;
else nominal_data10 <= data_in[2];
// synopsys translate_off
initial
nominal_data11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data11 <= 1'b0;
else nominal_data11 <= data_in[3];
// synopsys translate_off
initial
nominal_data12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data12 <= 1'b0;
else nominal_data12 <= data_in[4];
// synopsys translate_off
initial
nominal_data13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data13 <= 1'b0;
else nominal_data13 <= data_in[5];
// synopsys translate_off
initial
nominal_data14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data14 <= 1'b0;
else nominal_data14 <= data_in[6];
// synopsys translate_off
initial
nominal_data15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data15 <= 1'b0;
else nominal_data15 <= data_in[7];
// synopsys translate_off
initial
nominal_data16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data16 <= 1'b0;
else nominal_data16 <= data_in[8];
// synopsys translate_off
initial
nominal_data17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) nominal_data17 <= 1'b0;
else nominal_data17 <= wire_cmpr7_aeb;
// synopsys translate_off
initial
read_data_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_data_nominal_state <= 1'b0;
else read_data_nominal_state <= ((read_first_nominal_state & (~ width_counter_done)) | (read_data_nominal_state & (~ width_counter_done)));
// synopsys translate_off
initial
read_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_data_state <= 1'b0;
else read_data_state <= ((read_first_state & (~ width_counter_done)) | (read_data_state & (~ width_counter_done)));
// synopsys translate_off
initial
read_first_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_first_nominal_state <= 1'b0;
else read_first_nominal_state <= read_init_nominal_state;
// synopsys translate_off
initial
read_first_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_first_state <= 1'b0;
else read_first_state <= read_init_state;
// synopsys translate_off
initial
read_init_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_nominal_state <= 1'b0;
else read_init_nominal_state <= ((idle_state & read_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
// synopsys translate_off
initial
read_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_init_state <= 1'b0;
else read_init_state <= ((idle_state & read_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
// synopsys translate_off
initial
read_last_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_last_nominal_state <= 1'b0;
else read_last_nominal_state <= ((read_first_nominal_state & width_counter_done) | (read_data_nominal_state & width_counter_done));
// synopsys translate_off
initial
read_last_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) read_last_state <= 1'b0;
else read_last_state <= ((read_first_state & width_counter_done) | (read_data_state & width_counter_done));
// synopsys translate_off
initial
reconfig_counter_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_counter_state <= 1'b0;
else reconfig_counter_state <= ((((((((((reconfig_init_state | C0_data_state) | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state) | C0_ena_state) | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state);
// synopsys translate_off
initial
reconfig_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_init_state <= 1'b0;
else reconfig_init_state <= (idle_state & reconfig);
// synopsys translate_off
initial
reconfig_post_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_post_state <= 1'b0;
else reconfig_post_state <= ((reconfig_seq_data_state & reconfig_width_counter_done) | (reconfig_post_state & (~ reconfig_post_done)));
// synopsys translate_off
initial
reconfig_seq_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_seq_data_state <= 1'b0;
else reconfig_seq_data_state <= (reconfig_seq_ena_state | (reconfig_seq_data_state & (~ reconfig_width_counter_done)));
// synopsys translate_off
initial
reconfig_seq_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_seq_ena_state <= 1'b0;
else reconfig_seq_ena_state <= tmp_seq_ena_state;
// synopsys translate_off
initial
reconfig_wait_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reconfig_wait_state <= 1'b0;
else reconfig_wait_state <= ((reconfig_post_state & reconfig_post_done) | (reconfig_wait_state & (~ reconfig_done)));
// synopsys translate_off
initial
reset_state = {1{1'b1}};
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) reset_state <= {1{1'b1}};
else reset_state <= power_up;
// synopsys translate_off
initial
shift_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg0 <= 1'b0;
else if (wire_shift_reg_ena[0:0] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg0 <= 1'b0;
else shift_reg0 <= ((((shift_reg_load_nominal_enable & nominal_data17[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg_serial_in)) | (shift_reg_shift_nominal_enable & shift_reg_serial_in));
// synopsys translate_off
initial
shift_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg1 <= 1'b0;
else if (wire_shift_reg_ena[1:1] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg1 <= 1'b0;
else shift_reg1 <= ((((shift_reg_load_nominal_enable & nominal_data16[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg0[0:0])) | (shift_reg_shift_nominal_enable & shift_reg0[0:0]));
// synopsys translate_off
initial
shift_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg2 <= 1'b0;
else if (wire_shift_reg_ena[2:2] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg2 <= 1'b0;
else shift_reg2 <= ((((shift_reg_load_nominal_enable & nominal_data15[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg1[0:0])) | (shift_reg_shift_nominal_enable & shift_reg1[0:0]));
// synopsys translate_off
initial
shift_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg3 <= 1'b0;
else if (wire_shift_reg_ena[3:3] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg3 <= 1'b0;
else shift_reg3 <= ((((shift_reg_load_nominal_enable & nominal_data14[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg2[0:0])) | (shift_reg_shift_nominal_enable & shift_reg2[0:0]));
// synopsys translate_off
initial
shift_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg4 <= 1'b0;
else if (wire_shift_reg_ena[4:4] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg4 <= 1'b0;
else shift_reg4 <= ((((shift_reg_load_nominal_enable & nominal_data13[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg3[0:0])) | (shift_reg_shift_nominal_enable & shift_reg3[0:0]));
// synopsys translate_off
initial
shift_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg5 <= 1'b0;
else if (wire_shift_reg_ena[5:5] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg5 <= 1'b0;
else shift_reg5 <= ((((shift_reg_load_nominal_enable & nominal_data12[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg4[0:0])) | (shift_reg_shift_nominal_enable & shift_reg4[0:0]));
// synopsys translate_off
initial
shift_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg6 <= 1'b0;
else if (wire_shift_reg_ena[6:6] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg6 <= 1'b0;
else shift_reg6 <= ((((shift_reg_load_nominal_enable & nominal_data11[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg5[0:0])) | (shift_reg_shift_nominal_enable & shift_reg5[0:0]));
// synopsys translate_off
initial
shift_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg7 <= 1'b0;
else if (wire_shift_reg_ena[7:7] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg7 <= 1'b0;
else shift_reg7 <= ((((shift_reg_load_nominal_enable & nominal_data10[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg6[0:0])) | (shift_reg_shift_nominal_enable & shift_reg6[0:0]));
// synopsys translate_off
initial
shift_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg8 <= 1'b0;
else if (wire_shift_reg_ena[8:8] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg8 <= 1'b0;
else shift_reg8 <= ((((shift_reg_load_nominal_enable & nominal_data9[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg7[0:0])) | (shift_reg_shift_nominal_enable & shift_reg7[0:0]));
// synopsys translate_off
initial
shift_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg9 <= 1'b0;
else if (wire_shift_reg_ena[9:9] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg9 <= 1'b0;
else shift_reg9 <= ((((shift_reg_load_nominal_enable & nominal_data8[0:0]) | (shift_reg_load_enable & data_in[8])) | (shift_reg_shift_enable & shift_reg8[0:0])) | (shift_reg_shift_nominal_enable & shift_reg8[0:0]));
// synopsys translate_off
initial
shift_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg10 <= 1'b0;
else if (wire_shift_reg_ena[10:10] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg10 <= 1'b0;
else shift_reg10 <= ((((shift_reg_load_nominal_enable & nominal_data7[0:0]) | (shift_reg_load_enable & data_in[7])) | (shift_reg_shift_enable & shift_reg9[0:0])) | (shift_reg_shift_nominal_enable & shift_reg9[0:0]));
// synopsys translate_off
initial
shift_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg11 <= 1'b0;
else if (wire_shift_reg_ena[11:11] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg11 <= 1'b0;
else shift_reg11 <= ((((shift_reg_load_nominal_enable & nominal_data6[0:0]) | (shift_reg_load_enable & data_in[6])) | (shift_reg_shift_enable & shift_reg10[0:0])) | (shift_reg_shift_nominal_enable & shift_reg10[0:0]));
// synopsys translate_off
initial
shift_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg12 <= 1'b0;
else if (wire_shift_reg_ena[12:12] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg12 <= 1'b0;
else shift_reg12 <= ((((shift_reg_load_nominal_enable & nominal_data5[0:0]) | (shift_reg_load_enable & data_in[5])) | (shift_reg_shift_enable & shift_reg11[0:0])) | (shift_reg_shift_nominal_enable & shift_reg11[0:0]));
// synopsys translate_off
initial
shift_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg13 <= 1'b0;
else if (wire_shift_reg_ena[13:13] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg13 <= 1'b0;
else shift_reg13 <= ((((shift_reg_load_nominal_enable & nominal_data4[0:0]) | (shift_reg_load_enable & data_in[4])) | (shift_reg_shift_enable & shift_reg12[0:0])) | (shift_reg_shift_nominal_enable & shift_reg12[0:0]));
// synopsys translate_off
initial
shift_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg14 <= 1'b0;
else if (wire_shift_reg_ena[14:14] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg14 <= 1'b0;
else shift_reg14 <= ((((shift_reg_load_nominal_enable & nominal_data3[0:0]) | (shift_reg_load_enable & data_in[3])) | (shift_reg_shift_enable & shift_reg13[0:0])) | (shift_reg_shift_nominal_enable & shift_reg13[0:0]));
// synopsys translate_off
initial
shift_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg15 <= 1'b0;
else if (wire_shift_reg_ena[15:15] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg15 <= 1'b0;
else shift_reg15 <= ((((shift_reg_load_nominal_enable & nominal_data2[0:0]) | (shift_reg_load_enable & data_in[2])) | (shift_reg_shift_enable & shift_reg14[0:0])) | (shift_reg_shift_nominal_enable & shift_reg14[0:0]));
// synopsys translate_off
initial
shift_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg16 <= 1'b0;
else if (wire_shift_reg_ena[16:16] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg16 <= 1'b0;
else shift_reg16 <= ((((shift_reg_load_nominal_enable & nominal_data1[0:0]) | (shift_reg_load_enable & data_in[1])) | (shift_reg_shift_enable & shift_reg15[0:0])) | (shift_reg_shift_nominal_enable & shift_reg15[0:0]));
// synopsys translate_off
initial
shift_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) shift_reg17 <= 1'b0;
else if (wire_shift_reg_ena[17:17] == 1'b1)
if (shift_reg_clear == 1'b1) shift_reg17 <= 1'b0;
else shift_reg17 <= ((((shift_reg_load_nominal_enable & nominal_data0[0:0]) | (shift_reg_load_enable & data_in[0])) | (shift_reg_shift_enable & shift_reg16[0:0])) | (shift_reg_shift_nominal_enable & shift_reg16[0:0]));
assign
wire_shift_reg_ena = {18{((((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_load_nominal_enable) | shift_reg_shift_nominal_enable) | shift_reg_clear)}};
// synopsys translate_off
initial
tmp_nominal_data_out_state = 0;
// synopsys translate_on
always @ ( posedge clock)
tmp_nominal_data_out_state <= ((read_last_nominal_state & (~ idle_state)) | (tmp_nominal_data_out_state & idle_state));
// synopsys translate_off
initial
tmp_seq_ena_state = 0;
// synopsys translate_on
always @ ( posedge clock)
tmp_seq_ena_state <= (reconfig_counter_state & (C0_data_state & rotate_width_counter_done));
// synopsys translate_off
initial
write_data_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_data_state <= 1'b0;
else write_data_state <= (write_init_state | (write_data_state & (~ width_counter_done)));
// synopsys translate_off
initial
write_init_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_nominal_state <= 1'b0;
else write_init_nominal_state <= ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
// synopsys translate_off
initial
write_init_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_init_state <= 1'b0;
else write_init_state <= ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
// synopsys translate_off
initial
write_nominal_state = 0;
// synopsys translate_on
always @ ( posedge clock or posedge reset)
if (reset == 1'b1) write_nominal_state <= 1'b0;
else write_nominal_state <= (write_init_nominal_state | (write_nominal_state & (~ width_counter_done)));
lpm_add_sub add_sub5
(
.cin(1'b0),
.cout(),
.dataa({1'b0, shift_reg8[0:0], shift_reg7[0:0], shift_reg6[0:0], shift_reg5[0:0], shift_reg4[0:0], shift_reg3[0:0], shift_reg2[0:0], shift_reg1[0:0]}),
.datab({1'b0, shift_reg17[0:0], shift_reg16[0:0], shift_reg15[0:0], shift_reg14[0:0], shift_reg13[0:0], shift_reg12[0:0], shift_reg11[0:0], shift_reg10[0:0]}),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_width = 9,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cin(data_in[0]),
.cout(),
.dataa({data_in[8:1]}),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0),
.datab({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_width = 8,
add_sub6.lpm_type = "lpm_add_sub";
lpm_compare cmpr7
(
.aeb(wire_cmpr7_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa({data_in[7:0]}),
.datab(8'b00000001)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr7.lpm_width = 8,
cmpr7.lpm_type = "lpm_compare";
lpm_counter cntr1
(
.clock(clock),
.cnt_en(addr_counter_enable),
.cout(),
.data(addr_counter_sload_value),
.eq(),
.q(wire_cntr1_q),
.sload(addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr1.lpm_direction = "DOWN",
cntr1.lpm_modulus = 144,
cntr1.lpm_port_updown = "PORT_UNUSED",
cntr1.lpm_width = 8,
cntr1.lpm_type = "lpm_counter";
lpm_counter cntr12
(
.clock(clock),
.cnt_en(reconfig_addr_counter_enable),
.cout(),
.data(reconfig_addr_counter_sload_value),
.eq(),
.q(wire_cntr12_q),
.sload(reconfig_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr12.lpm_direction = "DOWN",
cntr12.lpm_modulus = 144,
cntr12.lpm_port_updown = "PORT_UNUSED",
cntr12.lpm_width = 8,
cntr12.lpm_type = "lpm_counter";
lpm_counter cntr13
(
.clock(clock),
.cnt_en(reconfig_width_counter_enable),
.cout(),
.data(reconfig_width_counter_sload_value),
.eq(),
.q(wire_cntr13_q),
.sload(reconfig_width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr13.lpm_direction = "DOWN",
cntr13.lpm_port_updown = "PORT_UNUSED",
cntr13.lpm_width = 6,
cntr13.lpm_type = "lpm_counter";
lpm_counter cntr14
(
.clock(clock),
.cnt_en(rotate_width_counter_enable),
.cout(),
.data(rotate_width_counter_sload_value),
.eq(),
.q(wire_cntr14_q),
.sload(rotate_width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr14.lpm_direction = "DOWN",
cntr14.lpm_port_updown = "PORT_UNUSED",
cntr14.lpm_width = 5,
cntr14.lpm_type = "lpm_counter";
lpm_counter cntr15
(
.clock(clock),
.cnt_en(rotate_addr_counter_enable),
.cout(),
.data(rotate_addr_counter_sload_value),
.eq(),
.q(wire_cntr15_q),
.sload(rotate_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr15.lpm_direction = "DOWN",
cntr15.lpm_modulus = 144,
cntr15.lpm_port_updown = "PORT_UNUSED",
cntr15.lpm_width = 8,
cntr15.lpm_type = "lpm_counter";
lpm_counter cntr2
(
.clock(clock),
.cnt_en(read_addr_counter_enable),
.cout(),
.data(read_addr_counter_sload_value),
.eq(),
.q(wire_cntr2_q),
.sload(read_addr_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr2.lpm_direction = "UP",
cntr2.lpm_port_updown = "PORT_UNUSED",
cntr2.lpm_width = 8,
cntr2.lpm_type = "lpm_counter";
lpm_counter cntr3
(
.clock(clock),
.cnt_en(width_counter_enable),
.cout(),
.data(width_counter_sload_value),
.eq(),
.q(wire_cntr3_q),
.sload(width_counter_sload)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.sclr(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cntr3.lpm_direction = "DOWN",
cntr3.lpm_port_updown = "PORT_UNUSED",
cntr3.lpm_width = 5,
cntr3.lpm_type = "lpm_counter";
lpm_decode decode11
(
.data(cuda_combout_wire),
.eq(wire_decode11_eq)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.enable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
decode11.lpm_decodes = 5,
decode11.lpm_width = 3,
decode11.lpm_type = "lpm_decode";
assign
addr_counter_enable = (write_data_state | write_nominal_state),
addr_counter_out = wire_cntr1_q,
addr_counter_sload = (write_init_state | write_init_nominal_state),
addr_counter_sload_value = (addr_decoder_out & {8{(write_init_state | write_init_nominal_state)}}),
addr_decoder_out = ((((((((((((((((((((((((((((((((((({{7{1'b0}}, (sel_type_cplf & sel_param_bypass_LF_unused)} | {{6{1'b0}}, {2{(sel_type_cplf & sel_param_c)}}}) | {{4{1'b0}}, (sel_type_cplf & sel_param_low_r), {3{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, {3{(sel_type_cplf & sel_param_odd_CP_unused)}}, 1'b0}) | {{3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale), {3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale)}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}, 1'b0, (sel_type_n & sel_param_high_i_postscale), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_low_r), {3{1'b0}}, {2{(sel_type_n & sel_param_low_r)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_nominal_count), {3{1'b0}}, {2{(sel_type_n & sel_param_nominal_count)}}}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, {2{(sel_type_m & sel_param_high_i_postscale)}}, {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_low_r)}}, 1'b0, (sel_type_m & sel_param_low_r), 1'b0, (sel_type_m & sel_param_low_r)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_nominal_count)}}, 1'b0, (sel_type_m & sel_param_nominal_count), 1'b0, (sel_type_m & sel_param_nominal_count)}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {5{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r
), {3{1'b0}}, {3{(sel_type_c0 & sel_param_low_r)}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), 1'b0, (sel_type_c1 & sel_param_high_i_postscale), {4{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, {2{(sel_type_c1 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c1 & sel_param_low_r)}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, {3{1'b0}}, (sel_type_c2 & sel_param_high_i_postscale), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, 1'b0, (sel_type_c2 & sel_param_low_r), 1'b0, {2{(sel_type_c2 & sel_param_low_r)}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale), {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {5{(sel_type_c3 & sel_param_low_r)}}, 1'b0, (sel_type_c3 & sel_param_low_r)}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {(sel_type_c4 & sel_param_high_i_postscale), {4{1'b0}}, {2{(sel_type_c4 & sel_param_high_i_postscale)}}, 1'b0}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, {4{(sel_type_c4 & sel_param_low_r)}}}),
busy = ((~ idle_state) | areset_state),
c0_wire = 8'b01000111,
c1_wire = 8'b01011001,
c2_wire = 8'b01101011,
c3_wire = 8'b01111101,
c4_wire = 8'b10001111,
counter_param_latch = counter_param_latch_reg,
counter_type_latch = counter_type_latch_reg,
cuda_combout_wire = {wire_le_comb10_combout, wire_le_comb9_combout, wire_le_comb8_combout},
data_out = {((shift_reg8[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[8] & read_nominal_out)), ((shift_reg7[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[7] & read_nominal_out)), ((shift_reg6[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[6] & read_nominal_out)), ((shift_reg5[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[5] & read_nominal_out)), ((shift_reg4[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[4] & read_nominal_out)), ((shift_reg3[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[3] & read_nominal_out)), ((shift_reg2[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[2] & read_nominal_out)), ((shift_reg1[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[1] & read_nominal_out)), ((shift_reg0[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[0] & read_nominal_out))},
dummy_scandataout = pll_scandataout,
encode_out = {C4_ena_state, (C2_ena_state | C3_ena_state), (C1_ena_state | C3_ena_state)},
input_latch_enable = (idle_state & (write_param | read_param)),
pll_areset = (pll_areset_in | (areset_state & reconfig_wait_state)),
pll_configupdate = (configupdate_state & (~ configupdate3_state)),
pll_scanclk = clock,
pll_scanclkena = ((rotate_width_counter_enable & (~ rotate_width_counter_done)) | reconfig_seq_data_state),
pll_scandata = (scan_cache_out & ((rotate_width_counter_enable | reconfig_seq_data_state) | reconfig_post_state)),
power_up = ((((((((((((((((((((~ reset_state) & (~ idle_state)) & (~ read_init_state)) & (~ read_first_state)) & (~ read_data_state)) & (~ read_last_state)) & (~ read_init_nominal_state)) & (~ read_first_nominal_state)) & (~ read_data_nominal_state)) & (~ read_last_nominal_state)) & (~ write_init_state)) & (~ write_data_state)) & (~ write_init_nominal_state)) & (~ write_nominal_state)) & (~ reconfig_init_state)) & (~ reconfig_counter_state)) & (~ reconfig_seq_ena_state)) & (~ reconfig_seq_data_state)) & (~ reconfig_post_state)) & (~ reconfig_wait_state)),
read_addr_counter_enable = (((read_first_state | read_data_state) | read_first_nominal_state) | read_data_nominal_state),
read_addr_counter_out = wire_cntr2_q,
read_addr_counter_sload = (read_init_state | read_init_nominal_state),
read_addr_counter_sload_value = (read_addr_decoder_out & {8{(read_init_state | read_init_nominal_state)}}),
read_addr_decoder_out = ((((((((((((((((((((((((((((((((((({8{1'b0}} | {{6{1'b0}}, (sel_type_cplf & sel_param_c), 1'b0}) | {{5{1'b0}}, (sel_type_cplf & sel_param_low_r), {2{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0}) | {{4{1'b0}}, {4{(sel_type_cplf & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, (sel_type_n & sel_param_high_i_postscale), {2{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{3{1'b0}}, {3{(sel_type_n & sel_param_low_r)}}, {2{1'b0}}}) | {{3{1'b0}}, (sel_type_n & sel_param_nominal_count), {2{1'b0}}, (sel_type_n & sel_param_nominal_count), 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, (sel_type_m & sel_param_high_i_postscale)}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, (sel_type_m & sel_param_low_r), 1'b0, {3{(sel_type_m & sel_param_low_r)}}, 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0, {3{(sel_type_c0 & sel_param_high_i_postscale)}}}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r), {6{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused
), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale)}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, (sel_type_c1 & sel_param_low_r), {2{1'b0}}, (sel_type_c1 & sel_param_low_r), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_high_i_postscale), 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c2 & sel_param_low_r), {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale)}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {3{(sel_type_c3 & sel_param_low_r)}}, 1'b0, {2{(sel_type_c3 & sel_param_low_r)}}, 1'b0}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {1'b0, {7{(sel_type_c4 & sel_param_high_i_postscale)}}}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, (sel_type_c4 & sel_param_low_r), {3{1'b0}}}),
read_nominal_out = tmp_nominal_data_out_state,
reconfig_addr_counter_enable = reconfig_seq_data_state,
reconfig_addr_counter_out = wire_cntr12_q,
reconfig_addr_counter_sload = reconfig_seq_ena_state,
reconfig_addr_counter_sload_value = ({8{reconfig_seq_ena_state}} & seq_addr_wire),
reconfig_done = ((~ pll_scandone) & (dummy_scandataout | (~ dummy_scandataout))),
reconfig_post_done = pll_scandone,
reconfig_width_counter_done = ((((((~ wire_cntr13_q[0]) & (~ wire_cntr13_q[1])) & (~ wire_cntr13_q[2])) & (~ wire_cntr13_q[3])) & (~ wire_cntr13_q[4])) & (~ wire_cntr13_q[5])),
reconfig_width_counter_enable = reconfig_seq_data_state,
reconfig_width_counter_sload = reconfig_seq_ena_state,
reconfig_width_counter_sload_value = ({6{reconfig_seq_ena_state}} & seq_sload_value),
rotate_addr_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
rotate_addr_counter_out = wire_cntr15_q,
rotate_addr_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
rotate_addr_counter_sload_value = (((((c0_wire & {8{rotate_decoder_wires[0]}}) | (c1_wire & {8{rotate_decoder_wires[1]}})) | (c2_wire & {8{rotate_decoder_wires[2]}})) | (c3_wire & {8{rotate_decoder_wires[3]}})) | (c4_wire & {8{rotate_decoder_wires[4]}})),
rotate_decoder_wires = wire_decode11_eq,
rotate_width_counter_done = (((((~ wire_cntr14_q[0]) & (~ wire_cntr14_q[1])) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[3])) & (~ wire_cntr14_q[4])),
rotate_width_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
rotate_width_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
rotate_width_counter_sload_value = 5'b10010,
scan_cache_address = ((((addr_counter_out & {8{addr_counter_enable}}) | (read_addr_counter_out & {8{read_addr_counter_enable}})) | (rotate_addr_counter_out & {8{rotate_addr_counter_enable}})) | (reconfig_addr_counter_out & {8{reconfig_addr_counter_enable}})),
scan_cache_in = shift_reg_serial_out,
scan_cache_out = wire_altsyncram4_q_a[0],
scan_cache_write_enable = (write_data_state | write_nominal_state),
sel_param_bypass_LF_unused = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & counter_param_latch[2]),
sel_param_c = (((~ counter_param_latch[0]) & counter_param_latch[1]) & (~ counter_param_latch[2])),
sel_param_high_i_postscale = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
sel_param_low_r = ((counter_param_latch[0] & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
sel_param_nominal_count = ((counter_param_latch[0] & counter_param_latch[1]) & counter_param_latch[2]),
sel_param_odd_CP_unused = ((counter_param_latch[0] & (~ counter_param_latch[1])) & counter_param_latch[2]),
sel_type_c0 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c1 = (((counter_type_latch[0] & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c2 = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c3 = (((counter_type_latch[0] & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
sel_type_c4 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & counter_type_latch[3]),
sel_type_cplf = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_m = (((counter_type_latch[0] & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_n = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
sel_type_vco = (((counter_type_latch[0] & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
seq_addr_wire = 8'b00110101,
seq_sload_value = 6'b110110,
shift_reg_clear = (read_init_state | read_init_nominal_state),
shift_reg_load_enable = ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]))),
shift_reg_load_nominal_enable = ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])),
shift_reg_serial_in = scan_cache_out,
shift_reg_serial_out = ((((((((shift_reg17[0:0] & shift_reg_width_select[0]) | (shift_reg17[0:0] & shift_reg_width_select[1])) | (shift_reg17[0:0] & shift_reg_width_select[2])) | (shift_reg17[0:0] & shift_reg_width_select[3])) | (shift_reg17[0:0] & shift_reg_width_select[4])) | (shift_reg17[0:0] & shift_reg_width_select[5])) | (shift_reg17[0:0] & shift_reg_width_select[6])) | (shift_reg17[0:0] & shift_reg_width_select[7])),
shift_reg_shift_enable = ((read_data_state | read_last_state) | write_data_state),
shift_reg_shift_nominal_enable = ((read_data_nominal_state | read_last_nominal_state) | write_nominal_state),
shift_reg_width_select = width_decoder_select,
w1565w = 1'b0,
w1592w = 1'b0,
w64w = 1'b0,
width_counter_done = (((((~ wire_cntr3_q[0]) & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[2])) & (~ wire_cntr3_q[3])) & (~ wire_cntr3_q[4])),
width_counter_enable = ((((read_first_state | read_data_state) | write_data_state) | read_data_nominal_state) | write_nominal_state),
width_counter_sload = (((read_init_state | write_init_state) | read_init_nominal_state) | write_init_nominal_state),
width_counter_sload_value = width_decoder_out,
width_decoder_out = ((((({5{1'b0}} | {width_decoder_select[2], {3{1'b0}}, width_decoder_select[2]}) | {{4{1'b0}}, width_decoder_select[3]}) | {{2{1'b0}}, {3{width_decoder_select[5]}}}) | {{3{1'b0}}, width_decoder_select[6], 1'b0}) | {{2{1'b0}}, width_decoder_select[7], {2{1'b0}}}),
width_decoder_select = {((sel_type_cplf & sel_param_low_r) | (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) | (sel_type_n & sel_param_low_r)) | (sel_type_m & sel_param_high_i_postscale)) | (sel_type_m & sel_param_low_r)) | (sel_type_c0 & sel_param_high_i_postscale)) | (sel_type_c0 & sel_param_low_r)) | (sel_type_c1 & sel_param_high_i_postscale)) | (sel_type_c1 & sel_param_low_r)) | (sel_type_c2 & sel_param_high_i_postscale)) | (sel_type_c2 & sel_param_low_r)) | (sel_type_c3 & sel_param_high_i_postscale)) | (sel_type_c3 & sel_param_low_r)) | (sel_type_c4 & sel_param_high_i_postscale)) | (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) | (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) | (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) | (sel_type_n & sel_param_bypass_LF_unused)) | (sel_type_n & sel_param_odd_CP_unused)) | (sel_type_m & sel_param_bypass_LF_unused)) | (sel_type_m & sel_param_odd_CP_unused)) | (sel_type_c0 & sel_param_bypass_LF_unused)) | (sel_type_c0 & sel_param_odd_CP_unused)) | (sel_type_c1 & sel_param_bypass_LF_unused)) | (sel_type_c1 & sel_param_odd_CP_unused)) | (sel_type_c2 & sel_param_bypass_LF_unused)) | (sel_type_c2 & sel_param_odd_CP_unused)) | (sel_type_c3 & sel_param_bypass_LF_unused)) | (sel_type_c3 & sel_param_odd_CP_unused)) | (sel_type_c4 & sel_param_bypass_LF_unused)) | (sel_type_c4 & sel_param_odd_CP_unused))},
write_from_rom = 1'b0;
endmodule //pll_cfg_pllrcfg_9mu
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll_cfg (
clock,
counter_param,
counter_type,
data_in,
pll_areset_in,
pll_scandataout,
pll_scandone,
read_param,
reconfig,
reset,
write_param,
busy,
data_out,
pll_areset,
pll_configupdate,
pll_scanclk,
pll_scanclkena,
pll_scandata)/* synthesis synthesis_clearbox = 2 */;
input clock;
input [2:0] counter_param;
input [3:0] counter_type;
input [8:0] data_in;
input pll_areset_in;
input pll_scandataout;
input pll_scandone;
input read_param;
input reconfig;
input reset;
input write_param;
output busy;
output [8:0] data_out;
output pll_areset;
output pll_configupdate;
output pll_scanclk;
output pll_scanclkena;
output pll_scandata;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 pll_areset_in;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [8:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire pll_configupdate = sub_wire0;
wire [8:0] data_out = sub_wire1[8:0];
wire pll_scanclk = sub_wire2;
wire pll_scanclkena = sub_wire3;
wire pll_scandata = sub_wire4;
wire busy = sub_wire5;
wire pll_areset = sub_wire6;
pll_cfg_pllrcfg_9mu pll_cfg_pllrcfg_9mu_component (
.counter_param (counter_param),
.data_in (data_in),
.counter_type (counter_type),
.pll_areset_in (pll_areset_in),
.reconfig (reconfig),
.pll_scandataout (pll_scandataout),
.pll_scandone (pll_scandone),
.reset (reset),
.write_param (write_param),
.clock (clock),
.read_param (read_param),
.pll_configupdate (sub_wire0),
.data_out (sub_wire1),
.pll_scanclk (sub_wire2),
.pll_scanclkena (sub_wire3),
.pll_scandata (sub_wire4),
.busy (sub_wire5),
.pll_areset (sub_wire6))/* synthesis synthesis_clearbox=2
clearbox_macroname = altpll_reconfig
clearbox_defparam = "init_from_rom=YES;intended_device_family=Cyclone IV E;scan_init_file=./pll_dyn.mif;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./pll_dyn.mif"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_INIT_FILE STRING "1"
// Retrieval info: CONSTANT: INIT_FROM_ROM STRING "NO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: SCAN_INIT_FILE STRING "./pll_dyn.mif"
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
// Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
// Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
// Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
// Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
// Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
// Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
// Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
// Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
// Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
// Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
// Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
// Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
// Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
// Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
// Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
// Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
// Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
// Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
// Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
// Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
// Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
// Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
// Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
// Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
// Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
// Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
// Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
// Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_cfg.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_cfg.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_cfg.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_cfg.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_cfg_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_cfg_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cycloneive
// Retrieval info: LIB_FILE: lpm
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: ADDSUBWIDE.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ADDSUBWIDE (
add_sub,
dataa,
datab,
result);
input add_sub;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
wire [25:0] sub_wire0;
wire [25:0] result = sub_wire0[25:0];
lpm_add_sub LPM_ADD_SUB_component (
.add_sub (add_sub),
.dataa (dataa),
.datab (datab),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.cin (),
.clken (),
.clock (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "UNUSED",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 26;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "2"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "26"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
// Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL "add_sub"
// Retrieval info: USED_PORT: dataa 0 0 26 0 INPUT NODEFVAL "dataa[25..0]"
// Retrieval info: USED_PORT: datab 0 0 26 0 INPUT NODEFVAL "datab[25..0]"
// Retrieval info: USED_PORT: result 0 0 26 0 OUTPUT NODEFVAL "result[25..0]"
// Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 26 0 dataa 0 0 26 0
// Retrieval info: CONNECT: @datab 0 0 26 0 datab 0 0 26 0
// Retrieval info: CONNECT: result 0 0 26 0 @result 0 0 26 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ADDSUBWIDE.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADDSUBWIDE.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADDSUBWIDE.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADDSUBWIDE.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADDSUBWIDE_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ADDSUBWIDE_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A21O_FUNCTIONAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21O_FUNCTIONAL_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 1.9
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/07 13:45:16 $
// \ \ / \ Date Created : Tue Sept 21 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level testbench for testing DDR3.
// Instantiates:
// 1. IP_TOP (top-level representing FPGA, contains core,
// clocking, built-in testbench/memory checker and other
// support structures)
// 2. DDR3 Memory
// 3. Miscellaneous clock generation and reset logic
// 4. For ECC ON case inserts error on LSB bit
// of data from DRAM to FPGA.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/100fs
module sim_tb_top;
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter SIMULATION = "TRUE";
parameter BL_WIDTH = 10;
parameter PORT_MODE = "BI_MODE";
parameter DATA_MODE = 4'b0010;
parameter ADDR_MODE = 4'b0011;
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE";
parameter EYE_TEST = "FALSE";
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL";
// For small devices, choose one only.
// For large device, choose "DGEN_ALL"
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL";
// "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000;
parameter END_ADDRESS = 32'h00000fff;
parameter PRBS_EADDR_MASK_POS = 32'hff000000;
parameter SEL_VICTIM_LINE = 11;
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 2;
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 2;
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 2;
// # of CKE outputs to memory.
parameter DATA_BUF_ADDR_WIDTH = 4;
parameter DQ_CNT_WIDTH = 6;
// = ceil(log2(DQ_WIDTH))
parameter DQ_PER_DM = 8;
parameter DM_WIDTH = 8;
// # of DM (data mask)
parameter DQ_WIDTH = 64;
// # of DQ (data)
parameter DQS_WIDTH = 8;
parameter DQS_CNT_WIDTH = 3;
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8;
// # of DQ per DQS
parameter ECC = "OFF";
parameter nBANK_MACHS = 4;
parameter RANKS = 2;
// # of Ranks.
parameter ODT_WIDTH = 2;
// # of ODT outputs to memory.
parameter ROW_WIDTH = 15;
// # of memory Row Address bits.
parameter ADDR_WIDTH = 29;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
parameter USE_CS_PORT = 1;
// # = 1, When CS output is enabled
// = 0, When CS output is disabled
// If CS_N disabled, user must connect
// DRAM CS_N input(s) to ground
parameter USE_DM_PORT = 1;
// # = 1, When Data Mask option is enabled
// = 0, When Data Mask option is disbaled
// When Data Mask option is disabled in
// MIG Controller Options page, the logic
// related to Data Mask should not get
// synthesized
parameter USE_ODT_PORT = 1;
// # = 1, When ODT output is enabled
// = 0, When ODT output is disabled
// Parameter configuration for Dynamic ODT support:
// USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120".
// This configuration allows to save ODT pin mapping from FPGA.
// The user can tie the ODT input of DRAM to HIGH.
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter AL = "0";
// DDR3 SDRAM:
// Additive Latency (Mode Register 1).
// # = "0", "CL-1", "CL-2".
// DDR2 SDRAM:
// Additive Latency (Extended Mode Register).
parameter nAL = 0;
// # Additive Latency in number of clock
// cycles.
parameter BURST_MODE = "8";
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
parameter BURST_TYPE = "SEQ";
// DDR3 SDRAM: Burst Type (Mode Register 0).
// DDR2 SDRAM: Burst Type (Mode Register).
// # = "SEQ" - (Sequential),
// = "INT" - (Interleaved).
parameter CL = 6;
// in number of clock cycles
// DDR3 SDRAM: CAS Latency (Mode Register 0).
// DDR2 SDRAM: CAS Latency (Mode Register).
parameter CWL = 5;
// in number of clock cycles
// DDR3 SDRAM: CAS Write Latency (Mode Register 2).
// DDR2 SDRAM: Can be ignored
parameter OUTPUT_DRV = "HIGH";
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter RTT_NOM = "60";
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF";
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter ADDR_CMD_MODE = "1T" ;
// # = "1T", "2T".
parameter REG_CTRL = "OFF";
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
parameter CA_MIRROR = "OFF";
// C/A mirror opt for DDR3 dual rank
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 20000;
// Input Clock Period
parameter CLKFBOUT_MULT = 16;
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1;
// write PLL VCO divisor
parameter CLKOUT0_DIVIDE = 2;
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 2;
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 32;
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 4;
// VCO output divisor for PLL output clock (CLKOUT3)
//***************************************************************************
// Memory Timing Parameters. These parameters varies based on the selected
// memory part.
//***************************************************************************
parameter tCKE = 5000;
// memory tCKE paramter in pS
parameter tFAW = 32000;
// memory tRAW paramter in pS.
parameter tRAS = 35000;
// memory tRAS paramter in pS.
parameter tRCD = 13125;
// memory tRCD paramter in pS.
parameter tREFI = 7800000;
// memory tREFI paramter in pS.
parameter tRFC = 160000;
// memory tRFC paramter in pS.
parameter tRP = 13125;
// memory tRP paramter in pS.
parameter tRRD = 6000;
// memory tRRD paramter in pS.
parameter tRTP = 7500;
// memory tRTP paramter in pS.
parameter tWTR = 7500;
// memory tWTR paramter in pS.
parameter tZQI = 128_000_000;
// memory tZQI paramter in nS.
parameter tZQCS = 64;
// memory tZQCS paramter in clock cycles.
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "SIM_INIT_CAL_FULL" - Complete
// memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// The following parameters varies based on the pin out entered in MIG GUI.
// Do not change any of these parameters directly by editing the RTL.
// Any changes required should be done through GUI and the design regenerated.
//***************************************************************************
parameter BYTE_LANES_B0 = 4'b1111;
// Byte lanes used in an IO column.
parameter BYTE_LANES_B1 = 4'b1111;
// Byte lanes used in an IO column.
parameter BYTE_LANES_B2 = 4'b1111;
// Byte lanes used in an IO column.
parameter BYTE_LANES_B3 = 4'b0000;
// Byte lanes used in an IO column.
parameter BYTE_LANES_B4 = 4'b0000;
// Byte lanes used in an IO column.
parameter DATA_CTL_B0 = 4'b1111;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B1 = 4'b0000;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B2 = 4'b1111;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B3 = 4'b0000;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter DATA_CTL_B4 = 4'b0000;
// Indicates Byte lane is data byte lane
// or control Byte lane. '1' in a bit
// position indicates a data byte lane and
// a '0' indicates a control byte lane
parameter PHY_0_BITLANES = 48'h3FE_3FE_3FE_2FF;
parameter PHY_1_BITLANES = 48'hFFF_FD3_43E_000;
parameter PHY_2_BITLANES = 48'h3FE_3FE_3FE_2FF;
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_10_10;
parameter ADDR_MAP
= 192'h000_126_115_131_135_138_13A_128_130_127_124_129_132_12A_12B_136;
parameter BANK_MAP = 36'h134_133_137;
parameter CAS_MAP = 12'h112;
parameter CKE_ODT_BYTE_MAP = 8'h00;
parameter CKE_MAP = 96'h000_000_000_000_000_000_121_120;
parameter ODT_MAP = 96'h000_000_000_000_000_000_111_113;
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_139_13B;
parameter PARITY_MAP = 12'h000;
parameter RAS_MAP = 12'h11A;
parameter WE_MAP = 12'h114;
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_20_21_22_23_00_01_02_03;
parameter DATA0_MAP = 96'h039_033_038_037_032_031_035_036;
parameter DATA1_MAP = 96'h022_024_028_029_023_021_027_026;
parameter DATA2_MAP = 96'h016_011_013_012_015_014_018_019;
parameter DATA3_MAP = 96'h003_002_006_004_009_001_000_007;
parameter DATA4_MAP = 96'h238_239_237_234_232_233_235_236;
parameter DATA5_MAP = 96'h221_224_227_226_222_223_229_225;
parameter DATA6_MAP = 96'h211_213_219_216_214_215_212_217;
parameter DATA7_MAP = 96'h202_204_207_201_206_203_200_205;
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000;
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000;
parameter MASK0_MAP = 108'h000_209_218_228_231_005_017_025_034;
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000;
parameter SLOT_0_CONFIG = 8'b0000_0011;
// Mapping of Ranks.
parameter SLOT_1_CONFIG = 8'b0000_0000;
// Mapping of Ranks.
parameter MEM_ADDR_ORDER
= "TG_TEST";
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IODELAY_HP_MODE = "ON";
// to phy_top
parameter IBUF_LPWR_MODE = "OFF";
// to phy_top
parameter DATA_IO_IDLE_PWRDWN = "OFF";
// # = "ON", "OFF"
parameter DATA_IO_PRIM_TYPE = "DEFAULT";
// # = "HP_LP", "HR_LP", "DEFAULT"
parameter USER_REFRESH = "OFF";
parameter WRLVL = "ON";
// # = "ON" - DDR3 SDRAM
// = "OFF" - DDR2 SDRAM.
parameter ORDERING = "NORM";
// # = "NORM", "STRICT", "RELAXED".
parameter CALIB_ROW_ADD = 16'h0000;
// Calibration row address will be used for
// calibration read and write operations
parameter CALIB_COL_ADD = 12'h000;
// Calibration column address will be used for
// calibration read and write operations
parameter CALIB_BA_ADD = 3'h0;
// Calibration bank address will be used for
// calibration read and write operations
parameter TCQ = 100;
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter IODELAY_GRP = "IODELAY_MIG";
// It is associated to a set of IODELAYs with
// an IDELAYCTRL that have same IODELAY CONTROLLER
// clock frequency.
parameter SYSCLK_TYPE = "DIFFERENTIAL";
// System clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter REFCLK_TYPE = "NO_BUFFER";
// Reference clock type DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter RST_ACT_LOW = 1;
// =1 for active low reset,
// =0 for active high.
parameter CAL_WIDTH = "HALF";
parameter STARVE_LIMIT = 2;
// # = 2,3,4.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0;
// IODELAYCTRL reference clock frequency
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 2500;
// memory tCK paramter.
// # = Clock Period in pS.
parameter nCK_PER_CLK = 2;
// # of memory CKs per fabric CLK
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DRAM_TYPE = "DDR3";
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00;
// Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00;
// Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00;
// Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00;
// Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00;
// Delay for data signal during Read operation
localparam MEMORY_WIDTH = 8;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam RESET_PERIOD = 200000; //in pSec
localparam real SYSCLK_PERIOD = tCK;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wire sys_rst;
reg sys_clk_i;
wire sys_clk_p;
wire sys_clk_n;
reg clk_ref_i;
wire ddr3_reset_n;
wire [DQ_WIDTH-1:0] ddr3_dq_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga;
wire [ROW_WIDTH-1:0] ddr3_addr_fpga;
wire [BANK_WIDTH-1:0] ddr3_ba_fpga;
wire ddr3_ras_n_fpga;
wire ddr3_cas_n_fpga;
wire ddr3_we_n_fpga;
wire [CKE_WIDTH-1:0] ddr3_cke_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_n_fpga;
wire init_calib_complete;
wire tg_compare_error;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_fpga;
wire [DM_WIDTH-1:0] ddr3_dm_fpga;
wire [ODT_WIDTH-1:0] ddr3_odt_fpga;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram_tmp;
reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp;
reg [ODT_WIDTH-1:0] ddr3_odt_sdram_tmp;
wire [DQ_WIDTH-1:0] ddr3_dq_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_sdram [0:1];
reg [BANK_WIDTH-1:0] ddr3_ba_sdram [0:1];
reg ddr3_ras_n_sdram;
reg ddr3_cas_n_sdram;
reg ddr3_we_n_sdram;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram;
wire [ODT_WIDTH-1:0] ddr3_odt_sdram;
reg [CKE_WIDTH-1:0] ddr3_cke_sdram;
wire [DM_WIDTH-1:0] ddr3_dm_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_n_sdram;
//**************************************************************************//
//**************************************************************************//
// Reset Generation
//**************************************************************************//
initial begin
sys_rst_n = 1'b0;
#RESET_PERIOD
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
//**************************************************************************//
// Clock Generation
//**************************************************************************//
initial
sys_clk_i = 1'b0;
always
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
assign sys_clk_p = sys_clk_i;
assign sys_clk_n = ~sys_clk_i;
initial
clk_ref_i = 1'b0;
always
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
always @( * ) begin
ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga;
ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga;
ddr3_addr_sdram[0] <= #(TPROP_PCB_CTRL) ddr3_addr_fpga;
ddr3_addr_sdram[1] <= #(TPROP_PCB_CTRL) (CA_MIRROR == "ON") ?
{ddr3_addr_fpga[ROW_WIDTH-1:9],
ddr3_addr_fpga[7], ddr3_addr_fpga[8],
ddr3_addr_fpga[5], ddr3_addr_fpga[6],
ddr3_addr_fpga[3], ddr3_addr_fpga[4],
ddr3_addr_fpga[2:0]} :
ddr3_addr_fpga;
ddr3_ba_sdram[0] <= #(TPROP_PCB_CTRL) ddr3_ba_fpga;
ddr3_ba_sdram[1] <= #(TPROP_PCB_CTRL) (CA_MIRROR == "ON") ?
{ddr3_ba_fpga[BANK_WIDTH-1:2],
ddr3_ba_fpga[0],
ddr3_ba_fpga[1]} :
ddr3_ba_fpga;
ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga;
ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga;
ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga;
ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga;
end
always @( * )
ddr3_cs_n_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga;
assign ddr3_cs_n_sdram = ddr3_cs_n_sdram_tmp;
always @( * )
ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation
assign ddr3_dm_sdram = ddr3_dm_sdram_tmp;
always @( * )
ddr3_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr3_odt_fpga;
assign ddr3_odt_sdram = ddr3_odt_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq
(
.A (ddr3_dq_fpga[dqwd]),
.B (ddr3_dq_sdram[dqwd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
// For ECC ON case error is inserted on LSB bit from DRAM to FPGA
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT (ECC)
)
u_delay_dq_0
(
.A (ddr3_dq_fpga[0]),
.B (ddr3_dq_sdram[0]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_p
(
.A (ddr3_dqs_p_fpga[dqswd]),
.B (ddr3_dqs_p_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_n
(
.A (ddr3_dqs_n_fpga[dqswd]),
.B (ddr3_dqs_n_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
endgenerate
//===========================================================================
// FPGA Memory Controller
//===========================================================================
example_top #
(
.SIMULATION (SIMULATION),
.BL_WIDTH (BL_WIDTH),
.PORT_MODE (PORT_MODE),
.DATA_MODE (DATA_MODE),
.ADDR_MODE (ADDR_MODE),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
.EYE_TEST (EYE_TEST),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_PER_DM (DQ_PER_DM),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.AL (AL),
.nAL (nAL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CL (CL),
.CWL (CWL),
.OUTPUT_DRV (OUTPUT_DRV),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.REG_CTRL (REG_CTRL),
.CA_MIRROR (CA_MIRROR),
.CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.tCKE (tCKE),
.tFAW (tFAW),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.USER_REFRESH (USER_REFRESH),
.WRLVL (WRLVL),
.ORDERING (ORDERING),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.TCQ (TCQ),
.IODELAY_GRP (IODELAY_GRP),
.SYSCLK_TYPE (SYSCLK_TYPE),
.REFCLK_TYPE (REFCLK_TYPE),
.DRAM_TYPE (DRAM_TYPE),
.CAL_WIDTH (CAL_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT),
.REFCLK_FREQ (REFCLK_FREQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.DEBUG_PORT (DEBUG_PORT),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_ip_top
(
.ddr3_dq (ddr3_dq_fpga),
.ddr3_dqs_n (ddr3_dqs_n_fpga),
.ddr3_dqs_p (ddr3_dqs_p_fpga),
.ddr3_addr (ddr3_addr_fpga),
.ddr3_ba (ddr3_ba_fpga),
.ddr3_ras_n (ddr3_ras_n_fpga),
.ddr3_cas_n (ddr3_cas_n_fpga),
.ddr3_we_n (ddr3_we_n_fpga),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_ck_p (ddr3_ck_p_fpga),
.ddr3_ck_n (ddr3_ck_n_fpga),
.ddr3_cke (ddr3_cke_fpga),
.ddr3_cs_n (ddr3_cs_n_fpga),
.ddr3_dm (ddr3_dm_fpga),
.ddr3_odt (ddr3_odt_fpga),
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.clk_ref_i (clk_ref_i),
.device_temp_i (12'b0),
.init_calib_complete (init_calib_complete),
.tg_compare_error (tg_compare_error),
.sys_rst (sys_rst)
);
//**************************************************************************//
// Memory Models instantiations
//**************************************************************************//
genvar r,i;
generate
for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram[r]),
.addr (ddr3_addr_sdram[r]),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
endgenerate
//***************************************************************************
// Reporting the test case status
// Status reporting logic exists both in simulation test bench (sim_tb_top)
// and sim.do file for ModelSim. Any update in simulation run time or time out
// in this file need to be updated in sim.do file as well.
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (init_calib_complete);
$display("Calibration Done");
#50000000.0;
if (!tg_compare_error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
if (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")
#2500000000.0;
else
#1000000000.0;
if (!init_calib_complete) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* FSM: finite state machine
* halt if $ctrl == 0$
*/
module FSM(clk, reset, rom_addr, rom_q, ram_a_addr, ram_b_addr, ram_b_w, pe, done);
input clk;
input reset;
output reg [8:0] rom_addr; /* command id. extra bits? */
input [25:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
output ram_b_w;
output reg [10:0] pe;
output reg done;
reg [5:0] state;
parameter START=0, READ_SRC1=1, READ_SRC2=2, CALC=4, WAIT=8, WRITE=16, DON=32;
wire [5:0] dest, src1, src2, times; wire [1:0] op;
assign {dest, src1, op, times, src2} = rom_q;
reg [5:0] count;
always @ (posedge clk)
if (reset)
state<=START;
else
case (state)
START:
state<=READ_SRC1;
READ_SRC1:
state<=READ_SRC2;
READ_SRC2:
if (times==0) state<=DON; else state<=CALC;
CALC:
if (count==1) state<=WAIT;
WAIT:
state<=WRITE;
WRITE:
state<=READ_SRC1;
endcase
/* we support two loops with 48 loop times */
parameter LOOP1_START = 9'd22,
LOOP1_END = 9'd117,
LOOP2_START = 9'd280,
LOOP2_END = 9'd293;
reg [46:0] loop1, loop2;
always @ (posedge clk)
if (reset) rom_addr<=0;
else if (state==WAIT)
begin
if(rom_addr == LOOP1_END && loop1[0])
rom_addr <= LOOP1_START;
else if(rom_addr == LOOP2_END && loop2[0])
rom_addr <= LOOP2_START;
else
rom_addr <= rom_addr + 1;
end
always @ (posedge clk)
if (reset) loop1 <= ~0;
else if(state==WAIT && rom_addr==LOOP1_END)
loop1 <= loop1 >> 1;
always @ (posedge clk)
if (reset) loop2 <= ~0;
else if(state==WAIT && rom_addr==LOOP2_END)
loop2 <= loop2 >> 1;
always @ (posedge clk)
if (reset)
count<=0;
else if (state==READ_SRC1)
count<=times;
else if (state==CALC)
count<=count-1;
always @ (posedge clk)
if (reset) done<=0;
else if (state==DON) done<=1;
else done<=0;
always @ (state, src1, src2)
case (state)
READ_SRC1: ram_a_addr=src1;
READ_SRC2: ram_a_addr=src2;
default: ram_a_addr=0;
endcase
parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
always @ (posedge clk)
case (state)
READ_SRC1:
case (op)
ADD: pe<=11'b11001000000;
SUB: pe<=11'b11001000000;
CUBIC: pe<=11'b11111000000;
MULT: pe<=11'b11110000000;
default: pe<=0;
endcase
READ_SRC2:
case (op)
ADD: pe<=11'b00110000000;
SUB: pe<=11'b00110000000;
CUBIC: pe<=0;
MULT: pe<=11'b00001000000;
default: pe<=0;
endcase
CALC:
case (op)
ADD: pe<=11'b00000010001;
SUB: pe<=11'b00000010001;
CUBIC: pe<=11'b01010000001;
MULT: pe<=11'b00000111111;
default: pe<=0;
endcase
default:
pe<=0;
endcase
always @ (state, op, src2, dest)
case (state)
READ_SRC1:
case (op)
ADD: ram_b_addr=CMD_ADD;
SUB: ram_b_addr=CMD_SUB;
CUBIC: ram_b_addr=CMD_CUBIC;
default: ram_b_addr=0;
endcase
READ_SRC2: ram_b_addr=src2;
WRITE: ram_b_addr=dest;
default: ram_b_addr=0;
endcase
assign ram_b_w = (state==WRITE) ? 1'b1 : 1'b0;
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lcd_0 (
// inputs:
address,
begintransfer,
clk,
read,
reset_n,
write,
writedata,
// outputs:
LCD_E,
LCD_RS,
LCD_RW,
LCD_data,
readdata
)
;
output LCD_E;
output LCD_RS;
output LCD_RW;
inout [ 7: 0] LCD_data;
output [ 7: 0] readdata;
input [ 1: 0] address;
input begintransfer;
input clk;
input read;
input reset_n;
input write;
input [ 7: 0] writedata;
wire LCD_E;
wire LCD_RS;
wire LCD_RW;
wire [ 7: 0] LCD_data;
wire [ 7: 0] readdata;
assign LCD_RW = address[0];
assign LCD_RS = address[1];
assign LCD_E = read | write;
assign LCD_data = (address[0]) ? 8'bz : writedata;
assign readdata = LCD_data;
//control_slave, which is an e_avalon_slave
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axis_dma_rx (
// adc interface
adc_clk,
adc_rst,
// dma interface
dma_clk,
dma_rst,
dma_start,
dma_stream,
dma_count,
dma_ovf,
dma_unf,
dma_status,
dma_bw,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00050063;
parameter PCORE_ID = 0;
// adc interface
input adc_clk;
output adc_rst;
// dma interface
input dma_clk;
output dma_rst;
output dma_start;
output dma_stream;
output [31:0] dma_count;
input dma_ovf;
input dma_unf;
input dma_status;
input [31:0] dma_bw;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_dma_stream = 'd0;
reg up_dma_start = 'd0;
reg [31:0] up_dma_count = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg dma_start_d = 'd0;
reg dma_start_2d = 'd0;
reg dma_start = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire up_dma_ovf_s;
wire up_dma_unf_s;
wire up_dma_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_waddr[13:8] == 6'h00) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_dma_stream <= 'd0;
up_dma_start <= 'd0;
up_dma_count <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_dma_stream <= up_wdata[1];
up_dma_start <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_dma_count <= up_wdata;
end
if (up_dma_ovf_s == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[2];
end
if (up_dma_unf_s == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[1];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'd0, up_resetn};
8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start};
8'h21: up_rdata <= up_dma_count;
8'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status_s};
8'h23: up_rdata <= dma_bw;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(adc_clk), .rst(adc_rst));
ad_rst i_dma_rst_reg (.preset(up_preset_s), .clk(dma_clk), .rst(dma_rst));
// dma control & status
up_xfer_cntrl #(.DATA_WIDTH(34)) i_dma_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_dma_start,
up_dma_stream,
up_dma_count}),
.d_rst (dma_rst),
.d_clk (dma_clk),
.d_data_cntrl ({ dma_start_s,
dma_stream,
dma_count}));
up_xfer_status #(.DATA_WIDTH(3)) i_dma_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_dma_ovf_s,
up_dma_unf_s,
up_dma_status_s}),
.d_rst (dma_rst),
.d_clk (dma_clk),
.d_data_status ({ dma_ovf,
dma_unf,
dma_status}));
// start needs to be a pulse
always @(posedge dma_clk) begin
dma_start_d <= dma_start_s;
dma_start_2d <= dma_start_d;
dma_start <= dma_start_d & ~dma_start_2d;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
module MyInterSynthModule(bitdata, AdcConvComplete_i, AdcDoConvert_o, AdcValue_i, I2C_Busy_i, I2C_DataIn_o, I2C_DataOut_i, I2C_Error_i, I2C_FIFOEmpty_i, I2C_FIFOFull_i, I2C_FIFOReadNext_o, I2C_FIFOWrite_o, I2C_ReadCount_o, I2C_ReceiveSend_n_o, I2C_StartProcess_o, Inputs_i_0, Inputs_i_1, Inputs_i_2, Inputs_i_3, Inputs_i_4, Inputs_i_5, Inputs_i_6, Inputs_i_7, Outputs_o_0, Outputs_o_1, Outputs_o_2, Outputs_o_3, Outputs_o_4, Outputs_o_5, Outputs_o_6, Outputs_o_7, ReconfModuleIRQs_o_0, ReconfModuleIRQs_o_1, ReconfModuleIRQs_o_2, ReconfModuleIRQs_o_3, ReconfModuleIRQs_o_4, SPI_CPHA_o, SPI_CPOL_o, SPI_DataIn_o, SPI_DataOut_i, SPI_FIFOEmpty_i, SPI_FIFOFull_i, SPI_LSBFE_o, SPI_ReadNext_o, SPI_Transmission_i, SPI_Write_o, ReconfModuleIn_i_0, ReconfModuleIn_i_1, ReconfModuleIn_i_2, ReconfModuleIn_i_3, ReconfModuleIn_i_4, ReconfModuleIn_i_5, ReconfModuleIn_i_6, ReconfModuleIn_i_7, ReconfModuleOut_o_0, ReconfModuleOut_o_1, ReconfModuleOut_o_2, ReconfModuleOut_o_3, ReconfModuleOut_o_4, ReconfModuleOut_o_5, ReconfModuleOut_o_6, ReconfModuleOut_o_7, ParamIn_Word_i, ParamOut_Word_o, Clk_i, Reset_n_i, CfgMode_i, CfgClk_TRFSM0_i, CfgClk_TRFSM1_i, CfgShift_TRFSM0_i, CfgShift_TRFSM1_i, CfgDataIn_i, CfgDataOut_TRFSM0_o, CfgDataOut_TRFSM1_o);
input [1281:0] bitdata;
// user inputs and outputs
input AdcConvComplete_i;
output AdcDoConvert_o;
input [15:0] AdcValue_i;
input I2C_Busy_i;
output [7:0] I2C_DataIn_o;
input [7:0] I2C_DataOut_i;
input I2C_Error_i;
input I2C_FIFOEmpty_i;
input I2C_FIFOFull_i;
output I2C_FIFOReadNext_o;
output I2C_FIFOWrite_o;
output [7:0] I2C_ReadCount_o;
output I2C_ReceiveSend_n_o;
output I2C_StartProcess_o;
input Inputs_i_0;
input Inputs_i_1;
input Inputs_i_2;
input Inputs_i_3;
input Inputs_i_4;
input Inputs_i_5;
input Inputs_i_6;
input Inputs_i_7;
output Outputs_o_0;
output Outputs_o_1;
output Outputs_o_2;
output Outputs_o_3;
output Outputs_o_4;
output Outputs_o_5;
output Outputs_o_6;
output Outputs_o_7;
output ReconfModuleIRQs_o_0;
output ReconfModuleIRQs_o_1;
output ReconfModuleIRQs_o_2;
output ReconfModuleIRQs_o_3;
output ReconfModuleIRQs_o_4;
output SPI_CPHA_o;
output SPI_CPOL_o;
output [7:0] SPI_DataIn_o;
input [7:0] SPI_DataOut_i;
input SPI_FIFOEmpty_i;
input SPI_FIFOFull_i;
output SPI_LSBFE_o;
output SPI_ReadNext_o;
input SPI_Transmission_i;
output SPI_Write_o;
input ReconfModuleIn_i_0;
input ReconfModuleIn_i_1;
input ReconfModuleIn_i_2;
input ReconfModuleIn_i_3;
input ReconfModuleIn_i_4;
input ReconfModuleIn_i_5;
input ReconfModuleIn_i_6;
input ReconfModuleIn_i_7;
output ReconfModuleOut_o_0;
output ReconfModuleOut_o_1;
output ReconfModuleOut_o_2;
output ReconfModuleOut_o_3;
output ReconfModuleOut_o_4;
output ReconfModuleOut_o_5;
output ReconfModuleOut_o_6;
output ReconfModuleOut_o_7;
input [79:0] ParamIn_Word_i;
output [31:0] ParamOut_Word_o;
input Clk_i;
input Reset_n_i;
input CfgMode_i;
input CfgClk_TRFSM0_i;
input CfgClk_TRFSM1_i;
input CfgShift_TRFSM0_i;
input CfgShift_TRFSM1_i;
input CfgDataIn_i;
output CfgDataOut_TRFSM0_o;
output CfgDataOut_TRFSM1_o;
// CellInAdcConvComplete_i[0]
wire cell_0_0; // PORT
// CellOutAdcDoConvert_o[0]
wire cell_1_0; // PORT
// CellInAdcValue_i[0]
wire [15:0] cell_2_0; // PORT
// CellInI2C_Busy_i[0]
wire cell_3_0; // PORT
// CellOutI2C_DataIn_o[0]
wire [7:0] cell_4_0; // PORT
// CellInI2C_DataOut_i[0]
wire [7:0] cell_5_0; // PORT
// CellInI2C_Error_i[0]
wire cell_6_0; // PORT
// CellInI2C_FIFOEmpty_i[0]
wire cell_7_0; // PORT
// CellInI2C_FIFOFull_i[0]
wire cell_8_0; // PORT
// CellOutI2C_FIFOReadNext_o[0]
wire cell_9_0; // PORT
// CellOutI2C_FIFOWrite_o[0]
wire cell_10_0; // PORT
// CellOutI2C_ReadCount_o[0]
wire [7:0] cell_11_0; // PORT
// CellOutI2C_ReceiveSend_n_o[0]
wire cell_12_0; // PORT
// CellOutI2C_StartProcess_o[0]
wire cell_13_0; // PORT
// CellInInputs_i_0[0]
wire cell_14_0; // PORT
// CellInInputs_i_1[0]
wire cell_15_0; // PORT
// CellInInputs_i_2[0]
wire cell_16_0; // PORT
// CellInInputs_i_3[0]
wire cell_17_0; // PORT
// CellInInputs_i_4[0]
wire cell_18_0; // PORT
// CellInInputs_i_5[0]
wire cell_19_0; // PORT
// CellInInputs_i_6[0]
wire cell_20_0; // PORT
// CellInInputs_i_7[0]
wire cell_21_0; // PORT
// CellOutOutputs_o_0[0]
wire cell_22_0; // PORT
// CellOutOutputs_o_1[0]
wire cell_23_0; // PORT
// CellOutOutputs_o_2[0]
wire cell_24_0; // PORT
// CellOutOutputs_o_3[0]
wire cell_25_0; // PORT
// CellOutOutputs_o_4[0]
wire cell_26_0; // PORT
// CellOutOutputs_o_5[0]
wire cell_27_0; // PORT
// CellOutOutputs_o_6[0]
wire cell_28_0; // PORT
// CellOutOutputs_o_7[0]
wire cell_29_0; // PORT
// CellOutReconfModuleIRQs_o_0[0]
wire cell_30_0; // PORT
// CellOutReconfModuleIRQs_o_1[0]
wire cell_31_0; // PORT
// CellOutReconfModuleIRQs_o_2[0]
wire cell_32_0; // PORT
// CellOutReconfModuleIRQs_o_3[0]
wire cell_33_0; // PORT
// CellOutReconfModuleIRQs_o_4[0]
wire cell_34_0; // PORT
// CellOutSPI_CPHA_o[0]
wire cell_35_0; // PORT
// CellOutSPI_CPOL_o[0]
wire cell_36_0; // PORT
// CellOutSPI_DataIn_o[0]
wire [7:0] cell_37_0; // PORT
// CellInSPI_DataOut_i[0]
wire [7:0] cell_38_0; // PORT
// CellInSPI_FIFOEmpty_i[0]
wire cell_39_0; // PORT
// CellInSPI_FIFOFull_i[0]
wire cell_40_0; // PORT
// CellOutSPI_LSBFE_o[0]
wire cell_41_0; // PORT
// CellOutSPI_ReadNext_o[0]
wire cell_42_0; // PORT
// CellInSPI_Transmission_i[0]
wire cell_43_0; // PORT
// CellOutSPI_Write_o[0]
wire cell_44_0; // PORT
// CellInReconfModuleIn_i_0[0]
wire cell_45_0; // PORT
// CellInReconfModuleIn_i_1[0]
wire cell_46_0; // PORT
// CellInReconfModuleIn_i_2[0]
wire cell_47_0; // PORT
// CellInReconfModuleIn_i_3[0]
wire cell_48_0; // PORT
// CellInReconfModuleIn_i_4[0]
wire cell_49_0; // PORT
// CellInReconfModuleIn_i_5[0]
wire cell_50_0; // PORT
// CellInReconfModuleIn_i_6[0]
wire cell_51_0; // PORT
// CellInReconfModuleIn_i_7[0]
wire cell_52_0; // PORT
// CellOutReconfModuleOut_o_0[0]
wire cell_53_0; // PORT
// CellOutReconfModuleOut_o_1[0]
wire cell_54_0; // PORT
// CellOutReconfModuleOut_o_2[0]
wire cell_55_0; // PORT
// CellOutReconfModuleOut_o_3[0]
wire cell_56_0; // PORT
// CellOutReconfModuleOut_o_4[0]
wire cell_57_0; // PORT
// CellOutReconfModuleOut_o_5[0]
wire cell_58_0; // PORT
// CellOutReconfModuleOut_o_6[0]
wire cell_59_0; // PORT
// CellOutReconfModuleOut_o_7[0]
wire cell_60_0; // PORT
// Counter[0]
wire [15:0] cell_61_5; // D_o
wire cell_61_3; // Direction_i
wire cell_61_2; // Enable_i
wire cell_61_6; // Overflow_o
wire [15:0] cell_61_4; // PresetVal_i
wire cell_61_1; // Preset_i
wire cell_61_0; // ResetSig_i
wire cell_61_7; // Zero_o
Counter cell_61 (
.D_o(cell_61_5),
.Direction_i(cell_61_3),
.Enable_i(cell_61_2),
.Overflow_o(cell_61_6),
.PresetVal_i(cell_61_4),
.Preset_i(cell_61_1),
.ResetSig_i(cell_61_0),
.Zero_o(cell_61_7),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// Counter[1]
wire [15:0] cell_62_5; // D_o
wire cell_62_3; // Direction_i
wire cell_62_2; // Enable_i
wire cell_62_6; // Overflow_o
wire [15:0] cell_62_4; // PresetVal_i
wire cell_62_1; // Preset_i
wire cell_62_0; // ResetSig_i
wire cell_62_7; // Zero_o
Counter cell_62 (
.D_o(cell_62_5),
.Direction_i(cell_62_3),
.Enable_i(cell_62_2),
.Overflow_o(cell_62_6),
.PresetVal_i(cell_62_4),
.Preset_i(cell_62_1),
.ResetSig_i(cell_62_0),
.Zero_o(cell_62_7),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// Counter32[0]
wire [15:0] cell_63_6; // DH_o
wire [15:0] cell_63_7; // DL_o
wire cell_63_3; // Direction_i
wire cell_63_2; // Enable_i
wire cell_63_8; // Overflow_o
wire [15:0] cell_63_4; // PresetValH_i
wire [15:0] cell_63_5; // PresetValL_i
wire cell_63_1; // Preset_i
wire cell_63_0; // ResetSig_i
wire cell_63_9; // Zero_o
Counter32 cell_63 (
.DH_o(cell_63_6),
.DL_o(cell_63_7),
.Direction_i(cell_63_3),
.Enable_i(cell_63_2),
.Overflow_o(cell_63_8),
.PresetValH_i(cell_63_4),
.PresetValL_i(cell_63_5),
.Preset_i(cell_63_1),
.ResetSig_i(cell_63_0),
.Zero_o(cell_63_9),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// Counter32[1]
wire [15:0] cell_64_6; // DH_o
wire [15:0] cell_64_7; // DL_o
wire cell_64_3; // Direction_i
wire cell_64_2; // Enable_i
wire cell_64_8; // Overflow_o
wire [15:0] cell_64_4; // PresetValH_i
wire [15:0] cell_64_5; // PresetValL_i
wire cell_64_1; // Preset_i
wire cell_64_0; // ResetSig_i
wire cell_64_9; // Zero_o
Counter32 cell_64 (
.DH_o(cell_64_6),
.DL_o(cell_64_7),
.Direction_i(cell_64_3),
.Enable_i(cell_64_2),
.Overflow_o(cell_64_8),
.PresetValH_i(cell_64_4),
.PresetValL_i(cell_64_5),
.Preset_i(cell_64_1),
.ResetSig_i(cell_64_0),
.Zero_o(cell_64_9),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// AbsDiff[0]
wire [15:0] cell_65_0; // A_i
wire [15:0] cell_65_1; // B_i
wire [15:0] cell_65_2; // D_o
AbsDiff cell_65 (
.A_i(cell_65_0),
.B_i(cell_65_1),
.D_o(cell_65_2)
);
// WordRegister[0]
wire [15:0] cell_66_0; // D_i
wire cell_66_2; // Enable_i
wire [15:0] cell_66_1; // Q_o
WordRegister cell_66 (
.D_i(cell_66_0),
.Enable_i(cell_66_2),
.Q_o(cell_66_1),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// WordRegister[1]
wire [15:0] cell_67_0; // D_i
wire cell_67_2; // Enable_i
wire [15:0] cell_67_1; // Q_o
WordRegister cell_67 (
.D_i(cell_67_0),
.Enable_i(cell_67_2),
.Q_o(cell_67_1),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// WordRegister[2]
wire [15:0] cell_68_0; // D_i
wire cell_68_2; // Enable_i
wire [15:0] cell_68_1; // Q_o
WordRegister cell_68 (
.D_i(cell_68_0),
.Enable_i(cell_68_2),
.Q_o(cell_68_1),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// ByteRegister[0]
wire [7:0] cell_69_0; // D_i
wire cell_69_2; // Enable_i
wire [7:0] cell_69_1; // Q_o
ByteRegister cell_69 (
.D_i(cell_69_0),
.Enable_i(cell_69_2),
.Q_o(cell_69_1),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// ByteRegister[1]
wire [7:0] cell_70_0; // D_i
wire cell_70_2; // Enable_i
wire [7:0] cell_70_1; // Q_o
ByteRegister cell_70 (
.D_i(cell_70_0),
.Enable_i(cell_70_2),
.Q_o(cell_70_1),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i)
);
// AddSubCmp[0]
wire [15:0] cell_71_1; // A_i
wire cell_71_0; // AddOrSub_i
wire [15:0] cell_71_2; // B_i
wire cell_71_4; // Carry_i
wire cell_71_5; // Carry_o
wire [15:0] cell_71_3; // D_o
wire cell_71_8; // Overflow_o
wire cell_71_7; // Sign_o
wire cell_71_6; // Zero_o
AddSubCmp cell_71 (
.A_i(cell_71_1),
.AddOrSub_i(cell_71_0),
.B_i(cell_71_2),
.Carry_i(cell_71_4),
.Carry_o(cell_71_5),
.D_o(cell_71_3),
.Overflow_o(cell_71_8),
.Sign_o(cell_71_7),
.Zero_o(cell_71_6)
);
// AddSubCmp[1]
wire [15:0] cell_72_1; // A_i
wire cell_72_0; // AddOrSub_i
wire [15:0] cell_72_2; // B_i
wire cell_72_4; // Carry_i
wire cell_72_5; // Carry_o
wire [15:0] cell_72_3; // D_o
wire cell_72_8; // Overflow_o
wire cell_72_7; // Sign_o
wire cell_72_6; // Zero_o
AddSubCmp cell_72 (
.A_i(cell_72_1),
.AddOrSub_i(cell_72_0),
.B_i(cell_72_2),
.Carry_i(cell_72_4),
.Carry_o(cell_72_5),
.D_o(cell_72_3),
.Overflow_o(cell_72_8),
.Sign_o(cell_72_7),
.Zero_o(cell_72_6)
);
// ByteMuxQuad[0]
wire [7:0] cell_73_0; // A_i
wire [7:0] cell_73_1; // B_i
wire [7:0] cell_73_2; // C_i
wire [7:0] cell_73_3; // D_i
wire cell_73_4; // SAB_i
wire cell_73_5; // SC_i
wire cell_73_6; // SD_i
wire [7:0] cell_73_7; // Y_o
ByteMuxQuad cell_73 (
.A_i(cell_73_0),
.B_i(cell_73_1),
.C_i(cell_73_2),
.D_i(cell_73_3),
.SAB_i(cell_73_4),
.SC_i(cell_73_5),
.SD_i(cell_73_6),
.Y_o(cell_73_7)
);
// ByteMuxDual[0]
wire [7:0] cell_74_0; // A_i
wire [7:0] cell_74_1; // B_i
wire cell_74_2; // S_i
wire [7:0] cell_74_3; // Y_o
ByteMuxDual cell_74 (
.A_i(cell_74_0),
.B_i(cell_74_1),
.S_i(cell_74_2),
.Y_o(cell_74_3)
);
// ByteMuxDual[1]
wire [7:0] cell_75_0; // A_i
wire [7:0] cell_75_1; // B_i
wire cell_75_2; // S_i
wire [7:0] cell_75_3; // Y_o
ByteMuxDual cell_75 (
.A_i(cell_75_0),
.B_i(cell_75_1),
.S_i(cell_75_2),
.Y_o(cell_75_3)
);
// Byte2Word[0]
wire [7:0] cell_76_0; // H_i
wire [7:0] cell_76_1; // L_i
wire [15:0] cell_76_2; // Y_o
Byte2Word cell_76 (
.H_i(cell_76_0),
.L_i(cell_76_1),
.Y_o(cell_76_2)
);
// Byte2WordSel[0]
wire [7:0] cell_77_0; // H_i
wire [7:0] cell_77_1; // L_i
wire [15:0] cell_77_2; // Y_o
Byte2WordSel cell_77 (
.H_i(cell_77_0),
.L_i(cell_77_1),
.Y_o(cell_77_2),
.Mask_i(bitdata[1215:1212]),
.Shift_i(bitdata[1211:1208])
);
// WordMuxDual[0]
wire [15:0] cell_78_0; // A_i
wire [15:0] cell_78_1; // B_i
wire cell_78_2; // S_i
wire [15:0] cell_78_3; // Y_o
WordMuxDual cell_78 (
.A_i(cell_78_0),
.B_i(cell_78_1),
.S_i(cell_78_2),
.Y_o(cell_78_3)
);
// WordMuxDual[1]
wire [15:0] cell_79_0; // A_i
wire [15:0] cell_79_1; // B_i
wire cell_79_2; // S_i
wire [15:0] cell_79_3; // Y_o
WordMuxDual cell_79 (
.A_i(cell_79_0),
.B_i(cell_79_1),
.S_i(cell_79_2),
.Y_o(cell_79_3)
);
// TRFSM0[0]
wire cell_80_0; // In0_i
wire cell_80_1; // In1_i
wire cell_80_2; // In2_i
wire cell_80_3; // In3_i
wire cell_80_4; // In4_i
wire cell_80_5; // In5_i
wire cell_80_6; // Out0_o
wire cell_80_7; // Out1_o
wire cell_80_8; // Out2_o
wire cell_80_9; // Out3_o
wire cell_80_10; // Out4_o
wire cell_80_11; // Out5_o
wire cell_80_12; // Out6_o
wire cell_80_13; // Out7_o
wire cell_80_14; // Out8_o
wire cell_80_15; // Out9_o
TRFSM0 cell_80 (
.In0_i(cell_80_0),
.In1_i(cell_80_1),
.In2_i(cell_80_2),
.In3_i(cell_80_3),
.In4_i(cell_80_4),
.In5_i(cell_80_5),
.Out0_o(cell_80_6),
.Out1_o(cell_80_7),
.Out2_o(cell_80_8),
.Out3_o(cell_80_9),
.Out4_o(cell_80_10),
.Out5_o(cell_80_11),
.Out6_o(cell_80_12),
.Out7_o(cell_80_13),
.Out8_o(cell_80_14),
.Out9_o(cell_80_15),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_TRFSM0_i),
.CfgShift_i(CfgShift_TRFSM0_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_TRFSM0_o)
);
// TRFSM1[0]
wire cell_81_0; // In0_i
wire cell_81_1; // In1_i
wire cell_81_2; // In2_i
wire cell_81_3; // In3_i
wire cell_81_4; // In4_i
wire cell_81_5; // In5_i
wire cell_81_6; // In6_i
wire cell_81_7; // In7_i
wire cell_81_8; // In8_i
wire cell_81_9; // In9_i
wire cell_81_10; // Out0_o
wire cell_81_20; // Out10_o
wire cell_81_21; // Out11_o
wire cell_81_22; // Out12_o
wire cell_81_23; // Out13_o
wire cell_81_24; // Out14_o
wire cell_81_11; // Out1_o
wire cell_81_12; // Out2_o
wire cell_81_13; // Out3_o
wire cell_81_14; // Out4_o
wire cell_81_15; // Out5_o
wire cell_81_16; // Out6_o
wire cell_81_17; // Out7_o
wire cell_81_18; // Out8_o
wire cell_81_19; // Out9_o
TRFSM1 cell_81 (
.In0_i(cell_81_0),
.In1_i(cell_81_1),
.In2_i(cell_81_2),
.In3_i(cell_81_3),
.In4_i(cell_81_4),
.In5_i(cell_81_5),
.In6_i(cell_81_6),
.In7_i(cell_81_7),
.In8_i(cell_81_8),
.In9_i(cell_81_9),
.Out0_o(cell_81_10),
.Out10_o(cell_81_20),
.Out11_o(cell_81_21),
.Out12_o(cell_81_22),
.Out13_o(cell_81_23),
.Out14_o(cell_81_24),
.Out1_o(cell_81_11),
.Out2_o(cell_81_12),
.Out3_o(cell_81_13),
.Out4_o(cell_81_14),
.Out5_o(cell_81_15),
.Out6_o(cell_81_16),
.Out7_o(cell_81_17),
.Out8_o(cell_81_18),
.Out9_o(cell_81_19),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_TRFSM1_i),
.CfgShift_i(CfgShift_TRFSM1_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_TRFSM1_o)
);
// CONST_Bit[0]
wire cell_82_0; // Value_o
CONST_Bit cell_82 (
.Value_o(cell_82_0),
.CfgValue_i(bitdata[1216:1216])
);
// CONST_Bit[1]
wire cell_83_0; // Value_o
CONST_Bit cell_83 (
.Value_o(cell_83_0),
.CfgValue_i(bitdata[1217:1217])
);
// CONST_Byte[0]
wire [7:0] cell_84_0; // Value_o
CONST_Byte cell_84 (
.Value_o(cell_84_0),
.CfgValue_i(bitdata[1225:1218])
);
// CONST_Byte[1]
wire [7:0] cell_85_0; // Value_o
CONST_Byte cell_85 (
.Value_o(cell_85_0),
.CfgValue_i(bitdata[1233:1226])
);
// CONST_Byte[2]
wire [7:0] cell_86_0; // Value_o
CONST_Byte cell_86 (
.Value_o(cell_86_0),
.CfgValue_i(bitdata[1241:1234])
);
// CONST_Byte[3]
wire [7:0] cell_87_0; // Value_o
CONST_Byte cell_87 (
.Value_o(cell_87_0),
.CfgValue_i(bitdata[1249:1242])
);
// CONST_Byte[4]
wire [7:0] cell_88_0; // Value_o
CONST_Byte cell_88 (
.Value_o(cell_88_0),
.CfgValue_i(bitdata[1257:1250])
);
// CONST_Byte[5]
wire [7:0] cell_89_0; // Value_o
CONST_Byte cell_89 (
.Value_o(cell_89_0),
.CfgValue_i(bitdata[1265:1258])
);
// CONST_Word[0]
wire [15:0] cell_90_0; // Value_o
CONST_Word cell_90 (
.Value_o(cell_90_0),
.CfgValue_i(bitdata[1281:1266])
);
// CellParamIn_Word[0]
wire [15:0] cell_91_0; // PORT
// CellParamIn_Word[1]
wire [15:0] cell_92_0; // PORT
// CellParamIn_Word[2]
wire [15:0] cell_93_0; // PORT
// CellParamIn_Word[3]
wire [15:0] cell_94_0; // PORT
// CellParamIn_Word[4]
wire [15:0] cell_95_0; // PORT
// CellParamOut_Word[0]
wire [15:0] cell_96_0; // PORT
// CellParamOut_Word[1]
wire [15:0] cell_97_0; // PORT
// input and output mappings to interconnect signals
assign cell_0_0 = AdcConvComplete_i;
assign AdcDoConvert_o = cell_1_0;
assign cell_2_0 = AdcValue_i;
assign cell_3_0 = I2C_Busy_i;
assign I2C_DataIn_o = cell_4_0;
assign cell_5_0 = I2C_DataOut_i;
assign cell_6_0 = I2C_Error_i;
assign cell_7_0 = I2C_FIFOEmpty_i;
assign cell_8_0 = I2C_FIFOFull_i;
assign I2C_FIFOReadNext_o = cell_9_0;
assign I2C_FIFOWrite_o = cell_10_0;
assign I2C_ReadCount_o = cell_11_0;
assign I2C_ReceiveSend_n_o = cell_12_0;
assign I2C_StartProcess_o = cell_13_0;
assign cell_14_0 = Inputs_i_0;
assign cell_15_0 = Inputs_i_1;
assign cell_16_0 = Inputs_i_2;
assign cell_17_0 = Inputs_i_3;
assign cell_18_0 = Inputs_i_4;
assign cell_19_0 = Inputs_i_5;
assign cell_20_0 = Inputs_i_6;
assign cell_21_0 = Inputs_i_7;
assign Outputs_o_0 = cell_22_0;
assign Outputs_o_1 = cell_23_0;
assign Outputs_o_2 = cell_24_0;
assign Outputs_o_3 = cell_25_0;
assign Outputs_o_4 = cell_26_0;
assign Outputs_o_5 = cell_27_0;
assign Outputs_o_6 = cell_28_0;
assign Outputs_o_7 = cell_29_0;
assign ReconfModuleIRQs_o_0 = cell_30_0;
assign ReconfModuleIRQs_o_1 = cell_31_0;
assign ReconfModuleIRQs_o_2 = cell_32_0;
assign ReconfModuleIRQs_o_3 = cell_33_0;
assign ReconfModuleIRQs_o_4 = cell_34_0;
assign SPI_CPHA_o = cell_35_0;
assign SPI_CPOL_o = cell_36_0;
assign SPI_DataIn_o = cell_37_0;
assign cell_38_0 = SPI_DataOut_i;
assign cell_39_0 = SPI_FIFOEmpty_i;
assign cell_40_0 = SPI_FIFOFull_i;
assign SPI_LSBFE_o = cell_41_0;
assign SPI_ReadNext_o = cell_42_0;
assign cell_43_0 = SPI_Transmission_i;
assign SPI_Write_o = cell_44_0;
assign cell_45_0 = ReconfModuleIn_i_0;
assign cell_46_0 = ReconfModuleIn_i_1;
assign cell_47_0 = ReconfModuleIn_i_2;
assign cell_48_0 = ReconfModuleIn_i_3;
assign cell_49_0 = ReconfModuleIn_i_4;
assign cell_50_0 = ReconfModuleIn_i_5;
assign cell_51_0 = ReconfModuleIn_i_6;
assign cell_52_0 = ReconfModuleIn_i_7;
assign ReconfModuleOut_o_0 = cell_53_0;
assign ReconfModuleOut_o_1 = cell_54_0;
assign ReconfModuleOut_o_2 = cell_55_0;
assign ReconfModuleOut_o_3 = cell_56_0;
assign ReconfModuleOut_o_4 = cell_57_0;
assign ReconfModuleOut_o_5 = cell_58_0;
assign ReconfModuleOut_o_6 = cell_59_0;
assign ReconfModuleOut_o_7 = cell_60_0;
assign cell_91_0 = ParamIn_Word_i[15:0];
assign cell_92_0 = ParamIn_Word_i[31:16];
assign cell_93_0 = ParamIn_Word_i[47:32];
assign cell_94_0 = ParamIn_Word_i[63:48];
assign cell_95_0 = ParamIn_Word_i[79:64];
assign ParamOut_Word_o[15:0] = cell_96_0;
assign ParamOut_Word_o[31:16] = cell_97_0;
// conntype=0, tree=0, switch=1
wire sw_0_0_1_up0;
wire sw_0_0_1_down0;
// conntype=0, tree=0, switch=2
wire sw_0_0_2_up0;
wire sw_0_0_2_down0;
// conntype=0, tree=0, switch=3
wire sw_0_0_3_up0;
wire sw_0_0_3_down0;
// conntype=0, tree=0, switch=4
wire sw_0_0_4_up0;
wire sw_0_0_4_down0;
// conntype=0, tree=0, switch=5
wire sw_0_0_5_up0;
wire sw_0_0_5_down0;
// conntype=0, tree=0, switch=6
wire sw_0_0_6_up0;
wire sw_0_0_6_down0;
// conntype=0, tree=0, switch=7
wire sw_0_0_7_up0;
wire sw_0_0_7_down0;
// conntype=0, tree=0, switch=8
wire sw_0_0_8_up0;
wire sw_0_0_8_up1;
wire sw_0_0_8_up2;
wire sw_0_0_8_down0;
wire sw_0_0_8_down1;
wire sw_0_0_8_down2;
wire sw_0_0_8_down3;
wire sw_0_0_8_down4;
// conntype=0, tree=0, switch=9
wire sw_0_0_9_up0;
wire sw_0_0_9_up1;
wire sw_0_0_9_up2;
wire sw_0_0_9_up3;
// conntype=0, tree=0, switch=10
wire sw_0_0_10_up0;
wire sw_0_0_10_down0;
wire sw_0_0_10_down1;
wire sw_0_0_10_down2;
// conntype=0, tree=0, switch=11
wire sw_0_0_11_up0;
wire sw_0_0_11_down0;
wire sw_0_0_11_down1;
// conntype=0, tree=0, switch=12
wire sw_0_0_12_up0;
wire sw_0_0_12_down0;
// conntype=0, tree=0, switch=13
wire sw_0_0_13_down0;
// conntype=0, tree=0, switch=14
wire sw_0_0_14_down0;
// conntype=0, tree=0, switch=15
wire sw_0_0_15_up0;
// conntype=0, tree=0, switch=16
wire sw_0_0_16_up0;
wire sw_0_0_16_down0;
// conntype=0, tree=0, switch=17
wire sw_0_0_17_down0;
// conntype=0, tree=0, switch=18
wire sw_0_0_18_up0;
wire sw_0_0_18_down0;
// conntype=0, tree=0, switch=19
wire sw_0_0_19_down0;
// conntype=0, tree=0, switch=20
wire sw_0_0_20_up0;
wire sw_0_0_20_down0;
// conntype=0, tree=0, switch=21
wire sw_0_0_21_down0;
// conntype=0, tree=0, switch=22
wire sw_0_0_22_up0;
wire sw_0_0_22_down0;
// conntype=0, tree=0, switch=23
wire sw_0_0_23_up0;
// conntype=0, tree=0, switch=24
wire sw_0_0_24_up0;
wire sw_0_0_24_down0;
wire sw_0_0_24_down1;
wire sw_0_0_24_down2;
// conntype=0, tree=0, switch=25
wire sw_0_0_25_up0;
wire sw_0_0_25_up1;
wire sw_0_0_25_up2;
wire sw_0_0_25_up3;
wire sw_0_0_25_down0;
wire sw_0_0_25_down1;
wire sw_0_0_25_down2;
// conntype=0, tree=0, switch=26
wire sw_0_0_26_up0;
wire sw_0_0_26_down0;
wire sw_0_0_26_down1;
// conntype=0, tree=1, switch=1
wire sw_0_1_1_up0;
wire sw_0_1_1_down0;
// conntype=0, tree=1, switch=2
wire sw_0_1_2_up0;
wire sw_0_1_2_down0;
// conntype=0, tree=1, switch=3
wire sw_0_1_3_up0;
wire sw_0_1_3_up1;
wire sw_0_1_3_up2;
wire sw_0_1_3_up3;
wire sw_0_1_3_up4;
wire sw_0_1_3_up5;
wire sw_0_1_3_down0;
wire sw_0_1_3_down1;
// conntype=0, tree=1, switch=4
wire sw_0_1_4_up0;
wire sw_0_1_4_down0;
wire sw_0_1_4_down1;
// conntype=0, tree=1, switch=5
wire sw_0_1_5_up0;
wire sw_0_1_5_up1;
wire sw_0_1_5_down0;
wire sw_0_1_5_down1;
wire sw_0_1_5_down2;
wire sw_0_1_5_down3;
wire sw_0_1_5_down4;
// conntype=0, tree=1, switch=6
wire sw_0_1_6_up0;
wire sw_0_1_6_down0;
// conntype=0, tree=1, switch=7
wire sw_0_1_7_up0;
wire sw_0_1_7_down0;
// conntype=0, tree=1, switch=8
wire sw_0_1_8_up0;
wire sw_0_1_8_up1;
wire sw_0_1_8_up2;
wire sw_0_1_8_up3;
wire sw_0_1_8_up4;
wire sw_0_1_8_up5;
wire sw_0_1_8_up6;
wire sw_0_1_8_up7;
wire sw_0_1_8_up8;
wire sw_0_1_8_up9;
wire sw_0_1_8_down0;
wire sw_0_1_8_down1;
wire sw_0_1_8_down2;
wire sw_0_1_8_down3;
wire sw_0_1_8_down4;
wire sw_0_1_8_down5;
// conntype=0, tree=1, switch=9
wire sw_0_1_9_up0;
wire sw_0_1_9_down0;
wire sw_0_1_9_down1;
wire sw_0_1_9_down2;
// conntype=0, tree=1, switch=10
wire sw_0_1_10_up0;
wire sw_0_1_10_up1;
wire sw_0_1_10_up2;
wire sw_0_1_10_down0;
wire sw_0_1_10_down1;
wire sw_0_1_10_down2;
wire sw_0_1_10_down3;
wire sw_0_1_10_down4;
// conntype=0, tree=1, switch=11
wire sw_0_1_11_up0;
wire sw_0_1_11_up1;
wire sw_0_1_11_up2;
wire sw_0_1_11_up3;
wire sw_0_1_11_down0;
wire sw_0_1_11_down1;
wire sw_0_1_11_down2;
wire sw_0_1_11_down3;
// conntype=0, tree=1, switch=12
wire sw_0_1_12_down0;
wire sw_0_1_12_down1;
// conntype=0, tree=1, switch=13
wire sw_0_1_13_down0;
// conntype=0, tree=1, switch=14
wire sw_0_1_14_down0;
// conntype=0, tree=1, switch=15
wire sw_0_1_15_up0;
// conntype=0, tree=1, switch=16
wire sw_0_1_16_up0;
wire sw_0_1_16_up1;
// conntype=0, tree=1, switch=17
wire sw_0_1_17_up0;
wire sw_0_1_17_down0;
wire sw_0_1_17_down1;
wire sw_0_1_17_down2;
// conntype=0, tree=1, switch=18
wire sw_0_1_18_up0;
wire sw_0_1_18_down0;
wire sw_0_1_18_down1;
wire sw_0_1_18_down2;
// conntype=0, tree=1, switch=19
wire sw_0_1_19_up0;
wire sw_0_1_19_down0;
wire sw_0_1_19_down1;
// conntype=0, tree=1, switch=20
wire sw_0_1_20_down0;
// conntype=0, tree=1, switch=21
wire sw_0_1_21_down0;
// conntype=0, tree=1, switch=22
wire sw_0_1_22_up0;
wire sw_0_1_22_down0;
// conntype=0, tree=1, switch=23
wire sw_0_1_23_up0;
// conntype=0, tree=1, switch=24
wire sw_0_1_24_up0;
wire sw_0_1_24_down0;
// conntype=0, tree=1, switch=25
wire sw_0_1_25_up0;
wire sw_0_1_25_down0;
// conntype=0, tree=1, switch=26
wire sw_0_1_26_up0;
wire sw_0_1_26_down0;
// conntype=1, tree=0, switch=1
wire [7:0] sw_1_0_1_up0;
wire [7:0] sw_1_0_1_down0;
// conntype=1, tree=0, switch=2
wire [7:0] sw_1_0_2_up0;
wire [7:0] sw_1_0_2_down0;
// conntype=1, tree=0, switch=3
wire [7:0] sw_1_0_3_up0;
wire [7:0] sw_1_0_3_down0;
wire [7:0] sw_1_0_3_down1;
// conntype=1, tree=0, switch=4
wire [7:0] sw_1_0_4_up0;
wire [7:0] sw_1_0_4_up1;
wire [7:0] sw_1_0_4_down0;
// conntype=1, tree=0, switch=5
wire [7:0] sw_1_0_5_up0;
wire [7:0] sw_1_0_5_down0;
// conntype=1, tree=0, switch=6
wire [7:0] sw_1_0_6_up0;
wire [7:0] sw_1_0_6_down0;
// conntype=1, tree=0, switch=7
wire [7:0] sw_1_0_7_up0;
// conntype=1, tree=1, switch=1
wire [7:0] sw_1_1_1_up0;
wire [7:0] sw_1_1_1_down0;
// conntype=1, tree=1, switch=2
wire [7:0] sw_1_1_2_up0;
wire [7:0] sw_1_1_2_down0;
// conntype=1, tree=1, switch=3
wire [7:0] sw_1_1_3_up0;
wire [7:0] sw_1_1_3_down0;
// conntype=1, tree=1, switch=4
wire [7:0] sw_1_1_4_up0;
wire [7:0] sw_1_1_4_up1;
wire [7:0] sw_1_1_4_down0;
// conntype=1, tree=1, switch=5
wire [7:0] sw_1_1_5_up0;
wire [7:0] sw_1_1_5_down0;
wire [7:0] sw_1_1_5_down1;
// conntype=1, tree=1, switch=6
wire [7:0] sw_1_1_6_up0;
wire [7:0] sw_1_1_6_down0;
// conntype=1, tree=1, switch=7
wire [7:0] sw_1_1_7_down0;
// conntype=2, tree=0, switch=1
wire [15:0] sw_2_0_1_up0;
wire [15:0] sw_2_0_1_down0;
// conntype=2, tree=0, switch=2
wire [15:0] sw_2_0_2_up0;
wire [15:0] sw_2_0_2_down0;
// conntype=2, tree=0, switch=3
wire [15:0] sw_2_0_3_up0;
wire [15:0] sw_2_0_3_down0;
// conntype=2, tree=0, switch=4
wire [15:0] sw_2_0_4_up0;
wire [15:0] sw_2_0_4_down0;
// conntype=2, tree=0, switch=5
wire [15:0] sw_2_0_5_up0;
wire [15:0] sw_2_0_5_down0;
// conntype=2, tree=0, switch=6
wire [15:0] sw_2_0_6_up0;
wire [15:0] sw_2_0_6_down0;
// conntype=2, tree=0, switch=7
wire [15:0] sw_2_0_7_up0;
wire [15:0] sw_2_0_7_down0;
// conntype=2, tree=0, switch=8
wire [15:0] sw_2_0_8_up0;
wire [15:0] sw_2_0_8_down0;
// conntype=2, tree=1, switch=1
wire [15:0] sw_2_1_1_up0;
wire [15:0] sw_2_1_1_down0;
// conntype=2, tree=1, switch=2
wire [15:0] sw_2_1_2_up0;
wire [15:0] sw_2_1_2_down0;
// conntype=2, tree=1, switch=3
wire [15:0] sw_2_1_3_up0;
wire [15:0] sw_2_1_3_down0;
// conntype=2, tree=1, switch=4
wire [15:0] sw_2_1_4_up0;
wire [15:0] sw_2_1_4_down0;
// conntype=2, tree=1, switch=5
wire [15:0] sw_2_1_5_up0;
wire [15:0] sw_2_1_5_down0;
// conntype=2, tree=1, switch=6
wire [15:0] sw_2_1_6_up0;
wire [15:0] sw_2_1_6_up1;
wire [15:0] sw_2_1_6_down0;
// conntype=2, tree=1, switch=7
wire [15:0] sw_2_1_7_up0;
wire [15:0] sw_2_1_7_down0;
wire [15:0] sw_2_1_7_down1;
// conntype=2, tree=1, switch=8
wire [15:0] sw_2_1_8_up0;
wire [15:0] sw_2_1_8_down0;
// multiplexer
assign cell_10_0 =
(bitdata[271:269] == 3'b010 ? sw_0_0_24_down0 :
bitdata[271:269] == 3'b110 ? sw_0_0_24_down1 :
bitdata[271:269] == 3'b001 ? sw_0_0_24_down2 :
bitdata[271:269] == 3'b100 ? cell_3_0 :
bitdata[271:269] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[898:897] == 2'b01 ? sw_0_1_24_down0 :
bitdata[898:897] == 2'b10 ? cell_14_0 :
bitdata[898:897] == 2'b0 ? 1'b0 : 1'bx);
assign cell_11_0 =
(bitdata[946:944] == 3'b001 ? sw_1_0_4_down0 :
bitdata[946:944] == 3'b100 ? cell_74_3 :
bitdata[946:944] == 3'b010 ? cell_84_0 :
bitdata[946:944] == 3'b110 ? cell_85_0 :
bitdata[946:944] == 3'b0 ? 8'b0 : 8'bx) |
(bitdata[1031:1031] == 1'b1 ? sw_1_1_7_down0 :
bitdata[1031:1031] == 1'b0 ? 8'b0 : 8'bx);
assign cell_12_0 =
(bitdata[369:368] == 2'b01 ? sw_0_0_26_down0 :
bitdata[369:368] == 2'b11 ? sw_0_0_26_down1 :
bitdata[369:368] == 2'b10 ? cell_6_0 :
bitdata[369:368] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[900:899] == 2'b01 ? sw_0_1_24_down0 :
bitdata[900:899] == 2'b10 ? cell_14_0 :
bitdata[900:899] == 2'b0 ? 1'b0 : 1'bx);
assign cell_13_0 =
(bitdata[274:272] == 3'b010 ? sw_0_0_24_down0 :
bitdata[274:272] == 3'b110 ? sw_0_0_24_down1 :
bitdata[274:272] == 3'b001 ? sw_0_0_24_down2 :
bitdata[274:272] == 3'b100 ? cell_3_0 :
bitdata[274:272] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[902:901] == 2'b01 ? sw_0_1_24_down0 :
bitdata[902:901] == 2'b10 ? cell_14_0 :
bitdata[902:901] == 2'b0 ? 1'b0 : 1'bx);
assign cell_1_0 =
(bitdata[180:177] == 4'b0110 ? sw_0_0_10_down0 :
bitdata[180:177] == 4'b1110 ? sw_0_0_10_down1 :
bitdata[180:177] == 4'b0001 ? sw_0_0_10_down2 :
bitdata[180:177] == 4'b1000 ? cell_62_6 :
bitdata[180:177] == 4'b0100 ? cell_62_7 :
bitdata[180:177] == 4'b1100 ? cell_64_8 :
bitdata[180:177] == 4'b0010 ? cell_64_9 :
bitdata[180:177] == 4'b1010 ? cell_83_0 :
bitdata[180:177] == 4'b0 ? 1'b0 : 1'bx) |
(bitdata[910:909] == 2'b11 ? sw_0_1_26_down0 :
bitdata[910:909] == 2'b10 ? cell_0_0 :
bitdata[910:909] == 2'b01 ? cell_3_0 :
bitdata[910:909] == 2'b0 ? 1'b0 : 1'bx);
assign cell_22_0 =
(bitdata[206:205] == 2'b01 ? sw_0_0_11_down0 :
bitdata[206:205] == 2'b11 ? sw_0_0_11_down1 :
bitdata[206:205] == 2'b10 ? cell_43_0 :
bitdata[206:205] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[718:716] == 3'b010 ? sw_0_1_9_down0 :
bitdata[718:716] == 3'b110 ? sw_0_1_9_down1 :
bitdata[718:716] == 3'b001 ? sw_0_1_9_down2 :
bitdata[718:716] == 3'b100 ? cell_43_0 :
bitdata[718:716] == 3'b0 ? 1'b0 : 1'bx);
assign cell_23_0 =
(bitdata[208:207] == 2'b01 ? sw_0_0_11_down0 :
bitdata[208:207] == 2'b11 ? sw_0_0_11_down1 :
bitdata[208:207] == 2'b10 ? cell_43_0 :
bitdata[208:207] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[886:886] == 1'b1 ? sw_0_1_21_down0 :
bitdata[886:886] == 1'b0 ? 1'b0 : 1'bx);
assign cell_24_0 =
(bitdata[258:258] == 1'b1 ? sw_0_0_21_down0 :
bitdata[258:258] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[887:887] == 1'b1 ? sw_0_1_21_down0 :
bitdata[887:887] == 1'b0 ? 1'b0 : 1'bx);
assign cell_25_0 =
(bitdata[259:259] == 1'b1 ? sw_0_0_21_down0 :
bitdata[259:259] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[888:888] == 1'b1 ? sw_0_1_21_down0 :
bitdata[888:888] == 1'b0 ? 1'b0 : 1'bx);
assign cell_26_0 =
(bitdata[260:260] == 1'b1 ? sw_0_0_21_down0 :
bitdata[260:260] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[889:889] == 1'b1 ? sw_0_1_21_down0 :
bitdata[889:889] == 1'b0 ? 1'b0 : 1'bx);
assign cell_27_0 =
(bitdata[253:252] == 2'b01 ? sw_0_0_20_down0 :
bitdata[253:252] == 2'b10 ? cell_7_0 :
bitdata[253:252] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[882:882] == 1'b1 ? sw_0_1_20_down0 :
bitdata[882:882] == 1'b0 ? 1'b0 : 1'bx);
assign cell_28_0 =
(bitdata[255:254] == 2'b01 ? sw_0_0_20_down0 :
bitdata[255:254] == 2'b10 ? cell_7_0 :
bitdata[255:254] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[883:883] == 1'b1 ? sw_0_1_20_down0 :
bitdata[883:883] == 1'b0 ? 1'b0 : 1'bx);
assign cell_29_0 =
(bitdata[257:256] == 2'b01 ? sw_0_0_20_down0 :
bitdata[257:256] == 2'b10 ? cell_7_0 :
bitdata[257:256] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[884:884] == 1'b1 ? sw_0_1_20_down0 :
bitdata[884:884] == 1'b0 ? 1'b0 : 1'bx);
assign cell_30_0 =
(bitdata[111:107] == 5'b10001 ? sw_0_0_8_down0 :
bitdata[111:107] == 5'b01001 ? sw_0_0_8_down1 :
bitdata[111:107] == 5'b11001 ? sw_0_0_8_down2 :
bitdata[111:107] == 5'b00101 ? sw_0_0_8_down3 :
bitdata[111:107] == 5'b10101 ? sw_0_0_8_down4 :
bitdata[111:107] == 5'b10000 ? cell_61_6 :
bitdata[111:107] == 5'b01000 ? cell_61_7 :
bitdata[111:107] == 5'b11000 ? cell_71_5 :
bitdata[111:107] == 5'b00100 ? cell_71_6 :
bitdata[111:107] == 5'b10100 ? cell_71_7 :
bitdata[111:107] == 5'b01100 ? cell_71_8 :
bitdata[111:107] == 5'b11100 ? cell_80_6 :
bitdata[111:107] == 5'b00010 ? cell_80_7 :
bitdata[111:107] == 5'b10010 ? cell_80_8 :
bitdata[111:107] == 5'b01010 ? cell_80_9 :
bitdata[111:107] == 5'b11010 ? cell_80_10 :
bitdata[111:107] == 5'b00110 ? cell_80_11 :
bitdata[111:107] == 5'b10110 ? cell_80_12 :
bitdata[111:107] == 5'b01110 ? cell_80_13 :
bitdata[111:107] == 5'b11110 ? cell_80_14 :
bitdata[111:107] == 5'b00001 ? cell_80_15 :
bitdata[111:107] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[877:876] == 2'b01 ? sw_0_1_19_down0 :
bitdata[877:876] == 2'b11 ? sw_0_1_19_down1 :
bitdata[877:876] == 2'b10 ? cell_40_0 :
bitdata[877:876] == 2'b0 ? 1'b0 : 1'bx);
assign cell_31_0 =
(bitdata[248:248] == 1'b1 ? sw_0_0_19_down0 :
bitdata[248:248] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[894:892] == 3'b001 ? sw_0_1_22_down0 :
bitdata[894:892] == 3'b100 ? cell_19_0 :
bitdata[894:892] == 3'b010 ? cell_20_0 :
bitdata[894:892] == 3'b110 ? cell_21_0 :
bitdata[894:892] == 3'b0 ? 1'b0 : 1'bx);
assign cell_32_0 =
(bitdata[249:249] == 1'b1 ? sw_0_0_19_down0 :
bitdata[249:249] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[885:885] == 1'b1 ? sw_0_1_20_down0 :
bitdata[885:885] == 1'b0 ? 1'b0 : 1'bx);
assign cell_33_0 =
(bitdata[250:250] == 1'b1 ? sw_0_0_19_down0 :
bitdata[250:250] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[879:878] == 2'b01 ? sw_0_1_19_down0 :
bitdata[879:878] == 2'b11 ? sw_0_1_19_down1 :
bitdata[879:878] == 2'b10 ? cell_40_0 :
bitdata[879:878] == 2'b0 ? 1'b0 : 1'bx);
assign cell_34_0 =
(bitdata[251:251] == 1'b1 ? sw_0_0_19_down0 :
bitdata[251:251] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[881:880] == 2'b01 ? sw_0_1_19_down0 :
bitdata[881:880] == 2'b11 ? sw_0_1_19_down1 :
bitdata[881:880] == 2'b10 ? cell_40_0 :
bitdata[881:880] == 2'b0 ? 1'b0 : 1'bx);
assign cell_35_0 =
(bitdata[245:244] == 2'b11 ? sw_0_0_18_down0 :
bitdata[245:244] == 2'b10 ? cell_39_0 :
bitdata[245:244] == 2'b01 ? cell_40_0 :
bitdata[245:244] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[865:863] == 3'b101 ? sw_0_1_18_down0 :
bitdata[865:863] == 3'b011 ? sw_0_1_18_down1 :
bitdata[865:863] == 3'b111 ? sw_0_1_18_down2 :
bitdata[865:863] == 3'b100 ? cell_72_5 :
bitdata[865:863] == 3'b010 ? cell_72_6 :
bitdata[865:863] == 3'b110 ? cell_72_7 :
bitdata[865:863] == 3'b001 ? cell_72_8 :
bitdata[865:863] == 3'b0 ? 1'b0 : 1'bx);
assign cell_36_0 =
(bitdata[247:246] == 2'b11 ? sw_0_0_18_down0 :
bitdata[247:246] == 2'b10 ? cell_39_0 :
bitdata[247:246] == 2'b01 ? cell_40_0 :
bitdata[247:246] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[868:866] == 3'b101 ? sw_0_1_18_down0 :
bitdata[868:866] == 3'b011 ? sw_0_1_18_down1 :
bitdata[868:866] == 3'b111 ? sw_0_1_18_down2 :
bitdata[868:866] == 3'b100 ? cell_72_5 :
bitdata[868:866] == 3'b010 ? cell_72_6 :
bitdata[868:866] == 3'b110 ? cell_72_7 :
bitdata[868:866] == 3'b001 ? cell_72_8 :
bitdata[868:866] == 3'b0 ? 1'b0 : 1'bx);
assign cell_37_0 =
(bitdata[927:925] == 3'b001 ? sw_1_0_3_down0 :
bitdata[927:925] == 3'b101 ? sw_1_0_3_down1 :
bitdata[927:925] == 3'b100 ? cell_73_7 :
bitdata[927:925] == 3'b010 ? cell_87_0 :
bitdata[927:925] == 3'b110 ? cell_89_0 :
bitdata[927:925] == 3'b0 ? 8'b0 : 8'bx) |
(bitdata[1032:1032] == 1'b1 ? sw_1_1_7_down0 :
bitdata[1032:1032] == 1'b0 ? 8'b0 : 8'bx);
assign cell_41_0 =
(bitdata[239:239] == 1'b1 ? sw_0_0_17_down0 :
bitdata[239:239] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[871:869] == 3'b101 ? sw_0_1_18_down0 :
bitdata[871:869] == 3'b011 ? sw_0_1_18_down1 :
bitdata[871:869] == 3'b111 ? sw_0_1_18_down2 :
bitdata[871:869] == 3'b100 ? cell_72_5 :
bitdata[871:869] == 3'b010 ? cell_72_6 :
bitdata[871:869] == 3'b110 ? cell_72_7 :
bitdata[871:869] == 3'b001 ? cell_72_8 :
bitdata[871:869] == 3'b0 ? 1'b0 : 1'bx);
assign cell_42_0 =
(bitdata[277:275] == 3'b010 ? sw_0_0_24_down0 :
bitdata[277:275] == 3'b110 ? sw_0_0_24_down1 :
bitdata[277:275] == 3'b001 ? sw_0_0_24_down2 :
bitdata[277:275] == 3'b100 ? cell_3_0 :
bitdata[277:275] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[854:852] == 3'b010 ? sw_0_1_17_down0 :
bitdata[854:852] == 3'b110 ? sw_0_1_17_down1 :
bitdata[854:852] == 3'b001 ? sw_0_1_17_down2 :
bitdata[854:852] == 3'b100 ? cell_39_0 :
bitdata[854:852] == 3'b0 ? 1'b0 : 1'bx);
assign cell_44_0 =
(bitdata[210:209] == 2'b01 ? sw_0_0_11_down0 :
bitdata[210:209] == 2'b11 ? sw_0_0_11_down1 :
bitdata[210:209] == 2'b10 ? cell_43_0 :
bitdata[210:209] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[721:719] == 3'b010 ? sw_0_1_9_down0 :
bitdata[721:719] == 3'b110 ? sw_0_1_9_down1 :
bitdata[721:719] == 3'b001 ? sw_0_1_9_down2 :
bitdata[721:719] == 3'b100 ? cell_43_0 :
bitdata[721:719] == 3'b0 ? 1'b0 : 1'bx);
assign cell_4_0 =
(bitdata[953:952] == 2'b11 ? sw_1_0_5_down0 :
bitdata[953:952] == 2'b10 ? cell_75_3 :
bitdata[953:952] == 2'b01 ? cell_86_0 :
bitdata[953:952] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[1030:1030] == 1'b1 ? sw_1_1_7_down0 :
bitdata[1030:1030] == 1'b0 ? 8'b0 : 8'bx);
assign cell_53_0 =
(bitdata[228:228] == 1'b1 ? sw_0_0_14_down0 :
bitdata[228:228] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[842:842] == 1'b1 ? sw_0_1_14_down0 :
bitdata[842:842] == 1'b0 ? 1'b0 : 1'bx);
assign cell_54_0 =
(bitdata[229:229] == 1'b1 ? sw_0_0_14_down0 :
bitdata[229:229] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[843:843] == 1'b1 ? sw_0_1_14_down0 :
bitdata[843:843] == 1'b0 ? 1'b0 : 1'bx);
assign cell_55_0 =
(bitdata[230:230] == 1'b1 ? sw_0_0_14_down0 :
bitdata[230:230] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[844:844] == 1'b1 ? sw_0_1_14_down0 :
bitdata[844:844] == 1'b0 ? 1'b0 : 1'bx);
assign cell_56_0 =
(bitdata[231:231] == 1'b1 ? sw_0_0_14_down0 :
bitdata[231:231] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[845:845] == 1'b1 ? sw_0_1_14_down0 :
bitdata[845:845] == 1'b0 ? 1'b0 : 1'bx);
assign cell_57_0 =
(bitdata[224:224] == 1'b1 ? sw_0_0_13_down0 :
bitdata[224:224] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[838:838] == 1'b1 ? sw_0_1_13_down0 :
bitdata[838:838] == 1'b0 ? 1'b0 : 1'bx);
assign cell_58_0 =
(bitdata[225:225] == 1'b1 ? sw_0_0_13_down0 :
bitdata[225:225] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[839:839] == 1'b1 ? sw_0_1_13_down0 :
bitdata[839:839] == 1'b0 ? 1'b0 : 1'bx);
assign cell_59_0 =
(bitdata[226:226] == 1'b1 ? sw_0_0_13_down0 :
bitdata[226:226] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[840:840] == 1'b1 ? sw_0_1_13_down0 :
bitdata[840:840] == 1'b0 ? 1'b0 : 1'bx);
assign cell_60_0 =
(bitdata[227:227] == 1'b1 ? sw_0_0_13_down0 :
bitdata[227:227] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[841:841] == 1'b1 ? sw_0_1_13_down0 :
bitdata[841:841] == 1'b0 ? 1'b0 : 1'bx);
assign cell_61_0 =
(bitdata[116:112] == 5'b11110 ? sw_0_0_8_down0 :
bitdata[116:112] == 5'b00001 ? sw_0_0_8_down1 :
bitdata[116:112] == 5'b10001 ? sw_0_0_8_down2 :
bitdata[116:112] == 5'b01001 ? sw_0_0_8_down3 :
bitdata[116:112] == 5'b11001 ? sw_0_0_8_down4 :
bitdata[116:112] == 5'b10000 ? cell_71_5 :
bitdata[116:112] == 5'b01000 ? cell_71_6 :
bitdata[116:112] == 5'b11000 ? cell_71_7 :
bitdata[116:112] == 5'b00100 ? cell_71_8 :
bitdata[116:112] == 5'b10100 ? cell_80_6 :
bitdata[116:112] == 5'b01100 ? cell_80_7 :
bitdata[116:112] == 5'b11100 ? cell_80_8 :
bitdata[116:112] == 5'b00010 ? cell_80_9 :
bitdata[116:112] == 5'b10010 ? cell_80_10 :
bitdata[116:112] == 5'b01010 ? cell_80_11 :
bitdata[116:112] == 5'b11010 ? cell_80_12 :
bitdata[116:112] == 5'b00110 ? cell_80_13 :
bitdata[116:112] == 5'b10110 ? cell_80_14 :
bitdata[116:112] == 5'b01110 ? cell_80_15 :
bitdata[116:112] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[789:786] == 4'b0001 ? sw_0_1_11_down0 :
bitdata[789:786] == 4'b1001 ? sw_0_1_11_down1 :
bitdata[789:786] == 4'b0101 ? sw_0_1_11_down2 :
bitdata[789:786] == 4'b1101 ? sw_0_1_11_down3 :
bitdata[789:786] == 4'b1000 ? cell_63_8 :
bitdata[789:786] == 4'b0100 ? cell_63_9 :
bitdata[789:786] == 4'b1100 ? cell_71_5 :
bitdata[789:786] == 4'b0010 ? cell_71_6 :
bitdata[789:786] == 4'b1010 ? cell_71_7 :
bitdata[789:786] == 4'b0110 ? cell_71_8 :
bitdata[789:786] == 4'b1110 ? cell_83_0 :
bitdata[789:786] == 4'b0 ? 1'b0 : 1'bx);
assign cell_61_1 =
(bitdata[121:117] == 5'b11110 ? sw_0_0_8_down0 :
bitdata[121:117] == 5'b00001 ? sw_0_0_8_down1 :
bitdata[121:117] == 5'b10001 ? sw_0_0_8_down2 :
bitdata[121:117] == 5'b01001 ? sw_0_0_8_down3 :
bitdata[121:117] == 5'b11001 ? sw_0_0_8_down4 :
bitdata[121:117] == 5'b10000 ? cell_71_5 :
bitdata[121:117] == 5'b01000 ? cell_71_6 :
bitdata[121:117] == 5'b11000 ? cell_71_7 :
bitdata[121:117] == 5'b00100 ? cell_71_8 :
bitdata[121:117] == 5'b10100 ? cell_80_6 :
bitdata[121:117] == 5'b01100 ? cell_80_7 :
bitdata[121:117] == 5'b11100 ? cell_80_8 :
bitdata[121:117] == 5'b00010 ? cell_80_9 :
bitdata[121:117] == 5'b10010 ? cell_80_10 :
bitdata[121:117] == 5'b01010 ? cell_80_11 :
bitdata[121:117] == 5'b11010 ? cell_80_12 :
bitdata[121:117] == 5'b00110 ? cell_80_13 :
bitdata[121:117] == 5'b10110 ? cell_80_14 :
bitdata[121:117] == 5'b01110 ? cell_80_15 :
bitdata[121:117] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[793:790] == 4'b0001 ? sw_0_1_11_down0 :
bitdata[793:790] == 4'b1001 ? sw_0_1_11_down1 :
bitdata[793:790] == 4'b0101 ? sw_0_1_11_down2 :
bitdata[793:790] == 4'b1101 ? sw_0_1_11_down3 :
bitdata[793:790] == 4'b1000 ? cell_63_8 :
bitdata[793:790] == 4'b0100 ? cell_63_9 :
bitdata[793:790] == 4'b1100 ? cell_71_5 :
bitdata[793:790] == 4'b0010 ? cell_71_6 :
bitdata[793:790] == 4'b1010 ? cell_71_7 :
bitdata[793:790] == 4'b0110 ? cell_71_8 :
bitdata[793:790] == 4'b1110 ? cell_83_0 :
bitdata[793:790] == 4'b0 ? 1'b0 : 1'bx);
assign cell_61_2 =
(bitdata[126:122] == 5'b11110 ? sw_0_0_8_down0 :
bitdata[126:122] == 5'b00001 ? sw_0_0_8_down1 :
bitdata[126:122] == 5'b10001 ? sw_0_0_8_down2 :
bitdata[126:122] == 5'b01001 ? sw_0_0_8_down3 :
bitdata[126:122] == 5'b11001 ? sw_0_0_8_down4 :
bitdata[126:122] == 5'b10000 ? cell_71_5 :
bitdata[126:122] == 5'b01000 ? cell_71_6 :
bitdata[126:122] == 5'b11000 ? cell_71_7 :
bitdata[126:122] == 5'b00100 ? cell_71_8 :
bitdata[126:122] == 5'b10100 ? cell_80_6 :
bitdata[126:122] == 5'b01100 ? cell_80_7 :
bitdata[126:122] == 5'b11100 ? cell_80_8 :
bitdata[126:122] == 5'b00010 ? cell_80_9 :
bitdata[126:122] == 5'b10010 ? cell_80_10 :
bitdata[126:122] == 5'b01010 ? cell_80_11 :
bitdata[126:122] == 5'b11010 ? cell_80_12 :
bitdata[126:122] == 5'b00110 ? cell_80_13 :
bitdata[126:122] == 5'b10110 ? cell_80_14 :
bitdata[126:122] == 5'b01110 ? cell_80_15 :
bitdata[126:122] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[797:794] == 4'b0001 ? sw_0_1_11_down0 :
bitdata[797:794] == 4'b1001 ? sw_0_1_11_down1 :
bitdata[797:794] == 4'b0101 ? sw_0_1_11_down2 :
bitdata[797:794] == 4'b1101 ? sw_0_1_11_down3 :
bitdata[797:794] == 4'b1000 ? cell_63_8 :
bitdata[797:794] == 4'b0100 ? cell_63_9 :
bitdata[797:794] == 4'b1100 ? cell_71_5 :
bitdata[797:794] == 4'b0010 ? cell_71_6 :
bitdata[797:794] == 4'b1010 ? cell_71_7 :
bitdata[797:794] == 4'b0110 ? cell_71_8 :
bitdata[797:794] == 4'b1110 ? cell_83_0 :
bitdata[797:794] == 4'b0 ? 1'b0 : 1'bx);
assign cell_61_3 =
(bitdata[131:127] == 5'b11110 ? sw_0_0_8_down0 :
bitdata[131:127] == 5'b00001 ? sw_0_0_8_down1 :
bitdata[131:127] == 5'b10001 ? sw_0_0_8_down2 :
bitdata[131:127] == 5'b01001 ? sw_0_0_8_down3 :
bitdata[131:127] == 5'b11001 ? sw_0_0_8_down4 :
bitdata[131:127] == 5'b10000 ? cell_71_5 :
bitdata[131:127] == 5'b01000 ? cell_71_6 :
bitdata[131:127] == 5'b11000 ? cell_71_7 :
bitdata[131:127] == 5'b00100 ? cell_71_8 :
bitdata[131:127] == 5'b10100 ? cell_80_6 :
bitdata[131:127] == 5'b01100 ? cell_80_7 :
bitdata[131:127] == 5'b11100 ? cell_80_8 :
bitdata[131:127] == 5'b00010 ? cell_80_9 :
bitdata[131:127] == 5'b10010 ? cell_80_10 :
bitdata[131:127] == 5'b01010 ? cell_80_11 :
bitdata[131:127] == 5'b11010 ? cell_80_12 :
bitdata[131:127] == 5'b00110 ? cell_80_13 :
bitdata[131:127] == 5'b10110 ? cell_80_14 :
bitdata[131:127] == 5'b01110 ? cell_80_15 :
bitdata[131:127] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[801:798] == 4'b0001 ? sw_0_1_11_down0 :
bitdata[801:798] == 4'b1001 ? sw_0_1_11_down1 :
bitdata[801:798] == 4'b0101 ? sw_0_1_11_down2 :
bitdata[801:798] == 4'b1101 ? sw_0_1_11_down3 :
bitdata[801:798] == 4'b1000 ? cell_63_8 :
bitdata[801:798] == 4'b0100 ? cell_63_9 :
bitdata[801:798] == 4'b1100 ? cell_71_5 :
bitdata[801:798] == 4'b0010 ? cell_71_6 :
bitdata[801:798] == 4'b1010 ? cell_71_7 :
bitdata[801:798] == 4'b0110 ? cell_71_8 :
bitdata[801:798] == 4'b1110 ? cell_83_0 :
bitdata[801:798] == 4'b0 ? 1'b0 : 1'bx);
assign cell_61_4 =
(bitdata[1064:1063] == 2'b11 ? sw_2_0_4_down0 :
bitdata[1064:1063] == 2'b10 ? cell_79_3 :
bitdata[1064:1063] == 2'b01 ? cell_91_0 :
bitdata[1064:1063] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1200:1198] == 3'b001 ? sw_2_1_8_down0 :
bitdata[1200:1198] == 3'b100 ? cell_62_5 :
bitdata[1200:1198] == 3'b010 ? cell_64_6 :
bitdata[1200:1198] == 3'b110 ? cell_64_7 :
bitdata[1200:1198] == 3'b0 ? 16'b0 : 16'bx);
assign cell_62_0 =
(bitdata[183:181] == 3'b001 ? sw_0_0_10_down0 :
bitdata[183:181] == 3'b101 ? sw_0_0_10_down1 :
bitdata[183:181] == 3'b011 ? sw_0_0_10_down2 :
bitdata[183:181] == 3'b100 ? cell_64_8 :
bitdata[183:181] == 3'b010 ? cell_64_9 :
bitdata[183:181] == 3'b110 ? cell_83_0 :
bitdata[183:181] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[737:734] == 4'b0010 ? sw_0_1_10_down0 :
bitdata[737:734] == 4'b1010 ? sw_0_1_10_down1 :
bitdata[737:734] == 4'b0110 ? sw_0_1_10_down2 :
bitdata[737:734] == 4'b1110 ? sw_0_1_10_down3 :
bitdata[737:734] == 4'b0001 ? sw_0_1_10_down4 :
bitdata[737:734] == 4'b1000 ? cell_64_8 :
bitdata[737:734] == 4'b0100 ? cell_64_9 :
bitdata[737:734] == 4'b1100 ? cell_82_0 :
bitdata[737:734] == 4'b0 ? 1'b0 : 1'bx);
assign cell_62_1 =
(bitdata[186:184] == 3'b001 ? sw_0_0_10_down0 :
bitdata[186:184] == 3'b101 ? sw_0_0_10_down1 :
bitdata[186:184] == 3'b011 ? sw_0_0_10_down2 :
bitdata[186:184] == 3'b100 ? cell_64_8 :
bitdata[186:184] == 3'b010 ? cell_64_9 :
bitdata[186:184] == 3'b110 ? cell_83_0 :
bitdata[186:184] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[741:738] == 4'b0010 ? sw_0_1_10_down0 :
bitdata[741:738] == 4'b1010 ? sw_0_1_10_down1 :
bitdata[741:738] == 4'b0110 ? sw_0_1_10_down2 :
bitdata[741:738] == 4'b1110 ? sw_0_1_10_down3 :
bitdata[741:738] == 4'b0001 ? sw_0_1_10_down4 :
bitdata[741:738] == 4'b1000 ? cell_64_8 :
bitdata[741:738] == 4'b0100 ? cell_64_9 :
bitdata[741:738] == 4'b1100 ? cell_82_0 :
bitdata[741:738] == 4'b0 ? 1'b0 : 1'bx);
assign cell_62_2 =
(bitdata[189:187] == 3'b001 ? sw_0_0_10_down0 :
bitdata[189:187] == 3'b101 ? sw_0_0_10_down1 :
bitdata[189:187] == 3'b011 ? sw_0_0_10_down2 :
bitdata[189:187] == 3'b100 ? cell_64_8 :
bitdata[189:187] == 3'b010 ? cell_64_9 :
bitdata[189:187] == 3'b110 ? cell_83_0 :
bitdata[189:187] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[745:742] == 4'b0010 ? sw_0_1_10_down0 :
bitdata[745:742] == 4'b1010 ? sw_0_1_10_down1 :
bitdata[745:742] == 4'b0110 ? sw_0_1_10_down2 :
bitdata[745:742] == 4'b1110 ? sw_0_1_10_down3 :
bitdata[745:742] == 4'b0001 ? sw_0_1_10_down4 :
bitdata[745:742] == 4'b1000 ? cell_64_8 :
bitdata[745:742] == 4'b0100 ? cell_64_9 :
bitdata[745:742] == 4'b1100 ? cell_82_0 :
bitdata[745:742] == 4'b0 ? 1'b0 : 1'bx);
assign cell_62_3 =
(bitdata[192:190] == 3'b001 ? sw_0_0_10_down0 :
bitdata[192:190] == 3'b101 ? sw_0_0_10_down1 :
bitdata[192:190] == 3'b011 ? sw_0_0_10_down2 :
bitdata[192:190] == 3'b100 ? cell_64_8 :
bitdata[192:190] == 3'b010 ? cell_64_9 :
bitdata[192:190] == 3'b110 ? cell_83_0 :
bitdata[192:190] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[749:746] == 4'b0010 ? sw_0_1_10_down0 :
bitdata[749:746] == 4'b1010 ? sw_0_1_10_down1 :
bitdata[749:746] == 4'b0110 ? sw_0_1_10_down2 :
bitdata[749:746] == 4'b1110 ? sw_0_1_10_down3 :
bitdata[749:746] == 4'b0001 ? sw_0_1_10_down4 :
bitdata[749:746] == 4'b1000 ? cell_64_8 :
bitdata[749:746] == 4'b0100 ? cell_64_9 :
bitdata[749:746] == 4'b1100 ? cell_82_0 :
bitdata[749:746] == 4'b0 ? 1'b0 : 1'bx);
assign cell_62_4 =
(bitdata[1054:1052] == 3'b101 ? sw_2_0_3_down0 :
bitdata[1054:1052] == 3'b100 ? cell_63_6 :
bitdata[1054:1052] == 3'b010 ? cell_63_7 :
bitdata[1054:1052] == 3'b110 ? cell_93_0 :
bitdata[1054:1052] == 3'b001 ? cell_94_0 :
bitdata[1054:1052] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1203:1201] == 3'b001 ? sw_2_1_8_down0 :
bitdata[1203:1201] == 3'b100 ? cell_61_5 :
bitdata[1203:1201] == 3'b010 ? cell_64_6 :
bitdata[1203:1201] == 3'b110 ? cell_64_7 :
bitdata[1203:1201] == 3'b0 ? 16'b0 : 16'bx);
assign cell_63_0 =
(bitdata[307:303] == 5'b00001 ? sw_0_0_25_down0 :
bitdata[307:303] == 5'b10001 ? sw_0_0_25_down1 :
bitdata[307:303] == 5'b01001 ? sw_0_0_25_down2 :
bitdata[307:303] == 5'b10000 ? cell_81_10 :
bitdata[307:303] == 5'b01000 ? cell_81_11 :
bitdata[307:303] == 5'b11000 ? cell_81_12 :
bitdata[307:303] == 5'b00100 ? cell_81_13 :
bitdata[307:303] == 5'b10100 ? cell_81_14 :
bitdata[307:303] == 5'b01100 ? cell_81_15 :
bitdata[307:303] == 5'b11100 ? cell_81_16 :
bitdata[307:303] == 5'b00010 ? cell_81_17 :
bitdata[307:303] == 5'b10010 ? cell_81_18 :
bitdata[307:303] == 5'b01010 ? cell_81_19 :
bitdata[307:303] == 5'b11010 ? cell_81_20 :
bitdata[307:303] == 5'b00110 ? cell_81_21 :
bitdata[307:303] == 5'b10110 ? cell_81_22 :
bitdata[307:303] == 5'b01110 ? cell_81_23 :
bitdata[307:303] == 5'b11110 ? cell_81_24 :
bitdata[307:303] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[805:802] == 4'b0001 ? sw_0_1_11_down0 :
bitdata[805:802] == 4'b1001 ? sw_0_1_11_down1 :
bitdata[805:802] == 4'b0101 ? sw_0_1_11_down2 :
bitdata[805:802] == 4'b1101 ? sw_0_1_11_down3 :
bitdata[805:802] == 4'b1000 ? cell_61_6 :
bitdata[805:802] == 4'b0100 ? cell_61_7 :
bitdata[805:802] == 4'b1100 ? cell_71_5 :
bitdata[805:802] == 4'b0010 ? cell_71_6 :
bitdata[805:802] == 4'b1010 ? cell_71_7 :
bitdata[805:802] == 4'b0110 ? cell_71_8 :
bitdata[805:802] == 4'b1110 ? cell_83_0 :
bitdata[805:802] == 4'b0 ? 1'b0 : 1'bx);
assign cell_63_1 =
(bitdata[312:308] == 5'b00001 ? sw_0_0_25_down0 :
bitdata[312:308] == 5'b10001 ? sw_0_0_25_down1 :
bitdata[312:308] == 5'b01001 ? sw_0_0_25_down2 :
bitdata[312:308] == 5'b10000 ? cell_81_10 :
bitdata[312:308] == 5'b01000 ? cell_81_11 :
bitdata[312:308] == 5'b11000 ? cell_81_12 :
bitdata[312:308] == 5'b00100 ? cell_81_13 :
bitdata[312:308] == 5'b10100 ? cell_81_14 :
bitdata[312:308] == 5'b01100 ? cell_81_15 :
bitdata[312:308] == 5'b11100 ? cell_81_16 :
bitdata[312:308] == 5'b00010 ? cell_81_17 :
bitdata[312:308] == 5'b10010 ? cell_81_18 :
bitdata[312:308] == 5'b01010 ? cell_81_19 :
bitdata[312:308] == 5'b11010 ? cell_81_20 :
bitdata[312:308] == 5'b00110 ? cell_81_21 :
bitdata[312:308] == 5'b10110 ? cell_81_22 :
bitdata[312:308] == 5'b01110 ? cell_81_23 :
bitdata[312:308] == 5'b11110 ? cell_81_24 :
bitdata[312:308] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[809:806] == 4'b0001 ? sw_0_1_11_down0 :
bitdata[809:806] == 4'b1001 ? sw_0_1_11_down1 :
bitdata[809:806] == 4'b0101 ? sw_0_1_11_down2 :
bitdata[809:806] == 4'b1101 ? sw_0_1_11_down3 :
bitdata[809:806] == 4'b1000 ? cell_61_6 :
bitdata[809:806] == 4'b0100 ? cell_61_7 :
bitdata[809:806] == 4'b1100 ? cell_71_5 :
bitdata[809:806] == 4'b0010 ? cell_71_6 :
bitdata[809:806] == 4'b1010 ? cell_71_7 :
bitdata[809:806] == 4'b0110 ? cell_71_8 :
bitdata[809:806] == 4'b1110 ? cell_83_0 :
bitdata[809:806] == 4'b0 ? 1'b0 : 1'bx);
assign cell_63_2 =
(bitdata[317:313] == 5'b00001 ? sw_0_0_25_down0 :
bitdata[317:313] == 5'b10001 ? sw_0_0_25_down1 :
bitdata[317:313] == 5'b01001 ? sw_0_0_25_down2 :
bitdata[317:313] == 5'b10000 ? cell_81_10 :
bitdata[317:313] == 5'b01000 ? cell_81_11 :
bitdata[317:313] == 5'b11000 ? cell_81_12 :
bitdata[317:313] == 5'b00100 ? cell_81_13 :
bitdata[317:313] == 5'b10100 ? cell_81_14 :
bitdata[317:313] == 5'b01100 ? cell_81_15 :
bitdata[317:313] == 5'b11100 ? cell_81_16 :
bitdata[317:313] == 5'b00010 ? cell_81_17 :
bitdata[317:313] == 5'b10010 ? cell_81_18 :
bitdata[317:313] == 5'b01010 ? cell_81_19 :
bitdata[317:313] == 5'b11010 ? cell_81_20 :
bitdata[317:313] == 5'b00110 ? cell_81_21 :
bitdata[317:313] == 5'b10110 ? cell_81_22 :
bitdata[317:313] == 5'b01110 ? cell_81_23 :
bitdata[317:313] == 5'b11110 ? cell_81_24 :
bitdata[317:313] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[813:810] == 4'b0001 ? sw_0_1_11_down0 :
bitdata[813:810] == 4'b1001 ? sw_0_1_11_down1 :
bitdata[813:810] == 4'b0101 ? sw_0_1_11_down2 :
bitdata[813:810] == 4'b1101 ? sw_0_1_11_down3 :
bitdata[813:810] == 4'b1000 ? cell_61_6 :
bitdata[813:810] == 4'b0100 ? cell_61_7 :
bitdata[813:810] == 4'b1100 ? cell_71_5 :
bitdata[813:810] == 4'b0010 ? cell_71_6 :
bitdata[813:810] == 4'b1010 ? cell_71_7 :
bitdata[813:810] == 4'b0110 ? cell_71_8 :
bitdata[813:810] == 4'b1110 ? cell_83_0 :
bitdata[813:810] == 4'b0 ? 1'b0 : 1'bx);
assign cell_63_3 =
(bitdata[322:318] == 5'b00001 ? sw_0_0_25_down0 :
bitdata[322:318] == 5'b10001 ? sw_0_0_25_down1 :
bitdata[322:318] == 5'b01001 ? sw_0_0_25_down2 :
bitdata[322:318] == 5'b10000 ? cell_81_10 :
bitdata[322:318] == 5'b01000 ? cell_81_11 :
bitdata[322:318] == 5'b11000 ? cell_81_12 :
bitdata[322:318] == 5'b00100 ? cell_81_13 :
bitdata[322:318] == 5'b10100 ? cell_81_14 :
bitdata[322:318] == 5'b01100 ? cell_81_15 :
bitdata[322:318] == 5'b11100 ? cell_81_16 :
bitdata[322:318] == 5'b00010 ? cell_81_17 :
bitdata[322:318] == 5'b10010 ? cell_81_18 :
bitdata[322:318] == 5'b01010 ? cell_81_19 :
bitdata[322:318] == 5'b11010 ? cell_81_20 :
bitdata[322:318] == 5'b00110 ? cell_81_21 :
bitdata[322:318] == 5'b10110 ? cell_81_22 :
bitdata[322:318] == 5'b01110 ? cell_81_23 :
bitdata[322:318] == 5'b11110 ? cell_81_24 :
bitdata[322:318] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[817:814] == 4'b0001 ? sw_0_1_11_down0 :
bitdata[817:814] == 4'b1001 ? sw_0_1_11_down1 :
bitdata[817:814] == 4'b0101 ? sw_0_1_11_down2 :
bitdata[817:814] == 4'b1101 ? sw_0_1_11_down3 :
bitdata[817:814] == 4'b1000 ? cell_61_6 :
bitdata[817:814] == 4'b0100 ? cell_61_7 :
bitdata[817:814] == 4'b1100 ? cell_71_5 :
bitdata[817:814] == 4'b0010 ? cell_71_6 :
bitdata[817:814] == 4'b1010 ? cell_71_7 :
bitdata[817:814] == 4'b0110 ? cell_71_8 :
bitdata[817:814] == 4'b1110 ? cell_83_0 :
bitdata[817:814] == 4'b0 ? 1'b0 : 1'bx);
assign cell_63_4 =
(bitdata[1057:1055] == 3'b001 ? sw_2_0_3_down0 :
bitdata[1057:1055] == 3'b100 ? cell_62_5 :
bitdata[1057:1055] == 3'b010 ? cell_93_0 :
bitdata[1057:1055] == 3'b110 ? cell_94_0 :
bitdata[1057:1055] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1159:1157] == 3'b001 ? sw_2_1_5_down0 :
bitdata[1159:1157] == 3'b100 ? cell_79_3 :
bitdata[1159:1157] == 3'b010 ? cell_90_0 :
bitdata[1159:1157] == 3'b110 ? cell_91_0 :
bitdata[1159:1157] == 3'b0 ? 16'b0 : 16'bx);
assign cell_63_5 =
(bitdata[1060:1058] == 3'b001 ? sw_2_0_3_down0 :
bitdata[1060:1058] == 3'b100 ? cell_62_5 :
bitdata[1060:1058] == 3'b010 ? cell_93_0 :
bitdata[1060:1058] == 3'b110 ? cell_94_0 :
bitdata[1060:1058] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1162:1160] == 3'b001 ? sw_2_1_5_down0 :
bitdata[1162:1160] == 3'b100 ? cell_79_3 :
bitdata[1162:1160] == 3'b010 ? cell_90_0 :
bitdata[1162:1160] == 3'b110 ? cell_91_0 :
bitdata[1162:1160] == 3'b0 ? 16'b0 : 16'bx);
assign cell_64_0 =
(bitdata[195:193] == 3'b001 ? sw_0_0_10_down0 :
bitdata[195:193] == 3'b101 ? sw_0_0_10_down1 :
bitdata[195:193] == 3'b011 ? sw_0_0_10_down2 :
bitdata[195:193] == 3'b100 ? cell_62_6 :
bitdata[195:193] == 3'b010 ? cell_62_7 :
bitdata[195:193] == 3'b110 ? cell_83_0 :
bitdata[195:193] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[753:750] == 4'b0010 ? sw_0_1_10_down0 :
bitdata[753:750] == 4'b1010 ? sw_0_1_10_down1 :
bitdata[753:750] == 4'b0110 ? sw_0_1_10_down2 :
bitdata[753:750] == 4'b1110 ? sw_0_1_10_down3 :
bitdata[753:750] == 4'b0001 ? sw_0_1_10_down4 :
bitdata[753:750] == 4'b1000 ? cell_62_6 :
bitdata[753:750] == 4'b0100 ? cell_62_7 :
bitdata[753:750] == 4'b1100 ? cell_82_0 :
bitdata[753:750] == 4'b0 ? 1'b0 : 1'bx);
assign cell_64_1 =
(bitdata[198:196] == 3'b001 ? sw_0_0_10_down0 :
bitdata[198:196] == 3'b101 ? sw_0_0_10_down1 :
bitdata[198:196] == 3'b011 ? sw_0_0_10_down2 :
bitdata[198:196] == 3'b100 ? cell_62_6 :
bitdata[198:196] == 3'b010 ? cell_62_7 :
bitdata[198:196] == 3'b110 ? cell_83_0 :
bitdata[198:196] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[757:754] == 4'b0010 ? sw_0_1_10_down0 :
bitdata[757:754] == 4'b1010 ? sw_0_1_10_down1 :
bitdata[757:754] == 4'b0110 ? sw_0_1_10_down2 :
bitdata[757:754] == 4'b1110 ? sw_0_1_10_down3 :
bitdata[757:754] == 4'b0001 ? sw_0_1_10_down4 :
bitdata[757:754] == 4'b1000 ? cell_62_6 :
bitdata[757:754] == 4'b0100 ? cell_62_7 :
bitdata[757:754] == 4'b1100 ? cell_82_0 :
bitdata[757:754] == 4'b0 ? 1'b0 : 1'bx);
assign cell_64_2 =
(bitdata[201:199] == 3'b001 ? sw_0_0_10_down0 :
bitdata[201:199] == 3'b101 ? sw_0_0_10_down1 :
bitdata[201:199] == 3'b011 ? sw_0_0_10_down2 :
bitdata[201:199] == 3'b100 ? cell_62_6 :
bitdata[201:199] == 3'b010 ? cell_62_7 :
bitdata[201:199] == 3'b110 ? cell_83_0 :
bitdata[201:199] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[761:758] == 4'b0010 ? sw_0_1_10_down0 :
bitdata[761:758] == 4'b1010 ? sw_0_1_10_down1 :
bitdata[761:758] == 4'b0110 ? sw_0_1_10_down2 :
bitdata[761:758] == 4'b1110 ? sw_0_1_10_down3 :
bitdata[761:758] == 4'b0001 ? sw_0_1_10_down4 :
bitdata[761:758] == 4'b1000 ? cell_62_6 :
bitdata[761:758] == 4'b0100 ? cell_62_7 :
bitdata[761:758] == 4'b1100 ? cell_82_0 :
bitdata[761:758] == 4'b0 ? 1'b0 : 1'bx);
assign cell_64_3 =
(bitdata[204:202] == 3'b001 ? sw_0_0_10_down0 :
bitdata[204:202] == 3'b101 ? sw_0_0_10_down1 :
bitdata[204:202] == 3'b011 ? sw_0_0_10_down2 :
bitdata[204:202] == 3'b100 ? cell_62_6 :
bitdata[204:202] == 3'b010 ? cell_62_7 :
bitdata[204:202] == 3'b110 ? cell_83_0 :
bitdata[204:202] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[765:762] == 4'b0010 ? sw_0_1_10_down0 :
bitdata[765:762] == 4'b1010 ? sw_0_1_10_down1 :
bitdata[765:762] == 4'b0110 ? sw_0_1_10_down2 :
bitdata[765:762] == 4'b1110 ? sw_0_1_10_down3 :
bitdata[765:762] == 4'b0001 ? sw_0_1_10_down4 :
bitdata[765:762] == 4'b1000 ? cell_62_6 :
bitdata[765:762] == 4'b0100 ? cell_62_7 :
bitdata[765:762] == 4'b1100 ? cell_82_0 :
bitdata[765:762] == 4'b0 ? 1'b0 : 1'bx);
assign cell_64_4 =
(bitdata[1094:1092] == 3'b001 ? sw_2_0_6_down0 :
bitdata[1094:1092] == 3'b100 ? cell_76_2 :
bitdata[1094:1092] == 3'b010 ? cell_92_0 :
bitdata[1094:1092] == 3'b110 ? cell_95_0 :
bitdata[1094:1092] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1205:1204] == 2'b11 ? sw_2_1_8_down0 :
bitdata[1205:1204] == 2'b10 ? cell_61_5 :
bitdata[1205:1204] == 2'b01 ? cell_62_5 :
bitdata[1205:1204] == 2'b0 ? 16'b0 : 16'bx);
assign cell_64_5 =
(bitdata[1097:1095] == 3'b001 ? sw_2_0_6_down0 :
bitdata[1097:1095] == 3'b100 ? cell_76_2 :
bitdata[1097:1095] == 3'b010 ? cell_92_0 :
bitdata[1097:1095] == 3'b110 ? cell_95_0 :
bitdata[1097:1095] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1207:1206] == 2'b11 ? sw_2_1_8_down0 :
bitdata[1207:1206] == 2'b10 ? cell_61_5 :
bitdata[1207:1206] == 2'b01 ? cell_62_5 :
bitdata[1207:1206] == 2'b0 ? 16'b0 : 16'bx);
assign cell_65_0 =
(bitdata[1101:1100] == 2'b11 ? sw_2_0_7_down0 :
bitdata[1101:1100] == 2'b10 ? cell_66_1 :
bitdata[1101:1100] == 2'b01 ? cell_71_3 :
bitdata[1101:1100] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1189:1187] == 3'b001 ? sw_2_1_7_down0 :
bitdata[1189:1187] == 3'b101 ? sw_2_1_7_down1 :
bitdata[1189:1187] == 3'b100 ? cell_2_0 :
bitdata[1189:1187] == 3'b010 ? cell_66_1 :
bitdata[1189:1187] == 3'b110 ? cell_76_2 :
bitdata[1189:1187] == 3'b0 ? 16'b0 : 16'bx);
assign cell_65_1 =
(bitdata[1103:1102] == 2'b11 ? sw_2_0_7_down0 :
bitdata[1103:1102] == 2'b10 ? cell_66_1 :
bitdata[1103:1102] == 2'b01 ? cell_71_3 :
bitdata[1103:1102] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1192:1190] == 3'b001 ? sw_2_1_7_down0 :
bitdata[1192:1190] == 3'b101 ? sw_2_1_7_down1 :
bitdata[1192:1190] == 3'b100 ? cell_2_0 :
bitdata[1192:1190] == 3'b010 ? cell_66_1 :
bitdata[1192:1190] == 3'b110 ? cell_76_2 :
bitdata[1192:1190] == 3'b0 ? 16'b0 : 16'bx);
assign cell_66_0 =
(bitdata[1105:1104] == 2'b11 ? sw_2_0_7_down0 :
bitdata[1105:1104] == 2'b10 ? cell_65_2 :
bitdata[1105:1104] == 2'b01 ? cell_71_3 :
bitdata[1105:1104] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1195:1193] == 3'b001 ? sw_2_1_7_down0 :
bitdata[1195:1193] == 3'b101 ? sw_2_1_7_down1 :
bitdata[1195:1193] == 3'b100 ? cell_2_0 :
bitdata[1195:1193] == 3'b010 ? cell_65_2 :
bitdata[1195:1193] == 3'b110 ? cell_76_2 :
bitdata[1195:1193] == 3'b0 ? 16'b0 : 16'bx);
assign cell_66_2 =
(bitdata[216:214] == 3'b011 ? sw_0_0_12_down0 :
bitdata[216:214] == 3'b100 ? cell_8_0 :
bitdata[216:214] == 3'b010 ? cell_72_5 :
bitdata[216:214] == 3'b110 ? cell_72_6 :
bitdata[216:214] == 3'b001 ? cell_72_7 :
bitdata[216:214] == 3'b101 ? cell_72_8 :
bitdata[216:214] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[630:626] == 5'b01011 ? sw_0_1_8_down0 :
bitdata[630:626] == 5'b11011 ? sw_0_1_8_down1 :
bitdata[630:626] == 5'b00111 ? sw_0_1_8_down2 :
bitdata[630:626] == 5'b10111 ? sw_0_1_8_down3 :
bitdata[630:626] == 5'b01111 ? sw_0_1_8_down4 :
bitdata[630:626] == 5'b11111 ? sw_0_1_8_down5 :
bitdata[630:626] == 5'b10000 ? cell_80_6 :
bitdata[630:626] == 5'b01000 ? cell_80_7 :
bitdata[630:626] == 5'b11000 ? cell_80_8 :
bitdata[630:626] == 5'b00100 ? cell_80_9 :
bitdata[630:626] == 5'b10100 ? cell_80_10 :
bitdata[630:626] == 5'b01100 ? cell_80_11 :
bitdata[630:626] == 5'b11100 ? cell_80_12 :
bitdata[630:626] == 5'b00010 ? cell_80_13 :
bitdata[630:626] == 5'b10010 ? cell_80_14 :
bitdata[630:626] == 5'b01010 ? cell_80_15 :
bitdata[630:626] == 5'b11010 ? cell_81_10 :
bitdata[630:626] == 5'b00110 ? cell_81_11 :
bitdata[630:626] == 5'b10110 ? cell_81_12 :
bitdata[630:626] == 5'b01110 ? cell_81_13 :
bitdata[630:626] == 5'b11110 ? cell_81_14 :
bitdata[630:626] == 5'b00001 ? cell_81_15 :
bitdata[630:626] == 5'b10001 ? cell_81_16 :
bitdata[630:626] == 5'b01001 ? cell_81_17 :
bitdata[630:626] == 5'b11001 ? cell_81_18 :
bitdata[630:626] == 5'b00101 ? cell_81_19 :
bitdata[630:626] == 5'b10101 ? cell_81_20 :
bitdata[630:626] == 5'b01101 ? cell_81_21 :
bitdata[630:626] == 5'b11101 ? cell_81_22 :
bitdata[630:626] == 5'b00011 ? cell_81_23 :
bitdata[630:626] == 5'b10011 ? cell_81_24 :
bitdata[630:626] == 5'b0 ? 1'b0 : 1'bx);
assign cell_67_0 =
(bitdata[1076:1074] == 3'b001 ? sw_2_0_5_down0 :
bitdata[1076:1074] == 3'b100 ? cell_72_3 :
bitdata[1076:1074] == 3'b010 ? cell_77_2 :
bitdata[1076:1074] == 3'b110 ? cell_78_3 :
bitdata[1076:1074] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1175:1173] == 3'b001 ? sw_2_1_6_down0 :
bitdata[1175:1173] == 3'b100 ? cell_68_1 :
bitdata[1175:1173] == 3'b010 ? cell_72_3 :
bitdata[1175:1173] == 3'b110 ? cell_77_2 :
bitdata[1175:1173] == 3'b0 ? 16'b0 : 16'bx);
assign cell_67_2 =
(bitdata[240:240] == 1'b1 ? sw_0_0_17_down0 :
bitdata[240:240] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[827:826] == 2'b10 ? sw_0_1_12_down0 :
bitdata[827:826] == 2'b01 ? sw_0_1_12_down1 :
bitdata[827:826] == 2'b0 ? 1'b0 : 1'bx);
assign cell_68_0 =
(bitdata[1116:1115] == 2'b11 ? sw_2_0_8_down0 :
bitdata[1116:1115] == 2'b10 ? cell_2_0 :
bitdata[1116:1115] == 2'b01 ? cell_90_0 :
bitdata[1116:1115] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1178:1176] == 3'b001 ? sw_2_1_6_down0 :
bitdata[1178:1176] == 3'b100 ? cell_67_1 :
bitdata[1178:1176] == 3'b010 ? cell_72_3 :
bitdata[1178:1176] == 3'b110 ? cell_77_2 :
bitdata[1178:1176] == 3'b0 ? 16'b0 : 16'bx);
assign cell_68_2 =
(bitdata[241:241] == 1'b1 ? sw_0_0_17_down0 :
bitdata[241:241] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[829:828] == 2'b10 ? sw_0_1_12_down0 :
bitdata[829:828] == 2'b01 ? sw_0_1_12_down1 :
bitdata[829:828] == 2'b0 ? 1'b0 : 1'bx);
assign cell_69_0 =
(bitdata[960:959] == 2'b01 ? sw_1_0_6_down0 :
bitdata[960:959] == 2'b10 ? cell_70_1 :
bitdata[960:959] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[1026:1024] == 3'b001 ? sw_1_1_6_down0 :
bitdata[1026:1024] == 3'b100 ? cell_5_0 :
bitdata[1026:1024] == 3'b010 ? cell_38_0 :
bitdata[1026:1024] == 3'b110 ? cell_70_1 :
bitdata[1026:1024] == 3'b0 ? 8'b0 : 8'bx);
assign cell_69_2 =
(bitdata[261:261] == 1'b1 ? sw_0_0_21_down0 :
bitdata[261:261] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[635:631] == 5'b01011 ? sw_0_1_8_down0 :
bitdata[635:631] == 5'b11011 ? sw_0_1_8_down1 :
bitdata[635:631] == 5'b00111 ? sw_0_1_8_down2 :
bitdata[635:631] == 5'b10111 ? sw_0_1_8_down3 :
bitdata[635:631] == 5'b01111 ? sw_0_1_8_down4 :
bitdata[635:631] == 5'b11111 ? sw_0_1_8_down5 :
bitdata[635:631] == 5'b10000 ? cell_80_6 :
bitdata[635:631] == 5'b01000 ? cell_80_7 :
bitdata[635:631] == 5'b11000 ? cell_80_8 :
bitdata[635:631] == 5'b00100 ? cell_80_9 :
bitdata[635:631] == 5'b10100 ? cell_80_10 :
bitdata[635:631] == 5'b01100 ? cell_80_11 :
bitdata[635:631] == 5'b11100 ? cell_80_12 :
bitdata[635:631] == 5'b00010 ? cell_80_13 :
bitdata[635:631] == 5'b10010 ? cell_80_14 :
bitdata[635:631] == 5'b01010 ? cell_80_15 :
bitdata[635:631] == 5'b11010 ? cell_81_10 :
bitdata[635:631] == 5'b00110 ? cell_81_11 :
bitdata[635:631] == 5'b10110 ? cell_81_12 :
bitdata[635:631] == 5'b01110 ? cell_81_13 :
bitdata[635:631] == 5'b11110 ? cell_81_14 :
bitdata[635:631] == 5'b00001 ? cell_81_15 :
bitdata[635:631] == 5'b10001 ? cell_81_16 :
bitdata[635:631] == 5'b01001 ? cell_81_17 :
bitdata[635:631] == 5'b11001 ? cell_81_18 :
bitdata[635:631] == 5'b00101 ? cell_81_19 :
bitdata[635:631] == 5'b10101 ? cell_81_20 :
bitdata[635:631] == 5'b01101 ? cell_81_21 :
bitdata[635:631] == 5'b11101 ? cell_81_22 :
bitdata[635:631] == 5'b00011 ? cell_81_23 :
bitdata[635:631] == 5'b10011 ? cell_81_24 :
bitdata[635:631] == 5'b0 ? 1'b0 : 1'bx);
assign cell_70_0 =
(bitdata[962:961] == 2'b01 ? sw_1_0_6_down0 :
bitdata[962:961] == 2'b10 ? cell_69_1 :
bitdata[962:961] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[1029:1027] == 3'b001 ? sw_1_1_6_down0 :
bitdata[1029:1027] == 3'b100 ? cell_5_0 :
bitdata[1029:1027] == 3'b010 ? cell_38_0 :
bitdata[1029:1027] == 3'b110 ? cell_69_1 :
bitdata[1029:1027] == 3'b0 ? 8'b0 : 8'bx);
assign cell_70_2 =
(bitdata[266:264] == 3'b001 ? sw_0_0_22_down0 :
bitdata[266:264] == 3'b100 ? cell_19_0 :
bitdata[266:264] == 3'b010 ? cell_20_0 :
bitdata[266:264] == 3'b110 ? cell_21_0 :
bitdata[266:264] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[769:766] == 4'b0110 ? sw_0_1_10_down0 :
bitdata[769:766] == 4'b1110 ? sw_0_1_10_down1 :
bitdata[769:766] == 4'b0001 ? sw_0_1_10_down2 :
bitdata[769:766] == 4'b1001 ? sw_0_1_10_down3 :
bitdata[769:766] == 4'b0101 ? sw_0_1_10_down4 :
bitdata[769:766] == 4'b1000 ? cell_62_6 :
bitdata[769:766] == 4'b0100 ? cell_62_7 :
bitdata[769:766] == 4'b1100 ? cell_64_8 :
bitdata[769:766] == 4'b0010 ? cell_64_9 :
bitdata[769:766] == 4'b1010 ? cell_82_0 :
bitdata[769:766] == 4'b0 ? 1'b0 : 1'bx);
assign cell_71_0 =
(bitdata[136:132] == 5'b10110 ? sw_0_0_8_down0 :
bitdata[136:132] == 5'b01110 ? sw_0_0_8_down1 :
bitdata[136:132] == 5'b11110 ? sw_0_0_8_down2 :
bitdata[136:132] == 5'b00001 ? sw_0_0_8_down3 :
bitdata[136:132] == 5'b10001 ? sw_0_0_8_down4 :
bitdata[136:132] == 5'b10000 ? cell_61_6 :
bitdata[136:132] == 5'b01000 ? cell_61_7 :
bitdata[136:132] == 5'b11000 ? cell_80_6 :
bitdata[136:132] == 5'b00100 ? cell_80_7 :
bitdata[136:132] == 5'b10100 ? cell_80_8 :
bitdata[136:132] == 5'b01100 ? cell_80_9 :
bitdata[136:132] == 5'b11100 ? cell_80_10 :
bitdata[136:132] == 5'b00010 ? cell_80_11 :
bitdata[136:132] == 5'b10010 ? cell_80_12 :
bitdata[136:132] == 5'b01010 ? cell_80_13 :
bitdata[136:132] == 5'b11010 ? cell_80_14 :
bitdata[136:132] == 5'b00110 ? cell_80_15 :
bitdata[136:132] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[821:818] == 4'b0110 ? sw_0_1_11_down0 :
bitdata[821:818] == 4'b1110 ? sw_0_1_11_down1 :
bitdata[821:818] == 4'b0001 ? sw_0_1_11_down2 :
bitdata[821:818] == 4'b1001 ? sw_0_1_11_down3 :
bitdata[821:818] == 4'b1000 ? cell_61_6 :
bitdata[821:818] == 4'b0100 ? cell_61_7 :
bitdata[821:818] == 4'b1100 ? cell_63_8 :
bitdata[821:818] == 4'b0010 ? cell_63_9 :
bitdata[821:818] == 4'b1010 ? cell_83_0 :
bitdata[821:818] == 4'b0 ? 1'b0 : 1'bx);
assign cell_71_1 =
(bitdata[1107:1106] == 2'b11 ? sw_2_0_7_down0 :
bitdata[1107:1106] == 2'b10 ? cell_65_2 :
bitdata[1107:1106] == 2'b01 ? cell_66_1 :
bitdata[1107:1106] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1144:1142] == 3'b001 ? sw_2_1_4_down0 :
bitdata[1144:1142] == 3'b100 ? cell_78_3 :
bitdata[1144:1142] == 3'b010 ? cell_92_0 :
bitdata[1144:1142] == 3'b110 ? cell_93_0 :
bitdata[1144:1142] == 3'b0 ? 16'b0 : 16'bx);
assign cell_71_2 =
(bitdata[1109:1108] == 2'b11 ? sw_2_0_7_down0 :
bitdata[1109:1108] == 2'b10 ? cell_65_2 :
bitdata[1109:1108] == 2'b01 ? cell_66_1 :
bitdata[1109:1108] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1147:1145] == 3'b001 ? sw_2_1_4_down0 :
bitdata[1147:1145] == 3'b100 ? cell_78_3 :
bitdata[1147:1145] == 3'b010 ? cell_92_0 :
bitdata[1147:1145] == 3'b110 ? cell_93_0 :
bitdata[1147:1145] == 3'b0 ? 16'b0 : 16'bx);
assign cell_71_4 =
(bitdata[141:137] == 5'b10110 ? sw_0_0_8_down0 :
bitdata[141:137] == 5'b01110 ? sw_0_0_8_down1 :
bitdata[141:137] == 5'b11110 ? sw_0_0_8_down2 :
bitdata[141:137] == 5'b00001 ? sw_0_0_8_down3 :
bitdata[141:137] == 5'b10001 ? sw_0_0_8_down4 :
bitdata[141:137] == 5'b10000 ? cell_61_6 :
bitdata[141:137] == 5'b01000 ? cell_61_7 :
bitdata[141:137] == 5'b11000 ? cell_80_6 :
bitdata[141:137] == 5'b00100 ? cell_80_7 :
bitdata[141:137] == 5'b10100 ? cell_80_8 :
bitdata[141:137] == 5'b01100 ? cell_80_9 :
bitdata[141:137] == 5'b11100 ? cell_80_10 :
bitdata[141:137] == 5'b00010 ? cell_80_11 :
bitdata[141:137] == 5'b10010 ? cell_80_12 :
bitdata[141:137] == 5'b01010 ? cell_80_13 :
bitdata[141:137] == 5'b11010 ? cell_80_14 :
bitdata[141:137] == 5'b00110 ? cell_80_15 :
bitdata[141:137] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[825:822] == 4'b0110 ? sw_0_1_11_down0 :
bitdata[825:822] == 4'b1110 ? sw_0_1_11_down1 :
bitdata[825:822] == 4'b0001 ? sw_0_1_11_down2 :
bitdata[825:822] == 4'b1001 ? sw_0_1_11_down3 :
bitdata[825:822] == 4'b1000 ? cell_61_6 :
bitdata[825:822] == 4'b0100 ? cell_61_7 :
bitdata[825:822] == 4'b1100 ? cell_63_8 :
bitdata[825:822] == 4'b0010 ? cell_63_9 :
bitdata[825:822] == 4'b1010 ? cell_83_0 :
bitdata[825:822] == 4'b0 ? 1'b0 : 1'bx);
assign cell_72_0 =
(bitdata[218:217] == 2'b01 ? sw_0_0_12_down0 :
bitdata[218:217] == 2'b10 ? cell_8_0 :
bitdata[218:217] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[873:872] == 2'b10 ? sw_0_1_18_down0 :
bitdata[873:872] == 2'b01 ? sw_0_1_18_down1 :
bitdata[873:872] == 2'b11 ? sw_0_1_18_down2 :
bitdata[873:872] == 2'b0 ? 1'b0 : 1'bx);
assign cell_72_1 =
(bitdata[1079:1077] == 3'b001 ? sw_2_0_5_down0 :
bitdata[1079:1077] == 3'b100 ? cell_67_1 :
bitdata[1079:1077] == 3'b010 ? cell_77_2 :
bitdata[1079:1077] == 3'b110 ? cell_78_3 :
bitdata[1079:1077] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1181:1179] == 3'b001 ? sw_2_1_6_down0 :
bitdata[1181:1179] == 3'b100 ? cell_67_1 :
bitdata[1181:1179] == 3'b010 ? cell_68_1 :
bitdata[1181:1179] == 3'b110 ? cell_77_2 :
bitdata[1181:1179] == 3'b0 ? 16'b0 : 16'bx);
assign cell_72_2 =
(bitdata[1082:1080] == 3'b001 ? sw_2_0_5_down0 :
bitdata[1082:1080] == 3'b100 ? cell_67_1 :
bitdata[1082:1080] == 3'b010 ? cell_77_2 :
bitdata[1082:1080] == 3'b110 ? cell_78_3 :
bitdata[1082:1080] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1184:1182] == 3'b001 ? sw_2_1_6_down0 :
bitdata[1184:1182] == 3'b100 ? cell_67_1 :
bitdata[1184:1182] == 3'b010 ? cell_68_1 :
bitdata[1184:1182] == 3'b110 ? cell_77_2 :
bitdata[1184:1182] == 3'b0 ? 16'b0 : 16'bx);
assign cell_72_4 =
(bitdata[220:219] == 2'b01 ? sw_0_0_12_down0 :
bitdata[220:219] == 2'b10 ? cell_8_0 :
bitdata[220:219] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[875:874] == 2'b10 ? sw_0_1_18_down0 :
bitdata[875:874] == 2'b01 ? sw_0_1_18_down1 :
bitdata[875:874] == 2'b11 ? sw_0_1_18_down2 :
bitdata[875:874] == 2'b0 ? 1'b0 : 1'bx);
assign cell_73_0 =
(bitdata[930:928] == 3'b110 ? sw_1_0_3_down0 :
bitdata[930:928] == 3'b001 ? sw_1_0_3_down1 :
bitdata[930:928] == 3'b100 ? cell_87_0 :
bitdata[930:928] == 3'b010 ? cell_89_0 :
bitdata[930:928] == 3'b0 ? 8'b0 : 8'bx) |
(bitdata[1006:1004] == 3'b110 ? sw_1_1_5_down0 :
bitdata[1006:1004] == 3'b001 ? sw_1_1_5_down1 :
bitdata[1006:1004] == 3'b100 ? cell_75_3 :
bitdata[1006:1004] == 3'b010 ? cell_88_0 :
bitdata[1006:1004] == 3'b0 ? 8'b0 : 8'bx);
assign cell_73_1 =
(bitdata[933:931] == 3'b110 ? sw_1_0_3_down0 :
bitdata[933:931] == 3'b001 ? sw_1_0_3_down1 :
bitdata[933:931] == 3'b100 ? cell_87_0 :
bitdata[933:931] == 3'b010 ? cell_89_0 :
bitdata[933:931] == 3'b0 ? 8'b0 : 8'bx) |
(bitdata[1009:1007] == 3'b110 ? sw_1_1_5_down0 :
bitdata[1009:1007] == 3'b001 ? sw_1_1_5_down1 :
bitdata[1009:1007] == 3'b100 ? cell_75_3 :
bitdata[1009:1007] == 3'b010 ? cell_88_0 :
bitdata[1009:1007] == 3'b0 ? 8'b0 : 8'bx);
assign cell_73_2 =
(bitdata[936:934] == 3'b110 ? sw_1_0_3_down0 :
bitdata[936:934] == 3'b001 ? sw_1_0_3_down1 :
bitdata[936:934] == 3'b100 ? cell_87_0 :
bitdata[936:934] == 3'b010 ? cell_89_0 :
bitdata[936:934] == 3'b0 ? 8'b0 : 8'bx) |
(bitdata[1012:1010] == 3'b110 ? sw_1_1_5_down0 :
bitdata[1012:1010] == 3'b001 ? sw_1_1_5_down1 :
bitdata[1012:1010] == 3'b100 ? cell_75_3 :
bitdata[1012:1010] == 3'b010 ? cell_88_0 :
bitdata[1012:1010] == 3'b0 ? 8'b0 : 8'bx);
assign cell_73_3 =
(bitdata[939:937] == 3'b110 ? sw_1_0_3_down0 :
bitdata[939:937] == 3'b001 ? sw_1_0_3_down1 :
bitdata[939:937] == 3'b100 ? cell_87_0 :
bitdata[939:937] == 3'b010 ? cell_89_0 :
bitdata[939:937] == 3'b0 ? 8'b0 : 8'bx) |
(bitdata[1015:1013] == 3'b110 ? sw_1_1_5_down0 :
bitdata[1015:1013] == 3'b001 ? sw_1_1_5_down1 :
bitdata[1015:1013] == 3'b100 ? cell_75_3 :
bitdata[1015:1013] == 3'b010 ? cell_88_0 :
bitdata[1015:1013] == 3'b0 ? 8'b0 : 8'bx);
assign cell_73_4 =
(bitdata[327:323] == 5'b01001 ? sw_0_0_25_down0 :
bitdata[327:323] == 5'b11001 ? sw_0_0_25_down1 :
bitdata[327:323] == 5'b00101 ? sw_0_0_25_down2 :
bitdata[327:323] == 5'b10000 ? cell_63_8 :
bitdata[327:323] == 5'b01000 ? cell_63_9 :
bitdata[327:323] == 5'b11000 ? cell_81_10 :
bitdata[327:323] == 5'b00100 ? cell_81_11 :
bitdata[327:323] == 5'b10100 ? cell_81_12 :
bitdata[327:323] == 5'b01100 ? cell_81_13 :
bitdata[327:323] == 5'b11100 ? cell_81_14 :
bitdata[327:323] == 5'b00010 ? cell_81_15 :
bitdata[327:323] == 5'b10010 ? cell_81_16 :
bitdata[327:323] == 5'b01010 ? cell_81_17 :
bitdata[327:323] == 5'b11010 ? cell_81_18 :
bitdata[327:323] == 5'b00110 ? cell_81_19 :
bitdata[327:323] == 5'b10110 ? cell_81_20 :
bitdata[327:323] == 5'b01110 ? cell_81_21 :
bitdata[327:323] == 5'b11110 ? cell_81_22 :
bitdata[327:323] == 5'b00001 ? cell_81_23 :
bitdata[327:323] == 5'b10001 ? cell_81_24 :
bitdata[327:323] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[831:830] == 2'b10 ? sw_0_1_12_down0 :
bitdata[831:830] == 2'b01 ? sw_0_1_12_down1 :
bitdata[831:830] == 2'b0 ? 1'b0 : 1'bx);
assign cell_73_5 =
(bitdata[332:328] == 5'b01001 ? sw_0_0_25_down0 :
bitdata[332:328] == 5'b11001 ? sw_0_0_25_down1 :
bitdata[332:328] == 5'b00101 ? sw_0_0_25_down2 :
bitdata[332:328] == 5'b10000 ? cell_63_8 :
bitdata[332:328] == 5'b01000 ? cell_63_9 :
bitdata[332:328] == 5'b11000 ? cell_81_10 :
bitdata[332:328] == 5'b00100 ? cell_81_11 :
bitdata[332:328] == 5'b10100 ? cell_81_12 :
bitdata[332:328] == 5'b01100 ? cell_81_13 :
bitdata[332:328] == 5'b11100 ? cell_81_14 :
bitdata[332:328] == 5'b00010 ? cell_81_15 :
bitdata[332:328] == 5'b10010 ? cell_81_16 :
bitdata[332:328] == 5'b01010 ? cell_81_17 :
bitdata[332:328] == 5'b11010 ? cell_81_18 :
bitdata[332:328] == 5'b00110 ? cell_81_19 :
bitdata[332:328] == 5'b10110 ? cell_81_20 :
bitdata[332:328] == 5'b01110 ? cell_81_21 :
bitdata[332:328] == 5'b11110 ? cell_81_22 :
bitdata[332:328] == 5'b00001 ? cell_81_23 :
bitdata[332:328] == 5'b10001 ? cell_81_24 :
bitdata[332:328] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[833:832] == 2'b10 ? sw_0_1_12_down0 :
bitdata[833:832] == 2'b01 ? sw_0_1_12_down1 :
bitdata[833:832] == 2'b0 ? 1'b0 : 1'bx);
assign cell_73_6 =
(bitdata[337:333] == 5'b01001 ? sw_0_0_25_down0 :
bitdata[337:333] == 5'b11001 ? sw_0_0_25_down1 :
bitdata[337:333] == 5'b00101 ? sw_0_0_25_down2 :
bitdata[337:333] == 5'b10000 ? cell_63_8 :
bitdata[337:333] == 5'b01000 ? cell_63_9 :
bitdata[337:333] == 5'b11000 ? cell_81_10 :
bitdata[337:333] == 5'b00100 ? cell_81_11 :
bitdata[337:333] == 5'b10100 ? cell_81_12 :
bitdata[337:333] == 5'b01100 ? cell_81_13 :
bitdata[337:333] == 5'b11100 ? cell_81_14 :
bitdata[337:333] == 5'b00010 ? cell_81_15 :
bitdata[337:333] == 5'b10010 ? cell_81_16 :
bitdata[337:333] == 5'b01010 ? cell_81_17 :
bitdata[337:333] == 5'b11010 ? cell_81_18 :
bitdata[337:333] == 5'b00110 ? cell_81_19 :
bitdata[337:333] == 5'b10110 ? cell_81_20 :
bitdata[337:333] == 5'b01110 ? cell_81_21 :
bitdata[337:333] == 5'b11110 ? cell_81_22 :
bitdata[337:333] == 5'b00001 ? cell_81_23 :
bitdata[337:333] == 5'b10001 ? cell_81_24 :
bitdata[337:333] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[835:834] == 2'b10 ? sw_0_1_12_down0 :
bitdata[835:834] == 2'b01 ? sw_0_1_12_down1 :
bitdata[835:834] == 2'b0 ? 1'b0 : 1'bx);
assign cell_74_0 =
(bitdata[948:947] == 2'b11 ? sw_1_0_4_down0 :
bitdata[948:947] == 2'b10 ? cell_84_0 :
bitdata[948:947] == 2'b01 ? cell_85_0 :
bitdata[948:947] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[988:986] == 3'b001 ? sw_1_1_3_down0 :
bitdata[988:986] == 3'b100 ? cell_86_0 :
bitdata[988:986] == 3'b010 ? cell_87_0 :
bitdata[988:986] == 3'b110 ? cell_89_0 :
bitdata[988:986] == 3'b0 ? 8'b0 : 8'bx);
assign cell_74_1 =
(bitdata[950:949] == 2'b11 ? sw_1_0_4_down0 :
bitdata[950:949] == 2'b10 ? cell_84_0 :
bitdata[950:949] == 2'b01 ? cell_85_0 :
bitdata[950:949] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[991:989] == 3'b001 ? sw_1_1_3_down0 :
bitdata[991:989] == 3'b100 ? cell_86_0 :
bitdata[991:989] == 3'b010 ? cell_87_0 :
bitdata[991:989] == 3'b110 ? cell_89_0 :
bitdata[991:989] == 3'b0 ? 8'b0 : 8'bx);
assign cell_74_2 =
(bitdata[371:370] == 2'b01 ? sw_0_0_26_down0 :
bitdata[371:370] == 2'b11 ? sw_0_0_26_down1 :
bitdata[371:370] == 2'b10 ? cell_6_0 :
bitdata[371:370] == 2'b0 ? 1'b0 : 1'bx) |
(bitdata[837:836] == 2'b10 ? sw_0_1_12_down0 :
bitdata[837:836] == 2'b01 ? sw_0_1_12_down1 :
bitdata[837:836] == 2'b0 ? 1'b0 : 1'bx);
assign cell_75_0 =
(bitdata[955:954] == 2'b01 ? sw_1_0_5_down0 :
bitdata[955:954] == 2'b10 ? cell_86_0 :
bitdata[955:954] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[1018:1016] == 3'b110 ? sw_1_1_5_down0 :
bitdata[1018:1016] == 3'b001 ? sw_1_1_5_down1 :
bitdata[1018:1016] == 3'b100 ? cell_73_7 :
bitdata[1018:1016] == 3'b010 ? cell_88_0 :
bitdata[1018:1016] == 3'b0 ? 8'b0 : 8'bx);
assign cell_75_1 =
(bitdata[957:956] == 2'b01 ? sw_1_0_5_down0 :
bitdata[957:956] == 2'b10 ? cell_86_0 :
bitdata[957:956] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[1021:1019] == 3'b110 ? sw_1_1_5_down0 :
bitdata[1021:1019] == 3'b001 ? sw_1_1_5_down1 :
bitdata[1021:1019] == 3'b100 ? cell_73_7 :
bitdata[1021:1019] == 3'b010 ? cell_88_0 :
bitdata[1021:1019] == 3'b0 ? 8'b0 : 8'bx);
assign cell_75_2 =
(bitdata[223:221] == 3'b011 ? sw_0_0_12_down0 :
bitdata[223:221] == 3'b100 ? cell_8_0 :
bitdata[223:221] == 3'b010 ? cell_72_5 :
bitdata[223:221] == 3'b110 ? cell_72_6 :
bitdata[223:221] == 3'b001 ? cell_72_7 :
bitdata[223:221] == 3'b101 ? cell_72_8 :
bitdata[223:221] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[724:722] == 3'b010 ? sw_0_1_9_down0 :
bitdata[724:722] == 3'b110 ? sw_0_1_9_down1 :
bitdata[724:722] == 3'b001 ? sw_0_1_9_down2 :
bitdata[724:722] == 3'b100 ? cell_43_0 :
bitdata[724:722] == 3'b0 ? 1'b0 : 1'bx);
assign cell_76_0 =
(bitdata[964:963] == 2'b11 ? sw_1_0_6_down0 :
bitdata[964:963] == 2'b10 ? cell_69_1 :
bitdata[964:963] == 2'b01 ? cell_70_1 :
bitdata[964:963] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[995:994] == 2'b11 ? sw_1_1_4_down0 :
bitdata[995:994] == 2'b10 ? cell_84_0 :
bitdata[995:994] == 2'b01 ? cell_85_0 :
bitdata[995:994] == 2'b0 ? 8'b0 : 8'bx);
assign cell_76_1 =
(bitdata[966:965] == 2'b11 ? sw_1_0_6_down0 :
bitdata[966:965] == 2'b10 ? cell_69_1 :
bitdata[966:965] == 2'b01 ? cell_70_1 :
bitdata[966:965] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[997:996] == 2'b11 ? sw_1_1_4_down0 :
bitdata[997:996] == 2'b10 ? cell_84_0 :
bitdata[997:996] == 2'b01 ? cell_85_0 :
bitdata[997:996] == 2'b0 ? 8'b0 : 8'bx);
assign cell_77_0 =
(bitdata[968:967] == 2'b11 ? sw_1_0_6_down0 :
bitdata[968:967] == 2'b10 ? cell_69_1 :
bitdata[968:967] == 2'b01 ? cell_70_1 :
bitdata[968:967] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[999:998] == 2'b11 ? sw_1_1_4_down0 :
bitdata[999:998] == 2'b10 ? cell_84_0 :
bitdata[999:998] == 2'b01 ? cell_85_0 :
bitdata[999:998] == 2'b0 ? 8'b0 : 8'bx);
assign cell_77_1 =
(bitdata[970:969] == 2'b11 ? sw_1_0_6_down0 :
bitdata[970:969] == 2'b10 ? cell_69_1 :
bitdata[970:969] == 2'b01 ? cell_70_1 :
bitdata[970:969] == 2'b0 ? 8'b0 : 8'bx) |
(bitdata[1001:1000] == 2'b11 ? sw_1_1_4_down0 :
bitdata[1001:1000] == 2'b10 ? cell_84_0 :
bitdata[1001:1000] == 2'b01 ? cell_85_0 :
bitdata[1001:1000] == 2'b0 ? 8'b0 : 8'bx);
assign cell_78_0 =
(bitdata[1085:1083] == 3'b001 ? sw_2_0_5_down0 :
bitdata[1085:1083] == 3'b100 ? cell_67_1 :
bitdata[1085:1083] == 3'b010 ? cell_72_3 :
bitdata[1085:1083] == 3'b110 ? cell_77_2 :
bitdata[1085:1083] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1150:1148] == 3'b001 ? sw_2_1_4_down0 :
bitdata[1150:1148] == 3'b100 ? cell_71_3 :
bitdata[1150:1148] == 3'b010 ? cell_92_0 :
bitdata[1150:1148] == 3'b110 ? cell_93_0 :
bitdata[1150:1148] == 3'b0 ? 16'b0 : 16'bx);
assign cell_78_1 =
(bitdata[1088:1086] == 3'b001 ? sw_2_0_5_down0 :
bitdata[1088:1086] == 3'b100 ? cell_67_1 :
bitdata[1088:1086] == 3'b010 ? cell_72_3 :
bitdata[1088:1086] == 3'b110 ? cell_77_2 :
bitdata[1088:1086] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1153:1151] == 3'b001 ? sw_2_1_4_down0 :
bitdata[1153:1151] == 3'b100 ? cell_71_3 :
bitdata[1153:1151] == 3'b010 ? cell_92_0 :
bitdata[1153:1151] == 3'b110 ? cell_93_0 :
bitdata[1153:1151] == 3'b0 ? 16'b0 : 16'bx);
assign cell_78_2 =
(bitdata[242:242] == 1'b1 ? sw_0_0_17_down0 :
bitdata[242:242] == 1'b0 ? 1'b0 : 1'bx) |
(bitdata[857:855] == 3'b010 ? sw_0_1_17_down0 :
bitdata[857:855] == 3'b110 ? sw_0_1_17_down1 :
bitdata[857:855] == 3'b001 ? sw_0_1_17_down2 :
bitdata[857:855] == 3'b100 ? cell_39_0 :
bitdata[857:855] == 3'b0 ? 1'b0 : 1'bx);
assign cell_79_0 =
(bitdata[1066:1065] == 2'b11 ? sw_2_0_4_down0 :
bitdata[1066:1065] == 2'b10 ? cell_61_5 :
bitdata[1066:1065] == 2'b01 ? cell_91_0 :
bitdata[1066:1065] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1165:1163] == 3'b101 ? sw_2_1_5_down0 :
bitdata[1165:1163] == 3'b100 ? cell_63_6 :
bitdata[1165:1163] == 3'b010 ? cell_63_7 :
bitdata[1165:1163] == 3'b110 ? cell_90_0 :
bitdata[1165:1163] == 3'b001 ? cell_91_0 :
bitdata[1165:1163] == 3'b0 ? 16'b0 : 16'bx);
assign cell_79_1 =
(bitdata[1068:1067] == 2'b11 ? sw_2_0_4_down0 :
bitdata[1068:1067] == 2'b10 ? cell_61_5 :
bitdata[1068:1067] == 2'b01 ? cell_91_0 :
bitdata[1068:1067] == 2'b0 ? 16'b0 : 16'bx) |
(bitdata[1168:1166] == 3'b101 ? sw_2_1_5_down0 :
bitdata[1168:1166] == 3'b100 ? cell_63_6 :
bitdata[1168:1166] == 3'b010 ? cell_63_7 :
bitdata[1168:1166] == 3'b110 ? cell_90_0 :
bitdata[1168:1166] == 3'b001 ? cell_91_0 :
bitdata[1168:1166] == 3'b0 ? 16'b0 : 16'bx);
assign cell_79_2 =
(bitdata[238:236] == 3'b001 ? sw_0_0_16_down0 :
bitdata[238:236] == 3'b100 ? cell_46_0 :
bitdata[238:236] == 3'b010 ? cell_47_0 :
bitdata[238:236] == 3'b110 ? cell_48_0 :
bitdata[238:236] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[860:858] == 3'b010 ? sw_0_1_17_down0 :
bitdata[860:858] == 3'b110 ? sw_0_1_17_down1 :
bitdata[860:858] == 3'b001 ? sw_0_1_17_down2 :
bitdata[860:858] == 3'b100 ? cell_39_0 :
bitdata[860:858] == 3'b0 ? 1'b0 : 1'bx);
assign cell_80_0 =
(bitdata[145:142] == 4'b1110 ? sw_0_0_8_down0 :
bitdata[145:142] == 4'b0001 ? sw_0_0_8_down1 :
bitdata[145:142] == 4'b1001 ? sw_0_0_8_down2 :
bitdata[145:142] == 4'b0101 ? sw_0_0_8_down3 :
bitdata[145:142] == 4'b1101 ? sw_0_0_8_down4 :
bitdata[145:142] == 4'b1000 ? cell_61_6 :
bitdata[145:142] == 4'b0100 ? cell_61_7 :
bitdata[145:142] == 4'b1100 ? cell_71_5 :
bitdata[145:142] == 4'b0010 ? cell_71_6 :
bitdata[145:142] == 4'b1010 ? cell_71_7 :
bitdata[145:142] == 4'b0110 ? cell_71_8 :
bitdata[145:142] == 4'b0 ? 1'b0 : 1'bx) |
(bitdata[640:636] == 5'b00001 ? sw_0_1_8_down0 :
bitdata[640:636] == 5'b10001 ? sw_0_1_8_down1 :
bitdata[640:636] == 5'b01001 ? sw_0_1_8_down2 :
bitdata[640:636] == 5'b11001 ? sw_0_1_8_down3 :
bitdata[640:636] == 5'b00101 ? sw_0_1_8_down4 :
bitdata[640:636] == 5'b10101 ? sw_0_1_8_down5 :
bitdata[640:636] == 5'b10000 ? cell_81_10 :
bitdata[640:636] == 5'b01000 ? cell_81_11 :
bitdata[640:636] == 5'b11000 ? cell_81_12 :
bitdata[640:636] == 5'b00100 ? cell_81_13 :
bitdata[640:636] == 5'b10100 ? cell_81_14 :
bitdata[640:636] == 5'b01100 ? cell_81_15 :
bitdata[640:636] == 5'b11100 ? cell_81_16 :
bitdata[640:636] == 5'b00010 ? cell_81_17 :
bitdata[640:636] == 5'b10010 ? cell_81_18 :
bitdata[640:636] == 5'b01010 ? cell_81_19 :
bitdata[640:636] == 5'b11010 ? cell_81_20 :
bitdata[640:636] == 5'b00110 ? cell_81_21 :
bitdata[640:636] == 5'b10110 ? cell_81_22 :
bitdata[640:636] == 5'b01110 ? cell_81_23 :
bitdata[640:636] == 5'b11110 ? cell_81_24 :
bitdata[640:636] == 5'b0 ? 1'b0 : 1'bx);
assign cell_80_1 =
(bitdata[149:146] == 4'b1110 ? sw_0_0_8_down0 :
bitdata[149:146] == 4'b0001 ? sw_0_0_8_down1 :
bitdata[149:146] == 4'b1001 ? sw_0_0_8_down2 :
bitdata[149:146] == 4'b0101 ? sw_0_0_8_down3 :
bitdata[149:146] == 4'b1101 ? sw_0_0_8_down4 :
bitdata[149:146] == 4'b1000 ? cell_61_6 :
bitdata[149:146] == 4'b0100 ? cell_61_7 :
bitdata[149:146] == 4'b1100 ? cell_71_5 :
bitdata[149:146] == 4'b0010 ? cell_71_6 :
bitdata[149:146] == 4'b1010 ? cell_71_7 :
bitdata[149:146] == 4'b0110 ? cell_71_8 :
bitdata[149:146] == 4'b0 ? 1'b0 : 1'bx) |
(bitdata[645:641] == 5'b00001 ? sw_0_1_8_down0 :
bitdata[645:641] == 5'b10001 ? sw_0_1_8_down1 :
bitdata[645:641] == 5'b01001 ? sw_0_1_8_down2 :
bitdata[645:641] == 5'b11001 ? sw_0_1_8_down3 :
bitdata[645:641] == 5'b00101 ? sw_0_1_8_down4 :
bitdata[645:641] == 5'b10101 ? sw_0_1_8_down5 :
bitdata[645:641] == 5'b10000 ? cell_81_10 :
bitdata[645:641] == 5'b01000 ? cell_81_11 :
bitdata[645:641] == 5'b11000 ? cell_81_12 :
bitdata[645:641] == 5'b00100 ? cell_81_13 :
bitdata[645:641] == 5'b10100 ? cell_81_14 :
bitdata[645:641] == 5'b01100 ? cell_81_15 :
bitdata[645:641] == 5'b11100 ? cell_81_16 :
bitdata[645:641] == 5'b00010 ? cell_81_17 :
bitdata[645:641] == 5'b10010 ? cell_81_18 :
bitdata[645:641] == 5'b01010 ? cell_81_19 :
bitdata[645:641] == 5'b11010 ? cell_81_20 :
bitdata[645:641] == 5'b00110 ? cell_81_21 :
bitdata[645:641] == 5'b10110 ? cell_81_22 :
bitdata[645:641] == 5'b01110 ? cell_81_23 :
bitdata[645:641] == 5'b11110 ? cell_81_24 :
bitdata[645:641] == 5'b0 ? 1'b0 : 1'bx);
assign cell_80_2 =
(bitdata[153:150] == 4'b1110 ? sw_0_0_8_down0 :
bitdata[153:150] == 4'b0001 ? sw_0_0_8_down1 :
bitdata[153:150] == 4'b1001 ? sw_0_0_8_down2 :
bitdata[153:150] == 4'b0101 ? sw_0_0_8_down3 :
bitdata[153:150] == 4'b1101 ? sw_0_0_8_down4 :
bitdata[153:150] == 4'b1000 ? cell_61_6 :
bitdata[153:150] == 4'b0100 ? cell_61_7 :
bitdata[153:150] == 4'b1100 ? cell_71_5 :
bitdata[153:150] == 4'b0010 ? cell_71_6 :
bitdata[153:150] == 4'b1010 ? cell_71_7 :
bitdata[153:150] == 4'b0110 ? cell_71_8 :
bitdata[153:150] == 4'b0 ? 1'b0 : 1'bx) |
(bitdata[650:646] == 5'b00001 ? sw_0_1_8_down0 :
bitdata[650:646] == 5'b10001 ? sw_0_1_8_down1 :
bitdata[650:646] == 5'b01001 ? sw_0_1_8_down2 :
bitdata[650:646] == 5'b11001 ? sw_0_1_8_down3 :
bitdata[650:646] == 5'b00101 ? sw_0_1_8_down4 :
bitdata[650:646] == 5'b10101 ? sw_0_1_8_down5 :
bitdata[650:646] == 5'b10000 ? cell_81_10 :
bitdata[650:646] == 5'b01000 ? cell_81_11 :
bitdata[650:646] == 5'b11000 ? cell_81_12 :
bitdata[650:646] == 5'b00100 ? cell_81_13 :
bitdata[650:646] == 5'b10100 ? cell_81_14 :
bitdata[650:646] == 5'b01100 ? cell_81_15 :
bitdata[650:646] == 5'b11100 ? cell_81_16 :
bitdata[650:646] == 5'b00010 ? cell_81_17 :
bitdata[650:646] == 5'b10010 ? cell_81_18 :
bitdata[650:646] == 5'b01010 ? cell_81_19 :
bitdata[650:646] == 5'b11010 ? cell_81_20 :
bitdata[650:646] == 5'b00110 ? cell_81_21 :
bitdata[650:646] == 5'b10110 ? cell_81_22 :
bitdata[650:646] == 5'b01110 ? cell_81_23 :
bitdata[650:646] == 5'b11110 ? cell_81_24 :
bitdata[650:646] == 5'b0 ? 1'b0 : 1'bx);
assign cell_80_3 =
(bitdata[157:154] == 4'b1110 ? sw_0_0_8_down0 :
bitdata[157:154] == 4'b0001 ? sw_0_0_8_down1 :
bitdata[157:154] == 4'b1001 ? sw_0_0_8_down2 :
bitdata[157:154] == 4'b0101 ? sw_0_0_8_down3 :
bitdata[157:154] == 4'b1101 ? sw_0_0_8_down4 :
bitdata[157:154] == 4'b1000 ? cell_61_6 :
bitdata[157:154] == 4'b0100 ? cell_61_7 :
bitdata[157:154] == 4'b1100 ? cell_71_5 :
bitdata[157:154] == 4'b0010 ? cell_71_6 :
bitdata[157:154] == 4'b1010 ? cell_71_7 :
bitdata[157:154] == 4'b0110 ? cell_71_8 :
bitdata[157:154] == 4'b0 ? 1'b0 : 1'bx) |
(bitdata[655:651] == 5'b00001 ? sw_0_1_8_down0 :
bitdata[655:651] == 5'b10001 ? sw_0_1_8_down1 :
bitdata[655:651] == 5'b01001 ? sw_0_1_8_down2 :
bitdata[655:651] == 5'b11001 ? sw_0_1_8_down3 :
bitdata[655:651] == 5'b00101 ? sw_0_1_8_down4 :
bitdata[655:651] == 5'b10101 ? sw_0_1_8_down5 :
bitdata[655:651] == 5'b10000 ? cell_81_10 :
bitdata[655:651] == 5'b01000 ? cell_81_11 :
bitdata[655:651] == 5'b11000 ? cell_81_12 :
bitdata[655:651] == 5'b00100 ? cell_81_13 :
bitdata[655:651] == 5'b10100 ? cell_81_14 :
bitdata[655:651] == 5'b01100 ? cell_81_15 :
bitdata[655:651] == 5'b11100 ? cell_81_16 :
bitdata[655:651] == 5'b00010 ? cell_81_17 :
bitdata[655:651] == 5'b10010 ? cell_81_18 :
bitdata[655:651] == 5'b01010 ? cell_81_19 :
bitdata[655:651] == 5'b11010 ? cell_81_20 :
bitdata[655:651] == 5'b00110 ? cell_81_21 :
bitdata[655:651] == 5'b10110 ? cell_81_22 :
bitdata[655:651] == 5'b01110 ? cell_81_23 :
bitdata[655:651] == 5'b11110 ? cell_81_24 :
bitdata[655:651] == 5'b0 ? 1'b0 : 1'bx);
assign cell_80_4 =
(bitdata[161:158] == 4'b1110 ? sw_0_0_8_down0 :
bitdata[161:158] == 4'b0001 ? sw_0_0_8_down1 :
bitdata[161:158] == 4'b1001 ? sw_0_0_8_down2 :
bitdata[161:158] == 4'b0101 ? sw_0_0_8_down3 :
bitdata[161:158] == 4'b1101 ? sw_0_0_8_down4 :
bitdata[161:158] == 4'b1000 ? cell_61_6 :
bitdata[161:158] == 4'b0100 ? cell_61_7 :
bitdata[161:158] == 4'b1100 ? cell_71_5 :
bitdata[161:158] == 4'b0010 ? cell_71_6 :
bitdata[161:158] == 4'b1010 ? cell_71_7 :
bitdata[161:158] == 4'b0110 ? cell_71_8 :
bitdata[161:158] == 4'b0 ? 1'b0 : 1'bx) |
(bitdata[660:656] == 5'b00001 ? sw_0_1_8_down0 :
bitdata[660:656] == 5'b10001 ? sw_0_1_8_down1 :
bitdata[660:656] == 5'b01001 ? sw_0_1_8_down2 :
bitdata[660:656] == 5'b11001 ? sw_0_1_8_down3 :
bitdata[660:656] == 5'b00101 ? sw_0_1_8_down4 :
bitdata[660:656] == 5'b10101 ? sw_0_1_8_down5 :
bitdata[660:656] == 5'b10000 ? cell_81_10 :
bitdata[660:656] == 5'b01000 ? cell_81_11 :
bitdata[660:656] == 5'b11000 ? cell_81_12 :
bitdata[660:656] == 5'b00100 ? cell_81_13 :
bitdata[660:656] == 5'b10100 ? cell_81_14 :
bitdata[660:656] == 5'b01100 ? cell_81_15 :
bitdata[660:656] == 5'b11100 ? cell_81_16 :
bitdata[660:656] == 5'b00010 ? cell_81_17 :
bitdata[660:656] == 5'b10010 ? cell_81_18 :
bitdata[660:656] == 5'b01010 ? cell_81_19 :
bitdata[660:656] == 5'b11010 ? cell_81_20 :
bitdata[660:656] == 5'b00110 ? cell_81_21 :
bitdata[660:656] == 5'b10110 ? cell_81_22 :
bitdata[660:656] == 5'b01110 ? cell_81_23 :
bitdata[660:656] == 5'b11110 ? cell_81_24 :
bitdata[660:656] == 5'b0 ? 1'b0 : 1'bx);
assign cell_80_5 =
(bitdata[165:162] == 4'b1110 ? sw_0_0_8_down0 :
bitdata[165:162] == 4'b0001 ? sw_0_0_8_down1 :
bitdata[165:162] == 4'b1001 ? sw_0_0_8_down2 :
bitdata[165:162] == 4'b0101 ? sw_0_0_8_down3 :
bitdata[165:162] == 4'b1101 ? sw_0_0_8_down4 :
bitdata[165:162] == 4'b1000 ? cell_61_6 :
bitdata[165:162] == 4'b0100 ? cell_61_7 :
bitdata[165:162] == 4'b1100 ? cell_71_5 :
bitdata[165:162] == 4'b0010 ? cell_71_6 :
bitdata[165:162] == 4'b1010 ? cell_71_7 :
bitdata[165:162] == 4'b0110 ? cell_71_8 :
bitdata[165:162] == 4'b0 ? 1'b0 : 1'bx) |
(bitdata[665:661] == 5'b00001 ? sw_0_1_8_down0 :
bitdata[665:661] == 5'b10001 ? sw_0_1_8_down1 :
bitdata[665:661] == 5'b01001 ? sw_0_1_8_down2 :
bitdata[665:661] == 5'b11001 ? sw_0_1_8_down3 :
bitdata[665:661] == 5'b00101 ? sw_0_1_8_down4 :
bitdata[665:661] == 5'b10101 ? sw_0_1_8_down5 :
bitdata[665:661] == 5'b10000 ? cell_81_10 :
bitdata[665:661] == 5'b01000 ? cell_81_11 :
bitdata[665:661] == 5'b11000 ? cell_81_12 :
bitdata[665:661] == 5'b00100 ? cell_81_13 :
bitdata[665:661] == 5'b10100 ? cell_81_14 :
bitdata[665:661] == 5'b01100 ? cell_81_15 :
bitdata[665:661] == 5'b11100 ? cell_81_16 :
bitdata[665:661] == 5'b00010 ? cell_81_17 :
bitdata[665:661] == 5'b10010 ? cell_81_18 :
bitdata[665:661] == 5'b01010 ? cell_81_19 :
bitdata[665:661] == 5'b11010 ? cell_81_20 :
bitdata[665:661] == 5'b00110 ? cell_81_21 :
bitdata[665:661] == 5'b10110 ? cell_81_22 :
bitdata[665:661] == 5'b01110 ? cell_81_23 :
bitdata[665:661] == 5'b11110 ? cell_81_24 :
bitdata[665:661] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_0 =
(bitdata[340:338] == 3'b110 ? sw_0_0_25_down0 :
bitdata[340:338] == 3'b001 ? sw_0_0_25_down1 :
bitdata[340:338] == 3'b101 ? sw_0_0_25_down2 :
bitdata[340:338] == 3'b100 ? cell_63_8 :
bitdata[340:338] == 3'b010 ? cell_63_9 :
bitdata[340:338] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[670:666] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[670:666] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[670:666] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[670:666] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[670:666] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[670:666] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[670:666] == 5'b10000 ? cell_80_6 :
bitdata[670:666] == 5'b01000 ? cell_80_7 :
bitdata[670:666] == 5'b11000 ? cell_80_8 :
bitdata[670:666] == 5'b00100 ? cell_80_9 :
bitdata[670:666] == 5'b10100 ? cell_80_10 :
bitdata[670:666] == 5'b01100 ? cell_80_11 :
bitdata[670:666] == 5'b11100 ? cell_80_12 :
bitdata[670:666] == 5'b00010 ? cell_80_13 :
bitdata[670:666] == 5'b10010 ? cell_80_14 :
bitdata[670:666] == 5'b01010 ? cell_80_15 :
bitdata[670:666] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_1 =
(bitdata[343:341] == 3'b110 ? sw_0_0_25_down0 :
bitdata[343:341] == 3'b001 ? sw_0_0_25_down1 :
bitdata[343:341] == 3'b101 ? sw_0_0_25_down2 :
bitdata[343:341] == 3'b100 ? cell_63_8 :
bitdata[343:341] == 3'b010 ? cell_63_9 :
bitdata[343:341] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[675:671] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[675:671] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[675:671] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[675:671] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[675:671] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[675:671] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[675:671] == 5'b10000 ? cell_80_6 :
bitdata[675:671] == 5'b01000 ? cell_80_7 :
bitdata[675:671] == 5'b11000 ? cell_80_8 :
bitdata[675:671] == 5'b00100 ? cell_80_9 :
bitdata[675:671] == 5'b10100 ? cell_80_10 :
bitdata[675:671] == 5'b01100 ? cell_80_11 :
bitdata[675:671] == 5'b11100 ? cell_80_12 :
bitdata[675:671] == 5'b00010 ? cell_80_13 :
bitdata[675:671] == 5'b10010 ? cell_80_14 :
bitdata[675:671] == 5'b01010 ? cell_80_15 :
bitdata[675:671] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_2 =
(bitdata[346:344] == 3'b110 ? sw_0_0_25_down0 :
bitdata[346:344] == 3'b001 ? sw_0_0_25_down1 :
bitdata[346:344] == 3'b101 ? sw_0_0_25_down2 :
bitdata[346:344] == 3'b100 ? cell_63_8 :
bitdata[346:344] == 3'b010 ? cell_63_9 :
bitdata[346:344] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[680:676] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[680:676] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[680:676] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[680:676] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[680:676] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[680:676] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[680:676] == 5'b10000 ? cell_80_6 :
bitdata[680:676] == 5'b01000 ? cell_80_7 :
bitdata[680:676] == 5'b11000 ? cell_80_8 :
bitdata[680:676] == 5'b00100 ? cell_80_9 :
bitdata[680:676] == 5'b10100 ? cell_80_10 :
bitdata[680:676] == 5'b01100 ? cell_80_11 :
bitdata[680:676] == 5'b11100 ? cell_80_12 :
bitdata[680:676] == 5'b00010 ? cell_80_13 :
bitdata[680:676] == 5'b10010 ? cell_80_14 :
bitdata[680:676] == 5'b01010 ? cell_80_15 :
bitdata[680:676] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_3 =
(bitdata[349:347] == 3'b110 ? sw_0_0_25_down0 :
bitdata[349:347] == 3'b001 ? sw_0_0_25_down1 :
bitdata[349:347] == 3'b101 ? sw_0_0_25_down2 :
bitdata[349:347] == 3'b100 ? cell_63_8 :
bitdata[349:347] == 3'b010 ? cell_63_9 :
bitdata[349:347] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[685:681] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[685:681] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[685:681] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[685:681] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[685:681] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[685:681] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[685:681] == 5'b10000 ? cell_80_6 :
bitdata[685:681] == 5'b01000 ? cell_80_7 :
bitdata[685:681] == 5'b11000 ? cell_80_8 :
bitdata[685:681] == 5'b00100 ? cell_80_9 :
bitdata[685:681] == 5'b10100 ? cell_80_10 :
bitdata[685:681] == 5'b01100 ? cell_80_11 :
bitdata[685:681] == 5'b11100 ? cell_80_12 :
bitdata[685:681] == 5'b00010 ? cell_80_13 :
bitdata[685:681] == 5'b10010 ? cell_80_14 :
bitdata[685:681] == 5'b01010 ? cell_80_15 :
bitdata[685:681] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_4 =
(bitdata[352:350] == 3'b110 ? sw_0_0_25_down0 :
bitdata[352:350] == 3'b001 ? sw_0_0_25_down1 :
bitdata[352:350] == 3'b101 ? sw_0_0_25_down2 :
bitdata[352:350] == 3'b100 ? cell_63_8 :
bitdata[352:350] == 3'b010 ? cell_63_9 :
bitdata[352:350] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[690:686] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[690:686] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[690:686] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[690:686] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[690:686] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[690:686] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[690:686] == 5'b10000 ? cell_80_6 :
bitdata[690:686] == 5'b01000 ? cell_80_7 :
bitdata[690:686] == 5'b11000 ? cell_80_8 :
bitdata[690:686] == 5'b00100 ? cell_80_9 :
bitdata[690:686] == 5'b10100 ? cell_80_10 :
bitdata[690:686] == 5'b01100 ? cell_80_11 :
bitdata[690:686] == 5'b11100 ? cell_80_12 :
bitdata[690:686] == 5'b00010 ? cell_80_13 :
bitdata[690:686] == 5'b10010 ? cell_80_14 :
bitdata[690:686] == 5'b01010 ? cell_80_15 :
bitdata[690:686] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_5 =
(bitdata[355:353] == 3'b110 ? sw_0_0_25_down0 :
bitdata[355:353] == 3'b001 ? sw_0_0_25_down1 :
bitdata[355:353] == 3'b101 ? sw_0_0_25_down2 :
bitdata[355:353] == 3'b100 ? cell_63_8 :
bitdata[355:353] == 3'b010 ? cell_63_9 :
bitdata[355:353] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[695:691] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[695:691] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[695:691] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[695:691] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[695:691] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[695:691] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[695:691] == 5'b10000 ? cell_80_6 :
bitdata[695:691] == 5'b01000 ? cell_80_7 :
bitdata[695:691] == 5'b11000 ? cell_80_8 :
bitdata[695:691] == 5'b00100 ? cell_80_9 :
bitdata[695:691] == 5'b10100 ? cell_80_10 :
bitdata[695:691] == 5'b01100 ? cell_80_11 :
bitdata[695:691] == 5'b11100 ? cell_80_12 :
bitdata[695:691] == 5'b00010 ? cell_80_13 :
bitdata[695:691] == 5'b10010 ? cell_80_14 :
bitdata[695:691] == 5'b01010 ? cell_80_15 :
bitdata[695:691] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_6 =
(bitdata[358:356] == 3'b110 ? sw_0_0_25_down0 :
bitdata[358:356] == 3'b001 ? sw_0_0_25_down1 :
bitdata[358:356] == 3'b101 ? sw_0_0_25_down2 :
bitdata[358:356] == 3'b100 ? cell_63_8 :
bitdata[358:356] == 3'b010 ? cell_63_9 :
bitdata[358:356] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[700:696] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[700:696] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[700:696] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[700:696] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[700:696] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[700:696] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[700:696] == 5'b10000 ? cell_80_6 :
bitdata[700:696] == 5'b01000 ? cell_80_7 :
bitdata[700:696] == 5'b11000 ? cell_80_8 :
bitdata[700:696] == 5'b00100 ? cell_80_9 :
bitdata[700:696] == 5'b10100 ? cell_80_10 :
bitdata[700:696] == 5'b01100 ? cell_80_11 :
bitdata[700:696] == 5'b11100 ? cell_80_12 :
bitdata[700:696] == 5'b00010 ? cell_80_13 :
bitdata[700:696] == 5'b10010 ? cell_80_14 :
bitdata[700:696] == 5'b01010 ? cell_80_15 :
bitdata[700:696] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_7 =
(bitdata[361:359] == 3'b110 ? sw_0_0_25_down0 :
bitdata[361:359] == 3'b001 ? sw_0_0_25_down1 :
bitdata[361:359] == 3'b101 ? sw_0_0_25_down2 :
bitdata[361:359] == 3'b100 ? cell_63_8 :
bitdata[361:359] == 3'b010 ? cell_63_9 :
bitdata[361:359] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[705:701] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[705:701] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[705:701] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[705:701] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[705:701] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[705:701] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[705:701] == 5'b10000 ? cell_80_6 :
bitdata[705:701] == 5'b01000 ? cell_80_7 :
bitdata[705:701] == 5'b11000 ? cell_80_8 :
bitdata[705:701] == 5'b00100 ? cell_80_9 :
bitdata[705:701] == 5'b10100 ? cell_80_10 :
bitdata[705:701] == 5'b01100 ? cell_80_11 :
bitdata[705:701] == 5'b11100 ? cell_80_12 :
bitdata[705:701] == 5'b00010 ? cell_80_13 :
bitdata[705:701] == 5'b10010 ? cell_80_14 :
bitdata[705:701] == 5'b01010 ? cell_80_15 :
bitdata[705:701] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_8 =
(bitdata[364:362] == 3'b110 ? sw_0_0_25_down0 :
bitdata[364:362] == 3'b001 ? sw_0_0_25_down1 :
bitdata[364:362] == 3'b101 ? sw_0_0_25_down2 :
bitdata[364:362] == 3'b100 ? cell_63_8 :
bitdata[364:362] == 3'b010 ? cell_63_9 :
bitdata[364:362] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[710:706] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[710:706] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[710:706] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[710:706] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[710:706] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[710:706] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[710:706] == 5'b10000 ? cell_80_6 :
bitdata[710:706] == 5'b01000 ? cell_80_7 :
bitdata[710:706] == 5'b11000 ? cell_80_8 :
bitdata[710:706] == 5'b00100 ? cell_80_9 :
bitdata[710:706] == 5'b10100 ? cell_80_10 :
bitdata[710:706] == 5'b01100 ? cell_80_11 :
bitdata[710:706] == 5'b11100 ? cell_80_12 :
bitdata[710:706] == 5'b00010 ? cell_80_13 :
bitdata[710:706] == 5'b10010 ? cell_80_14 :
bitdata[710:706] == 5'b01010 ? cell_80_15 :
bitdata[710:706] == 5'b0 ? 1'b0 : 1'bx);
assign cell_81_9 =
(bitdata[367:365] == 3'b110 ? sw_0_0_25_down0 :
bitdata[367:365] == 3'b001 ? sw_0_0_25_down1 :
bitdata[367:365] == 3'b101 ? sw_0_0_25_down2 :
bitdata[367:365] == 3'b100 ? cell_63_8 :
bitdata[367:365] == 3'b010 ? cell_63_9 :
bitdata[367:365] == 3'b0 ? 1'b0 : 1'bx) |
(bitdata[715:711] == 5'b11010 ? sw_0_1_8_down0 :
bitdata[715:711] == 5'b00110 ? sw_0_1_8_down1 :
bitdata[715:711] == 5'b10110 ? sw_0_1_8_down2 :
bitdata[715:711] == 5'b01110 ? sw_0_1_8_down3 :
bitdata[715:711] == 5'b11110 ? sw_0_1_8_down4 :
bitdata[715:711] == 5'b00001 ? sw_0_1_8_down5 :
bitdata[715:711] == 5'b10000 ? cell_80_6 :
bitdata[715:711] == 5'b01000 ? cell_80_7 :
bitdata[715:711] == 5'b11000 ? cell_80_8 :
bitdata[715:711] == 5'b00100 ? cell_80_9 :
bitdata[715:711] == 5'b10100 ? cell_80_10 :
bitdata[715:711] == 5'b01100 ? cell_80_11 :
bitdata[715:711] == 5'b11100 ? cell_80_12 :
bitdata[715:711] == 5'b00010 ? cell_80_13 :
bitdata[715:711] == 5'b10010 ? cell_80_14 :
bitdata[715:711] == 5'b01010 ? cell_80_15 :
bitdata[715:711] == 5'b0 ? 1'b0 : 1'bx);
assign cell_96_0 =
(bitdata[1112:1110] == 3'b001 ? sw_2_0_7_down0 :
bitdata[1112:1110] == 3'b100 ? cell_65_2 :
bitdata[1112:1110] == 3'b010 ? cell_66_1 :
bitdata[1112:1110] == 3'b110 ? cell_71_3 :
bitdata[1112:1110] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1137:1136] == 2'b11 ? sw_2_1_3_down0 :
bitdata[1137:1136] == 2'b10 ? cell_94_0 :
bitdata[1137:1136] == 2'b01 ? cell_95_0 :
bitdata[1137:1136] == 2'b0 ? 16'b0 : 16'bx);
assign cell_97_0 =
(bitdata[1071:1069] == 3'b001 ? sw_2_0_4_down0 :
bitdata[1071:1069] == 3'b100 ? cell_61_5 :
bitdata[1071:1069] == 3'b010 ? cell_79_3 :
bitdata[1071:1069] == 3'b110 ? cell_91_0 :
bitdata[1071:1069] == 3'b0 ? 16'b0 : 16'bx) |
(bitdata[1139:1138] == 2'b11 ? sw_2_1_3_down0 :
bitdata[1139:1138] == 2'b10 ? cell_94_0 :
bitdata[1139:1138] == 2'b01 ? cell_95_0 :
bitdata[1139:1138] == 2'b0 ? 16'b0 : 16'bx);
assign cell_9_0 =
(bitdata[302:298] == 5'b01001 ? sw_0_0_25_down0 :
bitdata[302:298] == 5'b11001 ? sw_0_0_25_down1 :
bitdata[302:298] == 5'b00101 ? sw_0_0_25_down2 :
bitdata[302:298] == 5'b10000 ? cell_63_8 :
bitdata[302:298] == 5'b01000 ? cell_63_9 :
bitdata[302:298] == 5'b11000 ? cell_81_10 :
bitdata[302:298] == 5'b00100 ? cell_81_11 :
bitdata[302:298] == 5'b10100 ? cell_81_12 :
bitdata[302:298] == 5'b01100 ? cell_81_13 :
bitdata[302:298] == 5'b11100 ? cell_81_14 :
bitdata[302:298] == 5'b00010 ? cell_81_15 :
bitdata[302:298] == 5'b10010 ? cell_81_16 :
bitdata[302:298] == 5'b01010 ? cell_81_17 :
bitdata[302:298] == 5'b11010 ? cell_81_18 :
bitdata[302:298] == 5'b00110 ? cell_81_19 :
bitdata[302:298] == 5'b10110 ? cell_81_20 :
bitdata[302:298] == 5'b01110 ? cell_81_21 :
bitdata[302:298] == 5'b11110 ? cell_81_22 :
bitdata[302:298] == 5'b00001 ? cell_81_23 :
bitdata[302:298] == 5'b10001 ? cell_81_24 :
bitdata[302:298] == 5'b0 ? 1'b0 : 1'bx) |
(bitdata[907:905] == 3'b001 ? sw_0_1_25_down0 :
bitdata[907:905] == 3'b100 ? cell_6_0 :
bitdata[907:905] == 3'b010 ? cell_7_0 :
bitdata[907:905] == 3'b110 ? cell_8_0 :
bitdata[907:905] == 3'b0 ? 1'b0 : 1'bx);
assign sw_0_0_10_down0 =
(bitdata[33:30] == 4'b0001 ? sw_0_0_3_down0 :
bitdata[33:30] == 4'b0000 ? sw_0_0_8_up0 :
bitdata[33:30] == 4'b1000 ? sw_0_0_8_up1 :
bitdata[33:30] == 4'b0100 ? sw_0_0_8_up2 :
bitdata[33:30] == 4'b1100 ? sw_0_0_9_up0 :
bitdata[33:30] == 4'b0010 ? sw_0_0_9_up1 :
bitdata[33:30] == 4'b1010 ? sw_0_0_9_up2 :
bitdata[33:30] == 4'b0110 ? sw_0_0_9_up3 :
bitdata[33:30] == 4'b1110 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_10_down1 =
(bitdata[37:34] == 4'b0001 ? sw_0_0_3_down0 :
bitdata[37:34] == 4'b0000 ? sw_0_0_8_up0 :
bitdata[37:34] == 4'b1000 ? sw_0_0_8_up1 :
bitdata[37:34] == 4'b0100 ? sw_0_0_8_up2 :
bitdata[37:34] == 4'b1100 ? sw_0_0_9_up0 :
bitdata[37:34] == 4'b0010 ? sw_0_0_9_up1 :
bitdata[37:34] == 4'b1010 ? sw_0_0_9_up2 :
bitdata[37:34] == 4'b0110 ? sw_0_0_9_up3 :
bitdata[37:34] == 4'b1110 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_10_down2 =
(bitdata[41:38] == 4'b0001 ? sw_0_0_3_down0 :
bitdata[41:38] == 4'b0000 ? sw_0_0_8_up0 :
bitdata[41:38] == 4'b1000 ? sw_0_0_8_up1 :
bitdata[41:38] == 4'b0100 ? sw_0_0_8_up2 :
bitdata[41:38] == 4'b1100 ? sw_0_0_9_up0 :
bitdata[41:38] == 4'b0010 ? sw_0_0_9_up1 :
bitdata[41:38] == 4'b1010 ? sw_0_0_9_up2 :
bitdata[41:38] == 4'b0110 ? sw_0_0_9_up3 :
bitdata[41:38] == 4'b1110 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_10_up0 =
(bitdata[176:174] == 3'b000 ? cell_62_6 :
bitdata[176:174] == 3'b100 ? cell_62_7 :
bitdata[176:174] == 3'b010 ? cell_64_8 :
bitdata[176:174] == 3'b110 ? cell_64_9 :
bitdata[176:174] == 3'b001 ? cell_83_0 : 1'bx);
assign sw_0_0_11_down0 =
(bitdata[45:42] == 4'b0001 ? sw_0_0_3_down0 :
bitdata[45:42] == 4'b0000 ? sw_0_0_8_up0 :
bitdata[45:42] == 4'b1000 ? sw_0_0_8_up1 :
bitdata[45:42] == 4'b0100 ? sw_0_0_8_up2 :
bitdata[45:42] == 4'b1100 ? sw_0_0_9_up0 :
bitdata[45:42] == 4'b0010 ? sw_0_0_9_up1 :
bitdata[45:42] == 4'b1010 ? sw_0_0_9_up2 :
bitdata[45:42] == 4'b0110 ? sw_0_0_9_up3 :
bitdata[45:42] == 4'b1110 ? sw_0_0_10_up0 : 1'bx);
assign sw_0_0_11_down1 =
(bitdata[49:46] == 4'b0001 ? sw_0_0_3_down0 :
bitdata[49:46] == 4'b0000 ? sw_0_0_8_up0 :
bitdata[49:46] == 4'b1000 ? sw_0_0_8_up1 :
bitdata[49:46] == 4'b0100 ? sw_0_0_8_up2 :
bitdata[49:46] == 4'b1100 ? sw_0_0_9_up0 :
bitdata[49:46] == 4'b0010 ? sw_0_0_9_up1 :
bitdata[49:46] == 4'b1010 ? sw_0_0_9_up2 :
bitdata[49:46] == 4'b0110 ? sw_0_0_9_up3 :
bitdata[49:46] == 4'b1110 ? sw_0_0_10_up0 : 1'bx);
assign sw_0_0_11_up0 = cell_43_0;
assign sw_0_0_12_down0 =
(bitdata[51:51] == 1'b1 ? sw_0_0_4_down0 :
bitdata[51:51] == 1'b0 ? sw_0_0_15_up0 : 1'bx);
assign sw_0_0_12_up0 =
(bitdata[213:211] == 3'b000 ? cell_8_0 :
bitdata[213:211] == 3'b100 ? cell_72_5 :
bitdata[213:211] == 3'b010 ? cell_72_6 :
bitdata[213:211] == 3'b110 ? cell_72_7 :
bitdata[213:211] == 3'b001 ? cell_72_8 : 1'bx);
assign sw_0_0_13_down0 =
(bitdata[53:52] == 2'b01 ? sw_0_0_4_down0 :
bitdata[53:52] == 2'b00 ? sw_0_0_12_up0 :
bitdata[53:52] == 2'b10 ? sw_0_0_15_up0 : 1'bx);
assign sw_0_0_14_down0 =
(bitdata[55:54] == 2'b01 ? sw_0_0_4_down0 :
bitdata[55:54] == 2'b00 ? sw_0_0_12_up0 :
bitdata[55:54] == 2'b10 ? sw_0_0_15_up0 : 1'bx);
assign sw_0_0_15_up0 =
(bitdata[233:232] == 2'b00 ? cell_49_0 :
bitdata[233:232] == 2'b10 ? cell_50_0 :
bitdata[233:232] == 2'b01 ? cell_51_0 :
bitdata[233:232] == 2'b11 ? cell_52_0 : 1'bx);
assign sw_0_0_16_down0 =
(bitdata[57:57] == 1'b1 ? sw_0_0_5_down0 :
bitdata[57:57] == 1'b0 ? sw_0_0_18_up0 : 1'bx);
assign sw_0_0_16_up0 =
(bitdata[235:234] == 2'b00 ? cell_46_0 :
bitdata[235:234] == 2'b10 ? cell_47_0 :
bitdata[235:234] == 2'b01 ? cell_48_0 : 1'bx);
assign sw_0_0_17_down0 =
(bitdata[59:58] == 2'b01 ? sw_0_0_5_down0 :
bitdata[59:58] == 2'b00 ? sw_0_0_16_up0 :
bitdata[59:58] == 2'b10 ? sw_0_0_18_up0 : 1'bx);
assign sw_0_0_18_down0 =
(bitdata[60:60] == 1'b1 ? sw_0_0_5_down0 :
bitdata[60:60] == 1'b0 ? sw_0_0_16_up0 : 1'bx);
assign sw_0_0_18_up0 =
(bitdata[243:243] == 1'b0 ? cell_39_0 :
bitdata[243:243] == 1'b1 ? cell_40_0 : 1'bx);
assign sw_0_0_19_down0 =
(bitdata[62:61] == 2'b01 ? sw_0_0_5_down0 :
bitdata[62:61] == 2'b00 ? sw_0_0_16_up0 :
bitdata[62:61] == 2'b10 ? sw_0_0_18_up0 : 1'bx);
assign sw_0_0_1_down0 = sw_0_0_2_up0;
assign sw_0_0_1_up0 =
(bitdata[1:0] == 2'b00 ? sw_0_0_3_up0 :
bitdata[1:0] == 2'b10 ? sw_0_0_4_up0 :
bitdata[1:0] == 2'b01 ? sw_0_0_5_up0 : 1'bx);
assign sw_0_0_20_down0 =
(bitdata[66:65] == 2'b01 ? sw_0_0_6_down0 :
bitdata[66:65] == 2'b00 ? sw_0_0_22_up0 :
bitdata[66:65] == 2'b10 ? sw_0_0_23_up0 : 1'bx);
assign sw_0_0_20_up0 = cell_7_0;
assign sw_0_0_21_down0 =
(bitdata[68:67] == 2'b11 ? sw_0_0_6_down0 :
bitdata[68:67] == 2'b00 ? sw_0_0_20_up0 :
bitdata[68:67] == 2'b10 ? sw_0_0_22_up0 :
bitdata[68:67] == 2'b01 ? sw_0_0_23_up0 : 1'bx);
assign sw_0_0_22_down0 =
(bitdata[70:69] == 2'b01 ? sw_0_0_6_down0 :
bitdata[70:69] == 2'b00 ? sw_0_0_20_up0 :
bitdata[70:69] == 2'b10 ? sw_0_0_23_up0 : 1'bx);
assign sw_0_0_22_up0 =
(bitdata[263:262] == 2'b00 ? cell_19_0 :
bitdata[263:262] == 2'b10 ? cell_20_0 :
bitdata[263:262] == 2'b01 ? cell_21_0 : 1'bx);
assign sw_0_0_23_up0 =
(bitdata[268:267] == 2'b00 ? cell_15_0 :
bitdata[268:267] == 2'b10 ? cell_16_0 :
bitdata[268:267] == 2'b01 ? cell_17_0 :
bitdata[268:267] == 2'b11 ? cell_18_0 : 1'bx);
assign sw_0_0_24_down0 =
(bitdata[76:74] == 3'b101 ? sw_0_0_7_down0 :
bitdata[76:74] == 3'b000 ? sw_0_0_25_up0 :
bitdata[76:74] == 3'b100 ? sw_0_0_25_up1 :
bitdata[76:74] == 3'b010 ? sw_0_0_25_up2 :
bitdata[76:74] == 3'b110 ? sw_0_0_25_up3 :
bitdata[76:74] == 3'b001 ? sw_0_0_26_up0 : 1'bx);
assign sw_0_0_24_down1 =
(bitdata[79:77] == 3'b101 ? sw_0_0_7_down0 :
bitdata[79:77] == 3'b000 ? sw_0_0_25_up0 :
bitdata[79:77] == 3'b100 ? sw_0_0_25_up1 :
bitdata[79:77] == 3'b010 ? sw_0_0_25_up2 :
bitdata[79:77] == 3'b110 ? sw_0_0_25_up3 :
bitdata[79:77] == 3'b001 ? sw_0_0_26_up0 : 1'bx);
assign sw_0_0_24_down2 =
(bitdata[82:80] == 3'b101 ? sw_0_0_7_down0 :
bitdata[82:80] == 3'b000 ? sw_0_0_25_up0 :
bitdata[82:80] == 3'b100 ? sw_0_0_25_up1 :
bitdata[82:80] == 3'b010 ? sw_0_0_25_up2 :
bitdata[82:80] == 3'b110 ? sw_0_0_25_up3 :
bitdata[82:80] == 3'b001 ? sw_0_0_26_up0 : 1'bx);
assign sw_0_0_24_up0 = cell_3_0;
assign sw_0_0_25_down0 =
(bitdata[84:83] == 2'b01 ? sw_0_0_7_down0 :
bitdata[84:83] == 2'b00 ? sw_0_0_24_up0 :
bitdata[84:83] == 2'b10 ? sw_0_0_26_up0 : 1'bx);
assign sw_0_0_25_down1 =
(bitdata[86:85] == 2'b01 ? sw_0_0_7_down0 :
bitdata[86:85] == 2'b00 ? sw_0_0_24_up0 :
bitdata[86:85] == 2'b10 ? sw_0_0_26_up0 : 1'bx);
assign sw_0_0_25_down2 =
(bitdata[88:87] == 2'b01 ? sw_0_0_7_down0 :
bitdata[88:87] == 2'b00 ? sw_0_0_24_up0 :
bitdata[88:87] == 2'b10 ? sw_0_0_26_up0 : 1'bx);
assign sw_0_0_25_up0 =
(bitdata[282:278] == 5'b00000 ? cell_63_8 :
bitdata[282:278] == 5'b10000 ? cell_63_9 :
bitdata[282:278] == 5'b01000 ? cell_81_10 :
bitdata[282:278] == 5'b11000 ? cell_81_11 :
bitdata[282:278] == 5'b00100 ? cell_81_12 :
bitdata[282:278] == 5'b10100 ? cell_81_13 :
bitdata[282:278] == 5'b01100 ? cell_81_14 :
bitdata[282:278] == 5'b11100 ? cell_81_15 :
bitdata[282:278] == 5'b00010 ? cell_81_16 :
bitdata[282:278] == 5'b10010 ? cell_81_17 :
bitdata[282:278] == 5'b01010 ? cell_81_18 :
bitdata[282:278] == 5'b11010 ? cell_81_19 :
bitdata[282:278] == 5'b00110 ? cell_81_20 :
bitdata[282:278] == 5'b10110 ? cell_81_21 :
bitdata[282:278] == 5'b01110 ? cell_81_22 :
bitdata[282:278] == 5'b11110 ? cell_81_23 :
bitdata[282:278] == 5'b00001 ? cell_81_24 : 1'bx);
assign sw_0_0_25_up1 =
(bitdata[287:283] == 5'b00000 ? cell_63_8 :
bitdata[287:283] == 5'b10000 ? cell_63_9 :
bitdata[287:283] == 5'b01000 ? cell_81_10 :
bitdata[287:283] == 5'b11000 ? cell_81_11 :
bitdata[287:283] == 5'b00100 ? cell_81_12 :
bitdata[287:283] == 5'b10100 ? cell_81_13 :
bitdata[287:283] == 5'b01100 ? cell_81_14 :
bitdata[287:283] == 5'b11100 ? cell_81_15 :
bitdata[287:283] == 5'b00010 ? cell_81_16 :
bitdata[287:283] == 5'b10010 ? cell_81_17 :
bitdata[287:283] == 5'b01010 ? cell_81_18 :
bitdata[287:283] == 5'b11010 ? cell_81_19 :
bitdata[287:283] == 5'b00110 ? cell_81_20 :
bitdata[287:283] == 5'b10110 ? cell_81_21 :
bitdata[287:283] == 5'b01110 ? cell_81_22 :
bitdata[287:283] == 5'b11110 ? cell_81_23 :
bitdata[287:283] == 5'b00001 ? cell_81_24 : 1'bx);
assign sw_0_0_25_up2 =
(bitdata[292:288] == 5'b00000 ? cell_63_8 :
bitdata[292:288] == 5'b10000 ? cell_63_9 :
bitdata[292:288] == 5'b01000 ? cell_81_10 :
bitdata[292:288] == 5'b11000 ? cell_81_11 :
bitdata[292:288] == 5'b00100 ? cell_81_12 :
bitdata[292:288] == 5'b10100 ? cell_81_13 :
bitdata[292:288] == 5'b01100 ? cell_81_14 :
bitdata[292:288] == 5'b11100 ? cell_81_15 :
bitdata[292:288] == 5'b00010 ? cell_81_16 :
bitdata[292:288] == 5'b10010 ? cell_81_17 :
bitdata[292:288] == 5'b01010 ? cell_81_18 :
bitdata[292:288] == 5'b11010 ? cell_81_19 :
bitdata[292:288] == 5'b00110 ? cell_81_20 :
bitdata[292:288] == 5'b10110 ? cell_81_21 :
bitdata[292:288] == 5'b01110 ? cell_81_22 :
bitdata[292:288] == 5'b11110 ? cell_81_23 :
bitdata[292:288] == 5'b00001 ? cell_81_24 : 1'bx);
assign sw_0_0_25_up3 =
(bitdata[297:293] == 5'b00000 ? cell_63_8 :
bitdata[297:293] == 5'b10000 ? cell_63_9 :
bitdata[297:293] == 5'b01000 ? cell_81_10 :
bitdata[297:293] == 5'b11000 ? cell_81_11 :
bitdata[297:293] == 5'b00100 ? cell_81_12 :
bitdata[297:293] == 5'b10100 ? cell_81_13 :
bitdata[297:293] == 5'b01100 ? cell_81_14 :
bitdata[297:293] == 5'b11100 ? cell_81_15 :
bitdata[297:293] == 5'b00010 ? cell_81_16 :
bitdata[297:293] == 5'b10010 ? cell_81_17 :
bitdata[297:293] == 5'b01010 ? cell_81_18 :
bitdata[297:293] == 5'b11010 ? cell_81_19 :
bitdata[297:293] == 5'b00110 ? cell_81_20 :
bitdata[297:293] == 5'b10110 ? cell_81_21 :
bitdata[297:293] == 5'b01110 ? cell_81_22 :
bitdata[297:293] == 5'b11110 ? cell_81_23 :
bitdata[297:293] == 5'b00001 ? cell_81_24 : 1'bx);
assign sw_0_0_26_down0 =
(bitdata[91:89] == 3'b101 ? sw_0_0_7_down0 :
bitdata[91:89] == 3'b000 ? sw_0_0_24_up0 :
bitdata[91:89] == 3'b100 ? sw_0_0_25_up0 :
bitdata[91:89] == 3'b010 ? sw_0_0_25_up1 :
bitdata[91:89] == 3'b110 ? sw_0_0_25_up2 :
bitdata[91:89] == 3'b001 ? sw_0_0_25_up3 : 1'bx);
assign sw_0_0_26_down1 =
(bitdata[94:92] == 3'b101 ? sw_0_0_7_down0 :
bitdata[94:92] == 3'b000 ? sw_0_0_24_up0 :
bitdata[94:92] == 3'b100 ? sw_0_0_25_up0 :
bitdata[94:92] == 3'b010 ? sw_0_0_25_up1 :
bitdata[94:92] == 3'b110 ? sw_0_0_25_up2 :
bitdata[94:92] == 3'b001 ? sw_0_0_25_up3 : 1'bx);
assign sw_0_0_26_up0 = cell_6_0;
assign sw_0_0_2_down0 = sw_0_0_1_up0;
assign sw_0_0_2_up0 =
(bitdata[8:8] == 1'b0 ? sw_0_0_6_up0 :
bitdata[8:8] == 1'b1 ? sw_0_0_7_up0 : 1'bx);
assign sw_0_0_3_down0 =
(bitdata[3:2] == 2'b01 ? sw_0_0_1_down0 :
bitdata[3:2] == 2'b00 ? sw_0_0_4_up0 :
bitdata[3:2] == 2'b10 ? sw_0_0_5_up0 : 1'bx);
assign sw_0_0_3_up0 =
(bitdata[14:11] == 4'b0000 ? sw_0_0_8_up0 :
bitdata[14:11] == 4'b1000 ? sw_0_0_8_up1 :
bitdata[14:11] == 4'b0100 ? sw_0_0_8_up2 :
bitdata[14:11] == 4'b1100 ? sw_0_0_9_up0 :
bitdata[14:11] == 4'b0010 ? sw_0_0_9_up1 :
bitdata[14:11] == 4'b1010 ? sw_0_0_9_up2 :
bitdata[14:11] == 4'b0110 ? sw_0_0_9_up3 :
bitdata[14:11] == 4'b1110 ? sw_0_0_10_up0 :
bitdata[14:11] == 4'b0001 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_4_down0 =
(bitdata[5:4] == 2'b01 ? sw_0_0_1_down0 :
bitdata[5:4] == 2'b00 ? sw_0_0_3_up0 :
bitdata[5:4] == 2'b10 ? sw_0_0_5_up0 : 1'bx);
assign sw_0_0_4_up0 =
(bitdata[50:50] == 1'b0 ? sw_0_0_12_up0 :
bitdata[50:50] == 1'b1 ? sw_0_0_15_up0 : 1'bx);
assign sw_0_0_5_down0 =
(bitdata[7:6] == 2'b01 ? sw_0_0_1_down0 :
bitdata[7:6] == 2'b00 ? sw_0_0_3_up0 :
bitdata[7:6] == 2'b10 ? sw_0_0_4_up0 : 1'bx);
assign sw_0_0_5_up0 =
(bitdata[56:56] == 1'b0 ? sw_0_0_16_up0 :
bitdata[56:56] == 1'b1 ? sw_0_0_18_up0 : 1'bx);
assign sw_0_0_6_down0 =
(bitdata[9:9] == 1'b1 ? sw_0_0_2_down0 :
bitdata[9:9] == 1'b0 ? sw_0_0_7_up0 : 1'bx);
assign sw_0_0_6_up0 =
(bitdata[64:63] == 2'b00 ? sw_0_0_20_up0 :
bitdata[64:63] == 2'b10 ? sw_0_0_22_up0 :
bitdata[64:63] == 2'b01 ? sw_0_0_23_up0 : 1'bx);
assign sw_0_0_7_down0 =
(bitdata[10:10] == 1'b1 ? sw_0_0_2_down0 :
bitdata[10:10] == 1'b0 ? sw_0_0_6_up0 : 1'bx);
assign sw_0_0_7_up0 =
(bitdata[73:71] == 3'b000 ? sw_0_0_24_up0 :
bitdata[73:71] == 3'b100 ? sw_0_0_25_up0 :
bitdata[73:71] == 3'b010 ? sw_0_0_25_up1 :
bitdata[73:71] == 3'b110 ? sw_0_0_25_up2 :
bitdata[73:71] == 3'b001 ? sw_0_0_25_up3 :
bitdata[73:71] == 3'b101 ? sw_0_0_26_up0 : 1'bx);
assign sw_0_0_8_down0 =
(bitdata[17:15] == 3'b011 ? sw_0_0_3_down0 :
bitdata[17:15] == 3'b000 ? sw_0_0_9_up0 :
bitdata[17:15] == 3'b100 ? sw_0_0_9_up1 :
bitdata[17:15] == 3'b010 ? sw_0_0_9_up2 :
bitdata[17:15] == 3'b110 ? sw_0_0_9_up3 :
bitdata[17:15] == 3'b001 ? sw_0_0_10_up0 :
bitdata[17:15] == 3'b101 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_8_down1 =
(bitdata[20:18] == 3'b011 ? sw_0_0_3_down0 :
bitdata[20:18] == 3'b000 ? sw_0_0_9_up0 :
bitdata[20:18] == 3'b100 ? sw_0_0_9_up1 :
bitdata[20:18] == 3'b010 ? sw_0_0_9_up2 :
bitdata[20:18] == 3'b110 ? sw_0_0_9_up3 :
bitdata[20:18] == 3'b001 ? sw_0_0_10_up0 :
bitdata[20:18] == 3'b101 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_8_down2 =
(bitdata[23:21] == 3'b011 ? sw_0_0_3_down0 :
bitdata[23:21] == 3'b000 ? sw_0_0_9_up0 :
bitdata[23:21] == 3'b100 ? sw_0_0_9_up1 :
bitdata[23:21] == 3'b010 ? sw_0_0_9_up2 :
bitdata[23:21] == 3'b110 ? sw_0_0_9_up3 :
bitdata[23:21] == 3'b001 ? sw_0_0_10_up0 :
bitdata[23:21] == 3'b101 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_8_down3 =
(bitdata[26:24] == 3'b011 ? sw_0_0_3_down0 :
bitdata[26:24] == 3'b000 ? sw_0_0_9_up0 :
bitdata[26:24] == 3'b100 ? sw_0_0_9_up1 :
bitdata[26:24] == 3'b010 ? sw_0_0_9_up2 :
bitdata[26:24] == 3'b110 ? sw_0_0_9_up3 :
bitdata[26:24] == 3'b001 ? sw_0_0_10_up0 :
bitdata[26:24] == 3'b101 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_8_down4 =
(bitdata[29:27] == 3'b011 ? sw_0_0_3_down0 :
bitdata[29:27] == 3'b000 ? sw_0_0_9_up0 :
bitdata[29:27] == 3'b100 ? sw_0_0_9_up1 :
bitdata[29:27] == 3'b010 ? sw_0_0_9_up2 :
bitdata[29:27] == 3'b110 ? sw_0_0_9_up3 :
bitdata[29:27] == 3'b001 ? sw_0_0_10_up0 :
bitdata[29:27] == 3'b101 ? sw_0_0_11_up0 : 1'bx);
assign sw_0_0_8_up0 =
(bitdata[98:95] == 4'b0000 ? cell_61_6 :
bitdata[98:95] == 4'b1000 ? cell_61_7 :
bitdata[98:95] == 4'b0100 ? cell_71_5 :
bitdata[98:95] == 4'b1100 ? cell_71_6 :
bitdata[98:95] == 4'b0010 ? cell_71_7 :
bitdata[98:95] == 4'b1010 ? cell_71_8 :
bitdata[98:95] == 4'b0110 ? cell_80_6 :
bitdata[98:95] == 4'b1110 ? cell_80_7 :
bitdata[98:95] == 4'b0001 ? cell_80_8 :
bitdata[98:95] == 4'b1001 ? cell_80_9 :
bitdata[98:95] == 4'b0101 ? cell_80_10 :
bitdata[98:95] == 4'b1101 ? cell_80_11 :
bitdata[98:95] == 4'b0011 ? cell_80_12 :
bitdata[98:95] == 4'b1011 ? cell_80_13 :
bitdata[98:95] == 4'b0111 ? cell_80_14 :
bitdata[98:95] == 4'b1111 ? cell_80_15 : 1'bx);
assign sw_0_0_8_up1 =
(bitdata[102:99] == 4'b0000 ? cell_61_6 :
bitdata[102:99] == 4'b1000 ? cell_61_7 :
bitdata[102:99] == 4'b0100 ? cell_71_5 :
bitdata[102:99] == 4'b1100 ? cell_71_6 :
bitdata[102:99] == 4'b0010 ? cell_71_7 :
bitdata[102:99] == 4'b1010 ? cell_71_8 :
bitdata[102:99] == 4'b0110 ? cell_80_6 :
bitdata[102:99] == 4'b1110 ? cell_80_7 :
bitdata[102:99] == 4'b0001 ? cell_80_8 :
bitdata[102:99] == 4'b1001 ? cell_80_9 :
bitdata[102:99] == 4'b0101 ? cell_80_10 :
bitdata[102:99] == 4'b1101 ? cell_80_11 :
bitdata[102:99] == 4'b0011 ? cell_80_12 :
bitdata[102:99] == 4'b1011 ? cell_80_13 :
bitdata[102:99] == 4'b0111 ? cell_80_14 :
bitdata[102:99] == 4'b1111 ? cell_80_15 : 1'bx);
assign sw_0_0_8_up2 =
(bitdata[106:103] == 4'b0000 ? cell_61_6 :
bitdata[106:103] == 4'b1000 ? cell_61_7 :
bitdata[106:103] == 4'b0100 ? cell_71_5 :
bitdata[106:103] == 4'b1100 ? cell_71_6 :
bitdata[106:103] == 4'b0010 ? cell_71_7 :
bitdata[106:103] == 4'b1010 ? cell_71_8 :
bitdata[106:103] == 4'b0110 ? cell_80_6 :
bitdata[106:103] == 4'b1110 ? cell_80_7 :
bitdata[106:103] == 4'b0001 ? cell_80_8 :
bitdata[106:103] == 4'b1001 ? cell_80_9 :
bitdata[106:103] == 4'b0101 ? cell_80_10 :
bitdata[106:103] == 4'b1101 ? cell_80_11 :
bitdata[106:103] == 4'b0011 ? cell_80_12 :
bitdata[106:103] == 4'b1011 ? cell_80_13 :
bitdata[106:103] == 4'b0111 ? cell_80_14 :
bitdata[106:103] == 4'b1111 ? cell_80_15 : 1'bx);
assign sw_0_0_9_up0 =
(bitdata[167:166] == 2'b00 ? cell_0_0 :
bitdata[167:166] == 2'b10 ? cell_14_0 :
bitdata[167:166] == 2'b01 ? cell_45_0 :
bitdata[167:166] == 2'b11 ? cell_82_0 : 1'bx);
assign sw_0_0_9_up1 =
(bitdata[169:168] == 2'b00 ? cell_0_0 :
bitdata[169:168] == 2'b10 ? cell_14_0 :
bitdata[169:168] == 2'b01 ? cell_45_0 :
bitdata[169:168] == 2'b11 ? cell_82_0 : 1'bx);
assign sw_0_0_9_up2 =
(bitdata[171:170] == 2'b00 ? cell_0_0 :
bitdata[171:170] == 2'b10 ? cell_14_0 :
bitdata[171:170] == 2'b01 ? cell_45_0 :
bitdata[171:170] == 2'b11 ? cell_82_0 : 1'bx);
assign sw_0_0_9_up3 =
(bitdata[173:172] == 2'b00 ? cell_0_0 :
bitdata[173:172] == 2'b10 ? cell_14_0 :
bitdata[173:172] == 2'b01 ? cell_45_0 :
bitdata[173:172] == 2'b11 ? cell_82_0 : 1'bx);
assign sw_0_1_10_down0 =
(bitdata[479:475] == 5'b11110 ? sw_0_1_3_down0 :
bitdata[479:475] == 5'b00001 ? sw_0_1_3_down1 :
bitdata[479:475] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[479:475] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[479:475] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[479:475] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[479:475] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[479:475] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[479:475] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[479:475] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[479:475] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[479:475] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[479:475] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[479:475] == 5'b11010 ? sw_0_1_11_up0 :
bitdata[479:475] == 5'b00110 ? sw_0_1_11_up1 :
bitdata[479:475] == 5'b10110 ? sw_0_1_11_up2 :
bitdata[479:475] == 5'b01110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_10_down1 =
(bitdata[484:480] == 5'b11110 ? sw_0_1_3_down0 :
bitdata[484:480] == 5'b00001 ? sw_0_1_3_down1 :
bitdata[484:480] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[484:480] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[484:480] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[484:480] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[484:480] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[484:480] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[484:480] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[484:480] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[484:480] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[484:480] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[484:480] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[484:480] == 5'b11010 ? sw_0_1_11_up0 :
bitdata[484:480] == 5'b00110 ? sw_0_1_11_up1 :
bitdata[484:480] == 5'b10110 ? sw_0_1_11_up2 :
bitdata[484:480] == 5'b01110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_10_down2 =
(bitdata[489:485] == 5'b11110 ? sw_0_1_3_down0 :
bitdata[489:485] == 5'b00001 ? sw_0_1_3_down1 :
bitdata[489:485] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[489:485] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[489:485] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[489:485] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[489:485] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[489:485] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[489:485] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[489:485] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[489:485] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[489:485] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[489:485] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[489:485] == 5'b11010 ? sw_0_1_11_up0 :
bitdata[489:485] == 5'b00110 ? sw_0_1_11_up1 :
bitdata[489:485] == 5'b10110 ? sw_0_1_11_up2 :
bitdata[489:485] == 5'b01110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_10_down3 =
(bitdata[494:490] == 5'b11110 ? sw_0_1_3_down0 :
bitdata[494:490] == 5'b00001 ? sw_0_1_3_down1 :
bitdata[494:490] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[494:490] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[494:490] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[494:490] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[494:490] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[494:490] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[494:490] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[494:490] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[494:490] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[494:490] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[494:490] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[494:490] == 5'b11010 ? sw_0_1_11_up0 :
bitdata[494:490] == 5'b00110 ? sw_0_1_11_up1 :
bitdata[494:490] == 5'b10110 ? sw_0_1_11_up2 :
bitdata[494:490] == 5'b01110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_10_down4 =
(bitdata[499:495] == 5'b11110 ? sw_0_1_3_down0 :
bitdata[499:495] == 5'b00001 ? sw_0_1_3_down1 :
bitdata[499:495] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[499:495] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[499:495] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[499:495] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[499:495] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[499:495] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[499:495] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[499:495] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[499:495] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[499:495] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[499:495] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[499:495] == 5'b11010 ? sw_0_1_11_up0 :
bitdata[499:495] == 5'b00110 ? sw_0_1_11_up1 :
bitdata[499:495] == 5'b10110 ? sw_0_1_11_up2 :
bitdata[499:495] == 5'b01110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_10_up0 =
(bitdata[727:725] == 3'b000 ? cell_62_6 :
bitdata[727:725] == 3'b100 ? cell_62_7 :
bitdata[727:725] == 3'b010 ? cell_64_8 :
bitdata[727:725] == 3'b110 ? cell_64_9 :
bitdata[727:725] == 3'b001 ? cell_82_0 : 1'bx);
assign sw_0_1_10_up1 =
(bitdata[730:728] == 3'b000 ? cell_62_6 :
bitdata[730:728] == 3'b100 ? cell_62_7 :
bitdata[730:728] == 3'b010 ? cell_64_8 :
bitdata[730:728] == 3'b110 ? cell_64_9 :
bitdata[730:728] == 3'b001 ? cell_82_0 : 1'bx);
assign sw_0_1_10_up2 =
(bitdata[733:731] == 3'b000 ? cell_62_6 :
bitdata[733:731] == 3'b100 ? cell_62_7 :
bitdata[733:731] == 3'b010 ? cell_64_8 :
bitdata[733:731] == 3'b110 ? cell_64_9 :
bitdata[733:731] == 3'b001 ? cell_82_0 : 1'bx);
assign sw_0_1_11_down0 =
(bitdata[503:500] == 4'b0111 ? sw_0_1_3_down0 :
bitdata[503:500] == 4'b1111 ? sw_0_1_3_down1 :
bitdata[503:500] == 4'b0000 ? sw_0_1_8_up0 :
bitdata[503:500] == 4'b1000 ? sw_0_1_8_up1 :
bitdata[503:500] == 4'b0100 ? sw_0_1_8_up2 :
bitdata[503:500] == 4'b1100 ? sw_0_1_8_up3 :
bitdata[503:500] == 4'b0010 ? sw_0_1_8_up4 :
bitdata[503:500] == 4'b1010 ? sw_0_1_8_up5 :
bitdata[503:500] == 4'b0110 ? sw_0_1_8_up6 :
bitdata[503:500] == 4'b1110 ? sw_0_1_8_up7 :
bitdata[503:500] == 4'b0001 ? sw_0_1_8_up8 :
bitdata[503:500] == 4'b1001 ? sw_0_1_8_up9 :
bitdata[503:500] == 4'b0101 ? sw_0_1_9_up0 :
bitdata[503:500] == 4'b1101 ? sw_0_1_10_up0 :
bitdata[503:500] == 4'b0011 ? sw_0_1_10_up1 :
bitdata[503:500] == 4'b1011 ? sw_0_1_10_up2 : 1'bx);
assign sw_0_1_11_down1 =
(bitdata[507:504] == 4'b0111 ? sw_0_1_3_down0 :
bitdata[507:504] == 4'b1111 ? sw_0_1_3_down1 :
bitdata[507:504] == 4'b0000 ? sw_0_1_8_up0 :
bitdata[507:504] == 4'b1000 ? sw_0_1_8_up1 :
bitdata[507:504] == 4'b0100 ? sw_0_1_8_up2 :
bitdata[507:504] == 4'b1100 ? sw_0_1_8_up3 :
bitdata[507:504] == 4'b0010 ? sw_0_1_8_up4 :
bitdata[507:504] == 4'b1010 ? sw_0_1_8_up5 :
bitdata[507:504] == 4'b0110 ? sw_0_1_8_up6 :
bitdata[507:504] == 4'b1110 ? sw_0_1_8_up7 :
bitdata[507:504] == 4'b0001 ? sw_0_1_8_up8 :
bitdata[507:504] == 4'b1001 ? sw_0_1_8_up9 :
bitdata[507:504] == 4'b0101 ? sw_0_1_9_up0 :
bitdata[507:504] == 4'b1101 ? sw_0_1_10_up0 :
bitdata[507:504] == 4'b0011 ? sw_0_1_10_up1 :
bitdata[507:504] == 4'b1011 ? sw_0_1_10_up2 : 1'bx);
assign sw_0_1_11_down2 =
(bitdata[511:508] == 4'b0111 ? sw_0_1_3_down0 :
bitdata[511:508] == 4'b1111 ? sw_0_1_3_down1 :
bitdata[511:508] == 4'b0000 ? sw_0_1_8_up0 :
bitdata[511:508] == 4'b1000 ? sw_0_1_8_up1 :
bitdata[511:508] == 4'b0100 ? sw_0_1_8_up2 :
bitdata[511:508] == 4'b1100 ? sw_0_1_8_up3 :
bitdata[511:508] == 4'b0010 ? sw_0_1_8_up4 :
bitdata[511:508] == 4'b1010 ? sw_0_1_8_up5 :
bitdata[511:508] == 4'b0110 ? sw_0_1_8_up6 :
bitdata[511:508] == 4'b1110 ? sw_0_1_8_up7 :
bitdata[511:508] == 4'b0001 ? sw_0_1_8_up8 :
bitdata[511:508] == 4'b1001 ? sw_0_1_8_up9 :
bitdata[511:508] == 4'b0101 ? sw_0_1_9_up0 :
bitdata[511:508] == 4'b1101 ? sw_0_1_10_up0 :
bitdata[511:508] == 4'b0011 ? sw_0_1_10_up1 :
bitdata[511:508] == 4'b1011 ? sw_0_1_10_up2 : 1'bx);
assign sw_0_1_11_down3 =
(bitdata[515:512] == 4'b0111 ? sw_0_1_3_down0 :
bitdata[515:512] == 4'b1111 ? sw_0_1_3_down1 :
bitdata[515:512] == 4'b0000 ? sw_0_1_8_up0 :
bitdata[515:512] == 4'b1000 ? sw_0_1_8_up1 :
bitdata[515:512] == 4'b0100 ? sw_0_1_8_up2 :
bitdata[515:512] == 4'b1100 ? sw_0_1_8_up3 :
bitdata[515:512] == 4'b0010 ? sw_0_1_8_up4 :
bitdata[515:512] == 4'b1010 ? sw_0_1_8_up5 :
bitdata[515:512] == 4'b0110 ? sw_0_1_8_up6 :
bitdata[515:512] == 4'b1110 ? sw_0_1_8_up7 :
bitdata[515:512] == 4'b0001 ? sw_0_1_8_up8 :
bitdata[515:512] == 4'b1001 ? sw_0_1_8_up9 :
bitdata[515:512] == 4'b0101 ? sw_0_1_9_up0 :
bitdata[515:512] == 4'b1101 ? sw_0_1_10_up0 :
bitdata[515:512] == 4'b0011 ? sw_0_1_10_up1 :
bitdata[515:512] == 4'b1011 ? sw_0_1_10_up2 : 1'bx);
assign sw_0_1_11_up0 =
(bitdata[773:770] == 4'b0000 ? cell_61_6 :
bitdata[773:770] == 4'b1000 ? cell_61_7 :
bitdata[773:770] == 4'b0100 ? cell_63_8 :
bitdata[773:770] == 4'b1100 ? cell_63_9 :
bitdata[773:770] == 4'b0010 ? cell_71_5 :
bitdata[773:770] == 4'b1010 ? cell_71_6 :
bitdata[773:770] == 4'b0110 ? cell_71_7 :
bitdata[773:770] == 4'b1110 ? cell_71_8 :
bitdata[773:770] == 4'b0001 ? cell_83_0 : 1'bx);
assign sw_0_1_11_up1 =
(bitdata[777:774] == 4'b0000 ? cell_61_6 :
bitdata[777:774] == 4'b1000 ? cell_61_7 :
bitdata[777:774] == 4'b0100 ? cell_63_8 :
bitdata[777:774] == 4'b1100 ? cell_63_9 :
bitdata[777:774] == 4'b0010 ? cell_71_5 :
bitdata[777:774] == 4'b1010 ? cell_71_6 :
bitdata[777:774] == 4'b0110 ? cell_71_7 :
bitdata[777:774] == 4'b1110 ? cell_71_8 :
bitdata[777:774] == 4'b0001 ? cell_83_0 : 1'bx);
assign sw_0_1_11_up2 =
(bitdata[781:778] == 4'b0000 ? cell_61_6 :
bitdata[781:778] == 4'b1000 ? cell_61_7 :
bitdata[781:778] == 4'b0100 ? cell_63_8 :
bitdata[781:778] == 4'b1100 ? cell_63_9 :
bitdata[781:778] == 4'b0010 ? cell_71_5 :
bitdata[781:778] == 4'b1010 ? cell_71_6 :
bitdata[781:778] == 4'b0110 ? cell_71_7 :
bitdata[781:778] == 4'b1110 ? cell_71_8 :
bitdata[781:778] == 4'b0001 ? cell_83_0 : 1'bx);
assign sw_0_1_11_up3 =
(bitdata[785:782] == 4'b0000 ? cell_61_6 :
bitdata[785:782] == 4'b1000 ? cell_61_7 :
bitdata[785:782] == 4'b0100 ? cell_63_8 :
bitdata[785:782] == 4'b1100 ? cell_63_9 :
bitdata[785:782] == 4'b0010 ? cell_71_5 :
bitdata[785:782] == 4'b1010 ? cell_71_6 :
bitdata[785:782] == 4'b0110 ? cell_71_7 :
bitdata[785:782] == 4'b1110 ? cell_71_8 :
bitdata[785:782] == 4'b0001 ? cell_83_0 : 1'bx);
assign sw_0_1_12_down0 =
(bitdata[517:516] == 2'b10 ? sw_0_1_4_down0 :
bitdata[517:516] == 2'b01 ? sw_0_1_4_down1 :
bitdata[517:516] == 2'b00 ? sw_0_1_15_up0 : 1'bx);
assign sw_0_1_12_down1 =
(bitdata[519:518] == 2'b10 ? sw_0_1_4_down0 :
bitdata[519:518] == 2'b01 ? sw_0_1_4_down1 :
bitdata[519:518] == 2'b00 ? sw_0_1_15_up0 : 1'bx);
assign sw_0_1_13_down0 =
(bitdata[521:520] == 2'b10 ? sw_0_1_4_down0 :
bitdata[521:520] == 2'b01 ? sw_0_1_4_down1 :
bitdata[521:520] == 2'b00 ? sw_0_1_15_up0 : 1'bx);
assign sw_0_1_14_down0 =
(bitdata[523:522] == 2'b10 ? sw_0_1_4_down0 :
bitdata[523:522] == 2'b01 ? sw_0_1_4_down1 :
bitdata[523:522] == 2'b00 ? sw_0_1_15_up0 : 1'bx);
assign sw_0_1_15_up0 =
(bitdata[847:846] == 2'b00 ? cell_49_0 :
bitdata[847:846] == 2'b10 ? cell_50_0 :
bitdata[847:846] == 2'b01 ? cell_51_0 :
bitdata[847:846] == 2'b11 ? cell_52_0 : 1'bx);
assign sw_0_1_16_up0 =
(bitdata[849:848] == 2'b00 ? cell_45_0 :
bitdata[849:848] == 2'b10 ? cell_46_0 :
bitdata[849:848] == 2'b01 ? cell_47_0 :
bitdata[849:848] == 2'b11 ? cell_48_0 : 1'bx);
assign sw_0_1_16_up1 =
(bitdata[851:850] == 2'b00 ? cell_45_0 :
bitdata[851:850] == 2'b10 ? cell_46_0 :
bitdata[851:850] == 2'b01 ? cell_47_0 :
bitdata[851:850] == 2'b11 ? cell_48_0 : 1'bx);
assign sw_0_1_17_down0 =
(bitdata[533:530] == 4'b0010 ? sw_0_1_5_down0 :
bitdata[533:530] == 4'b1010 ? sw_0_1_5_down1 :
bitdata[533:530] == 4'b0110 ? sw_0_1_5_down2 :
bitdata[533:530] == 4'b1110 ? sw_0_1_5_down3 :
bitdata[533:530] == 4'b0001 ? sw_0_1_5_down4 :
bitdata[533:530] == 4'b0000 ? sw_0_1_16_up0 :
bitdata[533:530] == 4'b1000 ? sw_0_1_16_up1 :
bitdata[533:530] == 4'b0100 ? sw_0_1_18_up0 :
bitdata[533:530] == 4'b1100 ? sw_0_1_19_up0 : 1'bx);
assign sw_0_1_17_down1 =
(bitdata[537:534] == 4'b0010 ? sw_0_1_5_down0 :
bitdata[537:534] == 4'b1010 ? sw_0_1_5_down1 :
bitdata[537:534] == 4'b0110 ? sw_0_1_5_down2 :
bitdata[537:534] == 4'b1110 ? sw_0_1_5_down3 :
bitdata[537:534] == 4'b0001 ? sw_0_1_5_down4 :
bitdata[537:534] == 4'b0000 ? sw_0_1_16_up0 :
bitdata[537:534] == 4'b1000 ? sw_0_1_16_up1 :
bitdata[537:534] == 4'b0100 ? sw_0_1_18_up0 :
bitdata[537:534] == 4'b1100 ? sw_0_1_19_up0 : 1'bx);
assign sw_0_1_17_down2 =
(bitdata[541:538] == 4'b0010 ? sw_0_1_5_down0 :
bitdata[541:538] == 4'b1010 ? sw_0_1_5_down1 :
bitdata[541:538] == 4'b0110 ? sw_0_1_5_down2 :
bitdata[541:538] == 4'b1110 ? sw_0_1_5_down3 :
bitdata[541:538] == 4'b0001 ? sw_0_1_5_down4 :
bitdata[541:538] == 4'b0000 ? sw_0_1_16_up0 :
bitdata[541:538] == 4'b1000 ? sw_0_1_16_up1 :
bitdata[541:538] == 4'b0100 ? sw_0_1_18_up0 :
bitdata[541:538] == 4'b1100 ? sw_0_1_19_up0 : 1'bx);
assign sw_0_1_17_up0 = cell_39_0;
assign sw_0_1_18_down0 =
(bitdata[545:542] == 4'b0010 ? sw_0_1_5_down0 :
bitdata[545:542] == 4'b1010 ? sw_0_1_5_down1 :
bitdata[545:542] == 4'b0110 ? sw_0_1_5_down2 :
bitdata[545:542] == 4'b1110 ? sw_0_1_5_down3 :
bitdata[545:542] == 4'b0001 ? sw_0_1_5_down4 :
bitdata[545:542] == 4'b0000 ? sw_0_1_16_up0 :
bitdata[545:542] == 4'b1000 ? sw_0_1_16_up1 :
bitdata[545:542] == 4'b0100 ? sw_0_1_17_up0 :
bitdata[545:542] == 4'b1100 ? sw_0_1_19_up0 : 1'bx);
assign sw_0_1_18_down1 =
(bitdata[549:546] == 4'b0010 ? sw_0_1_5_down0 :
bitdata[549:546] == 4'b1010 ? sw_0_1_5_down1 :
bitdata[549:546] == 4'b0110 ? sw_0_1_5_down2 :
bitdata[549:546] == 4'b1110 ? sw_0_1_5_down3 :
bitdata[549:546] == 4'b0001 ? sw_0_1_5_down4 :
bitdata[549:546] == 4'b0000 ? sw_0_1_16_up0 :
bitdata[549:546] == 4'b1000 ? sw_0_1_16_up1 :
bitdata[549:546] == 4'b0100 ? sw_0_1_17_up0 :
bitdata[549:546] == 4'b1100 ? sw_0_1_19_up0 : 1'bx);
assign sw_0_1_18_down2 =
(bitdata[553:550] == 4'b0010 ? sw_0_1_5_down0 :
bitdata[553:550] == 4'b1010 ? sw_0_1_5_down1 :
bitdata[553:550] == 4'b0110 ? sw_0_1_5_down2 :
bitdata[553:550] == 4'b1110 ? sw_0_1_5_down3 :
bitdata[553:550] == 4'b0001 ? sw_0_1_5_down4 :
bitdata[553:550] == 4'b0000 ? sw_0_1_16_up0 :
bitdata[553:550] == 4'b1000 ? sw_0_1_16_up1 :
bitdata[553:550] == 4'b0100 ? sw_0_1_17_up0 :
bitdata[553:550] == 4'b1100 ? sw_0_1_19_up0 : 1'bx);
assign sw_0_1_18_up0 =
(bitdata[862:861] == 2'b00 ? cell_72_5 :
bitdata[862:861] == 2'b10 ? cell_72_6 :
bitdata[862:861] == 2'b01 ? cell_72_7 :
bitdata[862:861] == 2'b11 ? cell_72_8 : 1'bx);
assign sw_0_1_19_down0 =
(bitdata[557:554] == 4'b0010 ? sw_0_1_5_down0 :
bitdata[557:554] == 4'b1010 ? sw_0_1_5_down1 :
bitdata[557:554] == 4'b0110 ? sw_0_1_5_down2 :
bitdata[557:554] == 4'b1110 ? sw_0_1_5_down3 :
bitdata[557:554] == 4'b0001 ? sw_0_1_5_down4 :
bitdata[557:554] == 4'b0000 ? sw_0_1_16_up0 :
bitdata[557:554] == 4'b1000 ? sw_0_1_16_up1 :
bitdata[557:554] == 4'b0100 ? sw_0_1_17_up0 :
bitdata[557:554] == 4'b1100 ? sw_0_1_18_up0 : 1'bx);
assign sw_0_1_19_down1 =
(bitdata[561:558] == 4'b0010 ? sw_0_1_5_down0 :
bitdata[561:558] == 4'b1010 ? sw_0_1_5_down1 :
bitdata[561:558] == 4'b0110 ? sw_0_1_5_down2 :
bitdata[561:558] == 4'b1110 ? sw_0_1_5_down3 :
bitdata[561:558] == 4'b0001 ? sw_0_1_5_down4 :
bitdata[561:558] == 4'b0000 ? sw_0_1_16_up0 :
bitdata[561:558] == 4'b1000 ? sw_0_1_16_up1 :
bitdata[561:558] == 4'b0100 ? sw_0_1_17_up0 :
bitdata[561:558] == 4'b1100 ? sw_0_1_18_up0 : 1'bx);
assign sw_0_1_19_up0 = cell_40_0;
assign sw_0_1_1_down0 = sw_0_1_2_up0;
assign sw_0_1_1_up0 =
(bitdata[375:372] == 4'b0000 ? sw_0_1_3_up0 :
bitdata[375:372] == 4'b1000 ? sw_0_1_3_up1 :
bitdata[375:372] == 4'b0100 ? sw_0_1_3_up2 :
bitdata[375:372] == 4'b1100 ? sw_0_1_3_up3 :
bitdata[375:372] == 4'b0010 ? sw_0_1_3_up4 :
bitdata[375:372] == 4'b1010 ? sw_0_1_3_up5 :
bitdata[375:372] == 4'b0110 ? sw_0_1_4_up0 :
bitdata[375:372] == 4'b1110 ? sw_0_1_5_up0 :
bitdata[375:372] == 4'b0001 ? sw_0_1_5_up1 : 1'bx);
assign sw_0_1_20_down0 =
(bitdata[564:563] == 2'b01 ? sw_0_1_6_down0 :
bitdata[564:563] == 2'b00 ? sw_0_1_22_up0 :
bitdata[564:563] == 2'b10 ? sw_0_1_23_up0 : 1'bx);
assign sw_0_1_21_down0 =
(bitdata[566:565] == 2'b01 ? sw_0_1_6_down0 :
bitdata[566:565] == 2'b00 ? sw_0_1_22_up0 :
bitdata[566:565] == 2'b10 ? sw_0_1_23_up0 : 1'bx);
assign sw_0_1_22_down0 =
(bitdata[567:567] == 1'b1 ? sw_0_1_6_down0 :
bitdata[567:567] == 1'b0 ? sw_0_1_23_up0 : 1'bx);
assign sw_0_1_22_up0 =
(bitdata[891:890] == 2'b00 ? cell_19_0 :
bitdata[891:890] == 2'b10 ? cell_20_0 :
bitdata[891:890] == 2'b01 ? cell_21_0 : 1'bx);
assign sw_0_1_23_up0 =
(bitdata[896:895] == 2'b00 ? cell_15_0 :
bitdata[896:895] == 2'b10 ? cell_16_0 :
bitdata[896:895] == 2'b01 ? cell_17_0 :
bitdata[896:895] == 2'b11 ? cell_18_0 : 1'bx);
assign sw_0_1_24_down0 =
(bitdata[571:570] == 2'b01 ? sw_0_1_7_down0 :
bitdata[571:570] == 2'b00 ? sw_0_1_25_up0 :
bitdata[571:570] == 2'b10 ? sw_0_1_26_up0 : 1'bx);
assign sw_0_1_24_up0 = cell_14_0;
assign sw_0_1_25_down0 =
(bitdata[573:572] == 2'b01 ? sw_0_1_7_down0 :
bitdata[573:572] == 2'b00 ? sw_0_1_24_up0 :
bitdata[573:572] == 2'b10 ? sw_0_1_26_up0 : 1'bx);
assign sw_0_1_25_up0 =
(bitdata[904:903] == 2'b00 ? cell_6_0 :
bitdata[904:903] == 2'b10 ? cell_7_0 :
bitdata[904:903] == 2'b01 ? cell_8_0 : 1'bx);
assign sw_0_1_26_down0 =
(bitdata[575:574] == 2'b01 ? sw_0_1_7_down0 :
bitdata[575:574] == 2'b00 ? sw_0_1_24_up0 :
bitdata[575:574] == 2'b10 ? sw_0_1_25_up0 : 1'bx);
assign sw_0_1_26_up0 =
(bitdata[908:908] == 1'b0 ? cell_0_0 :
bitdata[908:908] == 1'b1 ? cell_3_0 : 1'bx);
assign sw_0_1_2_down0 = sw_0_1_1_up0;
assign sw_0_1_2_up0 =
(bitdata[403:403] == 1'b0 ? sw_0_1_6_up0 :
bitdata[403:403] == 1'b1 ? sw_0_1_7_up0 : 1'bx);
assign sw_0_1_3_down0 =
(bitdata[377:376] == 2'b11 ? sw_0_1_1_down0 :
bitdata[377:376] == 2'b00 ? sw_0_1_4_up0 :
bitdata[377:376] == 2'b10 ? sw_0_1_5_up0 :
bitdata[377:376] == 2'b01 ? sw_0_1_5_up1 : 1'bx);
assign sw_0_1_3_down1 =
(bitdata[379:378] == 2'b11 ? sw_0_1_1_down0 :
bitdata[379:378] == 2'b00 ? sw_0_1_4_up0 :
bitdata[379:378] == 2'b10 ? sw_0_1_5_up0 :
bitdata[379:378] == 2'b01 ? sw_0_1_5_up1 : 1'bx);
assign sw_0_1_3_up0 =
(bitdata[410:406] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[410:406] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[410:406] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[410:406] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[410:406] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[410:406] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[410:406] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[410:406] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[410:406] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[410:406] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[410:406] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[410:406] == 5'b11010 ? sw_0_1_10_up0 :
bitdata[410:406] == 5'b00110 ? sw_0_1_10_up1 :
bitdata[410:406] == 5'b10110 ? sw_0_1_10_up2 :
bitdata[410:406] == 5'b01110 ? sw_0_1_11_up0 :
bitdata[410:406] == 5'b11110 ? sw_0_1_11_up1 :
bitdata[410:406] == 5'b00001 ? sw_0_1_11_up2 :
bitdata[410:406] == 5'b10001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_3_up1 =
(bitdata[415:411] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[415:411] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[415:411] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[415:411] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[415:411] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[415:411] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[415:411] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[415:411] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[415:411] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[415:411] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[415:411] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[415:411] == 5'b11010 ? sw_0_1_10_up0 :
bitdata[415:411] == 5'b00110 ? sw_0_1_10_up1 :
bitdata[415:411] == 5'b10110 ? sw_0_1_10_up2 :
bitdata[415:411] == 5'b01110 ? sw_0_1_11_up0 :
bitdata[415:411] == 5'b11110 ? sw_0_1_11_up1 :
bitdata[415:411] == 5'b00001 ? sw_0_1_11_up2 :
bitdata[415:411] == 5'b10001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_3_up2 =
(bitdata[420:416] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[420:416] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[420:416] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[420:416] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[420:416] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[420:416] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[420:416] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[420:416] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[420:416] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[420:416] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[420:416] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[420:416] == 5'b11010 ? sw_0_1_10_up0 :
bitdata[420:416] == 5'b00110 ? sw_0_1_10_up1 :
bitdata[420:416] == 5'b10110 ? sw_0_1_10_up2 :
bitdata[420:416] == 5'b01110 ? sw_0_1_11_up0 :
bitdata[420:416] == 5'b11110 ? sw_0_1_11_up1 :
bitdata[420:416] == 5'b00001 ? sw_0_1_11_up2 :
bitdata[420:416] == 5'b10001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_3_up3 =
(bitdata[425:421] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[425:421] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[425:421] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[425:421] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[425:421] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[425:421] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[425:421] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[425:421] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[425:421] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[425:421] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[425:421] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[425:421] == 5'b11010 ? sw_0_1_10_up0 :
bitdata[425:421] == 5'b00110 ? sw_0_1_10_up1 :
bitdata[425:421] == 5'b10110 ? sw_0_1_10_up2 :
bitdata[425:421] == 5'b01110 ? sw_0_1_11_up0 :
bitdata[425:421] == 5'b11110 ? sw_0_1_11_up1 :
bitdata[425:421] == 5'b00001 ? sw_0_1_11_up2 :
bitdata[425:421] == 5'b10001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_3_up4 =
(bitdata[430:426] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[430:426] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[430:426] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[430:426] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[430:426] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[430:426] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[430:426] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[430:426] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[430:426] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[430:426] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[430:426] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[430:426] == 5'b11010 ? sw_0_1_10_up0 :
bitdata[430:426] == 5'b00110 ? sw_0_1_10_up1 :
bitdata[430:426] == 5'b10110 ? sw_0_1_10_up2 :
bitdata[430:426] == 5'b01110 ? sw_0_1_11_up0 :
bitdata[430:426] == 5'b11110 ? sw_0_1_11_up1 :
bitdata[430:426] == 5'b00001 ? sw_0_1_11_up2 :
bitdata[430:426] == 5'b10001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_3_up5 =
(bitdata[435:431] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[435:431] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[435:431] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[435:431] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[435:431] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[435:431] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[435:431] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[435:431] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[435:431] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[435:431] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[435:431] == 5'b01010 ? sw_0_1_9_up0 :
bitdata[435:431] == 5'b11010 ? sw_0_1_10_up0 :
bitdata[435:431] == 5'b00110 ? sw_0_1_10_up1 :
bitdata[435:431] == 5'b10110 ? sw_0_1_10_up2 :
bitdata[435:431] == 5'b01110 ? sw_0_1_11_up0 :
bitdata[435:431] == 5'b11110 ? sw_0_1_11_up1 :
bitdata[435:431] == 5'b00001 ? sw_0_1_11_up2 :
bitdata[435:431] == 5'b10001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_4_down0 =
(bitdata[383:380] == 4'b0001 ? sw_0_1_1_down0 :
bitdata[383:380] == 4'b0000 ? sw_0_1_3_up0 :
bitdata[383:380] == 4'b1000 ? sw_0_1_3_up1 :
bitdata[383:380] == 4'b0100 ? sw_0_1_3_up2 :
bitdata[383:380] == 4'b1100 ? sw_0_1_3_up3 :
bitdata[383:380] == 4'b0010 ? sw_0_1_3_up4 :
bitdata[383:380] == 4'b1010 ? sw_0_1_3_up5 :
bitdata[383:380] == 4'b0110 ? sw_0_1_5_up0 :
bitdata[383:380] == 4'b1110 ? sw_0_1_5_up1 : 1'bx);
assign sw_0_1_4_down1 =
(bitdata[387:384] == 4'b0001 ? sw_0_1_1_down0 :
bitdata[387:384] == 4'b0000 ? sw_0_1_3_up0 :
bitdata[387:384] == 4'b1000 ? sw_0_1_3_up1 :
bitdata[387:384] == 4'b0100 ? sw_0_1_3_up2 :
bitdata[387:384] == 4'b1100 ? sw_0_1_3_up3 :
bitdata[387:384] == 4'b0010 ? sw_0_1_3_up4 :
bitdata[387:384] == 4'b1010 ? sw_0_1_3_up5 :
bitdata[387:384] == 4'b0110 ? sw_0_1_5_up0 :
bitdata[387:384] == 4'b1110 ? sw_0_1_5_up1 : 1'bx);
assign sw_0_1_4_up0 = sw_0_1_15_up0;
assign sw_0_1_5_down0 =
(bitdata[390:388] == 3'b111 ? sw_0_1_1_down0 :
bitdata[390:388] == 3'b000 ? sw_0_1_3_up0 :
bitdata[390:388] == 3'b100 ? sw_0_1_3_up1 :
bitdata[390:388] == 3'b010 ? sw_0_1_3_up2 :
bitdata[390:388] == 3'b110 ? sw_0_1_3_up3 :
bitdata[390:388] == 3'b001 ? sw_0_1_3_up4 :
bitdata[390:388] == 3'b101 ? sw_0_1_3_up5 :
bitdata[390:388] == 3'b011 ? sw_0_1_4_up0 : 1'bx);
assign sw_0_1_5_down1 =
(bitdata[393:391] == 3'b111 ? sw_0_1_1_down0 :
bitdata[393:391] == 3'b000 ? sw_0_1_3_up0 :
bitdata[393:391] == 3'b100 ? sw_0_1_3_up1 :
bitdata[393:391] == 3'b010 ? sw_0_1_3_up2 :
bitdata[393:391] == 3'b110 ? sw_0_1_3_up3 :
bitdata[393:391] == 3'b001 ? sw_0_1_3_up4 :
bitdata[393:391] == 3'b101 ? sw_0_1_3_up5 :
bitdata[393:391] == 3'b011 ? sw_0_1_4_up0 : 1'bx);
assign sw_0_1_5_down2 =
(bitdata[396:394] == 3'b111 ? sw_0_1_1_down0 :
bitdata[396:394] == 3'b000 ? sw_0_1_3_up0 :
bitdata[396:394] == 3'b100 ? sw_0_1_3_up1 :
bitdata[396:394] == 3'b010 ? sw_0_1_3_up2 :
bitdata[396:394] == 3'b110 ? sw_0_1_3_up3 :
bitdata[396:394] == 3'b001 ? sw_0_1_3_up4 :
bitdata[396:394] == 3'b101 ? sw_0_1_3_up5 :
bitdata[396:394] == 3'b011 ? sw_0_1_4_up0 : 1'bx);
assign sw_0_1_5_down3 =
(bitdata[399:397] == 3'b111 ? sw_0_1_1_down0 :
bitdata[399:397] == 3'b000 ? sw_0_1_3_up0 :
bitdata[399:397] == 3'b100 ? sw_0_1_3_up1 :
bitdata[399:397] == 3'b010 ? sw_0_1_3_up2 :
bitdata[399:397] == 3'b110 ? sw_0_1_3_up3 :
bitdata[399:397] == 3'b001 ? sw_0_1_3_up4 :
bitdata[399:397] == 3'b101 ? sw_0_1_3_up5 :
bitdata[399:397] == 3'b011 ? sw_0_1_4_up0 : 1'bx);
assign sw_0_1_5_down4 =
(bitdata[402:400] == 3'b111 ? sw_0_1_1_down0 :
bitdata[402:400] == 3'b000 ? sw_0_1_3_up0 :
bitdata[402:400] == 3'b100 ? sw_0_1_3_up1 :
bitdata[402:400] == 3'b010 ? sw_0_1_3_up2 :
bitdata[402:400] == 3'b110 ? sw_0_1_3_up3 :
bitdata[402:400] == 3'b001 ? sw_0_1_3_up4 :
bitdata[402:400] == 3'b101 ? sw_0_1_3_up5 :
bitdata[402:400] == 3'b011 ? sw_0_1_4_up0 : 1'bx);
assign sw_0_1_5_up0 =
(bitdata[526:524] == 3'b000 ? sw_0_1_16_up0 :
bitdata[526:524] == 3'b100 ? sw_0_1_16_up1 :
bitdata[526:524] == 3'b010 ? sw_0_1_17_up0 :
bitdata[526:524] == 3'b110 ? sw_0_1_18_up0 :
bitdata[526:524] == 3'b001 ? sw_0_1_19_up0 : 1'bx);
assign sw_0_1_5_up1 =
(bitdata[529:527] == 3'b000 ? sw_0_1_16_up0 :
bitdata[529:527] == 3'b100 ? sw_0_1_16_up1 :
bitdata[529:527] == 3'b010 ? sw_0_1_17_up0 :
bitdata[529:527] == 3'b110 ? sw_0_1_18_up0 :
bitdata[529:527] == 3'b001 ? sw_0_1_19_up0 : 1'bx);
assign sw_0_1_6_down0 =
(bitdata[404:404] == 1'b1 ? sw_0_1_2_down0 :
bitdata[404:404] == 1'b0 ? sw_0_1_7_up0 : 1'bx);
assign sw_0_1_6_up0 =
(bitdata[562:562] == 1'b0 ? sw_0_1_22_up0 :
bitdata[562:562] == 1'b1 ? sw_0_1_23_up0 : 1'bx);
assign sw_0_1_7_down0 =
(bitdata[405:405] == 1'b1 ? sw_0_1_2_down0 :
bitdata[405:405] == 1'b0 ? sw_0_1_6_up0 : 1'bx);
assign sw_0_1_7_up0 =
(bitdata[569:568] == 2'b00 ? sw_0_1_24_up0 :
bitdata[569:568] == 2'b10 ? sw_0_1_25_up0 :
bitdata[569:568] == 2'b01 ? sw_0_1_26_up0 : 1'bx);
assign sw_0_1_8_down0 =
(bitdata[439:436] == 4'b0001 ? sw_0_1_3_down0 :
bitdata[439:436] == 4'b1001 ? sw_0_1_3_down1 :
bitdata[439:436] == 4'b0000 ? sw_0_1_9_up0 :
bitdata[439:436] == 4'b1000 ? sw_0_1_10_up0 :
bitdata[439:436] == 4'b0100 ? sw_0_1_10_up1 :
bitdata[439:436] == 4'b1100 ? sw_0_1_10_up2 :
bitdata[439:436] == 4'b0010 ? sw_0_1_11_up0 :
bitdata[439:436] == 4'b1010 ? sw_0_1_11_up1 :
bitdata[439:436] == 4'b0110 ? sw_0_1_11_up2 :
bitdata[439:436] == 4'b1110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_8_down1 =
(bitdata[443:440] == 4'b0001 ? sw_0_1_3_down0 :
bitdata[443:440] == 4'b1001 ? sw_0_1_3_down1 :
bitdata[443:440] == 4'b0000 ? sw_0_1_9_up0 :
bitdata[443:440] == 4'b1000 ? sw_0_1_10_up0 :
bitdata[443:440] == 4'b0100 ? sw_0_1_10_up1 :
bitdata[443:440] == 4'b1100 ? sw_0_1_10_up2 :
bitdata[443:440] == 4'b0010 ? sw_0_1_11_up0 :
bitdata[443:440] == 4'b1010 ? sw_0_1_11_up1 :
bitdata[443:440] == 4'b0110 ? sw_0_1_11_up2 :
bitdata[443:440] == 4'b1110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_8_down2 =
(bitdata[447:444] == 4'b0001 ? sw_0_1_3_down0 :
bitdata[447:444] == 4'b1001 ? sw_0_1_3_down1 :
bitdata[447:444] == 4'b0000 ? sw_0_1_9_up0 :
bitdata[447:444] == 4'b1000 ? sw_0_1_10_up0 :
bitdata[447:444] == 4'b0100 ? sw_0_1_10_up1 :
bitdata[447:444] == 4'b1100 ? sw_0_1_10_up2 :
bitdata[447:444] == 4'b0010 ? sw_0_1_11_up0 :
bitdata[447:444] == 4'b1010 ? sw_0_1_11_up1 :
bitdata[447:444] == 4'b0110 ? sw_0_1_11_up2 :
bitdata[447:444] == 4'b1110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_8_down3 =
(bitdata[451:448] == 4'b0001 ? sw_0_1_3_down0 :
bitdata[451:448] == 4'b1001 ? sw_0_1_3_down1 :
bitdata[451:448] == 4'b0000 ? sw_0_1_9_up0 :
bitdata[451:448] == 4'b1000 ? sw_0_1_10_up0 :
bitdata[451:448] == 4'b0100 ? sw_0_1_10_up1 :
bitdata[451:448] == 4'b1100 ? sw_0_1_10_up2 :
bitdata[451:448] == 4'b0010 ? sw_0_1_11_up0 :
bitdata[451:448] == 4'b1010 ? sw_0_1_11_up1 :
bitdata[451:448] == 4'b0110 ? sw_0_1_11_up2 :
bitdata[451:448] == 4'b1110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_8_down4 =
(bitdata[455:452] == 4'b0001 ? sw_0_1_3_down0 :
bitdata[455:452] == 4'b1001 ? sw_0_1_3_down1 :
bitdata[455:452] == 4'b0000 ? sw_0_1_9_up0 :
bitdata[455:452] == 4'b1000 ? sw_0_1_10_up0 :
bitdata[455:452] == 4'b0100 ? sw_0_1_10_up1 :
bitdata[455:452] == 4'b1100 ? sw_0_1_10_up2 :
bitdata[455:452] == 4'b0010 ? sw_0_1_11_up0 :
bitdata[455:452] == 4'b1010 ? sw_0_1_11_up1 :
bitdata[455:452] == 4'b0110 ? sw_0_1_11_up2 :
bitdata[455:452] == 4'b1110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_8_down5 =
(bitdata[459:456] == 4'b0001 ? sw_0_1_3_down0 :
bitdata[459:456] == 4'b1001 ? sw_0_1_3_down1 :
bitdata[459:456] == 4'b0000 ? sw_0_1_9_up0 :
bitdata[459:456] == 4'b1000 ? sw_0_1_10_up0 :
bitdata[459:456] == 4'b0100 ? sw_0_1_10_up1 :
bitdata[459:456] == 4'b1100 ? sw_0_1_10_up2 :
bitdata[459:456] == 4'b0010 ? sw_0_1_11_up0 :
bitdata[459:456] == 4'b1010 ? sw_0_1_11_up1 :
bitdata[459:456] == 4'b0110 ? sw_0_1_11_up2 :
bitdata[459:456] == 4'b1110 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_8_up0 =
(bitdata[580:576] == 5'b00000 ? cell_80_6 :
bitdata[580:576] == 5'b10000 ? cell_80_7 :
bitdata[580:576] == 5'b01000 ? cell_80_8 :
bitdata[580:576] == 5'b11000 ? cell_80_9 :
bitdata[580:576] == 5'b00100 ? cell_80_10 :
bitdata[580:576] == 5'b10100 ? cell_80_11 :
bitdata[580:576] == 5'b01100 ? cell_80_12 :
bitdata[580:576] == 5'b11100 ? cell_80_13 :
bitdata[580:576] == 5'b00010 ? cell_80_14 :
bitdata[580:576] == 5'b10010 ? cell_80_15 :
bitdata[580:576] == 5'b01010 ? cell_81_10 :
bitdata[580:576] == 5'b11010 ? cell_81_11 :
bitdata[580:576] == 5'b00110 ? cell_81_12 :
bitdata[580:576] == 5'b10110 ? cell_81_13 :
bitdata[580:576] == 5'b01110 ? cell_81_14 :
bitdata[580:576] == 5'b11110 ? cell_81_15 :
bitdata[580:576] == 5'b00001 ? cell_81_16 :
bitdata[580:576] == 5'b10001 ? cell_81_17 :
bitdata[580:576] == 5'b01001 ? cell_81_18 :
bitdata[580:576] == 5'b11001 ? cell_81_19 :
bitdata[580:576] == 5'b00101 ? cell_81_20 :
bitdata[580:576] == 5'b10101 ? cell_81_21 :
bitdata[580:576] == 5'b01101 ? cell_81_22 :
bitdata[580:576] == 5'b11101 ? cell_81_23 :
bitdata[580:576] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up1 =
(bitdata[585:581] == 5'b00000 ? cell_80_6 :
bitdata[585:581] == 5'b10000 ? cell_80_7 :
bitdata[585:581] == 5'b01000 ? cell_80_8 :
bitdata[585:581] == 5'b11000 ? cell_80_9 :
bitdata[585:581] == 5'b00100 ? cell_80_10 :
bitdata[585:581] == 5'b10100 ? cell_80_11 :
bitdata[585:581] == 5'b01100 ? cell_80_12 :
bitdata[585:581] == 5'b11100 ? cell_80_13 :
bitdata[585:581] == 5'b00010 ? cell_80_14 :
bitdata[585:581] == 5'b10010 ? cell_80_15 :
bitdata[585:581] == 5'b01010 ? cell_81_10 :
bitdata[585:581] == 5'b11010 ? cell_81_11 :
bitdata[585:581] == 5'b00110 ? cell_81_12 :
bitdata[585:581] == 5'b10110 ? cell_81_13 :
bitdata[585:581] == 5'b01110 ? cell_81_14 :
bitdata[585:581] == 5'b11110 ? cell_81_15 :
bitdata[585:581] == 5'b00001 ? cell_81_16 :
bitdata[585:581] == 5'b10001 ? cell_81_17 :
bitdata[585:581] == 5'b01001 ? cell_81_18 :
bitdata[585:581] == 5'b11001 ? cell_81_19 :
bitdata[585:581] == 5'b00101 ? cell_81_20 :
bitdata[585:581] == 5'b10101 ? cell_81_21 :
bitdata[585:581] == 5'b01101 ? cell_81_22 :
bitdata[585:581] == 5'b11101 ? cell_81_23 :
bitdata[585:581] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up2 =
(bitdata[590:586] == 5'b00000 ? cell_80_6 :
bitdata[590:586] == 5'b10000 ? cell_80_7 :
bitdata[590:586] == 5'b01000 ? cell_80_8 :
bitdata[590:586] == 5'b11000 ? cell_80_9 :
bitdata[590:586] == 5'b00100 ? cell_80_10 :
bitdata[590:586] == 5'b10100 ? cell_80_11 :
bitdata[590:586] == 5'b01100 ? cell_80_12 :
bitdata[590:586] == 5'b11100 ? cell_80_13 :
bitdata[590:586] == 5'b00010 ? cell_80_14 :
bitdata[590:586] == 5'b10010 ? cell_80_15 :
bitdata[590:586] == 5'b01010 ? cell_81_10 :
bitdata[590:586] == 5'b11010 ? cell_81_11 :
bitdata[590:586] == 5'b00110 ? cell_81_12 :
bitdata[590:586] == 5'b10110 ? cell_81_13 :
bitdata[590:586] == 5'b01110 ? cell_81_14 :
bitdata[590:586] == 5'b11110 ? cell_81_15 :
bitdata[590:586] == 5'b00001 ? cell_81_16 :
bitdata[590:586] == 5'b10001 ? cell_81_17 :
bitdata[590:586] == 5'b01001 ? cell_81_18 :
bitdata[590:586] == 5'b11001 ? cell_81_19 :
bitdata[590:586] == 5'b00101 ? cell_81_20 :
bitdata[590:586] == 5'b10101 ? cell_81_21 :
bitdata[590:586] == 5'b01101 ? cell_81_22 :
bitdata[590:586] == 5'b11101 ? cell_81_23 :
bitdata[590:586] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up3 =
(bitdata[595:591] == 5'b00000 ? cell_80_6 :
bitdata[595:591] == 5'b10000 ? cell_80_7 :
bitdata[595:591] == 5'b01000 ? cell_80_8 :
bitdata[595:591] == 5'b11000 ? cell_80_9 :
bitdata[595:591] == 5'b00100 ? cell_80_10 :
bitdata[595:591] == 5'b10100 ? cell_80_11 :
bitdata[595:591] == 5'b01100 ? cell_80_12 :
bitdata[595:591] == 5'b11100 ? cell_80_13 :
bitdata[595:591] == 5'b00010 ? cell_80_14 :
bitdata[595:591] == 5'b10010 ? cell_80_15 :
bitdata[595:591] == 5'b01010 ? cell_81_10 :
bitdata[595:591] == 5'b11010 ? cell_81_11 :
bitdata[595:591] == 5'b00110 ? cell_81_12 :
bitdata[595:591] == 5'b10110 ? cell_81_13 :
bitdata[595:591] == 5'b01110 ? cell_81_14 :
bitdata[595:591] == 5'b11110 ? cell_81_15 :
bitdata[595:591] == 5'b00001 ? cell_81_16 :
bitdata[595:591] == 5'b10001 ? cell_81_17 :
bitdata[595:591] == 5'b01001 ? cell_81_18 :
bitdata[595:591] == 5'b11001 ? cell_81_19 :
bitdata[595:591] == 5'b00101 ? cell_81_20 :
bitdata[595:591] == 5'b10101 ? cell_81_21 :
bitdata[595:591] == 5'b01101 ? cell_81_22 :
bitdata[595:591] == 5'b11101 ? cell_81_23 :
bitdata[595:591] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up4 =
(bitdata[600:596] == 5'b00000 ? cell_80_6 :
bitdata[600:596] == 5'b10000 ? cell_80_7 :
bitdata[600:596] == 5'b01000 ? cell_80_8 :
bitdata[600:596] == 5'b11000 ? cell_80_9 :
bitdata[600:596] == 5'b00100 ? cell_80_10 :
bitdata[600:596] == 5'b10100 ? cell_80_11 :
bitdata[600:596] == 5'b01100 ? cell_80_12 :
bitdata[600:596] == 5'b11100 ? cell_80_13 :
bitdata[600:596] == 5'b00010 ? cell_80_14 :
bitdata[600:596] == 5'b10010 ? cell_80_15 :
bitdata[600:596] == 5'b01010 ? cell_81_10 :
bitdata[600:596] == 5'b11010 ? cell_81_11 :
bitdata[600:596] == 5'b00110 ? cell_81_12 :
bitdata[600:596] == 5'b10110 ? cell_81_13 :
bitdata[600:596] == 5'b01110 ? cell_81_14 :
bitdata[600:596] == 5'b11110 ? cell_81_15 :
bitdata[600:596] == 5'b00001 ? cell_81_16 :
bitdata[600:596] == 5'b10001 ? cell_81_17 :
bitdata[600:596] == 5'b01001 ? cell_81_18 :
bitdata[600:596] == 5'b11001 ? cell_81_19 :
bitdata[600:596] == 5'b00101 ? cell_81_20 :
bitdata[600:596] == 5'b10101 ? cell_81_21 :
bitdata[600:596] == 5'b01101 ? cell_81_22 :
bitdata[600:596] == 5'b11101 ? cell_81_23 :
bitdata[600:596] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up5 =
(bitdata[605:601] == 5'b00000 ? cell_80_6 :
bitdata[605:601] == 5'b10000 ? cell_80_7 :
bitdata[605:601] == 5'b01000 ? cell_80_8 :
bitdata[605:601] == 5'b11000 ? cell_80_9 :
bitdata[605:601] == 5'b00100 ? cell_80_10 :
bitdata[605:601] == 5'b10100 ? cell_80_11 :
bitdata[605:601] == 5'b01100 ? cell_80_12 :
bitdata[605:601] == 5'b11100 ? cell_80_13 :
bitdata[605:601] == 5'b00010 ? cell_80_14 :
bitdata[605:601] == 5'b10010 ? cell_80_15 :
bitdata[605:601] == 5'b01010 ? cell_81_10 :
bitdata[605:601] == 5'b11010 ? cell_81_11 :
bitdata[605:601] == 5'b00110 ? cell_81_12 :
bitdata[605:601] == 5'b10110 ? cell_81_13 :
bitdata[605:601] == 5'b01110 ? cell_81_14 :
bitdata[605:601] == 5'b11110 ? cell_81_15 :
bitdata[605:601] == 5'b00001 ? cell_81_16 :
bitdata[605:601] == 5'b10001 ? cell_81_17 :
bitdata[605:601] == 5'b01001 ? cell_81_18 :
bitdata[605:601] == 5'b11001 ? cell_81_19 :
bitdata[605:601] == 5'b00101 ? cell_81_20 :
bitdata[605:601] == 5'b10101 ? cell_81_21 :
bitdata[605:601] == 5'b01101 ? cell_81_22 :
bitdata[605:601] == 5'b11101 ? cell_81_23 :
bitdata[605:601] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up6 =
(bitdata[610:606] == 5'b00000 ? cell_80_6 :
bitdata[610:606] == 5'b10000 ? cell_80_7 :
bitdata[610:606] == 5'b01000 ? cell_80_8 :
bitdata[610:606] == 5'b11000 ? cell_80_9 :
bitdata[610:606] == 5'b00100 ? cell_80_10 :
bitdata[610:606] == 5'b10100 ? cell_80_11 :
bitdata[610:606] == 5'b01100 ? cell_80_12 :
bitdata[610:606] == 5'b11100 ? cell_80_13 :
bitdata[610:606] == 5'b00010 ? cell_80_14 :
bitdata[610:606] == 5'b10010 ? cell_80_15 :
bitdata[610:606] == 5'b01010 ? cell_81_10 :
bitdata[610:606] == 5'b11010 ? cell_81_11 :
bitdata[610:606] == 5'b00110 ? cell_81_12 :
bitdata[610:606] == 5'b10110 ? cell_81_13 :
bitdata[610:606] == 5'b01110 ? cell_81_14 :
bitdata[610:606] == 5'b11110 ? cell_81_15 :
bitdata[610:606] == 5'b00001 ? cell_81_16 :
bitdata[610:606] == 5'b10001 ? cell_81_17 :
bitdata[610:606] == 5'b01001 ? cell_81_18 :
bitdata[610:606] == 5'b11001 ? cell_81_19 :
bitdata[610:606] == 5'b00101 ? cell_81_20 :
bitdata[610:606] == 5'b10101 ? cell_81_21 :
bitdata[610:606] == 5'b01101 ? cell_81_22 :
bitdata[610:606] == 5'b11101 ? cell_81_23 :
bitdata[610:606] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up7 =
(bitdata[615:611] == 5'b00000 ? cell_80_6 :
bitdata[615:611] == 5'b10000 ? cell_80_7 :
bitdata[615:611] == 5'b01000 ? cell_80_8 :
bitdata[615:611] == 5'b11000 ? cell_80_9 :
bitdata[615:611] == 5'b00100 ? cell_80_10 :
bitdata[615:611] == 5'b10100 ? cell_80_11 :
bitdata[615:611] == 5'b01100 ? cell_80_12 :
bitdata[615:611] == 5'b11100 ? cell_80_13 :
bitdata[615:611] == 5'b00010 ? cell_80_14 :
bitdata[615:611] == 5'b10010 ? cell_80_15 :
bitdata[615:611] == 5'b01010 ? cell_81_10 :
bitdata[615:611] == 5'b11010 ? cell_81_11 :
bitdata[615:611] == 5'b00110 ? cell_81_12 :
bitdata[615:611] == 5'b10110 ? cell_81_13 :
bitdata[615:611] == 5'b01110 ? cell_81_14 :
bitdata[615:611] == 5'b11110 ? cell_81_15 :
bitdata[615:611] == 5'b00001 ? cell_81_16 :
bitdata[615:611] == 5'b10001 ? cell_81_17 :
bitdata[615:611] == 5'b01001 ? cell_81_18 :
bitdata[615:611] == 5'b11001 ? cell_81_19 :
bitdata[615:611] == 5'b00101 ? cell_81_20 :
bitdata[615:611] == 5'b10101 ? cell_81_21 :
bitdata[615:611] == 5'b01101 ? cell_81_22 :
bitdata[615:611] == 5'b11101 ? cell_81_23 :
bitdata[615:611] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up8 =
(bitdata[620:616] == 5'b00000 ? cell_80_6 :
bitdata[620:616] == 5'b10000 ? cell_80_7 :
bitdata[620:616] == 5'b01000 ? cell_80_8 :
bitdata[620:616] == 5'b11000 ? cell_80_9 :
bitdata[620:616] == 5'b00100 ? cell_80_10 :
bitdata[620:616] == 5'b10100 ? cell_80_11 :
bitdata[620:616] == 5'b01100 ? cell_80_12 :
bitdata[620:616] == 5'b11100 ? cell_80_13 :
bitdata[620:616] == 5'b00010 ? cell_80_14 :
bitdata[620:616] == 5'b10010 ? cell_80_15 :
bitdata[620:616] == 5'b01010 ? cell_81_10 :
bitdata[620:616] == 5'b11010 ? cell_81_11 :
bitdata[620:616] == 5'b00110 ? cell_81_12 :
bitdata[620:616] == 5'b10110 ? cell_81_13 :
bitdata[620:616] == 5'b01110 ? cell_81_14 :
bitdata[620:616] == 5'b11110 ? cell_81_15 :
bitdata[620:616] == 5'b00001 ? cell_81_16 :
bitdata[620:616] == 5'b10001 ? cell_81_17 :
bitdata[620:616] == 5'b01001 ? cell_81_18 :
bitdata[620:616] == 5'b11001 ? cell_81_19 :
bitdata[620:616] == 5'b00101 ? cell_81_20 :
bitdata[620:616] == 5'b10101 ? cell_81_21 :
bitdata[620:616] == 5'b01101 ? cell_81_22 :
bitdata[620:616] == 5'b11101 ? cell_81_23 :
bitdata[620:616] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_8_up9 =
(bitdata[625:621] == 5'b00000 ? cell_80_6 :
bitdata[625:621] == 5'b10000 ? cell_80_7 :
bitdata[625:621] == 5'b01000 ? cell_80_8 :
bitdata[625:621] == 5'b11000 ? cell_80_9 :
bitdata[625:621] == 5'b00100 ? cell_80_10 :
bitdata[625:621] == 5'b10100 ? cell_80_11 :
bitdata[625:621] == 5'b01100 ? cell_80_12 :
bitdata[625:621] == 5'b11100 ? cell_80_13 :
bitdata[625:621] == 5'b00010 ? cell_80_14 :
bitdata[625:621] == 5'b10010 ? cell_80_15 :
bitdata[625:621] == 5'b01010 ? cell_81_10 :
bitdata[625:621] == 5'b11010 ? cell_81_11 :
bitdata[625:621] == 5'b00110 ? cell_81_12 :
bitdata[625:621] == 5'b10110 ? cell_81_13 :
bitdata[625:621] == 5'b01110 ? cell_81_14 :
bitdata[625:621] == 5'b11110 ? cell_81_15 :
bitdata[625:621] == 5'b00001 ? cell_81_16 :
bitdata[625:621] == 5'b10001 ? cell_81_17 :
bitdata[625:621] == 5'b01001 ? cell_81_18 :
bitdata[625:621] == 5'b11001 ? cell_81_19 :
bitdata[625:621] == 5'b00101 ? cell_81_20 :
bitdata[625:621] == 5'b10101 ? cell_81_21 :
bitdata[625:621] == 5'b01101 ? cell_81_22 :
bitdata[625:621] == 5'b11101 ? cell_81_23 :
bitdata[625:621] == 5'b00011 ? cell_81_24 : 1'bx);
assign sw_0_1_9_down0 =
(bitdata[464:460] == 5'b10001 ? sw_0_1_3_down0 :
bitdata[464:460] == 5'b01001 ? sw_0_1_3_down1 :
bitdata[464:460] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[464:460] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[464:460] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[464:460] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[464:460] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[464:460] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[464:460] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[464:460] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[464:460] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[464:460] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[464:460] == 5'b01010 ? sw_0_1_10_up0 :
bitdata[464:460] == 5'b11010 ? sw_0_1_10_up1 :
bitdata[464:460] == 5'b00110 ? sw_0_1_10_up2 :
bitdata[464:460] == 5'b10110 ? sw_0_1_11_up0 :
bitdata[464:460] == 5'b01110 ? sw_0_1_11_up1 :
bitdata[464:460] == 5'b11110 ? sw_0_1_11_up2 :
bitdata[464:460] == 5'b00001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_9_down1 =
(bitdata[469:465] == 5'b10001 ? sw_0_1_3_down0 :
bitdata[469:465] == 5'b01001 ? sw_0_1_3_down1 :
bitdata[469:465] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[469:465] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[469:465] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[469:465] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[469:465] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[469:465] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[469:465] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[469:465] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[469:465] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[469:465] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[469:465] == 5'b01010 ? sw_0_1_10_up0 :
bitdata[469:465] == 5'b11010 ? sw_0_1_10_up1 :
bitdata[469:465] == 5'b00110 ? sw_0_1_10_up2 :
bitdata[469:465] == 5'b10110 ? sw_0_1_11_up0 :
bitdata[469:465] == 5'b01110 ? sw_0_1_11_up1 :
bitdata[469:465] == 5'b11110 ? sw_0_1_11_up2 :
bitdata[469:465] == 5'b00001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_9_down2 =
(bitdata[474:470] == 5'b10001 ? sw_0_1_3_down0 :
bitdata[474:470] == 5'b01001 ? sw_0_1_3_down1 :
bitdata[474:470] == 5'b00000 ? sw_0_1_8_up0 :
bitdata[474:470] == 5'b10000 ? sw_0_1_8_up1 :
bitdata[474:470] == 5'b01000 ? sw_0_1_8_up2 :
bitdata[474:470] == 5'b11000 ? sw_0_1_8_up3 :
bitdata[474:470] == 5'b00100 ? sw_0_1_8_up4 :
bitdata[474:470] == 5'b10100 ? sw_0_1_8_up5 :
bitdata[474:470] == 5'b01100 ? sw_0_1_8_up6 :
bitdata[474:470] == 5'b11100 ? sw_0_1_8_up7 :
bitdata[474:470] == 5'b00010 ? sw_0_1_8_up8 :
bitdata[474:470] == 5'b10010 ? sw_0_1_8_up9 :
bitdata[474:470] == 5'b01010 ? sw_0_1_10_up0 :
bitdata[474:470] == 5'b11010 ? sw_0_1_10_up1 :
bitdata[474:470] == 5'b00110 ? sw_0_1_10_up2 :
bitdata[474:470] == 5'b10110 ? sw_0_1_11_up0 :
bitdata[474:470] == 5'b01110 ? sw_0_1_11_up1 :
bitdata[474:470] == 5'b11110 ? sw_0_1_11_up2 :
bitdata[474:470] == 5'b00001 ? sw_0_1_11_up3 : 1'bx);
assign sw_0_1_9_up0 = cell_43_0;
assign sw_1_0_1_down0 = sw_1_0_2_up0;
assign sw_1_0_1_up0 =
(bitdata[912:911] == 2'b00 ? sw_1_0_3_up0 :
bitdata[912:911] == 2'b10 ? sw_1_0_4_up0 :
bitdata[912:911] == 2'b01 ? sw_1_0_4_up1 :
bitdata[912:911] == 2'b11 ? sw_1_0_5_up0 : 8'bx);
assign sw_1_0_2_down0 = sw_1_0_1_up0;
assign sw_1_0_2_up0 =
(bitdata[921:921] == 1'b0 ? sw_1_0_6_up0 :
bitdata[921:921] == 1'b1 ? sw_1_0_7_up0 : 8'bx);
assign sw_1_0_3_down0 =
(bitdata[914:913] == 2'b11 ? sw_1_0_1_down0 :
bitdata[914:913] == 2'b00 ? sw_1_0_4_up0 :
bitdata[914:913] == 2'b10 ? sw_1_0_4_up1 :
bitdata[914:913] == 2'b01 ? sw_1_0_5_up0 : 8'bx);
assign sw_1_0_3_down1 =
(bitdata[916:915] == 2'b11 ? sw_1_0_1_down0 :
bitdata[916:915] == 2'b00 ? sw_1_0_4_up0 :
bitdata[916:915] == 2'b10 ? sw_1_0_4_up1 :
bitdata[916:915] == 2'b01 ? sw_1_0_5_up0 : 8'bx);
assign sw_1_0_3_up0 =
(bitdata[924:923] == 2'b00 ? cell_73_7 :
bitdata[924:923] == 2'b10 ? cell_87_0 :
bitdata[924:923] == 2'b01 ? cell_89_0 : 8'bx);
assign sw_1_0_4_down0 =
(bitdata[918:917] == 2'b01 ? sw_1_0_1_down0 :
bitdata[918:917] == 2'b00 ? sw_1_0_3_up0 :
bitdata[918:917] == 2'b10 ? sw_1_0_5_up0 : 8'bx);
assign sw_1_0_4_up0 =
(bitdata[941:940] == 2'b00 ? cell_74_3 :
bitdata[941:940] == 2'b10 ? cell_84_0 :
bitdata[941:940] == 2'b01 ? cell_85_0 : 8'bx);
assign sw_1_0_4_up1 =
(bitdata[943:942] == 2'b00 ? cell_74_3 :
bitdata[943:942] == 2'b10 ? cell_84_0 :
bitdata[943:942] == 2'b01 ? cell_85_0 : 8'bx);
assign sw_1_0_5_down0 =
(bitdata[920:919] == 2'b11 ? sw_1_0_1_down0 :
bitdata[920:919] == 2'b00 ? sw_1_0_3_up0 :
bitdata[920:919] == 2'b10 ? sw_1_0_4_up0 :
bitdata[920:919] == 2'b01 ? sw_1_0_4_up1 : 8'bx);
assign sw_1_0_5_up0 =
(bitdata[951:951] == 1'b0 ? cell_75_3 :
bitdata[951:951] == 1'b1 ? cell_86_0 : 8'bx);
assign sw_1_0_6_down0 =
(bitdata[922:922] == 1'b1 ? sw_1_0_2_down0 :
bitdata[922:922] == 1'b0 ? sw_1_0_7_up0 : 8'bx);
assign sw_1_0_6_up0 =
(bitdata[958:958] == 1'b0 ? cell_69_1 :
bitdata[958:958] == 1'b1 ? cell_70_1 : 8'bx);
assign sw_1_0_7_up0 =
(bitdata[972:971] == 2'b00 ? cell_5_0 :
bitdata[972:971] == 2'b10 ? cell_38_0 :
bitdata[972:971] == 2'b01 ? cell_88_0 : 8'bx);
assign sw_1_1_1_down0 = sw_1_1_2_up0;
assign sw_1_1_1_up0 =
(bitdata[974:973] == 2'b00 ? sw_1_1_3_up0 :
bitdata[974:973] == 2'b10 ? sw_1_1_4_up0 :
bitdata[974:973] == 2'b01 ? sw_1_1_4_up1 :
bitdata[974:973] == 2'b11 ? sw_1_1_5_up0 : 8'bx);
assign sw_1_1_2_down0 = sw_1_1_1_up0;
assign sw_1_1_2_up0 = sw_1_1_6_up0;
assign sw_1_1_3_down0 =
(bitdata[976:975] == 2'b11 ? sw_1_1_1_down0 :
bitdata[976:975] == 2'b00 ? sw_1_1_4_up0 :
bitdata[976:975] == 2'b10 ? sw_1_1_4_up1 :
bitdata[976:975] == 2'b01 ? sw_1_1_5_up0 : 8'bx);
assign sw_1_1_3_up0 =
(bitdata[985:984] == 2'b00 ? cell_74_3 :
bitdata[985:984] == 2'b10 ? cell_86_0 :
bitdata[985:984] == 2'b01 ? cell_87_0 :
bitdata[985:984] == 2'b11 ? cell_89_0 : 8'bx);
assign sw_1_1_4_down0 =
(bitdata[978:977] == 2'b01 ? sw_1_1_1_down0 :
bitdata[978:977] == 2'b00 ? sw_1_1_3_up0 :
bitdata[978:977] == 2'b10 ? sw_1_1_5_up0 : 8'bx);
assign sw_1_1_4_up0 =
(bitdata[992:992] == 1'b0 ? cell_84_0 :
bitdata[992:992] == 1'b1 ? cell_85_0 : 8'bx);
assign sw_1_1_4_up1 =
(bitdata[993:993] == 1'b0 ? cell_84_0 :
bitdata[993:993] == 1'b1 ? cell_85_0 : 8'bx);
assign sw_1_1_5_down0 =
(bitdata[980:979] == 2'b11 ? sw_1_1_1_down0 :
bitdata[980:979] == 2'b00 ? sw_1_1_3_up0 :
bitdata[980:979] == 2'b10 ? sw_1_1_4_up0 :
bitdata[980:979] == 2'b01 ? sw_1_1_4_up1 : 8'bx);
assign sw_1_1_5_down1 =
(bitdata[982:981] == 2'b11 ? sw_1_1_1_down0 :
bitdata[982:981] == 2'b00 ? sw_1_1_3_up0 :
bitdata[982:981] == 2'b10 ? sw_1_1_4_up0 :
bitdata[982:981] == 2'b01 ? sw_1_1_4_up1 : 8'bx);
assign sw_1_1_5_up0 =
(bitdata[1003:1002] == 2'b00 ? cell_73_7 :
bitdata[1003:1002] == 2'b10 ? cell_75_3 :
bitdata[1003:1002] == 2'b01 ? cell_88_0 : 8'bx);
assign sw_1_1_6_down0 = sw_1_1_2_down0;
assign sw_1_1_6_up0 =
(bitdata[1023:1022] == 2'b00 ? cell_5_0 :
bitdata[1023:1022] == 2'b10 ? cell_38_0 :
bitdata[1023:1022] == 2'b01 ? cell_69_1 :
bitdata[1023:1022] == 2'b11 ? cell_70_1 : 8'bx);
assign sw_1_1_7_down0 =
(bitdata[983:983] == 1'b1 ? sw_1_1_2_down0 :
bitdata[983:983] == 1'b0 ? sw_1_1_6_up0 : 8'bx);
assign sw_2_0_1_down0 = sw_2_0_2_up0;
assign sw_2_0_1_up0 =
(bitdata[1034:1033] == 2'b00 ? sw_2_0_3_up0 :
bitdata[1034:1033] == 2'b10 ? sw_2_0_4_up0 :
bitdata[1034:1033] == 2'b01 ? sw_2_0_5_up0 : 16'bx);
assign sw_2_0_2_down0 = sw_2_0_1_up0;
assign sw_2_0_2_up0 =
(bitdata[1042:1041] == 2'b00 ? sw_2_0_6_up0 :
bitdata[1042:1041] == 2'b10 ? sw_2_0_7_up0 :
bitdata[1042:1041] == 2'b01 ? sw_2_0_8_up0 : 16'bx);
assign sw_2_0_3_down0 =
(bitdata[1036:1035] == 2'b01 ? sw_2_0_1_down0 :
bitdata[1036:1035] == 2'b00 ? sw_2_0_4_up0 :
bitdata[1036:1035] == 2'b10 ? sw_2_0_5_up0 : 16'bx);
assign sw_2_0_3_up0 =
(bitdata[1051:1049] == 3'b000 ? cell_62_5 :
bitdata[1051:1049] == 3'b100 ? cell_63_6 :
bitdata[1051:1049] == 3'b010 ? cell_63_7 :
bitdata[1051:1049] == 3'b110 ? cell_93_0 :
bitdata[1051:1049] == 3'b001 ? cell_94_0 : 16'bx);
assign sw_2_0_4_down0 =
(bitdata[1038:1037] == 2'b01 ? sw_2_0_1_down0 :
bitdata[1038:1037] == 2'b00 ? sw_2_0_3_up0 :
bitdata[1038:1037] == 2'b10 ? sw_2_0_5_up0 : 16'bx);
assign sw_2_0_4_up0 =
(bitdata[1062:1061] == 2'b00 ? cell_61_5 :
bitdata[1062:1061] == 2'b10 ? cell_79_3 :
bitdata[1062:1061] == 2'b01 ? cell_91_0 : 16'bx);
assign sw_2_0_5_down0 =
(bitdata[1040:1039] == 2'b01 ? sw_2_0_1_down0 :
bitdata[1040:1039] == 2'b00 ? sw_2_0_3_up0 :
bitdata[1040:1039] == 2'b10 ? sw_2_0_4_up0 : 16'bx);
assign sw_2_0_5_up0 =
(bitdata[1073:1072] == 2'b00 ? cell_67_1 :
bitdata[1073:1072] == 2'b10 ? cell_72_3 :
bitdata[1073:1072] == 2'b01 ? cell_77_2 :
bitdata[1073:1072] == 2'b11 ? cell_78_3 : 16'bx);
assign sw_2_0_6_down0 =
(bitdata[1044:1043] == 2'b01 ? sw_2_0_2_down0 :
bitdata[1044:1043] == 2'b00 ? sw_2_0_7_up0 :
bitdata[1044:1043] == 2'b10 ? sw_2_0_8_up0 : 16'bx);
assign sw_2_0_6_up0 =
(bitdata[1091:1089] == 3'b000 ? cell_64_6 :
bitdata[1091:1089] == 3'b100 ? cell_64_7 :
bitdata[1091:1089] == 3'b010 ? cell_76_2 :
bitdata[1091:1089] == 3'b110 ? cell_92_0 :
bitdata[1091:1089] == 3'b001 ? cell_95_0 : 16'bx);
assign sw_2_0_7_down0 =
(bitdata[1046:1045] == 2'b01 ? sw_2_0_2_down0 :
bitdata[1046:1045] == 2'b00 ? sw_2_0_6_up0 :
bitdata[1046:1045] == 2'b10 ? sw_2_0_8_up0 : 16'bx);
assign sw_2_0_7_up0 =
(bitdata[1099:1098] == 2'b00 ? cell_65_2 :
bitdata[1099:1098] == 2'b10 ? cell_66_1 :
bitdata[1099:1098] == 2'b01 ? cell_71_3 : 16'bx);
assign sw_2_0_8_down0 =
(bitdata[1048:1047] == 2'b01 ? sw_2_0_2_down0 :
bitdata[1048:1047] == 2'b00 ? sw_2_0_6_up0 :
bitdata[1048:1047] == 2'b10 ? sw_2_0_7_up0 : 16'bx);
assign sw_2_0_8_up0 =
(bitdata[1114:1113] == 2'b00 ? cell_2_0 :
bitdata[1114:1113] == 2'b10 ? cell_68_1 :
bitdata[1114:1113] == 2'b01 ? cell_90_0 : 16'bx);
assign sw_2_1_1_down0 = sw_2_1_2_up0;
assign sw_2_1_1_up0 =
(bitdata[1118:1117] == 2'b00 ? sw_2_1_3_up0 :
bitdata[1118:1117] == 2'b10 ? sw_2_1_4_up0 :
bitdata[1118:1117] == 2'b01 ? sw_2_1_5_up0 : 16'bx);
assign sw_2_1_2_down0 = sw_2_1_1_up0;
assign sw_2_1_2_up0 =
(bitdata[1126:1125] == 2'b00 ? sw_2_1_6_up0 :
bitdata[1126:1125] == 2'b10 ? sw_2_1_6_up1 :
bitdata[1126:1125] == 2'b01 ? sw_2_1_7_up0 :
bitdata[1126:1125] == 2'b11 ? sw_2_1_8_up0 : 16'bx);
assign sw_2_1_3_down0 =
(bitdata[1120:1119] == 2'b01 ? sw_2_1_1_down0 :
bitdata[1120:1119] == 2'b00 ? sw_2_1_4_up0 :
bitdata[1120:1119] == 2'b10 ? sw_2_1_5_up0 : 16'bx);
assign sw_2_1_3_up0 =
(bitdata[1135:1135] == 1'b0 ? cell_94_0 :
bitdata[1135:1135] == 1'b1 ? cell_95_0 : 16'bx);
assign sw_2_1_4_down0 =
(bitdata[1122:1121] == 2'b01 ? sw_2_1_1_down0 :
bitdata[1122:1121] == 2'b00 ? sw_2_1_3_up0 :
bitdata[1122:1121] == 2'b10 ? sw_2_1_5_up0 : 16'bx);
assign sw_2_1_4_up0 =
(bitdata[1141:1140] == 2'b00 ? cell_71_3 :
bitdata[1141:1140] == 2'b10 ? cell_78_3 :
bitdata[1141:1140] == 2'b01 ? cell_92_0 :
bitdata[1141:1140] == 2'b11 ? cell_93_0 : 16'bx);
assign sw_2_1_5_down0 =
(bitdata[1124:1123] == 2'b01 ? sw_2_1_1_down0 :
bitdata[1124:1123] == 2'b00 ? sw_2_1_3_up0 :
bitdata[1124:1123] == 2'b10 ? sw_2_1_4_up0 : 16'bx);
assign sw_2_1_5_up0 =
(bitdata[1156:1154] == 3'b000 ? cell_63_6 :
bitdata[1156:1154] == 3'b100 ? cell_63_7 :
bitdata[1156:1154] == 3'b010 ? cell_79_3 :
bitdata[1156:1154] == 3'b110 ? cell_90_0 :
bitdata[1156:1154] == 3'b001 ? cell_91_0 : 16'bx);
assign sw_2_1_6_down0 =
(bitdata[1128:1127] == 2'b01 ? sw_2_1_2_down0 :
bitdata[1128:1127] == 2'b00 ? sw_2_1_7_up0 :
bitdata[1128:1127] == 2'b10 ? sw_2_1_8_up0 : 16'bx);
assign sw_2_1_6_up0 =
(bitdata[1170:1169] == 2'b00 ? cell_67_1 :
bitdata[1170:1169] == 2'b10 ? cell_68_1 :
bitdata[1170:1169] == 2'b01 ? cell_72_3 :
bitdata[1170:1169] == 2'b11 ? cell_77_2 : 16'bx);
assign sw_2_1_6_up1 =
(bitdata[1172:1171] == 2'b00 ? cell_67_1 :
bitdata[1172:1171] == 2'b10 ? cell_68_1 :
bitdata[1172:1171] == 2'b01 ? cell_72_3 :
bitdata[1172:1171] == 2'b11 ? cell_77_2 : 16'bx);
assign sw_2_1_7_down0 =
(bitdata[1130:1129] == 2'b11 ? sw_2_1_2_down0 :
bitdata[1130:1129] == 2'b00 ? sw_2_1_6_up0 :
bitdata[1130:1129] == 2'b10 ? sw_2_1_6_up1 :
bitdata[1130:1129] == 2'b01 ? sw_2_1_8_up0 : 16'bx);
assign sw_2_1_7_down1 =
(bitdata[1132:1131] == 2'b11 ? sw_2_1_2_down0 :
bitdata[1132:1131] == 2'b00 ? sw_2_1_6_up0 :
bitdata[1132:1131] == 2'b10 ? sw_2_1_6_up1 :
bitdata[1132:1131] == 2'b01 ? sw_2_1_8_up0 : 16'bx);
assign sw_2_1_7_up0 =
(bitdata[1186:1185] == 2'b00 ? cell_2_0 :
bitdata[1186:1185] == 2'b10 ? cell_65_2 :
bitdata[1186:1185] == 2'b01 ? cell_66_1 :
bitdata[1186:1185] == 2'b11 ? cell_76_2 : 16'bx);
assign sw_2_1_8_down0 =
(bitdata[1134:1133] == 2'b11 ? sw_2_1_2_down0 :
bitdata[1134:1133] == 2'b00 ? sw_2_1_6_up0 :
bitdata[1134:1133] == 2'b10 ? sw_2_1_6_up1 :
bitdata[1134:1133] == 2'b01 ? sw_2_1_7_up0 : 16'bx);
assign sw_2_1_8_up0 =
(bitdata[1197:1196] == 2'b00 ? cell_61_5 :
bitdata[1197:1196] == 2'b10 ? cell_62_5 :
bitdata[1197:1196] == 2'b01 ? cell_64_6 :
bitdata[1197:1196] == 2'b11 ? cell_64_7 : 16'bx);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_adc_8c (
// adc interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_frame_p,
adc_frame_n,
// dma interface
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
// delay clock (200MHz)
delay_clk,
// debug interface
dma_dbg_data,
dma_dbg_trigger,
// debug interface
adc_dbg_data,
adc_dbg_trigger,
// monitor signals
adc_clk,
adc_mon_valid,
adc_mon_data);
// adc interface
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_frame_p;
input adc_frame_n;
// dma interface
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// delay clock (200MHz)
input delay_clk;
// debug interface
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
// debug interface
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
// monitor signals
output adc_clk;
output adc_mon_valid;
output [143:0] adc_mon_data;
reg up_capture = 'd0;
reg [15:0] up_capture_count = 'd0;
reg up_dma_unf_hold = 'd0;
reg up_dma_ovf_hold = 'd0;
reg up_dma_status = 'd0;
reg [ 7:0] up_adc_pn_oos_hold = 'd0;
reg [ 7:0] up_adc_pn_err_hold = 'd0;
reg up_adc_err_hold = 'd0;
reg [ 7:0] up_pn_type = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
reg up_dma_ovf_m1 = 'd0;
reg up_dma_ovf_m2 = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf_m1 = 'd0;
reg up_dma_unf_m2 = 'd0;
reg up_dma_unf = 'd0;
reg up_dma_complete_m1 = 'd0;
reg up_dma_complete_m2 = 'd0;
reg up_dma_complete_m3 = 'd0;
reg up_dma_complete = 'd0;
reg up_serdes_preset = 'd0;
reg up_adc_err_m1 = 'd0;
reg up_adc_err_m2 = 'd0;
reg up_adc_err = 'd0;
reg [ 7:0] up_adc_pn_oos_m1 = 'd0;
reg [ 7:0] up_adc_pn_oos_m2 = 'd0;
reg [ 7:0] up_adc_pn_oos = 'd0;
reg [ 7:0] up_adc_pn_err_m1 = 'd0;
reg [ 7:0] up_adc_pn_err_m2 = 'd0;
reg [ 7:0] up_adc_pn_err = 'd0;
wire up_wr_s;
wire up_ack_s;
wire dma_ovf_s;
wire dma_unf_s;
wire dma_complete_s;
wire adc_valid_s;
wire [63:0] adc_data_s;
wire adc_err_s;
wire [ 7:0] adc_pn_oos_s;
wire [ 7:0] adc_pn_err_s;
// processor control signals
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_capture <= 'd0;
up_capture_count <= 'd0;
up_dma_unf_hold <= 'd0;
up_dma_ovf_hold <= 'd0;
up_dma_status <= 'd0;
up_adc_pn_oos_hold <= 'd0;
up_adc_pn_err_hold <= 'd0;
up_adc_err_hold <= 'd0;
up_pn_type <= 'd0;
end else begin
if ((up_addr == 5'h03) && (up_wr_s == 1'b1)) begin
up_capture <= up_wdata[16];
up_capture_count <= up_wdata[15:0];
end
if (up_dma_unf == 1'b1) begin
up_dma_unf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_dma_unf_hold <= up_dma_unf_hold & ~up_wdata[2];
end
if (up_dma_ovf == 1'b1) begin
up_dma_ovf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_dma_ovf_hold <= up_dma_ovf_hold & ~up_wdata[2];
end
if (up_dma_complete == 1'b1) begin
up_dma_status <= 1'b0;
end else if ((up_addr == 5'h03) && (up_wr_s == 1'b1) && (up_dma_status == 1'b0)) begin
up_dma_status <= up_wdata[16];
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_oos_hold <= up_adc_pn_oos_hold & ~up_wdata[7:0];
end else begin
up_adc_pn_oos_hold <= up_adc_pn_oos_hold | up_adc_pn_oos;
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_err_hold <= up_adc_pn_err_hold & ~up_wdata[15:8];
end else begin
up_adc_pn_err_hold <= up_adc_pn_err_hold | up_adc_pn_err;
end
if (up_adc_err == 1'b1) begin
up_adc_err_hold <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_err_hold <= up_adc_err_hold & ~up_wdata[0];
end
if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_pn_type <= up_wdata[7:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010062;
5'h03: up_rdata <= {15'd0, up_capture, up_capture_count};
5'h04: up_rdata <= {29'd0, up_dma_unf_hold, up_dma_ovf_hold, up_dma_status};
5'h05: up_rdata <= {15'd0, up_adc_err_hold, up_adc_pn_err_hold, up_adc_pn_oos_hold};
5'h09: up_rdata <= {24'd0, up_pn_type};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// transfer status signals to processor clock domain
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_ovf_m1 <= 'd0;
up_dma_ovf_m2 <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf_m1 <= 'd0;
up_dma_unf_m2 <= 'd0;
up_dma_unf <= 'd0;
up_dma_complete_m1 <= 'd0;
up_dma_complete_m2 <= 'd0;
up_dma_complete_m3 <= 'd0;
up_dma_complete <= 'd0;
end else begin
up_dma_ovf_m1 <= dma_ovf_s;
up_dma_ovf_m2 <= up_dma_ovf_m1;
up_dma_ovf <= up_dma_ovf_m2;
up_dma_unf_m1 <= dma_unf_s;
up_dma_unf_m2 <= up_dma_unf_m1;
up_dma_unf <= up_dma_unf_m2;
up_dma_complete_m1 <= dma_complete_s;
up_dma_complete_m2 <= up_dma_complete_m1;
up_dma_complete_m3 <= up_dma_complete_m2;
up_dma_complete <= up_dma_complete_m3 ^ up_dma_complete_m2;
end
end
// transfer status signals to processor clock domain
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_serdes_preset <= 'd1;
up_adc_err_m1 <= 'd0;
up_adc_err_m2 <= 'd0;
up_adc_err <= 'd0;
up_adc_pn_oos_m1 <= 'd0;
up_adc_pn_oos_m2 <= 'd0;
up_adc_pn_oos <= 'd0;
up_adc_pn_err_m1 <= 'd0;
up_adc_pn_err_m2 <= 'd0;
up_adc_pn_err <= 'd0;
end else begin
up_serdes_preset <= 'd0;
up_adc_err_m1 <= adc_err_s;
up_adc_err_m2 <= up_adc_err_m1;
up_adc_err <= up_adc_err_m2;
up_adc_pn_oos_m1 <= adc_pn_oos_s;
up_adc_pn_oos_m2 <= up_adc_pn_oos_m1;
up_adc_pn_oos <= up_adc_pn_oos_m2;
up_adc_pn_err_m1 <= adc_pn_err_s;
up_adc_pn_err_m2 <= up_adc_pn_err_m1;
up_adc_pn_err <= up_adc_pn_err_m2;
end
end
// dma write interface
cf_dma_wr i_dma_wr (
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_master_capture (up_capture),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_complete (dma_complete_s),
.up_capture_count (up_capture_count),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger));
// adc capture interface
cf_adc_if i_adc_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_frame_p (adc_frame_p),
.adc_frame_n (adc_frame_n),
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_err (adc_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.up_serdes_preset (up_serdes_preset),
.up_pn_type (up_pn_type),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module intermediator_tb;
parameter INTERMEDIATOR_DEPTH = 1024;
parameter LOG2_INTERMEDIATOR_DEPTH = log2(INTERMEDIATOR_DEPTH - 1);
reg clk, rst, wr0;
reg [LOG2_INTERMEDIATOR_DEPTH - 1:0] row0;
reg [65:0] v0;
reg wr1;
reg [LOG2_INTERMEDIATOR_DEPTH - 1:0] row1;
reg [65:0] v1;
wire push_to_adder;
wire [LOG2_INTERMEDIATOR_DEPTH - 1:0] row_to_adder;
wire [65:0] v0_to_adder;
wire [65:0] v1_to_adder;
wire push_to_y;
wire [65:0] v_to_y;
reg eof;
intermediator #(8) dut(clk, rst, wr0, row0, v0, wr1, row1, v1, push_to_adder, row_to_adder, v0_to_adder, v1_to_adder, push_to_y, v_to_y, eof);
initial begin
clk = 0;
forever #5 clk = !clk;
end
initial begin
#3000 $display("watchdog reached");
$finish;
end
integer i;
initial begin
rst = 1;
wr0 = 0;
row0 = 0;
v0 = 0;
wr1 = 0;
row1 = 0;
v1 = 0;
eof = 0;
#100 rst = 0;
#100 wr0 = 1;
#10 wr0 = 0;
#10 wr0 = 1;
#10 wr0 = 0;
//TODO: figure out
for(i = 0; i < 8; i = i + 1) begin
wr0 = 1;
row0 = i;
#10;
end
wr0 = 0;
#2000 wr0 = 1;
row0 = 4;
wr1 = 1;
row1 = 5;
#10 wr0 = 0;
wr1 = 0;
#100 wr0 = 1;
row0 = 4;
wr1 = 1;
row1 = 4;
#10 wr0 = 0;
wr1 = 0;
end
integer store_count;
initial store_count = 0;
integer adder_count;
initial adder_count = 0;
always @(posedge clk) begin
//$display("debug: ");
//$display("%d", push_to_adder);
if(dut.p0_stage_1)
$display("p0_stage_1");
if(dut.p0_stage_2) begin
$display("p0_stage_2");
$display("r0_stage_2: %d", dut.r0_stage_2);
$display("occupency0_stage_2_comb: %d", dut.occupency0_stage_2_comb);
end
if(dut.p0_stage_3) begin
$display("p0_stage_3");
$display("occupency0_stage_3: %d", dut.occupency0_stage_3);
end
if(dut.to_store_stage_2_comb)
$display("to_store_stage_2_comb");
//$display("to_store_stage_2_comb: %d", dut.to_store_stage_2_comb);
if(dut.p0_retrieve_from_intermediator_stage_4)
$display("p0_retrieve_stage_4");
if(dut.p0_store_to_intermediator_stage_4)
$display("p0_store_stage_4");
if(dut.p0_retrieve_from_intermediator_stage_4 || dut.p0_store_to_intermediator_stage_4) begin
end
if(dut.p0_stage_5)
$display("p0_stage_5");
if(dut.p0_stage_6)
$display("p0_stage_6");
if(dut.row_cmp_stage_3)
$display("row_cmp_stage_3");
//$display("p1_stage3: %d", dut.p1_stage_3);
if(push_to_adder) begin
$display("pushed to adder count: %d time: %d", adder_count, $time);
adder_count = adder_count + 1;
end
if(push_to_y) begin
$display("pushed to y count: %d", store_count);
store_count = store_count + 1;
//$finish;
end
end
`include "common.vh"
endmodule
|
// "flop_it-c.v"
// @vcs-flags@ -P pli.tab
`timescale 1ps / 1ps
// `include "standard.v"
`include "standard.v-wrap"
`include "clkgen.v"
//-----------------------------------------------------------------------------
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg a;
wire clk;
wire z;
clk_gen #(.HALF_PERIOD(50)) cg(clk);
initial
begin
// @haco@ flop_it.haco-c
$prsim("flop_it.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$to_prsim("TOP.a", "a");
$to_prsim("TOP.clk", "clk");
$from_prsim("z", "TOP.z");
end
// these could be automatically generated
// by finding all globally unique instances of processes
// along with their hierarchical names
// e.g. from hacobjdump of .haco-c file
// test using escaped identifiers
HAC_POS_FLOP #(.prsim_name("F.f[0]")) \F.f[0] ();
HAC_POS_FLOP #(.prsim_name("F.f[1]")) \F.f[1] ();
HAC_POS_FLOP #(.prsim_name("F.f[2]")) \F.f[2] ();
HAC_POS_FLOP #(.prsim_name("F.f[3]")) \F.f[3] ();
initial
begin
#20 a <= 1'b0;
#400 a <= 1'b1;
#400 a <= 1'b0;
#100 a <= 1'b1;
#100 a <= 1'b0;
#100 a <= 1'b1;
#300 a <= 1'b0;
#50 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND2_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND2_BLACKBOX_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_transition_assert #(
.width(width))
assert_transition_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_state(start_state),
.next_state(next_state),
.test_expr(test_expr) ,
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_transition_assume #(
.width(width) )
assert_transition_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_state(start_state),
.next_state(next_state),
.test_expr(test_expr) ,
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_transition_cover #(
.width (width),
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_transition_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.start_state(start_state),
.test_expr(test_expr) );
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_transition.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_transition_assert (clk, reset_n, start_state, next_state, test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n;
input [width-1:0] test_expr, start_state, next_state;
input xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_transition_assume (clk, reset_n, start_state, next_state, test_expr, xzcheck_enable);
parameter width = 8;
input clk, reset_n;
input [width-1:0] test_expr, start_state, next_state;
input xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_transition_cover (clk, reset_n, start_state, test_expr);
parameter width = 8;
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n;
input [width-1:0] test_expr, start_state;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_80x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_80x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [79:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [79:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [79:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [79:0] q = sub_wire2[79:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 80,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "80"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "80"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "80"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 80 0 INPUT NODEFVAL data[79..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 80 0 OUTPUT NODEFVAL q[79..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 80 0 data 0 0 80 0
// Retrieval info: CONNECT: q 0 0 80 0 @q 0 0 80 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_80x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_80x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_80x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_80x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_80x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_80x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_80x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_80x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_decoder.v
// Title : Instruction decoder
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Support for static branch prediction. Information about
// : branch type is generated and passed on to the predictor.
// Version : 3.2
// : No change
// Version : 3.3
// : Renamed port names that conflict with keywords reserved
// : in System-Verilog.
// =============================================================================
`include "lm32_include.v"
// Index of opcode field in an instruction
`define LM32_OPCODE_RNG 31:26
`define LM32_OP_RNG 30:26
// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
`define LM32_OPCODE_ADD 5'b01101
`define LM32_OPCODE_AND 5'b01000
`define LM32_OPCODE_ANDHI 6'b011000
`define LM32_OPCODE_B 6'b110000
`define LM32_OPCODE_BI 6'b111000
`define LM32_OPCODE_BE 6'b010001
`define LM32_OPCODE_BG 6'b010010
`define LM32_OPCODE_BGE 6'b010011
`define LM32_OPCODE_BGEU 6'b010100
`define LM32_OPCODE_BGU 6'b010101
`define LM32_OPCODE_BNE 6'b010111
`define LM32_OPCODE_CALL 6'b110110
`define LM32_OPCODE_CALLI 6'b111110
`define LM32_OPCODE_CMPE 5'b11001
`define LM32_OPCODE_CMPG 5'b11010
`define LM32_OPCODE_CMPGE 5'b11011
`define LM32_OPCODE_CMPGEU 5'b11100
`define LM32_OPCODE_CMPGU 5'b11101
`define LM32_OPCODE_CMPNE 5'b11111
`define LM32_OPCODE_DIVU 6'b100011
`define LM32_OPCODE_LB 6'b000100
`define LM32_OPCODE_LBU 6'b010000
`define LM32_OPCODE_LH 6'b000111
`define LM32_OPCODE_LHU 6'b001011
`define LM32_OPCODE_LW 6'b001010
`define LM32_OPCODE_MODU 6'b110001
`define LM32_OPCODE_MUL 5'b00010
`define LM32_OPCODE_NOR 5'b00001
`define LM32_OPCODE_OR 5'b01110
`define LM32_OPCODE_ORHI 6'b011110
`define LM32_OPCODE_RAISE 6'b101011
`define LM32_OPCODE_RCSR 6'b100100
`define LM32_OPCODE_SB 6'b001100
`define LM32_OPCODE_SEXTB 6'b101100
`define LM32_OPCODE_SEXTH 6'b110111
`define LM32_OPCODE_SH 6'b000011
`define LM32_OPCODE_SL 5'b01111
`define LM32_OPCODE_SR 5'b00101
`define LM32_OPCODE_SRU 5'b00000
`define LM32_OPCODE_SUB 6'b110010
`define LM32_OPCODE_SW 6'b010110
`define LM32_OPCODE_USER 6'b110011
`define LM32_OPCODE_WCSR 6'b110100
`define LM32_OPCODE_XNOR 5'b01001
`define LM32_OPCODE_XOR 5'b00110
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_decoder (
// ----- Inputs -------
instruction,
// ----- Outputs -------
d_result_sel_0,
d_result_sel_1,
x_result_sel_csr,
`ifdef LM32_MC_ARITHMETIC_ENABLED
x_result_sel_mc_arith,
`endif
`ifdef LM32_NO_BARREL_SHIFT
x_result_sel_shift,
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext,
`endif
x_result_sel_logic,
`ifdef CFG_USER_ENABLED
x_result_sel_user,
`endif
x_result_sel_add,
m_result_sel_compare,
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift,
`endif
w_result_sel_load,
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul,
`endif
x_bypass_enable,
m_bypass_enable,
read_enable_0,
read_idx_0,
read_enable_1,
read_idx_1,
write_enable,
write_idx,
immediate,
branch_offset,
load,
store,
size,
sign_extend,
adder_op,
logic_op,
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
direction,
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
shift_left,
shift_right,
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
multiply,
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
divide,
modulus,
`endif
branch,
branch_reg,
condition,
bi_conditional,
bi_unconditional,
`ifdef CFG_DEBUG_ENABLED
break_opcode,
`endif
scall,
eret,
`ifdef CFG_DEBUG_ENABLED
bret,
`endif
`ifdef CFG_USER_ENABLED
user_opcode,
`endif
csr_write_enable
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
reg [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
reg [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
output x_result_sel_csr;
reg x_result_sel_csr;
`ifdef LM32_MC_ARITHMETIC_ENABLED
output x_result_sel_mc_arith;
reg x_result_sel_mc_arith;
`endif
`ifdef LM32_NO_BARREL_SHIFT
output x_result_sel_shift;
reg x_result_sel_shift;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
output x_result_sel_sext;
reg x_result_sel_sext;
`endif
output x_result_sel_logic;
reg x_result_sel_logic;
`ifdef CFG_USER_ENABLED
output x_result_sel_user;
reg x_result_sel_user;
`endif
output x_result_sel_add;
reg x_result_sel_add;
output m_result_sel_compare;
reg m_result_sel_compare;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
output m_result_sel_shift;
reg m_result_sel_shift;
`endif
output w_result_sel_load;
reg w_result_sel_load;
`ifdef CFG_PL_MULTIPLY_ENABLED
output w_result_sel_mul;
reg w_result_sel_mul;
`endif
output x_bypass_enable;
wire x_bypass_enable;
output m_bypass_enable;
wire m_bypass_enable;
output read_enable_0;
wire read_enable_0;
output [`LM32_REG_IDX_RNG] read_idx_0;
wire [`LM32_REG_IDX_RNG] read_idx_0;
output read_enable_1;
wire read_enable_1;
output [`LM32_REG_IDX_RNG] read_idx_1;
wire [`LM32_REG_IDX_RNG] read_idx_1;
output write_enable;
wire write_enable;
output [`LM32_REG_IDX_RNG] write_idx;
wire [`LM32_REG_IDX_RNG] write_idx;
output [`LM32_WORD_RNG] immediate;
wire [`LM32_WORD_RNG] immediate;
output [`LM32_PC_RNG] branch_offset;
wire [`LM32_PC_RNG] branch_offset;
output load;
wire load;
output store;
wire store;
output [`LM32_SIZE_RNG] size;
wire [`LM32_SIZE_RNG] size;
output sign_extend;
wire sign_extend;
output adder_op;
wire adder_op;
output [`LM32_LOGIC_OP_RNG] logic_op;
wire [`LM32_LOGIC_OP_RNG] logic_op;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
output direction;
wire direction;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
output shift_left;
wire shift_left;
output shift_right;
wire shift_right;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
output multiply;
wire multiply;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
output divide;
wire divide;
output modulus;
wire modulus;
`endif
output branch;
wire branch;
output branch_reg;
wire branch_reg;
output [`LM32_CONDITION_RNG] condition;
wire [`LM32_CONDITION_RNG] condition;
output bi_conditional;
wire bi_conditional;
output bi_unconditional;
wire bi_unconditional;
`ifdef CFG_DEBUG_ENABLED
output break_opcode;
wire break_opcode;
`endif
output scall;
wire scall;
output eret;
wire eret;
`ifdef CFG_DEBUG_ENABLED
output bret;
wire bret;
`endif
`ifdef CFG_USER_ENABLED
output [`LM32_USER_OPCODE_RNG] user_opcode;
wire [`LM32_USER_OPCODE_RNG] user_opcode;
`endif
output csr_write_enable;
wire csr_write_enable;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate
wire [`LM32_WORD_RNG] high_immediate; // Immediate as high 16 bits
wire [`LM32_WORD_RNG] call_immediate; // Call immediate
wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate
wire sign_extend_immediate; // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
wire select_high_immediate; // Whether to select the high immediate
wire select_call_immediate; // Whether to select the call immediate
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Determine opcode
assign op_add = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
assign op_and = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
assign op_andhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
assign op_b = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
assign op_bi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
assign op_be = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
assign op_bg = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
assign op_bge = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
assign op_bgeu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
assign op_bgu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
assign op_bne = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
assign op_call = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
assign op_calli = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
assign op_cmpe = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
assign op_cmpg = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
assign op_cmpge = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
assign op_cmpgu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
assign op_cmpne = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
`ifdef CFG_MC_DIVIDE_ENABLED
assign op_divu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
`endif
assign op_lb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
assign op_lbu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
assign op_lh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
assign op_lhu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
assign op_lw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
`ifdef CFG_MC_DIVIDE_ENABLED
assign op_modu = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
`endif
`ifdef LM32_MULTIPLY_ENABLED
assign op_mul = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
`endif
assign op_nor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
assign op_or = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
assign op_orhi = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
assign op_raise = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
assign op_rcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
assign op_sb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
`ifdef CFG_SIGN_EXTEND_ENABLED
assign op_sextb = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
assign op_sexth = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
`endif
assign op_sh = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
`ifdef LM32_BARREL_SHIFT_ENABLED
assign op_sl = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;
`endif
assign op_sr = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
assign op_sru = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
assign op_sub = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
assign op_sw = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
assign op_user = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
assign op_wcsr = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
assign op_xnor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
assign op_xor = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
// Group opcodes by function
assign arith = op_add | op_sub;
assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
assign bi_conditional = op_be | op_bg | op_bge | op_bgeu | op_bgu | op_bne;
assign bi_unconditional = op_bi;
assign bra = op_b | bi_unconditional | bi_conditional;
assign call = op_call | op_calli;
`ifdef LM32_BARREL_SHIFT_ENABLED
assign shift = op_sl | op_sr | op_sru;
`endif
`ifdef LM32_NO_BARREL_SHIFT
assign shift = op_sr | op_sru;
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
assign shift_left = op_sl;
assign shift_right = op_sr | op_sru;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
assign sext = op_sextb | op_sexth;
`endif
`ifdef LM32_MULTIPLY_ENABLED
assign multiply = op_mul;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
assign divide = op_divu;
assign modulus = op_modu;
`endif
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw;
// Select pipeline multiplexor controls
always @(*)
begin
// D stage
if (call)
d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
else
d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
if (call)
d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;
else if ((instruction[31] == 1'b0) && !bra)
d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
else
d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1;
// X stage
x_result_sel_csr = `FALSE;
`ifdef LM32_MC_ARITHMETIC_ENABLED
x_result_sel_mc_arith = `FALSE;
`endif
`ifdef LM32_NO_BARREL_SHIFT
x_result_sel_shift = `FALSE;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
x_result_sel_sext = `FALSE;
`endif
x_result_sel_logic = `FALSE;
`ifdef CFG_USER_ENABLED
x_result_sel_user = `FALSE;
`endif
x_result_sel_add = `FALSE;
if (op_rcsr)
x_result_sel_csr = `TRUE;
`ifdef LM32_MC_ARITHMETIC_ENABLED
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
else if (shift_left | shift_right)
x_result_sel_mc_arith = `TRUE;
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
else if (divide | modulus)
x_result_sel_mc_arith = `TRUE;
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
else if (multiply)
x_result_sel_mc_arith = `TRUE;
`endif
`endif
`ifdef LM32_NO_BARREL_SHIFT
else if (shift)
x_result_sel_shift = `TRUE;
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
else if (sext)
x_result_sel_sext = `TRUE;
`endif
else if (logical)
x_result_sel_logic = `TRUE;
`ifdef CFG_USER_ENABLED
else if (op_user)
x_result_sel_user = `TRUE;
`endif
else
x_result_sel_add = `TRUE;
// M stage
m_result_sel_compare = cmp;
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
m_result_sel_shift = shift;
`endif
// W stage
w_result_sel_load = load;
`ifdef CFG_PL_MULTIPLY_ENABLED
w_result_sel_mul = op_mul;
`endif
end
// Set if result is valid at end of X stage
assign x_bypass_enable = arith
| logical
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
| shift_left
| shift_right
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
| multiply
`endif
`ifdef CFG_MC_DIVIDE_ENABLED
| divide
| modulus
`endif
`ifdef LM32_NO_BARREL_SHIFT
| shift
`endif
`ifdef CFG_SIGN_EXTEND_ENABLED
| sext
`endif
`ifdef CFG_USER_ENABLED
| op_user
`endif
| op_rcsr
;
// Set if result is valid at end of M stage
assign m_bypass_enable = x_bypass_enable
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
| shift
`endif
| cmp
;
// Register file read port 0
assign read_enable_0 = ~(op_bi | op_calli);
assign read_idx_0 = instruction[25:21];
// Register file read port 1
assign read_enable_1 = ~(op_bi | op_calli | load);
assign read_idx_1 = instruction[20:16];
// Register file write port
assign write_enable = ~(bra | op_raise | store | op_wcsr);
assign write_idx = call
? 5'd29
: instruction[31] == 1'b0
? instruction[20:16]
: instruction[15:11];
// Size of load/stores
assign size = instruction[27:26];
// Whether to sign or zero extend
assign sign_extend = instruction[28];
// Set adder_op to 1 to perform a subtraction
assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
// Logic operation (and, or, etc)
assign logic_op = instruction[29:26];
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
// Shift direction
assign direction = instruction[29];
`endif
// Control flow microcodes
assign branch = bra | call;
assign branch_reg = op_call | op_b;
assign condition = instruction[28:26];
`ifdef CFG_DEBUG_ENABLED
assign break_opcode = op_raise & ~instruction[2];
`endif
assign scall = op_raise & instruction[2];
assign eret = op_b & (instruction[25:21] == 5'd30);
`ifdef CFG_DEBUG_ENABLED
assign bret = op_b & (instruction[25:21] == 5'd31);
`endif
`ifdef CFG_USER_ENABLED
// Extract user opcode
assign user_opcode = instruction[10:0];
`endif
// CSR read/write
assign csr_write_enable = op_wcsr;
// Extract immediate from instruction
assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
assign select_high_immediate = op_andhi | op_orhi;
assign select_call_immediate = instruction[31];
assign high_immediate = {instruction[15:0], 16'h0000};
assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
assign immediate = select_high_immediate == `TRUE
? high_immediate
: extended_immediate;
assign branch_offset = select_call_immediate == `TRUE
? call_immediate
: branch_immediate;
endmodule
|
//hardware top level module
module sm_top
(
input clkIn,
input rst_n,
input [ 3:0 ] clkDevide,
input clkEnable,
output clk,
input [ 4:0 ] regAddr,
output [31:0 ] regData,
input [ 7:0 ] exData
);
//metastability input filters
wire [ 3:0 ] devide;
wire enable;
wire [ 4:0 ] addr;
sm_metafilter #(.SIZE(4)) f0(clkIn, clkDevide, devide);
sm_metafilter #(.SIZE(1)) f1(clkIn, clkEnable, enable);
sm_metafilter #(.SIZE(5)) f2(clkIn, regAddr, addr );
//cores
//clock devider
sm_clk_divider sm_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( devide ),
.enable ( enable ),
.clkOut ( clk )
);
//instruction memory
wire [31:0] imAddr;
wire [31:0] imData;
sm_rom reset_rom(imAddr, imData);
sm_cpu sm_cpu
(
.clk ( clk ),
.rst_n ( rst_n ),
.regAddr ( addr ),
.regData ( regData ),
.imAddr ( imAddr ),
.imData ( imData ),
.exData ( exData )
);
endmodule
//metastability input filter module
module sm_metafilter
#(
parameter SIZE = 1
)
(
input clk,
input [ SIZE - 1 : 0] d,
output reg [ SIZE - 1 : 0] q
);
reg [ SIZE - 1 : 0] data;
always @ (posedge clk) begin
data <= d;
q <= data;
end
endmodule
//tunable clock devider
module sm_clk_divider
#(
parameter shift = 16
)
(
input clkIn,
input rst_n,
input [ 3:0 ] devide,
input enable,
output clkOut
);
wire [31:0] cntr;
wire [31:0] cntrNext = cntr + 1;
sm_register_we r_cntr(clkIn, rst_n, enable, cntrNext, cntr);
assign clkOut = cntr[shift + devide];
endmodule
|
module reg32(Rout, clr, clk, write_enable, write_value);
input clr,clk, write_enable;
input [31:0] write_value;
output [31:0]Rout;
reg[31:0] Rout;
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(write_enable) begin
Rout = write_value;
end
end
endmodule
module reg32_R0(Rout, clr, clk, BA_out, write_enable, write_value);
input clr,clk, write_enable, BA_out;
input [31:0] write_value;
output [31:0]Rout;
reg[31:0] Rout;
always @ (posedge clk)begin
if(clr) begin
Rout = 32'h00000000;
end
if(write_enable) begin
Rout = write_value & (!BA_out);
end
end
endmodule
module reg32_MDR(Memory_output, Bus_output, Mem_RW, clr, clk, MDR_write_enable, Memory_write_enable, Memory_read_enable, Bus_input, Memory_input);
input clr,clk, Memory_write_enable, Memory_read_enable, MDR_write_enable;
input [31:0] Bus_input, Memory_input;
output [31:0]Memory_output, Bus_output;
output Mem_RW;
reg Mem_RW;
reg[31:0] Rout;
wire[31:0] register;
MDMux_in input_select(Bus_input, Memory_input, Memory_read_enable, register);
MDMux_out output_select(Rout, Memory_write_enable, Bus_output, Memory_output);
always @ (posedge clk)begin
Mem_RW = MDR_write_enable & (!Memory_read_enable);
if(clr) begin
Rout = 32'h00000000;
end
if(MDR_write_enable) begin
Rout = register;
end
end
endmodule
module reg32_MAR(Rout, clr, clk, write_enable, write_value);
input clr,clk, write_enable;
input [31:0] write_value;
output [8:0] Rout;
reg[31:0] value;
assign Rout = value[8:0];
always @ (posedge clk)begin
if(clr) begin
value = 32'h00000000;
end
if(write_enable) begin
value = write_value;
end
end
endmodule
module MDMux_in(Bus_data, Mdata_in, Mem_read_enable, MDMux_out); //BusMuxOut
input Mem_read_enable;
input[31:0] Bus_data, Mdata_in;
output[31:0] MDMux_out;
//assign MDMux_out = (Mem_read_enable & Mdata_in) | (!Mem_read_enable & Bus_data);
assign MDMux_out = (Mem_read_enable) ? Mdata_in : Bus_data;
endmodule
module MDMux_out(MDR_data, Mem_write_enable, BusData_out, Mdata_out);
input Mem_write_enable;
input[31:0] MDR_data;
output[31:0] BusData_out, Mdata_out;
assign Mdata_out = (Mem_write_enable) ? MDR_data : 0; //MDR_data & Mem_write_enable;
assign BusData_out = (!Mem_write_enable) ? MDR_data : 0; //MDR_data & (!Mem_write_enable);
endmodule
module reg64(Rout_hi, Rout_low, clr, clk, write_enable, input_value);
input clr,clk, write_enable;
input [63:0] input_value;
output [31:0]Rout_hi, Rout_low;
reg[31:0] Rout_hi, Rout_low;
always @ (posedge clk)begin
if(write_enable == 1) begin
Rout_hi = input_value[63:32];
Rout_low = input_value[31:0];
end
else if(clr) begin
Rout_hi = 0;
Rout_low = 0;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:20:46 03/23/2016
// Design Name: FA
// Module Name: Y:/TEOCOA/EXP2/TEST_FA.v
// Project Name: EXP2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: FA
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TEST_FA;
// Inputs
reg A;
reg B;
reg C;
// Outputs
wire F;
// Instantiate the Unit Under Test (UUT)
FA uut (
.A(A),
.B(B),
.C(C),
.F(F),
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
C = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 0;
B = 0;
C = 1;
// Wait 100 ns for global reset to finish
#100;
A = 0;
B = 1;
C = 0;
// Wait 100 ns for global reset to finish
#100;
A = 0;
B = 1;
C = 1;
// Wait 100 ns for global reset to finish
#100;
A = 1;
B = 0;
C = 0;
// Wait 100 ns for global reset to finish
#100;
A = 1;
B = 1;
C = 0;
// Wait 100 ns for global reset to finish
#100;
A = 1;
B = 1;
C = 1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule
|
module qdec(rst_n, freq_clk, enable, pha, phb,index, led);
input rst_n;
input freq_clk;
input enable;
output pha;
output phb;
output index;
output led;
reg pha_reg;
reg phb_reg;
reg index_reg;
reg[7:0] pha_count;
//debug led
reg led;
// generate 100 Hz from 50 MHz
reg [31:0] count_reg;
reg out_200hz;
always @(posedge freq_clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
out_200hz <= 0;
count_reg <= 0;
out_200hz <= 0;
end
else if (enable)
begin
if (count_reg < 124999) begin
count_reg <= count_reg + 1;
end else begin
count_reg <= 0;
out_200hz <= ~out_200hz;
end
end
end
/*
we will be generating waveform like below
_ _
pha | |_| |_
_ _
phb _| |_| |_
_
home <every 12 clock of pha> _| |_
_
index <every 12 clock of pha> _| |_
*/
/* process the pha_count*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
pha_count <= 8'd0;
led <= 1'b0;
end
else if (out_200hz)
begin
led <= ~led;
if(pha_count>8'd24)
pha_count <= 8'd0;
else
pha_count <= pha_count + 8'd1;
end
end
reg[1:0] Phase90_Count;
/*process the pha signal*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
Phase90_Count <= 2'b0;
end
else if (out_200hz)
begin
case (Phase90_Count)
2'd0:
begin
pha_reg <= 1'd1;
phb_reg <= 1'd1;
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd1:
begin
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd2:
begin
pha_reg <= 1'd0;
phb_reg <= 1'd0;
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd3:
begin
Phase90_Count <= 2'd0;
end
endcase
end
end
assign pha = pha_reg;
assign phb = phb_reg;
/*process the index signal*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
index_reg <= 1'b0;
end
else if (out_200hz)
begin
case (pha_count)
8'd23: index_reg <= 1'd1;
8'd24: index_reg <= 1'd1;
default: index_reg <= 1'd0;
endcase
end
end
assign index = index_reg;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__isobufsrc (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_BEHAVIORAL_V
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_6 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
output [DATA_SZ-1:0] read_5;
input [DATA_SZ-1:0] write_5;
input EN_write_5;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
wire [DATA_SZ-1:0] wire_6;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign wire_6 = EN_write_5 ? write_5 : wire_5;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
assign read_5 = wire_5;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_6;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_1_V
`define SKY130_FD_SC_LS__A222O_1_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a222o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a222o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a222o_1 (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_1_V
|
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`include "../../vtr/dff/dff.sim.v"
`include "../dsp_combinational/dsp_combinational.sim.v"
/* DSP Block with register on both the inputs and the output, which use different clocks */
module DSP_INOUT_REGISTERED_DUALCLK (iclk, oclk, a, b, m, out);
localparam DATA_WIDTH = 4;
input wire iclk;
input wire oclk;
input wire [DATA_WIDTH/2-1:0] a;
input wire [DATA_WIDTH/2-1:0] b;
input wire m;
output wire [DATA_WIDTH-1:0] out;
/* Input registers on iclk */
(* pack="DFF-DSP" *)
wire [DATA_WIDTH/2-1:0] q_a;
(* pack="DFF-DSP" *)
wire [DATA_WIDTH/2-1:0] q_b;
(* pack="DFF-DSP" *)
wire q_m;
genvar i;
for (i=0; i<DATA_WIDTH/2; i=i+1) begin: input_dffs_gen
DFF q_a_ff(.D(a[i]), .Q(q_a[i]), .CLK(iclk));
DFF q_b_ff(.D(b[i]), .Q(q_b[i]), .CLK(iclk));
end
DFF m_ff(.D(m), .Q(q_m), .CLK(iclk));
/* Combinational logic */
(* pack="DFF-DSP" *)
wire [DATA_WIDTH-1:0] c_out;
DSP_COMBINATIONAL comb (.a(q_a), .b(q_b), .m(q_m), .out(c_out));
/* Output register on oclk */
wire [DATA_WIDTH-1:0] q_out;
genvar j;
for (j=0; j<DATA_WIDTH; j=j+1) begin: output_dffs_gen
DFF q_out_ff(.D(c_out[j]), .Q(out[j]), .CLK(oclk));
end
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module switch_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 17: 0] in_port;
input reset_n;
wire clk_en;
wire [ 17: 0] data_in;
wire [ 17: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {18 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 18}{1'b0}},read_mux_out};
end
assign data_in = in_port;
endmodule
|
//======================================================================
//
// chacha_core.v
// --------------
// Verilog 2001 implementation of the stream cipher ChaCha.
// This is the internal core with wide interfaces.
//
//
// Copyright (c) 2013 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module chacha_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire [255 : 0] key,
input wire keylen,
input wire [63 : 0] iv,
input wire [63 : 0] ctr,
input wire [4 : 0] rounds,
input wire [511 : 0] data_in,
output wire ready,
output wire [511 : 0] data_out,
output wire data_out_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// Datapath quartterround states names.
localparam QR0 = 0;
localparam QR1 = 1;
localparam NUM_ROUNDS = 4'h8;
localparam TAU0 = 32'h61707865;
localparam TAU1 = 32'h3120646e;
localparam TAU2 = 32'h79622d36;
localparam TAU3 = 32'h6b206574;
localparam SIGMA0 = 32'h61707865;
localparam SIGMA1 = 32'h3320646e;
localparam SIGMA2 = 32'h79622d32;
localparam SIGMA3 = 32'h6b206574;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
localparam CTRL_ROUNDS = 3'h2;
localparam CTRL_FINALIZE = 3'h3;
localparam CTRL_DONE = 3'h4;
//----------------------------------------------------------------
// l2b()
//
// Swap bytes from little to big endian byte order.
//----------------------------------------------------------------
function [31 : 0] l2b(input [31 : 0] op);
begin
l2b = {op[7 : 0], op[15 : 8], op[23 : 16], op[31 : 24]};
end
endfunction // b2l
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] state_reg [0 : 15];
reg [31 : 0] state_new [0 : 15];
reg state_we;
reg [511 : 0] data_out_reg;
reg [511 : 0] data_out_new;
reg data_out_valid_reg;
reg data_out_valid_new;
reg data_out_valid_we;
reg qr_ctr_reg;
reg qr_ctr_new;
reg qr_ctr_we;
reg qr_ctr_inc;
reg qr_ctr_rst;
reg [3 : 0] dr_ctr_reg;
reg [3 : 0] dr_ctr_new;
reg dr_ctr_we;
reg dr_ctr_inc;
reg dr_ctr_rst;
reg [31 : 0] block0_ctr_reg;
reg [31 : 0] block0_ctr_new;
reg block0_ctr_we;
reg [31 : 0] block1_ctr_reg;
reg [31 : 0] block1_ctr_new;
reg block1_ctr_we;
reg block_ctr_inc;
reg block_ctr_set;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [2 : 0] chacha_ctrl_reg;
reg [2 : 0] chacha_ctrl_new;
reg chacha_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] init_state_word [0 : 15];
reg init_state;
reg update_state;
reg update_output;
reg [31 : 0] qr0_a;
reg [31 : 0] qr0_b;
reg [31 : 0] qr0_c;
reg [31 : 0] qr0_d;
wire [31 : 0] qr0_a_prim;
wire [31 : 0] qr0_b_prim;
wire [31 : 0] qr0_c_prim;
wire [31 : 0] qr0_d_prim;
reg [31 : 0] qr1_a;
reg [31 : 0] qr1_b;
reg [31 : 0] qr1_c;
reg [31 : 0] qr1_d;
wire [31 : 0] qr1_a_prim;
wire [31 : 0] qr1_b_prim;
wire [31 : 0] qr1_c_prim;
wire [31 : 0] qr1_d_prim;
reg [31 : 0] qr2_a;
reg [31 : 0] qr2_b;
reg [31 : 0] qr2_c;
reg [31 : 0] qr2_d;
wire [31 : 0] qr2_a_prim;
wire [31 : 0] qr2_b_prim;
wire [31 : 0] qr2_c_prim;
wire [31 : 0] qr2_d_prim;
reg [31 : 0] qr3_a;
reg [31 : 0] qr3_b;
reg [31 : 0] qr3_c;
reg [31 : 0] qr3_d;
wire [31 : 0] qr3_a_prim;
wire [31 : 0] qr3_b_prim;
wire [31 : 0] qr3_c_prim;
wire [31 : 0] qr3_d_prim;
//----------------------------------------------------------------
// Instantiation of the qr modules.
//----------------------------------------------------------------
chacha_qr qr0(
.a(qr0_a),
.b(qr0_b),
.c(qr0_c),
.d(qr0_d),
.a_prim(qr0_a_prim),
.b_prim(qr0_b_prim),
.c_prim(qr0_c_prim),
.d_prim(qr0_d_prim)
);
chacha_qr qr1(
.a(qr1_a),
.b(qr1_b),
.c(qr1_c),
.d(qr1_d),
.a_prim(qr1_a_prim),
.b_prim(qr1_b_prim),
.c_prim(qr1_c_prim),
.d_prim(qr1_d_prim)
);
chacha_qr qr2(
.a(qr2_a),
.b(qr2_b),
.c(qr2_c),
.d(qr2_d),
.a_prim(qr2_a_prim),
.b_prim(qr2_b_prim),
.c_prim(qr2_c_prim),
.d_prim(qr2_d_prim)
);
chacha_qr qr3(
.a(qr3_a),
.b(qr3_b),
.c(qr3_c),
.d(qr3_d),
.a_prim(qr3_a_prim),
.b_prim(qr3_b_prim),
.c_prim(qr3_c_prim),
.d_prim(qr3_d_prim)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0 ; i < 16 ; i = i + 1)
state_reg[i] <= 32'h0;
data_out_reg <= 512'h0;
data_out_valid_reg <= 0;
qr_ctr_reg <= QR0;
dr_ctr_reg <= 0;
block0_ctr_reg <= 32'h0;
block1_ctr_reg <= 32'h0;
chacha_ctrl_reg <= CTRL_IDLE;
ready_reg <= 1;
end
else
begin
if (state_we)
begin
for (i = 0 ; i < 16 ; i = i + 1)
state_reg[i] <= state_new[i];
end
if (update_output)
data_out_reg <= data_out_new;
if (data_out_valid_we)
data_out_valid_reg <= data_out_valid_new;
if (qr_ctr_we)
qr_ctr_reg <= qr_ctr_new;
if (dr_ctr_we)
dr_ctr_reg <= dr_ctr_new;
if (block0_ctr_we)
block0_ctr_reg <= block0_ctr_new;
if (block1_ctr_we)
block1_ctr_reg <= block1_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (chacha_ctrl_we)
chacha_ctrl_reg <= chacha_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// init_state_logic
//
// Calculates the initial state for a given block.
//----------------------------------------------------------------
always @*
begin : init_state_logic
reg [31 : 0] key0;
reg [31 : 0] key1;
reg [31 : 0] key2;
reg [31 : 0] key3;
reg [31 : 0] key4;
reg [31 : 0] key5;
reg [31 : 0] key6;
reg [31 : 0] key7;
key0 = l2b(key[255 : 224]);
key1 = l2b(key[223 : 192]);
key2 = l2b(key[191 : 160]);
key3 = l2b(key[159 : 128]);
key4 = l2b(key[127 : 96]);
key5 = l2b(key[95 : 64]);
key6 = l2b(key[63 : 32]);
key7 = l2b(key[31 : 0]);
init_state_word[04] = key0;
init_state_word[05] = key1;
init_state_word[06] = key2;
init_state_word[07] = key3;
init_state_word[12] = block0_ctr_reg;
init_state_word[13] = block1_ctr_reg;
init_state_word[14] = l2b(iv[63 : 32]);
init_state_word[15] = l2b(iv[31 : 0]);
if (keylen)
begin
// 256 bit key.
init_state_word[00] = SIGMA0;
init_state_word[01] = SIGMA1;
init_state_word[02] = SIGMA2;
init_state_word[03] = SIGMA3;
init_state_word[08] = key4;
init_state_word[09] = key5;
init_state_word[10] = key6;
init_state_word[11] = key7;
end
else
begin
// 128 bit key.
init_state_word[00] = TAU0;
init_state_word[01] = TAU1;
init_state_word[02] = TAU2;
init_state_word[03] = TAU3;
init_state_word[08] = key0;
init_state_word[09] = key1;
init_state_word[10] = key2;
init_state_word[11] = key3;
end
end
//----------------------------------------------------------------
// state_logic
// Logic to init and update the internal state.
//----------------------------------------------------------------
always @*
begin : state_logic
integer i;
for (i = 0 ; i < 16 ; i = i + 1)
state_new[i] = 32'h0;
state_we = 0;
qr0_a = 32'h0;
qr0_b = 32'h0;
qr0_c = 32'h0;
qr0_d = 32'h0;
qr1_a = 32'h0;
qr1_b = 32'h0;
qr1_c = 32'h0;
qr1_d = 32'h0;
qr2_a = 32'h0;
qr2_b = 32'h0;
qr2_c = 32'h0;
qr2_d = 32'h0;
qr3_a = 32'h0;
qr3_b = 32'h0;
qr3_c = 32'h0;
qr3_d = 32'h0;
if (init_state)
begin
for (i = 0 ; i < 16 ; i = i + 1)
state_new[i] = init_state_word[i];
state_we = 1;
end // if (init_state)
if (update_state)
begin
state_we = 1;
case (qr_ctr_reg)
QR0:
begin
qr0_a = state_reg[00];
qr0_b = state_reg[04];
qr0_c = state_reg[08];
qr0_d = state_reg[12];
qr1_a = state_reg[01];
qr1_b = state_reg[05];
qr1_c = state_reg[09];
qr1_d = state_reg[13];
qr2_a = state_reg[02];
qr2_b = state_reg[06];
qr2_c = state_reg[10];
qr2_d = state_reg[14];
qr3_a = state_reg[03];
qr3_b = state_reg[07];
qr3_c = state_reg[11];
qr3_d = state_reg[15];
state_new[00] = qr0_a_prim;
state_new[04] = qr0_b_prim;
state_new[08] = qr0_c_prim;
state_new[12] = qr0_d_prim;
state_new[01] = qr1_a_prim;
state_new[05] = qr1_b_prim;
state_new[09] = qr1_c_prim;
state_new[13] = qr1_d_prim;
state_new[02] = qr2_a_prim;
state_new[06] = qr2_b_prim;
state_new[10] = qr2_c_prim;
state_new[14] = qr2_d_prim;
state_new[03] = qr3_a_prim;
state_new[07] = qr3_b_prim;
state_new[11] = qr3_c_prim;
state_new[15] = qr3_d_prim;
end
QR1:
begin
qr0_a = state_reg[00];
qr0_b = state_reg[05];
qr0_c = state_reg[10];
qr0_d = state_reg[15];
qr1_a = state_reg[01];
qr1_b = state_reg[06];
qr1_c = state_reg[11];
qr1_d = state_reg[12];
qr2_a = state_reg[02];
qr2_b = state_reg[07];
qr2_c = state_reg[08];
qr2_d = state_reg[13];
qr3_a = state_reg[03];
qr3_b = state_reg[04];
qr3_c = state_reg[09];
qr3_d = state_reg[14];
state_new[00] = qr0_a_prim;
state_new[05] = qr0_b_prim;
state_new[10] = qr0_c_prim;
state_new[15] = qr0_d_prim;
state_new[01] = qr1_a_prim;
state_new[06] = qr1_b_prim;
state_new[11] = qr1_c_prim;
state_new[12] = qr1_d_prim;
state_new[02] = qr2_a_prim;
state_new[07] = qr2_b_prim;
state_new[08] = qr2_c_prim;
state_new[13] = qr2_d_prim;
state_new[03] = qr3_a_prim;
state_new[04] = qr3_b_prim;
state_new[09] = qr3_c_prim;
state_new[14] = qr3_d_prim;
end
endcase // case (quarterround_select)
end // if (update_state)
end // state_logic
//----------------------------------------------------------------
// data_out_logic
// Final output logic that combines the result from state
// update with the input block. This adds a 16 rounds and
// a final layer of XOR gates.
//
// Note that we also remap all the words into LSB format.
//----------------------------------------------------------------
always @*
begin : data_out_logic
integer i;
reg [31 : 0] msb_block_state [0 : 15];
reg [31 : 0] lsb_block_state [0 : 15];
reg [511 : 0] block_state;
for (i = 0 ; i < 16 ; i = i + 1)
begin
msb_block_state[i] = init_state_word[i] + state_reg[i];
lsb_block_state[i] = l2b(msb_block_state[i][31 : 0]);
end
block_state = {lsb_block_state[00], lsb_block_state[01],
lsb_block_state[02], lsb_block_state[03],
lsb_block_state[04], lsb_block_state[05],
lsb_block_state[06], lsb_block_state[07],
lsb_block_state[08], lsb_block_state[09],
lsb_block_state[10], lsb_block_state[11],
lsb_block_state[12], lsb_block_state[13],
lsb_block_state[14], lsb_block_state[15]};
data_out_new = data_in ^ block_state;
end // data_out_logic
//----------------------------------------------------------------
// qr_ctr
// Update logic for the quarterround counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : qr_ctr
qr_ctr_new = 0;
qr_ctr_we = 0;
if (qr_ctr_rst)
begin
qr_ctr_new = 0;
qr_ctr_we = 1;
end
if (qr_ctr_inc)
begin
qr_ctr_new = qr_ctr_reg + 1'b1;
qr_ctr_we = 1;
end
end // qr_ctr
//----------------------------------------------------------------
// dr_ctr
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : dr_ctr
dr_ctr_new = 0;
dr_ctr_we = 0;
if (dr_ctr_rst)
begin
dr_ctr_new = 0;
dr_ctr_we = 1;
end
if (dr_ctr_inc)
begin
dr_ctr_new = dr_ctr_reg + 1'b1;
dr_ctr_we = 1;
end
end // dr_ctr
//----------------------------------------------------------------
// block_ctr
// Update logic for the 64-bit block counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : block_ctr
block0_ctr_new = 32'h0;
block1_ctr_new = 32'h0;
block0_ctr_we = 0;
block1_ctr_we = 0;
if (block_ctr_set)
begin
block0_ctr_new = ctr[31 : 00];
block1_ctr_new = ctr[63 : 32];
block0_ctr_we = 1;
block1_ctr_we = 1;
end
if (block_ctr_inc)
begin
block0_ctr_new = block0_ctr_reg + 1;
block0_ctr_we = 1;
// Avoid chaining the 32-bit adders.
if (block0_ctr_reg == 32'hffffffff)
begin
block1_ctr_new = block1_ctr_reg + 1;
block1_ctr_we = 1;
end
end
end // block_ctr
//----------------------------------------------------------------
// chacha_ctrl_fsm
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : chacha_ctrl_fsm
init_state = 0;
update_state = 0;
update_output = 0;
qr_ctr_inc = 0;
qr_ctr_rst = 0;
dr_ctr_inc = 0;
dr_ctr_rst = 0;
block_ctr_inc = 0;
block_ctr_set = 0;
ready_new = 0;
ready_we = 0;
data_out_valid_new = 0;
data_out_valid_we = 0;
chacha_ctrl_new = CTRL_IDLE;
chacha_ctrl_we = 0;
case (chacha_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
block_ctr_set = 1;
ready_new = 0;
ready_we = 1;
chacha_ctrl_new = CTRL_INIT;
chacha_ctrl_we = 1;
end
end
CTRL_INIT:
begin
init_state = 1;
qr_ctr_rst = 1;
dr_ctr_rst = 1;
chacha_ctrl_new = CTRL_ROUNDS;
chacha_ctrl_we = 1;
end
CTRL_ROUNDS:
begin
update_state = 1;
qr_ctr_inc = 1;
if (qr_ctr_reg == QR1)
begin
dr_ctr_inc = 1;
if (dr_ctr_reg == (rounds[4 : 1] - 1))
begin
chacha_ctrl_new = CTRL_FINALIZE;
chacha_ctrl_we = 1;
end
end
end
CTRL_FINALIZE:
begin
ready_new = 1;
ready_we = 1;
update_output = 1;
data_out_valid_new = 1;
data_out_valid_we = 1;
chacha_ctrl_new = CTRL_DONE;
chacha_ctrl_we = 1;
end
CTRL_DONE:
begin
if (init)
begin
ready_new = 0;
ready_we = 1;
data_out_valid_new = 0;
data_out_valid_we = 1;
block_ctr_set = 1;
chacha_ctrl_new = CTRL_INIT;
chacha_ctrl_we = 1;
end
else if (next)
begin
ready_new = 0;
ready_we = 1;
data_out_valid_new = 0;
data_out_valid_we = 1;
block_ctr_inc = 1;
chacha_ctrl_new = CTRL_INIT;
chacha_ctrl_we = 1;
end
end
default:
begin
end
endcase // case (chacha_ctrl_reg)
end // chacha_ctrl_fsm
endmodule // chacha_core
//======================================================================
// EOF chacha_core.v
//======================================================================
|
`include "seeed_tft_defines.v"
module seeed_tft_command (
input rst,
input clk,
output [31:0] debug,
//Control Signals
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output reg [7:0] o_cmd_data,
input i_enable,
input i_cmd_rs,
output reg o_cmd_finished,
//Physical Signals
output o_cmd_mode,
output reg o_write,
output reg o_read,
output reg [7:0] o_data_out,
input [7:0] i_data_in,
output reg o_data_out_en
);
//Local Parameters
localparam IDLE = 4'h0;
localparam DELAY = 4'h1;
localparam FINISHED = 4'h2;
//Registers/Wires
reg [3:0] state;
reg [7:0] count;
//Submodules
//Asynchronous Logic
assign o_cmd_mode = i_cmd_rs;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
o_data_out_en <= 0;
o_data_out <= 0;
o_cmd_finished <= 0;
o_cmd_data <= 0;
o_write <= 0;
o_read <= 0;
count <= 0;
end
else begin
//Strobes
o_cmd_finished <= 0;
if (count < `DELAY_COUNT) begin
count <= count + 1;
end
//State Machine
case (state)
IDLE: begin
o_write <= 0;
o_read <= 0;
count <= `DELAY_COUNT;
o_data_out_en <= 0;
if (i_cmd_write_stb) begin
//Change the bus to an output
o_data_out_en <= 1;
//Put the data on the bus
o_data_out <= i_cmd_data;
o_write <= 1;
state <= DELAY;
count <= 0;
end
else if (i_cmd_read_stb) begin
//Change the bus to an input
o_data_out_en <= 0;
o_read <= 1;
state <= DELAY;
count <= 0;
end
end
DELAY: begin
if (count >= `DELAY_COUNT) begin
state <= FINISHED;
end
end
FINISHED: begin
o_write <= 0;
o_read <= 0;
if (!o_data_out_en) begin
//XXX: The appliction note doesn't describe how to explicitly read
//and the protocol is different from the 8080 MCU interface
o_cmd_data <= i_data_in;
end
o_cmd_finished <= 1;
state <= IDLE;
end
endcase
end
end
endmodule
|
module butterfly1_32(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [15:0] i_0;
input signed [15:0] i_1;
input signed [15:0] i_2;
input signed [15:0] i_3;
input signed [15:0] i_4;
input signed [15:0] i_5;
input signed [15:0] i_6;
input signed [15:0] i_7;
input signed [15:0] i_8;
input signed [15:0] i_9;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
output signed [16:0] o_0;
output signed [16:0] o_1;
output signed [16:0] o_2;
output signed [16:0] o_3;
output signed [16:0] o_4;
output signed [16:0] o_5;
output signed [16:0] o_6;
output signed [16:0] o_7;
output signed [16:0] o_8;
output signed [16:0] o_9;
output signed [16:0] o_10;
output signed [16:0] o_11;
output signed [16:0] o_12;
output signed [16:0] o_13;
output signed [16:0] o_14;
output signed [16:0] o_15;
output signed [16:0] o_16;
output signed [16:0] o_17;
output signed [16:0] o_18;
output signed [16:0] o_19;
output signed [16:0] o_20;
output signed [16:0] o_21;
output signed [16:0] o_22;
output signed [16:0] o_23;
output signed [16:0] o_24;
output signed [16:0] o_25;
output signed [16:0] o_26;
output signed [16:0] o_27;
output signed [16:0] o_28;
output signed [16:0] o_29;
output signed [16:0] o_30;
output signed [16:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [16:0] b_0;
wire signed [16:0] b_1;
wire signed [16:0] b_2;
wire signed [16:0] b_3;
wire signed [16:0] b_4;
wire signed [16:0] b_5;
wire signed [16:0] b_6;
wire signed [16:0] b_7;
wire signed [16:0] b_8;
wire signed [16:0] b_9;
wire signed [16:0] b_10;
wire signed [16:0] b_11;
wire signed [16:0] b_12;
wire signed [16:0] b_13;
wire signed [16:0] b_14;
wire signed [16:0] b_15;
wire signed [16:0] b_16;
wire signed [16:0] b_17;
wire signed [16:0] b_18;
wire signed [16:0] b_19;
wire signed [16:0] b_20;
wire signed [16:0] b_21;
wire signed [16:0] b_22;
wire signed [16:0] b_23;
wire signed [16:0] b_24;
wire signed [16:0] b_25;
wire signed [16:0] b_26;
wire signed [16:0] b_27;
wire signed [16:0] b_28;
wire signed [16:0] b_29;
wire signed [16:0] b_30;
wire signed [16:0] b_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_31;
assign b_1=i_1+i_30;
assign b_2=i_2+i_29;
assign b_3=i_3+i_28;
assign b_4=i_4+i_27;
assign b_5=i_5+i_26;
assign b_6=i_6+i_25;
assign b_7=i_7+i_24;
assign b_8=i_8+i_23;
assign b_9=i_9+i_22;
assign b_10=i_10+i_21;
assign b_11=i_11+i_20;
assign b_12=i_12+i_19;
assign b_13=i_13+i_18;
assign b_14=i_14+i_17;
assign b_15=i_15+i_16;
assign b_16=i_15-i_16;
assign b_17=i_14-i_17;
assign b_18=i_13-i_18;
assign b_19=i_12-i_19;
assign b_20=i_11-i_20;
assign b_21=i_10-i_21;
assign b_22=i_9-i_22;
assign b_23=i_8-i_23;
assign b_24=i_7-i_24;
assign b_25=i_6-i_25;
assign b_26=i_5-i_26;
assign b_27=i_4-i_27;
assign b_28=i_3-i_28;
assign b_29=i_2-i_29;
assign b_30=i_1-i_30;
assign b_31=i_0-i_31;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
assign o_8=enable?b_8:i_8;
assign o_9=enable?b_9:i_9;
assign o_10=enable?b_10:i_10;
assign o_11=enable?b_11:i_11;
assign o_12=enable?b_12:i_12;
assign o_13=enable?b_13:i_13;
assign o_14=enable?b_14:i_14;
assign o_15=enable?b_15:i_15;
assign o_16=enable?b_16:i_16;
assign o_17=enable?b_17:i_17;
assign o_18=enable?b_18:i_18;
assign o_19=enable?b_19:i_19;
assign o_20=enable?b_20:i_20;
assign o_21=enable?b_21:i_21;
assign o_22=enable?b_22:i_22;
assign o_23=enable?b_23:i_23;
assign o_24=enable?b_24:i_24;
assign o_25=enable?b_25:i_25;
assign o_26=enable?b_26:i_26;
assign o_27=enable?b_27:i_27;
assign o_28=enable?b_28:i_28;
assign o_29=enable?b_29:i_29;
assign o_30=enable?b_30:i_30;
assign o_31=enable?b_31:i_31;
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
------------------ (E_Plus)
P t1 t2 || n1 + n2
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit and state a few definitions and
theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.) *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
induction Hy1; intros y2 Hy2.
- (* ST_PlusConstConst *) inversion Hy2.
+ (* ST_PlusConstConst *) reflexivity.
+ (* ST_Plus1 *) inversion H2.
+ (* ST_Plus2 *) inversion H2.
- (* ST_Plus1 *) inversion Hy2.
+ (* ST_PlusConstConst *) rewrite <- H0 in Hy1. inversion Hy1.
+ (* ST_Plus1 *)
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
+ (* ST_Plus2 *) rewrite <- H in Hy1. inversion Hy1.
- (* ST_Plus2 *) inversion Hy2.
+ (* ST_PlusConstConst *) rewrite <- H1 in Hy1. inversion Hy1.
+ (* ST_Plus1 *) inversion H2.
+ (* ST_Plus2 *)
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
(** There is some annoying repetition in this proof.
Each use of [inversion Hy2] results in three subcases,
only one of which is relevant (the one which matches the
current case in the induction on [Hy1]). The other two
subcases need to be dismissed by finding the contradiction
among the hypotheses and doing inversion on it.
There is a tactic called [solve by inversion] defined in [SfLib.v]
that can be of use in such cases. It will solve the goal if it
can be solved by inverting some hypothesis; otherwise, it fails.
(There are variants [solve by inversion 2] and [solve by inversion 3]
that work if two or three consecutive inversions will solve the goal.)
The example below shows how a proof of the previous theorem can be
simplified using this tactic.
*)
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
induction Hy1; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
- (* ST_PlusConstConst *) reflexivity.
- (* ST_Plus1 *)
apply IHHy1 in H2. rewrite H2. reflexivity.
- (* ST_Plus2 *)
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
induction t.
- (* C *) left. apply v_const.
- (* P *) right. inversion IHt1.
+ (* l *) inversion IHt2.
* (* l *) inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
* (* r *) inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
+ (* r *) inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
{ (* Proof of assertion *) apply strong_progress. }
inversion G.
+ (* l *) apply H0.
+ (* r *) apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* FILL IN HERE *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* FILL IN HERE *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
induction G.
- (* multi_refl *) assumption.
- (* multi_step *)
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. induction H.
- (* multi_refl *) apply multi_refl.
- (* multi_step *) apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
induction t.
- (* C *)
exists (C n).
split.
+ (* l *) apply multi_refl.
+ (* r *)
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
- (* P *)
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
+ (* l *)
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
+ (* r *)
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date$ *)
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Xess Traffic Cop ////
//// ////
//// This file is part of the OR1K test application ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// This block connectes the RISC and peripheral controller ////
//// cores together. ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 OpenCores ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: tc_top.v,v $
// Revision 1.4 2004/04/05 08:44:34 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2 2002/03/29 20:57:30 lampret
// Removed unused ports wb_clki and wb_rst_i
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
//
// Width of address bus
//
`define TC_AW 32
//
// Width of data bus
//
`define TC_DW 32
//
// Width of byte select bus
//
`define TC_BSW 4
//
// Width of WB target inputs (coming from WB slave)
//
// data bus width + ack + err
//
`define TC_TIN_W `TC_DW+1+1
//
// Width of WB initiator inputs (coming from WB masters)
//
// cyc + stb + address bus width +
// byte select bus width + we + data bus width
//
`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW
//
// Traffic Cop Top
//
module minsoc_tc_top (
wb_clk_i,
wb_rst_i,
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
i0_wb_dat_i,
i0_wb_dat_o,
i0_wb_ack_o,
i0_wb_err_o,
i0_wb_cti_i,
i0_wb_bte_i,
i1_wb_cyc_i,
i1_wb_stb_i,
i1_wb_adr_i,
i1_wb_sel_i,
i1_wb_we_i,
i1_wb_dat_i,
i1_wb_dat_o,
i1_wb_ack_o,
i1_wb_err_o,
i1_wb_cti_i,
i1_wb_bte_i,
i2_wb_cyc_i,
i2_wb_stb_i,
i2_wb_adr_i,
i2_wb_sel_i,
i2_wb_we_i,
i2_wb_dat_i,
i2_wb_dat_o,
i2_wb_ack_o,
i2_wb_err_o,
i2_wb_cti_i,
i2_wb_bte_i,
i3_wb_cyc_i,
i3_wb_stb_i,
i3_wb_adr_i,
i3_wb_sel_i,
i3_wb_we_i,
i3_wb_dat_i,
i3_wb_dat_o,
i3_wb_ack_o,
i3_wb_err_o,
i3_wb_cti_i,
i3_wb_bte_i,
i4_wb_cyc_i,
i4_wb_stb_i,
i4_wb_adr_i,
i4_wb_sel_i,
i4_wb_we_i,
i4_wb_dat_i,
i4_wb_dat_o,
i4_wb_ack_o,
i4_wb_err_o,
i4_wb_cti_i,
i4_wb_bte_i,
i5_wb_cyc_i,
i5_wb_stb_i,
i5_wb_adr_i,
i5_wb_sel_i,
i5_wb_we_i,
i5_wb_dat_i,
i5_wb_dat_o,
i5_wb_ack_o,
i5_wb_err_o,
i5_wb_cti_i,
i5_wb_bte_i,
i6_wb_cyc_i,
i6_wb_stb_i,
i6_wb_adr_i,
i6_wb_sel_i,
i6_wb_we_i,
i6_wb_dat_i,
i6_wb_dat_o,
i6_wb_ack_o,
i6_wb_err_o,
i6_wb_cti_i,
i6_wb_bte_i,
i7_wb_cyc_i,
i7_wb_stb_i,
i7_wb_adr_i,
i7_wb_sel_i,
i7_wb_we_i,
i7_wb_dat_i,
i7_wb_dat_o,
i7_wb_ack_o,
i7_wb_err_o,
i7_wb_cti_i,
i7_wb_bte_i,
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
t0_wb_dat_o,
t0_wb_dat_i,
t0_wb_ack_i,
t0_wb_err_i,
t0_wb_cti_o,
t0_wb_bte_o,
t1_wb_cyc_o,
t1_wb_stb_o,
t1_wb_adr_o,
t1_wb_sel_o,
t1_wb_we_o,
t1_wb_dat_o,
t1_wb_dat_i,
t1_wb_ack_i,
t1_wb_err_i,
t1_wb_cti_o,
t1_wb_bte_o,
t2_wb_cyc_o,
t2_wb_stb_o,
t2_wb_adr_o,
t2_wb_sel_o,
t2_wb_we_o,
t2_wb_dat_o,
t2_wb_dat_i,
t2_wb_ack_i,
t2_wb_err_i,
t2_wb_cti_o,
t2_wb_bte_o,
t3_wb_cyc_o,
t3_wb_stb_o,
t3_wb_adr_o,
t3_wb_sel_o,
t3_wb_we_o,
t3_wb_dat_o,
t3_wb_dat_i,
t3_wb_ack_i,
t3_wb_err_i,
t3_wb_cti_o,
t3_wb_bte_o,
t4_wb_cyc_o,
t4_wb_stb_o,
t4_wb_adr_o,
t4_wb_sel_o,
t4_wb_we_o,
t4_wb_dat_o,
t4_wb_dat_i,
t4_wb_ack_i,
t4_wb_err_i,
t4_wb_cti_o,
t4_wb_bte_o,
t5_wb_cyc_o,
t5_wb_stb_o,
t5_wb_adr_o,
t5_wb_sel_o,
t5_wb_we_o,
t5_wb_dat_o,
t5_wb_dat_i,
t5_wb_ack_i,
t5_wb_err_i,
t5_wb_cti_o,
t5_wb_bte_o,
t6_wb_cyc_o,
t6_wb_stb_o,
t6_wb_adr_o,
t6_wb_sel_o,
t6_wb_we_o,
t6_wb_dat_o,
t6_wb_dat_i,
t6_wb_ack_i,
t6_wb_err_i,
t6_wb_cti_o,
t6_wb_bte_o,
t7_wb_cyc_o,
t7_wb_stb_o,
t7_wb_adr_o,
t7_wb_sel_o,
t7_wb_we_o,
t7_wb_dat_o,
t7_wb_dat_i,
t7_wb_ack_i,
t7_wb_err_i,
t7_wb_cti_o,
t7_wb_bte_o,
t8_wb_cyc_o,
t8_wb_stb_o,
t8_wb_adr_o,
t8_wb_sel_o,
t8_wb_we_o,
t8_wb_dat_o,
t8_wb_dat_i,
t8_wb_ack_i,
t8_wb_err_i,
t8_wb_cti_o,
t8_wb_bte_o
);
//
// Parameters
//
parameter t0_addr_w = 4;
parameter t0_addr = 4'd8;
parameter t1_addr_w = 4;
parameter t1_addr = 4'd0;
parameter t28c_addr_w = 4;
parameter t28_addr = 4'd0;
parameter t28i_addr_w = 4;
parameter t2_addr = 4'd1;
parameter t3_addr = 4'd2;
parameter t4_addr = 4'd3;
parameter t5_addr = 4'd4;
parameter t6_addr = 4'd5;
parameter t7_addr = 4'd6;
parameter t8_addr = 4'd7;
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f connecting initiator 0
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
input [`TC_DW-1:0] i0_wb_dat_i;
output [`TC_DW-1:0] i0_wb_dat_o;
output i0_wb_ack_o;
output i0_wb_err_o;
input [2:0] i0_wb_cti_i;
input [1:0] i0_wb_bte_i;
//
// WB slave i/f connecting initiator 1
//
input i1_wb_cyc_i;
input i1_wb_stb_i;
input [`TC_AW-1:0] i1_wb_adr_i;
input [`TC_BSW-1:0] i1_wb_sel_i;
input i1_wb_we_i;
input [`TC_DW-1:0] i1_wb_dat_i;
output [`TC_DW-1:0] i1_wb_dat_o;
output i1_wb_ack_o;
output i1_wb_err_o;
input [2:0] i1_wb_cti_i;
input [1:0] i1_wb_bte_i;
//
// WB slave i/f connecting initiator 2
//
input i2_wb_cyc_i;
input i2_wb_stb_i;
input [`TC_AW-1:0] i2_wb_adr_i;
input [`TC_BSW-1:0] i2_wb_sel_i;
input i2_wb_we_i;
input [`TC_DW-1:0] i2_wb_dat_i;
output [`TC_DW-1:0] i2_wb_dat_o;
output i2_wb_ack_o;
output i2_wb_err_o;
input [2:0] i2_wb_cti_i;
input [1:0] i2_wb_bte_i;
//
// WB slave i/f connecting initiator 3
//
input i3_wb_cyc_i;
input i3_wb_stb_i;
input [`TC_AW-1:0] i3_wb_adr_i;
input [`TC_BSW-1:0] i3_wb_sel_i;
input i3_wb_we_i;
input [`TC_DW-1:0] i3_wb_dat_i;
output [`TC_DW-1:0] i3_wb_dat_o;
output i3_wb_ack_o;
output i3_wb_err_o;
input [2:0] i3_wb_cti_i;
input [1:0] i3_wb_bte_i;
//
// WB slave i/f connecting initiator 4
//
input i4_wb_cyc_i;
input i4_wb_stb_i;
input [`TC_AW-1:0] i4_wb_adr_i;
input [`TC_BSW-1:0] i4_wb_sel_i;
input i4_wb_we_i;
input [`TC_DW-1:0] i4_wb_dat_i;
output [`TC_DW-1:0] i4_wb_dat_o;
output i4_wb_ack_o;
output i4_wb_err_o;
input [2:0] i4_wb_cti_i;
input [1:0] i4_wb_bte_i;
//
// WB slave i/f connecting initiator 5
//
input i5_wb_cyc_i;
input i5_wb_stb_i;
input [`TC_AW-1:0] i5_wb_adr_i;
input [`TC_BSW-1:0] i5_wb_sel_i;
input i5_wb_we_i;
input [`TC_DW-1:0] i5_wb_dat_i;
output [`TC_DW-1:0] i5_wb_dat_o;
output i5_wb_ack_o;
output i5_wb_err_o;
input [2:0] i5_wb_cti_i;
input [1:0] i5_wb_bte_i;
//
// WB slave i/f connecting initiator 6
//
input i6_wb_cyc_i;
input i6_wb_stb_i;
input [`TC_AW-1:0] i6_wb_adr_i;
input [`TC_BSW-1:0] i6_wb_sel_i;
input i6_wb_we_i;
input [`TC_DW-1:0] i6_wb_dat_i;
output [`TC_DW-1:0] i6_wb_dat_o;
output i6_wb_ack_o;
output i6_wb_err_o;
input [2:0] i6_wb_cti_i;
input [1:0] i6_wb_bte_i;
//
// WB slave i/f connecting initiator 7
//
input i7_wb_cyc_i;
input i7_wb_stb_i;
input [`TC_AW-1:0] i7_wb_adr_i;
input [`TC_BSW-1:0] i7_wb_sel_i;
input i7_wb_we_i;
input [`TC_DW-1:0] i7_wb_dat_i;
output [`TC_DW-1:0] i7_wb_dat_o;
output i7_wb_ack_o;
output i7_wb_err_o;
input [2:0] i7_wb_cti_i;
input [1:0] i7_wb_bte_i;
//
// WB master i/f connecting target 0
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
output [`TC_DW-1:0] t0_wb_dat_o;
input [`TC_DW-1:0] t0_wb_dat_i;
input t0_wb_ack_i;
input t0_wb_err_i;
output [2:0] t0_wb_cti_o;
output [1:0] t0_wb_bte_o;
//
// WB master i/f connecting target 1
//
output t1_wb_cyc_o;
output t1_wb_stb_o;
output [`TC_AW-1:0] t1_wb_adr_o;
output [`TC_BSW-1:0] t1_wb_sel_o;
output t1_wb_we_o;
output [`TC_DW-1:0] t1_wb_dat_o;
input [`TC_DW-1:0] t1_wb_dat_i;
input t1_wb_ack_i;
input t1_wb_err_i;
output [2:0] t1_wb_cti_o;
output [1:0] t1_wb_bte_o;
//
// WB master i/f connecting target 2
//
output t2_wb_cyc_o;
output t2_wb_stb_o;
output [`TC_AW-1:0] t2_wb_adr_o;
output [`TC_BSW-1:0] t2_wb_sel_o;
output t2_wb_we_o;
output [`TC_DW-1:0] t2_wb_dat_o;
input [`TC_DW-1:0] t2_wb_dat_i;
input t2_wb_ack_i;
input t2_wb_err_i;
output [2:0] t2_wb_cti_o;
output [1:0] t2_wb_bte_o;
//
// WB master i/f connecting target 3
//
output t3_wb_cyc_o;
output t3_wb_stb_o;
output [`TC_AW-1:0] t3_wb_adr_o;
output [`TC_BSW-1:0] t3_wb_sel_o;
output t3_wb_we_o;
output [`TC_DW-1:0] t3_wb_dat_o;
input [`TC_DW-1:0] t3_wb_dat_i;
input t3_wb_ack_i;
input t3_wb_err_i;
output [2:0] t3_wb_cti_o;
output [1:0] t3_wb_bte_o;
//
// WB master i/f connecting target 4
//
output t4_wb_cyc_o;
output t4_wb_stb_o;
output [`TC_AW-1:0] t4_wb_adr_o;
output [`TC_BSW-1:0] t4_wb_sel_o;
output t4_wb_we_o;
output [`TC_DW-1:0] t4_wb_dat_o;
input [`TC_DW-1:0] t4_wb_dat_i;
input t4_wb_ack_i;
input t4_wb_err_i;
output [2:0] t4_wb_cti_o;
output [1:0] t4_wb_bte_o;
//
// WB master i/f connecting target 5
//
output t5_wb_cyc_o;
output t5_wb_stb_o;
output [`TC_AW-1:0] t5_wb_adr_o;
output [`TC_BSW-1:0] t5_wb_sel_o;
output t5_wb_we_o;
output [`TC_DW-1:0] t5_wb_dat_o;
input [`TC_DW-1:0] t5_wb_dat_i;
input t5_wb_ack_i;
input t5_wb_err_i;
output [2:0] t5_wb_cti_o;
output [1:0] t5_wb_bte_o;
//
// WB master i/f connecting target 6
//
output t6_wb_cyc_o;
output t6_wb_stb_o;
output [`TC_AW-1:0] t6_wb_adr_o;
output [`TC_BSW-1:0] t6_wb_sel_o;
output t6_wb_we_o;
output [`TC_DW-1:0] t6_wb_dat_o;
input [`TC_DW-1:0] t6_wb_dat_i;
input t6_wb_ack_i;
input t6_wb_err_i;
output [2:0] t6_wb_cti_o;
output [1:0] t6_wb_bte_o;
//
// WB master i/f connecting target 7
//
output t7_wb_cyc_o;
output t7_wb_stb_o;
output [`TC_AW-1:0] t7_wb_adr_o;
output [`TC_BSW-1:0] t7_wb_sel_o;
output t7_wb_we_o;
output [`TC_DW-1:0] t7_wb_dat_o;
input [`TC_DW-1:0] t7_wb_dat_i;
input t7_wb_ack_i;
input t7_wb_err_i;
output [2:0] t7_wb_cti_o;
output [1:0] t7_wb_bte_o;
//
// WB master i/f connecting target 8
//
output t8_wb_cyc_o;
output t8_wb_stb_o;
output [`TC_AW-1:0] t8_wb_adr_o;
output [`TC_BSW-1:0] t8_wb_sel_o;
output t8_wb_we_o;
output [`TC_DW-1:0] t8_wb_dat_o;
input [`TC_DW-1:0] t8_wb_dat_i;
input t8_wb_ack_i;
input t8_wb_err_i;
output [2:0] t8_wb_cti_o;
output [1:0] t8_wb_bte_o;
//
// Internal wires & registers
//
//
// Outputs for initiators from both mi_to_st blocks
//
wire [`TC_DW-1:0] xi0_wb_dat_o;
wire xi0_wb_ack_o;
wire xi0_wb_err_o;
wire [`TC_DW-1:0] xi1_wb_dat_o;
wire xi1_wb_ack_o;
wire xi1_wb_err_o;
wire [`TC_DW-1:0] xi2_wb_dat_o;
wire xi2_wb_ack_o;
wire xi2_wb_err_o;
wire [`TC_DW-1:0] xi3_wb_dat_o;
wire xi3_wb_ack_o;
wire xi3_wb_err_o;
wire [`TC_DW-1:0] xi4_wb_dat_o;
wire xi4_wb_ack_o;
wire xi4_wb_err_o;
wire [`TC_DW-1:0] xi5_wb_dat_o;
wire xi5_wb_ack_o;
wire xi5_wb_err_o;
wire [`TC_DW-1:0] xi6_wb_dat_o;
wire xi6_wb_ack_o;
wire xi6_wb_err_o;
wire [`TC_DW-1:0] xi7_wb_dat_o;
wire xi7_wb_ack_o;
wire xi7_wb_err_o;
wire [`TC_DW-1:0] yi0_wb_dat_o;
wire yi0_wb_ack_o;
wire yi0_wb_err_o;
wire [`TC_DW-1:0] yi1_wb_dat_o;
wire yi1_wb_ack_o;
wire yi1_wb_err_o;
wire [`TC_DW-1:0] yi2_wb_dat_o;
wire yi2_wb_ack_o;
wire yi2_wb_err_o;
wire [`TC_DW-1:0] yi3_wb_dat_o;
wire yi3_wb_ack_o;
wire yi3_wb_err_o;
wire [`TC_DW-1:0] yi4_wb_dat_o;
wire yi4_wb_ack_o;
wire yi4_wb_err_o;
wire [`TC_DW-1:0] yi5_wb_dat_o;
wire yi5_wb_ack_o;
wire yi5_wb_err_o;
wire [`TC_DW-1:0] yi6_wb_dat_o;
wire yi6_wb_ack_o;
wire yi6_wb_err_o;
wire [`TC_DW-1:0] yi7_wb_dat_o;
wire yi7_wb_ack_o;
wire yi7_wb_err_o;
//
// Intermediate signals connecting peripheral channel's
// mi_to_st and si_to_mt blocks.
//
wire z_wb_cyc_i;
wire z_wb_stb_i;
wire [`TC_AW-1:0] z_wb_adr_i;
wire [`TC_BSW-1:0] z_wb_sel_i;
wire z_wb_we_i;
wire [`TC_DW-1:0] z_wb_dat_i;
wire [`TC_DW-1:0] z_wb_dat_t;
wire z_wb_ack_t;
wire z_wb_err_t;
wire [2:0] z_wb_cti_i;
wire [1:0] z_wb_bte_i;
//
// Outputs for initiators are ORed from both mi_to_st blocks
//
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
assign i0_wb_err_o = xi0_wb_err_o | yi0_wb_err_o;
assign i1_wb_dat_o = xi1_wb_dat_o | yi1_wb_dat_o;
assign i1_wb_ack_o = xi1_wb_ack_o | yi1_wb_ack_o;
assign i1_wb_err_o = xi1_wb_err_o | yi1_wb_err_o;
assign i2_wb_dat_o = xi2_wb_dat_o | yi2_wb_dat_o;
assign i2_wb_ack_o = xi2_wb_ack_o | yi2_wb_ack_o;
assign i2_wb_err_o = xi2_wb_err_o | yi2_wb_err_o;
assign i3_wb_dat_o = xi3_wb_dat_o | yi3_wb_dat_o;
assign i3_wb_ack_o = xi3_wb_ack_o | yi3_wb_ack_o;
assign i3_wb_err_o = xi3_wb_err_o | yi3_wb_err_o;
assign i4_wb_dat_o = xi4_wb_dat_o | yi4_wb_dat_o;
assign i4_wb_ack_o = xi4_wb_ack_o | yi4_wb_ack_o;
assign i4_wb_err_o = xi4_wb_err_o | yi4_wb_err_o;
assign i5_wb_dat_o = xi5_wb_dat_o | yi5_wb_dat_o;
assign i5_wb_ack_o = xi5_wb_ack_o | yi5_wb_ack_o;
assign i5_wb_err_o = xi5_wb_err_o | yi5_wb_err_o;
assign i6_wb_dat_o = xi6_wb_dat_o | yi6_wb_dat_o;
assign i6_wb_ack_o = xi6_wb_ack_o | yi6_wb_ack_o;
assign i6_wb_err_o = xi6_wb_err_o | yi6_wb_err_o;
assign i7_wb_dat_o = xi7_wb_dat_o | yi7_wb_dat_o;
assign i7_wb_ack_o = xi7_wb_ack_o | yi7_wb_ack_o;
assign i7_wb_err_o = xi7_wb_err_o | yi7_wb_err_o;
//
// From initiators to target 0
//
tc_mi_to_st #(t0_addr_w, t0_addr,
0, t0_addr_w, t0_addr) t0_ch(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.i0_wb_cyc_i(i0_wb_cyc_i),
.i0_wb_stb_i(i0_wb_stb_i),
.i0_wb_adr_i(i0_wb_adr_i),
.i0_wb_sel_i(i0_wb_sel_i),
.i0_wb_we_i(i0_wb_we_i),
.i0_wb_dat_i(i0_wb_dat_i),
.i0_wb_dat_o(xi0_wb_dat_o),
.i0_wb_ack_o(xi0_wb_ack_o),
.i0_wb_err_o(xi0_wb_err_o),
.i0_wb_cti_i(i0_wb_cti_i),
.i0_wb_bte_i(i0_wb_bte_i),
.i1_wb_cyc_i(i1_wb_cyc_i),
.i1_wb_stb_i(i1_wb_stb_i),
.i1_wb_adr_i(i1_wb_adr_i),
.i1_wb_sel_i(i1_wb_sel_i),
.i1_wb_we_i(i1_wb_we_i),
.i1_wb_dat_i(i1_wb_dat_i),
.i1_wb_dat_o(xi1_wb_dat_o),
.i1_wb_ack_o(xi1_wb_ack_o),
.i1_wb_err_o(xi1_wb_err_o),
.i1_wb_cti_i(i1_wb_cti_i),
.i1_wb_bte_i(i1_wb_bte_i),
.i2_wb_cyc_i(i2_wb_cyc_i),
.i2_wb_stb_i(i2_wb_stb_i),
.i2_wb_adr_i(i2_wb_adr_i),
.i2_wb_sel_i(i2_wb_sel_i),
.i2_wb_we_i(i2_wb_we_i),
.i2_wb_dat_i(i2_wb_dat_i),
.i2_wb_dat_o(xi2_wb_dat_o),
.i2_wb_ack_o(xi2_wb_ack_o),
.i2_wb_err_o(xi2_wb_err_o),
.i2_wb_cti_i(i2_wb_cti_i),
.i2_wb_bte_i(i2_wb_bte_i),
.i3_wb_cyc_i(i3_wb_cyc_i),
.i3_wb_stb_i(i3_wb_stb_i),
.i3_wb_adr_i(i3_wb_adr_i),
.i3_wb_sel_i(i3_wb_sel_i),
.i3_wb_we_i(i3_wb_we_i),
.i3_wb_dat_i(i3_wb_dat_i),
.i3_wb_dat_o(xi3_wb_dat_o),
.i3_wb_ack_o(xi3_wb_ack_o),
.i3_wb_err_o(xi3_wb_err_o),
.i3_wb_cti_i(i3_wb_cti_i),
.i3_wb_bte_i(i3_wb_bte_i),
.i4_wb_cyc_i(i4_wb_cyc_i),
.i4_wb_stb_i(i4_wb_stb_i),
.i4_wb_adr_i(i4_wb_adr_i),
.i4_wb_sel_i(i4_wb_sel_i),
.i4_wb_we_i(i4_wb_we_i),
.i4_wb_dat_i(i4_wb_dat_i),
.i4_wb_dat_o(xi4_wb_dat_o),
.i4_wb_ack_o(xi4_wb_ack_o),
.i4_wb_err_o(xi4_wb_err_o),
.i4_wb_cti_i(i4_wb_cti_i),
.i4_wb_bte_i(i4_wb_bte_i),
.i5_wb_cyc_i(i5_wb_cyc_i),
.i5_wb_stb_i(i5_wb_stb_i),
.i5_wb_adr_i(i5_wb_adr_i),
.i5_wb_sel_i(i5_wb_sel_i),
.i5_wb_we_i(i5_wb_we_i),
.i5_wb_dat_i(i5_wb_dat_i),
.i5_wb_dat_o(xi5_wb_dat_o),
.i5_wb_ack_o(xi5_wb_ack_o),
.i5_wb_err_o(xi5_wb_err_o),
.i5_wb_cti_i(i5_wb_cti_i),
.i5_wb_bte_i(i5_wb_bte_i),
.i6_wb_cyc_i(i6_wb_cyc_i),
.i6_wb_stb_i(i6_wb_stb_i),
.i6_wb_adr_i(i6_wb_adr_i),
.i6_wb_sel_i(i6_wb_sel_i),
.i6_wb_we_i(i6_wb_we_i),
.i6_wb_dat_i(i6_wb_dat_i),
.i6_wb_dat_o(xi6_wb_dat_o),
.i6_wb_ack_o(xi6_wb_ack_o),
.i6_wb_err_o(xi6_wb_err_o),
.i6_wb_cti_i(i6_wb_cti_i),
.i6_wb_bte_i(i6_wb_bte_i),
.i7_wb_cyc_i(i7_wb_cyc_i),
.i7_wb_stb_i(i7_wb_stb_i),
.i7_wb_adr_i(i7_wb_adr_i),
.i7_wb_sel_i(i7_wb_sel_i),
.i7_wb_we_i(i7_wb_we_i),
.i7_wb_dat_i(i7_wb_dat_i),
.i7_wb_dat_o(xi7_wb_dat_o),
.i7_wb_ack_o(xi7_wb_ack_o),
.i7_wb_err_o(xi7_wb_err_o),
.i7_wb_cti_i(i7_wb_cti_i),
.i7_wb_bte_i(i7_wb_bte_i),
.t0_wb_cyc_o(t0_wb_cyc_o),
.t0_wb_stb_o(t0_wb_stb_o),
.t0_wb_adr_o(t0_wb_adr_o),
.t0_wb_sel_o(t0_wb_sel_o),
.t0_wb_we_o(t0_wb_we_o),
.t0_wb_dat_o(t0_wb_dat_o),
.t0_wb_dat_i(t0_wb_dat_i),
.t0_wb_ack_i(t0_wb_ack_i),
.t0_wb_err_i(t0_wb_err_i),
.t0_wb_cti_o(t0_wb_cti_o),
.t0_wb_bte_o(t0_wb_bte_o)
);
//
// From initiators to targets 1-8 (upper part)
//
tc_mi_to_st #(t1_addr_w, t1_addr,
1, t28c_addr_w, t28_addr) t18_ch_upper(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.i0_wb_cyc_i(i0_wb_cyc_i),
.i0_wb_stb_i(i0_wb_stb_i),
.i0_wb_adr_i(i0_wb_adr_i),
.i0_wb_sel_i(i0_wb_sel_i),
.i0_wb_we_i(i0_wb_we_i),
.i0_wb_dat_i(i0_wb_dat_i),
.i0_wb_dat_o(yi0_wb_dat_o),
.i0_wb_ack_o(yi0_wb_ack_o),
.i0_wb_err_o(yi0_wb_err_o),
.i0_wb_cti_i(i0_wb_cti_i),
.i0_wb_bte_i(i0_wb_bte_i),
.i1_wb_cyc_i(i1_wb_cyc_i),
.i1_wb_stb_i(i1_wb_stb_i),
.i1_wb_adr_i(i1_wb_adr_i),
.i1_wb_sel_i(i1_wb_sel_i),
.i1_wb_we_i(i1_wb_we_i),
.i1_wb_dat_i(i1_wb_dat_i),
.i1_wb_dat_o(yi1_wb_dat_o),
.i1_wb_ack_o(yi1_wb_ack_o),
.i1_wb_err_o(yi1_wb_err_o),
.i1_wb_cti_i(i1_wb_cti_i),
.i1_wb_bte_i(i1_wb_bte_i),
.i2_wb_cyc_i(i2_wb_cyc_i),
.i2_wb_stb_i(i2_wb_stb_i),
.i2_wb_adr_i(i2_wb_adr_i),
.i2_wb_sel_i(i2_wb_sel_i),
.i2_wb_we_i(i2_wb_we_i),
.i2_wb_dat_i(i2_wb_dat_i),
.i2_wb_dat_o(yi2_wb_dat_o),
.i2_wb_ack_o(yi2_wb_ack_o),
.i2_wb_err_o(yi2_wb_err_o),
.i2_wb_cti_i(i2_wb_cti_i),
.i2_wb_bte_i(i2_wb_bte_i),
.i3_wb_cyc_i(i3_wb_cyc_i),
.i3_wb_stb_i(i3_wb_stb_i),
.i3_wb_adr_i(i3_wb_adr_i),
.i3_wb_sel_i(i3_wb_sel_i),
.i3_wb_we_i(i3_wb_we_i),
.i3_wb_dat_i(i3_wb_dat_i),
.i3_wb_dat_o(yi3_wb_dat_o),
.i3_wb_ack_o(yi3_wb_ack_o),
.i3_wb_err_o(yi3_wb_err_o),
.i3_wb_cti_i(i3_wb_cti_i),
.i3_wb_bte_i(i3_wb_bte_i),
.i4_wb_cyc_i(i4_wb_cyc_i),
.i4_wb_stb_i(i4_wb_stb_i),
.i4_wb_adr_i(i4_wb_adr_i),
.i4_wb_sel_i(i4_wb_sel_i),
.i4_wb_we_i(i4_wb_we_i),
.i4_wb_dat_i(i4_wb_dat_i),
.i4_wb_dat_o(yi4_wb_dat_o),
.i4_wb_ack_o(yi4_wb_ack_o),
.i4_wb_err_o(yi4_wb_err_o),
.i4_wb_cti_i(i4_wb_cti_i),
.i4_wb_bte_i(i4_wb_bte_i),
.i5_wb_cyc_i(i5_wb_cyc_i),
.i5_wb_stb_i(i5_wb_stb_i),
.i5_wb_adr_i(i5_wb_adr_i),
.i5_wb_sel_i(i5_wb_sel_i),
.i5_wb_we_i(i5_wb_we_i),
.i5_wb_dat_i(i5_wb_dat_i),
.i5_wb_dat_o(yi5_wb_dat_o),
.i5_wb_ack_o(yi5_wb_ack_o),
.i5_wb_err_o(yi5_wb_err_o),
.i5_wb_cti_i(i5_wb_cti_i),
.i5_wb_bte_i(i5_wb_bte_i),
.i6_wb_cyc_i(i6_wb_cyc_i),
.i6_wb_stb_i(i6_wb_stb_i),
.i6_wb_adr_i(i6_wb_adr_i),
.i6_wb_sel_i(i6_wb_sel_i),
.i6_wb_we_i(i6_wb_we_i),
.i6_wb_dat_i(i6_wb_dat_i),
.i6_wb_dat_o(yi6_wb_dat_o),
.i6_wb_ack_o(yi6_wb_ack_o),
.i6_wb_err_o(yi6_wb_err_o),
.i6_wb_cti_i(i6_wb_cti_i),
.i6_wb_bte_i(i6_wb_bte_i),
.i7_wb_cyc_i(i7_wb_cyc_i),
.i7_wb_stb_i(i7_wb_stb_i),
.i7_wb_adr_i(i7_wb_adr_i),
.i7_wb_sel_i(i7_wb_sel_i),
.i7_wb_we_i(i7_wb_we_i),
.i7_wb_dat_i(i7_wb_dat_i),
.i7_wb_dat_o(yi7_wb_dat_o),
.i7_wb_ack_o(yi7_wb_ack_o),
.i7_wb_err_o(yi7_wb_err_o),
.i7_wb_cti_i(i7_wb_cti_i),
.i7_wb_bte_i(i7_wb_bte_i),
.t0_wb_cyc_o(z_wb_cyc_i),
.t0_wb_stb_o(z_wb_stb_i),
.t0_wb_adr_o(z_wb_adr_i),
.t0_wb_sel_o(z_wb_sel_i),
.t0_wb_we_o(z_wb_we_i),
.t0_wb_dat_o(z_wb_dat_i),
.t0_wb_dat_i(z_wb_dat_t),
.t0_wb_ack_i(z_wb_ack_t),
.t0_wb_err_i(z_wb_err_t),
.t0_wb_cti_o(z_wb_cti_i),
.t0_wb_bte_o(z_wb_bte_i)
);
//
// From initiators to targets 1-8 (lower part)
//
tc_si_to_mt #(t1_addr_w, t1_addr, t28i_addr_w, t2_addr, t3_addr,
t4_addr, t5_addr, t6_addr, t7_addr, t8_addr) t18_ch_lower(
.i0_wb_cyc_i(z_wb_cyc_i),
.i0_wb_stb_i(z_wb_stb_i),
.i0_wb_adr_i(z_wb_adr_i),
.i0_wb_sel_i(z_wb_sel_i),
.i0_wb_we_i(z_wb_we_i),
.i0_wb_dat_i(z_wb_dat_i),
.i0_wb_dat_o(z_wb_dat_t),
.i0_wb_ack_o(z_wb_ack_t),
.i0_wb_err_o(z_wb_err_t),
.i0_wb_cti_i(z_wb_cti_i),
.i0_wb_bte_i(z_wb_bte_i),
.t0_wb_cyc_o(t1_wb_cyc_o),
.t0_wb_stb_o(t1_wb_stb_o),
.t0_wb_adr_o(t1_wb_adr_o),
.t0_wb_sel_o(t1_wb_sel_o),
.t0_wb_we_o(t1_wb_we_o),
.t0_wb_dat_o(t1_wb_dat_o),
.t0_wb_dat_i(t1_wb_dat_i),
.t0_wb_ack_i(t1_wb_ack_i),
.t0_wb_err_i(t1_wb_err_i),
.t0_wb_cti_o(t1_wb_cti_o),
.t0_wb_bte_o(t1_wb_bte_o),
.t1_wb_cyc_o(t2_wb_cyc_o),
.t1_wb_stb_o(t2_wb_stb_o),
.t1_wb_adr_o(t2_wb_adr_o),
.t1_wb_sel_o(t2_wb_sel_o),
.t1_wb_we_o(t2_wb_we_o),
.t1_wb_dat_o(t2_wb_dat_o),
.t1_wb_dat_i(t2_wb_dat_i),
.t1_wb_ack_i(t2_wb_ack_i),
.t1_wb_err_i(t2_wb_err_i),
.t1_wb_cti_o(t2_wb_cti_o),
.t1_wb_bte_o(t2_wb_bte_o),
.t2_wb_cyc_o(t3_wb_cyc_o),
.t2_wb_stb_o(t3_wb_stb_o),
.t2_wb_adr_o(t3_wb_adr_o),
.t2_wb_sel_o(t3_wb_sel_o),
.t2_wb_we_o(t3_wb_we_o),
.t2_wb_dat_o(t3_wb_dat_o),
.t2_wb_dat_i(t3_wb_dat_i),
.t2_wb_ack_i(t3_wb_ack_i),
.t2_wb_err_i(t3_wb_err_i),
.t2_wb_cti_o(t3_wb_cti_o),
.t2_wb_bte_o(t3_wb_bte_o),
.t3_wb_cyc_o(t4_wb_cyc_o),
.t3_wb_stb_o(t4_wb_stb_o),
.t3_wb_adr_o(t4_wb_adr_o),
.t3_wb_sel_o(t4_wb_sel_o),
.t3_wb_we_o(t4_wb_we_o),
.t3_wb_dat_o(t4_wb_dat_o),
.t3_wb_dat_i(t4_wb_dat_i),
.t3_wb_ack_i(t4_wb_ack_i),
.t3_wb_err_i(t4_wb_err_i),
.t3_wb_cti_o(t4_wb_cti_o),
.t3_wb_bte_o(t4_wb_bte_o),
.t4_wb_cyc_o(t5_wb_cyc_o),
.t4_wb_stb_o(t5_wb_stb_o),
.t4_wb_adr_o(t5_wb_adr_o),
.t4_wb_sel_o(t5_wb_sel_o),
.t4_wb_we_o(t5_wb_we_o),
.t4_wb_dat_o(t5_wb_dat_o),
.t4_wb_dat_i(t5_wb_dat_i),
.t4_wb_ack_i(t5_wb_ack_i),
.t4_wb_err_i(t5_wb_err_i),
.t4_wb_cti_o(t5_wb_cti_o),
.t4_wb_bte_o(t5_wb_bte_o),
.t5_wb_cyc_o(t6_wb_cyc_o),
.t5_wb_stb_o(t6_wb_stb_o),
.t5_wb_adr_o(t6_wb_adr_o),
.t5_wb_sel_o(t6_wb_sel_o),
.t5_wb_we_o(t6_wb_we_o),
.t5_wb_dat_o(t6_wb_dat_o),
.t5_wb_dat_i(t6_wb_dat_i),
.t5_wb_ack_i(t6_wb_ack_i),
.t5_wb_err_i(t6_wb_err_i),
.t5_wb_cti_o(t6_wb_cti_o),
.t5_wb_bte_o(t6_wb_bte_o),
.t6_wb_cyc_o(t7_wb_cyc_o),
.t6_wb_stb_o(t7_wb_stb_o),
.t6_wb_adr_o(t7_wb_adr_o),
.t6_wb_sel_o(t7_wb_sel_o),
.t6_wb_we_o(t7_wb_we_o),
.t6_wb_dat_o(t7_wb_dat_o),
.t6_wb_dat_i(t7_wb_dat_i),
.t6_wb_ack_i(t7_wb_ack_i),
.t6_wb_err_i(t7_wb_err_i),
.t6_wb_cti_o(t7_wb_cti_o),
.t6_wb_bte_o(t7_wb_bte_o),
.t7_wb_cyc_o(t8_wb_cyc_o),
.t7_wb_stb_o(t8_wb_stb_o),
.t7_wb_adr_o(t8_wb_adr_o),
.t7_wb_sel_o(t8_wb_sel_o),
.t7_wb_we_o(t8_wb_we_o),
.t7_wb_dat_o(t8_wb_dat_o),
.t7_wb_dat_i(t8_wb_dat_i),
.t7_wb_ack_i(t8_wb_ack_i),
.t7_wb_err_i(t8_wb_err_i),
.t7_wb_cti_o(t8_wb_cti_o),
.t7_wb_bte_o(t8_wb_bte_o),
);
endmodule
//
// Multiple initiator to single target
//
module tc_mi_to_st (
wb_clk_i,
wb_rst_i,
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
i0_wb_dat_i,
i0_wb_dat_o,
i0_wb_ack_o,
i0_wb_err_o,
i0_wb_cti_i,
i0_wb_bte_i,
i1_wb_cyc_i,
i1_wb_stb_i,
i1_wb_adr_i,
i1_wb_sel_i,
i1_wb_we_i,
i1_wb_dat_i,
i1_wb_dat_o,
i1_wb_ack_o,
i1_wb_err_o,
i1_wb_cti_i,
i1_wb_bte_i,
i2_wb_cyc_i,
i2_wb_stb_i,
i2_wb_adr_i,
i2_wb_sel_i,
i2_wb_we_i,
i2_wb_dat_i,
i2_wb_dat_o,
i2_wb_ack_o,
i2_wb_err_o,
i2_wb_cti_i,
i2_wb_bte_i,
i3_wb_cyc_i,
i3_wb_stb_i,
i3_wb_adr_i,
i3_wb_sel_i,
i3_wb_we_i,
i3_wb_dat_i,
i3_wb_dat_o,
i3_wb_ack_o,
i3_wb_err_o,
i3_wb_cti_i,
i3_wb_bte_i,
i4_wb_cyc_i,
i4_wb_stb_i,
i4_wb_adr_i,
i4_wb_sel_i,
i4_wb_we_i,
i4_wb_dat_i,
i4_wb_dat_o,
i4_wb_ack_o,
i4_wb_err_o,
i4_wb_cti_i,
i4_wb_bte_i,
i5_wb_cyc_i,
i5_wb_stb_i,
i5_wb_adr_i,
i5_wb_sel_i,
i5_wb_we_i,
i5_wb_dat_i,
i5_wb_dat_o,
i5_wb_ack_o,
i5_wb_err_o,
i5_wb_cti_i,
i5_wb_bte_i,
i6_wb_cyc_i,
i6_wb_stb_i,
i6_wb_adr_i,
i6_wb_sel_i,
i6_wb_we_i,
i6_wb_dat_i,
i6_wb_dat_o,
i6_wb_ack_o,
i6_wb_err_o,
i6_wb_cti_i,
i6_wb_bte_i,
i7_wb_cyc_i,
i7_wb_stb_i,
i7_wb_adr_i,
i7_wb_sel_i,
i7_wb_we_i,
i7_wb_dat_i,
i7_wb_dat_o,
i7_wb_ack_o,
i7_wb_err_o,
i7_wb_cti_i,
i7_wb_bte_i,
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
t0_wb_dat_o,
t0_wb_dat_i,
t0_wb_ack_i,
t0_wb_err_i,
t0_wb_cti_o,
t0_wb_bte_o
);
//
// Parameters
//
parameter t0_addr_w = 2;
parameter t0_addr = 2'b00;
parameter multitarg = 1'b0;
parameter t17_addr_w = 2;
parameter t17_addr = 2'b00;
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f connecting initiator 0
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
input [`TC_DW-1:0] i0_wb_dat_i;
output [`TC_DW-1:0] i0_wb_dat_o;
output i0_wb_ack_o;
output i0_wb_err_o;
input [2:0] i0_wb_cti_i;
input [1:0] i0_wb_bte_i;
//
// WB slave i/f connecting initiator 1
//
input i1_wb_cyc_i;
input i1_wb_stb_i;
input [`TC_AW-1:0] i1_wb_adr_i;
input [`TC_BSW-1:0] i1_wb_sel_i;
input i1_wb_we_i;
input [`TC_DW-1:0] i1_wb_dat_i;
output [`TC_DW-1:0] i1_wb_dat_o;
output i1_wb_ack_o;
output i1_wb_err_o;
input [2:0] i1_wb_cti_i;
input [1:0] i1_wb_bte_i;
//
// WB slave i/f connecting initiator 2
//
input i2_wb_cyc_i;
input i2_wb_stb_i;
input [`TC_AW-1:0] i2_wb_adr_i;
input [`TC_BSW-1:0] i2_wb_sel_i;
input i2_wb_we_i;
input [`TC_DW-1:0] i2_wb_dat_i;
output [`TC_DW-1:0] i2_wb_dat_o;
output i2_wb_ack_o;
output i2_wb_err_o;
input [2:0] i2_wb_cti_i;
input [1:0] i2_wb_bte_i;
//
// WB slave i/f connecting initiator 3
//
input i3_wb_cyc_i;
input i3_wb_stb_i;
input [`TC_AW-1:0] i3_wb_adr_i;
input [`TC_BSW-1:0] i3_wb_sel_i;
input i3_wb_we_i;
input [`TC_DW-1:0] i3_wb_dat_i;
output [`TC_DW-1:0] i3_wb_dat_o;
output i3_wb_ack_o;
output i3_wb_err_o;
input [2:0] i3_wb_cti_i;
input [1:0] i3_wb_bte_i;
//
// WB slave i/f connecting initiator 4
//
input i4_wb_cyc_i;
input i4_wb_stb_i;
input [`TC_AW-1:0] i4_wb_adr_i;
input [`TC_BSW-1:0] i4_wb_sel_i;
input i4_wb_we_i;
input [`TC_DW-1:0] i4_wb_dat_i;
output [`TC_DW-1:0] i4_wb_dat_o;
output i4_wb_ack_o;
output i4_wb_err_o;
input [2:0] i4_wb_cti_i;
input [1:0] i4_wb_bte_i;
//
// WB slave i/f connecting initiator 5
//
input i5_wb_cyc_i;
input i5_wb_stb_i;
input [`TC_AW-1:0] i5_wb_adr_i;
input [`TC_BSW-1:0] i5_wb_sel_i;
input i5_wb_we_i;
input [`TC_DW-1:0] i5_wb_dat_i;
output [`TC_DW-1:0] i5_wb_dat_o;
output i5_wb_ack_o;
output i5_wb_err_o;
input [2:0] i5_wb_cti_i;
input [1:0] i5_wb_bte_i;
//
// WB slave i/f connecting initiator 6
//
input i6_wb_cyc_i;
input i6_wb_stb_i;
input [`TC_AW-1:0] i6_wb_adr_i;
input [`TC_BSW-1:0] i6_wb_sel_i;
input i6_wb_we_i;
input [`TC_DW-1:0] i6_wb_dat_i;
output [`TC_DW-1:0] i6_wb_dat_o;
output i6_wb_ack_o;
output i6_wb_err_o;
input [2:0] i6_wb_cti_i;
input [1:0] i6_wb_bte_i;
//
// WB slave i/f connecting initiator 7
//
input i7_wb_cyc_i;
input i7_wb_stb_i;
input [`TC_AW-1:0] i7_wb_adr_i;
input [`TC_BSW-1:0] i7_wb_sel_i;
input i7_wb_we_i;
input [`TC_DW-1:0] i7_wb_dat_i;
output [`TC_DW-1:0] i7_wb_dat_o;
output i7_wb_ack_o;
output i7_wb_err_o;
input [2:0] i7_wb_cti_i;
input [1:0] i7_wb_bte_i;
//
// WB master i/f connecting target
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
output [`TC_DW-1:0] t0_wb_dat_o;
input [`TC_DW-1:0] t0_wb_dat_i;
input t0_wb_ack_i;
input t0_wb_err_i;
output [2:0] t0_wb_cti_o;
output [1:0] t0_wb_bte_o;
//
// Internal wires & registers
//
wire [`TC_IIN_W-1:0] i0_in, i1_in,
i2_in, i3_in,
i4_in, i5_in,
i6_in, i7_in;
wire [`TC_TIN_W-1:0] i0_out, i1_out,
i2_out, i3_out,
i4_out, i5_out,
i6_out, i7_out;
wire [`TC_IIN_W-1:0] t0_out;
wire [`TC_TIN_W-1:0] t0_in;
wire [7:0] req_i;
wire [2:0] req_won;
reg req_cont;
reg [2:0] req_r;
//
// Group WB initiator 0 i/f inputs and outputs
//
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i};
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
//
// Group WB initiator 1 i/f inputs and outputs
//
assign i1_in = {i1_wb_cyc_i, i1_wb_stb_i, i1_wb_adr_i,
i1_wb_sel_i, i1_wb_we_i, i1_wb_dat_i, i1_wb_cti_i, i1_wb_bte_i};
assign {i1_wb_dat_o, i1_wb_ack_o, i1_wb_err_o} = i1_out;
//
// Group WB initiator 2 i/f inputs and outputs
//
assign i2_in = {i2_wb_cyc_i, i2_wb_stb_i, i2_wb_adr_i,
i2_wb_sel_i, i2_wb_we_i, i2_wb_dat_i, i2_wb_cti_i, i2_wb_bte_i};
assign {i2_wb_dat_o, i2_wb_ack_o, i2_wb_err_o} = i2_out;
//
// Group WB initiator 3 i/f inputs and outputs
//
assign i3_in = {i3_wb_cyc_i, i3_wb_stb_i, i3_wb_adr_i,
i3_wb_sel_i, i3_wb_we_i, i3_wb_dat_i, i3_wb_cti_i, i3_wb_bte_i};
assign {i3_wb_dat_o, i3_wb_ack_o, i3_wb_err_o} = i3_out;
//
// Group WB initiator 4 i/f inputs and outputs
//
assign i4_in = {i4_wb_cyc_i, i4_wb_stb_i, i4_wb_adr_i,
i4_wb_sel_i, i4_wb_we_i, i4_wb_dat_i, i4_wb_cti_i, i4_wb_bte_i};
assign {i4_wb_dat_o, i4_wb_ack_o, i4_wb_err_o} = i4_out;
//
// Group WB initiator 5 i/f inputs and outputs
//
assign i5_in = {i5_wb_cyc_i, i5_wb_stb_i, i5_wb_adr_i,
i5_wb_sel_i, i5_wb_we_i, i5_wb_dat_i, i5_wb_cti_i, i5_wb_bte_i};
assign {i5_wb_dat_o, i5_wb_ack_o, i5_wb_err_o} = i5_out;
//
// Group WB initiator 6 i/f inputs and outputs
//
assign i6_in = {i6_wb_cyc_i, i6_wb_stb_i, i6_wb_adr_i,
i6_wb_sel_i, i6_wb_we_i, i6_wb_dat_i, i6_wb_cti_i, i6_wb_bte_i};
assign {i6_wb_dat_o, i6_wb_ack_o, i6_wb_err_o} = i6_out;
//
// Group WB initiator 7 i/f inputs and outputs
//
assign i7_in = {i7_wb_cyc_i, i7_wb_stb_i, i7_wb_adr_i,
i7_wb_sel_i, i7_wb_we_i, i7_wb_dat_i, i7_wb_cti_i, i7_wb_bte_i};
assign {i7_wb_dat_o, i7_wb_ack_o, i7_wb_err_o} = i7_out;
//
// Group WB target 0 i/f inputs and outputs
//
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out;
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
//
// Assign to WB initiator i/f outputs
//
// Either inputs from the target are assigned or zeros.
//
assign i0_out = (req_won == 3'd0) ? t0_in : {`TC_TIN_W{1'b0}};
assign i1_out = (req_won == 3'd1) ? t0_in : {`TC_TIN_W{1'b0}};
assign i2_out = (req_won == 3'd2) ? t0_in : {`TC_TIN_W{1'b0}};
assign i3_out = (req_won == 3'd3) ? t0_in : {`TC_TIN_W{1'b0}};
assign i4_out = (req_won == 3'd4) ? t0_in : {`TC_TIN_W{1'b0}};
assign i5_out = (req_won == 3'd5) ? t0_in : {`TC_TIN_W{1'b0}};
assign i6_out = (req_won == 3'd6) ? t0_in : {`TC_TIN_W{1'b0}};
assign i7_out = (req_won == 3'd7) ? t0_in : {`TC_TIN_W{1'b0}};
//
// Assign to WB target i/f outputs
//
// Assign inputs from initiator to target outputs according to
// which initiator has won. If there is no request for the target,
// assign zeros.
//
assign t0_out = (req_won == 3'd0) ? i0_in :
(req_won == 3'd1) ? i1_in :
(req_won == 3'd2) ? i2_in :
(req_won == 3'd3) ? i3_in :
(req_won == 3'd4) ? i4_in :
(req_won == 3'd5) ? i5_in :
(req_won == 3'd6) ? i6_in :
(req_won == 3'd7) ? i7_in : {`TC_IIN_W{1'b0}};
//
// Determine if an initiator has address of the target.
//
assign req_i[0] = i0_wb_cyc_i &
((i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[1] = i1_wb_cyc_i &
((i1_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i1_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[2] = i2_wb_cyc_i &
((i2_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i2_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[3] = i3_wb_cyc_i &
((i3_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i3_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[4] = i4_wb_cyc_i &
((i4_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i4_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[5] = i5_wb_cyc_i &
((i5_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i5_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[6] = i6_wb_cyc_i &
((i6_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i6_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
assign req_i[7] = i7_wb_cyc_i &
((i7_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr) |
multitarg & (i7_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t17_addr));
//
// Determine who gets current access to the target.
//
// If current initiator still asserts request, do nothing
// (keep current initiator).
// Otherwise check each initiator's request, starting from initiator 0
// (highest priority).
// If there is no requests from initiators, park initiator 0.
//
assign req_won = req_cont ? req_r :
req_i[0] ? 3'd0 :
req_i[1] ? 3'd1 :
req_i[2] ? 3'd2 :
req_i[3] ? 3'd3 :
req_i[4] ? 3'd4 :
req_i[5] ? 3'd5 :
req_i[6] ? 3'd6 :
req_i[7] ? 3'd7 : 3'd0;
//
// Check if current initiator still wants access to the target and if
// it does, assert req_cont.
//
always @(req_r or req_i)
case (req_r) // synopsys parallel_case
3'd0: req_cont = req_i[0];
3'd1: req_cont = req_i[1];
3'd2: req_cont = req_i[2];
3'd3: req_cont = req_i[3];
3'd4: req_cont = req_i[4];
3'd5: req_cont = req_i[5];
3'd6: req_cont = req_i[6];
3'd7: req_cont = req_i[7];
endcase
//
// Register who has current access to the target.
//
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
req_r <= #1 3'd0;
else
req_r <= #1 req_won;
endmodule
//
// Single initiator to multiple targets
//
module tc_si_to_mt (
i0_wb_cyc_i,
i0_wb_stb_i,
i0_wb_adr_i,
i0_wb_sel_i,
i0_wb_we_i,
i0_wb_dat_i,
i0_wb_dat_o,
i0_wb_ack_o,
i0_wb_err_o,
i0_wb_cti_i,
i0_wb_bte_i,
t0_wb_cyc_o,
t0_wb_stb_o,
t0_wb_adr_o,
t0_wb_sel_o,
t0_wb_we_o,
t0_wb_dat_o,
t0_wb_dat_i,
t0_wb_ack_i,
t0_wb_err_i,
t0_wb_cti_o,
t0_wb_bte_o,
t1_wb_cyc_o,
t1_wb_stb_o,
t1_wb_adr_o,
t1_wb_sel_o,
t1_wb_we_o,
t1_wb_dat_o,
t1_wb_dat_i,
t1_wb_ack_i,
t1_wb_err_i,
t1_wb_cti_o,
t1_wb_bte_o,
t2_wb_cyc_o,
t2_wb_stb_o,
t2_wb_adr_o,
t2_wb_sel_o,
t2_wb_we_o,
t2_wb_dat_o,
t2_wb_dat_i,
t2_wb_ack_i,
t2_wb_err_i,
t2_wb_cti_o,
t2_wb_bte_o,
t3_wb_cyc_o,
t3_wb_stb_o,
t3_wb_adr_o,
t3_wb_sel_o,
t3_wb_we_o,
t3_wb_dat_o,
t3_wb_dat_i,
t3_wb_ack_i,
t3_wb_err_i,
t3_wb_cti_o,
t3_wb_bte_o,
t4_wb_cyc_o,
t4_wb_stb_o,
t4_wb_adr_o,
t4_wb_sel_o,
t4_wb_we_o,
t4_wb_dat_o,
t4_wb_dat_i,
t4_wb_ack_i,
t4_wb_err_i,
t4_wb_cti_o,
t4_wb_bte_o,
t5_wb_cyc_o,
t5_wb_stb_o,
t5_wb_adr_o,
t5_wb_sel_o,
t5_wb_we_o,
t5_wb_dat_o,
t5_wb_dat_i,
t5_wb_ack_i,
t5_wb_err_i,
t5_wb_cti_o,
t5_wb_bte_o,
t6_wb_cyc_o,
t6_wb_stb_o,
t6_wb_adr_o,
t6_wb_sel_o,
t6_wb_we_o,
t6_wb_dat_o,
t6_wb_dat_i,
t6_wb_ack_i,
t6_wb_err_i,
t6_wb_cti_o,
t6_wb_bte_o,
t7_wb_cyc_o,
t7_wb_stb_o,
t7_wb_adr_o,
t7_wb_sel_o,
t7_wb_we_o,
t7_wb_dat_o,
t7_wb_dat_i,
t7_wb_ack_i,
t7_wb_err_i,
t7_wb_cti_o,
t7_wb_bte_o
);
//
// Parameters
//
parameter t0_addr_w = 3;
parameter t0_addr = 3'd0;
parameter t17_addr_w = 3;
parameter t1_addr = 3'd1;
parameter t2_addr = 3'd2;
parameter t3_addr = 3'd3;
parameter t4_addr = 3'd4;
parameter t5_addr = 3'd5;
parameter t6_addr = 3'd6;
parameter t7_addr = 3'd7;
//
// I/O Ports
//
//
// WB slave i/f connecting initiator 0
//
input i0_wb_cyc_i;
input i0_wb_stb_i;
input [`TC_AW-1:0] i0_wb_adr_i;
input [`TC_BSW-1:0] i0_wb_sel_i;
input i0_wb_we_i;
input [`TC_DW-1:0] i0_wb_dat_i;
output [`TC_DW-1:0] i0_wb_dat_o;
output i0_wb_ack_o;
output i0_wb_err_o;
input [2:0] i0_wb_cti_i;
input [1:0] i0_wb_bte_i;
//
// WB master i/f connecting target 0
//
output t0_wb_cyc_o;
output t0_wb_stb_o;
output [`TC_AW-1:0] t0_wb_adr_o;
output [`TC_BSW-1:0] t0_wb_sel_o;
output t0_wb_we_o;
output [`TC_DW-1:0] t0_wb_dat_o;
input [`TC_DW-1:0] t0_wb_dat_i;
input t0_wb_ack_i;
input t0_wb_err_i;
output [2:0] t0_wb_cti_o;
output [1:0] t0_wb_bte_o;
//
// WB master i/f connecting target 1
//
output t1_wb_cyc_o;
output t1_wb_stb_o;
output [`TC_AW-1:0] t1_wb_adr_o;
output [`TC_BSW-1:0] t1_wb_sel_o;
output t1_wb_we_o;
output [`TC_DW-1:0] t1_wb_dat_o;
input [`TC_DW-1:0] t1_wb_dat_i;
input t1_wb_ack_i;
input t1_wb_err_i;
output [2:0] t1_wb_cti_o;
output [1:0] t1_wb_bte_o;
//
// WB master i/f connecting target 2
//
output t2_wb_cyc_o;
output t2_wb_stb_o;
output [`TC_AW-1:0] t2_wb_adr_o;
output [`TC_BSW-1:0] t2_wb_sel_o;
output t2_wb_we_o;
output [`TC_DW-1:0] t2_wb_dat_o;
input [`TC_DW-1:0] t2_wb_dat_i;
input t2_wb_ack_i;
input t2_wb_err_i;
output [2:0] t2_wb_cti_o;
output [1:0] t2_wb_bte_o;
//
// WB master i/f connecting target 3
//
output t3_wb_cyc_o;
output t3_wb_stb_o;
output [`TC_AW-1:0] t3_wb_adr_o;
output [`TC_BSW-1:0] t3_wb_sel_o;
output t3_wb_we_o;
output [`TC_DW-1:0] t3_wb_dat_o;
input [`TC_DW-1:0] t3_wb_dat_i;
input t3_wb_ack_i;
input t3_wb_err_i;
output [2:0] t3_wb_cti_o;
output [1:0] t3_wb_bte_o;
//
// WB master i/f connecting target 4
//
output t4_wb_cyc_o;
output t4_wb_stb_o;
output [`TC_AW-1:0] t4_wb_adr_o;
output [`TC_BSW-1:0] t4_wb_sel_o;
output t4_wb_we_o;
output [`TC_DW-1:0] t4_wb_dat_o;
input [`TC_DW-1:0] t4_wb_dat_i;
input t4_wb_ack_i;
input t4_wb_err_i;
output [2:0] t4_wb_cti_o;
output [1:0] t4_wb_bte_o;
//
// WB master i/f connecting target 5
//
output t5_wb_cyc_o;
output t5_wb_stb_o;
output [`TC_AW-1:0] t5_wb_adr_o;
output [`TC_BSW-1:0] t5_wb_sel_o;
output t5_wb_we_o;
output [`TC_DW-1:0] t5_wb_dat_o;
input [`TC_DW-1:0] t5_wb_dat_i;
input t5_wb_ack_i;
input t5_wb_err_i;
output [2:0] t5_wb_cti_o;
output [1:0] t5_wb_bte_o;
//
// WB master i/f connecting target 6
//
output t6_wb_cyc_o;
output t6_wb_stb_o;
output [`TC_AW-1:0] t6_wb_adr_o;
output [`TC_BSW-1:0] t6_wb_sel_o;
output t6_wb_we_o;
output [`TC_DW-1:0] t6_wb_dat_o;
input [`TC_DW-1:0] t6_wb_dat_i;
input t6_wb_ack_i;
input t6_wb_err_i;
output [2:0] t6_wb_cti_o;
output [1:0] t6_wb_bte_o;
//
// WB master i/f connecting target 7
//
output t7_wb_cyc_o;
output t7_wb_stb_o;
output [`TC_AW-1:0] t7_wb_adr_o;
output [`TC_BSW-1:0] t7_wb_sel_o;
output t7_wb_we_o;
output [`TC_DW-1:0] t7_wb_dat_o;
input [`TC_DW-1:0] t7_wb_dat_i;
input t7_wb_ack_i;
input t7_wb_err_i;
output [2:0] t7_wb_cti_o;
output [1:0] t7_wb_bte_o;
//
// Internal wires & registers
//
wire [`TC_IIN_W-1:0] i0_in;
wire [`TC_TIN_W-1:0] i0_out;
wire [`TC_IIN_W-1:0] t0_out, t1_out,
t2_out, t3_out,
t4_out, t5_out,
t6_out, t7_out;
wire [`TC_TIN_W-1:0] t0_in, t1_in,
t2_in, t3_in,
t4_in, t5_in,
t6_in, t7_in;
wire [7:0] req_t;
//
// Group WB initiator 0 i/f inputs and outputs
//
assign i0_in = {i0_wb_cyc_i, i0_wb_stb_i, i0_wb_adr_i,
i0_wb_sel_i, i0_wb_we_i, i0_wb_dat_i, i0_wb_cti_i, i0_wb_bte_i};
assign {i0_wb_dat_o, i0_wb_ack_o, i0_wb_err_o} = i0_out;
//
// Group WB target 0 i/f inputs and outputs
//
assign {t0_wb_cyc_o, t0_wb_stb_o, t0_wb_adr_o,
t0_wb_sel_o, t0_wb_we_o, t0_wb_dat_o, t0_wb_cti_o, t0_wb_bte_o} = t0_out;
assign t0_in = {t0_wb_dat_i, t0_wb_ack_i, t0_wb_err_i};
//
// Group WB target 1 i/f inputs and outputs
//
assign {t1_wb_cyc_o, t1_wb_stb_o, t1_wb_adr_o,
t1_wb_sel_o, t1_wb_we_o, t1_wb_dat_o, t1_wb_cti_o, t1_wb_bte_o} = t1_out;
assign t1_in = {t1_wb_dat_i, t1_wb_ack_i, t1_wb_err_i};
//
// Group WB target 2 i/f inputs and outputs
//
assign {t2_wb_cyc_o, t2_wb_stb_o, t2_wb_adr_o,
t2_wb_sel_o, t2_wb_we_o, t2_wb_dat_o, t2_wb_cti_o, t2_wb_bte_o} = t2_out;
assign t2_in = {t2_wb_dat_i, t2_wb_ack_i, t2_wb_err_i};
//
// Group WB target 3 i/f inputs and outputs
//
assign {t3_wb_cyc_o, t3_wb_stb_o, t3_wb_adr_o,
t3_wb_sel_o, t3_wb_we_o, t3_wb_dat_o, t3_wb_cti_o, t3_wb_bte_o} = t3_out;
assign t3_in = {t3_wb_dat_i, t3_wb_ack_i, t3_wb_err_i};
//
// Group WB target 4 i/f inputs and outputs
//
assign {t4_wb_cyc_o, t4_wb_stb_o, t4_wb_adr_o,
t4_wb_sel_o, t4_wb_we_o, t4_wb_dat_o, t4_wb_cti_o, t4_wb_bte_o} = t4_out;
assign t4_in = {t4_wb_dat_i, t4_wb_ack_i, t4_wb_err_i};
//
// Group WB target 5 i/f inputs and outputs
//
assign {t5_wb_cyc_o, t5_wb_stb_o, t5_wb_adr_o,
t5_wb_sel_o, t5_wb_we_o, t5_wb_dat_o, t5_wb_cti_o, t5_wb_bte_o} = t5_out;
assign t5_in = {t5_wb_dat_i, t5_wb_ack_i, t5_wb_err_i};
//
// Group WB target 6 i/f inputs and outputs
//
assign {t6_wb_cyc_o, t6_wb_stb_o, t6_wb_adr_o,
t6_wb_sel_o, t6_wb_we_o, t6_wb_dat_o, t6_wb_cti_o, t6_wb_bte_o} = t6_out;
assign t6_in = {t6_wb_dat_i, t6_wb_ack_i, t6_wb_err_i};
//
// Group WB target 7 i/f inputs and outputs
//
assign {t7_wb_cyc_o, t7_wb_stb_o, t7_wb_adr_o,
t7_wb_sel_o, t7_wb_we_o, t7_wb_dat_o, t7_wb_cti_o, t7_wb_bte_o} = t7_out;
assign t7_in = {t7_wb_dat_i, t7_wb_ack_i, t7_wb_err_i};
//
// Assign to WB target i/f outputs
//
// Either inputs from the initiator are assigned or zeros.
//
assign t0_out = req_t[0] ? i0_in : {`TC_IIN_W{1'b0}};
assign t1_out = req_t[1] ? i0_in : {`TC_IIN_W{1'b0}};
assign t2_out = req_t[2] ? i0_in : {`TC_IIN_W{1'b0}};
assign t3_out = req_t[3] ? i0_in : {`TC_IIN_W{1'b0}};
assign t4_out = req_t[4] ? i0_in : {`TC_IIN_W{1'b0}};
assign t5_out = req_t[5] ? i0_in : {`TC_IIN_W{1'b0}};
assign t6_out = req_t[6] ? i0_in : {`TC_IIN_W{1'b0}};
assign t7_out = req_t[7] ? i0_in : {`TC_IIN_W{1'b0}};
//
// Assign to WB initiator i/f outputs
//
// Assign inputs from target to initiator outputs according to
// which target is accessed. If there is no request for a target,
// assign zeros.
//
assign i0_out = req_t[0] ? t0_in :
req_t[1] ? t1_in :
req_t[2] ? t2_in :
req_t[3] ? t3_in :
req_t[4] ? t4_in :
req_t[5] ? t5_in :
req_t[6] ? t6_in :
req_t[7] ? t7_in : {`TC_TIN_W{1'b0}};
//
// Determine which target is being accessed.
//
assign req_t[0] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t0_addr_w] == t0_addr);
assign req_t[1] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t1_addr);
assign req_t[2] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t2_addr);
assign req_t[3] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t3_addr);
assign req_t[4] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t4_addr);
assign req_t[5] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t5_addr);
assign req_t[6] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t6_addr);
assign req_t[7] = i0_wb_cyc_i & (i0_wb_adr_i[`TC_AW-1:`TC_AW-t17_addr_w] == t7_addr);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYGATE4SD1_PP_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd1 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD1_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_4_V
`define SKY130_FD_SC_HS__AND3_4_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_4_V
|
module MUX8_1_Icontrol(Sel,S0,S1,S2,S3,S4,S5,S6,S7,out);
input [2:0] Sel;
input S0,S1,S2,S3,S4,S5,S6,S7;
output out;
assign out = (Sel[2])? (Sel[1]?(Sel[0]?S7:S6) : (Sel[0]?S5:S4)) : (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module MUX8_1_SL(Sel,Write_Byte_En,S0,S1,S2,S3,S4,S5,S6,S7,out);
input [3:0] Sel;
input [3:0] Write_Byte_En;
input [3:0] S0,S1,S2,S3,S4,S5,S6,S7;
output [3:0] out;
assign out = (Sel[3])?Write_Byte_En:((Sel[2])? (Sel[1]?(Sel[0]?S7:S6) : (Sel[0]?S5:S4)) : (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0)));
//assign out = (Sel[2])? (Sel[1]?(Sel[0]?S7:S6) : (Sel[0]?S5:S4)) : (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module MUX4_1_SL(Sel,S0,S1,S2,S3,out);
input [1:0] Sel;
input [3:0] S0,S1,S2,S3;
output [3:0]out;
assign out = (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module Condition_Check(
input [2:0] Condition,PC_Write,
input [1:0] addr,
input MemWBSrc,
input OverflowEn,Branch,Overflow,
input [3:0] Mem_Byte_Write,
input [3:0] Rd_Write_Byte_en,
input Less,Zero,
output BranchValid,
output [3:0] RdWriteEn,
output [3:0] MemWriteEn
);
wire[1:0] Right;
wire Load,Store;
wire [3:0] LoadOut,StoreOut;
//110-right-01 010-left-00 other-10
assign Right = (PC_Write == 3'b110 ?2'b01:(PC_Write == 3'b010)?2'b00:2'b10);
//assign StoreRight = (PC_Write == 3'b110 ?1'b1:1'b0);
assign Load = (MemWBSrc == 1'b1)?1'b1:1'b0;
assign Store = (Mem_Byte_Write == 4'b1111);
MUX8_1_SL sl1({Right,addr[1:0]},Rd_Write_Byte_en,4'b1111,4'b1110,4'b1100,4'b1000,4'b0001,4'b0011,4'b0111,4'b1111,LoadOut);
MUX8_1_SL sl2({Right,addr[1:0]},Mem_Byte_Write,4'b1111,4'b0111,4'b0011,4'b0001,4'b1000,4'b1100,4'b1110,4'b1111,StoreOut);
wire condition_out;
MUX8_1_Icontrol MUX_Con(Condition,1'b0,Zero,!Zero,!Less,!(Less^Zero),Less^Zero,Less,1'b1,condition_out);
assign BranchValid = condition_out & Branch;
assign RdWriteEn = (Load === 1'b1)?LoadOut:((OverflowEn == 0)?(Rd_Write_Byte_en):((Overflow == 1'b0)?(4'b1111):(4'b0000)));
assign MemWriteEn = (Store === 1'b1) ? StoreOut:4'b0000;
endmodule
|
//PS2 mouse controller.
//This module decodes the standard 3 byte packet of an PS/2 compatible 2 or 3 button mouse, or alternatively, if an intellimouse is detected, a 4-byte packet is supported with scrollwheel support.
//The module also automatically handles power-up initailzation of the mouse.
module userio_ps2mouse
(
input clk, // 28MHz clock
input clk7_en,
input reset, //reset
inout ps2mdat, //mouse PS/2 data
inout ps2mclk, //mouse PS/2 clk
input [5:0] mou_emu,
input sof,
output reg [7:0]zcount, // mouse Z counter
output reg [7:0]ycount, //mouse Y counter
output reg [7:0]xcount, //mouse X counter
output reg _mleft, //left mouse button output
output reg _mthird, //third(middle) mouse button output
output reg _mright, //right mouse button output
input test_load, //load test value to mouse counter
input [15:0] test_data //mouse counter test value
);
reg mclkout;
wire mdatout;
reg [ 2-1:0] mdatr;
reg [ 3-1:0] mclkr;
reg [11-1:0] mreceive;
reg [12-1:0] msend;
reg [16-1:0] mtimer;
reg [ 3-1:0] mstate;
reg [ 3-1:0] mnext;
wire mclkneg;
reg mrreset;
wire mrready;
reg msreset;
wire msready;
reg mtreset;
wire mtready;
wire mthalf;
reg [ 3-1:0] mpacket;
reg intellimouse=0;
wire mcmd_done;
reg [ 4-1:0] mcmd_cnt=1;
reg mcmd_inc=0;
reg [12-1:0] mcmd;
// bidirectional open collector IO buffers
assign ps2mclk = (mclkout) ? 1'bz : 1'b0;
assign ps2mdat = (mdatout) ? 1'bz : 1'b0;
// input synchronization of external signals
always @ (posedge clk) begin
if (clk7_en) begin
mdatr[1:0] <= #1 {mdatr[0], ps2mdat};
mclkr[2:0] <= #1 {mclkr[1:0], ps2mclk};
end
end
// detect mouse clock negative edge
assign mclkneg = mclkr[2] & !mclkr[1];
// PS2 mouse input shifter
always @ (posedge clk) begin
if (clk7_en) begin
if (mrreset)
mreceive[10:0] <= #1 11'b11111111111;
else if (mclkneg)
mreceive[10:0] <= #1 {mdatr[1],mreceive[10:1]};
end
end
assign mrready = !mreceive[0];
// PS2 mouse data counter
always @ (posedge clk) begin
if (clk7_en) begin
if (reset)
mcmd_cnt <= #1 4'd0;
else if (mcmd_inc && !mcmd_done)
mcmd_cnt <= #1 mcmd_cnt + 4'd1;
end
end
assign mcmd_done = (mcmd_cnt == 4'd9);
// mouse init commands
always @ (*) begin
case (mcmd_cnt)
// GUARD STOP PARITY DATA START
4'h0 : mcmd = {1'b1, 1'b1, 1'b1, 8'hff, 1'b0}; // reset
4'h1 : mcmd = {1'b1, 1'b1, 1'b1, 8'hf3, 1'b0}; // set sample rate
4'h2 : mcmd = {1'b1, 1'b1, 1'b0, 8'hc8, 1'b0}; // sample rate = 200
4'h3 : mcmd = {1'b1, 1'b1, 1'b1, 8'hf3, 1'b0}; // set sample rate
4'h4 : mcmd = {1'b1, 1'b1, 1'b0, 8'h64, 1'b0}; // sample rate = 100
4'h5 : mcmd = {1'b1, 1'b1, 1'b1, 8'hf3, 1'b0}; // set sample rate
4'h6 : mcmd = {1'b1, 1'b1, 1'b1, 8'h50, 1'b0}; // sample rate = 80
4'h7 : mcmd = {1'b1, 1'b1, 1'b0, 8'hf2, 1'b0}; // read device type
4'h8 : mcmd = {1'b1, 1'b1, 1'b0, 8'hf4, 1'b0}; // enable data reporting
default : mcmd = {1'b1, 1'b1, 1'b0, 8'hf4, 1'b0}; // enable data reporting
endcase
end
// PS2 mouse send shifter
always @ (posedge clk) begin
if (clk7_en) begin
if (msreset)
msend[11:0] <= #1 mcmd;
else if (!msready && mclkneg)
msend[11:0] <= #1 {1'b0,msend[11:1]};
end
end
assign msready = (msend[11:0]==12'b000000000001);
assign mdatout = msend[0];
// PS2 mouse timer
always @(posedge clk) begin
if (clk7_en) begin
if (mtreset)
mtimer[15:0] <= #1 16'h0000;
else
mtimer[15:0] <= #1 mtimer[15:0] + 16'd1;
end
end
assign mtready = (mtimer[15:0]==16'hffff);
assign mthalf = mtimer[11];
// PS2 mouse packet decoding and handling
always @ (posedge clk) begin
if (clk7_en) begin
if (reset) begin
{_mthird,_mright,_mleft} <= #1 3'b111;
xcount[7:0] <= #1 8'h00;
ycount[7:0] <= #1 8'h00;
zcount[7:0] <= #1 8'h00;
end else begin
if (test_load) // test value preload
{ycount[7:2],xcount[7:2]} <= #1 {test_data[15:10],test_data[7:2]};
else if (mpacket == 3'd1) // buttons
{_mthird,_mright,_mleft} <= #1 ~mreceive[3:1];
else if (mpacket == 3'd2) // delta X movement
xcount[7:0] <= #1 xcount[7:0] + mreceive[8:1];
else if (mpacket == 3'd3) // delta Y movement
ycount[7:0] <= #1 ycount[7:0] - mreceive[8:1];
else if (mpacket == 3'd4) // delta Z movement
zcount[7:0] <= #1 zcount[7:0] + {{4{mreceive[4]}}, mreceive[4:1]};
else if (sof) begin
if (mou_emu[3]) ycount <= #1 ycount - 1'b1;
else if (mou_emu[2]) ycount <= #1 ycount + 1'b1;
if (mou_emu[1]) xcount <= #1 xcount - 1'b1;
else if (mou_emu[0]) xcount <= #1 xcount + 1'b1;
end
end
end
end
// PS2 intellimouse flag
always @ (posedge clk) begin
if (clk7_en) begin
if (reset)
intellimouse <= #1 1'b0;
else if ((mpacket==3'd5) && (mreceive[2:1] == 2'b11))
intellimouse <= #1 1'b1;
end
end
// PS2 mouse state machine
always @ (posedge clk) begin
if (clk7_en) begin
if (reset || mtready)
mstate <= #1 0;
else
mstate <= #1 mnext;
end
end
always @ (*) begin
mclkout = 1'b1;
mtreset = 1'b1;
mrreset = 1'b0;
msreset = 1'b0;
mpacket = 3'd0;
mcmd_inc = 1'b0;
case(mstate)
0 : begin
// initialize mouse phase 0, start timer
mtreset=1;
mnext=1;
end
1 : begin
//initialize mouse phase 1, hold clk low and reset send logic
mclkout=0;
mtreset=0;
msreset=1;
if (mthalf) begin
// clk was low long enough, go to next state
mnext=2;
end else begin
mnext=1;
end
end
2 : begin
// initialize mouse phase 2, send command/data to mouse
mrreset=1;
mtreset=0;
if (msready) begin
// command sent
mcmd_inc = 1;
case (mcmd_cnt)
0 : mnext = 4;
1 : mnext = 6;
2 : mnext = 6;
3 : mnext = 6;
4 : mnext = 6;
5 : mnext = 6;
6 : mnext = 6;
7 : mnext = 5;
8 : mnext = 6;
default : mnext = 6;
endcase
end else begin
mnext=2;
end
end
3 : begin
// get first packet byte
mtreset=1;
if (mrready) begin
// we got our first packet byte
mpacket=1;
mrreset=1;
mnext=4;
end else begin
// we are still waiting
mnext=3;
end
end
4 : begin
// get second packet byte
mtreset=1;
if (mrready) begin
// we got our second packet byte
mpacket=2;
mrreset=1;
mnext=5;
end else begin
// we are still waiting
mnext=4;
end
end
5 : begin
// get third packet byte
mtreset=1;
if (mrready) begin
// we got our third packet byte
mpacket=3;
mrreset=1;
mnext = (intellimouse || !mcmd_done) ? 6 : 3;
end else begin
// we are still waiting
mnext=5;
end
end
6 : begin
// get fourth packet byte
mtreset=1;
if (mrready) begin
// we got our fourth packet byte
mpacket = (mcmd_cnt == 8) ? 5 : 4;
mrreset=1;
mnext = !mcmd_done ? 0 : 3;
end else begin
// we are still waiting
mnext=6;
end
end
default : begin
//we should never come here
mclkout=1'bx;
mrreset=1'bx;
mtreset=1'bx;
msreset=1'bx;
mpacket=3'bxxx;
mnext=0;
end
endcase
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Boundary Scan Logic Control Circuit for VIRTEX7
// /___/ /\ Filename : BSCANE2.v
// \ \ / \ Timestamp : Mon Feb 8 22:02:00 PST 2010
// \___\/\___\
//
// Revision:
// 02/08/10 - Initial version.
// 06/10/11 - CR 613789.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// 04/07/15 - Added negedge to SEL (CR 857726).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BSCANE2 (
CAPTURE,
DRCK,
RESET,
RUNTEST,
SEL,
SHIFT,
TCK,
TDI,
TMS,
UPDATE,
TDO
);
parameter DISABLE_JTAG = "FALSE";
parameter integer JTAG_CHAIN = 1;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output CAPTURE;
output DRCK;
output RESET;
output RUNTEST;
output SEL;
output SHIFT;
output TCK;
output TDI;
output TMS;
output UPDATE;
input TDO;
reg SEL_reg;
reg SEL_zd;
pulldown (DRCK);
pulldown (RESET);
pulldown (SEL);
pulldown (SHIFT);
pulldown (TDI);
pulldown (UPDATE);
//--####################################################################
//--##### Initialization ###
//--####################################################################
initial begin
//-------- JTAG_CHAIN
if ((JTAG_CHAIN != 1) && (JTAG_CHAIN != 2) && (JTAG_CHAIN != 3) && (JTAG_CHAIN != 4)) begin
$display("Attribute Syntax Error : The attribute JTAG_CHAIN on BSCANE2 instance %m is set to %d. Legal values for this attribute are 1, 2, 3 or 4.", JTAG_CHAIN);
#1 $finish;
end
end
//--####################################################################
//--##### Jtag_select ###
//--####################################################################
always@(glbl.JTAG_SEL1_GLBL or glbl.JTAG_SEL2_GLBL or glbl.JTAG_SEL3_GLBL or glbl.JTAG_SEL4_GLBL) begin
if (JTAG_CHAIN == 1) SEL_zd = glbl.JTAG_SEL1_GLBL;
else if (JTAG_CHAIN == 2) SEL_zd = glbl.JTAG_SEL2_GLBL;
else if (JTAG_CHAIN == 3) SEL_zd = glbl.JTAG_SEL3_GLBL;
else if (JTAG_CHAIN == 4) SEL_zd = glbl.JTAG_SEL4_GLBL;
end
//--####################################################################
//--##### USER_TDO ###
//--####################################################################
always@(TDO) begin
if (JTAG_CHAIN == 1) glbl.JTAG_USER_TDO1_GLBL = TDO;
else if (JTAG_CHAIN == 2) glbl.JTAG_USER_TDO2_GLBL = TDO;
else if (JTAG_CHAIN == 3) glbl.JTAG_USER_TDO3_GLBL = TDO;
else if (JTAG_CHAIN == 4) glbl.JTAG_USER_TDO4_GLBL = TDO;
end
//--####################################################################
//--##### USER_SEL ###
//--####################################################################
always @(negedge glbl.JTAG_TCK_GLBL or posedge SEL_zd) begin
SEL_reg = SEL_zd;
end
assign SEL = SEL_reg;
//--####################################################################
//--##### Output ###
//--####################################################################
assign CAPTURE = glbl.JTAG_CAPTURE_GLBL;
assign #5 DRCK = ((SEL_zd & !glbl.JTAG_SHIFT_GLBL & !glbl.JTAG_CAPTURE_GLBL)
||
(SEL_zd & glbl.JTAG_SHIFT_GLBL & glbl.JTAG_TCK_GLBL)
||
(SEL_zd & glbl.JTAG_CAPTURE_GLBL & glbl.JTAG_TCK_GLBL));
assign RESET = glbl.JTAG_RESET_GLBL;
assign RUNTEST = glbl.JTAG_RUNTEST_GLBL;
assign SHIFT = glbl.JTAG_SHIFT_GLBL;
assign TDI = glbl.JTAG_TDI_GLBL;
assign TCK = glbl.JTAG_TCK_GLBL;
assign TMS = glbl.JTAG_TMS_GLBL;
assign UPDATE = glbl.JTAG_UPDATE_GLBL;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
(** * StlcProp: Properties of STLC *)
Require Import SfLib.
Require Import Maps.
Require Import Types.
Require Import Stlc.
Require Import Smallstep.
Module STLCProp.
Import STLC.
(** In this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ###################################################################### *)
(** * Canonical Forms *)
(** As we saw for the simple calculus in the [Types] chapter, the
first step in establishing basic properties of reduction and types
is to identify the possible _canonical forms_ (i.e., well-typed
closed values) belonging to each type. For [Bool], these are the boolean
values [ttrue] and [tfalse]. For arrow types, the canonical forms
are lambda-abstractions. *)
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
(* ###################################################################### *)
(** * Progress *)
(** As before, the _progress_ theorem tells us that closed, well-typed
terms are not stuck: either a well-typed term is a value, or it
can take a reduction step. The proof is a relatively
straightforward extension of the progress proof we saw in the
[Types] chapter. We'll give the proof in English first, then the
formal version. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
(** _Proof_: By induction on the derivation of [|- t \in T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we can see by inspecting the rule that [t]
is a value.
- If the last rule of the derivation is [T_App], then [t] has the
form [t1 t2] for som e[t1] and [t2], where we know that [t1] and
[t2] are also well typed in the empty context; in particular,
there exists a type [T2] such that [|- t1 \in T2 -> T] and [|-
t2 \in T2]. By the induction hypothesis, either [t1] is a value
or it can take a reduction step.
- If [t1] is a value, then consider [t2], which by the other
induction hypothesis must also either be a value or take a step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation is [T_If], then [t = if t1
then t2 else t3], where [t1] has type [Bool]. By the IH, [t1]
either is a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps
to [t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]). *)
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
induction Ht; subst Gamma...
- (* T_Var *)
(* contradictory: variables cannot be typed in an
empty context *)
inversion H.
- (* T_App *)
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct IHHt2...
* (* t2 is also a value *)
assert (exists x0 t0, t1 = tabs x0 T11 t0).
eapply canonical_forms_fun; eauto.
destruct H1 as [x0 [t0 Heq]]. subst.
exists ([x0:=t2]t0)...
* (* t2 steps *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_If *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct (canonical_forms_bool t1); subst; eauto.
+ (* t1 also steps *)
inversion H as [t1' Hstp]. exists (tif t1' t2 t3)...
Qed.
(** **** Exercise: 3 stars, optional (progress_from_term_ind) *)
(** Show that progress can also be proved by induction on terms
instead of induction on typing derivations. *)
Theorem progress' : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof.
intros t.
induction t; intros T Ht; auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Preservation *)
(** The other half of the type soundness property is the preservation
of types during reduction. For this, we need to develop some
technical machinery for reasoning about variables and
substitution. Working from top to bottom (from the high-level
property we are actually interested in to the lowest-level
technical lemmas that are needed by various cases of the more
interesting proofs), the story goes like this:
- The _preservation theorem_ is proved by induction on a typing
derivation, pretty much as we did in the [Types] chapter. The
one case that is significantly different is the one for the
[ST_AppAbs] rule, whose definition uses the substitution
operation. To see that this step preserves typing, we need to
know that the substitution itself does. So we prove a...
- _substitution lemma_, stating that substituting a (closed)
term [s] for a variable [x] in a term [t] preserves the type
of [t]. The proof goes by induction on the form of [t] and
requires looking at all the different cases in the definition
of substitition. This time, the tricky cases are the ones for
variables and for function abstractions. In both cases, we
discover that we need to take a term [s] that has been shown
to be well-typed in some context [Gamma] and consider the same
term [s] in a slightly different context [Gamma']. For this
we prove a...
- _context invariance_ lemma, showing that typing is preserved
under "inessential changes" to the context [Gamma] -- in
particular, changes that do not affect any of the free
variables of the term. And finally, for this, we need a
careful definition of...
- the _free variables_ of a term -- i.e., those variables
mentioned in a term and not in the scope of an enclosing
function abstraction binding a variable of the same name.
To make Coq happy, we need to formalize the story in the opposite
order... *)
(* ###################################################################### *)
(** ** Free Occurrences *)
(** A variable [x] _appears free in_ a term _t_ if [t] contains some
occurrence of [x] that is not under an abstraction labeled [x].
For example:
- [y] appears free, but [x] does not, in [\x:T->U. x y]
- both [x] and [y] appear free in [(\x:T->U. x y) x]
- no variables appear free in [\x:T->U. \y:T. x y]
Formally: *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Hint Constructors appears_free_in.
(** A term in which no variables appear free is said to be _closed_. *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(** **** Exercise: 1 star (afi) *)
(** If the definition of [appears_free_in] is not crystal clear to
you, it is a good idea to take a piece of paper and write out the
rules in informal inference-rule notation. (Although it is a
rather low-level, technical definition, understanding it is
crucial to understanding substitution and its properties, which
are really the crux of the lambda-calculus.) *)
(** [] *)
(* ###################################################################### *)
(** ** Substitution *)
(** To prove that substitution preserves typing, we first need a
technical lemma connecting free variables and typing contexts: If
a variable [x] appears free in a term [t], and if we know [t] is
well typed in context [Gamma], then it must be the case that
[Gamma] assigns a type to [x]. *)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
(** _Proof_: We show, by induction on the proof that [x] appears
free in [t], that, for all contexts [Gamma], if [t] is well
typed under [Gamma], then [Gamma] assigns some type to [x].
- If the last rule used was [afi_var], then [t = x], and from
the assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used was [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma],
we can see from the typing rules that [t1] must also be, and
the IH then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed
under [Gamma] as well, and the IH gives us exactly the
conclusion we want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T11.t12], and [x] appears free in [t12]; we also know that
[x] is different from [y]. The difference from the previous
cases is that whereas [t] is well typed under [Gamma], its
body [t12] is well typed under [(Gamma, y:T11)], so the IH
allows us to conclude that [x] is assigned some type by the
extended context [(Gamma, y:T11)]. To conclude that [Gamma]
assigns a type to [x], we appeal to lemma [update_neq], noting
that [x] and [y] are different variables. *)
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
induction H;
intros; try solve [inversion H0; eauto].
- (* afi_abs *)
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite update_neq in H7; assumption.
Qed.
(** Next, we'll need the fact that any term [t] which is well typed in
the empty context is closed (it has no free variables). *)
(** **** Exercise: 2 stars, optional (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
empty |- t \in T ->
closed t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, when we have a proof [Gamma |- t : T], we will need to
replace [Gamma] by a different context [Gamma']. When is it safe
to do this? Intuitively, it must at least be the case that
[Gamma'] assigns the same types as [Gamma] to all the variables
that appear free in [t]. In fact, this is the only condition that
is needed. *)
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
(** _Proof_: By induction on the derivation of
[Gamma |- t \in T].
- If the last rule in the derivation was [T_Var], then [t = x]
and [Gamma x = T]. By assumption, [Gamma' x = T] as well, and
hence [Gamma' |- t \in T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T11. t12], with [T
= T11 -> T12] and [Gamma, y:T11 |- t12 \in T12]. The
induction hypothesis is that, for any context [Gamma''], if
[Gamma, y:T11] and [Gamma''] assign the same types to all the
free variables in [t12], then [t12] has type [T12] under
[Gamma'']. Let [Gamma'] be a context which agrees with
[Gamma] on the free variables in [t]; we must show [Gamma' |-
\y:T11. t12 \in T11 -> T12].
By [T_Abs], it suffices to show that [Gamma', y:T11 |- t12 \in
T12]. By the IH (setting [Gamma'' = Gamma', y:T11]), it
suffices to show that [Gamma, y:T11] and [Gamma', y:T11] agree
on all the variables that appear free in [t12].
Any variable occurring free in [t12] must be either [y] or
some other variable. [Gamma, y:T11] and [Gamma', y:T11]
clearly agree on [y]. Otherwise, note that any variable other
than [y] that occurs free in [t12] also occurs free in [t =
\y:T11. t12], and by assumption [Gamma] and [Gamma'] agree on
all such variables; hence so do [Gamma, y:T11] and [Gamma',
y:T11].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma |-
t1 \in T2 -> T] and [Gamma |- t2 \in T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1]
has type [T2 -> T] under [Gamma']; there is a similar IH for
[t2]. We must show that [t1 t2] also has type [T] under
[Gamma'], given the assumption that [Gamma'] agrees with
[Gamma] on all the free variables in [t1 t2]. By [T_App], it
suffices to show that [t1] and [t2] each have the same type
under [Gamma'] as under [Gamma]. But all free variables in
[t1] are also free in [t1 t2], and similarly for [t2]; hence
the desired result follows from the induction hypotheses. *)
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
- (* T_Var *)
apply T_Var. rewrite <- H0...
- (* T_Abs *)
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [update Gamma x T11] *)
unfold update. unfold t_update. destruct (beq_id x0 x1) eqn: Hx0x1...
rewrite beq_id_false_iff in Hx0x1. auto.
- (* T_App *)
apply T_App with T11...
Qed.
(** Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types.
Formally, the so-called _Substitution Lemma_ says this: Suppose we
have a term [t] with a free variable [x], and suppose we've been
able to assign a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we should be
able to substitute [v] for each of the occurrences of [x] in [t]
and obtain a new term that still has type [T]. *)
(** _Lemma_: If [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T]. *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
update Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
(** One technical subtlety in the statement of the lemma is that
we assign [v] the type [U] in the _empty_ context -- in other
words, we assume [v] is closed. This assumption considerably
simplifies the [T_Abs] case of the proof (compared to assuming
[Gamma |- v \in U], which would be the other reasonable assumption
at this point) because the context invariance lemma then tells us
that [v] has type [U] in any context at all -- we don't have to
worry about free variables in [v] clashing with the variable being
introduced into the context by [T_Abs].
The substitution lemma can be viewed as a kind of "commutation"
property. Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [x:=v] t ] -- the result is the same either
way.
_Proof_: We show, by induction on [t], that for all [T] and
[Gamma], if [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma
|- [x:=v]t \in T].
- If [t] is a variable there are two cases to consider,
depending on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [Gamma, x:U |- x \in
T] we conclude that [U = T]. We must show that [[x:=v]x =
v] has type [T] under [Gamma], given the assumption that
[v] has type [U = T] under the empty context. This
follows from context invariance: if a closed term has type
[T] in the empty context, it has that type in any context.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [Gamma,
x:U] as under [Gamma].
- If [t] is an abstraction [\y:T11. t12], then the IH tells us,
for all [Gamma'] and [T'], that if [Gamma',x:U |- t12 \in T']
and [|- v \in U], then [Gamma' |- [x:=v]t12 \in T'].
The substitution in the conclusion behaves differently
depending on whether [x] and [y] are the same variable.
First, suppose [x = y]. Then, by the definition of
substitution, [[x:=v]t = t], so we just need to show [Gamma |-
t \in T]. But we know [Gamma,x:U |- t : T], and, since [y]
does not appear free in [\y:T11. t12], the context invariance
lemma yields [Gamma |- t \in T].
Second, suppose [x <> y]. We know [Gamma,x:U,y:T11 |- t12 \in
T12] by inversion of the typing relation, from which
[Gamma,y:T11,x:U |- t12 \in T12] follows by the context
invariance lemma, so the IH applies, giving us [Gamma,y:T11 |-
[x:=v]t12 \in T12]. By [T_Abs], [Gamma |- \y:T11. [x:=v]t12
\in T11->T12], and by the definition of substitution (noting
that [x <> y]), [Gamma |- \y:T11. [x:=v]t12 \in T11->T12] as
required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case.
One more technical note: This proof is a rare case where an
induction on terms, rather than typing derivations, yields a
simpler argument. The reason for this is that the assumption
[update Gamma x U |- t \in T] is not completely generic, in the
sense that one of the "slots" in the typing relation -- namely the
context -- is not just a variable, and this means that Coq's
native induction tactic does not give us the induction hypothesis
that we want. It is possible to work around this, but the needed
generalization is a little tricky. The term [t], on the other
hand, _is_ completely generic. *)
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
- (* tvar *)
rename i into y. destruct (beq_idP x y) as [Hxy|Hxy].
+ (* x=y *)
subst.
rewrite update_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
apply T_Var. rewrite update_neq in H2...
- (* tabs *)
rename i into y. apply T_Abs.
destruct (beq_idP x y) as [Hxy | Hxy].
+ (* x=y *)
subst.
eapply context_invariance...
intros x Hafi. unfold update, t_update.
destruct (beq_id y x) eqn: Hyx...
+ (* x<>y *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z) as [Hyz | Hyz]; subst; trivial.
rewrite <- beq_id_false_iff in Hxy.
rewrite Hxy...
Qed.
(* ###################################################################### *)
(** ** Main Theorem *)
(** We now have the tools we need to prove preservation: if a closed
term [t] has type [T] and takes a step to [t'], then [t']
is also a closed term with type [T]. In other words, the small-step
reduction relation preserves types. *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
(** _Proof_: By induction on the derivation of [|- t \in T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as the final rules in the derivation, since in each of
these cases [t] cannot take a step.
- If the last rule in the derivation was [T_App], then [t = t1
t2]. There are three cases to consider, one for each rule that
could have been used to show that [t1 t2] takes a step to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then by the IH [t1'] has the same type as [t1], and
hence [t1' t2] has the same type as [t1 t2].
- The [ST_App2] case is similar.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T11.t12] and [t1 t2] steps to [[x:=t2]t12]; the
desired result now follows from the fact that substitution
preserves types.
- If the last rule in the derivation was [T_If], then [t = if t1
then t2 else t3], and there are again three cases depending on
how [t] steps.
- If [t] steps to [t2] or [t3], the result is immediate, since
[t2] and [t3] have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired conclusion
follows directly from the induction hypothesis. *)
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
induction HT;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
- (* T_App *)
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
+ (* ST_AppAbs *)
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
(** **** Exercise: 2 stars, recommended (subject_expansion_stlc) *)
(** An exercise in the [Types] chapter asked about the subject
expansion property for the simple language of arithmetic and
boolean expressions. Does this property hold for STLC? That is,
is it always the case that, if [t ==> t'] and [has_type t' T],
then [empty |- t \in T]? If so, prove it. If not, give a
counter-example not involving conditionals.
(* FILL IN HERE *)
[]
*)
(* ###################################################################### *)
(** * Type Soundness *)
(** **** Exercise: 2 stars, optional (type_soundness) *)
(** Put progress and preservation together and show that a well-typed
term can _never_ reach a stuck state. *)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Uniqueness of Types *)
(** **** Exercise: 3 stars (types_unique) *)
(** Another nice property of the STLC is that types are unique: a
given term (in a given context) has at most one type. *)
(** Formalize this statement and prove it. *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 1 star (progress_preservation_statement) *)
(** Without peeking at their statements above, write down the progress
and preservation theorems for the simply typed lambda-calculus. *)
(** [] *)
(** **** Exercise: 2 stars (stlc_variation1) *)
(** Suppose we add a new term [zap] with the following reduction rule
--------- (ST_Zap)
t ==> zap
and the following typing rule:
---------------- (T_Zap)
Gamma |- zap : T
Which of the following properties of the STLC remain true in
the presence of these rules? For each property, write either
"remains true" or "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (stlc_variation2) *)
(** Suppose instead that we add a new term [foo] with the following
reduction rules:
----------------- (ST_Foo1)
(\x:A. x) ==> foo
------------ (ST_Foo2)
foo ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars (stlc_variation3) *)
(** Suppose instead that we remove the rule [ST_App1] from the [step]
relation. Which of the following properties of the STLC remain
true in the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation4) *)
(** Suppose instead that we add the following new rule to the
reduction relation:
---------------------------------- (ST_FunnyIfTrue)
(if true then t1 else t2) ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation5) *)
(** Suppose instead that we add the following new rule to the typing
relation:
Gamma |- t1 \in Bool->Bool->Bool
Gamma |- t2 \in Bool
------------------------------ (T_FunnyApp)
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation6) *)
(** Suppose instead that we add the following new rule to the typing
relation:
Gamma |- t1 \in Bool
Gamma |- t2 \in Bool
--------------------- (T_FunnyApp')
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
(** **** Exercise: 2 stars, optional (stlc_variation7) *)
(** Suppose we add the following new rule to the typing relation
of the STLC:
------------------- (T_FunnyAbs)
|- \x:Bool.t \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
End STLCProp.
(* ###################################################################### *)
(* ###################################################################### *)
(** ** Exercise: STLC with Arithmetic *)
(** To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
Module STLCArith.
(** To types, we add a base type of natural numbers (and remove
booleans, for brevity). *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty.
(** To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing. *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm.
(** **** Exercise: 4 stars (stlc_arith) *)
(** Finish formalizing the definition and properties of the STLC extended
with arithmetic. Specifically:
- Copy the whole development of STLC that we went through above (from
the definition of values through the Type Soundness theorem), and
paste it into the file at this point.
- Extend the definitions of the [subst] operation and the [step]
relation to include appropriate clauses for the arithmetic operators.
- Extend the proofs of all the properties (up to [soundness]) of
the original STLC to deal with the new syntactic forms. Make
sure Coq accepts the whole file. *)
(* FILL IN HERE *)
(** [] *)
End STLCArith.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlygate4sd3 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <[email protected]>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
/*
* Helper module for synchronizing bit signals from one clock domain to another.
* It uses the standard approach of 2 FF in series.
* Note, that while the module allows to synchronize multiple bits at once it is
* only able to synchronize multi-bit signals where at max one bit changes per
* clock cycle (e.g. a gray counter).
*/
module sync_bits
(
input [NUM_OF_BITS-1:0] in,
input out_resetn,
input out_clk,
output [NUM_OF_BITS-1:0] out
);
// Number of bits to synchronize
parameter NUM_OF_BITS = 1;
// Whether input and output clocks are asynchronous, if 0 the synchronizer will
// be bypassed and the output signal equals the input signal.
parameter ASYNC_CLK = 1;
reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
always @(posedge out_clk)
begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'b0;
cdc_sync_stage2 <= 'b0;
end else begin
cdc_sync_stage1 <= in;
cdc_sync_stage2 <= cdc_sync_stage1;
end
end
assign out = ASYNC_CLK ? cdc_sync_stage2 : in;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: sa1_mult.v
// /___/ /\ Timestamp: Fri Oct 02 09:06:37 2020
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_sa1/ipcore_dir/tmp/_cg/sa1_mult.ngc D:/prj/sd2snes/verilog/sd2snes_sa1/ipcore_dir/tmp/_cg/sa1_mult.v
// Device : 3s400pq208-4
// Input file : D:/prj/sd2snes/verilog/sd2snes_sa1/ipcore_dir/tmp/_cg/sa1_mult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_sa1/ipcore_dir/tmp/_cg/sa1_mult.v
// # of Modules : 1
// Design Name : sa1_mult
// Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module sa1_mult (
clk, p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [31 : 0] p;
input [15 : 0] a;
input [15 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \blk00000001/sig00000031 ;
wire \blk00000001/sig00000030 ;
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
wire \blk00000001/sig0000002d ;
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig00000028 ;
wire \blk00000001/sig00000027 ;
wire \blk00000001/sig00000026 ;
wire \blk00000001/sig00000025 ;
wire \blk00000001/sig00000024 ;
wire \blk00000001/sig00000023 ;
wire \blk00000001/sig00000022 ;
wire \NLW_blk00000001/blk00000022_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000022_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000022_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000022_P<31>_UNCONNECTED ;
MULT18X18 \blk00000001/blk00000022 (
.A({a[15], a[15], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({b[15], b[15], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\blk00000001/sig0000003a , \NLW_blk00000001/blk00000022_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000022_P<33>_UNCONNECTED ,
\NLW_blk00000001/blk00000022_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000022_P<31>_UNCONNECTED , \blk00000001/sig00000039 , \blk00000001/sig00000037
, \blk00000001/sig00000036 , \blk00000001/sig00000035 , \blk00000001/sig00000034 , \blk00000001/sig00000033 , \blk00000001/sig00000032 ,
\blk00000001/sig00000031 , \blk00000001/sig00000030 , \blk00000001/sig0000002f , \blk00000001/sig0000002e , \blk00000001/sig0000002c ,
\blk00000001/sig0000002b , \blk00000001/sig0000002a , \blk00000001/sig00000029 , \blk00000001/sig00000028 , \blk00000001/sig00000027 ,
\blk00000001/sig00000026 , \blk00000001/sig00000025 , \blk00000001/sig00000024 , \blk00000001/sig00000023 , \blk00000001/sig00000041 ,
\blk00000001/sig00000040 , \blk00000001/sig0000003f , \blk00000001/sig0000003e , \blk00000001/sig0000003d , \blk00000001/sig0000003c ,
\blk00000001/sig0000003b , \blk00000001/sig00000038 , \blk00000001/sig0000002d , \blk00000001/sig00000022 })
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(clk),
.D(\blk00000001/sig0000003a ),
.Q(p[31])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000020 (
.C(clk),
.D(\blk00000001/sig00000039 ),
.Q(p[30])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001f (
.C(clk),
.D(\blk00000001/sig00000037 ),
.Q(p[29])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(clk),
.D(\blk00000001/sig00000036 ),
.Q(p[28])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(clk),
.D(\blk00000001/sig00000035 ),
.Q(p[27])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001c (
.C(clk),
.D(\blk00000001/sig00000034 ),
.Q(p[26])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001b (
.C(clk),
.D(\blk00000001/sig00000033 ),
.Q(p[25])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(clk),
.D(\blk00000001/sig00000032 ),
.Q(p[24])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(clk),
.D(\blk00000001/sig00000031 ),
.Q(p[23])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000018 (
.C(clk),
.D(\blk00000001/sig00000030 ),
.Q(p[22])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000017 (
.C(clk),
.D(\blk00000001/sig0000002f ),
.Q(p[21])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000016 (
.C(clk),
.D(\blk00000001/sig0000002e ),
.Q(p[20])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000015 (
.C(clk),
.D(\blk00000001/sig0000002c ),
.Q(p[19])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000014 (
.C(clk),
.D(\blk00000001/sig0000002b ),
.Q(p[18])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(clk),
.D(\blk00000001/sig0000002a ),
.Q(p[17])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(clk),
.D(\blk00000001/sig00000029 ),
.Q(p[16])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(clk),
.D(\blk00000001/sig00000028 ),
.Q(p[15])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000010 (
.C(clk),
.D(\blk00000001/sig00000027 ),
.Q(p[14])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000f (
.C(clk),
.D(\blk00000001/sig00000026 ),
.Q(p[13])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000e (
.C(clk),
.D(\blk00000001/sig00000025 ),
.Q(p[12])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000d (
.C(clk),
.D(\blk00000001/sig00000024 ),
.Q(p[11])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000c (
.C(clk),
.D(\blk00000001/sig00000023 ),
.Q(p[10])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000b (
.C(clk),
.D(\blk00000001/sig00000041 ),
.Q(p[9])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(clk),
.D(\blk00000001/sig00000040 ),
.Q(p[8])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(clk),
.D(\blk00000001/sig0000003f ),
.Q(p[7])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(clk),
.D(\blk00000001/sig0000003e ),
.Q(p[6])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(clk),
.D(\blk00000001/sig0000003d ),
.Q(p[5])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(clk),
.D(\blk00000001/sig0000003c ),
.Q(p[4])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(clk),
.D(\blk00000001/sig0000003b ),
.Q(p[3])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(clk),
.D(\blk00000001/sig00000038 ),
.Q(p[2])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000003 (
.C(clk),
.D(\blk00000001/sig0000002d ),
.Q(p[1])
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000002 (
.C(clk),
.D(\blk00000001/sig00000022 ),
.Q(p[0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_1_V
`define SKY130_FD_SC_HDLL__XNOR2_1_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xnor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_1_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//////////////////////////////////////////////////////////////////
// Float to fixed converts floating point numbers to 16.16 sign
//
//
module flt_fx_23p9
(
input [31:0] fp_in, // Floating point in IEEE fmt
output reg [31:0] int_out // Fixed point integer out
);
//
// 23.9, UV.
//
wire [7:0] bias_exp; /* Real exponent -127 - 128 */
wire [7:0] bias_exp2; /* Real exponent 2's comp */
wire [39:0] fixed_out2; /* 2's complement of fixed out */
wire [47:0] bias_mant; /* mantissa expanded to 16.16 fmt */
reg [47:0] int_fixed_out;
reg [31:0] fixed_out;
assign bias_mant = {25'h0001, fp_in[22:0]};
assign bias_exp = fp_in[30:23] - 'd127;
assign bias_exp2 = ~bias_exp + 1;
// infinity or NaN - Don't do anything special, will overflow
always @* begin
// zero condition
if (fp_in[30:0] == 31'b0) int_fixed_out = 0;
// negative exponent
else if (bias_exp[7]) int_fixed_out = bias_mant >> bias_exp2;
// positive exponent
else int_fixed_out = bias_mant << bias_exp;
fixed_out = int_fixed_out[45:14];
int_out = (fp_in[31]) ? ~fixed_out + 1 : fixed_out;
end
endmodule
|
module I2C_AV_Config ( // Host Side
iCLK,
iRST_N,
o_I2C_END,
// I2C Side
I2C_SCLK,
I2C_SDAT );
// Host Side
input iCLK;
input iRST_N;
output o_I2C_END;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [23:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [15:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
reg o_I2C_END;
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 50;
// Audio Data Index
parameter SET_LIN_L = 0;
parameter SET_LIN_R = 1;
parameter SET_HEAD_L = 2;
parameter SET_HEAD_R = 3;
parameter A_PATH_CTRL = 4;
parameter D_PATH_CTRL = 5;
parameter POWER_ON = 6;
parameter SET_FORMAT = 7;
parameter SAMPLE_CTRL = 8;
parameter SET_ACTIVE = 9;
// Video Data Index
parameter SET_VIDEO = 10;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(iRST_N) );
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
o_I2C_END <= 0 ;
case(mSetup_ST)
0: begin
if(LUT_INDEX<SET_VIDEO)
mI2C_DATA <= {8'h34,LUT_DATA};
else
mI2C_DATA <= {8'h40,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
else begin
o_I2C_END <= 1 ;end
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
// Audio Config Data
SET_LIN_L : LUT_DATA <= 16'h001A;
SET_LIN_R : LUT_DATA <= 16'h021A;
SET_HEAD_L : LUT_DATA <= 16'h047B;
SET_HEAD_R : LUT_DATA <= 16'h067B;
A_PATH_CTRL : LUT_DATA <= 16'h08F8;
D_PATH_CTRL : LUT_DATA <= 16'h0A06;
POWER_ON : LUT_DATA <= 16'h0C00;
SET_FORMAT : LUT_DATA <= 16'h0E01;
SAMPLE_CTRL : LUT_DATA <= 16'h1002;
SET_ACTIVE : LUT_DATA <= 16'h1201;
// Video Config Data
SET_VIDEO+0 : LUT_DATA <= 16'h1500;
SET_VIDEO+1 : LUT_DATA <= 16'h1741;
SET_VIDEO+2 : LUT_DATA <= 16'h3a16;
SET_VIDEO+3 : LUT_DATA <= 16'h5004;
SET_VIDEO+4 : LUT_DATA <= 16'hc305;
SET_VIDEO+5 : LUT_DATA <= 16'hc480;
SET_VIDEO+6 : LUT_DATA <= 16'h0e80;
SET_VIDEO+7 : LUT_DATA <= 16'h5020;
SET_VIDEO+8 : LUT_DATA <= 16'h5218;
SET_VIDEO+9 : LUT_DATA <= 16'h58ed;
SET_VIDEO+10: LUT_DATA <= 16'h77c5;
SET_VIDEO+11: LUT_DATA <= 16'h7c93;
SET_VIDEO+12: LUT_DATA <= 16'h7d00;
SET_VIDEO+13: LUT_DATA <= 16'hd048;
SET_VIDEO+14: LUT_DATA <= 16'hd5a0;
SET_VIDEO+15: LUT_DATA <= 16'hd7ea;
SET_VIDEO+16: LUT_DATA <= 16'he43e;
SET_VIDEO+17: LUT_DATA <= 16'hea0f;
SET_VIDEO+18: LUT_DATA <= 16'h3112;
SET_VIDEO+19: LUT_DATA <= 16'h3281;
SET_VIDEO+20: LUT_DATA <= 16'h3384;
SET_VIDEO+21: LUT_DATA <= 16'h37A0;
SET_VIDEO+22: LUT_DATA <= 16'he580;
SET_VIDEO+23: LUT_DATA <= 16'he603;
SET_VIDEO+24: LUT_DATA <= 16'he785;
SET_VIDEO+25: LUT_DATA <= 16'h5000;
SET_VIDEO+26: LUT_DATA <= 16'h5100;
SET_VIDEO+27: LUT_DATA <= 16'h0050;
SET_VIDEO+28: LUT_DATA <= 16'h1000;
SET_VIDEO+29: LUT_DATA <= 16'h0402;
SET_VIDEO+30: LUT_DATA <= 16'h0b00;
SET_VIDEO+31: LUT_DATA <= 16'h0a20;
SET_VIDEO+32: LUT_DATA <= 16'h1100;
SET_VIDEO+33: LUT_DATA <= 16'h2b00;
SET_VIDEO+34: LUT_DATA <= 16'h2c8c;
SET_VIDEO+35: LUT_DATA <= 16'h2df2;
SET_VIDEO+36: LUT_DATA <= 16'h2eee;
SET_VIDEO+37: LUT_DATA <= 16'h2ff4;
SET_VIDEO+38: LUT_DATA <= 16'h30d2;
SET_VIDEO+39: LUT_DATA <= 16'h0e05;
default: LUT_DATA <= 16'hxxxx;
endcase
end
////////////////////////////////////////////////////////////////////
endmodule
|
`timescale 1ns / 1ps
//-----------------------------------------------------------------------------
// Title : KPU top file for digilent arty board simulation
// Project : KPU
//-----------------------------------------------------------------------------
// File : kpu.v
// Author : acorallo <[email protected]>
// Created : 22.1.2017
//-----------------------------------------------------------------------------
// Description :
// Top module for kpu implementation on digilent arty development simulation
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2016 2017 by Andrea Corallo.
//------------------------------------------------------------------------------
// Modification history :
// 22.1.2017 : created
// 4.4.2017 : use for both vivado and iverilog
//-----------------------------------------------------------------------------
`include "kpu_conf.v"
`include "kcache_defs.v"
`define EXEC_INSTS(i) \
#(((i) + 5) * 10);
module top_kpu_sim();
reg clk_sim;
reg rst;
reg stop;
wire uart_rx;
wire uart_tx;
wire [7:0] ja;
reg [`IO_INT_N-1:0] io_int_line = `IO_INT_N'h0;
// sram lines
wire [`SRAM_ADDR_W-1:0] sram_addr;
wire [`SRAM_DATA_W-1:0] sram_data;
wire sram_cs;
wire sram_we;
wire sram_oe;
wire sram_hb;
wire sram_lb;
// uart test lines
wire cts;
reg test_transmit = 0;
reg [7:0] test_tx_byte = 8'h0;
wire test_received;
wire [7:0] test_rx_byte;
wire test_is_receiving;
wire test_is_transmitting;
wire test_rx_error;
wire wb_int_send;
wire tms;
wire tck;
wire trst;
wire tdi;
wire tdo;
wire tdo_oe;
initial begin
rst = 1;
stop = 0;
clk_sim = 0;
#10rst = 0;
#310; // First 32 cycles are internal reset
// We wait to see two time 0 on sram ext addr line
// This means kcache has finished his initial job
while (sram_addr != 0)
#1;
#100;
while (sram_addr != 0)
#1;
`ifdef DUMP_FILE
$dumpfile(`DUMP_FILE);
$dumpvars;
`endif
`ifdef TEST_PLAN
`include `TEST_PLAN
$finish;
`endif
end // initial begin
always #5 clk_sim <= !clk_sim;
kpu_soc kpu_soc_i(
`ifdef KPU_SIM_TRACE
.stop_debug(stop),
.io_int_line_debug(io_int_line),
`endif
.CLK100MHZ(clk_sim),
.rst_ext(rst),
.ja(ja),
.uart_tx(uart_tx),
.uart_rx(uart_rx),
// SRAM
.sram_addr_o(sram_addr),
.sram_data_io(sram_data),
.sram_cs_o(sram_cs),
.sram_we_o(sram_we),
.sram_oe_o(sram_oe),
.sram_hb_o(sram_hb),
.sram_lb_o(sram_lb),
// JTAG
.tms_pad_i(tms),
.tck_pad_i(tck),
.trstn_pad_i(trst),
.tdi_pad_i(tdi),
.tdo_pad_o(tdo),
.tdo_padoe_o(tdo_oe)
);
sram sram_i(
.addr_i(sram_addr),
.data_io(sram_data),
.CS_i(sram_cs),
.WE_i(sram_we),
.OE_i(sram_oe),
.HB_i(sram_hb),
.LB_i(sram_lb)
);
v_jtag v_jtag_i(
.clk_i(clk_sim),
.tms_o(tms),
.tck_o(tck),
.trst_o(trst),
.tdi_o(tdi),
.tdo_i(tdo),
.tdo_oe_i(tdo_oe)
);
uart_v3 u_test_i (.clk(clk_sim),
.rst(rst),
.rx(uart_tx),
.tx(uart_rx),
.transmit(test_transmit),
.tx_byte(test_tx_byte),
.received(test_received),
.rx_byte(test_rx_byte),
.is_receiving(test_is_receiving),
.is_transmitting(test_is_transmitting),
.rx_error(test_rx_error),
.set_clock_div(1'b0),
.user_clock_div(`N'b0));
endmodule
|
module Cache
#(parameter DATA_WIDTH = 32, parameter ADDR_WIDTH = 32,parameter Cache_Size = 16,parameter Cache_Size_log = 4,
parameter Block_Size = 2,parameter Block_Size_log = 1)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input [3:0] we,
input Clk,
output [(DATA_WIDTH-1):0] data_out,
output reg hit,
output [(DATA_WIDTH*Block_Size-1):0] ReadRam,
output writeback,
output[7:0] readramn,
output reg[7:0] writeramn
);
// Declare the RAM variable ram just use 9:2 10bit
reg [DATA_WIDTH-1:0] ram[2**(ADDR_WIDTH - 22) - 1:0];
reg up1,up2,up;
initial
begin
ram[64] = 32'hf0f0f0f0;
end
//assume Memory block size is 32bit rather than 8bit ,addr low 2 bit is 00
//31 7 6 3 2 2 1 0
//+--------+-------+--------+------+
//| tag | block | offset | 00 |
//+--------+-------+--------+------+
// 25 4 1 2
reg [(DATA_WIDTH*Block_Size-1):0] cache[Cache_Size-1:0];
reg [Cache_Size-1:0] valid;
reg [Cache_Size-1:0] dirty;
reg [(ADDR_WIDTH-Block_Size_log-Cache_Size_log-1-2):0] tag[Cache_Size-1:0];
//valid initial to 0
integer i;
initial begin
for (i=0;i<Cache_Size;i=i+1) begin
valid[i] = 0;
tag[i] = 0;
end
up1 = 0;
up2 = 0;
end
wire[(Cache_Size_log-1):0] block; //3:0 4bit
assign block = addr[31:2+Block_Size_log]%Cache_Size;
wire[(Block_Size_log-1):0] offset;
assign offset = addr[(Block_Size_log-1+2):2];
//wire[(DATA_WIDTH*Block_Size-1):0] ReadRam;
assign readramn = {addr[9:2+Block_Size_log],1'b0};
assign ReadRam = {ram[readramn+1'b1],ram[readramn]};
/*//------------------------------------------------------------------------------------
assign hit = valid[block] == 1 && tag[block] == addr[(ADDR_WIDTH-1):Block_Size_log+2+Cache_Size_log];
wire writeback;
assign writeback = (hit == 0 && valid[block] === 1 && dirty[block] ===1);
//------------------------------------------------------------------------------------*/
//assign writeramn = (tag[block][2:0]<<5)+(block<<1)+1'b0;
assign writeback = (hit == 0 && valid[block] === 1 && dirty[block] ===1);
always @(posedge Clk) begin
up1 = !up1;
hit = ((valid[block] == 1) && (tag[block] == addr[(ADDR_WIDTH-1):Block_Size_log+2+Cache_Size_log]));
writeramn = (tag[block][2:0]<<5)+(block<<1)+1'b0;
if(writeback) begin
//ram[writeramn] = 32'h87654321;//cache[block][31:0];
ram[writeramn] <= cache[block][31:0];
ram[writeramn+1] <= cache[block][63:32];
end
end
always @(negedge Clk) begin up2=!up2;
case(offset)
1'b0:case(hit)
1'b1:case(we)
4'b0001: cache[block][7:0] <= data[7:0];
4'b0010: cache[block][15:8] <= data[15:8];
4'b0011: cache[block][15:0] <= data[15:0];
4'b0100: cache[block][23:16] <= data[23:16];
4'b0101: begin cache[block][23:16] <= data[23:16]; cache[block][7:0] <= data[7:0];end
4'b0110: cache[block][23:8] <= data[23:8];
4'b0111: cache[block][23:0] <= data[23:0];
4'b1000: cache[block][31:24] <= data[31:24];
4'b1001: begin cache[block][31:24] <= data[31:24]; cache[block][7:0] <= data[7:0];end
4'b1010: begin cache[block][31:24] <= data[31:24]; cache[block][15:8] <= data[15:8];end
4'b1011: begin cache[block][31:24] <= data[31:24]; cache[block][15:0] <= data[15:0];end
4'b1100: cache[block][31:16] <= data[31:16];
4'b1101: begin cache[block][31:16] <= data[31:16]; cache[block][7:0] <= data[7:0];end
4'b1110: cache[block][31:8] <= data[31:8];
4'b1111: cache[block][31:0] <= data;
default:;
endcase
1'b0:case(we)
4'b0000: cache[block] <= ReadRam;
4'b0001: cache[block] <= {ReadRam[63:8],data[7:0]};
4'b0010: cache[block] <= {ReadRam[63:16],data[15:8],ReadRam[7:0]};
4'b0011: cache[block] <= {ReadRam[63:16],data[15:0]};
4'b0100: cache[block] <= {ReadRam[63:24],data[23:16],ReadRam[15:0]};
4'b0101: cache[block] <= {ReadRam[63:24],data[23:16],ReadRam[15:8],data[7:0]};
4'b0110: cache[block] <= {ReadRam[63:24],data[23:8],ReadRam[7:0]};
4'b0111: cache[block] <= {ReadRam[63:24],data[23:0]};
4'b1000: cache[block] <= {ReadRam[63:32],data[31:24],ReadRam[23:0]};
4'b1001: cache[block] <= {ReadRam[63:32],data[31:24],ReadRam[23:8],data[7:0]};
4'b1010: cache[block] <= {ReadRam[63:32],data[31:24],ReadRam[23:16],data[15:8]};
4'b1011: cache[block] <= {ReadRam[63:32],data[31:24],ReadRam[23:16],data[15:0]};
4'b1100: cache[block] <= {ReadRam[63:32],data[31:16],ReadRam[15:0]};
4'b1101: cache[block] <= {ReadRam[63:32],data[31:16],ReadRam[15:8],data[7:0]};
4'b1110: cache[block] <= {ReadRam[63:32],data[31:8],ReadRam[7:0]};
4'b1111: cache[block] <= {ReadRam[63:32],data};
default:;
endcase
endcase
1'b1:case(hit)
1'b1:case(we)
4'b0001: cache[block][32+7:32] <= data[7:0];
4'b0010: cache[block][32+15:32+8] <= data[15:8];
4'b0011: cache[block][32+15:32] <= data[15:0];
4'b0100: cache[block][32+23:32+16] <= data[23:16];
4'b0101: begin cache[block][32+23:32+16] <= data[23:16]; cache[block][32+7:32] <= data[7:0];end
4'b0110: cache[block][32+23:32+8] <= data[23:8];
4'b0111: cache[block][32+23:32] <= data[23:0];
4'b1000: cache[block][32+31:32+24] <= data[31:24];
4'b1001: begin cache[block][32+31:32+24] <= data[31:24]; cache[block][32+7:32] <= data[7:0];end
4'b1010: begin cache[block][32+31:32+24] <= data[31:24]; cache[block][32+15:32+8] <= data[15:8];end
4'b1011: begin cache[block][32+31:32+24] <= data[31:24]; cache[block][32+15:32] <= data[15:0];end
4'b1100: cache[block][32+31:32+16] <= data[31:16];
4'b1101: begin cache[block][32+31:32+16] <= data[31:16]; cache[block][32+7:32] <= data[7:0];end
4'b1110: cache[block][32+31:32+8] <= data[31:8];
4'b1111: cache[block][63:32] <= data;
default:;
endcase
1'b0:case(we)
4'b0000: cache[block] <= ReadRam;
4'b0001: cache[block] <= {ReadRam[63:40],data[7:0],ReadRam[31:0]};
4'b0010: cache[block] <= {ReadRam[63:48],data[15:8],ReadRam[39:0]};
4'b0011: cache[block] <= {ReadRam[63:48],data[15:0],ReadRam[31:0]};
4'b0100: cache[block] <= {ReadRam[63:56],data[23:16],ReadRam[47:0]};
4'b0101: cache[block] <= {ReadRam[63:56],data[23:16],ReadRam[48:40],data[7:0],ReadRam[31:0]};
4'b0110: cache[block] <= {ReadRam[63:56],data[23:8],ReadRam[39:32],ReadRam[31:0]};
4'b0111: cache[block] <= {ReadRam[63:56],data[23:0],ReadRam[31:0]};
4'b1000: cache[block] <= {data[31:24],ReadRam[55:0]};
4'b1001: cache[block] <= {data[31:24],ReadRam[55:40],data[7:0],ReadRam[31:0]};
4'b1010: cache[block] <= {data[31:24],ReadRam[55:48],data[15:8],ReadRam[39:0]};
4'b1011: cache[block] <= {data[31:24],ReadRam[55:48],data[15:0],ReadRam[31:0]};
4'b1100: cache[block] <= {data[31:16],ReadRam[47:0]};
4'b1101: cache[block] <= {data[31:16],ReadRam[47:40],data[7:0],ReadRam[31:0]};
4'b1110: cache[block] <= {data[31:8],ReadRam[39:0]};
4'b1111: cache[block] <= {data,ReadRam[31:0]};
default:;
endcase
endcase
endcase
valid[block] <= 1'b1;
tag[block] <= addr[(ADDR_WIDTH-1):Block_Size_log+2+Cache_Size_log];
dirty[block] <= (we == 4'b0000)?0:1;
end
always@(up1 or up2) begin
up = up1 ^ up2;
end
assign data_out = (up == 0)?(offset == 0)?cache[block][31:0]:cache[block][63:32]:(offset == 0)?ReadRam[31:0]:ReadRam[63:32];
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module hshrink(
input [3:0] SHRINK, // Shrink value
input CK, L,
output OUTA, OUTB
);
wire [3:0] nSHRINK;
wire [3:0] U193_REG;
wire [3:0] T196_REG;
wire [3:0] U243_REG;
wire [3:0] U226_REG;
wire [3:0] U193_P;
wire [3:0] T196_P;
wire [3:0] U243_P;
wire [3:0] U226_P;
assign nSHRINK[3:0] = ~SHRINK[3:0];
// Lookup
assign U193_P[0] = ~&{nSHRINK[3:2]};
assign U193_P[1] = ~&{nSHRINK[3:1]};
assign U193_P[2] = ~&{nSHRINK[3], ~&{SHRINK[2:1]}};
assign U193_P[3] = 1'b1;
assign T196_P[0] = ~|{&{SHRINK[2], ~|{SHRINK[1:0], SHRINK[3]}}, ~|{SHRINK[3:2]}};
assign T196_P[1] = ~&{nSHRINK[3:0]};
assign T196_P[2] = ~&{~&{SHRINK[1:0]}, ~|{SHRINK[3:2]}};
assign T196_P[3] = ~&{nSHRINK[3], ~&{SHRINK[2:0]}};
assign U243_P[0] = ~|{nSHRINK[3], ~|{SHRINK[2:1]}};
assign U243_P[1] = ~|{nSHRINK[3:2]};
assign U243_P[2] = ~|{nSHRINK[3:1]};
assign U243_P[3] = SHRINK[3];
assign U226_P[0] = ~&{~&{SHRINK[1:0], nSHRINK[2], SHRINK[3]}, ~&{SHRINK[3:2]}};
assign U226_P[1] = &{SHRINK[3:0]};
assign U226_P[2] = ~|{nSHRINK[3], ~|{SHRINK[2:0]}};
assign U226_P[3] = ~|{~&{SHRINK[3:2]}, ~|{SHRINK[1:0]}};
// Shift registers
FS2 U193(CK, U193_P, 1'b1, ~L, U193_REG);
BD3 T193A(U193_REG[3], T193A_OUT);
FS2 T196(CK, T196_P, T193A_OUT, ~L, T196_REG);
FS2 U243(CK, U243_P, 1'b1, ~L, U243_REG);
BD3 U258A(U243_REG[3], U258A_OUT);
FS2 U226(CK, U226_P, U258A_OUT, ~L, U226_REG);
assign OUTA = T196_REG[3];
assign OUTB = U226_REG[3];
/*always@(*)
begin
case (SHRINK)
4'h0: BITMAP <= 16'b0000000010000000;
4'h1: BITMAP <= 16'b0000100010000000;
4'h2: BITMAP <= 16'b0000100010001000;
4'h3: BITMAP <= 16'b0010100010001000;
4'h4: BITMAP <= 16'b0010100010001010;
4'h5: BITMAP <= 16'b0010101010001010;
4'h6: BITMAP <= 16'b0010101010101010;
4'h7: BITMAP <= 16'b1010101010101010;
4'h8: BITMAP <= 16'b1010101011101010;
4'h9: BITMAP <= 16'b1011101011101010;
4'hA: BITMAP <= 16'b1011101011101011;
4'hB: BITMAP <= 16'b1011101111101011;
4'hC: BITMAP <= 16'b1011101111101111;
4'hD: BITMAP <= 16'b1111101111101111;
4'hE: BITMAP <= 16'b1111101111111111;
4'hF: BITMAP <= 16'b1111111111111111;
endcase
end*/
endmodule
|
// file: Clock35MHz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____35.000______0.000______50.0______771.429____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Clock35MHz,clk_wiz_v3_6,{component_name=Clock35MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module Clock35MHz
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (20),
.CLKFX_MULTIPLY (7),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
/*
00: Set master reset
01: Shift register
10: Storage register
11: Output Enable
*/
module shift(
input clk ,
input rst ,
input vld ,
input [1:0] cmd ,
input cmd_oen ,
input [7:0] din ,
output done ,
output sft_shcp ,
output sft_ds ,
output sft_stcp ,
output sft_mr_n ,
output sft_oe_n
);
reg sft_mr_n ;
reg sft_oe_n ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_mr_n <= 1'b1 ;
else if( vld && cmd == 2'b00 )
sft_mr_n <= 1'b0 ;
else
sft_mr_n <= 1'b1 ;
end
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_oe_n <= 1'b1 ;
else if( vld && cmd == 2'b11 )
sft_oe_n <= cmd_oen ;
end
//--------------------------------------------------
// shcp counter
//--------------------------------------------------
reg [5:0] shcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
shcp_cnt <= 0 ;
else if( vld && cmd == 2'b01 )
shcp_cnt <= 1 ;
else if( |shcp_cnt )
shcp_cnt <= shcp_cnt + 1 ;
end
assign sft_shcp = shcp_cnt[2] ;
reg [7:0] data ;
always @ ( posedge clk ) begin
if( vld && cmd == 2'b01 )
data <= din ;
else if( &shcp_cnt[2:0] )
data <= data >> 1 ;
end
assign sft_ds = (vld&&cmd==2'b01) ? din[0] : data[0] ;
//--------------------------------------------------
// sft_stcp
//--------------------------------------------------
reg [5:0] stcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
stcp_cnt <= 0 ;
else if( vld && cmd == 2'b10 )
stcp_cnt <= 1 ;
else if( |stcp_cnt )
stcp_cnt <= stcp_cnt + 1 ;
end
assign sft_stcp = stcp_cnt[2] ;
//--------------------------------------------------
// done
//--------------------------------------------------
assign done = (stcp_cnt == 63) || (shcp_cnt == 63) ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFSTP_FUNCTIONAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRBP_1_V
`define SKY130_FD_SC_LS__SDFRBP_1_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRBP_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:56:56 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112,
n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128, n129, n130, n131, n132, n133, n134,
n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145,
n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156,
n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167,
n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178,
n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211,
n212, n213, n214, n215, n216, n217, n218, n219, n220, n221, n222,
n223, n224, n225, n226, n227, n228, n229, n230, n231, n232, n233,
n234, n235, n236, n237, n238, n239, n240, n241, n242, n243, n244,
n245, n246, n247, n248, n249, n250, n251, n252, n253, n254, n255,
n256, n257, n258, n259, n260, n261, n262, n263, n264, n265, n266,
n267, n268, n269, n270, n271, n272, n273, n274, n275, n276, n277,
n278, n279, n280, n281, n282, n283, n284, n285, n286, n287, n288,
n289, n290, n291, n292, n293, n294, n295, n296, n297, n298, n299,
n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310,
n311, n312, n313, n314, n315, n316, n317, n318, n319;
NAND2X1TS U35 ( .A(n57), .B(n219), .Y(n220) );
NAND2XLTS U36 ( .A(n52), .B(n267), .Y(n268) );
NAND2XLTS U37 ( .A(n58), .B(n258), .Y(n259) );
NAND2XLTS U38 ( .A(n51), .B(n263), .Y(n264) );
NAND2XLTS U39 ( .A(n249), .B(n248), .Y(n250) );
NAND2XLTS U40 ( .A(n4), .B(n222), .Y(n223) );
NAND2X1TS U41 ( .A(n238), .B(n237), .Y(n239) );
NAND2X1TS U42 ( .A(n245), .B(n244), .Y(n246) );
NAND2X1TS U43 ( .A(n231), .B(n230), .Y(n232) );
CMPR32X2TS U44 ( .A(in1[6]), .B(n100), .C(n79), .CO(n77), .S(res[6]) );
INVX2TS U45 ( .A(n274), .Y(n281) );
OR2X2TS U46 ( .A(n205), .B(in1[29]), .Y(n4) );
NAND2X2TS U47 ( .A(n197), .B(in1[26]), .Y(n244) );
NOR2X2TS U48 ( .A(n196), .B(in1[25]), .Y(n241) );
NAND2X2TS U49 ( .A(n198), .B(in1[27]), .Y(n237) );
NAND2X2TS U50 ( .A(n199), .B(in1[28]), .Y(n230) );
NAND2X2TS U51 ( .A(n206), .B(in1[30]), .Y(n219) );
CLKMX2X2TS U52 ( .A(in2[30]), .B(n202), .S0(n212), .Y(n206) );
NOR2X1TS U53 ( .A(n210), .B(in2[30]), .Y(n211) );
NOR2X2TS U54 ( .A(n288), .B(n283), .Y(n165) );
OR2X4TS U55 ( .A(n190), .B(in1[22]), .Y(n52) );
NAND2XLTS U56 ( .A(n12), .B(in2[28]), .Y(n26) );
OAI21X2TS U57 ( .A0(n7), .A1(n12), .B0(n6), .Y(n314) );
XNOR2X1TS U58 ( .A(n203), .B(in2[29]), .Y(n204) );
XNOR2X2TS U59 ( .A(n132), .B(in2[26]), .Y(n133) );
XNOR2X1TS U60 ( .A(n124), .B(in2[27]), .Y(n125) );
XOR2X2TS U61 ( .A(n28), .B(in2[28]), .Y(n27) );
NOR2X1TS U62 ( .A(n201), .B(n126), .Y(n124) );
MX2X2TS U63 ( .A(in2[21]), .B(n181), .S0(add_sub), .Y(n189) );
NOR2BX2TS U64 ( .AN(n131), .B(n200), .Y(n28) );
NAND2X6TS U65 ( .A(n16), .B(n296), .Y(n14) );
NAND2BX2TS U66 ( .AN(in2[29]), .B(n203), .Y(n210) );
NOR2X2TS U67 ( .A(n201), .B(in2[24]), .Y(n127) );
XNOR2X1TS U68 ( .A(n65), .B(in2[3]), .Y(n7) );
NAND2XLTS U69 ( .A(n12), .B(in2[23]), .Y(n43) );
OA21X2TS U70 ( .A0(n13), .A1(n12), .B0(n11), .Y(n155) );
XNOR2X2TS U71 ( .A(n166), .B(in2[18]), .Y(n160) );
XNOR2X2TS U72 ( .A(n182), .B(in2[20]), .Y(n171) );
XNOR2X1TS U73 ( .A(n201), .B(in2[24]), .Y(n178) );
XOR2X2TS U74 ( .A(n45), .B(in2[23]), .Y(n44) );
INVX2TS U75 ( .A(in2[4]), .Y(n71) );
NOR2X2TS U76 ( .A(n166), .B(in2[18]), .Y(n167) );
NAND2X2TS U77 ( .A(n184), .B(n183), .Y(n185) );
INVX2TS U78 ( .A(in2[21]), .Y(n3) );
NOR2X4TS U79 ( .A(n182), .B(in2[20]), .Y(n180) );
CLKINVX2TS U80 ( .A(n182), .Y(n184) );
NOR2X4TS U81 ( .A(n65), .B(in2[3]), .Y(n72) );
NAND2X1TS U82 ( .A(n130), .B(n134), .Y(n126) );
INVX4TS U83 ( .A(n170), .Y(n156) );
NOR2X2TS U84 ( .A(in2[25]), .B(in2[24]), .Y(n130) );
NAND3X1TS U85 ( .A(n151), .B(n150), .C(n149), .Y(n152) );
NOR2X6TS U86 ( .A(n142), .B(in1[13]), .Y(n145) );
AND2X2TS U87 ( .A(n159), .B(n122), .Y(n169) );
NAND2X2TS U88 ( .A(n142), .B(in1[13]), .Y(n143) );
NAND2X4TS U89 ( .A(n151), .B(n150), .Y(n146) );
XOR2X2TS U90 ( .A(n151), .B(in2[12]), .Y(n112) );
BUFX12TS U91 ( .A(add_sub), .Y(n186) );
NAND2X6TS U92 ( .A(n50), .B(n47), .Y(n98) );
CLKINVX6TS U93 ( .A(n110), .Y(n47) );
CLKINVX6TS U94 ( .A(n109), .Y(n50) );
NOR2X6TS U95 ( .A(in2[3]), .B(in2[2]), .Y(n48) );
CLKINVX6TS U96 ( .A(in2[8]), .Y(n93) );
NOR2XLTS U97 ( .A(in2[23]), .B(in2[22]), .Y(n123) );
NOR2XLTS U98 ( .A(in2[19]), .B(in2[18]), .Y(n122) );
NAND2X4TS U99 ( .A(n93), .B(n92), .Y(n109) );
NOR2X2TS U100 ( .A(n182), .B(n46), .Y(n45) );
NOR2X6TS U101 ( .A(in2[7]), .B(in2[6]), .Y(n49) );
MXI2X2TS U102 ( .A(n149), .B(n147), .S0(n186), .Y(n148) );
MXI2X2TS U103 ( .A(n179), .B(n178), .S0(n186), .Y(n194) );
NOR2X4TS U104 ( .A(n198), .B(in1[27]), .Y(n236) );
NOR2XLTS U105 ( .A(in1[7]), .B(n102), .Y(n87) );
NOR2X4TS U106 ( .A(in1[11]), .B(n137), .Y(n140) );
NAND2X2TS U107 ( .A(n40), .B(n299), .Y(n21) );
NAND2X1TS U108 ( .A(n205), .B(in1[29]), .Y(n222) );
XOR2X1TS U109 ( .A(in1[11]), .B(n106), .Y(n107) );
OAI21XLTS U110 ( .A0(n292), .A1(n288), .B0(n289), .Y(n287) );
INVX4TS U111 ( .A(n224), .Y(n251) );
ADDHXLTS U112 ( .A(in2[0]), .B(in1[0]), .CO(n311), .S(res[0]) );
BUFX4TS U113 ( .A(add_sub), .Y(n212) );
INVX4TS U114 ( .A(n186), .Y(n12) );
INVX2TS U115 ( .A(n219), .Y(n207) );
XOR2X2TS U116 ( .A(in1[9]), .B(n89), .Y(n90) );
OR2X4TS U117 ( .A(n194), .B(in1[24]), .Y(n58) );
NOR2X4TS U118 ( .A(n156), .B(in2[16]), .Y(n157) );
MX2X4TS U119 ( .A(in2[5]), .B(n74), .S0(add_sub), .Y(n319) );
INVX6TS U120 ( .A(in2[2]), .Y(n68) );
NOR2X2TS U121 ( .A(n306), .B(n303), .Y(n307) );
NOR2X4TS U122 ( .A(n38), .B(n262), .Y(n37) );
OAI21X2TS U123 ( .A0(n229), .A1(n237), .B0(n230), .Y(n32) );
INVX2TS U124 ( .A(n229), .Y(n231) );
INVX2TS U125 ( .A(n243), .Y(n245) );
INVX2TS U126 ( .A(n236), .Y(n238) );
OR2X4TS U127 ( .A(n206), .B(in1[30]), .Y(n57) );
NAND2X4TS U128 ( .A(n196), .B(in1[25]), .Y(n248) );
XNOR2X1TS U129 ( .A(n211), .B(in2[31]), .Y(n213) );
NAND2X4TS U130 ( .A(n189), .B(in1[21]), .Y(n270) );
OR2X4TS U131 ( .A(n193), .B(in1[23]), .Y(n51) );
NOR2X4TS U132 ( .A(n189), .B(in1[21]), .Y(n266) );
NAND2X4TS U133 ( .A(n173), .B(in1[19]), .Y(n279) );
MX2X2TS U134 ( .A(in2[29]), .B(n204), .S0(add_sub), .Y(n205) );
NOR3X4TS U135 ( .A(n201), .B(in2[28]), .C(n200), .Y(n203) );
OAI2BB1X2TS U136 ( .A0N(n102), .A1N(in1[7]), .B0(n101), .Y(n103) );
OAI211X2TS U137 ( .A0(in1[7]), .A1(n102), .B0(n100), .C0(in1[6]), .Y(n101)
);
NAND2X6TS U138 ( .A(n170), .B(n29), .Y(n201) );
NAND2X2TS U139 ( .A(n141), .B(in1[12]), .Y(n144) );
MX2X4TS U140 ( .A(in2[7]), .B(n60), .S0(add_sub), .Y(n102) );
OAI21X2TS U141 ( .A0(n273), .A1(n266), .B0(n270), .Y(n269) );
XOR2X1TS U142 ( .A(n273), .B(n272), .Y(res[21]) );
XOR2X1TS U143 ( .A(n278), .B(n277), .Y(res[20]) );
XOR2X1TS U144 ( .A(n292), .B(n291), .Y(res[17]) );
NAND2X2TS U145 ( .A(n215), .B(n304), .Y(n216) );
OA21X2TS U146 ( .A0(n306), .A1(n305), .B0(n304), .Y(n5) );
NAND2X2TS U147 ( .A(n214), .B(in1[31]), .Y(n304) );
MX2X2TS U148 ( .A(in2[31]), .B(n213), .S0(n212), .Y(n214) );
NAND2X4TS U149 ( .A(n51), .B(n58), .Y(n38) );
OR2X4TS U150 ( .A(n173), .B(in1[19]), .Y(n55) );
XOR2X1TS U151 ( .A(n302), .B(n301), .Y(res[14]) );
MX2X2TS U152 ( .A(in2[17]), .B(n158), .S0(add_sub), .Y(n162) );
NAND2X2TS U153 ( .A(n174), .B(in1[20]), .Y(n276) );
NAND2X2TS U154 ( .A(n194), .B(in1[24]), .Y(n258) );
NAND2X2TS U155 ( .A(n163), .B(in1[18]), .Y(n284) );
OR2X4TS U156 ( .A(n155), .B(in1[16]), .Y(n293) );
XOR2X2TS U157 ( .A(n77), .B(in1[7]), .Y(n78) );
NAND2X2TS U158 ( .A(n148), .B(in1[14]), .Y(n300) );
OR2X4TS U159 ( .A(n148), .B(in1[14]), .Y(n299) );
XOR2X1TS U160 ( .A(n319), .B(n318), .Y(res[5]) );
OAI2BB1X2TS U161 ( .A0N(n319), .A1N(in1[5]), .B0(n85), .Y(n86) );
OAI211X1TS U162 ( .A0(in1[5]), .A1(n319), .B0(n316), .C0(in1[4]), .Y(n85) );
MXI2X4TS U163 ( .A(n113), .B(n112), .S0(n186), .Y(n141) );
XNOR2X2TS U164 ( .A(n59), .B(in2[7]), .Y(n60) );
OAI2BB1X2TS U165 ( .A0N(n314), .A1N(in1[3]), .B0(n69), .Y(n70) );
XOR2X2TS U166 ( .A(n73), .B(in2[5]), .Y(n74) );
NAND2X2TS U167 ( .A(n72), .B(n71), .Y(n73) );
NAND2BX2TS U168 ( .AN(n66), .B(n12), .Y(n6) );
AND2X4TS U169 ( .A(n169), .B(n30), .Y(n29) );
NOR2X1TS U170 ( .A(n212), .B(n20), .Y(n19) );
CLKMX2X2TS U171 ( .A(in2[1]), .B(n308), .S0(add_sub), .Y(n312) );
INVX12TS U172 ( .A(in2[9]), .Y(n92) );
NAND2X4TS U173 ( .A(n271), .B(n52), .Y(n262) );
NAND2X2TS U174 ( .A(n8), .B(n5), .Y(res[32]) );
XOR2X4TS U175 ( .A(n180), .B(n3), .Y(n181) );
NAND2X2TS U176 ( .A(n18), .B(n17), .Y(n54) );
AOI21X2TS U177 ( .A0(n275), .A1(n53), .B0(n175), .Y(n176) );
NAND2X6TS U178 ( .A(n136), .B(in1[10]), .Y(n139) );
NAND2X4TS U179 ( .A(n50), .B(n25), .Y(n24) );
NAND2X2TS U180 ( .A(n151), .B(n113), .Y(n23) );
OAI21X4TS U181 ( .A0(n44), .A1(n12), .B0(n43), .Y(n193) );
MXI2X4TS U182 ( .A(n161), .B(n160), .S0(n186), .Y(n163) );
AOI21X2TS U183 ( .A0(n153), .A1(n212), .B0(n19), .Y(n18) );
AOI222X2TS U184 ( .A0(n100), .A1(in1[6]), .B0(n100), .B1(n86), .C0(in1[6]),
.C1(n86), .Y(n88) );
NAND2X4TS U185 ( .A(n80), .B(n68), .Y(n65) );
XOR2X1TS U186 ( .A(n137), .B(n107), .Y(res[11]) );
AOI222X2TS U187 ( .A0(n114), .A1(in1[8]), .B0(n114), .B1(n103), .C0(in1[8]),
.C1(n103), .Y(n105) );
NAND2X4TS U188 ( .A(n155), .B(in1[16]), .Y(n294) );
AOI21X4TS U189 ( .A0(n254), .A1(n58), .B0(n195), .Y(n36) );
NAND2X2TS U190 ( .A(n193), .B(in1[23]), .Y(n263) );
NAND2X8TS U191 ( .A(n294), .B(n10), .Y(n282) );
MXI2X4TS U192 ( .A(n96), .B(n95), .S0(n12), .Y(n137) );
XOR2X4TS U193 ( .A(n94), .B(in2[11]), .Y(n96) );
NOR2X4TS U194 ( .A(n98), .B(in2[10]), .Y(n94) );
OAI21X2TS U195 ( .A0(n273), .A1(n257), .B0(n256), .Y(n260) );
OAI21X2TS U196 ( .A0(n273), .A1(n262), .B0(n261), .Y(n265) );
XNOR2X4TS U197 ( .A(n157), .B(in2[17]), .Y(n158) );
AND2X2TS U198 ( .A(n123), .B(n183), .Y(n30) );
MXI2X4TS U199 ( .A(n97), .B(n99), .S0(n186), .Y(n136) );
XOR2X1TS U200 ( .A(n98), .B(n97), .Y(n99) );
NAND2X2TS U201 ( .A(n137), .B(in1[11]), .Y(n138) );
NOR2X2TS U202 ( .A(n141), .B(in1[12]), .Y(n135) );
NOR2X4TS U203 ( .A(n197), .B(in1[26]), .Y(n243) );
XOR2X1TS U204 ( .A(n152), .B(in2[15]), .Y(n153) );
INVX2TS U205 ( .A(in2[15]), .Y(n20) );
NAND2X1TS U206 ( .A(n12), .B(n154), .Y(n11) );
XNOR2X1TS U207 ( .A(n170), .B(in2[16]), .Y(n13) );
NAND3X6TS U208 ( .A(n22), .B(n21), .C(n300), .Y(n298) );
NAND3X4TS U209 ( .A(n42), .B(n39), .C(n299), .Y(n22) );
INVX2TS U210 ( .A(in1[15]), .Y(n17) );
NAND2X2TS U211 ( .A(n15), .B(in1[15]), .Y(n296) );
INVX2TS U212 ( .A(n18), .Y(n15) );
INVX2TS U213 ( .A(n241), .Y(n249) );
INVX2TS U214 ( .A(n222), .Y(n218) );
INVX2TS U215 ( .A(n303), .Y(n209) );
INVX2TS U216 ( .A(n305), .Y(n208) );
NAND2X2TS U217 ( .A(n57), .B(n4), .Y(n303) );
NOR2X4TS U218 ( .A(n214), .B(in1[31]), .Y(n306) );
NAND2X2TS U219 ( .A(n34), .B(n235), .Y(n33) );
AOI21X2TS U220 ( .A0(n34), .A1(n234), .B0(n32), .Y(n31) );
NOR2X4TS U221 ( .A(n229), .B(n236), .Y(n34) );
NAND2BX1TS U222 ( .AN(in2[22]), .B(n183), .Y(n46) );
NAND2X4TS U223 ( .A(n170), .B(n169), .Y(n182) );
INVX2TS U224 ( .A(n258), .Y(n195) );
NAND2X4TS U225 ( .A(n81), .B(n72), .Y(n61) );
NOR2X2TS U226 ( .A(in2[11]), .B(in2[10]), .Y(n25) );
INVX2TS U227 ( .A(n263), .Y(n254) );
NAND2X1TS U228 ( .A(n55), .B(n53), .Y(n177) );
NAND2X2TS U229 ( .A(n131), .B(n130), .Y(n132) );
NOR2X4TS U230 ( .A(n163), .B(in1[18]), .Y(n283) );
NOR2X4TS U231 ( .A(n162), .B(in1[17]), .Y(n288) );
NAND2X2TS U232 ( .A(n162), .B(in1[17]), .Y(n289) );
INVX2TS U233 ( .A(n282), .Y(n292) );
INVX2TS U234 ( .A(n279), .Y(n275) );
OR2X2TS U235 ( .A(n174), .B(in1[20]), .Y(n53) );
INVX2TS U236 ( .A(n266), .Y(n271) );
INVX2TS U237 ( .A(n267), .Y(n191) );
INVX2TS U238 ( .A(n270), .Y(n192) );
INVX2TS U239 ( .A(n262), .Y(n253) );
AOI21X1TS U240 ( .A0(n255), .A1(n51), .B0(n254), .Y(n256) );
INVX2TS U241 ( .A(n261), .Y(n255) );
INVX2TS U242 ( .A(n252), .Y(n273) );
INVX2TS U243 ( .A(n248), .Y(n242) );
NOR2X4TS U244 ( .A(n241), .B(n243), .Y(n235) );
NOR2X4TS U245 ( .A(n199), .B(in1[28]), .Y(n229) );
OAI21X1TS U246 ( .A0(n226), .A1(n236), .B0(n237), .Y(n227) );
NOR2X1TS U247 ( .A(n225), .B(n236), .Y(n228) );
INVX2TS U248 ( .A(n235), .Y(n225) );
XOR2X1TS U249 ( .A(in1[13]), .B(n119), .Y(n120) );
NAND2X1TS U250 ( .A(n299), .B(n300), .Y(n301) );
AOI21X1TS U251 ( .A0(n41), .A1(n42), .B0(n40), .Y(n302) );
OAI21XLTS U252 ( .A0(n140), .A1(n139), .B0(n138), .Y(n41) );
NAND2X1TS U253 ( .A(n54), .B(n296), .Y(n297) );
NAND2X1TS U254 ( .A(n293), .B(n294), .Y(n295) );
NAND2X1TS U255 ( .A(n290), .B(n289), .Y(n291) );
INVX2TS U256 ( .A(n288), .Y(n290) );
XNOR2X1TS U257 ( .A(n287), .B(n286), .Y(res[18]) );
NAND2X1TS U258 ( .A(n285), .B(n284), .Y(n286) );
INVX2TS U259 ( .A(n283), .Y(n285) );
NAND2X1TS U260 ( .A(n55), .B(n279), .Y(n280) );
NAND2X1TS U261 ( .A(n53), .B(n276), .Y(n277) );
AOI21X1TS U262 ( .A0(n281), .A1(n55), .B0(n275), .Y(n278) );
NAND2X1TS U263 ( .A(n271), .B(n270), .Y(n272) );
XNOR2X1TS U264 ( .A(n265), .B(n264), .Y(res[23]) );
XNOR2X1TS U265 ( .A(n260), .B(n259), .Y(res[24]) );
NAND2X1TS U266 ( .A(n253), .B(n51), .Y(n257) );
XNOR2X1TS U267 ( .A(n251), .B(n250), .Y(res[25]) );
INVX2TS U268 ( .A(n306), .Y(n215) );
OAI2BB2X1TS U269 ( .B0(n76), .B1(n75), .A0N(in1[5]), .A1N(n319), .Y(n79) );
NAND2X4TS U270 ( .A(n298), .B(n54), .Y(n16) );
INVX2TS U271 ( .A(n201), .Y(n131) );
OAI2BB2X1TS U272 ( .B0(n88), .B1(n87), .A0N(in1[7]), .A1N(n102), .Y(n91) );
MXI2X4TS U273 ( .A(n63), .B(n62), .S0(n212), .Y(n100) );
XNOR2X1TS U274 ( .A(n61), .B(in2[6]), .Y(n62) );
MXI2X4TS U275 ( .A(n93), .B(n84), .S0(n186), .Y(n114) );
OAI21X4TS U276 ( .A0(n224), .A1(n33), .B0(n31), .Y(n9) );
AOI21X4TS U277 ( .A0(n9), .A1(n209), .B0(n208), .Y(n217) );
AOI21X4TS U278 ( .A0(n9), .A1(n4), .B0(n218), .Y(n221) );
NAND2X2TS U279 ( .A(n9), .B(n307), .Y(n8) );
XNOR2X1TS U280 ( .A(n9), .B(n223), .Y(res[29]) );
NOR2X8TS U281 ( .A(in2[0]), .B(in2[1]), .Y(n80) );
NAND2X8TS U282 ( .A(n14), .B(n293), .Y(n10) );
XOR2X4TS U283 ( .A(n23), .B(in2[13]), .Y(n111) );
NOR2X8TS U284 ( .A(n24), .B(n110), .Y(n151) );
NAND2X4TS U285 ( .A(n170), .B(n159), .Y(n166) );
OAI21X4TS U286 ( .A0(n27), .A1(n12), .B0(n26), .Y(n199) );
OAI21X4TS U287 ( .A0(n274), .A1(n177), .B0(n176), .Y(n252) );
AOI21X4TS U288 ( .A0(n282), .A1(n165), .B0(n164), .Y(n274) );
AOI21X4TS U289 ( .A0(n252), .A1(n37), .B0(n35), .Y(n224) );
OAI21X4TS U290 ( .A0(n261), .A1(n38), .B0(n36), .Y(n35) );
AOI21X4TS U291 ( .A0(n192), .A1(n52), .B0(n191), .Y(n261) );
NOR2X4TS U292 ( .A(n145), .B(n135), .Y(n42) );
OAI21X4TS U293 ( .A0(n140), .A1(n139), .B0(n138), .Y(n39) );
OAI21X4TS U294 ( .A0(n145), .A1(n144), .B0(n143), .Y(n40) );
NAND4X8TS U295 ( .A(n80), .B(n49), .C(n81), .D(n48), .Y(n110) );
ADDFHX2TS U296 ( .A(in1[8]), .B(n114), .CI(n91), .CO(n89), .S(res[8]) );
ADDFHX2TS U297 ( .A(in1[12]), .B(n141), .CI(n121), .CO(n119), .S(res[12]) );
MXI2X8TS U298 ( .A(n92), .B(n83), .S0(n212), .Y(n116) );
XOR2X1TS U299 ( .A(n233), .B(n232), .Y(res[28]) );
XOR2X1TS U300 ( .A(n247), .B(n246), .Y(res[26]) );
XOR2X1TS U301 ( .A(n240), .B(n239), .Y(res[27]) );
MXI2X4TS U302 ( .A(n172), .B(n171), .S0(n186), .Y(n174) );
ADDFHX2TS U303 ( .A(in1[10]), .B(n136), .CI(n108), .CO(n106), .S(res[10]) );
MX2X4TS U304 ( .A(in2[19]), .B(n168), .S0(add_sub), .Y(n173) );
XNOR2X1TS U305 ( .A(n298), .B(n297), .Y(res[15]) );
NAND2X4TS U306 ( .A(n190), .B(in1[22]), .Y(n267) );
MXI2X2TS U307 ( .A(n68), .B(n67), .S0(n212), .Y(n310) );
MXI2X4TS U308 ( .A(n71), .B(n64), .S0(n212), .Y(n316) );
MX2X4TS U309 ( .A(in2[27]), .B(n125), .S0(add_sub), .Y(n198) );
AOI222X2TS U310 ( .A0(n136), .A1(in1[10]), .B0(n136), .B1(n117), .C0(in1[10]), .C1(n117), .Y(n118) );
OAI2BB1X4TS U311 ( .A0N(n116), .A1N(in1[9]), .B0(n115), .Y(n117) );
XNOR2X4TS U312 ( .A(n167), .B(in2[19]), .Y(n168) );
XNOR2X4TS U313 ( .A(n146), .B(in2[14]), .Y(n147) );
NOR2X8TS U314 ( .A(in2[5]), .B(in2[4]), .Y(n81) );
OAI2BB2X1TS U315 ( .B0(n118), .B1(n140), .A0N(in1[11]), .A1N(n137), .Y(n121)
);
NOR2X4TS U316 ( .A(n61), .B(in2[6]), .Y(n59) );
MXI2X4TS U317 ( .A(n188), .B(n187), .S0(n186), .Y(n190) );
XNOR2X4TS U318 ( .A(n185), .B(in2[22]), .Y(n187) );
MX2X4TS U319 ( .A(in2[13]), .B(n111), .S0(n212), .Y(n142) );
OAI2BB2X2TS U320 ( .B0(n105), .B1(n104), .A0N(in1[9]), .A1N(n116), .Y(n108)
);
XNOR2X4TS U321 ( .A(n82), .B(n92), .Y(n83) );
NOR3X8TS U322 ( .A(n146), .B(in2[15]), .C(in2[14]), .Y(n170) );
INVX2TS U323 ( .A(n276), .Y(n175) );
INVX2TS U324 ( .A(in2[6]), .Y(n63) );
XNOR2X1TS U325 ( .A(n72), .B(n71), .Y(n64) );
INVX2TS U326 ( .A(in2[3]), .Y(n66) );
XNOR2X1TS U327 ( .A(n80), .B(n68), .Y(n67) );
OAI211X1TS U328 ( .A0(in1[3]), .A1(n314), .B0(n310), .C0(in1[2]), .Y(n69) );
AOI222X1TS U329 ( .A0(n316), .A1(in1[4]), .B0(n316), .B1(n70), .C0(in1[4]),
.C1(n70), .Y(n76) );
NOR2X1TS U330 ( .A(in1[5]), .B(n319), .Y(n75) );
XOR2X1TS U331 ( .A(n102), .B(n78), .Y(res[7]) );
NOR2X1TS U332 ( .A(in2[8]), .B(n110), .Y(n82) );
XNOR2X1TS U333 ( .A(n110), .B(in2[8]), .Y(n84) );
XOR2X1TS U334 ( .A(n116), .B(n90), .Y(res[9]) );
INVX2TS U335 ( .A(in2[11]), .Y(n95) );
INVX2TS U336 ( .A(in2[10]), .Y(n97) );
NOR2X1TS U337 ( .A(in1[9]), .B(n116), .Y(n104) );
INVX2TS U338 ( .A(in2[12]), .Y(n113) );
OAI211X1TS U339 ( .A0(in1[9]), .A1(n116), .B0(n114), .C0(in1[8]), .Y(n115)
);
XOR2X1TS U340 ( .A(n142), .B(n120), .Y(res[13]) );
NOR2X2TS U341 ( .A(in2[13]), .B(in2[12]), .Y(n150) );
NOR2X2TS U342 ( .A(in2[17]), .B(in2[16]), .Y(n159) );
NOR2X2TS U343 ( .A(in2[21]), .B(in2[20]), .Y(n183) );
INVX2TS U344 ( .A(in2[26]), .Y(n134) );
OR2X2TS U345 ( .A(n126), .B(in2[27]), .Y(n200) );
XOR2X1TS U346 ( .A(n127), .B(in2[25]), .Y(n129) );
INVX2TS U347 ( .A(in2[25]), .Y(n128) );
MXI2X4TS U348 ( .A(n129), .B(n128), .S0(n12), .Y(n196) );
MXI2X4TS U349 ( .A(n134), .B(n133), .S0(n186), .Y(n197) );
INVX2TS U350 ( .A(in2[14]), .Y(n149) );
INVX2TS U351 ( .A(in2[16]), .Y(n154) );
INVX2TS U352 ( .A(in2[18]), .Y(n161) );
OAI21X4TS U353 ( .A0(n289), .A1(n283), .B0(n284), .Y(n164) );
INVX2TS U354 ( .A(in2[20]), .Y(n172) );
INVX2TS U355 ( .A(in2[24]), .Y(n179) );
INVX2TS U356 ( .A(in2[22]), .Y(n188) );
OAI21X4TS U357 ( .A0(n243), .A1(n248), .B0(n244), .Y(n234) );
XOR2X1TS U358 ( .A(n210), .B(in2[30]), .Y(n202) );
AOI21X4TS U359 ( .A0(n57), .A1(n218), .B0(n207), .Y(n305) );
XOR2X4TS U360 ( .A(n217), .B(n216), .Y(res[31]) );
XOR2X4TS U361 ( .A(n221), .B(n220), .Y(res[30]) );
INVX2TS U362 ( .A(n234), .Y(n226) );
AOI21X4TS U363 ( .A0(n251), .A1(n228), .B0(n227), .Y(n233) );
AOI21X4TS U364 ( .A0(n251), .A1(n235), .B0(n234), .Y(n240) );
AOI21X4TS U365 ( .A0(n251), .A1(n249), .B0(n242), .Y(n247) );
XNOR2X1TS U366 ( .A(n269), .B(n268), .Y(res[22]) );
XNOR2X1TS U367 ( .A(n281), .B(n280), .Y(res[19]) );
XNOR2X1TS U368 ( .A(n14), .B(n295), .Y(res[16]) );
XOR2X1TS U369 ( .A(in2[0]), .B(in2[1]), .Y(n308) );
CMPR32X2TS U370 ( .A(in1[2]), .B(n310), .C(n309), .CO(n313), .S(res[2]) );
CMPR32X2TS U371 ( .A(in1[1]), .B(n312), .C(n311), .CO(n309), .S(res[1]) );
CMPR32X2TS U372 ( .A(in1[3]), .B(n314), .C(n313), .CO(n315), .S(res[3]) );
CMPR32X2TS U373 ( .A(in1[4]), .B(n316), .C(n315), .CO(n317), .S(res[4]) );
XOR2X1TS U374 ( .A(in1[5]), .B(n317), .Y(n318) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_GeArN16R2P4_syn.sdf");
endmodule
|
(** * MoreInd: More on Induction *)
Require Export "ProofObjects".
(* ##################################################### *)
(** * Induction Principles *)
(** * 帰納法の原理 *)
(** This is a good point to pause and take a deeper look at induction
principles.
Every time we declare a new [Inductive] datatype, Coq
automatically generates and proves an _induction principle_
for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
(** よい機会ですので、ちょっと休憩して、より深く帰納法の原理について見て行くことにしましょう
新たに[Inductive]なデータ型を宣言するときはいつでも、Coqは自動的にこの型の帰納法の原理 (_induction principle_)を生成します。
型[t]に対応する帰納法の原理は[t_ind]という名前になります。
ここでは自然数に対するものを示します。
*)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** *** *)
(* The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
(** [induction] タクティックは、基本的には [apply t_ind] の単純なラッパーです。
もっとわかりやすくするために、[induction] タクティックのかわりに [apply nat_ind] を使っていくつかの証明をしてみる実験をしてみましょう。
例えば、[Basics_J] の章で見た定理の別の証明を見てみましょう。 *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
Case "O". reflexivity.
Case "S". simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(* This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** この証明は基本的には前述のものと同じですが、細かい点で特筆すべき違いがあります。
1つめは、帰納段階の証明（["S"] の場合）において、[induction] が自動でやってくれること（[intros]）を手作業で行なう必要があることです。
2つめは、[nat_ind] を適用する前にコンテキストに [n] を導入していないことです。
[nat_ind] の結論は限量子を含む式であり、[apply] で使うためにはこの結論と限量子を含んだゴールの形とぴったりと一致する必要があります。
[induction] タクティックはコンテキストにある変数にもゴール内の量子化された変数のどちらにでも使えます。
3つめは、[apply] タクティックは変数名（この場合はサブゴール内で使われる変数名）を自動で選びますが、[induction] は（[as ...] 節によって）使う名前を指定できることです。
実際には、この自動選択にはちょっと不都合な点があります。元の定理の [n] とは別の変数として [n] を再利用してしまいます。
これは [Case] 注釈がただの [S] だからです。
ほかの証明で使ってきたように省略しない形で書くと、これは [n = S n] という意味のなさない形になってしまいます。
このようなことがあるため、実際には [nat_ind] のような帰納法の原理を直接適用するよりも、素直に [induction] を使ったほうがよいでしょう。
しかし、ちょっとした例外を除けば実際にやりたいのは [nat_ind] の適用であるということを知っておくことは重要です。 *)
(* **** Exercise: 2 stars (plus_one_r') *)
(** **** 練習問題: ★★ (plus_one_r') *)
(* Complete this proof without using the [induction] tactic. *)
(** [induction] タクティックを使わずに、下記の証明を完成させなさい。 *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. (Although
we don't need induction to prove properties of non-recursive
datatypes, the idea of an induction principle still makes sense
for them: it gives a way to prove that a property holds for all
values of the type.)
These generated principles follow a similar pattern. If we define a
type [t] with constructors [c1] ... [cn], Coq generates a theorem
with this shape:
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
(** Coqは[Inductive]によって定義されたあらゆるデータ型に対して帰納法の原理を生成します。その中には、帰納的でないものも含まれます。
(帰納的でないデータ型の性質を証明するために帰納法はもちろん必要ないのですが、帰納法の原理のアイデアは帰納的でないデータ型にたいしても問題なく適用できます。)
このように生成された原理は、似たようなパターンに対しても適用できます。
コンストラクタ [c1] ... [cn] を持った型 [t] を定義すると、Coqは次の形の定理を生成します。
t_ind :
forall P : t -> Prop,
... c1の場合 ... ->
... c2の場合 ... ->
... ->
... cnの場合 ... ->
forall n : t, P n
各場合分けの形は、対応するコンストラクタの引数の数によって決まります。
一般的な規則を紹介する前に、もっと例を見てみましょう。
最初は、コンストラクタが引数を取らない場合です。
*)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(* **** Exercise: 1 star, optional (rgb) *)
(** **** 練習問題: ★ , optional (rgb) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
紙かまたはコメント中に答えを書いたのち、Coqの出力と比較しなさい。 *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
Check rgb_ind.
(** [] *)
(* Here's another example, this time with one of the constructors
taking some arguments. *)
(** 別の例を見てみましょう。引数を受け取るコンストラクタがある場合です。 *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little variable renaming for clarity)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(* **** Exercise: 1 star, optional (natlist1) *)
(** **** 練習問題: ★, optional (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
(** 上記の定義をすこし変えたとしましょう。 *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(* Now what will the induction principle look like? *)
(** このとき、帰納法の原理はどのようになるでしょうか？ *)
(** [] *)
(* From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of
type [t]), then [P] holds for [c x1 ... xn]".
*)
(** これらの例より、一般的な規則を導くことができます。
- 型宣言は複数のコンストラクタを持ち、各コンストラクタが帰納法の原理の各節に対応する。
- 各コンストラクタ [c] は引数 [a1]..[an] を取る。
- [ai] は [t]（定義しようとしているデータ型）、もしくは別の型 [s] かのどちらかである。
- 帰納法の原理において各節は以下のことを述べている。
- "型 [a1]...[an] のすべての値 [x1]...[xn] について、各 [x] について [P] が成り立つならば、[c x1 ... xn] についても [P] が成り立つ"
*)
(* **** Exercise: 1 star, optional (byntree_ind) *)
(** **** 練習問題: ★, optional (byntree_ind) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
紙かまたはコメント中に答えを書いたのち、Coqの出力と比較しなさい。 *)
Inductive byntree : Type :=
| bempty : byntree
| bleaf : yesno -> byntree
| nbranch : yesno -> byntree -> byntree -> byntree.
(** [] *)
(* **** Exercise: 1 star, optional (ex_set) *)
(** **** 練習問題: ★, optional (ex_set) *)
(* Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
(** ここに帰納的に定義された集合(set)の定義に対する帰納法の原理があります
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
[ExSet]の[Inductive]による帰納的な定義を書きなさい *)
Inductive ExSet : Type :=
(* FILL IN HERE *)
.
(** [] *)
(* What about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** 多相的なデータ型ではどのようになるでしょうか？
多相的なリストの帰納的定義は [natlist] によく似ています。
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
ここでの主な違いは、定義全体が集合 [X] によってパラメータ化されていることです。
つまり、それぞれの [X] ごとに帰納型 [list X] を定義していることになります。
(定義本体で [list] が登場するときは、常にパラメータ [X] に適用されていることに
注意してください。)
帰納法の原理も同様に [X] によってパラメータ化されます。
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
この表現（と [list_ind] の全体的な形）に注目してください。帰納法の原理全体が
[X] によってパラメータ化されています。
別の見方をすると、[list_ind] は多相関数と考えることができます。この関数は、型 [X] が適用されると、[list X] に特化した帰納法の原理を返します。
*)
(* **** Exercise: 1 star (tree) *)
(** **** 練習問題: ★ (tree) *)
(* Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
(** 次のデータ型に対してCoqが生成する帰納法の原理を予測しなさい。
答えが書けたら、それをCoqの出力と比較しなさい。 *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(** [] *)
(** **** Exercise: 1 star, optional (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
(** [] *)
(* **** Exercise: 1 star, optional (foo) *)
(* Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** **** 練習問題: ★ (mytype) *)
(** 以下の帰納法の原理を生成する帰納的定義を探しなさい。
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo') *)
(** **** 練習問題: ★, optional (foo') *)
(* Consider the following inductive definition: *)
(** 次のような帰納的定義があるとします。 *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(* What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [foo'] に対してCoqはどのような帰納法の原理を生成するでしょうか?
空欄を埋め、Coqの結果と比較しなさい
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ##################################################### *)
(* ** Induction Hypotheses *)
(** ** 帰納法の仮定 *)
(* Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
(** この概念において"帰納法の仮定"はどこにあてはまるでしょうか?
数に関する帰納法の原理
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
は、すべての命題 [P]（より正確には数値 n を引数にとる命題 [P] ）について成り立つ一般的な文です。
この原理を使うときはいつも、[nat->Prop] という型を持つ式を [P] として選びます。
この式に名前を与えることで、証明をもっと明確にできます。
例えば、[mult_0_r] を"[forall n, n * 0 = 0]"と宣言するかわりに、"[forall n, P_m0r n]"と宣言します。
なお、ここで [P_m0r] は次のように定義されています。
*)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(* ... or equivalently... *)
(** あるいは・・・ *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** でも同じ意味です。 *)
(* Now when we do the proof it is easier to see where [P_m0r]
appears. *)
(** これで、証明する際に [P_m0r] がどこに現れるかが分かりやすくなります。 *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
Case "n = O". reflexivity.
Case "n = S n'".
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(* This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(** このように名前をつける手順は通常の証明では不要です。
しかし、1つ2つ試してみると、帰納法の仮定がどのようなものなのかが分かりやすくなります。
[forall n, P_m0r n] を [n] による帰納法（[induction] か [apply nat_ind] を使う）によって証明しようとすると、最初のサブゴールでは [P_m0r 0]（"[P] が0に対して成り立つ"）を証明しなければならず、2つめのサブゴールでは [forall n', P_m0r n' -> P_m0r (S n')]（"[P] が [n'] について成り立つならば、[P] が [S n'] についても成り立つ"あるいは" [P] が [S] によって保存される"）を証明しなければなりません。
帰納法の仮定(_induction hypothesis_)は、2つめの推論の基礎になっています -- [P] が [n'] について成り立つことを仮定することにより、それによって [P] が [S n'] について成り立つことを示すことができます。
*)
(* ##################################################### *)
(* ** More on the [induction] Tactic *)
(** ** [induction] タクティックについてもう少し *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative...
*)
(** [induction] タクティックは、実はこれまで見てきたような、いささか
低レベルな作業をこなすだけのものではありません。
自然数に関する帰納的な公理の非形式的な記述を思い出してみてください。:
- もし [P n] が数値 n を意味する何かの命題だとして、命題 P が全ての数値 n に
ついて成り立つことを示したい場合は、このような推論を
することができます。:
- [P O] が成り立つことを示す
- もし [P n'] が成り立つなら, [P (S n')] が成り立つことを示す。
- 任意の n について [P n] が成り立つと結論する。
我々が証明を [intros n] で始め、次に [induction n] とすると、
これはCoqに「特定の」 [n] について（それを仮定取り込むことで）考えて
から、その後でそれを帰納法を使って任意の数値にまで推し進めるよう
示していることになります。
このようなときに Coq が内部的に行っていることは、帰納法を適用した変数を
「再一般化（ _re-generalize_ ）」することです。
例えば、[plus] の結合則を証明するケースでは、
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
(** ...最初に 3個の変数を全てコンテキストに導入しています。
これはつまり"任意の [n], [m], [p] について考える"という
意味になっています... *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
(** ...ここで、[induction] タクティックを使い [P n] （任意の [n] に
ついて [n + (m + p) = (n + m) + p]）を証明し、すぐに、
コンテキストにある特定の [n] についても証明します。 *)
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
(** [induction] が作成した（帰納法の手順とも言うべき）二つ目の
ゴールでは、 [P n'] ならば任意の [n'] で [P (S n')] が成り立つ
ことを証明する必要があります。 この時に [induction] タクティックは
[P (S n')] をゴールにしたまま、自動的に [n'] と [P n'] を
コンテキストに導入してくれます。
*)
simpl. rewrite -> IHn'. reflexivity. Qed.
(* It also works to apply [induction] to a variable that is
quantified in the goal. *)
(** [induction] をゴールにある量化された変数に適用してもかまいません。 *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
Case "n = O". intros m. rewrite -> plus_0_r. reflexivity.
Case "n = S n'". intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(* Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
(** [induction n] が [m] をゴールに残したままにしていることに注目してください。
つまり、今証明しようとしている帰納的な性質は、[forall m] で表されて
いるということです。
もし [induction] をゴールにおいて量化された変数に対して他の量化子の後に
適用すると、[induction] タクティックは自動的に変数をその量化子に基づいて
コンテキストに導入します。 *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
(** ここで [n] の代わりに [m] を induction しましょう。... *)
induction m as [| m'].
Case "m = O". simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** **** 練習問題: ★, optional (plus_explicit_prop) *)
(* Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(** [plus_assoc'] と [plus_comm'] を、その証明とともに上の [mult_0_r''] と
同じスタイルになるよう書き直しなさい。このことは、それぞれの定理が
帰納法で証明された命題に明確な定義を与え、この定義された命題から定理と
証明を示しています。 *)
(* FILL IN HERE *)
(** [] *)
(* ** Generalizing Inductions. *)
(** ** 帰納法を一般化すること *)
(** One potentially confusing feature of the [induction] tactic is
that it happily lets you try to set up an induction over a term
that isn't sufficiently general. The net effect of this will be
to lose information (much as [destruct] can do), and leave
you unable to complete the proof. Here's an example: *)
(** [induction]タクティクの潜在的に混乱させるかもしれない特徴は、十分に一般的でない用語の上に帰納法を試さなければならないことかもしれません。
このことにより、([destruct]が出来ることとほとんど同じように)情報が失われてしまい、証明を完成させることが出来なくなってしまうでしょう。
例
*)
Lemma one_not_beautiful_FAILED: ~ beautiful 1.
Proof.
intro H.
(* Just doing an [inversion] on [H] won't get us very far in the [b_sum]
case. (Try it!). So we'll need induction. A naive first attempt: *)
(** [H]上で[inversion]を行うことは[b_sum]の場合以上のことを我々に与えてくれません。(試してみましょう!)。そのため帰納法が必要になります。
素直な最初の試みは、*)
induction H.
(* But now, although we get four cases, as we would expect from
the definition of [beautiful], we lose all information about [H] ! *)
(** しかし、我々は[beautiful]の定義から期待したとおり、4つの場合が得られますが、 [H]についての全ての情報を失なってしまいました! *)
Abort.
(** The problem is that [induction] over a Prop only works properly over
completely general instances of the Prop, i.e. one in which all
the arguments are free (unconstrained) variables.
In this respect it behaves more
like [destruct] than like [inversion].
When you're tempted to do use [induction] like this, it is generally
an indication that you need to be proving something more general.
But in some cases, it suffices to pull out any concrete arguments
into separate equations, like this: *)
(** 問題は、命題上の[induction]が 命題の完全に一般的なインスタンス上でのみ適切に働かないことです。
たとえば、すべての引数のうちの一つに自由な(拘束されていない)変数がある場合です。この点において、inductionは、[inversion]よりは、[destruct]のように振舞います。
上記のような場合に、[induction]をつかいたいときは、もっと一般的な何かを証明するための帰納法が必要になります。しかしいくつかの場合においては、以下のように具体的な引数から
差分を抽出するだけで事足ります。
*)
Lemma one_not_beautiful: forall n, n = 1 -> ~ beautiful n.
Proof.
intros n E H.
induction H as [| | | p q Hp IHp Hq IHq].
Case "b_0".
inversion E.
Case "b_3".
inversion E.
Case "b_5".
inversion E.
Case "b_sum".
(* the rest is a tedious case analysis *)
(** 以下つまらないケース分析です *)
destruct p as [|p'].
SCase "p = 0".
destruct q as [|q'].
SSCase "q = 0".
inversion E.
SSCase "q = S q'".
apply IHq. apply E.
SCase "p = S p'".
destruct q as [|q'].
SSCase "q = 0".
apply IHp. rewrite plus_0_r in E. apply E.
SSCase "q = S q'".
simpl in E. inversion E. destruct p'. inversion H0. inversion H0.
Qed.
(* There's a handy [remember] tactic that can generate the second
proof state out of the original one. *)
(** 二つめの証明の状態を生成することの出来るもっとお手軽な[remember]タクティックというのもあります。 *)
Lemma one_not_beautiful': ~ beautiful 1.
Proof.
intros H.
remember 1 as n eqn:E.
(* now carry on as above *)
(** あとは上記と同じ *)
induction H.
Admitted.
(* ####################################################### *)
(* * Informal Proofs (Advanced) *)
(** 非形式的な証明 (Advanced) *)
(* Q: What is the relation between a formal proof of a proposition
[P] and an informal proof of the same proposition [P]?
A: The latter should _teach_ the reader how to produce the
former.
Q: How much detail is needed??
Unfortunately, There is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the informal proof amounts to just
transcribing the formal one into words). This gives the reader
the _ability_ to reproduce the formal one for themselves, but it
doesn't _teach_ them anything.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because
usually writing the proof requires some deep insights into the
thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard part of work
that we went through to find the proof in the first place) and
clear high-level suggestions for the more routine parts to save the
reader from spending too much time reconstructing these
parts (e.g., what the IH says and what must be shown in each case
of an inductive proof), but not so much detail that the main ideas
are obscured.
Another key point: if we're comparing a formal proof of a
proposition [P] and an informal proof of [P], the proposition [P]
doesn't change. That is, formal and informal proofs are _talking
about the same world_ and they _must play by the same rules_. *)
(** Q: 命題 [P] の形式的な証明と、同じ命題 [P] の非形式的な証明の間にはどのような関係があるのでしょうか？
A: 後者は、読む人に「どのように形式的な証明を導くか」を示すようなものとなっているべきです。
Q: どの程度細かく書く必要があるのですか？
A: この問いに唯一と言えるような解答はありません。回答には選択の幅があります。
その範囲の片方の端は、読み手にただ形式的な証明全体を与えればよいという考えです。つまり非形式的な証明は、形式的な証明をただ単に普通の言葉で書き換えただけ 、ということです。この方法は、読み手に形式的な証明を書かせるための能力を与えることはできますが、それについて何かも「教えてくれる」訳ではありません。
これに対しもう一方の端は、「その定理は真で、頑張ればできるはず」ような記述です。この方法も、「教える」ということに関してはあまりいいやり方とはいえません。なぜなら、証明を記述するときはいつも、今証明しようとしているものの奥深くにまで目を向け考えることが必要とされますが、細かく書きすぎると証明を読む側の人の多くは自分自身の力で同じ思考にたどり着くことなく、あきらめて証明の記述に頼ってしまうでしょう。
一番の答えはその中間にあります。全ての要点をかいつまんだ証明というのは、「かつてあなたが証明をしたときに非常に苦労した部分について、読む人が同じ苦労をしなくて済むようになっている」ようなものです。そしてまた、読み手が同じような苦労を何時間もかけてする必要がないよう、証明の中で使える部品などを高度に示唆するものでなければなりません（例えば、仮定 IH が何を言っているかや、帰納的な証明のどの部分に現れるかなど）。しかし、詳細が少なすぎると、証明の主要なアイデアがうまく伝わりません。
もう一つのキーポイント：もし我々が命題 P の形式的な証明と非形式的な証明について話しているならば、命題 P 自体は何も変わりません。このことは、形式的な証明も非形式的な証明も、同じ「世界」について話をしていて、同じルール(_rule_)に基づいていなければならない、と言うことを意味しています。
*)
(* ** Informal Proofs by Induction *)
(** ** 帰納法による非形式的な証明 *)
(** Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief
and telegraphic. The ideal is somewhere in between, of course,
but while you are getting used to the style it is better to start
out at the pedantic end. Also, during the learning phase, it is
probably helpful to have a clear standard to compare against.
With this in mind, we offer two templates below -- one for proofs
by induction over _data_ (i.e., where the thing we're doing
induction on lives in [Type]) and one for proofs by induction over
_evidence_ (i.e., where the inductively defined thing lives in
[Prop]). In the rest of this course, please follow one of the two
for _all_ of your inductive proofs. *)
(** ここまで、我々は「帰納法を使った形式的な証明の舞台裏」を覗くことにずいぶん章を割いてきました。そろそろ「帰納法を使った非形式的な証明」に話を向けてみましょう。
現実世界の数学的な事柄をやりとりするた記述された証明を見てみると、極端に風呂敷が広く衒学的なものから、逆に短く簡潔すぎるものまで様々です。理想的なものはその間のとこかにあります。もちろん、じぶんなりのスタイルを見つけるまでは、衒学的なスタイルから始めてみるほうがいいでしょう。また、学習中には、標準的なテンプレートと比較してみることも、学習の一助になるでしょう。
このような考えから、我々は以下の二つのテンプレートを用意しました。一つは「データ」に対して（「型」に潜む帰納的な構造について）帰納法を適用したもの、もう一つは「命題」に対して（命題に潜む機能的な定義について）帰納法を適用したものです。このコースが終わるまでに、あなたが行った帰納的な証明の全てに、どちらかの方法を適用してみましょう。
*)
(* *** Induction Over an Inductively Defined Set *)
(** *** 帰納的に定義された集合についての帰納法 *)
(* _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if length [[] = n], then [index (S n) [] =
None].
This follows immediately from the definition of index.
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be length [l']. [] *)
(** _Template_:
- 定理: < "For all [n:S], [P(n)],"の形で全量子化された命題。ただし [S] は帰納的に定義された集合。>
証明: [n] についての帰納法で証明する。
<集合 [S] の各コンストラクタ [c] について...>
- [n = c a1 ... ak] と仮定して、<...もし必要なら [S] のそれぞれの要素 [a] についてIHであることをを示す。>ならば
<...ここで再び [P(c a1 ... ak)] を示す> である。
< [P(n)] を証明してこのケースを終わらせる...>
- <他のケースも同様に記述する...> []
_Example_:
- _Theorem_: 任意の集合 [X] 、リスト [l : list X]、 自然数 [n] について、
もし [length l = n] が成り立つなら、[index (S n) l = None] も成り立つ。
_Proof_: [l] についての帰納法で証明する。
- まず、[l = []] と仮定して、任意の [n] でこれが成り立つことを示す。もし length [[] = n] ならば [index (S n) [] = None] 。
これは index の定義から直接導かれる 。
- 次に、 [x] と [l'] において [l = x :: l'] と仮定して、任意の [n'] について
[length l' = n'] ならば [index (S n') l' = None] である時、任意の [n] について、
もし [length (x::l') = n] ならば [index (S n) (x::l') = None] を示す。
[n] を [length l = n] となるような数とすると、
length l = length (x::l') = S (length l'),
これは以下の十分条件である。
index (S (length l')) l' = None.
しかしこれは仮定法の仮定から直接導かれる。
[l'] の length となるような [n'] を選択すればよい。 [] *)
(* *** Induction Over an Inductively Defined Proposition *)
(** *** 帰納的に定義された命題についての帰納法 *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(** 帰納的に定義された証明オブジェクトは、しばしば”導出木”と呼ばれるため、この形の証明は「導出による帰納法（ _induction on derivations_ ）」として知られています。
_Template_ :
- _Theorem_ : <"[Q -> P]," という形を持った命題。ただし [Q] は帰納的に定義された命題（さらに一般的には、"For all [x] [y] [z], [Q x y z -> P x y z]" という形の命題）>
_Proof_ : [Q] の導出による帰納法で証明する。 <もしくは、さらに一般化して、" [x], [y], [z]を仮定して、[Q x y z] ならば [P x y z] を示す。[Q x y z]の導出による帰納法によって"...>
<各コンストラクタ [c] による値 [Q] について...>
- [Q] が [c] であることを示した最後のルールを仮定して、
<...ここで [a] の全ての型をコンストラクタの定義にある等式と
共に示し、型 [Q] を持つ [a] がIHであることをそれぞれ示す。>
ならば <...ここで再び [P] を示す> である。
<がんばって [P] を証明し、このケースを閉じる...>
- <他のケースも同様に...> []
_Example_
- _Theorem_ : [<=] という関係は推移的である -- すなわち、任意の
数値 [n], [m], [o] について、もし [n <= m] と [m <= o] が成り立つ
ならば [n <= o] である。
_Proof_ : [m <= o] についての帰納法で証明する。
- [m <= o] が [le_n] であることを示した最後のルールであると仮定しましょう。
それにより [m = o] であることとその結果が直接導かれます。
- [m <= o] が [le_S] であることを示した最後のルールであると仮定しましょう。
それにより [m <= o'] を満たす [o'] について [o = S o'] が成り立つ。
帰納法の仮定法より [n <= o'] である。
従って[le_S] より [n <= o] である。 [] *)
*)
(* ##################################################### *)
(* * Optional Material *)
(** * 選択課題 *)
(* The remainder of this chapter offers some additional details on
how induction works in Coq, the process of building proof
trees, and the "trusted computing base" that underlies
Coq proofs. It can safely be skimmed on a first reading. (We
recommend skimming rather than skipping over it outright: it
answers some questions that occur to many Coq users at some point,
so it is useful to have a rough idea of what's here.) *)
(** この項では、Coq において帰納法がどのように機能しているか、もう少し詳しく示していきたいと思います。
最初にこの項を読むときは、全体を読み流す感じでもかまいません（完全に
読み飛ばすのではなく、概要だけでも眺めてください。ここに書いてあることは、
多くの Coq ユーザーにとって、概要だけでも頭に入れておくことで、いつか直面する問題に
対する回答となりえるものです。） *)
(* ##################################################### *)
(* ** Induction Principles in [Prop] *)
(** ** [Prop] における帰納法の原理 *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [gorgeous]
are a tiny bit more complicated. As with all induction
principles, we want to use the induction principle on [gorgeous]
to prove things by inductively considering the possible shapes
that something in [gorgeous] can have -- either it is evidence
that [0] is gorgeous, or it is evidence that, for some [n], [3+n]
is gorgeous, or it is evidence that, for some [n], [5+n] is
gorgeous and it includes evidence that [n] itself is. Intuitively
speaking, however, what we want to prove are not statements about
_evidence_ but statements about _numbers_. So we want an
induction principle that lets us prove properties of numbers by
induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [gorgeous]...
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+m)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+m).
...to give rise to an induction principle that looks like this...
gorgeous_ind_max :
forall P : (forall n : nat, gorgeous n -> Prop),
P O g_0 ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (3+m) (g_plus3 m e) ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (5+m) (g_plus5 m e) ->
forall (n : nat) (e : gorgeous n), P n e
... because:
- Since [gorgeous] is indexed by a number [n] (every [gorgeous]
object [e] is a piece of evidence that some particular number
[n] is gorgeous), the proposition [P] is parameterized by both
[n] and [e] -- that is, the induction principle can be used to
prove assertions involving both a gorgeous number and the
evidence that it is gorgeous.
- Since there are three ways of giving evidence of gorgeousness
([gorgeous] has three constructors), applying the induction
principle generates three subgoals:
- We must prove that [P] holds for [O] and [b_0].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [3+m] and [g_plus3 n e].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [5+m] and [g_plus5 n e].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ gorgeous numbers [n] and
evidence [e] of their gorgeousness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
gorgeousness, while all we really care about is proving
properties of _numbers_ that are gorgeous -- we are interested in
assertions about numbers, not about evidence. It would therefore
be more convenient to have an induction principle for proving
propositions [P] that are parameterized just by [n] and whose
conclusion establishes [P] for all gorgeous numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat, gorgeous n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [gorgeous]: *)
(** 最初のほうで、我々は帰納的に定義された「集合」に対して、Coqが生成する
帰納法の原理をつぶさに見てきました。[gorgeous] のように、帰納的に定義された
「命題」の帰納法の原理は、やや複雑でした。これらに共通して言えることですが、
これらを [gorgeous] の証明に使おうとする際、帰納的な発想のもとで [gorgeous] が持ちうる
ものの中から使えそうな形になっているものを探します。それは [0] がgorgeousであることの
根拠であったり、ある [n] について [n+3] はgorgeousであるという根拠（もちろん、
これには [n] 自身がgorgeousであるということの根拠も含まれていなければ
なりませんが）だったりするでしょう。しかしながら直観的な言い方をすると、
我々が証明したいものは根拠についての事柄ではなく、数値についての事柄です。
つまり、我々は根拠をベースに数値の属性を証明できるような帰納法の原理を
必要としているわけです。
例えば、ここまでにお話ししたように、[gorgeous] の帰納的な定義は、
こんな感じで...
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+m)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+m).
... ここから生成される帰納法の原理はこんな風になります ...
gorgeous_ind_max :
forall P : (forall n : nat, gorgeous n -> Prop),
P O g_0 ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (3+m) (g_plus3 m e) ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (5+m) (g_plus5 m e) ->
forall (n : nat) (e : gorgeous n), P n e
... なぜなら：
- [gorgeous] は数値 [n] でインデックスされている（ [gorgeous] に属するオブジェクト [e] は、いずれも特定の数 [n] がgorgeousであることの根拠となっている）ため、この命題 [P] は [n] と[e] の両方でパラメータ化されている。-- つまり、この帰納法の原理は一つのgorgeousな数と、それがgorgeousであることの根拠が揃っているような主張の証明に使われる。
- gorgeousであることに根拠を与える方法は3つある（ [gorgeous] のコンストラクタは3つある）ので、帰納法の原理を適用すると、3つのゴールが生成されます。:
- [P] が [O] と [g_0] で成り立つことを証明する必要がある。
- [m] がgorgeousで [e] がそのgorgeous性であることの根拠であるとき、もし [P] が [m] と [e] のもとで成り立つなら、
[3+m] と [g_plus3 m e] のもとで成り立つことを証明する必要がある。
- [m] がgorgeousで [e] がそのgorgeous性であることの根拠であるとき、もし [P] が [m] と [e] のもとで成り立つなら、
[5+m] と [g_plus5 m e] のもとで成り立つことを証明する必要がある。
- もしこれらのサブゴールが証明できれば、この帰納法の原理によって [P] が全ての gorgeous である[n] とそのgorgeous性の根拠 [e] のもとで真であることが示される。
しかしこれは、私たちが求めたり必要としているものより少しだけ柔軟にできていて、
gorgeous性の根拠の断片を属性として含むような論理的主張を証明する方法を与えてくれます。
我々の興味の対象は「数値の属性がgorgeousである」ことの証明なのですから、その興味の対象も数値に関する主張であって、
根拠に対するものではないはずです。これにより、単に [n] だけでパラメータ化されていて、
[P] がすべてのgorgeousな数 [n] で成り立つことを示せるような命題 [P] を証明する際に帰納法の原理を得ることがより楽になります。
forall P : nat -> Prop,
... ->
forall n : nat, gorgeous n -> P n
このような理由で、Coqは実際には [gorgeous] のために次のような帰納法の原理を生成します。: *)
Check gorgeous_ind.
(* ===> gorgeous_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, gorgeous n -> P n -> P (3 + n)) ->
(forall n : nat, gorgeous n -> P n -> P (5 + n)) ->
forall n : nat, gorgeous n -> P n *)
(* In particular, Coq has dropped the evidence term [e] as a
parameter of the the proposition [P], and consequently has
rewritten the assumption [forall (n : nat) (e: gorgeous n), ...]
to be [forall (n : nat), gorgeous n -> ...]; i.e., we no longer
require explicit evidence of the provability of [gorgeous n]. *)
(** とりわけ、Coqはパラメータとしての命題[P]の根拠となる項 [e]を削除し、
その結果として、[forall (n:nat)(e:gorgeos n),...]型の仮定を[forall (n : nat), gorgeous n -> ...]という型に書きかえてしまいます。
[gorgeous n]を証明する明確な根拠をもはや必要としないからです *)
(* In English, [gorgeous_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is gorgeous, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [3+n],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [5+n]. *)
(** [gorgeous_ind]を自然言語で書き直すと、
- P が自然数の属性である（つまり、P が全ての n についての命題である）と仮定し、P n が、[n]がgorgeousの場合常に成り立つことを示す。
これは、以下を示せば十分である。:
- [P]は0のときに成立つ。
- 全ての[n]について、[n]がgorgeousであり、[P]が[n]のときに成立つならば、[P]は[3+n]の場合にも成り立つ。
- 全ての[n]について、[n]がgorgeousであり、[P]が[n]のときに成立つならば、[P]は[5+n]の場合にも成り立つ。
*)
(* As expected, we can apply [gorgeous_ind] directly instead of using [induction]. *)
(** [induction]タクティックを使用するかわりに、直接[gorgeous_ind]を使用して、期待通り動作するか見てみましょう *)
Theorem gorgeous__beautiful' : forall n, gorgeous n -> beautiful n.
Proof.
intros.
apply gorgeous_ind.
Case "g_0".
apply b_0.
Case "g_plus3".
intros.
apply b_sum. apply b_3.
apply H1.
Case "g_plus5".
intros.
apply b_sum. apply b_5.
apply H1.
apply H.
Qed.
(* The precise form of an Inductive definition can affect the
induction principle Coq generates.
For example, in [Logic], we have defined [<=] as: *)
(** 帰納的な定義の正確な形はCoqが生成する帰納法の原理に影響を与えます。
例えば、[Logic]において、 我々は[<=]を以下のように定義しました。 *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(* This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
(** これはこれで <= という関係の妥当なな定義だと言えます。
しかし少し観察してみると 定義の左側のに現れる n は全て同じだということがわかります。
ということは、 個々のコンストラクタにではなく定義全体に全称量化子を使うことが できるということです。
*)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(* The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
(** 少し対称性が損なわれたようにも見えますが、この二番目の定義の方がいいのです。
なぜでしょうか？それは、こちらのほうがよりシンプルな帰納法の原理を
生成してくれるからです（ [eq] の二番目の定義にも同じことが言えます）。
*)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(* By contrast, the induction principle that Coq calculates for the
first definition has a lot of extra quantifiers, which makes it
messier to work with when proving things by induction. Here is
the induction principle for the first [le]: *)
(** 一方、最初の定義に Coq が生成する帰納法の原理には、もっと多くの量化子が
含まれることになります。これでは、帰納法を使った証明がごちゃごちゃしてしまいます。
これが [le] の最初の定義で生成された帰納法の原理です。
*)
(* le_ind :
forall P : nat -> nat -> Prop,
(forall n : nat, P n n) ->
(forall n m : nat, le n m -> P n m -> P n (S m)) ->
forall n n0 : nat, le n n0 -> P n n0 *)
(* ##################################################### *)
(** * Additional Exercises *)
(* **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** **** 練習問題: ★★, optional (foo_ind_principle) *)
(* Suppose we make the following inductive definition:
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
Fill in the blanks to complete the induction principle that will be
generated by Coq.
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
*)
(** 次のような、帰納的な定義をしたとします：
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
次の空欄を埋め、この定義のために Coq が生成する帰納法の原理を完成させなさい。
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, __________________________________) ->
(forall y : Y, __________________________________) ->
(________________________________________________) ->
________________________________________________
*)
(** [] *)
(* **** Exercise: 2 stars, optional (bar_ind_principle) *)
(** **** 練習問題: ★★, optional (bar_ind_principle) *)
(* Consider the following induction principle:
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
Write out the corresponding inductive set definition.
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
*)
(** 次に挙げた帰納法の原理について考えてみましょう：
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
これに対応する帰納的な集合の定義を書きなさい。
Inductive bar : Set :=
| bar1 : ________________________________________
| bar2 : ________________________________________
| bar3 : ________________________________________.
*)
(** [] *)
(* **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** **** 練習問題: ★★, optional (no_longer_than_ind) *)
(* Given the following inductively defined proposition:
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
write the induction principle generated by Coq.
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
*)
(** 次のような帰納的に定義された命題が与えられたとします：
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
この定義のために Coq が生成する帰納法の原理を書きなさい。
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, ____________________) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> ____________________ ->
_____________________________ ->
forall (l : list X) (n : nat), no_longer_than X l n ->
____________________
*)
(** [] *)
(* ##################################################### *)
(* ** Induction Principles for other Logical Propositions *)
(**他の論理命題に対する帰納法の原理 *)
(* Similarly, in [Logic] we have defined [eq] as: *)
(** 同様に、[Logic]において、[eq]を以下のように定義しました *)
(* Inductive eq (X:Type) : X -> X -> Prop :=
refl_equal : forall x, eq X x x. *)
(** In the Coq standard library, the definition of equality is
slightly different: *)
(** Coqの標準ライブラリでは、同値性の定義は少し違っています。 *)
Inductive eq' (X:Type) (x:X) : X -> Prop :=
refl_equal' : eq' X x x.
(* The advantage of this definition is that the induction
principle that Coq derives for it is precisely the familiar
principle of _Leibniz equality_: what we mean when we say "[x] and
[y] are equal" is that every property on [P] that is true of [x]
is also true of [y]. *)
(** この定義の優れたところは、Coqが生成する帰納法の原理が正確に
「ライプニッツの同値関係（ _Leibniz equality_ ）」と親和している点です。
それはつまり、「[x] と [y] が等しいということは、 任意の命題 [P] が
[x] でtrueとなるならば [y] でもtrueとなる」ということです。
*)
Check eq'_ind.
(* ===>
forall (X : Type) (x : X) (P : X -> Prop),
P x -> forall y : X, x =' y -> P y
===> (i.e., after a little reorganization)
forall (X : Type) (x : X) forall y : X,
x =' y ->
forall P : X -> Prop, P x -> P y *)
(* The induction principles for conjunction and disjunction are a
good illustration of Coq's way of generating simplified induction
principles for [Inductive]ly defined propositions, which we
discussed above. You try first: *)
(** 論理積（連言）や論理和（連言）に関する帰納法の原理は、帰納的に定義された
命題に対して簡約された帰納法の原理を Coq が生成する方法をとてもよく示しています。
これについては最後の章でお話しします。とりあえずこれに挑戦してみてください。
*)
(** **** Exercise: 1 star, optional (and_ind_principle) *)
(** **** 練習問題: ★ (and_ind_principle) *)
(** See if you can predict the induction principle for conjunction. *)
(** 連言（ conjunction ）についての帰納法の原理を予想して、確認しなさい。 *)
(* Check and_ind. *)
(** [] *)
(** **** Exercise: 1 star, optional (or_ind_principle) *)
(** **** 練習問題: ★ (or_ind_principle) *)
(** See if you can predict the induction principle for disjunction. *)
(** 選言（ disjunction ）についての帰納法の原理を予想して、確認しなさい。 *)
(* Check or_ind. *)
(** [] *)
Check and_ind.
(** From the inductive definition of the proposition [and P Q]
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
we might expect Coq to generate this induction principle
and_ind_max :
forall (P Q : Prop) (P0 : P /\ Q -> Prop),
(forall (a : P) (b : Q), P0 (conj P Q a b)) ->
forall a : P /\ Q, P0 a
but actually it generates this simpler and more useful one:
and_ind :
forall P Q P0 : Prop,
(P -> Q -> P0) ->
P /\ Q -> P0
In the same way, when given the inductive definition of [or P Q]
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
instead of the "maximal induction principle"
or_ind_max :
forall (P Q : Prop) (P0 : P \/ Q -> Prop),
(forall a : P, P0 (or_introl P Q a)) ->
(forall b : Q, P0 (or_intror P Q b)) ->
forall o : P \/ Q, P0 o
what Coq actually generates is this:
or_ind :
forall P Q P0 : Prop,
(P -> P0) ->
(Q -> P0) ->
P \/ Q -> P0
]]
*)
(** 命題 [and P Q] の帰納的な定義から、
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
我々は Coq がこのような帰納法の原理を生成することを期待します。
and_ind_max :
forall (P Q : Prop) (P0 : P /\ Q -> Prop),
(forall (a : P) (b : Q), P0 (conj P Q a b)) ->
forall a : P /\ Q, P0 a
しかし実際には、もっとシンプルで使いやすいものが生成されます。
and_ind :
forall P Q P0 : Prop,
(P -> Q -> P0) ->
P /\ Q -> P0
同様に、 [or P Q] の帰納的な定義が与えられると、
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
以下のような、原則通りの帰納法の原理を制する代わりに、
or_ind_max :
forall (P Q : Prop) (P0 : P \/ Q -> Prop),
(forall a : P, P0 (or_introl P Q a)) ->
(forall b : Q, P0 (or_intror P Q b)) ->
forall o : P \/ Q, P0 o
Coq はこのような帰納法の原理が生成されます。
or_ind :
forall P Q P0 : Prop,
(P -> P0) ->
(Q -> P0) ->
P \/ Q -> P0
*)
(** **** Exercise: 1 star, optional (False_ind_principle) *)
(** **** 練習問題: ★ (False_ind_principle) *)
(* Can you predict the induction principle for falsehood? *)
(** 「偽」に関する帰納法の原理を何か思いつくことができますか？ *)
(* Muri *)
(* Check False_ind. *)
(** [] *)
(** Here's the induction principle that Coq generates for existentials: *)
Check ex_ind.
(* ===> forall (X:Type) (P: X->Prop) (Q: Prop),
(forall witness:X, P witness -> Q) ->
ex X P ->
Q *)
(** This induction principle can be understood as follows: If we have
a function [f] that can construct evidence for [Q] given _any_
witness of type [X] together with evidence that this witness has
property [P], then from a proof of [ex X P] we can extract the
witness and evidence that must have been supplied to the
constructor, give these to [f], and thus obtain a proof of [Q]. *)
(* ######################################################### *)
(* ** Explicit Proof Objects for Induction *)
(** ** 帰納法のための明示的な証明オブジェクト *)
(* Although tactic-based proofs are normally much easier to
work with, the ability to write a proof term directly is sometimes
very handy, particularly when we want Coq to do something slightly
non-standard. *)
(** タクティックを使った証明は一般に簡単に済むことが多いですが、証明式を
直接書いてしまえるなら、そうしたほうが簡単な場合もあります。特に、
Coq にちょっとだけ変わった方法をとらせたい時はそうです。
*)
(** Recall the induction principle on naturals that Coq generates for
us automatically from the Inductive declation for [nat]. *)
(** [nat] の帰納的な定義からCoqが自動的に生成した自然数に関する帰納法の
原理を思い出してください。
*)
Check nat_ind.
(* ===>
nat_ind : forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** There's nothing magic about this induction lemma: it's just
another Coq lemma that requires a proof. Coq generates the proof
automatically too... *)
(** この帰納法についての補題には何のタネも仕掛けもありません。
これは単に、証明を必要とする Coq の別の補題です。Coq はこれにも
自動的に証明を生成してくれます。
*)
Print nat_ind.
Print nat_rect.
(* ===> (after some manual inlining and tidying)
nat_ind =
fun (P : nat -> Prop)
(f : P 0)
(f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n with
| 0 => f
| S n0 => f0 n0 (F n0)
end.
*)
(* We can read this as follows:
Suppose we have evidence [f] that [P] holds on 0, and
evidence [f0] that [forall n:nat, P n -> P (S n)].
Then we can prove that [P] holds of an arbitrary nat [n] via
a recursive function [F] (here defined using the expression
form [Fix] rather than by a top-level [Fixpoint]
declaration). [F] pattern matches on [n]:
- If it finds 0, [F] uses [f] to show that [P n] holds.
- If it finds [S n0], [F] applies itself recursively on [n0]
to obtain evidence that [P n0] holds; then it applies [f0]
on that evidence to show that [P (S n)] holds.
[F] is just an ordinary recursive function that happens to
operate on evidence in [Prop] rather than on terms in [Set].
*)
(** これは次のように読めます :
[P] が 0 の場合に成り立つという根拠 [f] と [forall n:nat, P n -> P (S n)]
の根拠 [f0] があると仮定します。
そうすると、 [P] が任意の自然数 [n] で成り立つことを、再帰的に定義された
関数 [F] （ここでは、トップレベルで使われる [Fixpoint] ではなく、
[Fix] を使って定義されています）を使って示すことができます。
[F] は [n] について以下のようなパターンマッチをしています：
- もし 0 ならば、 [F] は [f] を [P n] が成り立つことの根拠とする。
- もし [S n0] ならば、[F] は [P n0] が成り立つ根拠を手に入れるために、[n0] を持ってそれ自身を再帰呼び出しする。そうして得た根拠が [f0] に適用され [P (S n)] が成り立つことが示される。
[F] は、集合 [Set] ではなく、根拠 [Prop] を操作することになっただけの
普通の再帰的な関数です。
*)
(** We can adapt this approach to proving [nat_ind] to help prove
_non-standard_ induction principles too. Recall our desire to
prove that
[forall n : nat, even n -> ev n].
Attempts to do this by standard induction on [n] fail, because the
induction principle only lets us proceed when we can prove that
[even n -> even (S n)] -- which is of course never provable. What
we did in [Logic] was a bit of a hack:
[Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n))].
We can make a much better proof by defining and proving a
non-standard induction principle that goes "by twos":
*)
(** 我々は、 [nat_ind] の証明に使用したこのようなアプローチを、
標準的でない（ _non-standard_ ）帰納法の原理を証明する際にも使うことができます。
以前このような証明をしようとしていたことを思い出してください。
[forall n : nat, even n -> ev n].
これを、通常の [n] に対する帰納法でやろうとしても失敗してしまいます。
なぜなら、この帰納法の原理は [even n -> even (S n)] を証明しようとする
時にしかうまく機能してくれないからです。これはもちろん証明不能な命題です。
このような場合、前の章ではちょっとした小技を使いました。
[Theorem even_ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n))].
これについては、標準的でない帰納法の原理（二つずつ、となるような）を
定義して証明することで、より良い証明が得られます。
*)
Definition nat_ind2 :
forall (P : nat -> Prop),
P 0 ->
P 1 ->
(forall n : nat, P n -> P (S(S n))) ->
forall n : nat , P n :=
fun P => fun P0 => fun P1 => fun PSS =>
fix f (n:nat) := match n with
0 => P0
| 1 => P1
| S (S n') => PSS n' (f n')
end.
(* Once you get the hang of it, it is entirely straightforward to
give an explicit proof term for induction principles like this.
Proving this as a lemma using tactics is much less intuitive (try
it!).
The [induction ... using] tactic variant gives a convenient way to
specify a non-standard induction principle like this. *)
(** 一度これを手にいれてしまえば、今回のような帰納法の原理を使った
証明全般にこれを使うことができます。これを補題としてタクティックを
使うと、さらに直観に反したものになります（試してみてください！）。
[induction ... using] タクティックは、このように標準的でない
帰納法の原理を取る際に便利です。
*)
Lemma even__ev' : forall n, even n -> ev n.
Proof.
intros.
induction n as [ | |n'] using nat_ind2.
Case "even 0".
apply ev_0.
Case "even 1".
inversion H.
Case "even (S(S n'))".
apply ev_SS.
apply IHn'. unfold even. unfold even in H. simpl in H. apply H.
Qed.
(* ######################################################### *)
(* ** The Coq Trusted Computing Base *)
(** ** Coq の信頼できるコンピューティング基盤 *)
(** One issue that arises with any automated proof assistant is "why
trust it?": what if there is a bug in the implementation that
renders all its reasoning suspect?
While it is impossible to allay such concerns completely, the fact
that Coq is based on the Curry-Howard correspondence gives it a
strong foundation. Because propositions are just types and proofs
are just terms, checking that an alleged proof of a proposition is
valid just amounts to _type-checking_ the term. Type checkers are
relatively small and straightforward programs, so the "trusted
computing base" for Coq -- the part of the code that we have to
believe is operating correctly -- is small too.
What must a typechecker do? Its primary job is to make sure that
in each function application the expected and actual argument
types match, that the arms of a [match] expression are constructor
patterns belonging to the inductive type being matched over and
all arms of the [match] return the same type, and so on.
There are a few additional wrinkles:
- Since Coq types can themselves be expressions, the checker must
normalize these (by using the computation rules) before
comparing them.
- The checker must make sure that [match] expressions are
_exhaustive_. That is, there must be an arm for every possible
constructor. To see why, consider the following alleged proof
object:
Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
All the types here match correctly, but the [match] only
considers one of the possible constructors for [or]. Coq's
exhaustiveness check will reject this definition.
- The checker must make sure that each [fix] expression
terminates. It does this using a syntactic check to make sure
that each recursive call is on a subexpression of the original
argument. To see why this is essential, consider this alleged
proof:
Definition nat_false : forall (n:nat), False :=
fix f (n:nat) : False := f n.
Again, this is perfectly well-typed, but (fortunately) Coq will
reject it. *)
(** ここで一つの疑問が起こってきます。自動化された証明支援系が
「なぜ信用できるのか？」という疑問です。つまり、これらの実装に
バグがあるなら、その証明にも疑いを持たざるを得ません。
このような考えを完全に排除することはできませんが、Coq カリー・ハワード同型対応を
その基礎に置いているという事実は Coq 自身の強い基礎ともなっています。
なぜなら、命題は型であり、証明は項であり、まだ証明されていない命題が
妥当かどうかを調べることは、項の型をチェックする（ _type-checking_ ）ことに
等しいからです。型チェッカは十分に信頼できるほど小さく率直に書かれた
プログラムであり、それこそが Coq の「信頼できるコンピューティング基盤」と
なっています。その「信頼性が必要となる一部のコード」は正確に動き、また
十分に小さいのです。
型チェッカの役割とはなんでしょうか？その一番の役割は、各々の関数の適用で、
予想された型と実際の型が一致していることを確認することです。つまり、
[match] の各枝の式が、帰納的な型のコンストラクタと対応しており、すべてが
同じ型を返すようになっているか、などです。
しかしこれには若干の弱点もあります。
- Coq の型はそれ自身が式となっているため、その型チェッカがそれらを比較する前際に、変換ルールに基づいて正規化しなければならない。
- 型チェッカは、 [match] の式が「尽くされている（_exhaustive_ ）ことを確認しなければならない。つまり、その型ににあるコンストラクタに対応する枝をすべて持っていなければならい。その理由は、次に提示された証明オブジェクトについて考えればわかるはずです。
Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
この定義では、型は正しく一致していますが、 [match] が [or] の一方の
コンストラクタのことしか考えていません。Coq は、このようなケースがないか
をチェックし、このような定義を拒絶します。
- 型チェッカは、各 [fix] の式が終了することを確認しなければならない。これは文法レベルで「各々の再帰呼び出しに元々の引数にわたってきた式の部分式が渡されていること」をチェックをすることで実現されている。この理由の本質的なところを理解するために次の証明について考えてください。
Definition nat_false : forall (n:nat), False :=
fix f (n:nat) : False := f n.
やはり、これも型について何も問題はありませんが、残念なことに Coq はこの定義を
拒絶します。 *)
(** Note that the soundness of Coq depends only on the correctness of
this typechecking engine, not on the tactic machinery. If there
is a bug in a tactic implementation (and this certainly does
happen!), that tactic might construct an invalid proof term. But
when you type [Qed], Coq checks the term for validity from
scratch. Only lemmas whose proofs pass the type-checker can be
used in further proof developments. *)
(** Coq の「確実さ」は、タクティックの仕組みではなく、型チェックの仕組みに
よってもたらされていることに注目してください。もしタクティックの実装に
バグがあれば（実際にこれはあったことです！）、タクティックは間違った証明
を構築してしまうでしょう。しかし、[Qed] を入力した時点で、Coq はその正しさを
１から検証しなおします。型チェッカを通過した補題のみ、その後の証明の
構築に使える定理となることができるのです。
*)
(* $Date: 2014-06-05 07:22:21 -0400 (Thu, 05 Jun 2014) $ *)
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:54:25 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.v
// Design : system_ov7670_vga_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_vga_0_0,ov7670_vga,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_vga,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_vga_0_0
(pclk,
data,
rgb);
input pclk;
input [7:0]data;
output [15:0]rgb;
wire [7:0]data;
wire pclk;
wire [15:0]rgb;
system_ov7670_vga_0_0_ov7670_vga U0
(.data(data),
.pclk(pclk),
.rgb(rgb));
endmodule
(* ORIG_REF_NAME = "ov7670_vga" *)
module system_ov7670_vga_0_0_ov7670_vga
(rgb,
pclk,
data);
output [15:0]rgb;
input pclk;
input [7:0]data;
wire cycle;
wire [7:0]data;
wire p_0_in0;
wire pclk;
wire [15:0]rgb;
FDRE #(
.INIT(1'b0))
cycle_reg
(.C(pclk),
.CE(1'b1),
.D(p_0_in0),
.Q(cycle),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\rgb[15]_i_1
(.I0(cycle),
.O(p_0_in0));
FDRE \rgb_reg[0]
(.C(pclk),
.CE(cycle),
.D(data[0]),
.Q(rgb[0]),
.R(1'b0));
FDRE \rgb_reg[10]
(.C(pclk),
.CE(p_0_in0),
.D(data[2]),
.Q(rgb[10]),
.R(1'b0));
FDRE \rgb_reg[11]
(.C(pclk),
.CE(p_0_in0),
.D(data[3]),
.Q(rgb[11]),
.R(1'b0));
FDRE \rgb_reg[12]
(.C(pclk),
.CE(p_0_in0),
.D(data[4]),
.Q(rgb[12]),
.R(1'b0));
FDRE \rgb_reg[13]
(.C(pclk),
.CE(p_0_in0),
.D(data[5]),
.Q(rgb[13]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(pclk),
.CE(p_0_in0),
.D(data[6]),
.Q(rgb[14]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(pclk),
.CE(p_0_in0),
.D(data[7]),
.Q(rgb[15]),
.R(1'b0));
FDRE \rgb_reg[1]
(.C(pclk),
.CE(cycle),
.D(data[1]),
.Q(rgb[1]),
.R(1'b0));
FDRE \rgb_reg[2]
(.C(pclk),
.CE(cycle),
.D(data[2]),
.Q(rgb[2]),
.R(1'b0));
FDRE \rgb_reg[3]
(.C(pclk),
.CE(cycle),
.D(data[3]),
.Q(rgb[3]),
.R(1'b0));
FDRE \rgb_reg[4]
(.C(pclk),
.CE(cycle),
.D(data[4]),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[5]
(.C(pclk),
.CE(cycle),
.D(data[5]),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[6]
(.C(pclk),
.CE(cycle),
.D(data[6]),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[7]
(.C(pclk),
.CE(cycle),
.D(data[7]),
.Q(rgb[7]),
.R(1'b0));
FDRE \rgb_reg[8]
(.C(pclk),
.CE(p_0_in0),
.D(data[0]),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[9]
(.C(pclk),
.CE(p_0_in0),
.D(data[1]),
.Q(rgb[9]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_fe1
//
// Generated
// by: lutscher
// on: Tue Jun 23 11:51:21 2009
// cmd: /home/lutscher/work/MIX/mix_1.pl rs_test.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author$
// $Id$
// $Date$
// $Log$
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.109 2008/04/01 12:48:34 wig Exp
//
// Generator: mix_1.pl Revision: 1.3 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_fe1
//
// No user `defines in this module
`define tie0_1_c 1'b0
module rs_fe1
//
// Generated Module rs_fe1_i
//
(
input wire clk_f20_i,
input wire res_f20_n_i,
input wire mreset_n_i,
input wire [2:0] mcmd_i,
input wire [13:0] maddr_i,
input wire [31:0] mdata_i,
input wire mrespaccept_i,
output wire scmdaccept_o,
output wire [1:0] sresp_o,
output wire [31:0] sdata_o,
output wire sinterrupt_o,
input wire clk_a_i,
input wire res_a_n_i,
output wire [2:0] cvbsdetect_par_o,
input wire [2:0] cvbsdetect_set_p_i,
output wire cvbsdetect_trg_p_o,
input wire [7:0] sha_r_test_par_i,
output wire sha_r_test_trg_p_o,
input wire usr_r_test_par_i,
input wire usr_r_test_trans_done_p_i,
output wire usr_r_test_rd_p_o,
input wire ycdetect_par_i,
output wire [3:0] mvstart_par_o,
output wire [3:0] mvstop_par_o,
input wire [1:0] usr_ali_par_i,
input wire usr_ali_trans_done_p_i,
output wire usr_ali_rd_p_o,
output wire [3:0] usr_rw_test_par_o,
input wire [3:0] usr_rw_test_in_par_i,
input wire usr_rw_test_trans_done_p_i,
output wire usr_rw_test_rd_p_o,
output wire usr_rw_test_wr_p_o,
output wire [31:0] sha_rw2_par_o,
output wire [15:0] wd_16_test_par_o,
output wire [7:0] wd_16_test2_par_o,
output wire wd_16_test2_trg_p_o,
input wire upd_rw_en_i,
input wire upd_rw_force_i,
input wire upd_rw_i,
input wire upd_r_en_i,
input wire upd_r_force_i,
input wire upd_r_i,
output wire [3:0] dgatel_par_o,
output wire [4:0] dgates_par_o,
output wire [2:0] dummy_fe_par_o,
output wire [3:0] sha_w_test_par_o,
output wire sha_w_test_trg_p_o,
output wire [3:0] usr_w_test_par_o,
input wire usr_w_test_trans_done_p_i,
output wire usr_w_test_wr_p_o,
output wire [3:0] w_test_par_o,
input wire [2:0] r_test_par_i,
output wire r_test_trg_p_o,
input wire upd_w_en_i,
input wire upd_w_force_i,
input wire upd_w_i
);
// Module parameters:
parameter P__MVSTOP = -1;
parameter P__CVBSDETECT = -1;
parameter P__WD_16_TEST2 = -1;
parameter P__WD_16_TEST = -1;
parameter P__SHA_RW2 = -1;
parameter P__MVSTART = -1;
parameter P__SHA_W_TEST = -1;
parameter P__W_TEST = -1;
parameter P__DUMMY_FE = -1;
parameter P__DGATES = -1;
parameter P__DGATEL = -1;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [13:0] addr;
wire clk_a; // __W_PORT_SIGNAL_MAP_REQ
wire clk_f20; // __W_PORT_SIGNAL_MAP_REQ
wire [2:0] cvbsdetect_par; // __W_PORT_SIGNAL_MAP_REQ
wire [2:0] cvbsdetect_set_p; // __W_PORT_SIGNAL_MAP_REQ
wire cvbsdetect_trg_p; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] dgatel_par; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] dgates_par; // __W_PORT_SIGNAL_MAP_REQ
wire [2:0] dummy_fe_par; // __W_PORT_SIGNAL_MAP_REQ
wire [13:0] maddr; // __W_PORT_SIGNAL_MAP_REQ
wire [2:0] mcmd; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] mdata; // __W_PORT_SIGNAL_MAP_REQ
wire mreset_n; // __W_PORT_SIGNAL_MAP_REQ
wire mrespaccept; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] mvstart_par; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] mvstop_par; // __W_PORT_SIGNAL_MAP_REQ
wire pre_dec;
wire pre_dec_err;
wire [2:0] r_test_par; // __W_PORT_SIGNAL_MAP_REQ
wire r_test_trg_p; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] rd_data;
wire [63:0] rd_data_vec;
wire rd_err;
wire [1:0] rd_err_vec;
wire rd_wr;
wire res_a_n; // __W_PORT_SIGNAL_MAP_REQ
wire res_f20_n; // __W_PORT_SIGNAL_MAP_REQ
wire scmdaccept; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] sdata; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sha_r_test_par; // __W_PORT_SIGNAL_MAP_REQ
wire sha_r_test_trg_p; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] sha_rw2_par; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sha_w_test_par; // __W_PORT_SIGNAL_MAP_REQ
wire sha_w_test_trg_p; // __W_PORT_SIGNAL_MAP_REQ
wire sinterrupt; // __W_PORT_SIGNAL_MAP_REQ
wire [1:0] sresp; // __W_PORT_SIGNAL_MAP_REQ
wire tie0_1;
wire trans_done;
wire [1:0] trans_done_vec;
wire trans_start;
wire trans_start_0;
wire trans_start_1;
wire upd_r; // __W_PORT_SIGNAL_MAP_REQ
wire upd_r_en; // __W_PORT_SIGNAL_MAP_REQ
wire upd_r_force; // __W_PORT_SIGNAL_MAP_REQ
wire upd_rw; // __W_PORT_SIGNAL_MAP_REQ
wire upd_rw_en; // __W_PORT_SIGNAL_MAP_REQ
wire upd_rw_force; // __W_PORT_SIGNAL_MAP_REQ
wire upd_w; // __W_PORT_SIGNAL_MAP_REQ
wire upd_w_en; // __W_PORT_SIGNAL_MAP_REQ
wire upd_w_force; // __W_PORT_SIGNAL_MAP_REQ
wire [1:0] usr_ali_par; // __W_PORT_SIGNAL_MAP_REQ
wire usr_ali_rd_p; // __W_PORT_SIGNAL_MAP_REQ
wire usr_ali_trans_done_p; // __W_PORT_SIGNAL_MAP_REQ
wire usr_r_test_par; // __W_PORT_SIGNAL_MAP_REQ
wire usr_r_test_rd_p; // __W_PORT_SIGNAL_MAP_REQ
wire usr_r_test_trans_done_p; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] usr_rw_test_in_par; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] usr_rw_test_par; // __W_PORT_SIGNAL_MAP_REQ
wire usr_rw_test_rd_p; // __W_PORT_SIGNAL_MAP_REQ
wire usr_rw_test_trans_done_p; // __W_PORT_SIGNAL_MAP_REQ
wire usr_rw_test_wr_p; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] usr_w_test_par; // __W_PORT_SIGNAL_MAP_REQ
wire usr_w_test_trans_done_p; // __W_PORT_SIGNAL_MAP_REQ
wire usr_w_test_wr_p; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] w_test_par; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] wd_16_test2_par; // __W_PORT_SIGNAL_MAP_REQ
wire wd_16_test2_trg_p; // __W_PORT_SIGNAL_MAP_REQ
wire [15:0] wd_16_test_par; // __W_PORT_SIGNAL_MAP_REQ
wire [31:0] wr_data;
wire ycdetect_par; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign clk_a = clk_a_i; // __I_I_BIT_PORT
assign clk_f20 = clk_f20_i; // __I_I_BIT_PORT
assign cvbsdetect_par_o = cvbsdetect_par; // __I_O_BUS_PORT
assign cvbsdetect_set_p = cvbsdetect_set_p_i; // __I_I_BUS_PORT
assign cvbsdetect_trg_p_o = cvbsdetect_trg_p; // __I_O_BIT_PORT
assign dgatel_par_o = dgatel_par; // __I_O_BUS_PORT
assign dgates_par_o = dgates_par; // __I_O_BUS_PORT
assign dummy_fe_par_o = dummy_fe_par; // __I_O_BUS_PORT
assign maddr = maddr_i; // __I_I_BUS_PORT
assign mcmd = mcmd_i; // __I_I_BUS_PORT
assign mdata = mdata_i; // __I_I_BUS_PORT
assign mreset_n = mreset_n_i; // __I_I_BIT_PORT
assign mrespaccept = mrespaccept_i; // __I_I_BIT_PORT
assign mvstart_par_o = mvstart_par; // __I_O_BUS_PORT
assign mvstop_par_o = mvstop_par; // __I_O_BUS_PORT
assign r_test_par = r_test_par_i; // __I_I_BUS_PORT
assign r_test_trg_p_o = r_test_trg_p; // __I_O_BIT_PORT
assign res_a_n = res_a_n_i; // __I_I_BIT_PORT
assign res_f20_n = res_f20_n_i; // __I_I_BIT_PORT
assign scmdaccept_o = scmdaccept; // __I_O_BIT_PORT
assign sdata_o = sdata; // __I_O_BUS_PORT
assign sha_r_test_par = sha_r_test_par_i; // __I_I_BUS_PORT
assign sha_r_test_trg_p_o = sha_r_test_trg_p; // __I_O_BIT_PORT
assign sha_rw2_par_o = sha_rw2_par; // __I_O_BUS_PORT
assign sha_w_test_par_o = sha_w_test_par; // __I_O_BUS_PORT
assign sha_w_test_trg_p_o = sha_w_test_trg_p; // __I_O_BIT_PORT
assign sinterrupt_o = sinterrupt; // __I_O_BIT_PORT
assign sresp_o = sresp; // __I_O_BUS_PORT
assign tie0_1 = `tie0_1_c;
assign upd_r = upd_r_i; // __I_I_BIT_PORT
assign upd_r_en = upd_r_en_i; // __I_I_BIT_PORT
assign upd_r_force = upd_r_force_i; // __I_I_BIT_PORT
assign upd_rw = upd_rw_i; // __I_I_BIT_PORT
assign upd_rw_en = upd_rw_en_i; // __I_I_BIT_PORT
assign upd_rw_force = upd_rw_force_i; // __I_I_BIT_PORT
assign upd_w = upd_w_i; // __I_I_BIT_PORT
assign upd_w_en = upd_w_en_i; // __I_I_BIT_PORT
assign upd_w_force = upd_w_force_i; // __I_I_BIT_PORT
assign usr_ali_par = usr_ali_par_i; // __I_I_BUS_PORT
assign usr_ali_rd_p_o = usr_ali_rd_p; // __I_O_BIT_PORT
assign usr_ali_trans_done_p = usr_ali_trans_done_p_i; // __I_I_BIT_PORT
assign usr_r_test_par = usr_r_test_par_i; // __I_I_BIT_PORT
assign usr_r_test_rd_p_o = usr_r_test_rd_p; // __I_O_BIT_PORT
assign usr_r_test_trans_done_p = usr_r_test_trans_done_p_i; // __I_I_BIT_PORT
assign usr_rw_test_in_par = usr_rw_test_in_par_i; // __I_I_BUS_PORT
assign usr_rw_test_par_o = usr_rw_test_par; // __I_O_BUS_PORT
assign usr_rw_test_rd_p_o = usr_rw_test_rd_p; // __I_O_BIT_PORT
assign usr_rw_test_trans_done_p = usr_rw_test_trans_done_p_i; // __I_I_BIT_PORT
assign usr_rw_test_wr_p_o = usr_rw_test_wr_p; // __I_O_BIT_PORT
assign usr_w_test_par_o = usr_w_test_par; // __I_O_BUS_PORT
assign usr_w_test_trans_done_p = usr_w_test_trans_done_p_i; // __I_I_BIT_PORT
assign usr_w_test_wr_p_o = usr_w_test_wr_p; // __I_O_BIT_PORT
assign w_test_par_o = w_test_par; // __I_O_BUS_PORT
assign wd_16_test2_par_o = wd_16_test2_par; // __I_O_BUS_PORT
assign wd_16_test2_trg_p_o = wd_16_test2_trg_p; // __I_O_BIT_PORT
assign wd_16_test_par_o = wd_16_test_par; // __I_O_BUS_PORT
assign ycdetect_par = ycdetect_par_i; // __I_I_BIT_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for rs_cfg_fe1_clk_a_i
rs_cfg_fe1_clk_a #(
.P__DGATEL(P__DGATEL),
.P__DGATES(P__DGATES),
.P__DUMMY_FE(P__DUMMY_FE),
.P__SHA_W_TEST(P__SHA_W_TEST),
.P__W_TEST(P__W_TEST),
.sync(1)
) rs_cfg_fe1_clk_a_i ( // Config register module for clock domain 'clk_a'
.addr_i(addr),
.clk_a_i(clk_a),
.dgatel_par_o(dgatel_par),
.dgates_par_o(dgates_par),
.dummy_fe_par_o(dummy_fe_par),
.r_test_par_i(r_test_par),
.r_test_trg_p_o(r_test_trg_p),
.rd_data_o(rd_data_vec[31:0]),
.rd_err_o(rd_err_vec[0]),
.rd_wr_i(rd_wr),
.res_a_n_i(res_a_n),
.sha_w_test_par_o(sha_w_test_par),
.sha_w_test_trg_p_o(sha_w_test_trg_p),
.trans_done_o(trans_done_vec[0]),
.trans_start_0_i(trans_start_0),
.upd_w_en_i(upd_w_en),
.upd_w_force_i(upd_w_force),
.upd_w_i(upd_w),
.usr_w_test_par_o(usr_w_test_par),
.usr_w_test_trans_done_p_i(usr_w_test_trans_done_p),
.usr_w_test_wr_p_o(usr_w_test_wr_p),
.w_test_par_o(w_test_par),
.wr_data_i(wr_data)
);
// End of Generated Instance Port Map for rs_cfg_fe1_clk_a_i
// Generated Instance Port Map for rs_cfg_fe1_i
rs_cfg_fe1 #(
.P__CVBSDETECT(P__CVBSDETECT),
.P__MVSTART(P__MVSTART),
.P__MVSTOP(P__MVSTOP),
.P__SHA_RW2(P__SHA_RW2),
.P__WD_16_TEST(P__WD_16_TEST),
.P__WD_16_TEST2(P__WD_16_TEST2),
.sync(0)
) rs_cfg_fe1_i ( // Config register module
.addr_i(addr),
.clk_f20_i(clk_f20),
.cvbsdetect_par_o(cvbsdetect_par),
.cvbsdetect_set_p_i(cvbsdetect_set_p),
.cvbsdetect_trg_p_o(cvbsdetect_trg_p),
.mvstart_par_o(mvstart_par),
.mvstop_par_o(mvstop_par),
.rd_data_o(rd_data_vec[63:32]),
.rd_err_o(rd_err_vec[1]),
.rd_wr_i(rd_wr),
.res_f20_n_i(res_f20_n),
.sha_r_test_par_i(sha_r_test_par),
.sha_r_test_trg_p_o(sha_r_test_trg_p),
.sha_rw2_par_o(sha_rw2_par),
.trans_done_o(trans_done_vec[1]),
.trans_start_1_i(trans_start_1),
.upd_r_en_i(upd_r_en),
.upd_r_force_i(upd_r_force),
.upd_r_i(upd_r),
.upd_rw_en_i(upd_rw_en),
.upd_rw_force_i(upd_rw_force),
.upd_rw_i(upd_rw),
.usr_ali_par_i(usr_ali_par),
.usr_ali_rd_p_o(usr_ali_rd_p),
.usr_ali_trans_done_p_i(usr_ali_trans_done_p),
.usr_r_test_par_i(usr_r_test_par),
.usr_r_test_rd_p_o(usr_r_test_rd_p),
.usr_r_test_trans_done_p_i(usr_r_test_trans_done_p),
.usr_rw_test_in_par_i(usr_rw_test_in_par),
.usr_rw_test_par_o(usr_rw_test_par),
.usr_rw_test_rd_p_o(usr_rw_test_rd_p),
.usr_rw_test_trans_done_p_i(usr_rw_test_trans_done_p),
.usr_rw_test_wr_p_o(usr_rw_test_wr_p),
.wd_16_test2_par_o(wd_16_test2_par),
.wd_16_test2_trg_p_o(wd_16_test2_trg_p),
.wd_16_test_par_o(wd_16_test_par),
.wr_data_i(wr_data),
.ycdetect_par_i(ycdetect_par)
);
// End of Generated Instance Port Map for rs_cfg_fe1_i
// Generated Instance Port Map for rs_fe1_pre_dec_i
rs_fe1_pre_dec #(
.N_DOMAINS(2)
) rs_fe1_pre_dec_i ( // Multi-clock-domain Pre-decoder
.addr_i(addr),
.pre_dec_err_o(pre_dec_err),
.pre_dec_o(pre_dec)
);
// End of Generated Instance Port Map for rs_fe1_pre_dec_i
// Generated Instance Port Map for u0_sci_target_0002_i
sci_target_0002 #(
.P_AWIDTH(14),
.P_DWIDTH(32),
.P_ECSADDR(44),
.P_MIX_SIG("M1"),
.def_ien_p(0),
.def_rerr_en_p(0),
.def_val_p(7),
.ecs_writable_p(1),
.has_ecs(1),
.sync(0)
) u0_sci_target_0002_i ( // OCP target module
.addr_o(addr),
.clk_i(clk_f20),
.maddr_i(maddr),
.mcmd_i(mcmd),
.mdata_i(mdata),
.mreset_n_i(mreset_n),
.mrespaccept_i(mrespaccept),
.rd_data_i(rd_data),
.rd_err_i(rd_err),
.rd_wr_o(rd_wr),
.reset_n_i(res_f20_n),
.scmdaccept_o(scmdaccept),
.sdata_o(sdata),
.sinterrupt_o(sinterrupt),
.sresp_o(sresp),
.trans_done_i(trans_done),
.trans_start_o(trans_start),
.wr_data_o(wr_data),
.wr_err_i(tie0_1)
);
// End of Generated Instance Port Map for u0_sci_target_0002_i
`ifdef ASSERT_ON
// synopsys translate_off
// Generated Instance Port Map for u1_sci_target_m_checker_i
sci_target_m_checker #(
.P_AWIDTH(14),
.P_DWIDTH(32),
.P_WRITERESP_ENABLE(0)
) u1_sci_target_m_checker_i ( // OCP master checker module
.clk_i(clk_f20),
.maddr_i(maddr),
.mcmd_i(mcmd),
.mdata_i(mdata),
.mreset_n_i(mreset_n),
.mrespaccept_i(mrespaccept),
.reset_n_i(res_f20_n),
.scmdaccept_i(scmdaccept),
.sresp_i(sresp)
);
// End of Generated Instance Port Map for u1_sci_target_m_checker_i
// synopsys translate_on
`endif
// Generated Instance Port Map for u2_rs_mcda_0002_i
rs_mcda_0002 #(
.N_DOMAINS(2),
.N_SYNCDOM(1),
.P_DWIDTH(32),
.P_MIX_SIG("M1"),
.P_PRDWIDTH(1)
) u2_rs_mcda_0002_i ( // Multi-clock-domain Adapter
.clk_ocp(clk_f20),
.mreset_n_i(mreset_n),
.pre_dec_err_i(pre_dec_err),
.pre_dec_i(pre_dec),
.rd_data_o(rd_data),
.rd_data_vec_i(rd_data_vec),
.rd_err_o(rd_err),
.rd_err_vec_i(rd_err_vec),
.rst_ocp_n_i(res_f20_n),
.trans_done_o(trans_done),
.trans_done_vec_i(trans_done_vec),
.trans_start_i(trans_start),
.trans_start_vec_o({ trans_start_1, trans_start_0 }) // __I_BIT_TO_BUSPORT (x2) // __I_COMBINE_SPLICES
);
// End of Generated Instance Port Map for u2_rs_mcda_0002_i
endmodule
//
// End of Generated Module rtl of rs_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
`include "Defintions.v"
`define LOOP1 8'd8
`define LOOP2 8'd5
module ROM
(
input wire[15:0] iAddress,
output reg [27:0] oInstruction
);
always @ ( iAddress )
begin
case (iAddress)
/*
0: oInstruction = { `NOP ,24'd4000 };
1: oInstruction = { `STO , `R7,16'b0001 };
2: oInstruction = { `STO ,`R3,16'h1 };
3: oInstruction = { `STO, `R4,16'd1000 };
4: oInstruction = { `STO, `R5,16'd0 }; //j
//LOOP2:
5: oInstruction = { `LED ,8'b0,`R7,8'b0 };
6: oInstruction = { `STO ,`R1,16'h0 };
7: oInstruction = { `STO ,`R2,16'd5000 };
//LOOP1:
8: oInstruction = { `ADD ,`R1,`R1,`R3 };
9: oInstruction = { `BLE ,`LOOP1,`R1,`R2 };
10: oInstruction = { `ADD ,`R5,`R5,`R3 };
11: oInstruction = { `BLE ,`LOOP2,`R5,`R4 };
12: oInstruction = { `NOP ,24'd4000 };
13: oInstruction = { `SUB ,`R7,`R7,`R3 };
14: oInstruction = { `JMP , 8'd2,16'b0 };
*/
0: oInstruction = { `NOP ,24'd4000 };
1: oInstruction = { `STO ,`R1, 16'h0002};
2: oInstruction = { `STO ,`R2, 16'h0008};
3: oInstruction = { `STO ,`R3, 16'h0003};
4: oInstruction = { `CALL, 8'd14, 16'd0};
5: oInstruction = { `STO ,`R0, 16'h0000};
6: oInstruction = { `CALL, 8'd9, 16'b0 };
7: oInstruction = { `NOP , 24'd4000 };
8: oInstruction = { `JMP , 8'd7, 16'b0 };
//Fun R2++
9: oInstruction = { `STO ,`R1, 16'h0001};
10: oInstruction = {`ADD ,`R2, `R2, `R1};
11: oInstruction = {`NOP ,24'd4000 };
12: oInstruction = {`RET ,24'd0 };
13: oInstruction = {`NOP ,24'd4000 };
//Fun R1 = R2*R3
14: oInstruction = {`STO ,`R1, 16'h0000};
15: oInstruction = {`STO ,`R4, 16'h0001};
16: oInstruction = {`ADD ,`R1, `R1, `R2};
17: oInstruction = {`SUB ,`R3, `R3, `R4};
18: oInstruction = {`BLE ,8'd16, `R4, `R3};
19: oInstruction = {`RET ,24'd0 };
default:
oInstruction = { `LED , 24'b10101010 }; //NOP
endcase
end
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Ethernet demultiplexer
*/
module eth_demux #
(
parameter M_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire [ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame outputs
*/
output wire [M_COUNT-1:0] m_eth_hdr_valid,
input wire [M_COUNT-1:0] m_eth_hdr_ready,
output wire [M_COUNT*48-1:0] m_eth_dest_mac,
output wire [M_COUNT*48-1:0] m_eth_src_mac,
output wire [M_COUNT*16-1:0] m_eth_type,
output wire [M_COUNT*DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire [M_COUNT-1:0] m_eth_payload_axis_tvalid,
input wire [M_COUNT-1:0] m_eth_payload_axis_tready,
output wire [M_COUNT-1:0] m_eth_payload_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_eth_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire drop,
input wire [$clog2(M_COUNT)-1:0] select
);
parameter CL_M_COUNT = $clog2(M_COUNT);
reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
reg drop_reg = 1'b0, drop_ctl, drop_next;
reg frame_reg = 1'b0, frame_ctl, frame_next;
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
reg [M_COUNT-1:0] m_eth_hdr_valid_reg = 0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg [M_COUNT-1:0] m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg && enable;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg && enable;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = {M_COUNT{m_eth_dest_mac_reg}};
assign m_eth_src_mac = {M_COUNT{m_eth_src_mac_reg}};
assign m_eth_type = {M_COUNT{m_eth_type_reg}};
integer i;
always @* begin
select_next = select_reg;
select_ctl = select_reg;
drop_next = drop_reg;
drop_ctl = drop_reg;
frame_next = frame_reg;
frame_ctl = frame_reg;
s_eth_hdr_ready_next = 1'b0;
s_eth_payload_axis_tready_next = 1'b0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg & ~m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (s_eth_payload_axis_tvalid && s_eth_payload_axis_tready) begin
// end of frame detection
if (s_eth_payload_axis_tlast) begin
frame_next = 1'b0;
drop_next = 1'b0;
end
end
if (!frame_reg && s_eth_hdr_valid && s_eth_hdr_ready) begin
// start of frame, grab select value
select_ctl = select;
drop_ctl = drop;
frame_ctl = 1'b1;
select_next = select_ctl;
drop_next = drop_ctl;
frame_next = frame_ctl;
s_eth_hdr_ready_next = 1'b0;
m_eth_hdr_valid_next = (!drop_ctl) << select_ctl;
m_eth_dest_mac_next = s_eth_dest_mac;
m_eth_src_mac_next = s_eth_src_mac;
m_eth_type_next = s_eth_type;
end
s_eth_hdr_ready_next = !frame_next && !m_eth_hdr_valid_next;
s_eth_payload_axis_tready_next = (m_eth_payload_axis_tready_int_early || drop_ctl) && frame_ctl;
m_eth_payload_axis_tdata_int = s_eth_payload_axis_tdata;
m_eth_payload_axis_tkeep_int = s_eth_payload_axis_tkeep;
m_eth_payload_axis_tvalid_int = (s_eth_payload_axis_tvalid && s_eth_payload_axis_tready && !drop_ctl) << select_ctl;
m_eth_payload_axis_tlast_int = s_eth_payload_axis_tlast;
m_eth_payload_axis_tid_int = s_eth_payload_axis_tid;
m_eth_payload_axis_tdest_int = s_eth_payload_axis_tdest;
m_eth_payload_axis_tuser_int = s_eth_payload_axis_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 2'd0;
drop_reg <= 1'b0;
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= 1'b0;
s_eth_payload_axis_tready_reg <= 1'b0;
m_eth_hdr_valid_reg <= 0;
end else begin
select_reg <= select_next;
drop_reg <= drop_next;
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_eth_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] temp_m_eth_payload_axis_tvalid_reg = {M_COUNT{1'b0}}, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_eth_payload_axis_temp_to_output;
assign m_eth_payload_axis_tdata = {M_COUNT{m_eth_payload_axis_tdata_reg}};
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? {M_COUNT{m_eth_payload_axis_tkeep_reg}} : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = {M_COUNT{m_eth_payload_axis_tlast_reg}};
assign m_eth_payload_axis_tid = ID_ENABLE ? {M_COUNT{m_eth_payload_axis_tid_reg}} : {M_COUNT*ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? {M_COUNT{m_eth_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? {M_COUNT{m_eth_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if ((m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || !m_eth_payload_axis_tvalid) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_eth_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_eth_payload_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
`resetall
|
/***********************************************************
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: byte_lane.v,v 1.8.4.1 2011/01/08 11:34:37 karthip Exp $
// $Author: karthip $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable single 10 or 12 bit byte lane.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module byte_lane #(
// these are used to scale the index into phaser,calib,scan,mc vectors
// to access fields used in this instance
parameter ABCD = "A", // A,B,C, or D
parameter PO_DATA_CTL = "FALSE",
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b0000_0000_0000,
parameter DIFFERENTIAL_DQS = "TRUE",
parameter GENERATE_DDR_CK = "B",
//OUT_FIFO
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_ARRAY_MODE = "UNDECLARED",
parameter OF_OUTPUT_DISABLE = "TRUE",
parameter OF_SYNCHRONOUS_MODE = "TRUE",
//IN_FIFO
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_ARRAY_MODE = "UNDECLARED",
parameter IF_SYNCHRONOUS_MODE = "TRUE",
//PHASER_IN
parameter PI_BURST_MODE = "TRUE",
parameter PI_CLKOUT_DIV = 2,
parameter PI_FREQ_REF_DIV = "NONE",
parameter PI_FINE_DELAY = 1,
parameter PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter PI_SYNC_IN_DIV_RST = "FALSE",
//PHASER_OUT
parameter PO_CLKOUT_DIV = (PO_DATA_CTL == "FALSE") ? 4 : 2,
parameter PO_FINE_DELAY = 0,
parameter PO_COARSE_DELAY = 0,
parameter PO_OCLK_DELAY = 0,
parameter PO_OCLKDELAY_INV = "TRUE",
// parameter PO_OCLKDELAY_INV = "FALSE",
parameter PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PO_SYNC_IN_DIV_RST = "FALSE",
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
// local constants, do not pass in
parameter BUS_WIDTH = 12,
parameter MSB_BURST_PEND_PO = 3,
parameter MSB_BURST_PEND_PI = 7,
parameter MSB_RANK_SEL_I = MSB_BURST_PEND_PI+ 8,
parameter MSB_RANK_SEL_O = MSB_RANK_SEL_I + 8,
parameter MSB_DIV_RST = MSB_RANK_SEL_O + 1,
parameter MSB_PHASE_SELECT = MSB_DIV_RST + 1,
parameter MSB_BURST_PI = MSB_PHASE_SELECT + 4,
parameter PHASER_CTL_BUS_WIDTH = MSB_BURST_PI + 1
)(
input rst,
input phy_clk,
input freq_refclk,
input mem_refclk,
input sync_pulse,
inout [BUS_WIDTH-1:0] IO,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input [9:0] mem_dq_in,
output mem_dqs_out,
output mem_dqs_ts,
input mem_dqs_in,
inout DQS_P,
inout DQS_N,
output [1:0] ddr_ck_out,
output rclk,
output if_a_empty,
output if_empty,
output if_a_full,
output if_full,
output of_a_empty,
output of_empty,
output of_a_full,
output of_full,
output [79:0] phy_din,
input [79:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input if_empty_or,
input [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus,
// inout [`SCAN_TEST_BUS_WIDTH-1:0] scan_test_bus, // currently unused
input idelay_inc,
input idelay_ce,
input idelay_ld,
output po_coarse_overflow,
output po_fine_overflow,
output [8:0] po_counter_read_val,
input po_fine_enable,
input po_coarse_enable,
input [1:0] po_en_calib,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input [1:0] pi_en_calib,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output wire pi_iserdes_rst,
output pi_phase_locked,
output pi_fine_overflow,
output [5:0] pi_counter_read_val,
output wire pi_dqs_found,
output dqs_out_of_range
);
localparam PHASER_INDEX =
(ABCD=="B" ? 1 : (ABCD == "C") ? 2 : (ABCD == "D" ? 3 : 0));
localparam L_OF_ARRAY_MODE =
(OF_ARRAY_MODE != "UNDECLARED") ? OF_ARRAY_MODE :
(PO_DATA_CTL == "FALSE" ) ? "ARRAY_MODE_4_X_4" : "ARRAY_MODE_8_X_4";
localparam L_IF_ARRAY_MODE = (IF_ARRAY_MODE != "UNDECLARED") ? IF_ARRAY_MODE : "ARRAY_MODE_4_X_8" ;
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [3:0] of_q9;
wire [3:0] of_q8;
wire [3:0] of_q7;
wire [7:0] of_q6;
wire [7:0] of_q5;
wire [3:0] of_q4;
wire [3:0] of_q3;
wire [3:0] of_q2;
wire [3:0] of_q1;
wire [3:0] of_q0;
wire [7:0] of_d9;
wire [7:0] of_d8;
wire [7:0] of_d7;
wire [7:0] of_d6;
wire [7:0] of_d5;
wire [7:0] of_d4;
wire [7:0] of_d3;
wire [7:0] of_d2;
wire [7:0] of_d1;
wire [7:0] of_d0;
wire [7:0] if_q9;
wire [7:0] if_q8;
wire [7:0] if_q7;
wire [7:0] if_q6;
wire [7:0] if_q5;
wire [7:0] if_q4;
wire [7:0] if_q3;
wire [7:0] if_q2;
wire [7:0] if_q1;
wire [7:0] if_q0;
wire [3:0] if_d9;
wire [3:0] if_d8;
wire [3:0] if_d7;
wire [3:0] if_d6;
wire [3:0] if_d5;
wire [3:0] if_d4;
wire [3:0] if_d3;
wire [3:0] if_d2;
wire [3:0] if_d1;
wire [3:0] if_d0;
wire [3:0] dummy_i5;
wire [3:0] dummy_i6;
wire [48-1:0] of_dqbus;
wire [10*4-1:0] iserdes_dout;
wire ififo_wr_enable;
wire phy_rd_en_;
wire dqs_to_phaser;
wire phy_wr_en = ( PO_DATA_CTL == "FALSE" ) ? phy_cmd_wr_en : phy_data_wr_en;
wire if_empty_;
wire if_a_empty_;
wire if_full_;
wire if_a_full_;
wire of_full_;
wire of_a_full_;
wire if_empty_mux;
reg if_empty_r;
reg if_empty_r1;
wire [79:0] rd_data;
reg [79:0] rd_data_r;
reg [79:0] rd_data_r1;
reg use_pipe;
wire reset_dqs_find = rst | pi_rst_dqs_find;
// IN_FIFO EMPTY->RDEN TIMING FIX:
// Always read from IN_FIFO - it doesn't hurt to read from an empty FIFO
// since the IN_FIFO read pointers are not incr'ed when the FIFO is empty
assign #(25) phy_rd_en_ = 1'b1;
generate
if ( PO_DATA_CTL == "FALSE" ) begin : if_empty_null
assign if_empty = 0;
assign if_a_empty = 0;
assign if_full = 0;
assign if_a_full = 0;
end
else begin : if_empty_gen
assign if_empty = if_empty_mux; // Use output of timing fix logic
assign if_a_empty = if_a_empty_;
assign if_full = if_full_;
assign if_a_full = if_a_full_;
end
endgenerate
generate
if ( PO_DATA_CTL == "FALSE" ) begin : dq_gen_48
assign of_dqbus[48-1:0] = {of_q6[7:4], of_q5[7:4], of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
assign phy_din = 80'h0;
end
else begin : dq_gen_40
assign of_dqbus[40-1:0] = {of_q9, of_q8, of_q7, of_q6[3:0], of_q5[3:0], of_q4, of_q3, of_q2, of_q1, of_q0};
// IN_FIFO EMPTY->RDEN TIMING FIX:
assign rd_data = {if_q9, if_q8, if_q7, if_q6, if_q5, if_q4, if_q3, if_q2, if_q1, if_q0};
// Keep track of whether this particular IN_FIFO is either ahead, behind,
// or in sync with the other IN_FIFOs in terms of empty status. If it's
// "ahead" (i.e. !empty occurs one clock cycle sooner), then the use_delay
// signal will be set, and a delayed version of the IN_FIFO output data
// will be used.
always @(posedge phy_clk) begin
rd_data_r <= #(025) rd_data;
rd_data_r1 <= #(025) rd_data_r;
if_empty_r <= #(025) if_empty_;
if_empty_r1 <= #(025) if_empty_r;
if (if_empty_r)
// Reset use_pipe as soon as this FIFO goes empty - assumes that
// the following case will not happen:
// - FIFO[0] is "ahead" and has its use_pipe = 1
// - FIFO[1] is "behind" and has its use_pipe = 0
// - Both FIFOs go empty at the same time for one cycle, then
// go not empty afterwards
// In this case, in order for FIFO[0] to know that it is still
// "ahead" even after it has gone empty, it will need to know
// that FIFO[1] went empty the same time FIFO[0] did - which
// requires that the logic below use FIFO[1]'s empty flag -
// extending this to X IN_FIFOs, each FIFO's logic must check the
// empty flag for the other X-1 IN_FIFOs. This can be an issue with
// meeting place/route timing for a wide I/F
use_pipe <= #(025) 1'b0;
else if (!if_empty_r && if_empty_or)
// If this FIFO isn't empty, but others are, then this FIFO must
// be "ahead" of others
use_pipe <= #(025) 1'b1;
end
assign if_empty_mux = (use_pipe) ? if_empty_r1 : if_empty_r;
assign phy_din = (use_pipe) ? rd_data_r1 : rd_data_r;
end
endgenerate
wire iserdes_rst;
assign pi_iserdes_rst = iserdes_rst;
assign { if_d9, if_d8, if_d7, if_d6, if_d5, if_d4, if_d3, if_d2, if_d1, if_d0} = iserdes_dout;
assign {of_d9, of_d8, of_d7, of_d6, of_d5, of_d4, of_d3, of_d2, of_d1, of_d0} = phy_dout;
wire [1:0] rank_sel_i = ((phaser_ctl_bus[MSB_RANK_SEL_I :MSB_RANK_SEL_I -7] >> (PHASER_INDEX << 1)) & 2'b11);
wire [1:0] rank_sel_o = ((phaser_ctl_bus[MSB_RANK_SEL_O :MSB_RANK_SEL_O -7] >> (PHASER_INDEX << 1)) & 2'b11);
PHASER_IN_PHY #(
.BURST_MODE ( PI_BURST_MODE),
.CLKOUT_DIV ( PI_CLKOUT_DIV),
.FINE_DELAY ( PI_FINE_DELAY),
.FREQ_REF_DIV ( PI_FREQ_REF_DIV),
.OUTPUT_CLK_SRC ( PI_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PI_SYNC_IN_DIV_RST)
) phaser_in (
.DQSFOUND (pi_dqs_found),
.DQSOUTOFRANGE (dqs_out_of_range),
.FINEOVERFLOW (pi_fine_overflow),
.PHASELOCKED (pi_phase_locked),
.ISERDESRST (iserdes_rst),
.ICLKDIV (iserdes_clkdiv),
.ICLK (iserdes_clk),
.COUNTERREADVAL (pi_counter_read_val),
.RCLK (rclk),
.WRENABLE (ififo_wr_enable),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PI - 3 + PHASER_INDEX]),
.ENCALIBPHY (pi_en_calib),
.FINEENABLE (pi_fine_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (rank_sel_i),
.PHASEREFCLK (dqs_to_phaser),
.RSTDQSFIND (pi_rst_dqs_find),
.RST (rst),
.FINEINC (pi_fine_inc),
.COUNTERLOADEN (pi_counter_load_en),
.COUNTERREADEN (pi_counter_read_en),
.COUNTERLOADVAL (pi_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
wire #0 phase_ref = freq_refclk;
wire oserdes_clk;
PHASER_OUT_PHY #(
.CLKOUT_DIV ( PO_CLKOUT_DIV),
.DATA_CTL_N ( PO_DATA_CTL ),
.FINE_DELAY ( PO_FINE_DELAY),
.COARSE_DELAY ( PO_COARSE_DELAY),
.OCLK_DELAY ( PO_OCLK_DELAY),
.OCLKDELAY_INV ( PO_OCLKDELAY_INV),
.OUTPUT_CLK_SRC ( PO_OUTPUT_CLK_SRC),
.SYNC_IN_DIV_RST ( PO_SYNC_IN_DIV_RST)
) phaser_out (
.COARSEOVERFLOW (po_coarse_overflow),
.CTSBUS (oserdes_dqs_ts),
.DQSBUS (oserdes_dqs),
.DTSBUS (oserdes_dq_ts),
.FINEOVERFLOW (po_fine_overflow),
.OCLKDIV (oserdes_clkdiv),
.OCLK (oserdes_clk),
.OCLKDELAYED (oserdes_clk_delayed),
.COUNTERREADVAL (po_counter_read_val),
.BURSTPENDINGPHY (phaser_ctl_bus[MSB_BURST_PEND_PO -3 + PHASER_INDEX]),
.ENCALIBPHY (po_en_calib),
.RDENABLE (po_rd_enable),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.PHASEREFCLK (/*phase_ref*/),
.RST (rst),
.OSERDESRST (oserdes_rst),
.COARSEENABLE (po_coarse_enable),
.FINEENABLE (po_fine_enable),
.COARSEINC (po_coarse_inc),
.FINEINC (po_fine_inc),
.SELFINEOCLKDELAY (po_sel_fine_oclk_delay),
.COUNTERLOADEN (po_counter_load_en),
.COUNTERREADEN (po_counter_read_en),
.COUNTERLOADVAL (po_counter_load_val),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
IN_FIFO #(
.ALMOST_EMPTY_VALUE ( IF_ALMOST_EMPTY_VALUE ),
.ALMOST_FULL_VALUE ( IF_ALMOST_FULL_VALUE ),
.ARRAY_MODE ( L_IF_ARRAY_MODE),
.SYNCHRONOUS_MODE ( IF_SYNCHRONOUS_MODE)
) in_fifo (
.ALMOSTEMPTY (if_a_empty_),
.ALMOSTFULL (if_a_full_),
.EMPTY (if_empty_),
.FULL (if_full_),
.Q0 (if_q0),
.Q1 (if_q1),
.Q2 (if_q2),
.Q3 (if_q3),
.Q4 (if_q4),
.Q5 (if_q5),
.Q6 (if_q6),
.Q7 (if_q7),
.Q8 (if_q8),
.Q9 (if_q9),
//===
.D0 (if_d0),
.D1 (if_d1),
.D2 (if_d2),
.D3 (if_d3),
.D4 (if_d4),
.D5 ({dummy_i5,if_d5}),
.D6 ({dummy_i6,if_d6}),
.D7 (if_d7),
.D8 (if_d8),
.D9 (if_d9),
.RDCLK (phy_clk),
.RDEN (phy_rd_en_),
.RESET (rst),
.WRCLK (iserdes_clkdiv),
.WREN (ififo_wr_enable)
);
OUT_FIFO #(
.ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.ARRAY_MODE (L_OF_ARRAY_MODE),
.OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
.SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE)
) out_fifo (
.ALMOSTEMPTY (of_a_empty),
.ALMOSTFULL (of_a_full),
.EMPTY (of_empty),
.FULL (of_full),
.Q0 (of_q0),
.Q1 (of_q1),
.Q2 (of_q2),
.Q3 (of_q3),
.Q4 (of_q4),
.Q5 (of_q5),
.Q6 (of_q6),
.Q7 (of_q7),
.Q8 (of_q8),
.Q9 (of_q9),
.D0 (of_d0),
.D1 (of_d1),
.D2 (of_d2),
.D3 (of_d3),
.D4 (of_d4),
.D5 (of_d5),
.D6 (of_d6),
.D7 (of_d7),
.D8 (of_d8),
.D9 (of_d9),
.RDCLK (oserdes_clkdiv),
.RDEN (po_rd_enable),
.RESET (rst),
.WRCLK (phy_clk),
.WREN (phy_wr_en)
);
byte_group_io #
(
.BITLANES (BITLANES),
.BITLANES_OUTONLY (BITLANES_OUTONLY),
.OSERDES_DATA_RATE (PO_DATA_CTL == "FALSE" ? "SDR" : "DDR"),
.DIFFERENTIAL_DQS (DIFFERENTIAL_DQS),
.IDELAYE2_IDELAY_TYPE (IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (IDELAYE2_IDELAY_VALUE),
.IODELAY_GRP (IODELAY_GRP)
)
byte_group_io
(
.IO ( IO[BUS_WIDTH-1:0] /* iobuf terminated signals to memory */),
.DQS_P ( DQS_P ),
.DQS_N ( DQS_N ),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_in (mem_dqs_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.rst (rst),
.oserdes_rst (oserdes_rst),
.iserdes_rst (iserdes_rst ),
.iserdes_dout (iserdes_dout),
.dqs_to_phaser (dqs_to_phaser),
.phy_clk (phy_clk),
.iserdes_clk (iserdes_clk),
.iserdes_clkb (!iserdes_clk),
.iserdes_clkdiv (iserdes_clkdiv),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.oserdes_clk (oserdes_clk),
.oserdes_clk_delayed (oserdes_clk_delayed),
.oserdes_clkdiv (oserdes_clkdiv),
.oserdes_dqs ({oserdes_dqs[1], oserdes_dqs[0]}),
.oserdes_dqsts ({oserdes_dqs_ts[1], oserdes_dqs_ts[0]}),
.oserdes_dq (of_dqbus),
.oserdes_dqts ({oserdes_dq_ts[1], oserdes_dq_ts[0]})
);
generate
if ( PO_DATA_CTL== "FALSE" && GENERATE_DDR_CK == ABCD) begin : ddr_ck_gen
ODDR ddr_ck (
.C (oserdes_clk),
.R (oserdes_rst),
.S (),
.D1 (1'b0),
.D2 (1'b1),
.CE (1'b1),
.Q (ddr_ck_out_q)
);
OBUFDS ddr_ck_obuf (.I(ddr_ck_out_q), .O(ddr_ck_out[0]), .OB(ddr_ck_out[1]));
end
else begin : ddr_ck_null
assign ddr_ck_out = 2'b0;
end
endgenerate
endmodule // byte_lane
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S9_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAMB16_S9_altera (
address,
clock,
data,
rden,
wren,
q);
input [10:0] address;
input clock;
input [7:0] data;
input rden;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter init_file = "";
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.rden_a (rden),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = init_file,
//altsyncram_component.init_file = "./sources_ngnp_multicore/src/bb_ram00.mif",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sources_ngnp_multicore/src/bb_ram00.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sources_ngnp_multicore/src/bb_ram00.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S9_altera_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ****************************************************************************
// Copyright : NUDT.
// ============================================================================
// FILE NAME : SGMII_RX.v
// CREATE DATE : 2013-12-03
// AUTHOR : ZengQiang
// AUTHOR'S EMAIL : [email protected]
// AUTHOR'S TEL :
// ============================================================================
// RELEASE HISTORY -------------------------------------------------------
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2013-12-03 ZengQiang Original Verison
// ============================================================================
// KEYWORDS : N/A
// ----------------------------------------------------------------------------
// PURPOSE : MAC core output 8bit pkt format transform 134bit pkt format
// ----------------------------------------------------------------------------
// ============================================================================
// REUSE ISSUES
// Reset Strategy : Async clear,active high
// Clock Domains : ff_rx_clk
// Critical TiminG : N/A
// Instantiations : N/A
// Synthesizable : N/A
// Others : N/A
// ****************************************************************************
module SGMII_RX
(reset,
ff_rx_clk,
ff_rx_rdy,
ff_rx_data,
ff_rx_mod,
ff_rx_sop,
ff_rx_eop,
rx_err,
rx_err_stat,
rx_frm_type,
ff_rx_dsav,
ff_rx_dval,
ff_rx_a_full,
ff_rx_a_empty,
pkt_receive_add,
pkt_discard_add,
out_pkt_wrreq,
out_pkt,
out_pkt_almostfull,
out_valid_wrreq,
out_valid
);
input reset;
input ff_rx_clk;
output ff_rx_rdy;
input [31:0] ff_rx_data;
input [1:0] ff_rx_mod;
input ff_rx_sop;
input ff_rx_eop;
input [5:0] rx_err;
input [17:0] rx_err_stat;
input [3:0] rx_frm_type;
input ff_rx_dsav;
input ff_rx_dval;
input ff_rx_a_full;
input ff_rx_a_empty;
output pkt_receive_add;
output pkt_discard_add;
output out_pkt_wrreq;
output [133:0] out_pkt;
input out_pkt_almostfull;
output out_valid_wrreq;
output out_valid;
reg ff_rx_rdy;
reg pkt_receive_add;
reg pkt_discard_add;
reg out_pkt_wrreq;
reg [133:0] out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg [2:0]current_state;
parameter
transmit_byte0_s = 3'b001,
transmit_byte1_s = 3'b010,
transmit_byte2_s = 3'b011,
transmit_byte3_s = 3'b100,
discard_s = 3'b101;
always@(posedge ff_rx_clk or negedge reset)
if(!reset) begin
ff_rx_rdy <= 1'b0;
out_pkt_wrreq <= 1'b0;
out_pkt <= 134'b0;
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
pkt_receive_add <= 1'b0;
pkt_discard_add <= 1'b0;
current_state <= transmit_byte0_s;
end
else begin
ff_rx_rdy <= 1'b1;
case(current_state)
transmit_byte0_s: begin
out_valid_wrreq <= 1'b0;
out_valid <= 1'b0;
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[127:96] <= ff_rx_data;
if(ff_rx_sop == 1'b1) begin //pkt head
if(!out_pkt_almostfull) begin//FIFO can receive a 1518B pkt
out_pkt[133:132] <= 2'b01;
pkt_receive_add <= 1'b1;
current_state <= transmit_byte1_s;
end
else begin
pkt_discard_add <= 1'b1;
current_state <= discard_s;
end
end
else if(ff_rx_eop == 1'b1) begin//pkt tail
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= {2'b11,ff_rx_mod[1:0]};
out_pkt_wrreq <= 1'b1;
current_state <= transmit_byte0_s;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
end
else begin
out_pkt[133:132] <= 2'b11;
current_state <= transmit_byte1_s;
end
end
else begin
current_state <= transmit_byte0_s;
end
end
transmit_byte1_s: begin
out_pkt_wrreq <= 1'b0;
pkt_receive_add <= 1'b0;
if(ff_rx_dval == 1'b1) begin//data valid
out_pkt[95:64] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin//pkt head
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= {2'b10,ff_rx_mod[1:0]};
out_pkt_wrreq <= 1'b1;
current_state <= transmit_byte0_s;
if(rx_err == 6'b0) begin//pkt error
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
end
else begin
current_state <= transmit_byte2_s;
end
end
else begin
current_state <= transmit_byte1_s;
end
end
transmit_byte2_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[63:32] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= {2'b01,ff_rx_mod[1:0]};
out_pkt_wrreq <= 1'b1;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
current_state <= transmit_byte0_s;
end
else begin
current_state <= transmit_byte3_s;
end
end
else begin
current_state <= transmit_byte2_s;
end
end
transmit_byte3_s: begin
out_pkt_wrreq <= 1'b0;
if(ff_rx_dval == 1'b1) begin
out_pkt[31:0] <= ff_rx_data;
if(ff_rx_eop == 1'b1) begin
out_pkt[133:132] <= 2'b10;
out_pkt[131:128] <= {2'b00,ff_rx_mod[1:0]};
out_pkt_wrreq <= 1'b1;
current_state <= transmit_byte0_s;
if(rx_err == 6'b0) begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b1;
end
else begin
out_valid_wrreq <= 1'b1;
out_valid <= 1'b0;
end
end
else begin
out_pkt_wrreq <= 1'b1;
current_state <= transmit_byte0_s;
end
end
else begin
current_state <= transmit_byte3_s;
end
end
discard_s:begin
out_pkt_wrreq <= 1'b0;
pkt_discard_add <= 1'b0;
if((ff_rx_dval == 1'b1)&&(ff_rx_eop == 1'b1))begin
current_state <= transmit_byte0_s;
end
else begin
current_state <= discard_s;
end
end
endcase
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_irq_bridge/altera_irq_bridge.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// -------------------------------------------------------
// Altera IRQ Bridge
//
// Parameters
// IRQ_WIDTH : $IRQ_WIDTH
//
// -------------------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
`timescale 1 ns / 1 ns
module altera_irq_bridge
#(
parameter IRQ_WIDTH = 32
)
(
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset,
input [IRQ_WIDTH - 1:0] receiver_irq,
output sender31_irq,
output sender30_irq,
output sender29_irq,
output sender28_irq,
output sender27_irq,
output sender26_irq,
output sender25_irq,
output sender24_irq,
output sender23_irq,
output sender22_irq,
output sender21_irq,
output sender20_irq,
output sender19_irq,
output sender18_irq,
output sender17_irq,
output sender16_irq,
output sender15_irq,
output sender14_irq,
output sender13_irq,
output sender12_irq,
output sender11_irq,
output sender10_irq,
output sender9_irq,
output sender8_irq,
output sender7_irq,
output sender6_irq,
output sender5_irq,
output sender4_irq,
output sender3_irq,
output sender2_irq,
output sender1_irq,
output sender0_irq
);
wire [31:0] receiver_temp_irq;
assign receiver_temp_irq = {{(32 - IRQ_WIDTH){1'b0}}, receiver_irq}; //to align a non-32bit receiver interface with 32 interfaces of the receiver
assign sender0_irq = receiver_temp_irq[0];
assign sender1_irq = receiver_temp_irq[1];
assign sender2_irq = receiver_temp_irq[2];
assign sender3_irq = receiver_temp_irq[3];
assign sender4_irq = receiver_temp_irq[4];
assign sender5_irq = receiver_temp_irq[5];
assign sender6_irq = receiver_temp_irq[6];
assign sender7_irq = receiver_temp_irq[7];
assign sender8_irq = receiver_temp_irq[8];
assign sender9_irq = receiver_temp_irq[9];
assign sender10_irq = receiver_temp_irq[10];
assign sender11_irq = receiver_temp_irq[11];
assign sender12_irq = receiver_temp_irq[12];
assign sender13_irq = receiver_temp_irq[13];
assign sender14_irq = receiver_temp_irq[14];
assign sender15_irq = receiver_temp_irq[15];
assign sender16_irq = receiver_temp_irq[16];
assign sender17_irq = receiver_temp_irq[17];
assign sender18_irq = receiver_temp_irq[18];
assign sender19_irq = receiver_temp_irq[19];
assign sender20_irq = receiver_temp_irq[20];
assign sender21_irq = receiver_temp_irq[21];
assign sender22_irq = receiver_temp_irq[22];
assign sender23_irq = receiver_temp_irq[23];
assign sender24_irq = receiver_temp_irq[24];
assign sender25_irq = receiver_temp_irq[25];
assign sender26_irq = receiver_temp_irq[26];
assign sender27_irq = receiver_temp_irq[27];
assign sender28_irq = receiver_temp_irq[28];
assign sender29_irq = receiver_temp_irq[29];
assign sender30_irq = receiver_temp_irq[30];
assign sender31_irq = receiver_temp_irq[31];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_1_V
`define SKY130_FD_SC_MS__O221AI_1_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221ai_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_1_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_qsys_sequencer_cpu_inst_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IOBUF (O, IO, I, T);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
inout IO;
input I, T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
buf B1 (O, IO);
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(I => IO)= (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module pll (
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.010000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.038000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.01000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.03800000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5000"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25000"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "19"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import Cpdt.CpdtTactics.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(**
(*
%\part{Basic Programming and Proving}
\chapter{Introducing Inductive Types}%
*)
%\part{基本になるプログラミングと証明}
\chapter{帰納型の導入}%
*)
(**
(* The logical foundation of Coq is the Calculus of Inductive Constructions, or CIC. In a sense, CIC is built from just two relatively straightforward features: function types and inductive types. From this modest foundation, we can prove essentially all of the theorems of math and carry out effectively all program verifications, with enough effort expended. This chapter introduces induction and recursion for functional programming in Coq. Most of our examples reproduce functionality from the Coq standard library, and I have tried to copy the standard library's choices of identifiers, where possible, so many of the definitions here are already available in the default Coq environment.
*)
Coqの論理の基盤はCIC（Calculus of Inductive Constructions）です。
CICは、関数型（function type）と帰納型（inductive type）という、比較的簡単な2つの機能だけで構成されていると考えられます。
そのような簡素な基盤であるCICから、事実上あらゆる数学の定理が証明可能であり、
それなりに手間をかければ、あらゆるプログラム検証を効果的に実行できるのです。
本章では、Coqにおける関数型プログラミングのために帰納と再帰を導入します。
本章の例の大部分は、Coqの標準ライブラリの機能を再現するものです。
標準ライブラリで使われている識別子を可能な場合にはそのまま採用しているので、大半の定義はデフォルトのCoq環境ですぐに使えます。
(*
The last chapter took a deep dive into some of the more advanced Coq features, to highlight the unusual approach that I advocate in this book. However, from this point on, we will rewind and go back to basics, presenting the relevant features of Coq in a more bottom-up manner. A useful first step is a discussion of the differences and relationships between proofs and programs in Coq.
*)
前章では、筆者が本書で伝えたい特異なアプローチに焦点をあてるべく、Coqの深淵に潜りました。
ここから先は基本に戻り、関連するCoqの機能をボトムアップで見ていくことにしましょう。
はじめの一歩として、証明とCoqプログラムの差異および関係について考えます。
*)
(**
(* * Proof Terms *)
* 証明項
*)
(**
(*
Mainstream presentations of mathematics treat proofs as objects that exist outside of the universe of mathematical objects. However, for a variety of reasoning tasks, it is convenient to encode proofs, traditional mathematical objects, and programs within a single formal language. Validity checks on mathematical objects are useful in any setting, to catch typos and other uninteresting errors. The benefits of static typing for programs are widely recognized, and Coq brings those benefits to both mathematical objects and programs via a uniform mechanism. In fact, from this point on, we will not bother to distinguish between programs and mathematical objects. Many mathematical formalisms are most easily encoded in terms of programs.
*)
数学では、数学的対象の世界の外側にあるものとして証明を扱うのが主流です。
(* 池渕：「証明は数学の世界の外側にある」と言われると違和感があった。多分mathematical objectは普通の数学で言う集合を指していて、集合と証明は区別される、ということを言いたいんだと思う。*)
しかし、証明、伝統的な数学的対象、そしてプログラムを単一の形式的言語により符号化すれば、さまざまな論証の作業にとって都合がよくなります。
数学の対象に対する検証は、どのような形であれ、書き間違いやつまらないミスの発見に役立ちます。
Coqでは、すでに広く認知されているプログラムへの静的型付けによる有益性を、数学の対象とプログラムに対して同じ仕組みで利用できます。
そういうわけで、これ以降は、プログラムと数学の対象とをわざわざ区別することはやめにします。
数学における形式主義のほとんどはプログラムによって簡単に符号化できるのです。
(*
Proofs are fundamentally different from programs, because any two proofs of a theorem are considered equivalent, from a formal standpoint if not from an engineering standpoint. However, we can use the same type-checking technology to check proofs as we use to validate our programs. This is the%\index{Curry-Howard correspondence}% _Curry-Howard correspondence_ %\cite{Curry,Howard}%, an approach for relating proofs and programs. We represent mathematical theorems as types, such that a theorem's proofs are exactly those programs that type-check at the corresponding type.
*)
証明は、本来はプログラムとは違います。
ある定理に対する2つの証明は、工学的でなく形式的に見れば、等価なものであるとみなせるからです。
とはいえ、証明の検査には、プログラムの検証に使うのと同じ型検査の技術が使えます。
証明とプログラムは、_[Curry-Howard対応]_に%\index{Curry-Howard対応}%%\cite{Curry,Howard}%よって関連付けられるのです。
数学の定理を型として表現すると、その型を持つことを確認するプログラムそのものが、その定理の証明になります。
(*
The last chapter's example already snuck in an instance of Curry-Howard. We used the token [->] to stand for both function types and logical implications. One reasonable conclusion upon seeing this might be that some fancy overloading of notations is at work. In fact, functions and implications are precisely identical according to Curry-Howard! That is, they are just two ways of describing the same computational phenomenon.
*)
前章の例にはCurry-Howardの具体例を忍び込ませていました。
[->]という字句を、関数型と論理含意の両方を表すのに使っています。
それを見て、記法を多重定義しているのだろうと考えたかもしれません。
実際、関数と論理含意は、Curry-Howard対応によってまったく同一であるとみなせるのです！
これらは、計算における同一の現象を、2つの違う方法で表しているにすぎません。
(*
A short demonstration should explain how this can be. The identity function over the natural numbers is certainly not a controversial program.
*)
この仕組みは簡単な例で示せます。
自然数上の恒等関数は自明なプログラムでしょう。
*)
Check (fun x : nat => x).
(** [: nat -> nat] *)
(**
(*
%\smallskip{}%Consider this alternate program, which is almost identical to the last one.
*)
%\smallskip{}%この恒等関数の代わりに次の恒等プログラムを考えてみましょう。上記の例とほどんと同じものです。
*)
Check (fun x : True => x).
(** [: True -> True] *)
(**
(*
%\smallskip{}%The identity program is interpreted as a proof that %\index{Gallina terms!True}%[True], the always-true proposition, implies itself! What we see is that Curry-Howard interprets implications as functions, where an input is a proposition being assumed and an output is a proposition being deduced. This intuition is not too far from a common one for informal theorem proving, where we might already think of an implication proof as a process for transforming a hypothesis into a conclusion.
*)
%\smallskip{}%この恒等プログラムは、[True]%\index{Gallina terms!True}%、すなわち常に真であるという命題が自分自身を含意する、ということの証明であると解釈します。
含意を、Curry-Howard対応により、関数として解釈するわけです。
関数への入力は仮定された命題、関数からの出力は演繹された命題になります。
この見方は、定理を非形式的に証明するときの一般的な直観とかけ離れたものではありません。
含意を非形式的に証明するとき、仮説を結論に変換する工程であるかのように考えることもあるでしょう。
(*
There are also more primitive proof forms available. For instance, the term %\index{Gallina terms!I}%[I] is the single proof of [True], applicable in any context.
*)
Coqにはさらに基本的な形の証明も用意されています。
たとえば、%\index{Gallina terms!I}%[I]という項は[True]の唯一の証明で、あらゆる文脈で適用可能です。
*)
Check I.
(** [: True] *)
(**
(*
%\smallskip{}%With [I], we can prove another simple propositional theorem.
*)
%\smallskip{}%[I]を使って、命題論理の別の定理を証明できます。
*)
Check (fun _ : False => I).
(** [: False -> True] *)
(**
(* %\smallskip{}%No proofs of %\index{Gallina terms!False}%[False] exist in the top-level context, but the implication-as-function analogy gives us an easy way to, for example, show that [False] implies itself.
*)
%\smallskip{}% %\index{Gallina terms!False}%[False]の証明はトップレベルの文脈には存在しません。
しかし、たとえば[False]が自分自身を含意することは、「関数としての含意」からの類推で簡単に示せます。
*)
Check (fun x : False => x).
(** [: False -> False] *)
(**
(*
%\smallskip{}%Every one of these example programs whose type looks like a logical formula is a%\index{proof term}% _proof term_. We use that name for any Gallina term of a logical type, and we will elaborate shortly on what makes a type logical.
*)
%\smallskip{}%これらは、それぞれ型が論理式のように見えるプログラムの例になっており、いずれも%\index{しょうめいこう@証明項}% _[証明項]_と呼ばれます。
この名称は、論理的な型を持つ任意のGallinaの項を表すのに使うことにします。
どんな型が論理的であるかについては、すぐあとで詳細に述べます。
(*
In the rest of this chapter, we will introduce different ways of defining types. Every example type can be interpreted alternatively as a type of programs or proofs.
*)
本章の残りの部分では、型を定義する方法をいくつか導入します。
例に挙げる型は、いずれもプログラムの型もしくは証明として解釈できます。
(*
One of the first types we introduce will be [bool], with constructors [true] and [false]. Newcomers to Coq often wonder about the distinction between [True] and [true] and the distinction between [False] and [false]. One glib answer is that [True] and [False] are types, but [true] and [false] are not. A more useful answer is that Coq's metatheory guarantees that any term of type [bool] _evaluates_ to either [true] or [false]. This means that we have an _algorithm_ for answering any question phrased as an expression of type [bool]. Conversely, most propositions do not evaluate to [True] or [False]; the language of inductively defined propositions is much richer than that. We ought to be glad that we have no algorithm for deciding our formalized version of mathematical truth, since otherwise it would be clear that we could not formalize undecidable properties, like almost any interesting property of general-purpose programs.
*)
最初に導入する型は[bool]であり、その構成子は[true]および[false]です。
Coqに不慣れのうちは、[True]と[true]あるいは[False]と[false]の違いによく戸惑います。
もっともらしく言うと、[True]と[False]は型であり、[true]と[false]は型ではありません。
もう少しきちんと言うと、[bool]型の任意の項は[true]か[false]のどちらかに_[評価]_され、そのことがCoqのメタ定理によって保証されています。
つまり、型が[bool]であるような式で表されたどんな問題に対しても、それに答える_[アルゴリズム]_があるということです。
逆に言うと、ほとんどの命題は[True]あるいは[False]には評価されません。
帰納的に定義される命題の言語には、もっと豊かな表現力があるのです。(* 意味がよくわからない -nobsun *)
数学的に形式化された真理をアルゴリズムで決定できないことは、残念なことではありません。
そのようなアルゴリズムがあれば、決定不能な性質の形式化は不可能であることが明らかになってしまい、汎用のプログラムが持つような興味深い性質のほとんどを形式化できなくなってしまうでしょう。
*)
(**
(* * Enumerations *)
* 列挙
*)
(**
(* Coq inductive types generalize the %\index{algebraic datatypes}%algebraic datatypes found in %\index{Haskell}%Haskell and %\index{ML}%ML. Confusingly enough, inductive types also generalize %\index{generalized algebraic datatypes}%generalized algebraic datatypes (GADTs), by adding the possibility for type dependency. Even so, it is worth backing up from the examples of the last chapter and going over basic, algebraic-datatype uses of inductive datatypes, because the chance to prove things about the values of these types adds new wrinkles beyond usual practice in Haskell and ML.
*)
Coqの帰納型は、%\index{Haskell}%Haskellや%\index{ML}%MLにおける%\index{だいすうデータがた@代数データ型}%代数データ型を一般化したものです。
さらに、値への依存性を型に持たせることで、Coqの帰納型はGADT（一般化代数データ型）の一般化にもなっています。
混乱しやすいところですが、前章で説明した例を踏まえたうえで、帰納データ型における代数的データの基本的な使い方を丹念に見ておく価値はあります。
そのような型の値に関する証明を見ることで、HaskellやMLを普通に使っているだけでは手にできない知見が得られるからです。
(*
The singleton type [unit] is an inductive type:%\index{Gallina terms!unit}\index{Gallina terms!tt}%
*)
シングルトン型[unit]は帰納型です%\index{Gallinaこう@Gallina項!unit}\index{Gallinaこう@Gallina項!tt}%。
*)
Inductive unit : Set :=
| tt.
(**
(*
This vernacular command defines a new inductive type [unit] whose only value is [tt].
We can verify the types of the two identifiers we introduce:
*)
このVernacularコマンドにより、[tt]を唯一の値として持つ新しい帰納型[unit]が定義されます。
導入した二つの識別子の型は次のようにして検証できます。
*)
Check unit.
(** [unit : Set] *)
Check tt.
(** [tt : unit] *)
(**
(*
%\smallskip{}%We can prove that [unit] is a genuine singleton type.
*)
%\smallskip{}%[unit]が確かにシングルトン（値を一つしか持たない）型であることを証明しましょう。
*)
Theorem unit_singleton : forall x : unit, x = tt.
(**
(*
The important thing about an inductive type is, unsurprisingly, that you can do induction over its values, and induction is the key to proving this theorem. We ask to proceed by induction on the variable [x].%\index{tactics!induction}%
*)
帰納型については、当たり前のこととして、その値の上で帰納法を使える点が重要です。
そして上記の定理の証明では、まさに帰納法を使います。
変数[x]に関する帰納法を進めるよう、Coqに指示します。%\index{tactics!induction}%
*)
(* begin thide *)
induction x.
(**
(*
The goal changes to:
*)
ゴールは以下のようになります。
[[
tt = tt
]]
*)
(**
(*
%\noindent{}%...which we can discharge trivially.
*)
%\noindent{}%これは自明ですね。(* うまい訳を思いつかない-nobsun *)
*)
reflexivity.
Qed.
(* end thide *)
(**
(*
It seems kind of odd to write a proof by induction with no inductive hypotheses. We could have arrived at the same result by beginning the proof with:%\index{tactics!destruct}% [[
destruct x.
]]
*)
帰納法の仮説なしで帰納法による証明を書くのは、少し奇妙に思えます。
伝統的な数学における「場合分けによる証明」に対応するのは[destruct]タクティクです。%\index{tactics!destruct}%
[[
destruct x.
]]
(*
%\noindent%...which corresponds to "proof by case analysis" in classical math. For non-recursive inductive types, the two tactics will always have identical behavior. Often case analysis is sufficient, even in proofs about recursive types, and it is nice to avoid introducing unneeded induction hypotheses.
*)
%\noindent %上記のように証明を始めても、同じ結果になったでしょう。
[induction]と[destruct]の二つのタクティクは、再帰のない帰納型に対しては常にまったく同じ振る舞いをします。
再帰的な型に関する証明であっても、場合分けによる証明で十分なことが少なくありません。
また、場合分けによる証明により、不必要な帰納法の仮説を増やさないで済むこともあります。
(*
What exactly _is_ the %\index{induction principles}%induction principle for [unit]? We can ask Coq:
*)
ここで、[unit]の対する%\index{induction principles}%帰納法の原理をCoqに聞いてみましょう。
*)
Check unit_ind.
(** [unit_ind : forall P : unit -> Prop, P tt -> forall u : unit, P u] *)
(**
(*
%\smallskip{}%Every [Inductive] command defining a type [T] also defines an induction principle named [T_ind]. Recall from the last section that our type, operations over it, and principles for reasoning about it all live in the same language and are described by the same type system. The key to telling what is a program and what is a proof lies in the distinction between the type %\index{Gallina terms!Prop}%[Prop], which appears in our induction principle; and the type %\index{Gallina terms!Set}%[Set], which we have seen a few times already.
*)
%\smallskip{}%ある型[T]を定義する[Inductive]コマンドによって、[T_ind]という名前がついた帰納法の原理も定義されます。
前節で述べたように、型、それに対する操作、論証のための帰納法の原理は、すべて同一の言語によって表され、同一の型システムにより記述されています。
あるプログラムが何なのか、ある証明が何なのかを知りたいときに鍵となるのは、上記の帰納法の原理に出てくる%\index{Gallinaこう@Gallina項!Prop}%[Prop]型と、すでに何度か登場している%\index{Gallinaこう@Gallina項!Set}%[Set]型とをきちんと区別することです。
(*
The convention goes like this: [Set] is the type of normal types used in programming, and the values of such types are programs. [Prop] is the type of logical propositions, and the values of such types are proofs. Thus, an induction principle has a type that shows us that it is a function for building proofs.
*)
慣習によれば、[Set]はプログラミングで使われている通常の型を表す型で、そのような型の値がプログラムです。
[Prop]は論理的な命題を表す型で、そのような型の値が証明です。
したがって、帰納法の原理の型を見れば、帰納法の原理は「証明を構成するための関数」であることがわかります。
(*
Specifically, [unit_ind] quantifies over a predicate [P] over [unit] values. If we can present a proof that [P] holds of [tt], then we are rewarded with a proof that [P] holds for any value [u] of type [unit]. In our last proof, the predicate was [(fun u : unit => u = tt)].
*)
特に[unit_ind]では、[unit]値に対する述語[P]が限量化されています。
述語[P]が[tt]を満たすことの証明を提示できれば、[unit]型の任意の値[u]について[P]が成り立つことを証明したことになります。
さきほどの証明で述語[P]に相当するのは、[(fun u : unit => u = tt)]です。
(*
The definition of [unit] places the type in [Set]. By replacing [Set] with [Prop], [unit] with [True], and [tt] with [I], we arrive at precisely the definition of [True] that the Coq standard library employs! The program type [unit] is the Curry-Howard equivalent of the proposition [True]. We might make the tongue-in-cheek claim that, while philosophers have expended much ink on the nature of truth, we have now determined that truth is the [unit] type of functional programming.
*)
[unit]の定義では、型を[Set]としています。
[Set]を[Prop]に置き換え、[unit]を[True]に置き換え、[tt]を[I]に置き換えると、Coqの標準ライブラリが採用している[True]の定義とぴったり一致します。
プログラムの型[unit]は、Curry-Howard対応によって述語[True]と同等です。
皮肉っぽくいえば、哲学者が真とは何かをどんなに時間をかけて論じたところで、ここでは真を関数プログラミングの[unit]型であると決めた、ということです。
%\medskip%
(*
We can define an inductive type even simpler than [unit]:%\index{Gallina terms!Empty\_set}%
*)
[unit]よりさらに単純な帰納型も定義できます。%\index{Gallinaこう@Gallina項!Empty\_set}%
*)
Inductive Empty_set : Set := .
(**
(* [Empty_set] has no elements. We can prove fun theorems about it:
*)
[Empty_set]には要素がありません。
そんな[Empty_set]については面白い定理が証明できます。
*)
Theorem the_sky_is_falling : forall x : Empty_set, 2 + 2 = 5.
(* begin thide *)
destruct 1.
Qed.
(* end thide *)
(**
(*
Because [Empty_set] has no elements, the fact of having an element of this type implies anything. We use [destruct 1] instead of [destruct x] in the proof because unused quantified variables are relegated to being referred to by number. (There is a good reason for this, related to the unity of quantifiers and implication. At least within Coq's logical foundation of %\index{constructive logic}%constructive logic, which we elaborate on more in the next chapter, an implication is just a quantification over a proof, where the quantified variable is never used. It generally makes more sense to refer to implication hypotheses by number than by name, and Coq treats our quantifier over an unused variable as an implication in determining the proper behavior.)
*)
[Empty_set]には要素がないので、この型の要素があるという事実は、あらゆることを含意します。
証明の中で[destruct x]ではなく[destruct 1]を使っているのは、限量化された変数のうち使用しないものが格下げされて数字で参照されるようになるからです。
（これには限量化子と含意の統一した扱いに関係した正当な理由があります。
含意とは、少なくともCoqの構成的論理（constructive logic、次章で詳しく説明します）の基盤においては証明に対する限量化にすぎず、その証明において限量化された変数が使われることはありません。
一般に、含意における仮説は、変数名ではなく数字で参照するほうが理にかなっています。
Coqは、適切な挙動を決定するにあたり、使用されない変数に対する限量化子を含意として扱います。）
(*
We can see the induction principle that made this proof so easy:
*)
さきほどの証明が簡単にできたのは、次のようにして確認できる帰納法の原理のおかげです。
*)
Check Empty_set_ind.
(** [Empty_set_ind : forall (P : Empty_set -> Prop) (e : Empty_set), P e] *)
(**
(* %\smallskip{}%In other words, any predicate over values from the empty set holds vacuously of every such element. In the last proof, we chose the predicate [(fun _ : Empty_set => 2 + 2 = 5)].
*)
%\smallskip{}%要するに、空集合から取ってきた値に対しては、どんな述語も自明に満たされるということです。(* 良いいいまわしを思いつかない-nobsun / "holds vacuously ..."は「自明に満たされる」で（TaPLの訳のときの"satisfied vacuously"の訳を参考にしました） -kshikano *)
さきほどの証明では、述語として[(fun _ : Empty_set => 2 + 2 = 5)]を選びました。
(*
We can also apply this get-out-of-jail-free card programmatically. Here is a lazy way of converting values of [Empty_set] to values of [unit]:
*)
この魔法の切り札は、実際のプログラミングで応用することもできます。
以下に、[Empty_set]の値を[unit]の値に変換する横着な方法を示します。
*)
Definition e2u (e : Empty_set) : unit := match e with end.
(**
(* We employ [match] pattern matching as in the last chapter. Since we match on a value whose type has no constructors, there is no need to provide any branches. It turns out that [Empty_set] is the Curry-Howard equivalent of [False]. As for why [Empty_set] starts with a capital letter and not a lowercase letter like [unit] does, we must refer the reader to the authors of the Coq standard library, to which we try to be faithful.
*)
この定義では、前章でパターンマッチに使った[match]を採用しています。
構成子を持たない型の値に対してパターンマッチをしているので、ほかの選択肢は必要ありません。
[Empty_set]はCurry-Howard対応により[False]と同等であることがわかります。
[unit]と違って[Empty_set]の先頭が大文字である理由は、Coqの標準ライブラリの作者に聞いてもらうしかありません。
本書はCoqの標準ライブラリに忠実に従っているだけです。
%\medskip%
(*
Moving up the ladder of complexity, we can define the Booleans:%\index{Gallina terms!bool}\index{Gallina terms!true}\index{Gallina terms!false}%
*)
今度は複雑なほうへ話を進めましょう。論理値は次のように定義できます。%\index{Gallinaこう@Gallina項!bool}\index{Gallinaこう@Gallina項!true}\index{Gallinaこう@Gallina項!false}%
*)
Inductive bool : Set :=
| true
| false.
(**
(*
We can use less vacuous pattern matching to define Boolean negation.%\index{Gallina terms!negb}%
*)
それほど自明ではないパターンマッチを使って論理否定を定義できます。%\index{Gallinaこう@Gallina項!negb}%
*)
Definition negb (b : bool) : bool :=
match b with
| true => false
| false => true
end.
(**
(*
An alternative definition desugars to the above, thanks to an %\index{Gallina terms!if}%[if] notation overloaded to work with any inductive type that has exactly two constructors:
*)
ちょうど二つの構成子を持つ任意の帰納型に対して使えるようにオーバーロードされた[if]記法%\index{Gallinaこう@Gallina項!if}%を使って、上の定義の構文糖衣を剥がすこともできます。
*)
Definition negb' (b : bool) : bool :=
if b then false else true.
(**
(*
We might want to prove that [negb] is its own inverse operation.
*)
[negb]の逆演算が[negb]になることは証明しておきたいところです。
*)
Theorem negb_inverse : forall b : bool, negb (negb b) = b.
(* begin thide *)
destruct b.
(**
(*
After we case-analyze on [b], we are left with one subgoal for each constructor of [bool].
*)
[b]に関する場合分けをすべて調べると、[bool]の構成子ごとにサブゴールが一つずつ残ります。
[[
2 subgoals
============================
negb (negb true) = true
subgoal 2 is
negb (negb false) = false
]]
(*
The first subgoal follows by Coq's rules of computation, so we can dispatch it easily:
*)
最初のサブゴールはCoqの計算規則から示せるので、簡単に片付きます。
*)
reflexivity.
(**
(*
Likewise for the second subgoal, so we can restart the proof and give a very compact justification.%\index{Vernacular commands}%
*)
2つめのサブゴールも同様なので、証明を始めから再開して以下の簡潔な一行で証明を終わらせられます。%\index{Vernacularこまんど@Vernacularコマンド!Restart}%
(* いけぶち：「正当化」は日本語として不自然に感じた。うまい訳は思い付かなかったので意訳にしてみた。 *)
*)
Restart.
destruct b; reflexivity.
Qed.
(* end thide *)
(**
(*
Another theorem about Booleans illustrates another useful tactic.%\index{tactics!discriminate}%
*)
論理値に関する別の定理を使って、便利なタクティクをもう一つ紹介しましょう。%\index{たくてぃく@タクティク!discriminate}%
*)
Theorem negb_ineq : forall b : bool, negb b <> b.
(* begin thide *)
destruct b; discriminate.
Qed.
(* end thide *)
(**
(*
The [discriminate] tactic is used to prove that two values of an inductive type are not equal, whenever the values are formed with different constructors. In this case, the different constructors are [true] and [false].
*)
[discriminate]タクティクを使うと、ある帰納型の二つの値は、それらが別々の構成子で形成される場合には常に等しくない、ということを証明できます。
この場合には[true]と[false]が別々の構成子です。
(*
At this point, it is probably not hard to guess what the underlying induction principle for [bool] is.
*)
ここまでくれば、[bool]に対する帰納法の原理がどのようなものか、簡単に推測できるでしょう。
*)
Check bool_ind.
(** [bool_ind : forall P : bool -> Prop, P true -> P false -> forall b : bool, P b] *)
(**
(*
%\smallskip{}%That is, to prove that a property describes all [bool]s, prove that it describes both [true] and [false].
*)
%\smallskip{}%すなわち、すべての[bool]値についてある性質が成り立つことを証明するには、その性質が[true]と[false]の両方で成り立つことを証明すればよいということです。
(*
There is no interesting Curry-Howard analogue of [bool]. Of course, we can define such a type by replacing [Set] by [Prop] above, but the proposition we arrive at is not very useful. It is logically equivalent to [True], but it provides two indistinguishable primitive proofs, [true] and [false]. In the rest of the chapter, we will skip commenting on Curry-Howard versions of inductive definitions where such versions are not interesting.
*)
[bool]のCurry-Howard対応版はあまり面白くありません。
もちろん、上述の定義の[Set]を[Prop]に置き換えた型を定義することは可能です。しかし、それで得られる命題にあまり使い手はありません。
これは論理的には[True]に相当しますが、それによって得られる[true]と[false]の原始的な二つの証明は区別が不可能です。(* ここは意味がよくわからない-nobsun *)
以降では、帰納的な定義のCurry-Howard対応版について、このようにあまり意味がないものについては特に言及しないことにします。
*)
(**
(*
* Simple Recursive Types
*)
* 単純再帰型
*)
(**
(*
The natural numbers are the simplest common example of an inductive type that actually deserves the name.%\index{Gallina terms!nat}\index{Gallina terms!O}\index{Gallina terms!S}%
*)
帰納型のもっとも単純な例として一般的なのは自然数です。文字通り、もっとも自然な例といえるでしょう。%\index{Gallinaこう@Gallina項!nat}\index{Gallinaこう@Gallina項!O}\index{Gallinaこう@Gallina項!S}%
*)
Inductive nat : Set :=
| O : nat
| S : nat -> nat.
(**
(*
The constructor [O] is zero, and [S] is the successor function, so that [0] is syntactic sugar for [O], [1] for [S O], [2] for [S (S O)], and so on.
*)
構成子[O]はゼロ、[S]は後者関数です。したがって、[0]は[O]の構文糖衣、[1]は[S O]の構文糖衣、[2]は[S (S O)]の構文糖衣といった具合になります。
(*
Pattern matching works as we demonstrated in the last chapter:%\index{Gallina terms!pred}%
*)
前章で見たようにパターンマッチができます。
*)
Definition isZero (n : nat) : bool :=
match n with
| O => true
| S _ => false
end.
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(**
(*
We can prove theorems by case analysis with [destruct] as for simpler inductive types, but we can also now get into genuine inductive theorems. First, we will need a recursive function, to make things interesting.%\index{Gallina terms!plus}%
*)
比較的単純な帰納型なので[destruct]による場合分けを使って定理を証明することも可能ですが、ここでは正真正銘の帰納的な定理を考えてみましょう。
話を面白くするために、まずは再帰関数が必要です。
*)
Fixpoint plus (n m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(**
(*
Recall that [Fixpoint] is Coq's mechanism for recursive function definitions. Some theorems about [plus] can be proved without induction.
*)
[Fixpoint]は、Coqで再帰関数を定義する仕組みでしたね。
[plus]に関する定理には、帰納法を使わずに証明できるものがあります。
*)
Theorem O_plus_n : forall n : nat, plus O n = n.
(* begin thide *)
intro; reflexivity.
Qed.
(* end thide *)
(**
(*
Coq's computation rules automatically simplify the application of [plus], because unfolding the definition of [plus] gives us a [match] expression where the branch to be taken is obvious from syntax alone. If we just reverse the order of the arguments, though, this no longer works, and we need induction.
*)
[plus]の定義を展開すると、採用される選択肢が構文だけから明らかな[match]式が得られるので、[plus]の適用はCoqの計算規則によって自動的に単純化されます。
これは引数の順序を逆にすると機能しなくなり、帰納法が必要になります。
*)
Theorem n_plus_O : forall n : nat, plus n O = n.
(* begin thide *)
induction n.
(**
(*
Our first subgoal is [plus O O = O], which _is_ trivial by computation.
*)
最初のサブゴールは[plus O O = O]で、この計算は_[自明]_です。
*)
reflexivity.
(**
(*
Our second subgoal requires more work and also demonstrates our first inductive hypothesis.
*)
二つめのサブゴールにはもう少し手がかかります。これは帰納法の仮説の最初の例でもあります。
[[
n : nat
IHn : plus n O = n
============================
plus (S n) O = S n
]]
(*
We can start out by using computation to simplify the goal as far as we can.%\index{tactics!simpl}%
*)
このゴールを計算でできるだけ単純化することから始めましょう。%\index{たくてぃくす@タクティクス!simpl}%
*)
simpl.
(**
(*
Now the conclusion is [S (plus n O) = S n]. Using our inductive hypothesis:
*)
これにより結論は[S (plus n O) = S n]となります。
ここで帰納法の仮説を使います。
*)
rewrite IHn.
(**
(*
%\noindent{}%...we get a trivial conclusion [S n = S n].
*)
%\noindent{}%すると自明な結論[S n = S n]が得られます。
*)
reflexivity.
(**
(*
Not much really went on in this proof, so the [crush] tactic from the [CpdtTactics] module can prove this theorem automatically.
*)
この証明は、それほど手がかかるものではありませんでした。
そのため、[CpdtTactics]モジュールの[crush]タクティクを使ってこの定理を自動的に証明できます。
*)
Restart.
induction n; crush.
Qed.
(* end thide *)
(**
(*
We can check out the induction principle at work here:
*)
ここで使われる帰納法の原理は次のようにして確認できます。
*)
Check nat_ind.
(** %\vspace{-.15in}% [[
nat_ind : forall P : nat -> Prop,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
(*
Each of the two cases of our last proof came from the type of one of the arguments to [nat_ind]. We chose [P] to be [(fun n : nat => plus n O = n)]. The first proof case corresponded to [P O] and the second case to [(forall n : nat, P n -> P (S n))]. The free variable [n] and inductive hypothesis [IHn] came from the argument types given here.
*)
先ほどの証明における二つの場合分けは、それぞれ、[nat_ind]に対する引数のうちの一つが持つ型に対応しています。
[P]を[(fun n : nat => plus n O = n)]としましょう。
証明の場合分けのうち一つめは[P O]に対応し、二つめは[(forall n : nat, P n -> P (S n))]に対応します。
自由変数[n]および帰納法の仮説[IHn]は、これら引数の型に由来するのです。
(*
Since [nat] has a constructor that takes an argument, we may sometimes need to know that that constructor is injective.%\index{tactics!injection}\index{tactics!trivial}%
*)
[nat]には、引数を一つとる構成子があります。
この構成子が単射（injective）であることは確認しておきたいものです。%\index{たくてぃくす@タクティクス!injection}\index{たくてぃくす@タクティクス!trivial}%
*)
Theorem S_inj : forall n m : nat, S n = S m -> n = m.
(* begin thide *)
injection 1; trivial.
Qed.
(* end thide *)
(**
(*
The [injection] tactic refers to a premise by number, adding new equalities between the corresponding arguments of equated terms that are formed with the same constructor. We end up needing to prove [n = m -> n = m], so it is unsurprising that a tactic named [trivial] is able to finish the proof. This tactic attempts a variety of single proof steps, drawn from a user-specified database that we will later see how to extend.
*)
[injection]タクティクは、数字で指定された前提を参照し、等号の左右にある同じ構成子で構成された項について、対応する引数間の新しい同等性を追加します。(* equalities が複数形なのはなぜ-nobsun *)
結果的に[n = m -> n = m]を証明することになるので、その名も[trivial]というタクティクで証明を完了できます。
この[trivial]タクティクは、ユーザが指定したデータベース（のちほど拡張方法を説明します）にあるさまざまな単一の証明ステップを試します。
(*
There is also a very useful tactic called %\index{tactics!congruence}%[congruence] that can prove this theorem immediately. The [congruence] tactic generalizes [discriminate] and [injection], and it also adds reasoning about the general properties of equality, such as that a function returns equal results on equal arguments. That is, [congruence] is a%\index{theory of equality and uninterpreted functions}% _complete decision procedure for the theory of equality and uninterpreted functions_, plus some smarts about inductive types.
*)
この定理を一発で証明できる%\index{たくてぃくす@タクティクス!congruence}%[congruence]という便利なタクティクもあります。
[congruence]タクティクは、[discriminate]および[injection]を一般化し、さらに「関数は等しい引数について等しい結果を返す」といった同等性についての一般的な性質に対する論証を追加してくれます。
すなわち、[congruence]は%\index{みかいしゃくかんすうとどういつせいのりろん@未解釈関数と同一性の理論}%、_[未解釈関数と同一性の理論に対する完全な決定手続き]_に帰納型に関するさまざまな機能を追加したタクティクだといえます。
(* the theory of equality and uninterpreted functions は何のことか？-nobsun *)
(* いけぶち：the theory of equality and uninterpreted functions は論理記号が = のみで、項が(symbolicな)関数(や定数)から成るような公理の集合のことだと思います。 *)
%\medskip%
(*
We can define a type of lists of natural numbers.
*)
自然数のリストの型は以下のように定義できます。
*)
Inductive nat_list : Set :=
| NNil : nat_list
| NCons : nat -> nat_list -> nat_list.
(**
(*
Recursive definitions over [nat_list] are straightforward extensions of what we have seen before.
*)
すでに見た例を素直に拡張することで[nat_list]上の再帰的定義が得られます。
*)
Fixpoint nlength (ls : nat_list) : nat :=
match ls with
| NNil => O
| NCons _ ls' => S (nlength ls')
end.
Fixpoint napp (ls1 ls2 : nat_list) : nat_list :=
match ls1 with
| NNil => ls2
| NCons n ls1' => NCons n (napp ls1' ls2)
end.
(**
(*
Inductive theorem proving can again be automated quite effectively.
*)
やはり前と同様に、帰納的な定理の証明を効率的に自動化できます。
*)
Theorem nlength_napp : forall ls1 ls2 : nat_list, nlength (napp ls1 ls2)
= plus (nlength ls1) (nlength ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
Check nat_list_ind.
(** %\vspace{-.15in}% [[
nat_list_ind
: forall P : nat_list -> Prop,
P NNil ->
(forall (n : nat) (n0 : nat_list), P n0 -> P (NCons n n0)) ->
forall n : nat_list, P n
]]
%\medskip%
(*
In general, we can implement any "tree" type as an inductive type. For example, here are binary trees of naturals.
*)
一般に、「木」（tree）の型はすべて帰納型として実装可能です。
たとえば、自然数の二分木は以下のように実装できます。
*)
Inductive nat_btree : Set :=
| NLeaf : nat_btree
| NNode : nat_btree -> nat -> nat_btree -> nat_btree.
(**
(*
Here are two functions whose intuitive explanations are not so important. The first one computes the size of a tree, and the second performs some sort of splicing of one tree into the leftmost available leaf node of another.
*)
ここで関数を二つ用意します。
一つは木のサイズを計算する関数で、もう一つは一方の木を他方の木の最も左にある葉に接合する関数ですが、いずれも直観的な説明はあまり重要ではありません。
*)
Fixpoint nsize (tr : nat_btree) : nat :=
match tr with
| NLeaf => S O
| NNode tr1 _ tr2 => plus (nsize tr1) (nsize tr2)
end.
Fixpoint nsplice (tr1 tr2 : nat_btree) : nat_btree :=
match tr1 with
| NLeaf => NNode tr2 O NLeaf
| NNode tr1' n tr2' => NNode (nsplice tr1' tr2) n tr2'
end.
Theorem plus_assoc : forall n1 n2 n3 : nat, plus (plus n1 n2) n3 = plus n1 (plus n2 n3).
(* begin thide *)
induction n1; crush.
Qed.
(* end thide *)
Hint Rewrite n_plus_O plus_assoc.
Theorem nsize_nsplice : forall tr1 tr2 : nat_btree, nsize (nsplice tr1 tr2)
= plus (nsize tr2) (nsize tr1).
(* begin thide *)
induction tr1; crush.
Qed.
(* end thide *)
(**
(*
It is convenient that these proofs go through so easily, but it is still useful to look into the details of what happened, by checking the statement of the tree induction principle.
*)
こうした証明が簡単にできるのは便利なことですが、木の帰納法の原理がどのように提示されているか確認することで、その動作も詳しく調べておいたほうがいいでしょう。
*)
Check nat_btree_ind.
(** %\vspace{-.15in}% [[
nat_btree_ind
: forall P : nat_btree -> Prop,
P NLeaf ->
(forall n : nat_btree,
P n -> forall (n0 : nat) (n1 : nat_btree), P n1 -> P (NNode n n0 n1)) ->
forall n : nat_btree, P n
]]
(*
We have the usual two cases, one for each constructor of [nat_btree].
*)
いつものように二つの場合分けになっており、それぞれの場合分けが[nat_btree]の構成子に対応していることがわかります。
*)
(**
(*
* Parameterized Types
*)
* パラメータ付き型
(* parameterized type の定訳は？-nobsun *)
(* いけぶち：とりあえずよく使われる「-付き」にしてみた *)
*)
(**
(*
We can also define %\index{polymorphism}%polymorphic inductive types, as with algebraic datatypes in Haskell and ML.%\index{Gallina terms!list}\index{Gallina terms!Nil}\index{Gallina terms!Cons}\index{Gallina terms!length}\index{Gallina terms!app}%
*)
HaskellやMLにおける代数データ型と同様、多相的な帰納型も定義できます。%\index{たそうせい@多相性}%
%\index{Gallinaこう@Gallina項!list}\index{Gallinaこう@Gallina項!Nil}\index{Gallinaこう@Gallina項!Cons}\index{Gallinaこう@Gallina項!length}\index{Gallinaこう@Gallina項!app}%
*)
(* Set Asymmetric Patterns. が必要なので、脚注をいれたほうがよさそう -kshikano *)
Inductive list (T : Set) : Set :=
| Nil : list T
| Cons : T -> list T -> list T.
Fixpoint length T (ls : list T) : nat :=
match ls with
| Nil => O
| Cons _ ls' => S (length ls')
end.
Fixpoint app T (ls1 ls2 : list T) : list T :=
match ls1 with
| Nil => ls2
| Cons x ls1' => Cons x (app ls1' ls2)
end.
Theorem length_app : forall T (ls1 ls2 : list T), length (app ls1 ls2)
= plus (length ls1) (length ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
(**
(*
There is a useful shorthand for writing many definitions that share the same parameter, based on Coq's%\index{sections}\index{Vernacular commands!Section}\index{Vernacular commands!Variable}% _section_ mechanism. The following block of code is equivalent to the above:
*)
Coqには、同じパラメータを共有するさまざまな定義に対する便利な省略記法があります。これは、Coqの_[セクション]_（[Section]）という仕組みを利用したものです。
%\index{せくしょん@セクション}\index{Vernacularこんまんど@Vernacularコマンド!Section}\index{Vernacularこまんど@Vernacularコマンド!Variable}
上記のコードブロックは下記のように書いても同じです。
*)
(* begin hide *)
Reset list.
(* end hide *)
Section list.
Variable T : Set.
Inductive list : Set :=
| Nil : list
| Cons : T -> list -> list.
Fixpoint length (ls : list) : nat :=
match ls with
| Nil => O
| Cons _ ls' => S (length ls')
end.
Fixpoint app (ls1 ls2 : list) : list :=
match ls1 with
| Nil => ls2
| Cons x ls1' => Cons x (app ls1' ls2)
end.
Theorem length_app : forall ls1 ls2 : list, length (app ls1 ls2)
= plus (length ls1) (length ls2).
(* begin thide *)
induction ls1; crush.
Qed.
(* end thide *)
End list.
Arguments Nil [T].
(**
(*
After we end the section, the [Variable]s we used are added as extra function parameters for each defined identifier, as needed. With an [Arguments]%~\index{Vernacular commands!Arguments}% command, we ask that [T] be inferred when we use [Nil]; Coq's heuristics already decided to apply a similar policy to [Cons], because of the [Set Implicit Arguments]%~\index{Vernacular commands!Set Implicit Arguments}% command elided at the beginning of this chapter. We verify that our definitions have been saved properly using the [Print] command, a cousin of [Check] which shows the definition of a symbol, rather than just its type.
*)
セクションで使った[Variable]は、セクションを[End]で終端したあと、定義された各識別子に対する追加の関数パラメータとして付加されます。
[Arguments]%~\index{Vernacularこまんど@Vernacularコマンド!Arguments}%コマンドを使って、[Nil]を使用したときに[T]が推論されるようにしています。
[Cons]に対しては、Coqのヒューリスティクスによって、すでに同様の方針が適用されるようになっています。
これは、本章のソースファイルの冒頭に、[Set Implicit Arguments]%~\index{Vernacularこまんど@Vernacularコマンド!Set Implicit Arguments}%コマンドがあるからです。
定義が適切に保存されたかどうかは、[Print]コマンドを使って確認します。
[Print]コマンドは、[Check]コマンドに似ていますが、シンボルの型だけではなく定義も表示します。
*)
Print list.
(** %\vspace{-.15in}% [[
Inductive list (T : Set) : Set :=
Nil : list T | Cons : T -> list T -> list T
]]
(*
The final definition is the same as what we wrote manually before. The other elements of the section are altered similarly, turning out exactly as they were before, though we managed to write their definitions more succinctly.
*)
このように、[list]の最終的な定義は以前に手書きしたものと同じです。
[list]以外の定義も、セクションの中では前より少し簡潔に書けているにもかかわらず、以前の定義とぴったり同じになっていることがわかります。
*)
Check length.
(** %\vspace{-.15in}% [[
length
: forall T : Set, list T -> nat
]]
(*
The parameter [T] is treated as a new argument to the induction principle, too.
*)
パラメータ[T]は、帰納法の原理に対する新しい引数としても扱われます。
*)
Check list_ind.
(** %\vspace{-.15in}% [[
list_ind
: forall (T : Set) (P : list T -> Prop),
P (Nil T) ->
(forall (t : T) (l : list T), P l -> P (Cons t l)) ->
forall l : list T, P l
]]
(*
Thus, despite a very real sense in which the type [T] is an argument to the constructor [Cons], the inductive case in the type of [list_ind] (i.e., the third line of the type) includes no quantifier for [T], even though all of the other arguments are quantified explicitly. Parameters in other inductive definitions are treated similarly in stating induction principles.
*)
そのため、構成子[Cons]への引数として型[T]には確かに意味があるのですが、[list_ind]の型における帰納部（すなわち上記の3行め）では[T]に限量子が付いていません。
それ以外のすべての引数は明示的に限量化されているにもかかわらず、[T]は限量化されていないのです。
他の帰納的な定義におけるパラメータは、帰納法の原理で表明されているとおりに扱われます。
*)
(**
(*
* Mutually Inductive Types
*)
* 相互帰納型
*)
(**
(*
We can define inductive types that refer to each other:
*)
相互に参照する帰納型を以下のように定義できます。
*)
Inductive even_list : Set :=
| ENil : even_list
| ECons : nat -> odd_list -> even_list
with odd_list : Set :=
| OCons : nat -> even_list -> odd_list.
Fixpoint elength (el : even_list) : nat :=
match el with
| ENil => O
| ECons _ ol => S (olength ol)
end
with olength (ol : odd_list) : nat :=
match ol with
| OCons _ el => S (elength el)
end.
Fixpoint eapp (el1 el2 : even_list) : even_list :=
match el1 with
| ENil => el2
| ECons n ol => ECons n (oapp ol el2)
end
with oapp (ol : odd_list) (el : even_list) : odd_list :=
match ol with
| OCons n el' => OCons n (eapp el' el)
end.
(**
(*
Everything is going roughly the same as in past examples, until we try to prove a theorem similar to those that came before.
*)
大まかに見れば、いずれもこれまでの例と同じです。しかし、これまでと同じ要領で定理を証明しようとすると、様子が変わります。
*)
Theorem elength_eapp : forall el1 el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2).
(* begin thide *)
induction el1; crush.
(** One goal remains: [[
n : nat
o : odd_list
el2 : even_list
============================
S (olength (oapp o el2)) = S (plus (olength o) (elength el2))
]]
(*
We have no induction hypothesis, so we cannot prove this goal without starting another induction, which would reach a similar point, sending us into a futile infinite chain of inductions. The problem is that Coq's generation of [T_ind] principles is incomplete. We only get non-mutual induction principles generated by default.
*)
帰納法の仮説がないので、このゴールを証明するには別の帰納法から始めるしかありません。
しかし、別の帰納法から始めても同じような状況になるので、何も得られないまま帰納法の無限連鎖に陥ります。
問題なのは、Coqによる帰納法の原理[T_ind]の生成が不完全なことです。
デフォルトでは、相互参照がない帰納法の原理しか生成されないのです。
*)
Abort.
Check even_list_ind.
(** %\vspace{-.15in}% [[
even_list_ind
: forall P : even_list -> Prop,
P ENil ->
(forall (n : nat) (o : odd_list), P (ECons n o)) ->
forall e : even_list, P e
]]
(*
We see that no inductive hypotheses are included anywhere in the type. To get them, we must ask for mutual principles as we need them, using the %\index{Vernacular commands!Scheme}%[Scheme] command.
*)
この型には帰納法の仮定がどこにも含まれていません。
帰納法の仮定を手に入れるには、%\index{Vernacularこまんど@Vernacularコマンド!Scheme}%[Scheme]コマンドを使うことで、必要に応じて相互帰納法の原理を要求します。
*)
Scheme even_list_mut := Induction for even_list Sort Prop
with odd_list_mut := Induction for odd_list Sort Prop.
(**
(*
This invocation of [Scheme] asks for the creation of induction principles [even_list_mut] for the type [even_list] and [odd_list_mut] for the type [odd_list]. The [Induction] keyword says we want standard induction schemes, since [Scheme] supports more exotic choices. Finally, [Sort Prop] establishes that we really want induction schemes, not recursion schemes, which are the same according to Curry-Howard, save for the [Prop]/[Set] distinction.
*)
このように[Scheme]を呼び出すことで、型[even_list]の帰納法の原理[even_list_mut]と、型[odd_list]の帰納法の原理[odd_list_mut]を作るように指示しています。
[Induction]キーワードを指定しているのは、標準の帰納法スキームを要求するためです。[Scheme]キーワードは、かなり奇妙な選択肢にも対応しているので、この[Induction]キーワードが必要になります。
最後に[Srot Prop]コマンドを指定しているのは、いま要求しているのが帰納法のスキームであって再帰のスキームではないことを確実にするためです。
Curry-Howard対応により、帰納法のスキームと再帰のスキームは、[Prop]と[Set]の違いを除けば同じになります。
*)
Check even_list_mut.
(** %\vspace{-.15in}% [[
even_list_mut
: forall (P : even_list -> Prop) (P0 : odd_list -> Prop),
P ENil ->
(forall (n : nat) (o : odd_list), P0 o -> P (ECons n o)) ->
(forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) ->
forall e : even_list, P e
]]
(*
This is the principle we wanted in the first place.
*)
これが、そもそも必要としていた帰納法の原理になります。
(*
The [Scheme] command is for asking Coq to generate particular induction schemes that are mutual among a set of inductive types (possibly only one such type, in which case we get a normal induction principle). In a sense, it generalizes the induction scheme generation that goes on automatically for each inductive definition. Future Coq versions might make that automatic generation smarter, so that [Scheme] is needed in fewer places. In a few sections, we will see how induction principles are derived theorems in Coq, so that there is not actually any need to build in _any_ automatic scheme generation.
*)
[Scheme]コマンドは、いくつかの帰納型の集合において相互に関連するような帰納法のスキームを具体的に生成するよう、Coqに指示するためものです（帰納型が1つだけの場合もあり、その場合には通常の帰納法の原理が得られます）。
Coqでは帰納的な定義ごとに帰納法のスキームが自動生成されますが、これはその一般化だといえるでしょう。
将来のCoqのバージョンでは、この自動生成がもっとスマートになって、[Scheme]コマンドが必要な場面が少なくなるかもしれません。
この後の節で説明するように、帰納法の原理はCoqにおいて導出される定理です。
したがって、自動的なスキーム生成を組み込む必要は、実際のところどこにもありません。
(*
There is one more wrinkle left in using the [even_list_mut] induction principle: the [induction] tactic will not apply it for us automatically. It will be helpful to look at how to prove one of our past examples without using [induction], so that we can then generalize the technique to mutual inductive types.%\index{tactics!apply}%
*)
帰納法の原理[even_list_mut]には、使用にあたって困ったことがもう1つあります。
[induction]タクティクによって自動的に適用されないのです。
以前の例を[induction]を使わないで証明する方法を見てみると、相互帰納型への一般化に役立つでしょう。%\index{たくてぃくす@タクティクス!apply}%
*)
Theorem n_plus_O' : forall n : nat, plus n O = n.
apply nat_ind.
(**
(*
Here we use [apply], which is one of the most essential basic tactics. When we are trying to prove fact [P], and when [thm] is a theorem whose conclusion can be made to match [P] by proper choice of quantified variable values, the invocation [apply thm] will replace the current goal with one new goal for each premise of [thm].
*)
ここで使っている[apply]は、基本的なタクティクのなかでも特に本質的なものです。
[P]を証明しようとしているとき、限量化された変数の値をうまく選ぶことで帰結を[P]にマッチするようにできる定理[thm]があれば、[apply thm]を呼び出すことで、[thm]の仮定のそれぞれに対する新たなゴールへと現在のゴールを置き換えられます。
(*
This use of [apply] may seem a bit _too_ magical. To better see what is going on, we use a variant where we partially apply the theorem [nat_ind] to give an explicit value for the predicate that gives our induction hypothesis.
*)
このような[apply]の使い方は黒魔術に見えるかもしれません。
背景を理解するために、帰納法の仮定を与えてくれる述語に明示的な値を渡すことで定理[nat_ind]を部分適用したものを使ってみましょう。
*)
Undo.
apply (nat_ind (fun n => plus n O = n)); crush.
Qed.
(**
(*
From this example, we can see that [induction] is not magic. It only does some bookkeeping for us to make it easy to apply a theorem, which we can do directly with the [apply] tactic.
*)
この例を見れば、[induction]が魔法ではないことがわかります。
[induction]は、[apply]タクティクを使って定理を直接簡単に適用できるように、帳簿のようなものを付けてくれているだけなのです。
(*
This technique generalizes to our mutual example:
この技法を相互帰納型の例に一般化しましょう。
*)
*)
Theorem elength_eapp : forall el1 el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2).
apply (even_list_mut
(fun el1 : even_list => forall el2 : even_list,
elength (eapp el1 el2) = plus (elength el1) (elength el2))
(fun ol : odd_list => forall el : even_list,
olength (oapp ol el) = plus (olength ol) (elength el))); crush.
Qed.
(* end thide *)
(**
(*
We simply need to specify two predicates, one for each of the mutually inductive types. In general, it is not a good idea to assume that a proof assistant can infer extra predicates, so this way of applying mutual induction is about as straightforward as we may hope for.
*)
必要なのは、相互帰納型のそれぞれに、対応する二つの述語を指定することだけです。
証明支援器が余分な述語を推論してくれることは一般に望めないので、この方法で相互帰納を適用するのがもっとも直接的でしょう。
*)
(**
(*
* Reflexive Types
*)
* 反射的型
*)
(**
(*
A kind of inductive type called a _reflexive type_ includes at least one constructor that takes as an argument _a function returning the same type we are defining_. One very useful class of examples is in modeling variable binders. Our example will be an encoding of the syntax of first-order logic. Since the idea of syntactic encodings of logic may require a bit of acclimation, let us first consider a simpler formula type for a subset of propositional logic. We are not yet using a reflexive type, but later we will extend the example reflexively.
*)
「定義している型と同じ型を返す関数」を引数として取る構成子を、少くとも一つ持つような帰納型のことを、_[反射的型]_と呼びます。
反射的型の実用的な例として、変数束縛のモデリングが挙げられます。
ここでは、一階述語論理の構文を符号化する例を紹介します。
論理の構文を符号化するという考え方には少しばかり慣れが必要でしょうから、より単純な、命題論理のサブセットに対する論理式型[pformula]から考えてみましょう。
まだ反射的型は使いませんが、あとでこの例を反射的型へと拡張します。
*)
Inductive pformula : Set :=
| Truth : pformula
| Falsehood : pformula
| Conjunction : pformula -> pformula -> pformula.
(* begin hide *)
(* begin thide *)
Definition prod' := prod.
(* end thide *)
(* end hide *)
(**
(*
A key distinction here is between, for instance, the _syntax_ [Truth] and its _semantics_ [True]. We can make the semantics explicit with a recursive function. This function uses the infix operator %\index{Gallina operators!/\textbackslash}%[/\], which desugars to instances of the type family %\index{Gallina terms!and}%[and] from the standard library. The family [and] implements conjunction, the [Prop] Curry-Howard analogue of the usual pair type from functional programming (which is the type family %\index{Gallina terms!prod}%[prod] in Coq's standard library).
*)
ここで肝心なのは、_[構文]_と_[意味]_をはっきり区別することです。
たとえば、[Truth]は構文であり、その意味は[True]です。
意味を明らかにするには、次のような再帰関数が使えます。
この関数の定義にある[/\]という中置演算子%\index{Gallinaえんざんし@Gallina演算子!/\textbackslash}%は、標準ライブラリにある型族[and]のインスタンス%\index{Gallinaこう@Gallina項!and}%に展開されます。
型族[and]は、連言の実装です。
連言の[Prop]にCurry-Howard対応するのは、関数プログラミングにおける通常のペア型です（Coqでは標準ライブラリにある型族%\index{Gallinaこう@Gallina項!prod}%[prod]に相当）。
*)
Fixpoint pformulaDenote (f : pformula) : Prop :=
match f with
| Truth => True
| Falsehood => False
| Conjunction f1 f2 => pformulaDenote f1 /\ pformulaDenote f2
end.
(**
(*
This is just a warm-up that does not use reflexive types, the new feature we mean to introduce. When we set our sights on first-order logic instead, it becomes very handy to give constructors recursive arguments that are functions.
*)
ここまではウォーミングアップです。これから紹介する新しい機能である反射的型は、この命題論理の論理式型の例ではまだ使っていません。
そこで次は一階述語論理の論理式型[formula]を考えてみましょう。
[formula]を返す関数を再帰的な引数として構成子に与えられると、次のようにして[formula]を簡単に定義できることがわかります。
*)
Inductive formula : Set :=
| Eq : nat -> nat -> formula
| And : formula -> formula -> formula
| Forall : (nat -> formula) -> formula.
(**
(*
Our kinds of formulas are equalities between naturals, conjunction, and universal quantification over natural numbers. We avoid needing to include a notion of "variables" in our type, by using Coq functions to encode the syntax of quantification. For instance, here is the encoding of [forall x : nat, x = x]:%\index{Vernacular commands!Example}%
*)
[formula]としてありうるのは、自然数の間の等号、連言、自然数に対する全称限量化です。(* equalityの訳語に迷う-nobsun *)
ここで、型から「変数」という概念が不要になっていることに注目してください。
限量化の構文は、Coqの関数を使って符号化します。
たとえば、[forall x : nat, x = x]は次のように符号化できます。%\index{Vernacularこまんど@Vernacularコマンド!Example}%
*)
Example forall_refl : formula := Forall (fun x => Eq x x).
(**
(*
We can write recursive functions over reflexive types quite naturally. Here is one translating our formulas into native Coq propositions.
*)
反射的型の上の再帰関数はとても自然に書けます。
たとえば、いま定義した[formula]型の論理式をCoqの命題に翻訳する再帰関数は次のように書けます。
*)
Fixpoint formulaDenote (f : formula) : Prop :=
match f with
| Eq n1 n2 => n1 = n2
| And f1 f2 => formulaDenote f1 /\ formulaDenote f2
| Forall f' => forall n : nat, formulaDenote (f' n)
end.
(**
(* We can also encode a trivial formula transformation that swaps the order of equality and conjunction operands. *)
論理式に対する単純な変換も符号化できます。
等号と連言の順序を変更する変換の例を次に示します。
*)
Fixpoint swapper (f : formula) : formula :=
match f with
| Eq n1 n2 => Eq n2 n1
| And f1 f2 => And (swapper f2) (swapper f1)
| Forall f' => Forall (fun n => swapper (f' n))
end.
(**
(*
It is helpful to prove that this transformation does not make true formulas false.
*)
この変換によって真が偽になることがないことを証明しておきましょう。
*)
Theorem swapper_preserves_truth : forall f, formulaDenote f -> formulaDenote (swapper f).
(* begin thide *)
induction f; crush.
Qed.
(* end thide *)
(**
(*
We can take a look at the induction principle behind this proof.
*)
この証明の背後にある帰納法の原理は次のように確認できます。
*)
Check formula_ind.
(** %\vspace{-.15in}% [[
formula_ind
: forall P : formula -> Prop,
(forall n n0 : nat, P (Eq n n0)) ->
(forall f0 : formula,
P f0 -> forall f1 : formula, P f1 -> P (And f0 f1)) ->
(forall f1 : nat -> formula,
(forall n : nat, P (f1 n)) -> P (Forall f1)) ->
forall f2 : formula, P f2
]]
(*
Focusing on the [Forall] case, which comes third, we see that we are allowed to assume that the theorem holds _for any application of the argument function [f1]_. That is, Coq induction principles do not follow a simple rule that the textual representations of induction variables must get shorter in appeals to induction hypotheses. Luckily for us, the people behind the metatheory of Coq have verified that this flexibility does not introduce unsoundness.
*)
[Forall]に関する場合分け（3つめの場合分け）に注目してみると、「引数である関数[f1]の任意の適用」に対して定理が成り立つことを仮定してよい、となっています。
つまり、Coqの帰納法の原理は、「帰納法に関する変数のテキスト上の見た目が常に帰納法の仮定によって短くなる」という単純な法則に従っているわけではないということです。
このような柔軟性があっても体系が不健全にならないことは、Coqのメタ定理の開発者たちが検証してくれています。
%\medskip%
(*
Up to this point, we have seen how to encode in Coq more and more of what is possible with algebraic datatypes in %\index{Haskell}%Haskell and %\index{ML}%ML. This may have given the inaccurate impression that inductive types are a strict extension of algebraic datatypes. In fact, Coq must rule out some types allowed by Haskell and ML, for reasons of soundness. Reflexive types provide our first good example of such a case; only some of them are legal.
*)
ここまでは、%\index{Haskell}%Haskellや%\index{ML}%MLの代数データ型でできることの多くをCoqで符号化する方法を見てきました。
そのため、帰納型とは代数データ型の拡張であるという不正確な印象を抱かせてしまったかもしれません。
実際には、HaskellやMLの代数データ型で許されているような型であっても、Coqでは排除が必要なものがあります。
これは健全性を維持するためです。
反射的型は、そのことを説明する最初の好例です。Coqでは、ある種の反射的型だけしか許されていません。
(*
Given our last example of an inductive type, many readers are probably eager to try encoding the syntax of %\index{lambda calculus}%lambda calculus. Indeed, the function-based representation technique that we just used, called%\index{higher-order abstract syntax}\index{HOAS|see{higher-order abstract syntax}}% _higher-order abstract syntax_ (HOAS)%~\cite{HOAS}%, is the representation of choice for lambda calculi in %\index{Twelf}%Twelf and in many applications implemented in Haskell and ML. Let us try to import that choice to Coq:
*)
読者のなかには、さきほどの帰納型の例を見て、%\index{らむだけいさん@λ計算}%λ計算の構文をエンコードしようとする人も多いでしょう。
さきほどの例で見たような、関数による表現技法は、_[高階抽象構文]_（HOAS、higher-order abstract syntax）%\index{こうかいちゅうしょうこうぶん@高階抽象構文}\index{HOAS|see{高階抽象構文}}%と呼ばれています%~\cite{HOAS}%。HOASは、%\index{Twelf}%Twelfをはじめ、HaskellやMLで実装されたアプリケーションにおけるλ計算の表現として採用されています。
この技法をCoqでも使ってみましょう。
*)
(* begin hide *)
(* begin thide *)
Inductive term : Set := App | Abs.
Reset term.
Definition uhoh := O.
(* end thide *)
(* end hide *)
(** [[
Inductive term : Set :=
| App : term -> term -> term
| Abs : (term -> term) -> term.
]]
<<
Error: Non strictly positive occurrence of "term" in "(term -> term) -> term"
>>
(*
We have run afoul of the%\index{strict positivity requirement}\index{positivity requirement}% _strict positivity requirement_ for inductive definitions, which says that the type being defined may not occur to the left of an arrow in the type of a constructor argument. It is important that the type of a constructor is viewed in terms of a series of arguments and a result, since obviously we need recursive occurrences to the lefts of the outermost arrows if we are to have recursive occurrences at all. Our candidate definition above violates the positivity requirement because it involves an argument of type [term -> term], where the type [term] that we are defining appears to the left of an arrow. The candidate type of [App] is fine, however, since every occurrence of [term] is either a constructor argument or the final result type.
*)
ここで抵触したのは、帰納的定義に対する_[厳密陽性要件]_（strict positivity requirement）という制限です%\index{げんみつようせいようけん@厳密陽性要件}\index{ようせいようけん@陽性要件}%。
厳密陽性要件では、定義しようとしている型が、構成子の引数の型において矢印の左側に出現してはいけないことになっています。
もし再帰的な出現があれば、一番外側の矢印の左側に再帰的な出現が明らかに必要なので、構成子の型は引数と結果の列として見ればよい、というのがポイントです。
上記の定義では、[term -> term]型という形で、いま定義しようとしている[term]型が矢印の左側に出現する引数が関与しており、これが陽性要件に違反します。
ただし、[App]の型は問題ありません。
[App]では、すべての[term]の出現が、構成子の引数か最終結果の型のいずれかだからです。
(*
Why must Coq enforce this restriction? Imagine that our last definition had been accepted, allowing us to write this function:
*)
なぜCoqにはこのような制限があるのでしょうか。
さきほどの定義が許容されるとどうなるか想像してみましょう。
以下の関数が書けることになります。
%\vspace{-.15in}%[[
Definition uhoh (t : term) : term :=
match t with
| Abs f => f t
| _ => t
end.
]]
(*
Using an informal idea of Coq's semantics, it is easy to verify that the application [uhoh (Abs uhoh)] will run forever. This would be a mere curiosity in OCaml and Haskell, where non-termination is commonplace, though the fact that we have a non-terminating program without explicit recursive function definitions is unusual.
*)
Coqの意味論について非形式的に考えてみると、[uho (Abs uho)]のような適用が無限ループになってしまうことが容易に確認できます。
明示的に再帰関数として定義されていない停止しないプログラムの存在は異常ですが、停止しないことが普通にあるOCamlやHaskellでは「だからどうした」という話かもしれません。
(*
%\index{termination checking}%For Coq, however, this would be a disaster. The possibility of writing such a function would destroy all our confidence that proving a theorem means anything. Since Coq combines programs and proofs in one language, we would be able to prove every theorem with an infinite loop.
*)
%\index{ていしせいけんさ@停止性検査}%しかし、Coqでこれを認めるとひどいことになります。
このような関数を書けてしまうようでは、定理を証明することに意味があるという私たちの信念が台無しです。
Coqでは、プログラムと証明が単一の言語で結び付いているので、無限ループですべての定理が証明できることになってしまいます。
(*
Nonetheless, the basic insight of HOAS is a very useful one, and there are ways to realize most benefits of HOAS in Coq. We will study a particular technique of this kind in the final chapter, on programming language syntax and semantics.
*)
それでもHOASに関する基本的な洞察はきわめて有用であり、CoqでHOASの利点のほとんどを実現する方法もあります。
最終章では、そのような具体的な技法について、プログラミング言語の構文と意味を研究することにします。
*)
(**
(*
* An Interlude on Induction Principles
*)
* 帰納法の原理についての補足
*)
(**
(*
As we have emphasized a few times already, Coq proofs are actually programs, written in the same language we have been using in our examples all along. We can get a first sense of what this means by taking a look at the definitions of some of the %\index{induction principles}%induction principles we have used. A close look at the details here will help us construct induction principles manually, which we will see is necessary for some more advanced inductive definitions.
*)
なんどか強調したように、Coqの証明はこれまでの例題で使ってきた言語と同じ言語で書かれており、実のところプログラムです。
その意味をしっかりと把握できるように、これまでに使用した%\index{きのうほうのげんり@帰納法の原理}%帰納法の原理をここで確認しておきましょう。
帰納的定義の応用例では、帰納法の原理を自分の手で構成することが必要になる場合もあります。
これまでに使った帰納法の原理をここでしっかり確認しておけば、自分の手で帰納法の原理の構成が必要になるときに役立ちます。
*)
Print nat_ind.
(** %\vspace{-.15in}%[[
nat_ind =
fun P : nat -> Prop => nat_rect P
: forall P : nat -> Prop,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
(*
We see that this induction principle is defined in terms of a more general principle, [nat_rect]. The <<rec>> stands for "recursion principle," and the <<t>> at the end stands for [Type].
*)
上記に示した帰納法の原理は、さらに一般的な帰納法の原理である[nat_rect]を用いて定義されていることがわかります。
[nat_rect]という原理の名前に出てくる<<rect>>は、先頭の<<rec>>は「再帰（recursion）原理」であることを、末尾の<<t>>は[Type]を表しています。
*)
Check nat_rect.
(** %\vspace{-.15in}% [[
nat_rect
: forall P : nat -> Type,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
(*
The principle [nat_rect] gives [P] type [nat -> Type] instead of [nat -> Prop]. This [Type] is another universe, like [Set] and [Prop]. In fact, it is a common supertype of both. Later on, we will discuss exactly what the significances of the different universes are. For now, it is just important that we can use [Type] as a sort of meta-universe that may turn out to be either [Set] or [Prop]. We can see the symmetry inherent in the subtyping relationship by printing the definition of another principle that was generated for [nat] automatically:
*)
[nat_rect]という原理によって与えられるのは、[nat -> Type]型の[P]であり、[nat -> Prop]型ではありません。
[Type]は、[Set]や[Prop]と同じく、一つの領域です。(* universe の訳語は「領域」でよいか-nobsun *)
実際には、[Set]と[Prop]の両者の上位型になっています。(* supertype の訳語は「上位型」でよいか-nobsun *)
領域が別であることにどんな意味があるのか、正確なところは後で説明します。
今のところ重要なのは、[Type]は[Set]か[Prop]のどちらにもなりうるメタ領域のようなものとして使えるということです。
[nat]用に自動生成された別の帰納法の原理の定義を表示してみれば、部分型付けの関係になっていることに伴う対称性を確認できます。
*)
Print nat_rec.
(** %\vspace{-.15in}%[[
nat_rec =
fun P : nat -> Set => nat_rect P
: forall P : nat -> Set,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
(*
This is identical to the definition for [nat_ind], except that we have substituted [Set] for [Prop]. For most inductive types [T], then, we get not just induction principles [T_ind], but also %\index{recursion principles}%recursion principles [T_rec]. We can use [T_rec] to write recursive definitions without explicit [Fixpoint] recursion. For instance, the following two definitions are equivalent:
*)
これは、[Prop]を[Set]に置き換えれば[nat_ind]の定義と同じです。
さらに、ほとんどの帰納型[T]に対し、[T_ind]という帰納法の原理だけでなく、[T_rec]という%\index{さいきのげんり@再帰の原理}%再帰の原理も手に入ります。
[T_rec]を使えば、[Fixpoint]を明示しなくても再帰的な定義を書けます。
たとえば、以下の二つの定義は同じです。
*)
Fixpoint plus_recursive (n : nat) : nat -> nat :=
match n with
| O => fun m => m
| S n' => fun m => S (plus_recursive n' m)
end.
Definition plus_rec : nat -> nat -> nat :=
nat_rec (fun _ : nat => nat -> nat) (fun m => m) (fun _ r m => S (r m)).
Theorem plus_equivalent : plus_recursive = plus_rec.
reflexivity.
Qed.
(**
(*
Going even further down the rabbit hole, [nat_rect] itself is not even a primitive. It is a functional program that we can write manually.
*)
さらに不思議の国の奥へと降りていきましょう。
[nat_rect]自身はプリミティブでさえありません。
自分の手で書くこともできる関数プログラムです。
*)
Print nat_rect.
(** %\vspace{-.15in}%[[
nat_rect =
fun (P : nat -> Type) (f : P O) (f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n as n0 return (P n0) with
| O => f
| S n0 => f0 n0 (F n0)
end
: forall P : nat -> Type,
P O -> (forall n : nat, P n -> P (S n)) -> forall n : nat, P n
]]
(*
The only new wrinkles here are, first, an anonymous recursive function definition, using the %\index{Gallina terms!fix}%[fix] keyword of Gallina (which is like [fun] with recursion supported); and, second, the annotations on the [match] expression. This is a%\index{dependent pattern matching}% _dependently typed_ pattern match, because the _type_ of the expression depends on the _value_ being matched on. We will meet more involved examples later, especially in Part II of the book.
*)
ここで新しく登場したのは、%\index{Gallinaこう@Gallina項!fix}%[fix]というGallinaのキーワードを使った無名再帰関数（[fix]は[fun]と同じく再帰に対応しています）と、[match]式に対する注釈です。
このような[match]を_[依存型付きパターンマッチ]_と呼びます。%\index{dependent pattern matching}%
なぜかというと、この式の_[型]_は、マッチする_[値]_に依存するからです。
のちほど、特に第II部で、もっと複雑な例が登場します。
(*
%\index{type inference}%Type inference for dependent pattern matching is undecidable, which can be proved by reduction from %\index{higher-order unification}%higher-order unification%~\cite{HOU}%. Thus, we often find ourselves needing to annotate our programs in a way that explains dependencies to the type checker. In the example of [nat_rect], we have an %\index{Gallina terms!as}%[as] clause, which binds a name for the discriminee; and a %\index{Gallina terms!return}%[return] clause, which gives a way to compute the [match] result type as a function of the discriminee.
*)
%\index{かたすいろん@型推論}%依存型付きパターンマッチに対する型推論は、非決定的です。
このことは、%\index{こうかいたんいつか@高階単一化}%高階単一化からの簡約により証明できます%~\cite{HOU}%。
型推論が非決定的なので、プログラムに手で注釈を付けることにより型検査器に依存関係を伝えなければならないことがよくあります。
[nat_rect]の例では、
[as]節により識別対象の名前を束縛し%\index{Gallinaこう@Gallina項!as}%、
[return]節により[match]の結果の型を計算する手段を識別対象の関数として指定しています%\index{Gallinaこう@Gallina項!return}%。
(*
To prove that [nat_rect] is nothing special, we can reimplement it manually.
*)
[nat_rect]が特別なものでないことは、手で再実装してみれば証明できます。
*)
Fixpoint nat_rect' (P : nat -> Type)
(HO : P O)
(HS : forall n, P n -> P (S n)) (n : nat) :=
match n return P n with
| O => HO
| S n' => HS n' (nat_rect' P HO HS n')
end.
(**
(*
We can understand the definition of [nat_rect] better by reimplementing [nat_ind] using sections.
*)
[nat_rect]の定義をさらによく理解できるように、[nat_ind]をセクションで再実装してみましょう。
*)
Section nat_ind'.
(**
(*
First, we have the property of natural numbers that we aim to prove.
*)
まずは証明したい自然数の性質を用意します。
*)
Variable P : nat -> Prop.
(**
(*
Then we require a proof of the [O] case, which we declare with the command %\index{Vernacular commands!Hypothesis}%[Hypothesis], which is a synonym for [Variable] that, by convention, is used for variables whose types are propositions.
*)
まず必要なのは[O]の場合の証明です。これは%\index{Vernacularこまんど@Vernacularコマンド!Hypothesis}%[Hypothesis]コマンドで宣言します。
このコマンドは[Variable]のシノニムで、規約により、型が命題である変数に対して使うことになっています。
*)
Hypothesis O_case : P O.
(**
(*
Next is a proof of the [S] case, which may assume an inductive hypothesis.
*)
次は[S]の場合の証明です。
この場合には帰納法の仮説が使えるでしょう。
*)
Hypothesis S_case : forall n : nat, P n -> P (S n).
(**
(*
Finally, we define a recursive function to tie the pieces together.
*)
最後に、これらのピースをつなぐ再帰関数を定義します。
*)
Fixpoint nat_ind' (n : nat) : P n :=
match n with
| O => O_case
| S n' => S_case (nat_ind' n')
end.
End nat_ind'.
(**
(*
Closing the section adds the [Variable]s and [Hypothesis]es as new [fun]-bound arguments to [nat_ind'], and, modulo the use of [Prop] instead of [Type], we end up with the exact same definition that was generated automatically for [nat_rect].
*)
セクションを閉じると、[nat_ind']に対する、[fun]で束縛された新しい引数として、[Variable]と[Hypothesis]が追加されます。
[Type]の代りに[Prop]を使っている点を除くと、最終的には[nat_rect]のために自動生成された定義とまったく同じものになります。
%\medskip%
(*
We can also examine the definition of [even_list_mut], which we generated with [Scheme] for a mutually recursive type.
*)
相互再帰型では[even_list_mut]という帰納法の原理を使いました。
そのときは、[Scheme]を使って[even_list_mut]を生成しました。
この原理についても定義を詳しく調べることが可能です。
*)
Print even_list_mut.
(** %\vspace{-.15in}%[[
even_list_mut =
fun (P : even_list -> Prop) (P0 : odd_list -> Prop)
(f : P ENil) (f0 : forall (n : nat) (o : odd_list), P0 o -> P (ECons n o))
(f1 : forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) =>
fix F (e : even_list) : P e :=
match e as e0 return (P e0) with
| ENil => f
| ECons n o => f0 n o (F0 o)
end
with F0 (o : odd_list) : P0 o :=
match o as o0 return (P0 o0) with
| OCons n e => f1 n e (F e)
end
for F
: forall (P : even_list -> Prop) (P0 : odd_list -> Prop),
P ENil ->
(forall (n : nat) (o : odd_list), P0 o -> P (ECons n o)) ->
(forall (n : nat) (e : even_list), P e -> P0 (OCons n e)) ->
forall e : even_list, P e
]]
(*
We see a mutually recursive [fix], with the different functions separated by %\index{Gallina terms!with}%[with] in the same way that they would be separated by <<and>> in ML. A final %\index{Gallina terms!for}%[for] clause identifies which of the mutually recursive functions should be the final value of the [fix] expression. Using this definition as a template, we can reimplement [even_list_mut] directly.
*)
相互再帰する[fix]では、%\index{Gallinaこう@Gallina項!with}%[with]で区切ることで別々の関数を使っています。
ちょうど、MLにおいて<<and>>で区切るのと同じ要領です。
相互再帰する関数のいずれが[fix]式の最終的な値になるべきかは、最後の%\index{Gallinaこう@Gallina項!for}%[for]節で識別されます。
この定義をテンプレートにすることで、以下のように[even_list_mut]を直接定義できます。
*)
Section even_list_mut'.
(**
(*
First, we need the properties that we are proving.
*)
まず、これから証明する性質が必要です。
*)
Variable Peven : even_list -> Prop.
Variable Podd : odd_list -> Prop.
(**
(*
Next, we need proofs of the three cases.
*)
次に、三つの場合分けのそれぞれに対する証明が必要です。
*)
Hypothesis ENil_case : Peven ENil.
Hypothesis ECons_case : forall (n : nat) (o : odd_list), Podd o -> Peven (ECons n o).
Hypothesis OCons_case : forall (n : nat) (e : even_list), Peven e -> Podd (OCons n e).
(**
(*
Finally, we define the recursive functions.
*)
最後に再帰関数を定義します。
*)
Fixpoint even_list_mut' (e : even_list) : Peven e :=
match e with
| ENil => ENil_case
| ECons n o => ECons_case n (odd_list_mut' o)
end
with odd_list_mut' (o : odd_list) : Podd o :=
match o with
| OCons n e => OCons_case n (even_list_mut' e)
end.
End even_list_mut'.
(**
(*
Even induction principles for reflexive types are easy to implement directly. For our [formula] type, we can use a recursive definition much like those we wrote above.
*)
反射的型についても簡単に帰納法の原理を直接実装できます。
前に見た[formula]型に対しては、上記とほとんど同じ要領で再帰的な定義が使えます。
*)
Section formula_ind'.
Variable P : formula -> Prop.
Hypothesis Eq_case : forall n1 n2 : nat, P (Eq n1 n2).
Hypothesis And_case : forall f1 f2 : formula,
P f1 -> P f2 -> P (And f1 f2).
Hypothesis Forall_case : forall f : nat -> formula,
(forall n : nat, P (f n)) -> P (Forall f).
Fixpoint formula_ind' (f : formula) : P f :=
match f with
| Eq n1 n2 => Eq_case n1 n2
| And f1 f2 => And_case (formula_ind' f1) (formula_ind' f2)
| Forall f' => Forall_case f' (fun n => formula_ind' (f' n))
end.
End formula_ind'.
(**
(*
It is apparent that induction principle implementations involve some tedium but not terribly much creativity.
*)
帰納法の原理を実装するのは、どちらかというと退屈であり、それほど創造的ではありません。
*)
(**
(*
* Nested Inductive Types
*)
* ネストした帰納型
*)
(**
(*
Suppose we want to extend our earlier type of binary trees to trees with arbitrary finite branching. We can use lists to give a simple definition.
*)
すでに定義した二分木の型を拡張し、任意の数の分岐がある多分木の型を定義したいとします。
単純な定義は、以下のようにリストを使うものでしょう。
*)
Inductive nat_tree : Set :=
| NNode' : nat -> list nat_tree -> nat_tree.
(**
(*
This is an example of a%\index{nested inductive type}% _nested_ inductive type definition, because we use the type we are defining as an argument to a parameterized type family. Coq will not allow all such definitions; it effectively pretends that we are defining [nat_tree] mutually with a version of [list] specialized to [nat_tree], checking that the resulting expanded definition satisfies the usual rules. For instance, if we replaced [list] with a type family that used its parameter as a function argument, then the definition would be rejected as violating the positivity restriction.
*)
この定義では、定義しようとする型を、パラメタ化された型族への引数として使っています。
そのため、_[ネストした]_帰納型%\index{ねすとしたきのうがた@ネストした帰納型}%の定義の例になっています。
このような定義は、一般にはCoqは許してくれません。
Coqはこの定義を、[nat_tree]を適用した[list]を使って相互参照的に[nat_tree]を定義しているとみなし、定義が展開された結果が通常の規則を満すかどうかを確認します。
(* いけぶち：型パラメータへの代入をspecializeと言うけど、「特定化」と言って通じるのかよく分からなかったので「適用」にしてみた *)
たとえば、この定義の[list]を置き換えて、パラメータを関数引数として使うような型族にすれば、陽性要件に違反する定義であるとして拒絶されるでしょう。
(*
As we encountered with mutual inductive types, we find that the automatically generated induction principle for [nat_tree] is too weak.
*)
相互帰納型の例で見たように、[nat_tree]に対して自動生成される帰納法の原理は弱すぎるのです。
*)
(* begin hide *)
(* begin thide *)
Check Forall.
(* end thide *)
(* end hide *)
Check nat_tree_ind.
(** %\vspace{-.15in}% [[
nat_tree_ind
: forall P : nat_tree -> Prop,
(forall (n : nat) (l : list nat_tree), P (NNode' n l)) ->
forall n : nat_tree, P n
]]
(*
There is no command like [Scheme] that will implement an improved principle for us. In general, it takes creativity to figure out _good_ ways to incorporate nested uses of different type families. Now that we know how to implement induction principles manually, we are in a position to apply just such creativity to this problem.
*)
改良版の原理を実装してくれる[Scheme]のようなコマンドはありません。
異なる型族をネストして使う、うまい方法を見つけるには、通常は独創性が必要です。
すでに相互帰納法の原理を自分で実装する方法は説明したので、ここでそれを応用してみましょう。
(*
Many induction principles for types with nested uses of [list] could benefit from a unified predicate capturing the idea that some property holds of every element in a list. By defining this generic predicate once, we facilitate reuse of library theorems about it. (Here, we are actually duplicating the standard library's [Forall] predicate, with a different implementation, for didactic purposes.)
*)
ある性質がリストの各要素について満たされることを単一の述語で表せると、[list]をネストして使っている型に対する帰納法の原理で便利に使える場合がよくあります。
そうした汎用の述語は、一度だけ定義すれば、その述語に関するライブラリの定理として再利用できます
（ここでは、標準ライブラリの[Forall]という述語を説明のために改めて再実装しています）。
*)
Section All.
Variable T : Set.
Variable P : T -> Prop.
Fixpoint All (ls : list T) : Prop :=
match ls with
| Nil => True
| Cons h t => P h /\ All t
end.
End All.
(**
(*
It will be useful to review the definitions of [True] and [/\], since we will want to write manual proofs of them below.
*)
これから[True]および[/\]を自分たちで証明していきたいので、まずはそれらの定義を見返しておきましょう。
*)
Print True.
(** %\vspace{-.15in}%[[
Inductive True : Prop := I : True
]]
(*
That is, [True] is a proposition with exactly one proof, [I], which we may always supply trivially.
*)
要するに、[True]は[I]という証明を1つだけ持つ命題です。この証明[I]は常に自明に成り立ちます。
(*
Finding the definition of [/\] takes a little more work. Coq supports user registration of arbitrary parsing rules, and it is such a rule that is letting us write [/\] instead of an application of some inductive type family. We can find the underlying inductive type with the %\index{Vernacular commands!Locate}%[Locate] command, whose argument may be a parsing token.%\index{Gallina terms!and}%
*)
[/\]の定義については、もう少し考えることがあります。
帰納的な型族を適用する代わりに[/\]と書けるのは、Coqでは利用者が任意の構文解析の規則を登録できるようになっており、[/\]のための規則が登録されているからです。
[/\]の背景にある帰納型を調べるには、構文解析トークンを引数に取る%\index{Vernacularこまんど@Vernacularコマンド!Locate}%[Locate]コマンドを使います。
*)
Locate "/\".
(** %\vspace{-.15in}%[[
"A /\ B" := and A B : type_scope (default interpretation)
]]
*)
Print and.
(** %\vspace{-.15in}%[[
Inductive and (A : Prop) (B : Prop) : Prop := conj : A -> B -> A /\ B
]]
%\vspace{-.1in}%
<<
For conj: Arguments A, B are implicit
>>
(*
In addition to the definition of [and] itself, we get information on %\index{implicit arguments}%implicit arguments (and some other information that we omit here). The implicit argument information tells us that we build a proof of a conjunction by calling the constructor [conj] on proofs of the conjuncts, with no need to include the types of those proofs as explicit arguments.
*)
[and]の定義を[Print]コマンドで表示すると、定義の下に%\index{あんもくのひきすう@暗黙の引数}%暗黙の引数（implicit argument）に関する情報も得られます（それ以外の情報も表示されますが上記では省略しています）。
暗黙の引数に関するこの情報からは、
連言肢の証明に対して構成子[conj]を呼び出すことで連言の証明が構成され、その際に連言肢の証明の型を明示的な引数として含める必要はない、ということがわかります。
%\medskip%
(*
Now we create a section for our induction principle, following the same basic plan as in the previous section of this chapter.
*)
帰納法の原理のセクションを作り、前節の例と同じ基本的な方針で進めましょう。
*)
Section nat_tree_ind'.
Variable P : nat_tree -> Prop.
Hypothesis NNode'_case : forall (n : nat) (ls : list nat_tree),
All P ls -> P (NNode' n ls).
(* begin hide *)
(* begin thide *)
Definition list_nat_tree_ind := O.
(* end thide *)
(* end hide *)
(**
(*
A first attempt at writing the induction principle itself follows the intuition that nested inductive type definitions are expanded into mutual inductive definitions.
*)
帰納法の原理そのものを書き出すにあたり、まずは「ネストした帰納型の定義は相互帰納の定義に展開される」という直観に従ってみます。
%\vspace{-.15in}%[[
Fixpoint nat_tree_ind' (tr : nat_tree) : P tr :=
match tr with
| NNode' n ls => NNode'_case n ls (list_nat_tree_ind ls)
end
with list_nat_tree_ind (ls : list nat_tree) : All P ls :=
match ls with
| Nil => I
| Cons tr rest => conj (nat_tree_ind' tr) (list_nat_tree_ind rest)
end.
]]
(*
Coq rejects this definition, saying
*)
この定義は、以下のメッセージにより、Coqから拒絶されます。
<<
Recursive call to nat_tree_ind' has principal argument equal to "tr"
instead of rest.
>>
(*
There is no deep theoretical reason why this program should be rejected; Coq applies incomplete termination-checking heuristics, and it is necessary to learn a few of the most important rules. The term "nested inductive type" hints at the solution to this particular problem. Just as mutually inductive types require mutually recursive induction principles, nested types require nested recursion.
*)
このプログラムが拒絶されることに理論上の深淵な理由はありません。
停止性判定のヒューリスティクスをCoqが不完全に適用しただけなので、特に重要な規則をいくつかCoqに学ばせる必要があります。(* ここ意味がよくわからない -kshikano *)
この問題に対するヒントになるのは、「ネストした帰納的型」という言い方です。
相互帰納型では、相互再帰した帰納法の原理が必要でした。ネストした型には、ネストした再帰が必要です。
*)
Fixpoint nat_tree_ind' (tr : nat_tree) : P tr :=
match tr with
| NNode' n ls => NNode'_case n ls
((fix list_nat_tree_ind (ls : list nat_tree) : All P ls :=
match ls with
| Nil => I
| Cons tr' rest => conj (nat_tree_ind' tr') (list_nat_tree_ind rest)
end) ls)
end.
(**
(*
We include an anonymous [fix] version of [list_nat_tree_ind] that is literally _nested_ inside the definition of the recursive function corresponding to the inductive definition that had the nested use of [list].
*)
この定義では、[list_nat_tree_ind]を無名[fix]として使っており、これは再帰関数の定義の中で文字どおり_[ネスト]_しています。
この再帰関数に、[list]をネストさせて使っていた帰納的な定義が対応します。
*)
End nat_tree_ind'.
(**
(*
We can try our induction principle out by defining some recursive functions on [nat_tree] and proving a theorem about them. First, we define some helper functions that operate on lists.
*)
この帰納法の原理を使ってみましょう。
[nat_tree]上の再帰関数を定義し、それらに関する定理を証明してみます。
まず、リストを操作する補助関数をいくつか定義します。
*)
Section map.
Variables T T' : Set.
Variable F : T -> T'.
Fixpoint map (ls : list T) : list T' :=
match ls with
| Nil => Nil
| Cons h t => Cons (F h) (map t)
end.
End map.
Fixpoint sum (ls : list nat) : nat :=
match ls with
| Nil => O
| Cons h t => plus h (sum t)
end.
(**
(*
Now we can define a size function over our trees.
*)
これで木のサイズを測る関数を定義できます。
*)
Fixpoint ntsize (tr : nat_tree) : nat :=
match tr with
| NNode' _ trs => S (sum (map ntsize trs))
end.
(**
(*
Notice that Coq was smart enough to expand the definition of [map] to verify that we are using proper nested recursion, even through a use of a higher-order function.
*)
高階関数を使っていますが、Coqは賢いので、ネストした再帰が適切に使われていることを検証するために[map]の定義を展開してくれます。(* この原稿をCoqにかけると、この本文がある時点では展開済みなので、原文は過去形になっているけど、読みにくいので平叙文で -kshikano *)
*)
Fixpoint ntsplice (tr1 tr2 : nat_tree) : nat_tree :=
match tr1 with
| NNode' n Nil => NNode' n (Cons tr2 Nil)
| NNode' n (Cons tr trs) => NNode' n (Cons (ntsplice tr tr2) trs)
end.
(**
(*
We have defined another arbitrary notion of tree splicing, similar to before, and we can prove an analogous theorem about its relationship with tree size. We start with a useful lemma about addition.
*)
上記では、任意個の分岐を持つ木の接合（splice）を、二分木のときの[nsplice]と同様に定義しています。
この[ntsplice]についても、木のサイズとの関係について同様の定理が証明できます。
まずは加法に関する便利な補題を用意します。
*)
(* begin thide *)
Lemma plus_S : forall n1 n2 : nat,
plus n1 (S n2) = S (plus n1 n2).
induction n1; crush.
Qed.
(* end thide *)
(**
(*
Now we begin the proof of the theorem, adding the lemma [plus_S] as a hint.
*)
この補題[plus_S]をヒントとして追加することで、定理の証明を開始します。
*)
Hint Rewrite plus_S.
Theorem ntsize_ntsplice : forall tr1 tr2 : nat_tree, ntsize (ntsplice tr1 tr2)
= plus (ntsize tr2) (ntsize tr1).
(* begin thide *)
(**
(*
We know that the standard induction principle is insufficient for the task, so we need to provide a %\index{tactics!using}%[using] clause for the [induction] tactic to specify our alternate principle.
*)
標準の帰納法の原理では力不足なので、%\index{たくてぃっく@タクティク!using}%[induction]タクティクで[using]節を使って代替の原理を指定します。
*)
induction tr1 using nat_tree_ind'; crush.
(**
(*
One subgoal remains: [[
*)
サブゴールが一つ残っています。 [[
n : nat
ls : list nat_tree
H : All
(fun tr1 : nat_tree =>
forall tr2 : nat_tree,
ntsize (ntsplice tr1 tr2) = plus (ntsize tr2) (ntsize tr1)) ls
tr2 : nat_tree
============================
ntsize
match ls with
| Nil => NNode' n (Cons tr2 Nil)
| Cons tr trs => NNode' n (Cons (ntsplice tr tr2) trs)
end = S (plus (ntsize tr2) (sum (map ntsize ls)))
]]
(*
After a few moments of squinting at this goal, it becomes apparent that we need to do a case analysis on the structure of [ls]. The rest is routine.
*)
このゴールをしばらくじっと見ていると、[ls]の構造に関する場合分けが必要なことが見えてきます。
あとはいつもと同じです。
*)
destruct ls; crush.
(**
(*
We can go further in automating the proof by exploiting the hint mechanism.%\index{Vernacular commands!Hint Extern}%
*)
ヒントの仕組みをうまく使うことで、この証明をさらに自動化できます。%\index{Vernacularこまんど@Vernacularコマンド!Hint Extern}%
*)
Restart.
Hint Extern 1 (ntsize (match ?LS with Nil => _ | Cons _ _ => _ end) = _) =>
destruct LS; crush.
induction tr1 using nat_tree_ind'; crush.
Qed.
(* end thide *)
(**
(*
We will go into great detail on hints in a later chapter, but the only important thing to note here is that we register a pattern that describes a conclusion we expect to encounter during the proof. The pattern may contain unification variables, whose names are prefixed with question marks, and we may refer to those bound variables in a tactic that we ask to have run whenever the pattern matches.
*)
ヒントについては後の章で詳しく説明します。
ここで重要なのは、ヒントを使うことで、証明の途中で遭遇が予想される結論を記述するパターンが登録できるという点だけです。
このパターンには、単一化変数を含めてもかまいません。
その場合は、変数名の先頭に疑問符がつきます。
それらの束縛変数は、パターンにマッチしたときに実行させるタクティクの中で参照できます。
(*
The advantage of using the hint is not very clear here, because the original proof was so short. However, the hint has fundamentally improved the readability of our proof. Before, the proof referred to the local variable [ls], which has an automatically generated name. To a human reading the proof script without stepping through it interactively, it was not clear where [ls] came from. The hint explains to the reader the process for choosing which variables to case analyze, and the hint can continue working even if the rest of the proof structure changes significantly.
*)
この例では、証明がとても短いので、ヒントを使う利点はあまりありません。
それでも、ヒントによって証明の読みやすさは大きく改善しました。
ヒントを使う前は、証明でローカル変数[ls]が参照されていますが、この[ls]は自動生成された名前でした。
対話的に実行せずに証明スクリプトだけを読む人にとっては、[ls]がどこから来たのか明確ではありません。
ヒントは、証明を読む人に対し、場合分けにおいて選択する変数を説明してくれます。
なお、ヒントは、それ以外の証明の構造を大幅に変更しても正しく機能します。
*)
(**
(*
* Manual Proofs About Constructors
*)
* 構成子に関する手動の証明
*)
(**
(*
It can be useful to understand how tactics like %\index{tactics!discriminate}%[discriminate] and %\index{tactics!injection}%[injection] work, so it is worth stepping through a manual proof of each kind. We will start with a proof fit for [discriminate].
*)
%\index{たくてぃく@タクティク!discriminate}%[discriminate]や%\index{たくてぃく@タクティク!injection}%[injection]のようなタクティクがどのように機能するかを理解するために、これらのタクティクの仕事を手で追って証明してみましょう。
まずは[discriminate]です。
*)
Theorem true_neq_false : true <> false.
(* begin thide *)
(**
(*
We begin with the tactic %\index{tactics!red}%[red], which is short for "one step of reduction," to unfold the definition of logical negation.
*)
論理否定の定義を展開するために、[red]タクティクから始めます。
このタクティクの名前は「1ステップの簡約（one step of reduction）」からきています。
*)
red.
(** %\vspace{-.15in}%[[
============================
true = false -> False
]]
(*
The negation is replaced with an implication of falsehood. We use the tactic %\index{tactics!intro}%[intro H] to change the assumption of the implication into a hypothesis named [H].
*)
否定は、偽の含意で置き換えられます。
%\index{たくてぃくす@タクティクス!intro}%[intro H]というタクティクを使って、含意の仮定を[H]という名前の仮説にします。
*)
intro H.
(** %\vspace{-.15in}%[[
H : true = false
============================
False
]]
(*
This is the point in the proof where we apply some creativity. We define a function whose utility will become clear soon.
*)
ここで少し独創性が必要になります。
関数を一つ定義しましょう。
なぜこの関数を定義するかは、すぐにわかります。
*)
Definition toProp (b : bool) := if b then True else False.
(**
(*
It is worth recalling the difference between the lowercase and uppercase versions of truth and falsehood: [True] and [False] are logical propositions, while [true] and [false] are Boolean values that we can case-analyze. We have defined [toProp] such that our conclusion of [False] is computationally equivalent to [toProp false]. Thus, the %\index{tactics!change}%[change] tactic will let us change the conclusion to [toProp false]. The general form [change e] replaces the conclusion with [e], whenever Coq's built-in computation rules suffice to establish the equivalence of [e] with the original conclusion.
*)
先頭が小文字か大文字かで、真（true）と偽（false）に違いがあったことを思い出してください。
[True]と[False]は論理命題であり、[true]と[false]は場合分けが可能な論理値です。
[toProp]は、[False]の結論が[toProp false]と同等になるように定義しました。
したがって、%\index{たくてぃくす@タクティクス!change}%[change]タクティクにより、[False]の結論を[toProp false]に置き換え可能です。
一般に[change e]という形式は、結論が[e]と同等であることがCoqに組み込まれている計算規則により証明できるときは、常に元の結論を[e]に置き換えてくれます。
*)
change (toProp false).
(** %\vspace{-.15in}%[[
H : true = false
============================
toProp false
]]
(*
Now the righthand side of [H]'s equality appears in the conclusion, so we can rewrite, using the notation [<-] to request to replace the righthand side of the equality with the lefthand side.%\index{tactics!rewrite}%
*)
[H]の等式の右辺が結論に現れたので、等式の右辺を左辺に置き換えるように、[<-]記法を使って書き換えられます。
*)
rewrite <- H.
(** %\vspace{-.15in}%[[
H : true = false
============================
toProp true
]]
(*
We are almost done. Just how close we are to done is revealed by computational simplification.
*)
これでほぼおしまいです。
計算で単純化すれば、ほとんど完了していることがわかります。
*)
simpl.
(** %\vspace{-.15in}%[[
H : true = false
============================
True
]]
*)
trivial.
Qed.
(* end thide *)
(**
(*
I have no trivial automated version of this proof to suggest, beyond using [discriminate] or [congruence] in the first place.
*)
この証明の自動化をしてくれるのが、[discriminate]や[congruence]というわけです。
%\medskip%
(*
We can perform a similar manual proof of injectivity of the constructor [S]. I leave a walk-through of the details to curious readers who want to run the proof script interactively.
*)
構成子[S]の単射性の証明も同じように手動で実行できます。
詳細は、証明スクリプトを対話的に実行してみたい熱心な読者に残しておきます。
*)
Theorem S_inj' : forall n m : nat, S n = S m -> n = m.
(* begin thide *)
intros n m H.
change (pred (S n) = pred (S m)).
rewrite H.
reflexivity.
Qed.
(* end thide *)
(**
(*
The key piece of creativity in this theorem comes in the use of the natural number predecessor function [pred]. Embodied in the implementation of [injection] is a generic recipe for writing such type-specific functions.
*)
この定理で鍵となるのは、自然数の前者関数[pred]の使い方です。
[injection]の実装には、このような型に固有の関数を書くときの一般的なレシピが具現化されているのです。
(*
The examples in this section illustrate an important aspect of the design philosophy behind Coq. We could certainly design a Gallina replacement that built in rules for constructor discrimination and injectivity, but a simpler alternative is to include a few carefully chosen rules that enable the desired reasoning patterns and many others. A key benefit of this philosophy is that the complexity of proof checking is minimized, which bolsters our confidence that proved theorems are really true.
*)
本節で紹介した例からは、Coqの背景にある設計思想の重要な側面が見えてきます。
構成子の区別と単射性に関する規則を組み込み、Gallinaの代替を設計することは可能ですが、
むしろ、必要な論証パターンなどが可能になるように選び抜いた規則を含めておくほうが選択肢として単純です。
Coqの設計思想の利点は、証明の確認にかかる複雑さが最小限に抑えられていることで、証明された定理が本当に正しいという確信を強く持てることです。
*)
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: VC709Gen3x4If128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx VC709 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module VC709Gen3x4If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 12,
// Number of PCIe Lanes
parameter C_NUM_LANES = 4,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [7:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N
);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;// TODO: Connect to LED's
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
OBUF
#()
led_2_obuf
(.O(LED[2]),
.I(cfg_ltssm_state[2]));
OBUF
#()
led_3_obuf
(.O(LED[3]),
.I(cfg_ltssm_state[3]));
OBUF
#()
led_4_obuf
(.O(LED[4]),
.I(cfg_ltssm_state[4]));
OBUF
#()
led_5_obuf
(.O(LED[5]),
.I(cfg_ltssm_state[5]));
OBUF
#()
led_6_obuf
(.O(LED[6]),
.I(pcie_reset_n));
OBUF
#()
led_7_obuf
(.O(LED[7]),
.I(rst_out));
// Core Top Level Wrapper
PCIeGen3x4If128
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_vc709
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../engine/" "ultrascale/rx/" "ultrascale/tx/" "classic/rx/" "classic/tx/" "../../../riffa/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O311AI_PP_SYMBOL_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_SYMBOL_V
`define SKY130_FD_SC_MS__DLRBP_SYMBOL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_BLEEDER_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_BLEEDER_PP_BLACKBOX_V
/**
* lpflow_bleeder: Current bleeder (weak pulldown to ground).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_bleeder (
SHORT,
VPWR ,
VGND ,
VPB ,
VNB
);
input SHORT;
inout VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_FUNCTIONAL_V
`define SKY130_FD_SC_LS__HA_FUNCTIONAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__ha (
COUT,
SUM ,
A ,
B
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
// Local signals
wire and0_out_COUT;
wire xor0_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_4_V
`define SKY130_FD_SC_LP__A22OI_4_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_4 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_4_V
|
/**
* bsg_cache.v
*
* - two-stage pipelined.
* - n-way set associative.
* - pseudo-tree LRU replacement policy.
* - write-back, write-allocate
*
* @author tommy
*
* See https://docs.google.com/document/d/1AIjhuwTbOYwyZHdu-Uc4dr9Fwxi6ZKscKSGTiUeQEYo/edit for design doc
*/
`include "bsg_defines.v"
`include "bsg_cache.vh"
module bsg_cache
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p) // byte addr
,parameter `BSG_INV_PARAM(data_width_p) // word size
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter `BSG_INV_PARAM(sets_p)
,parameter `BSG_INV_PARAM(ways_p)
// Explicit size prevents size inference and allows for ((foo == bar) << e_cache_amo_swap)
,parameter [31:0] amo_support_p=(1 << e_cache_amo_swap)
| (1 << e_cache_amo_or)
// dma burst width
,parameter dma_data_width_p=data_width_p // default value. it can also be pow2 multiple of data_width_p.
,parameter bsg_cache_pkt_width_lp=`bsg_cache_pkt_width(addr_width_p,data_width_p)
,parameter bsg_cache_dma_pkt_width_lp=`bsg_cache_dma_pkt_width(addr_width_p)
,parameter debug_p=0
)
(
input clk_i
,input reset_i
,input [bsg_cache_pkt_width_lp-1:0] cache_pkt_i
,input v_i
,output logic ready_o
,output logic [data_width_p-1:0] data_o
,output logic v_o
,input yumi_i
,output logic [bsg_cache_dma_pkt_width_lp-1:0] dma_pkt_o
,output logic dma_pkt_v_o
,input dma_pkt_yumi_i
,input [dma_data_width_p-1:0] dma_data_i
,input dma_data_v_i
,output logic dma_data_ready_o
,output logic [dma_data_width_p-1:0] dma_data_o
,output logic dma_data_v_o
,input dma_data_yumi_i
// this signal tells the outside world that the instruction is moving from
// TL to TV stage. It can be used for some metadata outside the cache that
// needs to move together with the corresponding instruction. The usage of
// this signal is totally optional.
,output logic v_we_o
);
// localparam
//
localparam lg_sets_lp=`BSG_SAFE_CLOG2(sets_p);
localparam data_mask_width_lp=(data_width_p>>3);
localparam lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_mask_width_lp);
localparam lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p);
localparam block_offset_width_lp=(block_size_in_words_p > 1) ? lg_data_mask_width_lp+lg_block_size_in_words_lp : lg_data_mask_width_lp;
localparam tag_width_lp=(addr_width_p-lg_sets_lp-block_offset_width_lp);
localparam tag_info_width_lp=`bsg_cache_tag_info_width(tag_width_lp);
localparam lg_ways_lp=`BSG_SAFE_CLOG2(ways_p);
localparam stat_info_width_lp = `bsg_cache_stat_info_width(ways_p);
localparam data_sel_mux_els_lp = `BSG_MIN(4,lg_data_mask_width_lp+1);
localparam lg_data_sel_mux_els_lp = `BSG_SAFE_CLOG2(data_sel_mux_els_lp);
localparam burst_size_in_words_lp=(dma_data_width_p/data_width_p);
localparam lg_burst_size_in_words_lp=`BSG_SAFE_CLOG2(burst_size_in_words_lp);
localparam burst_len_lp=(block_size_in_words_p*data_width_p/dma_data_width_p);
localparam lg_burst_len_lp=`BSG_SAFE_CLOG2(burst_len_lp);
localparam dma_data_mask_width_lp=(dma_data_width_p>>3);
localparam data_mem_els_lp = sets_p*burst_len_lp;
localparam lg_data_mem_els_lp = `BSG_SAFE_CLOG2(data_mem_els_lp);
// instruction decoding
//
logic [lg_ways_lp-1:0] addr_way;
logic [lg_sets_lp-1:0] addr_index;
logic [lg_block_size_in_words_lp-1:0] addr_block_offset;
`declare_bsg_cache_pkt_s(addr_width_p, data_width_p);
bsg_cache_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
bsg_cache_decode_s decode;
bsg_cache_decode decode0 (
.opcode_i(cache_pkt.opcode)
,.decode_o(decode)
);
assign addr_way
= cache_pkt.addr[block_offset_width_lp+lg_sets_lp+:lg_ways_lp];
assign addr_index
= cache_pkt.addr[block_offset_width_lp+:lg_sets_lp];
assign addr_block_offset
= cache_pkt.addr[lg_data_mask_width_lp+:lg_block_size_in_words_lp];
logic [lg_data_mem_els_lp-1:0] ld_data_mem_addr;
if (burst_len_lp == 1) begin
assign ld_data_mem_addr = addr_index;
end
else if (burst_len_lp == block_size_in_words_p) begin
assign ld_data_mem_addr = {addr_index, cache_pkt.addr[lg_data_mask_width_lp+:lg_block_size_in_words_lp]};
end
else begin
assign ld_data_mem_addr = {addr_index, cache_pkt.addr[lg_data_mask_width_lp+lg_burst_size_in_words_lp+:lg_burst_len_lp]};
end
// tl_stage
//
logic v_tl_r;
bsg_cache_decode_s decode_tl_r;
logic [data_mask_width_lp-1:0] mask_tl_r;
logic [addr_width_p-1:0] addr_tl_r;
logic [data_width_p-1:0] data_tl_r;
logic sbuf_hazard;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_tl_r <= 1'b0;
{mask_tl_r
,addr_tl_r
,data_tl_r
,decode_tl_r} <= '0;
end
else begin
if (ready_o) begin
v_tl_r <= v_i;
if (v_i) begin
mask_tl_r <= cache_pkt.mask;
addr_tl_r <= cache_pkt.addr;
data_tl_r <= cache_pkt.data;
decode_tl_r <= decode;
end
end
else begin
if (sbuf_hazard)
v_tl_r <= 1'b0;
end
end
end
logic [lg_sets_lp-1:0] addr_index_tl;
logic [lg_block_size_in_words_lp-1:0] addr_block_offset_tl;
assign addr_index_tl =
addr_tl_r[block_offset_width_lp+:lg_sets_lp];
assign addr_block_offset_tl =
addr_tl_r[lg_data_mask_width_lp+:lg_block_size_in_words_lp];
logic [lg_data_mem_els_lp-1:0] recover_data_mem_addr;
if (burst_len_lp == 1) begin
assign recover_data_mem_addr = addr_index_tl;
end
else if (burst_len_lp == block_size_in_words_p) begin
assign recover_data_mem_addr = {addr_index_tl, addr_tl_r[lg_data_mask_width_lp+:lg_block_size_in_words_lp]};
end
else begin
assign recover_data_mem_addr = {addr_index_tl, addr_tl_r[lg_data_mask_width_lp+lg_burst_size_in_words_lp+:lg_burst_len_lp]};
end
// tag_mem
//
`declare_bsg_cache_tag_info_s(tag_width_lp);
logic tag_mem_v_li;
logic tag_mem_w_li;
logic [lg_sets_lp-1:0] tag_mem_addr_li;
bsg_cache_tag_info_s [ways_p-1:0] tag_mem_data_li;
bsg_cache_tag_info_s [ways_p-1:0] tag_mem_w_mask_li;
bsg_cache_tag_info_s [ways_p-1:0] tag_mem_data_lo;
bsg_mem_1rw_sync_mask_write_bit #(
.width_p(tag_info_width_lp*ways_p)
,.els_p(sets_p)
,.latch_last_read_p(1)
) tag_mem (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(tag_mem_v_li)
,.w_i(tag_mem_w_li)
,.addr_i(tag_mem_addr_li)
,.data_i(tag_mem_data_li)
,.w_mask_i(tag_mem_w_mask_li)
,.data_o(tag_mem_data_lo)
);
logic [ways_p-1:0] valid_tl;
logic [ways_p-1:0][tag_width_lp-1:0] tag_tl;
logic [ways_p-1:0] lock_tl;
for (genvar i = 0; i < ways_p; i++) begin
assign valid_tl[i] = tag_mem_data_lo[i].valid;
assign tag_tl[i] = tag_mem_data_lo[i].tag;
assign lock_tl[i] = tag_mem_data_lo[i].lock;
end
// data_mem
//
logic data_mem_v_li;
logic data_mem_w_li;
logic [lg_data_mem_els_lp-1:0] data_mem_addr_li;
logic [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_li;
logic [ways_p-1:0][dma_data_mask_width_lp-1:0] data_mem_w_mask_li;
logic [ways_p-1:0][dma_data_width_p-1:0] data_mem_data_lo;
bsg_mem_1rw_sync_mask_write_byte #(
.data_width_p(dma_data_width_p*ways_p)
,.els_p(data_mem_els_lp)
,.latch_last_read_p(1)
) data_mem (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(data_mem_v_li)
,.w_i(data_mem_w_li)
,.addr_i(data_mem_addr_li)
,.data_i(data_mem_data_li)
,.write_mask_i(data_mem_w_mask_li)
,.data_o(data_mem_data_lo)
);
// v stage
//
logic v_we;
logic v_v_r;
bsg_cache_decode_s decode_v_r;
logic [data_mask_width_lp-1:0] mask_v_r;
logic [addr_width_p-1:0] addr_v_r;
logic [data_width_p-1:0] data_v_r;
logic [ways_p-1:0] valid_v_r;
logic [ways_p-1:0] lock_v_r;
logic [ways_p-1:0][tag_width_lp-1:0] tag_v_r;
logic [ways_p-1:0][dma_data_width_p-1:0] ld_data_v_r;
logic retval_op_v;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_v_r <= 1'b0;
{mask_v_r
,decode_v_r
,addr_v_r
,data_v_r
,valid_v_r
,lock_v_r
,tag_v_r} <= '0;
end
else begin
if (v_we) begin
v_v_r <= v_tl_r;
if (v_tl_r) begin
mask_v_r <= mask_tl_r;
decode_v_r <= decode_tl_r;
addr_v_r <= addr_tl_r;
data_v_r <= data_tl_r;
valid_v_r <= valid_tl;
tag_v_r <= tag_tl;
lock_v_r <= lock_tl;
ld_data_v_r <= data_mem_data_lo;
end
end
end
end
assign v_we_o = v_we;
logic [tag_width_lp-1:0] addr_tag_v;
logic [lg_sets_lp-1:0] addr_index_v;
logic [lg_ways_lp-1:0] addr_way_v;
logic [ways_p-1:0] tag_hit_v;
assign addr_tag_v =
addr_v_r[block_offset_width_lp+lg_sets_lp+:tag_width_lp];
assign addr_index_v =
addr_v_r[block_offset_width_lp+:lg_sets_lp];
assign addr_way_v =
addr_v_r[block_offset_width_lp+lg_sets_lp+:lg_ways_lp];
for (genvar i = 0; i < ways_p; i++) begin
assign tag_hit_v[i] = (addr_tag_v == tag_v_r[i]) & valid_v_r[i];
end
logic [lg_ways_lp-1:0] tag_hit_way_id;
logic tag_hit_found;
bsg_priority_encode #(
.width_p(ways_p)
,.lo_to_hi_p(1)
) tag_hit_pe (
.i(tag_hit_v)
,.addr_o(tag_hit_way_id)
,.v_o(tag_hit_found)
);
wire ld_st_miss = ~tag_hit_found & (decode_v_r.ld_op | decode_v_r.st_op);
wire tagfl_hit = decode_v_r.tagfl_op & valid_v_r[addr_way_v];
wire aflinv_hit = (decode_v_r.afl_op | decode_v_r.aflinv_op| decode_v_r.ainv_op) & tag_hit_found;
wire alock_miss = decode_v_r.alock_op & (tag_hit_found ? ~lock_v_r[tag_hit_way_id] : 1'b1); // either the line is miss, or the line is unlocked.
wire aunlock_hit = decode_v_r.aunlock_op & (tag_hit_found ? lock_v_r[tag_hit_way_id] : 1'b0); // the line is hit and locked.
wire atomic_miss = decode_v_r.atomic_op & ~tag_hit_found;
// miss_v signal activates the miss handling unit.
// MBT: the ~decode_v_r.tagst_op is necessary at the top of this expression
// to avoid X-pessimism post synthesis due to X's coming out of the tags
wire miss_v = (~decode_v_r.tagst_op) & v_v_r
& (ld_st_miss | tagfl_hit | aflinv_hit | alock_miss | aunlock_hit | atomic_miss);
// ops that return some value other than '0.
assign retval_op_v = decode_v_r.ld_op | decode_v_r.taglv_op | decode_v_r.tagla_op | decode_v_r.atomic_op;
// stat_mem
//
`declare_bsg_cache_stat_info_s(ways_p);
logic stat_mem_v_li;
logic stat_mem_w_li;
logic [lg_sets_lp-1:0] stat_mem_addr_li;
bsg_cache_stat_info_s stat_mem_data_li;
bsg_cache_stat_info_s stat_mem_w_mask_li;
bsg_cache_stat_info_s stat_mem_data_lo;
bsg_mem_1rw_sync_mask_write_bit #(
.width_p(stat_info_width_lp)
,.els_p(sets_p)
,.latch_last_read_p(1)
) stat_mem (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(stat_mem_v_li)
,.w_i(stat_mem_w_li)
,.addr_i(stat_mem_addr_li)
,.data_i(stat_mem_data_li)
,.w_mask_i(stat_mem_w_mask_li)
,.data_o(stat_mem_data_lo)
);
// miss handler
//
bsg_cache_dma_cmd_e dma_cmd_lo;
logic [addr_width_p-1:0] dma_addr_lo;
logic [lg_ways_lp-1:0] dma_way_lo;
logic dma_done_li;
logic recover_lo;
logic miss_done_lo;
logic miss_stat_mem_v_lo;
logic miss_stat_mem_w_lo;
logic [lg_sets_lp-1:0] miss_stat_mem_addr_lo;
bsg_cache_stat_info_s miss_stat_mem_data_lo;
bsg_cache_stat_info_s miss_stat_mem_w_mask_lo;
logic miss_tag_mem_v_lo;
logic miss_tag_mem_w_lo;
logic [lg_sets_lp-1:0] miss_tag_mem_addr_lo;
bsg_cache_tag_info_s [ways_p-1:0] miss_tag_mem_data_lo;
bsg_cache_tag_info_s [ways_p-1:0] miss_tag_mem_w_mask_lo;
logic sbuf_empty_li;
logic [lg_ways_lp-1:0] chosen_way_lo;
logic select_snoop_data_r_lo;
bsg_cache_miss #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.sets_p(sets_p)
,.block_size_in_words_p(block_size_in_words_p)
,.ways_p(ways_p)
) miss (
.clk_i(clk_i)
,.reset_i(reset_i)
,.miss_v_i(miss_v)
,.decode_v_i(decode_v_r)
,.addr_v_i(addr_v_r)
,.tag_v_i(tag_v_r)
,.valid_v_i(valid_v_r)
,.lock_v_i(lock_v_r)
,.tag_hit_way_id_i(tag_hit_way_id)
,.tag_hit_v_i(tag_hit_v)
,.tag_hit_found_i(tag_hit_found)
,.sbuf_empty_i(sbuf_empty_li)
,.dma_cmd_o(dma_cmd_lo)
,.dma_way_o(dma_way_lo)
,.dma_addr_o(dma_addr_lo)
,.dma_done_i(dma_done_li)
,.stat_info_i(stat_mem_data_lo)
,.stat_mem_v_o(miss_stat_mem_v_lo)
,.stat_mem_w_o(miss_stat_mem_w_lo)
,.stat_mem_addr_o(miss_stat_mem_addr_lo)
,.stat_mem_data_o(miss_stat_mem_data_lo)
,.stat_mem_w_mask_o(miss_stat_mem_w_mask_lo)
,.tag_mem_v_o(miss_tag_mem_v_lo)
,.tag_mem_w_o(miss_tag_mem_w_lo)
,.tag_mem_addr_o(miss_tag_mem_addr_lo)
,.tag_mem_data_o(miss_tag_mem_data_lo)
,.tag_mem_w_mask_o(miss_tag_mem_w_mask_lo)
,.recover_o(recover_lo)
,.done_o(miss_done_lo)
,.chosen_way_o(chosen_way_lo)
,.ack_i(v_o & yumi_i)
,.select_snoop_data_r_o(select_snoop_data_r_lo)
);
// dma
//
logic [data_width_p-1:0] snoop_word_lo;
logic dma_data_mem_v_lo;
logic dma_data_mem_w_lo;
logic [lg_data_mem_els_lp-1:0] dma_data_mem_addr_lo;
logic [ways_p-1:0][dma_data_mask_width_lp-1:0] dma_data_mem_w_mask_lo;
logic [ways_p-1:0][dma_data_width_p-1:0] dma_data_mem_data_lo;
logic dma_evict_lo;
bsg_cache_dma #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.dma_data_width_p(dma_data_width_p)
,.debug_p(debug_p)
) dma (
.clk_i(clk_i)
,.reset_i(reset_i)
,.dma_cmd_i(dma_cmd_lo)
,.dma_way_i(dma_way_lo)
,.dma_addr_i(dma_addr_lo)
,.done_o(dma_done_li)
,.snoop_word_o(snoop_word_lo)
,.dma_pkt_o(dma_pkt_o)
,.dma_pkt_v_o(dma_pkt_v_o)
,.dma_pkt_yumi_i(dma_pkt_yumi_i)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_ready_o(dma_data_ready_o)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_yumi_i(dma_data_yumi_i)
,.data_mem_v_o(dma_data_mem_v_lo)
,.data_mem_w_o(dma_data_mem_w_lo)
,.data_mem_addr_o(dma_data_mem_addr_lo)
,.data_mem_w_mask_o(dma_data_mem_w_mask_lo)
,.data_mem_data_o(dma_data_mem_data_lo)
,.data_mem_data_i(data_mem_data_lo)
,.dma_evict_o(dma_evict_lo)
);
// store buffer
//
`declare_bsg_cache_sbuf_entry_s(addr_width_p, data_width_p, ways_p);
logic sbuf_v_li;
bsg_cache_sbuf_entry_s sbuf_entry_li;
logic sbuf_v_lo;
logic sbuf_yumi_li;
bsg_cache_sbuf_entry_s sbuf_entry_lo;
logic [addr_width_p-1:0] bypass_addr_li;
logic bypass_v_li;
logic [data_width_p-1:0] bypass_data_lo;
logic [data_mask_width_lp-1:0] bypass_mask_lo;
logic sbuf_full_lo;
bsg_cache_sbuf #(
.data_width_p(data_width_p)
,.addr_width_p(addr_width_p)
,.ways_p(ways_p)
) sbuf (
.clk_i(clk_i)
,.reset_i(reset_i)
,.sbuf_entry_i(sbuf_entry_li)
,.v_i(sbuf_v_li)
,.sbuf_entry_o(sbuf_entry_lo)
,.v_o(sbuf_v_lo)
,.yumi_i(sbuf_yumi_li)
,.empty_o(sbuf_empty_li)
,.full_o(sbuf_full_lo)
,.bypass_addr_i(bypass_addr_li)
,.bypass_v_i(bypass_v_li)
,.bypass_data_o(bypass_data_lo)
,.bypass_mask_o(bypass_mask_lo)
);
logic [ways_p-1:0] sbuf_way_decode;
bsg_decode #(
.num_out_p(ways_p)
) sbuf_way_demux (
.i(sbuf_entry_lo.way_id)
,.o(sbuf_way_decode)
);
logic [burst_size_in_words_lp-1:0] sbuf_burst_offset_decode;
bsg_decode #(
.num_out_p(burst_size_in_words_lp)
) sbuf_bo_demux (
.i(sbuf_entry_lo.addr[lg_data_mask_width_lp+:lg_burst_size_in_words_lp])
,.o(sbuf_burst_offset_decode)
);
logic [dma_data_mask_width_lp-1:0] sbuf_expand_mask;
bsg_expand_bitmask #(
.in_width_p(burst_size_in_words_lp)
,.expand_p(data_mask_width_lp)
) expand0 (
.i(sbuf_burst_offset_decode)
,.o(sbuf_expand_mask)
);
logic [ways_p-1:0][dma_data_mask_width_lp-1:0] sbuf_data_mem_w_mask;
logic [ways_p-1:0][dma_data_width_p-1:0] sbuf_data_mem_data;
logic [lg_data_mem_els_lp-1:0] sbuf_data_mem_addr;
for (genvar i = 0 ; i < ways_p; i++) begin
assign sbuf_data_mem_data[i] = {burst_size_in_words_lp{sbuf_entry_lo.data}};
assign sbuf_data_mem_w_mask[i] = sbuf_way_decode[i]
? (sbuf_expand_mask & {burst_size_in_words_lp{sbuf_entry_lo.mask}})
: '0;
end
if (burst_len_lp == 1) begin
assign sbuf_data_mem_addr = sbuf_entry_lo.addr[block_offset_width_lp+:lg_sets_lp];
end
else if (burst_len_lp == block_size_in_words_p) begin
assign sbuf_data_mem_addr = sbuf_entry_lo.addr[lg_data_mask_width_lp+:lg_block_size_in_words_lp+lg_sets_lp];
end
else begin
assign sbuf_data_mem_addr = sbuf_entry_lo.addr[lg_data_mask_width_lp+lg_burst_size_in_words_lp+:lg_burst_len_lp+lg_sets_lp];
end
// store buffer data/mask input
//
logic [data_sel_mux_els_lp-1:0][data_width_p-1:0] sbuf_data_in_mux_li;
logic [data_sel_mux_els_lp-1:0][data_mask_width_lp-1:0] sbuf_mask_in_mux_li;
logic [data_width_p-1:0] sbuf_data_in;
logic [data_mask_width_lp-1:0] sbuf_mask_in;
logic [data_width_p-1:0] snoop_or_ld_data;
logic [data_sel_mux_els_lp-1:0][data_width_p-1:0] ld_data_final_li;
logic [data_width_p-1:0] ld_data_final_lo;
bsg_mux #(
.width_p(data_width_p)
,.els_p(data_sel_mux_els_lp)
) sbuf_data_in_mux (
.data_i(sbuf_data_in_mux_li)
,.sel_i(decode_v_r.data_size_op[0+:lg_data_sel_mux_els_lp])
,.data_o(sbuf_data_in)
);
bsg_mux #(
.width_p(data_mask_width_lp)
,.els_p(data_sel_mux_els_lp)
) sbuf_mask_in_mux (
.data_i(sbuf_mask_in_mux_li)
,.sel_i(decode_v_r.data_size_op[0+:lg_data_sel_mux_els_lp])
,.data_o(sbuf_mask_in)
);
//
// Atomic operations
// Defined only for 32/64 operations
// Data incoming from cache_pkt
logic [`BSG_MIN(data_width_p, 64)-1:0] atomic_reg_data;
// Data read from the cache line
logic [`BSG_MIN(data_width_p, 64)-1:0] atomic_mem_data;
// Result of the atomic
logic [`BSG_MIN(data_width_p, 64)-1:0] atomic_alu_result;
// Final atomic data for store buffer
logic [`BSG_MIN(data_width_p, 64)-1:0] atomic_result;
// Shift data to high bits for operations less than 64-bits
// This allows us to share the arithmetic operators for 32/64 bit atomics
if (data_width_p >= 64) begin : atomic_64
wire [63:0] amo32_reg_in = data_v_r[0+:32] << 32;
wire [63:0] amo64_reg_in = data_v_r[0+:64];
assign atomic_reg_data = decode_v_r.data_size_op[0] ? amo64_reg_in : amo32_reg_in;
wire [63:0] amo32_mem_in = ld_data_final_li[2][0+:32] << 32;
wire [63:0] amo64_mem_in = ld_data_final_li[3][0+:64];
assign atomic_mem_data = decode_v_r.data_size_op[0] ? amo64_mem_in : amo32_mem_in;
end
else if (data_width_p >= 32) begin : atomic_32
assign atomic_reg_data = data_v_r[0+:32];
assign atomic_mem_data = ld_data_final_li[2];
end
// Atomic ALU
always_comb begin
// This logic was confirmed not to synthesize unsupported operators in
// Synopsys DC O-2018.06-SP4
unique casez({amo_support_p[decode_v_r.amo_subop], decode_v_r.amo_subop})
{1'b1, e_cache_amo_swap}: atomic_alu_result = atomic_reg_data;
{1'b1, e_cache_amo_and }: atomic_alu_result = atomic_reg_data & atomic_mem_data;
{1'b1, e_cache_amo_or }: atomic_alu_result = atomic_reg_data | atomic_mem_data;
{1'b1, e_cache_amo_xor }: atomic_alu_result = atomic_reg_data ^ atomic_mem_data;
{1'b1, e_cache_amo_add }: atomic_alu_result = atomic_reg_data + atomic_mem_data;
{1'b1, e_cache_amo_min }: atomic_alu_result =
(signed'(atomic_reg_data) < signed'(atomic_mem_data)) ? atomic_reg_data : atomic_mem_data;
{1'b1, e_cache_amo_max }: atomic_alu_result =
(signed'(atomic_reg_data) > signed'(atomic_mem_data)) ? atomic_reg_data : atomic_mem_data;
{1'b1, e_cache_amo_minu}: atomic_alu_result =
(atomic_reg_data < atomic_mem_data) ? atomic_reg_data : atomic_mem_data;
{1'b1, e_cache_amo_maxu}: atomic_alu_result =
(atomic_reg_data > atomic_mem_data) ? atomic_reg_data : atomic_mem_data;
// Noisily fail in simulation if an unsupported AMO operation is requested
{1'b0, 4'b???? }: atomic_alu_result = `BSG_UNDEFINED_IN_SIM(0);
default: atomic_alu_result = '0;
endcase
end
// Shift data from high bits for operations less than 64-bits
if (data_width_p >= 64) begin : fi
wire [63:0] amo32_out = atomic_alu_result >> 32;
wire [63:0] amo64_out = atomic_alu_result;
assign atomic_result = decode_v_r.data_size_op[0] ? amo64_out : amo32_out;
end
else begin
assign atomic_result = atomic_alu_result;
end
for (genvar i = 0; i < data_sel_mux_els_lp; i++) begin: sbuf_in_sel
localparam slice_width_lp = (8*(2**i));
logic [slice_width_lp-1:0] slice_data;
// AMO computation
// AMOs are only supported for words and double words
if ((i == 2'b10) || (i == 2'b11)) begin: atomic_in_sel
assign slice_data = decode_v_r.atomic_op
? atomic_result[0+:slice_width_lp]
: data_v_r[0+:slice_width_lp];
end
else begin
assign slice_data = data_v_r[0+:slice_width_lp];
end
assign sbuf_data_in_mux_li[i] = {(data_width_p/slice_width_lp){slice_data}};
logic [(data_width_p/slice_width_lp)-1:0] decode_lo;
bsg_decode #(
.num_out_p(data_width_p/slice_width_lp)
) dec (
.i(addr_v_r[i+:`BSG_MAX(lg_data_mask_width_lp-i,1)])
,.o(decode_lo)
);
bsg_expand_bitmask #(
.in_width_p(data_width_p/slice_width_lp)
,.expand_p(2**i)
) exp (
.i(decode_lo)
,.o(sbuf_mask_in_mux_li[i])
);
end
// store buffer data,mask input
always_comb begin
if (decode_v_r.mask_op) begin
sbuf_entry_li.data = data_v_r;
sbuf_entry_li.mask = mask_v_r;
end
else begin
sbuf_entry_li.data = sbuf_data_in;
sbuf_entry_li.mask = sbuf_mask_in;
end
end
// output stage
//
logic [dma_data_width_p-1:0] ld_data_way_picked;
logic [data_width_p-1:0] ld_data_offset_picked;
logic [data_width_p-1:0] bypass_data_masked;
logic [data_width_p-1:0] ld_data_masked;
bsg_mux #(
.width_p(dma_data_width_p)
,.els_p(ways_p)
) ld_data_mux (
.data_i(ld_data_v_r)
,.sel_i(tag_hit_way_id)
,.data_o(ld_data_way_picked)
);
bsg_mux #(
.width_p(data_width_p)
,.els_p(burst_size_in_words_lp)
) mux00 (
.data_i(ld_data_way_picked)
,.sel_i(addr_v_r[lg_data_mask_width_lp+:lg_burst_size_in_words_lp])
,.data_o(ld_data_offset_picked)
);
bsg_mux_segmented #(
.segments_p(data_mask_width_lp)
,.segment_width_p(8)
) bypass_mux_segmented (
.data0_i(ld_data_offset_picked)
,.data1_i(bypass_data_lo)
,.sel_i(bypass_mask_lo)
,.data_o(bypass_data_masked)
);
assign snoop_or_ld_data = select_snoop_data_r_lo
? snoop_word_lo
: bypass_data_masked;
logic [data_width_p-1:0] expanded_mask_v;
bsg_expand_bitmask #(
.in_width_p(data_mask_width_lp)
,.expand_p(8)
) mask_v_expand (
.i(mask_v_r)
,.o(expanded_mask_v)
);
assign ld_data_masked = snoop_or_ld_data & expanded_mask_v;
// select double/word/half/byte load data
//
for (genvar i = 0; i < data_sel_mux_els_lp; i++) begin: ld_data_sel
logic [(8*(2**i))-1:0] byte_sel;
bsg_mux #(
.width_p(8*(2**i))
,.els_p(data_width_p/(8*(2**i)))
) byte_mux (
.data_i(snoop_or_ld_data)
,.sel_i(addr_v_r[i+:`BSG_MAX(lg_data_mask_width_lp-i,1)])
,.data_o(byte_sel)
);
assign ld_data_final_li[i] =
{{(data_width_p-(8*(2**i))){decode_v_r.sigext_op & byte_sel[(8*(2**i))-1]}}, byte_sel};
end
bsg_mux #(
.width_p(data_width_p)
,.els_p(data_sel_mux_els_lp)
) ld_data_size_mux (
.data_i(ld_data_final_li)
,.sel_i(decode_v_r.data_size_op[0+:lg_data_sel_mux_els_lp])
,.data_o(ld_data_final_lo)
);
// final output mux
always_comb begin
if (retval_op_v) begin
if (decode_v_r.taglv_op) begin
data_o = {{(data_width_p-2){1'b0}}, lock_v_r[addr_way_v], valid_v_r[addr_way_v]};
end
else if (decode_v_r.tagla_op) begin
data_o = {tag_v_r[addr_way_v], addr_index_v, {(block_offset_width_lp){1'b0}}};
end
else if (decode_v_r.mask_op) begin
data_o = ld_data_masked;
end
else begin
data_o = ld_data_final_lo;
end
end
else begin
data_o = '0;
end
end
// ctrl logic
//
assign v_o = v_v_r & (miss_v
? miss_done_lo
: 1'b1);
assign v_we = v_v_r
? (v_o & yumi_i)
: 1'b1;
// when the store buffer is full, and the TV stage is inserting another entry,
// load/atomic cannot enter tl stage.
assign sbuf_hazard = (sbuf_full_lo & (v_o & yumi_i & (decode_v_r.st_op | decode_v_r.atomic_op)))
& (v_i & (decode.ld_op | decode.atomic_op));
// during miss, tl pipeline cannot take next instruction when
// 1) input is tagst
// 2) miss handler is writing to tag_mem
// 3) dma engine is writing to data_mem
// 4) tl_stage is recovering from tag_miss
// 5) DMA is evicting a block.
wire tl_ready = (miss_v
? (~(decode.tagst_op & v_i) & ~miss_tag_mem_v_lo & ~dma_data_mem_v_lo & ~recover_lo & ~dma_evict_lo)
: 1'b1) & ~sbuf_hazard;
assign ready_o = v_tl_r
? (v_we & tl_ready)
: tl_ready;
// tag_mem
// values written by tagst command
logic tagst_valid;
logic tagst_lock;
logic [tag_width_lp-1:0] tagst_tag;
logic tagst_write_en;
assign tagst_valid = cache_pkt.data[data_width_p-1];
assign tagst_lock = cache_pkt.data[data_width_p-2];
assign tagst_tag = cache_pkt.data[0+:tag_width_lp];
assign tagst_write_en = decode.tagst_op & ready_o & v_i;
logic [ways_p-1:0] addr_way_decode;
bsg_decode #(
.num_out_p(ways_p)
) addr_way_demux (
.i(addr_way)
,.o(addr_way_decode)
);
assign tag_mem_v_li = (decode.tag_read_op & ready_o & v_i)
| (recover_lo & decode_tl_r.tag_read_op & v_tl_r)
| miss_tag_mem_v_lo
| (decode.tagst_op & ready_o & v_i);
assign tag_mem_w_li = miss_v
? miss_tag_mem_w_lo
: tagst_write_en;
always_comb begin
if (miss_v) begin
tag_mem_addr_li = recover_lo
? addr_index_tl
: (miss_tag_mem_v_lo ? miss_tag_mem_addr_lo : addr_index);
tag_mem_data_li = miss_tag_mem_data_lo;
tag_mem_w_mask_li = miss_tag_mem_w_mask_lo;
end
else begin
// for TAGST
tag_mem_addr_li = addr_index;
for (integer i = 0; i < ways_p; i++) begin
tag_mem_data_li[i] = {tagst_valid, tagst_lock, tagst_tag};
tag_mem_w_mask_li[i] = {tag_info_width_lp{addr_way_decode[i]}};
end
end
end
// data_mem ctrl logic
//
assign data_mem_v_li = ((v_i & ready_o & (decode.ld_op | decode.atomic_op))
| (v_tl_r & recover_lo & (decode_tl_r.ld_op | decode_tl_r.atomic_op))
| dma_data_mem_v_lo
| (sbuf_v_lo & sbuf_yumi_li)
);
assign data_mem_w_li = dma_data_mem_w_lo | (sbuf_v_lo & sbuf_yumi_li);
assign data_mem_data_li = dma_data_mem_w_lo
? dma_data_mem_data_lo
: sbuf_data_mem_data;
assign data_mem_addr_li = recover_lo
? recover_data_mem_addr
: (dma_data_mem_v_lo
? dma_data_mem_addr_lo
: (((decode.ld_op | decode.atomic_op) & v_i & ready_o)
? ld_data_mem_addr
: sbuf_data_mem_addr));
assign data_mem_w_mask_li = dma_data_mem_w_lo
? dma_data_mem_w_mask_lo
: sbuf_data_mem_w_mask;
// stat_mem ctrl logic
// TAGST clears the stat_info as it exits tv stage.
// If it's load or store, and there is a hit, it updates the dirty bits and LRU.
// If there is a miss, stat_mem may be modified by the miss handler.
logic [ways_p-2:0] plru_decode_data_lo;
logic [ways_p-2:0] plru_decode_mask_lo;
bsg_lru_pseudo_tree_decode #(
.ways_p(ways_p)
) plru_decode (
.way_id_i(tag_hit_way_id)
,.data_o(plru_decode_data_lo)
,.mask_o(plru_decode_mask_lo)
);
always_comb begin
if (miss_v) begin
stat_mem_v_li = miss_stat_mem_v_lo;
stat_mem_w_li = miss_stat_mem_w_lo;
stat_mem_addr_li = miss_stat_mem_addr_lo; // essentially same as addr_index_v
stat_mem_data_li = miss_stat_mem_data_lo;
stat_mem_w_mask_li = miss_stat_mem_w_mask_lo;
end
else begin
stat_mem_v_li = ((decode_v_r.st_op | decode_v_r.ld_op | decode_v_r.tagst_op | decode_v_r.atomic_op) & v_o & yumi_i);
stat_mem_w_li = ((decode_v_r.st_op | decode_v_r.ld_op | decode_v_r.tagst_op | decode_v_r.atomic_op) & v_o & yumi_i);
stat_mem_addr_li = addr_index_v;
if (decode_v_r.tagst_op) begin
// for TAGST
stat_mem_data_li.dirty = {ways_p{1'b0}};
stat_mem_data_li.lru_bits = {(ways_p-1){1'b0}};
stat_mem_w_mask_li.dirty = {ways_p{1'b1}};
stat_mem_w_mask_li.lru_bits = {(ways_p-1){1'b1}};
end
else begin
// for LD, ST
stat_mem_data_li.dirty = {ways_p{decode_v_r.st_op | decode_v_r.atomic_op}};
stat_mem_data_li.lru_bits = plru_decode_data_lo;
stat_mem_w_mask_li.dirty = {ways_p{decode_v_r.st_op | decode_v_r.atomic_op}} & tag_hit_v;
stat_mem_w_mask_li.lru_bits = plru_decode_mask_lo;
end
end
end
// store buffer
//
assign sbuf_v_li = (decode_v_r.st_op | decode_v_r.atomic_op) & v_o & yumi_i;
assign sbuf_entry_li.way_id = miss_v ? chosen_way_lo : tag_hit_way_id;
assign sbuf_entry_li.addr = addr_v_r;
// store buffer can write to dmem when
// 1) there is valid entry in store buffer.
// 2) incoming request does not read DMEM.
// 3) DMA engine is not accessing DMEM.
// 4) TL read DMEM (and bypass from sbuf), and TV is not stalled (v_we).
// During miss, the store buffer can be drained.
assign sbuf_yumi_li = sbuf_v_lo
& ~((decode.ld_op | decode.atomic_op) & v_i & ready_o)
& (~dma_data_mem_v_lo)
& ~(v_tl_r & (decode_tl_r.ld_op | decode_tl_r.atomic_op) & (~v_we) & (~miss_v));
assign bypass_addr_li = addr_tl_r;
assign bypass_v_li = (decode_tl_r.ld_op | decode_tl_r.atomic_op) & v_tl_r & v_we;
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (v_v_r) begin
// check that there is no multiple hit.
assert($countones(tag_hit_v) <= 1)
else $error("[BSG_ERROR][BSG_CACHE] Multiple cache hit detected. %m, T=%t", $time);
// check that there is at least one unlocked way in a set.
assert($countones(lock_v_r) < ways_p)
else $error("[BSG_ERROR][BSG_CACHE] There should be at least one unlocked way in a set. %m, T=%t", $time);
// Check that client hasn't required unsupported AMO
assert(~decode_v_r.atomic_op | amo_support_p[decode_v_r.amo_subop])
else $error("[BSG_ERROR][BSG_CACHE] Unsupported AMO OP %d received. %m, T=%t", decode.amo_subop, $time);
assert(~decode_v_r.atomic_op || (data_width_p >= 64) || ~decode_v_r.data_size_op[0])
else $error("[BSG_ERROR][BSG_CACHE] AMO_D performed on data_width < 64. %m T=%t", $time);
assert(~decode_v_r.atomic_op || (data_width_p >= 32))
else $error("[BSG_ERROR][BSG_CACHE] AMO performed on data_width < 32. %m T=%t", $time);
end
end
end
if (debug_p) begin
always_ff @ (posedge clk_i) begin
if (v_o & yumi_i) begin
if (decode_v_r.ld_op) begin
$display("<VCACHE> M[%4h] == %8h // %8t", addr_v_r, data_o, $time);
end
if (decode_v_r.st_op) begin
$display("<VCACHE> M[%4h] := %8h // %8t", addr_v_r, sbuf_entry_li.data, $time);
end
end
if (tag_mem_v_li & tag_mem_w_li) begin
$display("<VCACHE> tag_mem_write. addr=%8h data_1=%8h data_0=%8h mask_1=%8h mask_0=%8h // %8t",
tag_mem_addr_li,
tag_mem_data_li[1+tag_width_lp+:1+tag_width_lp],
tag_mem_data_li[0+:1+tag_width_lp],
tag_mem_w_mask_li[1+tag_width_lp+:1+tag_width_lp],
tag_mem_w_mask_li[0+:1+tag_width_lp],
$time
);
end
end
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache)
|
`define WIDTH_P 2
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
This module generates gray codes of every possible binary number of WIDTH_P
and feeds these vales as test inputs to the DUT. An up-counter is used to
generate the binary numbers whose gray codes are test inputs to DUT. The
output of the DUT is compared with count to check correctness. Thus the DUT
is tested exhaustively for any given WIDTH_P.
2. PARAMETERIZATION
The DUT uses a module already defined in bsg_misc to calculate the
value of the input gray code. Hence tests with WIDTH_P = 1,2,..8 would give
sufficient confidence. Since the number of test cases grows exponentially
with WIDTH_P, simulations with WIDTH_P > 16 would take very long time to
complete apart from generating a large "output.log".
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_lo_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d\n", width_p);
end
logic [width_p-1:0] count, count_r;
bsg_cycle_counter #( .width_p(width_p)
) bcc
( .clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(count)
);
logic [width_p-1:0] test_input;
wire [width_p-1:0] test_output;
assign test_input = (count>>1) ^ count; // test_input is gray code of count
always_ff @(posedge clk)
begin
count_r <= count;
/*$display("\ntest_input: %b, count: %b, test_output: %b"
, test_input, count, test_output);*/
if(!reset)
assert(test_output == count)
else $error("mismatch on input %x", test_input);
if(!(|count) & (&count_r))
begin
$display("===============================================================\n");
$finish;
end
end
bsg_gray_to_binary #( .width_p(width_p)
) DUT
( .gray_i (test_input)
, .binary_o(test_output)
);
/*bsg_nonsynth_ascii_writer #( .width_p (width_p)
, .values_p (3)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("%x")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i ({test_output,
count,
test_input}
)
);*/
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Mar 22 12:42:23 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../io.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.1 2004/04/06 11:05:05 wig Exp $
// $Date: 2004/04/06 11:05:05 $
// $Log: inst_t_e.v,v $
// Revision 1.1 2004/04/06 11:05:05 wig
// Adding result/io
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No `defines in this module
module inst_t_e
//
// Generated module inst_t
//
(
sig_in_01,
sig_in_03,
sig_io_05,
sig_io_06,
sig_out_02,
sig_out_04
);
// Generated Module Inputs:
input sig_in_01;
input [7:0] sig_in_03;
// Generated Module In/Outputs:
inout [5:0] sig_io_05;
inout [6:0] sig_io_06;
// Generated Module Outputs:
output sig_out_02;
output [7:0] sig_out_04;
// Generated Wires:
wire sig_in_01;
wire [7:0] sig_in_03;
wire [5:0] sig_io_05;
wire [6:0] sig_io_06;
wire sig_out_02;
wire [7:0] sig_out_04;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_a
inst_a_e inst_a(
.p_mix_sig_in_01_gi(sig_in_01),
.p_mix_sig_in_03_gi(sig_in_03),
.p_mix_sig_io_05_gc(sig_io_05),
.p_mix_sig_io_06_gc(sig_io_06),
.p_mix_sig_out_02_go(sig_out_02),
.p_mix_sig_out_04_go(sig_out_04)
);
// End of Generated Instance Port Map for inst_a
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_TB_V
`define SKY130_FD_SC_LS__A41O_TB_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a41o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a41o dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:33:10 02/22/2015
// Design Name:
// Module Name: mult_k
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mult_k(
input [31:0] a_multiplicand,
input [31:0] b_multiplier,
input reset,
input clock,
output [31:0] FinalProduct
);
wire idle_Special, idle_Multiply, idle_NormaliseProd;
wire [32:0] aout_Special,bout_Special;
wire [32:0] zout_Special,zout_Multiply,zout_NormaliseProd;
wire [49:0] productout_Multiply, productout_NormaliseProd;
wire [31:0] FinalProduct_Idle1,FinalProduct_Idle2,FinalProduct_Idle3,FinalProduct_Idle4;
SpecialMult Mult1 (
.ain_Special(a_multiplicand),
.bin_Special(b_multiplier),
.reset(reset),
.clock(clock),
.idle_Special(idle_Special),
.aout_Special(aout_Special),
.bout_Special(bout_Special),
.zout_Special(zout_Special)
);
MultiplyMult Mult2 (
.aout_Special(aout_Special),
.bout_Special(bout_Special),
.zout_Special(zout_Special),
.idle_Special(idle_Special),
.clock(clock),
.idle_Multiply(idle_Multiply),
.zout_Multiply(zout_Multiply),
.productout_Multiply(productout_Multiply)
);
NormaliseProdMult Mult3 (
.zout_Multiply(zout_Multiply),
.productout_Multiply(productout_Multiply),
.clock(clock),
.idle_Multiply(idle_Multiply),
.idle_NormaliseProd(idle_NormaliseProd),
.zout_NormaliseProd(zout_NormaliseProd),
.productout_NormaliseProd(productout_NormaliseProd)
);
Pack_z Mult4 (
.idle_NormaliseProd(idle_NormaliseProd),
.zout_NormaliseProd(zout_NormaliseProd),
.productout_NormaliseProd(productout_NormaliseProd),
.clock(clock),
.FinalProduct(FinalProduct_Idle1)
);
IdleMult Mult5 (
.FinalProduct(FinalProduct_Idle1),
.clock(clock),
.FinalProductout(FinalProduct_Idle2)
);
IdleMult Mult6 (
.FinalProduct(FinalProduct_Idle2),
.clock(clock),
.FinalProductout(FinalProduct_Idle3)
);
IdleMult Mult7 (
.FinalProduct(FinalProduct_Idle3),
.clock(clock),
.FinalProductout(FinalProduct_Idle4)
);
IdleMult Mult8 (
.FinalProduct(FinalProduct_Idle4),
.clock(clock),
.FinalProductout(FinalProduct)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_dram_sc_bank0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//////////////////////////////////////////////////////////////////////
// Flop repeater for L2<-> dram controller signals.
// This repeter block has
// 8 row of data flops and 4 rows of ctl/addr flops.
// The 8 data rows are placed in one column ( 39 bits wide )
// the 4 addr/ctl rows are placed in one column ( 13 bits wide )
//////////////////////////////////////////////////////////////////////
module ff_dram_sc_bank0(/*AUTOARG*/
// Outputs
dram_scbuf_data_r2_d1, dram_scbuf_ecc_r2_d1,
scbuf_dram_wr_data_r5_d1, scbuf_dram_data_vld_r5_d1,
scbuf_dram_data_mecc_r5_d1, sctag_dram_rd_req_d1,
sctag_dram_rd_dummy_req_d1, sctag_dram_rd_req_id_d1,
sctag_dram_addr_d1, sctag_dram_wr_req_d1, dram_sctag_rd_ack_d1,
dram_sctag_wr_ack_d1, dram_sctag_chunk_id_r0_d1,
dram_sctag_data_vld_r0_d1, dram_sctag_rd_req_id_r0_d1,
dram_sctag_secc_err_r2_d1, dram_sctag_mecc_err_r2_d1,
dram_sctag_scb_mecc_err_d1, dram_sctag_scb_secc_err_d1, so,
// Inputs
dram_scbuf_data_r2, dram_scbuf_ecc_r2, scbuf_dram_wr_data_r5,
scbuf_dram_data_vld_r5, scbuf_dram_data_mecc_r5,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, dram_sctag_rd_ack,
dram_sctag_wr_ack, dram_sctag_chunk_id_r0, dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0, dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err, rclk, si, se
);
// dram-scbuf TOP
input [127:0] dram_scbuf_data_r2;
input [27:0] dram_scbuf_ecc_r2;
// BOTTOM
output [127:0] dram_scbuf_data_r2_d1;
output [27:0] dram_scbuf_ecc_r2_d1;
// scbuf to dram BOTTOM
input [63:0] scbuf_dram_wr_data_r5;
input scbuf_dram_data_vld_r5;
input scbuf_dram_data_mecc_r5;
// TOP
output [63:0] scbuf_dram_wr_data_r5_d1;
output scbuf_dram_data_vld_r5_d1;
output scbuf_dram_data_mecc_r5_d1;
// sctag_dram-sctag signals INputs
// @ the bottom.
// Outputs @ the top.
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
input sctag_dram_wr_req;
//
output sctag_dram_rd_req_d1;
output sctag_dram_rd_dummy_req_d1;
output [2:0] sctag_dram_rd_req_id_d1;
output [39:5] sctag_dram_addr_d1;
output sctag_dram_wr_req_d1;
// dram-sctag signals. Outputs @ bottom
// and Input pins on top.
input dram_sctag_rd_ack;
input dram_sctag_wr_ack;
input [1:0] dram_sctag_chunk_id_r0;
input dram_sctag_data_vld_r0;
input [2:0] dram_sctag_rd_req_id_r0;
input dram_sctag_secc_err_r2 ;
input dram_sctag_mecc_err_r2 ;
input dram_sctag_scb_mecc_err;
input dram_sctag_scb_secc_err;
//
output dram_sctag_rd_ack_d1;
output dram_sctag_wr_ack_d1;
output [1:0] dram_sctag_chunk_id_r0_d1;
output dram_sctag_data_vld_r0_d1;
output [2:0] dram_sctag_rd_req_id_r0_d1;
output dram_sctag_secc_err_r2_d1 ;
output dram_sctag_mecc_err_r2_d1 ;
output dram_sctag_scb_mecc_err_d1;
output dram_sctag_scb_secc_err_d1;
input rclk;
input si, se;
output so;
// dram-scbuf signals. 8 rows of flops.
// Input at the top and output at the bottom.
dff_s #(39) ff_flop_bank0_row_0 (.q({dram_scbuf_data_r2_d1[127],
dram_scbuf_data_r2_d1[123],
dram_scbuf_data_r2_d1[119],
dram_scbuf_data_r2_d1[115],
dram_scbuf_data_r2_d1[111],
dram_scbuf_data_r2_d1[107],
dram_scbuf_data_r2_d1[103],
dram_scbuf_data_r2_d1[99],
dram_scbuf_data_r2_d1[95],
dram_scbuf_data_r2_d1[91],
dram_scbuf_data_r2_d1[87],
dram_scbuf_data_r2_d1[83],
dram_scbuf_data_r2_d1[79],
dram_scbuf_data_r2_d1[75],
dram_scbuf_data_r2_d1[71],
dram_scbuf_data_r2_d1[67],
dram_scbuf_data_r2_d1[63],
dram_scbuf_data_r2_d1[59],
dram_scbuf_data_r2_d1[55],
dram_scbuf_data_r2_d1[51],
dram_scbuf_data_r2_d1[47],
dram_scbuf_data_r2_d1[43],
dram_scbuf_data_r2_d1[39],
dram_scbuf_data_r2_d1[35],
dram_scbuf_data_r2_d1[31],
dram_scbuf_data_r2_d1[27],
dram_scbuf_data_r2_d1[23],
dram_scbuf_data_r2_d1[19],
dram_scbuf_data_r2_d1[15],
dram_scbuf_data_r2_d1[11],
dram_scbuf_data_r2_d1[7],
dram_scbuf_data_r2_d1[3],
dram_scbuf_ecc_r2_d1[27],
dram_scbuf_ecc_r2_d1[23],
dram_scbuf_ecc_r2_d1[19],
dram_scbuf_ecc_r2_d1[15],
dram_scbuf_ecc_r2_d1[11],
dram_scbuf_ecc_r2_d1[7],
dram_scbuf_ecc_r2_d1[3] }),
.din({dram_scbuf_data_r2[127],
dram_scbuf_data_r2[123],
dram_scbuf_data_r2[119],
dram_scbuf_data_r2[115],
dram_scbuf_data_r2[111],
dram_scbuf_data_r2[107],
dram_scbuf_data_r2[103],
dram_scbuf_data_r2[99],
dram_scbuf_data_r2[95],
dram_scbuf_data_r2[91],
dram_scbuf_data_r2[87],
dram_scbuf_data_r2[83],
dram_scbuf_data_r2[79],
dram_scbuf_data_r2[75],
dram_scbuf_data_r2[71],
dram_scbuf_data_r2[67],
dram_scbuf_data_r2[63],
dram_scbuf_data_r2[59],
dram_scbuf_data_r2[55],
dram_scbuf_data_r2[51],
dram_scbuf_data_r2[47],
dram_scbuf_data_r2[43],
dram_scbuf_data_r2[39],
dram_scbuf_data_r2[35],
dram_scbuf_data_r2[31],
dram_scbuf_data_r2[27],
dram_scbuf_data_r2[23],
dram_scbuf_data_r2[19],
dram_scbuf_data_r2[15],
dram_scbuf_data_r2[11],
dram_scbuf_data_r2[7],
dram_scbuf_data_r2[3],
dram_scbuf_ecc_r2[27],
dram_scbuf_ecc_r2[23],
dram_scbuf_ecc_r2[19],
dram_scbuf_ecc_r2[15],
dram_scbuf_ecc_r2[11],
dram_scbuf_ecc_r2[7],
dram_scbuf_ecc_r2[3]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_1 (.q({dram_scbuf_data_r2_d1[126],
dram_scbuf_data_r2_d1[122],
dram_scbuf_data_r2_d1[118],
dram_scbuf_data_r2_d1[114],
dram_scbuf_data_r2_d1[110],
dram_scbuf_data_r2_d1[106],
dram_scbuf_data_r2_d1[102],
dram_scbuf_data_r2_d1[98],
dram_scbuf_data_r2_d1[94],
dram_scbuf_data_r2_d1[90],
dram_scbuf_data_r2_d1[86],
dram_scbuf_data_r2_d1[82],
dram_scbuf_data_r2_d1[78],
dram_scbuf_data_r2_d1[74],
dram_scbuf_data_r2_d1[70],
dram_scbuf_data_r2_d1[66],
dram_scbuf_data_r2_d1[62],
dram_scbuf_data_r2_d1[58],
dram_scbuf_data_r2_d1[54],
dram_scbuf_data_r2_d1[50],
dram_scbuf_data_r2_d1[46],
dram_scbuf_data_r2_d1[42],
dram_scbuf_data_r2_d1[38],
dram_scbuf_data_r2_d1[34],
dram_scbuf_data_r2_d1[30],
dram_scbuf_data_r2_d1[26],
dram_scbuf_data_r2_d1[22],
dram_scbuf_data_r2_d1[18],
dram_scbuf_data_r2_d1[14],
dram_scbuf_data_r2_d1[10],
dram_scbuf_data_r2_d1[6],
dram_scbuf_data_r2_d1[2],
dram_scbuf_ecc_r2_d1[26],
dram_scbuf_ecc_r2_d1[22],
dram_scbuf_ecc_r2_d1[18],
dram_scbuf_ecc_r2_d1[14],
dram_scbuf_ecc_r2_d1[10],
dram_scbuf_ecc_r2_d1[6],
dram_scbuf_ecc_r2_d1[2] }),
.din({dram_scbuf_data_r2[126],
dram_scbuf_data_r2[122],
dram_scbuf_data_r2[118],
dram_scbuf_data_r2[114],
dram_scbuf_data_r2[110],
dram_scbuf_data_r2[106],
dram_scbuf_data_r2[102],
dram_scbuf_data_r2[98],
dram_scbuf_data_r2[94],
dram_scbuf_data_r2[90],
dram_scbuf_data_r2[86],
dram_scbuf_data_r2[82],
dram_scbuf_data_r2[78],
dram_scbuf_data_r2[74],
dram_scbuf_data_r2[70],
dram_scbuf_data_r2[66],
dram_scbuf_data_r2[62],
dram_scbuf_data_r2[58],
dram_scbuf_data_r2[54],
dram_scbuf_data_r2[50],
dram_scbuf_data_r2[46],
dram_scbuf_data_r2[42],
dram_scbuf_data_r2[38],
dram_scbuf_data_r2[34],
dram_scbuf_data_r2[30],
dram_scbuf_data_r2[26],
dram_scbuf_data_r2[22],
dram_scbuf_data_r2[18],
dram_scbuf_data_r2[14],
dram_scbuf_data_r2[10],
dram_scbuf_data_r2[6],
dram_scbuf_data_r2[2],
dram_scbuf_ecc_r2[26],
dram_scbuf_ecc_r2[22],
dram_scbuf_ecc_r2[18],
dram_scbuf_ecc_r2[14],
dram_scbuf_ecc_r2[10],
dram_scbuf_ecc_r2[6],
dram_scbuf_ecc_r2[2]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_2 (.q({dram_scbuf_data_r2_d1[125],
dram_scbuf_data_r2_d1[121],
dram_scbuf_data_r2_d1[117],
dram_scbuf_data_r2_d1[113],
dram_scbuf_data_r2_d1[109],
dram_scbuf_data_r2_d1[105],
dram_scbuf_data_r2_d1[101],
dram_scbuf_data_r2_d1[97],
dram_scbuf_data_r2_d1[93],
dram_scbuf_data_r2_d1[89],
dram_scbuf_data_r2_d1[85],
dram_scbuf_data_r2_d1[81],
dram_scbuf_data_r2_d1[77],
dram_scbuf_data_r2_d1[73],
dram_scbuf_data_r2_d1[69],
dram_scbuf_data_r2_d1[65],
dram_scbuf_data_r2_d1[61],
dram_scbuf_data_r2_d1[57],
dram_scbuf_data_r2_d1[53],
dram_scbuf_data_r2_d1[49],
dram_scbuf_data_r2_d1[45],
dram_scbuf_data_r2_d1[41],
dram_scbuf_data_r2_d1[37],
dram_scbuf_data_r2_d1[33],
dram_scbuf_data_r2_d1[29],
dram_scbuf_data_r2_d1[25],
dram_scbuf_data_r2_d1[21],
dram_scbuf_data_r2_d1[17],
dram_scbuf_data_r2_d1[13],
dram_scbuf_data_r2_d1[9],
dram_scbuf_data_r2_d1[5],
dram_scbuf_data_r2_d1[1],
dram_scbuf_ecc_r2_d1[25],
dram_scbuf_ecc_r2_d1[21],
dram_scbuf_ecc_r2_d1[17],
dram_scbuf_ecc_r2_d1[13],
dram_scbuf_ecc_r2_d1[9],
dram_scbuf_ecc_r2_d1[5],
dram_scbuf_ecc_r2_d1[1] }),
.din({dram_scbuf_data_r2[125],
dram_scbuf_data_r2[121],
dram_scbuf_data_r2[117],
dram_scbuf_data_r2[113],
dram_scbuf_data_r2[109],
dram_scbuf_data_r2[105],
dram_scbuf_data_r2[101],
dram_scbuf_data_r2[97],
dram_scbuf_data_r2[93],
dram_scbuf_data_r2[89],
dram_scbuf_data_r2[85],
dram_scbuf_data_r2[81],
dram_scbuf_data_r2[77],
dram_scbuf_data_r2[73],
dram_scbuf_data_r2[69],
dram_scbuf_data_r2[65],
dram_scbuf_data_r2[61],
dram_scbuf_data_r2[57],
dram_scbuf_data_r2[53],
dram_scbuf_data_r2[49],
dram_scbuf_data_r2[45],
dram_scbuf_data_r2[41],
dram_scbuf_data_r2[37],
dram_scbuf_data_r2[33],
dram_scbuf_data_r2[29],
dram_scbuf_data_r2[25],
dram_scbuf_data_r2[21],
dram_scbuf_data_r2[17],
dram_scbuf_data_r2[13],
dram_scbuf_data_r2[9],
dram_scbuf_data_r2[5],
dram_scbuf_data_r2[1],
dram_scbuf_ecc_r2[25],
dram_scbuf_ecc_r2[21],
dram_scbuf_ecc_r2[17],
dram_scbuf_ecc_r2[13],
dram_scbuf_ecc_r2[9],
dram_scbuf_ecc_r2[5],
dram_scbuf_ecc_r2[1]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(39) ff_flop_bank0_row_3 (.q({dram_scbuf_data_r2_d1[124],
dram_scbuf_data_r2_d1[120],
dram_scbuf_data_r2_d1[116],
dram_scbuf_data_r2_d1[112],
dram_scbuf_data_r2_d1[108],
dram_scbuf_data_r2_d1[104],
dram_scbuf_data_r2_d1[100],
dram_scbuf_data_r2_d1[96],
dram_scbuf_data_r2_d1[92],
dram_scbuf_data_r2_d1[88],
dram_scbuf_data_r2_d1[84],
dram_scbuf_data_r2_d1[80],
dram_scbuf_data_r2_d1[76],
dram_scbuf_data_r2_d1[72],
dram_scbuf_data_r2_d1[68],
dram_scbuf_data_r2_d1[64],
dram_scbuf_data_r2_d1[60],
dram_scbuf_data_r2_d1[56],
dram_scbuf_data_r2_d1[52],
dram_scbuf_data_r2_d1[48],
dram_scbuf_data_r2_d1[44],
dram_scbuf_data_r2_d1[40],
dram_scbuf_data_r2_d1[36],
dram_scbuf_data_r2_d1[32],
dram_scbuf_data_r2_d1[28],
dram_scbuf_data_r2_d1[24],
dram_scbuf_data_r2_d1[20],
dram_scbuf_data_r2_d1[16],
dram_scbuf_data_r2_d1[12],
dram_scbuf_data_r2_d1[8],
dram_scbuf_data_r2_d1[4],
dram_scbuf_data_r2_d1[0],
dram_scbuf_ecc_r2_d1[24],
dram_scbuf_ecc_r2_d1[20],
dram_scbuf_ecc_r2_d1[16],
dram_scbuf_ecc_r2_d1[12],
dram_scbuf_ecc_r2_d1[8],
dram_scbuf_ecc_r2_d1[4],
dram_scbuf_ecc_r2_d1[0] }),
.din({dram_scbuf_data_r2[124],
dram_scbuf_data_r2[120],
dram_scbuf_data_r2[116],
dram_scbuf_data_r2[112],
dram_scbuf_data_r2[108],
dram_scbuf_data_r2[104],
dram_scbuf_data_r2[100],
dram_scbuf_data_r2[96],
dram_scbuf_data_r2[92],
dram_scbuf_data_r2[88],
dram_scbuf_data_r2[84],
dram_scbuf_data_r2[80],
dram_scbuf_data_r2[76],
dram_scbuf_data_r2[72],
dram_scbuf_data_r2[68],
dram_scbuf_data_r2[64],
dram_scbuf_data_r2[60],
dram_scbuf_data_r2[56],
dram_scbuf_data_r2[52],
dram_scbuf_data_r2[48],
dram_scbuf_data_r2[44],
dram_scbuf_data_r2[40],
dram_scbuf_data_r2[36],
dram_scbuf_data_r2[32],
dram_scbuf_data_r2[28],
dram_scbuf_data_r2[24],
dram_scbuf_data_r2[20],
dram_scbuf_data_r2[16],
dram_scbuf_data_r2[12],
dram_scbuf_data_r2[8],
dram_scbuf_data_r2[4],
dram_scbuf_data_r2[0],
dram_scbuf_ecc_r2[24],
dram_scbuf_ecc_r2[20],
dram_scbuf_ecc_r2[16],
dram_scbuf_ecc_r2[12],
dram_scbuf_ecc_r2[8],
dram_scbuf_ecc_r2[4],
dram_scbuf_ecc_r2[0]}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_bank0_row_4 (.q({scbuf_dram_wr_data_r5_d1[63],
scbuf_dram_wr_data_r5_d1[61],
scbuf_dram_wr_data_r5_d1[59],
scbuf_dram_wr_data_r5_d1[57],
scbuf_dram_wr_data_r5_d1[55],
scbuf_dram_wr_data_r5_d1[53],
scbuf_dram_wr_data_r5_d1[51],
scbuf_dram_wr_data_r5_d1[49],
scbuf_dram_wr_data_r5_d1[47],
scbuf_dram_wr_data_r5_d1[45],
scbuf_dram_wr_data_r5_d1[43],
scbuf_dram_wr_data_r5_d1[41],
scbuf_dram_wr_data_r5_d1[39],
scbuf_dram_wr_data_r5_d1[37],
scbuf_dram_wr_data_r5_d1[35],
scbuf_dram_wr_data_r5_d1[33],
scbuf_dram_wr_data_r5_d1[31],
scbuf_dram_wr_data_r5_d1[29],
scbuf_dram_wr_data_r5_d1[27],
scbuf_dram_wr_data_r5_d1[25],
scbuf_dram_wr_data_r5_d1[23],
scbuf_dram_wr_data_r5_d1[21],
scbuf_dram_wr_data_r5_d1[19],
scbuf_dram_wr_data_r5_d1[17],
scbuf_dram_wr_data_r5_d1[15],
scbuf_dram_wr_data_r5_d1[13],
scbuf_dram_wr_data_r5_d1[11],
scbuf_dram_wr_data_r5_d1[9],
scbuf_dram_wr_data_r5_d1[7],
scbuf_dram_wr_data_r5_d1[5],
scbuf_dram_wr_data_r5_d1[3],
scbuf_dram_wr_data_r5_d1[1]} ),
.din({scbuf_dram_wr_data_r5[63],
scbuf_dram_wr_data_r5[61],
scbuf_dram_wr_data_r5[59],
scbuf_dram_wr_data_r5[57],
scbuf_dram_wr_data_r5[55],
scbuf_dram_wr_data_r5[53],
scbuf_dram_wr_data_r5[51],
scbuf_dram_wr_data_r5[49],
scbuf_dram_wr_data_r5[47],
scbuf_dram_wr_data_r5[45],
scbuf_dram_wr_data_r5[43],
scbuf_dram_wr_data_r5[41],
scbuf_dram_wr_data_r5[39],
scbuf_dram_wr_data_r5[37],
scbuf_dram_wr_data_r5[35],
scbuf_dram_wr_data_r5[33],
scbuf_dram_wr_data_r5[31],
scbuf_dram_wr_data_r5[29],
scbuf_dram_wr_data_r5[27],
scbuf_dram_wr_data_r5[25],
scbuf_dram_wr_data_r5[23],
scbuf_dram_wr_data_r5[21],
scbuf_dram_wr_data_r5[19],
scbuf_dram_wr_data_r5[17],
scbuf_dram_wr_data_r5[15],
scbuf_dram_wr_data_r5[13],
scbuf_dram_wr_data_r5[11],
scbuf_dram_wr_data_r5[9],
scbuf_dram_wr_data_r5[7],
scbuf_dram_wr_data_r5[5],
scbuf_dram_wr_data_r5[3],
scbuf_dram_wr_data_r5[1]} ),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(34) ff_bank0_row_5 (.q({scbuf_dram_wr_data_r5_d1[62],
scbuf_dram_wr_data_r5_d1[60],
scbuf_dram_wr_data_r5_d1[58],
scbuf_dram_wr_data_r5_d1[56],
scbuf_dram_wr_data_r5_d1[54],
scbuf_dram_wr_data_r5_d1[52],
scbuf_dram_wr_data_r5_d1[50],
scbuf_dram_wr_data_r5_d1[48],
scbuf_dram_wr_data_r5_d1[46],
scbuf_dram_wr_data_r5_d1[44],
scbuf_dram_wr_data_r5_d1[42],
scbuf_dram_wr_data_r5_d1[40],
scbuf_dram_wr_data_r5_d1[38],
scbuf_dram_wr_data_r5_d1[36],
scbuf_dram_wr_data_r5_d1[34],
scbuf_dram_wr_data_r5_d1[32],
scbuf_dram_wr_data_r5_d1[30],
scbuf_dram_wr_data_r5_d1[28],
scbuf_dram_wr_data_r5_d1[26],
scbuf_dram_wr_data_r5_d1[24],
scbuf_dram_wr_data_r5_d1[22],
scbuf_dram_wr_data_r5_d1[20],
scbuf_dram_wr_data_r5_d1[18],
scbuf_dram_wr_data_r5_d1[16],
scbuf_dram_wr_data_r5_d1[14],
scbuf_dram_wr_data_r5_d1[12],
scbuf_dram_wr_data_r5_d1[10],
scbuf_dram_wr_data_r5_d1[8],
scbuf_dram_wr_data_r5_d1[6],
scbuf_dram_wr_data_r5_d1[4],
scbuf_dram_wr_data_r5_d1[2],
scbuf_dram_wr_data_r5_d1[0],
scbuf_dram_data_mecc_r5_d1,
scbuf_dram_data_vld_r5_d1
} ),
.din({scbuf_dram_wr_data_r5[62],
scbuf_dram_wr_data_r5[60],
scbuf_dram_wr_data_r5[58],
scbuf_dram_wr_data_r5[56],
scbuf_dram_wr_data_r5[54],
scbuf_dram_wr_data_r5[52],
scbuf_dram_wr_data_r5[50],
scbuf_dram_wr_data_r5[48],
scbuf_dram_wr_data_r5[46],
scbuf_dram_wr_data_r5[44],
scbuf_dram_wr_data_r5[42],
scbuf_dram_wr_data_r5[40],
scbuf_dram_wr_data_r5[38],
scbuf_dram_wr_data_r5[36],
scbuf_dram_wr_data_r5[34],
scbuf_dram_wr_data_r5[32],
scbuf_dram_wr_data_r5[30],
scbuf_dram_wr_data_r5[28],
scbuf_dram_wr_data_r5[26],
scbuf_dram_wr_data_r5[24],
scbuf_dram_wr_data_r5[22],
scbuf_dram_wr_data_r5[20],
scbuf_dram_wr_data_r5[18],
scbuf_dram_wr_data_r5[16],
scbuf_dram_wr_data_r5[14],
scbuf_dram_wr_data_r5[12],
scbuf_dram_wr_data_r5[10],
scbuf_dram_wr_data_r5[8],
scbuf_dram_wr_data_r5[6],
scbuf_dram_wr_data_r5[4],
scbuf_dram_wr_data_r5[2],
scbuf_dram_wr_data_r5[0],
scbuf_dram_data_mecc_r5,
scbuf_dram_data_vld_r5 }),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(41) ff_flop_bank0_col1_row012 (.q({sctag_dram_addr_d1[39:5],
sctag_dram_rd_req_id_d1[2:0],
sctag_dram_wr_req_d1,
sctag_dram_rd_dummy_req_d1,
sctag_dram_rd_req_d1}),
.din({sctag_dram_addr[39:5],
sctag_dram_rd_req_id[2:0],
sctag_dram_wr_req,
sctag_dram_rd_dummy_req,
sctag_dram_rd_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(12) ff_flop_bank0_col1_row3 (.q({dram_sctag_rd_ack_d1,
dram_sctag_wr_ack_d1,
dram_sctag_chunk_id_r0_d1[1:0],
dram_sctag_data_vld_r0_d1,
dram_sctag_rd_req_id_r0_d1[2:0],
dram_sctag_secc_err_r2_d1,
dram_sctag_mecc_err_r2_d1,
dram_sctag_scb_mecc_err_d1,
dram_sctag_scb_secc_err_d1}),
.din({dram_sctag_rd_ack,
dram_sctag_wr_ack,
dram_sctag_chunk_id_r0[1:0],
dram_sctag_data_vld_r0,
dram_sctag_rd_req_id_r0[2:0],
dram_sctag_secc_err_r2,
dram_sctag_mecc_err_r2,
dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
`define SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_pwrgood_pp_p.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VPWR = 1'b0;
#60 UDP_IN = 1'b1;
#80 VPWR = 1'b1;
#100 UDP_IN = 1'b0;
#120 VPWR = 1'b0;
#140 VPWR = 1'b1;
#160 UDP_IN = 1'b1;
#180 VPWR = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_ls__udp_pwrgood_pp$P dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_PWRGOOD_PP_P_TB_V
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_log_module (
// inputs:
clk,
data,
strobe,
valid
)
;
input clk;
input [ 7: 0] data;
input strobe;
input valid;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [31:0] text_handle; // for $fopen
initial text_handle = $fopen ("jtag_uart_0_output_stream.dat");
always @(posedge clk) begin
if (valid && strobe) begin
$fwrite (text_handle, "%b\n", data);
// echo raw binary strings to file as ascii to screen
$write("%s", ((data == 8'hd) ? 8'ha : data));
// non-standard; poorly documented; required to get real data stream.
$fflush (text_handle);
end
end // clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//jtag_uart_0_log, which is an e_log
jtag_uart_0_log_module jtag_uart_0_log
(
.clk (clk),
.data (fifo_wdata),
.strobe (fifo_wr),
.valid (fifo_wr)
);
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
jtag_uart_0_sim_scfifo_w the_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_drom_module (
// inputs:
clk,
incr_addr,
reset_n,
// outputs:
new_rom,
num_bytes,
q,
safe
)
;
parameter POLL_RATE = 100;
output new_rom;
output [ 31: 0] num_bytes;
output [ 7: 0] q;
output safe;
input clk;
input incr_addr;
input reset_n;
reg [ 11: 0] address;
reg d1_pre;
reg d2_pre;
reg d3_pre;
reg d4_pre;
reg d5_pre;
reg d6_pre;
reg d7_pre;
reg d8_pre;
reg d9_pre;
reg [ 7: 0] mem_array [2047: 0];
reg [ 31: 0] mutex [ 1: 0];
reg new_rom;
wire [ 31: 0] num_bytes;
reg pre;
wire [ 7: 0] q;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign q = mem_array[address];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_pre <= 0;
d2_pre <= 0;
d3_pre <= 0;
d4_pre <= 0;
d5_pre <= 0;
d6_pre <= 0;
d7_pre <= 0;
d8_pre <= 0;
d9_pre <= 0;
new_rom <= 0;
end
else
begin
d1_pre <= pre;
d2_pre <= d1_pre;
d3_pre <= d2_pre;
d4_pre <= d3_pre;
d5_pre <= d4_pre;
d6_pre <= d5_pre;
d7_pre <= d6_pre;
d8_pre <= d7_pre;
d9_pre <= d8_pre;
new_rom <= d9_pre;
end
end
assign num_bytes = mutex[1];
reg safe_delay;
reg [31:0] poll_count;
reg [31:0] mutex_handle;
wire interactive = 1'b0 ; // '
assign safe = (address < mutex[1]);
initial poll_count = POLL_RATE;
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin
safe_delay <= 0;
end else begin
safe_delay <= safe;
end
end // safe_delay
always @(posedge clk or negedge reset_n) begin
if (reset_n !== 1) begin // dont worry about null _stream.dat file
address <= 0;
mem_array[0] <= 0;
mutex[0] <= 0;
mutex[1] <= 0;
pre <= 0;
end else begin // deal with the non-reset case
pre <= 0;
if (incr_addr && safe) address <= address + 1;
if (mutex[0] && !safe && safe_delay) begin
// and blast the mutex after falling edge of safe if interactive
if (interactive) begin
mutex_handle = $fopen ("jtag_uart_0_input_mutex.dat");
$fdisplay (mutex_handle, "0");
$fclose (mutex_handle);
// $display ($stime, "\t%m:\n\t\tMutex cleared!");
end else begin
// sleep until next reset, do not bash mutex.
wait (!reset_n);
end
end // OK to bash mutex.
if (poll_count < POLL_RATE) begin // wait
poll_count = poll_count + 1;
end else begin // do the interesting stuff.
poll_count = 0;
if (mutex_handle) begin
$readmemh ("jtag_uart_0_input_mutex.dat", mutex);
end
if (mutex[0] && !safe) begin
// read stream into mem_array after current characters are gone!
// save mutex[0] value to compare to address (generates 'safe')
mutex[1] <= mutex[0];
// $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]);
$readmemb("jtag_uart_0_input_stream.dat", mem_array);
// bash address and send pulse outside to send the char:
address <= 0;
pre <= -1;
end // else mutex miss...
end // poll_count
end // reset
end // posedge clk
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
wire safe;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//jtag_uart_0_drom, which is an e_drom
jtag_uart_0_drom_module jtag_uart_0_drom
(
.clk (clk),
.incr_addr (fifo_rd_d),
.new_rom (new_rom),
.num_bytes (num_bytes),
.q (fifo_rdata),
.reset_n (rst_n),
.safe (safe)
);
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
jtag_uart_0_sim_scfifo_r the_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
jtag_uart_0_scfifo_w the_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
jtag_uart_0_scfifo_r the_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
// file: SysMon.v
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`timescale 1ns / 1 ps
(* X_CORE_INFO = "sysmon_wiz_v2_1, Coregen 12.4" *)
module SysMon
(
DADDR_IN, // Address bus for the dynamic reconfiguration port
DCLK_IN, // Clock input for the dynamic reconfiguration port
DEN_IN, // Enable Signal for the dynamic reconfiguration port
DI_IN, // Input data bus for the dynamic reconfiguration port
DWE_IN, // Write Enable for the dynamic reconfiguration port
BUSY_OUT, // ADC Busy signal
CHANNEL_OUT, // Channel Selection Outputs
DO_OUT, // Output data bus for dynamic reconfiguration port
DRDY_OUT, // Data ready signal for the dynamic reconfiguration port
EOC_OUT, // End of Conversion Signal
EOS_OUT, // End of Sequence Signal
JTAGBUSY_OUT, // JTAG DRP transaction is in progress signal
JTAGLOCKED_OUT, // DRP port lock request has been made by JTAG
JTAGMODIFIED_OUT, // Indicates JTAG Write to the DRP has occurred
VP_IN, // Dedicated Analog Input Pair
VN_IN);
input [6:0] DADDR_IN;
input DCLK_IN;
input DEN_IN;
input [15:0] DI_IN;
input DWE_IN;
input VP_IN;
input VN_IN;
output BUSY_OUT;
output [4:0] CHANNEL_OUT;
output [15:0] DO_OUT;
output DRDY_OUT;
output EOC_OUT;
output EOS_OUT;
output JTAGBUSY_OUT;
output JTAGLOCKED_OUT;
output JTAGMODIFIED_OUT;
wire FLOAT_VCCAUX;
wire FLOAT_VCCINT;
wire FLOAT_TEMP;
wire GND_BIT;
wire [2:0] GND_BUS3;
assign GND_BIT = 0;
wire [15:0] aux_channel_p;
wire [15:0] aux_channel_n;
assign aux_channel_p[0] = 1'b0;
assign aux_channel_n[0] = 1'b0;
assign aux_channel_p[1] = 1'b0;
assign aux_channel_n[1] = 1'b0;
assign aux_channel_p[2] = 1'b0;
assign aux_channel_n[2] = 1'b0;
assign aux_channel_p[3] = 1'b0;
assign aux_channel_n[3] = 1'b0;
assign aux_channel_p[4] = 1'b0;
assign aux_channel_n[4] = 1'b0;
assign aux_channel_p[5] = 1'b0;
assign aux_channel_n[5] = 1'b0;
assign aux_channel_p[6] = 1'b0;
assign aux_channel_n[6] = 1'b0;
assign aux_channel_p[7] = 1'b0;
assign aux_channel_n[7] = 1'b0;
assign aux_channel_p[8] = 1'b0;
assign aux_channel_n[8] = 1'b0;
assign aux_channel_p[9] = 1'b0;
assign aux_channel_n[9] = 1'b0;
assign aux_channel_p[10] = 1'b0;
assign aux_channel_n[10] = 1'b0;
assign aux_channel_p[11] = 1'b0;
assign aux_channel_n[11] = 1'b0;
assign aux_channel_p[12] = 1'b0;
assign aux_channel_n[12] = 1'b0;
assign aux_channel_p[13] = 1'b0;
assign aux_channel_n[13] = 1'b0;
assign aux_channel_p[14] = 1'b0;
assign aux_channel_n[14] = 1'b0;
assign aux_channel_p[15] = 1'b0;
assign aux_channel_n[15] = 1'b0;
SYSMON #(
.INIT_40(16'h3000), // config reg 0
.INIT_41(16'h30ff), // config reg 1
.INIT_42(16'h0800), // config reg 2
.INIT_48(16'h0100), // Sequencer channel selection
.INIT_49(16'h0000), // Sequencer channel selection
.INIT_4A(16'h0000), // Sequencer Average selection
.INIT_4B(16'h0000), // Sequencer Average selection
.INIT_4C(16'h0000), // Sequencer Bipolar selection
.INIT_4D(16'h0000), // Sequencer Bipolar selection
.INIT_4E(16'h0000), // Sequencer Acq time selection
.INIT_4F(16'h0000), // Sequencer Acq time selection
.INIT_50(16'hb5ed), // Temp alarm trigger
.INIT_51(16'h5999), // Vccint upper alarm limit
.INIT_52(16'he000), // Vccaux upper alarm limit
.INIT_54(16'ha93a), // Temp alarm reset
.INIT_55(16'h5111), // Vccint lower alarm limit
.INIT_56(16'hcaaa), // Vccaux lower alarm limit
.INIT_57(16'hae4e), // Temp alarm OT reset
.SIM_MONITOR_FILE("design.txt")
)
SYSMON_INST (
.CONVST(GND_BIT),
.CONVSTCLK(GND_BIT),
.DADDR(DADDR_IN[6:0]),
.DCLK(DCLK_IN),
.DEN(DEN_IN),
.DI(DI_IN[15:0]),
.DWE(DWE_IN),
.RESET(GND_BIT),
.VAUXN(aux_channel_n[15:0]),
.VAUXP(aux_channel_p[15:0]),
.ALM({FLOAT_VCCAUX, FLOAT_VCCINT, FLOAT_TEMP}),
.BUSY(BUSY_OUT),
.CHANNEL(CHANNEL_OUT[4:0]),
.DO(DO_OUT[15:0]),
.DRDY(DRDY_OUT),
.EOC(EOC_OUT),
.EOS(EOS_OUT),
.JTAGBUSY(JTAGBUSY_OUT),
.JTAGLOCKED(JTAGLOCKED_OUT),
.JTAGMODIFIED(JTAGMODIFIED_OUT),
.OT(),
.VP(VP_IN),
.VN(VN_IN)
);
endmodule
|
module mux_4to1_19bit(S, i1, i2, i3, i4, Q);
input[18:0] i1, i2, i3, i4;
input[1:0] S;
output[18:0] Q;
Mux_4_to_1 mux0(S, i1[0], i2[0], i3[0], i4[0], Q[0]);
Mux_4_to_1 mux1(S, i1[1], i2[1], i3[1], i4[1], Q[1]);
Mux_4_to_1 mux2(S, i1[2], i2[2], i3[2], i4[2], Q[2]);
Mux_4_to_1 mux3(S, i1[3], i2[3], i3[3], i4[3], Q[3]);
Mux_4_to_1 mux4(S, i1[4], i2[4], i3[4], i4[4], Q[4]);
Mux_4_to_1 mux5(S, i1[5], i2[5], i3[5], i4[5], Q[5]);
Mux_4_to_1 mux6(S, i1[6], i2[6], i3[6], i4[6], Q[6]);
Mux_4_to_1 mux7(S, i1[7], i2[7], i3[7], i4[7], Q[7]);
Mux_4_to_1 mux8(S, i1[8], i2[8], i3[8], i4[8], Q[8]);
Mux_4_to_1 mux9(S, i1[9], i2[9], i3[9], i4[9], Q[9]);
Mux_4_to_1 mux10(S, i1[10], i2[10], i3[10], i4[10], Q[10]);
Mux_4_to_1 mux11(S, i1[11], i2[11], i3[11], i4[11], Q[11]);
Mux_4_to_1 mux12(S, i1[12], i2[12], i3[12], i4[12], Q[12]);
Mux_4_to_1 mux13(S, i1[13], i2[13], i3[13], i4[13], Q[13]);
Mux_4_to_1 mux14(S, i1[14], i2[14], i3[14], i4[14], Q[14]);
Mux_4_to_1 mux15(S, i1[15], i2[15], i3[15], i4[15], Q[15]);
Mux_4_to_1 mux16(S, i1[16], i2[16], i3[16], i4[16], Q[16]);
Mux_4_to_1 mux17(S, i1[17], i2[17], i3[17], i4[17], Q[17]);
Mux_4_to_1 mux18(S, i1[18], i2[18], i3[18], i4[18], Q[18]);
endmodule
|
// Jagadeesh Vasudevamurthy nes_zybo_wrapper_X99.v
// Please do not remove the header
// Char array passed is as follows
//--------------------------------------
//0:000000 01101101
//1:000001 00100010
//2:000010 00000010
//3:000011 01000010
//4:000100 10000001
//5:000101 10100000
//6:000110 10100000
//7:000111 01100000
//8:001000 01000100
//9:001001 00001000
//10:001010 00001000
//11:001011 00000100
//12:001100 00000101
//13:001101 00000000
//14:001110 00000000
//15:001111 00000000
//16:010000 10110110
//17:010001 00001111
//18:010010 00100111
//19:010011 10000011
//20:010100 10100010
//21:010101 11100001
//22:010110 11000100
//23:010111 11001000
//24:011000 10001100
//25:011001 00010000
//26:011010 00010100
//27:011011 00010000
//28:011100 00010010
//29:011101 00000000
//30:011110 00000000
//31:011111 00000000
//32:100000 11111111
//33:100001 00110111
//34:100010 01010011
//35:100011 10110011
//36:100100 11101111
//37:100101 11101110
//38:100110 11101101
//39:100111 11110000
//40:101000 11110100
//41:101001 10011000
//42:101010 01011001
//43:101011 01011110
//44:101100 00011111
//45:101101 00000000
//46:101110 00000000
//47:101111 00000000
//48:110000 11111111
//49:110001 10111111
//50:110010 11011011
//51:110011 11011011
//52:110100 11111011
//53:110101 11111011
//54:110110 11110110
//55:110111 11111010
//56:111000 11111110
//57:111001 11111110
//58:111010 10111110
//59:111011 10111111
//60:111100 10011111
//61:111101 00000000
//62:111110 00000000
//63:111111 00000000
// default NOT given
// Parallel mux
//--------------------------------------
// PLA starts now
module nes_zybo_wrapper_X99(a,o);
input[5:0] a;
output reg[7:0] o;
always @(a)
begin
case(a)
6'b000000: o = 8'b01101101;
6'b000001: o = 8'b00100010;
6'b000010: o = 8'b00000010;
6'b000011: o = 8'b01000010;
6'b000100: o = 8'b10000001;
6'b000101: o = 8'b10100000;
6'b000110: o = 8'b10100000;
6'b000111: o = 8'b01100000;
6'b001000: o = 8'b01000100;
6'b001001: o = 8'b00001000;
6'b001010: o = 8'b00001000;
6'b001011: o = 8'b00000100;
6'b001100: o = 8'b00000101;
6'b001101: o = 8'b00000000;
6'b001110: o = 8'b00000000;
6'b001111: o = 8'b00000000;
6'b010000: o = 8'b10110110;
6'b010001: o = 8'b00001111;
6'b010010: o = 8'b00100111;
6'b010011: o = 8'b10000011;
6'b010100: o = 8'b10100010;
6'b010101: o = 8'b11100001;
6'b010110: o = 8'b11000100;
6'b010111: o = 8'b11001000;
6'b011000: o = 8'b10001100;
6'b011001: o = 8'b00010000;
6'b011010: o = 8'b00010100;
6'b011011: o = 8'b00010000;
6'b011100: o = 8'b00010010;
6'b011101: o = 8'b00000000;
6'b011110: o = 8'b00000000;
6'b011111: o = 8'b00000000;
6'b100000: o = 8'b11111111;
6'b100001: o = 8'b00110111;
6'b100010: o = 8'b01010011;
6'b100011: o = 8'b10110011;
6'b100100: o = 8'b11101111;
6'b100101: o = 8'b11101110;
6'b100110: o = 8'b11101101;
6'b100111: o = 8'b11110000;
6'b101000: o = 8'b11110100;
6'b101001: o = 8'b10011000;
6'b101010: o = 8'b01011001;
6'b101011: o = 8'b01011110;
6'b101100: o = 8'b00011111;
6'b101101: o = 8'b00000000;
6'b101110: o = 8'b00000000;
6'b101111: o = 8'b00000000;
6'b110000: o = 8'b11111111;
6'b110001: o = 8'b10111111;
6'b110010: o = 8'b11011011;
6'b110011: o = 8'b11011011;
6'b110100: o = 8'b11111011;
6'b110101: o = 8'b11111011;
6'b110110: o = 8'b11110110;
6'b110111: o = 8'b11111010;
6'b111000: o = 8'b11111110;
6'b111001: o = 8'b11111110;
6'b111010: o = 8'b10111110;
6'b111011: o = 8'b10111111;
6'b111100: o = 8'b10011111;
6'b111101: o = 8'b00000000;
6'b111110: o = 8'b00000000;
6'b111111: o = 8'b00000000;
// defaults of ALL_0 and ALL_X are never routine to input pla. ALL_X,ALL_1 are expanded by me. Output never has default
// Parallel mux
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:01:49 01/04/2015
// Design Name:
// Module Name: neopixel_tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module neopixel_tx(
input wire clk,
input wire sys_rst,
//input wire mode,
//input wire tx_enable,
//input wire [24:0] dIn,
//input wire wr_en,
//output wire rgb_full_flg,
//output wire cmd_full_flg,
//output wire empty_flg,
output wire [4:0] ctrlLed,
output wire neo_tx_out
);
// connectors between FIFOs and TX_FSM
wire neoClk;
wire neo_msgTyp;
wire [23:0] neo_rgb;
wire neo_rdEn;
wire cmd_empty_flg;
wire rgb_empty_flg;
// connectors between microblaze and parts
wire empty_flg;
wire rst;
wire tx_enable;
wire mode;
wire mb_rst;
wire gpi_int;
wire wr_en;
wire cmd_dIn;
wire [23:0]rgb_dIn;
// microblaze for loading fifos
mojo_mb mojo_mb (
.Clk(clk),
.Reset(~sys_rst), // goes nowhere
.GPI1_Interrupt(gpi_int),
.GPI1({cmd_full_flg, rgb_full_flg}),
.GPO1({rst, wr_en, cmd_dIn, mode, tx_enable}),
.GPO2(rgb_dIn)
);
// 20MHz source
clk_wiz_v3_6 clk20MHz (
// Clock in ports
.clk(clk),
// Clock out ports
.clk_20MHz(neoClk)
);
// data FIFO (1024*3 bytes)
FIFO_WxD #(
24,
10)
neo_rgbFIFO (
.rst(rst),
.dataIn(rgb_dIn),
.wr_en(wr_en),
.rd_en(neo_rdEn),
.dataOut(neo_rgb),
.full_flg(rgb_full_flg),
.empty_flg(rgb_empty_flg)
);
// command bit FIFO (31 bits)
FIFO_WxD #(
1,
10)
neo_cmdFIFO (
.rst(rst),
.dataIn(cmd_dIn),
.wr_en(wr_en),
.rd_en(neo_rdEn),
.dataOut(neo_msgTyp),
.full_flg(cmd_full_flg),
.empty_flg(cmd_empty_flg)
);
// Neopixel Transmitter
neopixel_tx_fsm neo_tx(
.clk(neoClk),
.rst(rst),
.mode(mode),
.tx_enable(tx_enable),
.empty_flg(empty_flg),
.neo_dIn(neo_rgb),
.rgb_msgTyp(neo_msgTyp),
.rd_next(neo_rdEn),
.neo_tx_out(neo_tx_out)
);
// combine the two empty flags
assign empty_flg = cmd_empty_flg | rgb_empty_flg;
assign ctrlLed[0] = tx_enable;
assign ctrlLed[1] = mode;
assign ctrlLed[2] = cmd_dIn;
assign ctrlLed[3] = wr_en;
assign ctrlLed[4] = rst;
endmodule
|
//======================================================================
//
// tb_aes_encipher_block.v
// -----------------------
// Testbench for the AES encipher block module.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module tb_aes_encipher_block();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter AES_128_BIT_KEY = 0;
parameter AES_256_BIT_KEY = 1;
parameter AES_DECIPHER = 1'b0;
parameter AES_ENCIPHER = 1'b1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_next;
reg tb_keylen;
wire tb_ready;
wire [3 : 0] tb_round;
wire [127 : 0] tb_round_key;
wire [31 : 0] tb_sboxw;
wire [31 : 0] tb_new_sboxw;
reg [127 : 0] tb_block;
wire [127 : 0] tb_new_block;
reg [127 : 0] key_mem [0 : 14];
//----------------------------------------------------------------
// Assignments.
//----------------------------------------------------------------
assign tb_round_key = key_mem[tb_round];
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
// We need an sbox for the tests.
aes_sbox sbox(
.sboxw(tb_sboxw),
.new_sboxw(tb_new_sboxw)
);
// The device under test.
aes_encipher_block dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.next(tb_next),
.keylen(tb_keylen),
.round(tb_round),
.round_key(tb_round_key),
.sboxw(tb_sboxw),
.new_sboxw(tb_new_sboxw),
.block(tb_block),
.new_block(tb_new_block),
.ready(tb_ready)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Interfaces");
$display("ready = 0x%01x, next = 0x%01x, keylen = 0x%01x",
dut.ready, dut.next, dut.keylen);
$display("block = 0x%032x", dut.block);
$display("new_block = 0x%032x", dut.new_block);
$display("");
$display("Control states");
$display("round = 0x%01x", dut.round);
$display("enc_ctrl = 0x%01x, update_type = 0x%01x, sword_ctr = 0x%01x, round_ctr = 0x%01x",
dut.enc_ctrl_reg, dut.update_type, dut.sword_ctr_reg, dut.round_ctr_reg);
$display("");
$display("Internal data values");
$display("round_key = 0x%016x", dut.round_key);
$display("sboxw = 0x%08x, new_sboxw = 0x%08x", dut.sboxw, dut.new_sboxw);
$display("block_w0_reg = 0x%08x, block_w1_reg = 0x%08x, block_w2_reg = 0x%08x, block_w3_reg = 0x%08x",
dut.block_w0_reg, dut.block_w1_reg, dut.block_w2_reg, dut.block_w3_reg);
$display("");
$display("old_block = 0x%08x", dut.round_logic.old_block);
$display("shiftrows_block = 0x%08x", dut.round_logic.shiftrows_block);
$display("mixcolumns_block = 0x%08x", dut.round_logic.mixcolumns_block);
$display("addkey_init_block = 0x%08x", dut.round_logic.addkey_init_block);
$display("addkey_main_block = 0x%08x", dut.round_logic.addkey_main_block);
$display("addkey_final_block = 0x%08x", dut.round_logic.addkey_final_block);
$display("block_w0_new = 0x%08x, block_w1_new = 0x%08x, block_w2_new = 0x%08x, block_w3_new = 0x%08x",
dut.block_new[127 : 096], dut.block_new[095 : 064],
dut.block_new[063 : 032], dut.block_new[031 : 000]);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("--- Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_next = 0;
tb_keylen = 0;
tb_block = {4{32'h00000000}};
end
endtask // init_sim
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("--- All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("--- %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_ready)
begin
#(CLK_PERIOD);
if (DUMP_WAIT)
begin
dump_dut_state();
end
end
end
endtask // wait_ready
//----------------------------------------------------------------
// test_ecb_enc()
//
// Perform ECB mode encryption test.
//----------------------------------------------------------------
task test_ecb_enc(
input key_length,
input [127 : 0] block,
input [127 : 0] expected);
begin
tc_ctr = tc_ctr + 1;
$display("--- TC %02d ECB mode test started.", tc_ctr);
// Init the cipher with the given key and length.
tb_keylen = key_length;
// Perform encipher operation on the block.
tb_block = block;
tb_next = 1;
#(2 * CLK_PERIOD);
tb_next = 0;
#(2 * CLK_PERIOD);
wait_ready();
if (tb_new_block == expected)
begin
$display("--- TC %02d successful.", tc_ctr);
$display("--- Got: 0x%032x", tb_new_block);
end
else
begin
$display("--- ERROR: TC %02d NOT successful.", tc_ctr);
$display("--- Expected: 0x%032x", expected);
$display("--- Got: 0x%032x", tb_new_block);
error_ctr = error_ctr + 1;
end
$display("--- TC %02d ECB mode test completed.", tc_ctr);
end
endtask // ecb_mode_single_block_test
//----------------------------------------------------------------
// load_nist128_key
//----------------------------------------------------------------
task load_nist128_key;
begin : load_nist128_key
key_mem[00] = 128'h2b7e151628aed2a6abf7158809cf4f3c;
key_mem[01] = 128'ha0fafe1788542cb123a339392a6c7605;
key_mem[02] = 128'hf2c295f27a96b9435935807a7359f67f;
key_mem[03] = 128'h3d80477d4716fe3e1e237e446d7a883b;
key_mem[04] = 128'hef44a541a8525b7fb671253bdb0bad00;
key_mem[05] = 128'hd4d1c6f87c839d87caf2b8bc11f915bc;
key_mem[06] = 128'h6d88a37a110b3efddbf98641ca0093fd;
key_mem[07] = 128'h4e54f70e5f5fc9f384a64fb24ea6dc4f;
key_mem[08] = 128'head27321b58dbad2312bf5607f8d292f;
key_mem[09] = 128'hac7766f319fadc2128d12941575c006e;
key_mem[10] = 128'hd014f9a8c9ee2589e13f0cc8b6630ca6;
key_mem[11] = 128'h00000000000000000000000000000000;
key_mem[12] = 128'h00000000000000000000000000000000;
key_mem[13] = 128'h00000000000000000000000000000000;
key_mem[14] = 128'h00000000000000000000000000000000;
end
endtask // load_nist128_key
//----------------------------------------------------------------
// load_nist256_key
//----------------------------------------------------------------
task load_nist256_key;
begin : load_nist256_key
key_mem[00] = 128'h603deb1015ca71be2b73aef0857d7781;
key_mem[01] = 128'h1f352c073b6108d72d9810a30914dff4;
key_mem[02] = 128'h9ba354118e6925afa51a8b5f2067fcde;
key_mem[03] = 128'ha8b09c1a93d194cdbe49846eb75d5b9a;
key_mem[04] = 128'hd59aecb85bf3c917fee94248de8ebe96;
key_mem[05] = 128'hb5a9328a2678a647983122292f6c79b3;
key_mem[06] = 128'h812c81addadf48ba24360af2fab8b464;
key_mem[07] = 128'h98c5bfc9bebd198e268c3ba709e04214;
key_mem[08] = 128'h68007bacb2df331696e939e46c518d80;
key_mem[09] = 128'hc814e20476a9fb8a5025c02d59c58239;
key_mem[10] = 128'hde1369676ccc5a71fa2563959674ee15;
key_mem[11] = 128'h5886ca5d2e2f31d77e0af1fa27cf73c3;
key_mem[12] = 128'h749c47ab18501ddae2757e4f7401905a;
key_mem[13] = 128'hcafaaae3e4d59b349adf6acebd10190d;
key_mem[14] = 128'hfe4890d1e6188d0b046df344706c631e;
end
endtask // load_nist256_key
//----------------------------------------------------------------
// test_nist_enc_128_1
//----------------------------------------------------------------
task test_nist_enc_128_1;
begin : nist_enc_128_1
reg [127 : 0] plaintext;
reg [127 : 0] ciphertext;
plaintext = 128'h6bc1bee22e409f96e93d7e117393172a;
ciphertext = 128'h3ad77bb40d7a3660a89ecaf32466ef97;
$display("--- test_nist_enc_128_1: Started.");
test_ecb_enc(AES_128_BIT_KEY, plaintext, ciphertext);
$display("--- test_nist_enc_128_1: Completed.");
$display("");
end
endtask // test_nist_enc_128_1
//----------------------------------------------------------------
// test_nist_enc_128_2
//----------------------------------------------------------------
task test_nist_enc_128_2;
begin : nist_enc_128_2
reg [127 : 0] plaintext;
reg [127 : 0] ciphertext;
plaintext = 128'hae2d8a571e03ac9c9eb76fac45af8e51;
ciphertext = 128'hf5d3d58503b9699de785895a96fdbaaf;
$display("--- test_nist_enc_128_2: Started.");
test_ecb_enc(AES_128_BIT_KEY, plaintext, ciphertext);
$display("--- test_nist_enc_128_2: Completed.");
$display("");
end
endtask // test_nist_enc_128_2
//----------------------------------------------------------------
// test_nist_enc_128_3
//----------------------------------------------------------------
task test_nist_enc_128_3;
begin : nist_enc_128_3
reg [127 : 0] plaintext;
reg [127 : 0] ciphertext;
plaintext = 128'h30c81c46a35ce411e5fbc1191a0a52ef;
ciphertext = 128'h43b1cd7f598ece23881b00e3ed030688;
$display("--- test_nist_enc_128_3: Started.");
test_ecb_enc(AES_128_BIT_KEY, plaintext, ciphertext);
$display("--- test_nist_enc_128_3: Completed.");
$display("");
end
endtask // test_nist_enc_128_3
//----------------------------------------------------------------
// test_nist_enc_128_4
//----------------------------------------------------------------
task test_nist_enc_128_4;
begin : nist_enc_128_4
reg [127 : 0] plaintext;
reg [127 : 0] ciphertext;
plaintext = 128'hf69f2445df4f9b17ad2b417be66c3710;
ciphertext = 128'h7b0c785e27e8ad3f8223207104725dd4;
$display("--- test_nist_enc_128_4: Started.");
test_ecb_enc(AES_128_BIT_KEY, plaintext, ciphertext);
$display("--- test_nist_enc_128_4: Completed.");
$display("");
end
endtask // test_nist_enc_128_4
//----------------------------------------------------------------
// test_nist_enc_256_1
//----------------------------------------------------------------
task test_nist_enc_256_1;
begin : nist_enc_256_1
reg [127 : 0] plaintext;
reg [127 : 0] ciphertext;
plaintext = 128'h6bc1bee22e409f96e93d7e117393172a;
ciphertext = 128'hf3eed1bdb5d2a03c064b5a7e3db181f8;
$display("--- test_nist_enc_256_1: Started.");
test_ecb_enc(AES_256_BIT_KEY, plaintext, ciphertext);
$display("--- test_nist_enc_256_1: Completed.");
$display("");
end
endtask // test_nist_enc_256_1
//----------------------------------------------------------------
// tb_aes_encipher_block
// The main test functionality.
//
// Test cases taken from NIST SP 800-38A:
// http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf
//----------------------------------------------------------------
initial
begin : tb_aes_encipher_block
reg [127 : 0] nist_plaintext0;
reg [127 : 0] nist_plaintext1;
reg [127 : 0] nist_plaintext2;
reg [127 : 0] nist_plaintext3;
reg [127 : 0] nist_ecb_256_enc_expected0;
reg [127 : 0] nist_ecb_256_enc_expected1;
reg [127 : 0] nist_ecb_256_enc_expected2;
reg [127 : 0] nist_ecb_256_enc_expected3;
nist_plaintext0 = 128'h6bc1bee22e409f96e93d7e117393172a;
nist_plaintext1 = 128'hae2d8a571e03ac9c9eb76fac45af8e51;
nist_plaintext2 = 128'h30c81c46a35ce411e5fbc1191a0a52ef;
nist_plaintext3 = 128'hf69f2445df4f9b17ad2b417be66c3710;
nist_ecb_256_enc_expected0 = 255'hf3eed1bdb5d2a03c064b5a7e3db181f8;
nist_ecb_256_enc_expected1 = 255'h591ccb10d410ed26dc5ba74a31362870;
nist_ecb_256_enc_expected2 = 255'hb6ed21b99ca6f4f9f153e7b1beafed1d;
nist_ecb_256_enc_expected3 = 255'h23304b7a39f9f3ff067d8d8f9e24ecc7;
$display(" -= Testbench for aes encipher block started =-");
$display(" ============================================");
$display("");
init_sim();
reset_dut();
load_nist128_key();
test_nist_enc_128_1();
test_nist_enc_128_2();
test_nist_enc_128_3();
test_nist_enc_128_4();
load_nist256_key();
test_nist_enc_256_1();
// test_ecb_enc(AES_256_BIT_KEY, nist_plaintext1, nist_ecb_256_enc_expected1);
// test_ecb_enc(AES_256_BIT_KEY, nist_plaintext2, nist_ecb_256_enc_expected2);
// test_ecb_enc(AES_256_BIT_KEY, nist_plaintext3, nist_ecb_256_enc_expected3);
display_test_result();
$display("");
$display(" -= Testbench for aes encipher block completed =-");
$display(" ============================================");
$finish;
end // tb_aes_encipher_block
endmodule // tb_aes_encipher_block
//======================================================================
// EOF tb_aes_encipher_block.v
//======================================================================
|
Require Import Int63 FloatClass.
(** * Definition of the interface for primitive floating-point arithmetic
This interface provides processor operators for the Binary64 format of the
IEEE 754-2008 standard. *)
(** ** Type definition for the co-domain of [compare] *)
Variant float_comparison : Set := FEq | FLt | FGt | FNotComparable.
Register float_comparison as kernel.ind_f_cmp.
Register float_class as kernel.ind_f_class.
(** ** The main type *)
(** [float]: primitive type for Binary64 floating-point numbers. *)
Primitive float := #float64_type.
(** ** Syntax support *)
Declare Scope float_scope.
Delimit Scope float_scope with float.
Bind Scope float_scope with float.
Declare ML Module "float_syntax_plugin".
(** ** Floating-point operators *)
Primitive classify := #float64_classify.
Primitive abs := #float64_abs.
Primitive sqrt := #float64_sqrt.
Primitive opp := #float64_opp.
Notation "- x" := (opp x) : float_scope.
Primitive eqb := #float64_eq.
Notation "x == y" := (eqb x y) (at level 70, no associativity) : float_scope.
Primitive ltb := #float64_lt.
Notation "x < y" := (ltb x y) (at level 70, no associativity) : float_scope.
Primitive leb := #float64_le.
Notation "x <= y" := (leb x y) (at level 70, no associativity) : float_scope.
Primitive compare := #float64_compare.
Notation "x ?= y" := (compare x y) (at level 70, no associativity) : float_scope.
Primitive mul := #float64_mul.
Notation "x * y" := (mul x y) : float_scope.
Primitive add := #float64_add.
Notation "x + y" := (add x y) : float_scope.
Primitive sub := #float64_sub.
Notation "x - y" := (sub x y) : float_scope.
Primitive div := #float64_div.
Notation "x / y" := (div x y) : float_scope.
(** ** Conversions *)
(** [of_int63]: convert a primitive integer into a float value.
The value is rounded if need be. *)
Primitive of_int63 := #float64_of_int63.
(** Specification of [normfr_mantissa]:
- If the input is a float value with an absolute value inside $[0.5, 1.)$#[0.5, 1.)#;
- Then return its mantissa as a primitive integer.
The mantissa will be a 53-bit integer with its most significant bit set to 1;
- Else return zero.
The sign bit is always ignored. *)
Primitive normfr_mantissa := #float64_normfr_mantissa.
(** ** Exponent manipulation functions *)
(** [frshiftexp]: convert a float to fractional part in $[0.5, 1.)$#[0.5, 1.)#
and integer part. *)
Primitive frshiftexp := #float64_frshiftexp.
(** [ldshiftexp]: multiply a float by an integral power of 2. *)
Primitive ldshiftexp := #float64_ldshiftexp.
(** ** Predecesor/Successor functions *)
(** [next_up]: return the next float towards positive infinity. *)
Primitive next_up := #float64_next_up.
(** [next_down]: return the next float towards negative infinity. *)
Primitive next_down := #float64_next_down.
(** ** Special values (needed for pretty-printing) *)
Definition infinity := Eval compute in div (of_int63 1) (of_int63 0).
Definition neg_infinity := Eval compute in opp infinity.
Definition nan := Eval compute in div (of_int63 0) (of_int63 0).
Register infinity as num.float.infinity.
Register neg_infinity as num.float.neg_infinity.
Register nan as num.float.nan.
(** ** Other special values *)
Definition one := Eval compute in (of_int63 1).
Definition zero := Eval compute in (of_int63 0).
Definition neg_zero := Eval compute in (-zero)%float.
Definition two := Eval compute in (of_int63 2).
(** ** Predicates and helper functions *)
Definition is_nan f := negb (f == f)%float.
Definition is_zero f := (f == zero)%float. (* note: 0 == -0 with floats *)
Definition is_infinity f := (abs f == infinity)%float.
Definition is_finite (x : float) := negb (is_nan x || is_infinity x).
(** [get_sign]: return [true] for [-] sign, [false] for [+] sign. *)
Definition get_sign f :=
let f := if is_zero f then (one / f)%float else f in
(f < zero)%float.
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:37:16 03/22/2015
// Design Name: mux1bit2x1
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW1/mux1bit2x1_test.v
// Project Name: HW1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mux1bit2x1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mux1bit2x1_test;
// Inputs
reg In0;
reg In1;
reg Sel;
// Outputs
wire Y;
// Variables
integer i;
// Instantiate the Unit Under Test (UUT)
mux1bit2x1 uut (
.Y(Y),
.In0(In0),
.In1(In1),
.Sel(Sel)
);
initial begin
// Initialize Inputs
In0 = 0;
In1 = 0;
Sel = 0;
// Loop Through All Possible Values
for(i=0; i<8; i = i + 1)
begin
#10 {Sel, In0, In1} = {Sel, In0, In1} + 1;
end
end
endmodule
|
// spw_babasu_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 593
`timescale 1 ps / 1 ps
module spw_babasu_hps_0_hps_io (
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [7:0] mem_dq, // .mem_dq
inout wire mem_dqs, // .mem_dqs
inout wire mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
spw_babasu_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: Lisa Liu
//
// Create Date: 06/30/2014 03:42:37 PM
// Design Name:
// Module Name: rx_isolation
// Project Name:
// Target Devices:
// Tool Versions:
// Description: read back presure signal (tready) from 8K byte FIFO and drop packets from xgmac whenever the empty space in the FIFO is less than 5K.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rx_isolation #(
FIFO_FULL_THRESHOLD = 11'd256
)
(
input [63:0] axi_str_tdata_from_xgmac,
input [7:0] axi_str_tkeep_from_xgmac,
input axi_str_tvalid_from_xgmac,
input axi_str_tlast_from_xgmac,
//input axi_str_tuser_from_xgmac,
input axi_str_tready_from_fifo,
output [63:0] axi_str_tdata_to_fifo,
output [7:0] axi_str_tkeep_to_fifo,
output axi_str_tvalid_to_fifo,
output axi_str_tlast_to_fifo,
input user_clk,
input reset
);
reg [63:0] axi_str_tdata_from_xgmac_r;
reg [7:0] axi_str_tkeep_from_xgmac_r;
reg axi_str_tvalid_from_xgmac_r;
reg axi_str_tlast_from_xgmac_r;
wire[10:0] fifo_occupacy_count;
wire s_axis_tvalid;
reg [10:0] wcount_r; //number of words in the current xgmac packet
wire fifo_has_space;
localparam IDLE = 1'd0,
STREAMING = 1'd1;
reg curr_state_r;
rx_fifo rx_fifo_inst (
.s_aclk(user_clk), // input wire s_aclk
.s_aresetn(~reset), // input wire s_aresetn
.s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid
.s_axis_tready(), // output wire s_axis_tready
.s_axis_tdata(axi_str_tdata_from_xgmac_r), // input wire [63 : 0] s_axis_tdata
.s_axis_tkeep(axi_str_tkeep_from_xgmac_r), // input wire [7 : 0] s_axis_tkeep
.s_axis_tlast(axi_str_tlast_from_xgmac_r), // input wire s_axis_tlast
.m_axis_tvalid(axi_str_tvalid_to_fifo), // output wire m_axis_tvalid
.m_axis_tready(axi_str_tready_from_fifo), // input wire m_axis_tready
.m_axis_tdata(axi_str_tdata_to_fifo), // output wire [63 : 0] m_axis_tdata
.m_axis_tkeep(axi_str_tkeep_to_fifo), // output wire [7 : 0] m_axis_tkeep
.m_axis_tlast(axi_str_tlast_to_fifo), // output wire m_axis_tlast
.axis_data_count(fifo_occupacy_count) // output wire [10 : 0] axis_data_count
);
assign fifo_has_space = (fifo_occupacy_count < FIFO_FULL_THRESHOLD);
assign s_axis_tvalid = axi_str_tvalid_from_xgmac_r & (((wcount_r == 0) & fifo_has_space) | (curr_state_r == STREAMING));
always @(posedge user_clk) begin
axi_str_tdata_from_xgmac_r <= axi_str_tdata_from_xgmac;
axi_str_tkeep_from_xgmac_r <= axi_str_tkeep_from_xgmac;
axi_str_tvalid_from_xgmac_r <= axi_str_tvalid_from_xgmac;
axi_str_tlast_from_xgmac_r <= axi_str_tlast_from_xgmac;
end
always @(posedge user_clk)
if (reset)
wcount_r <= 0;
else if (axi_str_tvalid_from_xgmac_r & ~axi_str_tlast_from_xgmac_r)
wcount_r <= wcount_r + 1;
else if (axi_str_tvalid_from_xgmac_r & axi_str_tlast_from_xgmac_r)
wcount_r <= 0;
always @(posedge user_clk)
if (reset)
curr_state_r <= IDLE;
else
case (curr_state_r)
IDLE: if ((wcount_r == 0) & fifo_has_space & axi_str_tvalid_from_xgmac_r)
curr_state_r <= STREAMING;
STREAMING: if (axi_str_tvalid_from_xgmac_r & axi_str_tlast_from_xgmac_r)
curr_state_r <= IDLE;
endcase
/*
//chipscope debugging -- mcdBbBinDummy_inExtractor.cpy
reg [255:0] data;
reg [31:0] trig0;
wire [35:0] control0, control1;
wire vio_reset;
chipscope_icon icon0
(
.CONTROL0(control0),
.CONTROL1(control1)
);
chipscope_ila ila0
(
.CLK(user_clk),
.CONTROL(control0),
.TRIG0(trig0),
.DATA(data)
);
chipscope_vio vio0
(
.CONTROL(control1),
.ASYNC_OUT(vio_reset)
);
always @(posedge user_clk) begin
data [63:0] <= axi_str_tdata_from_xgmac_r;
data [71:64] <= axi_str_tkeep_from_xgmac_r;
data[72] <= axi_str_tvalid_from_xgmac_r;
data[73] <= axi_str_tlast_from_xgmac_r;
data[74] <= axi_str_tready_from_fifo;
data[138:75] <= axi_str_tdata_to_fifo;
data[146:139] <= axi_str_tkeep_to_fifo;
data[147] <= axi_str_tvalid_to_fifo;
data[148] <= axi_str_tlast_to_fifo;
data[159:149] <= wcount_r;
data[160] <= curr_state_r;
data[171:161] <= fifo_occupacy_count;
trig0[10:0] <= wcount_r;
trig0[11] <= axi_str_tvalid_to_fifo;
trig0[12] <= axi_str_tready_from_fifo;
end
*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S15_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLYGATE4S15_BEHAVIORAL_V
/**
* dlygate4s15: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlygate4s15 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S15_BEHAVIORAL_V
|
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